Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 0
- Boot result: FAIL
- Warnings: 0
- Kernel Warnings: 0
1 00:59:25.300634 lava-dispatcher, installed at version: 2024.03
2 00:59:25.300836 start: 0 validate
3 00:59:25.300952 Start time: 2024-06-16 00:59:25.300944+00:00 (UTC)
4 00:59:25.301087 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:59:25.301234 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:59:25.568812 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:59:25.569480 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:59:25.824626 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:59:25.825463 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:59:26.081187 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:59:26.081819 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:59:26.342159 validate duration: 1.04
14 00:59:26.343606 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:59:26.344371 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:59:26.344976 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:59:26.345753 Not decompressing ramdisk as can be used compressed.
18 00:59:26.346329 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 00:59:26.346800 saving as /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/ramdisk/rootfs.cpio.gz
20 00:59:26.347418 total size: 47897469 (45 MB)
21 00:59:26.352980 progress 0 % (0 MB)
22 00:59:26.384996 progress 5 % (2 MB)
23 00:59:26.400034 progress 10 % (4 MB)
24 00:59:26.412304 progress 15 % (6 MB)
25 00:59:26.424176 progress 20 % (9 MB)
26 00:59:26.436052 progress 25 % (11 MB)
27 00:59:26.447975 progress 30 % (13 MB)
28 00:59:26.459764 progress 35 % (16 MB)
29 00:59:26.471637 progress 40 % (18 MB)
30 00:59:26.483286 progress 45 % (20 MB)
31 00:59:26.495403 progress 50 % (22 MB)
32 00:59:26.507483 progress 55 % (25 MB)
33 00:59:26.519694 progress 60 % (27 MB)
34 00:59:26.531668 progress 65 % (29 MB)
35 00:59:26.544509 progress 70 % (32 MB)
36 00:59:26.556745 progress 75 % (34 MB)
37 00:59:26.569221 progress 80 % (36 MB)
38 00:59:26.581513 progress 85 % (38 MB)
39 00:59:26.593781 progress 90 % (41 MB)
40 00:59:26.606188 progress 95 % (43 MB)
41 00:59:26.618517 progress 100 % (45 MB)
42 00:59:26.618746 45 MB downloaded in 0.27 s (168.35 MB/s)
43 00:59:26.618905 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:59:26.619235 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:59:26.619343 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:59:26.619424 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:59:26.619556 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:59:26.619619 saving as /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/kernel/Image
50 00:59:26.619673 total size: 54813184 (52 MB)
51 00:59:26.619727 No compression specified
52 00:59:26.620726 progress 0 % (0 MB)
53 00:59:26.634624 progress 5 % (2 MB)
54 00:59:26.648828 progress 10 % (5 MB)
55 00:59:26.662634 progress 15 % (7 MB)
56 00:59:26.676811 progress 20 % (10 MB)
57 00:59:26.691010 progress 25 % (13 MB)
58 00:59:26.704579 progress 30 % (15 MB)
59 00:59:26.718637 progress 35 % (18 MB)
60 00:59:26.732691 progress 40 % (20 MB)
61 00:59:26.746501 progress 45 % (23 MB)
62 00:59:26.760761 progress 50 % (26 MB)
63 00:59:26.774769 progress 55 % (28 MB)
64 00:59:26.788404 progress 60 % (31 MB)
65 00:59:26.802226 progress 65 % (34 MB)
66 00:59:26.815919 progress 70 % (36 MB)
67 00:59:26.829636 progress 75 % (39 MB)
68 00:59:26.843336 progress 80 % (41 MB)
69 00:59:26.857062 progress 85 % (44 MB)
70 00:59:26.870854 progress 90 % (47 MB)
71 00:59:26.884542 progress 95 % (49 MB)
72 00:59:26.897977 progress 100 % (52 MB)
73 00:59:26.898236 52 MB downloaded in 0.28 s (187.66 MB/s)
74 00:59:26.898387 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:59:26.898593 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:59:26.898675 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:59:26.898751 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:59:26.898876 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:59:26.898942 saving as /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/dtb/mt8192-asurada-spherion-r0.dtb
81 00:59:26.898997 total size: 47258 (0 MB)
82 00:59:26.899051 No compression specified
83 00:59:26.900060 progress 69 % (0 MB)
84 00:59:26.900318 progress 100 % (0 MB)
85 00:59:26.900463 0 MB downloaded in 0.00 s (30.78 MB/s)
86 00:59:26.900574 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:59:26.900796 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:59:26.900875 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:59:26.900950 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:59:26.901056 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:59:26.901125 saving as /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/modules/modules.tar
93 00:59:26.901179 total size: 8617404 (8 MB)
94 00:59:26.901232 Using unxz to decompress xz
95 00:59:26.902605 progress 0 % (0 MB)
96 00:59:26.920944 progress 5 % (0 MB)
97 00:59:26.946577 progress 10 % (0 MB)
98 00:59:26.973087 progress 15 % (1 MB)
99 00:59:26.996186 progress 20 % (1 MB)
100 00:59:27.019163 progress 25 % (2 MB)
101 00:59:27.041950 progress 30 % (2 MB)
102 00:59:27.067360 progress 35 % (2 MB)
103 00:59:27.090540 progress 40 % (3 MB)
104 00:59:27.112520 progress 45 % (3 MB)
105 00:59:27.136057 progress 50 % (4 MB)
106 00:59:27.160074 progress 55 % (4 MB)
107 00:59:27.183253 progress 60 % (4 MB)
108 00:59:27.206336 progress 65 % (5 MB)
109 00:59:27.231931 progress 70 % (5 MB)
110 00:59:27.255062 progress 75 % (6 MB)
111 00:59:27.279673 progress 80 % (6 MB)
112 00:59:27.302717 progress 85 % (7 MB)
113 00:59:27.326694 progress 90 % (7 MB)
114 00:59:27.350860 progress 95 % (7 MB)
115 00:59:27.374917 progress 100 % (8 MB)
116 00:59:27.380545 8 MB downloaded in 0.48 s (17.14 MB/s)
117 00:59:27.380694 end: 1.4.1 http-download (duration 00:00:00) [common]
119 00:59:27.380903 end: 1.4 download-retry (duration 00:00:00) [common]
120 00:59:27.380987 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:59:27.381063 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:59:27.381132 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:59:27.381202 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:59:27.381363 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts
125 00:59:27.381477 makedir: /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin
126 00:59:27.381565 makedir: /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/tests
127 00:59:27.381649 makedir: /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/results
128 00:59:27.381733 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-add-keys
129 00:59:27.381857 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-add-sources
130 00:59:27.381973 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-background-process-start
131 00:59:27.382135 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-background-process-stop
132 00:59:27.382256 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-common-functions
133 00:59:27.382369 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-echo-ipv4
134 00:59:27.382480 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-install-packages
135 00:59:27.382588 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-installed-packages
136 00:59:27.382697 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-os-build
137 00:59:27.382806 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-probe-channel
138 00:59:27.382915 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-probe-ip
139 00:59:27.383024 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-target-ip
140 00:59:27.383131 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-target-mac
141 00:59:27.383238 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-target-storage
142 00:59:27.383348 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-test-case
143 00:59:27.383457 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-test-event
144 00:59:27.383564 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-test-feedback
145 00:59:27.383672 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-test-raise
146 00:59:27.383781 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-test-reference
147 00:59:27.383889 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-test-runner
148 00:59:27.383996 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-test-set
149 00:59:27.384105 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-test-shell
150 00:59:27.384214 Updating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-install-packages (oe)
151 00:59:27.384349 Updating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/bin/lava-installed-packages (oe)
152 00:59:27.384456 Creating /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/environment
153 00:59:27.384540 LAVA metadata
154 00:59:27.384603 - LAVA_JOB_ID=14368629
155 00:59:27.384657 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:59:27.384744 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:59:27.384799 skipped lava-vland-overlay
158 00:59:27.384864 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:59:27.384933 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:59:27.384989 skipped lava-multinode-overlay
161 00:59:27.385054 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:59:27.385122 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:59:27.385183 Loading test definitions
164 00:59:27.385256 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:59:27.385314 Using /lava-14368629 at stage 0
166 00:59:27.385604 uuid=14368629_1.5.2.3.1 testdef=None
167 00:59:27.385683 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:59:27.385758 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:59:27.386256 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:59:27.386453 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:59:27.387006 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:59:27.387210 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:59:27.387742 runner path: /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/0/tests/0_igt-gpu-panfrost test_uuid 14368629_1.5.2.3.1
176 00:59:27.387884 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:59:27.388074 Creating lava-test-runner.conf files
179 00:59:27.388130 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368629/lava-overlay-wlppxyts/lava-14368629/0 for stage 0
180 00:59:27.388207 - 0_igt-gpu-panfrost
181 00:59:27.388295 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:59:27.388373 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:59:27.394235 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:59:27.394327 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:59:27.394404 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:59:27.394479 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:59:27.394553 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:59:29.093932 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 00:59:29.094089 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 00:59:29.094169 extracting modules file /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368629/extract-overlay-ramdisk-1kgtd6nj/ramdisk
191 00:59:29.318944 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:59:29.319074 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 00:59:29.319152 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368629/compress-overlay-jnc_v_yd/overlay-1.5.2.4.tar.gz to ramdisk
194 00:59:29.319211 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368629/compress-overlay-jnc_v_yd/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368629/extract-overlay-ramdisk-1kgtd6nj/ramdisk
195 00:59:29.325275 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:59:29.325370 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 00:59:29.325456 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:59:29.325541 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 00:59:29.325605 Building ramdisk /var/lib/lava/dispatcher/tmp/14368629/extract-overlay-ramdisk-1kgtd6nj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368629/extract-overlay-ramdisk-1kgtd6nj/ramdisk
200 00:59:30.503498 >> 465988 blocks
201 00:59:36.781661 rename /var/lib/lava/dispatcher/tmp/14368629/extract-overlay-ramdisk-1kgtd6nj/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/ramdisk/ramdisk.cpio.gz
202 00:59:36.781837 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 00:59:36.781929 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 00:59:36.782027 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 00:59:36.782120 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/kernel/Image']
206 00:59:49.994605 Returned 0 in 13 seconds
207 00:59:50.095092 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/kernel/image.itb
208 00:59:51.015056 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:59:51.015193 output: Created: Sun Jun 16 01:59:50 2024
210 00:59:51.015279 output: Image 0 (kernel-1)
211 00:59:51.015351 output: Description:
212 00:59:51.015425 output: Created: Sun Jun 16 01:59:50 2024
213 00:59:51.015497 output: Type: Kernel Image
214 00:59:51.015565 output: Compression: lzma compressed
215 00:59:51.015655 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
216 00:59:51.015741 output: Architecture: AArch64
217 00:59:51.015825 output: OS: Linux
218 00:59:51.015910 output: Load Address: 0x00000000
219 00:59:51.015993 output: Entry Point: 0x00000000
220 00:59:51.016079 output: Hash algo: crc32
221 00:59:51.016164 output: Hash value: f6f06660
222 00:59:51.016249 output: Image 1 (fdt-1)
223 00:59:51.016335 output: Description: mt8192-asurada-spherion-r0
224 00:59:51.016422 output: Created: Sun Jun 16 01:59:50 2024
225 00:59:51.016512 output: Type: Flat Device Tree
226 00:59:51.016601 output: Compression: uncompressed
227 00:59:51.016692 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:59:51.016782 output: Architecture: AArch64
229 00:59:51.016874 output: Hash algo: crc32
230 00:59:51.016962 output: Hash value: 0f8e4d2e
231 00:59:51.017051 output: Image 2 (ramdisk-1)
232 00:59:51.017140 output: Description: unavailable
233 00:59:51.017225 output: Created: Sun Jun 16 01:59:50 2024
234 00:59:51.017308 output: Type: RAMDisk Image
235 00:59:51.017389 output: Compression: uncompressed
236 00:59:51.017472 output: Data Size: 61022680 Bytes = 59592.46 KiB = 58.20 MiB
237 00:59:51.017554 output: Architecture: AArch64
238 00:59:51.017636 output: OS: Linux
239 00:59:51.017718 output: Load Address: unavailable
240 00:59:51.017799 output: Entry Point: unavailable
241 00:59:51.017882 output: Hash algo: crc32
242 00:59:51.017963 output: Hash value: b90e1e7f
243 00:59:51.018091 output: Default Configuration: 'conf-1'
244 00:59:51.018173 output: Configuration 0 (conf-1)
245 00:59:51.018255 output: Description: mt8192-asurada-spherion-r0
246 00:59:51.018338 output: Kernel: kernel-1
247 00:59:51.018420 output: Init Ramdisk: ramdisk-1
248 00:59:51.018502 output: FDT: fdt-1
249 00:59:51.018586 output: Loadables: kernel-1
250 00:59:51.018671 output:
251 00:59:51.018851 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 00:59:51.018967 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 00:59:51.019090 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 00:59:51.019208 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 00:59:51.019309 No LXC device requested
256 00:59:51.019422 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:59:51.019535 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 00:59:51.019639 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:59:51.019735 Checking files for TFTP limit of 4294967296 bytes.
260 00:59:51.020323 end: 1 tftp-deploy (duration 00:00:25) [common]
261 00:59:51.020454 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:59:51.020569 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:59:51.020730 substitutions:
264 00:59:51.020819 - {DTB}: 14368629/tftp-deploy-ekovxyqb/dtb/mt8192-asurada-spherion-r0.dtb
265 00:59:51.020912 - {INITRD}: 14368629/tftp-deploy-ekovxyqb/ramdisk/ramdisk.cpio.gz
266 00:59:51.020999 - {KERNEL}: 14368629/tftp-deploy-ekovxyqb/kernel/Image
267 00:59:51.021067 - {LAVA_MAC}: None
268 00:59:51.021172 - {PRESEED_CONFIG}: None
269 00:59:51.021275 - {PRESEED_LOCAL}: None
270 00:59:51.021363 - {RAMDISK}: 14368629/tftp-deploy-ekovxyqb/ramdisk/ramdisk.cpio.gz
271 00:59:51.021458 - {ROOT_PART}: None
272 00:59:51.021543 - {ROOT}: None
273 00:59:51.021627 - {SERVER_IP}: 192.168.201.1
274 00:59:51.021730 - {TEE}: None
275 00:59:51.021816 Parsed boot commands:
276 00:59:51.021899 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:59:51.022135 Parsed boot commands: tftpboot 192.168.201.1 14368629/tftp-deploy-ekovxyqb/kernel/image.itb 14368629/tftp-deploy-ekovxyqb/kernel/cmdline
278 00:59:51.022248 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:59:51.022359 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:59:51.022475 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:59:51.022584 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:59:51.022681 Not connected, no need to disconnect.
283 00:59:51.022786 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:59:51.022899 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:59:51.022987 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 00:59:51.026448 Setting prompt string to ['lava-test: # ']
287 00:59:51.026784 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:59:51.026911 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:59:51.027035 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:59:51.027155 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:59:51.027462 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 00:59:57.651562 >> Command sent successfully.
293 00:59:57.654794 Returned 0 in 6 seconds
294 00:59:57.755176 end: 2.2.2.1 pdu-reboot (duration 00:00:07) [common]
296 00:59:57.755488 end: 2.2.2 reset-device (duration 00:00:07) [common]
297 00:59:57.755594 start: 2.2.3 depthcharge-start (timeout 00:04:53) [common]
298 00:59:57.755691 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:59:57.755761 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:59:57.755865 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:59:57.756372 [Enter `^Ec?' for help]
302 00:59:57.756467
303 00:59:57.756560
304 00:59:57.756648 F0: 102B 0000
305 00:59:57.756719
306 00:59:57.756791 F3: 1001 0000 [0200]
307 00:59:57.756862
308 00:59:57.756965 F3: 1001 0000
309 00:59:57.757059
310 00:59:57.757149 F7: 102D 0000
311 00:59:57.757240
312 00:59:57.757330 F1: 0000 0000
313 00:59:57.757419
314 00:59:57.757509 V0: 0000 0000 [0001]
315 00:59:57.757597
316 00:59:57.757683 00: 0007 8000
317 00:59:57.757771
318 00:59:57.757855 01: 0000 0000
319 00:59:57.757941
320 00:59:57.758071 BP: 0C00 0209 [0000]
321 00:59:57.758155
322 00:59:57.758237 G0: 1182 0000
323 00:59:57.758320
324 00:59:57.758403 EC: 0000 0021 [4000]
325 00:59:57.758485
326 00:59:57.758568 S7: 0000 0000 [0000]
327 00:59:57.758650
328 00:59:57.758732 CC: 0000 0000 [0001]
329 00:59:57.758815
330 00:59:57.758900 T0: 0000 0040 [010F]
331 00:59:57.758989
332 00:59:57.759072 Jump to BL
333 00:59:57.759154
334 00:59:57.763620
335 00:59:57.763702
336 00:59:57.770886 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 00:59:57.774353 ARM64: Exception handlers installed.
338 00:59:57.777791 ARM64: Testing exception
339 00:59:57.780964 ARM64: Done test exception
340 00:59:57.787823 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 00:59:57.797381 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 00:59:57.804455 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 00:59:57.814515 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 00:59:57.821151 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 00:59:57.827906 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 00:59:57.839629 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 00:59:57.846373 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 00:59:57.865737 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 00:59:57.869709 WDT: Last reset was cold boot
350 00:59:57.872611 SPI1(PAD0) initialized at 2873684 Hz
351 00:59:57.876046 SPI5(PAD0) initialized at 992727 Hz
352 00:59:57.879262 VBOOT: Loading verstage.
353 00:59:57.886146 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 00:59:57.889528 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 00:59:57.892954 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 00:59:57.896528 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 00:59:57.903282 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 00:59:57.910173 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 00:59:57.920758 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 00:59:57.920877
361 00:59:57.920941
362 00:59:57.930888 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 00:59:57.934071 ARM64: Exception handlers installed.
364 00:59:57.937588 ARM64: Testing exception
365 00:59:57.937671 ARM64: Done test exception
366 00:59:57.944336 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 00:59:57.948039 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 00:59:57.961711 Probing TPM: . done!
369 00:59:57.961845 TPM ready after 0 ms
370 00:59:57.968377 Connected to device vid:did:rid of 1ae0:0028:00
371 00:59:57.975247 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 00:59:57.978765 Initialized TPM device CR50 revision 0
373 00:59:58.027739 tlcl_send_startup: Startup return code is 0
374 00:59:58.027878 TPM: setup succeeded
375 00:59:58.038989 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 00:59:58.047447 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 00:59:58.057811 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 00:59:58.066343 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 00:59:58.069740 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 00:59:58.073146 in-header: 03 07 00 00 08 00 00 00
381 00:59:58.077329 in-data: aa e4 47 04 13 02 00 00
382 00:59:58.079923 Chrome EC: UHEPI supported
383 00:59:58.086590 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 00:59:58.090187 in-header: 03 c9 00 00 08 00 00 00
385 00:59:58.093447 in-data: 04 00 20 08 00 00 00 00
386 00:59:58.093564 Phase 1
387 00:59:58.096831 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 00:59:58.103636 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 00:59:58.110162 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 00:59:58.113680 Recovery requested (1009000e)
391 00:59:58.119832 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:59:58.125462 tlcl_extend: response is 0
393 00:59:58.133383 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:59:58.139114 tlcl_extend: response is 0
395 00:59:58.145291 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:59:58.165749 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 00:59:58.172450 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:59:58.172559
399 00:59:58.172620
400 00:59:58.182741 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:59:58.186222 ARM64: Exception handlers installed.
402 00:59:58.189214 ARM64: Testing exception
403 00:59:58.189297 ARM64: Done test exception
404 00:59:58.211741 pmic_efuse_setting: Set efuses in 11 msecs
405 00:59:58.215042 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:59:58.221684 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:59:58.225198 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:59:58.231409 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:59:58.234646 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:59:58.241608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:59:58.244828 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:59:58.248240 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:59:58.254888 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:59:58.258257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:59:58.264941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:59:58.268263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:59:58.271796 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:59:58.278159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:59:58.284846 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:59:58.288373 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:59:58.295540 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:59:58.301707 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:59:58.305130 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:59:58.311634 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:59:58.318868 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:59:58.321957 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:59:58.328594 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:59:58.335493 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:59:58.338802 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:59:58.345470 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:59:58.352136 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:59:58.355364 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:59:58.361860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:59:58.365249 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:59:58.368570 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:59:58.375640 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:59:58.378695 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:59:58.385345 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:59:58.388871 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:59:58.395448 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:59:58.398802 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:59:58.405828 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:59:58.409010 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:59:58.415730 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:59:58.418925 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:59:58.421968 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:59:58.429911 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:59:58.433040 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:59:58.436108 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:59:58.439618 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:59:58.446217 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:59:58.449884 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:59:58.453036 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:59:58.459870 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:59:58.463459 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:59:58.466470 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:59:58.473408 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:59:58.483566 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:59:58.486576 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:59:58.496884 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:59:58.503294 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:59:58.510556 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:59:58.513508 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:59:58.517036 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:59:58.524229 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
466 00:59:58.530970 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:59:58.534558 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 00:59:58.537632 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:59:58.548595 [RTC]rtc_get_frequency_meter,154: input=15, output=789
470 00:59:58.558290 [RTC]rtc_get_frequency_meter,154: input=23, output=978
471 00:59:58.568220 [RTC]rtc_get_frequency_meter,154: input=19, output=884
472 00:59:58.577330 [RTC]rtc_get_frequency_meter,154: input=17, output=837
473 00:59:58.586822 [RTC]rtc_get_frequency_meter,154: input=16, output=813
474 00:59:58.596336 [RTC]rtc_get_frequency_meter,154: input=15, output=790
475 00:59:58.606017 [RTC]rtc_get_frequency_meter,154: input=16, output=814
476 00:59:58.609093 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 00:59:58.616046 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 00:59:58.619458 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 00:59:58.622875 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 00:59:58.629830 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 00:59:58.632940 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 00:59:58.636215 ADC[4]: Raw value=901697 ID=7
483 00:59:58.636297 ADC[3]: Raw value=213336 ID=1
484 00:59:58.639706 RAM Code: 0x71
485 00:59:58.643283 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 00:59:58.649901 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 00:59:58.656592 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 00:59:58.663308 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 00:59:58.666356 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 00:59:58.670101 in-header: 03 07 00 00 08 00 00 00
491 00:59:58.673173 in-data: aa e4 47 04 13 02 00 00
492 00:59:58.676578 Chrome EC: UHEPI supported
493 00:59:58.683522 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 00:59:58.686795 in-header: 03 c9 00 00 08 00 00 00
495 00:59:58.689894 in-data: 04 00 20 08 00 00 00 00
496 00:59:58.693269 MRC: failed to locate region type 0.
497 00:59:58.700233 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 00:59:58.703188 DRAM-K: Running full calibration
499 00:59:58.710516 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 00:59:58.710620 header.status = 0x0
501 00:59:58.713378 header.version = 0x6 (expected: 0x6)
502 00:59:58.716613 header.size = 0xd00 (expected: 0xd00)
503 00:59:58.720093 header.flags = 0x0
504 00:59:58.723427 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 00:59:58.742274 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 00:59:58.749099 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 00:59:58.752504 dram_init: ddr_geometry: 2
508 00:59:58.756092 [EMI] MDL number = 2
509 00:59:58.756179 [EMI] Get MDL freq = 0
510 00:59:58.759612 dram_init: ddr_type: 0
511 00:59:58.759694 is_discrete_lpddr4: 1
512 00:59:58.762957 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 00:59:58.763037
514 00:59:58.763096
515 00:59:58.766126 [Bian_co] ETT version 0.0.0.1
516 00:59:58.772741 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 00:59:58.772840
518 00:59:58.776146 dramc_set_vcore_voltage set vcore to 650000
519 00:59:58.776229 Read voltage for 800, 4
520 00:59:58.779729 Vio18 = 0
521 00:59:58.779809 Vcore = 650000
522 00:59:58.779870 Vdram = 0
523 00:59:58.783139 Vddq = 0
524 00:59:58.783219 Vmddr = 0
525 00:59:58.786691 dram_init: config_dvfs: 1
526 00:59:58.789345 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 00:59:58.796077 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 00:59:58.799420 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 00:59:58.802737 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 00:59:58.806139 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 00:59:58.809731 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 00:59:58.813219 MEM_TYPE=3, freq_sel=18
533 00:59:58.816415 sv_algorithm_assistance_LP4_1600
534 00:59:58.819706 ============ PULL DRAM RESETB DOWN ============
535 00:59:58.823059 ========== PULL DRAM RESETB DOWN end =========
536 00:59:58.830084 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 00:59:58.832869 ===================================
538 00:59:58.832954 LPDDR4 DRAM CONFIGURATION
539 00:59:58.836332 ===================================
540 00:59:58.839566 EX_ROW_EN[0] = 0x0
541 00:59:58.843324 EX_ROW_EN[1] = 0x0
542 00:59:58.843407 LP4Y_EN = 0x0
543 00:59:58.846326 WORK_FSP = 0x0
544 00:59:58.846405 WL = 0x2
545 00:59:58.850208 RL = 0x2
546 00:59:58.850294 BL = 0x2
547 00:59:58.853295 RPST = 0x0
548 00:59:58.853375 RD_PRE = 0x0
549 00:59:58.856753 WR_PRE = 0x1
550 00:59:58.856834 WR_PST = 0x0
551 00:59:58.860125 DBI_WR = 0x0
552 00:59:58.860206 DBI_RD = 0x0
553 00:59:58.863300 OTF = 0x1
554 00:59:58.866882 ===================================
555 00:59:58.870021 ===================================
556 00:59:58.870106 ANA top config
557 00:59:58.873688 ===================================
558 00:59:58.876853 DLL_ASYNC_EN = 0
559 00:59:58.880628 ALL_SLAVE_EN = 1
560 00:59:58.880713 NEW_RANK_MODE = 1
561 00:59:58.883374 DLL_IDLE_MODE = 1
562 00:59:58.886773 LP45_APHY_COMB_EN = 1
563 00:59:58.890241 TX_ODT_DIS = 1
564 00:59:58.890324 NEW_8X_MODE = 1
565 00:59:58.893267 ===================================
566 00:59:58.896720 ===================================
567 00:59:58.900562 data_rate = 1600
568 00:59:58.903563 CKR = 1
569 00:59:58.906980 DQ_P2S_RATIO = 8
570 00:59:58.910346 ===================================
571 00:59:58.913694 CA_P2S_RATIO = 8
572 00:59:58.916954 DQ_CA_OPEN = 0
573 00:59:58.917037 DQ_SEMI_OPEN = 0
574 00:59:58.920491 CA_SEMI_OPEN = 0
575 00:59:58.924168 CA_FULL_RATE = 0
576 00:59:58.926930 DQ_CKDIV4_EN = 1
577 00:59:58.930646 CA_CKDIV4_EN = 1
578 00:59:58.930730 CA_PREDIV_EN = 0
579 00:59:58.934020 PH8_DLY = 0
580 00:59:58.937345 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 00:59:58.940878 DQ_AAMCK_DIV = 4
582 00:59:58.943761 CA_AAMCK_DIV = 4
583 00:59:58.947463 CA_ADMCK_DIV = 4
584 00:59:58.947548 DQ_TRACK_CA_EN = 0
585 00:59:58.950494 CA_PICK = 800
586 00:59:58.953813 CA_MCKIO = 800
587 00:59:58.957206 MCKIO_SEMI = 0
588 00:59:58.960807 PLL_FREQ = 3068
589 00:59:58.963884 DQ_UI_PI_RATIO = 32
590 00:59:58.967261 CA_UI_PI_RATIO = 0
591 00:59:58.970386 ===================================
592 00:59:58.974418 ===================================
593 00:59:58.974507 memory_type:LPDDR4
594 00:59:58.977247 GP_NUM : 10
595 00:59:58.977327 SRAM_EN : 1
596 00:59:58.980833 MD32_EN : 0
597 00:59:58.984053 ===================================
598 00:59:58.987566 [ANA_INIT] >>>>>>>>>>>>>>
599 00:59:58.990839 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 00:59:58.994278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 00:59:58.997663 ===================================
602 00:59:58.997748 data_rate = 1600,PCW = 0X7600
603 00:59:59.000680 ===================================
604 00:59:59.004057 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 00:59:59.010862 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 00:59:59.017593 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:59:59.020745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 00:59:59.024147 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 00:59:59.027354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:59:59.030782 [ANA_INIT] flow start
611 00:59:59.030869 [ANA_INIT] PLL >>>>>>>>
612 00:59:59.034578 [ANA_INIT] PLL <<<<<<<<
613 00:59:59.037876 [ANA_INIT] MIDPI >>>>>>>>
614 00:59:59.037961 [ANA_INIT] MIDPI <<<<<<<<
615 00:59:59.041084 [ANA_INIT] DLL >>>>>>>>
616 00:59:59.044488 [ANA_INIT] flow end
617 00:59:59.047628 ============ LP4 DIFF to SE enter ============
618 00:59:59.050914 ============ LP4 DIFF to SE exit ============
619 00:59:59.054699 [ANA_INIT] <<<<<<<<<<<<<
620 00:59:59.057752 [Flow] Enable top DCM control >>>>>
621 00:59:59.061033 [Flow] Enable top DCM control <<<<<
622 00:59:59.064393 Enable DLL master slave shuffle
623 00:59:59.067727 ==============================================================
624 00:59:59.071362 Gating Mode config
625 00:59:59.077955 ==============================================================
626 00:59:59.078097 Config description:
627 00:59:59.088261 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 00:59:59.094832 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 00:59:59.098337 SELPH_MODE 0: By rank 1: By Phase
630 00:59:59.104918 ==============================================================
631 00:59:59.108126 GAT_TRACK_EN = 1
632 00:59:59.111774 RX_GATING_MODE = 2
633 00:59:59.115186 RX_GATING_TRACK_MODE = 2
634 00:59:59.118440 SELPH_MODE = 1
635 00:59:59.121829 PICG_EARLY_EN = 1
636 00:59:59.121934 VALID_LAT_VALUE = 1
637 00:59:59.128232 ==============================================================
638 00:59:59.131598 Enter into Gating configuration >>>>
639 00:59:59.134774 Exit from Gating configuration <<<<
640 00:59:59.138235 Enter into DVFS_PRE_config >>>>>
641 00:59:59.148260 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 00:59:59.151608 Exit from DVFS_PRE_config <<<<<
643 00:59:59.155119 Enter into PICG configuration >>>>
644 00:59:59.158332 Exit from PICG configuration <<<<
645 00:59:59.161569 [RX_INPUT] configuration >>>>>
646 00:59:59.164687 [RX_INPUT] configuration <<<<<
647 00:59:59.168537 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 00:59:59.175321 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 00:59:59.181917 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 00:59:59.188671 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 00:59:59.195046 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 00:59:59.198651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 00:59:59.205300 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 00:59:59.208489 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 00:59:59.211927 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 00:59:59.215233 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 00:59:59.218673 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 00:59:59.225095 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 00:59:59.228504 ===================================
660 00:59:59.228590 LPDDR4 DRAM CONFIGURATION
661 00:59:59.232127 ===================================
662 00:59:59.235336 EX_ROW_EN[0] = 0x0
663 00:59:59.238607 EX_ROW_EN[1] = 0x0
664 00:59:59.238685 LP4Y_EN = 0x0
665 00:59:59.241876 WORK_FSP = 0x0
666 00:59:59.241955 WL = 0x2
667 00:59:59.245160 RL = 0x2
668 00:59:59.245236 BL = 0x2
669 00:59:59.248428 RPST = 0x0
670 00:59:59.248506 RD_PRE = 0x0
671 00:59:59.252251 WR_PRE = 0x1
672 00:59:59.252327 WR_PST = 0x0
673 00:59:59.255414 DBI_WR = 0x0
674 00:59:59.255491 DBI_RD = 0x0
675 00:59:59.258760 OTF = 0x1
676 00:59:59.262276 ===================================
677 00:59:59.265350 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 00:59:59.268667 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 00:59:59.275129 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 00:59:59.278587 ===================================
681 00:59:59.278674 LPDDR4 DRAM CONFIGURATION
682 00:59:59.282177 ===================================
683 00:59:59.285708 EX_ROW_EN[0] = 0x10
684 00:59:59.285791 EX_ROW_EN[1] = 0x0
685 00:59:59.289012 LP4Y_EN = 0x0
686 00:59:59.291906 WORK_FSP = 0x0
687 00:59:59.291986 WL = 0x2
688 00:59:59.295520 RL = 0x2
689 00:59:59.295599 BL = 0x2
690 00:59:59.298587 RPST = 0x0
691 00:59:59.298665 RD_PRE = 0x0
692 00:59:59.301948 WR_PRE = 0x1
693 00:59:59.302077 WR_PST = 0x0
694 00:59:59.305287 DBI_WR = 0x0
695 00:59:59.305366 DBI_RD = 0x0
696 00:59:59.309432 OTF = 0x1
697 00:59:59.312293 ===================================
698 00:59:59.318619 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 00:59:59.321766 nWR fixed to 40
700 00:59:59.321848 [ModeRegInit_LP4] CH0 RK0
701 00:59:59.325241 [ModeRegInit_LP4] CH0 RK1
702 00:59:59.328481 [ModeRegInit_LP4] CH1 RK0
703 00:59:59.328563 [ModeRegInit_LP4] CH1 RK1
704 00:59:59.332363 match AC timing 13
705 00:59:59.335095 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 00:59:59.338773 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 00:59:59.345507 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 00:59:59.349060 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 00:59:59.355332 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 00:59:59.355426 [EMI DOE] emi_dcm 0
711 00:59:59.358531 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 00:59:59.362547 ==
713 00:59:59.365372 Dram Type= 6, Freq= 0, CH_0, rank 0
714 00:59:59.368711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 00:59:59.368797 ==
716 00:59:59.372024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 00:59:59.378697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 00:59:59.388787 [CA 0] Center 37 (7~68) winsize 62
719 00:59:59.391957 [CA 1] Center 37 (6~68) winsize 63
720 00:59:59.394996 [CA 2] Center 35 (4~66) winsize 63
721 00:59:59.398375 [CA 3] Center 34 (4~65) winsize 62
722 00:59:59.401691 [CA 4] Center 34 (3~65) winsize 63
723 00:59:59.405040 [CA 5] Center 33 (3~64) winsize 62
724 00:59:59.405124
725 00:59:59.409216 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 00:59:59.409299
727 00:59:59.412126 [CATrainingPosCal] consider 1 rank data
728 00:59:59.414822 u2DelayCellTimex100 = 270/100 ps
729 00:59:59.418277 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 00:59:59.421771 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 00:59:59.425465 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
732 00:59:59.429444 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 00:59:59.435569 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
734 00:59:59.438870 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 00:59:59.438956
736 00:59:59.442126 CA PerBit enable=1, Macro0, CA PI delay=33
737 00:59:59.442204
738 00:59:59.445576 [CBTSetCACLKResult] CA Dly = 33
739 00:59:59.445654 CS Dly: 5 (0~36)
740 00:59:59.445714 ==
741 00:59:59.448865 Dram Type= 6, Freq= 0, CH_0, rank 1
742 00:59:59.455900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 00:59:59.455996 ==
744 00:59:59.459200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 00:59:59.465508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 00:59:59.475085 [CA 0] Center 37 (6~68) winsize 63
747 00:59:59.477969 [CA 1] Center 37 (7~68) winsize 62
748 00:59:59.481286 [CA 2] Center 35 (5~66) winsize 62
749 00:59:59.484981 [CA 3] Center 35 (4~66) winsize 63
750 00:59:59.488219 [CA 4] Center 33 (3~64) winsize 62
751 00:59:59.491425 [CA 5] Center 33 (3~64) winsize 62
752 00:59:59.491539
753 00:59:59.494926 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 00:59:59.495006
755 00:59:59.498045 [CATrainingPosCal] consider 2 rank data
756 00:59:59.501488 u2DelayCellTimex100 = 270/100 ps
757 00:59:59.504653 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 00:59:59.508300 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 00:59:59.515061 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 00:59:59.518252 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 00:59:59.521579 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 00:59:59.525006 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 00:59:59.525087
764 00:59:59.528118 CA PerBit enable=1, Macro0, CA PI delay=33
765 00:59:59.528196
766 00:59:59.531622 [CBTSetCACLKResult] CA Dly = 33
767 00:59:59.531700 CS Dly: 5 (0~37)
768 00:59:59.531759
769 00:59:59.534669 ----->DramcWriteLeveling(PI) begin...
770 00:59:59.538205 ==
771 00:59:59.538287 Dram Type= 6, Freq= 0, CH_0, rank 0
772 00:59:59.545021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 00:59:59.545108 ==
774 00:59:59.548370 Write leveling (Byte 0): 28 => 28
775 00:59:59.551555 Write leveling (Byte 1): 32 => 32
776 00:59:59.554861 DramcWriteLeveling(PI) end<-----
777 00:59:59.554943
778 00:59:59.555002 ==
779 00:59:59.558318 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:59:59.561606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:59:59.561686 ==
782 00:59:59.565213 [Gating] SW mode calibration
783 00:59:59.571638 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 00:59:59.575013 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 00:59:59.581644 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 00:59:59.585135 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 00:59:59.588446 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 00:59:59.594904 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:59:59.598656 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:59:59.602025 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:59:59.608557 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:59:59.611962 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:59:59.615247 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:59:59.618512 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:59:59.625248 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:59:59.628438 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:59:59.632156 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:59:59.638813 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:59:59.642669 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:59:59.645404 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:59:59.652221 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:59:59.655211 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
803 00:59:59.658420 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 00:59:59.665202 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 00:59:59.668976 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:59:59.671988 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:59:59.679133 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:59:59.682324 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:59:59.685472 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:59:59.688766 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:59:59.695455 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 00:59:59.698752 0 9 12 | B1->B0 | 2525 3131 | 1 0 | (1 1) (0 0)
813 00:59:59.702418 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
814 00:59:59.709104 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:59:59.712457 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:59:59.715875 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:59:59.722123 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:59:59.725782 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 00:59:59.728878 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
820 00:59:59.735455 0 10 12 | B1->B0 | 2e2e 2525 | 0 0 | (1 1) (0 0)
821 00:59:59.739098 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:59:59.742557 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:59:59.749353 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:59:59.752605 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:59:59.755627 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:59:59.762499 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:59:59.765587 0 11 8 | B1->B0 | 2625 2f2f | 1 0 | (0 0) (0 0)
828 00:59:59.768890 0 11 12 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
829 00:59:59.772256 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 00:59:59.779107 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:59:59.782373 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:59:59.785737 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:59:59.792564 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:59:59.795714 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:59:59.799056 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
836 00:59:59.805883 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 00:59:59.809230 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:59:59.812617 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:59:59.819252 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:59:59.822508 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:59:59.825714 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:59:59.832278 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:59:59.835972 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:59:59.839267 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:59:59.845934 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:59:59.849606 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:59:59.852737 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:59:59.856207 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:59:59.862311 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:59:59.866132 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:59:59.868816 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 00:59:59.875576 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 00:59:59.879251 Total UI for P1: 0, mck2ui 16
854 00:59:59.882266 best dqsien dly found for B0: ( 0, 14, 10)
855 00:59:59.886015 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 00:59:59.889335 Total UI for P1: 0, mck2ui 16
857 00:59:59.892327 best dqsien dly found for B1: ( 0, 14, 12)
858 00:59:59.895973 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
859 00:59:59.899245 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
860 00:59:59.899325
861 00:59:59.902263 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 00:59:59.905666 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
863 00:59:59.909135 [Gating] SW calibration Done
864 00:59:59.909218 ==
865 00:59:59.912609 Dram Type= 6, Freq= 0, CH_0, rank 0
866 00:59:59.919427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 00:59:59.919540 ==
868 00:59:59.919627 RX Vref Scan: 0
869 00:59:59.919716
870 00:59:59.922670 RX Vref 0 -> 0, step: 1
871 00:59:59.922747
872 00:59:59.925748 RX Delay -130 -> 252, step: 16
873 00:59:59.929215 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
874 00:59:59.932639 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
875 00:59:59.935785 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 00:59:59.939384 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 00:59:59.946232 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
878 00:59:59.949493 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
879 00:59:59.952922 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 00:59:59.956098 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 00:59:59.959407 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
882 00:59:59.965853 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
883 00:59:59.969049 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 00:59:59.972430 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
885 00:59:59.975907 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
886 00:59:59.979226 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
887 00:59:59.985891 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
888 00:59:59.989348 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
889 00:59:59.989433 ==
890 00:59:59.992568 Dram Type= 6, Freq= 0, CH_0, rank 0
891 00:59:59.996228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 00:59:59.996308 ==
893 00:59:59.999155 DQS Delay:
894 00:59:59.999234 DQS0 = 0, DQS1 = 0
895 00:59:59.999293 DQM Delay:
896 01:00:00.002801 DQM0 = 85, DQM1 = 78
897 01:00:00.002879 DQ Delay:
898 01:00:00.005706 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 01:00:00.009642 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
900 01:00:00.012437 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 01:00:00.015810 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =93
902 01:00:00.015889
903 01:00:00.015949
904 01:00:00.016004 ==
905 01:00:00.019518 Dram Type= 6, Freq= 0, CH_0, rank 0
906 01:00:00.022501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 01:00:00.026357 ==
908 01:00:00.026436
909 01:00:00.026494
910 01:00:00.026549 TX Vref Scan disable
911 01:00:00.029632 == TX Byte 0 ==
912 01:00:00.032826 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 01:00:00.036071 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 01:00:00.039328 == TX Byte 1 ==
915 01:00:00.042782 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
916 01:00:00.046222 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
917 01:00:00.046304 ==
918 01:00:00.049551 Dram Type= 6, Freq= 0, CH_0, rank 0
919 01:00:00.056169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 01:00:00.056258 ==
921 01:00:00.068206 TX Vref=22, minBit 0, minWin=27, winSum=439
922 01:00:00.072041 TX Vref=24, minBit 3, minWin=27, winSum=445
923 01:00:00.074866 TX Vref=26, minBit 5, minWin=27, winSum=445
924 01:00:00.078688 TX Vref=28, minBit 12, minWin=27, winSum=449
925 01:00:00.081675 TX Vref=30, minBit 1, minWin=28, winSum=450
926 01:00:00.088594 TX Vref=32, minBit 0, minWin=28, winSum=451
927 01:00:00.091651 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
928 01:00:00.091739
929 01:00:00.095193 Final TX Range 1 Vref 32
930 01:00:00.095274
931 01:00:00.095333 ==
932 01:00:00.098357 Dram Type= 6, Freq= 0, CH_0, rank 0
933 01:00:00.102144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 01:00:00.102224 ==
935 01:00:00.102284
936 01:00:00.104795
937 01:00:00.104871 TX Vref Scan disable
938 01:00:00.108479 == TX Byte 0 ==
939 01:00:00.111690 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 01:00:00.115469 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 01:00:00.118431 == TX Byte 1 ==
942 01:00:00.121838 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
943 01:00:00.125113 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
944 01:00:00.128323
945 01:00:00.128405 [DATLAT]
946 01:00:00.128465 Freq=800, CH0 RK0
947 01:00:00.128520
948 01:00:00.131801 DATLAT Default: 0xa
949 01:00:00.131879 0, 0xFFFF, sum = 0
950 01:00:00.135362 1, 0xFFFF, sum = 0
951 01:00:00.135445 2, 0xFFFF, sum = 0
952 01:00:00.138479 3, 0xFFFF, sum = 0
953 01:00:00.138558 4, 0xFFFF, sum = 0
954 01:00:00.141943 5, 0xFFFF, sum = 0
955 01:00:00.142059 6, 0xFFFF, sum = 0
956 01:00:00.145033 7, 0xFFFF, sum = 0
957 01:00:00.148549 8, 0xFFFF, sum = 0
958 01:00:00.148629 9, 0x0, sum = 1
959 01:00:00.148689 10, 0x0, sum = 2
960 01:00:00.151697 11, 0x0, sum = 3
961 01:00:00.151776 12, 0x0, sum = 4
962 01:00:00.155591 best_step = 10
963 01:00:00.155675
964 01:00:00.155735 ==
965 01:00:00.158465 Dram Type= 6, Freq= 0, CH_0, rank 0
966 01:00:00.162317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 01:00:00.162399 ==
968 01:00:00.165464 RX Vref Scan: 1
969 01:00:00.165542
970 01:00:00.165601 Set Vref Range= 32 -> 127
971 01:00:00.165656
972 01:00:00.168997 RX Vref 32 -> 127, step: 1
973 01:00:00.169082
974 01:00:00.172014 RX Delay -95 -> 252, step: 8
975 01:00:00.172094
976 01:00:00.175302 Set Vref, RX VrefLevel [Byte0]: 32
977 01:00:00.178564 [Byte1]: 32
978 01:00:00.178647
979 01:00:00.181946 Set Vref, RX VrefLevel [Byte0]: 33
980 01:00:00.185427 [Byte1]: 33
981 01:00:00.188769
982 01:00:00.188851 Set Vref, RX VrefLevel [Byte0]: 34
983 01:00:00.192298 [Byte1]: 34
984 01:00:00.196205
985 01:00:00.196286 Set Vref, RX VrefLevel [Byte0]: 35
986 01:00:00.199626 [Byte1]: 35
987 01:00:00.203817
988 01:00:00.203900 Set Vref, RX VrefLevel [Byte0]: 36
989 01:00:00.207502 [Byte1]: 36
990 01:00:00.211898
991 01:00:00.211982 Set Vref, RX VrefLevel [Byte0]: 37
992 01:00:00.215000 [Byte1]: 37
993 01:00:00.219371
994 01:00:00.219455 Set Vref, RX VrefLevel [Byte0]: 38
995 01:00:00.222395 [Byte1]: 38
996 01:00:00.227006
997 01:00:00.227093 Set Vref, RX VrefLevel [Byte0]: 39
998 01:00:00.229905 [Byte1]: 39
999 01:00:00.234789
1000 01:00:00.234894 Set Vref, RX VrefLevel [Byte0]: 40
1001 01:00:00.237439 [Byte1]: 40
1002 01:00:00.242245
1003 01:00:00.242332 Set Vref, RX VrefLevel [Byte0]: 41
1004 01:00:00.245213 [Byte1]: 41
1005 01:00:00.249522
1006 01:00:00.249607 Set Vref, RX VrefLevel [Byte0]: 42
1007 01:00:00.253076 [Byte1]: 42
1008 01:00:00.257007
1009 01:00:00.257116 Set Vref, RX VrefLevel [Byte0]: 43
1010 01:00:00.260367 [Byte1]: 43
1011 01:00:00.264662
1012 01:00:00.264744 Set Vref, RX VrefLevel [Byte0]: 44
1013 01:00:00.267863 [Byte1]: 44
1014 01:00:00.272523
1015 01:00:00.272610 Set Vref, RX VrefLevel [Byte0]: 45
1016 01:00:00.275641 [Byte1]: 45
1017 01:00:00.279849
1018 01:00:00.279933 Set Vref, RX VrefLevel [Byte0]: 46
1019 01:00:00.283346 [Byte1]: 46
1020 01:00:00.287348
1021 01:00:00.287431 Set Vref, RX VrefLevel [Byte0]: 47
1022 01:00:00.290609 [Byte1]: 47
1023 01:00:00.295078
1024 01:00:00.295160 Set Vref, RX VrefLevel [Byte0]: 48
1025 01:00:00.298301 [Byte1]: 48
1026 01:00:00.302912
1027 01:00:00.302996 Set Vref, RX VrefLevel [Byte0]: 49
1028 01:00:00.306171 [Byte1]: 49
1029 01:00:00.310291
1030 01:00:00.310374 Set Vref, RX VrefLevel [Byte0]: 50
1031 01:00:00.313369 [Byte1]: 50
1032 01:00:00.317684
1033 01:00:00.317768 Set Vref, RX VrefLevel [Byte0]: 51
1034 01:00:00.321523 [Byte1]: 51
1035 01:00:00.325389
1036 01:00:00.325470 Set Vref, RX VrefLevel [Byte0]: 52
1037 01:00:00.328887 [Byte1]: 52
1038 01:00:00.332777
1039 01:00:00.332859 Set Vref, RX VrefLevel [Byte0]: 53
1040 01:00:00.336145 [Byte1]: 53
1041 01:00:00.340602
1042 01:00:00.340685 Set Vref, RX VrefLevel [Byte0]: 54
1043 01:00:00.343816 [Byte1]: 54
1044 01:00:00.348242
1045 01:00:00.348326 Set Vref, RX VrefLevel [Byte0]: 55
1046 01:00:00.351369 [Byte1]: 55
1047 01:00:00.356153
1048 01:00:00.356239 Set Vref, RX VrefLevel [Byte0]: 56
1049 01:00:00.359019 [Byte1]: 56
1050 01:00:00.363812
1051 01:00:00.363898 Set Vref, RX VrefLevel [Byte0]: 57
1052 01:00:00.366807 [Byte1]: 57
1053 01:00:00.370909
1054 01:00:00.370993 Set Vref, RX VrefLevel [Byte0]: 58
1055 01:00:00.374244 [Byte1]: 58
1056 01:00:00.378480
1057 01:00:00.378563 Set Vref, RX VrefLevel [Byte0]: 59
1058 01:00:00.382161 [Byte1]: 59
1059 01:00:00.386382
1060 01:00:00.386463 Set Vref, RX VrefLevel [Byte0]: 60
1061 01:00:00.389760 [Byte1]: 60
1062 01:00:00.393765
1063 01:00:00.393845 Set Vref, RX VrefLevel [Byte0]: 61
1064 01:00:00.397055 [Byte1]: 61
1065 01:00:00.401821
1066 01:00:00.401904 Set Vref, RX VrefLevel [Byte0]: 62
1067 01:00:00.404551 [Byte1]: 62
1068 01:00:00.409210
1069 01:00:00.409294 Set Vref, RX VrefLevel [Byte0]: 63
1070 01:00:00.412550 [Byte1]: 63
1071 01:00:00.416337
1072 01:00:00.416416 Set Vref, RX VrefLevel [Byte0]: 64
1073 01:00:00.420095 [Byte1]: 64
1074 01:00:00.424218
1075 01:00:00.424297 Set Vref, RX VrefLevel [Byte0]: 65
1076 01:00:00.428006 [Byte1]: 65
1077 01:00:00.431584
1078 01:00:00.434907 Set Vref, RX VrefLevel [Byte0]: 66
1079 01:00:00.438222 [Byte1]: 66
1080 01:00:00.438304
1081 01:00:00.441799 Set Vref, RX VrefLevel [Byte0]: 67
1082 01:00:00.444627 [Byte1]: 67
1083 01:00:00.444706
1084 01:00:00.448341 Set Vref, RX VrefLevel [Byte0]: 68
1085 01:00:00.451538 [Byte1]: 68
1086 01:00:00.451617
1087 01:00:00.455046 Set Vref, RX VrefLevel [Byte0]: 69
1088 01:00:00.458184 [Byte1]: 69
1089 01:00:00.462214
1090 01:00:00.462296 Set Vref, RX VrefLevel [Byte0]: 70
1091 01:00:00.465335 [Byte1]: 70
1092 01:00:00.469585
1093 01:00:00.469702 Set Vref, RX VrefLevel [Byte0]: 71
1094 01:00:00.472828 [Byte1]: 71
1095 01:00:00.477375
1096 01:00:00.477462 Set Vref, RX VrefLevel [Byte0]: 72
1097 01:00:00.480621 [Byte1]: 72
1098 01:00:00.484857
1099 01:00:00.484939 Set Vref, RX VrefLevel [Byte0]: 73
1100 01:00:00.488089 [Byte1]: 73
1101 01:00:00.492510
1102 01:00:00.492593 Set Vref, RX VrefLevel [Byte0]: 74
1103 01:00:00.495587 [Byte1]: 74
1104 01:00:00.500187
1105 01:00:00.500270 Set Vref, RX VrefLevel [Byte0]: 75
1106 01:00:00.503635 [Byte1]: 75
1107 01:00:00.507513
1108 01:00:00.507596 Set Vref, RX VrefLevel [Byte0]: 76
1109 01:00:00.510789 [Byte1]: 76
1110 01:00:00.515125
1111 01:00:00.515207 Final RX Vref Byte 0 = 62 to rank0
1112 01:00:00.518451 Final RX Vref Byte 1 = 58 to rank0
1113 01:00:00.522204 Final RX Vref Byte 0 = 62 to rank1
1114 01:00:00.525630 Final RX Vref Byte 1 = 58 to rank1==
1115 01:00:00.528633 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 01:00:00.535156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 01:00:00.535248 ==
1118 01:00:00.535310 DQS Delay:
1119 01:00:00.535365 DQS0 = 0, DQS1 = 0
1120 01:00:00.538590 DQM Delay:
1121 01:00:00.538668 DQM0 = 86, DQM1 = 79
1122 01:00:00.541734 DQ Delay:
1123 01:00:00.545463 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1124 01:00:00.548377 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1125 01:00:00.548459 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =76
1126 01:00:00.555651 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1127 01:00:00.555749
1128 01:00:00.555810
1129 01:00:00.561896 [DQSOSCAuto] RK0, (LSB)MR18= 0x280f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 399 ps
1130 01:00:00.565059 CH0 RK0: MR19=606, MR18=280F
1131 01:00:00.571760 CH0_RK0: MR19=0x606, MR18=0x280F, DQSOSC=399, MR23=63, INC=92, DEC=61
1132 01:00:00.571882
1133 01:00:00.575149 ----->DramcWriteLeveling(PI) begin...
1134 01:00:00.575231 ==
1135 01:00:00.578415 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 01:00:00.582264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 01:00:00.582347 ==
1138 01:00:00.585152 Write leveling (Byte 0): 29 => 29
1139 01:00:00.588643 Write leveling (Byte 1): 29 => 29
1140 01:00:00.592269 DramcWriteLeveling(PI) end<-----
1141 01:00:00.592352
1142 01:00:00.592413 ==
1143 01:00:00.595422 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 01:00:00.598809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 01:00:00.598890 ==
1146 01:00:00.602105 [Gating] SW mode calibration
1147 01:00:00.608368 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 01:00:00.615524 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 01:00:00.618656 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 01:00:00.621919 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 01:00:00.628808 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 01:00:00.632254 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 01:00:00.635292 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 01:00:00.641874 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 01:00:00.685789 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 01:00:00.686120 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 01:00:00.686210 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 01:00:00.686270 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 01:00:00.686768 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:00:00.687146 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:00:00.687880 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:00:00.687957 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:00:00.688196 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:00:00.688435 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 01:00:00.691924 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 01:00:00.694759 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1167 01:00:00.698089 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1168 01:00:00.701425 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 01:00:00.708407 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 01:00:00.711425 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 01:00:00.714785 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 01:00:00.718172 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 01:00:00.725134 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 01:00:00.728114 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 01:00:00.731441 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1176 01:00:00.737879 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1177 01:00:00.741186 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 01:00:00.744836 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 01:00:00.751537 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 01:00:00.755168 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 01:00:00.758439 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 01:00:00.765028 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1183 01:00:00.767948 0 10 8 | B1->B0 | 3333 2727 | 0 0 | (0 0) (0 0)
1184 01:00:00.771756 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1185 01:00:00.778276 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 01:00:00.781470 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 01:00:00.785256 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 01:00:00.791536 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 01:00:00.794748 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 01:00:00.798342 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1191 01:00:00.804593 0 11 8 | B1->B0 | 2f2f 3f3f | 0 0 | (0 0) (0 0)
1192 01:00:00.807895 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1193 01:00:00.811571 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 01:00:00.815188 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 01:00:00.821323 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 01:00:00.824787 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 01:00:00.828072 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 01:00:00.834887 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1199 01:00:00.837690 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1200 01:00:00.841483 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 01:00:00.848160 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 01:00:00.851570 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 01:00:00.854745 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 01:00:00.861510 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 01:00:00.864793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 01:00:00.868346 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 01:00:00.874810 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 01:00:00.878144 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 01:00:00.881344 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 01:00:00.888253 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 01:00:00.891659 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 01:00:00.894908 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 01:00:00.901399 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 01:00:00.904631 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1215 01:00:00.908220 Total UI for P1: 0, mck2ui 16
1216 01:00:00.911848 best dqsien dly found for B0: ( 0, 14, 2)
1217 01:00:00.915105 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 01:00:00.918444 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 01:00:00.921503 Total UI for P1: 0, mck2ui 16
1220 01:00:00.924931 best dqsien dly found for B1: ( 0, 14, 6)
1221 01:00:00.928094 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1222 01:00:00.931562 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1223 01:00:00.934843
1224 01:00:00.938239 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1225 01:00:00.941744 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1226 01:00:00.944569 [Gating] SW calibration Done
1227 01:00:00.944649 ==
1228 01:00:00.948221 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 01:00:00.951482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 01:00:00.951566 ==
1231 01:00:00.951626 RX Vref Scan: 0
1232 01:00:00.951681
1233 01:00:00.954869 RX Vref 0 -> 0, step: 1
1234 01:00:00.954947
1235 01:00:00.957949 RX Delay -130 -> 252, step: 16
1236 01:00:00.961411 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1237 01:00:00.964653 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1238 01:00:00.971185 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1239 01:00:00.974501 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1240 01:00:00.977685 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1241 01:00:00.981343 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1242 01:00:00.984614 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1243 01:00:00.991235 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1244 01:00:00.994719 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 01:00:00.997906 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1246 01:00:01.001368 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1247 01:00:01.004942 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1248 01:00:01.011357 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1249 01:00:01.014476 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1250 01:00:01.017737 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1251 01:00:01.021265 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1252 01:00:01.021347 ==
1253 01:00:01.024613 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 01:00:01.031371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 01:00:01.031463 ==
1256 01:00:01.031522 DQS Delay:
1257 01:00:01.031577 DQS0 = 0, DQS1 = 0
1258 01:00:01.034771 DQM Delay:
1259 01:00:01.034851 DQM0 = 85, DQM1 = 77
1260 01:00:01.037897 DQ Delay:
1261 01:00:01.041389 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1262 01:00:01.041471 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1263 01:00:01.044723 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1264 01:00:01.048302 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1265 01:00:01.051616
1266 01:00:01.051696
1267 01:00:01.051755 ==
1268 01:00:01.054304 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 01:00:01.057689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 01:00:01.057768 ==
1271 01:00:01.057826
1272 01:00:01.057879
1273 01:00:01.061531 TX Vref Scan disable
1274 01:00:01.061609 == TX Byte 0 ==
1275 01:00:01.067888 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1276 01:00:01.071354 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1277 01:00:01.071438 == TX Byte 1 ==
1278 01:00:01.077740 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1279 01:00:01.081022 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1280 01:00:01.081105 ==
1281 01:00:01.084851 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 01:00:01.087946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 01:00:01.088027 ==
1284 01:00:01.101274 TX Vref=22, minBit 1, minWin=27, winSum=439
1285 01:00:01.104550 TX Vref=24, minBit 2, minWin=27, winSum=445
1286 01:00:01.108198 TX Vref=26, minBit 3, minWin=27, winSum=449
1287 01:00:01.111530 TX Vref=28, minBit 3, minWin=27, winSum=452
1288 01:00:01.114939 TX Vref=30, minBit 0, minWin=28, winSum=456
1289 01:00:01.118018 TX Vref=32, minBit 4, minWin=27, winSum=452
1290 01:00:01.124912 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1291 01:00:01.125006
1292 01:00:01.127911 Final TX Range 1 Vref 30
1293 01:00:01.128013
1294 01:00:01.128105 ==
1295 01:00:01.131761 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 01:00:01.134587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 01:00:01.134665 ==
1298 01:00:01.134725
1299 01:00:01.138072
1300 01:00:01.138149 TX Vref Scan disable
1301 01:00:01.141158 == TX Byte 0 ==
1302 01:00:01.144725 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1303 01:00:01.148077 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1304 01:00:01.151018 == TX Byte 1 ==
1305 01:00:01.154356 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1306 01:00:01.161165 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1307 01:00:01.161261
1308 01:00:01.161320 [DATLAT]
1309 01:00:01.161374 Freq=800, CH0 RK1
1310 01:00:01.161426
1311 01:00:01.164431 DATLAT Default: 0xa
1312 01:00:01.164509 0, 0xFFFF, sum = 0
1313 01:00:01.168076 1, 0xFFFF, sum = 0
1314 01:00:01.168155 2, 0xFFFF, sum = 0
1315 01:00:01.171093 3, 0xFFFF, sum = 0
1316 01:00:01.171173 4, 0xFFFF, sum = 0
1317 01:00:01.174745 5, 0xFFFF, sum = 0
1318 01:00:01.177882 6, 0xFFFF, sum = 0
1319 01:00:01.177962 7, 0xFFFF, sum = 0
1320 01:00:01.181095 8, 0xFFFF, sum = 0
1321 01:00:01.181174 9, 0x0, sum = 1
1322 01:00:01.181235 10, 0x0, sum = 2
1323 01:00:01.184605 11, 0x0, sum = 3
1324 01:00:01.184683 12, 0x0, sum = 4
1325 01:00:01.188143 best_step = 10
1326 01:00:01.188221
1327 01:00:01.188279 ==
1328 01:00:01.191445 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 01:00:01.194711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 01:00:01.194791 ==
1331 01:00:01.198202 RX Vref Scan: 0
1332 01:00:01.198279
1333 01:00:01.198338 RX Vref 0 -> 0, step: 1
1334 01:00:01.198393
1335 01:00:01.201444 RX Delay -95 -> 252, step: 8
1336 01:00:01.208040 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1337 01:00:01.211761 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 01:00:01.214741 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1339 01:00:01.218266 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1340 01:00:01.221731 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 01:00:01.228305 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 01:00:01.231446 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 01:00:01.235015 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 01:00:01.238098 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 01:00:01.241427 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 01:00:01.245133 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 01:00:01.251744 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 01:00:01.255398 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1349 01:00:01.258202 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1350 01:00:01.261684 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 01:00:01.268433 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1352 01:00:01.268525 ==
1353 01:00:01.271602 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 01:00:01.275168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 01:00:01.275256 ==
1356 01:00:01.275317 DQS Delay:
1357 01:00:01.278454 DQS0 = 0, DQS1 = 0
1358 01:00:01.278533 DQM Delay:
1359 01:00:01.281438 DQM0 = 87, DQM1 = 78
1360 01:00:01.281515 DQ Delay:
1361 01:00:01.284748 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1362 01:00:01.288260 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1363 01:00:01.291417 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1364 01:00:01.295008 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1365 01:00:01.295089
1366 01:00:01.295149
1367 01:00:01.301681 [DQSOSCAuto] RK1, (LSB)MR18= 0x311b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1368 01:00:01.304644 CH0 RK1: MR19=606, MR18=311B
1369 01:00:01.311314 CH0_RK1: MR19=0x606, MR18=0x311B, DQSOSC=397, MR23=63, INC=93, DEC=62
1370 01:00:01.314736 [RxdqsGatingPostProcess] freq 800
1371 01:00:01.321408 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 01:00:01.324210 Pre-setting of DQS Precalculation
1373 01:00:01.327789 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 01:00:01.327867 ==
1375 01:00:01.331086 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 01:00:01.334561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 01:00:01.334652 ==
1378 01:00:01.341393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 01:00:01.347798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 01:00:01.356106 [CA 0] Center 36 (6~66) winsize 61
1381 01:00:01.359739 [CA 1] Center 36 (6~66) winsize 61
1382 01:00:01.362752 [CA 2] Center 35 (5~65) winsize 61
1383 01:00:01.366181 [CA 3] Center 33 (3~64) winsize 62
1384 01:00:01.369921 [CA 4] Center 34 (4~65) winsize 62
1385 01:00:01.372956 [CA 5] Center 33 (3~64) winsize 62
1386 01:00:01.373033
1387 01:00:01.376388 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 01:00:01.376466
1389 01:00:01.379876 [CATrainingPosCal] consider 1 rank data
1390 01:00:01.382890 u2DelayCellTimex100 = 270/100 ps
1391 01:00:01.386115 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1392 01:00:01.389869 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1393 01:00:01.393238 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1394 01:00:01.399843 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 01:00:01.403349 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 01:00:01.406195 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 01:00:01.406272
1398 01:00:01.410148 CA PerBit enable=1, Macro0, CA PI delay=33
1399 01:00:01.410227
1400 01:00:01.413135 [CBTSetCACLKResult] CA Dly = 33
1401 01:00:01.413211 CS Dly: 4 (0~35)
1402 01:00:01.413270 ==
1403 01:00:01.416803 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 01:00:01.423200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 01:00:01.423277 ==
1406 01:00:01.426297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 01:00:01.432766 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 01:00:01.442177 [CA 0] Center 36 (6~66) winsize 61
1409 01:00:01.445411 [CA 1] Center 36 (6~66) winsize 61
1410 01:00:01.448722 [CA 2] Center 34 (4~65) winsize 62
1411 01:00:01.452430 [CA 3] Center 33 (3~64) winsize 62
1412 01:00:01.456037 [CA 4] Center 34 (4~65) winsize 62
1413 01:00:01.459389 [CA 5] Center 33 (3~64) winsize 62
1414 01:00:01.459465
1415 01:00:01.462499 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 01:00:01.462575
1417 01:00:01.465897 [CATrainingPosCal] consider 2 rank data
1418 01:00:01.469311 u2DelayCellTimex100 = 270/100 ps
1419 01:00:01.472134 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 01:00:01.475521 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 01:00:01.479203 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1422 01:00:01.485692 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 01:00:01.489279 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 01:00:01.492732 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 01:00:01.492809
1426 01:00:01.495815 CA PerBit enable=1, Macro0, CA PI delay=33
1427 01:00:01.495892
1428 01:00:01.499065 [CBTSetCACLKResult] CA Dly = 33
1429 01:00:01.499142 CS Dly: 5 (0~38)
1430 01:00:01.499202
1431 01:00:01.502597 ----->DramcWriteLeveling(PI) begin...
1432 01:00:01.502674 ==
1433 01:00:01.505969 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 01:00:01.512559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 01:00:01.512637 ==
1436 01:00:01.515833 Write leveling (Byte 0): 28 => 28
1437 01:00:01.519146 Write leveling (Byte 1): 29 => 29
1438 01:00:01.519222 DramcWriteLeveling(PI) end<-----
1439 01:00:01.522401
1440 01:00:01.522477 ==
1441 01:00:01.525568 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 01:00:01.529041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 01:00:01.529118 ==
1444 01:00:01.532307 [Gating] SW mode calibration
1445 01:00:01.539431 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 01:00:01.542456 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 01:00:01.549211 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 01:00:01.552593 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1449 01:00:01.555858 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 01:00:01.562423 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 01:00:01.565676 0 6 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1452 01:00:01.569654 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 01:00:01.575816 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 01:00:01.579118 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 01:00:01.582272 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 01:00:01.589150 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:00:01.592561 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:00:01.595945 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 01:00:01.599274 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1460 01:00:01.606366 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:00:01.609431 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 01:00:01.612497 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 01:00:01.619166 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1464 01:00:01.622363 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1465 01:00:01.626329 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1466 01:00:01.632787 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 01:00:01.636134 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 01:00:01.639096 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 01:00:01.646141 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 01:00:01.649460 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 01:00:01.652497 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 01:00:01.659333 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 01:00:01.662833 0 9 8 | B1->B0 | 2525 2525 | 0 1 | (1 1) (0 0)
1474 01:00:01.666152 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1475 01:00:01.672702 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 01:00:01.675911 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1477 01:00:01.679615 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1478 01:00:01.686184 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 01:00:01.689502 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 01:00:01.692500 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1481 01:00:01.696102 0 10 8 | B1->B0 | 2f2f 2e2e | 0 1 | (0 1) (1 0)
1482 01:00:01.702713 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 01:00:01.706187 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 01:00:01.709333 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 01:00:01.716078 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 01:00:01.719241 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 01:00:01.722528 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 01:00:01.729554 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 01:00:01.732788 0 11 8 | B1->B0 | 3838 3838 | 0 1 | (0 0) (0 0)
1490 01:00:01.735951 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1491 01:00:01.742450 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 01:00:01.746223 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 01:00:01.749759 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 01:00:01.755854 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 01:00:01.759339 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 01:00:01.762796 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 01:00:01.769542 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 01:00:01.772877 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 01:00:01.776300 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 01:00:01.779571 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 01:00:01.786421 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 01:00:01.789335 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 01:00:01.792832 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 01:00:01.799448 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 01:00:01.802813 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 01:00:01.806120 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 01:00:01.812712 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 01:00:01.815815 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 01:00:01.819659 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 01:00:01.826418 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 01:00:01.829462 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 01:00:01.832984 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 01:00:01.839160 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 01:00:01.839238 Total UI for P1: 0, mck2ui 16
1515 01:00:01.845946 best dqsien dly found for B0: ( 0, 14, 6)
1516 01:00:01.846029 Total UI for P1: 0, mck2ui 16
1517 01:00:01.849453 best dqsien dly found for B1: ( 0, 14, 6)
1518 01:00:01.855856 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1519 01:00:01.859459 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1520 01:00:01.859537
1521 01:00:01.862537 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 01:00:01.866100 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1523 01:00:01.869144 [Gating] SW calibration Done
1524 01:00:01.869220 ==
1525 01:00:01.872669 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 01:00:01.875982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 01:00:01.876059 ==
1528 01:00:01.879718 RX Vref Scan: 0
1529 01:00:01.879793
1530 01:00:01.879851 RX Vref 0 -> 0, step: 1
1531 01:00:01.879906
1532 01:00:01.883099 RX Delay -130 -> 252, step: 16
1533 01:00:01.886356 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1534 01:00:01.892880 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1535 01:00:01.895828 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1536 01:00:01.899561 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1537 01:00:01.902852 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1538 01:00:01.906313 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1539 01:00:01.909635 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1540 01:00:01.915886 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1541 01:00:01.919066 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1542 01:00:01.922840 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1543 01:00:01.926122 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1544 01:00:01.929270 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1545 01:00:01.936447 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1546 01:00:01.939262 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1547 01:00:01.942768 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1548 01:00:01.946293 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1549 01:00:01.946372 ==
1550 01:00:01.949635 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 01:00:01.956053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 01:00:01.956137 ==
1553 01:00:01.956215 DQS Delay:
1554 01:00:01.959847 DQS0 = 0, DQS1 = 0
1555 01:00:01.959924 DQM Delay:
1556 01:00:01.959999 DQM0 = 83, DQM1 = 75
1557 01:00:01.962900 DQ Delay:
1558 01:00:01.966284 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1559 01:00:01.969655 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =77
1560 01:00:01.972846 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1561 01:00:01.976145 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1562 01:00:01.976226
1563 01:00:01.976303
1564 01:00:01.976375 ==
1565 01:00:01.979509 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 01:00:01.982837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 01:00:01.982923 ==
1568 01:00:01.983040
1569 01:00:01.983148
1570 01:00:01.986185 TX Vref Scan disable
1571 01:00:01.986263 == TX Byte 0 ==
1572 01:00:01.992976 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1573 01:00:01.996462 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1574 01:00:01.996542 == TX Byte 1 ==
1575 01:00:02.003211 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1576 01:00:02.006262 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1577 01:00:02.006342 ==
1578 01:00:02.009542 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 01:00:02.012828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 01:00:02.012909 ==
1581 01:00:02.026878 TX Vref=22, minBit 0, minWin=27, winSum=439
1582 01:00:02.029966 TX Vref=24, minBit 1, minWin=27, winSum=443
1583 01:00:02.033325 TX Vref=26, minBit 0, minWin=27, winSum=444
1584 01:00:02.036719 TX Vref=28, minBit 8, minWin=27, winSum=452
1585 01:00:02.040079 TX Vref=30, minBit 0, minWin=28, winSum=453
1586 01:00:02.043500 TX Vref=32, minBit 0, minWin=28, winSum=455
1587 01:00:02.049952 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 32
1588 01:00:02.050077
1589 01:00:02.053318 Final TX Range 1 Vref 32
1590 01:00:02.053395
1591 01:00:02.053482 ==
1592 01:00:02.056843 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 01:00:02.060190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 01:00:02.060274 ==
1595 01:00:02.060333
1596 01:00:02.063570
1597 01:00:02.063648 TX Vref Scan disable
1598 01:00:02.066954 == TX Byte 0 ==
1599 01:00:02.070439 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1600 01:00:02.073536 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1601 01:00:02.076636 == TX Byte 1 ==
1602 01:00:02.080014 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1603 01:00:02.083366 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1604 01:00:02.083444
1605 01:00:02.086573 [DATLAT]
1606 01:00:02.086650 Freq=800, CH1 RK0
1607 01:00:02.086709
1608 01:00:02.090147 DATLAT Default: 0xa
1609 01:00:02.090225 0, 0xFFFF, sum = 0
1610 01:00:02.093417 1, 0xFFFF, sum = 0
1611 01:00:02.093496 2, 0xFFFF, sum = 0
1612 01:00:02.096879 3, 0xFFFF, sum = 0
1613 01:00:02.096957 4, 0xFFFF, sum = 0
1614 01:00:02.099932 5, 0xFFFF, sum = 0
1615 01:00:02.100009 6, 0xFFFF, sum = 0
1616 01:00:02.103525 7, 0xFFFF, sum = 0
1617 01:00:02.106685 8, 0xFFFF, sum = 0
1618 01:00:02.106763 9, 0x0, sum = 1
1619 01:00:02.106822 10, 0x0, sum = 2
1620 01:00:02.110148 11, 0x0, sum = 3
1621 01:00:02.110226 12, 0x0, sum = 4
1622 01:00:02.113700 best_step = 10
1623 01:00:02.113776
1624 01:00:02.113834 ==
1625 01:00:02.117051 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 01:00:02.120327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 01:00:02.120404 ==
1628 01:00:02.123629 RX Vref Scan: 1
1629 01:00:02.123705
1630 01:00:02.123763 Set Vref Range= 32 -> 127
1631 01:00:02.123818
1632 01:00:02.126716 RX Vref 32 -> 127, step: 1
1633 01:00:02.126784
1634 01:00:02.129992 RX Delay -111 -> 252, step: 8
1635 01:00:02.130101
1636 01:00:02.133404 Set Vref, RX VrefLevel [Byte0]: 32
1637 01:00:02.136983 [Byte1]: 32
1638 01:00:02.137060
1639 01:00:02.139960 Set Vref, RX VrefLevel [Byte0]: 33
1640 01:00:02.143492 [Byte1]: 33
1641 01:00:02.147289
1642 01:00:02.147366 Set Vref, RX VrefLevel [Byte0]: 34
1643 01:00:02.150562 [Byte1]: 34
1644 01:00:02.154764
1645 01:00:02.154842 Set Vref, RX VrefLevel [Byte0]: 35
1646 01:00:02.158001 [Byte1]: 35
1647 01:00:02.162400
1648 01:00:02.162479 Set Vref, RX VrefLevel [Byte0]: 36
1649 01:00:02.165955 [Byte1]: 36
1650 01:00:02.169877
1651 01:00:02.169977 Set Vref, RX VrefLevel [Byte0]: 37
1652 01:00:02.173509 [Byte1]: 37
1653 01:00:02.177686
1654 01:00:02.177766 Set Vref, RX VrefLevel [Byte0]: 38
1655 01:00:02.181079 [Byte1]: 38
1656 01:00:02.185637
1657 01:00:02.185727 Set Vref, RX VrefLevel [Byte0]: 39
1658 01:00:02.188478 [Byte1]: 39
1659 01:00:02.193309
1660 01:00:02.193432 Set Vref, RX VrefLevel [Byte0]: 40
1661 01:00:02.196030 [Byte1]: 40
1662 01:00:02.200932
1663 01:00:02.201027 Set Vref, RX VrefLevel [Byte0]: 41
1664 01:00:02.204018 [Byte1]: 41
1665 01:00:02.208400
1666 01:00:02.208510 Set Vref, RX VrefLevel [Byte0]: 42
1667 01:00:02.211257 [Byte1]: 42
1668 01:00:02.215770
1669 01:00:02.215872 Set Vref, RX VrefLevel [Byte0]: 43
1670 01:00:02.219024 [Byte1]: 43
1671 01:00:02.223749
1672 01:00:02.223855 Set Vref, RX VrefLevel [Byte0]: 44
1673 01:00:02.227114 [Byte1]: 44
1674 01:00:02.231326
1675 01:00:02.231435 Set Vref, RX VrefLevel [Byte0]: 45
1676 01:00:02.234304 [Byte1]: 45
1677 01:00:02.238677
1678 01:00:02.238772 Set Vref, RX VrefLevel [Byte0]: 46
1679 01:00:02.242247 [Byte1]: 46
1680 01:00:02.246428
1681 01:00:02.246520 Set Vref, RX VrefLevel [Byte0]: 47
1682 01:00:02.249704 [Byte1]: 47
1683 01:00:02.254355
1684 01:00:02.254467 Set Vref, RX VrefLevel [Byte0]: 48
1685 01:00:02.257653 [Byte1]: 48
1686 01:00:02.261510
1687 01:00:02.261601 Set Vref, RX VrefLevel [Byte0]: 49
1688 01:00:02.265272 [Byte1]: 49
1689 01:00:02.269420
1690 01:00:02.269508 Set Vref, RX VrefLevel [Byte0]: 50
1691 01:00:02.272622 [Byte1]: 50
1692 01:00:02.277310
1693 01:00:02.277392 Set Vref, RX VrefLevel [Byte0]: 51
1694 01:00:02.280223 [Byte1]: 51
1695 01:00:02.284614
1696 01:00:02.284690 Set Vref, RX VrefLevel [Byte0]: 52
1697 01:00:02.288286 [Byte1]: 52
1698 01:00:02.292105
1699 01:00:02.292182 Set Vref, RX VrefLevel [Byte0]: 53
1700 01:00:02.295924 [Byte1]: 53
1701 01:00:02.299922
1702 01:00:02.299998 Set Vref, RX VrefLevel [Byte0]: 54
1703 01:00:02.303129 [Byte1]: 54
1704 01:00:02.307478
1705 01:00:02.307554 Set Vref, RX VrefLevel [Byte0]: 55
1706 01:00:02.310762 [Byte1]: 55
1707 01:00:02.315320
1708 01:00:02.315397 Set Vref, RX VrefLevel [Byte0]: 56
1709 01:00:02.318533 [Byte1]: 56
1710 01:00:02.322892
1711 01:00:02.322968 Set Vref, RX VrefLevel [Byte0]: 57
1712 01:00:02.326275 [Byte1]: 57
1713 01:00:02.330823
1714 01:00:02.330900 Set Vref, RX VrefLevel [Byte0]: 58
1715 01:00:02.333651 [Byte1]: 58
1716 01:00:02.338225
1717 01:00:02.338303 Set Vref, RX VrefLevel [Byte0]: 59
1718 01:00:02.341748 [Byte1]: 59
1719 01:00:02.346203
1720 01:00:02.346280 Set Vref, RX VrefLevel [Byte0]: 60
1721 01:00:02.349377 [Byte1]: 60
1722 01:00:02.353596
1723 01:00:02.353673 Set Vref, RX VrefLevel [Byte0]: 61
1724 01:00:02.357126 [Byte1]: 61
1725 01:00:02.361386
1726 01:00:02.361466 Set Vref, RX VrefLevel [Byte0]: 62
1727 01:00:02.364618 [Byte1]: 62
1728 01:00:02.368629
1729 01:00:02.368705 Set Vref, RX VrefLevel [Byte0]: 63
1730 01:00:02.372222 [Byte1]: 63
1731 01:00:02.376669
1732 01:00:02.376747 Set Vref, RX VrefLevel [Byte0]: 64
1733 01:00:02.379801 [Byte1]: 64
1734 01:00:02.384272
1735 01:00:02.384353 Set Vref, RX VrefLevel [Byte0]: 65
1736 01:00:02.387480 [Byte1]: 65
1737 01:00:02.391945
1738 01:00:02.392021 Set Vref, RX VrefLevel [Byte0]: 66
1739 01:00:02.394816 [Byte1]: 66
1740 01:00:02.399291
1741 01:00:02.399396 Set Vref, RX VrefLevel [Byte0]: 67
1742 01:00:02.402784 [Byte1]: 67
1743 01:00:02.406805
1744 01:00:02.406888 Set Vref, RX VrefLevel [Byte0]: 68
1745 01:00:02.410473 [Byte1]: 68
1746 01:00:02.414425
1747 01:00:02.414513 Set Vref, RX VrefLevel [Byte0]: 69
1748 01:00:02.417958 [Byte1]: 69
1749 01:00:02.422242
1750 01:00:02.422326 Set Vref, RX VrefLevel [Byte0]: 70
1751 01:00:02.425515 [Byte1]: 70
1752 01:00:02.429956
1753 01:00:02.430075 Set Vref, RX VrefLevel [Byte0]: 71
1754 01:00:02.433145 [Byte1]: 71
1755 01:00:02.437552
1756 01:00:02.437646 Set Vref, RX VrefLevel [Byte0]: 72
1757 01:00:02.440720 [Byte1]: 72
1758 01:00:02.445192
1759 01:00:02.445272 Set Vref, RX VrefLevel [Byte0]: 73
1760 01:00:02.448260 [Byte1]: 73
1761 01:00:02.452787
1762 01:00:02.452868 Set Vref, RX VrefLevel [Byte0]: 74
1763 01:00:02.456282 [Byte1]: 74
1764 01:00:02.460357
1765 01:00:02.460436 Set Vref, RX VrefLevel [Byte0]: 75
1766 01:00:02.464030 [Byte1]: 75
1767 01:00:02.468299
1768 01:00:02.468376 Set Vref, RX VrefLevel [Byte0]: 76
1769 01:00:02.471604 [Byte1]: 76
1770 01:00:02.476133
1771 01:00:02.476210 Set Vref, RX VrefLevel [Byte0]: 77
1772 01:00:02.479299 [Byte1]: 77
1773 01:00:02.483446
1774 01:00:02.483525 Set Vref, RX VrefLevel [Byte0]: 78
1775 01:00:02.486940 [Byte1]: 78
1776 01:00:02.491159
1777 01:00:02.491237 Final RX Vref Byte 0 = 60 to rank0
1778 01:00:02.494486 Final RX Vref Byte 1 = 60 to rank0
1779 01:00:02.497537 Final RX Vref Byte 0 = 60 to rank1
1780 01:00:02.501023 Final RX Vref Byte 1 = 60 to rank1==
1781 01:00:02.504746 Dram Type= 6, Freq= 0, CH_1, rank 0
1782 01:00:02.511283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 01:00:02.511371 ==
1784 01:00:02.511433 DQS Delay:
1785 01:00:02.511488 DQS0 = 0, DQS1 = 0
1786 01:00:02.514693 DQM Delay:
1787 01:00:02.514772 DQM0 = 82, DQM1 = 74
1788 01:00:02.518253 DQ Delay:
1789 01:00:02.520934 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =84
1790 01:00:02.521015 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =76
1791 01:00:02.524237 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1792 01:00:02.530822 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =76
1793 01:00:02.530923
1794 01:00:02.530983
1795 01:00:02.537703 [DQSOSCAuto] RK0, (LSB)MR18= 0x29fd, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1796 01:00:02.541162 CH1 RK0: MR19=605, MR18=29FD
1797 01:00:02.547974 CH1_RK0: MR19=0x605, MR18=0x29FD, DQSOSC=399, MR23=63, INC=92, DEC=61
1798 01:00:02.548101
1799 01:00:02.551002 ----->DramcWriteLeveling(PI) begin...
1800 01:00:02.551109 ==
1801 01:00:02.554442 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 01:00:02.557845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 01:00:02.557949 ==
1804 01:00:02.561160 Write leveling (Byte 0): 27 => 27
1805 01:00:02.564519 Write leveling (Byte 1): 27 => 27
1806 01:00:02.567847 DramcWriteLeveling(PI) end<-----
1807 01:00:02.567924
1808 01:00:02.567983 ==
1809 01:00:02.571225 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 01:00:02.574558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 01:00:02.574637 ==
1812 01:00:02.577853 [Gating] SW mode calibration
1813 01:00:02.584367 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1814 01:00:02.591574 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1815 01:00:02.594750 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1816 01:00:02.598121 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1817 01:00:02.604964 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 01:00:02.608367 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 01:00:02.611859 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 01:00:02.617970 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 01:00:02.621581 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 01:00:02.624848 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 01:00:02.628226 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 01:00:02.634788 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 01:00:02.638759 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 01:00:02.641698 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 01:00:02.647839 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 01:00:02.651411 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1829 01:00:02.655070 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 01:00:02.661573 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 01:00:02.664732 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1832 01:00:02.668164 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1833 01:00:02.674767 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 01:00:02.678110 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 01:00:02.681462 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 01:00:02.688104 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 01:00:02.691538 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 01:00:02.694954 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 01:00:02.701643 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 01:00:02.704538 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1841 01:00:02.707949 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1842 01:00:02.714710 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 01:00:02.718024 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 01:00:02.721529 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 01:00:02.727690 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 01:00:02.731489 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 01:00:02.734831 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 01:00:02.737963 0 10 4 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 1)
1849 01:00:02.744519 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1850 01:00:02.747956 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 01:00:02.751311 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 01:00:02.757853 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 01:00:02.761330 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 01:00:02.764453 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 01:00:02.771076 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1856 01:00:02.774447 0 11 4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (0 0)
1857 01:00:02.777762 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1858 01:00:02.784540 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 01:00:02.788064 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 01:00:02.791402 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 01:00:02.797887 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 01:00:02.801223 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 01:00:02.804627 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 01:00:02.810961 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1865 01:00:02.814603 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 01:00:02.817733 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 01:00:02.821141 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 01:00:02.827956 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 01:00:02.831353 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 01:00:02.834866 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 01:00:02.841095 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 01:00:02.844921 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 01:00:02.848096 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 01:00:02.854643 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 01:00:02.858049 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 01:00:02.861292 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 01:00:02.868249 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 01:00:02.871418 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 01:00:02.874463 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 01:00:02.881432 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1881 01:00:02.884858 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 01:00:02.888145 Total UI for P1: 0, mck2ui 16
1883 01:00:02.891744 best dqsien dly found for B0: ( 0, 14, 4)
1884 01:00:02.894987 Total UI for P1: 0, mck2ui 16
1885 01:00:02.898300 best dqsien dly found for B1: ( 0, 14, 4)
1886 01:00:02.901432 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1887 01:00:02.904921 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1888 01:00:02.904999
1889 01:00:02.907776 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1890 01:00:02.911265 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1891 01:00:02.915124 [Gating] SW calibration Done
1892 01:00:02.915201 ==
1893 01:00:02.917867 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 01:00:02.921500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 01:00:02.921578 ==
1896 01:00:02.925503 RX Vref Scan: 0
1897 01:00:02.925580
1898 01:00:02.925639 RX Vref 0 -> 0, step: 1
1899 01:00:02.928013
1900 01:00:02.928089 RX Delay -130 -> 252, step: 16
1901 01:00:02.934857 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1902 01:00:02.938340 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1903 01:00:02.941370 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1904 01:00:02.944851 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1905 01:00:02.948091 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1906 01:00:02.954633 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1907 01:00:02.958036 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1908 01:00:02.961430 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1909 01:00:02.965040 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1910 01:00:02.968237 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1911 01:00:02.971269 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1912 01:00:02.978703 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1913 01:00:02.981849 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1914 01:00:02.984907 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1915 01:00:02.988054 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1916 01:00:02.994822 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1917 01:00:02.994910 ==
1918 01:00:02.998585 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 01:00:03.001633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 01:00:03.001711 ==
1921 01:00:03.001770 DQS Delay:
1922 01:00:03.004953 DQS0 = 0, DQS1 = 0
1923 01:00:03.005029 DQM Delay:
1924 01:00:03.008193 DQM0 = 83, DQM1 = 76
1925 01:00:03.008269 DQ Delay:
1926 01:00:03.012050 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1927 01:00:03.014754 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1928 01:00:03.018124 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1929 01:00:03.021485 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1930 01:00:03.021561
1931 01:00:03.021620
1932 01:00:03.021675 ==
1933 01:00:03.024713 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 01:00:03.028083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 01:00:03.028165 ==
1936 01:00:03.028224
1937 01:00:03.028277
1938 01:00:03.031857 TX Vref Scan disable
1939 01:00:03.034973 == TX Byte 0 ==
1940 01:00:03.038710 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1941 01:00:03.041945 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1942 01:00:03.045430 == TX Byte 1 ==
1943 01:00:03.048644 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1944 01:00:03.052008 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1945 01:00:03.052084 ==
1946 01:00:03.055414 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 01:00:03.058626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 01:00:03.058703 ==
1949 01:00:03.072986 TX Vref=22, minBit 1, minWin=27, winSum=441
1950 01:00:03.076105 TX Vref=24, minBit 1, minWin=27, winSum=442
1951 01:00:03.079724 TX Vref=26, minBit 9, minWin=27, winSum=447
1952 01:00:03.082653 TX Vref=28, minBit 11, minWin=27, winSum=447
1953 01:00:03.086378 TX Vref=30, minBit 0, minWin=28, winSum=451
1954 01:00:03.093432 TX Vref=32, minBit 0, minWin=28, winSum=452
1955 01:00:03.095940 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 32
1956 01:00:03.096019
1957 01:00:03.099174 Final TX Range 1 Vref 32
1958 01:00:03.099251
1959 01:00:03.099310 ==
1960 01:00:03.102726 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 01:00:03.105964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 01:00:03.106081 ==
1963 01:00:03.106141
1964 01:00:03.109272
1965 01:00:03.109347 TX Vref Scan disable
1966 01:00:03.112832 == TX Byte 0 ==
1967 01:00:03.116073 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1968 01:00:03.122809 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1969 01:00:03.122917 == TX Byte 1 ==
1970 01:00:03.126192 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1971 01:00:03.132716 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1972 01:00:03.132796
1973 01:00:03.132855 [DATLAT]
1974 01:00:03.132910 Freq=800, CH1 RK1
1975 01:00:03.132964
1976 01:00:03.136032 DATLAT Default: 0xa
1977 01:00:03.136107 0, 0xFFFF, sum = 0
1978 01:00:03.139400 1, 0xFFFF, sum = 0
1979 01:00:03.139478 2, 0xFFFF, sum = 0
1980 01:00:03.142861 3, 0xFFFF, sum = 0
1981 01:00:03.142939 4, 0xFFFF, sum = 0
1982 01:00:03.145893 5, 0xFFFF, sum = 0
1983 01:00:03.149174 6, 0xFFFF, sum = 0
1984 01:00:03.149251 7, 0xFFFF, sum = 0
1985 01:00:03.153308 8, 0xFFFF, sum = 0
1986 01:00:03.153386 9, 0x0, sum = 1
1987 01:00:03.153446 10, 0x0, sum = 2
1988 01:00:03.156134 11, 0x0, sum = 3
1989 01:00:03.156211 12, 0x0, sum = 4
1990 01:00:03.159376 best_step = 10
1991 01:00:03.159451
1992 01:00:03.159509 ==
1993 01:00:03.162475 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 01:00:03.165860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 01:00:03.165936 ==
1996 01:00:03.169224 RX Vref Scan: 0
1997 01:00:03.169299
1998 01:00:03.169358 RX Vref 0 -> 0, step: 1
1999 01:00:03.169412
2000 01:00:03.172589 RX Delay -111 -> 252, step: 8
2001 01:00:03.179551 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2002 01:00:03.182914 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2003 01:00:03.186379 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2004 01:00:03.189860 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2005 01:00:03.192874 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2006 01:00:03.199625 iDelay=209, Bit 5, Center 92 (-15 ~ 200) 216
2007 01:00:03.202955 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2008 01:00:03.206179 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2009 01:00:03.209616 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2010 01:00:03.213020 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
2011 01:00:03.219577 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2012 01:00:03.222796 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2013 01:00:03.226173 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2014 01:00:03.229707 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2015 01:00:03.232738 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2016 01:00:03.239530 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2017 01:00:03.239607 ==
2018 01:00:03.242959 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 01:00:03.246096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 01:00:03.246173 ==
2021 01:00:03.246232 DQS Delay:
2022 01:00:03.249474 DQS0 = 0, DQS1 = 0
2023 01:00:03.249549 DQM Delay:
2024 01:00:03.252633 DQM0 = 80, DQM1 = 75
2025 01:00:03.252709 DQ Delay:
2026 01:00:03.256374 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2027 01:00:03.259581 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76
2028 01:00:03.263102 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68
2029 01:00:03.266247 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2030 01:00:03.266323
2031 01:00:03.266382
2032 01:00:03.272848 [DQSOSCAuto] RK1, (LSB)MR18= 0x242f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2033 01:00:03.276113 CH1 RK1: MR19=606, MR18=242F
2034 01:00:03.283170 CH1_RK1: MR19=0x606, MR18=0x242F, DQSOSC=397, MR23=63, INC=93, DEC=62
2035 01:00:03.286121 [RxdqsGatingPostProcess] freq 800
2036 01:00:03.293199 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2037 01:00:03.296497 Pre-setting of DQS Precalculation
2038 01:00:03.299637 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2039 01:00:03.306720 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2040 01:00:03.313246 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2041 01:00:03.313326
2042 01:00:03.313403
2043 01:00:03.316270 [Calibration Summary] 1600 Mbps
2044 01:00:03.319888 CH 0, Rank 0
2045 01:00:03.319969 SW Impedance : PASS
2046 01:00:03.322817 DUTY Scan : NO K
2047 01:00:03.326524 ZQ Calibration : PASS
2048 01:00:03.326614 Jitter Meter : NO K
2049 01:00:03.329945 CBT Training : PASS
2050 01:00:03.333336 Write leveling : PASS
2051 01:00:03.333414 RX DQS gating : PASS
2052 01:00:03.336472 RX DQ/DQS(RDDQC) : PASS
2053 01:00:03.336550 TX DQ/DQS : PASS
2054 01:00:03.339892 RX DATLAT : PASS
2055 01:00:03.343017 RX DQ/DQS(Engine): PASS
2056 01:00:03.343096 TX OE : NO K
2057 01:00:03.346283 All Pass.
2058 01:00:03.346383
2059 01:00:03.346460 CH 0, Rank 1
2060 01:00:03.349557 SW Impedance : PASS
2061 01:00:03.349634 DUTY Scan : NO K
2062 01:00:03.353405 ZQ Calibration : PASS
2063 01:00:03.356241 Jitter Meter : NO K
2064 01:00:03.356320 CBT Training : PASS
2065 01:00:03.360082 Write leveling : PASS
2066 01:00:03.362851 RX DQS gating : PASS
2067 01:00:03.362929 RX DQ/DQS(RDDQC) : PASS
2068 01:00:03.366206 TX DQ/DQS : PASS
2069 01:00:03.369650 RX DATLAT : PASS
2070 01:00:03.369729 RX DQ/DQS(Engine): PASS
2071 01:00:03.373162 TX OE : NO K
2072 01:00:03.373240 All Pass.
2073 01:00:03.373316
2074 01:00:03.376161 CH 1, Rank 0
2075 01:00:03.376240 SW Impedance : PASS
2076 01:00:03.379477 DUTY Scan : NO K
2077 01:00:03.379555 ZQ Calibration : PASS
2078 01:00:03.382879 Jitter Meter : NO K
2079 01:00:03.386519 CBT Training : PASS
2080 01:00:03.386598 Write leveling : PASS
2081 01:00:03.389764 RX DQS gating : PASS
2082 01:00:03.393386 RX DQ/DQS(RDDQC) : PASS
2083 01:00:03.393464 TX DQ/DQS : PASS
2084 01:00:03.396504 RX DATLAT : PASS
2085 01:00:03.399652 RX DQ/DQS(Engine): PASS
2086 01:00:03.399729 TX OE : NO K
2087 01:00:03.402977 All Pass.
2088 01:00:03.403054
2089 01:00:03.403131 CH 1, Rank 1
2090 01:00:03.406273 SW Impedance : PASS
2091 01:00:03.406373 DUTY Scan : NO K
2092 01:00:03.409687 ZQ Calibration : PASS
2093 01:00:03.412968 Jitter Meter : NO K
2094 01:00:03.413046 CBT Training : PASS
2095 01:00:03.416321 Write leveling : PASS
2096 01:00:03.419486 RX DQS gating : PASS
2097 01:00:03.419564 RX DQ/DQS(RDDQC) : PASS
2098 01:00:03.423472 TX DQ/DQS : PASS
2099 01:00:03.423550 RX DATLAT : PASS
2100 01:00:03.426361 RX DQ/DQS(Engine): PASS
2101 01:00:03.429987 TX OE : NO K
2102 01:00:03.430097 All Pass.
2103 01:00:03.430172
2104 01:00:03.432731 DramC Write-DBI off
2105 01:00:03.432808 PER_BANK_REFRESH: Hybrid Mode
2106 01:00:03.436164 TX_TRACKING: ON
2107 01:00:03.439519 [GetDramInforAfterCalByMRR] Vendor 6.
2108 01:00:03.443139 [GetDramInforAfterCalByMRR] Revision 606.
2109 01:00:03.446218 [GetDramInforAfterCalByMRR] Revision 2 0.
2110 01:00:03.446296 MR0 0x3b3b
2111 01:00:03.449517 MR8 0x5151
2112 01:00:03.452973 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 01:00:03.453053
2114 01:00:03.453129 MR0 0x3b3b
2115 01:00:03.456317 MR8 0x5151
2116 01:00:03.460012 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 01:00:03.460090
2118 01:00:03.466176 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2119 01:00:03.469911 [FAST_K] Save calibration result to emmc
2120 01:00:03.476615 [FAST_K] Save calibration result to emmc
2121 01:00:03.476699 dram_init: config_dvfs: 1
2122 01:00:03.479714 dramc_set_vcore_voltage set vcore to 662500
2123 01:00:03.483326 Read voltage for 1200, 2
2124 01:00:03.483404 Vio18 = 0
2125 01:00:03.486139 Vcore = 662500
2126 01:00:03.486215 Vdram = 0
2127 01:00:03.486274 Vddq = 0
2128 01:00:03.489881 Vmddr = 0
2129 01:00:03.493115 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2130 01:00:03.499846 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2131 01:00:03.499927 MEM_TYPE=3, freq_sel=15
2132 01:00:03.502922 sv_algorithm_assistance_LP4_1600
2133 01:00:03.509606 ============ PULL DRAM RESETB DOWN ============
2134 01:00:03.513032 ========== PULL DRAM RESETB DOWN end =========
2135 01:00:03.516440 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2136 01:00:03.519692 ===================================
2137 01:00:03.523074 LPDDR4 DRAM CONFIGURATION
2138 01:00:03.526560 ===================================
2139 01:00:03.526638 EX_ROW_EN[0] = 0x0
2140 01:00:03.529879 EX_ROW_EN[1] = 0x0
2141 01:00:03.533471 LP4Y_EN = 0x0
2142 01:00:03.533550 WORK_FSP = 0x0
2143 01:00:03.536244 WL = 0x4
2144 01:00:03.536321 RL = 0x4
2145 01:00:03.539955 BL = 0x2
2146 01:00:03.540032 RPST = 0x0
2147 01:00:03.542717 RD_PRE = 0x0
2148 01:00:03.542794 WR_PRE = 0x1
2149 01:00:03.546305 WR_PST = 0x0
2150 01:00:03.546382 DBI_WR = 0x0
2151 01:00:03.549674 DBI_RD = 0x0
2152 01:00:03.549751 OTF = 0x1
2153 01:00:03.552849 ===================================
2154 01:00:03.556196 ===================================
2155 01:00:03.560031 ANA top config
2156 01:00:03.562846 ===================================
2157 01:00:03.562923 DLL_ASYNC_EN = 0
2158 01:00:03.566260 ALL_SLAVE_EN = 0
2159 01:00:03.569693 NEW_RANK_MODE = 1
2160 01:00:03.572856 DLL_IDLE_MODE = 1
2161 01:00:03.572934 LP45_APHY_COMB_EN = 1
2162 01:00:03.576751 TX_ODT_DIS = 1
2163 01:00:03.579864 NEW_8X_MODE = 1
2164 01:00:03.582994 ===================================
2165 01:00:03.586512 ===================================
2166 01:00:03.589876 data_rate = 2400
2167 01:00:03.593177 CKR = 1
2168 01:00:03.593268 DQ_P2S_RATIO = 8
2169 01:00:03.596403 ===================================
2170 01:00:03.599918 CA_P2S_RATIO = 8
2171 01:00:03.603073 DQ_CA_OPEN = 0
2172 01:00:03.606717 DQ_SEMI_OPEN = 0
2173 01:00:03.610306 CA_SEMI_OPEN = 0
2174 01:00:03.613351 CA_FULL_RATE = 0
2175 01:00:03.613430 DQ_CKDIV4_EN = 0
2176 01:00:03.616597 CA_CKDIV4_EN = 0
2177 01:00:03.619807 CA_PREDIV_EN = 0
2178 01:00:03.623143 PH8_DLY = 17
2179 01:00:03.626739 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2180 01:00:03.629844 DQ_AAMCK_DIV = 4
2181 01:00:03.629921 CA_AAMCK_DIV = 4
2182 01:00:03.633268 CA_ADMCK_DIV = 4
2183 01:00:03.636496 DQ_TRACK_CA_EN = 0
2184 01:00:03.639873 CA_PICK = 1200
2185 01:00:03.643151 CA_MCKIO = 1200
2186 01:00:03.646293 MCKIO_SEMI = 0
2187 01:00:03.650077 PLL_FREQ = 2366
2188 01:00:03.650154 DQ_UI_PI_RATIO = 32
2189 01:00:03.653368 CA_UI_PI_RATIO = 0
2190 01:00:03.656543 ===================================
2191 01:00:03.660044 ===================================
2192 01:00:03.662942 memory_type:LPDDR4
2193 01:00:03.666310 GP_NUM : 10
2194 01:00:03.666388 SRAM_EN : 1
2195 01:00:03.670139 MD32_EN : 0
2196 01:00:03.673291 ===================================
2197 01:00:03.673369 [ANA_INIT] >>>>>>>>>>>>>>
2198 01:00:03.676942 <<<<<< [CONFIGURE PHASE]: ANA_TX
2199 01:00:03.679602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2200 01:00:03.683397 ===================================
2201 01:00:03.686493 data_rate = 2400,PCW = 0X5b00
2202 01:00:03.689830 ===================================
2203 01:00:03.693209 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2204 01:00:03.699748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 01:00:03.706604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 01:00:03.709666 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2207 01:00:03.713075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2208 01:00:03.716544 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2209 01:00:03.720026 [ANA_INIT] flow start
2210 01:00:03.720104 [ANA_INIT] PLL >>>>>>>>
2211 01:00:03.723295 [ANA_INIT] PLL <<<<<<<<
2212 01:00:03.726675 [ANA_INIT] MIDPI >>>>>>>>
2213 01:00:03.726754 [ANA_INIT] MIDPI <<<<<<<<
2214 01:00:03.729783 [ANA_INIT] DLL >>>>>>>>
2215 01:00:03.733233 [ANA_INIT] DLL <<<<<<<<
2216 01:00:03.733311 [ANA_INIT] flow end
2217 01:00:03.736427 ============ LP4 DIFF to SE enter ============
2218 01:00:03.743577 ============ LP4 DIFF to SE exit ============
2219 01:00:03.743658 [ANA_INIT] <<<<<<<<<<<<<
2220 01:00:03.746599 [Flow] Enable top DCM control >>>>>
2221 01:00:03.750088 [Flow] Enable top DCM control <<<<<
2222 01:00:03.753049 Enable DLL master slave shuffle
2223 01:00:03.760195 ==============================================================
2224 01:00:03.760282 Gating Mode config
2225 01:00:03.766557 ==============================================================
2226 01:00:03.769554 Config description:
2227 01:00:03.779737 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2228 01:00:03.786273 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2229 01:00:03.789798 SELPH_MODE 0: By rank 1: By Phase
2230 01:00:03.796899 ==============================================================
2231 01:00:03.799427 GAT_TRACK_EN = 1
2232 01:00:03.802898 RX_GATING_MODE = 2
2233 01:00:03.806138 RX_GATING_TRACK_MODE = 2
2234 01:00:03.806217 SELPH_MODE = 1
2235 01:00:03.809611 PICG_EARLY_EN = 1
2236 01:00:03.813057 VALID_LAT_VALUE = 1
2237 01:00:03.819462 ==============================================================
2238 01:00:03.822784 Enter into Gating configuration >>>>
2239 01:00:03.826149 Exit from Gating configuration <<<<
2240 01:00:03.829673 Enter into DVFS_PRE_config >>>>>
2241 01:00:03.839206 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2242 01:00:03.843026 Exit from DVFS_PRE_config <<<<<
2243 01:00:03.846367 Enter into PICG configuration >>>>
2244 01:00:03.849119 Exit from PICG configuration <<<<
2245 01:00:03.852904 [RX_INPUT] configuration >>>>>
2246 01:00:03.856277 [RX_INPUT] configuration <<<<<
2247 01:00:03.859190 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2248 01:00:03.865911 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2249 01:00:03.872757 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 01:00:03.879328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 01:00:03.882996 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 01:00:03.889416 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 01:00:03.892493 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2254 01:00:03.899117 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2255 01:00:03.902164 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2256 01:00:03.905529 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2257 01:00:03.908907 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2258 01:00:03.915501 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 01:00:03.919204 ===================================
2260 01:00:03.922486 LPDDR4 DRAM CONFIGURATION
2261 01:00:03.922566 ===================================
2262 01:00:03.925769 EX_ROW_EN[0] = 0x0
2263 01:00:03.928949 EX_ROW_EN[1] = 0x0
2264 01:00:03.929026 LP4Y_EN = 0x0
2265 01:00:03.932173 WORK_FSP = 0x0
2266 01:00:03.932249 WL = 0x4
2267 01:00:03.936041 RL = 0x4
2268 01:00:03.936118 BL = 0x2
2269 01:00:03.939193 RPST = 0x0
2270 01:00:03.939270 RD_PRE = 0x0
2271 01:00:03.942471 WR_PRE = 0x1
2272 01:00:03.942548 WR_PST = 0x0
2273 01:00:03.946022 DBI_WR = 0x0
2274 01:00:03.946113 DBI_RD = 0x0
2275 01:00:03.949160 OTF = 0x1
2276 01:00:03.952729 ===================================
2277 01:00:03.955462 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2278 01:00:03.959299 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2279 01:00:03.966447 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2280 01:00:03.969073 ===================================
2281 01:00:03.969152 LPDDR4 DRAM CONFIGURATION
2282 01:00:03.972273 ===================================
2283 01:00:03.975729 EX_ROW_EN[0] = 0x10
2284 01:00:03.979154 EX_ROW_EN[1] = 0x0
2285 01:00:03.979230 LP4Y_EN = 0x0
2286 01:00:03.982572 WORK_FSP = 0x0
2287 01:00:03.982649 WL = 0x4
2288 01:00:03.985827 RL = 0x4
2289 01:00:03.985904 BL = 0x2
2290 01:00:03.989182 RPST = 0x0
2291 01:00:03.989259 RD_PRE = 0x0
2292 01:00:03.992448 WR_PRE = 0x1
2293 01:00:03.992525 WR_PST = 0x0
2294 01:00:03.995687 DBI_WR = 0x0
2295 01:00:03.995770 DBI_RD = 0x0
2296 01:00:03.998933 OTF = 0x1
2297 01:00:04.002539 ===================================
2298 01:00:04.009012 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2299 01:00:04.009093 ==
2300 01:00:04.012768 Dram Type= 6, Freq= 0, CH_0, rank 0
2301 01:00:04.015938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2302 01:00:04.016017 ==
2303 01:00:04.019249 [Duty_Offset_Calibration]
2304 01:00:04.019327 B0:2 B1:-1 CA:1
2305 01:00:04.019386
2306 01:00:04.022650 [DutyScan_Calibration_Flow] k_type=0
2307 01:00:04.031174
2308 01:00:04.031253 ==CLK 0==
2309 01:00:04.034593 Final CLK duty delay cell = -4
2310 01:00:04.037874 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2311 01:00:04.041325 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2312 01:00:04.044721 [-4] AVG Duty = 4937%(X100)
2313 01:00:04.044798
2314 01:00:04.048141 CH0 CLK Duty spec in!! Max-Min= 125%
2315 01:00:04.051509 [DutyScan_Calibration_Flow] ====Done====
2316 01:00:04.051585
2317 01:00:04.054585 [DutyScan_Calibration_Flow] k_type=1
2318 01:00:04.070746
2319 01:00:04.070853 ==DQS 0 ==
2320 01:00:04.073651 Final DQS duty delay cell = 0
2321 01:00:04.076893 [0] MAX Duty = 5125%(X100), DQS PI = 48
2322 01:00:04.080212 [0] MIN Duty = 5000%(X100), DQS PI = 12
2323 01:00:04.083529 [0] AVG Duty = 5062%(X100)
2324 01:00:04.083605
2325 01:00:04.083664 ==DQS 1 ==
2326 01:00:04.086887 Final DQS duty delay cell = -4
2327 01:00:04.090753 [-4] MAX Duty = 5124%(X100), DQS PI = 18
2328 01:00:04.093440 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2329 01:00:04.097139 [-4] AVG Duty = 5062%(X100)
2330 01:00:04.097215
2331 01:00:04.100458 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2332 01:00:04.100534
2333 01:00:04.103834 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2334 01:00:04.106640 [DutyScan_Calibration_Flow] ====Done====
2335 01:00:04.106716
2336 01:00:04.109951 [DutyScan_Calibration_Flow] k_type=3
2337 01:00:04.127467
2338 01:00:04.127577 ==DQM 0 ==
2339 01:00:04.130734 Final DQM duty delay cell = 0
2340 01:00:04.134114 [0] MAX Duty = 5000%(X100), DQS PI = 54
2341 01:00:04.137099 [0] MIN Duty = 4907%(X100), DQS PI = 2
2342 01:00:04.137175 [0] AVG Duty = 4953%(X100)
2343 01:00:04.140626
2344 01:00:04.140703 ==DQM 1 ==
2345 01:00:04.144287 Final DQM duty delay cell = 0
2346 01:00:04.147383 [0] MAX Duty = 5156%(X100), DQS PI = 62
2347 01:00:04.150934 [0] MIN Duty = 4969%(X100), DQS PI = 10
2348 01:00:04.151010 [0] AVG Duty = 5062%(X100)
2349 01:00:04.154097
2350 01:00:04.157580 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2351 01:00:04.157656
2352 01:00:04.160859 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2353 01:00:04.164133 [DutyScan_Calibration_Flow] ====Done====
2354 01:00:04.164209
2355 01:00:04.167242 [DutyScan_Calibration_Flow] k_type=2
2356 01:00:04.183481
2357 01:00:04.183582 ==DQ 0 ==
2358 01:00:04.186349 Final DQ duty delay cell = -4
2359 01:00:04.189568 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2360 01:00:04.193108 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2361 01:00:04.196036 [-4] AVG Duty = 4953%(X100)
2362 01:00:04.196114
2363 01:00:04.196187 ==DQ 1 ==
2364 01:00:04.199951 Final DQ duty delay cell = 0
2365 01:00:04.202986 [0] MAX Duty = 5031%(X100), DQS PI = 18
2366 01:00:04.206342 [0] MIN Duty = 4907%(X100), DQS PI = 12
2367 01:00:04.206419 [0] AVG Duty = 4969%(X100)
2368 01:00:04.209840
2369 01:00:04.213108 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2370 01:00:04.213184
2371 01:00:04.216417 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2372 01:00:04.219766 [DutyScan_Calibration_Flow] ====Done====
2373 01:00:04.219842 ==
2374 01:00:04.222909 Dram Type= 6, Freq= 0, CH_1, rank 0
2375 01:00:04.226438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 01:00:04.226515 ==
2377 01:00:04.229724 [Duty_Offset_Calibration]
2378 01:00:04.229801 B0:1 B1:1 CA:2
2379 01:00:04.229865
2380 01:00:04.232927 [DutyScan_Calibration_Flow] k_type=0
2381 01:00:04.243277
2382 01:00:04.243357 ==CLK 0==
2383 01:00:04.246557 Final CLK duty delay cell = 0
2384 01:00:04.250176 [0] MAX Duty = 5156%(X100), DQS PI = 24
2385 01:00:04.253259 [0] MIN Duty = 4938%(X100), DQS PI = 40
2386 01:00:04.253337 [0] AVG Duty = 5047%(X100)
2387 01:00:04.256932
2388 01:00:04.259959 CH1 CLK Duty spec in!! Max-Min= 218%
2389 01:00:04.263090 [DutyScan_Calibration_Flow] ====Done====
2390 01:00:04.263168
2391 01:00:04.266420 [DutyScan_Calibration_Flow] k_type=1
2392 01:00:04.282791
2393 01:00:04.282892 ==DQS 0 ==
2394 01:00:04.285917 Final DQS duty delay cell = 0
2395 01:00:04.289495 [0] MAX Duty = 5031%(X100), DQS PI = 18
2396 01:00:04.293001 [0] MIN Duty = 4844%(X100), DQS PI = 48
2397 01:00:04.296105 [0] AVG Duty = 4937%(X100)
2398 01:00:04.296183
2399 01:00:04.296242 ==DQS 1 ==
2400 01:00:04.299158 Final DQS duty delay cell = 0
2401 01:00:04.302792 [0] MAX Duty = 5062%(X100), DQS PI = 36
2402 01:00:04.306237 [0] MIN Duty = 4907%(X100), DQS PI = 32
2403 01:00:04.309183 [0] AVG Duty = 4984%(X100)
2404 01:00:04.309259
2405 01:00:04.312645 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2406 01:00:04.312722
2407 01:00:04.315858 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2408 01:00:04.319250 [DutyScan_Calibration_Flow] ====Done====
2409 01:00:04.319327
2410 01:00:04.322351 [DutyScan_Calibration_Flow] k_type=3
2411 01:00:04.339243
2412 01:00:04.339333 ==DQM 0 ==
2413 01:00:04.342750 Final DQM duty delay cell = 0
2414 01:00:04.345627 [0] MAX Duty = 5093%(X100), DQS PI = 18
2415 01:00:04.349540 [0] MIN Duty = 4875%(X100), DQS PI = 50
2416 01:00:04.352696 [0] AVG Duty = 4984%(X100)
2417 01:00:04.352774
2418 01:00:04.352833 ==DQM 1 ==
2419 01:00:04.355937 Final DQM duty delay cell = 0
2420 01:00:04.359413 [0] MAX Duty = 5125%(X100), DQS PI = 0
2421 01:00:04.362427 [0] MIN Duty = 4938%(X100), DQS PI = 24
2422 01:00:04.365775 [0] AVG Duty = 5031%(X100)
2423 01:00:04.365853
2424 01:00:04.369082 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2425 01:00:04.369159
2426 01:00:04.372340 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2427 01:00:04.375685 [DutyScan_Calibration_Flow] ====Done====
2428 01:00:04.375763
2429 01:00:04.379245 [DutyScan_Calibration_Flow] k_type=2
2430 01:00:04.396064
2431 01:00:04.396165 ==DQ 0 ==
2432 01:00:04.399294 Final DQ duty delay cell = 0
2433 01:00:04.402256 [0] MAX Duty = 5124%(X100), DQS PI = 18
2434 01:00:04.405549 [0] MIN Duty = 4938%(X100), DQS PI = 50
2435 01:00:04.405626 [0] AVG Duty = 5031%(X100)
2436 01:00:04.409011
2437 01:00:04.409088 ==DQ 1 ==
2438 01:00:04.412545 Final DQ duty delay cell = 0
2439 01:00:04.415534 [0] MAX Duty = 5093%(X100), DQS PI = 8
2440 01:00:04.418705 [0] MIN Duty = 5000%(X100), DQS PI = 50
2441 01:00:04.418784 [0] AVG Duty = 5046%(X100)
2442 01:00:04.418844
2443 01:00:04.422500 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2444 01:00:04.426274
2445 01:00:04.426352 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2446 01:00:04.432095 [DutyScan_Calibration_Flow] ====Done====
2447 01:00:04.435589 nWR fixed to 30
2448 01:00:04.435668 [ModeRegInit_LP4] CH0 RK0
2449 01:00:04.438900 [ModeRegInit_LP4] CH0 RK1
2450 01:00:04.442302 [ModeRegInit_LP4] CH1 RK0
2451 01:00:04.442379 [ModeRegInit_LP4] CH1 RK1
2452 01:00:04.445409 match AC timing 7
2453 01:00:04.449205 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2454 01:00:04.452264 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2455 01:00:04.459351 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2456 01:00:04.462576 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2457 01:00:04.468850 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2458 01:00:04.468938 ==
2459 01:00:04.472613 Dram Type= 6, Freq= 0, CH_0, rank 0
2460 01:00:04.475838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 01:00:04.475918 ==
2462 01:00:04.482721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2463 01:00:04.485524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2464 01:00:04.495615 [CA 0] Center 40 (10~71) winsize 62
2465 01:00:04.498852 [CA 1] Center 39 (9~70) winsize 62
2466 01:00:04.502461 [CA 2] Center 36 (6~67) winsize 62
2467 01:00:04.505563 [CA 3] Center 36 (5~67) winsize 63
2468 01:00:04.508966 [CA 4] Center 35 (5~65) winsize 61
2469 01:00:04.512216 [CA 5] Center 34 (4~65) winsize 62
2470 01:00:04.512295
2471 01:00:04.515577 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2472 01:00:04.515657
2473 01:00:04.518940 [CATrainingPosCal] consider 1 rank data
2474 01:00:04.522416 u2DelayCellTimex100 = 270/100 ps
2475 01:00:04.525608 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2476 01:00:04.532301 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2477 01:00:04.535657 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2478 01:00:04.539085 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2479 01:00:04.542307 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2480 01:00:04.545747 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2481 01:00:04.545827
2482 01:00:04.549121 CA PerBit enable=1, Macro0, CA PI delay=34
2483 01:00:04.549201
2484 01:00:04.552552 [CBTSetCACLKResult] CA Dly = 34
2485 01:00:04.552630 CS Dly: 7 (0~38)
2486 01:00:04.555898 ==
2487 01:00:04.555978 Dram Type= 6, Freq= 0, CH_0, rank 1
2488 01:00:04.562531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 01:00:04.562621 ==
2490 01:00:04.565582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 01:00:04.572066 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2492 01:00:04.581776 [CA 0] Center 39 (9~70) winsize 62
2493 01:00:04.585089 [CA 1] Center 40 (10~70) winsize 61
2494 01:00:04.588371 [CA 2] Center 36 (6~67) winsize 62
2495 01:00:04.591629 [CA 3] Center 35 (5~66) winsize 62
2496 01:00:04.594620 [CA 4] Center 34 (4~65) winsize 62
2497 01:00:04.598070 [CA 5] Center 34 (4~64) winsize 61
2498 01:00:04.598166
2499 01:00:04.601775 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2500 01:00:04.601855
2501 01:00:04.604616 [CATrainingPosCal] consider 2 rank data
2502 01:00:04.608408 u2DelayCellTimex100 = 270/100 ps
2503 01:00:04.611455 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2504 01:00:04.618314 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2505 01:00:04.621612 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2506 01:00:04.624794 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2507 01:00:04.628083 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2508 01:00:04.631496 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2509 01:00:04.631577
2510 01:00:04.634735 CA PerBit enable=1, Macro0, CA PI delay=34
2511 01:00:04.634814
2512 01:00:04.638601 [CBTSetCACLKResult] CA Dly = 34
2513 01:00:04.638680 CS Dly: 8 (0~41)
2514 01:00:04.638740
2515 01:00:04.641573 ----->DramcWriteLeveling(PI) begin...
2516 01:00:04.645219 ==
2517 01:00:04.648161 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 01:00:04.651715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 01:00:04.651793 ==
2520 01:00:04.655136 Write leveling (Byte 0): 32 => 32
2521 01:00:04.658170 Write leveling (Byte 1): 29 => 29
2522 01:00:04.662019 DramcWriteLeveling(PI) end<-----
2523 01:00:04.662098
2524 01:00:04.662158 ==
2525 01:00:04.665044 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 01:00:04.668388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 01:00:04.668466 ==
2528 01:00:04.671936 [Gating] SW mode calibration
2529 01:00:04.678926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2530 01:00:04.681580 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2531 01:00:04.688258 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 01:00:04.692334 0 15 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
2533 01:00:04.695264 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 01:00:04.701877 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 01:00:04.705049 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 01:00:04.708563 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 01:00:04.715183 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 01:00:04.718237 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 01:00:04.722015 1 0 0 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
2540 01:00:04.728558 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2541 01:00:04.731764 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 01:00:04.735356 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 01:00:04.742220 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 01:00:04.744907 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 01:00:04.748342 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 01:00:04.755265 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 01:00:04.758107 1 1 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2548 01:00:04.761649 1 1 4 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
2549 01:00:04.768283 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 01:00:04.771499 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 01:00:04.774781 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 01:00:04.778304 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 01:00:04.785214 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 01:00:04.788482 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 01:00:04.791759 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2556 01:00:04.798334 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2557 01:00:04.801798 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 01:00:04.805058 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 01:00:04.811345 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 01:00:04.815039 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 01:00:04.818311 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 01:00:04.824999 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 01:00:04.828105 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 01:00:04.831636 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 01:00:04.838188 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 01:00:04.841376 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 01:00:04.845154 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 01:00:04.851990 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 01:00:04.855287 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 01:00:04.858099 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 01:00:04.865205 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2572 01:00:04.868487 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2573 01:00:04.871889 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 01:00:04.874724 Total UI for P1: 0, mck2ui 16
2575 01:00:04.877955 best dqsien dly found for B0: ( 1, 4, 2)
2576 01:00:04.881451 Total UI for P1: 0, mck2ui 16
2577 01:00:04.885048 best dqsien dly found for B1: ( 1, 4, 4)
2578 01:00:04.888159 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2579 01:00:04.891792 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2580 01:00:04.891869
2581 01:00:04.895253 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2582 01:00:04.898720 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2583 01:00:04.901841 [Gating] SW calibration Done
2584 01:00:04.901921 ==
2585 01:00:04.905524 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 01:00:04.908431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 01:00:04.908509 ==
2588 01:00:04.912238 RX Vref Scan: 0
2589 01:00:04.912314
2590 01:00:04.915006 RX Vref 0 -> 0, step: 1
2591 01:00:04.915083
2592 01:00:04.915142 RX Delay -40 -> 252, step: 8
2593 01:00:04.922670 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2594 01:00:04.925551 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2595 01:00:04.928532 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2596 01:00:04.931897 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2597 01:00:04.935369 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2598 01:00:04.941698 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2599 01:00:04.945209 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2600 01:00:04.948575 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2601 01:00:04.951772 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2602 01:00:04.955217 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2603 01:00:04.961498 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2604 01:00:04.965278 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2605 01:00:04.968663 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2606 01:00:04.971599 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2607 01:00:04.974954 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2608 01:00:04.981536 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2609 01:00:04.981614 ==
2610 01:00:04.984898 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 01:00:04.988153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 01:00:04.988231 ==
2613 01:00:04.988291 DQS Delay:
2614 01:00:04.992024 DQS0 = 0, DQS1 = 0
2615 01:00:04.992100 DQM Delay:
2616 01:00:04.995326 DQM0 = 115, DQM1 = 106
2617 01:00:04.995402 DQ Delay:
2618 01:00:04.998547 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2619 01:00:05.002378 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2620 01:00:05.005193 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2621 01:00:05.008609 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2622 01:00:05.008686
2623 01:00:05.008744
2624 01:00:05.011583 ==
2625 01:00:05.011659 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 01:00:05.018456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 01:00:05.018534 ==
2628 01:00:05.018594
2629 01:00:05.018648
2630 01:00:05.021880 TX Vref Scan disable
2631 01:00:05.021957 == TX Byte 0 ==
2632 01:00:05.024954 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2633 01:00:05.031678 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2634 01:00:05.031755 == TX Byte 1 ==
2635 01:00:05.035119 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2636 01:00:05.041955 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2637 01:00:05.042039 ==
2638 01:00:05.045409 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 01:00:05.048256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 01:00:05.048334 ==
2641 01:00:05.060176 TX Vref=22, minBit 1, minWin=25, winSum=421
2642 01:00:05.063477 TX Vref=24, minBit 1, minWin=25, winSum=423
2643 01:00:05.067330 TX Vref=26, minBit 0, minWin=26, winSum=431
2644 01:00:05.070117 TX Vref=28, minBit 1, minWin=26, winSum=433
2645 01:00:05.073642 TX Vref=30, minBit 1, minWin=26, winSum=437
2646 01:00:05.076898 TX Vref=32, minBit 0, minWin=26, winSum=435
2647 01:00:05.083930 [TxChooseVref] Worse bit 1, Min win 26, Win sum 437, Final Vref 30
2648 01:00:05.084008
2649 01:00:05.087242 Final TX Range 1 Vref 30
2650 01:00:05.087319
2651 01:00:05.087378 ==
2652 01:00:05.090564 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 01:00:05.093777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 01:00:05.093854 ==
2655 01:00:05.093914
2656 01:00:05.093968
2657 01:00:05.097133 TX Vref Scan disable
2658 01:00:05.100550 == TX Byte 0 ==
2659 01:00:05.104196 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2660 01:00:05.107345 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2661 01:00:05.110311 == TX Byte 1 ==
2662 01:00:05.113930 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2663 01:00:05.117310 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2664 01:00:05.117387
2665 01:00:05.120345 [DATLAT]
2666 01:00:05.120421 Freq=1200, CH0 RK0
2667 01:00:05.120480
2668 01:00:05.123862 DATLAT Default: 0xd
2669 01:00:05.123939 0, 0xFFFF, sum = 0
2670 01:00:05.127134 1, 0xFFFF, sum = 0
2671 01:00:05.127212 2, 0xFFFF, sum = 0
2672 01:00:05.130377 3, 0xFFFF, sum = 0
2673 01:00:05.130455 4, 0xFFFF, sum = 0
2674 01:00:05.133710 5, 0xFFFF, sum = 0
2675 01:00:05.133788 6, 0xFFFF, sum = 0
2676 01:00:05.137362 7, 0xFFFF, sum = 0
2677 01:00:05.137439 8, 0xFFFF, sum = 0
2678 01:00:05.140719 9, 0xFFFF, sum = 0
2679 01:00:05.143896 10, 0xFFFF, sum = 0
2680 01:00:05.143974 11, 0xFFFF, sum = 0
2681 01:00:05.147237 12, 0x0, sum = 1
2682 01:00:05.147315 13, 0x0, sum = 2
2683 01:00:05.147375 14, 0x0, sum = 3
2684 01:00:05.150433 15, 0x0, sum = 4
2685 01:00:05.150535 best_step = 13
2686 01:00:05.150621
2687 01:00:05.150701 ==
2688 01:00:05.153648 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 01:00:05.160434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 01:00:05.160511 ==
2691 01:00:05.160570 RX Vref Scan: 1
2692 01:00:05.160624
2693 01:00:05.163644 Set Vref Range= 32 -> 127
2694 01:00:05.163720
2695 01:00:05.166885 RX Vref 32 -> 127, step: 1
2696 01:00:05.166961
2697 01:00:05.170391 RX Delay -21 -> 252, step: 4
2698 01:00:05.170467
2699 01:00:05.173293 Set Vref, RX VrefLevel [Byte0]: 32
2700 01:00:05.177167 [Byte1]: 32
2701 01:00:05.177243
2702 01:00:05.180162 Set Vref, RX VrefLevel [Byte0]: 33
2703 01:00:05.183939 [Byte1]: 33
2704 01:00:05.184018
2705 01:00:05.187333 Set Vref, RX VrefLevel [Byte0]: 34
2706 01:00:05.189867 [Byte1]: 34
2707 01:00:05.194755
2708 01:00:05.194831 Set Vref, RX VrefLevel [Byte0]: 35
2709 01:00:05.197666 [Byte1]: 35
2710 01:00:05.202585
2711 01:00:05.202660 Set Vref, RX VrefLevel [Byte0]: 36
2712 01:00:05.205918 [Byte1]: 36
2713 01:00:05.210314
2714 01:00:05.210390 Set Vref, RX VrefLevel [Byte0]: 37
2715 01:00:05.213571 [Byte1]: 37
2716 01:00:05.218259
2717 01:00:05.218335 Set Vref, RX VrefLevel [Byte0]: 38
2718 01:00:05.221626 [Byte1]: 38
2719 01:00:05.225986
2720 01:00:05.226065 Set Vref, RX VrefLevel [Byte0]: 39
2721 01:00:05.229799 [Byte1]: 39
2722 01:00:05.234098
2723 01:00:05.234173 Set Vref, RX VrefLevel [Byte0]: 40
2724 01:00:05.237819 [Byte1]: 40
2725 01:00:05.242124
2726 01:00:05.242201 Set Vref, RX VrefLevel [Byte0]: 41
2727 01:00:05.245432 [Byte1]: 41
2728 01:00:05.250074
2729 01:00:05.250150 Set Vref, RX VrefLevel [Byte0]: 42
2730 01:00:05.253381 [Byte1]: 42
2731 01:00:05.258093
2732 01:00:05.258169 Set Vref, RX VrefLevel [Byte0]: 43
2733 01:00:05.261229 [Byte1]: 43
2734 01:00:05.265941
2735 01:00:05.266066 Set Vref, RX VrefLevel [Byte0]: 44
2736 01:00:05.268969 [Byte1]: 44
2737 01:00:05.273877
2738 01:00:05.273987 Set Vref, RX VrefLevel [Byte0]: 45
2739 01:00:05.277176 [Byte1]: 45
2740 01:00:05.281905
2741 01:00:05.282040 Set Vref, RX VrefLevel [Byte0]: 46
2742 01:00:05.285500 [Byte1]: 46
2743 01:00:05.289584
2744 01:00:05.289660 Set Vref, RX VrefLevel [Byte0]: 47
2745 01:00:05.292950 [Byte1]: 47
2746 01:00:05.297769
2747 01:00:05.297868 Set Vref, RX VrefLevel [Byte0]: 48
2748 01:00:05.300695 [Byte1]: 48
2749 01:00:05.305316
2750 01:00:05.305392 Set Vref, RX VrefLevel [Byte0]: 49
2751 01:00:05.308622 [Byte1]: 49
2752 01:00:05.313355
2753 01:00:05.313432 Set Vref, RX VrefLevel [Byte0]: 50
2754 01:00:05.316854 [Byte1]: 50
2755 01:00:05.321038
2756 01:00:05.321115 Set Vref, RX VrefLevel [Byte0]: 51
2757 01:00:05.324794 [Byte1]: 51
2758 01:00:05.329102
2759 01:00:05.329179 Set Vref, RX VrefLevel [Byte0]: 52
2760 01:00:05.332748 [Byte1]: 52
2761 01:00:05.337089
2762 01:00:05.337166 Set Vref, RX VrefLevel [Byte0]: 53
2763 01:00:05.340271 [Byte1]: 53
2764 01:00:05.345078
2765 01:00:05.345155 Set Vref, RX VrefLevel [Byte0]: 54
2766 01:00:05.348569 [Byte1]: 54
2767 01:00:05.352881
2768 01:00:05.352958 Set Vref, RX VrefLevel [Byte0]: 55
2769 01:00:05.356287 [Byte1]: 55
2770 01:00:05.360833
2771 01:00:05.360910 Set Vref, RX VrefLevel [Byte0]: 56
2772 01:00:05.364248 [Byte1]: 56
2773 01:00:05.368643
2774 01:00:05.368720 Set Vref, RX VrefLevel [Byte0]: 57
2775 01:00:05.371952 [Byte1]: 57
2776 01:00:05.376841
2777 01:00:05.376922 Set Vref, RX VrefLevel [Byte0]: 58
2778 01:00:05.380473 [Byte1]: 58
2779 01:00:05.384590
2780 01:00:05.384668 Set Vref, RX VrefLevel [Byte0]: 59
2781 01:00:05.387837 [Byte1]: 59
2782 01:00:05.392808
2783 01:00:05.392885 Set Vref, RX VrefLevel [Byte0]: 60
2784 01:00:05.396272 [Byte1]: 60
2785 01:00:05.400359
2786 01:00:05.400436 Set Vref, RX VrefLevel [Byte0]: 61
2787 01:00:05.403931 [Byte1]: 61
2788 01:00:05.408582
2789 01:00:05.408659 Set Vref, RX VrefLevel [Byte0]: 62
2790 01:00:05.411853 [Byte1]: 62
2791 01:00:05.416603
2792 01:00:05.416680 Set Vref, RX VrefLevel [Byte0]: 63
2793 01:00:05.420226 [Byte1]: 63
2794 01:00:05.424415
2795 01:00:05.424492 Set Vref, RX VrefLevel [Byte0]: 64
2796 01:00:05.427582 [Byte1]: 64
2797 01:00:05.432472
2798 01:00:05.432550 Set Vref, RX VrefLevel [Byte0]: 65
2799 01:00:05.435371 [Byte1]: 65
2800 01:00:05.440292
2801 01:00:05.440374 Set Vref, RX VrefLevel [Byte0]: 66
2802 01:00:05.443356 [Byte1]: 66
2803 01:00:05.448246
2804 01:00:05.448323 Set Vref, RX VrefLevel [Byte0]: 67
2805 01:00:05.451478 [Byte1]: 67
2806 01:00:05.456016
2807 01:00:05.456093 Set Vref, RX VrefLevel [Byte0]: 68
2808 01:00:05.459385 [Byte1]: 68
2809 01:00:05.464288
2810 01:00:05.464366 Final RX Vref Byte 0 = 54 to rank0
2811 01:00:05.467694 Final RX Vref Byte 1 = 52 to rank0
2812 01:00:05.470914 Final RX Vref Byte 0 = 54 to rank1
2813 01:00:05.474176 Final RX Vref Byte 1 = 52 to rank1==
2814 01:00:05.477646 Dram Type= 6, Freq= 0, CH_0, rank 0
2815 01:00:05.484030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 01:00:05.484110 ==
2817 01:00:05.484170 DQS Delay:
2818 01:00:05.484225 DQS0 = 0, DQS1 = 0
2819 01:00:05.487323 DQM Delay:
2820 01:00:05.487400 DQM0 = 115, DQM1 = 104
2821 01:00:05.490783 DQ Delay:
2822 01:00:05.493896 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2823 01:00:05.497450 DQ4 =116, DQ5 =110, DQ6 =122, DQ7 =122
2824 01:00:05.500688 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2825 01:00:05.504158 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2826 01:00:05.504235
2827 01:00:05.504295
2828 01:00:05.511086 [DQSOSCAuto] RK0, (LSB)MR18= 0xffef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2829 01:00:05.514376 CH0 RK0: MR19=303, MR18=FFEF
2830 01:00:05.520797 CH0_RK0: MR19=0x303, MR18=0xFFEF, DQSOSC=410, MR23=63, INC=39, DEC=26
2831 01:00:05.520875
2832 01:00:05.524280 ----->DramcWriteLeveling(PI) begin...
2833 01:00:05.524358 ==
2834 01:00:05.527463 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 01:00:05.530976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 01:00:05.531054 ==
2837 01:00:05.534124 Write leveling (Byte 0): 32 => 32
2838 01:00:05.537504 Write leveling (Byte 1): 30 => 30
2839 01:00:05.540506 DramcWriteLeveling(PI) end<-----
2840 01:00:05.540583
2841 01:00:05.540642 ==
2842 01:00:05.544081 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 01:00:05.550790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 01:00:05.550872 ==
2845 01:00:05.550934 [Gating] SW mode calibration
2846 01:00:05.560776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2847 01:00:05.564020 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2848 01:00:05.567470 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2849 01:00:05.574132 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2850 01:00:05.577878 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 01:00:05.581010 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 01:00:05.587588 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 01:00:05.590807 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 01:00:05.594111 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 01:00:05.600563 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2856 01:00:05.604288 1 0 0 | B1->B0 | 2d2d 2929 | 0 0 | (0 1) (0 0)
2857 01:00:05.607665 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 01:00:05.614284 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 01:00:05.617223 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 01:00:05.620653 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 01:00:05.627680 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 01:00:05.631017 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2863 01:00:05.634164 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2864 01:00:05.637282 1 1 0 | B1->B0 | 3232 4444 | 0 0 | (0 0) (0 0)
2865 01:00:05.644346 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 01:00:05.647533 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 01:00:05.650548 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 01:00:05.657270 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 01:00:05.661316 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 01:00:05.664014 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2871 01:00:05.671075 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2872 01:00:05.674341 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2873 01:00:05.677336 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 01:00:05.683935 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 01:00:05.687183 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 01:00:05.691169 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 01:00:05.697452 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 01:00:05.700809 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 01:00:05.704368 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 01:00:05.710805 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 01:00:05.713957 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 01:00:05.717589 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 01:00:05.720959 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 01:00:05.727604 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 01:00:05.730833 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 01:00:05.734372 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 01:00:05.741230 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2888 01:00:05.744422 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2889 01:00:05.747736 Total UI for P1: 0, mck2ui 16
2890 01:00:05.751201 best dqsien dly found for B0: ( 1, 3, 28)
2891 01:00:05.754543 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2892 01:00:05.761087 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 01:00:05.761165 Total UI for P1: 0, mck2ui 16
2894 01:00:05.767681 best dqsien dly found for B1: ( 1, 4, 2)
2895 01:00:05.771118 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2896 01:00:05.774252 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2897 01:00:05.774328
2898 01:00:05.777942 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2899 01:00:05.780764 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2900 01:00:05.784158 [Gating] SW calibration Done
2901 01:00:05.784236 ==
2902 01:00:05.787700 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 01:00:05.791038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 01:00:05.791116 ==
2905 01:00:05.794117 RX Vref Scan: 0
2906 01:00:05.794194
2907 01:00:05.794254 RX Vref 0 -> 0, step: 1
2908 01:00:05.794308
2909 01:00:05.797650 RX Delay -40 -> 252, step: 8
2910 01:00:05.801304 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2911 01:00:05.807721 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2912 01:00:05.810858 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2913 01:00:05.814245 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2914 01:00:05.817726 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2915 01:00:05.820929 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2916 01:00:05.824176 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2917 01:00:05.831042 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2918 01:00:05.834462 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2919 01:00:05.837760 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2920 01:00:05.841006 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2921 01:00:05.844245 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2922 01:00:05.851278 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2923 01:00:05.854581 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2924 01:00:05.857899 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2925 01:00:05.861408 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2926 01:00:05.861485 ==
2927 01:00:05.864759 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 01:00:05.870901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 01:00:05.870981 ==
2930 01:00:05.871041 DQS Delay:
2931 01:00:05.871094 DQS0 = 0, DQS1 = 0
2932 01:00:05.874087 DQM Delay:
2933 01:00:05.874163 DQM0 = 116, DQM1 = 105
2934 01:00:05.877563 DQ Delay:
2935 01:00:05.881258 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2936 01:00:05.884510 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2937 01:00:05.887924 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2938 01:00:05.891187 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2939 01:00:05.891263
2940 01:00:05.891321
2941 01:00:05.891377 ==
2942 01:00:05.894436 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 01:00:05.897873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 01:00:05.897973 ==
2945 01:00:05.898076
2946 01:00:05.898131
2947 01:00:05.901265 TX Vref Scan disable
2948 01:00:05.904459 == TX Byte 0 ==
2949 01:00:05.908218 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2950 01:00:05.911202 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2951 01:00:05.914580 == TX Byte 1 ==
2952 01:00:05.917869 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2953 01:00:05.921104 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2954 01:00:05.921180 ==
2955 01:00:05.924318 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 01:00:05.928113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 01:00:05.930992 ==
2958 01:00:05.941733 TX Vref=22, minBit 1, minWin=25, winSum=419
2959 01:00:05.944874 TX Vref=24, minBit 12, minWin=25, winSum=429
2960 01:00:05.947801 TX Vref=26, minBit 2, minWin=26, winSum=431
2961 01:00:05.951355 TX Vref=28, minBit 3, minWin=26, winSum=436
2962 01:00:05.954926 TX Vref=30, minBit 3, minWin=26, winSum=436
2963 01:00:05.962017 TX Vref=32, minBit 0, minWin=27, winSum=437
2964 01:00:05.965029 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 32
2965 01:00:05.965108
2966 01:00:05.968306 Final TX Range 1 Vref 32
2967 01:00:05.968384
2968 01:00:05.968448 ==
2969 01:00:05.971217 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 01:00:05.975112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 01:00:05.975190 ==
2972 01:00:05.978467
2973 01:00:05.978544
2974 01:00:05.978604 TX Vref Scan disable
2975 01:00:05.981216 == TX Byte 0 ==
2976 01:00:05.984609 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2977 01:00:05.988405 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2978 01:00:05.991327 == TX Byte 1 ==
2979 01:00:05.994535 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2980 01:00:05.997977 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2981 01:00:06.001566
2982 01:00:06.001645 [DATLAT]
2983 01:00:06.001706 Freq=1200, CH0 RK1
2984 01:00:06.001763
2985 01:00:06.004541 DATLAT Default: 0xd
2986 01:00:06.004619 0, 0xFFFF, sum = 0
2987 01:00:06.007963 1, 0xFFFF, sum = 0
2988 01:00:06.008042 2, 0xFFFF, sum = 0
2989 01:00:06.011595 3, 0xFFFF, sum = 0
2990 01:00:06.011674 4, 0xFFFF, sum = 0
2991 01:00:06.015006 5, 0xFFFF, sum = 0
2992 01:00:06.018060 6, 0xFFFF, sum = 0
2993 01:00:06.018139 7, 0xFFFF, sum = 0
2994 01:00:06.021173 8, 0xFFFF, sum = 0
2995 01:00:06.021250 9, 0xFFFF, sum = 0
2996 01:00:06.024720 10, 0xFFFF, sum = 0
2997 01:00:06.024800 11, 0xFFFF, sum = 0
2998 01:00:06.027926 12, 0x0, sum = 1
2999 01:00:06.028004 13, 0x0, sum = 2
3000 01:00:06.031465 14, 0x0, sum = 3
3001 01:00:06.031543 15, 0x0, sum = 4
3002 01:00:06.031604 best_step = 13
3003 01:00:06.031660
3004 01:00:06.034471 ==
3005 01:00:06.038099 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 01:00:06.041568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 01:00:06.041645 ==
3008 01:00:06.041706 RX Vref Scan: 0
3009 01:00:06.041761
3010 01:00:06.044807 RX Vref 0 -> 0, step: 1
3011 01:00:06.044885
3012 01:00:06.048091 RX Delay -21 -> 252, step: 4
3013 01:00:06.051560 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3014 01:00:06.058017 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3015 01:00:06.061094 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3016 01:00:06.064715 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3017 01:00:06.068178 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3018 01:00:06.071105 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3019 01:00:06.078176 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3020 01:00:06.081430 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3021 01:00:06.084634 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3022 01:00:06.088034 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3023 01:00:06.091237 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3024 01:00:06.094539 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3025 01:00:06.101623 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3026 01:00:06.104936 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3027 01:00:06.108230 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3028 01:00:06.111380 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3029 01:00:06.111458 ==
3030 01:00:06.114579 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 01:00:06.121455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 01:00:06.121535 ==
3033 01:00:06.121596 DQS Delay:
3034 01:00:06.124637 DQS0 = 0, DQS1 = 0
3035 01:00:06.124714 DQM Delay:
3036 01:00:06.124775 DQM0 = 114, DQM1 = 105
3037 01:00:06.127831 DQ Delay:
3038 01:00:06.131318 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3039 01:00:06.134627 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3040 01:00:06.138017 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3041 01:00:06.141263 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
3042 01:00:06.141341
3043 01:00:06.141401
3044 01:00:06.147898 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3045 01:00:06.151083 CH0 RK1: MR19=403, MR18=1F2
3046 01:00:06.157911 CH0_RK1: MR19=0x403, MR18=0x1F2, DQSOSC=409, MR23=63, INC=39, DEC=26
3047 01:00:06.161064 [RxdqsGatingPostProcess] freq 1200
3048 01:00:06.167879 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3049 01:00:06.171117 best DQS0 dly(2T, 0.5T) = (0, 12)
3050 01:00:06.171195 best DQS1 dly(2T, 0.5T) = (0, 12)
3051 01:00:06.174600 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3052 01:00:06.177876 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3053 01:00:06.181261 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 01:00:06.184445 best DQS1 dly(2T, 0.5T) = (0, 12)
3055 01:00:06.188230 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 01:00:06.191470 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3057 01:00:06.194851 Pre-setting of DQS Precalculation
3058 01:00:06.198114 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3059 01:00:06.201346 ==
3060 01:00:06.204784 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 01:00:06.207978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 01:00:06.208055 ==
3063 01:00:06.211346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3064 01:00:06.218149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3065 01:00:06.227300 [CA 0] Center 38 (9~68) winsize 60
3066 01:00:06.230252 [CA 1] Center 38 (8~68) winsize 61
3067 01:00:06.233799 [CA 2] Center 35 (5~65) winsize 61
3068 01:00:06.236995 [CA 3] Center 34 (4~65) winsize 62
3069 01:00:06.240239 [CA 4] Center 34 (4~65) winsize 62
3070 01:00:06.243912 [CA 5] Center 34 (4~64) winsize 61
3071 01:00:06.243989
3072 01:00:06.247090 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3073 01:00:06.247166
3074 01:00:06.250452 [CATrainingPosCal] consider 1 rank data
3075 01:00:06.253904 u2DelayCellTimex100 = 270/100 ps
3076 01:00:06.257037 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3077 01:00:06.260594 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3078 01:00:06.267464 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3079 01:00:06.270761 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3080 01:00:06.274317 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3081 01:00:06.277265 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3082 01:00:06.277341
3083 01:00:06.280608 CA PerBit enable=1, Macro0, CA PI delay=34
3084 01:00:06.280685
3085 01:00:06.283917 [CBTSetCACLKResult] CA Dly = 34
3086 01:00:06.283994 CS Dly: 6 (0~37)
3087 01:00:06.284054 ==
3088 01:00:06.287224 Dram Type= 6, Freq= 0, CH_1, rank 1
3089 01:00:06.293924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 01:00:06.294044 ==
3091 01:00:06.297130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 01:00:06.304038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3093 01:00:06.313139 [CA 0] Center 38 (8~68) winsize 61
3094 01:00:06.315835 [CA 1] Center 38 (8~68) winsize 61
3095 01:00:06.319111 [CA 2] Center 34 (4~65) winsize 62
3096 01:00:06.322730 [CA 3] Center 34 (4~65) winsize 62
3097 01:00:06.325704 [CA 4] Center 34 (4~65) winsize 62
3098 01:00:06.329617 [CA 5] Center 33 (3~63) winsize 61
3099 01:00:06.329693
3100 01:00:06.332381 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3101 01:00:06.332457
3102 01:00:06.335965 [CATrainingPosCal] consider 2 rank data
3103 01:00:06.339357 u2DelayCellTimex100 = 270/100 ps
3104 01:00:06.342471 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3105 01:00:06.346000 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3106 01:00:06.352356 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3107 01:00:06.355744 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3108 01:00:06.359207 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3109 01:00:06.362560 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3110 01:00:06.362637
3111 01:00:06.366265 CA PerBit enable=1, Macro0, CA PI delay=33
3112 01:00:06.366341
3113 01:00:06.368916 [CBTSetCACLKResult] CA Dly = 33
3114 01:00:06.368992 CS Dly: 7 (0~40)
3115 01:00:06.369049
3116 01:00:06.372576 ----->DramcWriteLeveling(PI) begin...
3117 01:00:06.375800 ==
3118 01:00:06.379578 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 01:00:06.382598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 01:00:06.382675 ==
3121 01:00:06.385847 Write leveling (Byte 0): 26 => 26
3122 01:00:06.389247 Write leveling (Byte 1): 28 => 28
3123 01:00:06.392999 DramcWriteLeveling(PI) end<-----
3124 01:00:06.393075
3125 01:00:06.393133 ==
3126 01:00:06.396007 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 01:00:06.399351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 01:00:06.399428 ==
3129 01:00:06.402941 [Gating] SW mode calibration
3130 01:00:06.409222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3131 01:00:06.412765 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3132 01:00:06.419222 0 15 0 | B1->B0 | 2525 2323 | 1 0 | (1 1) (0 0)
3133 01:00:06.422454 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 01:00:06.426299 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3135 01:00:06.432876 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 01:00:06.436181 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 01:00:06.439554 0 15 20 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
3138 01:00:06.446514 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3139 01:00:06.449146 0 15 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
3140 01:00:06.452656 1 0 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3141 01:00:06.459225 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 01:00:06.462982 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 01:00:06.465959 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 01:00:06.472494 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 01:00:06.475747 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 01:00:06.479261 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 01:00:06.485872 1 0 28 | B1->B0 | 2929 2525 | 0 0 | (1 1) (1 1)
3148 01:00:06.489359 1 1 0 | B1->B0 | 4646 3737 | 0 1 | (0 0) (0 0)
3149 01:00:06.492584 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 01:00:06.495878 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 01:00:06.502603 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 01:00:06.505846 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 01:00:06.509652 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 01:00:06.516024 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 01:00:06.519332 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3156 01:00:06.522437 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3157 01:00:06.529535 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 01:00:06.532476 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 01:00:06.535827 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 01:00:06.542864 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 01:00:06.546019 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 01:00:06.549418 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 01:00:06.556324 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 01:00:06.559467 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 01:00:06.562713 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 01:00:06.569723 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 01:00:06.573112 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 01:00:06.576823 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 01:00:06.579431 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 01:00:06.586166 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 01:00:06.589861 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3172 01:00:06.592701 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 01:00:06.596499 Total UI for P1: 0, mck2ui 16
3174 01:00:06.599638 best dqsien dly found for B0: ( 1, 3, 28)
3175 01:00:06.602827 Total UI for P1: 0, mck2ui 16
3176 01:00:06.606435 best dqsien dly found for B1: ( 1, 3, 28)
3177 01:00:06.609646 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3178 01:00:06.613166 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3179 01:00:06.613243
3180 01:00:06.619493 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3181 01:00:06.623401 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3182 01:00:06.626221 [Gating] SW calibration Done
3183 01:00:06.626298 ==
3184 01:00:06.629507 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 01:00:06.633234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 01:00:06.633312 ==
3187 01:00:06.633371 RX Vref Scan: 0
3188 01:00:06.633426
3189 01:00:06.636085 RX Vref 0 -> 0, step: 1
3190 01:00:06.636163
3191 01:00:06.639542 RX Delay -40 -> 252, step: 8
3192 01:00:06.643257 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3193 01:00:06.646651 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3194 01:00:06.649470 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3195 01:00:06.656082 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3196 01:00:06.659456 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3197 01:00:06.663099 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3198 01:00:06.666413 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3199 01:00:06.670040 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3200 01:00:06.676535 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3201 01:00:06.679759 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3202 01:00:06.682911 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3203 01:00:06.686178 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3204 01:00:06.689735 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3205 01:00:06.696483 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3206 01:00:06.699844 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3207 01:00:06.703072 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3208 01:00:06.703149 ==
3209 01:00:06.706330 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 01:00:06.709768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 01:00:06.709846 ==
3212 01:00:06.713056 DQS Delay:
3213 01:00:06.713133 DQS0 = 0, DQS1 = 0
3214 01:00:06.716163 DQM Delay:
3215 01:00:06.716275 DQM0 = 115, DQM1 = 108
3216 01:00:06.716339 DQ Delay:
3217 01:00:06.722957 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3218 01:00:06.726324 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3219 01:00:06.729549 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3220 01:00:06.733227 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3221 01:00:06.733305
3222 01:00:06.733365
3223 01:00:06.733419 ==
3224 01:00:06.736246 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 01:00:06.739468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 01:00:06.739563 ==
3227 01:00:06.739646
3228 01:00:06.739727
3229 01:00:06.743122 TX Vref Scan disable
3230 01:00:06.746489 == TX Byte 0 ==
3231 01:00:06.749900 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3232 01:00:06.753049 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3233 01:00:06.753126 == TX Byte 1 ==
3234 01:00:06.759674 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3235 01:00:06.763436 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3236 01:00:06.763513 ==
3237 01:00:06.766600 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 01:00:06.769806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 01:00:06.769882 ==
3240 01:00:06.782677 TX Vref=22, minBit 2, minWin=24, winSum=410
3241 01:00:06.786450 TX Vref=24, minBit 0, minWin=25, winSum=417
3242 01:00:06.789544 TX Vref=26, minBit 1, minWin=25, winSum=420
3243 01:00:06.792434 TX Vref=28, minBit 0, minWin=26, winSum=426
3244 01:00:06.796279 TX Vref=30, minBit 0, minWin=26, winSum=426
3245 01:00:06.799454 TX Vref=32, minBit 0, minWin=26, winSum=428
3246 01:00:06.805903 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 32
3247 01:00:06.806039
3248 01:00:06.809387 Final TX Range 1 Vref 32
3249 01:00:06.809464
3250 01:00:06.809522 ==
3251 01:00:06.812698 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 01:00:06.816183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 01:00:06.816260 ==
3254 01:00:06.816319
3255 01:00:06.819225
3256 01:00:06.819302 TX Vref Scan disable
3257 01:00:06.822446 == TX Byte 0 ==
3258 01:00:06.826180 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3259 01:00:06.829303 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3260 01:00:06.832997 == TX Byte 1 ==
3261 01:00:06.835772 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3262 01:00:06.839321 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3263 01:00:06.839419
3264 01:00:06.842733 [DATLAT]
3265 01:00:06.842808 Freq=1200, CH1 RK0
3266 01:00:06.842867
3267 01:00:06.845920 DATLAT Default: 0xd
3268 01:00:06.846060 0, 0xFFFF, sum = 0
3269 01:00:06.849302 1, 0xFFFF, sum = 0
3270 01:00:06.849403 2, 0xFFFF, sum = 0
3271 01:00:06.852743 3, 0xFFFF, sum = 0
3272 01:00:06.852843 4, 0xFFFF, sum = 0
3273 01:00:06.855924 5, 0xFFFF, sum = 0
3274 01:00:06.856001 6, 0xFFFF, sum = 0
3275 01:00:06.859546 7, 0xFFFF, sum = 0
3276 01:00:06.859623 8, 0xFFFF, sum = 0
3277 01:00:06.862697 9, 0xFFFF, sum = 0
3278 01:00:06.866100 10, 0xFFFF, sum = 0
3279 01:00:06.866202 11, 0xFFFF, sum = 0
3280 01:00:06.869280 12, 0x0, sum = 1
3281 01:00:06.869372 13, 0x0, sum = 2
3282 01:00:06.869455 14, 0x0, sum = 3
3283 01:00:06.872606 15, 0x0, sum = 4
3284 01:00:06.872683 best_step = 13
3285 01:00:06.872741
3286 01:00:06.876046 ==
3287 01:00:06.876120 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 01:00:06.882683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 01:00:06.882760 ==
3290 01:00:06.882818 RX Vref Scan: 1
3291 01:00:06.882872
3292 01:00:06.886011 Set Vref Range= 32 -> 127
3293 01:00:06.886123
3294 01:00:06.889247 RX Vref 32 -> 127, step: 1
3295 01:00:06.889336
3296 01:00:06.892441 RX Delay -21 -> 252, step: 4
3297 01:00:06.892517
3298 01:00:06.896195 Set Vref, RX VrefLevel [Byte0]: 32
3299 01:00:06.899159 [Byte1]: 32
3300 01:00:06.899235
3301 01:00:06.902763 Set Vref, RX VrefLevel [Byte0]: 33
3302 01:00:06.906160 [Byte1]: 33
3303 01:00:06.906235
3304 01:00:06.909485 Set Vref, RX VrefLevel [Byte0]: 34
3305 01:00:06.912676 [Byte1]: 34
3306 01:00:06.916537
3307 01:00:06.916613 Set Vref, RX VrefLevel [Byte0]: 35
3308 01:00:06.920185 [Byte1]: 35
3309 01:00:06.924985
3310 01:00:06.925061 Set Vref, RX VrefLevel [Byte0]: 36
3311 01:00:06.928414 [Byte1]: 36
3312 01:00:06.932613
3313 01:00:06.932689 Set Vref, RX VrefLevel [Byte0]: 37
3314 01:00:06.936071 [Byte1]: 37
3315 01:00:06.940545
3316 01:00:06.940644 Set Vref, RX VrefLevel [Byte0]: 38
3317 01:00:06.943781 [Byte1]: 38
3318 01:00:06.948858
3319 01:00:06.948933 Set Vref, RX VrefLevel [Byte0]: 39
3320 01:00:06.952131 [Byte1]: 39
3321 01:00:06.956288
3322 01:00:06.956364 Set Vref, RX VrefLevel [Byte0]: 40
3323 01:00:06.959656 [Byte1]: 40
3324 01:00:06.964492
3325 01:00:06.964569 Set Vref, RX VrefLevel [Byte0]: 41
3326 01:00:06.967707 [Byte1]: 41
3327 01:00:06.972010
3328 01:00:06.972086 Set Vref, RX VrefLevel [Byte0]: 42
3329 01:00:06.975671 [Byte1]: 42
3330 01:00:06.980180
3331 01:00:06.980255 Set Vref, RX VrefLevel [Byte0]: 43
3332 01:00:06.983568 [Byte1]: 43
3333 01:00:06.987811
3334 01:00:06.987887 Set Vref, RX VrefLevel [Byte0]: 44
3335 01:00:06.991338 [Byte1]: 44
3336 01:00:06.996055
3337 01:00:06.996130 Set Vref, RX VrefLevel [Byte0]: 45
3338 01:00:06.999356 [Byte1]: 45
3339 01:00:07.003674
3340 01:00:07.003750 Set Vref, RX VrefLevel [Byte0]: 46
3341 01:00:07.007269 [Byte1]: 46
3342 01:00:07.011620
3343 01:00:07.011695 Set Vref, RX VrefLevel [Byte0]: 47
3344 01:00:07.015446 [Byte1]: 47
3345 01:00:07.019648
3346 01:00:07.019724 Set Vref, RX VrefLevel [Byte0]: 48
3347 01:00:07.022874 [Byte1]: 48
3348 01:00:07.028077
3349 01:00:07.028152 Set Vref, RX VrefLevel [Byte0]: 49
3350 01:00:07.031407 [Byte1]: 49
3351 01:00:07.035373
3352 01:00:07.035448 Set Vref, RX VrefLevel [Byte0]: 50
3353 01:00:07.038776 [Byte1]: 50
3354 01:00:07.043284
3355 01:00:07.046879 Set Vref, RX VrefLevel [Byte0]: 51
3356 01:00:07.050207 [Byte1]: 51
3357 01:00:07.050305
3358 01:00:07.053430 Set Vref, RX VrefLevel [Byte0]: 52
3359 01:00:07.056458 [Byte1]: 52
3360 01:00:07.056562
3361 01:00:07.060330 Set Vref, RX VrefLevel [Byte0]: 53
3362 01:00:07.063659 [Byte1]: 53
3363 01:00:07.067384
3364 01:00:07.067460 Set Vref, RX VrefLevel [Byte0]: 54
3365 01:00:07.070551 [Byte1]: 54
3366 01:00:07.075205
3367 01:00:07.075281 Set Vref, RX VrefLevel [Byte0]: 55
3368 01:00:07.078338 [Byte1]: 55
3369 01:00:07.083110
3370 01:00:07.083186 Set Vref, RX VrefLevel [Byte0]: 56
3371 01:00:07.086316 [Byte1]: 56
3372 01:00:07.091159
3373 01:00:07.091238 Set Vref, RX VrefLevel [Byte0]: 57
3374 01:00:07.094851 [Byte1]: 57
3375 01:00:07.098805
3376 01:00:07.098881 Set Vref, RX VrefLevel [Byte0]: 58
3377 01:00:07.101974 [Byte1]: 58
3378 01:00:07.107081
3379 01:00:07.107156 Set Vref, RX VrefLevel [Byte0]: 59
3380 01:00:07.109977 [Byte1]: 59
3381 01:00:07.114803
3382 01:00:07.114879 Set Vref, RX VrefLevel [Byte0]: 60
3383 01:00:07.118167 [Byte1]: 60
3384 01:00:07.122808
3385 01:00:07.122886 Set Vref, RX VrefLevel [Byte0]: 61
3386 01:00:07.125946 [Byte1]: 61
3387 01:00:07.130842
3388 01:00:07.130917 Set Vref, RX VrefLevel [Byte0]: 62
3389 01:00:07.134176 [Byte1]: 62
3390 01:00:07.138510
3391 01:00:07.138586 Set Vref, RX VrefLevel [Byte0]: 63
3392 01:00:07.141800 [Byte1]: 63
3393 01:00:07.146441
3394 01:00:07.146518 Set Vref, RX VrefLevel [Byte0]: 64
3395 01:00:07.149618 [Byte1]: 64
3396 01:00:07.154588
3397 01:00:07.154664 Set Vref, RX VrefLevel [Byte0]: 65
3398 01:00:07.157873 [Byte1]: 65
3399 01:00:07.162323
3400 01:00:07.162399 Set Vref, RX VrefLevel [Byte0]: 66
3401 01:00:07.166115 [Byte1]: 66
3402 01:00:07.170295
3403 01:00:07.170371 Set Vref, RX VrefLevel [Byte0]: 67
3404 01:00:07.173297 [Byte1]: 67
3405 01:00:07.177889
3406 01:00:07.177994 Set Vref, RX VrefLevel [Byte0]: 68
3407 01:00:07.181349 [Byte1]: 68
3408 01:00:07.185860
3409 01:00:07.185960 Set Vref, RX VrefLevel [Byte0]: 69
3410 01:00:07.189642 [Byte1]: 69
3411 01:00:07.194128
3412 01:00:07.194204 Final RX Vref Byte 0 = 56 to rank0
3413 01:00:07.197658 Final RX Vref Byte 1 = 53 to rank0
3414 01:00:07.200739 Final RX Vref Byte 0 = 56 to rank1
3415 01:00:07.204374 Final RX Vref Byte 1 = 53 to rank1==
3416 01:00:07.207623 Dram Type= 6, Freq= 0, CH_1, rank 0
3417 01:00:07.214392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 01:00:07.214470 ==
3419 01:00:07.214528 DQS Delay:
3420 01:00:07.214581 DQS0 = 0, DQS1 = 0
3421 01:00:07.217606 DQM Delay:
3422 01:00:07.217680 DQM0 = 115, DQM1 = 109
3423 01:00:07.220964 DQ Delay:
3424 01:00:07.223881 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3425 01:00:07.227218 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =112
3426 01:00:07.230974 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3427 01:00:07.234198 DQ12 =118, DQ13 =114, DQ14 =116, DQ15 =114
3428 01:00:07.234275
3429 01:00:07.234333
3430 01:00:07.240742 [DQSOSCAuto] RK0, (LSB)MR18= 0xe5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3431 01:00:07.243858 CH1 RK0: MR19=403, MR18=E5
3432 01:00:07.251002 CH1_RK0: MR19=0x403, MR18=0xE5, DQSOSC=410, MR23=63, INC=39, DEC=26
3433 01:00:07.251082
3434 01:00:07.253769 ----->DramcWriteLeveling(PI) begin...
3435 01:00:07.253846 ==
3436 01:00:07.257678 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 01:00:07.260862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 01:00:07.260940 ==
3439 01:00:07.264137 Write leveling (Byte 0): 27 => 27
3440 01:00:07.267415 Write leveling (Byte 1): 28 => 28
3441 01:00:07.270520 DramcWriteLeveling(PI) end<-----
3442 01:00:07.270597
3443 01:00:07.270655 ==
3444 01:00:07.273761 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 01:00:07.277708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 01:00:07.280582 ==
3447 01:00:07.280657 [Gating] SW mode calibration
3448 01:00:07.287498 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3449 01:00:07.293682 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3450 01:00:07.297225 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3451 01:00:07.304113 0 15 4 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
3452 01:00:07.307053 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 01:00:07.310366 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 01:00:07.317334 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 01:00:07.320976 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3456 01:00:07.323535 0 15 24 | B1->B0 | 3333 2828 | 0 0 | (0 0) (1 0)
3457 01:00:07.330325 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3458 01:00:07.333972 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 01:00:07.337007 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 01:00:07.340603 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 01:00:07.347247 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 01:00:07.350832 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 01:00:07.353955 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 01:00:07.360722 1 0 24 | B1->B0 | 2424 4444 | 0 1 | (0 0) (0 0)
3465 01:00:07.363979 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3466 01:00:07.367355 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 01:00:07.373945 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 01:00:07.377342 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 01:00:07.380753 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 01:00:07.387198 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 01:00:07.391021 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3472 01:00:07.394320 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3473 01:00:07.400703 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3474 01:00:07.404172 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 01:00:07.407138 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 01:00:07.413951 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 01:00:07.417221 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 01:00:07.420293 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 01:00:07.427510 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 01:00:07.430648 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 01:00:07.433579 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 01:00:07.440530 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 01:00:07.443758 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 01:00:07.447157 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 01:00:07.450368 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 01:00:07.457284 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 01:00:07.460635 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3488 01:00:07.463686 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3489 01:00:07.470340 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3490 01:00:07.473933 Total UI for P1: 0, mck2ui 16
3491 01:00:07.476988 best dqsien dly found for B0: ( 1, 3, 22)
3492 01:00:07.480605 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 01:00:07.483458 Total UI for P1: 0, mck2ui 16
3494 01:00:07.487237 best dqsien dly found for B1: ( 1, 3, 26)
3495 01:00:07.490642 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3496 01:00:07.493670 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3497 01:00:07.493744
3498 01:00:07.496855 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3499 01:00:07.500581 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3500 01:00:07.503624 [Gating] SW calibration Done
3501 01:00:07.503699 ==
3502 01:00:07.506970 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 01:00:07.510502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 01:00:07.513564 ==
3505 01:00:07.513639 RX Vref Scan: 0
3506 01:00:07.513698
3507 01:00:07.517058 RX Vref 0 -> 0, step: 1
3508 01:00:07.517147
3509 01:00:07.520268 RX Delay -40 -> 252, step: 8
3510 01:00:07.523571 iDelay=192, Bit 0, Center 115 (40 ~ 191) 152
3511 01:00:07.526879 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3512 01:00:07.530305 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3513 01:00:07.533640 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3514 01:00:07.540734 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3515 01:00:07.544100 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3516 01:00:07.546917 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3517 01:00:07.550933 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3518 01:00:07.553801 iDelay=192, Bit 8, Center 99 (24 ~ 175) 152
3519 01:00:07.557282 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3520 01:00:07.563945 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3521 01:00:07.567130 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3522 01:00:07.570360 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3523 01:00:07.573860 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3524 01:00:07.577266 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3525 01:00:07.583771 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3526 01:00:07.583849 ==
3527 01:00:07.587509 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 01:00:07.590460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 01:00:07.590539 ==
3530 01:00:07.590598 DQS Delay:
3531 01:00:07.593724 DQS0 = 0, DQS1 = 0
3532 01:00:07.593801 DQM Delay:
3533 01:00:07.597007 DQM0 = 112, DQM1 = 110
3534 01:00:07.597084 DQ Delay:
3535 01:00:07.600876 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3536 01:00:07.603775 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3537 01:00:07.607606 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3538 01:00:07.610698 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3539 01:00:07.610775
3540 01:00:07.610834
3541 01:00:07.613772 ==
3542 01:00:07.617204 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 01:00:07.620795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 01:00:07.620874 ==
3545 01:00:07.620933
3546 01:00:07.620987
3547 01:00:07.623836 TX Vref Scan disable
3548 01:00:07.623914 == TX Byte 0 ==
3549 01:00:07.627109 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3550 01:00:07.634125 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3551 01:00:07.634203 == TX Byte 1 ==
3552 01:00:07.637337 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3553 01:00:07.644127 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3554 01:00:07.644204 ==
3555 01:00:07.647346 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 01:00:07.650494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 01:00:07.650572 ==
3558 01:00:07.662481 TX Vref=22, minBit 3, minWin=25, winSum=419
3559 01:00:07.665531 TX Vref=24, minBit 1, minWin=25, winSum=420
3560 01:00:07.669313 TX Vref=26, minBit 1, minWin=26, winSum=429
3561 01:00:07.672522 TX Vref=28, minBit 2, minWin=26, winSum=430
3562 01:00:07.675593 TX Vref=30, minBit 2, minWin=26, winSum=433
3563 01:00:07.679030 TX Vref=32, minBit 3, minWin=26, winSum=438
3564 01:00:07.685925 [TxChooseVref] Worse bit 3, Min win 26, Win sum 438, Final Vref 32
3565 01:00:07.686040
3566 01:00:07.689325 Final TX Range 1 Vref 32
3567 01:00:07.689403
3568 01:00:07.689462 ==
3569 01:00:07.692542 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 01:00:07.695848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 01:00:07.695927 ==
3572 01:00:07.695986
3573 01:00:07.696040
3574 01:00:07.699155 TX Vref Scan disable
3575 01:00:07.702658 == TX Byte 0 ==
3576 01:00:07.705678 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3577 01:00:07.709297 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3578 01:00:07.712373 == TX Byte 1 ==
3579 01:00:07.716079 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3580 01:00:07.719268 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3581 01:00:07.719350
3582 01:00:07.722680 [DATLAT]
3583 01:00:07.722756 Freq=1200, CH1 RK1
3584 01:00:07.722816
3585 01:00:07.725874 DATLAT Default: 0xd
3586 01:00:07.725974 0, 0xFFFF, sum = 0
3587 01:00:07.729247 1, 0xFFFF, sum = 0
3588 01:00:07.729325 2, 0xFFFF, sum = 0
3589 01:00:07.732648 3, 0xFFFF, sum = 0
3590 01:00:07.732725 4, 0xFFFF, sum = 0
3591 01:00:07.736075 5, 0xFFFF, sum = 0
3592 01:00:07.736218 6, 0xFFFF, sum = 0
3593 01:00:07.739350 7, 0xFFFF, sum = 0
3594 01:00:07.739468 8, 0xFFFF, sum = 0
3595 01:00:07.742520 9, 0xFFFF, sum = 0
3596 01:00:07.742599 10, 0xFFFF, sum = 0
3597 01:00:07.745933 11, 0xFFFF, sum = 0
3598 01:00:07.746032 12, 0x0, sum = 1
3599 01:00:07.749917 13, 0x0, sum = 2
3600 01:00:07.750082 14, 0x0, sum = 3
3601 01:00:07.752659 15, 0x0, sum = 4
3602 01:00:07.752802 best_step = 13
3603 01:00:07.752870
3604 01:00:07.752931 ==
3605 01:00:07.756194 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 01:00:07.763120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 01:00:07.763276 ==
3608 01:00:07.763354 RX Vref Scan: 0
3609 01:00:07.763422
3610 01:00:07.765943 RX Vref 0 -> 0, step: 1
3611 01:00:07.766092
3612 01:00:07.769551 RX Delay -21 -> 252, step: 4
3613 01:00:07.772707 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3614 01:00:07.775906 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3615 01:00:07.782716 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3616 01:00:07.786009 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3617 01:00:07.789317 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3618 01:00:07.792727 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3619 01:00:07.796254 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3620 01:00:07.799612 iDelay=191, Bit 7, Center 108 (43 ~ 174) 132
3621 01:00:07.805939 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3622 01:00:07.809536 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3623 01:00:07.813324 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3624 01:00:07.816463 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3625 01:00:07.822921 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3626 01:00:07.826288 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3627 01:00:07.829626 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3628 01:00:07.833315 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3629 01:00:07.833725 ==
3630 01:00:07.836216 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 01:00:07.839618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 01:00:07.843013 ==
3633 01:00:07.843405 DQS Delay:
3634 01:00:07.843671 DQS0 = 0, DQS1 = 0
3635 01:00:07.846322 DQM Delay:
3636 01:00:07.846713 DQM0 = 113, DQM1 = 110
3637 01:00:07.849699 DQ Delay:
3638 01:00:07.852959 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3639 01:00:07.856206 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =108
3640 01:00:07.859489 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3641 01:00:07.862756 DQ12 =116, DQ13 =118, DQ14 =118, DQ15 =120
3642 01:00:07.863010
3643 01:00:07.863135
3644 01:00:07.869425 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb03, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 412 ps
3645 01:00:07.872894 CH1 RK1: MR19=304, MR18=FB03
3646 01:00:07.879388 CH1_RK1: MR19=0x304, MR18=0xFB03, DQSOSC=408, MR23=63, INC=39, DEC=26
3647 01:00:07.882569 [RxdqsGatingPostProcess] freq 1200
3648 01:00:07.889371 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3649 01:00:07.893102 best DQS0 dly(2T, 0.5T) = (0, 11)
3650 01:00:07.893209 best DQS1 dly(2T, 0.5T) = (0, 11)
3651 01:00:07.896026 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3652 01:00:07.899696 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3653 01:00:07.902578 best DQS0 dly(2T, 0.5T) = (0, 11)
3654 01:00:07.905847 best DQS1 dly(2T, 0.5T) = (0, 11)
3655 01:00:07.909338 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3656 01:00:07.912499 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3657 01:00:07.915898 Pre-setting of DQS Precalculation
3658 01:00:07.922432 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3659 01:00:07.929406 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3660 01:00:07.935794 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3661 01:00:07.935917
3662 01:00:07.935978
3663 01:00:07.939074 [Calibration Summary] 2400 Mbps
3664 01:00:07.939160 CH 0, Rank 0
3665 01:00:07.943062 SW Impedance : PASS
3666 01:00:07.945899 DUTY Scan : NO K
3667 01:00:07.946011 ZQ Calibration : PASS
3668 01:00:07.949272 Jitter Meter : NO K
3669 01:00:07.949361 CBT Training : PASS
3670 01:00:07.952682 Write leveling : PASS
3671 01:00:07.956358 RX DQS gating : PASS
3672 01:00:07.956436 RX DQ/DQS(RDDQC) : PASS
3673 01:00:07.959198 TX DQ/DQS : PASS
3674 01:00:07.962634 RX DATLAT : PASS
3675 01:00:07.962729 RX DQ/DQS(Engine): PASS
3676 01:00:07.966121 TX OE : NO K
3677 01:00:07.966197 All Pass.
3678 01:00:07.966256
3679 01:00:07.969716 CH 0, Rank 1
3680 01:00:07.969792 SW Impedance : PASS
3681 01:00:07.972682 DUTY Scan : NO K
3682 01:00:07.976130 ZQ Calibration : PASS
3683 01:00:07.976265 Jitter Meter : NO K
3684 01:00:07.979630 CBT Training : PASS
3685 01:00:07.982579 Write leveling : PASS
3686 01:00:07.982708 RX DQS gating : PASS
3687 01:00:07.986542 RX DQ/DQS(RDDQC) : PASS
3688 01:00:07.986619 TX DQ/DQS : PASS
3689 01:00:07.989650 RX DATLAT : PASS
3690 01:00:07.992710 RX DQ/DQS(Engine): PASS
3691 01:00:07.992855 TX OE : NO K
3692 01:00:07.996340 All Pass.
3693 01:00:07.996421
3694 01:00:07.996480 CH 1, Rank 0
3695 01:00:07.999251 SW Impedance : PASS
3696 01:00:07.999327 DUTY Scan : NO K
3697 01:00:08.002471 ZQ Calibration : PASS
3698 01:00:08.005825 Jitter Meter : NO K
3699 01:00:08.005925 CBT Training : PASS
3700 01:00:08.009341 Write leveling : PASS
3701 01:00:08.012945 RX DQS gating : PASS
3702 01:00:08.013046 RX DQ/DQS(RDDQC) : PASS
3703 01:00:08.016420 TX DQ/DQS : PASS
3704 01:00:08.019516 RX DATLAT : PASS
3705 01:00:08.019599 RX DQ/DQS(Engine): PASS
3706 01:00:08.022619 TX OE : NO K
3707 01:00:08.022689 All Pass.
3708 01:00:08.022762
3709 01:00:08.025923 CH 1, Rank 1
3710 01:00:08.026023 SW Impedance : PASS
3711 01:00:08.029586 DUTY Scan : NO K
3712 01:00:08.029664 ZQ Calibration : PASS
3713 01:00:08.032795 Jitter Meter : NO K
3714 01:00:08.035800 CBT Training : PASS
3715 01:00:08.035879 Write leveling : PASS
3716 01:00:08.039448 RX DQS gating : PASS
3717 01:00:08.042564 RX DQ/DQS(RDDQC) : PASS
3718 01:00:08.042643 TX DQ/DQS : PASS
3719 01:00:08.046339 RX DATLAT : PASS
3720 01:00:08.049766 RX DQ/DQS(Engine): PASS
3721 01:00:08.049845 TX OE : NO K
3722 01:00:08.052708 All Pass.
3723 01:00:08.052786
3724 01:00:08.052863 DramC Write-DBI off
3725 01:00:08.056192 PER_BANK_REFRESH: Hybrid Mode
3726 01:00:08.056271 TX_TRACKING: ON
3727 01:00:08.066367 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3728 01:00:08.069325 [FAST_K] Save calibration result to emmc
3729 01:00:08.072691 dramc_set_vcore_voltage set vcore to 650000
3730 01:00:08.076029 Read voltage for 600, 5
3731 01:00:08.076107 Vio18 = 0
3732 01:00:08.079464 Vcore = 650000
3733 01:00:08.079542 Vdram = 0
3734 01:00:08.079618 Vddq = 0
3735 01:00:08.079691 Vmddr = 0
3736 01:00:08.086486 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3737 01:00:08.093031 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3738 01:00:08.093111 MEM_TYPE=3, freq_sel=19
3739 01:00:08.096244 sv_algorithm_assistance_LP4_1600
3740 01:00:08.099373 ============ PULL DRAM RESETB DOWN ============
3741 01:00:08.106362 ========== PULL DRAM RESETB DOWN end =========
3742 01:00:08.109591 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3743 01:00:08.112852 ===================================
3744 01:00:08.116344 LPDDR4 DRAM CONFIGURATION
3745 01:00:08.119298 ===================================
3746 01:00:08.119377 EX_ROW_EN[0] = 0x0
3747 01:00:08.122978 EX_ROW_EN[1] = 0x0
3748 01:00:08.123056 LP4Y_EN = 0x0
3749 01:00:08.126160 WORK_FSP = 0x0
3750 01:00:08.126239 WL = 0x2
3751 01:00:08.129460 RL = 0x2
3752 01:00:08.129537 BL = 0x2
3753 01:00:08.132861 RPST = 0x0
3754 01:00:08.136226 RD_PRE = 0x0
3755 01:00:08.136303 WR_PRE = 0x1
3756 01:00:08.139543 WR_PST = 0x0
3757 01:00:08.139621 DBI_WR = 0x0
3758 01:00:08.142633 DBI_RD = 0x0
3759 01:00:08.142711 OTF = 0x1
3760 01:00:08.146008 ===================================
3761 01:00:08.149273 ===================================
3762 01:00:08.149351 ANA top config
3763 01:00:08.152876 ===================================
3764 01:00:08.156153 DLL_ASYNC_EN = 0
3765 01:00:08.159536 ALL_SLAVE_EN = 1
3766 01:00:08.162677 NEW_RANK_MODE = 1
3767 01:00:08.166421 DLL_IDLE_MODE = 1
3768 01:00:08.166499 LP45_APHY_COMB_EN = 1
3769 01:00:08.169768 TX_ODT_DIS = 1
3770 01:00:08.172860 NEW_8X_MODE = 1
3771 01:00:08.176399 ===================================
3772 01:00:08.179271 ===================================
3773 01:00:08.182757 data_rate = 1200
3774 01:00:08.186361 CKR = 1
3775 01:00:08.186455 DQ_P2S_RATIO = 8
3776 01:00:08.189708 ===================================
3777 01:00:08.193252 CA_P2S_RATIO = 8
3778 01:00:08.195842 DQ_CA_OPEN = 0
3779 01:00:08.199267 DQ_SEMI_OPEN = 0
3780 01:00:08.202652 CA_SEMI_OPEN = 0
3781 01:00:08.206186 CA_FULL_RATE = 0
3782 01:00:08.206268 DQ_CKDIV4_EN = 1
3783 01:00:08.209383 CA_CKDIV4_EN = 1
3784 01:00:08.212678 CA_PREDIV_EN = 0
3785 01:00:08.216072 PH8_DLY = 0
3786 01:00:08.219216 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3787 01:00:08.223008 DQ_AAMCK_DIV = 4
3788 01:00:08.223086 CA_AAMCK_DIV = 4
3789 01:00:08.225928 CA_ADMCK_DIV = 4
3790 01:00:08.229537 DQ_TRACK_CA_EN = 0
3791 01:00:08.232597 CA_PICK = 600
3792 01:00:08.236249 CA_MCKIO = 600
3793 01:00:08.239527 MCKIO_SEMI = 0
3794 01:00:08.239604 PLL_FREQ = 2288
3795 01:00:08.242790 DQ_UI_PI_RATIO = 32
3796 01:00:08.246141 CA_UI_PI_RATIO = 0
3797 01:00:08.249248 ===================================
3798 01:00:08.252757 ===================================
3799 01:00:08.256049 memory_type:LPDDR4
3800 01:00:08.259171 GP_NUM : 10
3801 01:00:08.259249 SRAM_EN : 1
3802 01:00:08.262748 MD32_EN : 0
3803 01:00:08.266361 ===================================
3804 01:00:08.266441 [ANA_INIT] >>>>>>>>>>>>>>
3805 01:00:08.269308 <<<<<< [CONFIGURE PHASE]: ANA_TX
3806 01:00:08.272567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3807 01:00:08.276338 ===================================
3808 01:00:08.279208 data_rate = 1200,PCW = 0X5800
3809 01:00:08.282986 ===================================
3810 01:00:08.286294 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3811 01:00:08.292692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3812 01:00:08.295906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 01:00:08.302756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3814 01:00:08.305907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3815 01:00:08.309941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3816 01:00:08.310061 [ANA_INIT] flow start
3817 01:00:08.312749 [ANA_INIT] PLL >>>>>>>>
3818 01:00:08.315879 [ANA_INIT] PLL <<<<<<<<
3819 01:00:08.319513 [ANA_INIT] MIDPI >>>>>>>>
3820 01:00:08.319591 [ANA_INIT] MIDPI <<<<<<<<
3821 01:00:08.322555 [ANA_INIT] DLL >>>>>>>>
3822 01:00:08.326177 [ANA_INIT] flow end
3823 01:00:08.329300 ============ LP4 DIFF to SE enter ============
3824 01:00:08.332835 ============ LP4 DIFF to SE exit ============
3825 01:00:08.336382 [ANA_INIT] <<<<<<<<<<<<<
3826 01:00:08.339445 [Flow] Enable top DCM control >>>>>
3827 01:00:08.342787 [Flow] Enable top DCM control <<<<<
3828 01:00:08.342865 Enable DLL master slave shuffle
3829 01:00:08.349335 ==============================================================
3830 01:00:08.352902 Gating Mode config
3831 01:00:08.356081 ==============================================================
3832 01:00:08.359397 Config description:
3833 01:00:08.369416 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3834 01:00:08.376353 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3835 01:00:08.379580 SELPH_MODE 0: By rank 1: By Phase
3836 01:00:08.386019 ==============================================================
3837 01:00:08.389447 GAT_TRACK_EN = 1
3838 01:00:08.392903 RX_GATING_MODE = 2
3839 01:00:08.396510 RX_GATING_TRACK_MODE = 2
3840 01:00:08.399364 SELPH_MODE = 1
3841 01:00:08.399440 PICG_EARLY_EN = 1
3842 01:00:08.402726 VALID_LAT_VALUE = 1
3843 01:00:08.409382 ==============================================================
3844 01:00:08.412762 Enter into Gating configuration >>>>
3845 01:00:08.416582 Exit from Gating configuration <<<<
3846 01:00:08.419624 Enter into DVFS_PRE_config >>>>>
3847 01:00:08.429584 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3848 01:00:08.432869 Exit from DVFS_PRE_config <<<<<
3849 01:00:08.436202 Enter into PICG configuration >>>>
3850 01:00:08.439637 Exit from PICG configuration <<<<
3851 01:00:08.443094 [RX_INPUT] configuration >>>>>
3852 01:00:08.446270 [RX_INPUT] configuration <<<<<
3853 01:00:08.449815 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3854 01:00:08.456294 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3855 01:00:08.463224 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3856 01:00:08.470012 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3857 01:00:08.473334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3858 01:00:08.479814 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3859 01:00:08.482985 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3860 01:00:08.489711 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3861 01:00:08.493375 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3862 01:00:08.496250 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3863 01:00:08.500051 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3864 01:00:08.506238 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3865 01:00:08.510012 ===================================
3866 01:00:08.510103 LPDDR4 DRAM CONFIGURATION
3867 01:00:08.513354 ===================================
3868 01:00:08.516707 EX_ROW_EN[0] = 0x0
3869 01:00:08.520215 EX_ROW_EN[1] = 0x0
3870 01:00:08.520291 LP4Y_EN = 0x0
3871 01:00:08.523195 WORK_FSP = 0x0
3872 01:00:08.523270 WL = 0x2
3873 01:00:08.527080 RL = 0x2
3874 01:00:08.527156 BL = 0x2
3875 01:00:08.530416 RPST = 0x0
3876 01:00:08.530718 RD_PRE = 0x0
3877 01:00:08.533499 WR_PRE = 0x1
3878 01:00:08.533720 WR_PST = 0x0
3879 01:00:08.536580 DBI_WR = 0x0
3880 01:00:08.536801 DBI_RD = 0x0
3881 01:00:08.540409 OTF = 0x1
3882 01:00:08.543211 ===================================
3883 01:00:08.547033 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3884 01:00:08.550343 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3885 01:00:08.556649 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3886 01:00:08.556829 ===================================
3887 01:00:08.560123 LPDDR4 DRAM CONFIGURATION
3888 01:00:08.563412 ===================================
3889 01:00:08.566618 EX_ROW_EN[0] = 0x10
3890 01:00:08.566797 EX_ROW_EN[1] = 0x0
3891 01:00:08.570275 LP4Y_EN = 0x0
3892 01:00:08.570454 WORK_FSP = 0x0
3893 01:00:08.573431 WL = 0x2
3894 01:00:08.573608 RL = 0x2
3895 01:00:08.576602 BL = 0x2
3896 01:00:08.576779 RPST = 0x0
3897 01:00:08.579912 RD_PRE = 0x0
3898 01:00:08.583314 WR_PRE = 0x1
3899 01:00:08.583461 WR_PST = 0x0
3900 01:00:08.586630 DBI_WR = 0x0
3901 01:00:08.586778 DBI_RD = 0x0
3902 01:00:08.589849 OTF = 0x1
3903 01:00:08.593174 ===================================
3904 01:00:08.596506 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3905 01:00:08.601834 nWR fixed to 30
3906 01:00:08.605070 [ModeRegInit_LP4] CH0 RK0
3907 01:00:08.605171 [ModeRegInit_LP4] CH0 RK1
3908 01:00:08.608629 [ModeRegInit_LP4] CH1 RK0
3909 01:00:08.611728 [ModeRegInit_LP4] CH1 RK1
3910 01:00:08.611808 match AC timing 17
3911 01:00:08.618519 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3912 01:00:08.621829 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3913 01:00:08.625316 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3914 01:00:08.632079 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3915 01:00:08.635242 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3916 01:00:08.635319 ==
3917 01:00:08.638467 Dram Type= 6, Freq= 0, CH_0, rank 0
3918 01:00:08.642165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3919 01:00:08.642241 ==
3920 01:00:08.648609 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3921 01:00:08.655010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3922 01:00:08.658311 [CA 0] Center 36 (6~66) winsize 61
3923 01:00:08.662155 [CA 1] Center 36 (6~66) winsize 61
3924 01:00:08.665379 [CA 2] Center 34 (4~65) winsize 62
3925 01:00:08.668727 [CA 3] Center 34 (4~65) winsize 62
3926 01:00:08.672238 [CA 4] Center 34 (4~64) winsize 61
3927 01:00:08.675228 [CA 5] Center 33 (3~64) winsize 62
3928 01:00:08.675320
3929 01:00:08.678652 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3930 01:00:08.678728
3931 01:00:08.681813 [CATrainingPosCal] consider 1 rank data
3932 01:00:08.685317 u2DelayCellTimex100 = 270/100 ps
3933 01:00:08.688436 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3934 01:00:08.691768 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3935 01:00:08.695445 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3936 01:00:08.698565 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 01:00:08.701962 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3938 01:00:08.705576 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 01:00:08.705652
3940 01:00:08.712159 CA PerBit enable=1, Macro0, CA PI delay=33
3941 01:00:08.712240
3942 01:00:08.712299 [CBTSetCACLKResult] CA Dly = 33
3943 01:00:08.715583 CS Dly: 5 (0~36)
3944 01:00:08.715665 ==
3945 01:00:08.718429 Dram Type= 6, Freq= 0, CH_0, rank 1
3946 01:00:08.721738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3947 01:00:08.721817 ==
3948 01:00:08.728879 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3949 01:00:08.734963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3950 01:00:08.738899 [CA 0] Center 36 (6~66) winsize 61
3951 01:00:08.741880 [CA 1] Center 36 (6~66) winsize 61
3952 01:00:08.745299 [CA 2] Center 34 (4~65) winsize 62
3953 01:00:08.748708 [CA 3] Center 34 (4~65) winsize 62
3954 01:00:08.751882 [CA 4] Center 33 (3~64) winsize 62
3955 01:00:08.755255 [CA 5] Center 33 (3~64) winsize 62
3956 01:00:08.755333
3957 01:00:08.758582 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3958 01:00:08.758659
3959 01:00:08.761886 [CATrainingPosCal] consider 2 rank data
3960 01:00:08.765509 u2DelayCellTimex100 = 270/100 ps
3961 01:00:08.769423 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3962 01:00:08.772499 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3963 01:00:08.775692 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3964 01:00:08.779074 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3965 01:00:08.782135 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3966 01:00:08.785565 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 01:00:08.786024
3968 01:00:08.792331 CA PerBit enable=1, Macro0, CA PI delay=33
3969 01:00:08.792661
3970 01:00:08.792917 [CBTSetCACLKResult] CA Dly = 33
3971 01:00:08.795860 CS Dly: 4 (0~35)
3972 01:00:08.796188
3973 01:00:08.798691 ----->DramcWriteLeveling(PI) begin...
3974 01:00:08.799026 ==
3975 01:00:08.802381 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 01:00:08.805839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 01:00:08.806333 ==
3978 01:00:08.809028 Write leveling (Byte 0): 31 => 31
3979 01:00:08.812134 Write leveling (Byte 1): 29 => 29
3980 01:00:08.816224 DramcWriteLeveling(PI) end<-----
3981 01:00:08.816646
3982 01:00:08.816912 ==
3983 01:00:08.818803 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 01:00:08.822271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 01:00:08.825737 ==
3986 01:00:08.826161 [Gating] SW mode calibration
3987 01:00:08.832079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3988 01:00:08.839413 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3989 01:00:08.842750 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 01:00:08.849044 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 01:00:08.852704 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 01:00:08.855919 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 01:00:08.862773 0 9 16 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (0 0)
3994 01:00:08.866138 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3995 01:00:08.869503 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 01:00:08.872881 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 01:00:08.879216 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 01:00:08.882360 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 01:00:08.885645 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 01:00:08.892621 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 01:00:08.895943 0 10 16 | B1->B0 | 2f2f 3c3c | 0 1 | (0 0) (0 0)
4002 01:00:08.899327 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 01:00:08.905756 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 01:00:08.909382 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 01:00:08.912277 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 01:00:08.919157 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 01:00:08.922562 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 01:00:08.926223 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 01:00:08.932791 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4010 01:00:08.935809 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 01:00:08.939560 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 01:00:08.946365 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 01:00:08.949750 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 01:00:08.952645 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 01:00:08.959932 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 01:00:08.962807 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 01:00:08.966535 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 01:00:08.972611 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 01:00:08.976192 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 01:00:08.979199 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 01:00:08.982924 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 01:00:08.989500 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 01:00:08.992876 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 01:00:08.996119 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4025 01:00:09.002626 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4026 01:00:09.005691 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4027 01:00:09.009715 Total UI for P1: 0, mck2ui 16
4028 01:00:09.012440 best dqsien dly found for B0: ( 0, 13, 16)
4029 01:00:09.016228 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 01:00:09.019546 Total UI for P1: 0, mck2ui 16
4031 01:00:09.022666 best dqsien dly found for B1: ( 0, 13, 16)
4032 01:00:09.026193 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4033 01:00:09.029190 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4034 01:00:09.029694
4035 01:00:09.035797 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4036 01:00:09.039484 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4037 01:00:09.042466 [Gating] SW calibration Done
4038 01:00:09.042857 ==
4039 01:00:09.045895 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 01:00:09.049491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 01:00:09.049960 ==
4042 01:00:09.050317 RX Vref Scan: 0
4043 01:00:09.050599
4044 01:00:09.052990 RX Vref 0 -> 0, step: 1
4045 01:00:09.053458
4046 01:00:09.056088 RX Delay -230 -> 252, step: 16
4047 01:00:09.059436 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4048 01:00:09.062601 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4049 01:00:09.069273 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4050 01:00:09.072769 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4051 01:00:09.075896 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4052 01:00:09.079125 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4053 01:00:09.085906 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4054 01:00:09.089461 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4055 01:00:09.092623 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4056 01:00:09.095960 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4057 01:00:09.099028 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4058 01:00:09.105921 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4059 01:00:09.108859 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4060 01:00:09.112219 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4061 01:00:09.115753 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4062 01:00:09.121979 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4063 01:00:09.122421 ==
4064 01:00:09.125823 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 01:00:09.129205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 01:00:09.129694 ==
4067 01:00:09.130047 DQS Delay:
4068 01:00:09.131816 DQS0 = 0, DQS1 = 0
4069 01:00:09.132239 DQM Delay:
4070 01:00:09.135439 DQM0 = 43, DQM1 = 34
4071 01:00:09.135835 DQ Delay:
4072 01:00:09.138463 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4073 01:00:09.142060 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4074 01:00:09.145717 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4075 01:00:09.148619 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4076 01:00:09.149009
4077 01:00:09.149307
4078 01:00:09.149632 ==
4079 01:00:09.151947 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 01:00:09.155399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 01:00:09.158907 ==
4082 01:00:09.159379
4083 01:00:09.159685
4084 01:00:09.159967 TX Vref Scan disable
4085 01:00:09.162310 == TX Byte 0 ==
4086 01:00:09.165245 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4087 01:00:09.168579 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4088 01:00:09.171991 == TX Byte 1 ==
4089 01:00:09.175474 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4090 01:00:09.178812 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4091 01:00:09.182445 ==
4092 01:00:09.182922 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 01:00:09.188600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 01:00:09.189061 ==
4095 01:00:09.189365
4096 01:00:09.189643
4097 01:00:09.192131 TX Vref Scan disable
4098 01:00:09.192606 == TX Byte 0 ==
4099 01:00:09.198503 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4100 01:00:09.202315 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4101 01:00:09.202787 == TX Byte 1 ==
4102 01:00:09.208372 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4103 01:00:09.212057 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4104 01:00:09.212532
4105 01:00:09.212835 [DATLAT]
4106 01:00:09.214892 Freq=600, CH0 RK0
4107 01:00:09.215371
4108 01:00:09.215676 DATLAT Default: 0x9
4109 01:00:09.218754 0, 0xFFFF, sum = 0
4110 01:00:09.219162 1, 0xFFFF, sum = 0
4111 01:00:09.221650 2, 0xFFFF, sum = 0
4112 01:00:09.222027 3, 0xFFFF, sum = 0
4113 01:00:09.225301 4, 0xFFFF, sum = 0
4114 01:00:09.228305 5, 0xFFFF, sum = 0
4115 01:00:09.228664 6, 0xFFFF, sum = 0
4116 01:00:09.231921 7, 0xFFFF, sum = 0
4117 01:00:09.232375 8, 0x0, sum = 1
4118 01:00:09.232661 9, 0x0, sum = 2
4119 01:00:09.234529 10, 0x0, sum = 3
4120 01:00:09.234891 11, 0x0, sum = 4
4121 01:00:09.238532 best_step = 9
4122 01:00:09.238888
4123 01:00:09.239159 ==
4124 01:00:09.241338 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 01:00:09.244685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 01:00:09.245045 ==
4127 01:00:09.248475 RX Vref Scan: 1
4128 01:00:09.248918
4129 01:00:09.249200 RX Vref 0 -> 0, step: 1
4130 01:00:09.249459
4131 01:00:09.251119 RX Delay -195 -> 252, step: 8
4132 01:00:09.251472
4133 01:00:09.255104 Set Vref, RX VrefLevel [Byte0]: 54
4134 01:00:09.258706 [Byte1]: 52
4135 01:00:09.262612
4136 01:00:09.263056 Final RX Vref Byte 0 = 54 to rank0
4137 01:00:09.265389 Final RX Vref Byte 1 = 52 to rank0
4138 01:00:09.269202 Final RX Vref Byte 0 = 54 to rank1
4139 01:00:09.272137 Final RX Vref Byte 1 = 52 to rank1==
4140 01:00:09.275751 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 01:00:09.282638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 01:00:09.283082 ==
4143 01:00:09.283362 DQS Delay:
4144 01:00:09.283617 DQS0 = 0, DQS1 = 0
4145 01:00:09.285726 DQM Delay:
4146 01:00:09.286102 DQM0 = 42, DQM1 = 33
4147 01:00:09.289539 DQ Delay:
4148 01:00:09.292528 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4149 01:00:09.292971 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4150 01:00:09.295782 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4151 01:00:09.298816 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4152 01:00:09.302345
4153 01:00:09.302699
4154 01:00:09.309002 [DQSOSCAuto] RK0, (LSB)MR18= 0x401f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4155 01:00:09.312812 CH0 RK0: MR19=808, MR18=401F
4156 01:00:09.318734 CH0_RK0: MR19=0x808, MR18=0x401F, DQSOSC=397, MR23=63, INC=166, DEC=110
4157 01:00:09.319125
4158 01:00:09.322424 ----->DramcWriteLeveling(PI) begin...
4159 01:00:09.322797 ==
4160 01:00:09.325426 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 01:00:09.328869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 01:00:09.329310 ==
4163 01:00:09.332733 Write leveling (Byte 0): 31 => 31
4164 01:00:09.335182 Write leveling (Byte 1): 29 => 29
4165 01:00:09.338600 DramcWriteLeveling(PI) end<-----
4166 01:00:09.338954
4167 01:00:09.339225 ==
4168 01:00:09.342006 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 01:00:09.345417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 01:00:09.345780 ==
4171 01:00:09.348855 [Gating] SW mode calibration
4172 01:00:09.355689 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4173 01:00:09.362133 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4174 01:00:09.365566 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 01:00:09.368819 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 01:00:09.376181 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 01:00:09.379146 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4178 01:00:09.382230 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4179 01:00:09.388599 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 01:00:09.392045 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 01:00:09.395434 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 01:00:09.402156 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 01:00:09.405969 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 01:00:09.409026 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 01:00:09.416172 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4186 01:00:09.418708 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4187 01:00:09.422009 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 01:00:09.425601 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 01:00:09.432288 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 01:00:09.435618 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 01:00:09.439031 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 01:00:09.445438 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 01:00:09.448702 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4194 01:00:09.453014 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4195 01:00:09.459809 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 01:00:09.462761 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 01:00:09.466323 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 01:00:09.472300 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 01:00:09.475666 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 01:00:09.479314 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 01:00:09.486339 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 01:00:09.489407 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 01:00:09.492987 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 01:00:09.499287 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 01:00:09.502520 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 01:00:09.506056 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 01:00:09.509134 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 01:00:09.515774 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4209 01:00:09.519207 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4210 01:00:09.522609 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4211 01:00:09.525581 Total UI for P1: 0, mck2ui 16
4212 01:00:09.528998 best dqsien dly found for B0: ( 0, 13, 10)
4213 01:00:09.535683 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 01:00:09.538952 Total UI for P1: 0, mck2ui 16
4215 01:00:09.542654 best dqsien dly found for B1: ( 0, 13, 18)
4216 01:00:09.545818 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4217 01:00:09.548696 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4218 01:00:09.549099
4219 01:00:09.552942 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4220 01:00:09.555897 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4221 01:00:09.558869 [Gating] SW calibration Done
4222 01:00:09.559359 ==
4223 01:00:09.562313 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 01:00:09.565884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 01:00:09.566398 ==
4226 01:00:09.569230 RX Vref Scan: 0
4227 01:00:09.569718
4228 01:00:09.570211 RX Vref 0 -> 0, step: 1
4229 01:00:09.572661
4230 01:00:09.573167 RX Delay -230 -> 252, step: 16
4231 01:00:09.579075 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4232 01:00:09.582331 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4233 01:00:09.585674 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4234 01:00:09.588943 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4235 01:00:09.592466 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4236 01:00:09.598823 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
4237 01:00:09.602518 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4238 01:00:09.606085 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4239 01:00:09.609448 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4240 01:00:09.616002 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4241 01:00:09.619409 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4242 01:00:09.622290 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4243 01:00:09.625723 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4244 01:00:09.632847 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4245 01:00:09.636220 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4246 01:00:09.639303 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4247 01:00:09.639698 ==
4248 01:00:09.642381 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 01:00:09.645445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 01:00:09.645846 ==
4251 01:00:09.648906 DQS Delay:
4252 01:00:09.649301 DQS0 = 0, DQS1 = 0
4253 01:00:09.652615 DQM Delay:
4254 01:00:09.653147 DQM0 = 42, DQM1 = 35
4255 01:00:09.653464 DQ Delay:
4256 01:00:09.655553 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4257 01:00:09.658808 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4258 01:00:09.662318 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4259 01:00:09.665742 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4260 01:00:09.666182
4261 01:00:09.666488
4262 01:00:09.666764 ==
4263 01:00:09.668918 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 01:00:09.675477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 01:00:09.675839 ==
4266 01:00:09.676116
4267 01:00:09.676369
4268 01:00:09.676611 TX Vref Scan disable
4269 01:00:09.679756 == TX Byte 0 ==
4270 01:00:09.683085 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4271 01:00:09.686227 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4272 01:00:09.689755 == TX Byte 1 ==
4273 01:00:09.692902 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4274 01:00:09.696153 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4275 01:00:09.699738 ==
4276 01:00:09.703130 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 01:00:09.706256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 01:00:09.706617 ==
4279 01:00:09.706895
4280 01:00:09.707163
4281 01:00:09.709627 TX Vref Scan disable
4282 01:00:09.710016 == TX Byte 0 ==
4283 01:00:09.716661 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4284 01:00:09.719773 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4285 01:00:09.720173 == TX Byte 1 ==
4286 01:00:09.726033 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4287 01:00:09.729714 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4288 01:00:09.730217
4289 01:00:09.730501 [DATLAT]
4290 01:00:09.732690 Freq=600, CH0 RK1
4291 01:00:09.733072
4292 01:00:09.733362 DATLAT Default: 0x9
4293 01:00:09.736383 0, 0xFFFF, sum = 0
4294 01:00:09.736751 1, 0xFFFF, sum = 0
4295 01:00:09.740122 2, 0xFFFF, sum = 0
4296 01:00:09.740572 3, 0xFFFF, sum = 0
4297 01:00:09.743333 4, 0xFFFF, sum = 0
4298 01:00:09.743699 5, 0xFFFF, sum = 0
4299 01:00:09.746074 6, 0xFFFF, sum = 0
4300 01:00:09.749463 7, 0xFFFF, sum = 0
4301 01:00:09.749827 8, 0x0, sum = 1
4302 01:00:09.750149 9, 0x0, sum = 2
4303 01:00:09.753203 10, 0x0, sum = 3
4304 01:00:09.753657 11, 0x0, sum = 4
4305 01:00:09.756745 best_step = 9
4306 01:00:09.757194
4307 01:00:09.757473 ==
4308 01:00:09.760046 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 01:00:09.763392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 01:00:09.763842 ==
4311 01:00:09.766332 RX Vref Scan: 0
4312 01:00:09.766783
4313 01:00:09.767066 RX Vref 0 -> 0, step: 1
4314 01:00:09.767326
4315 01:00:09.769397 RX Delay -195 -> 252, step: 8
4316 01:00:09.777154 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4317 01:00:09.780312 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4318 01:00:09.783940 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4319 01:00:09.786756 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4320 01:00:09.793377 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4321 01:00:09.797126 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4322 01:00:09.800456 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4323 01:00:09.803464 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4324 01:00:09.806931 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4325 01:00:09.813891 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4326 01:00:09.817134 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4327 01:00:09.820418 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4328 01:00:09.823547 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4329 01:00:09.830422 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4330 01:00:09.833684 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4331 01:00:09.837129 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4332 01:00:09.837612 ==
4333 01:00:09.840353 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 01:00:09.843909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 01:00:09.844387 ==
4336 01:00:09.847380 DQS Delay:
4337 01:00:09.847854 DQS0 = 0, DQS1 = 0
4338 01:00:09.849913 DQM Delay:
4339 01:00:09.850354 DQM0 = 39, DQM1 = 32
4340 01:00:09.850662 DQ Delay:
4341 01:00:09.853244 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4342 01:00:09.856856 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4343 01:00:09.860284 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4344 01:00:09.863402 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4345 01:00:09.863798
4346 01:00:09.867222
4347 01:00:09.873430 [DQSOSCAuto] RK1, (LSB)MR18= 0x5134, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4348 01:00:09.877035 CH0 RK1: MR19=808, MR18=5134
4349 01:00:09.883446 CH0_RK1: MR19=0x808, MR18=0x5134, DQSOSC=394, MR23=63, INC=168, DEC=112
4350 01:00:09.883911 [RxdqsGatingPostProcess] freq 600
4351 01:00:09.890174 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4352 01:00:09.893760 Pre-setting of DQS Precalculation
4353 01:00:09.897067 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4354 01:00:09.900050 ==
4355 01:00:09.903348 Dram Type= 6, Freq= 0, CH_1, rank 0
4356 01:00:09.906451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 01:00:09.906845 ==
4358 01:00:09.910141 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4359 01:00:09.916921 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4360 01:00:09.920873 [CA 0] Center 35 (5~66) winsize 62
4361 01:00:09.923868 [CA 1] Center 35 (5~66) winsize 62
4362 01:00:09.926720 [CA 2] Center 33 (3~64) winsize 62
4363 01:00:09.930537 [CA 3] Center 33 (3~64) winsize 62
4364 01:00:09.933526 [CA 4] Center 33 (3~64) winsize 62
4365 01:00:09.937535 [CA 5] Center 33 (2~64) winsize 63
4366 01:00:09.938185
4367 01:00:09.940037 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4368 01:00:09.940427
4369 01:00:09.944282 [CATrainingPosCal] consider 1 rank data
4370 01:00:09.946815 u2DelayCellTimex100 = 270/100 ps
4371 01:00:09.950576 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4372 01:00:09.954060 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4373 01:00:09.960587 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4374 01:00:09.963978 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 01:00:09.966879 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4376 01:00:09.970218 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4377 01:00:09.970687
4378 01:00:09.973762 CA PerBit enable=1, Macro0, CA PI delay=33
4379 01:00:09.974282
4380 01:00:09.977334 [CBTSetCACLKResult] CA Dly = 33
4381 01:00:09.977803 CS Dly: 4 (0~35)
4382 01:00:09.980769 ==
4383 01:00:09.981243 Dram Type= 6, Freq= 0, CH_1, rank 1
4384 01:00:09.987050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 01:00:09.987504 ==
4386 01:00:09.990432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4387 01:00:09.997098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4388 01:00:10.000648 [CA 0] Center 35 (5~66) winsize 62
4389 01:00:10.003587 [CA 1] Center 35 (5~66) winsize 62
4390 01:00:10.007207 [CA 2] Center 34 (3~65) winsize 63
4391 01:00:10.010736 [CA 3] Center 33 (3~64) winsize 62
4392 01:00:10.013399 [CA 4] Center 34 (3~65) winsize 63
4393 01:00:10.016829 [CA 5] Center 33 (2~64) winsize 63
4394 01:00:10.017226
4395 01:00:10.020109 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4396 01:00:10.020505
4397 01:00:10.023686 [CATrainingPosCal] consider 2 rank data
4398 01:00:10.026979 u2DelayCellTimex100 = 270/100 ps
4399 01:00:10.030478 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 01:00:10.037490 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4401 01:00:10.040814 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4402 01:00:10.043658 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 01:00:10.047251 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 01:00:10.050157 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4405 01:00:10.050557
4406 01:00:10.053590 CA PerBit enable=1, Macro0, CA PI delay=33
4407 01:00:10.054104
4408 01:00:10.057288 [CBTSetCACLKResult] CA Dly = 33
4409 01:00:10.057757 CS Dly: 5 (0~37)
4410 01:00:10.058111
4411 01:00:10.060474 ----->DramcWriteLeveling(PI) begin...
4412 01:00:10.063437 ==
4413 01:00:10.066922 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 01:00:10.070563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 01:00:10.071041 ==
4416 01:00:10.073903 Write leveling (Byte 0): 29 => 29
4417 01:00:10.077537 Write leveling (Byte 1): 32 => 32
4418 01:00:10.080387 DramcWriteLeveling(PI) end<-----
4419 01:00:10.080861
4420 01:00:10.081171 ==
4421 01:00:10.083525 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 01:00:10.087222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 01:00:10.087700 ==
4424 01:00:10.090959 [Gating] SW mode calibration
4425 01:00:10.096873 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4426 01:00:10.100435 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4427 01:00:10.107320 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4428 01:00:10.110674 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4429 01:00:10.114277 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4430 01:00:10.120218 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4431 01:00:10.123574 0 9 16 | B1->B0 | 2d2d 2727 | 1 0 | (1 0) (1 0)
4432 01:00:10.127051 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 01:00:10.133825 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 01:00:10.137398 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4435 01:00:10.140338 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 01:00:10.146934 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 01:00:10.150074 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 01:00:10.154131 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4439 01:00:10.160718 0 10 16 | B1->B0 | 3e3e 4242 | 1 0 | (0 0) (0 0)
4440 01:00:10.163631 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 01:00:10.167219 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 01:00:10.173287 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 01:00:10.177176 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 01:00:10.180595 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 01:00:10.186950 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 01:00:10.190596 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4447 01:00:10.193594 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4448 01:00:10.200823 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 01:00:10.203451 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 01:00:10.207205 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 01:00:10.210423 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 01:00:10.216810 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 01:00:10.220366 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 01:00:10.223665 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 01:00:10.230600 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 01:00:10.234044 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 01:00:10.236977 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 01:00:10.243396 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 01:00:10.246975 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 01:00:10.250786 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 01:00:10.256742 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 01:00:10.260283 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 01:00:10.263771 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 01:00:10.267091 Total UI for P1: 0, mck2ui 16
4465 01:00:10.270742 best dqsien dly found for B0: ( 0, 13, 14)
4466 01:00:10.274182 Total UI for P1: 0, mck2ui 16
4467 01:00:10.277002 best dqsien dly found for B1: ( 0, 13, 14)
4468 01:00:10.280544 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4469 01:00:10.283672 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4470 01:00:10.284155
4471 01:00:10.290141 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4472 01:00:10.293571 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4473 01:00:10.294090 [Gating] SW calibration Done
4474 01:00:10.297128 ==
4475 01:00:10.297522 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 01:00:10.303555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 01:00:10.304019 ==
4478 01:00:10.304327 RX Vref Scan: 0
4479 01:00:10.304613
4480 01:00:10.307336 RX Vref 0 -> 0, step: 1
4481 01:00:10.307813
4482 01:00:10.310367 RX Delay -230 -> 252, step: 16
4483 01:00:10.313951 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4484 01:00:10.317132 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4485 01:00:10.323891 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4486 01:00:10.327203 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4487 01:00:10.330622 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4488 01:00:10.334135 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4489 01:00:10.337360 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4490 01:00:10.344195 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4491 01:00:10.347109 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4492 01:00:10.350644 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4493 01:00:10.353910 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4494 01:00:10.357190 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4495 01:00:10.363932 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4496 01:00:10.367015 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4497 01:00:10.370432 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4498 01:00:10.374281 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4499 01:00:10.376810 ==
4500 01:00:10.380859 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 01:00:10.383970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 01:00:10.384450 ==
4503 01:00:10.384760 DQS Delay:
4504 01:00:10.386844 DQS0 = 0, DQS1 = 0
4505 01:00:10.387237 DQM Delay:
4506 01:00:10.390096 DQM0 = 42, DQM1 = 34
4507 01:00:10.390489 DQ Delay:
4508 01:00:10.393716 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4509 01:00:10.396698 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4510 01:00:10.400501 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4511 01:00:10.403676 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4512 01:00:10.404095
4513 01:00:10.404467
4514 01:00:10.404855 ==
4515 01:00:10.406659 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 01:00:10.410179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 01:00:10.410588 ==
4518 01:00:10.410901
4519 01:00:10.411180
4520 01:00:10.413508 TX Vref Scan disable
4521 01:00:10.416750 == TX Byte 0 ==
4522 01:00:10.420517 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4523 01:00:10.424126 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4524 01:00:10.426892 == TX Byte 1 ==
4525 01:00:10.430346 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4526 01:00:10.433884 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4527 01:00:10.434389 ==
4528 01:00:10.437399 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 01:00:10.440823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 01:00:10.444008 ==
4531 01:00:10.444478
4532 01:00:10.444783
4533 01:00:10.445064 TX Vref Scan disable
4534 01:00:10.447263 == TX Byte 0 ==
4535 01:00:10.450722 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4536 01:00:10.454273 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4537 01:00:10.457582 == TX Byte 1 ==
4538 01:00:10.461080 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4539 01:00:10.464734 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4540 01:00:10.467439
4541 01:00:10.467823 [DATLAT]
4542 01:00:10.468127 Freq=600, CH1 RK0
4543 01:00:10.468502
4544 01:00:10.470919 DATLAT Default: 0x9
4545 01:00:10.471395 0, 0xFFFF, sum = 0
4546 01:00:10.474449 1, 0xFFFF, sum = 0
4547 01:00:10.475038 2, 0xFFFF, sum = 0
4548 01:00:10.477833 3, 0xFFFF, sum = 0
4549 01:00:10.478359 4, 0xFFFF, sum = 0
4550 01:00:10.480819 5, 0xFFFF, sum = 0
4551 01:00:10.481301 6, 0xFFFF, sum = 0
4552 01:00:10.484355 7, 0xFFFF, sum = 0
4553 01:00:10.484834 8, 0x0, sum = 1
4554 01:00:10.487409 9, 0x0, sum = 2
4555 01:00:10.487813 10, 0x0, sum = 3
4556 01:00:10.490588 11, 0x0, sum = 4
4557 01:00:10.490981 best_step = 9
4558 01:00:10.491282
4559 01:00:10.491558 ==
4560 01:00:10.494249 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 01:00:10.500672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 01:00:10.501064 ==
4563 01:00:10.501363 RX Vref Scan: 1
4564 01:00:10.501639
4565 01:00:10.504173 RX Vref 0 -> 0, step: 1
4566 01:00:10.504573
4567 01:00:10.507821 RX Delay -195 -> 252, step: 8
4568 01:00:10.508381
4569 01:00:10.510933 Set Vref, RX VrefLevel [Byte0]: 56
4570 01:00:10.514161 [Byte1]: 53
4571 01:00:10.514673
4572 01:00:10.517614 Final RX Vref Byte 0 = 56 to rank0
4573 01:00:10.520603 Final RX Vref Byte 1 = 53 to rank0
4574 01:00:10.523889 Final RX Vref Byte 0 = 56 to rank1
4575 01:00:10.527165 Final RX Vref Byte 1 = 53 to rank1==
4576 01:00:10.530641 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 01:00:10.534575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 01:00:10.535093 ==
4579 01:00:10.537340 DQS Delay:
4580 01:00:10.537763 DQS0 = 0, DQS1 = 0
4581 01:00:10.538242 DQM Delay:
4582 01:00:10.540660 DQM0 = 40, DQM1 = 32
4583 01:00:10.541059 DQ Delay:
4584 01:00:10.544060 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4585 01:00:10.547447 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4586 01:00:10.550754 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4587 01:00:10.554144 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4588 01:00:10.554545
4589 01:00:10.554935
4590 01:00:10.563955 [DQSOSCAuto] RK0, (LSB)MR18= 0x450a, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 396 ps
4591 01:00:10.564510 CH1 RK0: MR19=808, MR18=450A
4592 01:00:10.571159 CH1_RK0: MR19=0x808, MR18=0x450A, DQSOSC=396, MR23=63, INC=167, DEC=111
4593 01:00:10.571661
4594 01:00:10.574044 ----->DramcWriteLeveling(PI) begin...
4595 01:00:10.574443 ==
4596 01:00:10.577406 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 01:00:10.584066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 01:00:10.584544 ==
4599 01:00:10.587396 Write leveling (Byte 0): 30 => 30
4600 01:00:10.590979 Write leveling (Byte 1): 30 => 30
4601 01:00:10.591368 DramcWriteLeveling(PI) end<-----
4602 01:00:10.594406
4603 01:00:10.594797 ==
4604 01:00:10.597569 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 01:00:10.600919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 01:00:10.601397 ==
4607 01:00:10.604554 [Gating] SW mode calibration
4608 01:00:10.610972 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4609 01:00:10.614469 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4610 01:00:10.620744 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 01:00:10.624459 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 01:00:10.627247 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4613 01:00:10.634447 0 9 12 | B1->B0 | 3131 2e2e | 1 0 | (1 1) (0 0)
4614 01:00:10.637875 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4615 01:00:10.641330 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4616 01:00:10.648080 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 01:00:10.651144 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4618 01:00:10.654423 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 01:00:10.658082 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4620 01:00:10.664309 0 10 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
4621 01:00:10.667897 0 10 12 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
4622 01:00:10.671167 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 01:00:10.677710 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 01:00:10.681342 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 01:00:10.684494 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 01:00:10.691679 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 01:00:10.694673 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 01:00:10.698179 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 01:00:10.704550 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4630 01:00:10.707680 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4631 01:00:10.710893 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 01:00:10.717876 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 01:00:10.721284 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 01:00:10.724302 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 01:00:10.730994 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 01:00:10.734264 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 01:00:10.737673 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 01:00:10.740771 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 01:00:10.747491 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 01:00:10.750918 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 01:00:10.754288 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 01:00:10.761275 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 01:00:10.763990 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 01:00:10.767667 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4645 01:00:10.773932 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4646 01:00:10.777494 Total UI for P1: 0, mck2ui 16
4647 01:00:10.780570 best dqsien dly found for B0: ( 0, 13, 8)
4648 01:00:10.784291 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 01:00:10.787594 Total UI for P1: 0, mck2ui 16
4650 01:00:10.790881 best dqsien dly found for B1: ( 0, 13, 14)
4651 01:00:10.794130 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4652 01:00:10.797534 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4653 01:00:10.797614
4654 01:00:10.800858 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4655 01:00:10.803950 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4656 01:00:10.807312 [Gating] SW calibration Done
4657 01:00:10.807391 ==
4658 01:00:10.810705 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 01:00:10.814113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 01:00:10.817362 ==
4661 01:00:10.817482 RX Vref Scan: 0
4662 01:00:10.817550
4663 01:00:10.820952 RX Vref 0 -> 0, step: 1
4664 01:00:10.821095
4665 01:00:10.824198 RX Delay -230 -> 252, step: 16
4666 01:00:10.827807 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4667 01:00:10.831227 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4668 01:00:10.833880 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4669 01:00:10.837553 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4670 01:00:10.844133 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4671 01:00:10.847507 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4672 01:00:10.850855 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4673 01:00:10.854178 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4674 01:00:10.860636 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4675 01:00:10.864223 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4676 01:00:10.867441 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4677 01:00:10.871027 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4678 01:00:10.877864 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4679 01:00:10.880739 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4680 01:00:10.884438 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4681 01:00:10.888068 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4682 01:00:10.888517 ==
4683 01:00:10.891334 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 01:00:10.898103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 01:00:10.898587 ==
4686 01:00:10.898900 DQS Delay:
4687 01:00:10.899185 DQS0 = 0, DQS1 = 0
4688 01:00:10.901358 DQM Delay:
4689 01:00:10.901846 DQM0 = 37, DQM1 = 34
4690 01:00:10.904679 DQ Delay:
4691 01:00:10.907906 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4692 01:00:10.908391 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4693 01:00:10.911047 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4694 01:00:10.914445 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4695 01:00:10.917614
4696 01:00:10.918033
4697 01:00:10.918345 ==
4698 01:00:10.921509 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 01:00:10.925017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 01:00:10.925499 ==
4701 01:00:10.925807
4702 01:00:10.926141
4703 01:00:10.927620 TX Vref Scan disable
4704 01:00:10.928006 == TX Byte 0 ==
4705 01:00:10.934404 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4706 01:00:10.938220 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4707 01:00:10.938702 == TX Byte 1 ==
4708 01:00:10.944843 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4709 01:00:10.948292 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4710 01:00:10.948786 ==
4711 01:00:10.951270 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 01:00:10.954917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 01:00:10.955403 ==
4714 01:00:10.955713
4715 01:00:10.955990
4716 01:00:10.957620 TX Vref Scan disable
4717 01:00:10.961423 == TX Byte 0 ==
4718 01:00:10.964512 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4719 01:00:10.968087 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4720 01:00:10.971404 == TX Byte 1 ==
4721 01:00:10.974736 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4722 01:00:10.977910 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4723 01:00:10.978339
4724 01:00:10.980977 [DATLAT]
4725 01:00:10.981366 Freq=600, CH1 RK1
4726 01:00:10.981670
4727 01:00:10.984856 DATLAT Default: 0x9
4728 01:00:10.985247 0, 0xFFFF, sum = 0
4729 01:00:10.988145 1, 0xFFFF, sum = 0
4730 01:00:10.988632 2, 0xFFFF, sum = 0
4731 01:00:10.991450 3, 0xFFFF, sum = 0
4732 01:00:10.991849 4, 0xFFFF, sum = 0
4733 01:00:10.994568 5, 0xFFFF, sum = 0
4734 01:00:10.994967 6, 0xFFFF, sum = 0
4735 01:00:10.997914 7, 0xFFFF, sum = 0
4736 01:00:10.998449 8, 0x0, sum = 1
4737 01:00:11.001467 9, 0x0, sum = 2
4738 01:00:11.001953 10, 0x0, sum = 3
4739 01:00:11.004700 11, 0x0, sum = 4
4740 01:00:11.005182 best_step = 9
4741 01:00:11.005490
4742 01:00:11.005769 ==
4743 01:00:11.007811 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 01:00:11.011687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 01:00:11.014687 ==
4746 01:00:11.015082 RX Vref Scan: 0
4747 01:00:11.015391
4748 01:00:11.018259 RX Vref 0 -> 0, step: 1
4749 01:00:11.018653
4750 01:00:11.019082 RX Delay -195 -> 252, step: 8
4751 01:00:11.026244 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4752 01:00:11.029744 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4753 01:00:11.032865 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4754 01:00:11.036579 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4755 01:00:11.042562 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4756 01:00:11.046683 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4757 01:00:11.049696 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4758 01:00:11.052913 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4759 01:00:11.056249 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4760 01:00:11.063182 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4761 01:00:11.065891 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4762 01:00:11.069599 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4763 01:00:11.072712 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4764 01:00:11.079426 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4765 01:00:11.082736 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4766 01:00:11.086134 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4767 01:00:11.086609 ==
4768 01:00:11.089724 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 01:00:11.093068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 01:00:11.095776 ==
4771 01:00:11.096184 DQS Delay:
4772 01:00:11.096493 DQS0 = 0, DQS1 = 0
4773 01:00:11.099221 DQM Delay:
4774 01:00:11.099615 DQM0 = 37, DQM1 = 32
4775 01:00:11.102559 DQ Delay:
4776 01:00:11.102950 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =32
4777 01:00:11.106074 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4778 01:00:11.109825 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4779 01:00:11.112776 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4780 01:00:11.113176
4781 01:00:11.113481
4782 01:00:11.122959 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b4b, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4783 01:00:11.126385 CH1 RK1: MR19=808, MR18=3B4B
4784 01:00:11.130033 CH1_RK1: MR19=0x808, MR18=0x3B4B, DQSOSC=395, MR23=63, INC=168, DEC=112
4785 01:00:11.133243 [RxdqsGatingPostProcess] freq 600
4786 01:00:11.140135 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4787 01:00:11.143425 Pre-setting of DQS Precalculation
4788 01:00:11.146292 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4789 01:00:11.156682 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4790 01:00:11.163593 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4791 01:00:11.164069
4792 01:00:11.164374
4793 01:00:11.166372 [Calibration Summary] 1200 Mbps
4794 01:00:11.166770 CH 0, Rank 0
4795 01:00:11.169662 SW Impedance : PASS
4796 01:00:11.170179 DUTY Scan : NO K
4797 01:00:11.172817 ZQ Calibration : PASS
4798 01:00:11.176517 Jitter Meter : NO K
4799 01:00:11.176987 CBT Training : PASS
4800 01:00:11.180315 Write leveling : PASS
4801 01:00:11.180788 RX DQS gating : PASS
4802 01:00:11.183155 RX DQ/DQS(RDDQC) : PASS
4803 01:00:11.186848 TX DQ/DQS : PASS
4804 01:00:11.187246 RX DATLAT : PASS
4805 01:00:11.190192 RX DQ/DQS(Engine): PASS
4806 01:00:11.193363 TX OE : NO K
4807 01:00:11.193838 All Pass.
4808 01:00:11.194177
4809 01:00:11.194461 CH 0, Rank 1
4810 01:00:11.196552 SW Impedance : PASS
4811 01:00:11.199768 DUTY Scan : NO K
4812 01:00:11.200163 ZQ Calibration : PASS
4813 01:00:11.203265 Jitter Meter : NO K
4814 01:00:11.206779 CBT Training : PASS
4815 01:00:11.207249 Write leveling : PASS
4816 01:00:11.210115 RX DQS gating : PASS
4817 01:00:11.212888 RX DQ/DQS(RDDQC) : PASS
4818 01:00:11.213359 TX DQ/DQS : PASS
4819 01:00:11.216413 RX DATLAT : PASS
4820 01:00:11.219455 RX DQ/DQS(Engine): PASS
4821 01:00:11.219850 TX OE : NO K
4822 01:00:11.220161 All Pass.
4823 01:00:11.223296
4824 01:00:11.223687 CH 1, Rank 0
4825 01:00:11.226516 SW Impedance : PASS
4826 01:00:11.226912 DUTY Scan : NO K
4827 01:00:11.229620 ZQ Calibration : PASS
4828 01:00:11.230115 Jitter Meter : NO K
4829 01:00:11.233305 CBT Training : PASS
4830 01:00:11.236351 Write leveling : PASS
4831 01:00:11.236750 RX DQS gating : PASS
4832 01:00:11.239697 RX DQ/DQS(RDDQC) : PASS
4833 01:00:11.242878 TX DQ/DQS : PASS
4834 01:00:11.243278 RX DATLAT : PASS
4835 01:00:11.246377 RX DQ/DQS(Engine): PASS
4836 01:00:11.249696 TX OE : NO K
4837 01:00:11.250221 All Pass.
4838 01:00:11.250541
4839 01:00:11.250826 CH 1, Rank 1
4840 01:00:11.252960 SW Impedance : PASS
4841 01:00:11.256758 DUTY Scan : NO K
4842 01:00:11.257234 ZQ Calibration : PASS
4843 01:00:11.260055 Jitter Meter : NO K
4844 01:00:11.263566 CBT Training : PASS
4845 01:00:11.264043 Write leveling : PASS
4846 01:00:11.266234 RX DQS gating : PASS
4847 01:00:11.269924 RX DQ/DQS(RDDQC) : PASS
4848 01:00:11.270430 TX DQ/DQS : PASS
4849 01:00:11.273187 RX DATLAT : PASS
4850 01:00:11.273660 RX DQ/DQS(Engine): PASS
4851 01:00:11.276420 TX OE : NO K
4852 01:00:11.276894 All Pass.
4853 01:00:11.277202
4854 01:00:11.279205 DramC Write-DBI off
4855 01:00:11.282954 PER_BANK_REFRESH: Hybrid Mode
4856 01:00:11.283435 TX_TRACKING: ON
4857 01:00:11.292719 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4858 01:00:11.296328 [FAST_K] Save calibration result to emmc
4859 01:00:11.299257 dramc_set_vcore_voltage set vcore to 662500
4860 01:00:11.303298 Read voltage for 933, 3
4861 01:00:11.303778 Vio18 = 0
4862 01:00:11.306078 Vcore = 662500
4863 01:00:11.306473 Vdram = 0
4864 01:00:11.306783 Vddq = 0
4865 01:00:11.307064 Vmddr = 0
4866 01:00:11.313051 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4867 01:00:11.316064 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4868 01:00:11.319688 MEM_TYPE=3, freq_sel=17
4869 01:00:11.322939 sv_algorithm_assistance_LP4_1600
4870 01:00:11.326247 ============ PULL DRAM RESETB DOWN ============
4871 01:00:11.332950 ========== PULL DRAM RESETB DOWN end =========
4872 01:00:11.336299 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4873 01:00:11.339629 ===================================
4874 01:00:11.343077 LPDDR4 DRAM CONFIGURATION
4875 01:00:11.346095 ===================================
4876 01:00:11.346503 EX_ROW_EN[0] = 0x0
4877 01:00:11.349719 EX_ROW_EN[1] = 0x0
4878 01:00:11.350265 LP4Y_EN = 0x0
4879 01:00:11.353015 WORK_FSP = 0x0
4880 01:00:11.353411 WL = 0x3
4881 01:00:11.356424 RL = 0x3
4882 01:00:11.356907 BL = 0x2
4883 01:00:11.360003 RPST = 0x0
4884 01:00:11.360611 RD_PRE = 0x0
4885 01:00:11.363379 WR_PRE = 0x1
4886 01:00:11.363860 WR_PST = 0x0
4887 01:00:11.366708 DBI_WR = 0x0
4888 01:00:11.367196 DBI_RD = 0x0
4889 01:00:11.369582 OTF = 0x1
4890 01:00:11.373048 ===================================
4891 01:00:11.376841 ===================================
4892 01:00:11.377325 ANA top config
4893 01:00:11.379979 ===================================
4894 01:00:11.383734 DLL_ASYNC_EN = 0
4895 01:00:11.386692 ALL_SLAVE_EN = 1
4896 01:00:11.390113 NEW_RANK_MODE = 1
4897 01:00:11.390594 DLL_IDLE_MODE = 1
4898 01:00:11.393284 LP45_APHY_COMB_EN = 1
4899 01:00:11.396423 TX_ODT_DIS = 1
4900 01:00:11.399574 NEW_8X_MODE = 1
4901 01:00:11.403076 ===================================
4902 01:00:11.406421 ===================================
4903 01:00:11.410116 data_rate = 1866
4904 01:00:11.410595 CKR = 1
4905 01:00:11.413123 DQ_P2S_RATIO = 8
4906 01:00:11.416410 ===================================
4907 01:00:11.419362 CA_P2S_RATIO = 8
4908 01:00:11.422665 DQ_CA_OPEN = 0
4909 01:00:11.426536 DQ_SEMI_OPEN = 0
4910 01:00:11.429793 CA_SEMI_OPEN = 0
4911 01:00:11.430363 CA_FULL_RATE = 0
4912 01:00:11.432715 DQ_CKDIV4_EN = 1
4913 01:00:11.436542 CA_CKDIV4_EN = 1
4914 01:00:11.439950 CA_PREDIV_EN = 0
4915 01:00:11.443193 PH8_DLY = 0
4916 01:00:11.446087 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4917 01:00:11.446450 DQ_AAMCK_DIV = 4
4918 01:00:11.449453 CA_AAMCK_DIV = 4
4919 01:00:11.453183 CA_ADMCK_DIV = 4
4920 01:00:11.456651 DQ_TRACK_CA_EN = 0
4921 01:00:11.459467 CA_PICK = 933
4922 01:00:11.462765 CA_MCKIO = 933
4923 01:00:11.463244 MCKIO_SEMI = 0
4924 01:00:11.466348 PLL_FREQ = 3732
4925 01:00:11.469747 DQ_UI_PI_RATIO = 32
4926 01:00:11.472739 CA_UI_PI_RATIO = 0
4927 01:00:11.476038 ===================================
4928 01:00:11.479810 ===================================
4929 01:00:11.483410 memory_type:LPDDR4
4930 01:00:11.483903 GP_NUM : 10
4931 01:00:11.486443 SRAM_EN : 1
4932 01:00:11.489751 MD32_EN : 0
4933 01:00:11.492973 ===================================
4934 01:00:11.493373 [ANA_INIT] >>>>>>>>>>>>>>
4935 01:00:11.495956 <<<<<< [CONFIGURE PHASE]: ANA_TX
4936 01:00:11.499778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4937 01:00:11.503230 ===================================
4938 01:00:11.506084 data_rate = 1866,PCW = 0X8f00
4939 01:00:11.510042 ===================================
4940 01:00:11.513079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4941 01:00:11.519831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 01:00:11.523080 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 01:00:11.529393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4944 01:00:11.532985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4945 01:00:11.536538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4946 01:00:11.537020 [ANA_INIT] flow start
4947 01:00:11.539940 [ANA_INIT] PLL >>>>>>>>
4948 01:00:11.542864 [ANA_INIT] PLL <<<<<<<<
4949 01:00:11.543259 [ANA_INIT] MIDPI >>>>>>>>
4950 01:00:11.546308 [ANA_INIT] MIDPI <<<<<<<<
4951 01:00:11.550061 [ANA_INIT] DLL >>>>>>>>
4952 01:00:11.550543 [ANA_INIT] flow end
4953 01:00:11.556684 ============ LP4 DIFF to SE enter ============
4954 01:00:11.559900 ============ LP4 DIFF to SE exit ============
4955 01:00:11.563492 [ANA_INIT] <<<<<<<<<<<<<
4956 01:00:11.563973 [Flow] Enable top DCM control >>>>>
4957 01:00:11.566760 [Flow] Enable top DCM control <<<<<
4958 01:00:11.570142 Enable DLL master slave shuffle
4959 01:00:11.576410 ==============================================================
4960 01:00:11.576879 Gating Mode config
4961 01:00:11.583578 ==============================================================
4962 01:00:11.586574 Config description:
4963 01:00:11.596289 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4964 01:00:11.602939 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4965 01:00:11.606598 SELPH_MODE 0: By rank 1: By Phase
4966 01:00:11.613365 ==============================================================
4967 01:00:11.616668 GAT_TRACK_EN = 1
4968 01:00:11.617194 RX_GATING_MODE = 2
4969 01:00:11.620183 RX_GATING_TRACK_MODE = 2
4970 01:00:11.623591 SELPH_MODE = 1
4971 01:00:11.626999 PICG_EARLY_EN = 1
4972 01:00:11.629873 VALID_LAT_VALUE = 1
4973 01:00:11.636587 ==============================================================
4974 01:00:11.639686 Enter into Gating configuration >>>>
4975 01:00:11.643806 Exit from Gating configuration <<<<
4976 01:00:11.647028 Enter into DVFS_PRE_config >>>>>
4977 01:00:11.656955 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4978 01:00:11.660102 Exit from DVFS_PRE_config <<<<<
4979 01:00:11.663671 Enter into PICG configuration >>>>
4980 01:00:11.666855 Exit from PICG configuration <<<<
4981 01:00:11.669664 [RX_INPUT] configuration >>>>>
4982 01:00:11.670075 [RX_INPUT] configuration <<<<<
4983 01:00:11.676638 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4984 01:00:11.683278 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4985 01:00:11.689941 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 01:00:11.693120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 01:00:11.699524 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4988 01:00:11.707092 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4989 01:00:11.709670 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4990 01:00:11.713083 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4991 01:00:11.719871 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4992 01:00:11.723247 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4993 01:00:11.726176 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4994 01:00:11.733031 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4995 01:00:11.736548 ===================================
4996 01:00:11.737039 LPDDR4 DRAM CONFIGURATION
4997 01:00:11.739702 ===================================
4998 01:00:11.743045 EX_ROW_EN[0] = 0x0
4999 01:00:11.743443 EX_ROW_EN[1] = 0x0
5000 01:00:11.746275 LP4Y_EN = 0x0
5001 01:00:11.746669 WORK_FSP = 0x0
5002 01:00:11.749756 WL = 0x3
5003 01:00:11.752924 RL = 0x3
5004 01:00:11.753497 BL = 0x2
5005 01:00:11.756436 RPST = 0x0
5006 01:00:11.756922 RD_PRE = 0x0
5007 01:00:11.760039 WR_PRE = 0x1
5008 01:00:11.760522 WR_PST = 0x0
5009 01:00:11.762750 DBI_WR = 0x0
5010 01:00:11.763147 DBI_RD = 0x0
5011 01:00:11.766501 OTF = 0x1
5012 01:00:11.769801 ===================================
5013 01:00:11.773406 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5014 01:00:11.776196 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5015 01:00:11.779667 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 01:00:11.782713 ===================================
5017 01:00:11.786480 LPDDR4 DRAM CONFIGURATION
5018 01:00:11.789573 ===================================
5019 01:00:11.792962 EX_ROW_EN[0] = 0x10
5020 01:00:11.793355 EX_ROW_EN[1] = 0x0
5021 01:00:11.796312 LP4Y_EN = 0x0
5022 01:00:11.796707 WORK_FSP = 0x0
5023 01:00:11.799775 WL = 0x3
5024 01:00:11.800168 RL = 0x3
5025 01:00:11.802984 BL = 0x2
5026 01:00:11.803568 RPST = 0x0
5027 01:00:11.806462 RD_PRE = 0x0
5028 01:00:11.806946 WR_PRE = 0x1
5029 01:00:11.809630 WR_PST = 0x0
5030 01:00:11.812778 DBI_WR = 0x0
5031 01:00:11.813166 DBI_RD = 0x0
5032 01:00:11.816122 OTF = 0x1
5033 01:00:11.819370 ===================================
5034 01:00:11.822931 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5035 01:00:11.827893 nWR fixed to 30
5036 01:00:11.831485 [ModeRegInit_LP4] CH0 RK0
5037 01:00:11.831964 [ModeRegInit_LP4] CH0 RK1
5038 01:00:11.834856 [ModeRegInit_LP4] CH1 RK0
5039 01:00:11.838497 [ModeRegInit_LP4] CH1 RK1
5040 01:00:11.838967 match AC timing 9
5041 01:00:11.845127 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5042 01:00:11.848243 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5043 01:00:11.851679 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5044 01:00:11.858109 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5045 01:00:11.862067 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5046 01:00:11.862549 ==
5047 01:00:11.865152 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 01:00:11.868217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 01:00:11.868620 ==
5050 01:00:11.874946 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 01:00:11.881799 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5052 01:00:11.885174 [CA 0] Center 38 (8~69) winsize 62
5053 01:00:11.888306 [CA 1] Center 38 (7~69) winsize 63
5054 01:00:11.892183 [CA 2] Center 35 (5~66) winsize 62
5055 01:00:11.894842 [CA 3] Center 35 (4~66) winsize 63
5056 01:00:11.898593 [CA 4] Center 34 (4~64) winsize 61
5057 01:00:11.901848 [CA 5] Center 34 (4~64) winsize 61
5058 01:00:11.902292
5059 01:00:11.905025 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5060 01:00:11.905507
5061 01:00:11.908753 [CATrainingPosCal] consider 1 rank data
5062 01:00:11.911290 u2DelayCellTimex100 = 270/100 ps
5063 01:00:11.914970 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5064 01:00:11.918368 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5065 01:00:11.921730 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5066 01:00:11.924726 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5067 01:00:11.928362 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5068 01:00:11.931949 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5069 01:00:11.932436
5070 01:00:11.934697 CA PerBit enable=1, Macro0, CA PI delay=34
5071 01:00:11.938595
5072 01:00:11.938992 [CBTSetCACLKResult] CA Dly = 34
5073 01:00:11.942262 CS Dly: 6 (0~37)
5074 01:00:11.942747 ==
5075 01:00:11.945044 Dram Type= 6, Freq= 0, CH_0, rank 1
5076 01:00:11.948558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 01:00:11.949077 ==
5078 01:00:11.955064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 01:00:11.961513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5080 01:00:11.965340 [CA 0] Center 38 (8~69) winsize 62
5081 01:00:11.968201 [CA 1] Center 38 (7~69) winsize 63
5082 01:00:11.971594 [CA 2] Center 35 (5~66) winsize 62
5083 01:00:11.974717 [CA 3] Center 35 (5~66) winsize 62
5084 01:00:11.978328 [CA 4] Center 34 (3~65) winsize 63
5085 01:00:11.981860 [CA 5] Center 33 (3~64) winsize 62
5086 01:00:11.982405
5087 01:00:11.984939 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5088 01:00:11.985403
5089 01:00:11.988557 [CATrainingPosCal] consider 2 rank data
5090 01:00:11.992004 u2DelayCellTimex100 = 270/100 ps
5091 01:00:11.995228 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5092 01:00:11.998749 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5093 01:00:12.001653 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5094 01:00:12.005147 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5095 01:00:12.008770 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5096 01:00:12.011750 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5097 01:00:12.012192
5098 01:00:12.015161 CA PerBit enable=1, Macro0, CA PI delay=34
5099 01:00:12.015557
5100 01:00:12.018581 [CBTSetCACLKResult] CA Dly = 34
5101 01:00:12.021978 CS Dly: 7 (0~39)
5102 01:00:12.022415
5103 01:00:12.025327 ----->DramcWriteLeveling(PI) begin...
5104 01:00:12.025805 ==
5105 01:00:12.028635 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 01:00:12.031688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 01:00:12.032085 ==
5108 01:00:12.035154 Write leveling (Byte 0): 32 => 32
5109 01:00:12.038551 Write leveling (Byte 1): 25 => 25
5110 01:00:12.041823 DramcWriteLeveling(PI) end<-----
5111 01:00:12.042338
5112 01:00:12.042652 ==
5113 01:00:12.045299 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 01:00:12.048153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 01:00:12.048621 ==
5116 01:00:12.051919 [Gating] SW mode calibration
5117 01:00:12.058404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5118 01:00:12.065413 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5119 01:00:12.068466 0 14 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
5120 01:00:12.075625 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5121 01:00:12.078528 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 01:00:12.081809 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 01:00:12.085310 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 01:00:12.092097 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 01:00:12.095028 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 01:00:12.098388 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 01:00:12.105677 0 15 0 | B1->B0 | 3333 2929 | 0 0 | (0 1) (0 1)
5128 01:00:12.108907 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 01:00:12.112322 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 01:00:12.118845 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 01:00:12.121819 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 01:00:12.125783 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 01:00:12.132203 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 01:00:12.135191 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5135 01:00:12.138572 1 0 0 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (0 0)
5136 01:00:12.145810 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5137 01:00:12.149100 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 01:00:12.152312 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 01:00:12.156045 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 01:00:12.161942 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 01:00:12.165487 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 01:00:12.168861 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 01:00:12.175148 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5144 01:00:12.178977 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 01:00:12.182343 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 01:00:12.188627 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 01:00:12.191827 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 01:00:12.195238 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 01:00:12.201670 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 01:00:12.205397 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 01:00:12.208632 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 01:00:12.215766 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 01:00:12.218764 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 01:00:12.222583 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 01:00:12.228535 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 01:00:12.232264 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 01:00:12.235422 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 01:00:12.239178 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 01:00:12.245346 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5160 01:00:12.248933 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5161 01:00:12.252389 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 01:00:12.255907 Total UI for P1: 0, mck2ui 16
5163 01:00:12.259323 best dqsien dly found for B0: ( 1, 3, 2)
5164 01:00:12.262703 Total UI for P1: 0, mck2ui 16
5165 01:00:12.265940 best dqsien dly found for B1: ( 1, 3, 2)
5166 01:00:12.268828 best DQS0 dly(MCK, UI, PI) = (1, 3, 2)
5167 01:00:12.272081 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5168 01:00:12.272572
5169 01:00:12.278955 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 2)
5170 01:00:12.282227 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5171 01:00:12.282627 [Gating] SW calibration Done
5172 01:00:12.285711 ==
5173 01:00:12.288492 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 01:00:12.292361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 01:00:12.292917 ==
5176 01:00:12.293233 RX Vref Scan: 0
5177 01:00:12.293521
5178 01:00:12.295353 RX Vref 0 -> 0, step: 1
5179 01:00:12.295746
5180 01:00:12.298942 RX Delay -80 -> 252, step: 8
5181 01:00:12.302038 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5182 01:00:12.305368 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5183 01:00:12.308520 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5184 01:00:12.315146 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5185 01:00:12.318474 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5186 01:00:12.322098 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5187 01:00:12.325344 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5188 01:00:12.328845 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5189 01:00:12.331732 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5190 01:00:12.338454 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5191 01:00:12.342355 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5192 01:00:12.345719 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5193 01:00:12.348654 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5194 01:00:12.351691 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5195 01:00:12.358705 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5196 01:00:12.362096 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5197 01:00:12.362569 ==
5198 01:00:12.365457 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 01:00:12.368950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 01:00:12.369425 ==
5201 01:00:12.369734 DQS Delay:
5202 01:00:12.372380 DQS0 = 0, DQS1 = 0
5203 01:00:12.372863 DQM Delay:
5204 01:00:12.375341 DQM0 = 98, DQM1 = 87
5205 01:00:12.375736 DQ Delay:
5206 01:00:12.378669 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5207 01:00:12.381876 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =103
5208 01:00:12.385712 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =79
5209 01:00:12.388360 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5210 01:00:12.388753
5211 01:00:12.389060
5212 01:00:12.389347 ==
5213 01:00:12.391765 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 01:00:12.395553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 01:00:12.395952 ==
5216 01:00:12.398697
5217 01:00:12.399089
5218 01:00:12.399394 TX Vref Scan disable
5219 01:00:12.401940 == TX Byte 0 ==
5220 01:00:12.405568 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5221 01:00:12.408564 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5222 01:00:12.412108 == TX Byte 1 ==
5223 01:00:12.415835 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5224 01:00:12.418754 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5225 01:00:12.419233 ==
5226 01:00:12.421703 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 01:00:12.428651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 01:00:12.429134 ==
5229 01:00:12.429446
5230 01:00:12.429730
5231 01:00:12.430046 TX Vref Scan disable
5232 01:00:12.432773 == TX Byte 0 ==
5233 01:00:12.436077 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5234 01:00:12.439570 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5235 01:00:12.443091 == TX Byte 1 ==
5236 01:00:12.446843 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5237 01:00:12.450180 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5238 01:00:12.453380
5239 01:00:12.453851 [DATLAT]
5240 01:00:12.454201 Freq=933, CH0 RK0
5241 01:00:12.454493
5242 01:00:12.456863 DATLAT Default: 0xd
5243 01:00:12.457458 0, 0xFFFF, sum = 0
5244 01:00:12.459986 1, 0xFFFF, sum = 0
5245 01:00:12.460467 2, 0xFFFF, sum = 0
5246 01:00:12.463411 3, 0xFFFF, sum = 0
5247 01:00:12.463892 4, 0xFFFF, sum = 0
5248 01:00:12.466322 5, 0xFFFF, sum = 0
5249 01:00:12.469747 6, 0xFFFF, sum = 0
5250 01:00:12.470260 7, 0xFFFF, sum = 0
5251 01:00:12.473297 8, 0xFFFF, sum = 0
5252 01:00:12.473778 9, 0xFFFF, sum = 0
5253 01:00:12.476696 10, 0x0, sum = 1
5254 01:00:12.477176 11, 0x0, sum = 2
5255 01:00:12.477492 12, 0x0, sum = 3
5256 01:00:12.479745 13, 0x0, sum = 4
5257 01:00:12.480144 best_step = 11
5258 01:00:12.480447
5259 01:00:12.483080 ==
5260 01:00:12.483471 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 01:00:12.489639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 01:00:12.490074 ==
5263 01:00:12.490390 RX Vref Scan: 1
5264 01:00:12.490674
5265 01:00:12.493104 RX Vref 0 -> 0, step: 1
5266 01:00:12.493491
5267 01:00:12.496231 RX Delay -61 -> 252, step: 4
5268 01:00:12.496621
5269 01:00:12.499432 Set Vref, RX VrefLevel [Byte0]: 54
5270 01:00:12.502806 [Byte1]: 52
5271 01:00:12.503121
5272 01:00:12.506044 Final RX Vref Byte 0 = 54 to rank0
5273 01:00:12.509516 Final RX Vref Byte 1 = 52 to rank0
5274 01:00:12.512940 Final RX Vref Byte 0 = 54 to rank1
5275 01:00:12.516238 Final RX Vref Byte 1 = 52 to rank1==
5276 01:00:12.519587 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 01:00:12.523157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 01:00:12.523550 ==
5279 01:00:12.526563 DQS Delay:
5280 01:00:12.527029 DQS0 = 0, DQS1 = 0
5281 01:00:12.530075 DQM Delay:
5282 01:00:12.530741 DQM0 = 97, DQM1 = 87
5283 01:00:12.531076 DQ Delay:
5284 01:00:12.533224 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5285 01:00:12.536711 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =104
5286 01:00:12.539983 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =80
5287 01:00:12.543066 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =96
5288 01:00:12.543467
5289 01:00:12.543864
5290 01:00:12.553656 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5291 01:00:12.556982 CH0 RK0: MR19=504, MR18=12FD
5292 01:00:12.560084 CH0_RK0: MR19=0x504, MR18=0x12FD, DQSOSC=416, MR23=63, INC=62, DEC=41
5293 01:00:12.560559
5294 01:00:12.563684 ----->DramcWriteLeveling(PI) begin...
5295 01:00:12.566858 ==
5296 01:00:12.567338 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 01:00:12.574012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 01:00:12.574502 ==
5299 01:00:12.576557 Write leveling (Byte 0): 30 => 30
5300 01:00:12.580343 Write leveling (Byte 1): 29 => 29
5301 01:00:12.580822 DramcWriteLeveling(PI) end<-----
5302 01:00:12.583701
5303 01:00:12.584164 ==
5304 01:00:12.586891 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 01:00:12.590138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 01:00:12.590617 ==
5307 01:00:12.593611 [Gating] SW mode calibration
5308 01:00:12.600244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5309 01:00:12.603323 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5310 01:00:12.610297 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
5311 01:00:12.613686 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5312 01:00:12.616790 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 01:00:12.623377 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 01:00:12.626812 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 01:00:12.630106 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 01:00:12.636970 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 01:00:12.640322 0 14 28 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
5318 01:00:12.644157 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5319 01:00:12.650329 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 01:00:12.653816 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 01:00:12.657146 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 01:00:12.663991 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 01:00:12.667413 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 01:00:12.670321 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 01:00:12.673884 0 15 28 | B1->B0 | 2626 3a3a | 0 0 | (0 0) (0 0)
5326 01:00:12.680383 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5327 01:00:12.683780 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 01:00:12.687009 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 01:00:12.694184 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 01:00:12.697188 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 01:00:12.700285 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 01:00:12.706550 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5333 01:00:12.710134 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5334 01:00:12.713590 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5335 01:00:12.720375 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5336 01:00:12.723748 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 01:00:12.726724 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 01:00:12.733239 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 01:00:12.736873 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 01:00:12.740195 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 01:00:12.747350 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 01:00:12.750338 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 01:00:12.753790 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 01:00:12.760464 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 01:00:12.763999 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 01:00:12.766992 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 01:00:12.770629 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 01:00:12.776990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5349 01:00:12.780210 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5350 01:00:12.783743 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5351 01:00:12.786886 Total UI for P1: 0, mck2ui 16
5352 01:00:12.790500 best dqsien dly found for B0: ( 1, 2, 26)
5353 01:00:12.796839 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 01:00:12.797361 Total UI for P1: 0, mck2ui 16
5355 01:00:12.803354 best dqsien dly found for B1: ( 1, 3, 0)
5356 01:00:12.807477 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5357 01:00:12.810089 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5358 01:00:12.810484
5359 01:00:12.813684 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5360 01:00:12.816938 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5361 01:00:12.820367 [Gating] SW calibration Done
5362 01:00:12.820759 ==
5363 01:00:12.823754 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 01:00:12.827603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 01:00:12.828073 ==
5366 01:00:12.830056 RX Vref Scan: 0
5367 01:00:12.830601
5368 01:00:12.831057 RX Vref 0 -> 0, step: 1
5369 01:00:12.831362
5370 01:00:12.834117 RX Delay -80 -> 252, step: 8
5371 01:00:12.837235 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5372 01:00:12.840431 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5373 01:00:12.847440 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5374 01:00:12.850588 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5375 01:00:12.853645 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5376 01:00:12.857080 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5377 01:00:12.860363 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5378 01:00:12.863621 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5379 01:00:12.866773 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5380 01:00:12.873756 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5381 01:00:12.877240 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5382 01:00:12.880741 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5383 01:00:12.884052 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5384 01:00:12.886963 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5385 01:00:12.893966 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5386 01:00:12.896822 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5387 01:00:12.897216 ==
5388 01:00:12.900351 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 01:00:12.903764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 01:00:12.904162 ==
5391 01:00:12.904475 DQS Delay:
5392 01:00:12.907467 DQS0 = 0, DQS1 = 0
5393 01:00:12.908192 DQM Delay:
5394 01:00:12.910544 DQM0 = 97, DQM1 = 88
5395 01:00:12.910941 DQ Delay:
5396 01:00:12.913548 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5397 01:00:12.917267 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5398 01:00:12.920079 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5399 01:00:12.923557 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5400 01:00:12.923966
5401 01:00:12.924552
5402 01:00:12.925070 ==
5403 01:00:12.926804 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 01:00:12.930357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 01:00:12.933737 ==
5406 01:00:12.934289
5407 01:00:12.934606
5408 01:00:12.934941 TX Vref Scan disable
5409 01:00:12.937062 == TX Byte 0 ==
5410 01:00:12.940222 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5411 01:00:12.943842 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5412 01:00:12.946964 == TX Byte 1 ==
5413 01:00:12.950414 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5414 01:00:12.953376 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5415 01:00:12.956725 ==
5416 01:00:12.957119 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 01:00:12.963842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 01:00:12.964321 ==
5419 01:00:12.964634
5420 01:00:12.964916
5421 01:00:12.966672 TX Vref Scan disable
5422 01:00:12.967119 == TX Byte 0 ==
5423 01:00:12.973334 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5424 01:00:12.976754 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5425 01:00:12.977269 == TX Byte 1 ==
5426 01:00:12.983435 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5427 01:00:12.986807 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5428 01:00:12.987207
5429 01:00:12.987515 [DATLAT]
5430 01:00:12.989831 Freq=933, CH0 RK1
5431 01:00:12.990351
5432 01:00:12.990670 DATLAT Default: 0xb
5433 01:00:12.993561 0, 0xFFFF, sum = 0
5434 01:00:12.994198 1, 0xFFFF, sum = 0
5435 01:00:12.997092 2, 0xFFFF, sum = 0
5436 01:00:12.997490 3, 0xFFFF, sum = 0
5437 01:00:12.999848 4, 0xFFFF, sum = 0
5438 01:00:13.000249 5, 0xFFFF, sum = 0
5439 01:00:13.003192 6, 0xFFFF, sum = 0
5440 01:00:13.003880 7, 0xFFFF, sum = 0
5441 01:00:13.006628 8, 0xFFFF, sum = 0
5442 01:00:13.007026 9, 0xFFFF, sum = 0
5443 01:00:13.010151 10, 0x0, sum = 1
5444 01:00:13.010927 11, 0x0, sum = 2
5445 01:00:13.013517 12, 0x0, sum = 3
5446 01:00:13.014086 13, 0x0, sum = 4
5447 01:00:13.017425 best_step = 11
5448 01:00:13.017894
5449 01:00:13.018264 ==
5450 01:00:13.019938 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 01:00:13.024080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 01:00:13.024481 ==
5453 01:00:13.026763 RX Vref Scan: 0
5454 01:00:13.027158
5455 01:00:13.027463 RX Vref 0 -> 0, step: 1
5456 01:00:13.027747
5457 01:00:13.030221 RX Delay -61 -> 252, step: 4
5458 01:00:13.036871 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5459 01:00:13.040533 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5460 01:00:13.043766 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5461 01:00:13.047624 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5462 01:00:13.050086 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5463 01:00:13.053808 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5464 01:00:13.060596 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5465 01:00:13.063771 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5466 01:00:13.067075 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5467 01:00:13.070443 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5468 01:00:13.073509 iDelay=199, Bit 10, Center 90 (3 ~ 178) 176
5469 01:00:13.076909 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5470 01:00:13.083879 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5471 01:00:13.086801 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5472 01:00:13.090476 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5473 01:00:13.094096 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5474 01:00:13.094565 ==
5475 01:00:13.097044 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 01:00:13.100506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 01:00:13.103775 ==
5478 01:00:13.104172 DQS Delay:
5479 01:00:13.104480 DQS0 = 0, DQS1 = 0
5480 01:00:13.107272 DQM Delay:
5481 01:00:13.107665 DQM0 = 95, DQM1 = 87
5482 01:00:13.109970 DQ Delay:
5483 01:00:13.110401 DQ0 =96, DQ1 =96, DQ2 =94, DQ3 =94
5484 01:00:13.113655 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5485 01:00:13.116943 DQ8 =82, DQ9 =78, DQ10 =90, DQ11 =78
5486 01:00:13.120462 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5487 01:00:13.123655
5488 01:00:13.124144
5489 01:00:13.130379 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5490 01:00:13.133383 CH0 RK1: MR19=505, MR18=1B09
5491 01:00:13.140225 CH0_RK1: MR19=0x505, MR18=0x1B09, DQSOSC=413, MR23=63, INC=63, DEC=42
5492 01:00:13.143759 [RxdqsGatingPostProcess] freq 933
5493 01:00:13.146940 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5494 01:00:13.150472 best DQS0 dly(2T, 0.5T) = (0, 11)
5495 01:00:13.153364 best DQS1 dly(2T, 0.5T) = (0, 11)
5496 01:00:13.157117 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5497 01:00:13.160476 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5498 01:00:13.163182 best DQS0 dly(2T, 0.5T) = (0, 10)
5499 01:00:13.166885 best DQS1 dly(2T, 0.5T) = (0, 11)
5500 01:00:13.170486 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5501 01:00:13.173181 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5502 01:00:13.177015 Pre-setting of DQS Precalculation
5503 01:00:13.180315 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5504 01:00:13.180797 ==
5505 01:00:13.183602 Dram Type= 6, Freq= 0, CH_1, rank 0
5506 01:00:13.187152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 01:00:13.187553 ==
5508 01:00:13.193747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5509 01:00:13.200590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5510 01:00:13.203538 [CA 0] Center 36 (6~67) winsize 62
5511 01:00:13.207070 [CA 1] Center 36 (6~67) winsize 62
5512 01:00:13.210107 [CA 2] Center 34 (4~64) winsize 61
5513 01:00:13.214463 [CA 3] Center 33 (3~64) winsize 62
5514 01:00:13.217117 [CA 4] Center 34 (4~65) winsize 62
5515 01:00:13.220319 [CA 5] Center 33 (3~64) winsize 62
5516 01:00:13.220715
5517 01:00:13.223586 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5518 01:00:13.223979
5519 01:00:13.227254 [CATrainingPosCal] consider 1 rank data
5520 01:00:13.230841 u2DelayCellTimex100 = 270/100 ps
5521 01:00:13.234169 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5522 01:00:13.237383 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5523 01:00:13.240500 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5524 01:00:13.243771 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5525 01:00:13.247021 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5526 01:00:13.250936 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5527 01:00:13.251410
5528 01:00:13.257453 CA PerBit enable=1, Macro0, CA PI delay=33
5529 01:00:13.257848
5530 01:00:13.260668 [CBTSetCACLKResult] CA Dly = 33
5531 01:00:13.261139 CS Dly: 5 (0~36)
5532 01:00:13.261449 ==
5533 01:00:13.263866 Dram Type= 6, Freq= 0, CH_1, rank 1
5534 01:00:13.267249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 01:00:13.267725 ==
5536 01:00:13.274030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5537 01:00:13.280953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5538 01:00:13.283947 [CA 0] Center 36 (6~67) winsize 62
5539 01:00:13.287186 [CA 1] Center 36 (6~67) winsize 62
5540 01:00:13.290298 [CA 2] Center 33 (3~64) winsize 62
5541 01:00:13.293970 [CA 3] Center 33 (3~64) winsize 62
5542 01:00:13.297296 [CA 4] Center 34 (4~65) winsize 62
5543 01:00:13.300898 [CA 5] Center 33 (2~64) winsize 63
5544 01:00:13.301371
5545 01:00:13.303934 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5546 01:00:13.304331
5547 01:00:13.307377 [CATrainingPosCal] consider 2 rank data
5548 01:00:13.310562 u2DelayCellTimex100 = 270/100 ps
5549 01:00:13.314054 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5550 01:00:13.317475 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5551 01:00:13.320601 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5552 01:00:13.324134 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 01:00:13.327203 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5554 01:00:13.330929 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5555 01:00:13.331403
5556 01:00:13.337088 CA PerBit enable=1, Macro0, CA PI delay=33
5557 01:00:13.337562
5558 01:00:13.340678 [CBTSetCACLKResult] CA Dly = 33
5559 01:00:13.341157 CS Dly: 6 (0~38)
5560 01:00:13.341470
5561 01:00:13.344179 ----->DramcWriteLeveling(PI) begin...
5562 01:00:13.344666 ==
5563 01:00:13.348069 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 01:00:13.350395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 01:00:13.350794 ==
5566 01:00:13.354246 Write leveling (Byte 0): 25 => 25
5567 01:00:13.357376 Write leveling (Byte 1): 26 => 26
5568 01:00:13.360651 DramcWriteLeveling(PI) end<-----
5569 01:00:13.361133
5570 01:00:13.361442 ==
5571 01:00:13.364176 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 01:00:13.370803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 01:00:13.371282 ==
5574 01:00:13.371594 [Gating] SW mode calibration
5575 01:00:13.380403 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5576 01:00:13.383841 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5577 01:00:13.386786 0 14 0 | B1->B0 | 2e2e 3232 | 1 0 | (1 1) (0 0)
5578 01:00:13.393821 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 01:00:13.396963 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 01:00:13.400798 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 01:00:13.406855 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 01:00:13.410685 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 01:00:13.413793 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5584 01:00:13.420568 0 14 28 | B1->B0 | 3030 3232 | 1 1 | (1 0) (1 0)
5585 01:00:13.423374 0 15 0 | B1->B0 | 2727 2727 | 0 0 | (0 0) (1 1)
5586 01:00:13.427289 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 01:00:13.433644 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 01:00:13.436624 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 01:00:13.440368 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 01:00:13.447242 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 01:00:13.450895 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 01:00:13.453789 0 15 28 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 0)
5593 01:00:13.460224 1 0 0 | B1->B0 | 4444 3e3e | 0 0 | (0 0) (0 0)
5594 01:00:13.463557 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 01:00:13.466665 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 01:00:13.473537 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 01:00:13.477417 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 01:00:13.480352 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 01:00:13.487054 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 01:00:13.490494 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5601 01:00:13.493514 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5602 01:00:13.497004 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 01:00:13.503560 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 01:00:13.506888 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 01:00:13.510469 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 01:00:13.517267 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 01:00:13.520475 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 01:00:13.523309 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 01:00:13.530758 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 01:00:13.533966 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 01:00:13.537246 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 01:00:13.543406 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 01:00:13.546701 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 01:00:13.550591 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 01:00:13.556871 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 01:00:13.560654 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5617 01:00:13.563848 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 01:00:13.566377 Total UI for P1: 0, mck2ui 16
5619 01:00:13.570462 best dqsien dly found for B0: ( 1, 2, 28)
5620 01:00:13.573881 Total UI for P1: 0, mck2ui 16
5621 01:00:13.576415 best dqsien dly found for B1: ( 1, 2, 28)
5622 01:00:13.580609 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5623 01:00:13.583184 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5624 01:00:13.583622
5625 01:00:13.586840 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5626 01:00:13.593941 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5627 01:00:13.594493 [Gating] SW calibration Done
5628 01:00:13.594836 ==
5629 01:00:13.596682 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 01:00:13.603504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 01:00:13.604031 ==
5632 01:00:13.604376 RX Vref Scan: 0
5633 01:00:13.604691
5634 01:00:13.606503 RX Vref 0 -> 0, step: 1
5635 01:00:13.606940
5636 01:00:13.609923 RX Delay -80 -> 252, step: 8
5637 01:00:13.613585 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5638 01:00:13.616770 iDelay=200, Bit 1, Center 91 (0 ~ 183) 184
5639 01:00:13.620079 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5640 01:00:13.623450 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5641 01:00:13.630199 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5642 01:00:13.633527 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5643 01:00:13.637093 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5644 01:00:13.640343 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5645 01:00:13.643860 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5646 01:00:13.647101 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5647 01:00:13.653663 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5648 01:00:13.657091 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5649 01:00:13.660219 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5650 01:00:13.663368 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5651 01:00:13.667039 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5652 01:00:13.670423 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5653 01:00:13.670933 ==
5654 01:00:13.673836 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 01:00:13.680589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 01:00:13.681104 ==
5657 01:00:13.681444 DQS Delay:
5658 01:00:13.683258 DQS0 = 0, DQS1 = 0
5659 01:00:13.683693 DQM Delay:
5660 01:00:13.684030 DQM0 = 95, DQM1 = 89
5661 01:00:13.686953 DQ Delay:
5662 01:00:13.690467 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =95
5663 01:00:13.693964 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5664 01:00:13.696836 DQ8 =79, DQ9 =75, DQ10 =95, DQ11 =83
5665 01:00:13.700450 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5666 01:00:13.700961
5667 01:00:13.701300
5668 01:00:13.701608 ==
5669 01:00:13.703957 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 01:00:13.706732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 01:00:13.707259 ==
5672 01:00:13.707598
5673 01:00:13.707908
5674 01:00:13.710298 TX Vref Scan disable
5675 01:00:13.713247 == TX Byte 0 ==
5676 01:00:13.717052 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5677 01:00:13.720848 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5678 01:00:13.723219 == TX Byte 1 ==
5679 01:00:13.727072 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5680 01:00:13.730292 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5681 01:00:13.730697 ==
5682 01:00:13.733617 Dram Type= 6, Freq= 0, CH_1, rank 0
5683 01:00:13.737008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5684 01:00:13.737412 ==
5685 01:00:13.737809
5686 01:00:13.740298
5687 01:00:13.740696 TX Vref Scan disable
5688 01:00:13.743224 == TX Byte 0 ==
5689 01:00:13.746675 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5690 01:00:13.750223 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5691 01:00:13.753244 == TX Byte 1 ==
5692 01:00:13.757185 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5693 01:00:13.760042 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5694 01:00:13.764112
5695 01:00:13.764597 [DATLAT]
5696 01:00:13.764999 Freq=933, CH1 RK0
5697 01:00:13.765375
5698 01:00:13.767245 DATLAT Default: 0xd
5699 01:00:13.767727 0, 0xFFFF, sum = 0
5700 01:00:13.770259 1, 0xFFFF, sum = 0
5701 01:00:13.770670 2, 0xFFFF, sum = 0
5702 01:00:13.773406 3, 0xFFFF, sum = 0
5703 01:00:13.773893 4, 0xFFFF, sum = 0
5704 01:00:13.776930 5, 0xFFFF, sum = 0
5705 01:00:13.779794 6, 0xFFFF, sum = 0
5706 01:00:13.780197 7, 0xFFFF, sum = 0
5707 01:00:13.783185 8, 0xFFFF, sum = 0
5708 01:00:13.783587 9, 0xFFFF, sum = 0
5709 01:00:13.786721 10, 0x0, sum = 1
5710 01:00:13.787203 11, 0x0, sum = 2
5711 01:00:13.787520 12, 0x0, sum = 3
5712 01:00:13.790051 13, 0x0, sum = 4
5713 01:00:13.790550 best_step = 11
5714 01:00:13.790861
5715 01:00:13.791146 ==
5716 01:00:13.793434 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 01:00:13.800301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 01:00:13.800905 ==
5719 01:00:13.801225 RX Vref Scan: 1
5720 01:00:13.801514
5721 01:00:13.803575 RX Vref 0 -> 0, step: 1
5722 01:00:13.803969
5723 01:00:13.806929 RX Delay -69 -> 252, step: 4
5724 01:00:13.807327
5725 01:00:13.809866 Set Vref, RX VrefLevel [Byte0]: 56
5726 01:00:13.813293 [Byte1]: 53
5727 01:00:13.813691
5728 01:00:13.816547 Final RX Vref Byte 0 = 56 to rank0
5729 01:00:13.819932 Final RX Vref Byte 1 = 53 to rank0
5730 01:00:13.823302 Final RX Vref Byte 0 = 56 to rank1
5731 01:00:13.826686 Final RX Vref Byte 1 = 53 to rank1==
5732 01:00:13.830192 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 01:00:13.833523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 01:00:13.833926 ==
5735 01:00:13.837134 DQS Delay:
5736 01:00:13.837739 DQS0 = 0, DQS1 = 0
5737 01:00:13.840287 DQM Delay:
5738 01:00:13.840681 DQM0 = 97, DQM1 = 89
5739 01:00:13.840988 DQ Delay:
5740 01:00:13.843027 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5741 01:00:13.846955 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5742 01:00:13.850051 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =86
5743 01:00:13.853221 DQ12 =98, DQ13 =96, DQ14 =94, DQ15 =94
5744 01:00:13.853698
5745 01:00:13.854034
5746 01:00:13.863540 [DQSOSCAuto] RK0, (LSB)MR18= 0x16f2, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5747 01:00:13.866907 CH1 RK0: MR19=504, MR18=16F2
5748 01:00:13.870584 CH1_RK0: MR19=0x504, MR18=0x16F2, DQSOSC=414, MR23=63, INC=63, DEC=42
5749 01:00:13.873928
5750 01:00:13.874430 ----->DramcWriteLeveling(PI) begin...
5751 01:00:13.876917 ==
5752 01:00:13.880206 Dram Type= 6, Freq= 0, CH_1, rank 1
5753 01:00:13.883350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 01:00:13.883865 ==
5755 01:00:13.887008 Write leveling (Byte 0): 27 => 27
5756 01:00:13.890567 Write leveling (Byte 1): 27 => 27
5757 01:00:13.893395 DramcWriteLeveling(PI) end<-----
5758 01:00:13.893837
5759 01:00:13.894210 ==
5760 01:00:13.896685 Dram Type= 6, Freq= 0, CH_1, rank 1
5761 01:00:13.899855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 01:00:13.900277 ==
5763 01:00:13.903224 [Gating] SW mode calibration
5764 01:00:13.909661 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5765 01:00:13.916797 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5766 01:00:13.919887 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 01:00:13.923320 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 01:00:13.930123 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 01:00:13.933362 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 01:00:13.937266 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 01:00:13.940107 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5772 01:00:13.946580 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5773 01:00:13.949812 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
5774 01:00:13.953363 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5775 01:00:13.959857 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 01:00:13.963456 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 01:00:13.966809 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 01:00:13.973396 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 01:00:13.976897 0 15 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5780 01:00:13.980159 0 15 24 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
5781 01:00:13.987224 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5782 01:00:13.989920 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 01:00:13.993346 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 01:00:14.000494 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 01:00:14.003602 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 01:00:14.007117 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 01:00:14.013295 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 01:00:14.016735 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5789 01:00:14.020148 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 01:00:14.023297 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5791 01:00:14.030161 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 01:00:14.033641 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 01:00:14.036944 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 01:00:14.043575 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 01:00:14.046709 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 01:00:14.050384 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 01:00:14.057422 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 01:00:14.060812 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 01:00:14.064121 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 01:00:14.071008 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 01:00:14.073866 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 01:00:14.077156 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 01:00:14.084170 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 01:00:14.087054 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5805 01:00:14.090052 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5806 01:00:14.093493 Total UI for P1: 0, mck2ui 16
5807 01:00:14.097304 best dqsien dly found for B0: ( 1, 2, 24)
5808 01:00:14.100710 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 01:00:14.103388 Total UI for P1: 0, mck2ui 16
5810 01:00:14.106651 best dqsien dly found for B1: ( 1, 2, 26)
5811 01:00:14.109891 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5812 01:00:14.116974 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5813 01:00:14.117508
5814 01:00:14.120148 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5815 01:00:14.123674 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5816 01:00:14.127030 [Gating] SW calibration Done
5817 01:00:14.127426 ==
5818 01:00:14.130285 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 01:00:14.134048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 01:00:14.134527 ==
5821 01:00:14.134838 RX Vref Scan: 0
5822 01:00:14.136848
5823 01:00:14.137240 RX Vref 0 -> 0, step: 1
5824 01:00:14.137548
5825 01:00:14.140467 RX Delay -80 -> 252, step: 8
5826 01:00:14.144157 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5827 01:00:14.147106 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5828 01:00:14.153715 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5829 01:00:14.156991 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5830 01:00:14.160119 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5831 01:00:14.163878 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5832 01:00:14.166685 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5833 01:00:14.170420 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5834 01:00:14.173805 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5835 01:00:14.180487 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5836 01:00:14.183668 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5837 01:00:14.187663 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5838 01:00:14.190486 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5839 01:00:14.194031 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5840 01:00:14.200218 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5841 01:00:14.203695 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5842 01:00:14.204117 ==
5843 01:00:14.206895 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 01:00:14.210306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 01:00:14.210705 ==
5846 01:00:14.211009 DQS Delay:
5847 01:00:14.213791 DQS0 = 0, DQS1 = 0
5848 01:00:14.214218 DQM Delay:
5849 01:00:14.217098 DQM0 = 94, DQM1 = 89
5850 01:00:14.217492 DQ Delay:
5851 01:00:14.220485 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5852 01:00:14.223785 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5853 01:00:14.227093 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5854 01:00:14.230298 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5855 01:00:14.230688
5856 01:00:14.230992
5857 01:00:14.231273 ==
5858 01:00:14.233978 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 01:00:14.237506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 01:00:14.240259 ==
5861 01:00:14.240737
5862 01:00:14.241048
5863 01:00:14.241331 TX Vref Scan disable
5864 01:00:14.243871 == TX Byte 0 ==
5865 01:00:14.246958 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5866 01:00:14.250250 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5867 01:00:14.253294 == TX Byte 1 ==
5868 01:00:14.256792 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5869 01:00:14.261022 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5870 01:00:14.261497 ==
5871 01:00:14.263599 Dram Type= 6, Freq= 0, CH_1, rank 1
5872 01:00:14.270557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5873 01:00:14.271020 ==
5874 01:00:14.271330
5875 01:00:14.271611
5876 01:00:14.271881 TX Vref Scan disable
5877 01:00:14.274815 == TX Byte 0 ==
5878 01:00:14.277912 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5879 01:00:14.284552 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5880 01:00:14.284948 == TX Byte 1 ==
5881 01:00:14.288059 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5882 01:00:14.294461 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5883 01:00:14.294945
5884 01:00:14.295371 [DATLAT]
5885 01:00:14.295703 Freq=933, CH1 RK1
5886 01:00:14.296123
5887 01:00:14.297718 DATLAT Default: 0xb
5888 01:00:14.298151 0, 0xFFFF, sum = 0
5889 01:00:14.301063 1, 0xFFFF, sum = 0
5890 01:00:14.301466 2, 0xFFFF, sum = 0
5891 01:00:14.304394 3, 0xFFFF, sum = 0
5892 01:00:14.308020 4, 0xFFFF, sum = 0
5893 01:00:14.308418 5, 0xFFFF, sum = 0
5894 01:00:14.310888 6, 0xFFFF, sum = 0
5895 01:00:14.311294 7, 0xFFFF, sum = 0
5896 01:00:14.314471 8, 0xFFFF, sum = 0
5897 01:00:14.314871 9, 0xFFFF, sum = 0
5898 01:00:14.317926 10, 0x0, sum = 1
5899 01:00:14.318367 11, 0x0, sum = 2
5900 01:00:14.321345 12, 0x0, sum = 3
5901 01:00:14.321744 13, 0x0, sum = 4
5902 01:00:14.322100 best_step = 11
5903 01:00:14.322405
5904 01:00:14.324215 ==
5905 01:00:14.324609 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 01:00:14.330927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 01:00:14.331324 ==
5908 01:00:14.331630 RX Vref Scan: 0
5909 01:00:14.331919
5910 01:00:14.334320 RX Vref 0 -> 0, step: 1
5911 01:00:14.334650
5912 01:00:14.337809 RX Delay -61 -> 252, step: 4
5913 01:00:14.341209 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5914 01:00:14.347596 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5915 01:00:14.351122 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5916 01:00:14.354506 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5917 01:00:14.357934 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5918 01:00:14.361044 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5919 01:00:14.364648 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5920 01:00:14.367680 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5921 01:00:14.374609 iDelay=199, Bit 8, Center 82 (-9 ~ 174) 184
5922 01:00:14.377934 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5923 01:00:14.381262 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5924 01:00:14.384496 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5925 01:00:14.388310 iDelay=199, Bit 12, Center 94 (3 ~ 186) 184
5926 01:00:14.394662 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5927 01:00:14.398224 iDelay=199, Bit 14, Center 96 (3 ~ 190) 188
5928 01:00:14.401241 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5929 01:00:14.401717 ==
5930 01:00:14.404886 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 01:00:14.407888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 01:00:14.408384 ==
5933 01:00:14.411381 DQS Delay:
5934 01:00:14.411776 DQS0 = 0, DQS1 = 0
5935 01:00:14.412079 DQM Delay:
5936 01:00:14.414571 DQM0 = 94, DQM1 = 90
5937 01:00:14.414968 DQ Delay:
5938 01:00:14.417846 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =94
5939 01:00:14.421557 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =92
5940 01:00:14.424880 DQ8 =82, DQ9 =80, DQ10 =90, DQ11 =84
5941 01:00:14.427733 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =96
5942 01:00:14.428128
5943 01:00:14.428435
5944 01:00:14.438258 [DQSOSCAuto] RK1, (LSB)MR18= 0xf18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5945 01:00:14.438736 CH1 RK1: MR19=505, MR18=F18
5946 01:00:14.444531 CH1_RK1: MR19=0x505, MR18=0xF18, DQSOSC=414, MR23=63, INC=63, DEC=42
5947 01:00:14.447842 [RxdqsGatingPostProcess] freq 933
5948 01:00:14.454373 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5949 01:00:14.458190 best DQS0 dly(2T, 0.5T) = (0, 10)
5950 01:00:14.461590 best DQS1 dly(2T, 0.5T) = (0, 10)
5951 01:00:14.464646 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5952 01:00:14.468020 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5953 01:00:14.468628 best DQS0 dly(2T, 0.5T) = (0, 10)
5954 01:00:14.471678 best DQS1 dly(2T, 0.5T) = (0, 10)
5955 01:00:14.474931 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5956 01:00:14.478073 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5957 01:00:14.481362 Pre-setting of DQS Precalculation
5958 01:00:14.488295 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5959 01:00:14.494494 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5960 01:00:14.501359 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5961 01:00:14.501837
5962 01:00:14.502202
5963 01:00:14.504594 [Calibration Summary] 1866 Mbps
5964 01:00:14.504990 CH 0, Rank 0
5965 01:00:14.507965 SW Impedance : PASS
5966 01:00:14.511542 DUTY Scan : NO K
5967 01:00:14.512019 ZQ Calibration : PASS
5968 01:00:14.514516 Jitter Meter : NO K
5969 01:00:14.518093 CBT Training : PASS
5970 01:00:14.518569 Write leveling : PASS
5971 01:00:14.521134 RX DQS gating : PASS
5972 01:00:14.524679 RX DQ/DQS(RDDQC) : PASS
5973 01:00:14.525153 TX DQ/DQS : PASS
5974 01:00:14.527759 RX DATLAT : PASS
5975 01:00:14.531390 RX DQ/DQS(Engine): PASS
5976 01:00:14.531864 TX OE : NO K
5977 01:00:14.532179 All Pass.
5978 01:00:14.534595
5979 01:00:14.535098 CH 0, Rank 1
5980 01:00:14.537699 SW Impedance : PASS
5981 01:00:14.538133 DUTY Scan : NO K
5982 01:00:14.541189 ZQ Calibration : PASS
5983 01:00:14.541660 Jitter Meter : NO K
5984 01:00:14.544820 CBT Training : PASS
5985 01:00:14.548178 Write leveling : PASS
5986 01:00:14.548575 RX DQS gating : PASS
5987 01:00:14.551048 RX DQ/DQS(RDDQC) : PASS
5988 01:00:14.554646 TX DQ/DQS : PASS
5989 01:00:14.555041 RX DATLAT : PASS
5990 01:00:14.558006 RX DQ/DQS(Engine): PASS
5991 01:00:14.561811 TX OE : NO K
5992 01:00:14.562321 All Pass.
5993 01:00:14.562634
5994 01:00:14.562915 CH 1, Rank 0
5995 01:00:14.564455 SW Impedance : PASS
5996 01:00:14.567798 DUTY Scan : NO K
5997 01:00:14.568194 ZQ Calibration : PASS
5998 01:00:14.571900 Jitter Meter : NO K
5999 01:00:14.574663 CBT Training : PASS
6000 01:00:14.575137 Write leveling : PASS
6001 01:00:14.577751 RX DQS gating : PASS
6002 01:00:14.578179 RX DQ/DQS(RDDQC) : PASS
6003 01:00:14.581199 TX DQ/DQS : PASS
6004 01:00:14.584794 RX DATLAT : PASS
6005 01:00:14.585265 RX DQ/DQS(Engine): PASS
6006 01:00:14.587880 TX OE : NO K
6007 01:00:14.588279 All Pass.
6008 01:00:14.588589
6009 01:00:14.591696 CH 1, Rank 1
6010 01:00:14.592166 SW Impedance : PASS
6011 01:00:14.594742 DUTY Scan : NO K
6012 01:00:14.597789 ZQ Calibration : PASS
6013 01:00:14.598227 Jitter Meter : NO K
6014 01:00:14.601364 CBT Training : PASS
6015 01:00:14.604613 Write leveling : PASS
6016 01:00:14.605011 RX DQS gating : PASS
6017 01:00:14.608041 RX DQ/DQS(RDDQC) : PASS
6018 01:00:14.611228 TX DQ/DQS : PASS
6019 01:00:14.611621 RX DATLAT : PASS
6020 01:00:14.614733 RX DQ/DQS(Engine): PASS
6021 01:00:14.617627 TX OE : NO K
6022 01:00:14.618240 All Pass.
6023 01:00:14.618567
6024 01:00:14.618858 DramC Write-DBI off
6025 01:00:14.621142 PER_BANK_REFRESH: Hybrid Mode
6026 01:00:14.624511 TX_TRACKING: ON
6027 01:00:14.631480 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6028 01:00:14.634474 [FAST_K] Save calibration result to emmc
6029 01:00:14.641300 dramc_set_vcore_voltage set vcore to 650000
6030 01:00:14.641700 Read voltage for 400, 6
6031 01:00:14.642039 Vio18 = 0
6032 01:00:14.644642 Vcore = 650000
6033 01:00:14.645171 Vdram = 0
6034 01:00:14.645489 Vddq = 0
6035 01:00:14.647585 Vmddr = 0
6036 01:00:14.651124 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6037 01:00:14.657936 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6038 01:00:14.658461 MEM_TYPE=3, freq_sel=20
6039 01:00:14.661265 sv_algorithm_assistance_LP4_800
6040 01:00:14.668307 ============ PULL DRAM RESETB DOWN ============
6041 01:00:14.671672 ========== PULL DRAM RESETB DOWN end =========
6042 01:00:14.675220 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6043 01:00:14.678606 ===================================
6044 01:00:14.681730 LPDDR4 DRAM CONFIGURATION
6045 01:00:14.684977 ===================================
6046 01:00:14.685516 EX_ROW_EN[0] = 0x0
6047 01:00:14.688353 EX_ROW_EN[1] = 0x0
6048 01:00:14.691745 LP4Y_EN = 0x0
6049 01:00:14.692259 WORK_FSP = 0x0
6050 01:00:14.695215 WL = 0x2
6051 01:00:14.695727 RL = 0x2
6052 01:00:14.698158 BL = 0x2
6053 01:00:14.698667 RPST = 0x0
6054 01:00:14.701446 RD_PRE = 0x0
6055 01:00:14.701954 WR_PRE = 0x1
6056 01:00:14.704574 WR_PST = 0x0
6057 01:00:14.705007 DBI_WR = 0x0
6058 01:00:14.707790 DBI_RD = 0x0
6059 01:00:14.708220 OTF = 0x1
6060 01:00:14.711090 ===================================
6061 01:00:14.714714 ===================================
6062 01:00:14.717727 ANA top config
6063 01:00:14.720993 ===================================
6064 01:00:14.721421 DLL_ASYNC_EN = 0
6065 01:00:14.724627 ALL_SLAVE_EN = 1
6066 01:00:14.728131 NEW_RANK_MODE = 1
6067 01:00:14.731758 DLL_IDLE_MODE = 1
6068 01:00:14.734483 LP45_APHY_COMB_EN = 1
6069 01:00:14.734914 TX_ODT_DIS = 1
6070 01:00:14.737775 NEW_8X_MODE = 1
6071 01:00:14.741520 ===================================
6072 01:00:14.744741 ===================================
6073 01:00:14.748251 data_rate = 800
6074 01:00:14.751408 CKR = 1
6075 01:00:14.754356 DQ_P2S_RATIO = 4
6076 01:00:14.757651 ===================================
6077 01:00:14.758101 CA_P2S_RATIO = 4
6078 01:00:14.761516 DQ_CA_OPEN = 0
6079 01:00:14.764810 DQ_SEMI_OPEN = 1
6080 01:00:14.768003 CA_SEMI_OPEN = 1
6081 01:00:14.771524 CA_FULL_RATE = 0
6082 01:00:14.772011 DQ_CKDIV4_EN = 0
6083 01:00:14.774699 CA_CKDIV4_EN = 1
6084 01:00:14.778241 CA_PREDIV_EN = 0
6085 01:00:14.781508 PH8_DLY = 0
6086 01:00:14.784932 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6087 01:00:14.788163 DQ_AAMCK_DIV = 0
6088 01:00:14.788557 CA_AAMCK_DIV = 0
6089 01:00:14.791912 CA_ADMCK_DIV = 4
6090 01:00:14.795014 DQ_TRACK_CA_EN = 0
6091 01:00:14.798260 CA_PICK = 800
6092 01:00:14.801833 CA_MCKIO = 400
6093 01:00:14.805387 MCKIO_SEMI = 400
6094 01:00:14.808161 PLL_FREQ = 3016
6095 01:00:14.808556 DQ_UI_PI_RATIO = 32
6096 01:00:14.811419 CA_UI_PI_RATIO = 32
6097 01:00:14.814829 ===================================
6098 01:00:14.818287 ===================================
6099 01:00:14.821818 memory_type:LPDDR4
6100 01:00:14.824949 GP_NUM : 10
6101 01:00:14.825339 SRAM_EN : 1
6102 01:00:14.828083 MD32_EN : 0
6103 01:00:14.832347 ===================================
6104 01:00:14.834994 [ANA_INIT] >>>>>>>>>>>>>>
6105 01:00:14.835388 <<<<<< [CONFIGURE PHASE]: ANA_TX
6106 01:00:14.838184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6107 01:00:14.841419 ===================================
6108 01:00:14.845170 data_rate = 800,PCW = 0X7400
6109 01:00:14.848533 ===================================
6110 01:00:14.852105 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6111 01:00:14.858094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6112 01:00:14.868773 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6113 01:00:14.875114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6114 01:00:14.878511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6115 01:00:14.881419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6116 01:00:14.881817 [ANA_INIT] flow start
6117 01:00:14.885387 [ANA_INIT] PLL >>>>>>>>
6118 01:00:14.888161 [ANA_INIT] PLL <<<<<<<<
6119 01:00:14.888610 [ANA_INIT] MIDPI >>>>>>>>
6120 01:00:14.891793 [ANA_INIT] MIDPI <<<<<<<<
6121 01:00:14.895158 [ANA_INIT] DLL >>>>>>>>
6122 01:00:14.895632 [ANA_INIT] flow end
6123 01:00:14.901830 ============ LP4 DIFF to SE enter ============
6124 01:00:14.905460 ============ LP4 DIFF to SE exit ============
6125 01:00:14.908523 [ANA_INIT] <<<<<<<<<<<<<
6126 01:00:14.912192 [Flow] Enable top DCM control >>>>>
6127 01:00:14.914831 [Flow] Enable top DCM control <<<<<
6128 01:00:14.915232 Enable DLL master slave shuffle
6129 01:00:14.921928 ==============================================================
6130 01:00:14.925218 Gating Mode config
6131 01:00:14.928035 ==============================================================
6132 01:00:14.931900 Config description:
6133 01:00:14.941613 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6134 01:00:14.948663 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6135 01:00:14.951503 SELPH_MODE 0: By rank 1: By Phase
6136 01:00:14.958635 ==============================================================
6137 01:00:14.962077 GAT_TRACK_EN = 0
6138 01:00:14.964999 RX_GATING_MODE = 2
6139 01:00:14.968250 RX_GATING_TRACK_MODE = 2
6140 01:00:14.968765 SELPH_MODE = 1
6141 01:00:14.971785 PICG_EARLY_EN = 1
6142 01:00:14.975154 VALID_LAT_VALUE = 1
6143 01:00:14.981918 ==============================================================
6144 01:00:14.984863 Enter into Gating configuration >>>>
6145 01:00:14.988186 Exit from Gating configuration <<<<
6146 01:00:14.991926 Enter into DVFS_PRE_config >>>>>
6147 01:00:15.001721 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6148 01:00:15.004981 Exit from DVFS_PRE_config <<<<<
6149 01:00:15.008342 Enter into PICG configuration >>>>
6150 01:00:15.011499 Exit from PICG configuration <<<<
6151 01:00:15.014707 [RX_INPUT] configuration >>>>>
6152 01:00:15.018106 [RX_INPUT] configuration <<<<<
6153 01:00:15.021257 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6154 01:00:15.028118 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6155 01:00:15.035034 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6156 01:00:15.041871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6157 01:00:15.045273 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6158 01:00:15.051771 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6159 01:00:15.055064 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6160 01:00:15.061652 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6161 01:00:15.064719 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6162 01:00:15.068361 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6163 01:00:15.071889 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6164 01:00:15.078786 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6165 01:00:15.081493 ===================================
6166 01:00:15.082045 LPDDR4 DRAM CONFIGURATION
6167 01:00:15.085469 ===================================
6168 01:00:15.088494 EX_ROW_EN[0] = 0x0
6169 01:00:15.092232 EX_ROW_EN[1] = 0x0
6170 01:00:15.092753 LP4Y_EN = 0x0
6171 01:00:15.095487 WORK_FSP = 0x0
6172 01:00:15.096000 WL = 0x2
6173 01:00:15.098838 RL = 0x2
6174 01:00:15.099351 BL = 0x2
6175 01:00:15.101689 RPST = 0x0
6176 01:00:15.102257 RD_PRE = 0x0
6177 01:00:15.105206 WR_PRE = 0x1
6178 01:00:15.105644 WR_PST = 0x0
6179 01:00:15.108289 DBI_WR = 0x0
6180 01:00:15.108723 DBI_RD = 0x0
6181 01:00:15.112149 OTF = 0x1
6182 01:00:15.114891 ===================================
6183 01:00:15.118220 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6184 01:00:15.121678 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6185 01:00:15.128126 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6186 01:00:15.131421 ===================================
6187 01:00:15.131786 LPDDR4 DRAM CONFIGURATION
6188 01:00:15.134770 ===================================
6189 01:00:15.138065 EX_ROW_EN[0] = 0x10
6190 01:00:15.138600 EX_ROW_EN[1] = 0x0
6191 01:00:15.141452 LP4Y_EN = 0x0
6192 01:00:15.141881 WORK_FSP = 0x0
6193 01:00:15.145065 WL = 0x2
6194 01:00:15.148291 RL = 0x2
6195 01:00:15.148685 BL = 0x2
6196 01:00:15.151199 RPST = 0x0
6197 01:00:15.151589 RD_PRE = 0x0
6198 01:00:15.154849 WR_PRE = 0x1
6199 01:00:15.155237 WR_PST = 0x0
6200 01:00:15.158057 DBI_WR = 0x0
6201 01:00:15.158444 DBI_RD = 0x0
6202 01:00:15.161498 OTF = 0x1
6203 01:00:15.164800 ===================================
6204 01:00:15.168546 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6205 01:00:15.174090 nWR fixed to 30
6206 01:00:15.177413 [ModeRegInit_LP4] CH0 RK0
6207 01:00:15.177888 [ModeRegInit_LP4] CH0 RK1
6208 01:00:15.180569 [ModeRegInit_LP4] CH1 RK0
6209 01:00:15.184022 [ModeRegInit_LP4] CH1 RK1
6210 01:00:15.184498 match AC timing 19
6211 01:00:15.190571 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6212 01:00:15.193761 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6213 01:00:15.197615 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6214 01:00:15.204005 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6215 01:00:15.207089 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6216 01:00:15.207540 ==
6217 01:00:15.210754 Dram Type= 6, Freq= 0, CH_0, rank 0
6218 01:00:15.214009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6219 01:00:15.214534 ==
6220 01:00:15.220635 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6221 01:00:15.227223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6222 01:00:15.230416 [CA 0] Center 36 (8~64) winsize 57
6223 01:00:15.233831 [CA 1] Center 36 (8~64) winsize 57
6224 01:00:15.234307 [CA 2] Center 36 (8~64) winsize 57
6225 01:00:15.237406 [CA 3] Center 36 (8~64) winsize 57
6226 01:00:15.240870 [CA 4] Center 36 (8~64) winsize 57
6227 01:00:15.244088 [CA 5] Center 36 (8~64) winsize 57
6228 01:00:15.244602
6229 01:00:15.247037 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6230 01:00:15.247476
6231 01:00:15.254203 [CATrainingPosCal] consider 1 rank data
6232 01:00:15.254720 u2DelayCellTimex100 = 270/100 ps
6233 01:00:15.257409 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 01:00:15.263793 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 01:00:15.267265 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 01:00:15.270490 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 01:00:15.274040 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 01:00:15.277499 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 01:00:15.278045
6240 01:00:15.280727 CA PerBit enable=1, Macro0, CA PI delay=36
6241 01:00:15.281159
6242 01:00:15.284207 [CBTSetCACLKResult] CA Dly = 36
6243 01:00:15.287225 CS Dly: 1 (0~32)
6244 01:00:15.287729 ==
6245 01:00:15.290627 Dram Type= 6, Freq= 0, CH_0, rank 1
6246 01:00:15.293967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6247 01:00:15.294579 ==
6248 01:00:15.297636 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6249 01:00:15.303753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6250 01:00:15.307185 [CA 0] Center 36 (8~64) winsize 57
6251 01:00:15.310294 [CA 1] Center 36 (8~64) winsize 57
6252 01:00:15.314044 [CA 2] Center 36 (8~64) winsize 57
6253 01:00:15.316552 [CA 3] Center 36 (8~64) winsize 57
6254 01:00:15.320095 [CA 4] Center 36 (8~64) winsize 57
6255 01:00:15.323616 [CA 5] Center 36 (8~64) winsize 57
6256 01:00:15.324058
6257 01:00:15.326869 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6258 01:00:15.327260
6259 01:00:15.330041 [CATrainingPosCal] consider 2 rank data
6260 01:00:15.333625 u2DelayCellTimex100 = 270/100 ps
6261 01:00:15.336498 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 01:00:15.340057 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 01:00:15.343365 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 01:00:15.347006 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 01:00:15.353224 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 01:00:15.356240 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 01:00:15.356520
6268 01:00:15.360066 CA PerBit enable=1, Macro0, CA PI delay=36
6269 01:00:15.360345
6270 01:00:15.363394 [CBTSetCACLKResult] CA Dly = 36
6271 01:00:15.363670 CS Dly: 1 (0~32)
6272 01:00:15.363881
6273 01:00:15.366552 ----->DramcWriteLeveling(PI) begin...
6274 01:00:15.366910 ==
6275 01:00:15.369700 Dram Type= 6, Freq= 0, CH_0, rank 0
6276 01:00:15.376387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 01:00:15.376668 ==
6278 01:00:15.379591 Write leveling (Byte 0): 40 => 8
6279 01:00:15.379879 Write leveling (Byte 1): 32 => 0
6280 01:00:15.383027 DramcWriteLeveling(PI) end<-----
6281 01:00:15.383311
6282 01:00:15.386363 ==
6283 01:00:15.389698 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 01:00:15.393553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 01:00:15.393829 ==
6286 01:00:15.397161 [Gating] SW mode calibration
6287 01:00:15.403306 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6288 01:00:15.406326 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6289 01:00:15.412997 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6290 01:00:15.416592 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6291 01:00:15.419696 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 01:00:15.423687 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 01:00:15.430466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 01:00:15.433312 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 01:00:15.437152 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6296 01:00:15.443754 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 01:00:15.446639 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 01:00:15.450332 Total UI for P1: 0, mck2ui 16
6299 01:00:15.453558 best dqsien dly found for B0: ( 0, 14, 24)
6300 01:00:15.456942 Total UI for P1: 0, mck2ui 16
6301 01:00:15.460318 best dqsien dly found for B1: ( 0, 14, 24)
6302 01:00:15.463425 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6303 01:00:15.467136 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6304 01:00:15.467522
6305 01:00:15.470115 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6306 01:00:15.473736 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6307 01:00:15.476988 [Gating] SW calibration Done
6308 01:00:15.477374 ==
6309 01:00:15.480613 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 01:00:15.483873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 01:00:15.486944 ==
6312 01:00:15.487349 RX Vref Scan: 0
6313 01:00:15.487725
6314 01:00:15.490202 RX Vref 0 -> 0, step: 1
6315 01:00:15.490590
6316 01:00:15.493671 RX Delay -410 -> 252, step: 16
6317 01:00:15.496695 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6318 01:00:15.500043 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6319 01:00:15.503621 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6320 01:00:15.510465 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6321 01:00:15.513548 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6322 01:00:15.516722 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6323 01:00:15.519903 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6324 01:00:15.527060 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6325 01:00:15.529946 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6326 01:00:15.532965 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6327 01:00:15.536820 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6328 01:00:15.543813 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6329 01:00:15.547098 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6330 01:00:15.550033 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6331 01:00:15.553655 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6332 01:00:15.560399 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6333 01:00:15.560798 ==
6334 01:00:15.564261 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 01:00:15.567259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 01:00:15.567693 ==
6337 01:00:15.568170 DQS Delay:
6338 01:00:15.569969 DQS0 = 35, DQS1 = 51
6339 01:00:15.570471 DQM Delay:
6340 01:00:15.573279 DQM0 = 8, DQM1 = 10
6341 01:00:15.573757 DQ Delay:
6342 01:00:15.576827 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6343 01:00:15.580183 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6344 01:00:15.583360 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6345 01:00:15.586814 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6346 01:00:15.587355
6347 01:00:15.587688
6348 01:00:15.588043 ==
6349 01:00:15.590337 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 01:00:15.593297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 01:00:15.593841 ==
6352 01:00:15.594367
6353 01:00:15.594826
6354 01:00:15.597218 TX Vref Scan disable
6355 01:00:15.597760 == TX Byte 0 ==
6356 01:00:15.603658 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 01:00:15.606953 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 01:00:15.607442 == TX Byte 1 ==
6359 01:00:15.613927 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6360 01:00:15.616695 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6361 01:00:15.617062 ==
6362 01:00:15.620558 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 01:00:15.623617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 01:00:15.624087 ==
6365 01:00:15.624420
6366 01:00:15.624802
6367 01:00:15.626889 TX Vref Scan disable
6368 01:00:15.630124 == TX Byte 0 ==
6369 01:00:15.633925 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 01:00:15.636884 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 01:00:15.637400 == TX Byte 1 ==
6372 01:00:15.643786 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6373 01:00:15.647315 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6374 01:00:15.647718
6375 01:00:15.648180 [DATLAT]
6376 01:00:15.650277 Freq=400, CH0 RK0
6377 01:00:15.650800
6378 01:00:15.651283 DATLAT Default: 0xf
6379 01:00:15.653808 0, 0xFFFF, sum = 0
6380 01:00:15.654279 1, 0xFFFF, sum = 0
6381 01:00:15.656739 2, 0xFFFF, sum = 0
6382 01:00:15.657155 3, 0xFFFF, sum = 0
6383 01:00:15.660025 4, 0xFFFF, sum = 0
6384 01:00:15.663390 5, 0xFFFF, sum = 0
6385 01:00:15.663798 6, 0xFFFF, sum = 0
6386 01:00:15.666834 7, 0xFFFF, sum = 0
6387 01:00:15.667241 8, 0xFFFF, sum = 0
6388 01:00:15.670385 9, 0xFFFF, sum = 0
6389 01:00:15.670786 10, 0xFFFF, sum = 0
6390 01:00:15.673348 11, 0xFFFF, sum = 0
6391 01:00:15.673764 12, 0xFFFF, sum = 0
6392 01:00:15.676752 13, 0x0, sum = 1
6393 01:00:15.677197 14, 0x0, sum = 2
6394 01:00:15.680254 15, 0x0, sum = 3
6395 01:00:15.680682 16, 0x0, sum = 4
6396 01:00:15.681010 best_step = 14
6397 01:00:15.683441
6398 01:00:15.683858 ==
6399 01:00:15.686713 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 01:00:15.690283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 01:00:15.690680 ==
6402 01:00:15.690992 RX Vref Scan: 1
6403 01:00:15.691275
6404 01:00:15.693598 RX Vref 0 -> 0, step: 1
6405 01:00:15.694027
6406 01:00:15.697029 RX Delay -343 -> 252, step: 8
6407 01:00:15.697423
6408 01:00:15.699949 Set Vref, RX VrefLevel [Byte0]: 54
6409 01:00:15.703343 [Byte1]: 52
6410 01:00:15.707536
6411 01:00:15.708051 Final RX Vref Byte 0 = 54 to rank0
6412 01:00:15.711010 Final RX Vref Byte 1 = 52 to rank0
6413 01:00:15.713638 Final RX Vref Byte 0 = 54 to rank1
6414 01:00:15.717114 Final RX Vref Byte 1 = 52 to rank1==
6415 01:00:15.720470 Dram Type= 6, Freq= 0, CH_0, rank 0
6416 01:00:15.727575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 01:00:15.727968 ==
6418 01:00:15.728273 DQS Delay:
6419 01:00:15.730872 DQS0 = 44, DQS1 = 60
6420 01:00:15.731260 DQM Delay:
6421 01:00:15.731566 DQM0 = 11, DQM1 = 14
6422 01:00:15.733971 DQ Delay:
6423 01:00:15.737190 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6424 01:00:15.740793 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6425 01:00:15.741197 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6426 01:00:15.743732 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6427 01:00:15.746847
6428 01:00:15.747351
6429 01:00:15.753417 [DQSOSCAuto] RK0, (LSB)MR18= 0x8755, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
6430 01:00:15.757069 CH0 RK0: MR19=C0C, MR18=8755
6431 01:00:15.763624 CH0_RK0: MR19=0xC0C, MR18=0x8755, DQSOSC=392, MR23=63, INC=384, DEC=256
6432 01:00:15.764086 ==
6433 01:00:15.766619 Dram Type= 6, Freq= 0, CH_0, rank 1
6434 01:00:15.770079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 01:00:15.770445 ==
6436 01:00:15.773690 [Gating] SW mode calibration
6437 01:00:15.780385 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6438 01:00:15.787376 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6439 01:00:15.790102 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6440 01:00:15.793841 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6441 01:00:15.800576 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 01:00:15.803573 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 01:00:15.807297 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 01:00:15.813631 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 01:00:15.816691 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 01:00:15.820240 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 01:00:15.826596 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 01:00:15.827099 Total UI for P1: 0, mck2ui 16
6449 01:00:15.830008 best dqsien dly found for B0: ( 0, 14, 24)
6450 01:00:15.834094 Total UI for P1: 0, mck2ui 16
6451 01:00:15.836932 best dqsien dly found for B1: ( 0, 14, 24)
6452 01:00:15.840303 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6453 01:00:15.847020 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6454 01:00:15.847534
6455 01:00:15.850401 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6456 01:00:15.853664 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6457 01:00:15.856692 [Gating] SW calibration Done
6458 01:00:15.857157 ==
6459 01:00:15.860172 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 01:00:15.863599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 01:00:15.864010 ==
6462 01:00:15.864316 RX Vref Scan: 0
6463 01:00:15.866784
6464 01:00:15.867174 RX Vref 0 -> 0, step: 1
6465 01:00:15.867475
6466 01:00:15.870332 RX Delay -410 -> 252, step: 16
6467 01:00:15.873651 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6468 01:00:15.879935 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6469 01:00:15.883572 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6470 01:00:15.887137 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6471 01:00:15.890468 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6472 01:00:15.896827 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6473 01:00:15.900134 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6474 01:00:15.903576 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6475 01:00:15.906929 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6476 01:00:15.914236 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6477 01:00:15.916822 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6478 01:00:15.920144 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6479 01:00:15.923562 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6480 01:00:15.930497 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6481 01:00:15.933735 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6482 01:00:15.937363 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6483 01:00:15.937824 ==
6484 01:00:15.940073 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 01:00:15.943895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 01:00:15.946908 ==
6487 01:00:15.947324 DQS Delay:
6488 01:00:15.947646 DQS0 = 43, DQS1 = 51
6489 01:00:15.949960 DQM Delay:
6490 01:00:15.950388 DQM0 = 11, DQM1 = 10
6491 01:00:15.953587 DQ Delay:
6492 01:00:15.953978 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6493 01:00:15.956796 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6494 01:00:15.960181 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6495 01:00:15.963695 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6496 01:00:15.964085
6497 01:00:15.964390
6498 01:00:15.964667 ==
6499 01:00:15.966960 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 01:00:15.974185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 01:00:15.974675 ==
6502 01:00:15.974986
6503 01:00:15.975264
6504 01:00:15.975533 TX Vref Scan disable
6505 01:00:15.977263 == TX Byte 0 ==
6506 01:00:15.980817 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6507 01:00:15.984130 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6508 01:00:15.987349 == TX Byte 1 ==
6509 01:00:15.991224 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6510 01:00:15.994277 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6511 01:00:15.994762 ==
6512 01:00:15.997409 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 01:00:16.004178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 01:00:16.004727 ==
6515 01:00:16.005075
6516 01:00:16.005349
6517 01:00:16.005612 TX Vref Scan disable
6518 01:00:16.007456 == TX Byte 0 ==
6519 01:00:16.010303 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6520 01:00:16.014404 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6521 01:00:16.017484 == TX Byte 1 ==
6522 01:00:16.021118 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6523 01:00:16.023725 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6524 01:00:16.024161
6525 01:00:16.027122 [DATLAT]
6526 01:00:16.027511 Freq=400, CH0 RK1
6527 01:00:16.027813
6528 01:00:16.030601 DATLAT Default: 0xe
6529 01:00:16.030990 0, 0xFFFF, sum = 0
6530 01:00:16.034092 1, 0xFFFF, sum = 0
6531 01:00:16.034490 2, 0xFFFF, sum = 0
6532 01:00:16.037189 3, 0xFFFF, sum = 0
6533 01:00:16.037679 4, 0xFFFF, sum = 0
6534 01:00:16.040739 5, 0xFFFF, sum = 0
6535 01:00:16.041216 6, 0xFFFF, sum = 0
6536 01:00:16.043827 7, 0xFFFF, sum = 0
6537 01:00:16.044228 8, 0xFFFF, sum = 0
6538 01:00:16.047105 9, 0xFFFF, sum = 0
6539 01:00:16.047507 10, 0xFFFF, sum = 0
6540 01:00:16.050573 11, 0xFFFF, sum = 0
6541 01:00:16.050973 12, 0xFFFF, sum = 0
6542 01:00:16.054240 13, 0x0, sum = 1
6543 01:00:16.054733 14, 0x0, sum = 2
6544 01:00:16.057576 15, 0x0, sum = 3
6545 01:00:16.058113 16, 0x0, sum = 4
6546 01:00:16.060900 best_step = 14
6547 01:00:16.061384
6548 01:00:16.061692 ==
6549 01:00:16.063785 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 01:00:16.067599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 01:00:16.068075 ==
6552 01:00:16.070395 RX Vref Scan: 0
6553 01:00:16.070795
6554 01:00:16.071125 RX Vref 0 -> 0, step: 1
6555 01:00:16.071421
6556 01:00:16.073882 RX Delay -343 -> 252, step: 8
6557 01:00:16.081669 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6558 01:00:16.084684 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6559 01:00:16.088296 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6560 01:00:16.091792 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6561 01:00:16.098295 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6562 01:00:16.101212 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6563 01:00:16.105129 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6564 01:00:16.108647 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6565 01:00:16.115349 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6566 01:00:16.118281 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6567 01:00:16.121661 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6568 01:00:16.124746 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6569 01:00:16.131771 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6570 01:00:16.135425 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6571 01:00:16.138091 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6572 01:00:16.144929 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6573 01:00:16.145373 ==
6574 01:00:16.148574 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 01:00:16.151583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 01:00:16.152021 ==
6577 01:00:16.152374 DQS Delay:
6578 01:00:16.154868 DQS0 = 48, DQS1 = 60
6579 01:00:16.155277 DQM Delay:
6580 01:00:16.158317 DQM0 = 13, DQM1 = 13
6581 01:00:16.158832 DQ Delay:
6582 01:00:16.161746 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6583 01:00:16.164766 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6584 01:00:16.168279 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6585 01:00:16.171533 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6586 01:00:16.171924
6587 01:00:16.172226
6588 01:00:16.178562 [DQSOSCAuto] RK1, (LSB)MR18= 0x966a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6589 01:00:16.181841 CH0 RK1: MR19=C0C, MR18=966A
6590 01:00:16.188508 CH0_RK1: MR19=0xC0C, MR18=0x966A, DQSOSC=391, MR23=63, INC=386, DEC=257
6591 01:00:16.191905 [RxdqsGatingPostProcess] freq 400
6592 01:00:16.195101 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6593 01:00:16.198434 best DQS0 dly(2T, 0.5T) = (0, 10)
6594 01:00:16.201636 best DQS1 dly(2T, 0.5T) = (0, 10)
6595 01:00:16.205361 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6596 01:00:16.208087 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6597 01:00:16.211643 best DQS0 dly(2T, 0.5T) = (0, 10)
6598 01:00:16.214763 best DQS1 dly(2T, 0.5T) = (0, 10)
6599 01:00:16.218129 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6600 01:00:16.221745 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6601 01:00:16.224932 Pre-setting of DQS Precalculation
6602 01:00:16.228327 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6603 01:00:16.228865 ==
6604 01:00:16.231798 Dram Type= 6, Freq= 0, CH_1, rank 0
6605 01:00:16.238494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 01:00:16.238896 ==
6607 01:00:16.241959 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6608 01:00:16.248453 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6609 01:00:16.252158 [CA 0] Center 36 (8~64) winsize 57
6610 01:00:16.255320 [CA 1] Center 36 (8~64) winsize 57
6611 01:00:16.258431 [CA 2] Center 36 (8~64) winsize 57
6612 01:00:16.262218 [CA 3] Center 36 (8~64) winsize 57
6613 01:00:16.265644 [CA 4] Center 36 (8~64) winsize 57
6614 01:00:16.268417 [CA 5] Center 36 (8~64) winsize 57
6615 01:00:16.268862
6616 01:00:16.272022 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6617 01:00:16.272515
6618 01:00:16.275274 [CATrainingPosCal] consider 1 rank data
6619 01:00:16.278395 u2DelayCellTimex100 = 270/100 ps
6620 01:00:16.282406 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 01:00:16.285258 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 01:00:16.288920 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 01:00:16.292316 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 01:00:16.295524 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 01:00:16.298788 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 01:00:16.299177
6627 01:00:16.305149 CA PerBit enable=1, Macro0, CA PI delay=36
6628 01:00:16.305603
6629 01:00:16.308236 [CBTSetCACLKResult] CA Dly = 36
6630 01:00:16.308779 CS Dly: 1 (0~32)
6631 01:00:16.309186 ==
6632 01:00:16.311906 Dram Type= 6, Freq= 0, CH_1, rank 1
6633 01:00:16.315313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 01:00:16.315812 ==
6635 01:00:16.321856 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6636 01:00:16.328535 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6637 01:00:16.331759 [CA 0] Center 36 (8~64) winsize 57
6638 01:00:16.335162 [CA 1] Center 36 (8~64) winsize 57
6639 01:00:16.338610 [CA 2] Center 36 (8~64) winsize 57
6640 01:00:16.339191 [CA 3] Center 36 (8~64) winsize 57
6641 01:00:16.342018 [CA 4] Center 36 (8~64) winsize 57
6642 01:00:16.345386 [CA 5] Center 36 (8~64) winsize 57
6643 01:00:16.345855
6644 01:00:16.351959 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6645 01:00:16.352444
6646 01:00:16.355910 [CATrainingPosCal] consider 2 rank data
6647 01:00:16.356490 u2DelayCellTimex100 = 270/100 ps
6648 01:00:16.362097 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 01:00:16.365002 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 01:00:16.368387 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 01:00:16.371767 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 01:00:16.375884 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 01:00:16.378507 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 01:00:16.379047
6655 01:00:16.382038 CA PerBit enable=1, Macro0, CA PI delay=36
6656 01:00:16.382621
6657 01:00:16.385707 [CBTSetCACLKResult] CA Dly = 36
6658 01:00:16.389298 CS Dly: 1 (0~32)
6659 01:00:16.389720
6660 01:00:16.392076 ----->DramcWriteLeveling(PI) begin...
6661 01:00:16.392533 ==
6662 01:00:16.395584 Dram Type= 6, Freq= 0, CH_1, rank 0
6663 01:00:16.398844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 01:00:16.399241 ==
6665 01:00:16.402087 Write leveling (Byte 0): 40 => 8
6666 01:00:16.405677 Write leveling (Byte 1): 40 => 8
6667 01:00:16.408937 DramcWriteLeveling(PI) end<-----
6668 01:00:16.409463
6669 01:00:16.409775 ==
6670 01:00:16.412592 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 01:00:16.415775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 01:00:16.416254 ==
6673 01:00:16.418696 [Gating] SW mode calibration
6674 01:00:16.425277 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6675 01:00:16.432267 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6676 01:00:16.435281 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6677 01:00:16.438712 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6678 01:00:16.445395 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 01:00:16.448917 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 01:00:16.452230 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 01:00:16.455371 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 01:00:16.462345 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 01:00:16.465624 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 01:00:16.468655 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 01:00:16.471972 Total UI for P1: 0, mck2ui 16
6686 01:00:16.475389 best dqsien dly found for B0: ( 0, 14, 24)
6687 01:00:16.479353 Total UI for P1: 0, mck2ui 16
6688 01:00:16.482021 best dqsien dly found for B1: ( 0, 14, 24)
6689 01:00:16.485536 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6690 01:00:16.488973 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6691 01:00:16.489360
6692 01:00:16.495416 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6693 01:00:16.498946 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6694 01:00:16.501547 [Gating] SW calibration Done
6695 01:00:16.501622 ==
6696 01:00:16.505251 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 01:00:16.509166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 01:00:16.509306 ==
6699 01:00:16.509374 RX Vref Scan: 0
6700 01:00:16.509435
6701 01:00:16.511870 RX Vref 0 -> 0, step: 1
6702 01:00:16.511977
6703 01:00:16.515239 RX Delay -410 -> 252, step: 16
6704 01:00:16.518588 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6705 01:00:16.525226 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6706 01:00:16.528347 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6707 01:00:16.531949 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6708 01:00:16.535343 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6709 01:00:16.538378 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6710 01:00:16.545462 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6711 01:00:16.548842 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6712 01:00:16.552251 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6713 01:00:16.555838 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6714 01:00:16.562295 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6715 01:00:16.565495 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6716 01:00:16.568573 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6717 01:00:16.571911 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6718 01:00:16.578974 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6719 01:00:16.582143 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6720 01:00:16.582538 ==
6721 01:00:16.585757 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 01:00:16.588768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 01:00:16.589161 ==
6724 01:00:16.592575 DQS Delay:
6725 01:00:16.593055 DQS0 = 51, DQS1 = 59
6726 01:00:16.595584 DQM Delay:
6727 01:00:16.595971 DQM0 = 19, DQM1 = 16
6728 01:00:16.596272 DQ Delay:
6729 01:00:16.598782 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6730 01:00:16.602241 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6731 01:00:16.605460 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6732 01:00:16.608544 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6733 01:00:16.608929
6734 01:00:16.609231
6735 01:00:16.609512 ==
6736 01:00:16.612245 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 01:00:16.619048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 01:00:16.619439 ==
6739 01:00:16.619739
6740 01:00:16.620016
6741 01:00:16.620278 TX Vref Scan disable
6742 01:00:16.622485 == TX Byte 0 ==
6743 01:00:16.625824 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 01:00:16.629198 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 01:00:16.632609 == TX Byte 1 ==
6746 01:00:16.635694 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 01:00:16.639201 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 01:00:16.639598 ==
6749 01:00:16.642548 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 01:00:16.648853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 01:00:16.649247 ==
6752 01:00:16.649550
6753 01:00:16.649829
6754 01:00:16.650155 TX Vref Scan disable
6755 01:00:16.652316 == TX Byte 0 ==
6756 01:00:16.655865 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 01:00:16.658719 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 01:00:16.662450 == TX Byte 1 ==
6759 01:00:16.665574 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 01:00:16.668924 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 01:00:16.669327
6762 01:00:16.672411 [DATLAT]
6763 01:00:16.672803 Freq=400, CH1 RK0
6764 01:00:16.673110
6765 01:00:16.675759 DATLAT Default: 0xf
6766 01:00:16.676149 0, 0xFFFF, sum = 0
6767 01:00:16.679148 1, 0xFFFF, sum = 0
6768 01:00:16.679541 2, 0xFFFF, sum = 0
6769 01:00:16.682504 3, 0xFFFF, sum = 0
6770 01:00:16.682901 4, 0xFFFF, sum = 0
6771 01:00:16.685402 5, 0xFFFF, sum = 0
6772 01:00:16.685797 6, 0xFFFF, sum = 0
6773 01:00:16.688956 7, 0xFFFF, sum = 0
6774 01:00:16.689352 8, 0xFFFF, sum = 0
6775 01:00:16.692599 9, 0xFFFF, sum = 0
6776 01:00:16.693090 10, 0xFFFF, sum = 0
6777 01:00:16.695613 11, 0xFFFF, sum = 0
6778 01:00:16.698743 12, 0xFFFF, sum = 0
6779 01:00:16.699138 13, 0x0, sum = 1
6780 01:00:16.702320 14, 0x0, sum = 2
6781 01:00:16.702712 15, 0x0, sum = 3
6782 01:00:16.703023 16, 0x0, sum = 4
6783 01:00:16.705375 best_step = 14
6784 01:00:16.705766
6785 01:00:16.706109 ==
6786 01:00:16.708750 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 01:00:16.712147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 01:00:16.712540 ==
6789 01:00:16.715877 RX Vref Scan: 1
6790 01:00:16.716265
6791 01:00:16.716584 RX Vref 0 -> 0, step: 1
6792 01:00:16.716868
6793 01:00:16.718774 RX Delay -359 -> 252, step: 8
6794 01:00:16.719229
6795 01:00:16.722174 Set Vref, RX VrefLevel [Byte0]: 56
6796 01:00:16.725715 [Byte1]: 53
6797 01:00:16.730738
6798 01:00:16.731218 Final RX Vref Byte 0 = 56 to rank0
6799 01:00:16.733873 Final RX Vref Byte 1 = 53 to rank0
6800 01:00:16.737428 Final RX Vref Byte 0 = 56 to rank1
6801 01:00:16.740833 Final RX Vref Byte 1 = 53 to rank1==
6802 01:00:16.744583 Dram Type= 6, Freq= 0, CH_1, rank 0
6803 01:00:16.747626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 01:00:16.750975 ==
6805 01:00:16.751455 DQS Delay:
6806 01:00:16.751761 DQS0 = 48, DQS1 = 60
6807 01:00:16.754099 DQM Delay:
6808 01:00:16.754493 DQM0 = 12, DQM1 = 13
6809 01:00:16.757747 DQ Delay:
6810 01:00:16.760852 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6811 01:00:16.761247 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6812 01:00:16.764806 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6813 01:00:16.767522 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6814 01:00:16.768001
6815 01:00:16.768307
6816 01:00:16.777888 [DQSOSCAuto] RK0, (LSB)MR18= 0x9238, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
6817 01:00:16.781134 CH1 RK0: MR19=C0C, MR18=9238
6818 01:00:16.787526 CH1_RK0: MR19=0xC0C, MR18=0x9238, DQSOSC=391, MR23=63, INC=386, DEC=257
6819 01:00:16.788050 ==
6820 01:00:16.790901 Dram Type= 6, Freq= 0, CH_1, rank 1
6821 01:00:16.794335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 01:00:16.794852 ==
6823 01:00:16.797623 [Gating] SW mode calibration
6824 01:00:16.804643 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6825 01:00:16.807484 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6826 01:00:16.813816 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6827 01:00:16.817128 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6828 01:00:16.821101 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 01:00:16.827552 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 01:00:16.830529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 01:00:16.834342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 01:00:16.840891 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6833 01:00:16.844414 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 01:00:16.847386 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 01:00:16.850800 Total UI for P1: 0, mck2ui 16
6836 01:00:16.854025 best dqsien dly found for B0: ( 0, 14, 24)
6837 01:00:16.857337 Total UI for P1: 0, mck2ui 16
6838 01:00:16.860863 best dqsien dly found for B1: ( 0, 14, 24)
6839 01:00:16.864371 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6840 01:00:16.867361 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6841 01:00:16.867792
6842 01:00:16.874300 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6843 01:00:16.877308 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6844 01:00:16.877726 [Gating] SW calibration Done
6845 01:00:16.880955 ==
6846 01:00:16.881370 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 01:00:16.887481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 01:00:16.887940 ==
6849 01:00:16.888375 RX Vref Scan: 0
6850 01:00:16.888678
6851 01:00:16.890750 RX Vref 0 -> 0, step: 1
6852 01:00:16.891276
6853 01:00:16.894212 RX Delay -410 -> 252, step: 16
6854 01:00:16.897610 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6855 01:00:16.900429 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6856 01:00:16.907642 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6857 01:00:16.910667 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6858 01:00:16.914059 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6859 01:00:16.917063 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6860 01:00:16.923898 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6861 01:00:16.927290 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6862 01:00:16.930717 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6863 01:00:16.933851 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6864 01:00:16.940978 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6865 01:00:16.943919 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6866 01:00:16.947637 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6867 01:00:16.950837 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6868 01:00:16.957317 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6869 01:00:16.960936 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6870 01:00:16.961449 ==
6871 01:00:16.963996 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 01:00:16.967193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 01:00:16.967644 ==
6874 01:00:16.970472 DQS Delay:
6875 01:00:16.970860 DQS0 = 43, DQS1 = 59
6876 01:00:16.974169 DQM Delay:
6877 01:00:16.974666 DQM0 = 9, DQM1 = 20
6878 01:00:16.974992 DQ Delay:
6879 01:00:16.977092 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6880 01:00:16.980640 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6881 01:00:16.983920 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6882 01:00:16.987449 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6883 01:00:16.987839
6884 01:00:16.988140
6885 01:00:16.988416 ==
6886 01:00:16.990960 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 01:00:16.993830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 01:00:16.997191 ==
6889 01:00:16.997588
6890 01:00:16.997893
6891 01:00:16.998205 TX Vref Scan disable
6892 01:00:17.000801 == TX Byte 0 ==
6893 01:00:17.003996 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6894 01:00:17.007581 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6895 01:00:17.010561 == TX Byte 1 ==
6896 01:00:17.013925 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6897 01:00:17.017437 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6898 01:00:17.017831 ==
6899 01:00:17.020867 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 01:00:17.024457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 01:00:17.027216 ==
6902 01:00:17.027627
6903 01:00:17.028113
6904 01:00:17.028419 TX Vref Scan disable
6905 01:00:17.030720 == TX Byte 0 ==
6906 01:00:17.034082 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6907 01:00:17.037590 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6908 01:00:17.040551 == TX Byte 1 ==
6909 01:00:17.044034 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6910 01:00:17.047480 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6911 01:00:17.047879
6912 01:00:17.048301 [DATLAT]
6913 01:00:17.050834 Freq=400, CH1 RK1
6914 01:00:17.051229
6915 01:00:17.053748 DATLAT Default: 0xe
6916 01:00:17.054276 0, 0xFFFF, sum = 0
6917 01:00:17.057105 1, 0xFFFF, sum = 0
6918 01:00:17.057674 2, 0xFFFF, sum = 0
6919 01:00:17.060921 3, 0xFFFF, sum = 0
6920 01:00:17.061326 4, 0xFFFF, sum = 0
6921 01:00:17.064274 5, 0xFFFF, sum = 0
6922 01:00:17.064674 6, 0xFFFF, sum = 0
6923 01:00:17.067705 7, 0xFFFF, sum = 0
6924 01:00:17.068230 8, 0xFFFF, sum = 0
6925 01:00:17.070551 9, 0xFFFF, sum = 0
6926 01:00:17.070953 10, 0xFFFF, sum = 0
6927 01:00:17.073696 11, 0xFFFF, sum = 0
6928 01:00:17.074133 12, 0xFFFF, sum = 0
6929 01:00:17.076989 13, 0x0, sum = 1
6930 01:00:17.077394 14, 0x0, sum = 2
6931 01:00:17.080909 15, 0x0, sum = 3
6932 01:00:17.081342 16, 0x0, sum = 4
6933 01:00:17.083946 best_step = 14
6934 01:00:17.084435
6935 01:00:17.084874 ==
6936 01:00:17.087143 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 01:00:17.090467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 01:00:17.090919 ==
6939 01:00:17.094433 RX Vref Scan: 0
6940 01:00:17.094948
6941 01:00:17.095322 RX Vref 0 -> 0, step: 1
6942 01:00:17.095692
6943 01:00:17.097121 RX Delay -359 -> 252, step: 8
6944 01:00:17.104985 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6945 01:00:17.108246 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6946 01:00:17.111698 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6947 01:00:17.115093 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6948 01:00:17.121781 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6949 01:00:17.124876 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6950 01:00:17.128707 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6951 01:00:17.131735 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6952 01:00:17.138584 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6953 01:00:17.141639 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6954 01:00:17.144965 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6955 01:00:17.148348 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6956 01:00:17.155698 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6957 01:00:17.158271 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6958 01:00:17.161742 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6959 01:00:17.165096 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6960 01:00:17.168580 ==
6961 01:00:17.171803 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 01:00:17.175022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 01:00:17.175604 ==
6964 01:00:17.176116 DQS Delay:
6965 01:00:17.178321 DQS0 = 52, DQS1 = 56
6966 01:00:17.178869 DQM Delay:
6967 01:00:17.181844 DQM0 = 13, DQM1 = 8
6968 01:00:17.182312 DQ Delay:
6969 01:00:17.185072 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6970 01:00:17.188559 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6971 01:00:17.191778 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6972 01:00:17.195239 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6973 01:00:17.195515
6974 01:00:17.195727
6975 01:00:17.202193 [DQSOSCAuto] RK1, (LSB)MR18= 0x738a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6976 01:00:17.205447 CH1 RK1: MR19=C0C, MR18=738A
6977 01:00:17.211819 CH1_RK1: MR19=0xC0C, MR18=0x738A, DQSOSC=392, MR23=63, INC=384, DEC=256
6978 01:00:17.215212 [RxdqsGatingPostProcess] freq 400
6979 01:00:17.218143 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6980 01:00:17.221876 best DQS0 dly(2T, 0.5T) = (0, 10)
6981 01:00:17.225283 best DQS1 dly(2T, 0.5T) = (0, 10)
6982 01:00:17.228640 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6983 01:00:17.231754 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6984 01:00:17.235272 best DQS0 dly(2T, 0.5T) = (0, 10)
6985 01:00:17.238468 best DQS1 dly(2T, 0.5T) = (0, 10)
6986 01:00:17.242339 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6987 01:00:17.245274 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6988 01:00:17.248814 Pre-setting of DQS Precalculation
6989 01:00:17.252287 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6990 01:00:17.258744 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6991 01:00:17.268964 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6992 01:00:17.269361
6993 01:00:17.269664
6994 01:00:17.269949 [Calibration Summary] 800 Mbps
6995 01:00:17.272134 CH 0, Rank 0
6996 01:00:17.272528 SW Impedance : PASS
6997 01:00:17.275247 DUTY Scan : NO K
6998 01:00:17.278936 ZQ Calibration : PASS
6999 01:00:17.279331 Jitter Meter : NO K
7000 01:00:17.282133 CBT Training : PASS
7001 01:00:17.285123 Write leveling : PASS
7002 01:00:17.285547 RX DQS gating : PASS
7003 01:00:17.289322 RX DQ/DQS(RDDQC) : PASS
7004 01:00:17.292270 TX DQ/DQS : PASS
7005 01:00:17.292834 RX DATLAT : PASS
7006 01:00:17.295458 RX DQ/DQS(Engine): PASS
7007 01:00:17.298671 TX OE : NO K
7008 01:00:17.299149 All Pass.
7009 01:00:17.299512
7010 01:00:17.299962 CH 0, Rank 1
7011 01:00:17.301884 SW Impedance : PASS
7012 01:00:17.305303 DUTY Scan : NO K
7013 01:00:17.305698 ZQ Calibration : PASS
7014 01:00:17.308785 Jitter Meter : NO K
7015 01:00:17.312245 CBT Training : PASS
7016 01:00:17.312642 Write leveling : NO K
7017 01:00:17.315594 RX DQS gating : PASS
7018 01:00:17.315990 RX DQ/DQS(RDDQC) : PASS
7019 01:00:17.318981 TX DQ/DQS : PASS
7020 01:00:17.321878 RX DATLAT : PASS
7021 01:00:17.322325 RX DQ/DQS(Engine): PASS
7022 01:00:17.325520 TX OE : NO K
7023 01:00:17.326125 All Pass.
7024 01:00:17.326452
7025 01:00:17.328651 CH 1, Rank 0
7026 01:00:17.329045 SW Impedance : PASS
7027 01:00:17.332067 DUTY Scan : NO K
7028 01:00:17.335436 ZQ Calibration : PASS
7029 01:00:17.335838 Jitter Meter : NO K
7030 01:00:17.338560 CBT Training : PASS
7031 01:00:17.342079 Write leveling : PASS
7032 01:00:17.342467 RX DQS gating : PASS
7033 01:00:17.345491 RX DQ/DQS(RDDQC) : PASS
7034 01:00:17.349027 TX DQ/DQS : PASS
7035 01:00:17.349417 RX DATLAT : PASS
7036 01:00:17.352377 RX DQ/DQS(Engine): PASS
7037 01:00:17.352802 TX OE : NO K
7038 01:00:17.355278 All Pass.
7039 01:00:17.355758
7040 01:00:17.356170 CH 1, Rank 1
7041 01:00:17.358723 SW Impedance : PASS
7042 01:00:17.359245 DUTY Scan : NO K
7043 01:00:17.362248 ZQ Calibration : PASS
7044 01:00:17.365628 Jitter Meter : NO K
7045 01:00:17.366177 CBT Training : PASS
7046 01:00:17.368917 Write leveling : NO K
7047 01:00:17.371867 RX DQS gating : PASS
7048 01:00:17.372342 RX DQ/DQS(RDDQC) : PASS
7049 01:00:17.375469 TX DQ/DQS : PASS
7050 01:00:17.378841 RX DATLAT : PASS
7051 01:00:17.379354 RX DQ/DQS(Engine): PASS
7052 01:00:17.381794 TX OE : NO K
7053 01:00:17.382358 All Pass.
7054 01:00:17.382806
7055 01:00:17.385753 DramC Write-DBI off
7056 01:00:17.388816 PER_BANK_REFRESH: Hybrid Mode
7057 01:00:17.389211 TX_TRACKING: ON
7058 01:00:17.398776 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7059 01:00:17.402851 [FAST_K] Save calibration result to emmc
7060 01:00:17.405842 dramc_set_vcore_voltage set vcore to 725000
7061 01:00:17.408966 Read voltage for 1600, 0
7062 01:00:17.409440 Vio18 = 0
7063 01:00:17.409746 Vcore = 725000
7064 01:00:17.412248 Vdram = 0
7065 01:00:17.412644 Vddq = 0
7066 01:00:17.412952 Vmddr = 0
7067 01:00:17.419129 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7068 01:00:17.422371 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7069 01:00:17.426148 MEM_TYPE=3, freq_sel=13
7070 01:00:17.429176 sv_algorithm_assistance_LP4_3733
7071 01:00:17.432611 ============ PULL DRAM RESETB DOWN ============
7072 01:00:17.435675 ========== PULL DRAM RESETB DOWN end =========
7073 01:00:17.442165 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7074 01:00:17.446253 ===================================
7075 01:00:17.446650 LPDDR4 DRAM CONFIGURATION
7076 01:00:17.448698 ===================================
7077 01:00:17.452285 EX_ROW_EN[0] = 0x0
7078 01:00:17.456009 EX_ROW_EN[1] = 0x0
7079 01:00:17.456481 LP4Y_EN = 0x0
7080 01:00:17.458659 WORK_FSP = 0x1
7081 01:00:17.459054 WL = 0x5
7082 01:00:17.462392 RL = 0x5
7083 01:00:17.462940 BL = 0x2
7084 01:00:17.465244 RPST = 0x0
7085 01:00:17.465641 RD_PRE = 0x0
7086 01:00:17.469189 WR_PRE = 0x1
7087 01:00:17.469663 WR_PST = 0x1
7088 01:00:17.472196 DBI_WR = 0x0
7089 01:00:17.472719 DBI_RD = 0x0
7090 01:00:17.475859 OTF = 0x1
7091 01:00:17.479109 ===================================
7092 01:00:17.482601 ===================================
7093 01:00:17.483076 ANA top config
7094 01:00:17.486198 ===================================
7095 01:00:17.489526 DLL_ASYNC_EN = 0
7096 01:00:17.492463 ALL_SLAVE_EN = 0
7097 01:00:17.492912 NEW_RANK_MODE = 1
7098 01:00:17.495722 DLL_IDLE_MODE = 1
7099 01:00:17.498671 LP45_APHY_COMB_EN = 1
7100 01:00:17.502453 TX_ODT_DIS = 0
7101 01:00:17.505466 NEW_8X_MODE = 1
7102 01:00:17.508910 ===================================
7103 01:00:17.511914 ===================================
7104 01:00:17.512283 data_rate = 3200
7105 01:00:17.515782 CKR = 1
7106 01:00:17.519086 DQ_P2S_RATIO = 8
7107 01:00:17.522530 ===================================
7108 01:00:17.525895 CA_P2S_RATIO = 8
7109 01:00:17.528909 DQ_CA_OPEN = 0
7110 01:00:17.532437 DQ_SEMI_OPEN = 0
7111 01:00:17.532831 CA_SEMI_OPEN = 0
7112 01:00:17.535973 CA_FULL_RATE = 0
7113 01:00:17.539341 DQ_CKDIV4_EN = 0
7114 01:00:17.542583 CA_CKDIV4_EN = 0
7115 01:00:17.545736 CA_PREDIV_EN = 0
7116 01:00:17.549207 PH8_DLY = 12
7117 01:00:17.549676 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7118 01:00:17.552496 DQ_AAMCK_DIV = 4
7119 01:00:17.555859 CA_AAMCK_DIV = 4
7120 01:00:17.559106 CA_ADMCK_DIV = 4
7121 01:00:17.562703 DQ_TRACK_CA_EN = 0
7122 01:00:17.565700 CA_PICK = 1600
7123 01:00:17.566135 CA_MCKIO = 1600
7124 01:00:17.569308 MCKIO_SEMI = 0
7125 01:00:17.572366 PLL_FREQ = 3068
7126 01:00:17.575542 DQ_UI_PI_RATIO = 32
7127 01:00:17.578822 CA_UI_PI_RATIO = 0
7128 01:00:17.582492 ===================================
7129 01:00:17.585825 ===================================
7130 01:00:17.588963 memory_type:LPDDR4
7131 01:00:17.589429 GP_NUM : 10
7132 01:00:17.592373 SRAM_EN : 1
7133 01:00:17.592841 MD32_EN : 0
7134 01:00:17.595787 ===================================
7135 01:00:17.598943 [ANA_INIT] >>>>>>>>>>>>>>
7136 01:00:17.602847 <<<<<< [CONFIGURE PHASE]: ANA_TX
7137 01:00:17.606044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7138 01:00:17.609290 ===================================
7139 01:00:17.612667 data_rate = 3200,PCW = 0X7600
7140 01:00:17.615357 ===================================
7141 01:00:17.618943 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7142 01:00:17.622446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7143 01:00:17.629018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7144 01:00:17.632475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7145 01:00:17.635993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7146 01:00:17.642567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7147 01:00:17.643028 [ANA_INIT] flow start
7148 01:00:17.646071 [ANA_INIT] PLL >>>>>>>>
7149 01:00:17.646472 [ANA_INIT] PLL <<<<<<<<
7150 01:00:17.649795 [ANA_INIT] MIDPI >>>>>>>>
7151 01:00:17.652213 [ANA_INIT] MIDPI <<<<<<<<
7152 01:00:17.655889 [ANA_INIT] DLL >>>>>>>>
7153 01:00:17.656364 [ANA_INIT] DLL <<<<<<<<
7154 01:00:17.658869 [ANA_INIT] flow end
7155 01:00:17.662453 ============ LP4 DIFF to SE enter ============
7156 01:00:17.665730 ============ LP4 DIFF to SE exit ============
7157 01:00:17.669483 [ANA_INIT] <<<<<<<<<<<<<
7158 01:00:17.672715 [Flow] Enable top DCM control >>>>>
7159 01:00:17.676231 [Flow] Enable top DCM control <<<<<
7160 01:00:17.679262 Enable DLL master slave shuffle
7161 01:00:17.686361 ==============================================================
7162 01:00:17.686838 Gating Mode config
7163 01:00:17.693102 ==============================================================
7164 01:00:17.693582 Config description:
7165 01:00:17.702987 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7166 01:00:17.709471 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7167 01:00:17.715574 SELPH_MODE 0: By rank 1: By Phase
7168 01:00:17.718956 ==============================================================
7169 01:00:17.722731 GAT_TRACK_EN = 1
7170 01:00:17.725879 RX_GATING_MODE = 2
7171 01:00:17.729052 RX_GATING_TRACK_MODE = 2
7172 01:00:17.732753 SELPH_MODE = 1
7173 01:00:17.736562 PICG_EARLY_EN = 1
7174 01:00:17.739868 VALID_LAT_VALUE = 1
7175 01:00:17.742292 ==============================================================
7176 01:00:17.746153 Enter into Gating configuration >>>>
7177 01:00:17.749802 Exit from Gating configuration <<<<
7178 01:00:17.752832 Enter into DVFS_PRE_config >>>>>
7179 01:00:17.766182 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7180 01:00:17.766683 Exit from DVFS_PRE_config <<<<<
7181 01:00:17.769101 Enter into PICG configuration >>>>
7182 01:00:17.772451 Exit from PICG configuration <<<<
7183 01:00:17.775834 [RX_INPUT] configuration >>>>>
7184 01:00:17.779422 [RX_INPUT] configuration <<<<<
7185 01:00:17.785941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7186 01:00:17.788912 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7187 01:00:17.796265 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7188 01:00:17.802535 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7189 01:00:17.809347 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7190 01:00:17.815746 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7191 01:00:17.819226 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7192 01:00:17.822449 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7193 01:00:17.825785 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7194 01:00:17.832381 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7195 01:00:17.835694 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7196 01:00:17.839607 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7197 01:00:17.842576 ===================================
7198 01:00:17.846075 LPDDR4 DRAM CONFIGURATION
7199 01:00:17.849345 ===================================
7200 01:00:17.849739 EX_ROW_EN[0] = 0x0
7201 01:00:17.852898 EX_ROW_EN[1] = 0x0
7202 01:00:17.853364 LP4Y_EN = 0x0
7203 01:00:17.856470 WORK_FSP = 0x1
7204 01:00:17.859377 WL = 0x5
7205 01:00:17.859878 RL = 0x5
7206 01:00:17.862483 BL = 0x2
7207 01:00:17.862993 RPST = 0x0
7208 01:00:17.865893 RD_PRE = 0x0
7209 01:00:17.866341 WR_PRE = 0x1
7210 01:00:17.869339 WR_PST = 0x1
7211 01:00:17.869734 DBI_WR = 0x0
7212 01:00:17.872401 DBI_RD = 0x0
7213 01:00:17.872788 OTF = 0x1
7214 01:00:17.876116 ===================================
7215 01:00:17.879462 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7216 01:00:17.885653 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7217 01:00:17.889262 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7218 01:00:17.892523 ===================================
7219 01:00:17.895965 LPDDR4 DRAM CONFIGURATION
7220 01:00:17.899120 ===================================
7221 01:00:17.899583 EX_ROW_EN[0] = 0x10
7222 01:00:17.902793 EX_ROW_EN[1] = 0x0
7223 01:00:17.903263 LP4Y_EN = 0x0
7224 01:00:17.906305 WORK_FSP = 0x1
7225 01:00:17.906704 WL = 0x5
7226 01:00:17.909710 RL = 0x5
7227 01:00:17.910142 BL = 0x2
7228 01:00:17.912704 RPST = 0x0
7229 01:00:17.913100 RD_PRE = 0x0
7230 01:00:17.915946 WR_PRE = 0x1
7231 01:00:17.916342 WR_PST = 0x1
7232 01:00:17.919193 DBI_WR = 0x0
7233 01:00:17.919607 DBI_RD = 0x0
7234 01:00:17.922602 OTF = 0x1
7235 01:00:17.926259 ===================================
7236 01:00:17.932516 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7237 01:00:17.932916 ==
7238 01:00:17.936002 Dram Type= 6, Freq= 0, CH_0, rank 0
7239 01:00:17.939750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7240 01:00:17.940229 ==
7241 01:00:17.942712 [Duty_Offset_Calibration]
7242 01:00:17.943106 B0:2 B1:-1 CA:1
7243 01:00:17.943413
7244 01:00:17.945950 [DutyScan_Calibration_Flow] k_type=0
7245 01:00:17.956576
7246 01:00:17.957044 ==CLK 0==
7247 01:00:17.960000 Final CLK duty delay cell = -4
7248 01:00:17.963125 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7249 01:00:17.966522 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7250 01:00:17.969911 [-4] AVG Duty = 4937%(X100)
7251 01:00:17.970424
7252 01:00:17.973393 CH0 CLK Duty spec in!! Max-Min= 187%
7253 01:00:17.976519 [DutyScan_Calibration_Flow] ====Done====
7254 01:00:17.976994
7255 01:00:17.979523 [DutyScan_Calibration_Flow] k_type=1
7256 01:00:17.995916
7257 01:00:17.996300 ==DQS 0 ==
7258 01:00:17.999387 Final DQS duty delay cell = 0
7259 01:00:18.002542 [0] MAX Duty = 5125%(X100), DQS PI = 20
7260 01:00:18.005841 [0] MIN Duty = 5000%(X100), DQS PI = 14
7261 01:00:18.009408 [0] AVG Duty = 5062%(X100)
7262 01:00:18.009940
7263 01:00:18.010398 ==DQS 1 ==
7264 01:00:18.012684 Final DQS duty delay cell = -4
7265 01:00:18.015567 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7266 01:00:18.019252 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7267 01:00:18.022199 [-4] AVG Duty = 5046%(X100)
7268 01:00:18.022812
7269 01:00:18.025767 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7270 01:00:18.026404
7271 01:00:18.028864 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7272 01:00:18.032454 [DutyScan_Calibration_Flow] ====Done====
7273 01:00:18.032876
7274 01:00:18.035776 [DutyScan_Calibration_Flow] k_type=3
7275 01:00:18.052836
7276 01:00:18.053021 ==DQM 0 ==
7277 01:00:18.056311 Final DQM duty delay cell = 0
7278 01:00:18.059633 [0] MAX Duty = 5000%(X100), DQS PI = 18
7279 01:00:18.062751 [0] MIN Duty = 4875%(X100), DQS PI = 6
7280 01:00:18.066315 [0] AVG Duty = 4937%(X100)
7281 01:00:18.066739
7282 01:00:18.067116 ==DQM 1 ==
7283 01:00:18.069766 Final DQM duty delay cell = 0
7284 01:00:18.073173 [0] MAX Duty = 5156%(X100), DQS PI = 28
7285 01:00:18.076461 [0] MIN Duty = 4969%(X100), DQS PI = 20
7286 01:00:18.079867 [0] AVG Duty = 5062%(X100)
7287 01:00:18.080257
7288 01:00:18.082952 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7289 01:00:18.083406
7290 01:00:18.086422 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7291 01:00:18.089738 [DutyScan_Calibration_Flow] ====Done====
7292 01:00:18.090157
7293 01:00:18.093390 [DutyScan_Calibration_Flow] k_type=2
7294 01:00:18.109573
7295 01:00:18.109723 ==DQ 0 ==
7296 01:00:18.112525 Final DQ duty delay cell = -4
7297 01:00:18.115961 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7298 01:00:18.119215 [-4] MIN Duty = 4844%(X100), DQS PI = 20
7299 01:00:18.122796 [-4] AVG Duty = 4922%(X100)
7300 01:00:18.122902
7301 01:00:18.122985 ==DQ 1 ==
7302 01:00:18.126162 Final DQ duty delay cell = 0
7303 01:00:18.129114 [0] MAX Duty = 5031%(X100), DQS PI = 30
7304 01:00:18.132660 [0] MIN Duty = 4907%(X100), DQS PI = 18
7305 01:00:18.135829 [0] AVG Duty = 4969%(X100)
7306 01:00:18.135916
7307 01:00:18.139116 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7308 01:00:18.139201
7309 01:00:18.142446 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7310 01:00:18.145838 [DutyScan_Calibration_Flow] ====Done====
7311 01:00:18.145916 ==
7312 01:00:18.149253 Dram Type= 6, Freq= 0, CH_1, rank 0
7313 01:00:18.152636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7314 01:00:18.152714 ==
7315 01:00:18.155908 [Duty_Offset_Calibration]
7316 01:00:18.155985 B0:1 B1:1 CA:2
7317 01:00:18.156044
7318 01:00:18.158952 [DutyScan_Calibration_Flow] k_type=0
7319 01:00:18.169834
7320 01:00:18.169911 ==CLK 0==
7321 01:00:18.173531 Final CLK duty delay cell = 0
7322 01:00:18.176844 [0] MAX Duty = 5187%(X100), DQS PI = 24
7323 01:00:18.180152 [0] MIN Duty = 4969%(X100), DQS PI = 40
7324 01:00:18.180292 [0] AVG Duty = 5078%(X100)
7325 01:00:18.180357
7326 01:00:18.183394 CH1 CLK Duty spec in!! Max-Min= 218%
7327 01:00:18.189994 [DutyScan_Calibration_Flow] ====Done====
7328 01:00:18.190150
7329 01:00:18.193623 [DutyScan_Calibration_Flow] k_type=1
7330 01:00:18.209767
7331 01:00:18.209956 ==DQS 0 ==
7332 01:00:18.213132 Final DQS duty delay cell = 0
7333 01:00:18.216714 [0] MAX Duty = 5031%(X100), DQS PI = 20
7334 01:00:18.219925 [0] MIN Duty = 4813%(X100), DQS PI = 50
7335 01:00:18.222849 [0] AVG Duty = 4922%(X100)
7336 01:00:18.223048
7337 01:00:18.223177 ==DQS 1 ==
7338 01:00:18.226312 Final DQS duty delay cell = 0
7339 01:00:18.230057 [0] MAX Duty = 5031%(X100), DQS PI = 56
7340 01:00:18.233083 [0] MIN Duty = 4938%(X100), DQS PI = 12
7341 01:00:18.236513 [0] AVG Duty = 4984%(X100)
7342 01:00:18.236880
7343 01:00:18.239867 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7344 01:00:18.240234
7345 01:00:18.243674 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7346 01:00:18.246570 [DutyScan_Calibration_Flow] ====Done====
7347 01:00:18.246968
7348 01:00:18.249677 [DutyScan_Calibration_Flow] k_type=3
7349 01:00:18.267000
7350 01:00:18.267470 ==DQM 0 ==
7351 01:00:18.270517 Final DQM duty delay cell = 0
7352 01:00:18.273546 [0] MAX Duty = 5124%(X100), DQS PI = 20
7353 01:00:18.277520 [0] MIN Duty = 4844%(X100), DQS PI = 50
7354 01:00:18.280538 [0] AVG Duty = 4984%(X100)
7355 01:00:18.281012
7356 01:00:18.281320 ==DQM 1 ==
7357 01:00:18.283427 Final DQM duty delay cell = 0
7358 01:00:18.286787 [0] MAX Duty = 5156%(X100), DQS PI = 60
7359 01:00:18.290072 [0] MIN Duty = 4907%(X100), DQS PI = 18
7360 01:00:18.294011 [0] AVG Duty = 5031%(X100)
7361 01:00:18.294489
7362 01:00:18.297066 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7363 01:00:18.297537
7364 01:00:18.300317 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7365 01:00:18.303763 [DutyScan_Calibration_Flow] ====Done====
7366 01:00:18.304244
7367 01:00:18.306784 [DutyScan_Calibration_Flow] k_type=2
7368 01:00:18.324218
7369 01:00:18.324725 ==DQ 0 ==
7370 01:00:18.327211 Final DQ duty delay cell = 0
7371 01:00:18.330197 [0] MAX Duty = 5156%(X100), DQS PI = 20
7372 01:00:18.333790 [0] MIN Duty = 4907%(X100), DQS PI = 52
7373 01:00:18.334367 [0] AVG Duty = 5031%(X100)
7374 01:00:18.334934
7375 01:00:18.337161 ==DQ 1 ==
7376 01:00:18.340543 Final DQ duty delay cell = 0
7377 01:00:18.343653 [0] MAX Duty = 5093%(X100), DQS PI = 6
7378 01:00:18.347099 [0] MIN Duty = 5031%(X100), DQS PI = 2
7379 01:00:18.347496 [0] AVG Duty = 5062%(X100)
7380 01:00:18.347800
7381 01:00:18.350487 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7382 01:00:18.350883
7383 01:00:18.353963 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7384 01:00:18.357159 [DutyScan_Calibration_Flow] ====Done====
7385 01:00:18.362649 nWR fixed to 30
7386 01:00:18.365890 [ModeRegInit_LP4] CH0 RK0
7387 01:00:18.366320 [ModeRegInit_LP4] CH0 RK1
7388 01:00:18.369282 [ModeRegInit_LP4] CH1 RK0
7389 01:00:18.372961 [ModeRegInit_LP4] CH1 RK1
7390 01:00:18.373433 match AC timing 5
7391 01:00:18.379631 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7392 01:00:18.382943 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7393 01:00:18.386206 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7394 01:00:18.392813 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7395 01:00:18.396314 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7396 01:00:18.396803 [MiockJmeterHQA]
7397 01:00:18.397115
7398 01:00:18.399409 [DramcMiockJmeter] u1RxGatingPI = 0
7399 01:00:18.402774 0 : 4363, 4137
7400 01:00:18.403252 4 : 4257, 4029
7401 01:00:18.406090 8 : 4363, 4137
7402 01:00:18.406571 12 : 4252, 4027
7403 01:00:18.409410 16 : 4363, 4137
7404 01:00:18.409893 20 : 4253, 4026
7405 01:00:18.410245 24 : 4252, 4027
7406 01:00:18.413233 28 : 4252, 4027
7407 01:00:18.413713 32 : 4253, 4027
7408 01:00:18.415977 36 : 4252, 4027
7409 01:00:18.416378 40 : 4363, 4137
7410 01:00:18.418954 44 : 4363, 4137
7411 01:00:18.419353 48 : 4252, 4027
7412 01:00:18.422344 52 : 4253, 4026
7413 01:00:18.422746 56 : 4252, 4027
7414 01:00:18.423065 60 : 4250, 4027
7415 01:00:18.425802 64 : 4253, 4026
7416 01:00:18.426235 68 : 4360, 4138
7417 01:00:18.429229 72 : 4250, 4026
7418 01:00:18.429628 76 : 4250, 4027
7419 01:00:18.432789 80 : 4250, 4027
7420 01:00:18.433264 84 : 4250, 4027
7421 01:00:18.433580 88 : 4250, 4027
7422 01:00:18.436047 92 : 4360, 4137
7423 01:00:18.436449 96 : 4361, 3464
7424 01:00:18.439599 100 : 4250, 0
7425 01:00:18.440001 104 : 4361, 0
7426 01:00:18.440313 108 : 4250, 0
7427 01:00:18.442892 112 : 4250, 0
7428 01:00:18.443292 116 : 4250, 0
7429 01:00:18.445927 120 : 4252, 0
7430 01:00:18.446368 124 : 4253, 0
7431 01:00:18.446687 128 : 4250, 0
7432 01:00:18.449470 132 : 4252, 0
7433 01:00:18.449871 136 : 4363, 0
7434 01:00:18.452401 140 : 4250, 0
7435 01:00:18.452803 144 : 4250, 0
7436 01:00:18.453118 148 : 4255, 0
7437 01:00:18.456011 152 : 4360, 0
7438 01:00:18.456490 156 : 4361, 0
7439 01:00:18.459143 160 : 4250, 0
7440 01:00:18.459545 164 : 4250, 0
7441 01:00:18.459858 168 : 4250, 0
7442 01:00:18.462659 172 : 4253, 0
7443 01:00:18.463060 176 : 4250, 0
7444 01:00:18.463371 180 : 4250, 0
7445 01:00:18.466083 184 : 4252, 0
7446 01:00:18.466487 188 : 4363, 0
7447 01:00:18.469103 192 : 4250, 0
7448 01:00:18.469559 196 : 4250, 0
7449 01:00:18.469881 200 : 4253, 0
7450 01:00:18.472648 204 : 4360, 0
7451 01:00:18.473125 208 : 4361, 0
7452 01:00:18.476576 212 : 4252, 41
7453 01:00:18.477053 216 : 4361, 3522
7454 01:00:18.479344 220 : 4250, 4027
7455 01:00:18.479822 224 : 4250, 4027
7456 01:00:18.480176 228 : 4363, 4140
7457 01:00:18.482429 232 : 4250, 4027
7458 01:00:18.482913 236 : 4250, 4027
7459 01:00:18.486109 240 : 4250, 4026
7460 01:00:18.486592 244 : 4250, 4027
7461 01:00:18.489642 248 : 4250, 4027
7462 01:00:18.490155 252 : 4249, 4027
7463 01:00:18.492715 256 : 4360, 4137
7464 01:00:18.493115 260 : 4250, 4027
7465 01:00:18.496090 264 : 4250, 4027
7466 01:00:18.496581 268 : 4361, 4138
7467 01:00:18.499089 272 : 4249, 4027
7468 01:00:18.499492 276 : 4250, 4027
7469 01:00:18.499803 280 : 4361, 4137
7470 01:00:18.502760 284 : 4250, 4027
7471 01:00:18.503162 288 : 4251, 4027
7472 01:00:18.505819 292 : 4250, 4026
7473 01:00:18.506246 296 : 4250, 4026
7474 01:00:18.509314 300 : 4250, 4027
7475 01:00:18.509788 304 : 4250, 4027
7476 01:00:18.512978 308 : 4360, 4137
7477 01:00:18.513382 312 : 4250, 4026
7478 01:00:18.515731 316 : 4250, 4027
7479 01:00:18.516131 320 : 4363, 4140
7480 01:00:18.519121 324 : 4249, 4027
7481 01:00:18.519520 328 : 4250, 4026
7482 01:00:18.522405 332 : 4361, 3161
7483 01:00:18.522805 336 : 4250, 27
7484 01:00:18.523117
7485 01:00:18.526141 MIOCK jitter meter ch=0
7486 01:00:18.526612
7487 01:00:18.529253 1T = (336-100) = 236 dly cells
7488 01:00:18.532693 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7489 01:00:18.533090 ==
7490 01:00:18.536203 Dram Type= 6, Freq= 0, CH_0, rank 0
7491 01:00:18.542630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7492 01:00:18.543138 ==
7493 01:00:18.545963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7494 01:00:18.549275 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7495 01:00:18.556405 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7496 01:00:18.562388 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7497 01:00:18.570555 [CA 0] Center 44 (14~75) winsize 62
7498 01:00:18.573834 [CA 1] Center 44 (14~75) winsize 62
7499 01:00:18.576721 [CA 2] Center 40 (11~69) winsize 59
7500 01:00:18.580471 [CA 3] Center 39 (10~69) winsize 60
7501 01:00:18.583688 [CA 4] Center 38 (8~68) winsize 61
7502 01:00:18.586964 [CA 5] Center 37 (7~67) winsize 61
7503 01:00:18.587452
7504 01:00:18.590444 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7505 01:00:18.590923
7506 01:00:18.594066 [CATrainingPosCal] consider 1 rank data
7507 01:00:18.596613 u2DelayCellTimex100 = 275/100 ps
7508 01:00:18.603437 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7509 01:00:18.606920 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7510 01:00:18.610485 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7511 01:00:18.613369 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7512 01:00:18.616613 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7513 01:00:18.620372 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7514 01:00:18.620846
7515 01:00:18.623566 CA PerBit enable=1, Macro0, CA PI delay=37
7516 01:00:18.623962
7517 01:00:18.627277 [CBTSetCACLKResult] CA Dly = 37
7518 01:00:18.630421 CS Dly: 10 (0~41)
7519 01:00:18.633819 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7520 01:00:18.637067 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7521 01:00:18.637462 ==
7522 01:00:18.640242 Dram Type= 6, Freq= 0, CH_0, rank 1
7523 01:00:18.643544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 01:00:18.643945 ==
7525 01:00:18.650677 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 01:00:18.653689 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 01:00:18.660969 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 01:00:18.664181 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 01:00:18.673941 [CA 0] Center 44 (14~75) winsize 62
7530 01:00:18.677232 [CA 1] Center 44 (14~75) winsize 62
7531 01:00:18.680559 [CA 2] Center 40 (11~69) winsize 59
7532 01:00:18.684036 [CA 3] Center 39 (10~69) winsize 60
7533 01:00:18.687409 [CA 4] Center 37 (8~67) winsize 60
7534 01:00:18.690508 [CA 5] Center 37 (7~67) winsize 61
7535 01:00:18.690962
7536 01:00:18.694014 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7537 01:00:18.694527
7538 01:00:18.697166 [CATrainingPosCal] consider 2 rank data
7539 01:00:18.700704 u2DelayCellTimex100 = 275/100 ps
7540 01:00:18.707218 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7541 01:00:18.710772 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7542 01:00:18.714201 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7543 01:00:18.717070 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7544 01:00:18.720477 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7545 01:00:18.723992 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7546 01:00:18.724388
7547 01:00:18.727637 CA PerBit enable=1, Macro0, CA PI delay=37
7548 01:00:18.728110
7549 01:00:18.730545 [CBTSetCACLKResult] CA Dly = 37
7550 01:00:18.733650 CS Dly: 11 (0~44)
7551 01:00:18.736931 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 01:00:18.740167 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 01:00:18.740563
7554 01:00:18.743603 ----->DramcWriteLeveling(PI) begin...
7555 01:00:18.744002 ==
7556 01:00:18.747964 Dram Type= 6, Freq= 0, CH_0, rank 0
7557 01:00:18.754077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 01:00:18.754591 ==
7559 01:00:18.757482 Write leveling (Byte 0): 36 => 36
7560 01:00:18.757951 Write leveling (Byte 1): 26 => 26
7561 01:00:18.760940 DramcWriteLeveling(PI) end<-----
7562 01:00:18.761413
7563 01:00:18.761725 ==
7564 01:00:18.764101 Dram Type= 6, Freq= 0, CH_0, rank 0
7565 01:00:18.771334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7566 01:00:18.771819 ==
7567 01:00:18.772138 [Gating] SW mode calibration
7568 01:00:18.780876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7569 01:00:18.784359 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7570 01:00:18.790816 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 01:00:18.793629 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 01:00:18.797264 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 01:00:18.804399 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 01:00:18.807435 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 01:00:18.810933 1 4 20 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7576 01:00:18.814441 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
7577 01:00:18.821017 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7578 01:00:18.823980 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7579 01:00:18.827277 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 01:00:18.834169 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 01:00:18.837683 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 01:00:18.840634 1 5 16 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
7583 01:00:18.846792 1 5 20 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
7584 01:00:18.850680 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7585 01:00:18.853856 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 01:00:18.860768 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 01:00:18.864027 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 01:00:18.867630 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 01:00:18.874396 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 01:00:18.877279 1 6 16 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7591 01:00:18.880612 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7592 01:00:18.887142 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7593 01:00:18.890351 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 01:00:18.894448 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 01:00:18.897406 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 01:00:18.904173 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 01:00:18.907631 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 01:00:18.910965 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 01:00:18.917239 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7600 01:00:18.920574 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7601 01:00:18.923832 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 01:00:18.930752 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 01:00:18.934107 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 01:00:18.937588 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 01:00:18.944063 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 01:00:18.947308 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 01:00:18.950523 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 01:00:18.957877 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 01:00:18.960797 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 01:00:18.963990 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 01:00:18.970744 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 01:00:18.973933 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 01:00:18.977932 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7614 01:00:18.983933 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7615 01:00:18.987538 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7616 01:00:18.990698 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 01:00:18.993937 Total UI for P1: 0, mck2ui 16
7618 01:00:18.997828 best dqsien dly found for B0: ( 1, 9, 16)
7619 01:00:19.000448 Total UI for P1: 0, mck2ui 16
7620 01:00:19.003783 best dqsien dly found for B1: ( 1, 9, 18)
7621 01:00:19.007445 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7622 01:00:19.010712 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7623 01:00:19.011107
7624 01:00:19.013763 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7625 01:00:19.020468 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7626 01:00:19.020866 [Gating] SW calibration Done
7627 01:00:19.021174 ==
7628 01:00:19.023802 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 01:00:19.030360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 01:00:19.030757 ==
7631 01:00:19.031062 RX Vref Scan: 0
7632 01:00:19.031341
7633 01:00:19.034154 RX Vref 0 -> 0, step: 1
7634 01:00:19.034567
7635 01:00:19.037204 RX Delay 0 -> 252, step: 8
7636 01:00:19.041021 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7637 01:00:19.044009 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7638 01:00:19.047561 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7639 01:00:19.050522 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7640 01:00:19.057198 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7641 01:00:19.060549 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7642 01:00:19.064175 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7643 01:00:19.067735 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7644 01:00:19.070931 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7645 01:00:19.077213 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7646 01:00:19.080978 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7647 01:00:19.084114 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7648 01:00:19.087791 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7649 01:00:19.090579 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7650 01:00:19.097673 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7651 01:00:19.101185 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7652 01:00:19.101660 ==
7653 01:00:19.104505 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 01:00:19.107738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 01:00:19.108138 ==
7656 01:00:19.108445 DQS Delay:
7657 01:00:19.111201 DQS0 = 0, DQS1 = 0
7658 01:00:19.111671 DQM Delay:
7659 01:00:19.114134 DQM0 = 132, DQM1 = 124
7660 01:00:19.114785 DQ Delay:
7661 01:00:19.117533 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7662 01:00:19.121001 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7663 01:00:19.124316 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7664 01:00:19.127420 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7665 01:00:19.130922
7666 01:00:19.131316
7667 01:00:19.131623 ==
7668 01:00:19.134084 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 01:00:19.137648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 01:00:19.138318 ==
7671 01:00:19.138855
7672 01:00:19.139035
7673 01:00:19.140644 TX Vref Scan disable
7674 01:00:19.140737 == TX Byte 0 ==
7675 01:00:19.147062 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7676 01:00:19.150388 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7677 01:00:19.150535 == TX Byte 1 ==
7678 01:00:19.157246 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7679 01:00:19.160588 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7680 01:00:19.160697 ==
7681 01:00:19.164152 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 01:00:19.167584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 01:00:19.167673 ==
7684 01:00:19.181970
7685 01:00:19.185638 TX Vref early break, caculate TX vref
7686 01:00:19.189179 TX Vref=16, minBit 1, minWin=21, winSum=356
7687 01:00:19.191706 TX Vref=18, minBit 1, minWin=22, winSum=369
7688 01:00:19.195550 TX Vref=20, minBit 7, minWin=22, winSum=378
7689 01:00:19.198679 TX Vref=22, minBit 1, minWin=23, winSum=387
7690 01:00:19.201601 TX Vref=24, minBit 1, minWin=24, winSum=402
7691 01:00:19.208550 TX Vref=26, minBit 3, minWin=25, winSum=412
7692 01:00:19.212389 TX Vref=28, minBit 4, minWin=25, winSum=420
7693 01:00:19.215617 TX Vref=30, minBit 1, minWin=26, winSum=420
7694 01:00:19.218827 TX Vref=32, minBit 4, minWin=24, winSum=411
7695 01:00:19.222116 TX Vref=34, minBit 9, minWin=23, winSum=397
7696 01:00:19.228675 [TxChooseVref] Worse bit 1, Min win 26, Win sum 420, Final Vref 30
7697 01:00:19.229071
7698 01:00:19.232705 Final TX Range 0 Vref 30
7699 01:00:19.233187
7700 01:00:19.233498 ==
7701 01:00:19.235555 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 01:00:19.238778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 01:00:19.239360 ==
7704 01:00:19.239751
7705 01:00:19.240044
7706 01:00:19.242171 TX Vref Scan disable
7707 01:00:19.249025 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7708 01:00:19.249682 == TX Byte 0 ==
7709 01:00:19.252447 u2DelayCellOfst[0]=14 cells (4 PI)
7710 01:00:19.256301 u2DelayCellOfst[1]=21 cells (6 PI)
7711 01:00:19.259556 u2DelayCellOfst[2]=10 cells (3 PI)
7712 01:00:19.262118 u2DelayCellOfst[3]=10 cells (3 PI)
7713 01:00:19.265719 u2DelayCellOfst[4]=7 cells (2 PI)
7714 01:00:19.269106 u2DelayCellOfst[5]=0 cells (0 PI)
7715 01:00:19.269691 u2DelayCellOfst[6]=17 cells (5 PI)
7716 01:00:19.272706 u2DelayCellOfst[7]=17 cells (5 PI)
7717 01:00:19.279588 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7718 01:00:19.282446 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7719 01:00:19.282842 == TX Byte 1 ==
7720 01:00:19.285726 u2DelayCellOfst[8]=0 cells (0 PI)
7721 01:00:19.288970 u2DelayCellOfst[9]=0 cells (0 PI)
7722 01:00:19.292660 u2DelayCellOfst[10]=7 cells (2 PI)
7723 01:00:19.295555 u2DelayCellOfst[11]=0 cells (0 PI)
7724 01:00:19.299121 u2DelayCellOfst[12]=10 cells (3 PI)
7725 01:00:19.302553 u2DelayCellOfst[13]=10 cells (3 PI)
7726 01:00:19.305856 u2DelayCellOfst[14]=17 cells (5 PI)
7727 01:00:19.309234 u2DelayCellOfst[15]=10 cells (3 PI)
7728 01:00:19.312662 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7729 01:00:19.316270 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7730 01:00:19.319072 DramC Write-DBI on
7731 01:00:19.319465 ==
7732 01:00:19.322291 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 01:00:19.325623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 01:00:19.326048 ==
7735 01:00:19.326363
7736 01:00:19.326647
7737 01:00:19.328987 TX Vref Scan disable
7738 01:00:19.332568 == TX Byte 0 ==
7739 01:00:19.335630 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7740 01:00:19.339485 == TX Byte 1 ==
7741 01:00:19.342532 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7742 01:00:19.342930 DramC Write-DBI off
7743 01:00:19.343241
7744 01:00:19.345893 [DATLAT]
7745 01:00:19.346326 Freq=1600, CH0 RK0
7746 01:00:19.346637
7747 01:00:19.348959 DATLAT Default: 0xf
7748 01:00:19.349351 0, 0xFFFF, sum = 0
7749 01:00:19.352305 1, 0xFFFF, sum = 0
7750 01:00:19.352789 2, 0xFFFF, sum = 0
7751 01:00:19.356013 3, 0xFFFF, sum = 0
7752 01:00:19.356494 4, 0xFFFF, sum = 0
7753 01:00:19.359612 5, 0xFFFF, sum = 0
7754 01:00:19.360094 6, 0xFFFF, sum = 0
7755 01:00:19.362608 7, 0xFFFF, sum = 0
7756 01:00:19.363009 8, 0xFFFF, sum = 0
7757 01:00:19.365707 9, 0xFFFF, sum = 0
7758 01:00:19.369215 10, 0xFFFF, sum = 0
7759 01:00:19.369694 11, 0xFFFF, sum = 0
7760 01:00:19.372341 12, 0xFFFF, sum = 0
7761 01:00:19.372743 13, 0xFFFF, sum = 0
7762 01:00:19.375750 14, 0x0, sum = 1
7763 01:00:19.376150 15, 0x0, sum = 2
7764 01:00:19.379476 16, 0x0, sum = 3
7765 01:00:19.379959 17, 0x0, sum = 4
7766 01:00:19.380277 best_step = 15
7767 01:00:19.380561
7768 01:00:19.382307 ==
7769 01:00:19.385666 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 01:00:19.389161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 01:00:19.389558 ==
7772 01:00:19.389865 RX Vref Scan: 1
7773 01:00:19.390186
7774 01:00:19.392313 Set Vref Range= 24 -> 127
7775 01:00:19.392709
7776 01:00:19.396082 RX Vref 24 -> 127, step: 1
7777 01:00:19.396556
7778 01:00:19.398976 RX Delay 11 -> 252, step: 4
7779 01:00:19.399371
7780 01:00:19.402068 Set Vref, RX VrefLevel [Byte0]: 24
7781 01:00:19.405493 [Byte1]: 24
7782 01:00:19.405888
7783 01:00:19.409302 Set Vref, RX VrefLevel [Byte0]: 25
7784 01:00:19.412643 [Byte1]: 25
7785 01:00:19.413119
7786 01:00:19.416007 Set Vref, RX VrefLevel [Byte0]: 26
7787 01:00:19.419134 [Byte1]: 26
7788 01:00:19.422765
7789 01:00:19.423251 Set Vref, RX VrefLevel [Byte0]: 27
7790 01:00:19.425655 [Byte1]: 27
7791 01:00:19.430128
7792 01:00:19.430606 Set Vref, RX VrefLevel [Byte0]: 28
7793 01:00:19.432851 [Byte1]: 28
7794 01:00:19.437163
7795 01:00:19.437553 Set Vref, RX VrefLevel [Byte0]: 29
7796 01:00:19.441055 [Byte1]: 29
7797 01:00:19.445279
7798 01:00:19.445688 Set Vref, RX VrefLevel [Byte0]: 30
7799 01:00:19.448726 [Byte1]: 30
7800 01:00:19.452891
7801 01:00:19.456427 Set Vref, RX VrefLevel [Byte0]: 31
7802 01:00:19.459374 [Byte1]: 31
7803 01:00:19.459845
7804 01:00:19.462490 Set Vref, RX VrefLevel [Byte0]: 32
7805 01:00:19.466293 [Byte1]: 32
7806 01:00:19.466764
7807 01:00:19.469380 Set Vref, RX VrefLevel [Byte0]: 33
7808 01:00:19.472633 [Byte1]: 33
7809 01:00:19.473085
7810 01:00:19.476401 Set Vref, RX VrefLevel [Byte0]: 34
7811 01:00:19.478905 [Byte1]: 34
7812 01:00:19.483214
7813 01:00:19.483689 Set Vref, RX VrefLevel [Byte0]: 35
7814 01:00:19.486585 [Byte1]: 35
7815 01:00:19.490564
7816 01:00:19.490962 Set Vref, RX VrefLevel [Byte0]: 36
7817 01:00:19.494437 [Byte1]: 36
7818 01:00:19.498467
7819 01:00:19.498864 Set Vref, RX VrefLevel [Byte0]: 37
7820 01:00:19.501758 [Byte1]: 37
7821 01:00:19.506134
7822 01:00:19.506610 Set Vref, RX VrefLevel [Byte0]: 38
7823 01:00:19.509460 [Byte1]: 38
7824 01:00:19.513800
7825 01:00:19.514292 Set Vref, RX VrefLevel [Byte0]: 39
7826 01:00:19.517501 [Byte1]: 39
7827 01:00:19.521186
7828 01:00:19.521583 Set Vref, RX VrefLevel [Byte0]: 40
7829 01:00:19.524943 [Byte1]: 40
7830 01:00:19.528836
7831 01:00:19.529307 Set Vref, RX VrefLevel [Byte0]: 41
7832 01:00:19.532072 [Byte1]: 41
7833 01:00:19.536486
7834 01:00:19.537008 Set Vref, RX VrefLevel [Byte0]: 42
7835 01:00:19.540339 [Byte1]: 42
7836 01:00:19.544247
7837 01:00:19.544718 Set Vref, RX VrefLevel [Byte0]: 43
7838 01:00:19.547386 [Byte1]: 43
7839 01:00:19.551562
7840 01:00:19.551955 Set Vref, RX VrefLevel [Byte0]: 44
7841 01:00:19.554802 [Byte1]: 44
7842 01:00:19.559434
7843 01:00:19.559905 Set Vref, RX VrefLevel [Byte0]: 45
7844 01:00:19.562644 [Byte1]: 45
7845 01:00:19.566669
7846 01:00:19.567062 Set Vref, RX VrefLevel [Byte0]: 46
7847 01:00:19.570389 [Byte1]: 46
7848 01:00:19.574334
7849 01:00:19.574808 Set Vref, RX VrefLevel [Byte0]: 47
7850 01:00:19.577919 [Byte1]: 47
7851 01:00:19.582046
7852 01:00:19.582522 Set Vref, RX VrefLevel [Byte0]: 48
7853 01:00:19.585715 [Byte1]: 48
7854 01:00:19.590111
7855 01:00:19.590590 Set Vref, RX VrefLevel [Byte0]: 49
7856 01:00:19.592761 [Byte1]: 49
7857 01:00:19.597509
7858 01:00:19.598000 Set Vref, RX VrefLevel [Byte0]: 50
7859 01:00:19.600568 [Byte1]: 50
7860 01:00:19.605050
7861 01:00:19.605518 Set Vref, RX VrefLevel [Byte0]: 51
7862 01:00:19.608484 [Byte1]: 51
7863 01:00:19.612802
7864 01:00:19.613288 Set Vref, RX VrefLevel [Byte0]: 52
7865 01:00:19.615962 [Byte1]: 52
7866 01:00:19.620360
7867 01:00:19.620757 Set Vref, RX VrefLevel [Byte0]: 53
7868 01:00:19.623344 [Byte1]: 53
7869 01:00:19.628050
7870 01:00:19.628446 Set Vref, RX VrefLevel [Byte0]: 54
7871 01:00:19.630824 [Byte1]: 54
7872 01:00:19.635479
7873 01:00:19.635952 Set Vref, RX VrefLevel [Byte0]: 55
7874 01:00:19.638651 [Byte1]: 55
7875 01:00:19.642667
7876 01:00:19.643060 Set Vref, RX VrefLevel [Byte0]: 56
7877 01:00:19.646305 [Byte1]: 56
7878 01:00:19.650802
7879 01:00:19.651268 Set Vref, RX VrefLevel [Byte0]: 57
7880 01:00:19.654234 [Byte1]: 57
7881 01:00:19.658121
7882 01:00:19.658599 Set Vref, RX VrefLevel [Byte0]: 58
7883 01:00:19.661650 [Byte1]: 58
7884 01:00:19.666017
7885 01:00:19.666412 Set Vref, RX VrefLevel [Byte0]: 59
7886 01:00:19.668900 [Byte1]: 59
7887 01:00:19.673455
7888 01:00:19.673932 Set Vref, RX VrefLevel [Byte0]: 60
7889 01:00:19.677070 [Byte1]: 60
7890 01:00:19.681510
7891 01:00:19.681979 Set Vref, RX VrefLevel [Byte0]: 61
7892 01:00:19.687510 [Byte1]: 61
7893 01:00:19.687969
7894 01:00:19.690920 Set Vref, RX VrefLevel [Byte0]: 62
7895 01:00:19.694415 [Byte1]: 62
7896 01:00:19.694813
7897 01:00:19.697897 Set Vref, RX VrefLevel [Byte0]: 63
7898 01:00:19.701496 [Byte1]: 63
7899 01:00:19.701966
7900 01:00:19.704398 Set Vref, RX VrefLevel [Byte0]: 64
7901 01:00:19.707541 [Byte1]: 64
7902 01:00:19.711357
7903 01:00:19.711772 Set Vref, RX VrefLevel [Byte0]: 65
7904 01:00:19.714916 [Byte1]: 65
7905 01:00:19.718854
7906 01:00:19.719249 Set Vref, RX VrefLevel [Byte0]: 66
7907 01:00:19.722618 [Byte1]: 66
7908 01:00:19.726818
7909 01:00:19.727289 Set Vref, RX VrefLevel [Byte0]: 67
7910 01:00:19.730053 [Byte1]: 67
7911 01:00:19.734408
7912 01:00:19.734804 Set Vref, RX VrefLevel [Byte0]: 68
7913 01:00:19.737648 [Byte1]: 68
7914 01:00:19.742207
7915 01:00:19.742677 Set Vref, RX VrefLevel [Byte0]: 69
7916 01:00:19.745393 [Byte1]: 69
7917 01:00:19.749541
7918 01:00:19.750046 Set Vref, RX VrefLevel [Byte0]: 70
7919 01:00:19.752834 [Byte1]: 70
7920 01:00:19.757709
7921 01:00:19.758213 Set Vref, RX VrefLevel [Byte0]: 71
7922 01:00:19.760682 [Byte1]: 71
7923 01:00:19.765077
7924 01:00:19.765551 Set Vref, RX VrefLevel [Byte0]: 72
7925 01:00:19.767971 [Byte1]: 72
7926 01:00:19.772668
7927 01:00:19.773154 Set Vref, RX VrefLevel [Byte0]: 73
7928 01:00:19.775831 [Byte1]: 73
7929 01:00:19.780334
7930 01:00:19.780808 Set Vref, RX VrefLevel [Byte0]: 74
7931 01:00:19.783332 [Byte1]: 74
7932 01:00:19.787866
7933 01:00:19.788345 Set Vref, RX VrefLevel [Byte0]: 75
7934 01:00:19.790924 [Byte1]: 75
7935 01:00:19.796054
7936 01:00:19.796569 Set Vref, RX VrefLevel [Byte0]: 76
7937 01:00:19.798571 [Byte1]: 76
7938 01:00:19.802625
7939 01:00:19.803020 Set Vref, RX VrefLevel [Byte0]: 77
7940 01:00:19.806179 [Byte1]: 77
7941 01:00:19.810572
7942 01:00:19.811083 Final RX Vref Byte 0 = 55 to rank0
7943 01:00:19.813607 Final RX Vref Byte 1 = 63 to rank0
7944 01:00:19.817385 Final RX Vref Byte 0 = 55 to rank1
7945 01:00:19.820417 Final RX Vref Byte 1 = 63 to rank1==
7946 01:00:19.824112 Dram Type= 6, Freq= 0, CH_0, rank 0
7947 01:00:19.830631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7948 01:00:19.831070 ==
7949 01:00:19.831381 DQS Delay:
7950 01:00:19.831667 DQS0 = 0, DQS1 = 0
7951 01:00:19.833927 DQM Delay:
7952 01:00:19.834363 DQM0 = 129, DQM1 = 122
7953 01:00:19.837487 DQ Delay:
7954 01:00:19.840610 DQ0 =128, DQ1 =132, DQ2 =122, DQ3 =126
7955 01:00:19.844350 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7956 01:00:19.847071 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7957 01:00:19.850337 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =132
7958 01:00:19.850775
7959 01:00:19.851111
7960 01:00:19.851421
7961 01:00:19.853852 [DramC_TX_OE_Calibration] TA2
7962 01:00:19.857534 Original DQ_B0 (3 6) =30, OEN = 27
7963 01:00:19.860744 Original DQ_B1 (3 6) =30, OEN = 27
7964 01:00:19.863527 24, 0x0, End_B0=24 End_B1=24
7965 01:00:19.863926 25, 0x0, End_B0=25 End_B1=25
7966 01:00:19.866996 26, 0x0, End_B0=26 End_B1=26
7967 01:00:19.870706 27, 0x0, End_B0=27 End_B1=27
7968 01:00:19.873768 28, 0x0, End_B0=28 End_B1=28
7969 01:00:19.874313 29, 0x0, End_B0=29 End_B1=29
7970 01:00:19.877025 30, 0x0, End_B0=30 End_B1=30
7971 01:00:19.880153 31, 0x4141, End_B0=30 End_B1=30
7972 01:00:19.884256 Byte0 end_step=30 best_step=27
7973 01:00:19.887125 Byte1 end_step=30 best_step=27
7974 01:00:19.890341 Byte0 TX OE(2T, 0.5T) = (3, 3)
7975 01:00:19.890740 Byte1 TX OE(2T, 0.5T) = (3, 3)
7976 01:00:19.891047
7977 01:00:19.893970
7978 01:00:19.900534 [DQSOSCAuto] RK0, (LSB)MR18= 0x1308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 400 ps
7979 01:00:19.903613 CH0 RK0: MR19=303, MR18=1308
7980 01:00:19.910387 CH0_RK0: MR19=0x303, MR18=0x1308, DQSOSC=400, MR23=63, INC=23, DEC=15
7981 01:00:19.910868
7982 01:00:19.913747 ----->DramcWriteLeveling(PI) begin...
7983 01:00:19.914259 ==
7984 01:00:19.917294 Dram Type= 6, Freq= 0, CH_0, rank 1
7985 01:00:19.920245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7986 01:00:19.920687 ==
7987 01:00:19.923432 Write leveling (Byte 0): 33 => 33
7988 01:00:19.928096 Write leveling (Byte 1): 26 => 26
7989 01:00:19.930499 DramcWriteLeveling(PI) end<-----
7990 01:00:19.930895
7991 01:00:19.931196 ==
7992 01:00:19.934091 Dram Type= 6, Freq= 0, CH_0, rank 1
7993 01:00:19.936984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7994 01:00:19.937464 ==
7995 01:00:19.940465 [Gating] SW mode calibration
7996 01:00:19.946678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7997 01:00:19.953580 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7998 01:00:19.957325 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 01:00:19.960366 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 01:00:19.967354 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8001 01:00:19.970674 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8002 01:00:19.973769 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8003 01:00:19.980365 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
8004 01:00:19.983618 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 01:00:19.986782 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 01:00:19.993648 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 01:00:19.996697 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8008 01:00:20.000511 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8009 01:00:20.006953 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
8010 01:00:20.010481 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8011 01:00:20.013856 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (0 0) (0 0)
8012 01:00:20.017492 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8013 01:00:20.023608 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 01:00:20.026973 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 01:00:20.030035 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 01:00:20.037259 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8017 01:00:20.040520 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8018 01:00:20.043447 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8019 01:00:20.050154 1 6 20 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
8020 01:00:20.053920 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 01:00:20.056986 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 01:00:20.063932 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 01:00:20.066686 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8024 01:00:20.070041 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 01:00:20.077033 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8026 01:00:20.080420 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8027 01:00:20.083741 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8028 01:00:20.089912 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8029 01:00:20.093779 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 01:00:20.097226 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 01:00:20.104036 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 01:00:20.107212 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 01:00:20.110356 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 01:00:20.117226 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 01:00:20.120510 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 01:00:20.123197 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 01:00:20.127236 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 01:00:20.133485 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 01:00:20.136931 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 01:00:20.140339 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8041 01:00:20.146965 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8042 01:00:20.150186 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8043 01:00:20.153692 Total UI for P1: 0, mck2ui 16
8044 01:00:20.157097 best dqsien dly found for B0: ( 1, 9, 10)
8045 01:00:20.159772 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8046 01:00:20.167059 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 01:00:20.167531 Total UI for P1: 0, mck2ui 16
8048 01:00:20.173503 best dqsien dly found for B1: ( 1, 9, 20)
8049 01:00:20.176933 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8050 01:00:20.180063 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8051 01:00:20.180534
8052 01:00:20.183634 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8053 01:00:20.186961 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8054 01:00:20.190256 [Gating] SW calibration Done
8055 01:00:20.190729 ==
8056 01:00:20.193499 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 01:00:20.197367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 01:00:20.197841 ==
8059 01:00:20.200883 RX Vref Scan: 0
8060 01:00:20.201358
8061 01:00:20.201666 RX Vref 0 -> 0, step: 1
8062 01:00:20.201950
8063 01:00:20.203377 RX Delay 0 -> 252, step: 8
8064 01:00:20.207007 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8065 01:00:20.213361 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8066 01:00:20.216347 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8067 01:00:20.220033 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8068 01:00:20.223121 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8069 01:00:20.226923 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8070 01:00:20.233315 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8071 01:00:20.236865 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8072 01:00:20.239767 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8073 01:00:20.243269 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8074 01:00:20.246334 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8075 01:00:20.253143 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8076 01:00:20.256139 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8077 01:00:20.259818 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8078 01:00:20.263121 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8079 01:00:20.266929 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8080 01:00:20.270139 ==
8081 01:00:20.273649 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 01:00:20.276960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 01:00:20.277434 ==
8084 01:00:20.277745 DQS Delay:
8085 01:00:20.279559 DQS0 = 0, DQS1 = 0
8086 01:00:20.279953 DQM Delay:
8087 01:00:20.283204 DQM0 = 131, DQM1 = 125
8088 01:00:20.283598 DQ Delay:
8089 01:00:20.286425 DQ0 =131, DQ1 =135, DQ2 =123, DQ3 =131
8090 01:00:20.289593 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8091 01:00:20.293108 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
8092 01:00:20.296442 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8093 01:00:20.296840
8094 01:00:20.297147
8095 01:00:20.297428 ==
8096 01:00:20.299614 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 01:00:20.306116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 01:00:20.306520 ==
8099 01:00:20.306828
8100 01:00:20.307111
8101 01:00:20.307382 TX Vref Scan disable
8102 01:00:20.310608 == TX Byte 0 ==
8103 01:00:20.313453 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8104 01:00:20.316820 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8105 01:00:20.320031 == TX Byte 1 ==
8106 01:00:20.323156 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8107 01:00:20.326789 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8108 01:00:20.329801 ==
8109 01:00:20.333248 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 01:00:20.336828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 01:00:20.337309 ==
8112 01:00:20.351043
8113 01:00:20.354536 TX Vref early break, caculate TX vref
8114 01:00:20.357411 TX Vref=16, minBit 1, minWin=22, winSum=367
8115 01:00:20.361375 TX Vref=18, minBit 9, minWin=22, winSum=374
8116 01:00:20.363926 TX Vref=20, minBit 4, minWin=23, winSum=387
8117 01:00:20.367222 TX Vref=22, minBit 8, minWin=23, winSum=393
8118 01:00:20.370896 TX Vref=24, minBit 3, minWin=24, winSum=405
8119 01:00:20.377445 TX Vref=26, minBit 1, minWin=24, winSum=407
8120 01:00:20.381054 TX Vref=28, minBit 0, minWin=25, winSum=415
8121 01:00:20.383948 TX Vref=30, minBit 0, minWin=25, winSum=414
8122 01:00:20.387398 TX Vref=32, minBit 4, minWin=24, winSum=411
8123 01:00:20.391052 TX Vref=34, minBit 0, minWin=24, winSum=398
8124 01:00:20.394202 TX Vref=36, minBit 4, minWin=23, winSum=390
8125 01:00:20.400585 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8126 01:00:20.400983
8127 01:00:20.404048 Final TX Range 0 Vref 28
8128 01:00:20.404519
8129 01:00:20.404826 ==
8130 01:00:20.407640 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 01:00:20.410739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 01:00:20.411156 ==
8133 01:00:20.411463
8134 01:00:20.411747
8135 01:00:20.414224 TX Vref Scan disable
8136 01:00:20.420819 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8137 01:00:20.421217 == TX Byte 0 ==
8138 01:00:20.424119 u2DelayCellOfst[0]=14 cells (4 PI)
8139 01:00:20.427480 u2DelayCellOfst[1]=17 cells (5 PI)
8140 01:00:20.430776 u2DelayCellOfst[2]=10 cells (3 PI)
8141 01:00:20.434063 u2DelayCellOfst[3]=10 cells (3 PI)
8142 01:00:20.437233 u2DelayCellOfst[4]=10 cells (3 PI)
8143 01:00:20.440446 u2DelayCellOfst[5]=0 cells (0 PI)
8144 01:00:20.444150 u2DelayCellOfst[6]=17 cells (5 PI)
8145 01:00:20.447350 u2DelayCellOfst[7]=17 cells (5 PI)
8146 01:00:20.450785 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8147 01:00:20.454349 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8148 01:00:20.457381 == TX Byte 1 ==
8149 01:00:20.460856 u2DelayCellOfst[8]=3 cells (1 PI)
8150 01:00:20.461333 u2DelayCellOfst[9]=0 cells (0 PI)
8151 01:00:20.464403 u2DelayCellOfst[10]=7 cells (2 PI)
8152 01:00:20.467580 u2DelayCellOfst[11]=3 cells (1 PI)
8153 01:00:20.471024 u2DelayCellOfst[12]=14 cells (4 PI)
8154 01:00:20.474325 u2DelayCellOfst[13]=10 cells (3 PI)
8155 01:00:20.477288 u2DelayCellOfst[14]=17 cells (5 PI)
8156 01:00:20.481166 u2DelayCellOfst[15]=14 cells (4 PI)
8157 01:00:20.484250 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8158 01:00:20.490565 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8159 01:00:20.490965 DramC Write-DBI on
8160 01:00:20.491272 ==
8161 01:00:20.494070 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 01:00:20.497696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 01:00:20.501203 ==
8164 01:00:20.501677
8165 01:00:20.502009
8166 01:00:20.502303 TX Vref Scan disable
8167 01:00:20.504415 == TX Byte 0 ==
8168 01:00:20.507432 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8169 01:00:20.511086 == TX Byte 1 ==
8170 01:00:20.514347 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8171 01:00:20.517492 DramC Write-DBI off
8172 01:00:20.517960
8173 01:00:20.518314 [DATLAT]
8174 01:00:20.518608 Freq=1600, CH0 RK1
8175 01:00:20.518882
8176 01:00:20.520720 DATLAT Default: 0xf
8177 01:00:20.521117 0, 0xFFFF, sum = 0
8178 01:00:20.524270 1, 0xFFFF, sum = 0
8179 01:00:20.527713 2, 0xFFFF, sum = 0
8180 01:00:20.528115 3, 0xFFFF, sum = 0
8181 01:00:20.531199 4, 0xFFFF, sum = 0
8182 01:00:20.531679 5, 0xFFFF, sum = 0
8183 01:00:20.534084 6, 0xFFFF, sum = 0
8184 01:00:20.534490 7, 0xFFFF, sum = 0
8185 01:00:20.537378 8, 0xFFFF, sum = 0
8186 01:00:20.537780 9, 0xFFFF, sum = 0
8187 01:00:20.541202 10, 0xFFFF, sum = 0
8188 01:00:20.541880 11, 0xFFFF, sum = 0
8189 01:00:20.544298 12, 0xFFFF, sum = 0
8190 01:00:20.544783 13, 0xFFFF, sum = 0
8191 01:00:20.547510 14, 0x0, sum = 1
8192 01:00:20.547911 15, 0x0, sum = 2
8193 01:00:20.551095 16, 0x0, sum = 3
8194 01:00:20.551498 17, 0x0, sum = 4
8195 01:00:20.553944 best_step = 15
8196 01:00:20.554377
8197 01:00:20.554687 ==
8198 01:00:20.557677 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 01:00:20.561008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 01:00:20.561406 ==
8201 01:00:20.561713 RX Vref Scan: 0
8202 01:00:20.564426
8203 01:00:20.564896 RX Vref 0 -> 0, step: 1
8204 01:00:20.565202
8205 01:00:20.567358 RX Delay 11 -> 252, step: 4
8206 01:00:20.570616 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8207 01:00:20.577465 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8208 01:00:20.581346 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8209 01:00:20.584787 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8210 01:00:20.587930 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8211 01:00:20.591059 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8212 01:00:20.597755 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8213 01:00:20.600979 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8214 01:00:20.604455 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8215 01:00:20.607735 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8216 01:00:20.611124 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8217 01:00:20.614496 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8218 01:00:20.621016 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8219 01:00:20.624496 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8220 01:00:20.627493 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8221 01:00:20.631348 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8222 01:00:20.631818 ==
8223 01:00:20.634390 Dram Type= 6, Freq= 0, CH_0, rank 1
8224 01:00:20.641308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 01:00:20.641786 ==
8226 01:00:20.642282 DQS Delay:
8227 01:00:20.644893 DQS0 = 0, DQS1 = 0
8228 01:00:20.645364 DQM Delay:
8229 01:00:20.645671 DQM0 = 126, DQM1 = 122
8230 01:00:20.647976 DQ Delay:
8231 01:00:20.651321 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8232 01:00:20.654488 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =134
8233 01:00:20.657637 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8234 01:00:20.661083 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8235 01:00:20.661480
8236 01:00:20.661784
8237 01:00:20.662105
8238 01:00:20.664693 [DramC_TX_OE_Calibration] TA2
8239 01:00:20.667933 Original DQ_B0 (3 6) =30, OEN = 27
8240 01:00:20.670889 Original DQ_B1 (3 6) =30, OEN = 27
8241 01:00:20.674717 24, 0x0, End_B0=24 End_B1=24
8242 01:00:20.675230 25, 0x0, End_B0=25 End_B1=25
8243 01:00:20.677690 26, 0x0, End_B0=26 End_B1=26
8244 01:00:20.681499 27, 0x0, End_B0=27 End_B1=27
8245 01:00:20.684508 28, 0x0, End_B0=28 End_B1=28
8246 01:00:20.688150 29, 0x0, End_B0=29 End_B1=29
8247 01:00:20.688631 30, 0x0, End_B0=30 End_B1=30
8248 01:00:20.691678 31, 0x4545, End_B0=30 End_B1=30
8249 01:00:20.694228 Byte0 end_step=30 best_step=27
8250 01:00:20.697955 Byte1 end_step=30 best_step=27
8251 01:00:20.701764 Byte0 TX OE(2T, 0.5T) = (3, 3)
8252 01:00:20.702310 Byte1 TX OE(2T, 0.5T) = (3, 3)
8253 01:00:20.704462
8254 01:00:20.704941
8255 01:00:20.711326 [DQSOSCAuto] RK1, (LSB)MR18= 0x160b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8256 01:00:20.714614 CH0 RK1: MR19=303, MR18=160B
8257 01:00:20.721127 CH0_RK1: MR19=0x303, MR18=0x160B, DQSOSC=398, MR23=63, INC=23, DEC=15
8258 01:00:20.724363 [RxdqsGatingPostProcess] freq 1600
8259 01:00:20.727542 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8260 01:00:20.731030 best DQS0 dly(2T, 0.5T) = (1, 1)
8261 01:00:20.734254 best DQS1 dly(2T, 0.5T) = (1, 1)
8262 01:00:20.738052 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8263 01:00:20.741351 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8264 01:00:20.744489 best DQS0 dly(2T, 0.5T) = (1, 1)
8265 01:00:20.747504 best DQS1 dly(2T, 0.5T) = (1, 1)
8266 01:00:20.750939 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8267 01:00:20.754217 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8268 01:00:20.754690 Pre-setting of DQS Precalculation
8269 01:00:20.761240 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8270 01:00:20.761705 ==
8271 01:00:20.764417 Dram Type= 6, Freq= 0, CH_1, rank 0
8272 01:00:20.767976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 01:00:20.768505 ==
8274 01:00:20.774492 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8275 01:00:20.778139 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8276 01:00:20.784464 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8277 01:00:20.787520 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8278 01:00:20.797518 [CA 0] Center 42 (14~70) winsize 57
8279 01:00:20.801108 [CA 1] Center 42 (13~71) winsize 59
8280 01:00:20.804241 [CA 2] Center 37 (9~66) winsize 58
8281 01:00:20.807721 [CA 3] Center 36 (7~66) winsize 60
8282 01:00:20.811331 [CA 4] Center 37 (8~66) winsize 59
8283 01:00:20.814095 [CA 5] Center 36 (6~66) winsize 61
8284 01:00:20.814533
8285 01:00:20.817649 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8286 01:00:20.818161
8287 01:00:20.820824 [CATrainingPosCal] consider 1 rank data
8288 01:00:20.824187 u2DelayCellTimex100 = 275/100 ps
8289 01:00:20.827603 CA0 delay=42 (14~70),Diff = 6 PI (21 cell)
8290 01:00:20.834291 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8291 01:00:20.837635 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8292 01:00:20.841140 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8293 01:00:20.844438 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8294 01:00:20.847612 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8295 01:00:20.848087
8296 01:00:20.850728 CA PerBit enable=1, Macro0, CA PI delay=36
8297 01:00:20.851118
8298 01:00:20.854684 [CBTSetCACLKResult] CA Dly = 36
8299 01:00:20.855072 CS Dly: 9 (0~40)
8300 01:00:20.860993 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8301 01:00:20.864099 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8302 01:00:20.864492 ==
8303 01:00:20.867485 Dram Type= 6, Freq= 0, CH_1, rank 1
8304 01:00:20.870699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 01:00:20.871092 ==
8306 01:00:20.877916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8307 01:00:20.881347 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8308 01:00:20.884746 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8309 01:00:20.890900 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8310 01:00:20.900623 [CA 0] Center 43 (14~72) winsize 59
8311 01:00:20.904037 [CA 1] Center 43 (14~72) winsize 59
8312 01:00:20.907408 [CA 2] Center 38 (9~67) winsize 59
8313 01:00:20.910474 [CA 3] Center 37 (7~67) winsize 61
8314 01:00:20.913537 [CA 4] Center 38 (8~68) winsize 61
8315 01:00:20.917119 [CA 5] Center 37 (8~66) winsize 59
8316 01:00:20.917578
8317 01:00:20.920625 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8318 01:00:20.921141
8319 01:00:20.923571 [CATrainingPosCal] consider 2 rank data
8320 01:00:20.926909 u2DelayCellTimex100 = 275/100 ps
8321 01:00:20.930213 CA0 delay=42 (14~70),Diff = 6 PI (21 cell)
8322 01:00:20.937112 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8323 01:00:20.940829 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8324 01:00:20.944161 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8325 01:00:20.946967 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8326 01:00:20.950412 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8327 01:00:20.950800
8328 01:00:20.954088 CA PerBit enable=1, Macro0, CA PI delay=36
8329 01:00:20.954555
8330 01:00:20.957410 [CBTSetCACLKResult] CA Dly = 36
8331 01:00:20.957800 CS Dly: 11 (0~44)
8332 01:00:20.964142 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8333 01:00:20.967391 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8334 01:00:20.967864
8335 01:00:20.970506 ----->DramcWriteLeveling(PI) begin...
8336 01:00:20.970904 ==
8337 01:00:20.973836 Dram Type= 6, Freq= 0, CH_1, rank 0
8338 01:00:20.977189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 01:00:20.977665 ==
8340 01:00:20.980610 Write leveling (Byte 0): 24 => 24
8341 01:00:20.983798 Write leveling (Byte 1): 28 => 28
8342 01:00:20.987164 DramcWriteLeveling(PI) end<-----
8343 01:00:20.987560
8344 01:00:20.987863 ==
8345 01:00:20.990501 Dram Type= 6, Freq= 0, CH_1, rank 0
8346 01:00:20.997318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8347 01:00:20.997795 ==
8348 01:00:20.998157 [Gating] SW mode calibration
8349 01:00:21.007306 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8350 01:00:21.010614 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8351 01:00:21.014006 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 01:00:21.020685 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 01:00:21.024136 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 01:00:21.027126 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 01:00:21.033855 1 4 16 | B1->B0 | 3030 2727 | 0 1 | (0 0) (1 1)
8356 01:00:21.037625 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8357 01:00:21.040937 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 01:00:21.047245 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 01:00:21.050572 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 01:00:21.054110 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 01:00:21.060909 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 01:00:21.064334 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8363 01:00:21.067882 1 5 16 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
8364 01:00:21.074204 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 01:00:21.077510 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 01:00:21.080469 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 01:00:21.083783 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 01:00:21.090967 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 01:00:21.094339 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 01:00:21.097338 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 01:00:21.104197 1 6 16 | B1->B0 | 3838 2e2e | 0 0 | (1 1) (0 0)
8372 01:00:21.107678 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 01:00:21.110926 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 01:00:21.117759 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 01:00:21.120692 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 01:00:21.123975 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 01:00:21.130742 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 01:00:21.133881 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8379 01:00:21.137689 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8380 01:00:21.144390 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8381 01:00:21.148081 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 01:00:21.150557 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 01:00:21.157546 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 01:00:21.160878 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 01:00:21.164756 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 01:00:21.167839 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 01:00:21.174551 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 01:00:21.177666 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 01:00:21.180833 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 01:00:21.187582 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 01:00:21.191092 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 01:00:21.194535 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 01:00:21.201229 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 01:00:21.204334 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8395 01:00:21.208096 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8396 01:00:21.211052 Total UI for P1: 0, mck2ui 16
8397 01:00:21.214499 best dqsien dly found for B0: ( 1, 9, 12)
8398 01:00:21.221399 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 01:00:21.221857 Total UI for P1: 0, mck2ui 16
8400 01:00:21.224482 best dqsien dly found for B1: ( 1, 9, 14)
8401 01:00:21.231078 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8402 01:00:21.234472 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8403 01:00:21.234869
8404 01:00:21.238149 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8405 01:00:21.241184 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8406 01:00:21.244288 [Gating] SW calibration Done
8407 01:00:21.244773 ==
8408 01:00:21.247525 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 01:00:21.251397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 01:00:21.251796 ==
8411 01:00:21.254217 RX Vref Scan: 0
8412 01:00:21.254611
8413 01:00:21.254917 RX Vref 0 -> 0, step: 1
8414 01:00:21.255202
8415 01:00:21.257472 RX Delay 0 -> 252, step: 8
8416 01:00:21.261062 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8417 01:00:21.264344 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8418 01:00:21.271239 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8419 01:00:21.274703 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8420 01:00:21.278373 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8421 01:00:21.281072 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8422 01:00:21.284521 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8423 01:00:21.291203 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8424 01:00:21.294363 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8425 01:00:21.297825 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8426 01:00:21.301618 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8427 01:00:21.304921 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8428 01:00:21.310788 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8429 01:00:21.314144 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8430 01:00:21.317524 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8431 01:00:21.321094 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8432 01:00:21.321493 ==
8433 01:00:21.324574 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 01:00:21.330912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 01:00:21.331376 ==
8436 01:00:21.331683 DQS Delay:
8437 01:00:21.331966 DQS0 = 0, DQS1 = 0
8438 01:00:21.334122 DQM Delay:
8439 01:00:21.334523 DQM0 = 135, DQM1 = 126
8440 01:00:21.337793 DQ Delay:
8441 01:00:21.341182 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8442 01:00:21.344688 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8443 01:00:21.347549 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8444 01:00:21.350849 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8445 01:00:21.351243
8446 01:00:21.351549
8447 01:00:21.351829 ==
8448 01:00:21.354433 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 01:00:21.357672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 01:00:21.358188 ==
8451 01:00:21.361340
8452 01:00:21.361733
8453 01:00:21.362094 TX Vref Scan disable
8454 01:00:21.364640 == TX Byte 0 ==
8455 01:00:21.368238 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8456 01:00:21.371299 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8457 01:00:21.374670 == TX Byte 1 ==
8458 01:00:21.378376 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8459 01:00:21.381635 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8460 01:00:21.382156 ==
8461 01:00:21.384811 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 01:00:21.391008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 01:00:21.391484 ==
8464 01:00:21.404271
8465 01:00:21.407459 TX Vref early break, caculate TX vref
8466 01:00:21.410945 TX Vref=16, minBit 8, minWin=21, winSum=358
8467 01:00:21.413960 TX Vref=18, minBit 8, minWin=21, winSum=370
8468 01:00:21.417517 TX Vref=20, minBit 8, minWin=22, winSum=384
8469 01:00:21.420665 TX Vref=22, minBit 8, minWin=23, winSum=397
8470 01:00:21.423922 TX Vref=24, minBit 8, minWin=23, winSum=407
8471 01:00:21.430460 TX Vref=26, minBit 5, minWin=24, winSum=412
8472 01:00:21.434093 TX Vref=28, minBit 8, minWin=24, winSum=417
8473 01:00:21.437069 TX Vref=30, minBit 8, minWin=24, winSum=415
8474 01:00:21.440786 TX Vref=32, minBit 9, minWin=24, winSum=410
8475 01:00:21.443945 TX Vref=34, minBit 8, minWin=23, winSum=401
8476 01:00:21.447283 TX Vref=36, minBit 9, minWin=22, winSum=388
8477 01:00:21.454207 [TxChooseVref] Worse bit 8, Min win 24, Win sum 417, Final Vref 28
8478 01:00:21.454677
8479 01:00:21.457735 Final TX Range 0 Vref 28
8480 01:00:21.458270
8481 01:00:21.458590 ==
8482 01:00:21.460930 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 01:00:21.464206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 01:00:21.464688 ==
8485 01:00:21.465002
8486 01:00:21.465286
8487 01:00:21.467460 TX Vref Scan disable
8488 01:00:21.474129 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8489 01:00:21.474608 == TX Byte 0 ==
8490 01:00:21.477561 u2DelayCellOfst[0]=17 cells (5 PI)
8491 01:00:21.480973 u2DelayCellOfst[1]=14 cells (4 PI)
8492 01:00:21.484493 u2DelayCellOfst[2]=0 cells (0 PI)
8493 01:00:21.487375 u2DelayCellOfst[3]=7 cells (2 PI)
8494 01:00:21.490518 u2DelayCellOfst[4]=7 cells (2 PI)
8495 01:00:21.494305 u2DelayCellOfst[5]=17 cells (5 PI)
8496 01:00:21.497614 u2DelayCellOfst[6]=17 cells (5 PI)
8497 01:00:21.498125 u2DelayCellOfst[7]=7 cells (2 PI)
8498 01:00:21.504077 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8499 01:00:21.507633 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8500 01:00:21.510962 == TX Byte 1 ==
8501 01:00:21.511480 u2DelayCellOfst[8]=0 cells (0 PI)
8502 01:00:21.513714 u2DelayCellOfst[9]=3 cells (1 PI)
8503 01:00:21.517016 u2DelayCellOfst[10]=7 cells (2 PI)
8504 01:00:21.520576 u2DelayCellOfst[11]=3 cells (1 PI)
8505 01:00:21.523818 u2DelayCellOfst[12]=10 cells (3 PI)
8506 01:00:21.526930 u2DelayCellOfst[13]=14 cells (4 PI)
8507 01:00:21.530436 u2DelayCellOfst[14]=14 cells (4 PI)
8508 01:00:21.533619 u2DelayCellOfst[15]=14 cells (4 PI)
8509 01:00:21.537176 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8510 01:00:21.543906 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8511 01:00:21.544498 DramC Write-DBI on
8512 01:00:21.544947 ==
8513 01:00:21.547017 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 01:00:21.550375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 01:00:21.550779 ==
8516 01:00:21.554136
8517 01:00:21.554531
8518 01:00:21.554838 TX Vref Scan disable
8519 01:00:21.556884 == TX Byte 0 ==
8520 01:00:21.560385 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8521 01:00:21.564021 == TX Byte 1 ==
8522 01:00:21.567177 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8523 01:00:21.567770 DramC Write-DBI off
8524 01:00:21.570481
8525 01:00:21.570872 [DATLAT]
8526 01:00:21.571184 Freq=1600, CH1 RK0
8527 01:00:21.571476
8528 01:00:21.573883 DATLAT Default: 0xf
8529 01:00:21.574339 0, 0xFFFF, sum = 0
8530 01:00:21.576762 1, 0xFFFF, sum = 0
8531 01:00:21.577163 2, 0xFFFF, sum = 0
8532 01:00:21.580635 3, 0xFFFF, sum = 0
8533 01:00:21.581154 4, 0xFFFF, sum = 0
8534 01:00:21.583648 5, 0xFFFF, sum = 0
8535 01:00:21.587031 6, 0xFFFF, sum = 0
8536 01:00:21.587434 7, 0xFFFF, sum = 0
8537 01:00:21.590427 8, 0xFFFF, sum = 0
8538 01:00:21.590829 9, 0xFFFF, sum = 0
8539 01:00:21.593976 10, 0xFFFF, sum = 0
8540 01:00:21.594414 11, 0xFFFF, sum = 0
8541 01:00:21.597344 12, 0xFFFF, sum = 0
8542 01:00:21.597745 13, 0xFFFF, sum = 0
8543 01:00:21.600172 14, 0x0, sum = 1
8544 01:00:21.600570 15, 0x0, sum = 2
8545 01:00:21.603733 16, 0x0, sum = 3
8546 01:00:21.604210 17, 0x0, sum = 4
8547 01:00:21.606960 best_step = 15
8548 01:00:21.607351
8549 01:00:21.607798 ==
8550 01:00:21.610461 Dram Type= 6, Freq= 0, CH_1, rank 0
8551 01:00:21.613723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8552 01:00:21.614155 ==
8553 01:00:21.614466 RX Vref Scan: 1
8554 01:00:21.614751
8555 01:00:21.617359 Set Vref Range= 24 -> 127
8556 01:00:21.617830
8557 01:00:21.620632 RX Vref 24 -> 127, step: 1
8558 01:00:21.621028
8559 01:00:21.623484 RX Delay 11 -> 252, step: 4
8560 01:00:21.623876
8561 01:00:21.627213 Set Vref, RX VrefLevel [Byte0]: 24
8562 01:00:21.630774 [Byte1]: 24
8563 01:00:21.631171
8564 01:00:21.633677 Set Vref, RX VrefLevel [Byte0]: 25
8565 01:00:21.636862 [Byte1]: 25
8566 01:00:21.637256
8567 01:00:21.640292 Set Vref, RX VrefLevel [Byte0]: 26
8568 01:00:21.643725 [Byte1]: 26
8569 01:00:21.647582
8570 01:00:21.648007 Set Vref, RX VrefLevel [Byte0]: 27
8571 01:00:21.650497 [Byte1]: 27
8572 01:00:21.654915
8573 01:00:21.655431 Set Vref, RX VrefLevel [Byte0]: 28
8574 01:00:21.658420 [Byte1]: 28
8575 01:00:21.662730
8576 01:00:21.663273 Set Vref, RX VrefLevel [Byte0]: 29
8577 01:00:21.666023 [Byte1]: 29
8578 01:00:21.670068
8579 01:00:21.670465 Set Vref, RX VrefLevel [Byte0]: 30
8580 01:00:21.673604 [Byte1]: 30
8581 01:00:21.677973
8582 01:00:21.678409 Set Vref, RX VrefLevel [Byte0]: 31
8583 01:00:21.681000 [Byte1]: 31
8584 01:00:21.685113
8585 01:00:21.685504 Set Vref, RX VrefLevel [Byte0]: 32
8586 01:00:21.688371 [Byte1]: 32
8587 01:00:21.692997
8588 01:00:21.693466 Set Vref, RX VrefLevel [Byte0]: 33
8589 01:00:21.696549 [Byte1]: 33
8590 01:00:21.700633
8591 01:00:21.701111 Set Vref, RX VrefLevel [Byte0]: 34
8592 01:00:21.703876 [Byte1]: 34
8593 01:00:21.708342
8594 01:00:21.708745 Set Vref, RX VrefLevel [Byte0]: 35
8595 01:00:21.712044 [Byte1]: 35
8596 01:00:21.716016
8597 01:00:21.716488 Set Vref, RX VrefLevel [Byte0]: 36
8598 01:00:21.719407 [Byte1]: 36
8599 01:00:21.724037
8600 01:00:21.724515 Set Vref, RX VrefLevel [Byte0]: 37
8601 01:00:21.726702 [Byte1]: 37
8602 01:00:21.731365
8603 01:00:21.731840 Set Vref, RX VrefLevel [Byte0]: 38
8604 01:00:21.734574 [Byte1]: 38
8605 01:00:21.739430
8606 01:00:21.739901 Set Vref, RX VrefLevel [Byte0]: 39
8607 01:00:21.742224 [Byte1]: 39
8608 01:00:21.746540
8609 01:00:21.747005 Set Vref, RX VrefLevel [Byte0]: 40
8610 01:00:21.749755 [Byte1]: 40
8611 01:00:21.753731
8612 01:00:21.754195 Set Vref, RX VrefLevel [Byte0]: 41
8613 01:00:21.757117 [Byte1]: 41
8614 01:00:21.761337
8615 01:00:21.761725 Set Vref, RX VrefLevel [Byte0]: 42
8616 01:00:21.765027 [Byte1]: 42
8617 01:00:21.769128
8618 01:00:21.769615 Set Vref, RX VrefLevel [Byte0]: 43
8619 01:00:21.772581 [Byte1]: 43
8620 01:00:21.776764
8621 01:00:21.777236 Set Vref, RX VrefLevel [Byte0]: 44
8622 01:00:21.780023 [Byte1]: 44
8623 01:00:21.784380
8624 01:00:21.784769 Set Vref, RX VrefLevel [Byte0]: 45
8625 01:00:21.787569 [Byte1]: 45
8626 01:00:21.792260
8627 01:00:21.792765 Set Vref, RX VrefLevel [Byte0]: 46
8628 01:00:21.795215 [Byte1]: 46
8629 01:00:21.799671
8630 01:00:21.800139 Set Vref, RX VrefLevel [Byte0]: 47
8631 01:00:21.802919 [Byte1]: 47
8632 01:00:21.807505
8633 01:00:21.807972 Set Vref, RX VrefLevel [Byte0]: 48
8634 01:00:21.810794 [Byte1]: 48
8635 01:00:21.814785
8636 01:00:21.815260 Set Vref, RX VrefLevel [Byte0]: 49
8637 01:00:21.818129 [Byte1]: 49
8638 01:00:21.822919
8639 01:00:21.823394 Set Vref, RX VrefLevel [Byte0]: 50
8640 01:00:21.826142 [Byte1]: 50
8641 01:00:21.830775
8642 01:00:21.831298 Set Vref, RX VrefLevel [Byte0]: 51
8643 01:00:21.833375 [Byte1]: 51
8644 01:00:21.838116
8645 01:00:21.838629 Set Vref, RX VrefLevel [Byte0]: 52
8646 01:00:21.841098 [Byte1]: 52
8647 01:00:21.845274
8648 01:00:21.845780 Set Vref, RX VrefLevel [Byte0]: 53
8649 01:00:21.849089 [Byte1]: 53
8650 01:00:21.853136
8651 01:00:21.853566 Set Vref, RX VrefLevel [Byte0]: 54
8652 01:00:21.855984 [Byte1]: 54
8653 01:00:21.860264
8654 01:00:21.860665 Set Vref, RX VrefLevel [Byte0]: 55
8655 01:00:21.863904 [Byte1]: 55
8656 01:00:21.868255
8657 01:00:21.868738 Set Vref, RX VrefLevel [Byte0]: 56
8658 01:00:21.871442 [Byte1]: 56
8659 01:00:21.875620
8660 01:00:21.876092 Set Vref, RX VrefLevel [Byte0]: 57
8661 01:00:21.879301 [Byte1]: 57
8662 01:00:21.883398
8663 01:00:21.883877 Set Vref, RX VrefLevel [Byte0]: 58
8664 01:00:21.886799 [Byte1]: 58
8665 01:00:21.890676
8666 01:00:21.891066 Set Vref, RX VrefLevel [Byte0]: 59
8667 01:00:21.894281 [Byte1]: 59
8668 01:00:21.898409
8669 01:00:21.898800 Set Vref, RX VrefLevel [Byte0]: 60
8670 01:00:21.901669 [Byte1]: 60
8671 01:00:21.906279
8672 01:00:21.906758 Set Vref, RX VrefLevel [Byte0]: 61
8673 01:00:21.909350 [Byte1]: 61
8674 01:00:21.914013
8675 01:00:21.914544 Set Vref, RX VrefLevel [Byte0]: 62
8676 01:00:21.917013 [Byte1]: 62
8677 01:00:21.921384
8678 01:00:21.921775 Set Vref, RX VrefLevel [Byte0]: 63
8679 01:00:21.924847 [Byte1]: 63
8680 01:00:21.929036
8681 01:00:21.929508 Set Vref, RX VrefLevel [Byte0]: 64
8682 01:00:21.932222 [Byte1]: 64
8683 01:00:21.937058
8684 01:00:21.937530 Set Vref, RX VrefLevel [Byte0]: 65
8685 01:00:21.939972 [Byte1]: 65
8686 01:00:21.944602
8687 01:00:21.945075 Set Vref, RX VrefLevel [Byte0]: 66
8688 01:00:21.947754 [Byte1]: 66
8689 01:00:21.952115
8690 01:00:21.952508 Set Vref, RX VrefLevel [Byte0]: 67
8691 01:00:21.955260 [Byte1]: 67
8692 01:00:21.959576
8693 01:00:21.959968 Set Vref, RX VrefLevel [Byte0]: 68
8694 01:00:21.962622 [Byte1]: 68
8695 01:00:21.966660
8696 01:00:21.970790 Set Vref, RX VrefLevel [Byte0]: 69
8697 01:00:21.973799 [Byte1]: 69
8698 01:00:21.974223
8699 01:00:21.977239 Set Vref, RX VrefLevel [Byte0]: 70
8700 01:00:21.980266 [Byte1]: 70
8701 01:00:21.980676
8702 01:00:21.983860 Set Vref, RX VrefLevel [Byte0]: 71
8703 01:00:21.986971 [Byte1]: 71
8704 01:00:21.987441
8705 01:00:21.990612 Set Vref, RX VrefLevel [Byte0]: 72
8706 01:00:21.993462 [Byte1]: 72
8707 01:00:21.997543
8708 01:00:21.997934 Set Vref, RX VrefLevel [Byte0]: 73
8709 01:00:22.001332 [Byte1]: 73
8710 01:00:22.005350
8711 01:00:22.005742 Set Vref, RX VrefLevel [Byte0]: 74
8712 01:00:22.008887 [Byte1]: 74
8713 01:00:22.013028
8714 01:00:22.013498 Set Vref, RX VrefLevel [Byte0]: 75
8715 01:00:22.016150 [Byte1]: 75
8716 01:00:22.020517
8717 01:00:22.020985 Set Vref, RX VrefLevel [Byte0]: 76
8718 01:00:22.023570 [Byte1]: 76
8719 01:00:22.028306
8720 01:00:22.028777 Final RX Vref Byte 0 = 57 to rank0
8721 01:00:22.031059 Final RX Vref Byte 1 = 55 to rank0
8722 01:00:22.034890 Final RX Vref Byte 0 = 57 to rank1
8723 01:00:22.038210 Final RX Vref Byte 1 = 55 to rank1==
8724 01:00:22.041828 Dram Type= 6, Freq= 0, CH_1, rank 0
8725 01:00:22.047990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 01:00:22.048465 ==
8727 01:00:22.048772 DQS Delay:
8728 01:00:22.049055 DQS0 = 0, DQS1 = 0
8729 01:00:22.051301 DQM Delay:
8730 01:00:22.051693 DQM0 = 131, DQM1 = 124
8731 01:00:22.054706 DQ Delay:
8732 01:00:22.057642 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8733 01:00:22.061085 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8734 01:00:22.065153 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8735 01:00:22.068693 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8736 01:00:22.069177
8737 01:00:22.069491
8738 01:00:22.069772
8739 01:00:22.071506 [DramC_TX_OE_Calibration] TA2
8740 01:00:22.074804 Original DQ_B0 (3 6) =30, OEN = 27
8741 01:00:22.078143 Original DQ_B1 (3 6) =30, OEN = 27
8742 01:00:22.081717 24, 0x0, End_B0=24 End_B1=24
8743 01:00:22.082317 25, 0x0, End_B0=25 End_B1=25
8744 01:00:22.085524 26, 0x0, End_B0=26 End_B1=26
8745 01:00:22.088710 27, 0x0, End_B0=27 End_B1=27
8746 01:00:22.091288 28, 0x0, End_B0=28 End_B1=28
8747 01:00:22.091687 29, 0x0, End_B0=29 End_B1=29
8748 01:00:22.094830 30, 0x0, End_B0=30 End_B1=30
8749 01:00:22.097969 31, 0x5151, End_B0=30 End_B1=30
8750 01:00:22.101599 Byte0 end_step=30 best_step=27
8751 01:00:22.104992 Byte1 end_step=30 best_step=27
8752 01:00:22.108331 Byte0 TX OE(2T, 0.5T) = (3, 3)
8753 01:00:22.108802 Byte1 TX OE(2T, 0.5T) = (3, 3)
8754 01:00:22.109112
8755 01:00:22.109396
8756 01:00:22.118203 [DQSOSCAuto] RK0, (LSB)MR18= 0x15fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
8757 01:00:22.121736 CH1 RK0: MR19=302, MR18=15FE
8758 01:00:22.124991 CH1_RK0: MR19=0x302, MR18=0x15FE, DQSOSC=399, MR23=63, INC=23, DEC=15
8759 01:00:22.127946
8760 01:00:22.131717 ----->DramcWriteLeveling(PI) begin...
8761 01:00:22.132115 ==
8762 01:00:22.135406 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 01:00:22.138220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 01:00:22.138617 ==
8765 01:00:22.141842 Write leveling (Byte 0): 24 => 24
8766 01:00:22.145124 Write leveling (Byte 1): 28 => 28
8767 01:00:22.148248 DramcWriteLeveling(PI) end<-----
8768 01:00:22.148717
8769 01:00:22.149023 ==
8770 01:00:22.151353 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 01:00:22.154831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 01:00:22.155228 ==
8773 01:00:22.158429 [Gating] SW mode calibration
8774 01:00:22.164919 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8775 01:00:22.171743 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8776 01:00:22.174794 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 01:00:22.178153 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 01:00:22.181896 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
8779 01:00:22.188466 1 4 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8780 01:00:22.191443 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 01:00:22.195034 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 01:00:22.201654 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 01:00:22.205125 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 01:00:22.208402 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 01:00:22.214946 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8786 01:00:22.218974 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8787 01:00:22.221788 1 5 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
8788 01:00:22.228457 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8789 01:00:22.231492 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 01:00:22.234503 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 01:00:22.241726 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 01:00:22.244973 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 01:00:22.248633 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 01:00:22.254675 1 6 8 | B1->B0 | 2525 3b3b | 0 0 | (0 0) (0 0)
8795 01:00:22.258332 1 6 12 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
8796 01:00:22.261841 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 01:00:22.268376 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 01:00:22.271552 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 01:00:22.274782 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 01:00:22.278388 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 01:00:22.284991 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 01:00:22.288182 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8803 01:00:22.291649 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8804 01:00:22.298271 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8805 01:00:22.301555 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 01:00:22.305251 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 01:00:22.311759 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 01:00:22.315324 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 01:00:22.318335 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 01:00:22.324905 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 01:00:22.328611 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 01:00:22.331479 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 01:00:22.338133 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 01:00:22.341854 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 01:00:22.345232 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 01:00:22.351796 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 01:00:22.355292 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8818 01:00:22.358760 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8819 01:00:22.362197 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8820 01:00:22.365070 Total UI for P1: 0, mck2ui 16
8821 01:00:22.368681 best dqsien dly found for B0: ( 1, 9, 6)
8822 01:00:22.375466 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8823 01:00:22.378941 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 01:00:22.381785 Total UI for P1: 0, mck2ui 16
8825 01:00:22.385551 best dqsien dly found for B1: ( 1, 9, 14)
8826 01:00:22.388724 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8827 01:00:22.391874 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8828 01:00:22.392267
8829 01:00:22.394909 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8830 01:00:22.398282 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8831 01:00:22.401940 [Gating] SW calibration Done
8832 01:00:22.402451 ==
8833 01:00:22.405506 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 01:00:22.408944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 01:00:22.412186 ==
8836 01:00:22.412663 RX Vref Scan: 0
8837 01:00:22.412975
8838 01:00:22.415228 RX Vref 0 -> 0, step: 1
8839 01:00:22.415625
8840 01:00:22.418807 RX Delay 0 -> 252, step: 8
8841 01:00:22.421792 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8842 01:00:22.425078 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8843 01:00:22.429191 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8844 01:00:22.432091 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8845 01:00:22.435426 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8846 01:00:22.442207 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8847 01:00:22.445290 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8848 01:00:22.448658 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8849 01:00:22.451791 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8850 01:00:22.455245 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8851 01:00:22.461633 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8852 01:00:22.465388 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8853 01:00:22.468836 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8854 01:00:22.472116 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8855 01:00:22.478369 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8856 01:00:22.482035 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8857 01:00:22.482512 ==
8858 01:00:22.485528 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 01:00:22.488802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 01:00:22.489280 ==
8861 01:00:22.489592 DQS Delay:
8862 01:00:22.492095 DQS0 = 0, DQS1 = 0
8863 01:00:22.492564 DQM Delay:
8864 01:00:22.495354 DQM0 = 132, DQM1 = 127
8865 01:00:22.495745 DQ Delay:
8866 01:00:22.498251 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8867 01:00:22.501923 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8868 01:00:22.505187 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8869 01:00:22.508770 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8870 01:00:22.512362
8871 01:00:22.512831
8872 01:00:22.513135 ==
8873 01:00:22.515398 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 01:00:22.518853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 01:00:22.519323 ==
8876 01:00:22.519632
8877 01:00:22.519913
8878 01:00:22.521978 TX Vref Scan disable
8879 01:00:22.522405 == TX Byte 0 ==
8880 01:00:22.525262 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8881 01:00:22.532119 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8882 01:00:22.532621 == TX Byte 1 ==
8883 01:00:22.535342 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8884 01:00:22.542613 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8885 01:00:22.543088 ==
8886 01:00:22.545470 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 01:00:22.549167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 01:00:22.549662 ==
8889 01:00:22.562012
8890 01:00:22.565412 TX Vref early break, caculate TX vref
8891 01:00:22.568948 TX Vref=16, minBit 8, minWin=22, winSum=382
8892 01:00:22.572220 TX Vref=18, minBit 8, minWin=23, winSum=387
8893 01:00:22.574951 TX Vref=20, minBit 8, minWin=23, winSum=396
8894 01:00:22.578693 TX Vref=22, minBit 8, minWin=23, winSum=402
8895 01:00:22.582182 TX Vref=24, minBit 8, minWin=24, winSum=411
8896 01:00:22.589222 TX Vref=26, minBit 6, minWin=25, winSum=419
8897 01:00:22.592438 TX Vref=28, minBit 8, minWin=25, winSum=424
8898 01:00:22.595986 TX Vref=30, minBit 13, minWin=25, winSum=421
8899 01:00:22.598648 TX Vref=32, minBit 0, minWin=25, winSum=414
8900 01:00:22.602347 TX Vref=34, minBit 0, minWin=24, winSum=401
8901 01:00:22.609445 [TxChooseVref] Worse bit 8, Min win 25, Win sum 424, Final Vref 28
8902 01:00:22.609902
8903 01:00:22.612146 Final TX Range 0 Vref 28
8904 01:00:22.612618
8905 01:00:22.612934 ==
8906 01:00:22.615447 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 01:00:22.618681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 01:00:22.619155 ==
8909 01:00:22.619463
8910 01:00:22.619748
8911 01:00:22.622241 TX Vref Scan disable
8912 01:00:22.625874 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8913 01:00:22.629315 == TX Byte 0 ==
8914 01:00:22.631918 u2DelayCellOfst[0]=17 cells (5 PI)
8915 01:00:22.635667 u2DelayCellOfst[1]=10 cells (3 PI)
8916 01:00:22.639119 u2DelayCellOfst[2]=0 cells (0 PI)
8917 01:00:22.642346 u2DelayCellOfst[3]=7 cells (2 PI)
8918 01:00:22.642778 u2DelayCellOfst[4]=7 cells (2 PI)
8919 01:00:22.645425 u2DelayCellOfst[5]=21 cells (6 PI)
8920 01:00:22.649436 u2DelayCellOfst[6]=17 cells (5 PI)
8921 01:00:22.652484 u2DelayCellOfst[7]=7 cells (2 PI)
8922 01:00:22.659283 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8923 01:00:22.662416 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8924 01:00:22.662811 == TX Byte 1 ==
8925 01:00:22.665785 u2DelayCellOfst[8]=0 cells (0 PI)
8926 01:00:22.669016 u2DelayCellOfst[9]=3 cells (1 PI)
8927 01:00:22.672516 u2DelayCellOfst[10]=10 cells (3 PI)
8928 01:00:22.675503 u2DelayCellOfst[11]=7 cells (2 PI)
8929 01:00:22.678882 u2DelayCellOfst[12]=14 cells (4 PI)
8930 01:00:22.682520 u2DelayCellOfst[13]=14 cells (4 PI)
8931 01:00:22.685831 u2DelayCellOfst[14]=17 cells (5 PI)
8932 01:00:22.689085 u2DelayCellOfst[15]=17 cells (5 PI)
8933 01:00:22.692805 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8934 01:00:22.696206 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8935 01:00:22.698734 DramC Write-DBI on
8936 01:00:22.699128 ==
8937 01:00:22.702288 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 01:00:22.705831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 01:00:22.706261 ==
8940 01:00:22.706571
8941 01:00:22.706850
8942 01:00:22.708666 TX Vref Scan disable
8943 01:00:22.712354 == TX Byte 0 ==
8944 01:00:22.715509 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8945 01:00:22.715955 == TX Byte 1 ==
8946 01:00:22.722202 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8947 01:00:22.722807 DramC Write-DBI off
8948 01:00:22.723127
8949 01:00:22.723541 [DATLAT]
8950 01:00:22.725591 Freq=1600, CH1 RK1
8951 01:00:22.726081
8952 01:00:22.729235 DATLAT Default: 0xf
8953 01:00:22.729908 0, 0xFFFF, sum = 0
8954 01:00:22.732477 1, 0xFFFF, sum = 0
8955 01:00:22.732916 2, 0xFFFF, sum = 0
8956 01:00:22.735865 3, 0xFFFF, sum = 0
8957 01:00:22.736262 4, 0xFFFF, sum = 0
8958 01:00:22.738871 5, 0xFFFF, sum = 0
8959 01:00:22.739268 6, 0xFFFF, sum = 0
8960 01:00:22.742474 7, 0xFFFF, sum = 0
8961 01:00:22.742903 8, 0xFFFF, sum = 0
8962 01:00:22.745530 9, 0xFFFF, sum = 0
8963 01:00:22.745924 10, 0xFFFF, sum = 0
8964 01:00:22.748683 11, 0xFFFF, sum = 0
8965 01:00:22.749078 12, 0xFFFF, sum = 0
8966 01:00:22.752275 13, 0xFFFF, sum = 0
8967 01:00:22.752673 14, 0x0, sum = 1
8968 01:00:22.755565 15, 0x0, sum = 2
8969 01:00:22.755965 16, 0x0, sum = 3
8970 01:00:22.759198 17, 0x0, sum = 4
8971 01:00:22.759595 best_step = 15
8972 01:00:22.759898
8973 01:00:22.760178 ==
8974 01:00:22.762255 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 01:00:22.768914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 01:00:22.769429 ==
8977 01:00:22.769869 RX Vref Scan: 0
8978 01:00:22.770257
8979 01:00:22.772764 RX Vref 0 -> 0, step: 1
8980 01:00:22.773231
8981 01:00:22.775770 RX Delay 11 -> 252, step: 4
8982 01:00:22.778753 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8983 01:00:22.782078 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8984 01:00:22.785541 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8985 01:00:22.792607 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8986 01:00:22.796026 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8987 01:00:22.799133 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8988 01:00:22.802468 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8989 01:00:22.805703 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8990 01:00:22.812350 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8991 01:00:22.815311 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8992 01:00:22.818768 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8993 01:00:22.822327 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8994 01:00:22.825744 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8995 01:00:22.832107 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8996 01:00:22.835403 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8997 01:00:22.838709 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8998 01:00:22.839105 ==
8999 01:00:22.842177 Dram Type= 6, Freq= 0, CH_1, rank 1
9000 01:00:22.845456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9001 01:00:22.845851 ==
9002 01:00:22.848686 DQS Delay:
9003 01:00:22.849080 DQS0 = 0, DQS1 = 0
9004 01:00:22.852185 DQM Delay:
9005 01:00:22.852577 DQM0 = 129, DQM1 = 126
9006 01:00:22.852881 DQ Delay:
9007 01:00:22.859046 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9008 01:00:22.861947 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9009 01:00:22.865390 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =116
9010 01:00:22.868907 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =136
9011 01:00:22.869373
9012 01:00:22.869681
9013 01:00:22.869959
9014 01:00:22.872496 [DramC_TX_OE_Calibration] TA2
9015 01:00:22.875238 Original DQ_B0 (3 6) =30, OEN = 27
9016 01:00:22.878659 Original DQ_B1 (3 6) =30, OEN = 27
9017 01:00:22.879135 24, 0x0, End_B0=24 End_B1=24
9018 01:00:22.882161 25, 0x0, End_B0=25 End_B1=25
9019 01:00:22.885757 26, 0x0, End_B0=26 End_B1=26
9020 01:00:22.888938 27, 0x0, End_B0=27 End_B1=27
9021 01:00:22.889417 28, 0x0, End_B0=28 End_B1=28
9022 01:00:22.892524 29, 0x0, End_B0=29 End_B1=29
9023 01:00:22.895724 30, 0x0, End_B0=30 End_B1=30
9024 01:00:22.899431 31, 0x4141, End_B0=30 End_B1=30
9025 01:00:22.902078 Byte0 end_step=30 best_step=27
9026 01:00:22.905508 Byte1 end_step=30 best_step=27
9027 01:00:22.905902 Byte0 TX OE(2T, 0.5T) = (3, 3)
9028 01:00:22.908923 Byte1 TX OE(2T, 0.5T) = (3, 3)
9029 01:00:22.909394
9030 01:00:22.909701
9031 01:00:22.919036 [DQSOSCAuto] RK1, (LSB)MR18= 0xf16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 402 ps
9032 01:00:22.922742 CH1 RK1: MR19=303, MR18=F16
9033 01:00:22.926148 CH1_RK1: MR19=0x303, MR18=0xF16, DQSOSC=398, MR23=63, INC=23, DEC=15
9034 01:00:22.929161 [RxdqsGatingPostProcess] freq 1600
9035 01:00:22.935545 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9036 01:00:22.938773 best DQS0 dly(2T, 0.5T) = (1, 1)
9037 01:00:22.942330 best DQS1 dly(2T, 0.5T) = (1, 1)
9038 01:00:22.945803 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9039 01:00:22.949266 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9040 01:00:22.949735 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 01:00:22.952172 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 01:00:22.956243 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 01:00:22.959283 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 01:00:22.962350 Pre-setting of DQS Precalculation
9045 01:00:22.968807 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9046 01:00:22.975410 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9047 01:00:22.982303 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9048 01:00:22.982758
9049 01:00:22.983058
9050 01:00:22.985874 [Calibration Summary] 3200 Mbps
9051 01:00:22.986383 CH 0, Rank 0
9052 01:00:22.989298 SW Impedance : PASS
9053 01:00:22.992837 DUTY Scan : NO K
9054 01:00:22.993308 ZQ Calibration : PASS
9055 01:00:22.995845 Jitter Meter : NO K
9056 01:00:22.998766 CBT Training : PASS
9057 01:00:22.999159 Write leveling : PASS
9058 01:00:23.002508 RX DQS gating : PASS
9059 01:00:23.002979 RX DQ/DQS(RDDQC) : PASS
9060 01:00:23.005884 TX DQ/DQS : PASS
9061 01:00:23.009428 RX DATLAT : PASS
9062 01:00:23.009819 RX DQ/DQS(Engine): PASS
9063 01:00:23.012920 TX OE : PASS
9064 01:00:23.013394 All Pass.
9065 01:00:23.013700
9066 01:00:23.016105 CH 0, Rank 1
9067 01:00:23.016544 SW Impedance : PASS
9068 01:00:23.019150 DUTY Scan : NO K
9069 01:00:23.022626 ZQ Calibration : PASS
9070 01:00:23.023099 Jitter Meter : NO K
9071 01:00:23.025861 CBT Training : PASS
9072 01:00:23.029480 Write leveling : PASS
9073 01:00:23.029959 RX DQS gating : PASS
9074 01:00:23.033004 RX DQ/DQS(RDDQC) : PASS
9075 01:00:23.035696 TX DQ/DQS : PASS
9076 01:00:23.036091 RX DATLAT : PASS
9077 01:00:23.038888 RX DQ/DQS(Engine): PASS
9078 01:00:23.039282 TX OE : PASS
9079 01:00:23.042564 All Pass.
9080 01:00:23.043049
9081 01:00:23.043397 CH 1, Rank 0
9082 01:00:23.045801 SW Impedance : PASS
9083 01:00:23.046240 DUTY Scan : NO K
9084 01:00:23.049005 ZQ Calibration : PASS
9085 01:00:23.052135 Jitter Meter : NO K
9086 01:00:23.052529 CBT Training : PASS
9087 01:00:23.055552 Write leveling : PASS
9088 01:00:23.059176 RX DQS gating : PASS
9089 01:00:23.059654 RX DQ/DQS(RDDQC) : PASS
9090 01:00:23.062756 TX DQ/DQS : PASS
9091 01:00:23.065581 RX DATLAT : PASS
9092 01:00:23.066095 RX DQ/DQS(Engine): PASS
9093 01:00:23.068527 TX OE : PASS
9094 01:00:23.068919 All Pass.
9095 01:00:23.069224
9096 01:00:23.072190 CH 1, Rank 1
9097 01:00:23.072657 SW Impedance : PASS
9098 01:00:23.075976 DUTY Scan : NO K
9099 01:00:23.078917 ZQ Calibration : PASS
9100 01:00:23.079310 Jitter Meter : NO K
9101 01:00:23.082256 CBT Training : PASS
9102 01:00:23.085532 Write leveling : PASS
9103 01:00:23.086028 RX DQS gating : PASS
9104 01:00:23.089161 RX DQ/DQS(RDDQC) : PASS
9105 01:00:23.089633 TX DQ/DQS : PASS
9106 01:00:23.091919 RX DATLAT : PASS
9107 01:00:23.095959 RX DQ/DQS(Engine): PASS
9108 01:00:23.096431 TX OE : PASS
9109 01:00:23.098710 All Pass.
9110 01:00:23.099180
9111 01:00:23.099488 DramC Write-DBI on
9112 01:00:23.102565 PER_BANK_REFRESH: Hybrid Mode
9113 01:00:23.105616 TX_TRACKING: ON
9114 01:00:23.112311 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9115 01:00:23.122412 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9116 01:00:23.129212 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9117 01:00:23.132693 [FAST_K] Save calibration result to emmc
9118 01:00:23.135241 sync common calibartion params.
9119 01:00:23.135717 sync cbt_mode0:1, 1:1
9120 01:00:23.138697 dram_init: ddr_geometry: 2
9121 01:00:23.142548 dram_init: ddr_geometry: 2
9122 01:00:23.145540 dram_init: ddr_geometry: 2
9123 01:00:23.145975 0:dram_rank_size:100000000
9124 01:00:23.149023 1:dram_rank_size:100000000
9125 01:00:23.155675 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9126 01:00:23.156239 DFS_SHUFFLE_HW_MODE: ON
9127 01:00:23.158666 dramc_set_vcore_voltage set vcore to 725000
9128 01:00:23.162270 Read voltage for 1600, 0
9129 01:00:23.162792 Vio18 = 0
9130 01:00:23.165845 Vcore = 725000
9131 01:00:23.166394 Vdram = 0
9132 01:00:23.166734 Vddq = 0
9133 01:00:23.169151 Vmddr = 0
9134 01:00:23.169660 switch to 3200 Mbps bootup
9135 01:00:23.172487 [DramcRunTimeConfig]
9136 01:00:23.172992 PHYPLL
9137 01:00:23.175401 DPM_CONTROL_AFTERK: ON
9138 01:00:23.175847 PER_BANK_REFRESH: ON
9139 01:00:23.178737 REFRESH_OVERHEAD_REDUCTION: ON
9140 01:00:23.182049 CMD_PICG_NEW_MODE: OFF
9141 01:00:23.182522 XRTWTW_NEW_MODE: ON
9142 01:00:23.185489 XRTRTR_NEW_MODE: ON
9143 01:00:23.185963 TX_TRACKING: ON
9144 01:00:23.188817 RDSEL_TRACKING: OFF
9145 01:00:23.192713 DQS Precalculation for DVFS: ON
9146 01:00:23.193185 RX_TRACKING: OFF
9147 01:00:23.195608 HW_GATING DBG: ON
9148 01:00:23.196001 ZQCS_ENABLE_LP4: ON
9149 01:00:23.198949 RX_PICG_NEW_MODE: ON
9150 01:00:23.199429 TX_PICG_NEW_MODE: ON
9151 01:00:23.202235 ENABLE_RX_DCM_DPHY: ON
9152 01:00:23.205959 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9153 01:00:23.208830 DUMMY_READ_FOR_TRACKING: OFF
9154 01:00:23.209228 !!! SPM_CONTROL_AFTERK: OFF
9155 01:00:23.212054 !!! SPM could not control APHY
9156 01:00:23.215558 IMPEDANCE_TRACKING: ON
9157 01:00:23.216037 TEMP_SENSOR: ON
9158 01:00:23.219085 HW_SAVE_FOR_SR: OFF
9159 01:00:23.222539 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9160 01:00:23.225833 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9161 01:00:23.226598 Read ODT Tracking: ON
9162 01:00:23.228937 Refresh Rate DeBounce: ON
9163 01:00:23.232496 DFS_NO_QUEUE_FLUSH: ON
9164 01:00:23.235655 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9165 01:00:23.236053 ENABLE_DFS_RUNTIME_MRW: OFF
9166 01:00:23.238928 DDR_RESERVE_NEW_MODE: ON
9167 01:00:23.242458 MR_CBT_SWITCH_FREQ: ON
9168 01:00:23.242853 =========================
9169 01:00:23.262983 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9170 01:00:23.266392 dram_init: ddr_geometry: 2
9171 01:00:23.284372 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9172 01:00:23.287712 dram_init: dram init end (result: 0)
9173 01:00:23.294098 DRAM-K: Full calibration passed in 24579 msecs
9174 01:00:23.297068 MRC: failed to locate region type 0.
9175 01:00:23.297504 DRAM rank0 size:0x100000000,
9176 01:00:23.301391 DRAM rank1 size=0x100000000
9177 01:00:23.311018 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9178 01:00:23.317460 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9179 01:00:23.324196 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9180 01:00:23.330759 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9181 01:00:23.334427 DRAM rank0 size:0x100000000,
9182 01:00:23.337660 DRAM rank1 size=0x100000000
9183 01:00:23.338209 CBMEM:
9184 01:00:23.340609 IMD: root @ 0xfffff000 254 entries.
9185 01:00:23.344637 IMD: root @ 0xffffec00 62 entries.
9186 01:00:23.347485 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9187 01:00:23.350688 WARNING: RO_VPD is uninitialized or empty.
9188 01:00:23.357077 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9189 01:00:23.364016 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9190 01:00:23.377621 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9191 01:00:23.388765 BS: romstage times (exec / console): total (unknown) / 24082 ms
9192 01:00:23.389292
9193 01:00:23.389631
9194 01:00:23.398645 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9195 01:00:23.401812 ARM64: Exception handlers installed.
9196 01:00:23.405040 ARM64: Testing exception
9197 01:00:23.405432 ARM64: Done test exception
9198 01:00:23.408682 Enumerating buses...
9199 01:00:23.412125 Show all devs... Before device enumeration.
9200 01:00:23.414856 Root Device: enabled 1
9201 01:00:23.418441 CPU_CLUSTER: 0: enabled 1
9202 01:00:23.418835 CPU: 00: enabled 1
9203 01:00:23.421641 Compare with tree...
9204 01:00:23.422061 Root Device: enabled 1
9205 01:00:23.424842 CPU_CLUSTER: 0: enabled 1
9206 01:00:23.428345 CPU: 00: enabled 1
9207 01:00:23.428558 Root Device scanning...
9208 01:00:23.431410 scan_static_bus for Root Device
9209 01:00:23.434841 CPU_CLUSTER: 0 enabled
9210 01:00:23.438027 scan_static_bus for Root Device done
9211 01:00:23.441678 scan_bus: bus Root Device finished in 8 msecs
9212 01:00:23.441821 done
9213 01:00:23.448415 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9214 01:00:23.451846 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9215 01:00:23.458421 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9216 01:00:23.461654 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9217 01:00:23.465133 Allocating resources...
9218 01:00:23.465228 Reading resources...
9219 01:00:23.468183 Root Device read_resources bus 0 link: 0
9220 01:00:23.471792 DRAM rank0 size:0x100000000,
9221 01:00:23.475163 DRAM rank1 size=0x100000000
9222 01:00:23.478240 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9223 01:00:23.481811 CPU: 00 missing read_resources
9224 01:00:23.484901 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9225 01:00:23.488224 Root Device read_resources bus 0 link: 0 done
9226 01:00:23.491678 Done reading resources.
9227 01:00:23.498916 Show resources in subtree (Root Device)...After reading.
9228 01:00:23.501731 Root Device child on link 0 CPU_CLUSTER: 0
9229 01:00:23.504919 CPU_CLUSTER: 0 child on link 0 CPU: 00
9230 01:00:23.512163 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9231 01:00:23.515009 CPU: 00
9232 01:00:23.518447 Root Device assign_resources, bus 0 link: 0
9233 01:00:23.521925 CPU_CLUSTER: 0 missing set_resources
9234 01:00:23.525474 Root Device assign_resources, bus 0 link: 0 done
9235 01:00:23.528339 Done setting resources.
9236 01:00:23.534922 Show resources in subtree (Root Device)...After assigning values.
9237 01:00:23.538533 Root Device child on link 0 CPU_CLUSTER: 0
9238 01:00:23.541769 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 01:00:23.551884 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 01:00:23.552245 CPU: 00
9241 01:00:23.555256 Done allocating resources.
9242 01:00:23.558185 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9243 01:00:23.561944 Enabling resources...
9244 01:00:23.562471 done.
9245 01:00:23.565426 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9246 01:00:23.568476 Initializing devices...
9247 01:00:23.568946 Root Device init
9248 01:00:23.571950 init hardware done!
9249 01:00:23.575390 0x00000018: ctrlr->caps
9250 01:00:23.575793 52.000 MHz: ctrlr->f_max
9251 01:00:23.578653 0.400 MHz: ctrlr->f_min
9252 01:00:23.582418 0x40ff8080: ctrlr->voltages
9253 01:00:23.582914 sclk: 390625
9254 01:00:23.584999 Bus Width = 1
9255 01:00:23.585394 sclk: 390625
9256 01:00:23.585692 Bus Width = 1
9257 01:00:23.588303 Early init status = 3
9258 01:00:23.591812 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9259 01:00:23.595766 in-header: 03 fc 00 00 01 00 00 00
9260 01:00:23.599782 in-data: 00
9261 01:00:23.602365 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9262 01:00:23.606977 in-header: 03 fd 00 00 00 00 00 00
9263 01:00:23.610358 in-data:
9264 01:00:23.614349 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9265 01:00:23.617189 in-header: 03 fc 00 00 01 00 00 00
9266 01:00:23.620500 in-data: 00
9267 01:00:23.624409 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9268 01:00:23.628786 in-header: 03 fd 00 00 00 00 00 00
9269 01:00:23.632198 in-data:
9270 01:00:23.635472 [SSUSB] Setting up USB HOST controller...
9271 01:00:23.638789 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9272 01:00:23.642083 [SSUSB] phy power-on done.
9273 01:00:23.645086 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9274 01:00:23.652098 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9275 01:00:23.655012 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9276 01:00:23.661858 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9277 01:00:23.668410 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9278 01:00:23.675087 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9279 01:00:23.681655 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9280 01:00:23.688615 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9281 01:00:23.691546 SPM: binary array size = 0x9dc
9282 01:00:23.695062 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9283 01:00:23.701568 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9284 01:00:23.708130 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9285 01:00:23.711701 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9286 01:00:23.714904 configure_display: Starting display init
9287 01:00:23.751788 anx7625_power_on_init: Init interface.
9288 01:00:23.755044 anx7625_disable_pd_protocol: Disabled PD feature.
9289 01:00:23.758900 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9290 01:00:23.786589 anx7625_start_dp_work: Secure OCM version=00
9291 01:00:23.790045 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9292 01:00:23.804378 sp_tx_get_edid_block: EDID Block = 1
9293 01:00:23.906703 Extracted contents:
9294 01:00:23.909752 header: 00 ff ff ff ff ff ff 00
9295 01:00:23.913207 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9296 01:00:23.917117 version: 01 04
9297 01:00:23.919821 basic params: 95 1f 11 78 0a
9298 01:00:23.923199 chroma info: 76 90 94 55 54 90 27 21 50 54
9299 01:00:23.926540 established: 00 00 00
9300 01:00:23.933195 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9301 01:00:23.936301 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9302 01:00:23.942942 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9303 01:00:23.949580 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9304 01:00:23.956106 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9305 01:00:23.959812 extensions: 00
9306 01:00:23.960202 checksum: fb
9307 01:00:23.960496
9308 01:00:23.963427 Manufacturer: IVO Model 57d Serial Number 0
9309 01:00:23.966108 Made week 0 of 2020
9310 01:00:23.966699 EDID version: 1.4
9311 01:00:23.969558 Digital display
9312 01:00:23.973149 6 bits per primary color channel
9313 01:00:23.973553 DisplayPort interface
9314 01:00:23.976587 Maximum image size: 31 cm x 17 cm
9315 01:00:23.979531 Gamma: 220%
9316 01:00:23.979918 Check DPMS levels
9317 01:00:23.982970 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9318 01:00:23.986224 First detailed timing is preferred timing
9319 01:00:23.989696 Established timings supported:
9320 01:00:23.993035 Standard timings supported:
9321 01:00:23.995897 Detailed timings
9322 01:00:23.999287 Hex of detail: 383680a07038204018303c0035ae10000019
9323 01:00:24.002749 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9324 01:00:24.009560 0780 0798 07c8 0820 hborder 0
9325 01:00:24.012581 0438 043b 0447 0458 vborder 0
9326 01:00:24.015781 -hsync -vsync
9327 01:00:24.016398 Did detailed timing
9328 01:00:24.023098 Hex of detail: 000000000000000000000000000000000000
9329 01:00:24.023510 Manufacturer-specified data, tag 0
9330 01:00:24.029203 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9331 01:00:24.032409 ASCII string: InfoVision
9332 01:00:24.036147 Hex of detail: 000000fe00523134304e574635205248200a
9333 01:00:24.039074 ASCII string: R140NWF5 RH
9334 01:00:24.039464 Checksum
9335 01:00:24.042463 Checksum: 0xfb (valid)
9336 01:00:24.045643 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9337 01:00:24.049305 DSI data_rate: 832800000 bps
9338 01:00:24.055941 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9339 01:00:24.059388 anx7625_parse_edid: pixelclock(138800).
9340 01:00:24.062406 hactive(1920), hsync(48), hfp(24), hbp(88)
9341 01:00:24.065657 vactive(1080), vsync(12), vfp(3), vbp(17)
9342 01:00:24.069300 anx7625_dsi_config: config dsi.
9343 01:00:24.075716 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9344 01:00:24.088503 anx7625_dsi_config: success to config DSI
9345 01:00:24.092146 anx7625_dp_start: MIPI phy setup OK.
9346 01:00:24.095333 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9347 01:00:24.099026 mtk_ddp_mode_set invalid vrefresh 60
9348 01:00:24.101823 main_disp_path_setup
9349 01:00:24.102285 ovl_layer_smi_id_en
9350 01:00:24.105278 ovl_layer_smi_id_en
9351 01:00:24.105666 ccorr_config
9352 01:00:24.105966 aal_config
9353 01:00:24.108712 gamma_config
9354 01:00:24.109103 postmask_config
9355 01:00:24.112102 dither_config
9356 01:00:24.115725 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9357 01:00:24.121863 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9358 01:00:24.125307 Root Device init finished in 551 msecs
9359 01:00:24.125699 CPU_CLUSTER: 0 init
9360 01:00:24.135253 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9361 01:00:24.138618 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9362 01:00:24.141970 APU_MBOX 0x190000b0 = 0x10001
9363 01:00:24.145436 APU_MBOX 0x190001b0 = 0x10001
9364 01:00:24.148735 APU_MBOX 0x190005b0 = 0x10001
9365 01:00:24.152391 APU_MBOX 0x190006b0 = 0x10001
9366 01:00:24.155622 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9367 01:00:24.167380 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9368 01:00:24.180239 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9369 01:00:24.187093 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9370 01:00:24.198713 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9371 01:00:24.207461 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9372 01:00:24.210875 CPU_CLUSTER: 0 init finished in 81 msecs
9373 01:00:24.214230 Devices initialized
9374 01:00:24.217118 Show all devs... After init.
9375 01:00:24.217507 Root Device: enabled 1
9376 01:00:24.220501 CPU_CLUSTER: 0: enabled 1
9377 01:00:24.223997 CPU: 00: enabled 1
9378 01:00:24.227499 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9379 01:00:24.231103 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9380 01:00:24.233896 ELOG: NV offset 0x57f000 size 0x1000
9381 01:00:24.240511 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9382 01:00:24.247388 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9383 01:00:24.250674 ELOG: Event(17) added with size 13 at 2024-06-16 01:00:24 UTC
9384 01:00:24.253651 out: cmd=0x121: 03 db 21 01 00 00 00 00
9385 01:00:24.258237 in-header: 03 3f 00 00 2c 00 00 00
9386 01:00:24.271476 in-data: 15 18 d0 12 43 02 00 00 0a 00 00 00 06 80 00 00 86 a2 c5 12 06 80 00 00 d5 1c cc 12 06 80 00 00 9a d7 ce 12 06 80 00 00 86 96 cf 12
9387 01:00:24.278138 ELOG: Event(A1) added with size 10 at 2024-06-16 01:00:24 UTC
9388 01:00:24.285242 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9389 01:00:24.291325 ELOG: Event(A0) added with size 9 at 2024-06-16 01:00:24 UTC
9390 01:00:24.294993 elog_add_boot_reason: Logged dev mode boot
9391 01:00:24.297959 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9392 01:00:24.301220 Finalize devices...
9393 01:00:24.301615 Devices finalized
9394 01:00:24.308173 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9395 01:00:24.311537 Writing coreboot table at 0xffe64000
9396 01:00:24.314939 0. 000000000010a000-0000000000113fff: RAMSTAGE
9397 01:00:24.317936 1. 0000000040000000-00000000400fffff: RAM
9398 01:00:24.324814 2. 0000000040100000-000000004032afff: RAMSTAGE
9399 01:00:24.328215 3. 000000004032b000-00000000545fffff: RAM
9400 01:00:24.331576 4. 0000000054600000-000000005465ffff: BL31
9401 01:00:24.334665 5. 0000000054660000-00000000ffe63fff: RAM
9402 01:00:24.341372 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9403 01:00:24.344538 7. 0000000100000000-000000023fffffff: RAM
9404 01:00:24.344935 Passing 5 GPIOs to payload:
9405 01:00:24.351248 NAME | PORT | POLARITY | VALUE
9406 01:00:24.354516 EC in RW | 0x000000aa | low | undefined
9407 01:00:24.361227 EC interrupt | 0x00000005 | low | undefined
9408 01:00:24.364326 TPM interrupt | 0x000000ab | high | undefined
9409 01:00:24.367845 SD card detect | 0x00000011 | high | undefined
9410 01:00:24.374648 speaker enable | 0x00000093 | high | undefined
9411 01:00:24.377705 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9412 01:00:24.381186 in-header: 03 f9 00 00 02 00 00 00
9413 01:00:24.381583 in-data: 02 00
9414 01:00:24.384474 ADC[4]: Raw value=900221 ID=7
9415 01:00:24.387983 ADC[3]: Raw value=212967 ID=1
9416 01:00:24.388379 RAM Code: 0x71
9417 01:00:24.390962 ADC[6]: Raw value=74557 ID=0
9418 01:00:24.394427 ADC[5]: Raw value=212229 ID=1
9419 01:00:24.394822 SKU Code: 0x1
9420 01:00:24.401088 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 97c3
9421 01:00:24.404457 coreboot table: 964 bytes.
9422 01:00:24.407621 IMD ROOT 0. 0xfffff000 0x00001000
9423 01:00:24.411251 IMD SMALL 1. 0xffffe000 0x00001000
9424 01:00:24.414361 RO MCACHE 2. 0xffffc000 0x00001104
9425 01:00:24.417646 CONSOLE 3. 0xfff7c000 0x00080000
9426 01:00:24.421156 FMAP 4. 0xfff7b000 0x00000452
9427 01:00:24.424444 TIME STAMP 5. 0xfff7a000 0x00000910
9428 01:00:24.427884 VBOOT WORK 6. 0xfff66000 0x00014000
9429 01:00:24.431233 RAMOOPS 7. 0xffe66000 0x00100000
9430 01:00:24.434635 COREBOOT 8. 0xffe64000 0x00002000
9431 01:00:24.435032 IMD small region:
9432 01:00:24.437558 IMD ROOT 0. 0xffffec00 0x00000400
9433 01:00:24.441050 VPD 1. 0xffffeb80 0x0000006c
9434 01:00:24.444574 MMC STATUS 2. 0xffffeb60 0x00000004
9435 01:00:24.450937 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9436 01:00:24.454493 Probing TPM: done!
9437 01:00:24.457954 Connected to device vid:did:rid of 1ae0:0028:00
9438 01:00:24.468012 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9439 01:00:24.471456 Initialized TPM device CR50 revision 0
9440 01:00:24.474626 Checking cr50 for pending updates
9441 01:00:24.477851 Reading cr50 TPM mode
9442 01:00:24.486655 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9443 01:00:24.492943 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9444 01:00:24.533412 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9445 01:00:24.536891 Checking segment from ROM address 0x40100000
9446 01:00:24.539776 Checking segment from ROM address 0x4010001c
9447 01:00:24.546608 Loading segment from ROM address 0x40100000
9448 01:00:24.547023 code (compression=0)
9449 01:00:24.553554 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9450 01:00:24.563576 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9451 01:00:24.563975 it's not compressed!
9452 01:00:24.570351 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9453 01:00:24.573598 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9454 01:00:24.593878 Loading segment from ROM address 0x4010001c
9455 01:00:24.594320 Entry Point 0x80000000
9456 01:00:24.596873 Loaded segments
9457 01:00:24.600201 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9458 01:00:24.607206 Jumping to boot code at 0x80000000(0xffe64000)
9459 01:00:24.614149 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9460 01:00:24.620613 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9461 01:00:24.628364 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9462 01:00:24.631323 Checking segment from ROM address 0x40100000
9463 01:00:24.634962 Checking segment from ROM address 0x4010001c
9464 01:00:24.641626 Loading segment from ROM address 0x40100000
9465 01:00:24.642063 code (compression=1)
9466 01:00:24.648163 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9467 01:00:24.658247 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9468 01:00:24.658695 using LZMA
9469 01:00:24.666477 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9470 01:00:24.672914 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9471 01:00:24.676668 Loading segment from ROM address 0x4010001c
9472 01:00:24.677065 Entry Point 0x54601000
9473 01:00:24.679705 Loaded segments
9474 01:00:24.683188 NOTICE: MT8192 bl31_setup
9475 01:00:24.689878 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9476 01:00:24.693337 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9477 01:00:24.697359 WARNING: region 0:
9478 01:00:24.700231 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 01:00:24.700632 WARNING: region 1:
9480 01:00:24.706794 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9481 01:00:24.710512 WARNING: region 2:
9482 01:00:24.713648 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9483 01:00:24.716753 WARNING: region 3:
9484 01:00:24.720392 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 01:00:24.723663 WARNING: region 4:
9486 01:00:24.727136 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 01:00:24.730439 WARNING: region 5:
9488 01:00:24.733897 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 01:00:24.736682 WARNING: region 6:
9490 01:00:24.740067 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 01:00:24.740462 WARNING: region 7:
9492 01:00:24.747029 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 01:00:24.753527 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9494 01:00:24.756994 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9495 01:00:24.760413 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9496 01:00:24.766943 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9497 01:00:24.770215 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9498 01:00:24.773573 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9499 01:00:24.780085 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9500 01:00:24.784089 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9501 01:00:24.787298 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9502 01:00:24.793953 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9503 01:00:24.797508 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9504 01:00:24.800245 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9505 01:00:24.806997 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9506 01:00:24.810459 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9507 01:00:24.817253 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9508 01:00:24.820375 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9509 01:00:24.823835 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9510 01:00:24.830483 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9511 01:00:24.833662 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9512 01:00:24.837086 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9513 01:00:24.843890 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9514 01:00:24.847034 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9515 01:00:24.853698 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9516 01:00:24.856753 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9517 01:00:24.860292 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9518 01:00:24.867220 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9519 01:00:24.870143 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9520 01:00:24.876965 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9521 01:00:24.880414 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9522 01:00:24.883811 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9523 01:00:24.890539 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9524 01:00:24.893827 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9525 01:00:24.897120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9526 01:00:24.903735 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9527 01:00:24.907510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9528 01:00:24.910224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9529 01:00:24.913726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9530 01:00:24.920581 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9531 01:00:24.924275 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9532 01:00:24.927516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9533 01:00:24.930582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9534 01:00:24.937254 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9535 01:00:24.940656 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9536 01:00:24.943784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9537 01:00:24.947309 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9538 01:00:24.953754 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9539 01:00:24.957115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9540 01:00:24.960477 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9541 01:00:24.967071 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9542 01:00:24.970787 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9543 01:00:24.973899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9544 01:00:24.980891 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9545 01:00:24.983822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9546 01:00:24.990896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9547 01:00:24.994438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9548 01:00:24.997264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9549 01:00:25.003987 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9550 01:00:25.007378 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9551 01:00:25.014471 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9552 01:00:25.017848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9553 01:00:25.024216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9554 01:00:25.027519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9555 01:00:25.033930 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9556 01:00:25.037577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9557 01:00:25.040936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9558 01:00:25.047762 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9559 01:00:25.050688 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9560 01:00:25.057776 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9561 01:00:25.061172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9562 01:00:25.064649 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9563 01:00:25.071014 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9564 01:00:25.074336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9565 01:00:25.080998 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9566 01:00:25.084620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9567 01:00:25.091453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9568 01:00:25.094515 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9569 01:00:25.097912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9570 01:00:25.104969 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9571 01:00:25.108120 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9572 01:00:25.114712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9573 01:00:25.118248 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9574 01:00:25.124998 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9575 01:00:25.127845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9576 01:00:25.131634 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9577 01:00:25.138040 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9578 01:00:25.141277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9579 01:00:25.148308 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9580 01:00:25.151291 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9581 01:00:25.154828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9582 01:00:25.161574 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9583 01:00:25.165127 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9584 01:00:25.171612 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9585 01:00:25.175051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9586 01:00:25.181472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9587 01:00:25.184801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9588 01:00:25.191734 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9589 01:00:25.194808 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9590 01:00:25.198179 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9591 01:00:25.201897 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9592 01:00:25.208292 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9593 01:00:25.211875 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9594 01:00:25.215122 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9595 01:00:25.221958 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9596 01:00:25.225568 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9597 01:00:25.228343 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9598 01:00:25.234978 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9599 01:00:25.238800 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9600 01:00:25.245172 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9601 01:00:25.248370 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9602 01:00:25.251865 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9603 01:00:25.258735 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9604 01:00:25.262160 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9605 01:00:25.265084 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9606 01:00:25.272176 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9607 01:00:25.275548 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9608 01:00:25.281919 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9609 01:00:25.285411 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9610 01:00:25.288819 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9611 01:00:25.292390 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9612 01:00:25.298642 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9613 01:00:25.302015 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9614 01:00:25.305957 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9615 01:00:25.309044 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9616 01:00:25.315938 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9617 01:00:25.319000 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9618 01:00:25.322829 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9619 01:00:25.328946 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9620 01:00:25.332447 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9621 01:00:25.336249 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9622 01:00:25.342497 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9623 01:00:25.346159 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9624 01:00:25.352632 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9625 01:00:25.356237 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9626 01:00:25.359509 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9627 01:00:25.366209 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9628 01:00:25.369128 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9629 01:00:25.376073 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9630 01:00:25.379469 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9631 01:00:25.382841 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9632 01:00:25.389388 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9633 01:00:25.392719 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9634 01:00:25.395832 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9635 01:00:25.402773 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9636 01:00:25.406058 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9637 01:00:25.409742 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9638 01:00:25.416677 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9639 01:00:25.419606 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9640 01:00:25.426085 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9641 01:00:25.429615 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9642 01:00:25.432779 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9643 01:00:25.439846 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9644 01:00:25.443108 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9645 01:00:25.446451 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9646 01:00:25.453568 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9647 01:00:25.456341 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9648 01:00:25.463040 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9649 01:00:25.466714 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9650 01:00:25.470117 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9651 01:00:25.476760 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9652 01:00:25.479632 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9653 01:00:25.486662 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9654 01:00:25.489663 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9655 01:00:25.493288 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9656 01:00:25.499453 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9657 01:00:25.502822 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9658 01:00:25.509426 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9659 01:00:25.512849 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9660 01:00:25.516379 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9661 01:00:25.523135 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9662 01:00:25.525802 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9663 01:00:25.532395 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9664 01:00:25.535875 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9665 01:00:25.539533 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9666 01:00:25.545611 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9667 01:00:25.549169 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9668 01:00:25.552502 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9669 01:00:25.559193 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9670 01:00:25.562612 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9671 01:00:25.568935 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9672 01:00:25.572638 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9673 01:00:25.575679 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9674 01:00:25.582412 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9675 01:00:25.585660 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9676 01:00:25.592107 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9677 01:00:25.595562 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9678 01:00:25.598957 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9679 01:00:25.605883 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9680 01:00:25.608708 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9681 01:00:25.615466 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9682 01:00:25.618887 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9683 01:00:25.622195 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9684 01:00:25.629055 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9685 01:00:25.631825 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9686 01:00:25.639074 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9687 01:00:25.642689 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9688 01:00:25.645521 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9689 01:00:25.652246 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9690 01:00:25.655764 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9691 01:00:25.662104 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9692 01:00:25.665469 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9693 01:00:25.672153 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9694 01:00:25.675415 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9695 01:00:25.678599 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9696 01:00:25.685280 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9697 01:00:25.688903 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9698 01:00:25.695072 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9699 01:00:25.698453 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9700 01:00:25.701570 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9701 01:00:25.708675 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9702 01:00:25.712029 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9703 01:00:25.718405 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9704 01:00:25.721940 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9705 01:00:25.728599 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9706 01:00:25.731473 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9707 01:00:25.734803 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9708 01:00:25.741610 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9709 01:00:25.744985 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9710 01:00:25.751650 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9711 01:00:25.755186 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9712 01:00:25.761224 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9713 01:00:25.764676 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9714 01:00:25.768162 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9715 01:00:25.775101 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9716 01:00:25.777892 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9717 01:00:25.784696 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9718 01:00:25.787833 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9719 01:00:25.791315 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9720 01:00:25.797876 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9721 01:00:25.801391 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9722 01:00:25.804485 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9723 01:00:25.811294 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9724 01:00:25.814843 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9725 01:00:25.817862 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9726 01:00:25.821534 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9727 01:00:25.828131 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9728 01:00:25.831413 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9729 01:00:25.837623 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9730 01:00:25.841221 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9731 01:00:25.844497 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9732 01:00:25.850903 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9733 01:00:25.854741 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9734 01:00:25.858114 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9735 01:00:25.864480 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9736 01:00:25.868033 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9737 01:00:25.871498 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9738 01:00:25.877703 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9739 01:00:25.881098 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9740 01:00:25.887788 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9741 01:00:25.891237 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9742 01:00:25.894525 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9743 01:00:25.900812 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9744 01:00:25.904679 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9745 01:00:25.907988 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9746 01:00:25.914541 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9747 01:00:25.917482 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9748 01:00:25.921243 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9749 01:00:25.927773 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9750 01:00:25.930991 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9751 01:00:25.934376 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9752 01:00:25.940941 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9753 01:00:25.944110 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9754 01:00:25.950968 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9755 01:00:25.954184 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9756 01:00:25.957556 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9757 01:00:25.964015 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9758 01:00:25.967525 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9759 01:00:25.970907 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9760 01:00:25.977364 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9761 01:00:25.980779 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9762 01:00:25.984334 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9763 01:00:25.987822 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9764 01:00:25.994622 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9765 01:00:25.997816 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9766 01:00:26.000719 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9767 01:00:26.004221 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9768 01:00:26.010957 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9769 01:00:26.014083 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9770 01:00:26.017401 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9771 01:00:26.020819 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9772 01:00:26.027595 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9773 01:00:26.030544 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9774 01:00:26.034078 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9775 01:00:26.040450 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9776 01:00:26.043809 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9777 01:00:26.050727 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9778 01:00:26.053863 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9779 01:00:26.056991 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9780 01:00:26.063879 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9781 01:00:26.067211 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9782 01:00:26.073570 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9783 01:00:26.077343 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9784 01:00:26.080695 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9785 01:00:26.086854 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9786 01:00:26.090616 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9787 01:00:26.097046 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9788 01:00:26.100394 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9789 01:00:26.103681 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9790 01:00:26.110607 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9791 01:00:26.113566 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9792 01:00:26.120074 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9793 01:00:26.123866 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9794 01:00:26.127288 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9795 01:00:26.133445 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9796 01:00:26.137040 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9797 01:00:26.143463 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9798 01:00:26.146797 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9799 01:00:26.150255 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9800 01:00:26.156661 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9801 01:00:26.160110 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9802 01:00:26.166778 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9803 01:00:26.169936 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9804 01:00:26.176761 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9805 01:00:26.180149 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9806 01:00:26.183366 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9807 01:00:26.190251 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9808 01:00:26.193365 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9809 01:00:26.200434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9810 01:00:26.203550 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9811 01:00:26.206541 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9812 01:00:26.213164 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9813 01:00:26.216811 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9814 01:00:26.223323 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9815 01:00:26.226452 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9816 01:00:26.229812 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9817 01:00:26.236845 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9818 01:00:26.240295 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9819 01:00:26.246625 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9820 01:00:26.250124 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9821 01:00:26.256454 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9822 01:00:26.259672 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9823 01:00:26.263334 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9824 01:00:26.270173 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9825 01:00:26.273434 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9826 01:00:26.276567 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9827 01:00:26.283387 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9828 01:00:26.286445 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9829 01:00:26.293397 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9830 01:00:26.296881 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9831 01:00:26.299738 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9832 01:00:26.306685 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9833 01:00:26.310131 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9834 01:00:26.316436 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9835 01:00:26.320054 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9836 01:00:26.326380 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9837 01:00:26.329924 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9838 01:00:26.333057 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9839 01:00:26.339912 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9840 01:00:26.343328 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9841 01:00:26.349521 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9842 01:00:26.353136 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9843 01:00:26.356567 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9844 01:00:26.363270 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9845 01:00:26.366493 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9846 01:00:26.372868 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9847 01:00:26.376388 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9848 01:00:26.379484 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9849 01:00:26.386428 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9850 01:00:26.389293 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9851 01:00:26.396245 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9852 01:00:26.399768 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9853 01:00:26.405988 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9854 01:00:26.409396 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9855 01:00:26.412888 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9856 01:00:26.419630 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9857 01:00:26.423051 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9858 01:00:26.429326 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9859 01:00:26.432821 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9860 01:00:26.439517 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9861 01:00:26.442800 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9862 01:00:26.446103 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9863 01:00:26.452550 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9864 01:00:26.455996 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9865 01:00:26.462541 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9866 01:00:26.465840 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9867 01:00:26.472551 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9868 01:00:26.475893 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9869 01:00:26.482573 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9870 01:00:26.485828 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9871 01:00:26.489423 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9872 01:00:26.496219 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9873 01:00:26.499444 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9874 01:00:26.505892 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9875 01:00:26.509580 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9876 01:00:26.515901 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9877 01:00:26.519285 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9878 01:00:26.522705 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9879 01:00:26.529435 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9880 01:00:26.532279 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9881 01:00:26.539143 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9882 01:00:26.542602 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9883 01:00:26.549258 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9884 01:00:26.552674 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9885 01:00:26.555661 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9886 01:00:26.562346 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9887 01:00:26.565950 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9888 01:00:26.572590 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9889 01:00:26.575944 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9890 01:00:26.582875 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9891 01:00:26.585845 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9892 01:00:26.592193 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9893 01:00:26.596042 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9894 01:00:26.598783 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9895 01:00:26.605894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9896 01:00:26.608999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9897 01:00:26.615447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9898 01:00:26.618804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9899 01:00:26.622313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9900 01:00:26.629104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9901 01:00:26.632568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9902 01:00:26.638688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9903 01:00:26.642232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9904 01:00:26.648896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9905 01:00:26.652352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9906 01:00:26.659210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9907 01:00:26.662271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9908 01:00:26.669190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9909 01:00:26.672438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9910 01:00:26.679213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9911 01:00:26.682515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9912 01:00:26.689108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9913 01:00:26.692448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9914 01:00:26.695618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9915 01:00:26.702601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9916 01:00:26.709116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9917 01:00:26.712176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9918 01:00:26.715425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9919 01:00:26.722515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9920 01:00:26.725843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9921 01:00:26.732825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9922 01:00:26.736058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9923 01:00:26.742512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9924 01:00:26.745862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9925 01:00:26.752461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9926 01:00:26.755876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9927 01:00:26.762209 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9928 01:00:26.762286 INFO: [APUAPC] vio 0
9929 01:00:26.769872 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9930 01:00:26.773115 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9931 01:00:26.776543 INFO: [APUAPC] D0_APC_0: 0x400510
9932 01:00:26.779779 INFO: [APUAPC] D0_APC_1: 0x0
9933 01:00:26.782790 INFO: [APUAPC] D0_APC_2: 0x1540
9934 01:00:26.786102 INFO: [APUAPC] D0_APC_3: 0x0
9935 01:00:26.789555 INFO: [APUAPC] D1_APC_0: 0xffffffff
9936 01:00:26.792897 INFO: [APUAPC] D1_APC_1: 0xffffffff
9937 01:00:26.796343 INFO: [APUAPC] D1_APC_2: 0x3fffff
9938 01:00:26.799555 INFO: [APUAPC] D1_APC_3: 0x0
9939 01:00:26.803204 INFO: [APUAPC] D2_APC_0: 0xffffffff
9940 01:00:26.806207 INFO: [APUAPC] D2_APC_1: 0xffffffff
9941 01:00:26.809615 INFO: [APUAPC] D2_APC_2: 0x3fffff
9942 01:00:26.812944 INFO: [APUAPC] D2_APC_3: 0x0
9943 01:00:26.816068 INFO: [APUAPC] D3_APC_0: 0xffffffff
9944 01:00:26.819409 INFO: [APUAPC] D3_APC_1: 0xffffffff
9945 01:00:26.823170 INFO: [APUAPC] D3_APC_2: 0x3fffff
9946 01:00:26.823246 INFO: [APUAPC] D3_APC_3: 0x0
9947 01:00:26.829689 INFO: [APUAPC] D4_APC_0: 0xffffffff
9948 01:00:26.832653 INFO: [APUAPC] D4_APC_1: 0xffffffff
9949 01:00:26.835889 INFO: [APUAPC] D4_APC_2: 0x3fffff
9950 01:00:26.835964 INFO: [APUAPC] D4_APC_3: 0x0
9951 01:00:26.839710 INFO: [APUAPC] D5_APC_0: 0xffffffff
9952 01:00:26.843016 INFO: [APUAPC] D5_APC_1: 0xffffffff
9953 01:00:26.846538 INFO: [APUAPC] D5_APC_2: 0x3fffff
9954 01:00:26.849384 INFO: [APUAPC] D5_APC_3: 0x0
9955 01:00:26.852826 INFO: [APUAPC] D6_APC_0: 0xffffffff
9956 01:00:26.856191 INFO: [APUAPC] D6_APC_1: 0xffffffff
9957 01:00:26.859483 INFO: [APUAPC] D6_APC_2: 0x3fffff
9958 01:00:26.862530 INFO: [APUAPC] D6_APC_3: 0x0
9959 01:00:26.865802 INFO: [APUAPC] D7_APC_0: 0xffffffff
9960 01:00:26.869271 INFO: [APUAPC] D7_APC_1: 0xffffffff
9961 01:00:26.872591 INFO: [APUAPC] D7_APC_2: 0x3fffff
9962 01:00:26.876153 INFO: [APUAPC] D7_APC_3: 0x0
9963 01:00:26.879410 INFO: [APUAPC] D8_APC_0: 0xffffffff
9964 01:00:26.882615 INFO: [APUAPC] D8_APC_1: 0xffffffff
9965 01:00:26.886014 INFO: [APUAPC] D8_APC_2: 0x3fffff
9966 01:00:26.889441 INFO: [APUAPC] D8_APC_3: 0x0
9967 01:00:26.892970 INFO: [APUAPC] D9_APC_0: 0xffffffff
9968 01:00:26.896192 INFO: [APUAPC] D9_APC_1: 0xffffffff
9969 01:00:26.899177 INFO: [APUAPC] D9_APC_2: 0x3fffff
9970 01:00:26.902814 INFO: [APUAPC] D9_APC_3: 0x0
9971 01:00:26.906132 INFO: [APUAPC] D10_APC_0: 0xffffffff
9972 01:00:26.909382 INFO: [APUAPC] D10_APC_1: 0xffffffff
9973 01:00:26.912839 INFO: [APUAPC] D10_APC_2: 0x3fffff
9974 01:00:26.915749 INFO: [APUAPC] D10_APC_3: 0x0
9975 01:00:26.919038 INFO: [APUAPC] D11_APC_0: 0xffffffff
9976 01:00:26.922576 INFO: [APUAPC] D11_APC_1: 0xffffffff
9977 01:00:26.926127 INFO: [APUAPC] D11_APC_2: 0x3fffff
9978 01:00:26.929585 INFO: [APUAPC] D11_APC_3: 0x0
9979 01:00:26.932204 INFO: [APUAPC] D12_APC_0: 0xffffffff
9980 01:00:26.935595 INFO: [APUAPC] D12_APC_1: 0xffffffff
9981 01:00:26.938935 INFO: [APUAPC] D12_APC_2: 0x3fffff
9982 01:00:26.942596 INFO: [APUAPC] D12_APC_3: 0x0
9983 01:00:26.945652 INFO: [APUAPC] D13_APC_0: 0xffffffff
9984 01:00:26.949247 INFO: [APUAPC] D13_APC_1: 0xffffffff
9985 01:00:26.952285 INFO: [APUAPC] D13_APC_2: 0x3fffff
9986 01:00:26.955723 INFO: [APUAPC] D13_APC_3: 0x0
9987 01:00:26.959040 INFO: [APUAPC] D14_APC_0: 0xffffffff
9988 01:00:26.962422 INFO: [APUAPC] D14_APC_1: 0xffffffff
9989 01:00:26.965885 INFO: [APUAPC] D14_APC_2: 0x3fffff
9990 01:00:26.969308 INFO: [APUAPC] D14_APC_3: 0x0
9991 01:00:26.972181 INFO: [APUAPC] D15_APC_0: 0xffffffff
9992 01:00:26.975558 INFO: [APUAPC] D15_APC_1: 0xffffffff
9993 01:00:26.979036 INFO: [APUAPC] D15_APC_2: 0x3fffff
9994 01:00:26.982498 INFO: [APUAPC] D15_APC_3: 0x0
9995 01:00:26.985657 INFO: [APUAPC] APC_CON: 0x4
9996 01:00:26.989001 INFO: [NOCDAPC] D0_APC_0: 0x0
9997 01:00:26.992606 INFO: [NOCDAPC] D0_APC_1: 0x0
9998 01:00:26.995860 INFO: [NOCDAPC] D1_APC_0: 0x0
9999 01:00:26.995937 INFO: [NOCDAPC] D1_APC_1: 0xfff
10000 01:00:26.999207 INFO: [NOCDAPC] D2_APC_0: 0x0
10001 01:00:27.002625 INFO: [NOCDAPC] D2_APC_1: 0xfff
10002 01:00:27.005505 INFO: [NOCDAPC] D3_APC_0: 0x0
10003 01:00:27.009002 INFO: [NOCDAPC] D3_APC_1: 0xfff
10004 01:00:27.012389 INFO: [NOCDAPC] D4_APC_0: 0x0
10005 01:00:27.015796 INFO: [NOCDAPC] D4_APC_1: 0xfff
10006 01:00:27.018798 INFO: [NOCDAPC] D5_APC_0: 0x0
10007 01:00:27.022368 INFO: [NOCDAPC] D5_APC_1: 0xfff
10008 01:00:27.025822 INFO: [NOCDAPC] D6_APC_0: 0x0
10009 01:00:27.028875 INFO: [NOCDAPC] D6_APC_1: 0xfff
10010 01:00:27.028952 INFO: [NOCDAPC] D7_APC_0: 0x0
10011 01:00:27.032117 INFO: [NOCDAPC] D7_APC_1: 0xfff
10012 01:00:27.035485 INFO: [NOCDAPC] D8_APC_0: 0x0
10013 01:00:27.038933 INFO: [NOCDAPC] D8_APC_1: 0xfff
10014 01:00:27.042179 INFO: [NOCDAPC] D9_APC_0: 0x0
10015 01:00:27.045790 INFO: [NOCDAPC] D9_APC_1: 0xfff
10016 01:00:27.049058 INFO: [NOCDAPC] D10_APC_0: 0x0
10017 01:00:27.052458 INFO: [NOCDAPC] D10_APC_1: 0xfff
10018 01:00:27.055433 INFO: [NOCDAPC] D11_APC_0: 0x0
10019 01:00:27.059040 INFO: [NOCDAPC] D11_APC_1: 0xfff
10020 01:00:27.062502 INFO: [NOCDAPC] D12_APC_0: 0x0
10021 01:00:27.062579 INFO: [NOCDAPC] D12_APC_1: 0xfff
10022 01:00:27.065643 INFO: [NOCDAPC] D13_APC_0: 0x0
10023 01:00:27.068818 INFO: [NOCDAPC] D13_APC_1: 0xfff
10024 01:00:27.072526 INFO: [NOCDAPC] D14_APC_0: 0x0
10025 01:00:27.075584 INFO: [NOCDAPC] D14_APC_1: 0xfff
10026 01:00:27.079083 INFO: [NOCDAPC] D15_APC_0: 0x0
10027 01:00:27.082519 INFO: [NOCDAPC] D15_APC_1: 0xfff
10028 01:00:27.085918 INFO: [NOCDAPC] APC_CON: 0x4
10029 01:00:27.088744 INFO: [APUAPC] set_apusys_apc done
10030 01:00:27.091994 INFO: [DEVAPC] devapc_init done
10031 01:00:27.095439 INFO: GICv3 without legacy support detected.
10032 01:00:27.098773 INFO: ARM GICv3 driver initialized in EL3
10033 01:00:27.105183 INFO: Maximum SPI INTID supported: 639
10034 01:00:27.109218 INFO: BL31: Initializing runtime services
10035 01:00:27.111882 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10036 01:00:27.115338 INFO: SPM: enable CPC mode
10037 01:00:27.122144 INFO: mcdi ready for mcusys-off-idle and system suspend
10038 01:00:27.125548 INFO: BL31: Preparing for EL3 exit to normal world
10039 01:00:27.128828 INFO: Entry point address = 0x80000000
10040 01:00:27.131931 INFO: SPSR = 0x8
10041 01:00:27.137710
10042 01:00:27.137785
10043 01:00:27.137844
10044 01:00:27.140982 Starting depthcharge on Spherion...
10045 01:00:27.141057
10046 01:00:27.141116 Wipe memory regions:
10047 01:00:27.141171
10048 01:00:27.141839 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10049 01:00:27.141929 start: 2.2.4 bootloader-commands (timeout 00:04:24) [common]
10050 01:00:27.142022 Setting prompt string to ['asurada:']
10051 01:00:27.142106 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:24)
10052 01:00:27.144412 [0x00000040000000, 0x00000054600000)
10053 01:00:27.266641
10054 01:00:27.266740 [0x00000054660000, 0x00000080000000)
10055 01:00:27.527004
10056 01:00:27.527114 [0x000000821a7280, 0x000000ffe64000)
10057 01:00:28.272037
10058 01:00:28.272158 [0x00000100000000, 0x00000240000000)
10059 01:00:30.162563
10060 01:00:30.165716 Initializing XHCI USB controller at 0x11200000.
10061 01:00:31.204680
10062 01:00:31.208128 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10063 01:00:31.208207
10064 01:00:31.208268
10065 01:00:31.208548 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10067 01:00:31.308886 asurada: tftpboot 192.168.201.1 14368629/tftp-deploy-ekovxyqb/kernel/image.itb 14368629/tftp-deploy-ekovxyqb/kernel/cmdline
10068 01:00:31.309053 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10069 01:00:31.309129 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10070 01:00:31.312848 tftpboot 192.168.201.1 14368629/tftp-deploy-ekovxyqb/kernel/image.ittp-deploy-ekovxyqb/kernel/cmdline
10071 01:00:31.312928
10072 01:00:31.312988 Waiting for link
10073 01:00:31.471419
10074 01:00:31.471549 R8152: Initializing
10075 01:00:31.471611
10076 01:00:31.474498 Version 6 (ocp_data = 5c30)
10077 01:00:31.474576
10078 01:00:31.478017 R8152: Done initializing
10079 01:00:31.478111
10080 01:00:31.478171 Adding net device
10081 01:00:33.571900
10082 01:00:33.572018 done.
10083 01:00:33.572078
10084 01:00:33.572133 MAC: 00:24:32:30:78:52
10085 01:00:33.572186
10086 01:00:33.574762 Sending DHCP discover... done.
10087 01:00:33.574840
10088 01:00:33.578174 Waiting for reply... done.
10089 01:00:33.578275
10090 01:00:33.581630 Sending DHCP request... done.
10091 01:00:33.581730
10092 01:00:33.586234 Waiting for reply... done.
10093 01:00:33.586311
10094 01:00:33.586370 My ip is 192.168.201.14
10095 01:00:33.586426
10096 01:00:33.589246 The DHCP server ip is 192.168.201.1
10097 01:00:33.589333
10098 01:00:33.596012 TFTP server IP predefined by user: 192.168.201.1
10099 01:00:33.596090
10100 01:00:33.602911 Bootfile predefined by user: 14368629/tftp-deploy-ekovxyqb/kernel/image.itb
10101 01:00:33.602989
10102 01:00:33.603049 Sending tftp read request... done.
10103 01:00:33.605770
10104 01:00:33.609706 Waiting for the transfer...
10105 01:00:33.609783
10106 01:00:34.152195 00000000 ################################################################
10107 01:00:34.152333
10108 01:00:34.695745 00080000 ################################################################
10109 01:00:34.695872
10110 01:00:35.237444 00100000 ################################################################
10111 01:00:35.237571
10112 01:00:35.772009 00180000 ################################################################
10113 01:00:35.772135
10114 01:00:36.305449 00200000 ################################################################
10115 01:00:36.305586
10116 01:00:36.841667 00280000 ################################################################
10117 01:00:36.841785
10118 01:00:37.393535 00300000 ################################################################
10119 01:00:37.393656
10120 01:00:37.948300 00380000 ################################################################
10121 01:00:37.948426
10122 01:00:38.476576 00400000 ################################################################
10123 01:00:38.476699
10124 01:00:39.017611 00480000 ################################################################
10125 01:00:39.017739
10126 01:00:39.573975 00500000 ################################################################
10127 01:00:39.574090
10128 01:00:40.093133 00580000 ################################################################
10129 01:00:40.093251
10130 01:00:40.655563 00600000 ################################################################
10131 01:00:40.655688
10132 01:00:41.207943 00680000 ################################################################
10133 01:00:41.208071
10134 01:00:41.761766 00700000 ################################################################
10135 01:00:41.761896
10136 01:00:42.318242 00780000 ################################################################
10137 01:00:42.318355
10138 01:00:42.868078 00800000 ################################################################
10139 01:00:42.868195
10140 01:00:43.405765 00880000 ################################################################
10141 01:00:43.405884
10142 01:00:43.943282 00900000 ################################################################
10143 01:00:43.943402
10144 01:00:44.494081 00980000 ################################################################
10145 01:00:44.494197
10146 01:00:45.022442 00a00000 ################################################################
10147 01:00:45.022554
10148 01:00:45.555680 00a80000 ################################################################
10149 01:00:45.555792
10150 01:00:46.079268 00b00000 ################################################################
10151 01:00:46.079382
10152 01:00:46.632015 00b80000 ################################################################
10153 01:00:46.632157
10154 01:00:47.181473 00c00000 ################################################################
10155 01:00:47.181596
10156 01:00:47.719157 00c80000 ################################################################
10157 01:00:47.719277
10158 01:00:48.269478 00d00000 ################################################################
10159 01:00:48.269604
10160 01:00:48.802534 00d80000 ################################################################
10161 01:00:48.802657
10162 01:00:49.340638 00e00000 ################################################################
10163 01:00:49.340788
10164 01:00:49.863838 00e80000 ################################################################
10165 01:00:49.863966
10166 01:00:50.386828 00f00000 ################################################################
10167 01:00:50.386953
10168 01:00:50.921093 00f80000 ################################################################
10169 01:00:50.921221
10170 01:00:51.457682 01000000 ################################################################
10171 01:00:51.457805
10172 01:00:52.008596 01080000 ################################################################
10173 01:00:52.008722
10174 01:00:52.552815 01100000 ################################################################
10175 01:00:52.552931
10176 01:00:53.078953 01180000 ################################################################
10177 01:00:53.079067
10178 01:00:53.605284 01200000 ################################################################
10179 01:00:53.605401
10180 01:00:54.135531 01280000 ################################################################
10181 01:00:54.135654
10182 01:00:54.682227 01300000 ################################################################
10183 01:00:54.682375
10184 01:00:55.219746 01380000 ################################################################
10185 01:00:55.219876
10186 01:00:55.769920 01400000 ################################################################
10187 01:00:55.770094
10188 01:00:56.313942 01480000 ################################################################
10189 01:00:56.314110
10190 01:00:56.870972 01500000 ################################################################
10191 01:00:56.871094
10192 01:00:57.515496 01580000 ################################################################
10193 01:00:57.515969
10194 01:00:58.182859 01600000 ################################################################
10195 01:00:58.183328
10196 01:00:58.867391 01680000 ################################################################
10197 01:00:58.867858
10198 01:00:59.523839 01700000 ################################################################
10199 01:00:59.523956
10200 01:01:00.097115 01780000 ################################################################
10201 01:01:00.097231
10202 01:01:00.666875 01800000 ################################################################
10203 01:01:00.666991
10204 01:01:01.267019 01880000 ################################################################
10205 01:01:01.267147
10206 01:01:01.870893 01900000 ################################################################
10207 01:01:01.871012
10208 01:01:02.467333 01980000 ################################################################
10209 01:01:02.467457
10210 01:01:03.070783 01a00000 ################################################################
10211 01:01:03.071236
10212 01:01:03.675829 01a80000 ################################################################
10213 01:01:03.675941
10214 01:01:04.295364 01b00000 ################################################################
10215 01:01:04.295493
10216 01:01:04.830833 01b80000 ################################################################
10217 01:01:04.830958
10218 01:01:05.420016 01c00000 ################################################################
10219 01:01:05.420130
10220 01:01:06.074399 01c80000 ################################################################
10221 01:01:06.074865
10222 01:01:06.748273 01d00000 ################################################################
10223 01:01:06.748731
10224 01:01:07.418904 01d80000 ################################################################
10225 01:01:07.419362
10226 01:01:08.101017 01e00000 ################################################################
10227 01:01:08.101478
10228 01:01:08.791439 01e80000 ################################################################
10229 01:01:08.791903
10230 01:01:09.460771 01f00000 ################################################################
10231 01:01:09.461231
10232 01:01:10.083619 01f80000 ################################################################
10233 01:01:10.083866
10234 01:01:10.746044 02000000 ################################################################
10235 01:01:10.746523
10236 01:01:11.354238 02080000 ################################################################
10237 01:01:11.354380
10238 01:01:11.980736 02100000 ################################################################
10239 01:01:11.981182
10240 01:01:12.606460 02180000 ################################################################
10241 01:01:12.606935
10242 01:01:13.206020 02200000 ################################################################
10243 01:01:13.206146
10244 01:01:13.810414 02280000 ################################################################
10245 01:01:13.810537
10246 01:01:14.413761 02300000 ################################################################
10247 01:01:14.413883
10248 01:01:15.025344 02380000 ################################################################
10249 01:01:15.025487
10250 01:01:15.602133 02400000 ################################################################
10251 01:01:15.602252
10252 01:01:16.197812 02480000 ################################################################
10253 01:01:16.197962
10254 01:01:16.809180 02500000 ################################################################
10255 01:01:16.809297
10256 01:01:17.443032 02580000 ################################################################
10257 01:01:17.443511
10258 01:01:18.120398 02600000 ################################################################
10259 01:01:18.120890
10260 01:01:18.799702 02680000 ################################################################
10261 01:01:18.800163
10262 01:01:19.479780 02700000 ################################################################
10263 01:01:19.480293
10264 01:01:20.128067 02780000 ################################################################
10265 01:01:20.128579
10266 01:01:20.757679 02800000 ################################################################
10267 01:01:20.757938
10268 01:01:21.345628 02880000 ################################################################
10269 01:01:21.345765
10270 01:01:21.958662 02900000 ################################################################
10271 01:01:21.959284
10272 01:01:22.627963 02980000 ################################################################
10273 01:01:22.628517
10274 01:01:23.314176 02a00000 ################################################################
10275 01:01:23.314650
10276 01:01:23.979385 02a80000 ################################################################
10277 01:01:23.979858
10279 01:04:51.119608 end: 2.2.4 bootloader-commands (duration 00:04:24) [common]
10281 01:04:51.120501 depthcharge-retry failed: 1 of 1 attempts. 'wait for prompt timed out'
10283 01:04:51.121240 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
10286 01:04:51.122498 end: 2 depthcharge-action (duration 00:05:00) [common]
10288 01:04:51.123511 Cleaning after the job
10289 01:04:51.123919 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/ramdisk
10290 01:04:51.150972 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/kernel
10291 01:04:51.177547 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/dtb
10292 01:04:51.177826 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368629/tftp-deploy-ekovxyqb/modules
10293 01:04:51.184458 start: 4.1 power-off (timeout 00:00:30) [common]
10294 01:04:51.184632 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
10295 01:04:51.407583 >> Command sent successfully.
10296 01:04:51.420826 Returned 0 in 0 seconds
10297 01:04:51.522149 end: 4.1 power-off (duration 00:00:00) [common]
10299 01:04:51.523840 start: 4.2 read-feedback (timeout 00:10:00) [common]
10300 01:04:51.525022 Listened to connection for namespace 'common' for up to 1s
10301 01:04:52.525857 Finalising connection for namespace 'common'
10302 01:04:52.526518 Disconnecting from shell: Finalise
10303 01:04:52.526902 02b00000 ###########################
10304 01:04:52.627689 end: 4.2 read-feedback (duration 00:00:01) [common]
10305 01:04:52.628229 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368629
10306 01:04:52.773604 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368629
10307 01:04:52.773793 JobError: Your job cannot terminate cleanly.