Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 26
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:58:05.547546 lava-dispatcher, installed at version: 2024.03
2 00:58:05.547762 start: 0 validate
3 00:58:05.547901 Start time: 2024-06-16 00:58:05.547893+00:00 (UTC)
4 00:58:05.548025 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:58:05.548154 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:58:05.798599 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:58:05.798777 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:58:06.048028 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:58:06.048204 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:58:06.298058 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:58:06.298222 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:58:06.549867 validate duration: 1.00
14 00:58:06.550155 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:58:06.550269 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:58:06.550370 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:58:06.550498 Not decompressing ramdisk as can be used compressed.
18 00:58:06.550586 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 00:58:06.550650 saving as /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/ramdisk/rootfs.cpio.gz
20 00:58:06.550715 total size: 47897469 (45 MB)
21 00:58:06.551850 progress 0 % (0 MB)
22 00:58:06.564598 progress 5 % (2 MB)
23 00:58:06.576870 progress 10 % (4 MB)
24 00:58:06.589255 progress 15 % (6 MB)
25 00:58:06.601601 progress 20 % (9 MB)
26 00:58:06.614525 progress 25 % (11 MB)
27 00:58:06.626920 progress 30 % (13 MB)
28 00:58:06.639228 progress 35 % (16 MB)
29 00:58:06.651581 progress 40 % (18 MB)
30 00:58:06.663937 progress 45 % (20 MB)
31 00:58:06.676303 progress 50 % (22 MB)
32 00:58:06.688516 progress 55 % (25 MB)
33 00:58:06.701421 progress 60 % (27 MB)
34 00:58:06.713795 progress 65 % (29 MB)
35 00:58:06.726849 progress 70 % (32 MB)
36 00:58:06.739892 progress 75 % (34 MB)
37 00:58:06.752560 progress 80 % (36 MB)
38 00:58:06.765411 progress 85 % (38 MB)
39 00:58:06.778015 progress 90 % (41 MB)
40 00:58:06.790035 progress 95 % (43 MB)
41 00:58:06.802148 progress 100 % (45 MB)
42 00:58:06.802423 45 MB downloaded in 0.25 s (181.48 MB/s)
43 00:58:06.802600 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:58:06.802867 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:58:06.802968 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:58:06.803068 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:58:06.803219 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:58:06.803293 saving as /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/kernel/Image
50 00:58:06.803394 total size: 54813184 (52 MB)
51 00:58:06.803493 No compression specified
52 00:58:06.805147 progress 0 % (0 MB)
53 00:58:06.819253 progress 5 % (2 MB)
54 00:58:06.833572 progress 10 % (5 MB)
55 00:58:06.847794 progress 15 % (7 MB)
56 00:58:06.862056 progress 20 % (10 MB)
57 00:58:06.875941 progress 25 % (13 MB)
58 00:58:06.889771 progress 30 % (15 MB)
59 00:58:06.903613 progress 35 % (18 MB)
60 00:58:06.917497 progress 40 % (20 MB)
61 00:58:06.931262 progress 45 % (23 MB)
62 00:58:06.945418 progress 50 % (26 MB)
63 00:58:06.959621 progress 55 % (28 MB)
64 00:58:06.973691 progress 60 % (31 MB)
65 00:58:06.987768 progress 65 % (34 MB)
66 00:58:07.001557 progress 70 % (36 MB)
67 00:58:07.015434 progress 75 % (39 MB)
68 00:58:07.029438 progress 80 % (41 MB)
69 00:58:07.043263 progress 85 % (44 MB)
70 00:58:07.057075 progress 90 % (47 MB)
71 00:58:07.070834 progress 95 % (49 MB)
72 00:58:07.084630 progress 100 % (52 MB)
73 00:58:07.084926 52 MB downloaded in 0.28 s (185.68 MB/s)
74 00:58:07.085098 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:58:07.085429 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:58:07.085533 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:58:07.085632 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:58:07.085783 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:58:07.085863 saving as /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/dtb/mt8192-asurada-spherion-r0.dtb
81 00:58:07.085961 total size: 47258 (0 MB)
82 00:58:07.086061 No compression specified
83 00:58:07.087793 progress 69 % (0 MB)
84 00:58:07.088119 progress 100 % (0 MB)
85 00:58:07.088312 0 MB downloaded in 0.00 s (19.20 MB/s)
86 00:58:07.088480 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:58:07.088729 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:58:07.088829 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:58:07.088928 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:58:07.089059 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:58:07.089133 saving as /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/modules/modules.tar
93 00:58:07.089230 total size: 8617404 (8 MB)
94 00:58:07.089375 Using unxz to decompress xz
95 00:58:07.093807 progress 0 % (0 MB)
96 00:58:07.113116 progress 5 % (0 MB)
97 00:58:07.140757 progress 10 % (0 MB)
98 00:58:07.170699 progress 15 % (1 MB)
99 00:58:07.195165 progress 20 % (1 MB)
100 00:58:07.219397 progress 25 % (2 MB)
101 00:58:07.243518 progress 30 % (2 MB)
102 00:58:07.270346 progress 35 % (2 MB)
103 00:58:07.295703 progress 40 % (3 MB)
104 00:58:07.318987 progress 45 % (3 MB)
105 00:58:07.343613 progress 50 % (4 MB)
106 00:58:07.369164 progress 55 % (4 MB)
107 00:58:07.394242 progress 60 % (4 MB)
108 00:58:07.418684 progress 65 % (5 MB)
109 00:58:07.446026 progress 70 % (5 MB)
110 00:58:07.470695 progress 75 % (6 MB)
111 00:58:07.496912 progress 80 % (6 MB)
112 00:58:07.521420 progress 85 % (7 MB)
113 00:58:07.546981 progress 90 % (7 MB)
114 00:58:07.572890 progress 95 % (7 MB)
115 00:58:07.598553 progress 100 % (8 MB)
116 00:58:07.604593 8 MB downloaded in 0.52 s (15.95 MB/s)
117 00:58:07.604853 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:58:07.605127 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:58:07.605225 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:58:07.605364 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:58:07.605447 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:58:07.605537 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:58:07.605765 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr
125 00:58:07.605897 makedir: /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin
126 00:58:07.605999 makedir: /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/tests
127 00:58:07.606097 makedir: /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/results
128 00:58:07.606212 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-add-keys
129 00:58:07.606357 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-add-sources
130 00:58:07.606491 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-background-process-start
131 00:58:07.606622 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-background-process-stop
132 00:58:07.606748 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-common-functions
133 00:58:07.606873 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-echo-ipv4
134 00:58:07.606998 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-install-packages
135 00:58:07.607122 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-installed-packages
136 00:58:07.607245 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-os-build
137 00:58:07.607371 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-probe-channel
138 00:58:07.607517 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-probe-ip
139 00:58:07.607683 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-target-ip
140 00:58:07.607814 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-target-mac
141 00:58:07.607940 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-target-storage
142 00:58:07.608069 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-test-case
143 00:58:07.608193 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-test-event
144 00:58:07.608317 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-test-feedback
145 00:58:07.608440 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-test-raise
146 00:58:07.608563 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-test-reference
147 00:58:07.608688 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-test-runner
148 00:58:07.608812 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-test-set
149 00:58:07.608938 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-test-shell
150 00:58:07.609065 Updating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-install-packages (oe)
151 00:58:07.609215 Updating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/bin/lava-installed-packages (oe)
152 00:58:07.609378 Creating /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/environment
153 00:58:07.609478 LAVA metadata
154 00:58:07.609551 - LAVA_JOB_ID=14368604
155 00:58:07.609617 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:58:07.609718 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:58:07.609786 skipped lava-vland-overlay
158 00:58:07.609860 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:58:07.609948 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:58:07.610023 skipped lava-multinode-overlay
161 00:58:07.610097 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:58:07.610182 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:58:07.610257 Loading test definitions
164 00:58:07.610347 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:58:07.610419 Using /lava-14368604 at stage 0
166 00:58:07.610733 uuid=14368604_1.5.2.3.1 testdef=None
167 00:58:07.610822 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:58:07.610906 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:58:07.611433 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:58:07.611666 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:58:07.612302 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:58:07.612533 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:58:07.613162 runner path: /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/0/tests/0_igt-kms-mediatek test_uuid 14368604_1.5.2.3.1
176 00:58:07.613368 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:58:07.613576 Creating lava-test-runner.conf files
179 00:58:07.613640 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368604/lava-overlay-iz4jpvnr/lava-14368604/0 for stage 0
180 00:58:07.613730 - 0_igt-kms-mediatek
181 00:58:07.613825 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:58:07.613909 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:58:07.621151 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:58:07.621274 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:58:07.621363 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:58:07.621451 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:58:07.621535 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:58:09.390500 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 00:58:09.390881 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 00:58:09.390997 extracting modules file /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368604/extract-overlay-ramdisk-y4uvdmsk/ramdisk
191 00:58:09.612941 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:58:09.613115 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 00:58:09.613213 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368604/compress-overlay-q1ny6vvw/overlay-1.5.2.4.tar.gz to ramdisk
194 00:58:09.613326 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368604/compress-overlay-q1ny6vvw/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368604/extract-overlay-ramdisk-y4uvdmsk/ramdisk
195 00:58:09.620115 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:58:09.620247 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 00:58:09.620342 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:58:09.620431 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 00:58:09.620513 Building ramdisk /var/lib/lava/dispatcher/tmp/14368604/extract-overlay-ramdisk-y4uvdmsk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368604/extract-overlay-ramdisk-y4uvdmsk/ramdisk
200 00:58:10.855527 >> 465988 blocks
201 00:58:17.059750 rename /var/lib/lava/dispatcher/tmp/14368604/extract-overlay-ramdisk-y4uvdmsk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/ramdisk/ramdisk.cpio.gz
202 00:58:17.060201 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 00:58:17.060331 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 00:58:17.060439 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 00:58:17.060548 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/kernel/Image']
206 00:58:30.676606 Returned 0 in 13 seconds
207 00:58:30.777606 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/kernel/image.itb
208 00:58:31.665577 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:58:31.665959 output: Created: Sun Jun 16 01:58:31 2024
210 00:58:31.666056 output: Image 0 (kernel-1)
211 00:58:31.666142 output: Description:
212 00:58:31.666222 output: Created: Sun Jun 16 01:58:31 2024
213 00:58:31.666302 output: Type: Kernel Image
214 00:58:31.666380 output: Compression: lzma compressed
215 00:58:31.666477 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
216 00:58:31.666580 output: Architecture: AArch64
217 00:58:31.666676 output: OS: Linux
218 00:58:31.666772 output: Load Address: 0x00000000
219 00:58:31.666872 output: Entry Point: 0x00000000
220 00:58:31.666969 output: Hash algo: crc32
221 00:58:31.667069 output: Hash value: f6f06660
222 00:58:31.667166 output: Image 1 (fdt-1)
223 00:58:31.667263 output: Description: mt8192-asurada-spherion-r0
224 00:58:31.667357 output: Created: Sun Jun 16 01:58:31 2024
225 00:58:31.667449 output: Type: Flat Device Tree
226 00:58:31.667545 output: Compression: uncompressed
227 00:58:31.667648 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:58:31.667735 output: Architecture: AArch64
229 00:58:31.667819 output: Hash algo: crc32
230 00:58:31.667902 output: Hash value: 0f8e4d2e
231 00:58:31.667985 output: Image 2 (ramdisk-1)
232 00:58:31.668067 output: Description: unavailable
233 00:58:31.668149 output: Created: Sun Jun 16 01:58:31 2024
234 00:58:31.668231 output: Type: RAMDisk Image
235 00:58:31.668313 output: Compression: Unknown Compression
236 00:58:31.668395 output: Data Size: 60993954 Bytes = 59564.41 KiB = 58.17 MiB
237 00:58:31.668477 output: Architecture: AArch64
238 00:58:31.668559 output: OS: Linux
239 00:58:31.668640 output: Load Address: unavailable
240 00:58:31.668722 output: Entry Point: unavailable
241 00:58:31.668803 output: Hash algo: crc32
242 00:58:31.668885 output: Hash value: 76d32db1
243 00:58:31.668966 output: Default Configuration: 'conf-1'
244 00:58:31.669048 output: Configuration 0 (conf-1)
245 00:58:31.669129 output: Description: mt8192-asurada-spherion-r0
246 00:58:31.669211 output: Kernel: kernel-1
247 00:58:31.669348 output: Init Ramdisk: ramdisk-1
248 00:58:31.669432 output: FDT: fdt-1
249 00:58:31.669514 output: Loadables: kernel-1
250 00:58:31.669595 output:
251 00:58:31.669828 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 00:58:31.669953 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 00:58:31.670086 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 00:58:31.670209 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 00:58:31.670314 No LXC device requested
256 00:58:31.670425 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:58:31.670538 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 00:58:31.670643 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:58:31.670742 Checking files for TFTP limit of 4294967296 bytes.
260 00:58:31.671387 end: 1 tftp-deploy (duration 00:00:25) [common]
261 00:58:31.671517 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:58:31.671637 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:58:31.671794 substitutions:
264 00:58:31.671885 - {DTB}: 14368604/tftp-deploy-t37rlqdm/dtb/mt8192-asurada-spherion-r0.dtb
265 00:58:31.671977 - {INITRD}: 14368604/tftp-deploy-t37rlqdm/ramdisk/ramdisk.cpio.gz
266 00:58:31.672064 - {KERNEL}: 14368604/tftp-deploy-t37rlqdm/kernel/Image
267 00:58:31.672149 - {LAVA_MAC}: None
268 00:58:31.672234 - {PRESEED_CONFIG}: None
269 00:58:31.672318 - {PRESEED_LOCAL}: None
270 00:58:31.672402 - {RAMDISK}: 14368604/tftp-deploy-t37rlqdm/ramdisk/ramdisk.cpio.gz
271 00:58:31.672485 - {ROOT_PART}: None
272 00:58:31.672568 - {ROOT}: None
273 00:58:31.672651 - {SERVER_IP}: 192.168.201.1
274 00:58:31.672733 - {TEE}: None
275 00:58:31.672815 Parsed boot commands:
276 00:58:31.672896 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:58:31.673112 Parsed boot commands: tftpboot 192.168.201.1 14368604/tftp-deploy-t37rlqdm/kernel/image.itb 14368604/tftp-deploy-t37rlqdm/kernel/cmdline
278 00:58:31.673227 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:58:31.673368 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:58:31.673458 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:58:31.673543 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:58:31.673612 Not connected, no need to disconnect.
283 00:58:31.673684 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:58:31.673763 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:58:31.673830 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 00:58:31.677499 Setting prompt string to ['lava-test: # ']
287 00:58:31.677855 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:58:31.677955 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:58:31.678052 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:58:31.678141 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:58:31.678317 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
292 00:58:45.746662 Returned 0 in 14 seconds
293 00:58:45.847862 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 00:58:45.849857 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 00:58:45.850503 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 00:58:45.851076 Setting prompt string to 'Starting depthcharge on Spherion...'
298 00:58:45.851572 Changing prompt to 'Starting depthcharge on Spherion...'
299 00:58:45.852129 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 00:58:45.854375 [Enter `^Ec?' for help]
301 00:58:45.854775
302 00:58:45.855127
303 00:58:45.855451 F0: 102B 0000
304 00:58:45.855760
305 00:58:45.856065 F3: 1001 0000 [0200]
306 00:58:45.856369
307 00:58:45.856800 F3: 1001 0000
308 00:58:45.857118
309 00:58:45.857472 F7: 102D 0000
310 00:58:45.857771
311 00:58:45.858055 F1: 0000 0000
312 00:58:45.858339
313 00:58:45.858621 V0: 0000 0000 [0001]
314 00:58:45.859027
315 00:58:45.859346 00: 0007 8000
316 00:58:45.859644
317 00:58:45.859925 01: 0000 0000
318 00:58:45.860209
319 00:58:45.860491 BP: 0C00 0209 [0000]
320 00:58:45.860773
321 00:58:45.861108 G0: 1182 0000
322 00:58:45.861542
323 00:58:45.861928 EC: 0000 0021 [4000]
324 00:58:45.862309
325 00:58:45.862689 S7: 0000 0000 [0000]
326 00:58:45.863063
327 00:58:45.863477 CC: 0000 0000 [0001]
328 00:58:45.863857
329 00:58:45.864335 T0: 0000 0040 [010F]
330 00:58:45.864723
331 00:58:45.865102 Jump to BL
332 00:58:45.865591
333 00:58:45.865977
334 00:58:45.866355
335 00:58:45.866734 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 00:58:45.867137 ARM64: Exception handlers installed.
337 00:58:45.867521 ARM64: Testing exception
338 00:58:45.867900 ARM64: Done test exception
339 00:58:45.868381 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 00:58:45.868770 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 00:58:45.869276 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 00:58:45.869751 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 00:58:45.870141 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 00:58:45.870526 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 00:58:45.870907 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 00:58:45.871292 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 00:58:45.871676 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 00:58:45.872057 WDT: Last reset was cold boot
349 00:58:45.872440 SPI1(PAD0) initialized at 2873684 Hz
350 00:58:45.872922 SPI5(PAD0) initialized at 992727 Hz
351 00:58:45.873433 VBOOT: Loading verstage.
352 00:58:45.873824 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 00:58:45.874209 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 00:58:45.874590 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 00:58:45.874972 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 00:58:45.875353 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 00:58:45.875744 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 00:58:45.876016 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 00:58:45.876359
360 00:58:45.876702
361 00:58:45.877043 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 00:58:45.877404 ARM64: Exception handlers installed.
363 00:58:45.877682 ARM64: Testing exception
364 00:58:45.878026 ARM64: Done test exception
365 00:58:45.878335 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 00:58:45.878613 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 00:58:45.878886 Probing TPM: . done!
368 00:58:45.879156 TPM ready after 0 ms
369 00:58:45.879430 Connected to device vid:did:rid of 1ae0:0028:00
370 00:58:45.879702 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
371 00:58:45.879976 Initialized TPM device CR50 revision 0
372 00:58:45.880278 tlcl_send_startup: Startup return code is 0
373 00:58:45.880618 TPM: setup succeeded
374 00:58:45.880915 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 00:58:45.881174 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 00:58:45.881409 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 00:58:45.881618 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:58:45.881822 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 00:58:45.882027 in-header: 03 07 00 00 08 00 00 00
380 00:58:45.882232 in-data: aa e4 47 04 13 02 00 00
381 00:58:45.882437 Chrome EC: UHEPI supported
382 00:58:45.882694 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 00:58:45.882954 in-header: 03 a9 00 00 08 00 00 00
384 00:58:45.883212 in-data: 84 60 60 08 00 00 00 00
385 00:58:45.883415 Phase 1
386 00:58:45.883618 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 00:58:45.883823 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 00:58:45.884028 VB2:vb2_check_recovery() Recovery was requested manually
389 00:58:45.884232 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 00:58:45.884437 Recovery requested (1009000e)
391 00:58:45.884694 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:58:45.884953 tlcl_extend: response is 0
393 00:58:45.885212 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:58:45.885434 tlcl_extend: response is 0
395 00:58:45.885640 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:58:45.885838 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 00:58:45.886007 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:58:45.886214
399 00:58:45.886419
400 00:58:45.886632 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:58:45.886840 ARM64: Exception handlers installed.
402 00:58:45.887046 ARM64: Testing exception
403 00:58:45.887252 ARM64: Done test exception
404 00:58:45.887456 pmic_efuse_setting: Set efuses in 11 msecs
405 00:58:45.887662 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:58:45.887867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:58:45.888072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:58:45.888524 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:58:45.888752 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:58:45.888969 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:58:45.889181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:58:45.889415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:58:45.889612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:58:45.889744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:58:45.889870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:58:45.889993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:58:45.890115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:58:45.890236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:58:45.890437 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:58:45.890566 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:58:45.890688 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:58:45.890814 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:58:45.890920 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:58:45.891086 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:58:45.891226 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:58:45.891397 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:58:45.891533 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:58:45.891669 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:58:45.891839 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:58:45.892015 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:58:45.892151 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:58:45.892323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:58:45.892459 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:58:45.892595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:58:45.892737 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:58:45.892914 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:58:45.893086 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:58:45.893263 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:58:45.893438 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:58:45.893612 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:58:45.893784 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:58:45.893960 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:58:45.894134 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:58:45.894306 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:58:45.894479 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:58:45.894649 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:58:45.894821 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:58:45.894992 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:58:45.895177 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:58:45.895352 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:58:45.895524 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:58:45.895697 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:58:45.895865 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:58:45.896013 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:58:45.896162 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:58:45.896309 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:58:45.896455 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:58:45.896604 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:58:45.896752 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:58:45.896899 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:58:45.897047 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:58:45.897195 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:58:45.897357 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:58:45.897506 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:58:45.897654 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
466 00:58:45.897803 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:58:45.897951 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
468 00:58:45.898099 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:58:45.898247 [RTC]rtc_get_frequency_meter,154: input=15, output=852
470 00:58:45.898395 [RTC]rtc_get_frequency_meter,154: input=7, output=725
471 00:58:45.898542 [RTC]rtc_get_frequency_meter,154: input=11, output=789
472 00:58:45.898689 [RTC]rtc_get_frequency_meter,154: input=13, output=821
473 00:58:45.898836 [RTC]rtc_get_frequency_meter,154: input=12, output=805
474 00:58:45.898982 [RTC]rtc_get_frequency_meter,154: input=11, output=789
475 00:58:45.899128 [RTC]rtc_get_frequency_meter,154: input=12, output=804
476 00:58:45.899274 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
477 00:58:45.899421 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
478 00:58:45.899782 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 00:58:45.899938 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 00:58:45.900092 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 00:58:45.900254 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 00:58:45.900407 ADC[4]: Raw value=903325 ID=7
483 00:58:45.900558 ADC[3]: Raw value=213916 ID=1
484 00:58:45.900708 RAM Code: 0x71
485 00:58:45.900857 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 00:58:45.900988 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 00:58:45.901119 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 00:58:45.901255 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 00:58:45.901398 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 00:58:45.901531 in-header: 03 07 00 00 08 00 00 00
491 00:58:45.901662 in-data: aa e4 47 04 13 02 00 00
492 00:58:45.901793 Chrome EC: UHEPI supported
493 00:58:45.901923 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 00:58:45.902053 in-header: 03 a9 00 00 08 00 00 00
495 00:58:45.902185 in-data: 84 60 60 08 00 00 00 00
496 00:58:45.902315 MRC: failed to locate region type 0.
497 00:58:45.902444 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 00:58:45.902573 DRAM-K: Running full calibration
499 00:58:45.902702 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 00:58:45.902831 header.status = 0x0
501 00:58:45.902959 header.version = 0x6 (expected: 0x6)
502 00:58:45.903088 header.size = 0xd00 (expected: 0xd00)
503 00:58:45.903216 header.flags = 0x0
504 00:58:45.903344 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 00:58:45.903474 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 00:58:45.903603 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 00:58:45.903732 dram_init: ddr_geometry: 2
508 00:58:45.903860 [EMI] MDL number = 2
509 00:58:45.903989 [EMI] Get MDL freq = 0
510 00:58:45.904117 dram_init: ddr_type: 0
511 00:58:45.904260 is_discrete_lpddr4: 1
512 00:58:45.904389 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 00:58:45.904517
514 00:58:45.904646
515 00:58:45.904775 [Bian_co] ETT version 0.0.0.1
516 00:58:45.904905 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 00:58:45.905034
518 00:58:45.905163 dramc_set_vcore_voltage set vcore to 650000
519 00:58:45.905303 Read voltage for 800, 4
520 00:58:45.905408 Vio18 = 0
521 00:58:45.905511 Vcore = 650000
522 00:58:45.905613 Vdram = 0
523 00:58:45.905727 Vddq = 0
524 00:58:45.905843 Vmddr = 0
525 00:58:45.905959 dram_init: config_dvfs: 1
526 00:58:45.906075 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 00:58:45.906192 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 00:58:45.906308 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 00:58:45.906424 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 00:58:45.906540 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 00:58:45.906656 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 00:58:45.906771 MEM_TYPE=3, freq_sel=18
533 00:58:45.906886 sv_algorithm_assistance_LP4_1600
534 00:58:45.907001 ============ PULL DRAM RESETB DOWN ============
535 00:58:45.907117 ========== PULL DRAM RESETB DOWN end =========
536 00:58:45.907233 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 00:58:45.907348 ===================================
538 00:58:45.907463 LPDDR4 DRAM CONFIGURATION
539 00:58:45.907578 ===================================
540 00:58:45.907693 EX_ROW_EN[0] = 0x0
541 00:58:45.907807 EX_ROW_EN[1] = 0x0
542 00:58:45.907922 LP4Y_EN = 0x0
543 00:58:45.908037 WORK_FSP = 0x0
544 00:58:45.908151 WL = 0x2
545 00:58:45.908265 RL = 0x2
546 00:58:45.908380 BL = 0x2
547 00:58:45.908494 RPST = 0x0
548 00:58:45.908607 RD_PRE = 0x0
549 00:58:45.908720 WR_PRE = 0x1
550 00:58:45.908834 WR_PST = 0x0
551 00:58:45.908947 DBI_WR = 0x0
552 00:58:45.909060 DBI_RD = 0x0
553 00:58:45.909173 OTF = 0x1
554 00:58:45.909294 ===================================
555 00:58:45.909411 ===================================
556 00:58:45.909526 ANA top config
557 00:58:45.909640 ===================================
558 00:58:45.909755 DLL_ASYNC_EN = 0
559 00:58:45.909869 ALL_SLAVE_EN = 1
560 00:58:45.909983 NEW_RANK_MODE = 1
561 00:58:45.910101 DLL_IDLE_MODE = 1
562 00:58:45.910216 LP45_APHY_COMB_EN = 1
563 00:58:45.910330 TX_ODT_DIS = 1
564 00:58:45.910445 NEW_8X_MODE = 1
565 00:58:45.910560 ===================================
566 00:58:45.910675 ===================================
567 00:58:45.910797 data_rate = 1600
568 00:58:45.910899 CKR = 1
569 00:58:45.911002 DQ_P2S_RATIO = 8
570 00:58:45.911105 ===================================
571 00:58:45.911208 CA_P2S_RATIO = 8
572 00:58:45.911311 DQ_CA_OPEN = 0
573 00:58:45.911413 DQ_SEMI_OPEN = 0
574 00:58:45.911516 CA_SEMI_OPEN = 0
575 00:58:45.911618 CA_FULL_RATE = 0
576 00:58:45.911721 DQ_CKDIV4_EN = 1
577 00:58:45.911824 CA_CKDIV4_EN = 1
578 00:58:45.911926 CA_PREDIV_EN = 0
579 00:58:45.912028 PH8_DLY = 0
580 00:58:45.912130 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 00:58:45.912232 DQ_AAMCK_DIV = 4
582 00:58:45.912334 CA_AAMCK_DIV = 4
583 00:58:45.912436 CA_ADMCK_DIV = 4
584 00:58:45.912538 DQ_TRACK_CA_EN = 0
585 00:58:45.912640 CA_PICK = 800
586 00:58:45.912743 CA_MCKIO = 800
587 00:58:45.912845 MCKIO_SEMI = 0
588 00:58:45.912947 PLL_FREQ = 3068
589 00:58:45.913050 DQ_UI_PI_RATIO = 32
590 00:58:45.913153 CA_UI_PI_RATIO = 0
591 00:58:45.913254 ===================================
592 00:58:45.913363 ===================================
593 00:58:45.913466 memory_type:LPDDR4
594 00:58:45.913570 GP_NUM : 10
595 00:58:45.913673 SRAM_EN : 1
596 00:58:45.913776 MD32_EN : 0
597 00:58:45.913880 ===================================
598 00:58:45.914195 [ANA_INIT] >>>>>>>>>>>>>>
599 00:58:45.914301 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 00:58:45.914411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 00:58:45.914517 ===================================
602 00:58:45.914623 data_rate = 1600,PCW = 0X7600
603 00:58:45.914728 ===================================
604 00:58:45.914834 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 00:58:45.914939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 00:58:45.915044 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:58:45.915149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 00:58:45.915253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 00:58:45.915356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:58:45.915460 [ANA_INIT] flow start
611 00:58:45.915563 [ANA_INIT] PLL >>>>>>>>
612 00:58:45.915665 [ANA_INIT] PLL <<<<<<<<
613 00:58:45.915777 [ANA_INIT] MIDPI >>>>>>>>
614 00:58:45.915871 [ANA_INIT] MIDPI <<<<<<<<
615 00:58:45.915964 [ANA_INIT] DLL >>>>>>>>
616 00:58:45.916057 [ANA_INIT] flow end
617 00:58:45.916151 ============ LP4 DIFF to SE enter ============
618 00:58:45.916245 ============ LP4 DIFF to SE exit ============
619 00:58:45.916339 [ANA_INIT] <<<<<<<<<<<<<
620 00:58:45.916433 [Flow] Enable top DCM control >>>>>
621 00:58:45.916526 [Flow] Enable top DCM control <<<<<
622 00:58:45.916619 Enable DLL master slave shuffle
623 00:58:45.916713 ==============================================================
624 00:58:45.916807 Gating Mode config
625 00:58:45.916900 ==============================================================
626 00:58:45.916994 Config description:
627 00:58:45.917087 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 00:58:45.917182 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 00:58:45.917286 SELPH_MODE 0: By rank 1: By Phase
630 00:58:45.917383 ==============================================================
631 00:58:45.917478 GAT_TRACK_EN = 1
632 00:58:45.917572 RX_GATING_MODE = 2
633 00:58:45.917667 RX_GATING_TRACK_MODE = 2
634 00:58:45.917761 SELPH_MODE = 1
635 00:58:45.917855 PICG_EARLY_EN = 1
636 00:58:45.917949 VALID_LAT_VALUE = 1
637 00:58:45.918042 ==============================================================
638 00:58:45.918137 Enter into Gating configuration >>>>
639 00:58:45.918230 Exit from Gating configuration <<<<
640 00:58:45.918324 Enter into DVFS_PRE_config >>>>>
641 00:58:45.918417 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 00:58:45.918514 Exit from DVFS_PRE_config <<<<<
643 00:58:45.918608 Enter into PICG configuration >>>>
644 00:58:45.918702 Exit from PICG configuration <<<<
645 00:58:45.918795 [RX_INPUT] configuration >>>>>
646 00:58:45.918888 [RX_INPUT] configuration <<<<<
647 00:58:45.918982 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 00:58:45.919076 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 00:58:45.919170 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 00:58:45.919264 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 00:58:45.919358 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 00:58:45.919452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 00:58:45.919547 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 00:58:45.919640 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 00:58:45.919734 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 00:58:45.919828 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 00:58:45.919921 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 00:58:45.920015 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 00:58:45.920109 ===================================
660 00:58:45.920203 LPDDR4 DRAM CONFIGURATION
661 00:58:45.920296 ===================================
662 00:58:45.920390 EX_ROW_EN[0] = 0x0
663 00:58:45.920483 EX_ROW_EN[1] = 0x0
664 00:58:45.920576 LP4Y_EN = 0x0
665 00:58:45.920670 WORK_FSP = 0x0
666 00:58:45.920774 WL = 0x2
667 00:58:45.920865 RL = 0x2
668 00:58:45.920956 BL = 0x2
669 00:58:45.921047 RPST = 0x0
670 00:58:45.921139 RD_PRE = 0x0
671 00:58:45.921230 WR_PRE = 0x1
672 00:58:45.921359 WR_PST = 0x0
673 00:58:45.921451 DBI_WR = 0x0
674 00:58:45.921543 DBI_RD = 0x0
675 00:58:45.921634 OTF = 0x1
676 00:58:45.921725 ===================================
677 00:58:45.921817 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 00:58:45.921909 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 00:58:45.922001 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 00:58:45.922092 ===================================
681 00:58:45.922184 LPDDR4 DRAM CONFIGURATION
682 00:58:45.922276 ===================================
683 00:58:45.922368 EX_ROW_EN[0] = 0x10
684 00:58:45.922459 EX_ROW_EN[1] = 0x0
685 00:58:45.922550 LP4Y_EN = 0x0
686 00:58:45.922641 WORK_FSP = 0x0
687 00:58:45.922735 WL = 0x2
688 00:58:45.922826 RL = 0x2
689 00:58:45.922916 BL = 0x2
690 00:58:45.923007 RPST = 0x0
691 00:58:45.923097 RD_PRE = 0x0
692 00:58:45.923188 WR_PRE = 0x1
693 00:58:45.923279 WR_PST = 0x0
694 00:58:45.923370 DBI_WR = 0x0
695 00:58:45.923461 DBI_RD = 0x0
696 00:58:45.923551 OTF = 0x1
697 00:58:45.923642 ===================================
698 00:58:45.923734 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 00:58:45.923825 nWR fixed to 40
700 00:58:45.923918 [ModeRegInit_LP4] CH0 RK0
701 00:58:45.924009 [ModeRegInit_LP4] CH0 RK1
702 00:58:45.924100 [ModeRegInit_LP4] CH1 RK0
703 00:58:45.924191 [ModeRegInit_LP4] CH1 RK1
704 00:58:45.924282 match AC timing 13
705 00:58:45.924373 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 00:58:45.924662 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 00:58:45.924758 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 00:58:45.924855 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 00:58:45.924951 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 00:58:45.925045 [EMI DOE] emi_dcm 0
711 00:58:45.925138 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 00:58:45.925231 ==
713 00:58:45.925367 Dram Type= 6, Freq= 0, CH_0, rank 0
714 00:58:45.925462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 00:58:45.925556 ==
716 00:58:45.925649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 00:58:45.925742 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 00:58:45.925835 [CA 0] Center 37 (7~68) winsize 62
719 00:58:45.925928 [CA 1] Center 37 (6~68) winsize 63
720 00:58:45.926021 [CA 2] Center 35 (5~65) winsize 61
721 00:58:45.926114 [CA 3] Center 34 (4~65) winsize 62
722 00:58:45.926206 [CA 4] Center 33 (3~64) winsize 62
723 00:58:45.926298 [CA 5] Center 33 (3~64) winsize 62
724 00:58:45.926390
725 00:58:45.926482 [CmdBusTrainingLP45] Vref(ca) range 1: 32
726 00:58:45.926574
727 00:58:45.926666 [CATrainingPosCal] consider 1 rank data
728 00:58:45.926758 u2DelayCellTimex100 = 270/100 ps
729 00:58:45.926851 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 00:58:45.926944 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 00:58:45.927036 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
732 00:58:45.927129 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 00:58:45.927221 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 00:58:45.927313 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 00:58:45.927404
736 00:58:45.927496 CA PerBit enable=1, Macro0, CA PI delay=33
737 00:58:45.927588
738 00:58:45.927679 [CBTSetCACLKResult] CA Dly = 33
739 00:58:45.927771 CS Dly: 5 (0~36)
740 00:58:45.927862 ==
741 00:58:45.927954 Dram Type= 6, Freq= 0, CH_0, rank 1
742 00:58:45.928046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 00:58:45.928138 ==
744 00:58:45.928230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 00:58:45.928323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 00:58:45.928415 [CA 0] Center 38 (7~69) winsize 63
747 00:58:45.928507 [CA 1] Center 37 (7~68) winsize 62
748 00:58:45.928598 [CA 2] Center 35 (4~66) winsize 63
749 00:58:45.928690 [CA 3] Center 34 (4~65) winsize 62
750 00:58:45.928782 [CA 4] Center 34 (3~65) winsize 63
751 00:58:45.928873 [CA 5] Center 33 (3~64) winsize 62
752 00:58:45.928964
753 00:58:45.929056 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 00:58:45.929148
755 00:58:45.929240 [CATrainingPosCal] consider 2 rank data
756 00:58:45.929374 u2DelayCellTimex100 = 270/100 ps
757 00:58:45.929467 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 00:58:45.929559 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 00:58:45.929651 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
760 00:58:45.929744 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 00:58:45.929836 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 00:58:45.929927 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 00:58:45.930019
764 00:58:45.930110 CA PerBit enable=1, Macro0, CA PI delay=33
765 00:58:45.930202
766 00:58:45.930293 [CBTSetCACLKResult] CA Dly = 33
767 00:58:45.930385 CS Dly: 6 (0~38)
768 00:58:45.930477
769 00:58:45.930568 ----->DramcWriteLeveling(PI) begin...
770 00:58:45.930662 ==
771 00:58:45.930754 Dram Type= 6, Freq= 0, CH_0, rank 0
772 00:58:45.930846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 00:58:45.930938 ==
774 00:58:45.931030 Write leveling (Byte 0): 33 => 33
775 00:58:45.931122 Write leveling (Byte 1): 27 => 27
776 00:58:45.931214 DramcWriteLeveling(PI) end<-----
777 00:58:45.931305
778 00:58:45.931396 ==
779 00:58:45.931488 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:58:45.931580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:58:45.931672 ==
782 00:58:45.931764 [Gating] SW mode calibration
783 00:58:45.931856 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 00:58:45.931949 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 00:58:45.932041 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 00:58:45.932133 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 00:58:45.932226 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 00:58:45.932318 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 00:58:45.932419 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:58:45.932512 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:58:45.932604 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:58:45.932696 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:58:45.932788 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:58:45.932880 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:58:45.932972 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:58:45.933063 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:58:45.933155 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:58:45.933246 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:58:45.933383 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:58:45.933475 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:58:45.933566 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:58:45.933658 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 00:58:45.933750 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
804 00:58:45.933842 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 00:58:45.933934 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:58:45.934026 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:58:45.934117 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:58:45.934209 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:58:45.934300 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:58:45.934392 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:58:45.934496 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
812 00:58:45.934589 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
813 00:58:45.934681 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 00:58:45.934970 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:58:45.935066 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:58:45.935162 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:58:45.935256 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:58:45.935350 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
819 00:58:45.935444 0 10 8 | B1->B0 | 3131 2424 | 1 0 | (1 0) (0 0)
820 00:58:45.935537 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
821 00:58:45.935630 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:58:45.935722 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:58:45.935815 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:58:45.935908 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:58:45.936000 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:58:45.936092 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
827 00:58:45.936184 0 11 8 | B1->B0 | 2d2d 4545 | 0 0 | (0 0) (0 0)
828 00:58:45.936277 0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
829 00:58:45.936369 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 00:58:45.936469 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:58:45.936574 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:58:45.936663 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:58:45.936749 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:58:45.936835 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 00:58:45.936919 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
836 00:58:45.937003 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 00:58:45.937087 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:58:45.937171 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:58:45.937264 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:58:45.937386 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:58:45.937470 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:58:45.937555 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:58:45.937639 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:58:45.937723 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:58:45.937807 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:58:45.937890 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:58:45.937974 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:58:45.938058 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:58:45.938142 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:58:45.938225 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 00:58:45.938309 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 00:58:45.938393 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 00:58:45.938476 Total UI for P1: 0, mck2ui 16
854 00:58:45.938561 best dqsien dly found for B0: ( 0, 14, 6)
855 00:58:45.938645 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 00:58:45.938729 Total UI for P1: 0, mck2ui 16
857 00:58:45.938813 best dqsien dly found for B1: ( 0, 14, 10)
858 00:58:45.938897 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 00:58:45.938981 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 00:58:45.939064
861 00:58:45.939147 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 00:58:45.939232 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 00:58:45.939315 [Gating] SW calibration Done
864 00:58:45.939398 ==
865 00:58:45.939481 Dram Type= 6, Freq= 0, CH_0, rank 0
866 00:58:45.939565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 00:58:45.939649 ==
868 00:58:45.939732 RX Vref Scan: 0
869 00:58:45.939814
870 00:58:45.939897 RX Vref 0 -> 0, step: 1
871 00:58:45.939979
872 00:58:45.940062 RX Delay -130 -> 252, step: 16
873 00:58:45.940146 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 00:58:45.940230 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 00:58:45.940314 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 00:58:45.940398 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 00:58:45.940481 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 00:58:45.940565 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 00:58:45.940649 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 00:58:45.940733 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 00:58:45.940816 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 00:58:45.940900 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 00:58:45.940984 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 00:58:45.941068 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 00:58:45.941151 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 00:58:45.941235 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 00:58:45.941323 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 00:58:45.941407 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 00:58:45.941490 ==
890 00:58:45.941574 Dram Type= 6, Freq= 0, CH_0, rank 0
891 00:58:45.941658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 00:58:45.941741 ==
893 00:58:45.941824 DQS Delay:
894 00:58:45.941907 DQS0 = 0, DQS1 = 0
895 00:58:45.941990 DQM Delay:
896 00:58:45.942072 DQM0 = 88, DQM1 = 75
897 00:58:45.942155 DQ Delay:
898 00:58:45.942238 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 00:58:45.942322 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
900 00:58:45.942410 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
901 00:58:45.942467 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 00:58:45.942521
903 00:58:45.942573
904 00:58:45.942626 ==
905 00:58:45.942680 Dram Type= 6, Freq= 0, CH_0, rank 0
906 00:58:45.942733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 00:58:45.942788 ==
908 00:58:45.942841
909 00:58:45.942894
910 00:58:45.942946 TX Vref Scan disable
911 00:58:45.942999 == TX Byte 0 ==
912 00:58:45.943053 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 00:58:45.943107 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 00:58:45.943161 == TX Byte 1 ==
915 00:58:45.943214 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
916 00:58:45.943268 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
917 00:58:45.943321 ==
918 00:58:45.943375 Dram Type= 6, Freq= 0, CH_0, rank 0
919 00:58:45.943428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 00:58:45.943482 ==
921 00:58:45.943536 TX Vref=22, minBit 9, minWin=26, winSum=443
922 00:58:45.943781 TX Vref=24, minBit 1, minWin=27, winSum=445
923 00:58:45.943841 TX Vref=26, minBit 4, minWin=27, winSum=448
924 00:58:45.943897 TX Vref=28, minBit 5, minWin=27, winSum=451
925 00:58:45.943952 TX Vref=30, minBit 4, minWin=27, winSum=452
926 00:58:45.944006 TX Vref=32, minBit 5, minWin=27, winSum=447
927 00:58:45.944064 [TxChooseVref] Worse bit 4, Min win 27, Win sum 452, Final Vref 30
928 00:58:45.944118
929 00:58:45.944172 Final TX Range 1 Vref 30
930 00:58:45.944225
931 00:58:45.944278 ==
932 00:58:45.944332 Dram Type= 6, Freq= 0, CH_0, rank 0
933 00:58:45.944385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 00:58:45.944439 ==
935 00:58:45.944492
936 00:58:45.944582
937 00:58:45.944635 TX Vref Scan disable
938 00:58:45.944689 == TX Byte 0 ==
939 00:58:45.944742 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 00:58:45.944795 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 00:58:45.944849 == TX Byte 1 ==
942 00:58:45.944901 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 00:58:45.944958 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 00:58:45.945012
945 00:58:45.945065 [DATLAT]
946 00:58:45.945117 Freq=800, CH0 RK0
947 00:58:45.945171
948 00:58:45.945223 DATLAT Default: 0xa
949 00:58:45.945285 0, 0xFFFF, sum = 0
950 00:58:45.945341 1, 0xFFFF, sum = 0
951 00:58:45.945395 2, 0xFFFF, sum = 0
952 00:58:45.945449 3, 0xFFFF, sum = 0
953 00:58:45.945503 4, 0xFFFF, sum = 0
954 00:58:45.945557 5, 0xFFFF, sum = 0
955 00:58:45.945610 6, 0xFFFF, sum = 0
956 00:58:45.945663 7, 0xFFFF, sum = 0
957 00:58:45.945716 8, 0xFFFF, sum = 0
958 00:58:45.945770 9, 0x0, sum = 1
959 00:58:45.945823 10, 0x0, sum = 2
960 00:58:45.945877 11, 0x0, sum = 3
961 00:58:45.945930 12, 0x0, sum = 4
962 00:58:45.945984 best_step = 10
963 00:58:45.946037
964 00:58:45.946089 ==
965 00:58:45.946141 Dram Type= 6, Freq= 0, CH_0, rank 0
966 00:58:45.946195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 00:58:45.946248 ==
968 00:58:45.946300 RX Vref Scan: 1
969 00:58:45.946354
970 00:58:45.946410 Set Vref Range= 32 -> 127
971 00:58:45.946477
972 00:58:45.946530 RX Vref 32 -> 127, step: 1
973 00:58:45.946583
974 00:58:45.946636 RX Delay -111 -> 252, step: 8
975 00:58:45.946689
976 00:58:45.946741 Set Vref, RX VrefLevel [Byte0]: 32
977 00:58:45.946795 [Byte1]: 32
978 00:58:45.946848
979 00:58:45.946901 Set Vref, RX VrefLevel [Byte0]: 33
980 00:58:45.946955 [Byte1]: 33
981 00:58:45.947008
982 00:58:45.947061 Set Vref, RX VrefLevel [Byte0]: 34
983 00:58:45.947114 [Byte1]: 34
984 00:58:45.947167
985 00:58:45.947220 Set Vref, RX VrefLevel [Byte0]: 35
986 00:58:45.947273 [Byte1]: 35
987 00:58:45.947327
988 00:58:45.947379 Set Vref, RX VrefLevel [Byte0]: 36
989 00:58:45.947432 [Byte1]: 36
990 00:58:45.947485
991 00:58:45.947538 Set Vref, RX VrefLevel [Byte0]: 37
992 00:58:45.947590 [Byte1]: 37
993 00:58:45.947643
994 00:58:45.947697 Set Vref, RX VrefLevel [Byte0]: 38
995 00:58:45.947750 [Byte1]: 38
996 00:58:45.947803
997 00:58:45.947855 Set Vref, RX VrefLevel [Byte0]: 39
998 00:58:45.947908 [Byte1]: 39
999 00:58:45.947961
1000 00:58:45.948013 Set Vref, RX VrefLevel [Byte0]: 40
1001 00:58:45.948066 [Byte1]: 40
1002 00:58:45.948119
1003 00:58:45.948172 Set Vref, RX VrefLevel [Byte0]: 41
1004 00:58:45.948225 [Byte1]: 41
1005 00:58:45.948278
1006 00:58:45.948331 Set Vref, RX VrefLevel [Byte0]: 42
1007 00:58:45.948383 [Byte1]: 42
1008 00:58:45.948442
1009 00:58:45.948496 Set Vref, RX VrefLevel [Byte0]: 43
1010 00:58:45.948550 [Byte1]: 43
1011 00:58:45.948603
1012 00:58:45.948657 Set Vref, RX VrefLevel [Byte0]: 44
1013 00:58:45.948710 [Byte1]: 44
1014 00:58:45.948764
1015 00:58:45.948817 Set Vref, RX VrefLevel [Byte0]: 45
1016 00:58:45.948870 [Byte1]: 45
1017 00:58:45.948924
1018 00:58:45.948977 Set Vref, RX VrefLevel [Byte0]: 46
1019 00:58:45.949030 [Byte1]: 46
1020 00:58:45.949083
1021 00:58:45.949135 Set Vref, RX VrefLevel [Byte0]: 47
1022 00:58:45.949189 [Byte1]: 47
1023 00:58:45.949242
1024 00:58:45.949304 Set Vref, RX VrefLevel [Byte0]: 48
1025 00:58:45.949365 [Byte1]: 48
1026 00:58:45.949422
1027 00:58:45.949476 Set Vref, RX VrefLevel [Byte0]: 49
1028 00:58:45.949530 [Byte1]: 49
1029 00:58:45.949583
1030 00:58:45.949636 Set Vref, RX VrefLevel [Byte0]: 50
1031 00:58:45.949689 [Byte1]: 50
1032 00:58:45.949742
1033 00:58:45.949794 Set Vref, RX VrefLevel [Byte0]: 51
1034 00:58:45.949847 [Byte1]: 51
1035 00:58:45.949900
1036 00:58:45.949952 Set Vref, RX VrefLevel [Byte0]: 52
1037 00:58:45.950005 [Byte1]: 52
1038 00:58:45.950058
1039 00:58:45.950110 Set Vref, RX VrefLevel [Byte0]: 53
1040 00:58:45.950163 [Byte1]: 53
1041 00:58:45.950216
1042 00:58:45.950268 Set Vref, RX VrefLevel [Byte0]: 54
1043 00:58:45.950321 [Byte1]: 54
1044 00:58:45.950374
1045 00:58:45.950431 Set Vref, RX VrefLevel [Byte0]: 55
1046 00:58:45.950485 [Byte1]: 55
1047 00:58:45.950538
1048 00:58:45.950590 Set Vref, RX VrefLevel [Byte0]: 56
1049 00:58:45.950644 [Byte1]: 56
1050 00:58:45.950697
1051 00:58:45.950749 Set Vref, RX VrefLevel [Byte0]: 57
1052 00:58:45.950802 [Byte1]: 57
1053 00:58:45.950855
1054 00:58:45.950907 Set Vref, RX VrefLevel [Byte0]: 58
1055 00:58:45.950959 [Byte1]: 58
1056 00:58:45.951012
1057 00:58:45.951064 Set Vref, RX VrefLevel [Byte0]: 59
1058 00:58:45.951117 [Byte1]: 59
1059 00:58:45.951169
1060 00:58:45.951221 Set Vref, RX VrefLevel [Byte0]: 60
1061 00:58:45.951274 [Byte1]: 60
1062 00:58:45.951326
1063 00:58:45.951378 Set Vref, RX VrefLevel [Byte0]: 61
1064 00:58:45.951430 [Byte1]: 61
1065 00:58:45.951483
1066 00:58:45.951536 Set Vref, RX VrefLevel [Byte0]: 62
1067 00:58:45.951589 [Byte1]: 62
1068 00:58:45.951642
1069 00:58:45.951694 Set Vref, RX VrefLevel [Byte0]: 63
1070 00:58:45.951747 [Byte1]: 63
1071 00:58:45.951799
1072 00:58:45.951851 Set Vref, RX VrefLevel [Byte0]: 64
1073 00:58:45.951904 [Byte1]: 64
1074 00:58:45.951957
1075 00:58:45.952009 Set Vref, RX VrefLevel [Byte0]: 65
1076 00:58:45.952062 [Byte1]: 65
1077 00:58:45.952114
1078 00:58:45.952167 Set Vref, RX VrefLevel [Byte0]: 66
1079 00:58:45.952219 [Byte1]: 66
1080 00:58:45.952272
1081 00:58:45.952324 Set Vref, RX VrefLevel [Byte0]: 67
1082 00:58:45.952377 [Byte1]: 67
1083 00:58:45.952446
1084 00:58:45.952535 Set Vref, RX VrefLevel [Byte0]: 68
1085 00:58:45.952592 [Byte1]: 68
1086 00:58:45.952646
1087 00:58:45.952699 Set Vref, RX VrefLevel [Byte0]: 69
1088 00:58:45.952752 [Byte1]: 69
1089 00:58:45.952808
1090 00:58:45.953054 Set Vref, RX VrefLevel [Byte0]: 70
1091 00:58:45.953116 [Byte1]: 70
1092 00:58:45.953170
1093 00:58:45.953222 Set Vref, RX VrefLevel [Byte0]: 71
1094 00:58:45.953301 [Byte1]: 71
1095 00:58:45.953370
1096 00:58:45.953423 Set Vref, RX VrefLevel [Byte0]: 72
1097 00:58:45.953476 [Byte1]: 72
1098 00:58:45.953529
1099 00:58:45.953582 Set Vref, RX VrefLevel [Byte0]: 73
1100 00:58:45.953635 [Byte1]: 73
1101 00:58:45.953688
1102 00:58:45.953740 Final RX Vref Byte 0 = 57 to rank0
1103 00:58:45.953794 Final RX Vref Byte 1 = 59 to rank0
1104 00:58:45.953847 Final RX Vref Byte 0 = 57 to rank1
1105 00:58:45.953900 Final RX Vref Byte 1 = 59 to rank1==
1106 00:58:45.953953 Dram Type= 6, Freq= 0, CH_0, rank 0
1107 00:58:45.954006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1108 00:58:45.954059 ==
1109 00:58:45.954112 DQS Delay:
1110 00:58:45.954166 DQS0 = 0, DQS1 = 0
1111 00:58:45.954219 DQM Delay:
1112 00:58:45.954270 DQM0 = 88, DQM1 = 76
1113 00:58:45.954322 DQ Delay:
1114 00:58:45.954375 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1115 00:58:45.954427 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1116 00:58:45.954520 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1117 00:58:45.954573 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1118 00:58:45.954625
1119 00:58:45.954677
1120 00:58:45.954729 [DQSOSCAuto] RK0, (LSB)MR18= 0x3029, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1121 00:58:45.954783 CH0 RK0: MR19=606, MR18=3029
1122 00:58:45.954836 CH0_RK0: MR19=0x606, MR18=0x3029, DQSOSC=397, MR23=63, INC=93, DEC=62
1123 00:58:45.954889
1124 00:58:45.954942 ----->DramcWriteLeveling(PI) begin...
1125 00:58:45.954996 ==
1126 00:58:45.955049 Dram Type= 6, Freq= 0, CH_0, rank 1
1127 00:58:45.955101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1128 00:58:45.955155 ==
1129 00:58:45.955207 Write leveling (Byte 0): 30 => 30
1130 00:58:45.955261 Write leveling (Byte 1): 27 => 27
1131 00:58:45.955314 DramcWriteLeveling(PI) end<-----
1132 00:58:45.955367
1133 00:58:45.955419 ==
1134 00:58:45.955471 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 00:58:45.955525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 00:58:45.955579 ==
1137 00:58:45.955631 [Gating] SW mode calibration
1138 00:58:45.955684 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1139 00:58:45.955738 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1140 00:58:45.955791 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1141 00:58:45.955844 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1142 00:58:45.955897 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1143 00:58:45.955950 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1144 00:58:45.956003 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 00:58:45.956056 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 00:58:45.956108 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 00:58:45.956161 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 00:58:45.956214 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 00:58:45.956267 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 00:58:45.956320 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 00:58:45.956372 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 00:58:45.956425 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 00:58:45.956478 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 00:58:45.956530 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 00:58:45.956583 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 00:58:45.956636 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:58:45.956689 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1158 00:58:45.956741 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1159 00:58:45.956794 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:58:45.956846 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:58:45.956899 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:58:45.956951 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:58:45.957004 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:58:45.957057 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:58:45.957109 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1166 00:58:45.957162 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
1167 00:58:45.957215 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1168 00:58:45.957276 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 00:58:45.957366 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 00:58:45.957419 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 00:58:45.957472 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 00:58:45.957525 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 00:58:45.957578 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
1174 00:58:45.957631 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1175 00:58:45.957683 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:58:45.957736 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:58:45.957789 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:58:45.957841 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:58:45.957893 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:58:45.957946 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 00:58:45.957999 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1182 00:58:45.958052 0 11 8 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
1183 00:58:45.958104 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1184 00:58:45.958156 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 00:58:45.958209 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 00:58:45.958262 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 00:58:45.958314 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 00:58:45.958367 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1189 00:58:45.958419 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1190 00:58:45.958472 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1191 00:58:45.958716 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 00:58:45.958775 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 00:58:45.958867 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 00:58:45.958921 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 00:58:45.958974 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 00:58:45.959028 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 00:58:45.959081 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 00:58:45.959134 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 00:58:45.959187 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 00:58:45.959240 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 00:58:45.959293 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 00:58:45.959346 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 00:58:45.959399 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:58:45.959452 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:58:45.959505 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1206 00:58:45.959558 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 00:58:45.959610 Total UI for P1: 0, mck2ui 16
1208 00:58:45.959663 best dqsien dly found for B0: ( 0, 14, 4)
1209 00:58:45.959716 Total UI for P1: 0, mck2ui 16
1210 00:58:45.959769 best dqsien dly found for B1: ( 0, 14, 6)
1211 00:58:45.959822 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1212 00:58:45.959875 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1213 00:58:45.959928
1214 00:58:45.959980 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1215 00:58:45.960033 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1216 00:58:45.960086 [Gating] SW calibration Done
1217 00:58:45.960139 ==
1218 00:58:45.960191 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 00:58:45.960244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1220 00:58:45.960298 ==
1221 00:58:45.960350 RX Vref Scan: 0
1222 00:58:45.960402
1223 00:58:45.960454 RX Vref 0 -> 0, step: 1
1224 00:58:45.960506
1225 00:58:45.960558 RX Delay -130 -> 252, step: 16
1226 00:58:45.960612 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1227 00:58:45.960665 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1228 00:58:45.960717 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1229 00:58:45.960770 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1230 00:58:45.960822 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1231 00:58:45.960875 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1232 00:58:45.960928 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1233 00:58:45.960980 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1234 00:58:45.961033 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1235 00:58:45.961086 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1236 00:58:45.961138 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1237 00:58:45.961191 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1238 00:58:45.961244 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1239 00:58:45.961340 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1240 00:58:45.961394 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1241 00:58:45.961447 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1242 00:58:45.961499 ==
1243 00:58:45.961552 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 00:58:45.961605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1245 00:58:45.961658 ==
1246 00:58:45.961711 DQS Delay:
1247 00:58:45.961763 DQS0 = 0, DQS1 = 0
1248 00:58:45.961816 DQM Delay:
1249 00:58:45.961868 DQM0 = 86, DQM1 = 78
1250 00:58:45.961920 DQ Delay:
1251 00:58:45.961972 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1252 00:58:45.962025 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1253 00:58:45.962078 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1254 00:58:45.962130 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1255 00:58:45.962183
1256 00:58:45.962235
1257 00:58:45.962287 ==
1258 00:58:45.962339 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 00:58:45.962392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 00:58:45.962445 ==
1261 00:58:45.962497
1262 00:58:45.962548
1263 00:58:45.962599 TX Vref Scan disable
1264 00:58:45.962652 == TX Byte 0 ==
1265 00:58:45.962704 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1266 00:58:45.962758 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1267 00:58:45.962811 == TX Byte 1 ==
1268 00:58:45.962863 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1269 00:58:45.962916 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1270 00:58:45.962969 ==
1271 00:58:45.963021 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 00:58:45.963074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 00:58:45.963127 ==
1274 00:58:45.963180 TX Vref=22, minBit 5, minWin=26, winSum=439
1275 00:58:45.963232 TX Vref=24, minBit 1, minWin=27, winSum=445
1276 00:58:45.963286 TX Vref=26, minBit 1, minWin=27, winSum=449
1277 00:58:45.963338 TX Vref=28, minBit 1, minWin=27, winSum=450
1278 00:58:45.963391 TX Vref=30, minBit 1, minWin=27, winSum=452
1279 00:58:45.963444 TX Vref=32, minBit 2, minWin=27, winSum=451
1280 00:58:45.963498 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
1281 00:58:45.963551
1282 00:58:45.963603 Final TX Range 1 Vref 30
1283 00:58:45.963655
1284 00:58:45.963707 ==
1285 00:58:45.963759 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 00:58:45.963812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 00:58:45.963866 ==
1288 00:58:45.963918
1289 00:58:45.963970
1290 00:58:45.964022 TX Vref Scan disable
1291 00:58:45.964075 == TX Byte 0 ==
1292 00:58:45.964127 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1293 00:58:45.964180 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1294 00:58:45.964233 == TX Byte 1 ==
1295 00:58:45.964302 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1296 00:58:45.964358 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1297 00:58:45.964410
1298 00:58:45.964462 [DATLAT]
1299 00:58:45.964514 Freq=800, CH0 RK1
1300 00:58:45.964566
1301 00:58:45.964617 DATLAT Default: 0xa
1302 00:58:45.964669 0, 0xFFFF, sum = 0
1303 00:58:45.964722 1, 0xFFFF, sum = 0
1304 00:58:45.964776 2, 0xFFFF, sum = 0
1305 00:58:45.964828 3, 0xFFFF, sum = 0
1306 00:58:45.964882 4, 0xFFFF, sum = 0
1307 00:58:45.964935 5, 0xFFFF, sum = 0
1308 00:58:45.964987 6, 0xFFFF, sum = 0
1309 00:58:45.965040 7, 0xFFFF, sum = 0
1310 00:58:45.965093 8, 0xFFFF, sum = 0
1311 00:58:45.965145 9, 0x0, sum = 1
1312 00:58:45.965198 10, 0x0, sum = 2
1313 00:58:45.965250 11, 0x0, sum = 3
1314 00:58:45.965350 12, 0x0, sum = 4
1315 00:58:45.965403 best_step = 10
1316 00:58:45.965455
1317 00:58:45.965507 ==
1318 00:58:45.965559 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 00:58:45.965611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 00:58:45.965664 ==
1321 00:58:45.965716 RX Vref Scan: 0
1322 00:58:45.965768
1323 00:58:45.965820 RX Vref 0 -> 0, step: 1
1324 00:58:45.965872
1325 00:58:45.965924 RX Delay -95 -> 252, step: 8
1326 00:58:45.965976 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1327 00:58:45.966221 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1328 00:58:45.966279 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1329 00:58:45.966334 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1330 00:58:45.966387 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1331 00:58:45.966439 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1332 00:58:45.966491 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1333 00:58:45.966544 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1334 00:58:45.966596 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1335 00:58:45.966649 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1336 00:58:45.966702 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1337 00:58:45.966755 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1338 00:58:45.966807 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1339 00:58:45.966859 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1340 00:58:45.966911 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1341 00:58:45.966963 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1342 00:58:45.967015 ==
1343 00:58:45.967067 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 00:58:45.967119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 00:58:45.967171 ==
1346 00:58:45.967224 DQS Delay:
1347 00:58:45.967275 DQS0 = 0, DQS1 = 0
1348 00:58:45.967328 DQM Delay:
1349 00:58:45.967380 DQM0 = 86, DQM1 = 76
1350 00:58:45.967432 DQ Delay:
1351 00:58:45.967484 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1352 00:58:45.967536 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1353 00:58:45.967588 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1354 00:58:45.967640 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1355 00:58:45.967701
1356 00:58:45.967755
1357 00:58:45.967808 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1358 00:58:45.967861 CH0 RK1: MR19=606, MR18=2B28
1359 00:58:45.967915 CH0_RK1: MR19=0x606, MR18=0x2B28, DQSOSC=398, MR23=63, INC=93, DEC=62
1360 00:58:45.967967 [RxdqsGatingPostProcess] freq 800
1361 00:58:45.968020 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1362 00:58:45.968073 Pre-setting of DQS Precalculation
1363 00:58:45.968125 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1364 00:58:45.968178 ==
1365 00:58:45.968230 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 00:58:45.968283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 00:58:45.968336 ==
1368 00:58:45.968388 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1369 00:58:45.968440 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1370 00:58:45.968493 [CA 0] Center 37 (6~68) winsize 63
1371 00:58:45.968545 [CA 1] Center 37 (6~68) winsize 63
1372 00:58:45.968598 [CA 2] Center 35 (5~65) winsize 61
1373 00:58:45.968650 [CA 3] Center 34 (4~65) winsize 62
1374 00:58:45.968703 [CA 4] Center 34 (4~65) winsize 62
1375 00:58:45.968756 [CA 5] Center 33 (3~64) winsize 62
1376 00:58:45.968808
1377 00:58:45.968860 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1378 00:58:45.968912
1379 00:58:45.968964 [CATrainingPosCal] consider 1 rank data
1380 00:58:45.969017 u2DelayCellTimex100 = 270/100 ps
1381 00:58:45.969069 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1382 00:58:45.969121 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1383 00:58:45.969173 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1384 00:58:45.969226 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1385 00:58:45.969315 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1386 00:58:45.969412 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1387 00:58:45.969493
1388 00:58:45.969574 CA PerBit enable=1, Macro0, CA PI delay=33
1389 00:58:45.969661
1390 00:58:45.969738 [CBTSetCACLKResult] CA Dly = 33
1391 00:58:45.969828 CS Dly: 4 (0~35)
1392 00:58:45.969884 ==
1393 00:58:45.969937 Dram Type= 6, Freq= 0, CH_1, rank 1
1394 00:58:45.969990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 00:58:45.970044 ==
1396 00:58:45.970097 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1397 00:58:45.970150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1398 00:58:45.970202 [CA 0] Center 36 (6~67) winsize 62
1399 00:58:45.970255 [CA 1] Center 37 (6~68) winsize 63
1400 00:58:45.970307 [CA 2] Center 34 (4~65) winsize 62
1401 00:58:45.970359 [CA 3] Center 34 (3~65) winsize 63
1402 00:58:45.970411 [CA 4] Center 34 (4~65) winsize 62
1403 00:58:45.970463 [CA 5] Center 34 (3~65) winsize 63
1404 00:58:45.970515
1405 00:58:45.970566 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1406 00:58:45.970618
1407 00:58:45.970670 [CATrainingPosCal] consider 2 rank data
1408 00:58:45.970722 u2DelayCellTimex100 = 270/100 ps
1409 00:58:45.970774 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1410 00:58:45.970826 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1411 00:58:45.970878 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1412 00:58:45.970930 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 00:58:45.970983 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1414 00:58:45.971035 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1415 00:58:45.971087
1416 00:58:45.971139 CA PerBit enable=1, Macro0, CA PI delay=33
1417 00:58:45.971191
1418 00:58:45.971243 [CBTSetCACLKResult] CA Dly = 33
1419 00:58:45.971295 CS Dly: 5 (0~38)
1420 00:58:45.971347
1421 00:58:45.971398 ----->DramcWriteLeveling(PI) begin...
1422 00:58:45.971452 ==
1423 00:58:45.971503 Dram Type= 6, Freq= 0, CH_1, rank 0
1424 00:58:45.971556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 00:58:45.971608 ==
1426 00:58:45.971660 Write leveling (Byte 0): 27 => 27
1427 00:58:45.971712 Write leveling (Byte 1): 28 => 28
1428 00:58:45.971764 DramcWriteLeveling(PI) end<-----
1429 00:58:45.971816
1430 00:58:45.971868 ==
1431 00:58:45.971920 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 00:58:45.971972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 00:58:45.972024 ==
1434 00:58:45.972076 [Gating] SW mode calibration
1435 00:58:45.972129 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1436 00:58:45.972182 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1437 00:58:45.972234 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1438 00:58:45.972287 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1439 00:58:45.972339 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1440 00:58:45.972390 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 00:58:45.972442 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 00:58:45.972494 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 00:58:45.972546 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 00:58:45.972792 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 00:58:45.972853 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 00:58:45.972907 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 00:58:45.972960 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 00:58:45.973012 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 00:58:45.973065 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 00:58:45.973117 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 00:58:45.973170 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 00:58:45.973222 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 00:58:45.973312 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 00:58:45.973365 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1455 00:58:45.973417 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1456 00:58:45.973469 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:58:45.973521 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:58:45.973573 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:58:45.973626 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:58:45.973677 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:58:45.973729 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:58:45.973781 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:58:45.973833 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1464 00:58:45.973885 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1465 00:58:45.973937 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 00:58:45.973989 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 00:58:45.974041 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 00:58:45.974092 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 00:58:45.974144 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 00:58:45.974197 0 10 4 | B1->B0 | 3030 2e2e | 1 1 | (1 1) (1 1)
1471 00:58:45.974249 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1472 00:58:45.974301 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:58:45.974353 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:58:45.974405 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:58:45.974457 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:58:45.974509 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:58:45.974560 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 00:58:45.974612 0 11 4 | B1->B0 | 2c2c 2e2e | 1 0 | (0 0) (0 0)
1479 00:58:45.974664 0 11 8 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
1480 00:58:45.974717 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1481 00:58:45.974769 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 00:58:45.974821 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 00:58:45.974873 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 00:58:45.974926 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 00:58:45.974978 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 00:58:45.975030 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1487 00:58:45.975082 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1488 00:58:45.975135 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 00:58:45.975187 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 00:58:45.975239 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 00:58:45.975292 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 00:58:45.975344 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 00:58:45.975396 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 00:58:45.975448 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 00:58:45.975500 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 00:58:45.975552 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 00:58:45.975604 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 00:58:45.975656 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 00:58:45.975709 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 00:58:45.975761 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 00:58:45.975813 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 00:58:45.975865 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1503 00:58:45.975916 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 00:58:45.975968 Total UI for P1: 0, mck2ui 16
1505 00:58:45.976021 best dqsien dly found for B0: ( 0, 14, 4)
1506 00:58:45.976074 Total UI for P1: 0, mck2ui 16
1507 00:58:45.976126 best dqsien dly found for B1: ( 0, 14, 4)
1508 00:58:45.976178 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1509 00:58:45.976231 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1510 00:58:45.976283
1511 00:58:45.976335 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1512 00:58:45.976387 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1513 00:58:45.976439 [Gating] SW calibration Done
1514 00:58:45.976491 ==
1515 00:58:45.976543 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 00:58:45.976596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 00:58:45.976649 ==
1518 00:58:45.976701 RX Vref Scan: 0
1519 00:58:45.976752
1520 00:58:45.976805 RX Vref 0 -> 0, step: 1
1521 00:58:45.976857
1522 00:58:45.976908 RX Delay -130 -> 252, step: 16
1523 00:58:45.976960 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1524 00:58:45.977012 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1525 00:58:45.977064 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1526 00:58:45.977116 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1527 00:58:45.977168 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1528 00:58:45.977220 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1529 00:58:45.977299 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1530 00:58:45.977366 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1531 00:58:45.977418 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1532 00:58:45.977470 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1533 00:58:45.977522 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1534 00:58:45.977765 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1535 00:58:45.977823 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1536 00:58:45.977877 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1537 00:58:45.977930 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1538 00:58:45.977983 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1539 00:58:45.978035 ==
1540 00:58:45.978087 Dram Type= 6, Freq= 0, CH_1, rank 0
1541 00:58:45.978139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1542 00:58:45.978193 ==
1543 00:58:45.978245 DQS Delay:
1544 00:58:45.978297 DQS0 = 0, DQS1 = 0
1545 00:58:45.978349 DQM Delay:
1546 00:58:45.978401 DQM0 = 85, DQM1 = 77
1547 00:58:45.978454 DQ Delay:
1548 00:58:45.978506 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1549 00:58:45.978558 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1550 00:58:45.978611 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1551 00:58:45.978663 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1552 00:58:45.978715
1553 00:58:45.978766
1554 00:58:45.978817 ==
1555 00:58:45.978869 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 00:58:45.978920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 00:58:45.978973 ==
1558 00:58:45.979024
1559 00:58:45.979076
1560 00:58:45.979127 TX Vref Scan disable
1561 00:58:45.979179 == TX Byte 0 ==
1562 00:58:45.979232 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1563 00:58:45.979284 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1564 00:58:45.979336 == TX Byte 1 ==
1565 00:58:45.979388 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1566 00:58:45.979440 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1567 00:58:45.979492 ==
1568 00:58:45.979544 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 00:58:45.979596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 00:58:45.979648 ==
1571 00:58:45.979700 TX Vref=22, minBit 4, minWin=27, winSum=447
1572 00:58:45.979753 TX Vref=24, minBit 4, minWin=27, winSum=451
1573 00:58:45.979805 TX Vref=26, minBit 2, minWin=27, winSum=455
1574 00:58:45.979858 TX Vref=28, minBit 4, minWin=27, winSum=453
1575 00:58:45.979911 TX Vref=30, minBit 4, minWin=27, winSum=455
1576 00:58:45.979963 TX Vref=32, minBit 4, minWin=27, winSum=452
1577 00:58:45.980016 [TxChooseVref] Worse bit 2, Min win 27, Win sum 455, Final Vref 26
1578 00:58:45.980068
1579 00:58:45.980120 Final TX Range 1 Vref 26
1580 00:58:45.980172
1581 00:58:45.980224 ==
1582 00:58:45.980275 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 00:58:45.980327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 00:58:45.980380 ==
1585 00:58:45.980431
1586 00:58:45.980483
1587 00:58:45.980534 TX Vref Scan disable
1588 00:58:45.980586 == TX Byte 0 ==
1589 00:58:45.980638 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1590 00:58:45.980690 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1591 00:58:45.980742 == TX Byte 1 ==
1592 00:58:45.980794 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1593 00:58:45.980846 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1594 00:58:45.980898
1595 00:58:45.980950 [DATLAT]
1596 00:58:45.981001 Freq=800, CH1 RK0
1597 00:58:45.981053
1598 00:58:45.981105 DATLAT Default: 0xa
1599 00:58:45.981156 0, 0xFFFF, sum = 0
1600 00:58:45.981210 1, 0xFFFF, sum = 0
1601 00:58:45.981268 2, 0xFFFF, sum = 0
1602 00:58:45.981358 3, 0xFFFF, sum = 0
1603 00:58:45.981411 4, 0xFFFF, sum = 0
1604 00:58:45.981464 5, 0xFFFF, sum = 0
1605 00:58:45.981517 6, 0xFFFF, sum = 0
1606 00:58:45.981570 7, 0xFFFF, sum = 0
1607 00:58:45.981622 8, 0xFFFF, sum = 0
1608 00:58:45.981675 9, 0x0, sum = 1
1609 00:58:45.981728 10, 0x0, sum = 2
1610 00:58:45.981781 11, 0x0, sum = 3
1611 00:58:45.981834 12, 0x0, sum = 4
1612 00:58:45.981887 best_step = 10
1613 00:58:45.981939
1614 00:58:45.981990 ==
1615 00:58:45.982042 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 00:58:45.982095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 00:58:45.982147 ==
1618 00:58:45.982199 RX Vref Scan: 1
1619 00:58:45.982251
1620 00:58:45.982302 Set Vref Range= 32 -> 127
1621 00:58:45.982354
1622 00:58:45.982406 RX Vref 32 -> 127, step: 1
1623 00:58:45.982458
1624 00:58:45.982509 RX Delay -95 -> 252, step: 8
1625 00:58:45.982561
1626 00:58:45.982613 Set Vref, RX VrefLevel [Byte0]: 32
1627 00:58:45.982665 [Byte1]: 32
1628 00:58:45.982717
1629 00:58:45.982768 Set Vref, RX VrefLevel [Byte0]: 33
1630 00:58:45.982820 [Byte1]: 33
1631 00:58:45.982872
1632 00:58:45.982924 Set Vref, RX VrefLevel [Byte0]: 34
1633 00:58:45.982976 [Byte1]: 34
1634 00:58:45.983028
1635 00:58:45.983079 Set Vref, RX VrefLevel [Byte0]: 35
1636 00:58:45.983132 [Byte1]: 35
1637 00:58:45.983184
1638 00:58:45.983236 Set Vref, RX VrefLevel [Byte0]: 36
1639 00:58:45.983287 [Byte1]: 36
1640 00:58:45.983339
1641 00:58:45.983391 Set Vref, RX VrefLevel [Byte0]: 37
1642 00:58:45.983443 [Byte1]: 37
1643 00:58:45.983495
1644 00:58:45.983546 Set Vref, RX VrefLevel [Byte0]: 38
1645 00:58:45.983598 [Byte1]: 38
1646 00:58:45.983651
1647 00:58:45.983703 Set Vref, RX VrefLevel [Byte0]: 39
1648 00:58:45.983755 [Byte1]: 39
1649 00:58:45.983807
1650 00:58:45.983858 Set Vref, RX VrefLevel [Byte0]: 40
1651 00:58:45.983911 [Byte1]: 40
1652 00:58:45.983962
1653 00:58:45.984014 Set Vref, RX VrefLevel [Byte0]: 41
1654 00:58:45.984066 [Byte1]: 41
1655 00:58:45.984118
1656 00:58:45.984169 Set Vref, RX VrefLevel [Byte0]: 42
1657 00:58:45.984221 [Byte1]: 42
1658 00:58:45.984273
1659 00:58:45.984325 Set Vref, RX VrefLevel [Byte0]: 43
1660 00:58:45.984378 [Byte1]: 43
1661 00:58:45.984430
1662 00:58:45.984482 Set Vref, RX VrefLevel [Byte0]: 44
1663 00:58:45.984533 [Byte1]: 44
1664 00:58:45.984585
1665 00:58:45.984637 Set Vref, RX VrefLevel [Byte0]: 45
1666 00:58:45.984689 [Byte1]: 45
1667 00:58:45.984741
1668 00:58:45.984792 Set Vref, RX VrefLevel [Byte0]: 46
1669 00:58:45.984844 [Byte1]: 46
1670 00:58:45.984896
1671 00:58:45.984947 Set Vref, RX VrefLevel [Byte0]: 47
1672 00:58:45.984999 [Byte1]: 47
1673 00:58:45.985050
1674 00:58:45.985102 Set Vref, RX VrefLevel [Byte0]: 48
1675 00:58:45.985154 [Byte1]: 48
1676 00:58:45.985206
1677 00:58:45.985261 Set Vref, RX VrefLevel [Byte0]: 49
1678 00:58:45.985354 [Byte1]: 49
1679 00:58:45.985406
1680 00:58:45.985457 Set Vref, RX VrefLevel [Byte0]: 50
1681 00:58:45.985509 [Byte1]: 50
1682 00:58:45.985561
1683 00:58:45.985613 Set Vref, RX VrefLevel [Byte0]: 51
1684 00:58:45.985665 [Byte1]: 51
1685 00:58:45.985717
1686 00:58:45.985768 Set Vref, RX VrefLevel [Byte0]: 52
1687 00:58:45.985820 [Byte1]: 52
1688 00:58:45.985873
1689 00:58:45.985924 Set Vref, RX VrefLevel [Byte0]: 53
1690 00:58:45.985976 [Byte1]: 53
1691 00:58:45.986028
1692 00:58:45.986079 Set Vref, RX VrefLevel [Byte0]: 54
1693 00:58:45.986131 [Byte1]: 54
1694 00:58:45.986183
1695 00:58:45.986234 Set Vref, RX VrefLevel [Byte0]: 55
1696 00:58:45.986287 [Byte1]: 55
1697 00:58:45.986338
1698 00:58:45.986580 Set Vref, RX VrefLevel [Byte0]: 56
1699 00:58:45.986639 [Byte1]: 56
1700 00:58:45.986693
1701 00:58:45.986745 Set Vref, RX VrefLevel [Byte0]: 57
1702 00:58:45.986798 [Byte1]: 57
1703 00:58:45.986849
1704 00:58:45.986901 Set Vref, RX VrefLevel [Byte0]: 58
1705 00:58:45.986953 [Byte1]: 58
1706 00:58:45.987005
1707 00:58:45.987056 Set Vref, RX VrefLevel [Byte0]: 59
1708 00:58:45.987108 [Byte1]: 59
1709 00:58:45.987160
1710 00:58:45.987211 Set Vref, RX VrefLevel [Byte0]: 60
1711 00:58:45.987263 [Byte1]: 60
1712 00:58:45.987314
1713 00:58:45.987365 Set Vref, RX VrefLevel [Byte0]: 61
1714 00:58:45.987417 [Byte1]: 61
1715 00:58:45.987469
1716 00:58:45.987521 Set Vref, RX VrefLevel [Byte0]: 62
1717 00:58:45.987573 [Byte1]: 62
1718 00:58:45.987624
1719 00:58:45.987675 Set Vref, RX VrefLevel [Byte0]: 63
1720 00:58:45.987727 [Byte1]: 63
1721 00:58:45.987779
1722 00:58:45.987831 Set Vref, RX VrefLevel [Byte0]: 64
1723 00:58:45.987882 [Byte1]: 64
1724 00:58:45.987934
1725 00:58:45.987985 Set Vref, RX VrefLevel [Byte0]: 65
1726 00:58:45.988037 [Byte1]: 65
1727 00:58:45.988088
1728 00:58:45.988140 Set Vref, RX VrefLevel [Byte0]: 66
1729 00:58:45.988192 [Byte1]: 66
1730 00:58:45.988245
1731 00:58:45.988296 Set Vref, RX VrefLevel [Byte0]: 67
1732 00:58:45.988348 [Byte1]: 67
1733 00:58:45.988400
1734 00:58:45.988452 Set Vref, RX VrefLevel [Byte0]: 68
1735 00:58:45.988503 [Byte1]: 68
1736 00:58:45.988555
1737 00:58:45.988606 Set Vref, RX VrefLevel [Byte0]: 69
1738 00:58:45.988658 [Byte1]: 69
1739 00:58:45.988710
1740 00:58:45.988761 Set Vref, RX VrefLevel [Byte0]: 70
1741 00:58:45.988813 [Byte1]: 70
1742 00:58:45.988864
1743 00:58:45.988916 Set Vref, RX VrefLevel [Byte0]: 71
1744 00:58:45.988967 [Byte1]: 71
1745 00:58:45.989019
1746 00:58:45.989071 Set Vref, RX VrefLevel [Byte0]: 72
1747 00:58:45.989123 [Byte1]: 72
1748 00:58:45.989175
1749 00:58:45.989226 Set Vref, RX VrefLevel [Byte0]: 73
1750 00:58:45.989312 [Byte1]: 73
1751 00:58:45.989378
1752 00:58:45.989430 Set Vref, RX VrefLevel [Byte0]: 74
1753 00:58:45.989482 [Byte1]: 74
1754 00:58:45.989534
1755 00:58:45.989585 Final RX Vref Byte 0 = 57 to rank0
1756 00:58:45.989638 Final RX Vref Byte 1 = 59 to rank0
1757 00:58:45.989689 Final RX Vref Byte 0 = 57 to rank1
1758 00:58:45.989741 Final RX Vref Byte 1 = 59 to rank1==
1759 00:58:45.989794 Dram Type= 6, Freq= 0, CH_1, rank 0
1760 00:58:45.989846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1761 00:58:45.989899 ==
1762 00:58:45.989951 DQS Delay:
1763 00:58:45.990002 DQS0 = 0, DQS1 = 0
1764 00:58:45.990054 DQM Delay:
1765 00:58:45.990106 DQM0 = 85, DQM1 = 80
1766 00:58:45.990158 DQ Delay:
1767 00:58:45.990209 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1768 00:58:45.990262 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1769 00:58:45.990313 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1770 00:58:45.990365 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1771 00:58:45.990417
1772 00:58:45.990469
1773 00:58:45.990521 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b2e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1774 00:58:45.990573 CH1 RK0: MR19=606, MR18=1B2E
1775 00:58:45.990626 CH1_RK0: MR19=0x606, MR18=0x1B2E, DQSOSC=398, MR23=63, INC=93, DEC=62
1776 00:58:45.990679
1777 00:58:45.990730 ----->DramcWriteLeveling(PI) begin...
1778 00:58:45.990784 ==
1779 00:58:45.990836 Dram Type= 6, Freq= 0, CH_1, rank 1
1780 00:58:45.990888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 00:58:45.990941 ==
1782 00:58:45.990993 Write leveling (Byte 0): 25 => 25
1783 00:58:45.991044 Write leveling (Byte 1): 31 => 31
1784 00:58:45.991096 DramcWriteLeveling(PI) end<-----
1785 00:58:45.991148
1786 00:58:45.991200 ==
1787 00:58:45.991252 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 00:58:45.991304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 00:58:45.991356 ==
1790 00:58:45.991408 [Gating] SW mode calibration
1791 00:58:45.991461 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1792 00:58:45.991513 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1793 00:58:45.991566 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1794 00:58:45.991619 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1795 00:58:45.991672 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1796 00:58:45.991724 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1797 00:58:45.991776 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 00:58:45.991828 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 00:58:45.991880 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 00:58:45.991932 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 00:58:45.991984 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 00:58:45.992036 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 00:58:45.992088 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 00:58:45.992139 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 00:58:45.992191 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 00:58:45.992243 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 00:58:45.992295 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 00:58:45.992347 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 00:58:45.992399 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1810 00:58:45.992451 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1811 00:58:45.992503 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1812 00:58:45.992555 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:58:45.992607 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 00:58:45.992659 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:58:45.992711 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:58:45.992763 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:58:45.992814 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:58:45.992866 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1819 00:58:45.992918 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1820 00:58:45.992970 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1821 00:58:45.993022 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1822 00:58:45.993270 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 00:58:45.993366 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 00:58:45.993420 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 00:58:45.993473 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1826 00:58:45.993526 0 10 4 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (1 0)
1827 00:58:45.993578 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1828 00:58:45.993630 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:58:45.993683 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:58:45.993736 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:58:45.993788 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:58:45.993840 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:58:45.993892 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1834 00:58:45.993944 0 11 4 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)
1835 00:58:45.993997 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1836 00:58:45.994048 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1837 00:58:45.994101 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1838 00:58:45.994153 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 00:58:45.994205 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 00:58:45.994256 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 00:58:45.994308 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1842 00:58:45.994362 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1843 00:58:45.994414 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1844 00:58:45.994466 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1845 00:58:45.994518 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 00:58:45.994571 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 00:58:45.994623 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 00:58:45.994675 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 00:58:45.994727 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 00:58:45.994779 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 00:58:45.994831 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 00:58:45.994883 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 00:58:45.994934 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 00:58:45.994986 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 00:58:45.995037 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 00:58:45.995089 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 00:58:45.995140 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 00:58:45.995192 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1859 00:58:45.995244 Total UI for P1: 0, mck2ui 16
1860 00:58:45.995297 best dqsien dly found for B0: ( 0, 14, 2)
1861 00:58:45.995349 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 00:58:45.995401 Total UI for P1: 0, mck2ui 16
1863 00:58:45.995453 best dqsien dly found for B1: ( 0, 14, 6)
1864 00:58:45.995505 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1865 00:58:45.995557 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1866 00:58:45.995609
1867 00:58:45.995661 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1868 00:58:45.995712 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1869 00:58:45.995765 [Gating] SW calibration Done
1870 00:58:45.995817 ==
1871 00:58:45.995869 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 00:58:45.995921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 00:58:45.995973 ==
1874 00:58:45.996025 RX Vref Scan: 0
1875 00:58:45.996077
1876 00:58:45.996128 RX Vref 0 -> 0, step: 1
1877 00:58:45.996180
1878 00:58:45.996231 RX Delay -130 -> 252, step: 16
1879 00:58:45.996284 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1880 00:58:45.996336 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1881 00:58:45.996388 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1882 00:58:45.996440 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1883 00:58:45.996492 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1884 00:58:45.996544 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1885 00:58:45.996595 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1886 00:58:45.996648 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1887 00:58:45.996699 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1888 00:58:45.996751 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1889 00:58:45.996803 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1890 00:58:45.996855 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1891 00:58:45.996906 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1892 00:58:45.996958 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1893 00:58:45.997010 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1894 00:58:45.997062 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1895 00:58:45.997113 ==
1896 00:58:45.997166 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 00:58:45.997218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 00:58:45.997274 ==
1899 00:58:45.997360 DQS Delay:
1900 00:58:45.997411 DQS0 = 0, DQS1 = 0
1901 00:58:45.997464 DQM Delay:
1902 00:58:45.997515 DQM0 = 83, DQM1 = 81
1903 00:58:45.997567 DQ Delay:
1904 00:58:45.997618 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1905 00:58:45.997670 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1906 00:58:45.997723 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1907 00:58:45.997776 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1908 00:58:45.997827
1909 00:58:45.997879
1910 00:58:45.997931 ==
1911 00:58:45.997983 Dram Type= 6, Freq= 0, CH_1, rank 1
1912 00:58:45.998034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1913 00:58:45.998086 ==
1914 00:58:45.998139
1915 00:58:45.998190
1916 00:58:45.998241 TX Vref Scan disable
1917 00:58:45.998293 == TX Byte 0 ==
1918 00:58:45.998345 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1919 00:58:46.144372 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1920 00:58:46.144911 == TX Byte 1 ==
1921 00:58:46.145311 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1922 00:58:46.145703 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1923 00:58:46.146041 ==
1924 00:58:46.146365 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 00:58:46.146685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 00:58:46.147004 ==
1927 00:58:46.147311 TX Vref=22, minBit 1, minWin=27, winSum=445
1928 00:58:46.147718 TX Vref=24, minBit 4, minWin=27, winSum=451
1929 00:58:46.148043 TX Vref=26, minBit 5, minWin=27, winSum=450
1930 00:58:46.148768 TX Vref=28, minBit 1, minWin=27, winSum=455
1931 00:58:46.149113 TX Vref=30, minBit 5, minWin=27, winSum=451
1932 00:58:46.149482 TX Vref=32, minBit 0, minWin=27, winSum=449
1933 00:58:46.149989 [TxChooseVref] Worse bit 1, Min win 27, Win sum 455, Final Vref 28
1934 00:58:46.150373
1935 00:58:46.150686 Final TX Range 1 Vref 28
1936 00:58:46.150998
1937 00:58:46.151302 ==
1938 00:58:46.151603 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 00:58:46.151909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 00:58:46.152219 ==
1941 00:58:46.152519
1942 00:58:46.152818
1943 00:58:46.153117 TX Vref Scan disable
1944 00:58:46.153461 == TX Byte 0 ==
1945 00:58:46.153765 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1946 00:58:46.153859 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1947 00:58:46.153911 == TX Byte 1 ==
1948 00:58:46.153963 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1949 00:58:46.154016 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1950 00:58:46.154068
1951 00:58:46.154121 [DATLAT]
1952 00:58:46.154173 Freq=800, CH1 RK1
1953 00:58:46.154226
1954 00:58:46.154278 DATLAT Default: 0xa
1955 00:58:46.154330 0, 0xFFFF, sum = 0
1956 00:58:46.154384 1, 0xFFFF, sum = 0
1957 00:58:46.154438 2, 0xFFFF, sum = 0
1958 00:58:46.154491 3, 0xFFFF, sum = 0
1959 00:58:46.154544 4, 0xFFFF, sum = 0
1960 00:58:46.154598 5, 0xFFFF, sum = 0
1961 00:58:46.154652 6, 0xFFFF, sum = 0
1962 00:58:46.154705 7, 0xFFFF, sum = 0
1963 00:58:46.154758 8, 0xFFFF, sum = 0
1964 00:58:46.154811 9, 0x0, sum = 1
1965 00:58:46.154864 10, 0x0, sum = 2
1966 00:58:46.154917 11, 0x0, sum = 3
1967 00:58:46.154970 12, 0x0, sum = 4
1968 00:58:46.155023 best_step = 10
1969 00:58:46.155075
1970 00:58:46.155127 ==
1971 00:58:46.155179 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 00:58:46.155231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 00:58:46.155284 ==
1974 00:58:46.155336 RX Vref Scan: 0
1975 00:58:46.155388
1976 00:58:46.155440 RX Vref 0 -> 0, step: 1
1977 00:58:46.155492
1978 00:58:46.155543 RX Delay -95 -> 252, step: 8
1979 00:58:46.155595 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1980 00:58:46.155648 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1981 00:58:46.155700 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1982 00:58:46.155752 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1983 00:58:46.155804 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1984 00:58:46.155856 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1985 00:58:46.155907 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1986 00:58:46.155960 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1987 00:58:46.156011 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1988 00:58:46.156064 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1989 00:58:46.156116 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
1990 00:58:46.156168 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1991 00:58:46.156220 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1992 00:58:46.156273 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1993 00:58:46.156325 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1994 00:58:46.156377 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1995 00:58:46.156429 ==
1996 00:58:46.156481 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 00:58:46.156533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 00:58:46.156585 ==
1999 00:58:46.156636 DQS Delay:
2000 00:58:46.156688 DQS0 = 0, DQS1 = 0
2001 00:58:46.156741 DQM Delay:
2002 00:58:46.156792 DQM0 = 85, DQM1 = 82
2003 00:58:46.156844 DQ Delay:
2004 00:58:46.156895 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2005 00:58:46.156947 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2006 00:58:46.156999 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2007 00:58:46.157051 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2008 00:58:46.157103
2009 00:58:46.157155
2010 00:58:46.157207 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2011 00:58:46.157264 CH1 RK1: MR19=606, MR18=1E39
2012 00:58:46.157351 CH1_RK1: MR19=0x606, MR18=0x1E39, DQSOSC=395, MR23=63, INC=94, DEC=63
2013 00:58:46.157404 [RxdqsGatingPostProcess] freq 800
2014 00:58:46.157457 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2015 00:58:46.157510 Pre-setting of DQS Precalculation
2016 00:58:46.157562 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2017 00:58:46.157615 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2018 00:58:46.157668 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2019 00:58:46.157720
2020 00:58:46.157772
2021 00:58:46.157824 [Calibration Summary] 1600 Mbps
2022 00:58:46.157876 CH 0, Rank 0
2023 00:58:46.157928 SW Impedance : PASS
2024 00:58:46.157980 DUTY Scan : NO K
2025 00:58:46.158032 ZQ Calibration : PASS
2026 00:58:46.158085 Jitter Meter : NO K
2027 00:58:46.158137 CBT Training : PASS
2028 00:58:46.158189 Write leveling : PASS
2029 00:58:46.158241 RX DQS gating : PASS
2030 00:58:46.158293 RX DQ/DQS(RDDQC) : PASS
2031 00:58:46.158346 TX DQ/DQS : PASS
2032 00:58:46.158398 RX DATLAT : PASS
2033 00:58:46.158450 RX DQ/DQS(Engine): PASS
2034 00:58:46.158502 TX OE : NO K
2035 00:58:46.158555 All Pass.
2036 00:58:46.158608
2037 00:58:46.158659 CH 0, Rank 1
2038 00:58:46.158711 SW Impedance : PASS
2039 00:58:46.158763 DUTY Scan : NO K
2040 00:58:46.158815 ZQ Calibration : PASS
2041 00:58:46.158867 Jitter Meter : NO K
2042 00:58:46.158919 CBT Training : PASS
2043 00:58:46.158971 Write leveling : PASS
2044 00:58:46.159023 RX DQS gating : PASS
2045 00:58:46.159075 RX DQ/DQS(RDDQC) : PASS
2046 00:58:46.159127 TX DQ/DQS : PASS
2047 00:58:46.159179 RX DATLAT : PASS
2048 00:58:46.159232 RX DQ/DQS(Engine): PASS
2049 00:58:46.159284 TX OE : NO K
2050 00:58:46.159337 All Pass.
2051 00:58:46.159389
2052 00:58:46.159440 CH 1, Rank 0
2053 00:58:46.159492 SW Impedance : PASS
2054 00:58:46.159545 DUTY Scan : NO K
2055 00:58:46.159597 ZQ Calibration : PASS
2056 00:58:46.159649 Jitter Meter : NO K
2057 00:58:46.159705 CBT Training : PASS
2058 00:58:46.159782 Write leveling : PASS
2059 00:58:46.159855 RX DQS gating : PASS
2060 00:58:46.159927 RX DQ/DQS(RDDQC) : PASS
2061 00:58:46.159998 TX DQ/DQS : PASS
2062 00:58:46.160070 RX DATLAT : PASS
2063 00:58:46.160141 RX DQ/DQS(Engine): PASS
2064 00:58:46.160232 TX OE : NO K
2065 00:58:46.160323 All Pass.
2066 00:58:46.160414
2067 00:58:46.160505 CH 1, Rank 1
2068 00:58:46.160595 SW Impedance : PASS
2069 00:58:46.160685 DUTY Scan : NO K
2070 00:58:46.160775 ZQ Calibration : PASS
2071 00:58:46.160865 Jitter Meter : NO K
2072 00:58:46.160955 CBT Training : PASS
2073 00:58:46.161056 Write leveling : PASS
2074 00:58:46.161147 RX DQS gating : PASS
2075 00:58:46.161237 RX DQ/DQS(RDDQC) : PASS
2076 00:58:46.161365 TX DQ/DQS : PASS
2077 00:58:46.161457 RX DATLAT : PASS
2078 00:58:46.161547 RX DQ/DQS(Engine): PASS
2079 00:58:46.161637 TX OE : NO K
2080 00:58:46.161728 All Pass.
2081 00:58:46.161819
2082 00:58:46.161909 DramC Write-DBI off
2083 00:58:46.161998 PER_BANK_REFRESH: Hybrid Mode
2084 00:58:46.162288 TX_TRACKING: ON
2085 00:58:46.162412 [GetDramInforAfterCalByMRR] Vendor 6.
2086 00:58:46.162507 [GetDramInforAfterCalByMRR] Revision 606.
2087 00:58:46.162601 [GetDramInforAfterCalByMRR] Revision 2 0.
2088 00:58:46.162694 MR0 0x3b3b
2089 00:58:46.162785 MR8 0x5151
2090 00:58:46.162877 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2091 00:58:46.162969
2092 00:58:46.163071 MR0 0x3b3b
2093 00:58:46.163163 MR8 0x5151
2094 00:58:46.163255 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2095 00:58:46.163347
2096 00:58:46.163439 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2097 00:58:46.163532 [FAST_K] Save calibration result to emmc
2098 00:58:46.163624 [FAST_K] Save calibration result to emmc
2099 00:58:46.163715 dram_init: config_dvfs: 1
2100 00:58:46.163806 dramc_set_vcore_voltage set vcore to 662500
2101 00:58:46.163896 Read voltage for 1200, 2
2102 00:58:46.163987 Vio18 = 0
2103 00:58:46.164077 Vcore = 662500
2104 00:58:46.164167 Vdram = 0
2105 00:58:46.164257 Vddq = 0
2106 00:58:46.164347 Vmddr = 0
2107 00:58:46.164437 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2108 00:58:46.164527 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2109 00:58:46.164618 MEM_TYPE=3, freq_sel=15
2110 00:58:46.164709 sv_algorithm_assistance_LP4_1600
2111 00:58:46.164800 ============ PULL DRAM RESETB DOWN ============
2112 00:58:46.164891 ========== PULL DRAM RESETB DOWN end =========
2113 00:58:46.164983 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2114 00:58:46.165080 ===================================
2115 00:58:46.165177 LPDDR4 DRAM CONFIGURATION
2116 00:58:46.165296 ===================================
2117 00:58:46.165399 EX_ROW_EN[0] = 0x0
2118 00:58:46.165482 EX_ROW_EN[1] = 0x0
2119 00:58:46.165565 LP4Y_EN = 0x0
2120 00:58:46.165647 WORK_FSP = 0x0
2121 00:58:46.165729 WL = 0x4
2122 00:58:46.165810 RL = 0x4
2123 00:58:46.165892 BL = 0x2
2124 00:58:46.165973 RPST = 0x0
2125 00:58:46.166054 RD_PRE = 0x0
2126 00:58:46.166136 WR_PRE = 0x1
2127 00:58:46.166217 WR_PST = 0x0
2128 00:58:46.166298 DBI_WR = 0x0
2129 00:58:46.166379 DBI_RD = 0x0
2130 00:58:46.166461 OTF = 0x1
2131 00:58:46.166543 ===================================
2132 00:58:46.166625 ===================================
2133 00:58:46.166707 ANA top config
2134 00:58:46.166789 ===================================
2135 00:58:46.166871 DLL_ASYNC_EN = 0
2136 00:58:46.166953 ALL_SLAVE_EN = 0
2137 00:58:46.167035 NEW_RANK_MODE = 1
2138 00:58:46.167118 DLL_IDLE_MODE = 1
2139 00:58:46.167200 LP45_APHY_COMB_EN = 1
2140 00:58:46.167281 TX_ODT_DIS = 1
2141 00:58:46.167364 NEW_8X_MODE = 1
2142 00:58:46.167446 ===================================
2143 00:58:46.167529 ===================================
2144 00:58:46.167611 data_rate = 2400
2145 00:58:46.167693 CKR = 1
2146 00:58:46.167774 DQ_P2S_RATIO = 8
2147 00:58:46.167856 ===================================
2148 00:58:46.167938 CA_P2S_RATIO = 8
2149 00:58:46.168020 DQ_CA_OPEN = 0
2150 00:58:46.168101 DQ_SEMI_OPEN = 0
2151 00:58:46.168183 CA_SEMI_OPEN = 0
2152 00:58:46.168265 CA_FULL_RATE = 0
2153 00:58:46.168346 DQ_CKDIV4_EN = 0
2154 00:58:46.168428 CA_CKDIV4_EN = 0
2155 00:58:46.168509 CA_PREDIV_EN = 0
2156 00:58:46.168591 PH8_DLY = 17
2157 00:58:46.168673 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2158 00:58:46.168754 DQ_AAMCK_DIV = 4
2159 00:58:46.168835 CA_AAMCK_DIV = 4
2160 00:58:46.168917 CA_ADMCK_DIV = 4
2161 00:58:46.168998 DQ_TRACK_CA_EN = 0
2162 00:58:46.169080 CA_PICK = 1200
2163 00:58:46.169161 CA_MCKIO = 1200
2164 00:58:46.169243 MCKIO_SEMI = 0
2165 00:58:46.169366 PLL_FREQ = 2366
2166 00:58:46.169448 DQ_UI_PI_RATIO = 32
2167 00:58:46.169530 CA_UI_PI_RATIO = 0
2168 00:58:46.169612 ===================================
2169 00:58:46.169694 ===================================
2170 00:58:46.169776 memory_type:LPDDR4
2171 00:58:46.169858 GP_NUM : 10
2172 00:58:46.169939 SRAM_EN : 1
2173 00:58:46.170019 MD32_EN : 0
2174 00:58:46.170075 ===================================
2175 00:58:46.170129 [ANA_INIT] >>>>>>>>>>>>>>
2176 00:58:46.170182 <<<<<< [CONFIGURE PHASE]: ANA_TX
2177 00:58:46.170237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2178 00:58:46.170290 ===================================
2179 00:58:46.170343 data_rate = 2400,PCW = 0X5b00
2180 00:58:46.170396 ===================================
2181 00:58:46.170453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2182 00:58:46.170541 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2183 00:58:46.170632 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2184 00:58:46.170723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2185 00:58:46.170814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2186 00:58:46.170904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2187 00:58:46.170995 [ANA_INIT] flow start
2188 00:58:46.171086 [ANA_INIT] PLL >>>>>>>>
2189 00:58:46.171177 [ANA_INIT] PLL <<<<<<<<
2190 00:58:46.171267 [ANA_INIT] MIDPI >>>>>>>>
2191 00:58:46.171357 [ANA_INIT] MIDPI <<<<<<<<
2192 00:58:46.171447 [ANA_INIT] DLL >>>>>>>>
2193 00:58:46.171537 [ANA_INIT] DLL <<<<<<<<
2194 00:58:46.171626 [ANA_INIT] flow end
2195 00:58:46.171716 ============ LP4 DIFF to SE enter ============
2196 00:58:46.171807 ============ LP4 DIFF to SE exit ============
2197 00:58:46.171898 [ANA_INIT] <<<<<<<<<<<<<
2198 00:58:46.171988 [Flow] Enable top DCM control >>>>>
2199 00:58:46.172078 [Flow] Enable top DCM control <<<<<
2200 00:58:46.172169 Enable DLL master slave shuffle
2201 00:58:46.172259 ==============================================================
2202 00:58:46.172350 Gating Mode config
2203 00:58:46.172440 ==============================================================
2204 00:58:46.172530 Config description:
2205 00:58:46.172620 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2206 00:58:46.172712 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2207 00:58:46.173001 SELPH_MODE 0: By rank 1: By Phase
2208 00:58:46.173094 ==============================================================
2209 00:58:46.173216 GAT_TRACK_EN = 1
2210 00:58:46.173338 RX_GATING_MODE = 2
2211 00:58:46.173432 RX_GATING_TRACK_MODE = 2
2212 00:58:46.173525 SELPH_MODE = 1
2213 00:58:46.173617 PICG_EARLY_EN = 1
2214 00:58:46.173708 VALID_LAT_VALUE = 1
2215 00:58:46.173800 ==============================================================
2216 00:58:46.173892 Enter into Gating configuration >>>>
2217 00:58:46.173983 Exit from Gating configuration <<<<
2218 00:58:46.174074 Enter into DVFS_PRE_config >>>>>
2219 00:58:46.174166 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2220 00:58:46.174258 Exit from DVFS_PRE_config <<<<<
2221 00:58:46.174349 Enter into PICG configuration >>>>
2222 00:58:46.174440 Exit from PICG configuration <<<<
2223 00:58:46.174530 [RX_INPUT] configuration >>>>>
2224 00:58:46.174620 [RX_INPUT] configuration <<<<<
2225 00:58:46.174710 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2226 00:58:46.174801 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2227 00:58:46.174892 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2228 00:58:46.174983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2229 00:58:46.175074 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2230 00:58:46.175165 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2231 00:58:46.175259 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2232 00:58:46.175350 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2233 00:58:46.175441 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2234 00:58:46.175532 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2235 00:58:46.175622 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2236 00:58:46.175713 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2237 00:58:46.175815 ===================================
2238 00:58:46.175905 LPDDR4 DRAM CONFIGURATION
2239 00:58:46.175994 ===================================
2240 00:58:46.176083 EX_ROW_EN[0] = 0x0
2241 00:58:46.176171 EX_ROW_EN[1] = 0x0
2242 00:58:46.176259 LP4Y_EN = 0x0
2243 00:58:46.176347 WORK_FSP = 0x0
2244 00:58:46.176435 WL = 0x4
2245 00:58:46.176524 RL = 0x4
2246 00:58:46.176612 BL = 0x2
2247 00:58:46.176700 RPST = 0x0
2248 00:58:46.176787 RD_PRE = 0x0
2249 00:58:46.176875 WR_PRE = 0x1
2250 00:58:46.176963 WR_PST = 0x0
2251 00:58:46.177108 DBI_WR = 0x0
2252 00:58:46.177213 DBI_RD = 0x0
2253 00:58:46.177349 OTF = 0x1
2254 00:58:46.177440 ===================================
2255 00:58:46.177530 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2256 00:58:46.177619 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2257 00:58:46.177708 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 00:58:46.177797 ===================================
2259 00:58:46.177887 LPDDR4 DRAM CONFIGURATION
2260 00:58:46.177976 ===================================
2261 00:58:46.178065 EX_ROW_EN[0] = 0x10
2262 00:58:46.178153 EX_ROW_EN[1] = 0x0
2263 00:58:46.178241 LP4Y_EN = 0x0
2264 00:58:46.178329 WORK_FSP = 0x0
2265 00:58:46.178418 WL = 0x4
2266 00:58:46.178506 RL = 0x4
2267 00:58:46.178594 BL = 0x2
2268 00:58:46.178682 RPST = 0x0
2269 00:58:46.178770 RD_PRE = 0x0
2270 00:58:46.178858 WR_PRE = 0x1
2271 00:58:46.178945 WR_PST = 0x0
2272 00:58:46.179033 DBI_WR = 0x0
2273 00:58:46.179121 DBI_RD = 0x0
2274 00:58:46.179251 OTF = 0x1
2275 00:58:46.179339 ===================================
2276 00:58:46.179428 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2277 00:58:46.179518 ==
2278 00:58:46.179606 Dram Type= 6, Freq= 0, CH_0, rank 0
2279 00:58:46.179695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2280 00:58:46.179798 ==
2281 00:58:46.179888 [Duty_Offset_Calibration]
2282 00:58:46.179979 B0:2 B1:0 CA:4
2283 00:58:46.180069
2284 00:58:46.180159 [DutyScan_Calibration_Flow] k_type=0
2285 00:58:46.180249
2286 00:58:46.180339 ==CLK 0==
2287 00:58:46.180430 Final CLK duty delay cell = -4
2288 00:58:46.180521 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2289 00:58:46.180612 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2290 00:58:46.180702 [-4] AVG Duty = 4937%(X100)
2291 00:58:46.180792
2292 00:58:46.180882 CH0 CLK Duty spec in!! Max-Min= 187%
2293 00:58:46.180973 [DutyScan_Calibration_Flow] ====Done====
2294 00:58:46.181065
2295 00:58:46.181156 [DutyScan_Calibration_Flow] k_type=1
2296 00:58:46.181247
2297 00:58:46.181411 ==DQS 0 ==
2298 00:58:46.181500 Final DQS duty delay cell = 0
2299 00:58:46.181586 [0] MAX Duty = 5156%(X100), DQS PI = 18
2300 00:58:46.181671 [0] MIN Duty = 5093%(X100), DQS PI = 0
2301 00:58:46.181753 [0] AVG Duty = 5124%(X100)
2302 00:58:46.181835
2303 00:58:46.181914 ==DQS 1 ==
2304 00:58:46.181995 Final DQS duty delay cell = 0
2305 00:58:46.182075 [0] MAX Duty = 5125%(X100), DQS PI = 52
2306 00:58:46.182155 [0] MIN Duty = 5000%(X100), DQS PI = 0
2307 00:58:46.182235 [0] AVG Duty = 5062%(X100)
2308 00:58:46.182315
2309 00:58:46.182393 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2310 00:58:46.182473
2311 00:58:46.182551 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2312 00:58:46.182631 [DutyScan_Calibration_Flow] ====Done====
2313 00:58:46.182710
2314 00:58:46.182789 [DutyScan_Calibration_Flow] k_type=3
2315 00:58:46.182867
2316 00:58:46.182946 ==DQM 0 ==
2317 00:58:46.183025 Final DQM duty delay cell = 0
2318 00:58:46.183104 [0] MAX Duty = 5125%(X100), DQS PI = 20
2319 00:58:46.183207 [0] MIN Duty = 4844%(X100), DQS PI = 50
2320 00:58:46.183327 [0] AVG Duty = 4984%(X100)
2321 00:58:46.183406
2322 00:58:46.183484 ==DQM 1 ==
2323 00:58:46.183562 Final DQM duty delay cell = 0
2324 00:58:46.183641 [0] MAX Duty = 4969%(X100), DQS PI = 2
2325 00:58:46.183719 [0] MIN Duty = 4875%(X100), DQS PI = 20
2326 00:58:46.183798 [0] AVG Duty = 4922%(X100)
2327 00:58:46.183876
2328 00:58:46.183954 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2329 00:58:46.184032
2330 00:58:46.184110 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2331 00:58:46.184189 [DutyScan_Calibration_Flow] ====Done====
2332 00:58:46.184267
2333 00:58:46.184345 [DutyScan_Calibration_Flow] k_type=2
2334 00:58:46.184423
2335 00:58:46.184500 ==DQ 0 ==
2336 00:58:46.184578 Final DQ duty delay cell = 0
2337 00:58:46.184659 [0] MAX Duty = 5125%(X100), DQS PI = 18
2338 00:58:46.184738 [0] MIN Duty = 4969%(X100), DQS PI = 52
2339 00:58:46.185024 [0] AVG Duty = 5047%(X100)
2340 00:58:46.185117
2341 00:58:46.185226 ==DQ 1 ==
2342 00:58:46.185332 Final DQ duty delay cell = 0
2343 00:58:46.185415 [0] MAX Duty = 5125%(X100), DQS PI = 4
2344 00:58:46.185496 [0] MIN Duty = 4938%(X100), DQS PI = 16
2345 00:58:46.185577 [0] AVG Duty = 5031%(X100)
2346 00:58:46.185657
2347 00:58:46.185737 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2348 00:58:46.185817
2349 00:58:46.185896 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2350 00:58:46.185975 [DutyScan_Calibration_Flow] ====Done====
2351 00:58:46.186054 ==
2352 00:58:46.186134 Dram Type= 6, Freq= 0, CH_1, rank 0
2353 00:58:46.186213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2354 00:58:46.186293 ==
2355 00:58:46.186373 [Duty_Offset_Calibration]
2356 00:58:46.186453 B0:0 B1:-1 CA:3
2357 00:58:46.186531
2358 00:58:46.186610 [DutyScan_Calibration_Flow] k_type=0
2359 00:58:46.186688
2360 00:58:46.186767 ==CLK 0==
2361 00:58:46.186846 Final CLK duty delay cell = -4
2362 00:58:46.186926 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2363 00:58:46.187005 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2364 00:58:46.187087 [-4] AVG Duty = 4938%(X100)
2365 00:58:46.187169
2366 00:58:46.187248 CH1 CLK Duty spec in!! Max-Min= 124%
2367 00:58:46.187326 [DutyScan_Calibration_Flow] ====Done====
2368 00:58:46.187403
2369 00:58:46.187479 [DutyScan_Calibration_Flow] k_type=1
2370 00:58:46.187558
2371 00:58:46.187640 ==DQS 0 ==
2372 00:58:46.187722 Final DQS duty delay cell = 0
2373 00:58:46.187807 [0] MAX Duty = 5187%(X100), DQS PI = 18
2374 00:58:46.187890 [0] MIN Duty = 4907%(X100), DQS PI = 38
2375 00:58:46.187972 [0] AVG Duty = 5047%(X100)
2376 00:58:46.188055
2377 00:58:46.188137 ==DQS 1 ==
2378 00:58:46.188219 Final DQS duty delay cell = 0
2379 00:58:46.188300 [0] MAX Duty = 5156%(X100), DQS PI = 8
2380 00:58:46.188382 [0] MIN Duty = 5000%(X100), DQS PI = 26
2381 00:58:46.188465 [0] AVG Duty = 5078%(X100)
2382 00:58:46.188556
2383 00:58:46.188650 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2384 00:58:46.188744
2385 00:58:46.188840 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2386 00:58:46.188934 [DutyScan_Calibration_Flow] ====Done====
2387 00:58:46.189033
2388 00:58:46.189139 [DutyScan_Calibration_Flow] k_type=3
2389 00:58:46.189233
2390 00:58:46.189358 ==DQM 0 ==
2391 00:58:46.189444 Final DQM duty delay cell = 0
2392 00:58:46.189529 [0] MAX Duty = 5031%(X100), DQS PI = 30
2393 00:58:46.189613 [0] MIN Duty = 4782%(X100), DQS PI = 38
2394 00:58:46.189696 [0] AVG Duty = 4906%(X100)
2395 00:58:46.189778
2396 00:58:46.189865 ==DQM 1 ==
2397 00:58:46.189950 Final DQM duty delay cell = 0
2398 00:58:46.190033 [0] MAX Duty = 5000%(X100), DQS PI = 34
2399 00:58:46.190115 [0] MIN Duty = 4813%(X100), DQS PI = 62
2400 00:58:46.190197 [0] AVG Duty = 4906%(X100)
2401 00:58:46.190277
2402 00:58:46.190389 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2403 00:58:46.190471
2404 00:58:46.190552 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2405 00:58:46.190634 [DutyScan_Calibration_Flow] ====Done====
2406 00:58:46.190715
2407 00:58:46.190797 [DutyScan_Calibration_Flow] k_type=2
2408 00:58:46.190877
2409 00:58:46.190958 ==DQ 0 ==
2410 00:58:46.191040 Final DQ duty delay cell = -4
2411 00:58:46.191122 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2412 00:58:46.191208 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2413 00:58:46.191289 [-4] AVG Duty = 4937%(X100)
2414 00:58:46.191370
2415 00:58:46.191450 ==DQ 1 ==
2416 00:58:46.191531 Final DQ duty delay cell = 4
2417 00:58:46.191613 [4] MAX Duty = 5156%(X100), DQS PI = 26
2418 00:58:46.191695 [4] MIN Duty = 5031%(X100), DQS PI = 62
2419 00:58:46.191776 [4] AVG Duty = 5093%(X100)
2420 00:58:46.191856
2421 00:58:46.191937 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2422 00:58:46.192018
2423 00:58:46.192099 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2424 00:58:46.192180 [DutyScan_Calibration_Flow] ====Done====
2425 00:58:46.192261 nWR fixed to 30
2426 00:58:46.192344 [ModeRegInit_LP4] CH0 RK0
2427 00:58:46.192425 [ModeRegInit_LP4] CH0 RK1
2428 00:58:46.192506 [ModeRegInit_LP4] CH1 RK0
2429 00:58:46.192586 [ModeRegInit_LP4] CH1 RK1
2430 00:58:46.192667 match AC timing 7
2431 00:58:46.192749 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2432 00:58:46.192830 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2433 00:58:46.192912 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2434 00:58:46.192994 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2435 00:58:46.193076 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2436 00:58:46.193157 ==
2437 00:58:46.193267 Dram Type= 6, Freq= 0, CH_0, rank 0
2438 00:58:46.193364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2439 00:58:46.193446 ==
2440 00:58:46.193528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2441 00:58:46.193611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2442 00:58:46.193693 [CA 0] Center 39 (9~70) winsize 62
2443 00:58:46.193774 [CA 1] Center 39 (9~70) winsize 62
2444 00:58:46.193856 [CA 2] Center 35 (5~66) winsize 62
2445 00:58:46.193937 [CA 3] Center 35 (5~66) winsize 62
2446 00:58:46.194018 [CA 4] Center 33 (3~64) winsize 62
2447 00:58:46.194100 [CA 5] Center 33 (3~64) winsize 62
2448 00:58:46.194180
2449 00:58:46.194262 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2450 00:58:46.194342
2451 00:58:46.194424 [CATrainingPosCal] consider 1 rank data
2452 00:58:46.194505 u2DelayCellTimex100 = 270/100 ps
2453 00:58:46.194587 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2454 00:58:46.194668 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2455 00:58:46.194750 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2456 00:58:46.194831 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2457 00:58:46.194913 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2458 00:58:46.194994 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2459 00:58:46.195075
2460 00:58:46.195156 CA PerBit enable=1, Macro0, CA PI delay=33
2461 00:58:46.195237
2462 00:58:46.195318 [CBTSetCACLKResult] CA Dly = 33
2463 00:58:46.195399 CS Dly: 7 (0~38)
2464 00:58:46.195479 ==
2465 00:58:46.195561 Dram Type= 6, Freq= 0, CH_0, rank 1
2466 00:58:46.195642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 00:58:46.195723 ==
2468 00:58:46.195805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 00:58:46.195888 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2470 00:58:46.195969 [CA 0] Center 39 (9~70) winsize 62
2471 00:58:46.196050 [CA 1] Center 39 (9~70) winsize 62
2472 00:58:46.196131 [CA 2] Center 35 (5~66) winsize 62
2473 00:58:46.196212 [CA 3] Center 35 (5~66) winsize 62
2474 00:58:46.196293 [CA 4] Center 34 (4~65) winsize 62
2475 00:58:46.196374 [CA 5] Center 33 (3~64) winsize 62
2476 00:58:46.196454
2477 00:58:46.196535 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2478 00:58:46.196616
2479 00:58:46.196697 [CATrainingPosCal] consider 2 rank data
2480 00:58:46.196778 u2DelayCellTimex100 = 270/100 ps
2481 00:58:46.196859 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2482 00:58:46.197163 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2483 00:58:46.197261 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2484 00:58:46.197336 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2485 00:58:46.197390 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2486 00:58:46.197444 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2487 00:58:46.197496
2488 00:58:46.197549 CA PerBit enable=1, Macro0, CA PI delay=33
2489 00:58:46.197601
2490 00:58:46.197653 [CBTSetCACLKResult] CA Dly = 33
2491 00:58:46.197705 CS Dly: 8 (0~41)
2492 00:58:46.197757
2493 00:58:46.197808 ----->DramcWriteLeveling(PI) begin...
2494 00:58:46.197862 ==
2495 00:58:46.197915 Dram Type= 6, Freq= 0, CH_0, rank 0
2496 00:58:46.197968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 00:58:46.198020 ==
2498 00:58:46.198073 Write leveling (Byte 0): 31 => 31
2499 00:58:46.198125 Write leveling (Byte 1): 29 => 29
2500 00:58:46.198177 DramcWriteLeveling(PI) end<-----
2501 00:58:46.198230
2502 00:58:46.198282 ==
2503 00:58:46.198334 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 00:58:46.198386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 00:58:46.198439 ==
2506 00:58:46.198491 [Gating] SW mode calibration
2507 00:58:46.198543 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2508 00:58:46.198596 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2509 00:58:46.198649 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2510 00:58:46.198702 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2511 00:58:46.198754 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2512 00:58:46.198806 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2513 00:58:46.198858 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 00:58:46.198910 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 00:58:46.198962 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2516 00:58:46.199014 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
2517 00:58:46.199067 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
2518 00:58:46.199118 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2519 00:58:46.199171 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2520 00:58:46.199283 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 00:58:46.199373 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 00:58:46.199431 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 00:58:46.199484 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2524 00:58:46.199537 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2525 00:58:46.199589 1 1 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2526 00:58:46.199642 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2527 00:58:46.199694 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2528 00:58:46.199745 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 00:58:46.199797 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 00:58:46.199849 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 00:58:46.199901 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2532 00:58:46.199954 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2533 00:58:46.200006 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2534 00:58:46.200057 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2535 00:58:46.200110 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2536 00:58:46.200163 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 00:58:46.200215 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 00:58:46.200266 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 00:58:46.200318 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 00:58:46.200370 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 00:58:46.200422 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 00:58:46.200473 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 00:58:46.200525 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 00:58:46.200577 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 00:58:46.200629 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 00:58:46.200681 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 00:58:46.200732 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 00:58:46.200784 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2549 00:58:46.200836 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2550 00:58:46.200888 Total UI for P1: 0, mck2ui 16
2551 00:58:46.200941 best dqsien dly found for B0: ( 1, 3, 28)
2552 00:58:46.200993 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2553 00:58:46.201045 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 00:58:46.201096 Total UI for P1: 0, mck2ui 16
2555 00:58:46.201149 best dqsien dly found for B1: ( 1, 4, 2)
2556 00:58:46.201201 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2557 00:58:46.201253 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2558 00:58:46.201349
2559 00:58:46.201401 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2560 00:58:46.201454 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2561 00:58:46.201506 [Gating] SW calibration Done
2562 00:58:46.201558 ==
2563 00:58:46.201610 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 00:58:46.201662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 00:58:46.201715 ==
2566 00:58:46.201767 RX Vref Scan: 0
2567 00:58:46.201818
2568 00:58:46.201870 RX Vref 0 -> 0, step: 1
2569 00:58:46.201922
2570 00:58:46.201973 RX Delay -40 -> 252, step: 8
2571 00:58:46.202025 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2572 00:58:46.202077 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2573 00:58:46.202129 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2574 00:58:46.202182 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2575 00:58:46.202233 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2576 00:58:46.202285 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2577 00:58:46.202338 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2578 00:58:46.202390 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2579 00:58:46.202441 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2580 00:58:46.202493 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2581 00:58:46.202545 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2582 00:58:46.202596 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2583 00:58:46.202844 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2584 00:58:46.202905 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2585 00:58:46.202959 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2586 00:58:46.203012 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2587 00:58:46.203063 ==
2588 00:58:46.203115 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 00:58:46.203168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 00:58:46.203221 ==
2591 00:58:46.203273 DQS Delay:
2592 00:58:46.203325 DQS0 = 0, DQS1 = 0
2593 00:58:46.203433 DQM Delay:
2594 00:58:46.203500 DQM0 = 117, DQM1 = 108
2595 00:58:46.203552 DQ Delay:
2596 00:58:46.203603 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2597 00:58:46.203655 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2598 00:58:46.203707 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2599 00:58:46.203760 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2600 00:58:46.203812
2601 00:58:46.203864
2602 00:58:46.203915 ==
2603 00:58:46.203967 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 00:58:46.204018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 00:58:46.204070 ==
2606 00:58:46.204122
2607 00:58:46.204173
2608 00:58:46.204224 TX Vref Scan disable
2609 00:58:46.204275 == TX Byte 0 ==
2610 00:58:46.204327 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2611 00:58:46.204380 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2612 00:58:46.204432 == TX Byte 1 ==
2613 00:58:46.204484 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2614 00:58:46.204537 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2615 00:58:46.204588 ==
2616 00:58:46.204640 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 00:58:46.204692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 00:58:46.204744 ==
2619 00:58:46.204796 TX Vref=22, minBit 1, minWin=24, winSum=412
2620 00:58:46.204848 TX Vref=24, minBit 4, minWin=25, winSum=417
2621 00:58:46.204900 TX Vref=26, minBit 1, minWin=25, winSum=424
2622 00:58:46.204952 TX Vref=28, minBit 4, minWin=26, winSum=430
2623 00:58:46.205004 TX Vref=30, minBit 1, minWin=26, winSum=429
2624 00:58:46.205057 TX Vref=32, minBit 0, minWin=26, winSum=427
2625 00:58:46.205109 [TxChooseVref] Worse bit 4, Min win 26, Win sum 430, Final Vref 28
2626 00:58:46.205161
2627 00:58:46.205213 Final TX Range 1 Vref 28
2628 00:58:46.205291
2629 00:58:46.205358 ==
2630 00:58:46.205410 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 00:58:46.205461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 00:58:46.205514 ==
2633 00:58:46.205565
2634 00:58:46.205617
2635 00:58:46.205668 TX Vref Scan disable
2636 00:58:46.205720 == TX Byte 0 ==
2637 00:58:46.205772 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2638 00:58:46.205825 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2639 00:58:46.205877 == TX Byte 1 ==
2640 00:58:46.205928 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2641 00:58:46.205980 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2642 00:58:46.206032
2643 00:58:46.206083 [DATLAT]
2644 00:58:46.206134 Freq=1200, CH0 RK0
2645 00:58:46.206185
2646 00:58:46.206237 DATLAT Default: 0xd
2647 00:58:46.206288 0, 0xFFFF, sum = 0
2648 00:58:46.206341 1, 0xFFFF, sum = 0
2649 00:58:46.206394 2, 0xFFFF, sum = 0
2650 00:58:46.206447 3, 0xFFFF, sum = 0
2651 00:58:46.206500 4, 0xFFFF, sum = 0
2652 00:58:46.206553 5, 0xFFFF, sum = 0
2653 00:58:46.206606 6, 0xFFFF, sum = 0
2654 00:58:46.206658 7, 0xFFFF, sum = 0
2655 00:58:46.206712 8, 0xFFFF, sum = 0
2656 00:58:46.206765 9, 0xFFFF, sum = 0
2657 00:58:46.206817 10, 0xFFFF, sum = 0
2658 00:58:46.206870 11, 0xFFFF, sum = 0
2659 00:58:46.206922 12, 0x0, sum = 1
2660 00:58:46.206975 13, 0x0, sum = 2
2661 00:58:46.207028 14, 0x0, sum = 3
2662 00:58:46.207081 15, 0x0, sum = 4
2663 00:58:46.207133 best_step = 13
2664 00:58:46.207184
2665 00:58:46.207236 ==
2666 00:58:46.207288 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 00:58:46.207340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 00:58:46.207392 ==
2669 00:58:46.207444 RX Vref Scan: 1
2670 00:58:46.207496
2671 00:58:46.207547 Set Vref Range= 32 -> 127
2672 00:58:46.207599
2673 00:58:46.207650 RX Vref 32 -> 127, step: 1
2674 00:58:46.207701
2675 00:58:46.207752 RX Delay -21 -> 252, step: 4
2676 00:58:46.207804
2677 00:58:46.207855 Set Vref, RX VrefLevel [Byte0]: 32
2678 00:58:46.207907 [Byte1]: 32
2679 00:58:46.207959
2680 00:58:46.208010 Set Vref, RX VrefLevel [Byte0]: 33
2681 00:58:46.208062 [Byte1]: 33
2682 00:58:46.208114
2683 00:58:46.208165 Set Vref, RX VrefLevel [Byte0]: 34
2684 00:58:46.208217 [Byte1]: 34
2685 00:58:46.208268
2686 00:58:46.208319 Set Vref, RX VrefLevel [Byte0]: 35
2687 00:58:46.208371 [Byte1]: 35
2688 00:58:46.208422
2689 00:58:46.208474 Set Vref, RX VrefLevel [Byte0]: 36
2690 00:58:46.208526 [Byte1]: 36
2691 00:58:46.208578
2692 00:58:46.208629 Set Vref, RX VrefLevel [Byte0]: 37
2693 00:58:46.208681 [Byte1]: 37
2694 00:58:46.208732
2695 00:58:46.208783 Set Vref, RX VrefLevel [Byte0]: 38
2696 00:58:46.208835 [Byte1]: 38
2697 00:58:46.208887
2698 00:58:46.208938 Set Vref, RX VrefLevel [Byte0]: 39
2699 00:58:46.208990 [Byte1]: 39
2700 00:58:46.209042
2701 00:58:46.209094 Set Vref, RX VrefLevel [Byte0]: 40
2702 00:58:46.209146 [Byte1]: 40
2703 00:58:46.209197
2704 00:58:46.209248 Set Vref, RX VrefLevel [Byte0]: 41
2705 00:58:46.209342 [Byte1]: 41
2706 00:58:46.209395
2707 00:58:46.209446 Set Vref, RX VrefLevel [Byte0]: 42
2708 00:58:46.209497 [Byte1]: 42
2709 00:58:46.209549
2710 00:58:46.209600 Set Vref, RX VrefLevel [Byte0]: 43
2711 00:58:46.209652 [Byte1]: 43
2712 00:58:46.209704
2713 00:58:46.209754 Set Vref, RX VrefLevel [Byte0]: 44
2714 00:58:46.209806 [Byte1]: 44
2715 00:58:46.209858
2716 00:58:46.209909 Set Vref, RX VrefLevel [Byte0]: 45
2717 00:58:46.209960 [Byte1]: 45
2718 00:58:46.210012
2719 00:58:46.210063 Set Vref, RX VrefLevel [Byte0]: 46
2720 00:58:46.210115 [Byte1]: 46
2721 00:58:46.210166
2722 00:58:46.210217 Set Vref, RX VrefLevel [Byte0]: 47
2723 00:58:46.210269 [Byte1]: 47
2724 00:58:46.210320
2725 00:58:46.210371 Set Vref, RX VrefLevel [Byte0]: 48
2726 00:58:46.210423 [Byte1]: 48
2727 00:58:46.210475
2728 00:58:46.210526 Set Vref, RX VrefLevel [Byte0]: 49
2729 00:58:46.210578 [Byte1]: 49
2730 00:58:46.210629
2731 00:58:46.210680 Set Vref, RX VrefLevel [Byte0]: 50
2732 00:58:46.210732 [Byte1]: 50
2733 00:58:46.210783
2734 00:58:46.210835 Set Vref, RX VrefLevel [Byte0]: 51
2735 00:58:46.210886 [Byte1]: 51
2736 00:58:46.210938
2737 00:58:46.210989 Set Vref, RX VrefLevel [Byte0]: 52
2738 00:58:46.211041 [Byte1]: 52
2739 00:58:46.211092
2740 00:58:46.211143 Set Vref, RX VrefLevel [Byte0]: 53
2741 00:58:46.211195 [Byte1]: 53
2742 00:58:46.211247
2743 00:58:46.211298 Set Vref, RX VrefLevel [Byte0]: 54
2744 00:58:46.211350 [Byte1]: 54
2745 00:58:46.211401
2746 00:58:46.211453 Set Vref, RX VrefLevel [Byte0]: 55
2747 00:58:46.211504 [Byte1]: 55
2748 00:58:46.211555
2749 00:58:46.211796 Set Vref, RX VrefLevel [Byte0]: 56
2750 00:58:46.211855 [Byte1]: 56
2751 00:58:46.211908
2752 00:58:46.211960 Set Vref, RX VrefLevel [Byte0]: 57
2753 00:58:46.212012 [Byte1]: 57
2754 00:58:46.212064
2755 00:58:46.212116 Set Vref, RX VrefLevel [Byte0]: 58
2756 00:58:46.212168 [Byte1]: 58
2757 00:58:46.212220
2758 00:58:46.212271 Set Vref, RX VrefLevel [Byte0]: 59
2759 00:58:46.212323 [Byte1]: 59
2760 00:58:46.212375
2761 00:58:46.212426 Set Vref, RX VrefLevel [Byte0]: 60
2762 00:58:46.212478 [Byte1]: 60
2763 00:58:46.212530
2764 00:58:46.212581 Set Vref, RX VrefLevel [Byte0]: 61
2765 00:58:46.212633 [Byte1]: 61
2766 00:58:46.212685
2767 00:58:46.212736 Set Vref, RX VrefLevel [Byte0]: 62
2768 00:58:46.212788 [Byte1]: 62
2769 00:58:46.212840
2770 00:58:46.212891 Set Vref, RX VrefLevel [Byte0]: 63
2771 00:58:46.212943 [Byte1]: 63
2772 00:58:46.212994
2773 00:58:46.213046 Set Vref, RX VrefLevel [Byte0]: 64
2774 00:58:46.213098 [Byte1]: 64
2775 00:58:46.213149
2776 00:58:46.213201 Set Vref, RX VrefLevel [Byte0]: 65
2777 00:58:46.213253 [Byte1]: 65
2778 00:58:46.213346
2779 00:58:46.213398 Set Vref, RX VrefLevel [Byte0]: 66
2780 00:58:46.213449 [Byte1]: 66
2781 00:58:46.213501
2782 00:58:46.213553 Set Vref, RX VrefLevel [Byte0]: 67
2783 00:58:46.213605 [Byte1]: 67
2784 00:58:46.213657
2785 00:58:46.213708 Set Vref, RX VrefLevel [Byte0]: 68
2786 00:58:46.213760 [Byte1]: 68
2787 00:58:46.213811
2788 00:58:46.213863 Final RX Vref Byte 0 = 55 to rank0
2789 00:58:46.213915 Final RX Vref Byte 1 = 58 to rank0
2790 00:58:46.213967 Final RX Vref Byte 0 = 55 to rank1
2791 00:58:46.214019 Final RX Vref Byte 1 = 58 to rank1==
2792 00:58:46.214071 Dram Type= 6, Freq= 0, CH_0, rank 0
2793 00:58:46.214123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2794 00:58:46.214176 ==
2795 00:58:46.214228 DQS Delay:
2796 00:58:46.214279 DQS0 = 0, DQS1 = 0
2797 00:58:46.214331 DQM Delay:
2798 00:58:46.214382 DQM0 = 117, DQM1 = 105
2799 00:58:46.214434 DQ Delay:
2800 00:58:46.214485 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2801 00:58:46.214537 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =120
2802 00:58:46.214589 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2803 00:58:46.214641 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2804 00:58:46.214693
2805 00:58:46.214747
2806 00:58:46.214799 [DQSOSCAuto] RK0, (LSB)MR18= 0x400, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2807 00:58:46.214852 CH0 RK0: MR19=404, MR18=400
2808 00:58:46.214903 CH0_RK0: MR19=0x404, MR18=0x400, DQSOSC=408, MR23=63, INC=39, DEC=26
2809 00:58:46.214955
2810 00:58:46.215007 ----->DramcWriteLeveling(PI) begin...
2811 00:58:46.215061 ==
2812 00:58:46.215112 Dram Type= 6, Freq= 0, CH_0, rank 1
2813 00:58:46.215164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2814 00:58:46.215216 ==
2815 00:58:46.215268 Write leveling (Byte 0): 30 => 30
2816 00:58:46.215320 Write leveling (Byte 1): 26 => 26
2817 00:58:46.215372 DramcWriteLeveling(PI) end<-----
2818 00:58:46.215424
2819 00:58:46.215475 ==
2820 00:58:46.215527 Dram Type= 6, Freq= 0, CH_0, rank 1
2821 00:58:46.215580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 00:58:46.215632 ==
2823 00:58:46.215684 [Gating] SW mode calibration
2824 00:58:46.215737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2825 00:58:46.215789 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2826 00:58:46.215842 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
2827 00:58:46.215894 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2828 00:58:46.215946 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2829 00:58:46.215999 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2830 00:58:46.216051 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2831 00:58:46.216103 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2832 00:58:46.216155 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2833 00:58:46.216207 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
2834 00:58:46.216259 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
2835 00:58:46.216311 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2836 00:58:46.216363 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2837 00:58:46.216414 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2838 00:58:46.216466 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 00:58:46.216518 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 00:58:46.216570 1 0 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
2841 00:58:46.216621 1 0 28 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2842 00:58:46.216673 1 1 0 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
2843 00:58:46.216725 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2844 00:58:46.216777 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2845 00:58:46.216828 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 00:58:46.216880 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 00:58:46.216931 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 00:58:46.216982 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2849 00:58:46.217034 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2850 00:58:46.217085 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2851 00:58:46.217137 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2852 00:58:46.217189 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2853 00:58:46.217241 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 00:58:46.217351 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 00:58:46.217433 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 00:58:46.217515 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 00:58:46.217597 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 00:58:46.217679 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 00:58:46.217760 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 00:58:46.217842 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 00:58:46.217924 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 00:58:46.218005 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 00:58:46.218086 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 00:58:46.218360 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2865 00:58:46.218446 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2866 00:58:46.218529 Total UI for P1: 0, mck2ui 16
2867 00:58:46.218611 best dqsien dly found for B0: ( 1, 3, 24)
2868 00:58:46.218694 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2869 00:58:46.218776 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 00:58:46.218857 Total UI for P1: 0, mck2ui 16
2871 00:58:46.218939 best dqsien dly found for B1: ( 1, 3, 30)
2872 00:58:46.219020 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2873 00:58:46.219102 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2874 00:58:46.219182
2875 00:58:46.219263 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2876 00:58:46.219345 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2877 00:58:46.219426 [Gating] SW calibration Done
2878 00:58:46.219506 ==
2879 00:58:46.219588 Dram Type= 6, Freq= 0, CH_0, rank 1
2880 00:58:46.219669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2881 00:58:46.219751 ==
2882 00:58:46.219831 RX Vref Scan: 0
2883 00:58:46.219911
2884 00:58:46.219992 RX Vref 0 -> 0, step: 1
2885 00:58:46.220072
2886 00:58:46.220152 RX Delay -40 -> 252, step: 8
2887 00:58:46.220234 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2888 00:58:46.220315 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2889 00:58:46.220397 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2890 00:58:46.220478 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2891 00:58:46.220559 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2892 00:58:46.220641 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2893 00:58:46.220722 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2894 00:58:46.220804 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2895 00:58:46.220885 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2896 00:58:46.220967 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2897 00:58:46.221048 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2898 00:58:46.221130 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2899 00:58:46.221211 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2900 00:58:46.221330 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2901 00:58:46.221385 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2902 00:58:46.221438 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2903 00:58:46.221491 ==
2904 00:58:46.221543 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 00:58:46.221595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 00:58:46.221648 ==
2907 00:58:46.221700 DQS Delay:
2908 00:58:46.221752 DQS0 = 0, DQS1 = 0
2909 00:58:46.221804 DQM Delay:
2910 00:58:46.221856 DQM0 = 116, DQM1 = 109
2911 00:58:46.221908 DQ Delay:
2912 00:58:46.221959 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2913 00:58:46.222011 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2914 00:58:46.222064 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2915 00:58:46.222116 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =115
2916 00:58:46.222168
2917 00:58:46.222219
2918 00:58:46.222270 ==
2919 00:58:46.222322 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 00:58:46.222374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 00:58:46.222427 ==
2922 00:58:46.222478
2923 00:58:46.222529
2924 00:58:46.222580 TX Vref Scan disable
2925 00:58:46.222632 == TX Byte 0 ==
2926 00:58:46.222683 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2927 00:58:46.222735 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2928 00:58:46.222787 == TX Byte 1 ==
2929 00:58:46.222839 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2930 00:58:46.222891 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2931 00:58:46.222943 ==
2932 00:58:46.222995 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 00:58:46.223046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 00:58:46.319542 ==
2935 00:58:46.319694 TX Vref=22, minBit 1, minWin=25, winSum=411
2936 00:58:46.319805 TX Vref=24, minBit 1, minWin=25, winSum=413
2937 00:58:46.319910 TX Vref=26, minBit 5, minWin=25, winSum=422
2938 00:58:46.320012 TX Vref=28, minBit 0, minWin=26, winSum=425
2939 00:58:46.320112 TX Vref=30, minBit 0, minWin=26, winSum=426
2940 00:58:46.320212 TX Vref=32, minBit 5, minWin=25, winSum=421
2941 00:58:46.320310 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
2942 00:58:46.320409
2943 00:58:46.320506 Final TX Range 1 Vref 30
2944 00:58:46.320604
2945 00:58:46.320699 ==
2946 00:58:46.320796 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 00:58:46.320892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 00:58:46.320990 ==
2949 00:58:46.321086
2950 00:58:46.321182
2951 00:58:46.321285 TX Vref Scan disable
2952 00:58:46.321382 == TX Byte 0 ==
2953 00:58:46.321477 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2954 00:58:46.321574 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2955 00:58:46.321669 == TX Byte 1 ==
2956 00:58:46.321765 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2957 00:58:46.321861 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2958 00:58:46.321957
2959 00:58:46.322052 [DATLAT]
2960 00:58:46.322146 Freq=1200, CH0 RK1
2961 00:58:46.322241
2962 00:58:46.322334 DATLAT Default: 0xd
2963 00:58:46.322429 0, 0xFFFF, sum = 0
2964 00:58:46.322526 1, 0xFFFF, sum = 0
2965 00:58:46.322623 2, 0xFFFF, sum = 0
2966 00:58:46.322720 3, 0xFFFF, sum = 0
2967 00:58:46.322817 4, 0xFFFF, sum = 0
2968 00:58:46.322913 5, 0xFFFF, sum = 0
2969 00:58:46.323010 6, 0xFFFF, sum = 0
2970 00:58:46.323107 7, 0xFFFF, sum = 0
2971 00:58:46.323204 8, 0xFFFF, sum = 0
2972 00:58:46.323301 9, 0xFFFF, sum = 0
2973 00:58:46.323398 10, 0xFFFF, sum = 0
2974 00:58:46.323495 11, 0xFFFF, sum = 0
2975 00:58:46.323592 12, 0x0, sum = 1
2976 00:58:46.323689 13, 0x0, sum = 2
2977 00:58:46.323785 14, 0x0, sum = 3
2978 00:58:46.323882 15, 0x0, sum = 4
2979 00:58:46.323979 best_step = 13
2980 00:58:46.324073
2981 00:58:46.324178 ==
2982 00:58:46.324283 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 00:58:46.324388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 00:58:46.324494 ==
2985 00:58:46.324596 RX Vref Scan: 0
2986 00:58:46.324695
2987 00:58:46.324793 RX Vref 0 -> 0, step: 1
2988 00:58:46.324890
2989 00:58:46.324985 RX Delay -21 -> 252, step: 4
2990 00:58:46.325081 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
2991 00:58:46.325178 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
2992 00:58:46.325279 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
2993 00:58:46.325415 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
2994 00:58:46.325510 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
2995 00:58:46.325606 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
2996 00:58:46.325701 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
2997 00:58:46.325796 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
2998 00:58:46.325891 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
2999 00:58:46.325985 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3000 00:58:46.326080 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3001 00:58:46.326176 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3002 00:58:46.326486 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3003 00:58:46.326593 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3004 00:58:46.326693 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3005 00:58:46.326791 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3006 00:58:46.326889 ==
3007 00:58:46.326987 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 00:58:46.327085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 00:58:46.327182 ==
3010 00:58:46.327278 DQS Delay:
3011 00:58:46.327373 DQS0 = 0, DQS1 = 0
3012 00:58:46.327468 DQM Delay:
3013 00:58:46.327562 DQM0 = 116, DQM1 = 106
3014 00:58:46.327655 DQ Delay:
3015 00:58:46.327749 DQ0 =112, DQ1 =116, DQ2 =112, DQ3 =114
3016 00:58:46.327844 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3017 00:58:46.327938 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3018 00:58:46.328033 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3019 00:58:46.328128
3020 00:58:46.328222
3021 00:58:46.328316 [DQSOSCAuto] RK1, (LSB)MR18= 0xfdfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3022 00:58:46.328413 CH0 RK1: MR19=303, MR18=FDFB
3023 00:58:46.328508 CH0_RK1: MR19=0x303, MR18=0xFDFB, DQSOSC=411, MR23=63, INC=38, DEC=25
3024 00:58:46.328604 [RxdqsGatingPostProcess] freq 1200
3025 00:58:46.328699 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3026 00:58:46.328794 best DQS0 dly(2T, 0.5T) = (0, 11)
3027 00:58:46.328889 best DQS1 dly(2T, 0.5T) = (0, 12)
3028 00:58:46.328983 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3029 00:58:46.329078 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3030 00:58:46.329173 best DQS0 dly(2T, 0.5T) = (0, 11)
3031 00:58:46.329274 best DQS1 dly(2T, 0.5T) = (0, 11)
3032 00:58:46.329406 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3033 00:58:46.329501 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3034 00:58:46.329594 Pre-setting of DQS Precalculation
3035 00:58:46.329689 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3036 00:58:46.329785 ==
3037 00:58:46.329880 Dram Type= 6, Freq= 0, CH_1, rank 0
3038 00:58:46.329978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 00:58:46.330084 ==
3040 00:58:46.330189 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3041 00:58:46.330289 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3042 00:58:46.330388 [CA 0] Center 38 (8~68) winsize 61
3043 00:58:46.330486 [CA 1] Center 37 (7~68) winsize 62
3044 00:58:46.330581 [CA 2] Center 35 (6~65) winsize 60
3045 00:58:46.330678 [CA 3] Center 34 (4~64) winsize 61
3046 00:58:46.330774 [CA 4] Center 34 (4~65) winsize 62
3047 00:58:46.330869 [CA 5] Center 33 (3~64) winsize 62
3048 00:58:46.330964
3049 00:58:46.331058 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3050 00:58:46.331154
3051 00:58:46.331225 [CATrainingPosCal] consider 1 rank data
3052 00:58:46.331298 u2DelayCellTimex100 = 270/100 ps
3053 00:58:46.331371 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3054 00:58:46.331443 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3055 00:58:46.331515 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3056 00:58:46.331606 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3057 00:58:46.331698 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3058 00:58:46.331789 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3059 00:58:46.331880
3060 00:58:46.331971 CA PerBit enable=1, Macro0, CA PI delay=33
3061 00:58:46.332062
3062 00:58:46.332153 [CBTSetCACLKResult] CA Dly = 33
3063 00:58:46.332244 CS Dly: 5 (0~36)
3064 00:58:46.332335 ==
3065 00:58:46.332426 Dram Type= 6, Freq= 0, CH_1, rank 1
3066 00:58:46.332517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 00:58:46.332608 ==
3068 00:58:46.332699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3069 00:58:46.332790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3070 00:58:46.332881 [CA 0] Center 38 (8~68) winsize 61
3071 00:58:46.332972 [CA 1] Center 37 (7~68) winsize 62
3072 00:58:46.333062 [CA 2] Center 35 (5~65) winsize 61
3073 00:58:46.333152 [CA 3] Center 33 (3~64) winsize 62
3074 00:58:46.333242 [CA 4] Center 33 (4~63) winsize 60
3075 00:58:46.333374 [CA 5] Center 33 (3~64) winsize 62
3076 00:58:46.333464
3077 00:58:46.333555 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3078 00:58:46.333645
3079 00:58:46.333736 [CATrainingPosCal] consider 2 rank data
3080 00:58:46.333827 u2DelayCellTimex100 = 270/100 ps
3081 00:58:46.333918 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3082 00:58:46.334009 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3083 00:58:46.334100 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3084 00:58:46.334190 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3085 00:58:46.334281 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
3086 00:58:46.334371 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3087 00:58:46.334461
3088 00:58:46.334551 CA PerBit enable=1, Macro0, CA PI delay=33
3089 00:58:46.334642
3090 00:58:46.334732 [CBTSetCACLKResult] CA Dly = 33
3091 00:58:46.334822 CS Dly: 6 (0~39)
3092 00:58:46.334912
3093 00:58:46.335002 ----->DramcWriteLeveling(PI) begin...
3094 00:58:46.335094 ==
3095 00:58:46.335184 Dram Type= 6, Freq= 0, CH_1, rank 0
3096 00:58:46.335276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 00:58:46.335367 ==
3098 00:58:46.335458 Write leveling (Byte 0): 29 => 29
3099 00:58:46.335549 Write leveling (Byte 1): 28 => 28
3100 00:58:46.335640 DramcWriteLeveling(PI) end<-----
3101 00:58:46.335730
3102 00:58:46.335820 ==
3103 00:58:46.335910 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 00:58:46.336001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 00:58:46.336092 ==
3106 00:58:46.336182 [Gating] SW mode calibration
3107 00:58:46.336273 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3108 00:58:46.336364 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3109 00:58:46.336454 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3110 00:58:46.336544 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3111 00:58:46.336635 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3112 00:58:46.336725 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 00:58:46.336814 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 00:58:46.336905 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 00:58:46.336994 0 15 24 | B1->B0 | 3333 3131 | 0 1 | (0 1) (1 0)
3116 00:58:46.337084 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
3117 00:58:46.337174 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3118 00:58:46.337268 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3119 00:58:46.337396 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3120 00:58:46.337684 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3121 00:58:46.337779 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 00:58:46.337873 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 00:58:46.337966 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
3124 00:58:46.338059 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3125 00:58:46.338151 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3126 00:58:46.338243 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3127 00:58:46.338335 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 00:58:46.338426 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 00:58:46.338517 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 00:58:46.338608 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 00:58:46.338698 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 00:58:46.338789 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3133 00:58:46.338879 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3134 00:58:46.338969 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3135 00:58:46.339059 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 00:58:46.339149 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 00:58:46.339239 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 00:58:46.339328 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 00:58:46.339419 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 00:58:46.339509 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 00:58:46.339598 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 00:58:46.339688 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 00:58:46.339778 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 00:58:46.339868 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 00:58:46.339957 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 00:58:46.340047 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 00:58:46.340136 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3148 00:58:46.340225 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3149 00:58:46.340314 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 00:58:46.340404 Total UI for P1: 0, mck2ui 16
3151 00:58:46.340495 best dqsien dly found for B0: ( 1, 3, 26)
3152 00:58:46.340586 Total UI for P1: 0, mck2ui 16
3153 00:58:46.340676 best dqsien dly found for B1: ( 1, 3, 26)
3154 00:58:46.340767 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3155 00:58:46.340857 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3156 00:58:46.340947
3157 00:58:46.341036 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3158 00:58:46.341126 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3159 00:58:46.341216 [Gating] SW calibration Done
3160 00:58:46.341313 ==
3161 00:58:46.341405 Dram Type= 6, Freq= 0, CH_1, rank 0
3162 00:58:46.341496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 00:58:46.341587 ==
3164 00:58:46.341677 RX Vref Scan: 0
3165 00:58:46.341767
3166 00:58:46.341857 RX Vref 0 -> 0, step: 1
3167 00:58:46.341946
3168 00:58:46.342036 RX Delay -40 -> 252, step: 8
3169 00:58:46.342126 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3170 00:58:46.342216 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3171 00:58:46.342306 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3172 00:58:46.342395 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3173 00:58:46.342484 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3174 00:58:46.342574 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3175 00:58:46.342664 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3176 00:58:46.342754 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3177 00:58:46.342843 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3178 00:58:46.342933 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3179 00:58:46.343023 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3180 00:58:46.343113 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3181 00:58:46.343202 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3182 00:58:46.343292 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3183 00:58:46.343382 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3184 00:58:46.343471 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3185 00:58:46.343560 ==
3186 00:58:46.343650 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 00:58:46.343740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 00:58:46.343831 ==
3189 00:58:46.343957 DQS Delay:
3190 00:58:46.344046 DQS0 = 0, DQS1 = 0
3191 00:58:46.344136 DQM Delay:
3192 00:58:46.344225 DQM0 = 115, DQM1 = 112
3193 00:58:46.344314 DQ Delay:
3194 00:58:46.344404 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3195 00:58:46.344494 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3196 00:58:46.344584 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3197 00:58:46.344674 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3198 00:58:46.344763
3199 00:58:46.344853
3200 00:58:46.344942 ==
3201 00:58:46.345032 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 00:58:46.345122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 00:58:46.345212 ==
3204 00:58:46.345307
3205 00:58:46.345397
3206 00:58:46.345486 TX Vref Scan disable
3207 00:58:46.345576 == TX Byte 0 ==
3208 00:58:46.345665 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3209 00:58:46.345756 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3210 00:58:46.345846 == TX Byte 1 ==
3211 00:58:46.345936 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3212 00:58:46.346027 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3213 00:58:46.346117 ==
3214 00:58:46.346208 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 00:58:46.346297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 00:58:46.346388 ==
3217 00:58:46.346479 TX Vref=22, minBit 2, minWin=25, winSum=410
3218 00:58:46.346570 TX Vref=24, minBit 0, minWin=25, winSum=417
3219 00:58:46.346661 TX Vref=26, minBit 0, minWin=25, winSum=418
3220 00:58:46.346752 TX Vref=28, minBit 3, minWin=25, winSum=426
3221 00:58:46.346843 TX Vref=30, minBit 1, minWin=26, winSum=425
3222 00:58:46.346933 TX Vref=32, minBit 1, minWin=26, winSum=425
3223 00:58:46.347023 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 30
3224 00:58:46.347113
3225 00:58:46.347202 Final TX Range 1 Vref 30
3226 00:58:46.347293
3227 00:58:46.347382 ==
3228 00:58:46.347472 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 00:58:46.347562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 00:58:46.347652 ==
3231 00:58:46.347742
3232 00:58:46.347831
3233 00:58:46.347919 TX Vref Scan disable
3234 00:58:46.348010 == TX Byte 0 ==
3235 00:58:46.348295 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3236 00:58:46.348388 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3237 00:58:46.348482 == TX Byte 1 ==
3238 00:58:46.348575 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3239 00:58:46.348667 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3240 00:58:46.348759
3241 00:58:46.348850 [DATLAT]
3242 00:58:46.348943 Freq=1200, CH1 RK0
3243 00:58:46.349035
3244 00:58:46.349126 DATLAT Default: 0xd
3245 00:58:46.349217 0, 0xFFFF, sum = 0
3246 00:58:46.349358 1, 0xFFFF, sum = 0
3247 00:58:46.349452 2, 0xFFFF, sum = 0
3248 00:58:46.349545 3, 0xFFFF, sum = 0
3249 00:58:46.349638 4, 0xFFFF, sum = 0
3250 00:58:46.349731 5, 0xFFFF, sum = 0
3251 00:58:46.349823 6, 0xFFFF, sum = 0
3252 00:58:46.349915 7, 0xFFFF, sum = 0
3253 00:58:46.350007 8, 0xFFFF, sum = 0
3254 00:58:46.350099 9, 0xFFFF, sum = 0
3255 00:58:46.350190 10, 0xFFFF, sum = 0
3256 00:58:46.350283 11, 0xFFFF, sum = 0
3257 00:58:46.350375 12, 0x0, sum = 1
3258 00:58:46.350467 13, 0x0, sum = 2
3259 00:58:46.350559 14, 0x0, sum = 3
3260 00:58:46.350651 15, 0x0, sum = 4
3261 00:58:46.350743 best_step = 13
3262 00:58:46.350833
3263 00:58:46.350922 ==
3264 00:58:46.351013 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 00:58:46.351103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 00:58:46.351194 ==
3267 00:58:46.351284 RX Vref Scan: 1
3268 00:58:46.351374
3269 00:58:46.351464 Set Vref Range= 32 -> 127
3270 00:58:46.351554
3271 00:58:46.351644 RX Vref 32 -> 127, step: 1
3272 00:58:46.351734
3273 00:58:46.351824 RX Delay -13 -> 252, step: 4
3274 00:58:46.351914
3275 00:58:46.352003 Set Vref, RX VrefLevel [Byte0]: 32
3276 00:58:46.352094 [Byte1]: 32
3277 00:58:46.352184
3278 00:58:46.352274 Set Vref, RX VrefLevel [Byte0]: 33
3279 00:58:46.352365 [Byte1]: 33
3280 00:58:46.352455
3281 00:58:46.352545 Set Vref, RX VrefLevel [Byte0]: 34
3282 00:58:46.352634 [Byte1]: 34
3283 00:58:46.352724
3284 00:58:46.352814 Set Vref, RX VrefLevel [Byte0]: 35
3285 00:58:46.352903 [Byte1]: 35
3286 00:58:46.352992
3287 00:58:46.353082 Set Vref, RX VrefLevel [Byte0]: 36
3288 00:58:46.353172 [Byte1]: 36
3289 00:58:46.353264
3290 00:58:46.353393 Set Vref, RX VrefLevel [Byte0]: 37
3291 00:58:46.353483 [Byte1]: 37
3292 00:58:46.353573
3293 00:58:46.353663 Set Vref, RX VrefLevel [Byte0]: 38
3294 00:58:46.353763 [Byte1]: 38
3295 00:58:46.353855
3296 00:58:46.353945 Set Vref, RX VrefLevel [Byte0]: 39
3297 00:58:46.354040 [Byte1]: 39
3298 00:58:46.354130
3299 00:58:46.354214 Set Vref, RX VrefLevel [Byte0]: 40
3300 00:58:46.354301 [Byte1]: 40
3301 00:58:46.354386
3302 00:58:46.354469 Set Vref, RX VrefLevel [Byte0]: 41
3303 00:58:46.354553 [Byte1]: 41
3304 00:58:46.354636
3305 00:58:46.354717 Set Vref, RX VrefLevel [Byte0]: 42
3306 00:58:46.354800 [Byte1]: 42
3307 00:58:46.354883
3308 00:58:46.354968 Set Vref, RX VrefLevel [Byte0]: 43
3309 00:58:46.355050 [Byte1]: 43
3310 00:58:46.355133
3311 00:58:46.355214 Set Vref, RX VrefLevel [Byte0]: 44
3312 00:58:46.355296 [Byte1]: 44
3313 00:58:46.355379
3314 00:58:46.355460 Set Vref, RX VrefLevel [Byte0]: 45
3315 00:58:46.355542 [Byte1]: 45
3316 00:58:46.355623
3317 00:58:46.355704 Set Vref, RX VrefLevel [Byte0]: 46
3318 00:58:46.355786 [Byte1]: 46
3319 00:58:46.355868
3320 00:58:46.355948 Set Vref, RX VrefLevel [Byte0]: 47
3321 00:58:46.356029 [Byte1]: 47
3322 00:58:46.356111
3323 00:58:46.356194 Set Vref, RX VrefLevel [Byte0]: 48
3324 00:58:46.356276 [Byte1]: 48
3325 00:58:46.356357
3326 00:58:46.356438 Set Vref, RX VrefLevel [Byte0]: 49
3327 00:58:46.356520 [Byte1]: 49
3328 00:58:46.356601
3329 00:58:46.356685 Set Vref, RX VrefLevel [Byte0]: 50
3330 00:58:46.356767 [Byte1]: 50
3331 00:58:46.356848
3332 00:58:46.356928 Set Vref, RX VrefLevel [Byte0]: 51
3333 00:58:46.357010 [Byte1]: 51
3334 00:58:46.357091
3335 00:58:46.357172 Set Vref, RX VrefLevel [Byte0]: 52
3336 00:58:46.357254 [Byte1]: 52
3337 00:58:46.357380
3338 00:58:46.357462 Set Vref, RX VrefLevel [Byte0]: 53
3339 00:58:46.357543 [Byte1]: 53
3340 00:58:46.357626
3341 00:58:46.357707 Set Vref, RX VrefLevel [Byte0]: 54
3342 00:58:46.357789 [Byte1]: 54
3343 00:58:46.357870
3344 00:58:46.357951 Set Vref, RX VrefLevel [Byte0]: 55
3345 00:58:46.358033 [Byte1]: 55
3346 00:58:46.358114
3347 00:58:46.358194 Set Vref, RX VrefLevel [Byte0]: 56
3348 00:58:46.358277 [Byte1]: 56
3349 00:58:46.358358
3350 00:58:46.358439 Set Vref, RX VrefLevel [Byte0]: 57
3351 00:58:46.358520 [Byte1]: 57
3352 00:58:46.358601
3353 00:58:46.358681 Set Vref, RX VrefLevel [Byte0]: 58
3354 00:58:46.358762 [Byte1]: 58
3355 00:58:46.358844
3356 00:58:46.358924 Set Vref, RX VrefLevel [Byte0]: 59
3357 00:58:46.359005 [Byte1]: 59
3358 00:58:46.359087
3359 00:58:46.359167 Set Vref, RX VrefLevel [Byte0]: 60
3360 00:58:46.359249 [Byte1]: 60
3361 00:58:46.359330
3362 00:58:46.359411 Set Vref, RX VrefLevel [Byte0]: 61
3363 00:58:46.359493 [Byte1]: 61
3364 00:58:46.359573
3365 00:58:46.359653 Set Vref, RX VrefLevel [Byte0]: 62
3366 00:58:46.359735 [Byte1]: 62
3367 00:58:46.359816
3368 00:58:46.359898 Set Vref, RX VrefLevel [Byte0]: 63
3369 00:58:46.359978 [Byte1]: 63
3370 00:58:46.360056
3371 00:58:46.360132 Set Vref, RX VrefLevel [Byte0]: 64
3372 00:58:46.360208 [Byte1]: 64
3373 00:58:46.360283
3374 00:58:46.360363 Final RX Vref Byte 0 = 52 to rank0
3375 00:58:46.360447 Final RX Vref Byte 1 = 53 to rank0
3376 00:58:46.360530 Final RX Vref Byte 0 = 52 to rank1
3377 00:58:46.360613 Final RX Vref Byte 1 = 53 to rank1==
3378 00:58:46.360697 Dram Type= 6, Freq= 0, CH_1, rank 0
3379 00:58:46.360781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3380 00:58:46.360865 ==
3381 00:58:46.360948 DQS Delay:
3382 00:58:46.361028 DQS0 = 0, DQS1 = 0
3383 00:58:46.361108 DQM Delay:
3384 00:58:46.361187 DQM0 = 114, DQM1 = 112
3385 00:58:46.361276 DQ Delay:
3386 00:58:46.361406 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3387 00:58:46.361501 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3388 00:58:46.361598 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3389 00:58:46.361693 DQ12 =122, DQ13 =120, DQ14 =116, DQ15 =122
3390 00:58:46.361787
3391 00:58:46.361889
3392 00:58:46.361991 [DQSOSCAuto] RK0, (LSB)MR18= 0xf501, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 414 ps
3393 00:58:46.362083 CH1 RK0: MR19=304, MR18=F501
3394 00:58:46.362169 CH1_RK0: MR19=0x304, MR18=0xF501, DQSOSC=409, MR23=63, INC=39, DEC=26
3395 00:58:46.362253
3396 00:58:46.362336 ----->DramcWriteLeveling(PI) begin...
3397 00:58:46.362420 ==
3398 00:58:46.362503 Dram Type= 6, Freq= 0, CH_1, rank 1
3399 00:58:46.362784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3400 00:58:46.362872 ==
3401 00:58:46.362957 Write leveling (Byte 0): 25 => 25
3402 00:58:46.363040 Write leveling (Byte 1): 26 => 26
3403 00:58:46.363122 DramcWriteLeveling(PI) end<-----
3404 00:58:46.363203
3405 00:58:46.363284 ==
3406 00:58:46.363367 Dram Type= 6, Freq= 0, CH_1, rank 1
3407 00:58:46.363449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3408 00:58:46.363531 ==
3409 00:58:46.363613 [Gating] SW mode calibration
3410 00:58:46.363696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3411 00:58:46.363779 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3412 00:58:46.363861 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3413 00:58:46.363943 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3414 00:58:46.364026 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3415 00:58:46.364107 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3416 00:58:46.364189 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3417 00:58:46.364272 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3418 00:58:46.364354 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
3419 00:58:46.364436 0 15 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
3420 00:58:46.364518 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3421 00:58:46.364600 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3422 00:58:46.364682 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3423 00:58:46.364763 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3424 00:58:46.364845 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3425 00:58:46.364927 1 0 20 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
3426 00:58:46.365008 1 0 24 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
3427 00:58:46.365090 1 0 28 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
3428 00:58:46.365172 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3429 00:58:46.365254 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3430 00:58:46.365379 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3431 00:58:46.365462 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3432 00:58:46.365544 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3433 00:58:46.365626 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3434 00:58:46.365707 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3435 00:58:46.365789 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3436 00:58:46.365871 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3437 00:58:46.365953 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3438 00:58:46.366035 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3439 00:58:46.366116 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3440 00:58:46.366198 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3441 00:58:46.366280 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3442 00:58:46.366362 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3443 00:58:46.366444 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3444 00:58:46.366526 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 00:58:46.366607 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 00:58:46.366689 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 00:58:46.366771 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 00:58:46.366853 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 00:58:46.366934 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3450 00:58:46.367017 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3451 00:58:46.367099 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3452 00:58:46.367181 Total UI for P1: 0, mck2ui 16
3453 00:58:46.367263 best dqsien dly found for B0: ( 1, 3, 22)
3454 00:58:46.367346 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 00:58:46.367427 Total UI for P1: 0, mck2ui 16
3456 00:58:46.367510 best dqsien dly found for B1: ( 1, 3, 26)
3457 00:58:46.367592 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3458 00:58:46.367674 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3459 00:58:46.367755
3460 00:58:46.367836 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3461 00:58:46.367918 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3462 00:58:46.367999 [Gating] SW calibration Done
3463 00:58:46.368080 ==
3464 00:58:46.368162 Dram Type= 6, Freq= 0, CH_1, rank 1
3465 00:58:46.368244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 00:58:46.368326 ==
3467 00:58:46.368407 RX Vref Scan: 0
3468 00:58:46.368487
3469 00:58:46.368568 RX Vref 0 -> 0, step: 1
3470 00:58:46.368649
3471 00:58:46.368730 RX Delay -40 -> 252, step: 8
3472 00:58:46.368812 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3473 00:58:46.368893 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3474 00:58:46.368975 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3475 00:58:46.369057 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3476 00:58:46.369138 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3477 00:58:46.369220 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3478 00:58:46.369354 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3479 00:58:46.369437 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3480 00:58:46.369519 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3481 00:58:46.369601 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3482 00:58:46.369683 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3483 00:58:46.369764 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3484 00:58:46.369846 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3485 00:58:46.369927 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3486 00:58:46.370009 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3487 00:58:46.370090 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3488 00:58:46.370172 ==
3489 00:58:46.370257 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 00:58:46.370319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 00:58:46.370373 ==
3492 00:58:46.370426 DQS Delay:
3493 00:58:46.370478 DQS0 = 0, DQS1 = 0
3494 00:58:46.370530 DQM Delay:
3495 00:58:46.370582 DQM0 = 115, DQM1 = 111
3496 00:58:46.370634 DQ Delay:
3497 00:58:46.370686 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3498 00:58:46.370739 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3499 00:58:46.370790 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3500 00:58:46.370843 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3501 00:58:46.370895
3502 00:58:46.370947
3503 00:58:46.370999 ==
3504 00:58:46.371243 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 00:58:46.371316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 00:58:46.371373 ==
3507 00:58:46.371426
3508 00:58:46.371479
3509 00:58:46.371530 TX Vref Scan disable
3510 00:58:46.371582 == TX Byte 0 ==
3511 00:58:46.371634 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3512 00:58:46.371686 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3513 00:58:46.371738 == TX Byte 1 ==
3514 00:58:46.371790 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3515 00:58:46.371842 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3516 00:58:46.371894 ==
3517 00:58:46.371947 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 00:58:46.371999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 00:58:46.372051 ==
3520 00:58:46.372103 TX Vref=22, minBit 9, minWin=24, winSum=418
3521 00:58:46.372155 TX Vref=24, minBit 1, minWin=26, winSum=428
3522 00:58:46.372207 TX Vref=26, minBit 1, minWin=26, winSum=427
3523 00:58:46.372260 TX Vref=28, minBit 9, minWin=25, winSum=431
3524 00:58:46.372312 TX Vref=30, minBit 2, minWin=26, winSum=434
3525 00:58:46.372364 TX Vref=32, minBit 3, minWin=26, winSum=430
3526 00:58:46.372417 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 30
3527 00:58:46.372469
3528 00:58:46.372520 Final TX Range 1 Vref 30
3529 00:58:46.372574
3530 00:58:46.372625 ==
3531 00:58:46.372677 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 00:58:46.372728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 00:58:46.372780 ==
3534 00:58:46.372832
3535 00:58:46.372883
3536 00:58:46.372935 TX Vref Scan disable
3537 00:58:46.372986 == TX Byte 0 ==
3538 00:58:46.373038 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3539 00:58:46.373090 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3540 00:58:46.373143 == TX Byte 1 ==
3541 00:58:46.373195 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3542 00:58:46.373247 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3543 00:58:46.373358
3544 00:58:46.373445 [DATLAT]
3545 00:58:46.373500 Freq=1200, CH1 RK1
3546 00:58:46.373555
3547 00:58:46.373607 DATLAT Default: 0xd
3548 00:58:46.373659 0, 0xFFFF, sum = 0
3549 00:58:46.373713 1, 0xFFFF, sum = 0
3550 00:58:46.373767 2, 0xFFFF, sum = 0
3551 00:58:46.373819 3, 0xFFFF, sum = 0
3552 00:58:46.373872 4, 0xFFFF, sum = 0
3553 00:58:46.373925 5, 0xFFFF, sum = 0
3554 00:58:46.373978 6, 0xFFFF, sum = 0
3555 00:58:46.374031 7, 0xFFFF, sum = 0
3556 00:58:46.374084 8, 0xFFFF, sum = 0
3557 00:58:46.374136 9, 0xFFFF, sum = 0
3558 00:58:46.374189 10, 0xFFFF, sum = 0
3559 00:58:46.374242 11, 0xFFFF, sum = 0
3560 00:58:46.374296 12, 0x0, sum = 1
3561 00:58:46.374349 13, 0x0, sum = 2
3562 00:58:46.374401 14, 0x0, sum = 3
3563 00:58:46.374454 15, 0x0, sum = 4
3564 00:58:46.374506 best_step = 13
3565 00:58:46.374558
3566 00:58:46.374610 ==
3567 00:58:46.374662 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 00:58:46.374714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 00:58:46.374766 ==
3570 00:58:46.374819 RX Vref Scan: 0
3571 00:58:46.374870
3572 00:58:46.374922 RX Vref 0 -> 0, step: 1
3573 00:58:46.374973
3574 00:58:46.375026 RX Delay -13 -> 252, step: 4
3575 00:58:46.375078 iDelay=191, Bit 0, Center 118 (51 ~ 186) 136
3576 00:58:46.375130 iDelay=191, Bit 1, Center 112 (43 ~ 182) 140
3577 00:58:46.375182 iDelay=191, Bit 2, Center 106 (39 ~ 174) 136
3578 00:58:46.375235 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3579 00:58:46.375287 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3580 00:58:46.375339 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3581 00:58:46.375391 iDelay=191, Bit 6, Center 120 (51 ~ 190) 140
3582 00:58:46.375443 iDelay=191, Bit 7, Center 114 (47 ~ 182) 136
3583 00:58:46.375495 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3584 00:58:46.375547 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3585 00:58:46.375599 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3586 00:58:46.375650 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3587 00:58:46.375702 iDelay=191, Bit 12, Center 120 (59 ~ 182) 124
3588 00:58:46.375754 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3589 00:58:46.375806 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3590 00:58:46.375857 iDelay=191, Bit 15, Center 122 (59 ~ 186) 128
3591 00:58:46.375909 ==
3592 00:58:46.375961 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 00:58:46.376013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 00:58:46.376065 ==
3595 00:58:46.376117 DQS Delay:
3596 00:58:46.376169 DQS0 = 0, DQS1 = 0
3597 00:58:46.376221 DQM Delay:
3598 00:58:46.376272 DQM0 = 114, DQM1 = 112
3599 00:58:46.376324 DQ Delay:
3600 00:58:46.376376 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3601 00:58:46.376428 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =114
3602 00:58:46.376480 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3603 00:58:46.376532 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3604 00:58:46.376584
3605 00:58:46.376635
3606 00:58:46.376687 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3607 00:58:46.376740 CH1 RK1: MR19=304, MR18=F709
3608 00:58:46.376792 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3609 00:58:46.376845 [RxdqsGatingPostProcess] freq 1200
3610 00:58:46.376897 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3611 00:58:46.376949 best DQS0 dly(2T, 0.5T) = (0, 11)
3612 00:58:46.377002 best DQS1 dly(2T, 0.5T) = (0, 11)
3613 00:58:46.377054 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3614 00:58:46.377106 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3615 00:58:46.377158 best DQS0 dly(2T, 0.5T) = (0, 11)
3616 00:58:46.377210 best DQS1 dly(2T, 0.5T) = (0, 11)
3617 00:58:46.377288 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3618 00:58:46.377356 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3619 00:58:46.377408 Pre-setting of DQS Precalculation
3620 00:58:46.377461 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3621 00:58:46.377513 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3622 00:58:46.377566 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3623 00:58:46.377619
3624 00:58:46.377670
3625 00:58:46.377722 [Calibration Summary] 2400 Mbps
3626 00:58:46.377774 CH 0, Rank 0
3627 00:58:46.377826 SW Impedance : PASS
3628 00:58:46.377878 DUTY Scan : NO K
3629 00:58:46.377929 ZQ Calibration : PASS
3630 00:58:46.377981 Jitter Meter : NO K
3631 00:58:46.378033 CBT Training : PASS
3632 00:58:46.378084 Write leveling : PASS
3633 00:58:46.378135 RX DQS gating : PASS
3634 00:58:46.378187 RX DQ/DQS(RDDQC) : PASS
3635 00:58:46.378238 TX DQ/DQS : PASS
3636 00:58:46.378291 RX DATLAT : PASS
3637 00:58:46.378342 RX DQ/DQS(Engine): PASS
3638 00:58:46.378394 TX OE : NO K
3639 00:58:46.378446 All Pass.
3640 00:58:46.378498
3641 00:58:46.378549 CH 0, Rank 1
3642 00:58:46.378600 SW Impedance : PASS
3643 00:58:46.378652 DUTY Scan : NO K
3644 00:58:46.378704 ZQ Calibration : PASS
3645 00:58:46.378948 Jitter Meter : NO K
3646 00:58:46.379006 CBT Training : PASS
3647 00:58:46.379060 Write leveling : PASS
3648 00:58:46.379113 RX DQS gating : PASS
3649 00:58:46.379166 RX DQ/DQS(RDDQC) : PASS
3650 00:58:46.379218 TX DQ/DQS : PASS
3651 00:58:46.379270 RX DATLAT : PASS
3652 00:58:46.379322 RX DQ/DQS(Engine): PASS
3653 00:58:46.379374 TX OE : NO K
3654 00:58:46.379426 All Pass.
3655 00:58:46.379478
3656 00:58:46.379529 CH 1, Rank 0
3657 00:58:46.379581 SW Impedance : PASS
3658 00:58:46.379634 DUTY Scan : NO K
3659 00:58:46.379685 ZQ Calibration : PASS
3660 00:58:46.379737 Jitter Meter : NO K
3661 00:58:46.379788 CBT Training : PASS
3662 00:58:46.379840 Write leveling : PASS
3663 00:58:46.379892 RX DQS gating : PASS
3664 00:58:46.379943 RX DQ/DQS(RDDQC) : PASS
3665 00:58:46.379995 TX DQ/DQS : PASS
3666 00:58:46.380047 RX DATLAT : PASS
3667 00:58:46.380098 RX DQ/DQS(Engine): PASS
3668 00:58:46.380150 TX OE : NO K
3669 00:58:46.380202 All Pass.
3670 00:58:46.380253
3671 00:58:46.380305 CH 1, Rank 1
3672 00:58:46.380356 SW Impedance : PASS
3673 00:58:46.380407 DUTY Scan : NO K
3674 00:58:46.380458 ZQ Calibration : PASS
3675 00:58:46.380510 Jitter Meter : NO K
3676 00:58:46.380561 CBT Training : PASS
3677 00:58:46.380612 Write leveling : PASS
3678 00:58:46.380664 RX DQS gating : PASS
3679 00:58:46.380716 RX DQ/DQS(RDDQC) : PASS
3680 00:58:46.380767 TX DQ/DQS : PASS
3681 00:58:46.380819 RX DATLAT : PASS
3682 00:58:46.380871 RX DQ/DQS(Engine): PASS
3683 00:58:46.380922 TX OE : NO K
3684 00:58:46.380974 All Pass.
3685 00:58:46.381025
3686 00:58:46.381077 DramC Write-DBI off
3687 00:58:46.381129 PER_BANK_REFRESH: Hybrid Mode
3688 00:58:46.381181 TX_TRACKING: ON
3689 00:58:46.381233 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3690 00:58:46.381320 [FAST_K] Save calibration result to emmc
3691 00:58:46.381386 dramc_set_vcore_voltage set vcore to 650000
3692 00:58:46.381439 Read voltage for 600, 5
3693 00:58:46.381490 Vio18 = 0
3694 00:58:46.381542 Vcore = 650000
3695 00:58:46.381593 Vdram = 0
3696 00:58:46.381646 Vddq = 0
3697 00:58:46.381697 Vmddr = 0
3698 00:58:46.381749 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3699 00:58:46.381801 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3700 00:58:46.381854 MEM_TYPE=3, freq_sel=19
3701 00:58:46.381906 sv_algorithm_assistance_LP4_1600
3702 00:58:46.381958 ============ PULL DRAM RESETB DOWN ============
3703 00:58:46.382011 ========== PULL DRAM RESETB DOWN end =========
3704 00:58:46.382064 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3705 00:58:46.382116 ===================================
3706 00:58:46.382169 LPDDR4 DRAM CONFIGURATION
3707 00:58:46.382220 ===================================
3708 00:58:46.382273 EX_ROW_EN[0] = 0x0
3709 00:58:46.382324 EX_ROW_EN[1] = 0x0
3710 00:58:46.382376 LP4Y_EN = 0x0
3711 00:58:46.382428 WORK_FSP = 0x0
3712 00:58:46.382480 WL = 0x2
3713 00:58:46.382531 RL = 0x2
3714 00:58:46.382583 BL = 0x2
3715 00:58:46.382635 RPST = 0x0
3716 00:58:46.382686 RD_PRE = 0x0
3717 00:58:46.382738 WR_PRE = 0x1
3718 00:58:46.382790 WR_PST = 0x0
3719 00:58:46.382841 DBI_WR = 0x0
3720 00:58:46.382893 DBI_RD = 0x0
3721 00:58:46.382944 OTF = 0x1
3722 00:58:46.382996 ===================================
3723 00:58:46.383048 ===================================
3724 00:58:46.383100 ANA top config
3725 00:58:46.383152 ===================================
3726 00:58:46.383204 DLL_ASYNC_EN = 0
3727 00:58:46.383256 ALL_SLAVE_EN = 1
3728 00:58:46.383308 NEW_RANK_MODE = 1
3729 00:58:46.383360 DLL_IDLE_MODE = 1
3730 00:58:46.383412 LP45_APHY_COMB_EN = 1
3731 00:58:46.383464 TX_ODT_DIS = 1
3732 00:58:46.383516 NEW_8X_MODE = 1
3733 00:58:46.383568 ===================================
3734 00:58:46.383620 ===================================
3735 00:58:46.383672 data_rate = 1200
3736 00:58:46.383724 CKR = 1
3737 00:58:46.383776 DQ_P2S_RATIO = 8
3738 00:58:46.383828 ===================================
3739 00:58:46.383881 CA_P2S_RATIO = 8
3740 00:58:46.383933 DQ_CA_OPEN = 0
3741 00:58:46.383984 DQ_SEMI_OPEN = 0
3742 00:58:46.384036 CA_SEMI_OPEN = 0
3743 00:58:46.384088 CA_FULL_RATE = 0
3744 00:58:46.384139 DQ_CKDIV4_EN = 1
3745 00:58:46.384191 CA_CKDIV4_EN = 1
3746 00:58:46.384243 CA_PREDIV_EN = 0
3747 00:58:46.384296 PH8_DLY = 0
3748 00:58:46.384348 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3749 00:58:46.384400 DQ_AAMCK_DIV = 4
3750 00:58:46.384451 CA_AAMCK_DIV = 4
3751 00:58:46.384503 CA_ADMCK_DIV = 4
3752 00:58:46.384554 DQ_TRACK_CA_EN = 0
3753 00:58:46.384606 CA_PICK = 600
3754 00:58:46.384657 CA_MCKIO = 600
3755 00:58:46.384709 MCKIO_SEMI = 0
3756 00:58:46.384760 PLL_FREQ = 2288
3757 00:58:46.384812 DQ_UI_PI_RATIO = 32
3758 00:58:46.384864 CA_UI_PI_RATIO = 0
3759 00:58:46.384915 ===================================
3760 00:58:46.384968 ===================================
3761 00:58:46.385020 memory_type:LPDDR4
3762 00:58:46.385071 GP_NUM : 10
3763 00:58:46.385122 SRAM_EN : 1
3764 00:58:46.385174 MD32_EN : 0
3765 00:58:46.385226 ===================================
3766 00:58:46.385308 [ANA_INIT] >>>>>>>>>>>>>>
3767 00:58:46.385373 <<<<<< [CONFIGURE PHASE]: ANA_TX
3768 00:58:46.385426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3769 00:58:46.385478 ===================================
3770 00:58:46.385531 data_rate = 1200,PCW = 0X5800
3771 00:58:46.385583 ===================================
3772 00:58:46.385635 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3773 00:58:46.385688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3774 00:58:46.385740 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3775 00:58:46.385793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3776 00:58:46.385846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3777 00:58:46.385898 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3778 00:58:46.385950 [ANA_INIT] flow start
3779 00:58:46.386002 [ANA_INIT] PLL >>>>>>>>
3780 00:58:46.386053 [ANA_INIT] PLL <<<<<<<<
3781 00:58:46.386105 [ANA_INIT] MIDPI >>>>>>>>
3782 00:58:46.386156 [ANA_INIT] MIDPI <<<<<<<<
3783 00:58:46.386207 [ANA_INIT] DLL >>>>>>>>
3784 00:58:46.386258 [ANA_INIT] flow end
3785 00:58:46.386498 ============ LP4 DIFF to SE enter ============
3786 00:58:46.386557 ============ LP4 DIFF to SE exit ============
3787 00:58:46.386611 [ANA_INIT] <<<<<<<<<<<<<
3788 00:58:46.386664 [Flow] Enable top DCM control >>>>>
3789 00:58:46.386717 [Flow] Enable top DCM control <<<<<
3790 00:58:46.386769 Enable DLL master slave shuffle
3791 00:58:46.386822 ==============================================================
3792 00:58:46.386874 Gating Mode config
3793 00:58:46.386926 ==============================================================
3794 00:58:46.386979 Config description:
3795 00:58:46.387031 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3796 00:58:46.387085 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3797 00:58:46.387137 SELPH_MODE 0: By rank 1: By Phase
3798 00:58:46.387190 ==============================================================
3799 00:58:46.387243 GAT_TRACK_EN = 1
3800 00:58:46.387295 RX_GATING_MODE = 2
3801 00:58:46.387347 RX_GATING_TRACK_MODE = 2
3802 00:58:46.387399 SELPH_MODE = 1
3803 00:58:46.387451 PICG_EARLY_EN = 1
3804 00:58:46.387503 VALID_LAT_VALUE = 1
3805 00:58:46.387555 ==============================================================
3806 00:58:46.387607 Enter into Gating configuration >>>>
3807 00:58:46.388995 Exit from Gating configuration <<<<
3808 00:58:46.391761 Enter into DVFS_PRE_config >>>>>
3809 00:58:46.404764 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3810 00:58:46.404849 Exit from DVFS_PRE_config <<<<<
3811 00:58:46.408440 Enter into PICG configuration >>>>
3812 00:58:46.411549 Exit from PICG configuration <<<<
3813 00:58:46.414843 [RX_INPUT] configuration >>>>>
3814 00:58:46.417967 [RX_INPUT] configuration <<<<<
3815 00:58:46.425002 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3816 00:58:46.428215 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3817 00:58:46.434272 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3818 00:58:46.440614 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3819 00:58:46.447685 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3820 00:58:46.454090 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3821 00:58:46.457240 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3822 00:58:46.461095 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3823 00:58:46.467201 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3824 00:58:46.470511 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3825 00:58:46.474112 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3826 00:58:46.477189 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3827 00:58:46.480380 ===================================
3828 00:58:46.483704 LPDDR4 DRAM CONFIGURATION
3829 00:58:46.487075 ===================================
3830 00:58:46.490259 EX_ROW_EN[0] = 0x0
3831 00:58:46.490335 EX_ROW_EN[1] = 0x0
3832 00:58:46.493629 LP4Y_EN = 0x0
3833 00:58:46.493711 WORK_FSP = 0x0
3834 00:58:46.497180 WL = 0x2
3835 00:58:46.497316 RL = 0x2
3836 00:58:46.500261 BL = 0x2
3837 00:58:46.500332 RPST = 0x0
3838 00:58:46.503791 RD_PRE = 0x0
3839 00:58:46.503866 WR_PRE = 0x1
3840 00:58:46.506909 WR_PST = 0x0
3841 00:58:46.510213 DBI_WR = 0x0
3842 00:58:46.510290 DBI_RD = 0x0
3843 00:58:46.513555 OTF = 0x1
3844 00:58:46.516805 ===================================
3845 00:58:46.520063 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3846 00:58:46.523051 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3847 00:58:46.526359 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3848 00:58:46.529717 ===================================
3849 00:58:46.532826 LPDDR4 DRAM CONFIGURATION
3850 00:58:46.536232 ===================================
3851 00:58:46.539342 EX_ROW_EN[0] = 0x10
3852 00:58:46.539423 EX_ROW_EN[1] = 0x0
3853 00:58:46.542704 LP4Y_EN = 0x0
3854 00:58:46.542784 WORK_FSP = 0x0
3855 00:58:46.546030 WL = 0x2
3856 00:58:46.546116 RL = 0x2
3857 00:58:46.550039 BL = 0x2
3858 00:58:46.552790 RPST = 0x0
3859 00:58:46.552863 RD_PRE = 0x0
3860 00:58:46.556025 WR_PRE = 0x1
3861 00:58:46.556106 WR_PST = 0x0
3862 00:58:46.559472 DBI_WR = 0x0
3863 00:58:46.559547 DBI_RD = 0x0
3864 00:58:46.562548 OTF = 0x1
3865 00:58:46.566000 ===================================
3866 00:58:46.569460 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3867 00:58:46.574811 nWR fixed to 30
3868 00:58:46.578237 [ModeRegInit_LP4] CH0 RK0
3869 00:58:46.578315 [ModeRegInit_LP4] CH0 RK1
3870 00:58:46.581732 [ModeRegInit_LP4] CH1 RK0
3871 00:58:46.585007 [ModeRegInit_LP4] CH1 RK1
3872 00:58:46.585087 match AC timing 17
3873 00:58:46.591474 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3874 00:58:46.594387 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3875 00:58:46.598876 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3876 00:58:46.604262 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3877 00:58:46.607649 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3878 00:58:46.607734 ==
3879 00:58:46.611416 Dram Type= 6, Freq= 0, CH_0, rank 0
3880 00:58:46.614502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3881 00:58:46.614588 ==
3882 00:58:46.621114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3883 00:58:46.627354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3884 00:58:46.630597 [CA 0] Center 36 (6~67) winsize 62
3885 00:58:46.633950 [CA 1] Center 36 (6~66) winsize 61
3886 00:58:46.637324 [CA 2] Center 34 (3~65) winsize 63
3887 00:58:46.640834 [CA 3] Center 34 (4~65) winsize 62
3888 00:58:46.643864 [CA 4] Center 33 (3~64) winsize 62
3889 00:58:46.647058 [CA 5] Center 33 (3~64) winsize 62
3890 00:58:46.647141
3891 00:58:46.650570 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3892 00:58:46.650655
3893 00:58:46.653844 [CATrainingPosCal] consider 1 rank data
3894 00:58:46.656920 u2DelayCellTimex100 = 270/100 ps
3895 00:58:46.661410 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3896 00:58:46.663699 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3897 00:58:46.670208 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3898 00:58:46.673443 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3899 00:58:46.676883 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3900 00:58:46.680381 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3901 00:58:46.680464
3902 00:58:46.683715 CA PerBit enable=1, Macro0, CA PI delay=33
3903 00:58:46.683798
3904 00:58:46.686550 [CBTSetCACLKResult] CA Dly = 33
3905 00:58:46.686645 CS Dly: 4 (0~35)
3906 00:58:46.690579 ==
3907 00:58:46.690661 Dram Type= 6, Freq= 0, CH_0, rank 1
3908 00:58:46.696503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3909 00:58:46.696586 ==
3910 00:58:46.699702 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3911 00:58:46.706210 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3912 00:58:46.710162 [CA 0] Center 36 (6~67) winsize 62
3913 00:58:46.713696 [CA 1] Center 36 (6~67) winsize 62
3914 00:58:46.716897 [CA 2] Center 34 (4~65) winsize 62
3915 00:58:46.720102 [CA 3] Center 34 (4~65) winsize 62
3916 00:58:46.723332 [CA 4] Center 33 (3~64) winsize 62
3917 00:58:46.727174 [CA 5] Center 33 (3~64) winsize 62
3918 00:58:46.727248
3919 00:58:46.730466 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3920 00:58:46.730548
3921 00:58:46.733997 [CATrainingPosCal] consider 2 rank data
3922 00:58:46.737488 u2DelayCellTimex100 = 270/100 ps
3923 00:58:46.739896 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3924 00:58:46.746492 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3925 00:58:46.750431 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3926 00:58:46.753181 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3927 00:58:46.756586 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3928 00:58:46.759936 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3929 00:58:46.760017
3930 00:58:46.763549 CA PerBit enable=1, Macro0, CA PI delay=33
3931 00:58:46.763630
3932 00:58:46.766503 [CBTSetCACLKResult] CA Dly = 33
3933 00:58:46.766584 CS Dly: 5 (0~37)
3934 00:58:46.769622
3935 00:58:46.773093 ----->DramcWriteLeveling(PI) begin...
3936 00:58:46.773203 ==
3937 00:58:46.776423 Dram Type= 6, Freq= 0, CH_0, rank 0
3938 00:58:46.779730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 00:58:46.779815 ==
3940 00:58:46.782885 Write leveling (Byte 0): 31 => 31
3941 00:58:46.786246 Write leveling (Byte 1): 30 => 30
3942 00:58:46.789754 DramcWriteLeveling(PI) end<-----
3943 00:58:46.789838
3944 00:58:46.789921 ==
3945 00:58:46.793114 Dram Type= 6, Freq= 0, CH_0, rank 0
3946 00:58:46.796487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3947 00:58:46.796572 ==
3948 00:58:46.799551 [Gating] SW mode calibration
3949 00:58:46.806332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3950 00:58:46.812541 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3951 00:58:46.816467 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3952 00:58:46.819856 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3953 00:58:46.825815 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3954 00:58:46.829142 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
3955 00:58:46.832346 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
3956 00:58:46.839049 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3957 00:58:46.842491 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3958 00:58:46.845825 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3959 00:58:46.852501 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3960 00:58:46.855375 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3961 00:58:46.858581 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3962 00:58:46.865163 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
3963 00:58:46.868880 0 10 16 | B1->B0 | 3d3d 4141 | 1 0 | (0 0) (0 0)
3964 00:58:46.872083 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3965 00:58:46.878855 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3966 00:58:46.881686 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3967 00:58:46.884824 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3968 00:58:46.891631 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3969 00:58:46.894992 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3970 00:58:46.898635 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3971 00:58:46.904859 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3972 00:58:46.908995 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3973 00:58:46.911687 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3974 00:58:46.918370 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3975 00:58:46.921682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3976 00:58:46.925245 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3977 00:58:46.931450 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3978 00:58:46.934524 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 00:58:46.937788 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 00:58:46.944799 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 00:58:46.948451 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 00:58:46.951322 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 00:58:46.957564 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 00:58:46.961336 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 00:58:46.964102 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 00:58:46.970721 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3987 00:58:46.973868 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3988 00:58:46.977653 Total UI for P1: 0, mck2ui 16
3989 00:58:46.980810 best dqsien dly found for B0: ( 0, 13, 12)
3990 00:58:46.983858 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 00:58:46.987869 Total UI for P1: 0, mck2ui 16
3992 00:58:46.990549 best dqsien dly found for B1: ( 0, 13, 16)
3993 00:58:46.993821 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
3994 00:58:47.000617 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
3995 00:58:47.000701
3996 00:58:47.003466 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
3997 00:58:47.006685 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
3998 00:58:47.010219 [Gating] SW calibration Done
3999 00:58:47.010303 ==
4000 00:58:47.013529 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 00:58:47.016871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 00:58:47.016953 ==
4003 00:58:47.019846 RX Vref Scan: 0
4004 00:58:47.019928
4005 00:58:47.019995 RX Vref 0 -> 0, step: 1
4006 00:58:47.020056
4007 00:58:47.023456 RX Delay -230 -> 252, step: 16
4008 00:58:47.027441 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4009 00:58:47.032945 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4010 00:58:47.036262 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4011 00:58:47.039659 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4012 00:58:47.043101 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4013 00:58:47.049450 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4014 00:58:47.052927 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4015 00:58:47.056844 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4016 00:58:47.059691 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4017 00:58:47.066225 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4018 00:58:47.069293 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4019 00:58:47.072816 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4020 00:58:47.075724 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4021 00:58:47.082556 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4022 00:58:47.085779 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4023 00:58:47.089114 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4024 00:58:47.089198 ==
4025 00:58:47.092658 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 00:58:47.095783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 00:58:47.099368 ==
4028 00:58:47.099452 DQS Delay:
4029 00:58:47.099536 DQS0 = 0, DQS1 = 0
4030 00:58:47.102287 DQM Delay:
4031 00:58:47.102371 DQM0 = 43, DQM1 = 32
4032 00:58:47.105452 DQ Delay:
4033 00:58:47.108587 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4034 00:58:47.108671 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4035 00:58:47.112123 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4036 00:58:47.115145 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =33
4037 00:58:47.118794
4038 00:58:47.118878
4039 00:58:47.118962 ==
4040 00:58:47.121877 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 00:58:47.125197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 00:58:47.125318 ==
4043 00:58:47.125403
4044 00:58:47.125482
4045 00:58:47.128837 TX Vref Scan disable
4046 00:58:47.128921 == TX Byte 0 ==
4047 00:58:47.135081 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4048 00:58:47.138630 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4049 00:58:47.138714 == TX Byte 1 ==
4050 00:58:47.144804 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4051 00:58:47.148373 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4052 00:58:47.148456 ==
4053 00:58:47.151496 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 00:58:47.155157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 00:58:47.155240 ==
4056 00:58:47.155306
4057 00:58:47.158029
4058 00:58:47.158111 TX Vref Scan disable
4059 00:58:47.162043 == TX Byte 0 ==
4060 00:58:47.164671 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4061 00:58:47.171365 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4062 00:58:47.171448 == TX Byte 1 ==
4063 00:58:47.174776 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4064 00:58:47.181155 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4065 00:58:47.181289
4066 00:58:47.181373 [DATLAT]
4067 00:58:47.181436 Freq=600, CH0 RK0
4068 00:58:47.181496
4069 00:58:47.184924 DATLAT Default: 0x9
4070 00:58:47.188224 0, 0xFFFF, sum = 0
4071 00:58:47.188309 1, 0xFFFF, sum = 0
4072 00:58:47.191201 2, 0xFFFF, sum = 0
4073 00:58:47.191284 3, 0xFFFF, sum = 0
4074 00:58:47.194110 4, 0xFFFF, sum = 0
4075 00:58:47.194194 5, 0xFFFF, sum = 0
4076 00:58:47.197668 6, 0xFFFF, sum = 0
4077 00:58:47.197760 7, 0xFFFF, sum = 0
4078 00:58:47.201072 8, 0x0, sum = 1
4079 00:58:47.201156 9, 0x0, sum = 2
4080 00:58:47.204531 10, 0x0, sum = 3
4081 00:58:47.204615 11, 0x0, sum = 4
4082 00:58:47.204683 best_step = 9
4083 00:58:47.204768
4084 00:58:47.207566 ==
4085 00:58:47.211066 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 00:58:47.213945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 00:58:47.214028 ==
4088 00:58:47.214094 RX Vref Scan: 1
4089 00:58:47.214156
4090 00:58:47.217399 RX Vref 0 -> 0, step: 1
4091 00:58:47.217481
4092 00:58:47.221116 RX Delay -195 -> 252, step: 8
4093 00:58:47.221198
4094 00:58:47.224649 Set Vref, RX VrefLevel [Byte0]: 55
4095 00:58:47.227381 [Byte1]: 58
4096 00:58:47.230469
4097 00:58:47.230551 Final RX Vref Byte 0 = 55 to rank0
4098 00:58:47.234118 Final RX Vref Byte 1 = 58 to rank0
4099 00:58:47.237053 Final RX Vref Byte 0 = 55 to rank1
4100 00:58:47.240368 Final RX Vref Byte 1 = 58 to rank1==
4101 00:58:47.243814 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 00:58:47.250029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 00:58:47.250115 ==
4104 00:58:47.250182 DQS Delay:
4105 00:58:47.253398 DQS0 = 0, DQS1 = 0
4106 00:58:47.253481 DQM Delay:
4107 00:58:47.253548 DQM0 = 41, DQM1 = 33
4108 00:58:47.256807 DQ Delay:
4109 00:58:47.259880 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4110 00:58:47.263359 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4111 00:58:47.266661 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4112 00:58:47.270461 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4113 00:58:47.270544
4114 00:58:47.270610
4115 00:58:47.276949 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4116 00:58:47.279885 CH0 RK0: MR19=808, MR18=4D45
4117 00:58:47.286964 CH0_RK0: MR19=0x808, MR18=0x4D45, DQSOSC=395, MR23=63, INC=168, DEC=112
4118 00:58:47.287078
4119 00:58:47.289833 ----->DramcWriteLeveling(PI) begin...
4120 00:58:47.289918 ==
4121 00:58:47.292978 Dram Type= 6, Freq= 0, CH_0, rank 1
4122 00:58:47.296288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 00:58:47.296373 ==
4124 00:58:47.300260 Write leveling (Byte 0): 33 => 33
4125 00:58:47.303269 Write leveling (Byte 1): 31 => 31
4126 00:58:47.306045 DramcWriteLeveling(PI) end<-----
4127 00:58:47.306128
4128 00:58:47.306194 ==
4129 00:58:47.309644 Dram Type= 6, Freq= 0, CH_0, rank 1
4130 00:58:47.312756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 00:58:47.316110 ==
4132 00:58:47.316193 [Gating] SW mode calibration
4133 00:58:47.325991 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4134 00:58:47.329119 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4135 00:58:47.332311 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4136 00:58:47.338941 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4137 00:58:47.342469 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4138 00:58:47.345520 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
4139 00:58:47.352096 0 9 16 | B1->B0 | 2e2e 2424 | 1 1 | (1 0) (1 0)
4140 00:58:47.355535 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4141 00:58:47.358927 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4142 00:58:47.365233 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4143 00:58:47.368663 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4144 00:58:47.371968 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4145 00:58:47.378406 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4146 00:58:47.381926 0 10 12 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
4147 00:58:47.384843 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4148 00:58:47.391429 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4149 00:58:47.395209 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4150 00:58:47.401501 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4151 00:58:47.404569 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4152 00:58:47.408231 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4153 00:58:47.414438 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4154 00:58:47.417834 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4155 00:58:47.421135 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4156 00:58:47.427976 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4157 00:58:47.430923 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4158 00:58:47.434504 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4159 00:58:47.440889 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4160 00:58:47.444195 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4161 00:58:47.447759 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4162 00:58:47.454045 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 00:58:47.457372 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 00:58:47.460796 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 00:58:47.467129 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 00:58:47.470864 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 00:58:47.473772 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 00:58:47.480227 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 00:58:47.483518 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 00:58:47.487340 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4171 00:58:47.493828 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 00:58:47.493908 Total UI for P1: 0, mck2ui 16
4173 00:58:47.499978 best dqsien dly found for B0: ( 0, 13, 12)
4174 00:58:47.500082 Total UI for P1: 0, mck2ui 16
4175 00:58:47.503674 best dqsien dly found for B1: ( 0, 13, 12)
4176 00:58:47.509742 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4177 00:58:47.513379 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4178 00:58:47.513465
4179 00:58:47.516464 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4180 00:58:47.520031 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4181 00:58:47.522881 [Gating] SW calibration Done
4182 00:58:47.522969 ==
4183 00:58:47.526499 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 00:58:47.530032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 00:58:47.530112 ==
4186 00:58:47.532979 RX Vref Scan: 0
4187 00:58:47.533079
4188 00:58:47.533168 RX Vref 0 -> 0, step: 1
4189 00:58:47.533278
4190 00:58:47.536526 RX Delay -230 -> 252, step: 16
4191 00:58:47.542735 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4192 00:58:47.545903 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4193 00:58:47.549135 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4194 00:58:47.552539 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4195 00:58:47.559603 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4196 00:58:47.562651 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4197 00:58:47.565704 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4198 00:58:47.568905 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4199 00:58:47.572314 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4200 00:58:47.579383 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4201 00:58:47.582335 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4202 00:58:47.585508 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4203 00:58:47.589516 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4204 00:58:47.595634 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4205 00:58:47.598521 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4206 00:58:47.602693 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4207 00:58:47.602795 ==
4208 00:58:47.605520 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 00:58:47.611935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 00:58:47.612022 ==
4211 00:58:47.612090 DQS Delay:
4212 00:58:47.615718 DQS0 = 0, DQS1 = 0
4213 00:58:47.615802 DQM Delay:
4214 00:58:47.615870 DQM0 = 42, DQM1 = 34
4215 00:58:47.618666 DQ Delay:
4216 00:58:47.621657 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4217 00:58:47.624929 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4218 00:58:47.628126 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4219 00:58:47.631835 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4220 00:58:47.631938
4221 00:58:47.632028
4222 00:58:47.632129 ==
4223 00:58:47.635724 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 00:58:47.638800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 00:58:47.638884 ==
4226 00:58:47.638948
4227 00:58:47.639007
4228 00:58:47.641507 TX Vref Scan disable
4229 00:58:47.644791 == TX Byte 0 ==
4230 00:58:47.648414 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4231 00:58:47.651275 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4232 00:58:47.655000 == TX Byte 1 ==
4233 00:58:47.657940 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4234 00:58:47.661062 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4235 00:58:47.661176 ==
4236 00:58:47.664566 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 00:58:47.667942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 00:58:47.671685 ==
4239 00:58:47.671795
4240 00:58:47.671887
4241 00:58:47.671987 TX Vref Scan disable
4242 00:58:47.675061 == TX Byte 0 ==
4243 00:58:47.678656 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4244 00:58:47.685313 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4245 00:58:47.685433 == TX Byte 1 ==
4246 00:58:47.688209 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4247 00:58:47.695124 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4248 00:58:47.695231
4249 00:58:47.695326 [DATLAT]
4250 00:58:47.695420 Freq=600, CH0 RK1
4251 00:58:47.695510
4252 00:58:47.698119 DATLAT Default: 0x9
4253 00:58:47.698275 0, 0xFFFF, sum = 0
4254 00:58:47.701574 1, 0xFFFF, sum = 0
4255 00:58:47.704951 2, 0xFFFF, sum = 0
4256 00:58:47.705067 3, 0xFFFF, sum = 0
4257 00:58:47.707796 4, 0xFFFF, sum = 0
4258 00:58:47.707903 5, 0xFFFF, sum = 0
4259 00:58:47.711101 6, 0xFFFF, sum = 0
4260 00:58:47.711210 7, 0xFFFF, sum = 0
4261 00:58:47.714654 8, 0x0, sum = 1
4262 00:58:47.714772 9, 0x0, sum = 2
4263 00:58:47.717988 10, 0x0, sum = 3
4264 00:58:47.718110 11, 0x0, sum = 4
4265 00:58:47.718206 best_step = 9
4266 00:58:47.718299
4267 00:58:47.720987 ==
4268 00:58:47.721085 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 00:58:47.728218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 00:58:47.728336 ==
4271 00:58:47.728404 RX Vref Scan: 0
4272 00:58:47.728467
4273 00:58:47.731292 RX Vref 0 -> 0, step: 1
4274 00:58:47.731404
4275 00:58:47.735225 RX Delay -195 -> 252, step: 8
4276 00:58:47.741877 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4277 00:58:47.744522 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4278 00:58:47.747547 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4279 00:58:47.750636 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4280 00:58:47.754140 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4281 00:58:47.760822 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4282 00:58:47.764575 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4283 00:58:47.767051 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4284 00:58:47.770487 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4285 00:58:47.777468 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4286 00:58:47.780650 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4287 00:58:47.783801 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4288 00:58:47.787130 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4289 00:58:47.794087 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4290 00:58:47.797057 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4291 00:58:47.800079 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4292 00:58:47.800185 ==
4293 00:58:47.803889 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 00:58:47.806811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 00:58:47.810154 ==
4296 00:58:47.810232 DQS Delay:
4297 00:58:47.810297 DQS0 = 0, DQS1 = 0
4298 00:58:47.814261 DQM Delay:
4299 00:58:47.814365 DQM0 = 40, DQM1 = 32
4300 00:58:47.816574 DQ Delay:
4301 00:58:47.820543 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4302 00:58:47.820617 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =44
4303 00:58:47.823219 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4304 00:58:47.830171 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4305 00:58:47.830252
4306 00:58:47.830316
4307 00:58:47.836715 [DQSOSCAuto] RK1, (LSB)MR18= 0x4340, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4308 00:58:47.840071 CH0 RK1: MR19=808, MR18=4340
4309 00:58:47.846316 CH0_RK1: MR19=0x808, MR18=0x4340, DQSOSC=397, MR23=63, INC=166, DEC=110
4310 00:58:47.849740 [RxdqsGatingPostProcess] freq 600
4311 00:58:47.853217 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4312 00:58:47.856603 Pre-setting of DQS Precalculation
4313 00:58:47.863466 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4314 00:58:47.863575 ==
4315 00:58:47.866666 Dram Type= 6, Freq= 0, CH_1, rank 0
4316 00:58:47.870130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 00:58:47.870227 ==
4318 00:58:47.876019 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4319 00:58:47.882515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4320 00:58:47.885716 [CA 0] Center 35 (5~66) winsize 62
4321 00:58:47.889246 [CA 1] Center 35 (5~66) winsize 62
4322 00:58:47.892651 [CA 2] Center 34 (4~65) winsize 62
4323 00:58:47.896119 [CA 3] Center 34 (4~65) winsize 62
4324 00:58:47.898825 [CA 4] Center 34 (4~65) winsize 62
4325 00:58:47.902176 [CA 5] Center 34 (3~65) winsize 63
4326 00:58:47.902276
4327 00:58:47.905575 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4328 00:58:47.905654
4329 00:58:47.909090 [CATrainingPosCal] consider 1 rank data
4330 00:58:47.912415 u2DelayCellTimex100 = 270/100 ps
4331 00:58:47.915339 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4332 00:58:47.919037 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4333 00:58:47.921871 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4334 00:58:47.925731 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4335 00:58:47.928933 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4336 00:58:47.931918 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4337 00:58:47.931989
4338 00:58:47.938689 CA PerBit enable=1, Macro0, CA PI delay=34
4339 00:58:47.938766
4340 00:58:47.941854 [CBTSetCACLKResult] CA Dly = 34
4341 00:58:47.941936 CS Dly: 4 (0~35)
4342 00:58:47.942003 ==
4343 00:58:47.944813 Dram Type= 6, Freq= 0, CH_1, rank 1
4344 00:58:47.948576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 00:58:47.948650 ==
4346 00:58:47.954920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4347 00:58:47.962231 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4348 00:58:47.964453 [CA 0] Center 36 (6~66) winsize 61
4349 00:58:47.967908 [CA 1] Center 35 (5~66) winsize 62
4350 00:58:47.971235 [CA 2] Center 34 (4~65) winsize 62
4351 00:58:47.975130 [CA 3] Center 34 (3~65) winsize 63
4352 00:58:47.978150 [CA 4] Center 34 (4~65) winsize 62
4353 00:58:47.981548 [CA 5] Center 34 (3~65) winsize 63
4354 00:58:47.981649
4355 00:58:47.984593 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4356 00:58:47.984668
4357 00:58:47.987535 [CATrainingPosCal] consider 2 rank data
4358 00:58:47.990977 u2DelayCellTimex100 = 270/100 ps
4359 00:58:47.994628 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4360 00:58:47.997398 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4361 00:58:48.002182 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4362 00:58:48.007298 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4363 00:58:48.010749 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4364 00:58:48.013875 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4365 00:58:48.013961
4366 00:58:48.017379 CA PerBit enable=1, Macro0, CA PI delay=34
4367 00:58:48.017462
4368 00:58:48.020876 [CBTSetCACLKResult] CA Dly = 34
4369 00:58:48.020973 CS Dly: 5 (0~37)
4370 00:58:48.021063
4371 00:58:48.023649 ----->DramcWriteLeveling(PI) begin...
4372 00:58:48.027073 ==
4373 00:58:48.030269 Dram Type= 6, Freq= 0, CH_1, rank 0
4374 00:58:48.033623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 00:58:48.033696 ==
4376 00:58:48.037203 Write leveling (Byte 0): 30 => 30
4377 00:58:48.040032 Write leveling (Byte 1): 28 => 28
4378 00:58:48.043914 DramcWriteLeveling(PI) end<-----
4379 00:58:48.043988
4380 00:58:48.044055 ==
4381 00:58:48.046627 Dram Type= 6, Freq= 0, CH_1, rank 0
4382 00:58:48.050049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 00:58:48.050128 ==
4384 00:58:48.053399 [Gating] SW mode calibration
4385 00:58:48.059960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4386 00:58:48.066618 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4387 00:58:48.070045 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4388 00:58:48.073406 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4389 00:58:48.080108 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4390 00:58:48.082822 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (0 1) (1 1)
4391 00:58:48.086452 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4392 00:58:48.092546 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4393 00:58:48.096299 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4394 00:58:48.099395 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4395 00:58:48.106393 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4396 00:58:48.110298 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4397 00:58:48.113073 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4398 00:58:48.119690 0 10 12 | B1->B0 | 3232 3636 | 1 1 | (0 0) (1 1)
4399 00:58:48.122202 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4400 00:58:48.125635 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4401 00:58:48.132141 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4402 00:58:48.135636 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4403 00:58:48.138846 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4404 00:58:48.145188 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 00:58:48.148814 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 00:58:48.152068 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4407 00:58:48.159007 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4408 00:58:48.161856 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4409 00:58:48.165120 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4410 00:58:48.171481 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4411 00:58:48.175054 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 00:58:48.178781 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 00:58:48.184809 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 00:58:48.188428 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 00:58:48.191469 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 00:58:48.197971 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 00:58:48.201599 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 00:58:48.204832 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 00:58:48.211163 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 00:58:48.214723 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 00:58:48.218303 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 00:58:48.224559 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4423 00:58:48.227770 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 00:58:48.231354 Total UI for P1: 0, mck2ui 16
4425 00:58:48.234682 best dqsien dly found for B0: ( 0, 13, 12)
4426 00:58:48.237816 Total UI for P1: 0, mck2ui 16
4427 00:58:48.240923 best dqsien dly found for B1: ( 0, 13, 12)
4428 00:58:48.244517 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4429 00:58:48.247455 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4430 00:58:48.247563
4431 00:58:48.250683 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4432 00:58:48.254403 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4433 00:58:48.257268 [Gating] SW calibration Done
4434 00:58:48.257428 ==
4435 00:58:48.260975 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 00:58:48.266992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 00:58:48.267097 ==
4438 00:58:48.267200 RX Vref Scan: 0
4439 00:58:48.267291
4440 00:58:48.270652 RX Vref 0 -> 0, step: 1
4441 00:58:48.270728
4442 00:58:48.274181 RX Delay -230 -> 252, step: 16
4443 00:58:48.277140 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4444 00:58:48.280550 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4445 00:58:48.284004 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4446 00:58:48.290739 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4447 00:58:48.293732 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4448 00:58:48.297300 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4449 00:58:48.300444 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4450 00:58:48.307445 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4451 00:58:48.310099 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4452 00:58:48.313850 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4453 00:58:48.316584 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4454 00:58:48.323941 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4455 00:58:48.326872 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4456 00:58:48.330610 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4457 00:58:48.333762 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4458 00:58:48.340154 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4459 00:58:48.340236 ==
4460 00:58:48.343561 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 00:58:48.346892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 00:58:48.347049 ==
4463 00:58:48.347114 DQS Delay:
4464 00:58:48.350071 DQS0 = 0, DQS1 = 0
4465 00:58:48.350152 DQM Delay:
4466 00:58:48.353643 DQM0 = 41, DQM1 = 39
4467 00:58:48.353724 DQ Delay:
4468 00:58:48.356446 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4469 00:58:48.360604 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4470 00:58:48.363196 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4471 00:58:48.366526 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4472 00:58:48.366607
4473 00:58:48.366685
4474 00:58:48.366750 ==
4475 00:58:48.370401 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 00:58:48.373407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 00:58:48.373484 ==
4478 00:58:48.373556
4479 00:58:48.376658
4480 00:58:48.376757 TX Vref Scan disable
4481 00:58:48.380083 == TX Byte 0 ==
4482 00:58:48.382990 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4483 00:58:48.386315 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4484 00:58:48.389514 == TX Byte 1 ==
4485 00:58:48.392917 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4486 00:58:48.396863 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4487 00:58:48.396965 ==
4488 00:58:48.399558 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 00:58:48.406027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 00:58:48.406110 ==
4491 00:58:48.406175
4492 00:58:48.406235
4493 00:58:48.406293 TX Vref Scan disable
4494 00:58:48.410735 == TX Byte 0 ==
4495 00:58:48.414242 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4496 00:58:48.420770 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4497 00:58:48.420852 == TX Byte 1 ==
4498 00:58:48.423672 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4499 00:58:48.430449 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4500 00:58:48.430531
4501 00:58:48.430595 [DATLAT]
4502 00:58:48.430656 Freq=600, CH1 RK0
4503 00:58:48.430715
4504 00:58:48.433760 DATLAT Default: 0x9
4505 00:58:48.437234 0, 0xFFFF, sum = 0
4506 00:58:48.437340 1, 0xFFFF, sum = 0
4507 00:58:48.440341 2, 0xFFFF, sum = 0
4508 00:58:48.440423 3, 0xFFFF, sum = 0
4509 00:58:48.443765 4, 0xFFFF, sum = 0
4510 00:58:48.443847 5, 0xFFFF, sum = 0
4511 00:58:48.447037 6, 0xFFFF, sum = 0
4512 00:58:48.447119 7, 0xFFFF, sum = 0
4513 00:58:48.450536 8, 0x0, sum = 1
4514 00:58:48.450619 9, 0x0, sum = 2
4515 00:58:48.454046 10, 0x0, sum = 3
4516 00:58:48.454129 11, 0x0, sum = 4
4517 00:58:48.454194 best_step = 9
4518 00:58:48.454254
4519 00:58:48.457014 ==
4520 00:58:48.459941 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 00:58:48.463359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 00:58:48.463441 ==
4523 00:58:48.463506 RX Vref Scan: 1
4524 00:58:48.463566
4525 00:58:48.466484 RX Vref 0 -> 0, step: 1
4526 00:58:48.466566
4527 00:58:48.470143 RX Delay -179 -> 252, step: 8
4528 00:58:48.470224
4529 00:58:48.473859 Set Vref, RX VrefLevel [Byte0]: 52
4530 00:58:48.476559 [Byte1]: 53
4531 00:58:48.476660
4532 00:58:48.480318 Final RX Vref Byte 0 = 52 to rank0
4533 00:58:48.483238 Final RX Vref Byte 1 = 53 to rank0
4534 00:58:48.486594 Final RX Vref Byte 0 = 52 to rank1
4535 00:58:48.489955 Final RX Vref Byte 1 = 53 to rank1==
4536 00:58:48.493638 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 00:58:48.496844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 00:58:48.500323 ==
4539 00:58:48.500402 DQS Delay:
4540 00:58:48.500482 DQS0 = 0, DQS1 = 0
4541 00:58:48.503746 DQM Delay:
4542 00:58:48.503846 DQM0 = 42, DQM1 = 34
4543 00:58:48.506617 DQ Delay:
4544 00:58:48.509767 DQ0 =52, DQ1 =40, DQ2 =32, DQ3 =40
4545 00:58:48.509841 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4546 00:58:48.513105 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4547 00:58:48.516337 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4548 00:58:48.520204
4549 00:58:48.520304
4550 00:58:48.525998 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e48, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4551 00:58:48.529845 CH1 RK0: MR19=808, MR18=2E48
4552 00:58:48.535865 CH1_RK0: MR19=0x808, MR18=0x2E48, DQSOSC=396, MR23=63, INC=167, DEC=111
4553 00:58:48.535966
4554 00:58:48.539455 ----->DramcWriteLeveling(PI) begin...
4555 00:58:48.539534 ==
4556 00:58:48.542682 Dram Type= 6, Freq= 0, CH_1, rank 1
4557 00:58:48.545768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 00:58:48.545859 ==
4559 00:58:48.549693 Write leveling (Byte 0): 28 => 28
4560 00:58:48.552294 Write leveling (Byte 1): 31 => 31
4561 00:58:48.555959 DramcWriteLeveling(PI) end<-----
4562 00:58:48.556067
4563 00:58:48.556160 ==
4564 00:58:48.559109 Dram Type= 6, Freq= 0, CH_1, rank 1
4565 00:58:48.562790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 00:58:48.562897 ==
4567 00:58:48.566057 [Gating] SW mode calibration
4568 00:58:48.572330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4569 00:58:48.579255 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4570 00:58:48.582664 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4571 00:58:48.589089 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4572 00:58:48.591842 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4573 00:58:48.595559 0 9 12 | B1->B0 | 3131 2a2a | 1 1 | (0 1) (1 0)
4574 00:58:48.601865 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4575 00:58:48.605213 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4576 00:58:48.608393 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4577 00:58:48.615248 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4578 00:58:48.618942 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4579 00:58:48.621823 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4580 00:58:48.628761 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4581 00:58:48.631824 0 10 12 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
4582 00:58:48.635267 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4583 00:58:48.642174 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4584 00:58:48.644845 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4585 00:58:48.647954 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4586 00:58:48.654664 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4587 00:58:48.658297 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4588 00:58:48.661603 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4589 00:58:48.669063 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4590 00:58:48.671503 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4591 00:58:48.674577 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4592 00:58:48.681115 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4593 00:58:48.684379 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4594 00:58:48.687746 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4595 00:58:48.694036 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4596 00:58:48.697685 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 00:58:48.700755 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 00:58:48.707574 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 00:58:48.710815 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 00:58:48.714062 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 00:58:48.720761 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 00:58:48.724193 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 00:58:48.727333 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 00:58:48.734038 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4605 00:58:48.737377 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4606 00:58:48.740626 Total UI for P1: 0, mck2ui 16
4607 00:58:48.743979 best dqsien dly found for B0: ( 0, 13, 8)
4608 00:58:48.747408 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 00:58:48.750281 Total UI for P1: 0, mck2ui 16
4610 00:58:48.753909 best dqsien dly found for B1: ( 0, 13, 10)
4611 00:58:48.756896 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4612 00:58:48.760477 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4613 00:58:48.760585
4614 00:58:48.766919 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4615 00:58:48.769899 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4616 00:58:48.769974 [Gating] SW calibration Done
4617 00:58:48.773034 ==
4618 00:58:48.776769 Dram Type= 6, Freq= 0, CH_1, rank 1
4619 00:58:48.780177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 00:58:48.780276 ==
4621 00:58:48.780379 RX Vref Scan: 0
4622 00:58:48.780468
4623 00:58:48.783086 RX Vref 0 -> 0, step: 1
4624 00:58:48.783190
4625 00:58:48.786167 RX Delay -230 -> 252, step: 16
4626 00:58:48.789779 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4627 00:58:48.793297 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4628 00:58:48.799773 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4629 00:58:48.803191 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4630 00:58:48.806209 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4631 00:58:48.809475 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4632 00:58:48.816471 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4633 00:58:48.819206 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4634 00:58:48.823158 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4635 00:58:48.825805 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4636 00:58:48.832495 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4637 00:58:48.835672 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4638 00:58:48.839248 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4639 00:58:48.842200 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4640 00:58:48.849210 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4641 00:58:48.852166 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4642 00:58:48.852253 ==
4643 00:58:48.855534 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 00:58:48.859444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 00:58:48.859558 ==
4646 00:58:48.862780 DQS Delay:
4647 00:58:48.862876 DQS0 = 0, DQS1 = 0
4648 00:58:48.862967 DQM Delay:
4649 00:58:48.865650 DQM0 = 42, DQM1 = 39
4650 00:58:48.865721 DQ Delay:
4651 00:58:48.868753 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4652 00:58:48.872051 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4653 00:58:48.875212 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4654 00:58:48.878367 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4655 00:58:48.878467
4656 00:58:48.878569
4657 00:58:48.878657 ==
4658 00:58:48.882131 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 00:58:48.888610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 00:58:48.888716 ==
4661 00:58:48.888815
4662 00:58:48.888909
4663 00:58:48.888997 TX Vref Scan disable
4664 00:58:48.892678 == TX Byte 0 ==
4665 00:58:48.895699 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4666 00:58:48.898997 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4667 00:58:48.902639 == TX Byte 1 ==
4668 00:58:48.905605 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4669 00:58:48.912174 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4670 00:58:48.912289 ==
4671 00:58:48.915619 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 00:58:48.919001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 00:58:48.919102 ==
4674 00:58:48.919202
4675 00:58:48.919292
4676 00:58:48.922066 TX Vref Scan disable
4677 00:58:48.925353 == TX Byte 0 ==
4678 00:58:48.929020 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4679 00:58:48.932485 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4680 00:58:48.935552 == TX Byte 1 ==
4681 00:58:48.939161 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4682 00:58:48.941979 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4683 00:58:48.942087
4684 00:58:48.942188 [DATLAT]
4685 00:58:48.945475 Freq=600, CH1 RK1
4686 00:58:48.945580
4687 00:58:48.948502 DATLAT Default: 0x9
4688 00:58:48.948599 0, 0xFFFF, sum = 0
4689 00:58:48.951902 1, 0xFFFF, sum = 0
4690 00:58:48.952001 2, 0xFFFF, sum = 0
4691 00:58:48.955031 3, 0xFFFF, sum = 0
4692 00:58:48.955138 4, 0xFFFF, sum = 0
4693 00:58:48.958739 5, 0xFFFF, sum = 0
4694 00:58:48.958852 6, 0xFFFF, sum = 0
4695 00:58:48.961669 7, 0xFFFF, sum = 0
4696 00:58:48.961768 8, 0x0, sum = 1
4697 00:58:48.965006 9, 0x0, sum = 2
4698 00:58:48.965119 10, 0x0, sum = 3
4699 00:58:48.968397 11, 0x0, sum = 4
4700 00:58:48.968496 best_step = 9
4701 00:58:48.968598
4702 00:58:48.968688 ==
4703 00:58:48.971513 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 00:58:48.975303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 00:58:48.975440 ==
4706 00:58:48.978120 RX Vref Scan: 0
4707 00:58:48.978219
4708 00:58:48.981235 RX Vref 0 -> 0, step: 1
4709 00:58:48.981354
4710 00:58:48.981420 RX Delay -179 -> 252, step: 8
4711 00:58:48.989334 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4712 00:58:48.992668 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4713 00:58:48.995767 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4714 00:58:48.999297 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4715 00:58:49.005641 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4716 00:58:49.009005 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4717 00:58:49.012652 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4718 00:58:49.016396 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4719 00:58:49.022138 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4720 00:58:49.025493 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4721 00:58:49.029187 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4722 00:58:49.032463 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4723 00:58:49.038786 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4724 00:58:49.041858 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4725 00:58:49.045862 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4726 00:58:49.049416 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4727 00:58:49.049522 ==
4728 00:58:49.052084 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 00:58:49.058548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 00:58:49.058656 ==
4731 00:58:49.058749 DQS Delay:
4732 00:58:49.061615 DQS0 = 0, DQS1 = 0
4733 00:58:49.061708 DQM Delay:
4734 00:58:49.064988 DQM0 = 37, DQM1 = 34
4735 00:58:49.065113 DQ Delay:
4736 00:58:49.068453 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4737 00:58:49.071935 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =32
4738 00:58:49.074866 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =24
4739 00:58:49.078338 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4740 00:58:49.078444
4741 00:58:49.078537
4742 00:58:49.084965 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4743 00:58:49.087815 CH1 RK1: MR19=808, MR18=3A5F
4744 00:58:49.094704 CH1_RK1: MR19=0x808, MR18=0x3A5F, DQSOSC=391, MR23=63, INC=171, DEC=114
4745 00:58:49.098078 [RxdqsGatingPostProcess] freq 600
4746 00:58:49.104860 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4747 00:58:49.107896 Pre-setting of DQS Precalculation
4748 00:58:49.110892 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4749 00:58:49.117900 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4750 00:58:49.124237 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4751 00:58:49.124350
4752 00:58:49.124442
4753 00:58:49.127920 [Calibration Summary] 1200 Mbps
4754 00:58:49.131728 CH 0, Rank 0
4755 00:58:49.131837 SW Impedance : PASS
4756 00:58:49.134146 DUTY Scan : NO K
4757 00:58:49.137441 ZQ Calibration : PASS
4758 00:58:49.137544 Jitter Meter : NO K
4759 00:58:49.141105 CBT Training : PASS
4760 00:58:49.144432 Write leveling : PASS
4761 00:58:49.144532 RX DQS gating : PASS
4762 00:58:49.147046 RX DQ/DQS(RDDQC) : PASS
4763 00:58:49.150676 TX DQ/DQS : PASS
4764 00:58:49.150771 RX DATLAT : PASS
4765 00:58:49.153868 RX DQ/DQS(Engine): PASS
4766 00:58:49.157494 TX OE : NO K
4767 00:58:49.157575 All Pass.
4768 00:58:49.157641
4769 00:58:49.157702 CH 0, Rank 1
4770 00:58:49.160542 SW Impedance : PASS
4771 00:58:49.163540 DUTY Scan : NO K
4772 00:58:49.163646 ZQ Calibration : PASS
4773 00:58:49.167113 Jitter Meter : NO K
4774 00:58:49.167224 CBT Training : PASS
4775 00:58:49.170357 Write leveling : PASS
4776 00:58:49.174011 RX DQS gating : PASS
4777 00:58:49.174143 RX DQ/DQS(RDDQC) : PASS
4778 00:58:49.177129 TX DQ/DQS : PASS
4779 00:58:49.180100 RX DATLAT : PASS
4780 00:58:49.180199 RX DQ/DQS(Engine): PASS
4781 00:58:49.183423 TX OE : NO K
4782 00:58:49.183523 All Pass.
4783 00:58:49.183645
4784 00:58:49.186601 CH 1, Rank 0
4785 00:58:49.186737 SW Impedance : PASS
4786 00:58:49.189881 DUTY Scan : NO K
4787 00:58:49.193915 ZQ Calibration : PASS
4788 00:58:49.193990 Jitter Meter : NO K
4789 00:58:49.196810 CBT Training : PASS
4790 00:58:49.199835 Write leveling : PASS
4791 00:58:49.199934 RX DQS gating : PASS
4792 00:58:49.203637 RX DQ/DQS(RDDQC) : PASS
4793 00:58:49.206689 TX DQ/DQS : PASS
4794 00:58:49.206794 RX DATLAT : PASS
4795 00:58:49.209635 RX DQ/DQS(Engine): PASS
4796 00:58:49.213478 TX OE : NO K
4797 00:58:49.213551 All Pass.
4798 00:58:49.213613
4799 00:58:49.213676 CH 1, Rank 1
4800 00:58:49.216376 SW Impedance : PASS
4801 00:58:49.219565 DUTY Scan : NO K
4802 00:58:49.219666 ZQ Calibration : PASS
4803 00:58:49.223097 Jitter Meter : NO K
4804 00:58:49.226432 CBT Training : PASS
4805 00:58:49.226507 Write leveling : PASS
4806 00:58:49.229488 RX DQS gating : PASS
4807 00:58:49.232923 RX DQ/DQS(RDDQC) : PASS
4808 00:58:49.233021 TX DQ/DQS : PASS
4809 00:58:49.236086 RX DATLAT : PASS
4810 00:58:49.239374 RX DQ/DQS(Engine): PASS
4811 00:58:49.239476 TX OE : NO K
4812 00:58:49.243020 All Pass.
4813 00:58:49.243094
4814 00:58:49.243155 DramC Write-DBI off
4815 00:58:49.246076 PER_BANK_REFRESH: Hybrid Mode
4816 00:58:49.246148 TX_TRACKING: ON
4817 00:58:49.255536 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4818 00:58:49.259158 [FAST_K] Save calibration result to emmc
4819 00:58:49.262432 dramc_set_vcore_voltage set vcore to 662500
4820 00:58:49.265605 Read voltage for 933, 3
4821 00:58:49.265682 Vio18 = 0
4822 00:58:49.268770 Vcore = 662500
4823 00:58:49.268871 Vdram = 0
4824 00:58:49.268964 Vddq = 0
4825 00:58:49.272062 Vmddr = 0
4826 00:58:49.275340 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4827 00:58:49.282263 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4828 00:58:49.282382 MEM_TYPE=3, freq_sel=17
4829 00:58:49.285249 sv_algorithm_assistance_LP4_1600
4830 00:58:49.292067 ============ PULL DRAM RESETB DOWN ============
4831 00:58:49.295152 ========== PULL DRAM RESETB DOWN end =========
4832 00:58:49.298941 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4833 00:58:49.301637 ===================================
4834 00:58:49.305132 LPDDR4 DRAM CONFIGURATION
4835 00:58:49.308945 ===================================
4836 00:58:49.311875 EX_ROW_EN[0] = 0x0
4837 00:58:49.311949 EX_ROW_EN[1] = 0x0
4838 00:58:49.315410 LP4Y_EN = 0x0
4839 00:58:49.315512 WORK_FSP = 0x0
4840 00:58:49.318189 WL = 0x3
4841 00:58:49.318290 RL = 0x3
4842 00:58:49.321744 BL = 0x2
4843 00:58:49.321819 RPST = 0x0
4844 00:58:49.324561 RD_PRE = 0x0
4845 00:58:49.324660 WR_PRE = 0x1
4846 00:58:49.328191 WR_PST = 0x0
4847 00:58:49.328291 DBI_WR = 0x0
4848 00:58:49.331656 DBI_RD = 0x0
4849 00:58:49.331754 OTF = 0x1
4850 00:58:49.334577 ===================================
4851 00:58:49.338151 ===================================
4852 00:58:49.341478 ANA top config
4853 00:58:49.344347 ===================================
4854 00:58:49.348090 DLL_ASYNC_EN = 0
4855 00:58:49.348201 ALL_SLAVE_EN = 1
4856 00:58:49.351164 NEW_RANK_MODE = 1
4857 00:58:49.354627 DLL_IDLE_MODE = 1
4858 00:58:49.357887 LP45_APHY_COMB_EN = 1
4859 00:58:49.361171 TX_ODT_DIS = 1
4860 00:58:49.361276 NEW_8X_MODE = 1
4861 00:58:49.364176 ===================================
4862 00:58:49.368223 ===================================
4863 00:58:49.371199 data_rate = 1866
4864 00:58:49.373953 CKR = 1
4865 00:58:49.377675 DQ_P2S_RATIO = 8
4866 00:58:49.380844 ===================================
4867 00:58:49.384114 CA_P2S_RATIO = 8
4868 00:58:49.387406 DQ_CA_OPEN = 0
4869 00:58:49.387506 DQ_SEMI_OPEN = 0
4870 00:58:49.390550 CA_SEMI_OPEN = 0
4871 00:58:49.393581 CA_FULL_RATE = 0
4872 00:58:49.397156 DQ_CKDIV4_EN = 1
4873 00:58:49.400157 CA_CKDIV4_EN = 1
4874 00:58:49.404208 CA_PREDIV_EN = 0
4875 00:58:49.404311 PH8_DLY = 0
4876 00:58:49.407840 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4877 00:58:49.410045 DQ_AAMCK_DIV = 4
4878 00:58:49.413417 CA_AAMCK_DIV = 4
4879 00:58:49.417106 CA_ADMCK_DIV = 4
4880 00:58:49.420337 DQ_TRACK_CA_EN = 0
4881 00:58:49.423248 CA_PICK = 933
4882 00:58:49.423355 CA_MCKIO = 933
4883 00:58:49.426785 MCKIO_SEMI = 0
4884 00:58:49.429913 PLL_FREQ = 3732
4885 00:58:49.433466 DQ_UI_PI_RATIO = 32
4886 00:58:49.436673 CA_UI_PI_RATIO = 0
4887 00:58:49.440035 ===================================
4888 00:58:49.443058 ===================================
4889 00:58:49.446827 memory_type:LPDDR4
4890 00:58:49.446928 GP_NUM : 10
4891 00:58:49.449789 SRAM_EN : 1
4892 00:58:49.449893 MD32_EN : 0
4893 00:58:49.452943 ===================================
4894 00:58:49.456191 [ANA_INIT] >>>>>>>>>>>>>>
4895 00:58:49.459768 <<<<<< [CONFIGURE PHASE]: ANA_TX
4896 00:58:49.463111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4897 00:58:49.466538 ===================================
4898 00:58:49.469292 data_rate = 1866,PCW = 0X8f00
4899 00:58:49.473435 ===================================
4900 00:58:49.476161 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4901 00:58:49.482802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4902 00:58:49.486272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4903 00:58:49.492647 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4904 00:58:49.496047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4905 00:58:49.499939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4906 00:58:49.500047 [ANA_INIT] flow start
4907 00:58:49.502341 [ANA_INIT] PLL >>>>>>>>
4908 00:58:49.505962 [ANA_INIT] PLL <<<<<<<<
4909 00:58:49.509168 [ANA_INIT] MIDPI >>>>>>>>
4910 00:58:49.509279 [ANA_INIT] MIDPI <<<<<<<<
4911 00:58:49.513231 [ANA_INIT] DLL >>>>>>>>
4912 00:58:49.515597 [ANA_INIT] flow end
4913 00:58:49.519004 ============ LP4 DIFF to SE enter ============
4914 00:58:49.522055 ============ LP4 DIFF to SE exit ============
4915 00:58:49.525813 [ANA_INIT] <<<<<<<<<<<<<
4916 00:58:49.528886 [Flow] Enable top DCM control >>>>>
4917 00:58:49.532479 [Flow] Enable top DCM control <<<<<
4918 00:58:49.535748 Enable DLL master slave shuffle
4919 00:58:49.538796 ==============================================================
4920 00:58:49.542097 Gating Mode config
4921 00:58:49.549026 ==============================================================
4922 00:58:49.549139 Config description:
4923 00:58:49.558559 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4924 00:58:49.565026 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4925 00:58:49.568529 SELPH_MODE 0: By rank 1: By Phase
4926 00:58:49.574917 ==============================================================
4927 00:58:49.578603 GAT_TRACK_EN = 1
4928 00:58:49.581862 RX_GATING_MODE = 2
4929 00:58:49.585392 RX_GATING_TRACK_MODE = 2
4930 00:58:49.588320 SELPH_MODE = 1
4931 00:58:49.591547 PICG_EARLY_EN = 1
4932 00:58:49.594578 VALID_LAT_VALUE = 1
4933 00:58:49.598184 ==============================================================
4934 00:58:49.601280 Enter into Gating configuration >>>>
4935 00:58:49.604637 Exit from Gating configuration <<<<
4936 00:58:49.608008 Enter into DVFS_PRE_config >>>>>
4937 00:58:49.621086 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4938 00:58:49.624758 Exit from DVFS_PRE_config <<<<<
4939 00:58:49.627804 Enter into PICG configuration >>>>
4940 00:58:49.630910 Exit from PICG configuration <<<<
4941 00:58:49.630998 [RX_INPUT] configuration >>>>>
4942 00:58:49.634104 [RX_INPUT] configuration <<<<<
4943 00:58:49.640868 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4944 00:58:49.643824 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4945 00:58:49.650436 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4946 00:58:49.657155 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4947 00:58:49.663545 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4948 00:58:49.670190 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4949 00:58:49.673878 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4950 00:58:49.676762 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4951 00:58:49.683522 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4952 00:58:49.686919 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4953 00:58:49.690283 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4954 00:58:49.697074 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4955 00:58:49.700061 ===================================
4956 00:58:49.700169 LPDDR4 DRAM CONFIGURATION
4957 00:58:49.703289 ===================================
4958 00:58:49.706381 EX_ROW_EN[0] = 0x0
4959 00:58:49.706461 EX_ROW_EN[1] = 0x0
4960 00:58:49.709808 LP4Y_EN = 0x0
4961 00:58:49.709886 WORK_FSP = 0x0
4962 00:58:49.713234 WL = 0x3
4963 00:58:49.716608 RL = 0x3
4964 00:58:49.716708 BL = 0x2
4965 00:58:49.719624 RPST = 0x0
4966 00:58:49.719698 RD_PRE = 0x0
4967 00:58:49.723210 WR_PRE = 0x1
4968 00:58:49.723308 WR_PST = 0x0
4969 00:58:49.726674 DBI_WR = 0x0
4970 00:58:49.726772 DBI_RD = 0x0
4971 00:58:49.729883 OTF = 0x1
4972 00:58:49.733159 ===================================
4973 00:58:49.736138 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4974 00:58:49.739325 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4975 00:58:49.746070 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4976 00:58:49.749735 ===================================
4977 00:58:49.749827 LPDDR4 DRAM CONFIGURATION
4978 00:58:49.752566 ===================================
4979 00:58:49.756070 EX_ROW_EN[0] = 0x10
4980 00:58:49.756171 EX_ROW_EN[1] = 0x0
4981 00:58:49.759114 LP4Y_EN = 0x0
4982 00:58:49.762391 WORK_FSP = 0x0
4983 00:58:49.762473 WL = 0x3
4984 00:58:49.765860 RL = 0x3
4985 00:58:49.765943 BL = 0x2
4986 00:58:49.768735 RPST = 0x0
4987 00:58:49.768826 RD_PRE = 0x0
4988 00:58:49.772300 WR_PRE = 0x1
4989 00:58:49.772379 WR_PST = 0x0
4990 00:58:49.775904 DBI_WR = 0x0
4991 00:58:49.775985 DBI_RD = 0x0
4992 00:58:49.778915 OTF = 0x1
4993 00:58:49.782116 ===================================
4994 00:58:49.789395 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4995 00:58:49.791791 nWR fixed to 30
4996 00:58:49.791872 [ModeRegInit_LP4] CH0 RK0
4997 00:58:49.795413 [ModeRegInit_LP4] CH0 RK1
4998 00:58:49.798971 [ModeRegInit_LP4] CH1 RK0
4999 00:58:49.802127 [ModeRegInit_LP4] CH1 RK1
5000 00:58:49.802216 match AC timing 9
5001 00:58:49.808624 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5002 00:58:49.811796 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5003 00:58:49.815093 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5004 00:58:49.821477 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5005 00:58:49.825720 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5006 00:58:49.825832 ==
5007 00:58:49.828371 Dram Type= 6, Freq= 0, CH_0, rank 0
5008 00:58:49.832038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5009 00:58:49.832115 ==
5010 00:58:49.837794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5011 00:58:49.844638 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5012 00:58:49.848114 [CA 0] Center 38 (8~68) winsize 61
5013 00:58:49.851469 [CA 1] Center 37 (7~68) winsize 62
5014 00:58:49.854692 [CA 2] Center 34 (4~65) winsize 62
5015 00:58:49.858138 [CA 3] Center 34 (4~65) winsize 62
5016 00:58:49.861093 [CA 4] Center 32 (2~63) winsize 62
5017 00:58:49.864248 [CA 5] Center 32 (2~63) winsize 62
5018 00:58:49.864362
5019 00:58:49.867780 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5020 00:58:49.867860
5021 00:58:49.871105 [CATrainingPosCal] consider 1 rank data
5022 00:58:49.874464 u2DelayCellTimex100 = 270/100 ps
5023 00:58:49.877461 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5024 00:58:49.881026 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5025 00:58:49.884571 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5026 00:58:49.887456 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5027 00:58:49.894097 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5028 00:58:49.897492 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5029 00:58:49.897571
5030 00:58:49.900449 CA PerBit enable=1, Macro0, CA PI delay=32
5031 00:58:49.900557
5032 00:58:49.904378 [CBTSetCACLKResult] CA Dly = 32
5033 00:58:49.904480 CS Dly: 6 (0~37)
5034 00:58:49.904578 ==
5035 00:58:49.907671 Dram Type= 6, Freq= 0, CH_0, rank 1
5036 00:58:49.913962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5037 00:58:49.914041 ==
5038 00:58:49.917044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5039 00:58:49.923577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5040 00:58:49.927397 [CA 0] Center 38 (8~68) winsize 61
5041 00:58:49.930205 [CA 1] Center 37 (7~68) winsize 62
5042 00:58:49.933723 [CA 2] Center 35 (5~65) winsize 61
5043 00:58:49.936783 [CA 3] Center 34 (4~65) winsize 62
5044 00:58:49.940560 [CA 4] Center 33 (3~64) winsize 62
5045 00:58:49.943663 [CA 5] Center 32 (2~63) winsize 62
5046 00:58:49.943774
5047 00:58:49.947365 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5048 00:58:49.947468
5049 00:58:49.950132 [CATrainingPosCal] consider 2 rank data
5050 00:58:49.953626 u2DelayCellTimex100 = 270/100 ps
5051 00:58:49.956949 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5052 00:58:49.960391 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5053 00:58:49.966907 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5054 00:58:49.969657 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5055 00:58:49.973206 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5056 00:58:49.976585 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5057 00:58:49.976688
5058 00:58:49.979983 CA PerBit enable=1, Macro0, CA PI delay=32
5059 00:58:49.980088
5060 00:58:49.983264 [CBTSetCACLKResult] CA Dly = 32
5061 00:58:49.983370 CS Dly: 7 (0~39)
5062 00:58:49.986399
5063 00:58:49.989449 ----->DramcWriteLeveling(PI) begin...
5064 00:58:49.989555 ==
5065 00:58:49.993079 Dram Type= 6, Freq= 0, CH_0, rank 0
5066 00:58:49.996690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5067 00:58:49.996771 ==
5068 00:58:49.999478 Write leveling (Byte 0): 33 => 33
5069 00:58:50.003041 Write leveling (Byte 1): 27 => 27
5070 00:58:50.006530 DramcWriteLeveling(PI) end<-----
5071 00:58:50.006628
5072 00:58:50.006720 ==
5073 00:58:50.009552 Dram Type= 6, Freq= 0, CH_0, rank 0
5074 00:58:50.012775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5075 00:58:50.012878 ==
5076 00:58:50.015932 [Gating] SW mode calibration
5077 00:58:50.022651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5078 00:58:50.029633 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5079 00:58:50.032414 0 14 0 | B1->B0 | 2323 3332 | 1 1 | (1 1) (1 1)
5080 00:58:50.036118 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5081 00:58:50.042281 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5082 00:58:50.046120 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5083 00:58:50.048783 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5084 00:58:50.055218 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5085 00:58:50.059152 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5086 00:58:50.062428 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5087 00:58:50.068518 0 15 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
5088 00:58:50.072529 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5089 00:58:50.075056 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5090 00:58:50.082045 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5091 00:58:50.084891 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5092 00:58:50.088499 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5093 00:58:50.094705 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5094 00:58:50.099134 0 15 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (1 1)
5095 00:58:50.101600 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5096 00:58:50.107827 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5097 00:58:50.111549 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5098 00:58:50.114798 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5099 00:58:50.121629 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5100 00:58:50.124715 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5101 00:58:50.127587 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 00:58:50.134178 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5103 00:58:50.138009 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5104 00:58:50.141129 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5105 00:58:50.147498 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5106 00:58:50.150657 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5107 00:58:50.154023 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5108 00:58:50.161023 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 00:58:50.164064 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 00:58:50.170496 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 00:58:50.174249 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 00:58:50.177408 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 00:58:50.180375 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 00:58:50.187367 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 00:58:50.190428 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 00:58:50.196761 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 00:58:50.200317 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 00:58:50.203716 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5119 00:58:50.210079 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5120 00:58:50.210185 Total UI for P1: 0, mck2ui 16
5121 00:58:50.216793 best dqsien dly found for B0: ( 1, 2, 28)
5122 00:58:50.219783 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5123 00:58:50.223380 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 00:58:50.226308 Total UI for P1: 0, mck2ui 16
5125 00:58:50.229707 best dqsien dly found for B1: ( 1, 3, 2)
5126 00:58:50.233178 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5127 00:58:50.236229 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5128 00:58:50.236329
5129 00:58:50.239505 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5130 00:58:50.246261 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5131 00:58:50.246368 [Gating] SW calibration Done
5132 00:58:50.246462 ==
5133 00:58:50.249510 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 00:58:50.256183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 00:58:50.256286 ==
5136 00:58:50.256385 RX Vref Scan: 0
5137 00:58:50.256454
5138 00:58:50.259615 RX Vref 0 -> 0, step: 1
5139 00:58:50.259718
5140 00:58:50.263231 RX Delay -80 -> 252, step: 8
5141 00:58:50.265796 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5142 00:58:50.269379 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5143 00:58:50.272830 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5144 00:58:50.279010 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5145 00:58:50.282107 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5146 00:58:50.285818 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5147 00:58:50.288936 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5148 00:58:50.292466 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5149 00:58:50.295996 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5150 00:58:50.302302 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5151 00:58:50.305208 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5152 00:58:50.308690 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5153 00:58:50.312475 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5154 00:58:50.316616 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5155 00:58:50.322064 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5156 00:58:50.325569 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5157 00:58:50.325647 ==
5158 00:58:50.328224 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 00:58:50.331665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 00:58:50.331765 ==
5161 00:58:50.335408 DQS Delay:
5162 00:58:50.335506 DQS0 = 0, DQS1 = 0
5163 00:58:50.335600 DQM Delay:
5164 00:58:50.338797 DQM0 = 100, DQM1 = 88
5165 00:58:50.338899 DQ Delay:
5166 00:58:50.341406 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5167 00:58:50.345037 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5168 00:58:50.348514 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5169 00:58:50.351335 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5170 00:58:50.351435
5171 00:58:50.351528
5172 00:58:50.351616 ==
5173 00:58:50.355030 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 00:58:50.361401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 00:58:50.361481 ==
5176 00:58:50.361545
5177 00:58:50.361606
5178 00:58:50.361668 TX Vref Scan disable
5179 00:58:50.365384 == TX Byte 0 ==
5180 00:58:50.368770 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5181 00:58:50.374991 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5182 00:58:50.375093 == TX Byte 1 ==
5183 00:58:50.378612 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5184 00:58:50.385176 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5185 00:58:50.385315 ==
5186 00:58:50.388017 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 00:58:50.391465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 00:58:50.391569 ==
5189 00:58:50.391667
5190 00:58:50.391759
5191 00:58:50.394727 TX Vref Scan disable
5192 00:58:50.398026 == TX Byte 0 ==
5193 00:58:50.401281 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5194 00:58:50.405144 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5195 00:58:50.408170 == TX Byte 1 ==
5196 00:58:50.411289 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5197 00:58:50.414457 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5198 00:58:50.414530
5199 00:58:50.414593 [DATLAT]
5200 00:58:50.418660 Freq=933, CH0 RK0
5201 00:58:50.418730
5202 00:58:50.421151 DATLAT Default: 0xd
5203 00:58:50.421248 0, 0xFFFF, sum = 0
5204 00:58:50.424554 1, 0xFFFF, sum = 0
5205 00:58:50.424652 2, 0xFFFF, sum = 0
5206 00:58:50.427652 3, 0xFFFF, sum = 0
5207 00:58:50.427729 4, 0xFFFF, sum = 0
5208 00:58:50.430912 5, 0xFFFF, sum = 0
5209 00:58:50.431010 6, 0xFFFF, sum = 0
5210 00:58:50.434130 7, 0xFFFF, sum = 0
5211 00:58:50.434226 8, 0xFFFF, sum = 0
5212 00:58:50.437875 9, 0xFFFF, sum = 0
5213 00:58:50.437952 10, 0x0, sum = 1
5214 00:58:50.440779 11, 0x0, sum = 2
5215 00:58:50.440851 12, 0x0, sum = 3
5216 00:58:50.444526 13, 0x0, sum = 4
5217 00:58:50.444631 best_step = 11
5218 00:58:50.444721
5219 00:58:50.444812 ==
5220 00:58:50.447523 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 00:58:50.451174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 00:58:50.454136 ==
5223 00:58:50.454209 RX Vref Scan: 1
5224 00:58:50.454274
5225 00:58:50.457592 RX Vref 0 -> 0, step: 1
5226 00:58:50.457664
5227 00:58:50.460722 RX Delay -61 -> 252, step: 4
5228 00:58:50.460820
5229 00:58:50.464465 Set Vref, RX VrefLevel [Byte0]: 55
5230 00:58:50.467158 [Byte1]: 58
5231 00:58:50.467231
5232 00:58:50.470317 Final RX Vref Byte 0 = 55 to rank0
5233 00:58:50.474033 Final RX Vref Byte 1 = 58 to rank0
5234 00:58:50.477176 Final RX Vref Byte 0 = 55 to rank1
5235 00:58:50.480774 Final RX Vref Byte 1 = 58 to rank1==
5236 00:58:50.483829 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 00:58:50.486890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 00:58:50.486967 ==
5239 00:58:50.490242 DQS Delay:
5240 00:58:50.490315 DQS0 = 0, DQS1 = 0
5241 00:58:50.490377 DQM Delay:
5242 00:58:50.493717 DQM0 = 97, DQM1 = 87
5243 00:58:50.493816 DQ Delay:
5244 00:58:50.497124 DQ0 =100, DQ1 =98, DQ2 =92, DQ3 =94
5245 00:58:50.500328 DQ4 =98, DQ5 =90, DQ6 =106, DQ7 =104
5246 00:58:50.503366 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =84
5247 00:58:50.506627 DQ12 =96, DQ13 =90, DQ14 =96, DQ15 =94
5248 00:58:50.506701
5249 00:58:50.506762
5250 00:58:50.516367 [DQSOSCAuto] RK0, (LSB)MR18= 0x1914, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5251 00:58:50.520049 CH0 RK0: MR19=505, MR18=1914
5252 00:58:50.523401 CH0_RK0: MR19=0x505, MR18=0x1914, DQSOSC=413, MR23=63, INC=63, DEC=42
5253 00:58:50.527001
5254 00:58:50.530128 ----->DramcWriteLeveling(PI) begin...
5255 00:58:50.530209 ==
5256 00:58:50.532988 Dram Type= 6, Freq= 0, CH_0, rank 1
5257 00:58:50.536919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 00:58:50.537017 ==
5259 00:58:50.539746 Write leveling (Byte 0): 30 => 30
5260 00:58:50.543242 Write leveling (Byte 1): 28 => 28
5261 00:58:50.546395 DramcWriteLeveling(PI) end<-----
5262 00:58:50.546472
5263 00:58:50.546534 ==
5264 00:58:50.550149 Dram Type= 6, Freq= 0, CH_0, rank 1
5265 00:58:50.553278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 00:58:50.553396 ==
5267 00:58:50.556533 [Gating] SW mode calibration
5268 00:58:50.562714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5269 00:58:50.569555 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5270 00:58:50.572646 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5271 00:58:50.575875 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5272 00:58:50.582999 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5273 00:58:50.585784 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5274 00:58:50.589535 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5275 00:58:50.596267 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5276 00:58:50.599133 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5277 00:58:50.602626 0 14 28 | B1->B0 | 3333 2424 | 0 0 | (0 0) (0 0)
5278 00:58:50.609002 0 15 0 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (0 0)
5279 00:58:50.612068 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5280 00:58:50.615776 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5281 00:58:50.622116 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5282 00:58:50.626036 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5283 00:58:50.628995 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5284 00:58:50.635284 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5285 00:58:50.639362 0 15 28 | B1->B0 | 2c2c 3b3b | 0 1 | (0 0) (0 0)
5286 00:58:50.642143 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5287 00:58:50.648876 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5288 00:58:50.652028 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5289 00:58:50.655474 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5290 00:58:50.661691 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5291 00:58:50.665199 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5292 00:58:50.668538 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5293 00:58:50.674981 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5294 00:58:50.678077 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5295 00:58:50.681163 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5296 00:58:50.687941 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5297 00:58:50.691439 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5298 00:58:50.694661 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5299 00:58:50.701074 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 00:58:50.704743 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 00:58:50.707809 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 00:58:50.714422 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 00:58:50.718030 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 00:58:50.721009 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 00:58:50.728216 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 00:58:50.731038 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 00:58:50.734449 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 00:58:50.740812 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5309 00:58:50.744362 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5310 00:58:50.747490 Total UI for P1: 0, mck2ui 16
5311 00:58:50.750920 best dqsien dly found for B0: ( 1, 2, 24)
5312 00:58:50.754455 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5313 00:58:50.760581 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5314 00:58:50.763897 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 00:58:50.767020 Total UI for P1: 0, mck2ui 16
5316 00:58:50.770861 best dqsien dly found for B1: ( 1, 3, 2)
5317 00:58:50.773819 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5318 00:58:50.777044 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5319 00:58:50.777145
5320 00:58:50.780244 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5321 00:58:50.783576 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5322 00:58:50.786943 [Gating] SW calibration Done
5323 00:58:50.787024 ==
5324 00:58:50.790363 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 00:58:50.796360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 00:58:50.796465 ==
5327 00:58:50.796558 RX Vref Scan: 0
5328 00:58:50.796647
5329 00:58:50.799722 RX Vref 0 -> 0, step: 1
5330 00:58:50.799796
5331 00:58:50.803692 RX Delay -80 -> 252, step: 8
5332 00:58:50.806646 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5333 00:58:50.810304 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5334 00:58:50.813114 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5335 00:58:50.816735 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5336 00:58:50.823118 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5337 00:58:50.826414 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5338 00:58:50.829795 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5339 00:58:50.832974 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5340 00:58:50.836308 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5341 00:58:50.839672 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5342 00:58:50.846385 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5343 00:58:50.849407 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5344 00:58:50.852830 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5345 00:58:50.856104 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5346 00:58:50.859583 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5347 00:58:50.862925 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5348 00:58:50.866261 ==
5349 00:58:50.869716 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 00:58:50.872744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 00:58:50.872849 ==
5352 00:58:50.872941 DQS Delay:
5353 00:58:50.876016 DQS0 = 0, DQS1 = 0
5354 00:58:50.876090 DQM Delay:
5355 00:58:50.879053 DQM0 = 96, DQM1 = 90
5356 00:58:50.879126 DQ Delay:
5357 00:58:50.882532 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5358 00:58:50.885488 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5359 00:58:50.888954 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5360 00:58:50.891943 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5361 00:58:50.892021
5362 00:58:50.892085
5363 00:58:50.892145 ==
5364 00:58:50.895594 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 00:58:50.898645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 00:58:50.898751 ==
5367 00:58:50.901859
5368 00:58:50.901935
5369 00:58:50.902003 TX Vref Scan disable
5370 00:58:50.905687 == TX Byte 0 ==
5371 00:58:50.908870 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5372 00:58:50.912020 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5373 00:58:50.915433 == TX Byte 1 ==
5374 00:58:50.918654 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5375 00:58:50.922135 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5376 00:58:50.922236 ==
5377 00:58:50.925784 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 00:58:50.931500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 00:58:50.931605 ==
5380 00:58:50.931698
5381 00:58:50.931790
5382 00:58:50.935388 TX Vref Scan disable
5383 00:58:50.935487 == TX Byte 0 ==
5384 00:58:50.941805 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5385 00:58:50.945549 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5386 00:58:50.945625 == TX Byte 1 ==
5387 00:58:50.951945 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5388 00:58:50.955152 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5389 00:58:50.955226
5390 00:58:50.955289 [DATLAT]
5391 00:58:50.958085 Freq=933, CH0 RK1
5392 00:58:50.958158
5393 00:58:50.958219 DATLAT Default: 0xb
5394 00:58:50.961122 0, 0xFFFF, sum = 0
5395 00:58:50.961194 1, 0xFFFF, sum = 0
5396 00:58:50.964386 2, 0xFFFF, sum = 0
5397 00:58:50.964465 3, 0xFFFF, sum = 0
5398 00:58:50.967857 4, 0xFFFF, sum = 0
5399 00:58:50.967982 5, 0xFFFF, sum = 0
5400 00:58:50.971010 6, 0xFFFF, sum = 0
5401 00:58:50.974596 7, 0xFFFF, sum = 0
5402 00:58:50.974675 8, 0xFFFF, sum = 0
5403 00:58:50.977997 9, 0xFFFF, sum = 0
5404 00:58:50.978072 10, 0x0, sum = 1
5405 00:58:50.981188 11, 0x0, sum = 2
5406 00:58:50.981323 12, 0x0, sum = 3
5407 00:58:50.981389 13, 0x0, sum = 4
5408 00:58:50.984160 best_step = 11
5409 00:58:50.984253
5410 00:58:50.984344 ==
5411 00:58:50.988059 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 00:58:50.990807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 00:58:50.990883 ==
5414 00:58:50.994700 RX Vref Scan: 0
5415 00:58:50.994798
5416 00:58:50.997333 RX Vref 0 -> 0, step: 1
5417 00:58:50.997429
5418 00:58:50.997519 RX Delay -53 -> 252, step: 4
5419 00:58:51.004699 iDelay=195, Bit 0, Center 98 (11 ~ 186) 176
5420 00:58:51.008477 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5421 00:58:51.011775 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5422 00:58:51.014967 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5423 00:58:51.018415 iDelay=195, Bit 4, Center 98 (7 ~ 190) 184
5424 00:58:51.021832 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5425 00:58:51.028077 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5426 00:58:51.031561 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5427 00:58:51.034448 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5428 00:58:51.037978 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5429 00:58:51.041137 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5430 00:58:51.048029 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5431 00:58:51.051101 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5432 00:58:51.054771 iDelay=195, Bit 13, Center 96 (7 ~ 186) 180
5433 00:58:51.058159 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5434 00:58:51.061627 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5435 00:58:51.061732 ==
5436 00:58:51.064229 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 00:58:51.070662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 00:58:51.070771 ==
5439 00:58:51.070873 DQS Delay:
5440 00:58:51.074694 DQS0 = 0, DQS1 = 0
5441 00:58:51.074796 DQM Delay:
5442 00:58:51.077703 DQM0 = 97, DQM1 = 89
5443 00:58:51.077776 DQ Delay:
5444 00:58:51.081150 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5445 00:58:51.084082 DQ4 =98, DQ5 =86, DQ6 =108, DQ7 =104
5446 00:58:51.087584 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5447 00:58:51.090750 DQ12 =94, DQ13 =96, DQ14 =100, DQ15 =94
5448 00:58:51.090855
5449 00:58:51.090943
5450 00:58:51.097350 [DQSOSCAuto] RK1, (LSB)MR18= 0x1715, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5451 00:58:51.100379 CH0 RK1: MR19=505, MR18=1715
5452 00:58:51.107147 CH0_RK1: MR19=0x505, MR18=0x1715, DQSOSC=414, MR23=63, INC=63, DEC=42
5453 00:58:51.110392 [RxdqsGatingPostProcess] freq 933
5454 00:58:51.117010 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5455 00:58:51.120165 best DQS0 dly(2T, 0.5T) = (0, 10)
5456 00:58:51.123708 best DQS1 dly(2T, 0.5T) = (0, 11)
5457 00:58:51.126816 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5458 00:58:51.130001 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5459 00:58:51.130074 best DQS0 dly(2T, 0.5T) = (0, 10)
5460 00:58:51.133140 best DQS1 dly(2T, 0.5T) = (0, 11)
5461 00:58:51.137012 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5462 00:58:51.140123 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5463 00:58:51.143087 Pre-setting of DQS Precalculation
5464 00:58:51.149562 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5465 00:58:51.149669 ==
5466 00:58:51.154261 Dram Type= 6, Freq= 0, CH_1, rank 0
5467 00:58:51.156232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 00:58:51.156370 ==
5469 00:58:51.163345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5470 00:58:51.169514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5471 00:58:51.172979 [CA 0] Center 36 (6~67) winsize 62
5472 00:58:51.176075 [CA 1] Center 36 (6~67) winsize 62
5473 00:58:51.179237 [CA 2] Center 34 (4~64) winsize 61
5474 00:58:51.183397 [CA 3] Center 34 (4~64) winsize 61
5475 00:58:51.185747 [CA 4] Center 34 (4~64) winsize 61
5476 00:58:51.189409 [CA 5] Center 33 (3~64) winsize 62
5477 00:58:51.189490
5478 00:58:51.192686 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5479 00:58:51.192767
5480 00:58:51.195843 [CATrainingPosCal] consider 1 rank data
5481 00:58:51.198716 u2DelayCellTimex100 = 270/100 ps
5482 00:58:51.202259 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5483 00:58:51.205796 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5484 00:58:51.209069 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5485 00:58:51.212062 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5486 00:58:51.215674 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5487 00:58:51.218887 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5488 00:58:51.222039
5489 00:58:51.225037 CA PerBit enable=1, Macro0, CA PI delay=33
5490 00:58:51.225119
5491 00:58:51.228454 [CBTSetCACLKResult] CA Dly = 33
5492 00:58:51.228534 CS Dly: 4 (0~35)
5493 00:58:51.228598 ==
5494 00:58:51.232083 Dram Type= 6, Freq= 0, CH_1, rank 1
5495 00:58:51.235099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 00:58:51.238110 ==
5497 00:58:51.241737 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 00:58:51.247995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5499 00:58:51.251591 [CA 0] Center 36 (6~66) winsize 61
5500 00:58:51.255023 [CA 1] Center 36 (6~67) winsize 62
5501 00:58:51.258079 [CA 2] Center 34 (4~65) winsize 62
5502 00:58:51.261865 [CA 3] Center 33 (3~64) winsize 62
5503 00:58:51.264564 [CA 4] Center 34 (4~64) winsize 61
5504 00:58:51.268188 [CA 5] Center 33 (3~64) winsize 62
5505 00:58:51.268275
5506 00:58:51.271333 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5507 00:58:51.271414
5508 00:58:51.274481 [CATrainingPosCal] consider 2 rank data
5509 00:58:51.278021 u2DelayCellTimex100 = 270/100 ps
5510 00:58:51.281612 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5511 00:58:51.285182 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5512 00:58:51.287707 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5513 00:58:51.294617 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5514 00:58:51.297658 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5515 00:58:51.300943 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5516 00:58:51.301041
5517 00:58:51.304325 CA PerBit enable=1, Macro0, CA PI delay=33
5518 00:58:51.304396
5519 00:58:51.307725 [CBTSetCACLKResult] CA Dly = 33
5520 00:58:51.307821 CS Dly: 5 (0~38)
5521 00:58:51.307917
5522 00:58:51.310973 ----->DramcWriteLeveling(PI) begin...
5523 00:58:51.314989 ==
5524 00:58:51.315091 Dram Type= 6, Freq= 0, CH_1, rank 0
5525 00:58:51.321682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 00:58:51.321766 ==
5527 00:58:51.324086 Write leveling (Byte 0): 29 => 29
5528 00:58:51.327328 Write leveling (Byte 1): 29 => 29
5529 00:58:51.330597 DramcWriteLeveling(PI) end<-----
5530 00:58:51.330666
5531 00:58:51.330726 ==
5532 00:58:51.333923 Dram Type= 6, Freq= 0, CH_1, rank 0
5533 00:58:51.337548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 00:58:51.337642 ==
5535 00:58:51.341273 [Gating] SW mode calibration
5536 00:58:51.347011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5537 00:58:51.353655 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5538 00:58:51.357042 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5539 00:58:51.361272 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5540 00:58:51.366731 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 00:58:51.370536 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 00:58:51.373210 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 00:58:51.380121 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 00:58:51.383151 0 14 24 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
5545 00:58:51.386594 0 14 28 | B1->B0 | 3030 2424 | 0 0 | (0 1) (1 0)
5546 00:58:51.393408 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5547 00:58:51.396745 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 00:58:51.399536 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 00:58:51.406472 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 00:58:51.410156 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 00:58:51.413183 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 00:58:51.419900 0 15 24 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
5553 00:58:51.422819 0 15 28 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
5554 00:58:51.426074 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 00:58:51.432772 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 00:58:51.436489 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 00:58:51.439376 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 00:58:51.445877 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 00:58:51.448976 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 00:58:51.452728 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5561 00:58:51.459112 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5562 00:58:51.462708 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 00:58:51.466046 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 00:58:51.472875 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 00:58:51.475682 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 00:58:51.479125 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 00:58:51.485239 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 00:58:51.488972 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 00:58:51.492249 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 00:58:51.499022 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 00:58:51.502156 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 00:58:51.505252 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 00:58:51.512238 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 00:58:51.515151 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 00:58:51.518459 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 00:58:51.525172 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 00:58:51.529056 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5578 00:58:51.531349 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5579 00:58:51.535385 Total UI for P1: 0, mck2ui 16
5580 00:58:51.538367 best dqsien dly found for B0: ( 1, 2, 28)
5581 00:58:51.544569 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 00:58:51.544684 Total UI for P1: 0, mck2ui 16
5583 00:58:51.551432 best dqsien dly found for B1: ( 1, 2, 30)
5584 00:58:51.554512 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5585 00:58:51.558065 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5586 00:58:51.558186
5587 00:58:51.561154 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5588 00:58:51.564291 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5589 00:58:51.567863 [Gating] SW calibration Done
5590 00:58:51.567964 ==
5591 00:58:51.571039 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 00:58:51.574093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 00:58:51.574214 ==
5594 00:58:51.577630 RX Vref Scan: 0
5595 00:58:51.577712
5596 00:58:51.577788 RX Vref 0 -> 0, step: 1
5597 00:58:51.577876
5598 00:58:51.580721 RX Delay -80 -> 252, step: 8
5599 00:58:51.584055 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5600 00:58:51.591342 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5601 00:58:51.594095 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5602 00:58:51.597334 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5603 00:58:51.600922 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5604 00:58:51.604487 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5605 00:58:51.607897 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5606 00:58:51.614122 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5607 00:58:51.617664 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5608 00:58:51.620947 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5609 00:58:51.623758 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5610 00:58:51.627226 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5611 00:58:51.633932 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5612 00:58:51.636962 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5613 00:58:51.640311 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5614 00:58:51.643594 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5615 00:58:51.643693 ==
5616 00:58:51.647160 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 00:58:51.650765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 00:58:51.653916 ==
5619 00:58:51.654015 DQS Delay:
5620 00:58:51.654115 DQS0 = 0, DQS1 = 0
5621 00:58:51.657039 DQM Delay:
5622 00:58:51.657133 DQM0 = 100, DQM1 = 95
5623 00:58:51.660391 DQ Delay:
5624 00:58:51.663756 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5625 00:58:51.666629 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5626 00:58:51.670036 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5627 00:58:51.673561 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5628 00:58:51.673666
5629 00:58:51.673757
5630 00:58:51.673850 ==
5631 00:58:51.676731 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 00:58:51.680086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 00:58:51.680189 ==
5634 00:58:51.680283
5635 00:58:51.680371
5636 00:58:51.683045 TX Vref Scan disable
5637 00:58:51.686540 == TX Byte 0 ==
5638 00:58:51.690355 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5639 00:58:51.693238 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5640 00:58:51.696492 == TX Byte 1 ==
5641 00:58:51.700131 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5642 00:58:51.702821 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5643 00:58:51.702926 ==
5644 00:58:51.706427 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 00:58:51.709451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 00:58:51.713160 ==
5647 00:58:51.713283
5648 00:58:51.713364
5649 00:58:51.713445 TX Vref Scan disable
5650 00:58:51.717365 == TX Byte 0 ==
5651 00:58:51.719813 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5652 00:58:51.726723 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5653 00:58:51.726809 == TX Byte 1 ==
5654 00:58:51.730074 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5655 00:58:51.736108 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5656 00:58:51.736217
5657 00:58:51.736308 [DATLAT]
5658 00:58:51.736396 Freq=933, CH1 RK0
5659 00:58:51.736494
5660 00:58:51.739667 DATLAT Default: 0xd
5661 00:58:51.742783 0, 0xFFFF, sum = 0
5662 00:58:51.742886 1, 0xFFFF, sum = 0
5663 00:58:51.746137 2, 0xFFFF, sum = 0
5664 00:58:51.746246 3, 0xFFFF, sum = 0
5665 00:58:51.749197 4, 0xFFFF, sum = 0
5666 00:58:51.749329 5, 0xFFFF, sum = 0
5667 00:58:51.752417 6, 0xFFFF, sum = 0
5668 00:58:51.752519 7, 0xFFFF, sum = 0
5669 00:58:51.756033 8, 0xFFFF, sum = 0
5670 00:58:51.756143 9, 0xFFFF, sum = 0
5671 00:58:51.759611 10, 0x0, sum = 1
5672 00:58:51.759712 11, 0x0, sum = 2
5673 00:58:51.762735 12, 0x0, sum = 3
5674 00:58:51.762822 13, 0x0, sum = 4
5675 00:58:51.765912 best_step = 11
5676 00:58:51.766010
5677 00:58:51.766100 ==
5678 00:58:51.769200 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 00:58:51.773054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 00:58:51.773153 ==
5681 00:58:51.775820 RX Vref Scan: 1
5682 00:58:51.775891
5683 00:58:51.775991 RX Vref 0 -> 0, step: 1
5684 00:58:51.776079
5685 00:58:51.779056 RX Delay -53 -> 252, step: 4
5686 00:58:51.779152
5687 00:58:51.783311 Set Vref, RX VrefLevel [Byte0]: 52
5688 00:58:51.785363 [Byte1]: 53
5689 00:58:51.789109
5690 00:58:51.789225 Final RX Vref Byte 0 = 52 to rank0
5691 00:58:51.792417 Final RX Vref Byte 1 = 53 to rank0
5692 00:58:51.795483 Final RX Vref Byte 0 = 52 to rank1
5693 00:58:51.799155 Final RX Vref Byte 1 = 53 to rank1==
5694 00:58:51.802494 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 00:58:51.808667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 00:58:51.808773 ==
5697 00:58:51.808865 DQS Delay:
5698 00:58:51.812419 DQS0 = 0, DQS1 = 0
5699 00:58:51.812522 DQM Delay:
5700 00:58:51.812614 DQM0 = 98, DQM1 = 95
5701 00:58:51.815684 DQ Delay:
5702 00:58:51.818436 DQ0 =104, DQ1 =94, DQ2 =86, DQ3 =98
5703 00:58:51.821871 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5704 00:58:51.825160 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =88
5705 00:58:51.828344 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5706 00:58:51.828451
5707 00:58:51.828541
5708 00:58:51.835112 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5709 00:58:51.838160 CH1 RK0: MR19=505, MR18=C1B
5710 00:58:51.844571 CH1_RK0: MR19=0x505, MR18=0xC1B, DQSOSC=413, MR23=63, INC=63, DEC=42
5711 00:58:51.844649
5712 00:58:51.848349 ----->DramcWriteLeveling(PI) begin...
5713 00:58:51.848448 ==
5714 00:58:51.851427 Dram Type= 6, Freq= 0, CH_1, rank 1
5715 00:58:51.854589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 00:58:51.858200 ==
5717 00:58:51.858298 Write leveling (Byte 0): 23 => 23
5718 00:58:51.861362 Write leveling (Byte 1): 26 => 26
5719 00:58:51.864669 DramcWriteLeveling(PI) end<-----
5720 00:58:51.864775
5721 00:58:51.864878 ==
5722 00:58:51.868418 Dram Type= 6, Freq= 0, CH_1, rank 1
5723 00:58:51.874283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 00:58:51.874367 ==
5725 00:58:51.877630 [Gating] SW mode calibration
5726 00:58:51.884103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5727 00:58:51.887882 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5728 00:58:51.894028 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5729 00:58:51.897393 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5730 00:58:51.901185 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5731 00:58:51.907305 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5732 00:58:51.910675 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5733 00:58:51.913866 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5734 00:58:51.921555 0 14 24 | B1->B0 | 3232 2d2d | 1 0 | (1 1) (0 1)
5735 00:58:51.923850 0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5736 00:58:51.926822 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5737 00:58:51.933579 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5738 00:58:51.936622 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5739 00:58:51.940592 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5740 00:58:51.946699 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5741 00:58:51.950088 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5742 00:58:51.953516 0 15 24 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
5743 00:58:51.959729 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
5744 00:58:51.963008 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5745 00:58:51.967244 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5746 00:58:51.973148 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5747 00:58:51.976054 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5748 00:58:51.979274 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5749 00:58:51.986512 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5750 00:58:51.989416 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5751 00:58:51.993050 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5752 00:58:51.999172 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5753 00:58:52.002479 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5754 00:58:52.005812 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 00:58:52.012397 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 00:58:52.015501 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 00:58:52.019184 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 00:58:52.026370 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 00:58:52.028840 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 00:58:52.032322 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 00:58:52.038548 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 00:58:52.042068 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 00:58:52.045109 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 00:58:52.052747 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 00:58:52.055726 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 00:58:52.058259 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 00:58:52.065003 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5768 00:58:52.068576 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 00:58:52.072209 Total UI for P1: 0, mck2ui 16
5770 00:58:52.074944 best dqsien dly found for B0: ( 1, 2, 28)
5771 00:58:52.078033 Total UI for P1: 0, mck2ui 16
5772 00:58:52.082078 best dqsien dly found for B1: ( 1, 2, 28)
5773 00:58:52.084668 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5774 00:58:52.088770 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5775 00:58:52.088880
5776 00:58:52.091497 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5777 00:58:52.097673 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5778 00:58:52.097786 [Gating] SW calibration Done
5779 00:58:52.097880 ==
5780 00:58:52.101348 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 00:58:52.108322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 00:58:52.108425 ==
5783 00:58:52.108516 RX Vref Scan: 0
5784 00:58:52.108605
5785 00:58:52.111306 RX Vref 0 -> 0, step: 1
5786 00:58:52.111402
5787 00:58:52.114710 RX Delay -80 -> 252, step: 8
5788 00:58:52.117930 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5789 00:58:52.121197 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5790 00:58:52.124071 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5791 00:58:52.130596 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5792 00:58:52.134647 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5793 00:58:52.137614 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5794 00:58:52.140921 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5795 00:58:52.144335 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5796 00:58:52.147028 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5797 00:58:52.154036 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5798 00:58:52.157124 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5799 00:58:52.160831 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5800 00:58:52.163872 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5801 00:58:52.167650 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5802 00:58:52.170702 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5803 00:58:52.176935 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5804 00:58:52.177038 ==
5805 00:58:52.180110 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 00:58:52.183408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 00:58:52.183511 ==
5808 00:58:52.183651 DQS Delay:
5809 00:58:52.186749 DQS0 = 0, DQS1 = 0
5810 00:58:52.186852 DQM Delay:
5811 00:58:52.190176 DQM0 = 97, DQM1 = 94
5812 00:58:52.190249 DQ Delay:
5813 00:58:52.193252 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5814 00:58:52.196457 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5815 00:58:52.200001 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5816 00:58:52.203070 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5817 00:58:52.203177
5818 00:58:52.203273
5819 00:58:52.203361 ==
5820 00:58:52.206681 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 00:58:52.212999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 00:58:52.213106 ==
5823 00:58:52.213197
5824 00:58:52.213326
5825 00:58:52.213410 TX Vref Scan disable
5826 00:58:52.216579 == TX Byte 0 ==
5827 00:58:52.220562 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5828 00:58:52.226713 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5829 00:58:52.226815 == TX Byte 1 ==
5830 00:58:52.230610 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5831 00:58:52.237203 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5832 00:58:52.237352 ==
5833 00:58:52.240245 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 00:58:52.242988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 00:58:52.243088 ==
5836 00:58:52.243182
5837 00:58:52.243271
5838 00:58:52.246498 TX Vref Scan disable
5839 00:58:52.250044 == TX Byte 0 ==
5840 00:58:52.252966 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5841 00:58:52.256337 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5842 00:58:52.259489 == TX Byte 1 ==
5843 00:58:52.263053 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5844 00:58:52.265960 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5845 00:58:52.266059
5846 00:58:52.266151 [DATLAT]
5847 00:58:52.269413 Freq=933, CH1 RK1
5848 00:58:52.269507
5849 00:58:52.272747 DATLAT Default: 0xb
5850 00:58:52.272845 0, 0xFFFF, sum = 0
5851 00:58:52.275998 1, 0xFFFF, sum = 0
5852 00:58:52.276100 2, 0xFFFF, sum = 0
5853 00:58:52.279752 3, 0xFFFF, sum = 0
5854 00:58:52.279850 4, 0xFFFF, sum = 0
5855 00:58:52.282623 5, 0xFFFF, sum = 0
5856 00:58:52.282724 6, 0xFFFF, sum = 0
5857 00:58:52.285920 7, 0xFFFF, sum = 0
5858 00:58:52.286032 8, 0xFFFF, sum = 0
5859 00:58:52.289497 9, 0xFFFF, sum = 0
5860 00:58:52.289596 10, 0x0, sum = 1
5861 00:58:52.292440 11, 0x0, sum = 2
5862 00:58:52.292541 12, 0x0, sum = 3
5863 00:58:52.295976 13, 0x0, sum = 4
5864 00:58:52.296080 best_step = 11
5865 00:58:52.296170
5866 00:58:52.296256 ==
5867 00:58:52.298778 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 00:58:52.302605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 00:58:52.306751 ==
5870 00:58:52.306863 RX Vref Scan: 0
5871 00:58:52.306985
5872 00:58:52.309029 RX Vref 0 -> 0, step: 1
5873 00:58:52.309130
5874 00:58:52.312247 RX Delay -53 -> 252, step: 4
5875 00:58:52.315533 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5876 00:58:52.319435 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5877 00:58:52.325231 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5878 00:58:52.328676 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5879 00:58:52.332416 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5880 00:58:52.335419 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5881 00:58:52.339198 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5882 00:58:52.342220 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5883 00:58:52.348936 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5884 00:58:52.351676 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5885 00:58:52.354973 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5886 00:58:52.358445 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5887 00:58:52.361591 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5888 00:58:52.368434 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5889 00:58:52.372180 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5890 00:58:52.375177 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5891 00:58:52.375274 ==
5892 00:58:52.378008 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 00:58:52.381585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 00:58:52.384728 ==
5895 00:58:52.384833 DQS Delay:
5896 00:58:52.384924 DQS0 = 0, DQS1 = 0
5897 00:58:52.387602 DQM Delay:
5898 00:58:52.387705 DQM0 = 97, DQM1 = 92
5899 00:58:52.391099 DQ Delay:
5900 00:58:52.394769 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
5901 00:58:52.397681 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5902 00:58:52.401057 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5903 00:58:52.404780 DQ12 =100, DQ13 =102, DQ14 =96, DQ15 =102
5904 00:58:52.404887
5905 00:58:52.404977
5906 00:58:52.410942 [DQSOSCAuto] RK1, (LSB)MR18= 0xb22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5907 00:58:52.414348 CH1 RK1: MR19=505, MR18=B22
5908 00:58:52.420761 CH1_RK1: MR19=0x505, MR18=0xB22, DQSOSC=411, MR23=63, INC=64, DEC=42
5909 00:58:52.424100 [RxdqsGatingPostProcess] freq 933
5910 00:58:52.427678 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5911 00:58:52.430433 best DQS0 dly(2T, 0.5T) = (0, 10)
5912 00:58:52.433994 best DQS1 dly(2T, 0.5T) = (0, 10)
5913 00:58:52.437031 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5914 00:58:52.440778 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5915 00:58:52.443702 best DQS0 dly(2T, 0.5T) = (0, 10)
5916 00:58:52.447183 best DQS1 dly(2T, 0.5T) = (0, 10)
5917 00:58:52.450625 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5918 00:58:52.453704 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5919 00:58:52.456924 Pre-setting of DQS Precalculation
5920 00:58:52.461263 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5921 00:58:52.470795 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5922 00:58:52.476492 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5923 00:58:52.476599
5924 00:58:52.476692
5925 00:58:52.480152 [Calibration Summary] 1866 Mbps
5926 00:58:52.480250 CH 0, Rank 0
5927 00:58:52.483383 SW Impedance : PASS
5928 00:58:52.486676 DUTY Scan : NO K
5929 00:58:52.486775 ZQ Calibration : PASS
5930 00:58:52.490019 Jitter Meter : NO K
5931 00:58:52.490124 CBT Training : PASS
5932 00:58:52.493449 Write leveling : PASS
5933 00:58:52.496352 RX DQS gating : PASS
5934 00:58:52.496448 RX DQ/DQS(RDDQC) : PASS
5935 00:58:52.499882 TX DQ/DQS : PASS
5936 00:58:52.503376 RX DATLAT : PASS
5937 00:58:52.503474 RX DQ/DQS(Engine): PASS
5938 00:58:52.506468 TX OE : NO K
5939 00:58:52.506565 All Pass.
5940 00:58:52.506654
5941 00:58:52.509571 CH 0, Rank 1
5942 00:58:52.509668 SW Impedance : PASS
5943 00:58:52.513923 DUTY Scan : NO K
5944 00:58:52.516246 ZQ Calibration : PASS
5945 00:58:52.516352 Jitter Meter : NO K
5946 00:58:52.519359 CBT Training : PASS
5947 00:58:52.522618 Write leveling : PASS
5948 00:58:52.522728 RX DQS gating : PASS
5949 00:58:52.526338 RX DQ/DQS(RDDQC) : PASS
5950 00:58:52.529152 TX DQ/DQS : PASS
5951 00:58:52.529278 RX DATLAT : PASS
5952 00:58:52.532867 RX DQ/DQS(Engine): PASS
5953 00:58:52.536054 TX OE : NO K
5954 00:58:52.536157 All Pass.
5955 00:58:52.536254
5956 00:58:52.536341 CH 1, Rank 0
5957 00:58:52.538938 SW Impedance : PASS
5958 00:58:52.543473 DUTY Scan : NO K
5959 00:58:52.543570 ZQ Calibration : PASS
5960 00:58:52.545832 Jitter Meter : NO K
5961 00:58:52.549640 CBT Training : PASS
5962 00:58:52.549744 Write leveling : PASS
5963 00:58:52.552263 RX DQS gating : PASS
5964 00:58:52.555212 RX DQ/DQS(RDDQC) : PASS
5965 00:58:52.555321 TX DQ/DQS : PASS
5966 00:58:52.558826 RX DATLAT : PASS
5967 00:58:52.562120 RX DQ/DQS(Engine): PASS
5968 00:58:52.562220 TX OE : NO K
5969 00:58:52.565220 All Pass.
5970 00:58:52.565356
5971 00:58:52.565458 CH 1, Rank 1
5972 00:58:52.569061 SW Impedance : PASS
5973 00:58:52.569159 DUTY Scan : NO K
5974 00:58:52.571910 ZQ Calibration : PASS
5975 00:58:52.574918 Jitter Meter : NO K
5976 00:58:52.574996 CBT Training : PASS
5977 00:58:52.578652 Write leveling : PASS
5978 00:58:52.581932 RX DQS gating : PASS
5979 00:58:52.582050 RX DQ/DQS(RDDQC) : PASS
5980 00:58:52.584725 TX DQ/DQS : PASS
5981 00:58:52.588273 RX DATLAT : PASS
5982 00:58:52.588387 RX DQ/DQS(Engine): PASS
5983 00:58:52.591462 TX OE : NO K
5984 00:58:52.591561 All Pass.
5985 00:58:52.591663
5986 00:58:52.594832 DramC Write-DBI off
5987 00:58:52.597955 PER_BANK_REFRESH: Hybrid Mode
5988 00:58:52.598061 TX_TRACKING: ON
5989 00:58:52.607971 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5990 00:58:52.611755 [FAST_K] Save calibration result to emmc
5991 00:58:52.615066 dramc_set_vcore_voltage set vcore to 650000
5992 00:58:52.617988 Read voltage for 400, 6
5993 00:58:52.618093 Vio18 = 0
5994 00:58:52.618185 Vcore = 650000
5995 00:58:52.621161 Vdram = 0
5996 00:58:52.621283 Vddq = 0
5997 00:58:52.621392 Vmddr = 0
5998 00:58:52.627712 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5999 00:58:52.631150 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6000 00:58:52.634405 MEM_TYPE=3, freq_sel=20
6001 00:58:52.637593 sv_algorithm_assistance_LP4_800
6002 00:58:52.640888 ============ PULL DRAM RESETB DOWN ============
6003 00:58:52.644248 ========== PULL DRAM RESETB DOWN end =========
6004 00:58:52.650611 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6005 00:58:52.654260 ===================================
6006 00:58:52.654372 LPDDR4 DRAM CONFIGURATION
6007 00:58:52.657448 ===================================
6008 00:58:52.660641 EX_ROW_EN[0] = 0x0
6009 00:58:52.664151 EX_ROW_EN[1] = 0x0
6010 00:58:52.664255 LP4Y_EN = 0x0
6011 00:58:52.667108 WORK_FSP = 0x0
6012 00:58:52.667205 WL = 0x2
6013 00:58:52.670872 RL = 0x2
6014 00:58:52.670970 BL = 0x2
6015 00:58:52.674140 RPST = 0x0
6016 00:58:52.674265 RD_PRE = 0x0
6017 00:58:52.677102 WR_PRE = 0x1
6018 00:58:52.677213 WR_PST = 0x0
6019 00:58:52.680169 DBI_WR = 0x0
6020 00:58:52.680264 DBI_RD = 0x0
6021 00:58:52.683619 OTF = 0x1
6022 00:58:52.686827 ===================================
6023 00:58:52.690213 ===================================
6024 00:58:52.690316 ANA top config
6025 00:58:52.693740 ===================================
6026 00:58:52.697190 DLL_ASYNC_EN = 0
6027 00:58:52.700229 ALL_SLAVE_EN = 1
6028 00:58:52.703873 NEW_RANK_MODE = 1
6029 00:58:52.706845 DLL_IDLE_MODE = 1
6030 00:58:52.706947 LP45_APHY_COMB_EN = 1
6031 00:58:52.710207 TX_ODT_DIS = 1
6032 00:58:52.713703 NEW_8X_MODE = 1
6033 00:58:52.716703 ===================================
6034 00:58:52.719930 ===================================
6035 00:58:52.723081 data_rate = 800
6036 00:58:52.726828 CKR = 1
6037 00:58:52.726937 DQ_P2S_RATIO = 4
6038 00:58:52.729709 ===================================
6039 00:58:52.733369 CA_P2S_RATIO = 4
6040 00:58:52.736612 DQ_CA_OPEN = 0
6041 00:58:52.739681 DQ_SEMI_OPEN = 1
6042 00:58:52.742879 CA_SEMI_OPEN = 1
6043 00:58:52.746319 CA_FULL_RATE = 0
6044 00:58:52.746426 DQ_CKDIV4_EN = 0
6045 00:58:52.749465 CA_CKDIV4_EN = 1
6046 00:58:52.752577 CA_PREDIV_EN = 0
6047 00:58:52.756119 PH8_DLY = 0
6048 00:58:52.759412 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6049 00:58:52.762712 DQ_AAMCK_DIV = 0
6050 00:58:52.765754 CA_AAMCK_DIV = 0
6051 00:58:52.765838 CA_ADMCK_DIV = 4
6052 00:58:52.769213 DQ_TRACK_CA_EN = 0
6053 00:58:52.772617 CA_PICK = 800
6054 00:58:52.776048 CA_MCKIO = 400
6055 00:58:52.779774 MCKIO_SEMI = 400
6056 00:58:52.782588 PLL_FREQ = 3016
6057 00:58:52.785906 DQ_UI_PI_RATIO = 32
6058 00:58:52.789081 CA_UI_PI_RATIO = 32
6059 00:58:52.792241 ===================================
6060 00:58:52.796324 ===================================
6061 00:58:52.796399 memory_type:LPDDR4
6062 00:58:52.798977 GP_NUM : 10
6063 00:58:52.801889 SRAM_EN : 1
6064 00:58:52.801967 MD32_EN : 0
6065 00:58:52.805233 ===================================
6066 00:58:52.809185 [ANA_INIT] >>>>>>>>>>>>>>
6067 00:58:52.812291 <<<<<< [CONFIGURE PHASE]: ANA_TX
6068 00:58:52.815225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6069 00:58:52.818430 ===================================
6070 00:58:52.821570 data_rate = 800,PCW = 0X7400
6071 00:58:52.825204 ===================================
6072 00:58:52.828643 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6073 00:58:52.832161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6074 00:58:52.844769 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6075 00:58:52.848491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6076 00:58:52.851952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6077 00:58:52.854791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6078 00:58:52.858000 [ANA_INIT] flow start
6079 00:58:52.861411 [ANA_INIT] PLL >>>>>>>>
6080 00:58:52.861512 [ANA_INIT] PLL <<<<<<<<
6081 00:58:52.865266 [ANA_INIT] MIDPI >>>>>>>>
6082 00:58:52.868042 [ANA_INIT] MIDPI <<<<<<<<
6083 00:58:52.868142 [ANA_INIT] DLL >>>>>>>>
6084 00:58:52.871574 [ANA_INIT] flow end
6085 00:58:52.875507 ============ LP4 DIFF to SE enter ============
6086 00:58:52.877773 ============ LP4 DIFF to SE exit ============
6087 00:58:52.881137 [ANA_INIT] <<<<<<<<<<<<<
6088 00:58:52.884280 [Flow] Enable top DCM control >>>>>
6089 00:58:52.887751 [Flow] Enable top DCM control <<<<<
6090 00:58:52.890790 Enable DLL master slave shuffle
6091 00:58:52.898003 ==============================================================
6092 00:58:52.898110 Gating Mode config
6093 00:58:52.904279 ==============================================================
6094 00:58:52.907499 Config description:
6095 00:58:52.913995 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6096 00:58:52.920426 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6097 00:58:52.927685 SELPH_MODE 0: By rank 1: By Phase
6098 00:58:52.933715 ==============================================================
6099 00:58:52.936946 GAT_TRACK_EN = 0
6100 00:58:52.937054 RX_GATING_MODE = 2
6101 00:58:52.940869 RX_GATING_TRACK_MODE = 2
6102 00:58:52.944381 SELPH_MODE = 1
6103 00:58:52.946902 PICG_EARLY_EN = 1
6104 00:58:52.950185 VALID_LAT_VALUE = 1
6105 00:58:52.956744 ==============================================================
6106 00:58:52.960024 Enter into Gating configuration >>>>
6107 00:58:52.963524 Exit from Gating configuration <<<<
6108 00:58:52.966947 Enter into DVFS_PRE_config >>>>>
6109 00:58:52.977007 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6110 00:58:52.979831 Exit from DVFS_PRE_config <<<<<
6111 00:58:52.983151 Enter into PICG configuration >>>>
6112 00:58:52.986343 Exit from PICG configuration <<<<
6113 00:58:52.989504 [RX_INPUT] configuration >>>>>
6114 00:58:52.993318 [RX_INPUT] configuration <<<<<
6115 00:58:52.996323 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6116 00:58:53.002519 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6117 00:58:53.009422 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6118 00:58:53.016716 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6119 00:58:53.022509 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6120 00:58:53.025610 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6121 00:58:53.032172 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6122 00:58:53.035749 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6123 00:58:53.039059 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6124 00:58:53.042103 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6125 00:58:53.048920 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6126 00:58:53.052240 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6127 00:58:53.055412 ===================================
6128 00:58:53.058695 LPDDR4 DRAM CONFIGURATION
6129 00:58:53.061932 ===================================
6130 00:58:53.062004 EX_ROW_EN[0] = 0x0
6131 00:58:53.065240 EX_ROW_EN[1] = 0x0
6132 00:58:53.065357 LP4Y_EN = 0x0
6133 00:58:53.068790 WORK_FSP = 0x0
6134 00:58:53.071934 WL = 0x2
6135 00:58:53.072044 RL = 0x2
6136 00:58:53.074966 BL = 0x2
6137 00:58:53.075049 RPST = 0x0
6138 00:58:53.078213 RD_PRE = 0x0
6139 00:58:53.078294 WR_PRE = 0x1
6140 00:58:53.081762 WR_PST = 0x0
6141 00:58:53.081842 DBI_WR = 0x0
6142 00:58:53.085568 DBI_RD = 0x0
6143 00:58:53.085649 OTF = 0x1
6144 00:58:53.088416 ===================================
6145 00:58:53.092144 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6146 00:58:53.098178 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6147 00:58:53.101289 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 00:58:53.105355 ===================================
6149 00:58:53.108372 LPDDR4 DRAM CONFIGURATION
6150 00:58:53.111845 ===================================
6151 00:58:53.111952 EX_ROW_EN[0] = 0x10
6152 00:58:53.114700 EX_ROW_EN[1] = 0x0
6153 00:58:53.114801 LP4Y_EN = 0x0
6154 00:58:53.117825 WORK_FSP = 0x0
6155 00:58:53.121462 WL = 0x2
6156 00:58:53.121544 RL = 0x2
6157 00:58:53.124455 BL = 0x2
6158 00:58:53.124536 RPST = 0x0
6159 00:58:53.128182 RD_PRE = 0x0
6160 00:58:53.128264 WR_PRE = 0x1
6161 00:58:53.130917 WR_PST = 0x0
6162 00:58:53.130998 DBI_WR = 0x0
6163 00:58:53.134894 DBI_RD = 0x0
6164 00:58:53.135003 OTF = 0x1
6165 00:58:53.138089 ===================================
6166 00:58:53.144226 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6167 00:58:53.148400 nWR fixed to 30
6168 00:58:53.152194 [ModeRegInit_LP4] CH0 RK0
6169 00:58:53.152293 [ModeRegInit_LP4] CH0 RK1
6170 00:58:53.154936 [ModeRegInit_LP4] CH1 RK0
6171 00:58:53.158479 [ModeRegInit_LP4] CH1 RK1
6172 00:58:53.158561 match AC timing 19
6173 00:58:53.165132 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6174 00:58:53.168165 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6175 00:58:53.171417 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6176 00:58:53.178304 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6177 00:58:53.181450 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6178 00:58:53.181532 ==
6179 00:58:53.184780 Dram Type= 6, Freq= 0, CH_0, rank 0
6180 00:58:53.187865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6181 00:58:53.187967 ==
6182 00:58:53.194447 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6183 00:58:53.201232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6184 00:58:53.204274 [CA 0] Center 36 (8~64) winsize 57
6185 00:58:53.208168 [CA 1] Center 36 (8~64) winsize 57
6186 00:58:53.211066 [CA 2] Center 36 (8~64) winsize 57
6187 00:58:53.214419 [CA 3] Center 36 (8~64) winsize 57
6188 00:58:53.217848 [CA 4] Center 36 (8~64) winsize 57
6189 00:58:53.220969 [CA 5] Center 36 (8~64) winsize 57
6190 00:58:53.221054
6191 00:58:53.224151 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6192 00:58:53.224233
6193 00:58:53.227644 [CATrainingPosCal] consider 1 rank data
6194 00:58:53.230793 u2DelayCellTimex100 = 270/100 ps
6195 00:58:53.233934 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6196 00:58:53.237610 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6197 00:58:53.240336 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6198 00:58:53.243655 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6199 00:58:53.247287 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6200 00:58:53.250563 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6201 00:58:53.250645
6202 00:58:53.256927 CA PerBit enable=1, Macro0, CA PI delay=36
6203 00:58:53.257009
6204 00:58:53.260672 [CBTSetCACLKResult] CA Dly = 36
6205 00:58:53.260754 CS Dly: 1 (0~32)
6206 00:58:53.260836 ==
6207 00:58:53.263629 Dram Type= 6, Freq= 0, CH_0, rank 1
6208 00:58:53.267113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6209 00:58:53.267196 ==
6210 00:58:53.273472 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6211 00:58:53.279972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6212 00:58:53.283349 [CA 0] Center 36 (8~64) winsize 57
6213 00:58:53.286580 [CA 1] Center 36 (8~64) winsize 57
6214 00:58:53.290357 [CA 2] Center 36 (8~64) winsize 57
6215 00:58:53.293078 [CA 3] Center 36 (8~64) winsize 57
6216 00:58:53.297042 [CA 4] Center 36 (8~64) winsize 57
6217 00:58:53.297139 [CA 5] Center 36 (8~64) winsize 57
6218 00:58:53.299756
6219 00:58:53.303511 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6220 00:58:53.303593
6221 00:58:53.306765 [CATrainingPosCal] consider 2 rank data
6222 00:58:53.309654 u2DelayCellTimex100 = 270/100 ps
6223 00:58:53.312960 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 00:58:53.316674 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 00:58:53.320096 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 00:58:53.322919 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 00:58:53.326372 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 00:58:53.329374 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 00:58:53.329497
6230 00:58:53.332772 CA PerBit enable=1, Macro0, CA PI delay=36
6231 00:58:53.335911
6232 00:58:53.336000 [CBTSetCACLKResult] CA Dly = 36
6233 00:58:53.339957 CS Dly: 1 (0~32)
6234 00:58:53.340064
6235 00:58:53.342749 ----->DramcWriteLeveling(PI) begin...
6236 00:58:53.342850 ==
6237 00:58:53.346080 Dram Type= 6, Freq= 0, CH_0, rank 0
6238 00:58:53.349653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6239 00:58:53.349727 ==
6240 00:58:53.352457 Write leveling (Byte 0): 40 => 8
6241 00:58:53.355601 Write leveling (Byte 1): 40 => 8
6242 00:58:53.359131 DramcWriteLeveling(PI) end<-----
6243 00:58:53.359234
6244 00:58:53.359325 ==
6245 00:58:53.362307 Dram Type= 6, Freq= 0, CH_0, rank 0
6246 00:58:53.365455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6247 00:58:53.368958 ==
6248 00:58:53.369057 [Gating] SW mode calibration
6249 00:58:53.379079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6250 00:58:53.382105 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6251 00:58:53.385297 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6252 00:58:53.392007 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6253 00:58:53.395182 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6254 00:58:53.399391 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6255 00:58:53.405588 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6256 00:58:53.408596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6257 00:58:53.411836 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6258 00:58:53.419079 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6259 00:58:53.421633 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6260 00:58:53.425371 Total UI for P1: 0, mck2ui 16
6261 00:58:53.428287 best dqsien dly found for B0: ( 0, 14, 24)
6262 00:58:53.432051 Total UI for P1: 0, mck2ui 16
6263 00:58:53.434964 best dqsien dly found for B1: ( 0, 14, 24)
6264 00:58:53.438379 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6265 00:58:53.441354 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6266 00:58:53.441453
6267 00:58:53.445345 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6268 00:58:53.451187 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6269 00:58:53.451264 [Gating] SW calibration Done
6270 00:58:53.451344 ==
6271 00:58:53.454708 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 00:58:53.461351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 00:58:53.461434 ==
6274 00:58:53.461500 RX Vref Scan: 0
6275 00:58:53.461561
6276 00:58:53.464437 RX Vref 0 -> 0, step: 1
6277 00:58:53.464533
6278 00:58:53.468259 RX Delay -410 -> 252, step: 16
6279 00:58:53.471160 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6280 00:58:53.474854 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6281 00:58:53.480990 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6282 00:58:53.484278 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6283 00:58:53.487749 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6284 00:58:53.491157 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6285 00:58:53.497956 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6286 00:58:53.500737 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6287 00:58:53.504100 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6288 00:58:53.507430 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6289 00:58:53.513801 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6290 00:58:53.516867 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6291 00:58:53.520291 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6292 00:58:53.526708 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6293 00:58:53.530267 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6294 00:58:53.533658 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6295 00:58:53.533734 ==
6296 00:58:53.536565 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 00:58:53.540159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 00:58:53.543668 ==
6299 00:58:53.543774 DQS Delay:
6300 00:58:53.543867 DQS0 = 35, DQS1 = 59
6301 00:58:53.547235 DQM Delay:
6302 00:58:53.547335 DQM0 = 4, DQM1 = 18
6303 00:58:53.550342 DQ Delay:
6304 00:58:53.550447 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6305 00:58:53.553618 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6306 00:58:53.556432 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6307 00:58:53.559925 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6308 00:58:53.560034
6309 00:58:53.560127
6310 00:58:53.563278 ==
6311 00:58:53.566339 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 00:58:53.569630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 00:58:53.569725 ==
6314 00:58:53.569805
6315 00:58:53.569872
6316 00:58:53.573492 TX Vref Scan disable
6317 00:58:53.573581 == TX Byte 0 ==
6318 00:58:53.576449 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6319 00:58:53.582650 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6320 00:58:53.582759 == TX Byte 1 ==
6321 00:58:53.586114 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6322 00:58:53.592726 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6323 00:58:53.592837 ==
6324 00:58:53.596111 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 00:58:53.599409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 00:58:53.599511 ==
6327 00:58:53.599606
6328 00:58:53.599701
6329 00:58:53.602663 TX Vref Scan disable
6330 00:58:53.602758 == TX Byte 0 ==
6331 00:58:53.606133 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6332 00:58:53.612423 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6333 00:58:53.612522 == TX Byte 1 ==
6334 00:58:53.615605 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 00:58:53.622368 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 00:58:53.622469
6337 00:58:53.622564 [DATLAT]
6338 00:58:53.625880 Freq=400, CH0 RK0
6339 00:58:53.625949
6340 00:58:53.626009 DATLAT Default: 0xf
6341 00:58:53.629202 0, 0xFFFF, sum = 0
6342 00:58:53.629330 1, 0xFFFF, sum = 0
6343 00:58:53.632319 2, 0xFFFF, sum = 0
6344 00:58:53.632416 3, 0xFFFF, sum = 0
6345 00:58:53.636243 4, 0xFFFF, sum = 0
6346 00:58:53.636335 5, 0xFFFF, sum = 0
6347 00:58:53.638845 6, 0xFFFF, sum = 0
6348 00:58:53.638943 7, 0xFFFF, sum = 0
6349 00:58:53.642197 8, 0xFFFF, sum = 0
6350 00:58:53.642303 9, 0xFFFF, sum = 0
6351 00:58:53.645757 10, 0xFFFF, sum = 0
6352 00:58:53.645865 11, 0xFFFF, sum = 0
6353 00:58:53.648945 12, 0xFFFF, sum = 0
6354 00:58:53.649017 13, 0x0, sum = 1
6355 00:58:53.652454 14, 0x0, sum = 2
6356 00:58:53.652559 15, 0x0, sum = 3
6357 00:58:53.655132 16, 0x0, sum = 4
6358 00:58:53.655238 best_step = 14
6359 00:58:53.655326
6360 00:58:53.655420 ==
6361 00:58:53.658637 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 00:58:53.665648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 00:58:53.665758 ==
6364 00:58:53.665850 RX Vref Scan: 1
6365 00:58:53.665946
6366 00:58:53.668439 RX Vref 0 -> 0, step: 1
6367 00:58:53.668538
6368 00:58:53.671808 RX Delay -359 -> 252, step: 8
6369 00:58:53.671909
6370 00:58:53.675347 Set Vref, RX VrefLevel [Byte0]: 55
6371 00:58:53.678420 [Byte1]: 58
6372 00:58:53.682112
6373 00:58:53.682185 Final RX Vref Byte 0 = 55 to rank0
6374 00:58:53.685671 Final RX Vref Byte 1 = 58 to rank0
6375 00:58:53.688424 Final RX Vref Byte 0 = 55 to rank1
6376 00:58:53.691766 Final RX Vref Byte 1 = 58 to rank1==
6377 00:58:53.695377 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 00:58:53.701822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 00:58:53.701900 ==
6380 00:58:53.701967 DQS Delay:
6381 00:58:53.705100 DQS0 = 44, DQS1 = 60
6382 00:58:53.705207 DQM Delay:
6383 00:58:53.705324 DQM0 = 10, DQM1 = 16
6384 00:58:53.708497 DQ Delay:
6385 00:58:53.711486 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6386 00:58:53.715103 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6387 00:58:53.715214 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6388 00:58:53.721354 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6389 00:58:53.721432
6390 00:58:53.721496
6391 00:58:53.727880 [DQSOSCAuto] RK0, (LSB)MR18= 0x9387, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6392 00:58:53.731564 CH0 RK0: MR19=C0C, MR18=9387
6393 00:58:53.737708 CH0_RK0: MR19=0xC0C, MR18=0x9387, DQSOSC=391, MR23=63, INC=386, DEC=257
6394 00:58:53.737813 ==
6395 00:58:53.741061 Dram Type= 6, Freq= 0, CH_0, rank 1
6396 00:58:53.744542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 00:58:53.744642 ==
6398 00:58:53.747970 [Gating] SW mode calibration
6399 00:58:53.754432 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6400 00:58:53.761151 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6401 00:58:53.764562 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6402 00:58:53.767373 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6403 00:58:53.774112 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6404 00:58:53.777654 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6405 00:58:53.780311 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6406 00:58:53.787402 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 00:58:53.790440 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6408 00:58:53.793640 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6409 00:58:53.800420 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6410 00:58:53.804211 Total UI for P1: 0, mck2ui 16
6411 00:58:53.807851 best dqsien dly found for B0: ( 0, 14, 24)
6412 00:58:53.810401 Total UI for P1: 0, mck2ui 16
6413 00:58:53.813457 best dqsien dly found for B1: ( 0, 14, 24)
6414 00:58:53.816713 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6415 00:58:53.820052 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6416 00:58:53.820136
6417 00:58:53.823659 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6418 00:58:53.826780 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6419 00:58:53.829910 [Gating] SW calibration Done
6420 00:58:53.829993 ==
6421 00:58:53.833569 Dram Type= 6, Freq= 0, CH_0, rank 1
6422 00:58:53.836698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 00:58:53.836780 ==
6424 00:58:53.840069 RX Vref Scan: 0
6425 00:58:53.840150
6426 00:58:53.843955 RX Vref 0 -> 0, step: 1
6427 00:58:53.844037
6428 00:58:53.846509 RX Delay -410 -> 252, step: 16
6429 00:58:53.850046 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6430 00:58:53.853335 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6431 00:58:53.856659 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6432 00:58:53.863290 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6433 00:58:53.866557 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6434 00:58:53.869581 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6435 00:58:53.873140 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6436 00:58:53.879558 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6437 00:58:53.883482 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6438 00:58:53.886460 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6439 00:58:53.889516 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6440 00:58:53.895971 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6441 00:58:53.899518 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6442 00:58:53.902493 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6443 00:58:53.909509 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6444 00:58:53.912328 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6445 00:58:53.912413 ==
6446 00:58:53.915950 Dram Type= 6, Freq= 0, CH_0, rank 1
6447 00:58:53.919017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 00:58:53.919130 ==
6449 00:58:53.922462 DQS Delay:
6450 00:58:53.922545 DQS0 = 35, DQS1 = 51
6451 00:58:53.922641 DQM Delay:
6452 00:58:53.925648 DQM0 = 6, DQM1 = 9
6453 00:58:53.925730 DQ Delay:
6454 00:58:53.929165 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6455 00:58:53.931934 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6456 00:58:53.935625 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6457 00:58:53.939107 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6458 00:58:53.939190
6459 00:58:53.939254
6460 00:58:53.939314 ==
6461 00:58:53.942411 Dram Type= 6, Freq= 0, CH_0, rank 1
6462 00:58:53.945189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 00:58:53.945329 ==
6464 00:58:53.948512
6465 00:58:53.948593
6466 00:58:53.948657 TX Vref Scan disable
6467 00:58:53.952300 == TX Byte 0 ==
6468 00:58:53.955225 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6469 00:58:53.958956 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6470 00:58:53.961850 == TX Byte 1 ==
6471 00:58:53.965213 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6472 00:58:53.968236 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6473 00:58:53.968318 ==
6474 00:58:53.971728 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 00:58:53.978273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 00:58:53.978356 ==
6477 00:58:53.978422
6478 00:58:53.978482
6479 00:58:53.978540 TX Vref Scan disable
6480 00:58:53.981290 == TX Byte 0 ==
6481 00:58:53.984631 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6482 00:58:53.988286 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6483 00:58:53.991539 == TX Byte 1 ==
6484 00:58:53.994711 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6485 00:58:54.001447 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6486 00:58:54.001529
6487 00:58:54.001594 [DATLAT]
6488 00:58:54.001654 Freq=400, CH0 RK1
6489 00:58:54.001713
6490 00:58:54.004429 DATLAT Default: 0xe
6491 00:58:54.004510 0, 0xFFFF, sum = 0
6492 00:58:54.007843 1, 0xFFFF, sum = 0
6493 00:58:54.010952 2, 0xFFFF, sum = 0
6494 00:58:54.011035 3, 0xFFFF, sum = 0
6495 00:58:54.014142 4, 0xFFFF, sum = 0
6496 00:58:54.014265 5, 0xFFFF, sum = 0
6497 00:58:54.017408 6, 0xFFFF, sum = 0
6498 00:58:54.017529 7, 0xFFFF, sum = 0
6499 00:58:54.021020 8, 0xFFFF, sum = 0
6500 00:58:54.021104 9, 0xFFFF, sum = 0
6501 00:58:54.024331 10, 0xFFFF, sum = 0
6502 00:58:54.024414 11, 0xFFFF, sum = 0
6503 00:58:54.028050 12, 0xFFFF, sum = 0
6504 00:58:54.028133 13, 0x0, sum = 1
6505 00:58:54.031061 14, 0x0, sum = 2
6506 00:58:54.031145 15, 0x0, sum = 3
6507 00:58:54.034087 16, 0x0, sum = 4
6508 00:58:54.034171 best_step = 14
6509 00:58:54.034235
6510 00:58:54.034295 ==
6511 00:58:54.037280 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 00:58:54.044503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 00:58:54.044586 ==
6514 00:58:54.044650 RX Vref Scan: 0
6515 00:58:54.044711
6516 00:58:54.047310 RX Vref 0 -> 0, step: 1
6517 00:58:54.047391
6518 00:58:54.050876 RX Delay -343 -> 252, step: 8
6519 00:58:54.057053 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6520 00:58:54.060456 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6521 00:58:54.063705 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6522 00:58:54.066949 iDelay=209, Bit 3, Center -40 (-279 ~ 200) 480
6523 00:58:54.073428 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6524 00:58:54.077162 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6525 00:58:54.080421 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6526 00:58:54.083505 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6527 00:58:54.089721 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6528 00:58:54.093283 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6529 00:58:54.096502 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6530 00:58:54.100020 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6531 00:58:54.106229 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6532 00:58:54.109628 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6533 00:58:54.113213 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6534 00:58:54.120042 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6535 00:58:54.120124 ==
6536 00:58:54.122748 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 00:58:54.126432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 00:58:54.126510 ==
6539 00:58:54.126575 DQS Delay:
6540 00:58:54.129727 DQS0 = 44, DQS1 = 60
6541 00:58:54.129808 DQM Delay:
6542 00:58:54.132644 DQM0 = 9, DQM1 = 16
6543 00:58:54.132726 DQ Delay:
6544 00:58:54.136208 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6545 00:58:54.139547 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6546 00:58:54.143038 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6547 00:58:54.146154 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6548 00:58:54.146237
6549 00:58:54.146303
6550 00:58:54.152482 [DQSOSCAuto] RK1, (LSB)MR18= 0x8a83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6551 00:58:54.155705 CH0 RK1: MR19=C0C, MR18=8A83
6552 00:58:54.162632 CH0_RK1: MR19=0xC0C, MR18=0x8A83, DQSOSC=392, MR23=63, INC=384, DEC=256
6553 00:58:54.165541 [RxdqsGatingPostProcess] freq 400
6554 00:58:54.172523 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6555 00:58:54.175874 best DQS0 dly(2T, 0.5T) = (0, 10)
6556 00:58:54.178847 best DQS1 dly(2T, 0.5T) = (0, 10)
6557 00:58:54.182296 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6558 00:58:54.185577 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6559 00:58:54.185677 best DQS0 dly(2T, 0.5T) = (0, 10)
6560 00:58:54.188961 best DQS1 dly(2T, 0.5T) = (0, 10)
6561 00:58:54.191816 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6562 00:58:54.195066 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6563 00:58:54.198699 Pre-setting of DQS Precalculation
6564 00:58:54.205369 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6565 00:58:54.205446 ==
6566 00:58:54.208123 Dram Type= 6, Freq= 0, CH_1, rank 0
6567 00:58:54.211598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 00:58:54.211675 ==
6569 00:58:54.218227 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6570 00:58:54.224780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6571 00:58:54.228280 [CA 0] Center 36 (8~64) winsize 57
6572 00:58:54.231319 [CA 1] Center 36 (8~64) winsize 57
6573 00:58:54.231395 [CA 2] Center 36 (8~64) winsize 57
6574 00:58:54.234870 [CA 3] Center 36 (8~64) winsize 57
6575 00:58:54.238421 [CA 4] Center 36 (8~64) winsize 57
6576 00:58:54.241663 [CA 5] Center 36 (8~64) winsize 57
6577 00:58:54.241735
6578 00:58:54.245075 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6579 00:58:54.248064
6580 00:58:54.251510 [CATrainingPosCal] consider 1 rank data
6581 00:58:54.251580 u2DelayCellTimex100 = 270/100 ps
6582 00:58:54.257787 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6583 00:58:54.261495 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6584 00:58:54.265085 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6585 00:58:54.267733 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6586 00:58:54.270929 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6587 00:58:54.274972 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6588 00:58:54.275052
6589 00:58:54.277768 CA PerBit enable=1, Macro0, CA PI delay=36
6590 00:58:54.277848
6591 00:58:54.281512 [CBTSetCACLKResult] CA Dly = 36
6592 00:58:54.284382 CS Dly: 1 (0~32)
6593 00:58:54.284458 ==
6594 00:58:54.287739 Dram Type= 6, Freq= 0, CH_1, rank 1
6595 00:58:54.290706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 00:58:54.290782 ==
6597 00:58:54.297310 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6598 00:58:54.304628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6599 00:58:54.304706 [CA 0] Center 36 (8~64) winsize 57
6600 00:58:54.307556 [CA 1] Center 36 (8~64) winsize 57
6601 00:58:54.310725 [CA 2] Center 36 (8~64) winsize 57
6602 00:58:54.313857 [CA 3] Center 36 (8~64) winsize 57
6603 00:58:54.317479 [CA 4] Center 36 (8~64) winsize 57
6604 00:58:54.320458 [CA 5] Center 36 (8~64) winsize 57
6605 00:58:54.320533
6606 00:58:54.323647 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6607 00:58:54.323780
6608 00:58:54.327150 [CATrainingPosCal] consider 2 rank data
6609 00:58:54.330409 u2DelayCellTimex100 = 270/100 ps
6610 00:58:54.333405 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 00:58:54.340258 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 00:58:54.343491 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 00:58:54.347608 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 00:58:54.350096 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 00:58:54.353286 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 00:58:54.353372
6617 00:58:54.356611 CA PerBit enable=1, Macro0, CA PI delay=36
6618 00:58:54.356694
6619 00:58:54.359920 [CBTSetCACLKResult] CA Dly = 36
6620 00:58:54.363756 CS Dly: 1 (0~32)
6621 00:58:54.363834
6622 00:58:54.366762 ----->DramcWriteLeveling(PI) begin...
6623 00:58:54.366843 ==
6624 00:58:54.369606 Dram Type= 6, Freq= 0, CH_1, rank 0
6625 00:58:54.373350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 00:58:54.373429 ==
6627 00:58:54.376230 Write leveling (Byte 0): 40 => 8
6628 00:58:54.379441 Write leveling (Byte 1): 40 => 8
6629 00:58:54.383014 DramcWriteLeveling(PI) end<-----
6630 00:58:54.383086
6631 00:58:54.383148 ==
6632 00:58:54.386553 Dram Type= 6, Freq= 0, CH_1, rank 0
6633 00:58:54.389637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 00:58:54.389711 ==
6635 00:58:54.393064 [Gating] SW mode calibration
6636 00:58:54.399685 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6637 00:58:54.406105 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6638 00:58:54.408978 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6639 00:58:54.416289 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6640 00:58:54.419406 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6641 00:58:54.422765 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6642 00:58:54.429199 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6643 00:58:54.432525 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6644 00:58:54.435469 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6645 00:58:54.442434 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6646 00:58:54.445357 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6647 00:58:54.448897 Total UI for P1: 0, mck2ui 16
6648 00:58:54.451879 best dqsien dly found for B0: ( 0, 14, 24)
6649 00:58:54.455675 Total UI for P1: 0, mck2ui 16
6650 00:58:54.458389 best dqsien dly found for B1: ( 0, 14, 24)
6651 00:58:54.461990 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6652 00:58:54.465129 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6653 00:58:54.465220
6654 00:58:54.468152 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6655 00:58:54.471546 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6656 00:58:54.475306 [Gating] SW calibration Done
6657 00:58:54.475384 ==
6658 00:58:54.478159 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 00:58:54.484609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 00:58:54.484686 ==
6661 00:58:54.484749 RX Vref Scan: 0
6662 00:58:54.484809
6663 00:58:54.487841 RX Vref 0 -> 0, step: 1
6664 00:58:54.487918
6665 00:58:54.491415 RX Delay -410 -> 252, step: 16
6666 00:58:54.494768 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6667 00:58:54.497935 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6668 00:58:54.504659 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6669 00:58:54.508032 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6670 00:58:54.511166 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6671 00:58:54.514454 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6672 00:58:54.521497 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6673 00:58:54.524406 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6674 00:58:54.527768 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6675 00:58:54.531167 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6676 00:58:54.537630 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6677 00:58:54.541389 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6678 00:58:54.544444 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6679 00:58:54.548011 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6680 00:58:54.553857 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6681 00:58:54.557739 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6682 00:58:54.557822 ==
6683 00:58:54.561096 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 00:58:54.564183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 00:58:54.564267 ==
6686 00:58:54.566972 DQS Delay:
6687 00:58:54.567055 DQS0 = 35, DQS1 = 51
6688 00:58:54.570548 DQM Delay:
6689 00:58:54.570630 DQM0 = 6, DQM1 = 13
6690 00:58:54.570696 DQ Delay:
6691 00:58:54.573533 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6692 00:58:54.577129 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6693 00:58:54.580425 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6694 00:58:54.583558 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6695 00:58:54.583641
6696 00:58:54.583706
6697 00:58:54.583768 ==
6698 00:58:54.586767 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 00:58:54.593199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 00:58:54.593338 ==
6701 00:58:54.593405
6702 00:58:54.593467
6703 00:58:54.593526 TX Vref Scan disable
6704 00:58:54.597449 == TX Byte 0 ==
6705 00:58:54.599829 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6706 00:58:54.603031 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6707 00:58:54.606458 == TX Byte 1 ==
6708 00:58:54.609852 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6709 00:58:54.613265 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6710 00:58:54.613353 ==
6711 00:58:54.616470 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 00:58:54.623183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 00:58:54.623266 ==
6714 00:58:54.623333
6715 00:58:54.623395
6716 00:58:54.626774 TX Vref Scan disable
6717 00:58:54.626857 == TX Byte 0 ==
6718 00:58:54.630542 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6719 00:58:54.636205 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6720 00:58:54.636288 == TX Byte 1 ==
6721 00:58:54.639591 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 00:58:54.646669 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 00:58:54.646752
6724 00:58:54.646818 [DATLAT]
6725 00:58:54.646878 Freq=400, CH1 RK0
6726 00:58:54.646938
6727 00:58:54.649337 DATLAT Default: 0xf
6728 00:58:54.649420 0, 0xFFFF, sum = 0
6729 00:58:54.652731 1, 0xFFFF, sum = 0
6730 00:58:54.655938 2, 0xFFFF, sum = 0
6731 00:58:54.656022 3, 0xFFFF, sum = 0
6732 00:58:54.659226 4, 0xFFFF, sum = 0
6733 00:58:54.659309 5, 0xFFFF, sum = 0
6734 00:58:54.662413 6, 0xFFFF, sum = 0
6735 00:58:54.662496 7, 0xFFFF, sum = 0
6736 00:58:54.666112 8, 0xFFFF, sum = 0
6737 00:58:54.666197 9, 0xFFFF, sum = 0
6738 00:58:54.669243 10, 0xFFFF, sum = 0
6739 00:58:54.669332 11, 0xFFFF, sum = 0
6740 00:58:54.672237 12, 0xFFFF, sum = 0
6741 00:58:54.672321 13, 0x0, sum = 1
6742 00:58:54.675721 14, 0x0, sum = 2
6743 00:58:54.675808 15, 0x0, sum = 3
6744 00:58:54.679038 16, 0x0, sum = 4
6745 00:58:54.679122 best_step = 14
6746 00:58:54.679188
6747 00:58:54.679249 ==
6748 00:58:54.682359 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 00:58:54.688707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 00:58:54.688791 ==
6751 00:58:54.688857 RX Vref Scan: 1
6752 00:58:54.688920
6753 00:58:54.692388 RX Vref 0 -> 0, step: 1
6754 00:58:54.692471
6755 00:58:54.695328 RX Delay -343 -> 252, step: 8
6756 00:58:54.695411
6757 00:58:54.698700 Set Vref, RX VrefLevel [Byte0]: 52
6758 00:58:54.702363 [Byte1]: 53
6759 00:58:54.702482
6760 00:58:54.705134 Final RX Vref Byte 0 = 52 to rank0
6761 00:58:54.708744 Final RX Vref Byte 1 = 53 to rank0
6762 00:58:54.711879 Final RX Vref Byte 0 = 52 to rank1
6763 00:58:54.715237 Final RX Vref Byte 1 = 53 to rank1==
6764 00:58:54.718399 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 00:58:54.722231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 00:58:54.724911 ==
6767 00:58:54.724993 DQS Delay:
6768 00:58:54.725059 DQS0 = 44, DQS1 = 52
6769 00:58:54.728126 DQM Delay:
6770 00:58:54.728246 DQM0 = 9, DQM1 = 10
6771 00:58:54.731890 DQ Delay:
6772 00:58:54.731972 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6773 00:58:54.734757 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6774 00:58:54.738183 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6775 00:58:54.741775 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6776 00:58:54.741858
6777 00:58:54.741924
6778 00:58:54.751545 [DQSOSCAuto] RK0, (LSB)MR18= 0x7097, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6779 00:58:54.754917 CH1 RK0: MR19=C0C, MR18=7097
6780 00:58:54.761156 CH1_RK0: MR19=0xC0C, MR18=0x7097, DQSOSC=390, MR23=63, INC=388, DEC=258
6781 00:58:54.761273 ==
6782 00:58:54.764253 Dram Type= 6, Freq= 0, CH_1, rank 1
6783 00:58:54.768590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 00:58:54.768699 ==
6785 00:58:54.771051 [Gating] SW mode calibration
6786 00:58:54.778211 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6787 00:58:54.784361 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6788 00:58:54.787423 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6789 00:58:54.790781 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6790 00:58:54.797345 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6791 00:58:54.800726 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6792 00:58:54.804052 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6793 00:58:54.810446 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 00:58:54.813948 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6795 00:58:54.817167 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6796 00:58:54.824173 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6797 00:58:54.824256 Total UI for P1: 0, mck2ui 16
6798 00:58:54.830121 best dqsien dly found for B0: ( 0, 14, 24)
6799 00:58:54.830205 Total UI for P1: 0, mck2ui 16
6800 00:58:54.833827 best dqsien dly found for B1: ( 0, 14, 24)
6801 00:58:54.840378 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6802 00:58:54.843168 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6803 00:58:54.843251
6804 00:58:54.846753 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6805 00:58:54.850061 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6806 00:58:54.853462 [Gating] SW calibration Done
6807 00:58:54.853545 ==
6808 00:58:54.856889 Dram Type= 6, Freq= 0, CH_1, rank 1
6809 00:58:54.859699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 00:58:54.859783 ==
6811 00:58:54.863272 RX Vref Scan: 0
6812 00:58:54.863355
6813 00:58:54.863422 RX Vref 0 -> 0, step: 1
6814 00:58:54.863484
6815 00:58:54.866527 RX Delay -410 -> 252, step: 16
6816 00:58:54.873072 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6817 00:58:54.876575 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6818 00:58:54.879458 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6819 00:58:54.882964 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6820 00:58:54.889347 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6821 00:58:54.892870 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6822 00:58:54.896171 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6823 00:58:54.899556 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6824 00:58:54.906285 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6825 00:58:54.909311 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6826 00:58:54.912510 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6827 00:58:54.916381 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6828 00:58:54.922563 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6829 00:58:54.925812 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6830 00:58:54.929452 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6831 00:58:54.935535 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6832 00:58:54.935619 ==
6833 00:58:54.939054 Dram Type= 6, Freq= 0, CH_1, rank 1
6834 00:58:54.942685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 00:58:54.942771 ==
6836 00:58:54.942837 DQS Delay:
6837 00:58:54.945800 DQS0 = 43, DQS1 = 51
6838 00:58:54.945872 DQM Delay:
6839 00:58:54.948640 DQM0 = 9, DQM1 = 14
6840 00:58:54.948716 DQ Delay:
6841 00:58:54.952090 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6842 00:58:54.955476 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6843 00:58:54.959293 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6844 00:58:54.962381 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6845 00:58:54.962466
6846 00:58:54.962531
6847 00:58:54.962592 ==
6848 00:58:54.965439 Dram Type= 6, Freq= 0, CH_1, rank 1
6849 00:58:54.968795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 00:58:54.968872 ==
6851 00:58:54.968935
6852 00:58:54.968994
6853 00:58:54.971961 TX Vref Scan disable
6854 00:58:54.972043 == TX Byte 0 ==
6855 00:58:54.978781 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6856 00:58:54.981754 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6857 00:58:54.985908 == TX Byte 1 ==
6858 00:58:54.988530 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6859 00:58:54.991695 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6860 00:58:54.991778 ==
6861 00:58:54.995578 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 00:58:54.998153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 00:58:55.001508 ==
6864 00:58:55.001591
6865 00:58:55.001656
6866 00:58:55.001717 TX Vref Scan disable
6867 00:58:55.004715 == TX Byte 0 ==
6868 00:58:55.007834 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6869 00:58:55.011476 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6870 00:58:55.014908 == TX Byte 1 ==
6871 00:58:55.018024 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6872 00:58:55.021472 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6873 00:58:55.021570
6874 00:58:55.024690 [DATLAT]
6875 00:58:55.024772 Freq=400, CH1 RK1
6876 00:58:55.024838
6877 00:58:55.027835 DATLAT Default: 0xe
6878 00:58:55.027918 0, 0xFFFF, sum = 0
6879 00:58:55.031190 1, 0xFFFF, sum = 0
6880 00:58:55.031275 2, 0xFFFF, sum = 0
6881 00:58:55.034938 3, 0xFFFF, sum = 0
6882 00:58:55.035022 4, 0xFFFF, sum = 0
6883 00:58:55.037904 5, 0xFFFF, sum = 0
6884 00:58:55.037988 6, 0xFFFF, sum = 0
6885 00:58:55.041032 7, 0xFFFF, sum = 0
6886 00:58:55.041116 8, 0xFFFF, sum = 0
6887 00:58:55.044492 9, 0xFFFF, sum = 0
6888 00:58:55.047899 10, 0xFFFF, sum = 0
6889 00:58:55.048011 11, 0xFFFF, sum = 0
6890 00:58:55.050665 12, 0xFFFF, sum = 0
6891 00:58:55.050749 13, 0x0, sum = 1
6892 00:58:55.054150 14, 0x0, sum = 2
6893 00:58:55.054233 15, 0x0, sum = 3
6894 00:58:55.057370 16, 0x0, sum = 4
6895 00:58:55.057454 best_step = 14
6896 00:58:55.057519
6897 00:58:55.057580 ==
6898 00:58:55.061065 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 00:58:55.064134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 00:58:55.064217 ==
6901 00:58:55.067404 RX Vref Scan: 0
6902 00:58:55.067487
6903 00:58:55.071034 RX Vref 0 -> 0, step: 1
6904 00:58:55.071117
6905 00:58:55.071184 RX Delay -343 -> 252, step: 8
6906 00:58:55.079452 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6907 00:58:55.083085 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6908 00:58:55.085907 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6909 00:58:55.093360 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6910 00:58:55.096040 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6911 00:58:55.099442 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6912 00:58:55.102826 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6913 00:58:55.109192 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6914 00:58:55.112328 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6915 00:58:55.115464 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6916 00:58:55.119419 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6917 00:58:55.125317 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6918 00:58:55.128651 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6919 00:58:55.132097 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6920 00:58:55.135825 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6921 00:58:55.142016 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6922 00:58:55.142100 ==
6923 00:58:55.145131 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 00:58:55.148469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 00:58:55.148554 ==
6926 00:58:55.148619 DQS Delay:
6927 00:58:55.151658 DQS0 = 48, DQS1 = 52
6928 00:58:55.151767 DQM Delay:
6929 00:58:55.155180 DQM0 = 12, DQM1 = 10
6930 00:58:55.155262 DQ Delay:
6931 00:58:55.158623 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6932 00:58:55.161670 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6933 00:58:55.164987 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6934 00:58:55.168537 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6935 00:58:55.168620
6936 00:58:55.168685
6937 00:58:55.178022 [DQSOSCAuto] RK1, (LSB)MR18= 0x71a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6938 00:58:55.178117 CH1 RK1: MR19=C0C, MR18=71A9
6939 00:58:55.184921 CH1_RK1: MR19=0xC0C, MR18=0x71A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6940 00:58:55.187993 [RxdqsGatingPostProcess] freq 400
6941 00:58:55.195339 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6942 00:58:55.198244 best DQS0 dly(2T, 0.5T) = (0, 10)
6943 00:58:55.201501 best DQS1 dly(2T, 0.5T) = (0, 10)
6944 00:58:55.205420 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6945 00:58:55.207963 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6946 00:58:55.211301 best DQS0 dly(2T, 0.5T) = (0, 10)
6947 00:58:55.214642 best DQS1 dly(2T, 0.5T) = (0, 10)
6948 00:58:55.217768 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6949 00:58:55.220797 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6950 00:58:55.220895 Pre-setting of DQS Precalculation
6951 00:58:55.227400 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6952 00:58:55.234361 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6953 00:58:55.240579 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6954 00:58:55.240663
6955 00:58:55.240749
6956 00:58:55.244757 [Calibration Summary] 800 Mbps
6957 00:58:55.247035 CH 0, Rank 0
6958 00:58:55.247133 SW Impedance : PASS
6959 00:58:55.250564 DUTY Scan : NO K
6960 00:58:55.253785 ZQ Calibration : PASS
6961 00:58:55.253865 Jitter Meter : NO K
6962 00:58:55.257318 CBT Training : PASS
6963 00:58:55.260355 Write leveling : PASS
6964 00:58:55.260434 RX DQS gating : PASS
6965 00:58:55.263658 RX DQ/DQS(RDDQC) : PASS
6966 00:58:55.267271 TX DQ/DQS : PASS
6967 00:58:55.267348 RX DATLAT : PASS
6968 00:58:55.270242 RX DQ/DQS(Engine): PASS
6969 00:58:55.273363 TX OE : NO K
6970 00:58:55.273443 All Pass.
6971 00:58:55.273515
6972 00:58:55.273577 CH 0, Rank 1
6973 00:58:55.276728 SW Impedance : PASS
6974 00:58:55.280218 DUTY Scan : NO K
6975 00:58:55.280292 ZQ Calibration : PASS
6976 00:58:55.283466 Jitter Meter : NO K
6977 00:58:55.283543 CBT Training : PASS
6978 00:58:55.286912 Write leveling : NO K
6979 00:58:55.290371 RX DQS gating : PASS
6980 00:58:55.290443 RX DQ/DQS(RDDQC) : PASS
6981 00:58:55.293487 TX DQ/DQS : PASS
6982 00:58:55.297090 RX DATLAT : PASS
6983 00:58:55.297164 RX DQ/DQS(Engine): PASS
6984 00:58:55.300108 TX OE : NO K
6985 00:58:55.300179 All Pass.
6986 00:58:55.300249
6987 00:58:55.303697 CH 1, Rank 0
6988 00:58:55.303767 SW Impedance : PASS
6989 00:58:55.306409 DUTY Scan : NO K
6990 00:58:55.309818 ZQ Calibration : PASS
6991 00:58:55.309898 Jitter Meter : NO K
6992 00:58:55.313099 CBT Training : PASS
6993 00:58:55.316471 Write leveling : PASS
6994 00:58:55.316544 RX DQS gating : PASS
6995 00:58:55.319742 RX DQ/DQS(RDDQC) : PASS
6996 00:58:55.323155 TX DQ/DQS : PASS
6997 00:58:55.323235 RX DATLAT : PASS
6998 00:58:55.326497 RX DQ/DQS(Engine): PASS
6999 00:58:55.329991 TX OE : NO K
7000 00:58:55.330065 All Pass.
7001 00:58:55.330128
7002 00:58:55.330187 CH 1, Rank 1
7003 00:58:55.333424 SW Impedance : PASS
7004 00:58:55.336593 DUTY Scan : NO K
7005 00:58:55.336665 ZQ Calibration : PASS
7006 00:58:55.339844 Jitter Meter : NO K
7007 00:58:55.343414 CBT Training : PASS
7008 00:58:55.343487 Write leveling : NO K
7009 00:58:55.346130 RX DQS gating : PASS
7010 00:58:55.349726 RX DQ/DQS(RDDQC) : PASS
7011 00:58:55.349798 TX DQ/DQS : PASS
7012 00:58:55.352535 RX DATLAT : PASS
7013 00:58:55.352610 RX DQ/DQS(Engine): PASS
7014 00:58:55.356146 TX OE : NO K
7015 00:58:55.356223 All Pass.
7016 00:58:55.356287
7017 00:58:55.359408 DramC Write-DBI off
7018 00:58:55.362686 PER_BANK_REFRESH: Hybrid Mode
7019 00:58:55.362765 TX_TRACKING: ON
7020 00:58:55.372985 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7021 00:58:55.376100 [FAST_K] Save calibration result to emmc
7022 00:58:55.379939 dramc_set_vcore_voltage set vcore to 725000
7023 00:58:55.382652 Read voltage for 1600, 0
7024 00:58:55.382732 Vio18 = 0
7025 00:58:55.386052 Vcore = 725000
7026 00:58:55.386128 Vdram = 0
7027 00:58:55.386198 Vddq = 0
7028 00:58:55.386259 Vmddr = 0
7029 00:58:55.392698 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7030 00:58:55.399164 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7031 00:58:55.399248 MEM_TYPE=3, freq_sel=13
7032 00:58:55.402136 sv_algorithm_assistance_LP4_3733
7033 00:58:55.405792 ============ PULL DRAM RESETB DOWN ============
7034 00:58:55.412865 ========== PULL DRAM RESETB DOWN end =========
7035 00:58:55.416051 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7036 00:58:55.419296 ===================================
7037 00:58:55.422371 LPDDR4 DRAM CONFIGURATION
7038 00:58:55.425588 ===================================
7039 00:58:55.425670 EX_ROW_EN[0] = 0x0
7040 00:58:55.429140 EX_ROW_EN[1] = 0x0
7041 00:58:55.429248 LP4Y_EN = 0x0
7042 00:58:55.431965 WORK_FSP = 0x1
7043 00:58:55.435371 WL = 0x5
7044 00:58:55.435447 RL = 0x5
7045 00:58:55.438512 BL = 0x2
7046 00:58:55.438586 RPST = 0x0
7047 00:58:55.442007 RD_PRE = 0x0
7048 00:58:55.442095 WR_PRE = 0x1
7049 00:58:55.445204 WR_PST = 0x1
7050 00:58:55.445316 DBI_WR = 0x0
7051 00:58:55.448450 DBI_RD = 0x0
7052 00:58:55.448527 OTF = 0x1
7053 00:58:55.451925 ===================================
7054 00:58:55.455037 ===================================
7055 00:58:55.458846 ANA top config
7056 00:58:55.461841 ===================================
7057 00:58:55.461916 DLL_ASYNC_EN = 0
7058 00:58:55.465149 ALL_SLAVE_EN = 0
7059 00:58:55.468044 NEW_RANK_MODE = 1
7060 00:58:55.472148 DLL_IDLE_MODE = 1
7061 00:58:55.474687 LP45_APHY_COMB_EN = 1
7062 00:58:55.474771 TX_ODT_DIS = 0
7063 00:58:55.477977 NEW_8X_MODE = 1
7064 00:58:55.481502 ===================================
7065 00:58:55.484833 ===================================
7066 00:58:55.488088 data_rate = 3200
7067 00:58:55.491379 CKR = 1
7068 00:58:55.494941 DQ_P2S_RATIO = 8
7069 00:58:55.498272 ===================================
7070 00:58:55.501400 CA_P2S_RATIO = 8
7071 00:58:55.501483 DQ_CA_OPEN = 0
7072 00:58:55.504683 DQ_SEMI_OPEN = 0
7073 00:58:55.508422 CA_SEMI_OPEN = 0
7074 00:58:55.511038 CA_FULL_RATE = 0
7075 00:58:55.514290 DQ_CKDIV4_EN = 0
7076 00:58:55.517887 CA_CKDIV4_EN = 0
7077 00:58:55.517968 CA_PREDIV_EN = 0
7078 00:58:55.520906 PH8_DLY = 12
7079 00:58:55.524540 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7080 00:58:55.527824 DQ_AAMCK_DIV = 4
7081 00:58:55.531190 CA_AAMCK_DIV = 4
7082 00:58:55.533938 CA_ADMCK_DIV = 4
7083 00:58:55.534011 DQ_TRACK_CA_EN = 0
7084 00:58:55.537292 CA_PICK = 1600
7085 00:58:55.540514 CA_MCKIO = 1600
7086 00:58:55.544135 MCKIO_SEMI = 0
7087 00:58:55.547571 PLL_FREQ = 3068
7088 00:58:55.550647 DQ_UI_PI_RATIO = 32
7089 00:58:55.553866 CA_UI_PI_RATIO = 0
7090 00:58:55.557025 ===================================
7091 00:58:55.560418 ===================================
7092 00:58:55.564099 memory_type:LPDDR4
7093 00:58:55.564172 GP_NUM : 10
7094 00:58:55.567010 SRAM_EN : 1
7095 00:58:55.567088 MD32_EN : 0
7096 00:58:55.570162 ===================================
7097 00:58:55.573397 [ANA_INIT] >>>>>>>>>>>>>>
7098 00:58:55.576592 <<<<<< [CONFIGURE PHASE]: ANA_TX
7099 00:58:55.580348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7100 00:58:55.583885 ===================================
7101 00:58:55.586756 data_rate = 3200,PCW = 0X7600
7102 00:58:55.590237 ===================================
7103 00:58:55.593492 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7104 00:58:55.600083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7105 00:58:55.603089 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7106 00:58:55.609525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7107 00:58:55.613046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7108 00:58:55.616301 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7109 00:58:55.616379 [ANA_INIT] flow start
7110 00:58:55.619449 [ANA_INIT] PLL >>>>>>>>
7111 00:58:55.623165 [ANA_INIT] PLL <<<<<<<<
7112 00:58:55.623239 [ANA_INIT] MIDPI >>>>>>>>
7113 00:58:55.626185 [ANA_INIT] MIDPI <<<<<<<<
7114 00:58:55.629699 [ANA_INIT] DLL >>>>>>>>
7115 00:58:55.633505 [ANA_INIT] DLL <<<<<<<<
7116 00:58:55.633603 [ANA_INIT] flow end
7117 00:58:55.636172 ============ LP4 DIFF to SE enter ============
7118 00:58:55.642706 ============ LP4 DIFF to SE exit ============
7119 00:58:55.642789 [ANA_INIT] <<<<<<<<<<<<<
7120 00:58:55.646312 [Flow] Enable top DCM control >>>>>
7121 00:58:55.649739 [Flow] Enable top DCM control <<<<<
7122 00:58:55.652811 Enable DLL master slave shuffle
7123 00:58:55.659212 ==============================================================
7124 00:58:55.659297 Gating Mode config
7125 00:58:55.666068 ==============================================================
7126 00:58:55.668957 Config description:
7127 00:58:55.678696 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7128 00:58:55.685526 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7129 00:58:55.689130 SELPH_MODE 0: By rank 1: By Phase
7130 00:58:55.695679 ==============================================================
7131 00:58:55.698879 GAT_TRACK_EN = 1
7132 00:58:55.702286 RX_GATING_MODE = 2
7133 00:58:55.702366 RX_GATING_TRACK_MODE = 2
7134 00:58:55.705169 SELPH_MODE = 1
7135 00:58:55.708703 PICG_EARLY_EN = 1
7136 00:58:55.711664 VALID_LAT_VALUE = 1
7137 00:58:55.718684 ==============================================================
7138 00:58:55.721770 Enter into Gating configuration >>>>
7139 00:58:55.724883 Exit from Gating configuration <<<<
7140 00:58:55.728005 Enter into DVFS_PRE_config >>>>>
7141 00:58:55.738502 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7142 00:58:55.741109 Exit from DVFS_PRE_config <<<<<
7143 00:58:55.744515 Enter into PICG configuration >>>>
7144 00:58:55.748654 Exit from PICG configuration <<<<
7145 00:58:55.751216 [RX_INPUT] configuration >>>>>
7146 00:58:55.754331 [RX_INPUT] configuration <<<<<
7147 00:58:55.757839 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7148 00:58:55.764585 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7149 00:58:55.771041 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7150 00:58:55.777502 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7151 00:58:55.784871 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7152 00:58:55.790726 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7153 00:58:55.794081 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7154 00:58:55.797426 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7155 00:58:55.801237 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7156 00:58:55.807179 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7157 00:58:55.810462 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7158 00:58:55.813876 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7159 00:58:55.816978 ===================================
7160 00:58:55.820129 LPDDR4 DRAM CONFIGURATION
7161 00:58:55.823671 ===================================
7162 00:58:55.823748 EX_ROW_EN[0] = 0x0
7163 00:58:55.827380 EX_ROW_EN[1] = 0x0
7164 00:58:55.829939 LP4Y_EN = 0x0
7165 00:58:55.830015 WORK_FSP = 0x1
7166 00:58:55.833749 WL = 0x5
7167 00:58:55.833829 RL = 0x5
7168 00:58:55.837362 BL = 0x2
7169 00:58:55.837434 RPST = 0x0
7170 00:58:55.839874 RD_PRE = 0x0
7171 00:58:55.839949 WR_PRE = 0x1
7172 00:58:55.843077 WR_PST = 0x1
7173 00:58:55.843149 DBI_WR = 0x0
7174 00:58:55.846795 DBI_RD = 0x0
7175 00:58:55.846868 OTF = 0x1
7176 00:58:55.850315 ===================================
7177 00:58:55.856751 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7178 00:58:55.859612 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7179 00:58:55.863157 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7180 00:58:55.866110 ===================================
7181 00:58:55.870095 LPDDR4 DRAM CONFIGURATION
7182 00:58:55.872984 ===================================
7183 00:58:55.876283 EX_ROW_EN[0] = 0x10
7184 00:58:55.876394 EX_ROW_EN[1] = 0x0
7185 00:58:55.879767 LP4Y_EN = 0x0
7186 00:58:55.879879 WORK_FSP = 0x1
7187 00:58:55.883115 WL = 0x5
7188 00:58:55.883198 RL = 0x5
7189 00:58:55.886372 BL = 0x2
7190 00:58:55.886455 RPST = 0x0
7191 00:58:55.889195 RD_PRE = 0x0
7192 00:58:55.889317 WR_PRE = 0x1
7193 00:58:55.892550 WR_PST = 0x1
7194 00:58:55.892658 DBI_WR = 0x0
7195 00:58:55.896320 DBI_RD = 0x0
7196 00:58:55.896437 OTF = 0x1
7197 00:58:55.899260 ===================================
7198 00:58:55.906130 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7199 00:58:55.906213 ==
7200 00:58:55.909241 Dram Type= 6, Freq= 0, CH_0, rank 0
7201 00:58:55.916037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7202 00:58:55.916147 ==
7203 00:58:55.916231 [Duty_Offset_Calibration]
7204 00:58:55.919029 B0:2 B1:0 CA:4
7205 00:58:55.919111
7206 00:58:55.922410 [DutyScan_Calibration_Flow] k_type=0
7207 00:58:55.931066
7208 00:58:55.931152 ==CLK 0==
7209 00:58:55.934417 Final CLK duty delay cell = -4
7210 00:58:55.937407 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7211 00:58:55.940629 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7212 00:58:55.944098 [-4] AVG Duty = 4922%(X100)
7213 00:58:55.944181
7214 00:58:55.947736 CH0 CLK Duty spec in!! Max-Min= 218%
7215 00:58:55.950860 [DutyScan_Calibration_Flow] ====Done====
7216 00:58:55.950942
7217 00:58:55.953877 [DutyScan_Calibration_Flow] k_type=1
7218 00:58:55.971425
7219 00:58:55.971507 ==DQS 0 ==
7220 00:58:55.974517 Final DQS duty delay cell = 0
7221 00:58:55.977885 [0] MAX Duty = 5218%(X100), DQS PI = 38
7222 00:58:55.981071 [0] MIN Duty = 5093%(X100), DQS PI = 12
7223 00:58:55.984614 [0] AVG Duty = 5155%(X100)
7224 00:58:55.984696
7225 00:58:55.984762 ==DQS 1 ==
7226 00:58:55.987641 Final DQS duty delay cell = 0
7227 00:58:55.991132 [0] MAX Duty = 5156%(X100), DQS PI = 2
7228 00:58:55.994388 [0] MIN Duty = 4969%(X100), DQS PI = 10
7229 00:58:55.997444 [0] AVG Duty = 5062%(X100)
7230 00:58:55.997526
7231 00:58:56.001075 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7232 00:58:56.001157
7233 00:58:56.004438 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7234 00:58:56.007375 [DutyScan_Calibration_Flow] ====Done====
7235 00:58:56.007458
7236 00:58:56.010750 [DutyScan_Calibration_Flow] k_type=3
7237 00:58:56.028260
7238 00:58:56.028342 ==DQM 0 ==
7239 00:58:56.031465 Final DQM duty delay cell = 0
7240 00:58:56.034898 [0] MAX Duty = 5124%(X100), DQS PI = 22
7241 00:58:56.037971 [0] MIN Duty = 4844%(X100), DQS PI = 56
7242 00:58:56.041201 [0] AVG Duty = 4984%(X100)
7243 00:58:56.041305
7244 00:58:56.041372 ==DQM 1 ==
7245 00:58:56.044621 Final DQM duty delay cell = 0
7246 00:58:56.048191 [0] MAX Duty = 5000%(X100), DQS PI = 4
7247 00:58:56.051372 [0] MIN Duty = 4844%(X100), DQS PI = 16
7248 00:58:56.054815 [0] AVG Duty = 4922%(X100)
7249 00:58:56.054898
7250 00:58:56.058136 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7251 00:58:56.058219
7252 00:58:56.061123 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7253 00:58:56.064848 [DutyScan_Calibration_Flow] ====Done====
7254 00:58:56.064930
7255 00:58:56.067793 [DutyScan_Calibration_Flow] k_type=2
7256 00:58:56.085838
7257 00:58:56.085924 ==DQ 0 ==
7258 00:58:56.089217 Final DQ duty delay cell = 0
7259 00:58:56.092094 [0] MAX Duty = 5124%(X100), DQS PI = 20
7260 00:58:56.095500 [0] MIN Duty = 4938%(X100), DQS PI = 12
7261 00:58:56.095583 [0] AVG Duty = 5031%(X100)
7262 00:58:56.098638
7263 00:58:56.098719 ==DQ 1 ==
7264 00:58:56.101829 Final DQ duty delay cell = 0
7265 00:58:56.105416 [0] MAX Duty = 5187%(X100), DQS PI = 2
7266 00:58:56.108839 [0] MIN Duty = 4907%(X100), DQS PI = 34
7267 00:58:56.108962 [0] AVG Duty = 5047%(X100)
7268 00:58:56.112157
7269 00:58:56.115246 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7270 00:58:56.115329
7271 00:58:56.118257 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7272 00:58:56.121944 [DutyScan_Calibration_Flow] ====Done====
7273 00:58:56.122027 ==
7274 00:58:56.125398 Dram Type= 6, Freq= 0, CH_1, rank 0
7275 00:58:56.127977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7276 00:58:56.128060 ==
7277 00:58:56.131399 [Duty_Offset_Calibration]
7278 00:58:56.131481 B0:0 B1:-1 CA:3
7279 00:58:56.131547
7280 00:58:56.134948 [DutyScan_Calibration_Flow] k_type=0
7281 00:58:56.144779
7282 00:58:56.144860 ==CLK 0==
7283 00:58:56.148214 Final CLK duty delay cell = -4
7284 00:58:56.152221 [-4] MAX Duty = 5000%(X100), DQS PI = 6
7285 00:58:56.154758 [-4] MIN Duty = 4813%(X100), DQS PI = 40
7286 00:58:56.158622 [-4] AVG Duty = 4906%(X100)
7287 00:58:56.158705
7288 00:58:56.161179 CH1 CLK Duty spec in!! Max-Min= 187%
7289 00:58:56.165462 [DutyScan_Calibration_Flow] ====Done====
7290 00:58:56.165545
7291 00:58:56.167748 [DutyScan_Calibration_Flow] k_type=1
7292 00:58:56.183807
7293 00:58:56.183937 ==DQS 0 ==
7294 00:58:56.187266 Final DQS duty delay cell = 0
7295 00:58:56.190481 [0] MAX Duty = 5250%(X100), DQS PI = 30
7296 00:58:56.193725 [0] MIN Duty = 4907%(X100), DQS PI = 40
7297 00:58:56.197594 [0] AVG Duty = 5078%(X100)
7298 00:58:56.197682
7299 00:58:56.197746 ==DQS 1 ==
7300 00:58:56.200982 Final DQS duty delay cell = -4
7301 00:58:56.203733 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7302 00:58:56.207324 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7303 00:58:56.210099 [-4] AVG Duty = 4906%(X100)
7304 00:58:56.210180
7305 00:58:56.213639 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7306 00:58:56.213719
7307 00:58:56.216737 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7308 00:58:56.220659 [DutyScan_Calibration_Flow] ====Done====
7309 00:58:56.220744
7310 00:58:56.223293 [DutyScan_Calibration_Flow] k_type=3
7311 00:58:56.241148
7312 00:58:56.241278 ==DQM 0 ==
7313 00:58:56.244811 Final DQM duty delay cell = 0
7314 00:58:56.248040 [0] MAX Duty = 5062%(X100), DQS PI = 30
7315 00:58:56.251090 [0] MIN Duty = 4782%(X100), DQS PI = 40
7316 00:58:56.254919 [0] AVG Duty = 4922%(X100)
7317 00:58:56.255002
7318 00:58:56.255069 ==DQM 1 ==
7319 00:58:56.257869 Final DQM duty delay cell = 0
7320 00:58:56.261089 [0] MAX Duty = 4969%(X100), DQS PI = 30
7321 00:58:56.264456 [0] MIN Duty = 4813%(X100), DQS PI = 62
7322 00:58:56.267927 [0] AVG Duty = 4891%(X100)
7323 00:58:56.268007
7324 00:58:56.270705 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7325 00:58:56.270785
7326 00:58:56.274692 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7327 00:58:56.278110 [DutyScan_Calibration_Flow] ====Done====
7328 00:58:56.278190
7329 00:58:56.280798 [DutyScan_Calibration_Flow] k_type=2
7330 00:58:56.297420
7331 00:58:56.297502 ==DQ 0 ==
7332 00:58:56.301051 Final DQ duty delay cell = -4
7333 00:58:56.303916 [-4] MAX Duty = 4938%(X100), DQS PI = 8
7334 00:58:56.307220 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7335 00:58:56.310368 [-4] AVG Duty = 4875%(X100)
7336 00:58:56.310454
7337 00:58:56.310526 ==DQ 1 ==
7338 00:58:56.313784 Final DQ duty delay cell = 0
7339 00:58:56.317221 [0] MAX Duty = 5031%(X100), DQS PI = 32
7340 00:58:56.320478 [0] MIN Duty = 4875%(X100), DQS PI = 0
7341 00:58:56.323506 [0] AVG Duty = 4953%(X100)
7342 00:58:56.323587
7343 00:58:56.326913 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7344 00:58:56.326994
7345 00:58:56.330499 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7346 00:58:56.333891 [DutyScan_Calibration_Flow] ====Done====
7347 00:58:56.336859 nWR fixed to 30
7348 00:58:56.340155 [ModeRegInit_LP4] CH0 RK0
7349 00:58:56.340235 [ModeRegInit_LP4] CH0 RK1
7350 00:58:56.343581 [ModeRegInit_LP4] CH1 RK0
7351 00:58:56.346726 [ModeRegInit_LP4] CH1 RK1
7352 00:58:56.346814 match AC timing 5
7353 00:58:56.353215 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7354 00:58:56.356864 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7355 00:58:56.360167 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7356 00:58:56.366443 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7357 00:58:56.370297 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7358 00:58:56.370380 [MiockJmeterHQA]
7359 00:58:56.373203
7360 00:58:56.373327 [DramcMiockJmeter] u1RxGatingPI = 0
7361 00:58:56.376430 0 : 4257, 4030
7362 00:58:56.376539 4 : 4253, 4027
7363 00:58:56.379970 8 : 4363, 4137
7364 00:58:56.380053 12 : 4363, 4137
7365 00:58:56.383120 16 : 4363, 4138
7366 00:58:56.383202 20 : 4252, 4027
7367 00:58:56.386530 24 : 4252, 4027
7368 00:58:56.386613 28 : 4252, 4027
7369 00:58:56.386678 32 : 4252, 4026
7370 00:58:56.389750 36 : 4255, 4029
7371 00:58:56.389832 40 : 4363, 4137
7372 00:58:56.392885 44 : 4252, 4027
7373 00:58:56.392967 48 : 4252, 4027
7374 00:58:56.396590 52 : 4252, 4027
7375 00:58:56.396673 56 : 4255, 4029
7376 00:58:56.399893 60 : 4252, 4027
7377 00:58:56.399975 64 : 4363, 4137
7378 00:58:56.400041 68 : 4363, 4137
7379 00:58:56.402880 72 : 4250, 4027
7380 00:58:56.402972 76 : 4250, 4027
7381 00:58:56.405866 80 : 4250, 4027
7382 00:58:56.405948 84 : 4250, 4026
7383 00:58:56.409400 88 : 4253, 4029
7384 00:58:56.409497 92 : 4360, 4138
7385 00:58:56.412737 96 : 4250, 2845
7386 00:58:56.412841 100 : 4250, 0
7387 00:58:56.412969 104 : 4250, 0
7388 00:58:56.415637 108 : 4252, 0
7389 00:58:56.415726 112 : 4250, 0
7390 00:58:56.419201 116 : 4252, 0
7391 00:58:56.419332 120 : 4250, 0
7392 00:58:56.419417 124 : 4250, 0
7393 00:58:56.422755 128 : 4252, 0
7394 00:58:56.422863 132 : 4361, 0
7395 00:58:56.422933 136 : 4360, 0
7396 00:58:56.426100 140 : 4363, 0
7397 00:58:56.426223 144 : 4360, 0
7398 00:58:56.429187 148 : 4250, 0
7399 00:58:56.429321 152 : 4361, 0
7400 00:58:56.429392 156 : 4250, 0
7401 00:58:56.432101 160 : 4250, 0
7402 00:58:56.432185 164 : 4250, 0
7403 00:58:56.435658 168 : 4252, 0
7404 00:58:56.435742 172 : 4250, 0
7405 00:58:56.435810 176 : 4250, 0
7406 00:58:56.439022 180 : 4252, 0
7407 00:58:56.439105 184 : 4361, 0
7408 00:58:56.442138 188 : 4250, 0
7409 00:58:56.442236 192 : 4360, 0
7410 00:58:56.442305 196 : 4250, 0
7411 00:58:56.445683 200 : 4250, 0
7412 00:58:56.445767 204 : 4250, 0
7413 00:58:56.449010 208 : 4250, 0
7414 00:58:56.449132 212 : 4250, 0
7415 00:58:56.449199 216 : 4250, 0
7416 00:58:56.452723 220 : 4252, 620
7417 00:58:56.452807 224 : 4250, 4004
7418 00:58:56.455414 228 : 4250, 4027
7419 00:58:56.455498 232 : 4250, 4027
7420 00:58:56.458563 236 : 4252, 4030
7421 00:58:56.458647 240 : 4249, 4027
7422 00:58:56.462076 244 : 4250, 4026
7423 00:58:56.462160 248 : 4361, 4137
7424 00:58:56.466063 252 : 4250, 4027
7425 00:58:56.466147 256 : 4250, 4027
7426 00:58:56.466214 260 : 4361, 4137
7427 00:58:56.468902 264 : 4250, 4026
7428 00:58:56.468986 268 : 4250, 4027
7429 00:58:56.471975 272 : 4363, 4140
7430 00:58:56.472059 276 : 4249, 4027
7431 00:58:56.475535 280 : 4250, 4027
7432 00:58:56.475618 284 : 4250, 4027
7433 00:58:56.478317 288 : 4252, 4029
7434 00:58:56.478401 292 : 4249, 4027
7435 00:58:56.481918 296 : 4250, 4026
7436 00:58:56.482002 300 : 4361, 4137
7437 00:58:56.484842 304 : 4250, 4027
7438 00:58:56.484925 308 : 4249, 4027
7439 00:58:56.488539 312 : 4360, 4138
7440 00:58:56.488622 316 : 4250, 4027
7441 00:58:56.491875 320 : 4250, 4027
7442 00:58:56.491958 324 : 4363, 4140
7443 00:58:56.492025 328 : 4250, 4027
7444 00:58:56.495288 332 : 4250, 3863
7445 00:58:56.495372 336 : 4250, 1412
7446 00:58:56.495439
7447 00:58:56.498195 MIOCK jitter meter ch=0
7448 00:58:56.498277
7449 00:58:56.502064 1T = (336-100) = 236 dly cells
7450 00:58:56.508920 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7451 00:58:56.509004 ==
7452 00:58:56.511714 Dram Type= 6, Freq= 0, CH_0, rank 0
7453 00:58:56.514854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7454 00:58:56.514936 ==
7455 00:58:56.521399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7456 00:58:56.524576 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7457 00:58:56.528390 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7458 00:58:56.534703 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7459 00:58:56.543826 [CA 0] Center 44 (14~74) winsize 61
7460 00:58:56.547133 [CA 1] Center 43 (13~74) winsize 62
7461 00:58:56.550105 [CA 2] Center 38 (9~68) winsize 60
7462 00:58:56.553497 [CA 3] Center 38 (9~68) winsize 60
7463 00:58:56.556744 [CA 4] Center 36 (7~66) winsize 60
7464 00:58:56.560179 [CA 5] Center 36 (6~66) winsize 61
7465 00:58:56.560261
7466 00:58:56.563858 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7467 00:58:56.563940
7468 00:58:56.570369 [CATrainingPosCal] consider 1 rank data
7469 00:58:56.570450 u2DelayCellTimex100 = 275/100 ps
7470 00:58:56.576838 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7471 00:58:56.580086 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7472 00:58:56.583721 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7473 00:58:56.586358 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7474 00:58:56.589825 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7475 00:58:56.593028 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7476 00:58:56.593109
7477 00:58:56.596140 CA PerBit enable=1, Macro0, CA PI delay=36
7478 00:58:56.596222
7479 00:58:56.599765 [CBTSetCACLKResult] CA Dly = 36
7480 00:58:56.602972 CS Dly: 10 (0~41)
7481 00:58:56.606379 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7482 00:58:56.609627 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7483 00:58:56.609737 ==
7484 00:58:56.612999 Dram Type= 6, Freq= 0, CH_0, rank 1
7485 00:58:56.619600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7486 00:58:56.619683 ==
7487 00:58:56.622742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7488 00:58:56.629464 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7489 00:58:56.632209 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7490 00:58:56.638943 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7491 00:58:56.647362 [CA 0] Center 44 (14~75) winsize 62
7492 00:58:56.650996 [CA 1] Center 44 (14~74) winsize 61
7493 00:58:56.653721 [CA 2] Center 39 (10~69) winsize 60
7494 00:58:56.657308 [CA 3] Center 39 (10~68) winsize 59
7495 00:58:56.660780 [CA 4] Center 37 (7~67) winsize 61
7496 00:58:56.663638 [CA 5] Center 36 (7~66) winsize 60
7497 00:58:56.663747
7498 00:58:56.667064 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7499 00:58:56.667145
7500 00:58:56.670475 [CATrainingPosCal] consider 2 rank data
7501 00:58:56.673760 u2DelayCellTimex100 = 275/100 ps
7502 00:58:56.680263 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7503 00:58:56.683380 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7504 00:58:56.687541 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7505 00:58:56.690062 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7506 00:58:56.693569 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7507 00:58:56.696678 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7508 00:58:56.696759
7509 00:58:56.700616 CA PerBit enable=1, Macro0, CA PI delay=36
7510 00:58:56.700697
7511 00:58:56.703690 [CBTSetCACLKResult] CA Dly = 36
7512 00:58:56.707404 CS Dly: 11 (0~44)
7513 00:58:56.709665 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7514 00:58:56.713025 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7515 00:58:56.713106
7516 00:58:56.716447 ----->DramcWriteLeveling(PI) begin...
7517 00:58:56.721142 ==
7518 00:58:56.723060 Dram Type= 6, Freq= 0, CH_0, rank 0
7519 00:58:56.726236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7520 00:58:56.726318 ==
7521 00:58:56.730087 Write leveling (Byte 0): 34 => 34
7522 00:58:56.732896 Write leveling (Byte 1): 28 => 28
7523 00:58:56.736202 DramcWriteLeveling(PI) end<-----
7524 00:58:56.736283
7525 00:58:56.736346 ==
7526 00:58:56.739362 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 00:58:56.742916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 00:58:56.742999 ==
7529 00:58:56.746110 [Gating] SW mode calibration
7530 00:58:56.753391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7531 00:58:56.759537 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7532 00:58:56.762818 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7533 00:58:56.765793 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7534 00:58:56.772791 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7535 00:58:56.775622 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7536 00:58:56.780428 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7537 00:58:56.785628 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
7538 00:58:56.788804 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7539 00:58:56.792465 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 00:58:56.798553 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7541 00:58:56.802821 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7542 00:58:56.805224 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7543 00:58:56.811973 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7544 00:58:56.815078 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7545 00:58:56.818316 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7546 00:58:56.824763 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 00:58:56.829447 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 00:58:56.831811 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 00:58:56.838221 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 00:58:56.841791 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7551 00:58:56.844863 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7552 00:58:56.851249 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7553 00:58:56.854616 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
7554 00:58:56.857741 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7555 00:58:56.864344 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 00:58:56.868138 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 00:58:56.871446 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 00:58:56.877762 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7559 00:58:56.881150 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7560 00:58:56.884147 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7561 00:58:56.890879 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7562 00:58:56.894154 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7563 00:58:56.897519 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7564 00:58:56.904088 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 00:58:56.907424 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 00:58:56.910525 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 00:58:56.917181 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 00:58:56.920450 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 00:58:56.923938 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 00:58:56.930176 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 00:58:56.933779 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 00:58:56.936952 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 00:58:56.944041 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 00:58:56.946756 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7575 00:58:56.949971 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7576 00:58:56.953409 Total UI for P1: 0, mck2ui 16
7577 00:58:56.956913 best dqsien dly found for B0: ( 1, 9, 8)
7578 00:58:56.963540 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7579 00:58:56.966383 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7580 00:58:56.970361 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 00:58:56.973085 Total UI for P1: 0, mck2ui 16
7582 00:58:56.976213 best dqsien dly found for B1: ( 1, 9, 20)
7583 00:58:56.979487 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7584 00:58:56.983091 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7585 00:58:56.983217
7586 00:58:56.990086 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7587 00:58:56.993212 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7588 00:58:56.996492 [Gating] SW calibration Done
7589 00:58:56.996574 ==
7590 00:58:56.999954 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 00:58:57.003235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 00:58:57.003319 ==
7593 00:58:57.003384 RX Vref Scan: 0
7594 00:58:57.003446
7595 00:58:57.006438 RX Vref 0 -> 0, step: 1
7596 00:58:57.006521
7597 00:58:57.009804 RX Delay 0 -> 252, step: 8
7598 00:58:57.013120 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7599 00:58:57.015830 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7600 00:58:57.022708 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7601 00:58:57.025903 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7602 00:58:57.029435 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7603 00:58:57.033118 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7604 00:58:57.035993 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7605 00:58:57.043215 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7606 00:58:57.045563 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7607 00:58:57.049359 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7608 00:58:57.052298 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7609 00:58:57.055710 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7610 00:58:57.062072 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7611 00:58:57.065709 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7612 00:58:57.068966 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7613 00:58:57.072050 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7614 00:58:57.072133 ==
7615 00:58:57.075446 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 00:58:57.081967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 00:58:57.082078 ==
7618 00:58:57.082174 DQS Delay:
7619 00:58:57.085335 DQS0 = 0, DQS1 = 0
7620 00:58:57.085445 DQM Delay:
7621 00:58:57.089064 DQM0 = 131, DQM1 = 125
7622 00:58:57.089168 DQ Delay:
7623 00:58:57.092078 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =123
7624 00:58:57.095712 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7625 00:58:57.098347 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7626 00:58:57.101897 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7627 00:58:57.101979
7628 00:58:57.102045
7629 00:58:57.102106 ==
7630 00:58:57.105100 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 00:58:57.111586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 00:58:57.111669 ==
7633 00:58:57.111734
7634 00:58:57.111796
7635 00:58:57.111854 TX Vref Scan disable
7636 00:58:57.115372 == TX Byte 0 ==
7637 00:58:57.119085 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7638 00:58:57.125381 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7639 00:58:57.125464 == TX Byte 1 ==
7640 00:58:57.128937 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7641 00:58:57.135230 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7642 00:58:57.135340 ==
7643 00:58:57.138161 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 00:58:57.141988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 00:58:57.142101 ==
7646 00:58:57.155707
7647 00:58:57.159347 TX Vref early break, caculate TX vref
7648 00:58:57.162419 TX Vref=16, minBit 1, minWin=22, winSum=370
7649 00:58:57.165544 TX Vref=18, minBit 4, minWin=23, winSum=384
7650 00:58:57.168832 TX Vref=20, minBit 8, minWin=23, winSum=390
7651 00:58:57.172226 TX Vref=22, minBit 1, minWin=24, winSum=399
7652 00:58:57.175252 TX Vref=24, minBit 7, minWin=24, winSum=414
7653 00:58:57.182104 TX Vref=26, minBit 3, minWin=25, winSum=419
7654 00:58:57.185378 TX Vref=28, minBit 1, minWin=25, winSum=422
7655 00:58:57.189434 TX Vref=30, minBit 4, minWin=24, winSum=418
7656 00:58:57.191818 TX Vref=32, minBit 0, minWin=25, winSum=410
7657 00:58:57.195611 TX Vref=34, minBit 1, minWin=24, winSum=402
7658 00:58:57.202181 TX Vref=36, minBit 1, minWin=23, winSum=387
7659 00:58:57.205564 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
7660 00:58:57.205648
7661 00:58:57.208683 Final TX Range 0 Vref 28
7662 00:58:57.208766
7663 00:58:57.208832 ==
7664 00:58:57.211859 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 00:58:57.214985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 00:58:57.218822 ==
7667 00:58:57.218904
7668 00:58:57.218970
7669 00:58:57.219031 TX Vref Scan disable
7670 00:58:57.225064 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7671 00:58:57.225147 == TX Byte 0 ==
7672 00:58:57.228674 u2DelayCellOfst[0]=14 cells (4 PI)
7673 00:58:57.231653 u2DelayCellOfst[1]=17 cells (5 PI)
7674 00:58:57.235139 u2DelayCellOfst[2]=14 cells (4 PI)
7675 00:58:57.238147 u2DelayCellOfst[3]=14 cells (4 PI)
7676 00:58:57.241723 u2DelayCellOfst[4]=10 cells (3 PI)
7677 00:58:57.244680 u2DelayCellOfst[5]=0 cells (0 PI)
7678 00:58:57.248292 u2DelayCellOfst[6]=17 cells (5 PI)
7679 00:58:57.251738 u2DelayCellOfst[7]=17 cells (5 PI)
7680 00:58:57.256866 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7681 00:58:57.260900 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7682 00:58:57.261009 == TX Byte 1 ==
7683 00:58:57.265019 u2DelayCellOfst[8]=0 cells (0 PI)
7684 00:58:57.267650 u2DelayCellOfst[9]=0 cells (0 PI)
7685 00:58:57.270931 u2DelayCellOfst[10]=7 cells (2 PI)
7686 00:58:57.274335 u2DelayCellOfst[11]=0 cells (0 PI)
7687 00:58:57.277882 u2DelayCellOfst[12]=10 cells (3 PI)
7688 00:58:57.280552 u2DelayCellOfst[13]=10 cells (3 PI)
7689 00:58:57.284420 u2DelayCellOfst[14]=14 cells (4 PI)
7690 00:58:57.287357 u2DelayCellOfst[15]=10 cells (3 PI)
7691 00:58:57.291108 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7692 00:58:57.293715 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7693 00:58:57.297311 DramC Write-DBI on
7694 00:58:57.297393 ==
7695 00:58:57.300358 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 00:58:57.303864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 00:58:57.303939 ==
7698 00:58:57.304002
7699 00:58:57.304071
7700 00:58:57.306973 TX Vref Scan disable
7701 00:58:57.310578 == TX Byte 0 ==
7702 00:58:57.313760 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7703 00:58:57.313838 == TX Byte 1 ==
7704 00:58:57.320151 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7705 00:58:57.320252 DramC Write-DBI off
7706 00:58:57.320355
7707 00:58:57.320451 [DATLAT]
7708 00:58:57.323369 Freq=1600, CH0 RK0
7709 00:58:57.323468
7710 00:58:57.327415 DATLAT Default: 0xf
7711 00:58:57.327488 0, 0xFFFF, sum = 0
7712 00:58:57.330162 1, 0xFFFF, sum = 0
7713 00:58:57.330238 2, 0xFFFF, sum = 0
7714 00:58:57.333652 3, 0xFFFF, sum = 0
7715 00:58:57.333736 4, 0xFFFF, sum = 0
7716 00:58:57.337373 5, 0xFFFF, sum = 0
7717 00:58:57.337448 6, 0xFFFF, sum = 0
7718 00:58:57.340411 7, 0xFFFF, sum = 0
7719 00:58:57.340483 8, 0xFFFF, sum = 0
7720 00:58:57.343168 9, 0xFFFF, sum = 0
7721 00:58:57.343242 10, 0xFFFF, sum = 0
7722 00:58:57.347091 11, 0xFFFF, sum = 0
7723 00:58:57.347183 12, 0xFFFF, sum = 0
7724 00:58:57.349815 13, 0xFFFF, sum = 0
7725 00:58:57.349888 14, 0x0, sum = 1
7726 00:58:57.353721 15, 0x0, sum = 2
7727 00:58:57.353793 16, 0x0, sum = 3
7728 00:58:57.356601 17, 0x0, sum = 4
7729 00:58:57.356675 best_step = 15
7730 00:58:57.356752
7731 00:58:57.356830 ==
7732 00:58:57.360129 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 00:58:57.366575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 00:58:57.366652 ==
7735 00:58:57.366738 RX Vref Scan: 1
7736 00:58:57.366818
7737 00:58:57.369768 Set Vref Range= 24 -> 127
7738 00:58:57.369841
7739 00:58:57.373075 RX Vref 24 -> 127, step: 1
7740 00:58:57.373165
7741 00:58:57.376228 RX Delay 11 -> 252, step: 4
7742 00:58:57.376305
7743 00:58:57.379677 Set Vref, RX VrefLevel [Byte0]: 24
7744 00:58:57.382955 [Byte1]: 24
7745 00:58:57.383029
7746 00:58:57.386064 Set Vref, RX VrefLevel [Byte0]: 25
7747 00:58:57.389321 [Byte1]: 25
7748 00:58:57.389398
7749 00:58:57.392757 Set Vref, RX VrefLevel [Byte0]: 26
7750 00:58:57.395774 [Byte1]: 26
7751 00:58:57.399348
7752 00:58:57.399425 Set Vref, RX VrefLevel [Byte0]: 27
7753 00:58:57.403171 [Byte1]: 27
7754 00:58:57.407344
7755 00:58:57.407451 Set Vref, RX VrefLevel [Byte0]: 28
7756 00:58:57.410643 [Byte1]: 28
7757 00:58:57.415136
7758 00:58:57.415213 Set Vref, RX VrefLevel [Byte0]: 29
7759 00:58:57.417793 [Byte1]: 29
7760 00:58:57.422343
7761 00:58:57.422422 Set Vref, RX VrefLevel [Byte0]: 30
7762 00:58:57.425877 [Byte1]: 30
7763 00:58:57.430563
7764 00:58:57.430636 Set Vref, RX VrefLevel [Byte0]: 31
7765 00:58:57.433227 [Byte1]: 31
7766 00:58:57.437756
7767 00:58:57.437829 Set Vref, RX VrefLevel [Byte0]: 32
7768 00:58:57.440596 [Byte1]: 32
7769 00:58:57.445352
7770 00:58:57.445426 Set Vref, RX VrefLevel [Byte0]: 33
7771 00:58:57.448538 [Byte1]: 33
7772 00:58:57.453002
7773 00:58:57.453069 Set Vref, RX VrefLevel [Byte0]: 34
7774 00:58:57.456106 [Byte1]: 34
7775 00:58:57.460377
7776 00:58:57.460487 Set Vref, RX VrefLevel [Byte0]: 35
7777 00:58:57.463625 [Byte1]: 35
7778 00:58:57.467996
7779 00:58:57.468065 Set Vref, RX VrefLevel [Byte0]: 36
7780 00:58:57.471221 [Byte1]: 36
7781 00:58:57.475680
7782 00:58:57.475753 Set Vref, RX VrefLevel [Byte0]: 37
7783 00:58:57.479040 [Byte1]: 37
7784 00:58:57.483786
7785 00:58:57.483859 Set Vref, RX VrefLevel [Byte0]: 38
7786 00:58:57.486951 [Byte1]: 38
7787 00:58:57.491087
7788 00:58:57.491160 Set Vref, RX VrefLevel [Byte0]: 39
7789 00:58:57.494405 [Byte1]: 39
7790 00:58:57.498365
7791 00:58:57.498441 Set Vref, RX VrefLevel [Byte0]: 40
7792 00:58:57.501942 [Byte1]: 40
7793 00:58:57.506244
7794 00:58:57.506320 Set Vref, RX VrefLevel [Byte0]: 41
7795 00:58:57.509550 [Byte1]: 41
7796 00:58:57.513473
7797 00:58:57.513552 Set Vref, RX VrefLevel [Byte0]: 42
7798 00:58:57.517104 [Byte1]: 42
7799 00:58:57.521795
7800 00:58:57.521882 Set Vref, RX VrefLevel [Byte0]: 43
7801 00:58:57.524616 [Byte1]: 43
7802 00:58:57.528926
7803 00:58:57.529037 Set Vref, RX VrefLevel [Byte0]: 44
7804 00:58:57.532319 [Byte1]: 44
7805 00:58:57.536715
7806 00:58:57.536806 Set Vref, RX VrefLevel [Byte0]: 45
7807 00:58:57.539745 [Byte1]: 45
7808 00:58:57.544390
7809 00:58:57.544471 Set Vref, RX VrefLevel [Byte0]: 46
7810 00:58:57.547512 [Byte1]: 46
7811 00:58:57.551858
7812 00:58:57.551974 Set Vref, RX VrefLevel [Byte0]: 47
7813 00:58:57.555028 [Byte1]: 47
7814 00:58:57.559433
7815 00:58:57.559533 Set Vref, RX VrefLevel [Byte0]: 48
7816 00:58:57.562751 [Byte1]: 48
7817 00:58:57.567152
7818 00:58:57.567232 Set Vref, RX VrefLevel [Byte0]: 49
7819 00:58:57.570275 [Byte1]: 49
7820 00:58:57.574685
7821 00:58:57.574789 Set Vref, RX VrefLevel [Byte0]: 50
7822 00:58:57.578150 [Byte1]: 50
7823 00:58:57.583326
7824 00:58:57.583402 Set Vref, RX VrefLevel [Byte0]: 51
7825 00:58:57.585432 [Byte1]: 51
7826 00:58:57.590323
7827 00:58:57.590405 Set Vref, RX VrefLevel [Byte0]: 52
7828 00:58:57.593012 [Byte1]: 52
7829 00:58:57.597207
7830 00:58:57.597326 Set Vref, RX VrefLevel [Byte0]: 53
7831 00:58:57.601439 [Byte1]: 53
7832 00:58:57.605652
7833 00:58:57.605734 Set Vref, RX VrefLevel [Byte0]: 54
7834 00:58:57.608573 [Byte1]: 54
7835 00:58:57.612894
7836 00:58:57.613001 Set Vref, RX VrefLevel [Byte0]: 55
7837 00:58:57.616258 [Byte1]: 55
7838 00:58:57.620134
7839 00:58:57.620242 Set Vref, RX VrefLevel [Byte0]: 56
7840 00:58:57.623516 [Byte1]: 56
7841 00:58:57.628091
7842 00:58:57.628195 Set Vref, RX VrefLevel [Byte0]: 57
7843 00:58:57.631578 [Byte1]: 57
7844 00:58:57.635324
7845 00:58:57.635401 Set Vref, RX VrefLevel [Byte0]: 58
7846 00:58:57.638832 [Byte1]: 58
7847 00:58:57.643610
7848 00:58:57.643712 Set Vref, RX VrefLevel [Byte0]: 59
7849 00:58:57.646504 [Byte1]: 59
7850 00:58:57.650883
7851 00:58:57.650957 Set Vref, RX VrefLevel [Byte0]: 60
7852 00:58:57.657459 [Byte1]: 60
7853 00:58:57.657563
7854 00:58:57.660570 Set Vref, RX VrefLevel [Byte0]: 61
7855 00:58:57.663947 [Byte1]: 61
7856 00:58:57.664032
7857 00:58:57.667007 Set Vref, RX VrefLevel [Byte0]: 62
7858 00:58:57.670385 [Byte1]: 62
7859 00:58:57.673581
7860 00:58:57.673656 Set Vref, RX VrefLevel [Byte0]: 63
7861 00:58:57.677339 [Byte1]: 63
7862 00:58:57.680946
7863 00:58:57.681025 Set Vref, RX VrefLevel [Byte0]: 64
7864 00:58:57.684406 [Byte1]: 64
7865 00:58:57.688591
7866 00:58:57.688664 Set Vref, RX VrefLevel [Byte0]: 65
7867 00:58:57.692016 [Byte1]: 65
7868 00:58:57.696591
7869 00:58:57.696699 Set Vref, RX VrefLevel [Byte0]: 66
7870 00:58:57.699647 [Byte1]: 66
7871 00:58:57.704173
7872 00:58:57.704249 Set Vref, RX VrefLevel [Byte0]: 67
7873 00:58:57.707274 [Byte1]: 67
7874 00:58:57.711837
7875 00:58:57.711915 Set Vref, RX VrefLevel [Byte0]: 68
7876 00:58:57.714971 [Byte1]: 68
7877 00:58:57.719267
7878 00:58:57.719343 Set Vref, RX VrefLevel [Byte0]: 69
7879 00:58:57.722571 [Byte1]: 69
7880 00:58:57.726861
7881 00:58:57.726944 Set Vref, RX VrefLevel [Byte0]: 70
7882 00:58:57.730192 [Byte1]: 70
7883 00:58:57.734265
7884 00:58:57.734365 Set Vref, RX VrefLevel [Byte0]: 71
7885 00:58:57.737865 [Byte1]: 71
7886 00:58:57.742704
7887 00:58:57.742778 Set Vref, RX VrefLevel [Byte0]: 72
7888 00:58:57.745984 [Byte1]: 72
7889 00:58:57.749684
7890 00:58:57.749759 Set Vref, RX VrefLevel [Byte0]: 73
7891 00:58:57.753081 [Byte1]: 73
7892 00:58:57.757393
7893 00:58:57.757468 Set Vref, RX VrefLevel [Byte0]: 74
7894 00:58:57.761061 [Byte1]: 74
7895 00:58:57.765205
7896 00:58:57.765309 Final RX Vref Byte 0 = 55 to rank0
7897 00:58:57.768543 Final RX Vref Byte 1 = 61 to rank0
7898 00:58:57.771947 Final RX Vref Byte 0 = 55 to rank1
7899 00:58:57.775465 Final RX Vref Byte 1 = 61 to rank1==
7900 00:58:57.778556 Dram Type= 6, Freq= 0, CH_0, rank 0
7901 00:58:57.784922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7902 00:58:57.785005 ==
7903 00:58:57.785071 DQS Delay:
7904 00:58:57.787858 DQS0 = 0, DQS1 = 0
7905 00:58:57.787931 DQM Delay:
7906 00:58:57.787993 DQM0 = 128, DQM1 = 124
7907 00:58:57.791613 DQ Delay:
7908 00:58:57.794777 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7909 00:58:57.798263 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7910 00:58:57.801679 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
7911 00:58:57.804367 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7912 00:58:57.804469
7913 00:58:57.804563
7914 00:58:57.804650
7915 00:58:57.807714 [DramC_TX_OE_Calibration] TA2
7916 00:58:57.810962 Original DQ_B0 (3 6) =30, OEN = 27
7917 00:58:57.814501 Original DQ_B1 (3 6) =30, OEN = 27
7918 00:58:57.818483 24, 0x0, End_B0=24 End_B1=24
7919 00:58:57.818564 25, 0x0, End_B0=25 End_B1=25
7920 00:58:57.821293 26, 0x0, End_B0=26 End_B1=26
7921 00:58:57.824403 27, 0x0, End_B0=27 End_B1=27
7922 00:58:57.827881 28, 0x0, End_B0=28 End_B1=28
7923 00:58:57.831087 29, 0x0, End_B0=29 End_B1=29
7924 00:58:57.831164 30, 0x0, End_B0=30 End_B1=30
7925 00:58:57.834137 31, 0x4141, End_B0=30 End_B1=30
7926 00:58:57.837402 Byte0 end_step=30 best_step=27
7927 00:58:57.840723 Byte1 end_step=30 best_step=27
7928 00:58:57.844015 Byte0 TX OE(2T, 0.5T) = (3, 3)
7929 00:58:57.847357 Byte1 TX OE(2T, 0.5T) = (3, 3)
7930 00:58:57.847433
7931 00:58:57.847513
7932 00:58:57.854352 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
7933 00:58:57.857098 CH0 RK0: MR19=303, MR18=1A18
7934 00:58:57.863833 CH0_RK0: MR19=0x303, MR18=0x1A18, DQSOSC=396, MR23=63, INC=23, DEC=15
7935 00:58:57.863910
7936 00:58:57.866775 ----->DramcWriteLeveling(PI) begin...
7937 00:58:57.866853 ==
7938 00:58:57.870200 Dram Type= 6, Freq= 0, CH_0, rank 1
7939 00:58:57.873312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7940 00:58:57.873389 ==
7941 00:58:57.876941 Write leveling (Byte 0): 32 => 32
7942 00:58:57.880294 Write leveling (Byte 1): 29 => 29
7943 00:58:57.883473 DramcWriteLeveling(PI) end<-----
7944 00:58:57.883549
7945 00:58:57.883628 ==
7946 00:58:57.886624 Dram Type= 6, Freq= 0, CH_0, rank 1
7947 00:58:57.893189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7948 00:58:57.893341 ==
7949 00:58:57.893442 [Gating] SW mode calibration
7950 00:58:57.903396 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7951 00:58:57.906625 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7952 00:58:57.913175 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7953 00:58:57.916266 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7954 00:58:57.919863 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7955 00:58:57.926262 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7956 00:58:57.929596 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7957 00:58:57.933143 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7958 00:58:57.939518 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7959 00:58:57.942635 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7960 00:58:57.945913 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7961 00:58:57.949406 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7962 00:58:57.955938 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
7963 00:58:57.959716 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7964 00:58:57.962952 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7965 00:58:57.969329 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7966 00:58:57.972839 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 00:58:57.975956 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 00:58:57.982561 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7969 00:58:57.985680 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7970 00:58:57.989038 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7971 00:58:57.995400 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7972 00:58:57.999461 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7973 00:58:58.005221 1 6 20 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7974 00:58:58.008528 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7975 00:58:58.012149 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7976 00:58:58.018676 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7977 00:58:58.021660 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 00:58:58.025144 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7979 00:58:58.028239 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7980 00:58:58.035539 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7981 00:58:58.038298 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7982 00:58:58.041736 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 00:58:58.048078 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 00:58:58.051255 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 00:58:58.057964 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 00:58:58.061510 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 00:58:58.064665 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 00:58:58.071035 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 00:58:58.074619 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 00:58:58.078144 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 00:58:58.084293 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 00:58:58.087798 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 00:58:58.091107 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7994 00:58:58.097605 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7995 00:58:58.100683 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7996 00:58:58.104205 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7997 00:58:58.107226 Total UI for P1: 0, mck2ui 16
7998 00:58:58.110460 best dqsien dly found for B0: ( 1, 9, 8)
7999 00:58:58.117710 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8000 00:58:58.121094 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 00:58:58.123789 Total UI for P1: 0, mck2ui 16
8002 00:58:58.127923 best dqsien dly found for B1: ( 1, 9, 18)
8003 00:58:58.130373 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8004 00:58:58.134018 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8005 00:58:58.134095
8006 00:58:58.137205 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8007 00:58:58.140344 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8008 00:58:58.143801 [Gating] SW calibration Done
8009 00:58:58.143876 ==
8010 00:58:58.146922 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 00:58:58.150540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 00:58:58.153387 ==
8013 00:58:58.153473 RX Vref Scan: 0
8014 00:58:58.153545
8015 00:58:58.157031 RX Vref 0 -> 0, step: 1
8016 00:58:58.157107
8017 00:58:58.157176 RX Delay 0 -> 252, step: 8
8018 00:58:58.163123 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8019 00:58:58.166566 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8020 00:58:58.169570 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8021 00:58:58.173095 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8022 00:58:58.179870 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8023 00:58:58.183067 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8024 00:58:58.186719 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8025 00:58:58.189819 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8026 00:58:58.193317 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8027 00:58:58.199827 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8028 00:58:58.202568 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8029 00:58:58.206445 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8030 00:58:58.208947 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8031 00:58:58.212595 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8032 00:58:58.219435 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8033 00:58:58.222395 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8034 00:58:58.222476 ==
8035 00:58:58.226134 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 00:58:58.229022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 00:58:58.229130 ==
8038 00:58:58.232671 DQS Delay:
8039 00:58:58.232769 DQS0 = 0, DQS1 = 0
8040 00:58:58.235767 DQM Delay:
8041 00:58:58.235841 DQM0 = 131, DQM1 = 124
8042 00:58:58.235941 DQ Delay:
8043 00:58:58.238692 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8044 00:58:58.245332 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =135
8045 00:58:58.248889 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =115
8046 00:58:58.252766 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8047 00:58:58.252848
8048 00:58:58.252912
8049 00:58:58.252971 ==
8050 00:58:58.255314 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 00:58:58.259115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 00:58:58.259191 ==
8053 00:58:58.259260
8054 00:58:58.259324
8055 00:58:58.262002 TX Vref Scan disable
8056 00:58:58.265179 == TX Byte 0 ==
8057 00:58:58.268867 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8058 00:58:58.271719 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8059 00:58:58.275255 == TX Byte 1 ==
8060 00:58:58.278854 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8061 00:58:58.282068 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8062 00:58:58.282148 ==
8063 00:58:58.285030 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 00:58:58.291466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 00:58:58.291562 ==
8066 00:58:58.305151
8067 00:58:58.307817 TX Vref early break, caculate TX vref
8068 00:58:58.310944 TX Vref=16, minBit 1, minWin=23, winSum=382
8069 00:58:58.314101 TX Vref=18, minBit 8, minWin=23, winSum=388
8070 00:58:58.318136 TX Vref=20, minBit 4, minWin=24, winSum=400
8071 00:58:58.321205 TX Vref=22, minBit 0, minWin=25, winSum=403
8072 00:58:58.324139 TX Vref=24, minBit 1, minWin=25, winSum=416
8073 00:58:58.330671 TX Vref=26, minBit 0, minWin=26, winSum=423
8074 00:58:58.333907 TX Vref=28, minBit 0, minWin=26, winSum=424
8075 00:58:58.337092 TX Vref=30, minBit 1, minWin=25, winSum=416
8076 00:58:58.340200 TX Vref=32, minBit 1, minWin=25, winSum=413
8077 00:58:58.344309 TX Vref=34, minBit 1, minWin=24, winSum=403
8078 00:58:58.350519 TX Vref=36, minBit 0, minWin=24, winSum=393
8079 00:58:58.353672 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8080 00:58:58.353763
8081 00:58:58.358039 Final TX Range 0 Vref 28
8082 00:58:58.358114
8083 00:58:58.358187 ==
8084 00:58:58.360733 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 00:58:58.363794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 00:58:58.367108 ==
8087 00:58:58.367189
8088 00:58:58.367256
8089 00:58:58.367316 TX Vref Scan disable
8090 00:58:58.373537 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8091 00:58:58.373614 == TX Byte 0 ==
8092 00:58:58.377127 u2DelayCellOfst[0]=10 cells (3 PI)
8093 00:58:58.380250 u2DelayCellOfst[1]=14 cells (4 PI)
8094 00:58:58.383611 u2DelayCellOfst[2]=7 cells (2 PI)
8095 00:58:58.386855 u2DelayCellOfst[3]=10 cells (3 PI)
8096 00:58:58.390043 u2DelayCellOfst[4]=7 cells (2 PI)
8097 00:58:58.393344 u2DelayCellOfst[5]=0 cells (0 PI)
8098 00:58:58.396620 u2DelayCellOfst[6]=14 cells (4 PI)
8099 00:58:58.400279 u2DelayCellOfst[7]=14 cells (4 PI)
8100 00:58:58.403466 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8101 00:58:58.407014 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8102 00:58:58.409900 == TX Byte 1 ==
8103 00:58:58.413488 u2DelayCellOfst[8]=0 cells (0 PI)
8104 00:58:58.416442 u2DelayCellOfst[9]=0 cells (0 PI)
8105 00:58:58.419542 u2DelayCellOfst[10]=3 cells (1 PI)
8106 00:58:58.423147 u2DelayCellOfst[11]=3 cells (1 PI)
8107 00:58:58.426529 u2DelayCellOfst[12]=10 cells (3 PI)
8108 00:58:58.429813 u2DelayCellOfst[13]=10 cells (3 PI)
8109 00:58:58.429895 u2DelayCellOfst[14]=17 cells (5 PI)
8110 00:58:58.432628 u2DelayCellOfst[15]=10 cells (3 PI)
8111 00:58:58.439236 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8112 00:58:58.443088 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8113 00:58:58.445967 DramC Write-DBI on
8114 00:58:58.446042 ==
8115 00:58:58.449813 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 00:58:58.452659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 00:58:58.452762 ==
8118 00:58:58.452846
8119 00:58:58.452914
8120 00:58:58.455793 TX Vref Scan disable
8121 00:58:58.455861 == TX Byte 0 ==
8122 00:58:58.462802 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8123 00:58:58.462879 == TX Byte 1 ==
8124 00:58:58.465459 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8125 00:58:58.469094 DramC Write-DBI off
8126 00:58:58.469176
8127 00:58:58.469239 [DATLAT]
8128 00:58:58.472063 Freq=1600, CH0 RK1
8129 00:58:58.472168
8130 00:58:58.472236 DATLAT Default: 0xf
8131 00:58:58.475642 0, 0xFFFF, sum = 0
8132 00:58:58.479022 1, 0xFFFF, sum = 0
8133 00:58:58.479100 2, 0xFFFF, sum = 0
8134 00:58:58.482291 3, 0xFFFF, sum = 0
8135 00:58:58.482367 4, 0xFFFF, sum = 0
8136 00:58:58.486333 5, 0xFFFF, sum = 0
8137 00:58:58.486418 6, 0xFFFF, sum = 0
8138 00:58:58.488843 7, 0xFFFF, sum = 0
8139 00:58:58.488926 8, 0xFFFF, sum = 0
8140 00:58:58.492127 9, 0xFFFF, sum = 0
8141 00:58:58.492204 10, 0xFFFF, sum = 0
8142 00:58:58.495314 11, 0xFFFF, sum = 0
8143 00:58:58.495391 12, 0xFFFF, sum = 0
8144 00:58:58.499041 13, 0xFFFF, sum = 0
8145 00:58:58.499118 14, 0x0, sum = 1
8146 00:58:58.502401 15, 0x0, sum = 2
8147 00:58:58.502477 16, 0x0, sum = 3
8148 00:58:58.505118 17, 0x0, sum = 4
8149 00:58:58.505192 best_step = 15
8150 00:58:58.505285
8151 00:58:58.505364 ==
8152 00:58:58.509104 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 00:58:58.515586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 00:58:58.515700 ==
8155 00:58:58.515795 RX Vref Scan: 0
8156 00:58:58.515904
8157 00:58:58.518367 RX Vref 0 -> 0, step: 1
8158 00:58:58.518436
8159 00:58:58.522264 RX Delay 11 -> 252, step: 4
8160 00:58:58.525059 iDelay=187, Bit 0, Center 128 (79 ~ 178) 100
8161 00:58:58.528398 iDelay=187, Bit 1, Center 130 (79 ~ 182) 104
8162 00:58:58.531821 iDelay=187, Bit 2, Center 126 (75 ~ 178) 104
8163 00:58:58.538404 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8164 00:58:58.542029 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8165 00:58:58.545013 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8166 00:58:58.548766 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8167 00:58:58.551573 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8168 00:58:58.558246 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8169 00:58:58.561665 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8170 00:58:58.565289 iDelay=187, Bit 10, Center 128 (75 ~ 182) 108
8171 00:58:58.567900 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8172 00:58:58.574306 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8173 00:58:58.577717 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8174 00:58:58.580993 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8175 00:58:58.584216 iDelay=187, Bit 15, Center 130 (79 ~ 182) 104
8176 00:58:58.584301 ==
8177 00:58:58.587945 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 00:58:58.594422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 00:58:58.594501 ==
8180 00:58:58.594575 DQS Delay:
8181 00:58:58.597922 DQS0 = 0, DQS1 = 0
8182 00:58:58.597996 DQM Delay:
8183 00:58:58.598068 DQM0 = 129, DQM1 = 123
8184 00:58:58.600991 DQ Delay:
8185 00:58:58.604592 DQ0 =128, DQ1 =130, DQ2 =126, DQ3 =126
8186 00:58:58.607771 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =134
8187 00:58:58.610745 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =118
8188 00:58:58.613915 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8189 00:58:58.613993
8190 00:58:58.614079
8191 00:58:58.614155
8192 00:58:58.617180 [DramC_TX_OE_Calibration] TA2
8193 00:58:58.620483 Original DQ_B0 (3 6) =30, OEN = 27
8194 00:58:58.624521 Original DQ_B1 (3 6) =30, OEN = 27
8195 00:58:58.627294 24, 0x0, End_B0=24 End_B1=24
8196 00:58:58.630771 25, 0x0, End_B0=25 End_B1=25
8197 00:58:58.630845 26, 0x0, End_B0=26 End_B1=26
8198 00:58:58.634115 27, 0x0, End_B0=27 End_B1=27
8199 00:58:58.637515 28, 0x0, End_B0=28 End_B1=28
8200 00:58:58.640569 29, 0x0, End_B0=29 End_B1=29
8201 00:58:58.640648 30, 0x0, End_B0=30 End_B1=30
8202 00:58:58.643582 31, 0x4141, End_B0=30 End_B1=30
8203 00:58:58.646964 Byte0 end_step=30 best_step=27
8204 00:58:58.650018 Byte1 end_step=30 best_step=27
8205 00:58:58.653187 Byte0 TX OE(2T, 0.5T) = (3, 3)
8206 00:58:58.657152 Byte1 TX OE(2T, 0.5T) = (3, 3)
8207 00:58:58.657285
8208 00:58:58.657386
8209 00:58:58.663362 [DQSOSCAuto] RK1, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8210 00:58:58.666714 CH0 RK1: MR19=303, MR18=1312
8211 00:58:58.673682 CH0_RK1: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
8212 00:58:58.677000 [RxdqsGatingPostProcess] freq 1600
8213 00:58:58.682944 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8214 00:58:58.683025 best DQS0 dly(2T, 0.5T) = (1, 1)
8215 00:58:58.686711 best DQS1 dly(2T, 0.5T) = (1, 1)
8216 00:58:58.689679 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8217 00:58:58.693208 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8218 00:58:58.696467 best DQS0 dly(2T, 0.5T) = (1, 1)
8219 00:58:58.700006 best DQS1 dly(2T, 0.5T) = (1, 1)
8220 00:58:58.703098 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8221 00:58:58.706745 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8222 00:58:58.709499 Pre-setting of DQS Precalculation
8223 00:58:58.713024 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8224 00:58:58.715804 ==
8225 00:58:58.719366 Dram Type= 6, Freq= 0, CH_1, rank 0
8226 00:58:58.722404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 00:58:58.722488 ==
8228 00:58:58.728867 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8229 00:58:58.732312 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8230 00:58:58.735616 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8231 00:58:58.742371 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8232 00:58:58.750677 [CA 0] Center 42 (12~72) winsize 61
8233 00:58:58.754001 [CA 1] Center 41 (11~72) winsize 62
8234 00:58:58.757142 [CA 2] Center 38 (9~67) winsize 59
8235 00:58:58.760345 [CA 3] Center 36 (7~66) winsize 60
8236 00:58:58.763579 [CA 4] Center 37 (8~67) winsize 60
8237 00:58:58.767411 [CA 5] Center 36 (7~66) winsize 60
8238 00:58:58.767509
8239 00:58:58.770669 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8240 00:58:58.770743
8241 00:58:58.777225 [CATrainingPosCal] consider 1 rank data
8242 00:58:58.777322 u2DelayCellTimex100 = 275/100 ps
8243 00:58:58.783372 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8244 00:58:58.786734 CA1 delay=41 (11~72),Diff = 5 PI (17 cell)
8245 00:58:58.790561 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8246 00:58:58.793133 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8247 00:58:58.796802 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8248 00:58:58.799802 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8249 00:58:58.799914
8250 00:58:58.803002 CA PerBit enable=1, Macro0, CA PI delay=36
8251 00:58:58.803105
8252 00:58:58.806435 [CBTSetCACLKResult] CA Dly = 36
8253 00:58:58.810140 CS Dly: 8 (0~39)
8254 00:58:58.813309 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8255 00:58:58.816334 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8256 00:58:58.816425 ==
8257 00:58:58.819837 Dram Type= 6, Freq= 0, CH_1, rank 1
8258 00:58:58.826594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 00:58:58.826782 ==
8260 00:58:58.830194 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8261 00:58:58.836150 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8262 00:58:58.839430 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8263 00:58:58.846191 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8264 00:58:58.853993 [CA 0] Center 42 (12~72) winsize 61
8265 00:58:58.857187 [CA 1] Center 42 (13~72) winsize 60
8266 00:58:58.860725 [CA 2] Center 38 (8~68) winsize 61
8267 00:58:58.863702 [CA 3] Center 37 (7~67) winsize 61
8268 00:58:58.867016 [CA 4] Center 37 (8~67) winsize 60
8269 00:58:58.870234 [CA 5] Center 36 (7~66) winsize 60
8270 00:58:58.870313
8271 00:58:58.873645 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8272 00:58:58.873726
8273 00:58:58.880014 [CATrainingPosCal] consider 2 rank data
8274 00:58:58.880096 u2DelayCellTimex100 = 275/100 ps
8275 00:58:58.886527 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8276 00:58:58.889690 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8277 00:58:58.893554 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8278 00:58:58.896315 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8279 00:58:58.899764 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8280 00:58:58.903417 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8281 00:58:58.903536
8282 00:58:58.906348 CA PerBit enable=1, Macro0, CA PI delay=36
8283 00:58:58.906454
8284 00:58:58.910199 [CBTSetCACLKResult] CA Dly = 36
8285 00:58:58.912765 CS Dly: 10 (0~43)
8286 00:58:58.916790 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8287 00:58:58.919659 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8288 00:58:58.919771
8289 00:58:58.923191 ----->DramcWriteLeveling(PI) begin...
8290 00:58:58.923307 ==
8291 00:58:58.926060 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 00:58:58.932866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 00:58:58.932967 ==
8294 00:58:58.935975 Write leveling (Byte 0): 26 => 26
8295 00:58:58.939359 Write leveling (Byte 1): 26 => 26
8296 00:58:58.939459 DramcWriteLeveling(PI) end<-----
8297 00:58:58.943082
8298 00:58:58.943162 ==
8299 00:58:58.946502 Dram Type= 6, Freq= 0, CH_1, rank 0
8300 00:58:58.949084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 00:58:58.949191 ==
8302 00:58:58.953063 [Gating] SW mode calibration
8303 00:58:58.960318 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8304 00:58:58.962660 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8305 00:58:58.969056 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8306 00:58:58.972476 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8307 00:58:58.975745 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8308 00:58:58.982299 1 4 12 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
8309 00:58:58.985614 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8310 00:58:58.989178 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 00:58:58.995661 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 00:58:58.998715 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 00:58:59.005051 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 00:58:59.008394 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 00:58:59.011867 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
8316 00:58:59.015690 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
8317 00:58:59.022302 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 00:58:59.025280 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 00:58:59.031845 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 00:58:59.034676 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 00:58:59.038160 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 00:58:59.044747 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 00:58:59.048095 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8324 00:58:59.051587 1 6 12 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8325 00:58:59.058261 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 00:58:59.061193 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 00:58:59.064785 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 00:58:59.070925 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 00:58:59.074277 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 00:58:59.077333 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 00:58:59.084080 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8332 00:58:59.087269 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8333 00:58:59.091417 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 00:58:59.097211 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 00:58:59.100863 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 00:58:59.104223 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 00:58:59.110563 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 00:58:59.114053 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 00:58:59.116870 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 00:58:59.123731 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 00:58:59.126840 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 00:58:59.130462 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 00:58:59.136563 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 00:58:59.139834 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 00:58:59.144039 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 00:58:59.149876 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 00:58:59.153477 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8348 00:58:59.156455 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8349 00:58:59.163306 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 00:58:59.163388 Total UI for P1: 0, mck2ui 16
8351 00:58:59.169797 best dqsien dly found for B0: ( 1, 9, 10)
8352 00:58:59.169911 Total UI for P1: 0, mck2ui 16
8353 00:58:59.176264 best dqsien dly found for B1: ( 1, 9, 12)
8354 00:58:59.179725 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8355 00:58:59.183098 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8356 00:58:59.183175
8357 00:58:59.186407 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8358 00:58:59.189468 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8359 00:58:59.192972 [Gating] SW calibration Done
8360 00:58:59.193087 ==
8361 00:58:59.196130 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 00:58:59.199169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 00:58:59.199241 ==
8364 00:58:59.202565 RX Vref Scan: 0
8365 00:58:59.202633
8366 00:58:59.202692 RX Vref 0 -> 0, step: 1
8367 00:58:59.202752
8368 00:58:59.205784 RX Delay 0 -> 252, step: 8
8369 00:58:59.208924 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8370 00:58:59.215558 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8371 00:58:59.219020 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8372 00:58:59.222310 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8373 00:58:59.225766 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8374 00:58:59.229106 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8375 00:58:59.235536 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8376 00:58:59.238617 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8377 00:58:59.242374 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8378 00:58:59.245803 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8379 00:58:59.252270 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8380 00:58:59.255253 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8381 00:58:59.258742 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8382 00:58:59.262085 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8383 00:58:59.265213 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8384 00:58:59.272114 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8385 00:58:59.272203 ==
8386 00:58:59.274875 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 00:58:59.278520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 00:58:59.278647 ==
8389 00:58:59.278756 DQS Delay:
8390 00:58:59.281449 DQS0 = 0, DQS1 = 0
8391 00:58:59.281532 DQM Delay:
8392 00:58:59.285185 DQM0 = 135, DQM1 = 131
8393 00:58:59.285317 DQ Delay:
8394 00:58:59.288201 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8395 00:58:59.291343 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8396 00:58:59.294866 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8397 00:58:59.301269 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8398 00:58:59.301371
8399 00:58:59.301455
8400 00:58:59.301554 ==
8401 00:58:59.304846 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 00:58:59.308421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 00:58:59.308519 ==
8404 00:58:59.308634
8405 00:58:59.308712
8406 00:58:59.312087 TX Vref Scan disable
8407 00:58:59.312171 == TX Byte 0 ==
8408 00:58:59.318610 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8409 00:58:59.321091 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8410 00:58:59.321194 == TX Byte 1 ==
8411 00:58:59.327688 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8412 00:58:59.330923 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8413 00:58:59.331005 ==
8414 00:58:59.334497 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 00:58:59.337450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 00:58:59.337531 ==
8417 00:58:59.352460
8418 00:58:59.355218 TX Vref early break, caculate TX vref
8419 00:58:59.358628 TX Vref=16, minBit 9, minWin=21, winSum=369
8420 00:58:59.362292 TX Vref=18, minBit 8, minWin=21, winSum=373
8421 00:58:59.365399 TX Vref=20, minBit 8, minWin=23, winSum=386
8422 00:58:59.369029 TX Vref=22, minBit 8, minWin=23, winSum=398
8423 00:58:59.375679 TX Vref=24, minBit 13, minWin=24, winSum=407
8424 00:58:59.378326 TX Vref=26, minBit 1, minWin=25, winSum=413
8425 00:58:59.381942 TX Vref=28, minBit 3, minWin=25, winSum=415
8426 00:58:59.385584 TX Vref=30, minBit 9, minWin=24, winSum=414
8427 00:58:59.388413 TX Vref=32, minBit 9, minWin=24, winSum=407
8428 00:58:59.391909 TX Vref=34, minBit 0, minWin=23, winSum=397
8429 00:58:59.398919 TX Vref=36, minBit 11, minWin=22, winSum=385
8430 00:58:59.401608 [TxChooseVref] Worse bit 3, Min win 25, Win sum 415, Final Vref 28
8431 00:58:59.401691
8432 00:58:59.405425 Final TX Range 0 Vref 28
8433 00:58:59.405506
8434 00:58:59.405601 ==
8435 00:58:59.408976 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 00:58:59.411601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 00:58:59.415064 ==
8438 00:58:59.415145
8439 00:58:59.415210
8440 00:58:59.415270 TX Vref Scan disable
8441 00:58:59.421955 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8442 00:58:59.422036 == TX Byte 0 ==
8443 00:58:59.425000 u2DelayCellOfst[0]=17 cells (5 PI)
8444 00:58:59.428112 u2DelayCellOfst[1]=10 cells (3 PI)
8445 00:58:59.431508 u2DelayCellOfst[2]=0 cells (0 PI)
8446 00:58:59.434639 u2DelayCellOfst[3]=7 cells (2 PI)
8447 00:58:59.438363 u2DelayCellOfst[4]=10 cells (3 PI)
8448 00:58:59.441040 u2DelayCellOfst[5]=17 cells (5 PI)
8449 00:58:59.444373 u2DelayCellOfst[6]=14 cells (4 PI)
8450 00:58:59.447772 u2DelayCellOfst[7]=3 cells (1 PI)
8451 00:58:59.451502 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8452 00:58:59.454014 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8453 00:58:59.458180 == TX Byte 1 ==
8454 00:58:59.460954 u2DelayCellOfst[8]=0 cells (0 PI)
8455 00:58:59.464586 u2DelayCellOfst[9]=3 cells (1 PI)
8456 00:58:59.467468 u2DelayCellOfst[10]=10 cells (3 PI)
8457 00:58:59.470927 u2DelayCellOfst[11]=3 cells (1 PI)
8458 00:58:59.473913 u2DelayCellOfst[12]=14 cells (4 PI)
8459 00:58:59.477400 u2DelayCellOfst[13]=14 cells (4 PI)
8460 00:58:59.480557 u2DelayCellOfst[14]=17 cells (5 PI)
8461 00:58:59.484157 u2DelayCellOfst[15]=17 cells (5 PI)
8462 00:58:59.487305 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8463 00:58:59.490707 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8464 00:58:59.494465 DramC Write-DBI on
8465 00:58:59.494547 ==
8466 00:58:59.497678 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 00:58:59.500925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 00:58:59.501008 ==
8469 00:58:59.501074
8470 00:58:59.501135
8471 00:58:59.504104 TX Vref Scan disable
8472 00:58:59.507469 == TX Byte 0 ==
8473 00:58:59.510598 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8474 00:58:59.510698 == TX Byte 1 ==
8475 00:58:59.516712 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8476 00:58:59.516836 DramC Write-DBI off
8477 00:58:59.516930
8478 00:58:59.517020 [DATLAT]
8479 00:58:59.520200 Freq=1600, CH1 RK0
8480 00:58:59.520283
8481 00:58:59.523747 DATLAT Default: 0xf
8482 00:58:59.523829 0, 0xFFFF, sum = 0
8483 00:58:59.527125 1, 0xFFFF, sum = 0
8484 00:58:59.527284 2, 0xFFFF, sum = 0
8485 00:58:59.530049 3, 0xFFFF, sum = 0
8486 00:58:59.530133 4, 0xFFFF, sum = 0
8487 00:58:59.533528 5, 0xFFFF, sum = 0
8488 00:58:59.533614 6, 0xFFFF, sum = 0
8489 00:58:59.536837 7, 0xFFFF, sum = 0
8490 00:58:59.536920 8, 0xFFFF, sum = 0
8491 00:58:59.540210 9, 0xFFFF, sum = 0
8492 00:58:59.540295 10, 0xFFFF, sum = 0
8493 00:58:59.543383 11, 0xFFFF, sum = 0
8494 00:58:59.543496 12, 0xFFFF, sum = 0
8495 00:58:59.546703 13, 0xFFFF, sum = 0
8496 00:58:59.546786 14, 0x0, sum = 1
8497 00:58:59.550033 15, 0x0, sum = 2
8498 00:58:59.550228 16, 0x0, sum = 3
8499 00:58:59.552890 17, 0x0, sum = 4
8500 00:58:59.552976 best_step = 15
8501 00:58:59.553043
8502 00:58:59.553107 ==
8503 00:58:59.556560 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 00:58:59.563308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 00:58:59.563394 ==
8506 00:58:59.563461 RX Vref Scan: 1
8507 00:58:59.563524
8508 00:58:59.566423 Set Vref Range= 24 -> 127
8509 00:58:59.566507
8510 00:58:59.569269 RX Vref 24 -> 127, step: 1
8511 00:58:59.569354
8512 00:58:59.572943 RX Delay 19 -> 252, step: 4
8513 00:58:59.573028
8514 00:58:59.575766 Set Vref, RX VrefLevel [Byte0]: 24
8515 00:58:59.579130 [Byte1]: 24
8516 00:58:59.579214
8517 00:58:59.582717 Set Vref, RX VrefLevel [Byte0]: 25
8518 00:58:59.585671 [Byte1]: 25
8519 00:58:59.585755
8520 00:58:59.589082 Set Vref, RX VrefLevel [Byte0]: 26
8521 00:58:59.592453 [Byte1]: 26
8522 00:58:59.595966
8523 00:58:59.596049 Set Vref, RX VrefLevel [Byte0]: 27
8524 00:58:59.599290 [Byte1]: 27
8525 00:58:59.603767
8526 00:58:59.603851 Set Vref, RX VrefLevel [Byte0]: 28
8527 00:58:59.607136 [Byte1]: 28
8528 00:58:59.611296
8529 00:58:59.611380 Set Vref, RX VrefLevel [Byte0]: 29
8530 00:58:59.614282 [Byte1]: 29
8531 00:58:59.618274
8532 00:58:59.618358 Set Vref, RX VrefLevel [Byte0]: 30
8533 00:58:59.621813 [Byte1]: 30
8534 00:58:59.626424
8535 00:58:59.626506 Set Vref, RX VrefLevel [Byte0]: 31
8536 00:58:59.629428 [Byte1]: 31
8537 00:58:59.633651
8538 00:58:59.633750 Set Vref, RX VrefLevel [Byte0]: 32
8539 00:58:59.636749 [Byte1]: 32
8540 00:58:59.641300
8541 00:58:59.641382 Set Vref, RX VrefLevel [Byte0]: 33
8542 00:58:59.644741 [Byte1]: 33
8543 00:58:59.648537
8544 00:58:59.648619 Set Vref, RX VrefLevel [Byte0]: 34
8545 00:58:59.652365 [Byte1]: 34
8546 00:58:59.656562
8547 00:58:59.656644 Set Vref, RX VrefLevel [Byte0]: 35
8548 00:58:59.659904 [Byte1]: 35
8549 00:58:59.664625
8550 00:58:59.664726 Set Vref, RX VrefLevel [Byte0]: 36
8551 00:58:59.667263 [Byte1]: 36
8552 00:58:59.671697
8553 00:58:59.671778 Set Vref, RX VrefLevel [Byte0]: 37
8554 00:58:59.675073 [Byte1]: 37
8555 00:58:59.679549
8556 00:58:59.679667 Set Vref, RX VrefLevel [Byte0]: 38
8557 00:58:59.682371 [Byte1]: 38
8558 00:58:59.686493
8559 00:58:59.686600 Set Vref, RX VrefLevel [Byte0]: 39
8560 00:58:59.689961 [Byte1]: 39
8561 00:58:59.694697
8562 00:58:59.694780 Set Vref, RX VrefLevel [Byte0]: 40
8563 00:58:59.697293 [Byte1]: 40
8564 00:58:59.701985
8565 00:58:59.702099 Set Vref, RX VrefLevel [Byte0]: 41
8566 00:58:59.704985 [Byte1]: 41
8567 00:58:59.709349
8568 00:58:59.709450 Set Vref, RX VrefLevel [Byte0]: 42
8569 00:58:59.712469 [Byte1]: 42
8570 00:58:59.717112
8571 00:58:59.717213 Set Vref, RX VrefLevel [Byte0]: 43
8572 00:58:59.719987 [Byte1]: 43
8573 00:58:59.725218
8574 00:58:59.725356 Set Vref, RX VrefLevel [Byte0]: 44
8575 00:58:59.727658 [Byte1]: 44
8576 00:58:59.732218
8577 00:58:59.732341 Set Vref, RX VrefLevel [Byte0]: 45
8578 00:58:59.735549 [Byte1]: 45
8579 00:58:59.739864
8580 00:58:59.739978 Set Vref, RX VrefLevel [Byte0]: 46
8581 00:58:59.742932 [Byte1]: 46
8582 00:58:59.747600
8583 00:58:59.747702 Set Vref, RX VrefLevel [Byte0]: 47
8584 00:58:59.750469 [Byte1]: 47
8585 00:58:59.755017
8586 00:58:59.755095 Set Vref, RX VrefLevel [Byte0]: 48
8587 00:58:59.758368 [Byte1]: 48
8588 00:58:59.762382
8589 00:58:59.762480 Set Vref, RX VrefLevel [Byte0]: 49
8590 00:58:59.766113 [Byte1]: 49
8591 00:58:59.770349
8592 00:58:59.770435 Set Vref, RX VrefLevel [Byte0]: 50
8593 00:58:59.773624 [Byte1]: 50
8594 00:58:59.777807
8595 00:58:59.777914 Set Vref, RX VrefLevel [Byte0]: 51
8596 00:58:59.781240 [Byte1]: 51
8597 00:58:59.785384
8598 00:58:59.785467 Set Vref, RX VrefLevel [Byte0]: 52
8599 00:58:59.788250 [Byte1]: 52
8600 00:58:59.793011
8601 00:58:59.793093 Set Vref, RX VrefLevel [Byte0]: 53
8602 00:58:59.795878 [Byte1]: 53
8603 00:58:59.800693
8604 00:58:59.800778 Set Vref, RX VrefLevel [Byte0]: 54
8605 00:58:59.803868 [Byte1]: 54
8606 00:58:59.808072
8607 00:58:59.808155 Set Vref, RX VrefLevel [Byte0]: 55
8608 00:58:59.811016 [Byte1]: 55
8609 00:58:59.815542
8610 00:58:59.815625 Set Vref, RX VrefLevel [Byte0]: 56
8611 00:58:59.818634 [Byte1]: 56
8612 00:58:59.822984
8613 00:58:59.823066 Set Vref, RX VrefLevel [Byte0]: 57
8614 00:58:59.826416 [Byte1]: 57
8615 00:58:59.830971
8616 00:58:59.831052 Set Vref, RX VrefLevel [Byte0]: 58
8617 00:58:59.833584 [Byte1]: 58
8618 00:58:59.837905
8619 00:58:59.837987 Set Vref, RX VrefLevel [Byte0]: 59
8620 00:58:59.841407 [Byte1]: 59
8621 00:58:59.846054
8622 00:58:59.846137 Set Vref, RX VrefLevel [Byte0]: 60
8623 00:58:59.849065 [Byte1]: 60
8624 00:58:59.853477
8625 00:58:59.853559 Set Vref, RX VrefLevel [Byte0]: 61
8626 00:58:59.856516 [Byte1]: 61
8627 00:58:59.860659
8628 00:58:59.860782 Set Vref, RX VrefLevel [Byte0]: 62
8629 00:58:59.864266 [Byte1]: 62
8630 00:58:59.869022
8631 00:58:59.869105 Set Vref, RX VrefLevel [Byte0]: 63
8632 00:58:59.871787 [Byte1]: 63
8633 00:58:59.876472
8634 00:58:59.876580 Set Vref, RX VrefLevel [Byte0]: 64
8635 00:58:59.879062 [Byte1]: 64
8636 00:58:59.883819
8637 00:58:59.883926 Set Vref, RX VrefLevel [Byte0]: 65
8638 00:58:59.886961 [Byte1]: 65
8639 00:58:59.891018
8640 00:58:59.891117 Set Vref, RX VrefLevel [Byte0]: 66
8641 00:58:59.894606 [Byte1]: 66
8642 00:58:59.899032
8643 00:58:59.899131 Set Vref, RX VrefLevel [Byte0]: 67
8644 00:58:59.902171 [Byte1]: 67
8645 00:58:59.906106
8646 00:58:59.906188 Set Vref, RX VrefLevel [Byte0]: 68
8647 00:58:59.910417 [Byte1]: 68
8648 00:58:59.914017
8649 00:58:59.914087 Set Vref, RX VrefLevel [Byte0]: 69
8650 00:58:59.917242 [Byte1]: 69
8651 00:58:59.921738
8652 00:58:59.921811 Set Vref, RX VrefLevel [Byte0]: 70
8653 00:58:59.924912 [Byte1]: 70
8654 00:58:59.929395
8655 00:58:59.929468 Final RX Vref Byte 0 = 57 to rank0
8656 00:58:59.932613 Final RX Vref Byte 1 = 56 to rank0
8657 00:58:59.935973 Final RX Vref Byte 0 = 57 to rank1
8658 00:58:59.938869 Final RX Vref Byte 1 = 56 to rank1==
8659 00:58:59.942100 Dram Type= 6, Freq= 0, CH_1, rank 0
8660 00:58:59.948829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8661 00:58:59.948920 ==
8662 00:58:59.948986 DQS Delay:
8663 00:58:59.952270 DQS0 = 0, DQS1 = 0
8664 00:58:59.952367 DQM Delay:
8665 00:58:59.952464 DQM0 = 132, DQM1 = 129
8666 00:58:59.955453 DQ Delay:
8667 00:58:59.958907 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =132
8668 00:58:59.961864 DQ4 =128, DQ5 =142, DQ6 =146, DQ7 =126
8669 00:58:59.965406 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =122
8670 00:58:59.968861 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8671 00:58:59.968968
8672 00:58:59.969059
8673 00:58:59.969153
8674 00:58:59.971768 [DramC_TX_OE_Calibration] TA2
8675 00:58:59.975449 Original DQ_B0 (3 6) =30, OEN = 27
8676 00:58:59.978144 Original DQ_B1 (3 6) =30, OEN = 27
8677 00:58:59.981459 24, 0x0, End_B0=24 End_B1=24
8678 00:58:59.984749 25, 0x0, End_B0=25 End_B1=25
8679 00:58:59.984834 26, 0x0, End_B0=26 End_B1=26
8680 00:58:59.988447 27, 0x0, End_B0=27 End_B1=27
8681 00:58:59.991614 28, 0x0, End_B0=28 End_B1=28
8682 00:58:59.994995 29, 0x0, End_B0=29 End_B1=29
8683 00:58:59.995114 30, 0x0, End_B0=30 End_B1=30
8684 00:58:59.998410 31, 0x4141, End_B0=30 End_B1=30
8685 00:59:00.001639 Byte0 end_step=30 best_step=27
8686 00:59:00.005018 Byte1 end_step=30 best_step=27
8687 00:59:00.007936 Byte0 TX OE(2T, 0.5T) = (3, 3)
8688 00:59:00.011440 Byte1 TX OE(2T, 0.5T) = (3, 3)
8689 00:59:00.011522
8690 00:59:00.011588
8691 00:59:00.018230 [DQSOSCAuto] RK0, (LSB)MR18= 0xf18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8692 00:59:00.021009 CH1 RK0: MR19=303, MR18=F18
8693 00:59:00.027944 CH1_RK0: MR19=0x303, MR18=0xF18, DQSOSC=397, MR23=63, INC=23, DEC=15
8694 00:59:00.028039
8695 00:59:00.030963 ----->DramcWriteLeveling(PI) begin...
8696 00:59:00.031047 ==
8697 00:59:00.034375 Dram Type= 6, Freq= 0, CH_1, rank 1
8698 00:59:00.037962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8699 00:59:00.038046 ==
8700 00:59:00.041165 Write leveling (Byte 0): 24 => 24
8701 00:59:00.044383 Write leveling (Byte 1): 24 => 24
8702 00:59:00.047723 DramcWriteLeveling(PI) end<-----
8703 00:59:00.047806
8704 00:59:00.047871 ==
8705 00:59:00.050744 Dram Type= 6, Freq= 0, CH_1, rank 1
8706 00:59:00.054010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8707 00:59:00.057419 ==
8708 00:59:00.057501 [Gating] SW mode calibration
8709 00:59:00.067598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8710 00:59:00.070475 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8711 00:59:00.073932 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8712 00:59:00.080417 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8713 00:59:00.084129 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8714 00:59:00.087414 1 4 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8715 00:59:00.094057 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8716 00:59:00.096909 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8717 00:59:00.100253 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8718 00:59:00.106920 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8719 00:59:00.110144 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8720 00:59:00.113208 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8721 00:59:00.119932 1 5 8 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8722 00:59:00.123302 1 5 12 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8723 00:59:00.126908 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8724 00:59:00.133157 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8725 00:59:00.137625 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8726 00:59:00.139947 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8727 00:59:00.146589 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 00:59:00.149958 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8729 00:59:00.153191 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8730 00:59:00.159586 1 6 12 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
8731 00:59:00.162820 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8732 00:59:00.165966 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8733 00:59:00.172714 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8734 00:59:00.176086 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8735 00:59:00.179571 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8736 00:59:00.186497 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8737 00:59:00.189088 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8738 00:59:00.192366 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8739 00:59:00.199375 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8740 00:59:00.202493 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8741 00:59:00.205496 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8742 00:59:00.212149 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8743 00:59:00.215503 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8744 00:59:00.219048 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 00:59:00.225173 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 00:59:00.229087 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 00:59:00.231971 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 00:59:00.238876 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 00:59:00.242234 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 00:59:00.245392 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 00:59:00.251522 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 00:59:00.255188 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8753 00:59:00.258614 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8754 00:59:00.265066 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8755 00:59:00.268066 Total UI for P1: 0, mck2ui 16
8756 00:59:00.271345 best dqsien dly found for B0: ( 1, 9, 6)
8757 00:59:00.274897 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 00:59:00.278242 Total UI for P1: 0, mck2ui 16
8759 00:59:00.281152 best dqsien dly found for B1: ( 1, 9, 10)
8760 00:59:00.284708 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8761 00:59:00.288093 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8762 00:59:00.288201
8763 00:59:00.291541 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8764 00:59:00.297749 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8765 00:59:00.297832 [Gating] SW calibration Done
8766 00:59:00.297898 ==
8767 00:59:00.301123 Dram Type= 6, Freq= 0, CH_1, rank 1
8768 00:59:00.307767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8769 00:59:00.307850 ==
8770 00:59:00.307917 RX Vref Scan: 0
8771 00:59:00.307979
8772 00:59:00.310858 RX Vref 0 -> 0, step: 1
8773 00:59:00.310941
8774 00:59:00.314364 RX Delay 0 -> 252, step: 8
8775 00:59:00.317486 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8776 00:59:00.321148 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8777 00:59:00.324276 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8778 00:59:00.330832 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8779 00:59:00.334963 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8780 00:59:00.337075 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8781 00:59:00.340610 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8782 00:59:00.344220 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8783 00:59:00.350692 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8784 00:59:00.354124 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8785 00:59:00.357216 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8786 00:59:00.361045 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8787 00:59:00.363593 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8788 00:59:00.370094 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8789 00:59:00.373832 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8790 00:59:00.377036 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8791 00:59:00.377165 ==
8792 00:59:00.380453 Dram Type= 6, Freq= 0, CH_1, rank 1
8793 00:59:00.383350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 00:59:00.386666 ==
8795 00:59:00.386751 DQS Delay:
8796 00:59:00.386819 DQS0 = 0, DQS1 = 0
8797 00:59:00.390073 DQM Delay:
8798 00:59:00.390156 DQM0 = 136, DQM1 = 130
8799 00:59:00.393442 DQ Delay:
8800 00:59:00.397138 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8801 00:59:00.399996 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8802 00:59:00.402935 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8803 00:59:00.406744 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8804 00:59:00.406845
8805 00:59:00.406940
8806 00:59:00.407028 ==
8807 00:59:00.409566 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 00:59:00.413360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 00:59:00.416455 ==
8810 00:59:00.416556
8811 00:59:00.416647
8812 00:59:00.416740 TX Vref Scan disable
8813 00:59:00.420131 == TX Byte 0 ==
8814 00:59:00.423580 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8815 00:59:00.426278 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8816 00:59:00.429410 == TX Byte 1 ==
8817 00:59:00.432674 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8818 00:59:00.436728 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8819 00:59:00.439515 ==
8820 00:59:00.439619 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 00:59:00.445815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 00:59:00.445891 ==
8823 00:59:00.459042
8824 00:59:00.462423 TX Vref early break, caculate TX vref
8825 00:59:00.465473 TX Vref=16, minBit 0, minWin=23, winSum=381
8826 00:59:00.469372 TX Vref=18, minBit 9, minWin=22, winSum=389
8827 00:59:00.472067 TX Vref=20, minBit 9, minWin=23, winSum=398
8828 00:59:00.475365 TX Vref=22, minBit 9, minWin=23, winSum=401
8829 00:59:00.479007 TX Vref=24, minBit 9, minWin=24, winSum=411
8830 00:59:00.485998 TX Vref=26, minBit 5, minWin=25, winSum=418
8831 00:59:00.488275 TX Vref=28, minBit 9, minWin=25, winSum=424
8832 00:59:00.492045 TX Vref=30, minBit 5, minWin=25, winSum=418
8833 00:59:00.495145 TX Vref=32, minBit 0, minWin=24, winSum=416
8834 00:59:00.498300 TX Vref=34, minBit 0, minWin=24, winSum=403
8835 00:59:00.505071 TX Vref=36, minBit 0, minWin=23, winSum=400
8836 00:59:00.508059 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 28
8837 00:59:00.508158
8838 00:59:00.512020 Final TX Range 0 Vref 28
8839 00:59:00.512118
8840 00:59:00.512207 ==
8841 00:59:00.515008 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 00:59:00.518259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 00:59:00.521385 ==
8844 00:59:00.521467
8845 00:59:00.521533
8846 00:59:00.521594 TX Vref Scan disable
8847 00:59:00.528367 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8848 00:59:00.528450 == TX Byte 0 ==
8849 00:59:00.531723 u2DelayCellOfst[0]=14 cells (4 PI)
8850 00:59:00.535049 u2DelayCellOfst[1]=10 cells (3 PI)
8851 00:59:00.538007 u2DelayCellOfst[2]=0 cells (0 PI)
8852 00:59:00.541018 u2DelayCellOfst[3]=7 cells (2 PI)
8853 00:59:00.544386 u2DelayCellOfst[4]=7 cells (2 PI)
8854 00:59:00.547760 u2DelayCellOfst[5]=14 cells (4 PI)
8855 00:59:00.550968 u2DelayCellOfst[6]=14 cells (4 PI)
8856 00:59:00.554147 u2DelayCellOfst[7]=7 cells (2 PI)
8857 00:59:00.557425 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8858 00:59:00.561441 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8859 00:59:00.564309 == TX Byte 1 ==
8860 00:59:00.567996 u2DelayCellOfst[8]=0 cells (0 PI)
8861 00:59:00.570766 u2DelayCellOfst[9]=3 cells (1 PI)
8862 00:59:00.574389 u2DelayCellOfst[10]=10 cells (3 PI)
8863 00:59:00.577033 u2DelayCellOfst[11]=3 cells (1 PI)
8864 00:59:00.580813 u2DelayCellOfst[12]=14 cells (4 PI)
8865 00:59:00.583783 u2DelayCellOfst[13]=14 cells (4 PI)
8866 00:59:00.587392 u2DelayCellOfst[14]=17 cells (5 PI)
8867 00:59:00.590878 u2DelayCellOfst[15]=17 cells (5 PI)
8868 00:59:00.593966 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8869 00:59:00.597040 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8870 00:59:00.600211 DramC Write-DBI on
8871 00:59:00.600294 ==
8872 00:59:00.604281 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 00:59:00.606987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 00:59:00.607070 ==
8875 00:59:00.607136
8876 00:59:00.607197
8877 00:59:00.610087 TX Vref Scan disable
8878 00:59:00.613740 == TX Byte 0 ==
8879 00:59:00.616391 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8880 00:59:00.616481 == TX Byte 1 ==
8881 00:59:00.623042 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8882 00:59:00.623148 DramC Write-DBI off
8883 00:59:00.623241
8884 00:59:00.623330 [DATLAT]
8885 00:59:00.626630 Freq=1600, CH1 RK1
8886 00:59:00.626699
8887 00:59:00.630036 DATLAT Default: 0xf
8888 00:59:00.630111 0, 0xFFFF, sum = 0
8889 00:59:00.633423 1, 0xFFFF, sum = 0
8890 00:59:00.633497 2, 0xFFFF, sum = 0
8891 00:59:00.636271 3, 0xFFFF, sum = 0
8892 00:59:00.636367 4, 0xFFFF, sum = 0
8893 00:59:00.639887 5, 0xFFFF, sum = 0
8894 00:59:00.639971 6, 0xFFFF, sum = 0
8895 00:59:00.642854 7, 0xFFFF, sum = 0
8896 00:59:00.642927 8, 0xFFFF, sum = 0
8897 00:59:00.646327 9, 0xFFFF, sum = 0
8898 00:59:00.646398 10, 0xFFFF, sum = 0
8899 00:59:00.649777 11, 0xFFFF, sum = 0
8900 00:59:00.649856 12, 0xFFFF, sum = 0
8901 00:59:00.652660 13, 0xFFFF, sum = 0
8902 00:59:00.652757 14, 0x0, sum = 1
8903 00:59:00.656481 15, 0x0, sum = 2
8904 00:59:00.656578 16, 0x0, sum = 3
8905 00:59:00.659479 17, 0x0, sum = 4
8906 00:59:00.659581 best_step = 15
8907 00:59:00.659669
8908 00:59:00.659757 ==
8909 00:59:00.662540 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 00:59:00.669389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 00:59:00.669464 ==
8912 00:59:00.669527 RX Vref Scan: 0
8913 00:59:00.669587
8914 00:59:00.672404 RX Vref 0 -> 0, step: 1
8915 00:59:00.672497
8916 00:59:00.676303 RX Delay 11 -> 252, step: 4
8917 00:59:00.679525 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8918 00:59:00.682578 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8919 00:59:00.688968 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8920 00:59:00.692207 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8921 00:59:00.695988 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8922 00:59:00.698728 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8923 00:59:00.702054 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8924 00:59:00.709040 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8925 00:59:00.712711 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8926 00:59:00.715251 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8927 00:59:00.719144 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8928 00:59:00.725175 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8929 00:59:00.728740 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8930 00:59:00.731691 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8931 00:59:00.735061 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8932 00:59:00.738349 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8933 00:59:00.742331 ==
8934 00:59:00.742406 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 00:59:00.748120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 00:59:00.748223 ==
8937 00:59:00.748314 DQS Delay:
8938 00:59:00.751623 DQS0 = 0, DQS1 = 0
8939 00:59:00.751707 DQM Delay:
8940 00:59:00.754729 DQM0 = 133, DQM1 = 127
8941 00:59:00.754812 DQ Delay:
8942 00:59:00.758003 DQ0 =136, DQ1 =132, DQ2 =120, DQ3 =130
8943 00:59:00.761376 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
8944 00:59:00.764671 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8945 00:59:00.768083 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =136
8946 00:59:00.768166
8947 00:59:00.768232
8948 00:59:00.768294
8949 00:59:00.772056 [DramC_TX_OE_Calibration] TA2
8950 00:59:00.775175 Original DQ_B0 (3 6) =30, OEN = 27
8951 00:59:00.777880 Original DQ_B1 (3 6) =30, OEN = 27
8952 00:59:00.781045 24, 0x0, End_B0=24 End_B1=24
8953 00:59:00.784728 25, 0x0, End_B0=25 End_B1=25
8954 00:59:00.788105 26, 0x0, End_B0=26 End_B1=26
8955 00:59:00.788189 27, 0x0, End_B0=27 End_B1=27
8956 00:59:00.791066 28, 0x0, End_B0=28 End_B1=28
8957 00:59:00.794278 29, 0x0, End_B0=29 End_B1=29
8958 00:59:00.797591 30, 0x0, End_B0=30 End_B1=30
8959 00:59:00.800882 31, 0x4545, End_B0=30 End_B1=30
8960 00:59:00.800966 Byte0 end_step=30 best_step=27
8961 00:59:00.804119 Byte1 end_step=30 best_step=27
8962 00:59:00.807323 Byte0 TX OE(2T, 0.5T) = (3, 3)
8963 00:59:00.810924 Byte1 TX OE(2T, 0.5T) = (3, 3)
8964 00:59:00.811007
8965 00:59:00.811072
8966 00:59:00.817095 [DQSOSCAuto] RK1, (LSB)MR18= 0x1320, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
8967 00:59:00.820707 CH1 RK1: MR19=303, MR18=1320
8968 00:59:00.827153 CH1_RK1: MR19=0x303, MR18=0x1320, DQSOSC=393, MR23=63, INC=23, DEC=15
8969 00:59:00.830393 [RxdqsGatingPostProcess] freq 1600
8970 00:59:00.836752 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8971 00:59:00.840631 best DQS0 dly(2T, 0.5T) = (1, 1)
8972 00:59:00.843912 best DQS1 dly(2T, 0.5T) = (1, 1)
8973 00:59:00.843985 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8974 00:59:00.846918 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8975 00:59:00.850495 best DQS0 dly(2T, 0.5T) = (1, 1)
8976 00:59:00.853434 best DQS1 dly(2T, 0.5T) = (1, 1)
8977 00:59:00.856820 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8978 00:59:00.860054 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8979 00:59:00.863424 Pre-setting of DQS Precalculation
8980 00:59:00.870393 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8981 00:59:00.876924 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8982 00:59:00.883680 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8983 00:59:00.883768
8984 00:59:00.883835
8985 00:59:00.886467 [Calibration Summary] 3200 Mbps
8986 00:59:00.886551 CH 0, Rank 0
8987 00:59:00.889901 SW Impedance : PASS
8988 00:59:00.893367 DUTY Scan : NO K
8989 00:59:00.893470 ZQ Calibration : PASS
8990 00:59:00.896184 Jitter Meter : NO K
8991 00:59:00.899845 CBT Training : PASS
8992 00:59:00.899952 Write leveling : PASS
8993 00:59:00.903372 RX DQS gating : PASS
8994 00:59:00.906428 RX DQ/DQS(RDDQC) : PASS
8995 00:59:00.906528 TX DQ/DQS : PASS
8996 00:59:00.909504 RX DATLAT : PASS
8997 00:59:00.913064 RX DQ/DQS(Engine): PASS
8998 00:59:00.913163 TX OE : PASS
8999 00:59:00.913254 All Pass.
9000 00:59:00.916251
9001 00:59:00.916347 CH 0, Rank 1
9002 00:59:00.919816 SW Impedance : PASS
9003 00:59:00.919913 DUTY Scan : NO K
9004 00:59:00.922801 ZQ Calibration : PASS
9005 00:59:00.926577 Jitter Meter : NO K
9006 00:59:00.926675 CBT Training : PASS
9007 00:59:00.929285 Write leveling : PASS
9008 00:59:00.933194 RX DQS gating : PASS
9009 00:59:00.933310 RX DQ/DQS(RDDQC) : PASS
9010 00:59:00.936168 TX DQ/DQS : PASS
9011 00:59:00.936267 RX DATLAT : PASS
9012 00:59:00.939045 RX DQ/DQS(Engine): PASS
9013 00:59:00.942268 TX OE : PASS
9014 00:59:00.942344 All Pass.
9015 00:59:00.942408
9016 00:59:00.942477 CH 1, Rank 0
9017 00:59:00.945856 SW Impedance : PASS
9018 00:59:00.948986 DUTY Scan : NO K
9019 00:59:00.949059 ZQ Calibration : PASS
9020 00:59:00.951960 Jitter Meter : NO K
9021 00:59:00.955510 CBT Training : PASS
9022 00:59:00.955582 Write leveling : PASS
9023 00:59:00.959319 RX DQS gating : PASS
9024 00:59:00.961909 RX DQ/DQS(RDDQC) : PASS
9025 00:59:00.961979 TX DQ/DQS : PASS
9026 00:59:00.965282 RX DATLAT : PASS
9027 00:59:00.968824 RX DQ/DQS(Engine): PASS
9028 00:59:00.968926 TX OE : PASS
9029 00:59:00.972517 All Pass.
9030 00:59:00.972613
9031 00:59:00.972682 CH 1, Rank 1
9032 00:59:00.975653 SW Impedance : PASS
9033 00:59:00.975724 DUTY Scan : NO K
9034 00:59:00.978391 ZQ Calibration : PASS
9035 00:59:00.981832 Jitter Meter : NO K
9036 00:59:00.981906 CBT Training : PASS
9037 00:59:00.984834 Write leveling : PASS
9038 00:59:00.988547 RX DQS gating : PASS
9039 00:59:00.988620 RX DQ/DQS(RDDQC) : PASS
9040 00:59:00.991354 TX DQ/DQS : PASS
9041 00:59:00.994945 RX DATLAT : PASS
9042 00:59:00.995063 RX DQ/DQS(Engine): PASS
9043 00:59:00.998100 TX OE : PASS
9044 00:59:00.998199 All Pass.
9045 00:59:00.998292
9046 00:59:01.001550 DramC Write-DBI on
9047 00:59:01.004817 PER_BANK_REFRESH: Hybrid Mode
9048 00:59:01.004920 TX_TRACKING: ON
9049 00:59:01.015221 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9050 00:59:01.021632 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9051 00:59:01.027714 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9052 00:59:01.031236 [FAST_K] Save calibration result to emmc
9053 00:59:01.034696 sync common calibartion params.
9054 00:59:01.038038 sync cbt_mode0:1, 1:1
9055 00:59:01.040948 dram_init: ddr_geometry: 2
9056 00:59:01.041052 dram_init: ddr_geometry: 2
9057 00:59:01.044811 dram_init: ddr_geometry: 2
9058 00:59:01.047742 0:dram_rank_size:100000000
9059 00:59:01.050815 1:dram_rank_size:100000000
9060 00:59:01.054103 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9061 00:59:01.057919 DFS_SHUFFLE_HW_MODE: ON
9062 00:59:01.060747 dramc_set_vcore_voltage set vcore to 725000
9063 00:59:01.064418 Read voltage for 1600, 0
9064 00:59:01.064495 Vio18 = 0
9065 00:59:01.067238 Vcore = 725000
9066 00:59:01.067341 Vdram = 0
9067 00:59:01.067431 Vddq = 0
9068 00:59:01.067519 Vmddr = 0
9069 00:59:01.070953 switch to 3200 Mbps bootup
9070 00:59:01.074543 [DramcRunTimeConfig]
9071 00:59:01.074646 PHYPLL
9072 00:59:01.077538 DPM_CONTROL_AFTERK: ON
9073 00:59:01.077612 PER_BANK_REFRESH: ON
9074 00:59:01.080720 REFRESH_OVERHEAD_REDUCTION: ON
9075 00:59:01.084043 CMD_PICG_NEW_MODE: OFF
9076 00:59:01.084154 XRTWTW_NEW_MODE: ON
9077 00:59:01.087176 XRTRTR_NEW_MODE: ON
9078 00:59:01.087282 TX_TRACKING: ON
9079 00:59:01.090978 RDSEL_TRACKING: OFF
9080 00:59:01.091087 DQS Precalculation for DVFS: ON
9081 00:59:01.093967 RX_TRACKING: OFF
9082 00:59:01.094072 HW_GATING DBG: ON
9083 00:59:01.097517 ZQCS_ENABLE_LP4: ON
9084 00:59:01.100403 RX_PICG_NEW_MODE: ON
9085 00:59:01.100508 TX_PICG_NEW_MODE: ON
9086 00:59:01.103515 ENABLE_RX_DCM_DPHY: ON
9087 00:59:01.106759 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9088 00:59:01.110303 DUMMY_READ_FOR_TRACKING: OFF
9089 00:59:01.110382 !!! SPM_CONTROL_AFTERK: OFF
9090 00:59:01.113270 !!! SPM could not control APHY
9091 00:59:01.116461 IMPEDANCE_TRACKING: ON
9092 00:59:01.116538 TEMP_SENSOR: ON
9093 00:59:01.119932 HW_SAVE_FOR_SR: OFF
9094 00:59:01.123176 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9095 00:59:01.126408 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9096 00:59:01.126507 Read ODT Tracking: ON
9097 00:59:01.129765 Refresh Rate DeBounce: ON
9098 00:59:01.133361 DFS_NO_QUEUE_FLUSH: ON
9099 00:59:01.136682 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9100 00:59:01.136767 ENABLE_DFS_RUNTIME_MRW: OFF
9101 00:59:01.140243 DDR_RESERVE_NEW_MODE: ON
9102 00:59:01.143266 MR_CBT_SWITCH_FREQ: ON
9103 00:59:01.143350 =========================
9104 00:59:01.163736 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9105 00:59:01.166681 dram_init: ddr_geometry: 2
9106 00:59:01.185397 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9107 00:59:01.189130 dram_init: dram init end (result: 0)
9108 00:59:01.194809 DRAM-K: Full calibration passed in 24407 msecs
9109 00:59:01.197966 MRC: failed to locate region type 0.
9110 00:59:01.198050 DRAM rank0 size:0x100000000,
9111 00:59:01.201818 DRAM rank1 size=0x100000000
9112 00:59:01.211487 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9113 00:59:01.218050 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9114 00:59:01.227583 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9115 00:59:01.234232 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9116 00:59:01.234321 DRAM rank0 size:0x100000000,
9117 00:59:01.237664 DRAM rank1 size=0x100000000
9118 00:59:01.237748 CBMEM:
9119 00:59:01.240826 IMD: root @ 0xfffff000 254 entries.
9120 00:59:01.244412 IMD: root @ 0xffffec00 62 entries.
9121 00:59:01.250714 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9122 00:59:01.254105 WARNING: RO_VPD is uninitialized or empty.
9123 00:59:01.257185 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9124 00:59:01.265223 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9125 00:59:01.277978 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9126 00:59:01.289043 BS: romstage times (exec / console): total (unknown) / 23941 ms
9127 00:59:01.289154
9128 00:59:01.289251
9129 00:59:01.299080 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9130 00:59:01.302537 ARM64: Exception handlers installed.
9131 00:59:01.305416 ARM64: Testing exception
9132 00:59:01.309011 ARM64: Done test exception
9133 00:59:01.309112 Enumerating buses...
9134 00:59:01.312340 Show all devs... Before device enumeration.
9135 00:59:01.315437 Root Device: enabled 1
9136 00:59:01.318799 CPU_CLUSTER: 0: enabled 1
9137 00:59:01.318903 CPU: 00: enabled 1
9138 00:59:01.321933 Compare with tree...
9139 00:59:01.322011 Root Device: enabled 1
9140 00:59:01.325186 CPU_CLUSTER: 0: enabled 1
9141 00:59:01.329335 CPU: 00: enabled 1
9142 00:59:01.329413 Root Device scanning...
9143 00:59:01.331921 scan_static_bus for Root Device
9144 00:59:01.335157 CPU_CLUSTER: 0 enabled
9145 00:59:01.338489 scan_static_bus for Root Device done
9146 00:59:01.342170 scan_bus: bus Root Device finished in 8 msecs
9147 00:59:01.342353 done
9148 00:59:01.348513 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9149 00:59:01.351956 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9150 00:59:01.358530 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9151 00:59:01.362205 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9152 00:59:01.365519 Allocating resources...
9153 00:59:01.368744 Reading resources...
9154 00:59:01.371580 Root Device read_resources bus 0 link: 0
9155 00:59:01.374803 DRAM rank0 size:0x100000000,
9156 00:59:01.374905 DRAM rank1 size=0x100000000
9157 00:59:01.381714 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9158 00:59:01.381796 CPU: 00 missing read_resources
9159 00:59:01.388090 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9160 00:59:01.391329 Root Device read_resources bus 0 link: 0 done
9161 00:59:01.394911 Done reading resources.
9162 00:59:01.397695 Show resources in subtree (Root Device)...After reading.
9163 00:59:01.401525 Root Device child on link 0 CPU_CLUSTER: 0
9164 00:59:01.404376 CPU_CLUSTER: 0 child on link 0 CPU: 00
9165 00:59:01.414875 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9166 00:59:01.414980 CPU: 00
9167 00:59:01.421146 Root Device assign_resources, bus 0 link: 0
9168 00:59:01.424700 CPU_CLUSTER: 0 missing set_resources
9169 00:59:01.427550 Root Device assign_resources, bus 0 link: 0 done
9170 00:59:01.430998 Done setting resources.
9171 00:59:01.434417 Show resources in subtree (Root Device)...After assigning values.
9172 00:59:01.437234 Root Device child on link 0 CPU_CLUSTER: 0
9173 00:59:01.444049 CPU_CLUSTER: 0 child on link 0 CPU: 00
9174 00:59:01.450660 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9175 00:59:01.454008 CPU: 00
9176 00:59:01.454086 Done allocating resources.
9177 00:59:01.460732 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9178 00:59:01.460808 Enabling resources...
9179 00:59:01.463827 done.
9180 00:59:01.466851 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9181 00:59:01.470811 Initializing devices...
9182 00:59:01.470886 Root Device init
9183 00:59:01.473868 init hardware done!
9184 00:59:01.473941 0x00000018: ctrlr->caps
9185 00:59:01.476965 52.000 MHz: ctrlr->f_max
9186 00:59:01.480333 0.400 MHz: ctrlr->f_min
9187 00:59:01.483579 0x40ff8080: ctrlr->voltages
9188 00:59:01.483666 sclk: 390625
9189 00:59:01.483733 Bus Width = 1
9190 00:59:01.487084 sclk: 390625
9191 00:59:01.487166 Bus Width = 1
9192 00:59:01.490546 Early init status = 3
9193 00:59:01.493427 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9194 00:59:01.496807 in-header: 03 fc 00 00 01 00 00 00
9195 00:59:01.500136 in-data: 00
9196 00:59:01.503475 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9197 00:59:01.508632 in-header: 03 fd 00 00 00 00 00 00
9198 00:59:01.511354 in-data:
9199 00:59:01.514755 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9200 00:59:01.518231 in-header: 03 fc 00 00 01 00 00 00
9201 00:59:01.521504 in-data: 00
9202 00:59:01.524869 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9203 00:59:01.529194 in-header: 03 fd 00 00 00 00 00 00
9204 00:59:01.533017 in-data:
9205 00:59:01.535788 [SSUSB] Setting up USB HOST controller...
9206 00:59:01.539547 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9207 00:59:01.542398 [SSUSB] phy power-on done.
9208 00:59:01.545481 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9209 00:59:01.552328 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9210 00:59:01.556164 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9211 00:59:01.562539 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9212 00:59:01.568850 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9213 00:59:01.575081 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9214 00:59:01.581872 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9215 00:59:01.588913 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9216 00:59:01.592160 SPM: binary array size = 0x9dc
9217 00:59:01.595657 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9218 00:59:01.602115 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9219 00:59:01.608625 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9220 00:59:01.614819 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9221 00:59:01.617793 configure_display: Starting display init
9222 00:59:01.652765 anx7625_power_on_init: Init interface.
9223 00:59:01.655595 anx7625_disable_pd_protocol: Disabled PD feature.
9224 00:59:01.659247 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9225 00:59:01.687079 anx7625_start_dp_work: Secure OCM version=00
9226 00:59:01.690531 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9227 00:59:01.704888 sp_tx_get_edid_block: EDID Block = 1
9228 00:59:01.807709 Extracted contents:
9229 00:59:01.810801 header: 00 ff ff ff ff ff ff 00
9230 00:59:01.814275 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9231 00:59:01.817555 version: 01 04
9232 00:59:01.820870 basic params: 95 1f 11 78 0a
9233 00:59:01.824307 chroma info: 76 90 94 55 54 90 27 21 50 54
9234 00:59:01.827217 established: 00 00 00
9235 00:59:01.834295 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9236 00:59:01.840657 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9237 00:59:01.844040 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9238 00:59:01.850454 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9239 00:59:01.857046 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9240 00:59:01.860208 extensions: 00
9241 00:59:01.860291 checksum: fb
9242 00:59:01.860357
9243 00:59:01.863450 Manufacturer: IVO Model 57d Serial Number 0
9244 00:59:01.866914 Made week 0 of 2020
9245 00:59:01.870719 EDID version: 1.4
9246 00:59:01.870802 Digital display
9247 00:59:01.873572 6 bits per primary color channel
9248 00:59:01.873656 DisplayPort interface
9249 00:59:01.876578 Maximum image size: 31 cm x 17 cm
9250 00:59:01.880133 Gamma: 220%
9251 00:59:01.880216 Check DPMS levels
9252 00:59:01.886956 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9253 00:59:01.890242 First detailed timing is preferred timing
9254 00:59:01.890328 Established timings supported:
9255 00:59:01.893212 Standard timings supported:
9256 00:59:01.896634 Detailed timings
9257 00:59:01.900009 Hex of detail: 383680a07038204018303c0035ae10000019
9258 00:59:01.906519 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9259 00:59:01.909999 0780 0798 07c8 0820 hborder 0
9260 00:59:01.912773 0438 043b 0447 0458 vborder 0
9261 00:59:01.916209 -hsync -vsync
9262 00:59:01.916291 Did detailed timing
9263 00:59:01.922792 Hex of detail: 000000000000000000000000000000000000
9264 00:59:01.926098 Manufacturer-specified data, tag 0
9265 00:59:01.929537 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9266 00:59:01.932796 ASCII string: InfoVision
9267 00:59:01.935662 Hex of detail: 000000fe00523134304e574635205248200a
9268 00:59:01.939551 ASCII string: R140NWF5 RH
9269 00:59:01.939655 Checksum
9270 00:59:01.942297 Checksum: 0xfb (valid)
9271 00:59:01.945831 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9272 00:59:01.949346 DSI data_rate: 832800000 bps
9273 00:59:01.955797 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9274 00:59:01.959305 anx7625_parse_edid: pixelclock(138800).
9275 00:59:01.962400 hactive(1920), hsync(48), hfp(24), hbp(88)
9276 00:59:01.965840 vactive(1080), vsync(12), vfp(3), vbp(17)
9277 00:59:01.968849 anx7625_dsi_config: config dsi.
9278 00:59:01.975386 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9279 00:59:01.989668 anx7625_dsi_config: success to config DSI
9280 00:59:01.993563 anx7625_dp_start: MIPI phy setup OK.
9281 00:59:01.995977 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9282 00:59:01.999929 mtk_ddp_mode_set invalid vrefresh 60
9283 00:59:02.002603 main_disp_path_setup
9284 00:59:02.002680 ovl_layer_smi_id_en
9285 00:59:02.006500 ovl_layer_smi_id_en
9286 00:59:02.006604 ccorr_config
9287 00:59:02.006696 aal_config
9288 00:59:02.009194 gamma_config
9289 00:59:02.009333 postmask_config
9290 00:59:02.012657 dither_config
9291 00:59:02.016197 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9292 00:59:02.022730 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9293 00:59:02.026286 Root Device init finished in 551 msecs
9294 00:59:02.029240 CPU_CLUSTER: 0 init
9295 00:59:02.035990 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9296 00:59:02.042167 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9297 00:59:02.042249 APU_MBOX 0x190000b0 = 0x10001
9298 00:59:02.045330 APU_MBOX 0x190001b0 = 0x10001
9299 00:59:02.049515 APU_MBOX 0x190005b0 = 0x10001
9300 00:59:02.052413 APU_MBOX 0x190006b0 = 0x10001
9301 00:59:02.059138 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9302 00:59:02.068474 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9303 00:59:02.081086 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9304 00:59:02.087628 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9305 00:59:02.099382 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9306 00:59:02.108611 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9307 00:59:02.112169 CPU_CLUSTER: 0 init finished in 81 msecs
9308 00:59:02.115233 Devices initialized
9309 00:59:02.118217 Show all devs... After init.
9310 00:59:02.118322 Root Device: enabled 1
9311 00:59:02.121683 CPU_CLUSTER: 0: enabled 1
9312 00:59:02.124769 CPU: 00: enabled 1
9313 00:59:02.128130 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9314 00:59:02.131295 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9315 00:59:02.135270 ELOG: NV offset 0x57f000 size 0x1000
9316 00:59:02.142015 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9317 00:59:02.148003 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9318 00:59:02.151049 ELOG: Event(17) added with size 13 at 2024-06-16 00:59:01 UTC
9319 00:59:02.157747 out: cmd=0x121: 03 db 21 01 00 00 00 00
9320 00:59:02.161026 in-header: 03 fc 00 00 2c 00 00 00
9321 00:59:02.171326 in-data: 41 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9322 00:59:02.178014 ELOG: Event(A1) added with size 10 at 2024-06-16 00:59:01 UTC
9323 00:59:02.184607 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9324 00:59:02.192294 ELOG: Event(A0) added with size 9 at 2024-06-16 00:59:01 UTC
9325 00:59:02.194537 elog_add_boot_reason: Logged dev mode boot
9326 00:59:02.201064 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9327 00:59:02.201148 Finalize devices...
9328 00:59:02.204087 Devices finalized
9329 00:59:02.207745 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9330 00:59:02.210730 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9331 00:59:02.214040 in-header: 03 07 00 00 08 00 00 00
9332 00:59:02.217660 in-data: aa e4 47 04 13 02 00 00
9333 00:59:02.220592 Chrome EC: UHEPI supported
9334 00:59:02.227368 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9335 00:59:02.230475 in-header: 03 a9 00 00 08 00 00 00
9336 00:59:02.234197 in-data: 84 60 60 08 00 00 00 00
9337 00:59:02.240495 ELOG: Event(91) added with size 10 at 2024-06-16 00:59:01 UTC
9338 00:59:02.244164 Chrome EC: clear events_b mask to 0x0000000020004000
9339 00:59:02.250708 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9340 00:59:02.255210 in-header: 03 fd 00 00 00 00 00 00
9341 00:59:02.258065 in-data:
9342 00:59:02.260685 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9343 00:59:02.264486 Writing coreboot table at 0xffe64000
9344 00:59:02.270962 0. 000000000010a000-0000000000113fff: RAMSTAGE
9345 00:59:02.274266 1. 0000000040000000-00000000400fffff: RAM
9346 00:59:02.277097 2. 0000000040100000-000000004032afff: RAMSTAGE
9347 00:59:02.280538 3. 000000004032b000-00000000545fffff: RAM
9348 00:59:02.283782 4. 0000000054600000-000000005465ffff: BL31
9349 00:59:02.290087 5. 0000000054660000-00000000ffe63fff: RAM
9350 00:59:02.293650 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9351 00:59:02.297079 7. 0000000100000000-000000023fffffff: RAM
9352 00:59:02.300193 Passing 5 GPIOs to payload:
9353 00:59:02.303657 NAME | PORT | POLARITY | VALUE
9354 00:59:02.310396 EC in RW | 0x000000aa | low | undefined
9355 00:59:02.313476 EC interrupt | 0x00000005 | low | undefined
9356 00:59:02.319749 TPM interrupt | 0x000000ab | high | undefined
9357 00:59:02.323409 SD card detect | 0x00000011 | high | undefined
9358 00:59:02.329797 speaker enable | 0x00000093 | high | undefined
9359 00:59:02.333240 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9360 00:59:02.336476 in-header: 03 f9 00 00 02 00 00 00
9361 00:59:02.336555 in-data: 02 00
9362 00:59:02.339748 ADC[4]: Raw value=903325 ID=7
9363 00:59:02.343038 ADC[3]: Raw value=213916 ID=1
9364 00:59:02.343143 RAM Code: 0x71
9365 00:59:02.346585 ADC[6]: Raw value=74630 ID=0
9366 00:59:02.349953 ADC[5]: Raw value=213546 ID=1
9367 00:59:02.350059 SKU Code: 0x1
9368 00:59:02.356675 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c1bb
9369 00:59:02.359439 coreboot table: 964 bytes.
9370 00:59:02.363097 IMD ROOT 0. 0xfffff000 0x00001000
9371 00:59:02.366024 IMD SMALL 1. 0xffffe000 0x00001000
9372 00:59:02.369533 RO MCACHE 2. 0xffffc000 0x00001104
9373 00:59:02.373194 CONSOLE 3. 0xfff7c000 0x00080000
9374 00:59:02.375997 FMAP 4. 0xfff7b000 0x00000452
9375 00:59:02.379747 TIME STAMP 5. 0xfff7a000 0x00000910
9376 00:59:02.379831 VBOOT WORK 6. 0xfff66000 0x00014000
9377 00:59:02.382713 RAMOOPS 7. 0xffe66000 0x00100000
9378 00:59:02.386017 COREBOOT 8. 0xffe64000 0x00002000
9379 00:59:02.389566 IMD small region:
9380 00:59:02.393182 IMD ROOT 0. 0xffffec00 0x00000400
9381 00:59:02.396208 VPD 1. 0xffffeb80 0x0000006c
9382 00:59:02.399458 MMC STATUS 2. 0xffffeb60 0x00000004
9383 00:59:02.405724 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9384 00:59:02.412771 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9385 00:59:02.451636 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9386 00:59:02.454936 Checking segment from ROM address 0x40100000
9387 00:59:02.461146 Checking segment from ROM address 0x4010001c
9388 00:59:02.464718 Loading segment from ROM address 0x40100000
9389 00:59:02.464825 code (compression=0)
9390 00:59:02.474239 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9391 00:59:02.481248 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9392 00:59:02.484277 it's not compressed!
9393 00:59:02.487423 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9394 00:59:02.493993 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9395 00:59:02.511735 Loading segment from ROM address 0x4010001c
9396 00:59:02.511824 Entry Point 0x80000000
9397 00:59:02.514983 Loaded segments
9398 00:59:02.518215 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9399 00:59:02.525291 Jumping to boot code at 0x80000000(0xffe64000)
9400 00:59:02.531389 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9401 00:59:02.538058 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9402 00:59:02.546897 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9403 00:59:02.549682 Checking segment from ROM address 0x40100000
9404 00:59:02.552872 Checking segment from ROM address 0x4010001c
9405 00:59:02.559149 Loading segment from ROM address 0x40100000
9406 00:59:02.559233 code (compression=1)
9407 00:59:02.566031 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9408 00:59:02.575817 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9409 00:59:02.575902 using LZMA
9410 00:59:02.584761 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9411 00:59:02.591175 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9412 00:59:02.594628 Loading segment from ROM address 0x4010001c
9413 00:59:02.597394 Entry Point 0x54601000
9414 00:59:02.597481 Loaded segments
9415 00:59:02.600765 NOTICE: MT8192 bl31_setup
9416 00:59:02.608256 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9417 00:59:02.611569 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9418 00:59:02.614926 WARNING: region 0:
9419 00:59:02.618090 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9420 00:59:02.618174 WARNING: region 1:
9421 00:59:02.624833 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9422 00:59:02.628721 WARNING: region 2:
9423 00:59:02.631237 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9424 00:59:02.634628 WARNING: region 3:
9425 00:59:02.637780 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9426 00:59:02.641442 WARNING: region 4:
9427 00:59:02.648161 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9428 00:59:02.648248 WARNING: region 5:
9429 00:59:02.651303 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9430 00:59:02.654915 WARNING: region 6:
9431 00:59:02.657993 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9432 00:59:02.660878 WARNING: region 7:
9433 00:59:02.664041 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9434 00:59:02.671414 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9435 00:59:02.674210 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9436 00:59:02.681034 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9437 00:59:02.684214 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9438 00:59:02.687281 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9439 00:59:02.694497 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9440 00:59:02.697433 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9441 00:59:02.700445 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9442 00:59:02.707690 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9443 00:59:02.710212 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9444 00:59:02.716856 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9445 00:59:02.720443 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9446 00:59:02.723788 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9447 00:59:02.730196 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9448 00:59:02.734458 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9449 00:59:02.740203 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9450 00:59:02.744023 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9451 00:59:02.746772 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9452 00:59:02.753371 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9453 00:59:02.756599 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9454 00:59:02.759724 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9455 00:59:02.766612 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9456 00:59:02.769634 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9457 00:59:02.776194 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9458 00:59:02.779791 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9459 00:59:02.783131 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9460 00:59:02.789840 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9461 00:59:02.793432 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9462 00:59:02.799307 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9463 00:59:02.802629 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9464 00:59:02.809666 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9465 00:59:02.812451 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9466 00:59:02.815714 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9467 00:59:02.819090 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9468 00:59:02.825987 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9469 00:59:02.829187 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9470 00:59:02.832344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9471 00:59:02.839201 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9472 00:59:02.842029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9473 00:59:02.845469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9474 00:59:02.848525 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9475 00:59:02.855315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9476 00:59:02.858641 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9477 00:59:02.862319 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9478 00:59:02.865540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9479 00:59:02.871925 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9480 00:59:02.875317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9481 00:59:02.878744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9482 00:59:02.885807 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9483 00:59:02.888621 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9484 00:59:02.891527 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9485 00:59:02.898397 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9486 00:59:02.901629 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9487 00:59:02.908395 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9488 00:59:02.911516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9489 00:59:02.918450 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9490 00:59:02.921703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9491 00:59:02.925238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9492 00:59:02.931671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9493 00:59:02.934908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9494 00:59:02.941180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9495 00:59:02.944751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9496 00:59:02.951028 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9497 00:59:02.954472 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9498 00:59:02.961051 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9499 00:59:02.964891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9500 00:59:02.971131 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9501 00:59:02.974651 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9502 00:59:02.978489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9503 00:59:02.984481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9504 00:59:02.987842 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9505 00:59:02.994129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9506 00:59:02.997670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9507 00:59:03.003935 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9508 00:59:03.007089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9509 00:59:03.013934 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9510 00:59:03.017082 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9511 00:59:03.023560 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9512 00:59:03.027239 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9513 00:59:03.030324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9514 00:59:03.037277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9515 00:59:03.040272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9516 00:59:03.047225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9517 00:59:03.050085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9518 00:59:03.056947 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9519 00:59:03.060146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9520 00:59:03.066329 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9521 00:59:03.070379 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9522 00:59:03.073507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9523 00:59:03.079543 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9524 00:59:03.082920 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9525 00:59:03.089459 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9526 00:59:03.092564 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9527 00:59:03.099845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9528 00:59:03.102753 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9529 00:59:03.109532 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9530 00:59:03.112639 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9531 00:59:03.116109 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9532 00:59:03.119040 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9533 00:59:03.125773 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9534 00:59:03.129595 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9535 00:59:03.132359 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9536 00:59:03.138846 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9537 00:59:03.142011 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9538 00:59:03.148553 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9539 00:59:03.151985 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9540 00:59:03.155236 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9541 00:59:03.161760 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9542 00:59:03.165802 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9543 00:59:03.171623 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9544 00:59:03.175417 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9545 00:59:03.181926 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9546 00:59:03.184930 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9547 00:59:03.188590 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9548 00:59:03.195092 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9549 00:59:03.198125 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9550 00:59:03.201218 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9551 00:59:03.208338 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9552 00:59:03.211428 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9553 00:59:03.215175 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9554 00:59:03.221218 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9555 00:59:03.224629 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9556 00:59:03.227611 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9557 00:59:03.231134 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9558 00:59:03.237666 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9559 00:59:03.240786 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9560 00:59:03.247506 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9561 00:59:03.250963 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9562 00:59:03.253880 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9563 00:59:03.260516 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9564 00:59:03.263647 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9565 00:59:03.270912 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9566 00:59:03.274312 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9567 00:59:03.277034 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9568 00:59:03.283403 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9569 00:59:03.287397 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9570 00:59:03.293347 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9571 00:59:03.296825 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9572 00:59:03.300733 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9573 00:59:03.306706 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9574 00:59:03.310036 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9575 00:59:03.316542 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9576 00:59:03.319833 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9577 00:59:03.327325 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9578 00:59:03.329820 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9579 00:59:03.332919 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9580 00:59:03.339536 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9581 00:59:03.342805 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9582 00:59:03.349402 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9583 00:59:03.352750 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9584 00:59:03.356201 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9585 00:59:03.362632 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9586 00:59:03.366084 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9587 00:59:03.369617 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9588 00:59:03.375832 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9589 00:59:03.379498 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9590 00:59:03.386081 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9591 00:59:03.388846 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9592 00:59:03.392710 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9593 00:59:03.398941 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9594 00:59:03.402224 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9595 00:59:03.408717 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9596 00:59:03.411925 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9597 00:59:03.418674 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9598 00:59:03.422030 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9599 00:59:03.425726 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9600 00:59:03.431886 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9601 00:59:03.435354 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9602 00:59:03.441806 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9603 00:59:03.444924 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9604 00:59:03.448276 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9605 00:59:03.455051 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9606 00:59:03.458408 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9607 00:59:03.461444 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9608 00:59:03.468121 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9609 00:59:03.471704 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9610 00:59:03.478022 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9611 00:59:03.481177 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9612 00:59:03.487820 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9613 00:59:03.491487 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9614 00:59:03.494272 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9615 00:59:03.500910 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9616 00:59:03.504405 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9617 00:59:03.510963 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9618 00:59:03.514496 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9619 00:59:03.517445 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9620 00:59:03.524416 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9621 00:59:03.527999 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9622 00:59:03.534185 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9623 00:59:03.537305 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9624 00:59:03.540283 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9625 00:59:03.546912 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9626 00:59:03.550468 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9627 00:59:03.557052 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9628 00:59:03.560669 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9629 00:59:03.566965 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9630 00:59:03.570879 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9631 00:59:03.573457 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9632 00:59:03.579864 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9633 00:59:03.583450 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9634 00:59:03.590453 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9635 00:59:03.593161 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9636 00:59:03.599563 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9637 00:59:03.602818 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9638 00:59:03.606266 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9639 00:59:03.612866 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9640 00:59:03.616263 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9641 00:59:03.623011 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9642 00:59:03.626016 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9643 00:59:03.632652 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9644 00:59:03.636247 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9645 00:59:03.642532 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9646 00:59:03.645761 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9647 00:59:03.648871 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9648 00:59:03.655718 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9649 00:59:03.659269 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9650 00:59:03.665626 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9651 00:59:03.668917 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9652 00:59:03.672116 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9653 00:59:03.678910 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9654 00:59:03.681968 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9655 00:59:03.688772 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9656 00:59:03.692150 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9657 00:59:03.698891 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9658 00:59:03.701929 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9659 00:59:03.705402 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9660 00:59:03.711647 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9661 00:59:03.716134 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9662 00:59:03.721687 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9663 00:59:03.724697 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9664 00:59:03.728335 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9665 00:59:03.731342 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9666 00:59:03.738104 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9667 00:59:03.741108 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9668 00:59:03.744903 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9669 00:59:03.751498 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9670 00:59:03.754473 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9671 00:59:03.758041 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9672 00:59:03.764624 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9673 00:59:03.767889 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9674 00:59:03.773962 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9675 00:59:03.777465 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9676 00:59:03.780740 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9677 00:59:03.787712 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9678 00:59:03.791090 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9679 00:59:03.794633 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9680 00:59:03.801286 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9681 00:59:03.803657 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9682 00:59:03.807017 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9683 00:59:03.813546 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9684 00:59:03.817354 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9685 00:59:03.823307 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9686 00:59:03.827068 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9687 00:59:03.829844 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9688 00:59:03.836515 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9689 00:59:03.839849 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9690 00:59:03.846620 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9691 00:59:03.849618 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9692 00:59:03.853124 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9693 00:59:03.860261 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9694 00:59:03.863370 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9695 00:59:03.869825 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9696 00:59:03.872954 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9697 00:59:03.876529 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9698 00:59:03.882903 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9699 00:59:03.886446 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9700 00:59:03.889422 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9701 00:59:03.896280 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9702 00:59:03.899574 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9703 00:59:03.903071 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9704 00:59:03.905782 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9705 00:59:03.912805 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9706 00:59:03.916179 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9707 00:59:03.918980 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9708 00:59:03.922568 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9709 00:59:03.929355 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9710 00:59:03.932240 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9711 00:59:03.935413 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9712 00:59:03.938961 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9713 00:59:03.945291 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9714 00:59:03.948869 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9715 00:59:03.952163 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9716 00:59:03.958746 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9717 00:59:03.962365 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9718 00:59:03.968351 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9719 00:59:03.971816 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9720 00:59:03.978453 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9721 00:59:03.981942 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9722 00:59:03.985798 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9723 00:59:03.991498 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9724 00:59:03.995149 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9725 00:59:04.001470 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9726 00:59:04.004596 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9727 00:59:04.008252 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9728 00:59:04.015068 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9729 00:59:04.018066 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9730 00:59:04.024939 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9731 00:59:04.027912 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9732 00:59:04.034337 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9733 00:59:04.037890 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9734 00:59:04.040707 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9735 00:59:04.047685 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9736 00:59:04.050730 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9737 00:59:04.057407 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9738 00:59:04.060728 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9739 00:59:04.064476 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9740 00:59:04.070621 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9741 00:59:04.074084 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9742 00:59:04.080713 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9743 00:59:04.083540 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9744 00:59:04.090598 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9745 00:59:04.093480 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9746 00:59:04.100000 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9747 00:59:04.103946 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9748 00:59:04.106846 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9749 00:59:04.113424 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9750 00:59:04.116427 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9751 00:59:04.123403 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9752 00:59:04.126379 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9753 00:59:04.133020 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9754 00:59:04.136527 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9755 00:59:04.139894 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9756 00:59:04.146062 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9757 00:59:04.149084 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9758 00:59:04.155924 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9759 00:59:04.159178 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9760 00:59:04.162244 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9761 00:59:04.169545 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9762 00:59:04.172324 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9763 00:59:04.179369 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9764 00:59:04.182486 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9765 00:59:04.185413 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9766 00:59:04.192804 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9767 00:59:04.195843 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9768 00:59:04.202163 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9769 00:59:04.205307 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9770 00:59:04.211765 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9771 00:59:04.215668 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9772 00:59:04.218494 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9773 00:59:04.225413 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9774 00:59:04.228634 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9775 00:59:04.235401 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9776 00:59:04.238480 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9777 00:59:04.245556 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9778 00:59:04.248130 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9779 00:59:04.251721 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9780 00:59:04.258216 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9781 00:59:04.261169 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9782 00:59:04.268180 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9783 00:59:04.271212 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9784 00:59:04.275192 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9785 00:59:04.281243 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9786 00:59:04.284523 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9787 00:59:04.291055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9788 00:59:04.294181 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9789 00:59:04.300743 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9790 00:59:04.304297 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9791 00:59:04.307435 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9792 00:59:04.313939 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9793 00:59:04.317810 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9794 00:59:04.324765 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9795 00:59:04.327216 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9796 00:59:04.334098 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9797 00:59:04.337497 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9798 00:59:04.343857 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9799 00:59:04.347230 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9800 00:59:04.353944 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9801 00:59:04.357024 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9802 00:59:04.360204 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9803 00:59:04.366598 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9804 00:59:04.370195 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9805 00:59:04.376830 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9806 00:59:04.379958 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9807 00:59:04.387358 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9808 00:59:04.389767 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9809 00:59:04.396285 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9810 00:59:04.400390 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9811 00:59:04.402973 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9812 00:59:04.409713 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9813 00:59:04.413081 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9814 00:59:04.419473 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9815 00:59:04.422813 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9816 00:59:04.429360 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9817 00:59:04.433011 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9818 00:59:04.439383 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9819 00:59:04.444152 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9820 00:59:04.446442 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9821 00:59:04.452520 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9822 00:59:04.455563 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9823 00:59:04.462574 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9824 00:59:04.465925 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9825 00:59:04.472450 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9826 00:59:04.475670 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9827 00:59:04.479009 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9828 00:59:04.485234 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9829 00:59:04.489028 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9830 00:59:04.495292 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9831 00:59:04.498968 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9832 00:59:04.505351 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9833 00:59:04.509018 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9834 00:59:04.514869 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9835 00:59:04.518297 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9836 00:59:04.521553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9837 00:59:04.528043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9838 00:59:04.531348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9839 00:59:04.537747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9840 00:59:04.541197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9841 00:59:04.548322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9842 00:59:04.551364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9843 00:59:04.557532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9844 00:59:04.560981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9845 00:59:04.567702 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9846 00:59:04.571211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9847 00:59:04.577458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9848 00:59:04.581081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9849 00:59:04.587411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9850 00:59:04.590909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9851 00:59:04.597054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9852 00:59:04.600736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9853 00:59:04.607210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9854 00:59:04.610405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9855 00:59:04.617236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9856 00:59:04.620211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9857 00:59:04.626702 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9858 00:59:04.630475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9859 00:59:04.636592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9860 00:59:04.640804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9861 00:59:04.646905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9862 00:59:04.649901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9863 00:59:04.656708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9864 00:59:04.659925 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9865 00:59:04.666447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9866 00:59:04.669514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9867 00:59:04.676499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9868 00:59:04.679593 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9869 00:59:04.682982 INFO: [APUAPC] vio 0
9870 00:59:04.685941 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9871 00:59:04.692556 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9872 00:59:04.695838 INFO: [APUAPC] D0_APC_0: 0x400510
9873 00:59:04.699240 INFO: [APUAPC] D0_APC_1: 0x0
9874 00:59:04.702471 INFO: [APUAPC] D0_APC_2: 0x1540
9875 00:59:04.702560 INFO: [APUAPC] D0_APC_3: 0x0
9876 00:59:04.705917 INFO: [APUAPC] D1_APC_0: 0xffffffff
9877 00:59:04.708995 INFO: [APUAPC] D1_APC_1: 0xffffffff
9878 00:59:04.712639 INFO: [APUAPC] D1_APC_2: 0x3fffff
9879 00:59:04.716035 INFO: [APUAPC] D1_APC_3: 0x0
9880 00:59:04.718663 INFO: [APUAPC] D2_APC_0: 0xffffffff
9881 00:59:04.722051 INFO: [APUAPC] D2_APC_1: 0xffffffff
9882 00:59:04.725925 INFO: [APUAPC] D2_APC_2: 0x3fffff
9883 00:59:04.728605 INFO: [APUAPC] D2_APC_3: 0x0
9884 00:59:04.732168 INFO: [APUAPC] D3_APC_0: 0xffffffff
9885 00:59:04.735431 INFO: [APUAPC] D3_APC_1: 0xffffffff
9886 00:59:04.738670 INFO: [APUAPC] D3_APC_2: 0x3fffff
9887 00:59:04.741879 INFO: [APUAPC] D3_APC_3: 0x0
9888 00:59:04.745253 INFO: [APUAPC] D4_APC_0: 0xffffffff
9889 00:59:04.748660 INFO: [APUAPC] D4_APC_1: 0xffffffff
9890 00:59:04.752020 INFO: [APUAPC] D4_APC_2: 0x3fffff
9891 00:59:04.755810 INFO: [APUAPC] D4_APC_3: 0x0
9892 00:59:04.758491 INFO: [APUAPC] D5_APC_0: 0xffffffff
9893 00:59:04.762018 INFO: [APUAPC] D5_APC_1: 0xffffffff
9894 00:59:04.765164 INFO: [APUAPC] D5_APC_2: 0x3fffff
9895 00:59:04.768214 INFO: [APUAPC] D5_APC_3: 0x0
9896 00:59:04.771665 INFO: [APUAPC] D6_APC_0: 0xffffffff
9897 00:59:04.774944 INFO: [APUAPC] D6_APC_1: 0xffffffff
9898 00:59:04.778278 INFO: [APUAPC] D6_APC_2: 0x3fffff
9899 00:59:04.781576 INFO: [APUAPC] D6_APC_3: 0x0
9900 00:59:04.785313 INFO: [APUAPC] D7_APC_0: 0xffffffff
9901 00:59:04.788497 INFO: [APUAPC] D7_APC_1: 0xffffffff
9902 00:59:04.791878 INFO: [APUAPC] D7_APC_2: 0x3fffff
9903 00:59:04.794927 INFO: [APUAPC] D7_APC_3: 0x0
9904 00:59:04.798326 INFO: [APUAPC] D8_APC_0: 0xffffffff
9905 00:59:04.801172 INFO: [APUAPC] D8_APC_1: 0xffffffff
9906 00:59:04.804255 INFO: [APUAPC] D8_APC_2: 0x3fffff
9907 00:59:04.807496 INFO: [APUAPC] D8_APC_3: 0x0
9908 00:59:04.811275 INFO: [APUAPC] D9_APC_0: 0xffffffff
9909 00:59:04.814614 INFO: [APUAPC] D9_APC_1: 0xffffffff
9910 00:59:04.817525 INFO: [APUAPC] D9_APC_2: 0x3fffff
9911 00:59:04.820980 INFO: [APUAPC] D9_APC_3: 0x0
9912 00:59:04.824053 INFO: [APUAPC] D10_APC_0: 0xffffffff
9913 00:59:04.827731 INFO: [APUAPC] D10_APC_1: 0xffffffff
9914 00:59:04.830649 INFO: [APUAPC] D10_APC_2: 0x3fffff
9915 00:59:04.833926 INFO: [APUAPC] D10_APC_3: 0x0
9916 00:59:04.837209 INFO: [APUAPC] D11_APC_0: 0xffffffff
9917 00:59:04.840558 INFO: [APUAPC] D11_APC_1: 0xffffffff
9918 00:59:04.844211 INFO: [APUAPC] D11_APC_2: 0x3fffff
9919 00:59:04.847526 INFO: [APUAPC] D11_APC_3: 0x0
9920 00:59:04.850763 INFO: [APUAPC] D12_APC_0: 0xffffffff
9921 00:59:04.854104 INFO: [APUAPC] D12_APC_1: 0xffffffff
9922 00:59:04.856934 INFO: [APUAPC] D12_APC_2: 0x3fffff
9923 00:59:04.860359 INFO: [APUAPC] D12_APC_3: 0x0
9924 00:59:04.863643 INFO: [APUAPC] D13_APC_0: 0xffffffff
9925 00:59:04.867132 INFO: [APUAPC] D13_APC_1: 0xffffffff
9926 00:59:04.870277 INFO: [APUAPC] D13_APC_2: 0x3fffff
9927 00:59:04.873683 INFO: [APUAPC] D13_APC_3: 0x0
9928 00:59:04.877633 INFO: [APUAPC] D14_APC_0: 0xffffffff
9929 00:59:04.880316 INFO: [APUAPC] D14_APC_1: 0xffffffff
9930 00:59:04.883626 INFO: [APUAPC] D14_APC_2: 0x3fffff
9931 00:59:04.886786 INFO: [APUAPC] D14_APC_3: 0x0
9932 00:59:04.890031 INFO: [APUAPC] D15_APC_0: 0xffffffff
9933 00:59:04.893331 INFO: [APUAPC] D15_APC_1: 0xffffffff
9934 00:59:04.896973 INFO: [APUAPC] D15_APC_2: 0x3fffff
9935 00:59:04.900268 INFO: [APUAPC] D15_APC_3: 0x0
9936 00:59:04.903560 INFO: [APUAPC] APC_CON: 0x4
9937 00:59:04.907255 INFO: [NOCDAPC] D0_APC_0: 0x0
9938 00:59:04.909842 INFO: [NOCDAPC] D0_APC_1: 0x0
9939 00:59:04.913397 INFO: [NOCDAPC] D1_APC_0: 0x0
9940 00:59:04.916832 INFO: [NOCDAPC] D1_APC_1: 0xfff
9941 00:59:04.919702 INFO: [NOCDAPC] D2_APC_0: 0x0
9942 00:59:04.923405 INFO: [NOCDAPC] D2_APC_1: 0xfff
9943 00:59:04.923489 INFO: [NOCDAPC] D3_APC_0: 0x0
9944 00:59:04.926716 INFO: [NOCDAPC] D3_APC_1: 0xfff
9945 00:59:04.929723 INFO: [NOCDAPC] D4_APC_0: 0x0
9946 00:59:04.932952 INFO: [NOCDAPC] D4_APC_1: 0xfff
9947 00:59:04.936126 INFO: [NOCDAPC] D5_APC_0: 0x0
9948 00:59:04.939828 INFO: [NOCDAPC] D5_APC_1: 0xfff
9949 00:59:04.942838 INFO: [NOCDAPC] D6_APC_0: 0x0
9950 00:59:04.946518 INFO: [NOCDAPC] D6_APC_1: 0xfff
9951 00:59:04.949785 INFO: [NOCDAPC] D7_APC_0: 0x0
9952 00:59:04.953054 INFO: [NOCDAPC] D7_APC_1: 0xfff
9953 00:59:04.956046 INFO: [NOCDAPC] D8_APC_0: 0x0
9954 00:59:04.959354 INFO: [NOCDAPC] D8_APC_1: 0xfff
9955 00:59:04.959437 INFO: [NOCDAPC] D9_APC_0: 0x0
9956 00:59:04.962736 INFO: [NOCDAPC] D9_APC_1: 0xfff
9957 00:59:04.965964 INFO: [NOCDAPC] D10_APC_0: 0x0
9958 00:59:04.969527 INFO: [NOCDAPC] D10_APC_1: 0xfff
9959 00:59:04.972221 INFO: [NOCDAPC] D11_APC_0: 0x0
9960 00:59:04.975786 INFO: [NOCDAPC] D11_APC_1: 0xfff
9961 00:59:04.979245 INFO: [NOCDAPC] D12_APC_0: 0x0
9962 00:59:04.982417 INFO: [NOCDAPC] D12_APC_1: 0xfff
9963 00:59:04.985789 INFO: [NOCDAPC] D13_APC_0: 0x0
9964 00:59:04.988929 INFO: [NOCDAPC] D13_APC_1: 0xfff
9965 00:59:04.992352 INFO: [NOCDAPC] D14_APC_0: 0x0
9966 00:59:04.995189 INFO: [NOCDAPC] D14_APC_1: 0xfff
9967 00:59:04.998527 INFO: [NOCDAPC] D15_APC_0: 0x0
9968 00:59:05.002120 INFO: [NOCDAPC] D15_APC_1: 0xfff
9969 00:59:05.005326 INFO: [NOCDAPC] APC_CON: 0x4
9970 00:59:05.008974 INFO: [APUAPC] set_apusys_apc done
9971 00:59:05.012276 INFO: [DEVAPC] devapc_init done
9972 00:59:05.015080 INFO: GICv3 without legacy support detected.
9973 00:59:05.018767 INFO: ARM GICv3 driver initialized in EL3
9974 00:59:05.021617 INFO: Maximum SPI INTID supported: 639
9975 00:59:05.025035 INFO: BL31: Initializing runtime services
9976 00:59:05.031883 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9977 00:59:05.034813 INFO: SPM: enable CPC mode
9978 00:59:05.041722 INFO: mcdi ready for mcusys-off-idle and system suspend
9979 00:59:05.044768 INFO: BL31: Preparing for EL3 exit to normal world
9980 00:59:05.048502 INFO: Entry point address = 0x80000000
9981 00:59:05.051321 INFO: SPSR = 0x8
9982 00:59:05.055806
9983 00:59:05.055911
9984 00:59:05.056011
9985 00:59:05.059211 Starting depthcharge on Spherion...
9986 00:59:05.059286
9987 00:59:05.059351 Wipe memory regions:
9988 00:59:05.059425
9989 00:59:05.060043 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
9990 00:59:05.060155 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
9991 00:59:05.060243 Setting prompt string to ['asurada:']
9992 00:59:05.060322 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
9993 00:59:05.062751 [0x00000040000000, 0x00000054600000)
9994 00:59:05.185126
9995 00:59:05.185336 [0x00000054660000, 0x00000080000000)
9996 00:59:05.445542
9997 00:59:05.445681 [0x000000821a7280, 0x000000ffe64000)
9998 00:59:06.190870
9999 00:59:06.191051 [0x00000100000000, 0x00000240000000)
10000 00:59:08.080108
10001 00:59:08.083510 Initializing XHCI USB controller at 0x11200000.
10002 00:59:09.122663
10003 00:59:09.126070 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10004 00:59:09.126227
10005 00:59:09.126295
10006 00:59:09.126578 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10008 00:59:09.226932 asurada: tftpboot 192.168.201.1 14368604/tftp-deploy-t37rlqdm/kernel/image.itb 14368604/tftp-deploy-t37rlqdm/kernel/cmdline
10009 00:59:09.227069 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10010 00:59:09.227161 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10011 00:59:09.231455 tftpboot 192.168.201.1 14368604/tftp-deploy-t37rlqdm/kernel/image.ittp-deploy-t37rlqdm/kernel/cmdline
10012 00:59:09.231542
10013 00:59:09.231607 Waiting for link
10014 00:59:09.389634
10015 00:59:09.389763 R8152: Initializing
10016 00:59:09.389835
10017 00:59:09.392808 Version 6 (ocp_data = 5c30)
10018 00:59:09.392892
10019 00:59:09.396173 R8152: Done initializing
10020 00:59:09.396257
10021 00:59:09.396323 Adding net device
10022 00:59:11.269860
10023 00:59:11.269996 done.
10024 00:59:11.270066
10025 00:59:11.270129 MAC: 00:24:32:30:7c:7b
10026 00:59:11.270190
10027 00:59:11.272916 Sending DHCP discover... done.
10028 00:59:11.273004
10029 00:59:11.276168 Waiting for reply... done.
10030 00:59:11.276252
10031 00:59:11.279963 Sending DHCP request... done.
10032 00:59:11.280076
10033 00:59:11.284579 Waiting for reply... done.
10034 00:59:11.284663
10035 00:59:11.284730 My ip is 192.168.201.14
10036 00:59:11.284792
10037 00:59:11.287982 The DHCP server ip is 192.168.201.1
10038 00:59:11.288066
10039 00:59:11.294196 TFTP server IP predefined by user: 192.168.201.1
10040 00:59:11.294312
10041 00:59:11.301374 Bootfile predefined by user: 14368604/tftp-deploy-t37rlqdm/kernel/image.itb
10042 00:59:11.301459
10043 00:59:11.304084 Sending tftp read request... done.
10044 00:59:11.304169
10045 00:59:11.307982 Waiting for the transfer...
10046 00:59:11.308065
10047 00:59:11.832674 00000000 ################################################################
10048 00:59:11.832832
10049 00:59:12.358451 00080000 ################################################################
10050 00:59:12.358595
10051 00:59:12.887189 00100000 ################################################################
10052 00:59:12.887332
10053 00:59:13.423018 00180000 ################################################################
10054 00:59:13.423187
10055 00:59:13.942782 00200000 ################################################################
10056 00:59:13.942941
10057 00:59:14.470880 00280000 ################################################################
10058 00:59:14.471014
10059 00:59:14.995360 00300000 ################################################################
10060 00:59:14.995500
10061 00:59:15.536086 00380000 ################################################################
10062 00:59:15.536227
10063 00:59:16.066856 00400000 ################################################################
10064 00:59:16.067016
10065 00:59:16.594195 00480000 ################################################################
10066 00:59:16.594369
10067 00:59:17.120133 00500000 ################################################################
10068 00:59:17.120306
10069 00:59:17.657385 00580000 ################################################################
10070 00:59:17.657530
10071 00:59:18.201763 00600000 ################################################################
10072 00:59:18.201907
10073 00:59:18.760591 00680000 ################################################################
10074 00:59:18.760729
10075 00:59:19.300035 00700000 ################################################################
10076 00:59:19.300173
10077 00:59:19.843589 00780000 ################################################################
10078 00:59:19.843752
10079 00:59:20.390355 00800000 ################################################################
10080 00:59:20.390487
10081 00:59:20.948575 00880000 ################################################################
10082 00:59:20.948740
10083 00:59:21.482994 00900000 ################################################################
10084 00:59:21.483155
10085 00:59:22.018005 00980000 ################################################################
10086 00:59:22.018167
10087 00:59:22.554341 00a00000 ################################################################
10088 00:59:22.554475
10089 00:59:23.085171 00a80000 ################################################################
10090 00:59:23.085366
10091 00:59:23.699382 00b00000 ################################################################
10092 00:59:23.699897
10093 00:59:24.412069 00b80000 ################################################################
10094 00:59:24.412565
10095 00:59:25.108575 00c00000 ################################################################
10096 00:59:25.109068
10097 00:59:25.817799 00c80000 ################################################################
10098 00:59:25.818383
10099 00:59:26.526466 00d00000 ################################################################
10100 00:59:26.526971
10101 00:59:27.216015 00d80000 ################################################################
10102 00:59:27.216515
10103 00:59:27.887566 00e00000 ################################################################
10104 00:59:27.888081
10105 00:59:28.575360 00e80000 ################################################################
10106 00:59:28.575884
10107 00:59:29.278879 00f00000 ################################################################
10108 00:59:29.279383
10109 00:59:29.968271 00f80000 ################################################################
10110 00:59:29.968769
10111 00:59:30.657814 01000000 ################################################################
10112 00:59:30.658335
10113 00:59:31.364519 01080000 ################################################################
10114 00:59:31.365046
10115 00:59:32.042847 01100000 ################################################################
10116 00:59:32.043368
10117 00:59:32.731090 01180000 ################################################################
10118 00:59:32.731615
10119 00:59:33.438472 01200000 ################################################################
10120 00:59:33.439036
10121 00:59:34.140389 01280000 ################################################################
10122 00:59:34.140930
10123 00:59:34.857368 01300000 ################################################################
10124 00:59:34.857922
10125 00:59:35.535270 01380000 ################################################################
10126 00:59:35.535839
10127 00:59:36.219367 01400000 ################################################################
10128 00:59:36.219875
10129 00:59:36.897190 01480000 ################################################################
10130 00:59:36.897732
10131 00:59:37.586026 01500000 ################################################################
10132 00:59:37.586549
10133 00:59:38.250120 01580000 ################################################################
10134 00:59:38.250700
10135 00:59:38.935953 01600000 ################################################################
10136 00:59:38.936445
10137 00:59:39.638665 01680000 ################################################################
10138 00:59:39.639183
10139 00:59:40.310517 01700000 ################################################################
10140 00:59:40.311016
10141 00:59:40.986478 01780000 ################################################################
10142 00:59:40.986989
10143 00:59:41.692110 01800000 ################################################################
10144 00:59:41.692643
10145 00:59:42.377959 01880000 ################################################################
10146 00:59:42.378144
10147 00:59:43.023393 01900000 ################################################################
10148 00:59:43.023934
10149 00:59:43.730994 01980000 ################################################################
10150 00:59:43.731487
10151 00:59:44.430833 01a00000 ################################################################
10152 00:59:44.431005
10153 00:59:45.085794 01a80000 ################################################################
10154 00:59:45.086313
10155 00:59:45.782424 01b00000 ################################################################
10156 00:59:45.782988
10157 00:59:46.485227 01b80000 ################################################################
10158 00:59:46.485812
10159 00:59:47.170345 01c00000 ################################################################
10160 00:59:47.170861
10161 00:59:47.861076 01c80000 ################################################################
10162 00:59:47.861639
10163 00:59:48.570422 01d00000 ################################################################
10164 00:59:48.570950
10165 00:59:49.251237 01d80000 ################################################################
10166 00:59:49.251758
10167 00:59:49.938869 01e00000 ################################################################
10168 00:59:49.939386
10169 00:59:50.643662 01e80000 ################################################################
10170 00:59:50.644185
10171 00:59:51.337556 01f00000 ################################################################
10172 00:59:51.338079
10173 00:59:52.047791 01f80000 ################################################################
10174 00:59:52.048307
10175 00:59:52.744446 02000000 ################################################################
10176 00:59:52.744987
10177 00:59:53.440175 02080000 ################################################################
10178 00:59:53.440690
10179 00:59:54.126983 02100000 ################################################################
10180 00:59:54.127530
10181 00:59:54.823903 02180000 ################################################################
10182 00:59:54.824418
10183 00:59:55.495083 02200000 ################################################################
10184 00:59:55.495226
10185 00:59:56.155386 02280000 ################################################################
10186 00:59:56.155904
10187 00:59:56.848974 02300000 ################################################################
10188 00:59:56.849524
10189 00:59:57.535117 02380000 ################################################################
10190 00:59:57.535651
10191 00:59:58.217754 02400000 ################################################################
10192 00:59:58.218267
10193 00:59:58.876693 02480000 ################################################################
10194 00:59:58.876843
10195 00:59:59.560570 02500000 ################################################################
10196 00:59:59.561085
10197 01:00:00.262789 02580000 ################################################################
10198 01:00:00.263327
10199 01:00:00.964523 02600000 ################################################################
10200 01:00:00.965072
10201 01:00:01.659050 02680000 ################################################################
10202 01:00:01.659633
10203 01:00:02.343902 02700000 ################################################################
10204 01:00:02.344436
10205 01:00:03.022971 02780000 ################################################################
10206 01:00:03.023480
10207 01:00:03.719823 02800000 ################################################################
10208 01:00:03.720338
10209 01:00:04.435979 02880000 ################################################################
10210 01:00:04.436527
10211 01:00:05.136955 02900000 ################################################################
10212 01:00:05.137535
10213 01:00:05.791932 02980000 ################################################################
10214 01:00:05.792085
10215 01:00:06.488901 02a00000 ################################################################
10216 01:00:06.489480
10217 01:00:07.113379 02a80000 ################################################################
10218 01:00:07.113516
10219 01:00:07.681540 02b00000 ################################################################
10220 01:00:07.681680
10221 01:00:08.245200 02b80000 ################################################################
10222 01:00:08.245388
10223 01:00:08.820069 02c00000 ################################################################
10224 01:00:08.820272
10225 01:00:09.385200 02c80000 ################################################################
10226 01:00:09.385371
10227 01:00:09.959262 02d00000 ################################################################
10228 01:00:09.959431
10229 01:00:10.528933 02d80000 ################################################################
10230 01:00:10.529158
10231 01:00:11.110329 02e00000 ################################################################
10232 01:00:11.110510
10233 01:00:11.672977 02e80000 ################################################################
10234 01:00:11.673125
10235 01:00:12.229476 02f00000 ################################################################
10236 01:00:12.229626
10237 01:00:12.784468 02f80000 ################################################################
10238 01:00:12.784641
10239 01:00:13.335696 03000000 ################################################################
10240 01:00:13.335859
10241 01:00:13.903805 03080000 ################################################################
10242 01:00:13.903959
10243 01:00:14.471712 03100000 ################################################################
10244 01:00:14.471863
10245 01:00:15.058432 03180000 ################################################################
10246 01:00:15.058602
10247 01:00:15.629325 03200000 ################################################################
10248 01:00:15.629472
10249 01:00:16.199221 03280000 ################################################################
10250 01:00:16.199354
10251 01:00:16.770559 03300000 ################################################################
10252 01:00:16.770695
10253 01:00:17.365966 03380000 ################################################################
10254 01:00:17.366108
10255 01:00:17.925712 03400000 ################################################################
10256 01:00:17.925853
10257 01:00:18.490744 03480000 ################################################################
10258 01:00:18.490884
10259 01:00:19.051327 03500000 ################################################################
10260 01:00:19.051470
10261 01:00:19.622986 03580000 ################################################################
10262 01:00:19.623138
10263 01:00:20.195797 03600000 ################################################################
10264 01:00:20.195942
10265 01:00:20.760857 03680000 ################################################################
10266 01:00:20.760998
10267 01:00:21.328625 03700000 ################################################################
10268 01:00:21.328772
10269 01:00:21.894886 03780000 ################################################################
10270 01:00:21.895043
10271 01:00:22.456750 03800000 ################################################################
10272 01:00:22.456908
10273 01:00:23.021246 03880000 ################################################################
10274 01:00:23.021413
10275 01:00:23.604292 03900000 ################################################################
10276 01:00:23.604448
10277 01:00:24.177058 03980000 ################################################################
10278 01:00:24.177220
10279 01:00:24.749128 03a00000 ################################################################
10280 01:00:24.749316
10281 01:00:25.319157 03a80000 ################################################################
10282 01:00:25.319309
10283 01:00:25.877812 03b00000 ################################################################
10284 01:00:25.877966
10285 01:00:26.466664 03b80000 ################################################################
10286 01:00:26.466819
10287 01:00:27.030983 03c00000 ################################################################
10288 01:00:27.031133
10289 01:00:27.608974 03c80000 ################################################################
10290 01:00:27.609121
10291 01:00:28.166477 03d00000 ################################################################
10292 01:00:28.166628
10293 01:00:28.734742 03d80000 ################################################################
10294 01:00:28.734890
10295 01:00:29.303787 03e00000 ################################################################
10296 01:00:29.303940
10297 01:00:29.894189 03e80000 ################################################################
10298 01:00:29.894338
10299 01:00:30.460432 03f00000 ################################################################
10300 01:00:30.460571
10301 01:00:31.022714 03f80000 ################################################################
10302 01:00:31.022850
10303 01:00:31.597832 04000000 ################################################################
10304 01:00:31.597988
10305 01:00:32.246608 04080000 ################################################################
10306 01:00:32.247071
10307 01:00:32.930883 04100000 ################################################################
10308 01:00:32.931389
10309 01:00:33.609221 04180000 ################################################################
10310 01:00:33.609783
10311 01:00:34.284910 04200000 ################################################################
10312 01:00:34.285473
10313 01:00:34.980254 04280000 ################################################################
10314 01:00:34.980770
10315 01:00:35.673754 04300000 ################################################################
10316 01:00:35.674269
10317 01:00:36.352213 04380000 ################################################################
10318 01:00:36.352739
10319 01:00:36.996747 04400000 ################################################################
10320 01:00:36.997316
10321 01:00:37.665045 04480000 ################################################################
10322 01:00:37.665597
10323 01:00:38.356368 04500000 ################################################################
10324 01:00:38.357073
10325 01:00:39.032389 04580000 ################################################################
10326 01:00:39.032887
10327 01:00:39.738293 04600000 ################################################################
10328 01:00:39.738810
10329 01:00:40.054528 04680000 ############################## done.
10330 01:00:40.055058
10331 01:00:40.057698 The bootfile was 74168294 bytes long.
10332 01:00:40.058143
10333 01:00:40.060912 Sending tftp read request... done.
10334 01:00:40.061375
10335 01:00:40.065286 Waiting for the transfer...
10336 01:00:40.065729
10337 01:00:40.066063 00000000 # done.
10338 01:00:40.066384
10339 01:00:40.071862 Command line loaded dynamically from TFTP file: 14368604/tftp-deploy-t37rlqdm/kernel/cmdline
10340 01:00:40.072175
10341 01:00:40.084862 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10342 01:00:40.085123
10343 01:00:40.088263 Loading FIT.
10344 01:00:40.088430
10345 01:00:40.091650 Image ramdisk-1 has 60993954 bytes.
10346 01:00:40.091797
10347 01:00:40.094946 Image fdt-1 has 47258 bytes.
10348 01:00:40.095095
10349 01:00:40.095202 Image kernel-1 has 13125045 bytes.
10350 01:00:40.098291
10351 01:00:40.104677 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10352 01:00:40.104821
10353 01:00:40.122041 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10354 01:00:40.125246
10355 01:00:40.128766 Choosing best match conf-1 for compat google,spherion-rev2.
10356 01:00:40.132571
10357 01:00:40.137923 Connected to device vid:did:rid of 1ae0:0028:00
10358 01:00:40.145715
10359 01:00:40.148694 tpm_get_response: command 0x17b, return code 0x0
10360 01:00:40.149124
10361 01:00:40.155822 ec_init: CrosEC protocol v3 supported (256, 248)
10362 01:00:40.156344
10363 01:00:40.158827 tpm_cleanup: add release locality here.
10364 01:00:40.159275
10365 01:00:40.162117 Shutting down all USB controllers.
10366 01:00:40.162533
10367 01:00:40.165478 Removing current net device
10368 01:00:40.165895
10369 01:00:40.168456 Exiting depthcharge with code 4 at timestamp: 124334880
10370 01:00:40.168875
10371 01:00:40.175485 LZMA decompressing kernel-1 to 0x821a6718
10372 01:00:40.175993
10373 01:00:40.178711 LZMA decompressing kernel-1 to 0x40000000
10374 01:00:41.794539
10375 01:00:41.795101 jumping to kernel
10376 01:00:41.797414 end: 2.2.4 bootloader-commands (duration 00:01:37) [common]
10377 01:00:41.797964 start: 2.2.5 auto-login-action (timeout 00:02:50) [common]
10378 01:00:41.798376 Setting prompt string to ['Linux version [0-9]']
10379 01:00:41.798752 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10380 01:00:41.799131 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10381 01:00:41.876387
10382 01:00:41.879073 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10383 01:00:41.883447 start: 2.2.5.1 login-action (timeout 00:02:50) [common]
10384 01:00:41.884057 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10385 01:00:41.884457 Setting prompt string to []
10386 01:00:41.884888 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10387 01:00:41.885309 Using line separator: #'\n'#
10388 01:00:41.885654 No login prompt set.
10389 01:00:41.885997 Parsing kernel messages
10390 01:00:41.886309 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10391 01:00:41.886864 [login-action] Waiting for messages, (timeout 00:02:50)
10392 01:00:41.887233 Waiting using forced prompt support (timeout 00:01:25)
10393 01:00:41.902463 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
10394 01:00:41.906038 [ 0.000000] random: crng init done
10395 01:00:41.912856 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10396 01:00:41.915264 [ 0.000000] efi: UEFI not found.
10397 01:00:41.922102 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10398 01:00:41.932014 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10399 01:00:41.942077 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10400 01:00:41.948822 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10401 01:00:41.955581 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10402 01:00:41.961679 [ 0.000000] printk: bootconsole [mtk8250] enabled
10403 01:00:41.968542 [ 0.000000] NUMA: No NUMA configuration found
10404 01:00:41.974838 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10405 01:00:41.981682 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10406 01:00:41.982272 [ 0.000000] Zone ranges:
10407 01:00:41.988218 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10408 01:00:41.991644 [ 0.000000] DMA32 empty
10409 01:00:41.998012 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10410 01:00:42.001437 [ 0.000000] Movable zone start for each node
10411 01:00:42.004974 [ 0.000000] Early memory node ranges
10412 01:00:42.011718 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10413 01:00:42.017646 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10414 01:00:42.024382 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10415 01:00:42.031669 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10416 01:00:42.037466 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10417 01:00:42.044156 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10418 01:00:42.101113 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10419 01:00:42.107437 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10420 01:00:42.113894 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10421 01:00:42.117663 [ 0.000000] psci: probing for conduit method from DT.
10422 01:00:42.124108 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10423 01:00:42.127190 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10424 01:00:42.134214 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10425 01:00:42.136948 [ 0.000000] psci: SMC Calling Convention v1.2
10426 01:00:42.143908 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10427 01:00:42.147260 [ 0.000000] Detected VIPT I-cache on CPU0
10428 01:00:42.154011 [ 0.000000] CPU features: detected: GIC system register CPU interface
10429 01:00:42.160639 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10430 01:00:42.167340 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10431 01:00:42.173401 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10432 01:00:42.180291 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10433 01:00:42.190730 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10434 01:00:42.193322 [ 0.000000] alternatives: applying boot alternatives
10435 01:00:42.200792 [ 0.000000] Fallback order for Node 0: 0
10436 01:00:42.206807 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10437 01:00:42.210249 [ 0.000000] Policy zone: Normal
10438 01:00:42.223368 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10439 01:00:42.233117 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10440 01:00:42.246039 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10441 01:00:42.254982 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10442 01:00:42.261914 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10443 01:00:42.265316 <6>[ 0.000000] software IO TLB: area num 8.
10444 01:00:42.321617 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10445 01:00:42.471595 <6>[ 0.000000] Memory: 7904496K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 448272K reserved, 32768K cma-reserved)
10446 01:00:42.477858 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10447 01:00:42.484778 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10448 01:00:42.487638 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10449 01:00:42.494544 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10450 01:00:42.500865 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10451 01:00:42.504231 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10452 01:00:42.514215 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10453 01:00:42.520862 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10454 01:00:42.527865 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10455 01:00:42.533822 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10456 01:00:42.537579 <6>[ 0.000000] GICv3: 608 SPIs implemented
10457 01:00:42.540727 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10458 01:00:42.547737 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10459 01:00:42.550572 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10460 01:00:42.557192 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10461 01:00:42.570362 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10462 01:00:42.583553 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10463 01:00:42.590595 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10464 01:00:42.598103 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10465 01:00:42.611543 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10466 01:00:42.617732 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10467 01:00:42.624492 <6>[ 0.009179] Console: colour dummy device 80x25
10468 01:00:42.634311 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10469 01:00:42.641188 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10470 01:00:42.644430 <6>[ 0.029220] LSM: Security Framework initializing
10471 01:00:42.651028 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10472 01:00:42.661121 <6>[ 0.041973] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10473 01:00:42.670346 <6>[ 0.051393] cblist_init_generic: Setting adjustable number of callback queues.
10474 01:00:42.673985 <6>[ 0.058837] cblist_init_generic: Setting shift to 3 and lim to 1.
10475 01:00:42.683582 <6>[ 0.065215] cblist_init_generic: Setting adjustable number of callback queues.
10476 01:00:42.690911 <6>[ 0.072688] cblist_init_generic: Setting shift to 3 and lim to 1.
10477 01:00:42.693528 <6>[ 0.079089] rcu: Hierarchical SRCU implementation.
10478 01:00:42.700768 <6>[ 0.084104] rcu: Max phase no-delay instances is 1000.
10479 01:00:42.707428 <6>[ 0.091130] EFI services will not be available.
10480 01:00:42.710519 <6>[ 0.096091] smp: Bringing up secondary CPUs ...
10481 01:00:42.719247 <6>[ 0.101140] Detected VIPT I-cache on CPU1
10482 01:00:42.725885 <6>[ 0.101210] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10483 01:00:42.732443 <6>[ 0.101242] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10484 01:00:42.735162 <6>[ 0.101583] Detected VIPT I-cache on CPU2
10485 01:00:42.742340 <6>[ 0.101638] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10486 01:00:42.752459 <6>[ 0.101657] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10487 01:00:42.755338 <6>[ 0.101920] Detected VIPT I-cache on CPU3
10488 01:00:42.761401 <6>[ 0.101969] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10489 01:00:42.768772 <6>[ 0.101984] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10490 01:00:42.771874 <6>[ 0.102290] CPU features: detected: Spectre-v4
10491 01:00:42.778225 <6>[ 0.102296] CPU features: detected: Spectre-BHB
10492 01:00:42.781850 <6>[ 0.102301] Detected PIPT I-cache on CPU4
10493 01:00:42.788933 <6>[ 0.102359] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10494 01:00:42.794462 <6>[ 0.102376] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10495 01:00:42.800823 <6>[ 0.102671] Detected PIPT I-cache on CPU5
10496 01:00:42.807552 <6>[ 0.102733] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10497 01:00:42.814245 <6>[ 0.102750] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10498 01:00:42.817465 <6>[ 0.103033] Detected PIPT I-cache on CPU6
10499 01:00:42.823839 <6>[ 0.103098] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10500 01:00:42.831060 <6>[ 0.103114] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10501 01:00:42.837215 <6>[ 0.103412] Detected PIPT I-cache on CPU7
10502 01:00:42.843769 <6>[ 0.103477] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10503 01:00:42.850478 <6>[ 0.103493] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10504 01:00:42.854015 <6>[ 0.103540] smp: Brought up 1 node, 8 CPUs
10505 01:00:42.860589 <6>[ 0.244824] SMP: Total of 8 processors activated.
10506 01:00:42.864473 <6>[ 0.249745] CPU features: detected: 32-bit EL0 Support
10507 01:00:42.874494 <6>[ 0.255108] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10508 01:00:42.880127 <6>[ 0.263963] CPU features: detected: Common not Private translations
10509 01:00:42.886857 <6>[ 0.270439] CPU features: detected: CRC32 instructions
10510 01:00:42.890226 <6>[ 0.275791] CPU features: detected: RCpc load-acquire (LDAPR)
10511 01:00:42.896742 <6>[ 0.281751] CPU features: detected: LSE atomic instructions
10512 01:00:42.903851 <6>[ 0.287533] CPU features: detected: Privileged Access Never
10513 01:00:42.910621 <6>[ 0.293348] CPU features: detected: RAS Extension Support
10514 01:00:42.917056 <6>[ 0.298957] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10515 01:00:42.919984 <6>[ 0.306218] CPU: All CPU(s) started at EL2
10516 01:00:42.926720 <6>[ 0.310535] alternatives: applying system-wide alternatives
10517 01:00:42.935732 <6>[ 0.321364] devtmpfs: initialized
10518 01:00:42.951799 <6>[ 0.330300] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10519 01:00:42.958578 <6>[ 0.340260] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10520 01:00:42.965424 <6>[ 0.348275] pinctrl core: initialized pinctrl subsystem
10521 01:00:42.968820 <6>[ 0.354954] DMI not present or invalid.
10522 01:00:42.974743 <6>[ 0.359366] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10523 01:00:42.984596 <6>[ 0.366226] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10524 01:00:42.991837 <6>[ 0.373819] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10525 01:00:43.001809 <6>[ 0.382037] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10526 01:00:43.004655 <6>[ 0.390281] audit: initializing netlink subsys (disabled)
10527 01:00:43.014561 <5>[ 0.395976] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10528 01:00:43.021660 <6>[ 0.396697] thermal_sys: Registered thermal governor 'step_wise'
10529 01:00:43.028142 <6>[ 0.403944] thermal_sys: Registered thermal governor 'power_allocator'
10530 01:00:43.031215 <6>[ 0.410199] cpuidle: using governor menu
10531 01:00:43.038479 <6>[ 0.421157] NET: Registered PF_QIPCRTR protocol family
10532 01:00:43.044397 <6>[ 0.426634] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10533 01:00:43.048189 <6>[ 0.433738] ASID allocator initialised with 32768 entries
10534 01:00:43.055835 <6>[ 0.440327] Serial: AMBA PL011 UART driver
10535 01:00:43.064435 <4>[ 0.449187] Trying to register duplicate clock ID: 134
10536 01:00:43.124774 <6>[ 0.512440] KASLR enabled
10537 01:00:43.139109 <6>[ 0.520128] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10538 01:00:43.145409 <6>[ 0.527139] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10539 01:00:43.152144 <6>[ 0.533628] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10540 01:00:43.158666 <6>[ 0.540633] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10541 01:00:43.164875 <6>[ 0.547122] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10542 01:00:43.171625 <6>[ 0.554127] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10543 01:00:43.178254 <6>[ 0.560613] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10544 01:00:43.184757 <6>[ 0.567617] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10545 01:00:43.188434 <6>[ 0.575090] ACPI: Interpreter disabled.
10546 01:00:43.196805 <6>[ 0.581517] iommu: Default domain type: Translated
10547 01:00:43.203366 <6>[ 0.586667] iommu: DMA domain TLB invalidation policy: strict mode
10548 01:00:43.206311 <5>[ 0.593327] SCSI subsystem initialized
10549 01:00:43.213811 <6>[ 0.597575] usbcore: registered new interface driver usbfs
10550 01:00:43.219892 <6>[ 0.603307] usbcore: registered new interface driver hub
10551 01:00:43.223390 <6>[ 0.608856] usbcore: registered new device driver usb
10552 01:00:43.229952 <6>[ 0.614973] pps_core: LinuxPPS API ver. 1 registered
10553 01:00:43.240588 <6>[ 0.620168] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10554 01:00:43.243332 <6>[ 0.629513] PTP clock support registered
10555 01:00:43.246324 <6>[ 0.633758] EDAC MC: Ver: 3.0.0
10556 01:00:43.254515 <6>[ 0.638953] FPGA manager framework
10557 01:00:43.260392 <6>[ 0.642633] Advanced Linux Sound Architecture Driver Initialized.
10558 01:00:43.263991 <6>[ 0.649417] vgaarb: loaded
10559 01:00:43.270773 <6>[ 0.652513] clocksource: Switched to clocksource arch_sys_counter
10560 01:00:43.274389 <5>[ 0.658957] VFS: Disk quotas dquot_6.6.0
10561 01:00:43.280639 <6>[ 0.663143] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10562 01:00:43.283864 <6>[ 0.670336] pnp: PnP ACPI: disabled
10563 01:00:43.292619 <6>[ 0.677083] NET: Registered PF_INET protocol family
10564 01:00:43.302443 <6>[ 0.682671] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10565 01:00:43.313319 <6>[ 0.694994] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10566 01:00:43.323321 <6>[ 0.703808] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10567 01:00:43.329702 <6>[ 0.711776] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10568 01:00:43.339711 <6>[ 0.720475] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10569 01:00:43.346290 <6>[ 0.730231] TCP: Hash tables configured (established 65536 bind 65536)
10570 01:00:43.352846 <6>[ 0.737102] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10571 01:00:43.362720 <6>[ 0.744301] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10572 01:00:43.368974 <6>[ 0.752007] NET: Registered PF_UNIX/PF_LOCAL protocol family
10573 01:00:43.376500 <6>[ 0.758156] RPC: Registered named UNIX socket transport module.
10574 01:00:43.379795 <6>[ 0.764311] RPC: Registered udp transport module.
10575 01:00:43.385448 <6>[ 0.769245] RPC: Registered tcp transport module.
10576 01:00:43.392405 <6>[ 0.774179] RPC: Registered tcp NFSv4.1 backchannel transport module.
10577 01:00:43.395558 <6>[ 0.780846] PCI: CLS 0 bytes, default 64
10578 01:00:43.399383 <6>[ 0.785214] Unpacking initramfs...
10579 01:00:43.409125 <6>[ 0.788951] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10580 01:00:43.415652 <6>[ 0.797587] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10581 01:00:43.422023 <6>[ 0.806369] kvm [1]: IPA Size Limit: 40 bits
10582 01:00:43.425117 <6>[ 0.810894] kvm [1]: GICv3: no GICV resource entry
10583 01:00:43.431780 <6>[ 0.815917] kvm [1]: disabling GICv2 emulation
10584 01:00:43.438853 <6>[ 0.820608] kvm [1]: GIC system register CPU interface enabled
10585 01:00:43.441754 <6>[ 0.826774] kvm [1]: vgic interrupt IRQ18
10586 01:00:43.448173 <6>[ 0.832598] kvm [1]: VHE mode initialized successfully
10587 01:00:43.455364 <5>[ 0.839040] Initialise system trusted keyrings
10588 01:00:43.461383 <6>[ 0.843839] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10589 01:00:43.468894 <6>[ 0.853872] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10590 01:00:43.475616 <5>[ 0.860249] NFS: Registering the id_resolver key type
10591 01:00:43.478872 <5>[ 0.865553] Key type id_resolver registered
10592 01:00:43.485504 <5>[ 0.869967] Key type id_legacy registered
10593 01:00:43.491970 <6>[ 0.874253] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10594 01:00:43.498588 <6>[ 0.881176] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10595 01:00:43.505003 <6>[ 0.888946] 9p: Installing v9fs 9p2000 file system support
10596 01:00:43.541645 <5>[ 0.926282] Key type asymmetric registered
10597 01:00:43.544526 <5>[ 0.930618] Asymmetric key parser 'x509' registered
10598 01:00:43.554467 <6>[ 0.935765] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10599 01:00:43.557542 <6>[ 0.943379] io scheduler mq-deadline registered
10600 01:00:43.560841 <6>[ 0.948140] io scheduler kyber registered
10601 01:00:43.580337 <6>[ 0.965338] EINJ: ACPI disabled.
10602 01:00:43.613031 <4>[ 0.991337] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10603 01:00:43.623268 <4>[ 1.001977] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10604 01:00:43.637897 <6>[ 1.022986] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10605 01:00:43.645830 <6>[ 1.030970] printk: console [ttyS0] disabled
10606 01:00:43.674057 <6>[ 1.055618] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10607 01:00:43.680788 <6>[ 1.065102] printk: console [ttyS0] enabled
10608 01:00:43.683947 <6>[ 1.065102] printk: console [ttyS0] enabled
10609 01:00:43.691518 <6>[ 1.074000] printk: bootconsole [mtk8250] disabled
10610 01:00:43.693794 <6>[ 1.074000] printk: bootconsole [mtk8250] disabled
10611 01:00:43.700161 <6>[ 1.085336] SuperH (H)SCI(F) driver initialized
10612 01:00:43.703755 <6>[ 1.090622] msm_serial: driver initialized
10613 01:00:43.718121 <6>[ 1.099736] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10614 01:00:43.728419 <6>[ 1.108288] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10615 01:00:43.734484 <6>[ 1.116832] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10616 01:00:43.745328 <6>[ 1.125461] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10617 01:00:43.754464 <6>[ 1.134170] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10618 01:00:43.761065 <6>[ 1.142897] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10619 01:00:43.770749 <6>[ 1.151437] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10620 01:00:43.777189 <6>[ 1.160249] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10621 01:00:43.787158 <6>[ 1.168796] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10622 01:00:43.799380 <6>[ 1.184465] loop: module loaded
10623 01:00:43.806412 <6>[ 1.190318] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10624 01:00:43.829334 <4>[ 1.213909] mtk-pmic-keys: Failed to locate of_node [id: -1]
10625 01:00:43.836007 <6>[ 1.221028] megasas: 07.719.03.00-rc1
10626 01:00:43.845720 <6>[ 1.230991] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10627 01:00:43.855934 <6>[ 1.239908] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10628 01:00:43.872050 <6>[ 1.256417] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10629 01:00:43.927388 <6>[ 1.305729] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10630 01:00:46.089733 <6>[ 3.474864] Freeing initrd memory: 59560K
10631 01:00:46.101003 <6>[ 3.486408] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10632 01:00:46.112156 <6>[ 3.497315] tun: Universal TUN/TAP device driver, 1.6
10633 01:00:46.115275 <6>[ 3.503374] thunder_xcv, ver 1.0
10634 01:00:46.118667 <6>[ 3.506876] thunder_bgx, ver 1.0
10635 01:00:46.121960 <6>[ 3.510371] nicpf, ver 1.0
10636 01:00:46.132622 <6>[ 3.514396] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10637 01:00:46.135800 <6>[ 3.521872] hns3: Copyright (c) 2017 Huawei Corporation.
10638 01:00:46.142472 <6>[ 3.527459] hclge is initializing
10639 01:00:46.146180 <6>[ 3.531040] e1000: Intel(R) PRO/1000 Network Driver
10640 01:00:46.152396 <6>[ 3.536170] e1000: Copyright (c) 1999-2006 Intel Corporation.
10641 01:00:46.155882 <6>[ 3.542189] e1000e: Intel(R) PRO/1000 Network Driver
10642 01:00:46.162052 <6>[ 3.547404] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10643 01:00:46.168997 <6>[ 3.553590] igb: Intel(R) Gigabit Ethernet Network Driver
10644 01:00:46.175428 <6>[ 3.559239] igb: Copyright (c) 2007-2014 Intel Corporation.
10645 01:00:46.182264 <6>[ 3.565075] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10646 01:00:46.189191 <6>[ 3.571593] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10647 01:00:46.192287 <6>[ 3.578055] sky2: driver version 1.30
10648 01:00:46.198727 <6>[ 3.582977] usbcore: registered new device driver r8152-cfgselector
10649 01:00:46.205385 <6>[ 3.589513] usbcore: registered new interface driver r8152
10650 01:00:46.211721 <6>[ 3.595327] VFIO - User Level meta-driver version: 0.3
10651 01:00:46.218538 <6>[ 3.603551] usbcore: registered new interface driver usb-storage
10652 01:00:46.224924 <6>[ 3.610003] usbcore: registered new device driver onboard-usb-hub
10653 01:00:46.233931 <6>[ 3.619118] mt6397-rtc mt6359-rtc: registered as rtc0
10654 01:00:46.243579 <6>[ 3.624595] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T01:00:45 UTC (1718499645)
10655 01:00:46.246743 <6>[ 3.634196] i2c_dev: i2c /dev entries driver
10656 01:00:46.260983 <4>[ 3.646168] cpu cpu0: supply cpu not found, using dummy regulator
10657 01:00:46.267657 <4>[ 3.652604] cpu cpu1: supply cpu not found, using dummy regulator
10658 01:00:46.274057 <4>[ 3.659028] cpu cpu2: supply cpu not found, using dummy regulator
10659 01:00:46.280599 <4>[ 3.665428] cpu cpu3: supply cpu not found, using dummy regulator
10660 01:00:46.287349 <4>[ 3.671829] cpu cpu4: supply cpu not found, using dummy regulator
10661 01:00:46.294277 <4>[ 3.678224] cpu cpu5: supply cpu not found, using dummy regulator
10662 01:00:46.300656 <4>[ 3.684624] cpu cpu6: supply cpu not found, using dummy regulator
10663 01:00:46.307324 <4>[ 3.691033] cpu cpu7: supply cpu not found, using dummy regulator
10664 01:00:46.326683 <6>[ 3.711668] cpu cpu0: EM: created perf domain
10665 01:00:46.329714 <6>[ 3.716594] cpu cpu4: EM: created perf domain
10666 01:00:46.337387 <6>[ 3.722158] sdhci: Secure Digital Host Controller Interface driver
10667 01:00:46.343917 <6>[ 3.728593] sdhci: Copyright(c) Pierre Ossman
10668 01:00:46.350777 <6>[ 3.733559] Synopsys Designware Multimedia Card Interface Driver
10669 01:00:46.353493 <6>[ 3.740186] mmc0: CQHCI version 5.10
10670 01:00:46.359893 <6>[ 3.740193] sdhci-pltfm: SDHCI platform and OF driver helper
10671 01:00:46.366335 <6>[ 3.751012] ledtrig-cpu: registered to indicate activity on CPUs
10672 01:00:46.373088 <6>[ 3.757908] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10673 01:00:46.379652 <6>[ 3.764962] usbcore: registered new interface driver usbhid
10674 01:00:46.383247 <6>[ 3.770784] usbhid: USB HID core driver
10675 01:00:46.393429 <6>[ 3.774985] spi_master spi0: will run message pump with realtime priority
10676 01:00:46.439051 <6>[ 3.817540] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10677 01:00:46.459572 <6>[ 3.834383] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10678 01:00:46.462560 <6>[ 3.839572] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15014
10679 01:00:46.469510 <6>[ 3.849484] cros-ec-spi spi0.0: Chrome EC device registered
10680 01:00:46.472809 <6>[ 3.859859] mmc0: Command Queue Engine enabled
10681 01:00:46.479601 <6>[ 3.864600] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10682 01:00:46.486929 <6>[ 3.872042] mmcblk0: mmc0:0001 DA4128 116 GiB
10683 01:00:46.496784 <6>[ 3.874364] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10684 01:00:46.503390 <6>[ 3.881867] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10685 01:00:46.506366 <6>[ 3.887007] NET: Registered PF_PACKET protocol family
10686 01:00:46.513069 <6>[ 3.893503] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10687 01:00:46.516505 <6>[ 3.897341] 9pnet: Installing 9P2000 support
10688 01:00:46.523374 <6>[ 3.903200] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10689 01:00:46.526465 <5>[ 3.907045] Key type dns_resolver registered
10690 01:00:46.533606 <6>[ 3.912917] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10691 01:00:46.536502 <6>[ 3.917257] registered taskstats version 1
10692 01:00:46.543320 <5>[ 3.927668] Loading compiled-in X.509 certificates
10693 01:00:46.571037 <4>[ 3.949724] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10694 01:00:46.581294 <4>[ 3.960461] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10695 01:00:46.594565 <6>[ 3.980091] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10696 01:00:46.601871 <6>[ 3.986903] xhci-mtk 11200000.usb: xHCI Host Controller
10697 01:00:46.608510 <6>[ 3.992404] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10698 01:00:46.618311 <6>[ 4.000259] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10699 01:00:46.625865 <6>[ 4.009688] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10700 01:00:46.631945 <6>[ 4.015778] xhci-mtk 11200000.usb: xHCI Host Controller
10701 01:00:46.638134 <6>[ 4.021275] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10702 01:00:46.644708 <6>[ 4.029067] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10703 01:00:46.652186 <6>[ 4.037022] hub 1-0:1.0: USB hub found
10704 01:00:46.654883 <6>[ 4.041053] hub 1-0:1.0: 1 port detected
10705 01:00:46.665348 <6>[ 4.045387] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10706 01:00:46.668355 <6>[ 4.054164] hub 2-0:1.0: USB hub found
10707 01:00:46.672003 <6>[ 4.058192] hub 2-0:1.0: 1 port detected
10708 01:00:46.680806 <6>[ 4.065923] mtk-msdc 11f70000.mmc: Got CD GPIO
10709 01:00:46.700169 <6>[ 4.081721] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10710 01:00:46.709627 <6>[ 4.090096] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10711 01:00:46.716157 <6>[ 4.098437] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10712 01:00:46.726534 <6>[ 4.106777] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10713 01:00:46.732897 <6>[ 4.115118] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10714 01:00:46.743237 <6>[ 4.123456] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10715 01:00:46.749686 <6>[ 4.131797] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10716 01:00:46.759650 <6>[ 4.140140] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10717 01:00:46.766590 <6>[ 4.148478] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10718 01:00:46.775934 <6>[ 4.156815] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10719 01:00:46.782336 <6>[ 4.165161] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10720 01:00:46.792280 <6>[ 4.173500] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10721 01:00:46.799511 <6>[ 4.181838] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10722 01:00:46.809056 <6>[ 4.190175] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10723 01:00:46.815276 <6>[ 4.198513] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10724 01:00:46.822026 <6>[ 4.207214] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10725 01:00:46.829654 <6>[ 4.214373] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10726 01:00:46.836150 <6>[ 4.221181] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10727 01:00:46.846337 <6>[ 4.227961] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10728 01:00:46.852642 <6>[ 4.234896] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10729 01:00:46.859276 <6>[ 4.241762] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10730 01:00:46.868702 <6>[ 4.250895] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10731 01:00:46.879477 <6>[ 4.260014] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10732 01:00:46.888738 <6>[ 4.269312] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10733 01:00:46.898578 <6>[ 4.278780] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10734 01:00:46.908866 <6>[ 4.288246] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10735 01:00:46.916065 <6>[ 4.297365] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10736 01:00:46.925602 <6>[ 4.306832] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10737 01:00:46.935047 <6>[ 4.315960] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10738 01:00:46.945064 <6>[ 4.325254] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10739 01:00:46.954653 <6>[ 4.335415] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10740 01:00:46.965222 <6>[ 4.346966] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10741 01:00:47.062946 <6>[ 4.445017] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10742 01:00:47.090445 <6>[ 4.475745] hub 2-1:1.0: USB hub found
10743 01:00:47.093666 <6>[ 4.480195] hub 2-1:1.0: 3 ports detected
10744 01:00:47.103717 <6>[ 4.488340] hub 2-1:1.0: USB hub found
10745 01:00:47.106613 <6>[ 4.492820] hub 2-1:1.0: 3 ports detected
10746 01:00:47.214780 <6>[ 4.596798] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10747 01:00:47.369835 <6>[ 4.754946] hub 1-1:1.0: USB hub found
10748 01:00:47.373941 <6>[ 4.759445] hub 1-1:1.0: 4 ports detected
10749 01:00:47.385812 <6>[ 4.771215] hub 1-1:1.0: USB hub found
10750 01:00:47.388975 <6>[ 4.775631] hub 1-1:1.0: 4 ports detected
10751 01:00:47.447191 <6>[ 4.828904] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10752 01:00:47.555861 <6>[ 4.937212] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10753 01:00:47.587702 <4>[ 4.969547] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10754 01:00:47.597012 <4>[ 4.978676] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10755 01:00:47.632546 <6>[ 5.017698] r8152 2-1.3:1.0 eth0: v1.12.13
10756 01:00:47.711130 <6>[ 5.092821] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10757 01:00:47.842924 <6>[ 5.228657] hub 1-1.4:1.0: USB hub found
10758 01:00:47.846481 <6>[ 5.233328] hub 1-1.4:1.0: 2 ports detected
10759 01:00:47.860202 <6>[ 5.245262] hub 1-1.4:1.0: USB hub found
10760 01:00:47.863777 <6>[ 5.249844] hub 1-1.4:1.0: 2 ports detected
10761 01:00:48.158416 <6>[ 5.540829] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10762 01:00:48.354409 <6>[ 5.736798] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10763 01:00:49.292827 <6>[ 6.678977] r8152 2-1.3:1.0 eth0: carrier on
10764 01:00:51.730092 <5>[ 6.700635] Sending DHCP requests .., OK
10765 01:00:51.736933 <6>[ 9.120977] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10766 01:00:51.740446 <6>[ 9.129269] IP-Config: Complete:
10767 01:00:51.753469 <6>[ 9.132769] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10768 01:00:51.759861 <6>[ 9.143475] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10769 01:00:51.767121 <6>[ 9.152093] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10770 01:00:51.773299 <6>[ 9.152102] nameserver0=192.168.201.1
10771 01:00:51.776425 <6>[ 9.164263] clk: Disabling unused clocks
10772 01:00:51.780024 <6>[ 9.169807] ALSA device list:
10773 01:00:51.786424 <6>[ 9.173061] No soundcards found.
10774 01:00:51.793887 <6>[ 9.180332] Freeing unused kernel memory: 8512K
10775 01:00:51.797430 <6>[ 9.185292] Run /init as init process
10776 01:00:51.826941 <6>[ 9.213399] NET: Registered PF_INET6 protocol family
10777 01:00:51.833915 <6>[ 9.220183] Segment Routing with IPv6
10778 01:00:51.837137 <6>[ 9.224139] In-situ OAM (IOAM) with IPv6
10779 01:00:51.878805 <30>[ 9.238516] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10780 01:00:51.885151 <30>[ 9.271588] systemd[1]: Detected architecture arm64.
10781 01:00:51.885266
10782 01:00:51.891825 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10783 01:00:51.891933
10784 01:00:51.906918 <30>[ 9.292862] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10785 01:00:52.036772 <30>[ 9.419789] systemd[1]: Queued start job for default target graphical.target.
10786 01:00:52.067486 <30>[ 9.450851] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10787 01:00:52.073857 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10788 01:00:52.094339 <30>[ 9.477201] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10789 01:00:52.104287 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10790 01:00:52.123504 <30>[ 9.506548] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10791 01:00:52.133126 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10792 01:00:52.150702 <30>[ 9.533889] systemd[1]: Created slice user.slice - User and Session Slice.
10793 01:00:52.157294 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10794 01:00:52.177118 <30>[ 9.557172] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10795 01:00:52.187096 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10796 01:00:52.205211 <30>[ 9.584983] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10797 01:00:52.211861 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10798 01:00:52.240330 <30>[ 9.613374] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10799 01:00:52.250607 <30>[ 9.633274] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10800 01:00:52.256465 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10801 01:00:52.273837 <30>[ 9.656819] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10802 01:00:52.280441 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10803 01:00:52.297701 <30>[ 9.680851] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10804 01:00:52.307441 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10805 01:00:52.322938 <30>[ 9.708905] systemd[1]: Reached target paths.target - Path Units.
10806 01:00:52.332061 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10807 01:00:52.350050 <30>[ 9.733251] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10808 01:00:52.356541 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10809 01:00:52.370549 <30>[ 9.756864] systemd[1]: Reached target slices.target - Slice Units.
10810 01:00:52.380656 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10811 01:00:52.394961 <30>[ 9.781320] systemd[1]: Reached target swap.target - Swaps.
10812 01:00:52.401192 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10813 01:00:52.422130 <30>[ 9.805336] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10814 01:00:52.431849 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10815 01:00:52.450221 <30>[ 9.833384] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10816 01:00:52.459895 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10817 01:00:52.479102 <30>[ 9.862279] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10818 01:00:52.489071 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10819 01:00:52.506038 <30>[ 9.889399] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10820 01:00:52.515870 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10821 01:00:52.535897 <30>[ 9.918118] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10822 01:00:52.541679 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10823 01:00:52.562425 <30>[ 9.945492] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10824 01:00:52.571930 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10825 01:00:52.589997 <30>[ 9.973294] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10826 01:00:52.600025 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10827 01:00:52.653917 <30>[ 10.037038] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10828 01:00:52.660785 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10829 01:00:52.673567 <30>[ 10.056533] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10830 01:00:52.680445 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10831 01:00:52.702350 <30>[ 10.085171] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10832 01:00:52.708743 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10833 01:00:52.732654 <30>[ 10.109237] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10834 01:00:52.746428 <30>[ 10.129554] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10835 01:00:52.756548 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10836 01:00:52.778218 <30>[ 10.161427] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10837 01:00:52.787215 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10838 01:00:52.810753 <30>[ 10.193812] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10839 01:00:52.823844 Starting [0;1;39mmodpr<6>[ 10.204780] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10840 01:00:52.826908 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10841 01:00:52.882112 <30>[ 10.265410] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10842 01:00:52.888881 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10843 01:00:52.910006 <30>[ 10.293293] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10844 01:00:52.919844 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10845 01:00:52.981907 <30>[ 10.365148] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10846 01:00:52.988302 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10847 01:00:53.014299 <30>[ 10.397091] systemd[1]: Starting systemd-journald.service - Journal Service...
10848 01:00:53.020661 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10849 01:00:53.040505 <30>[ 10.423608] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10850 01:00:53.047142 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10851 01:00:53.075565 <30>[ 10.455643] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10852 01:00:53.082451 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10853 01:00:53.109918 <30>[ 10.492979] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10854 01:00:53.120061 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10855 01:00:53.144083 <30>[ 10.527051] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10856 01:00:53.150783 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10857 01:00:53.178102 <30>[ 10.561191] systemd[1]: Started systemd-journald.service - Journal Service.
10858 01:00:53.184493 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10859 01:00:53.208242 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10860 01:00:53.230214 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10861 01:00:53.254611 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10862 01:00:53.274942 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10863 01:00:53.295822 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10864 01:00:53.316380 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10865 01:00:53.335704 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10866 01:00:53.355904 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10867 01:00:53.377913 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10868 01:00:53.395958 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10869 01:00:53.418917 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10870 01:00:53.440250 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10871 01:00:53.458410 See 'systemctl status systemd-remount-fs.service' for details.
10872 01:00:53.468800 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10873 01:00:53.488241 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10874 01:00:53.545853 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10875 01:00:53.564286 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10876 01:00:53.581390 <46>[ 10.964148] systemd-journald[181]: Received client request to flush runtime journal.
10877 01:00:53.593202 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10878 01:00:53.618750 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10879 01:00:53.647066 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10880 01:00:53.680623 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10881 01:00:53.698853 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10882 01:00:53.718864 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10883 01:00:53.739371 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10884 01:00:53.758935 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10885 01:00:53.818314 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10886 01:00:53.841234 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10887 01:00:53.858030 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10888 01:00:53.878734 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10889 01:00:53.922151 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10890 01:00:53.942825 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10891 01:00:53.965880 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10892 01:00:54.016840 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10893 01:00:54.040398 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10894 01:00:54.062243 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10895 01:00:54.121029 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10896 01:00:54.140575 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10897 01:00:54.168863 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10898 01:00:54.273827 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10899 01:00:54.291239 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10900 01:00:54.310716 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10901 01:00:54.332445 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10902 01:00:54.350453 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10903 01:00:54.367139 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10904 01:00:54.378613 <3>[ 11.761335] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10905 01:00:54.384384 <6>[ 11.762797] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10906 01:00:54.394555 <3>[ 11.769488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10907 01:00:54.401118 <3>[ 11.785276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 01:00:54.407608 <6>[ 11.786362] remoteproc remoteproc0: scp is available
10909 01:00:54.414179 [[0;32m OK [<6>[ 11.798860] remoteproc remoteproc0: powering up scp
10910 01:00:54.420873 0m] Reached targ<6>[ 11.799388] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10911 01:00:54.430766 et [0;1;39msock<3>[ 11.800739] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10912 01:00:54.440542 <3>[ 11.800754] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10913 01:00:54.447676 <3>[ 11.800762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10914 01:00:54.457289 ets.target[0m -<3>[ 11.800769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 01:00:54.467520 <3>[ 11.800776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10916 01:00:54.467608 Socket Units.
10917 01:00:54.474211 <6>[ 11.804751] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10918 01:00:54.484202 <6>[ 11.805406] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10919 01:00:54.490425 <6>[ 11.805444] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10920 01:00:54.497182 <3>[ 11.806919] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 01:00:54.507164 <6>[ 11.814277] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10922 01:00:54.513962 <6>[ 11.816304] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10923 01:00:54.514043
10924 01:00:54.523699 <6>[ 11.816309] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10925 01:00:54.530249 <4>[ 11.816469] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10926 01:00:54.540099 <6>[ 11.817128] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10927 01:00:54.546628 <6>[ 11.817133] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10928 01:00:54.556492 <6>[ 11.822007] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10929 01:00:54.563372 <6>[ 11.822036] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10930 01:00:54.570458 <6>[ 11.822041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10931 01:00:54.580272 <6>[ 11.822048] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10932 01:00:54.586413 <3>[ 11.881121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10933 01:00:54.596865 <6>[ 11.889153] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10934 01:00:54.605871 <3>[ 11.897983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10935 01:00:54.612921 <6>[ 11.930892] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10936 01:00:54.619565 <6>[ 11.930936] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10937 01:00:54.626064 <6>[ 11.930944] remoteproc remoteproc0: remote processor scp is now up
10938 01:00:54.635794 <3>[ 11.938682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10939 01:00:54.642354 <4>[ 11.956275] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10940 01:00:54.648720 <3>[ 12.004167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10941 01:00:54.655531 <6>[ 12.004555] mc: Linux media interface: v0.10
10942 01:00:54.661945 <4>[ 12.018779] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10943 01:00:54.668432 <3>[ 12.026444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10944 01:00:54.678588 <3>[ 12.026454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10945 01:00:54.685098 <3>[ 12.026459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10946 01:00:54.694916 <6>[ 12.042790] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10947 01:00:54.701479 <3>[ 12.046354] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10948 01:00:54.714993 [[0;32m OK [0m] Reached targ<3>[ 12.095623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10949 01:00:54.721346 et [0;1;39mbasi<6>[ 12.095749] videodev: Linux video capture interface: v2.00
10950 01:00:54.724171 c.target[0m - Basic System.
10951 01:00:54.740368 <6>[ 12.120796] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10952 01:00:54.746965 <4>[ 12.123833] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10953 01:00:54.754199 <4>[ 12.123833] Fallback method does not support PEC.
10954 01:00:54.765848 <6>[ 12.149060] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10955 01:00:54.772492 <6>[ 12.149639] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10956 01:00:54.780235 <6>[ 12.165900] pci_bus 0000:00: root bus resource [bus 00-ff]
10957 01:00:54.786206 <6>[ 12.171753] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10958 01:00:54.796076 <3>[ 12.172325] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 01:00:54.806046 <6>[ 12.179197] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10960 01:00:54.813090 <6>[ 12.197825] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10961 01:00:54.820569 <6>[ 12.204194] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10962 01:00:54.830161 <3>[ 12.211244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 01:00:54.833267 <6>[ 12.211760] pci 0000:00:00.0: supports D1 D2
10964 01:00:54.840313 <6>[ 12.224975] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10965 01:00:54.849667 <6>[ 12.227692] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10966 01:00:54.883660 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10967 01:00:54.962455 <6>[ 12.349304] Bluetooth: Core ver 2.22
10968 01:00:54.972564 <6>[ 12.359380] NET: Registered PF_BLUETOOTH protocol family
10969 01:00:54.979470 <6>[ 12.365257] Bluetooth: HCI device and connection manager initialized
10970 01:00:54.985777 <6>[ 12.372573] Bluetooth: HCI socket layer initialized
10971 01:00:54.992606 <6>[ 12.377830] Bluetooth: L2CAP socket layer initialized
10972 01:00:54.996017 <6>[ 12.383765] Bluetooth: SCO socket layer initialized
10973 01:00:55.010173 <6>[ 12.393732] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10974 01:00:55.030080 <6>[ 12.416884] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10975 01:00:55.040469 <4>[ 12.417992] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10976 01:00:55.050113 <6>[ 12.423400] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10977 01:00:55.057355 <3>[ 12.433693] Bluetooth: hci0: Failed to load firmware file (-2)
10978 01:00:55.060120 <3>[ 12.433695] Bluetooth: hci0: Failed to set up firmware (-2)
10979 01:00:55.073531 <4>[ 12.433697] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10980 01:00:55.080352 <6>[ 12.463692] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10981 01:00:55.086892 <6>[ 12.471302] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10982 01:00:55.090344 <6>[ 12.479075] pci 0000:01:00.0: supports D1 D2
10983 01:00:55.100438 <6>[ 12.483769] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10984 01:00:55.106846 <3>[ 12.490658] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 01:00:55.113558 <6>[ 12.493306] usbcore: registered new interface driver btusb
10986 01:00:55.120196 <6>[ 12.502334] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10987 01:00:55.133936 Starting [0;1;39msystemd-logind.se…i<6>[ 12.516793] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10988 01:00:55.143666 ce[0m - User Lo<6>[ 12.523895] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10989 01:00:55.153263 gin Management..<6>[ 12.525826] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10990 01:00:55.153383 .
10991 01:00:55.160742 <6>[ 12.535876] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10992 01:00:55.166526 <6>[ 12.544584] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10993 01:00:55.173450 <6>[ 12.545050] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10994 01:00:55.187322 <6>[ 12.561406] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10995 01:00:55.194441 <6>[ 12.566127] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10996 01:00:55.200836 <6>[ 12.578902] usbcore: registered new interface driver uvcvideo
10997 01:00:55.211056 <3>[ 12.582347] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 01:00:55.218235 <3>[ 12.583085] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10999 01:00:55.225075 <6>[ 12.586404] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11000 01:00:55.235091 <3>[ 12.605779] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 01:00:55.241542 <6>[ 12.609950] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11002 01:00:55.248988 <6>[ 12.609967] pci 0000:00:00.0: PCI bridge to [bus 01]
11003 01:00:55.255219 <6>[ 12.639927] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11004 01:00:55.262489 <6>[ 12.640135] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11005 01:00:55.269727 Startin<6>[ 12.655057] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11006 01:00:55.279077 g [0;1;39msyste<3>[ 12.658494] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 01:00:55.289241 md-user-sess…v<6>[ 12.662606] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11008 01:00:55.292325 ice[0m - Permit User Sessions...
11009 01:00:55.312188 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11010 01:00:55.319277 <3>[ 12.702116] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 01:00:55.328550 <5>[ 12.704739] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11012 01:00:55.350475 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice<5>[ 12.734520] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11013 01:00:55.360612 [0m - Permit Us<5>[ 12.743185] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11014 01:00:55.360703 er Sessions.
11015 01:00:55.370600 <3>[ 12.746618] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11016 01:00:55.380292 <4>[ 12.752372] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11017 01:00:55.383793 <6>[ 12.771330] cfg80211: failed to load regulatory.db
11018 01:00:55.394094 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11019 01:00:55.404765 <3>[ 12.788236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11020 01:00:55.416772 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11021 01:00:55.435250 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11022 01:00:55.453167 <6>[ 12.836548] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11023 01:00:55.459930 <6>[ 12.844231] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11024 01:00:55.466488 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11025 01:00:55.482299 <6>[ 12.868583] mt7921e 0000:01:00.0: ASIC revision: 79610010
11026 01:00:55.524826 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11027 01:00:55.554188 <46>[ 12.924354] systemd-journald[181]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.4 (1543 of 2047 items, 524288 file size, 339 bytes per hash table item), suggesting rotation.
11028 01:00:55.567123 <46>[ 12.945616] systemd-journald[181]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11029 01:00:55.586253 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Get<6>[ 12.969313] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11030 01:00:55.589175 <6>[ 12.969313]
11031 01:00:55.589265 ty on ttyS0.
11032 01:00:55.607297 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11033 01:00:55.622200 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11034 01:00:55.642266 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11035 01:00:55.698815 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11036 01:00:55.723259 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11037 01:00:55.750035 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11038 01:00:55.816070 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11039 01:00:55.839073 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11040 01:00:55.857838 <6>[ 13.241096] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11041 01:00:55.867647 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11042 01:00:55.931361
11043 01:00:55.934288 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11044 01:00:55.934373
11045 01:00:55.938062 debian-bookworm-arm64 login: root (automatic login)
11046 01:00:55.938138
11047 01:00:55.953457 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
11048 01:00:55.953540
11049 01:00:55.960421 The programs included with the Debian GNU/Linux system are free software;
11050 01:00:55.966964 the exact distribution terms for each program are described in the
11051 01:00:55.969905 individual files in /usr/share/doc/*/copyright.
11052 01:00:55.969987
11053 01:00:55.976709 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11054 01:00:55.980123 permitted by applicable law.
11055 01:00:55.980505 Matched prompt #10: / #
11057 01:00:55.980713 Setting prompt string to ['/ #']
11058 01:00:55.980805 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11060 01:00:55.981004 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11061 01:00:55.981092 start: 2.2.6 expect-shell-connection (timeout 00:02:36) [common]
11062 01:00:55.981162 Setting prompt string to ['/ #']
11063 01:00:55.981229 Forcing a shell prompt, looking for ['/ #']
11065 01:00:56.031423 / #
11066 01:00:56.031529 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11067 01:00:56.031613 Waiting using forced prompt support (timeout 00:02:30)
11068 01:00:56.036081
11069 01:00:56.036341 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11070 01:00:56.036430 start: 2.2.7 export-device-env (timeout 00:02:36) [common]
11071 01:00:56.036531 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11072 01:00:56.036620 end: 2.2 depthcharge-retry (duration 00:02:24) [common]
11073 01:00:56.036709 end: 2 depthcharge-action (duration 00:02:24) [common]
11074 01:00:56.036796 start: 3 lava-test-retry (timeout 00:07:11) [common]
11075 01:00:56.036882 start: 3.1 lava-test-shell (timeout 00:07:11) [common]
11076 01:00:56.036962 Using namespace: common
11078 01:00:56.137226 / # #
11079 01:00:56.137387 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11080 01:00:56.142260 #
11081 01:00:56.142531 Using /lava-14368604
11083 01:00:56.242888 / # export SHELL=/bin/sh
11084 01:00:56.248062 export SHELL=/bin/sh
11086 01:00:56.348531 / # . /lava-14368604/environment
11087 01:00:56.353770 . /lava-14368604/environment
11089 01:00:56.454243 / # /lava-14368604/bin/lava-test-runner /lava-14368604/0
11090 01:00:56.454371 Test shell timeout: 10s (minimum of the action and connection timeout)
11091 01:00:56.460064 /lava-14368604/bin/lava-test-runner /lava-14368604/0
11092 01:00:56.485105 + export TESTRUN_ID=0_igt-kms-me<8>[ 13.871141] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14368604_1.5.2.3.1>
11093 01:00:56.485395 Received signal: <STARTRUN> 0_igt-kms-mediatek 14368604_1.5.2.3.1
11094 01:00:56.485480 Starting test lava.0_igt-kms-mediatek (14368604_1.5.2.3.1)
11095 01:00:56.485584 Skipping test definition patterns.
11096 01:00:56.488686 diatek
11097 01:00:56.491662 + cd /lava-14368604/0/tests/0_igt-kms-mediatek
11098 01:00:56.491747 + cat uuid
11099 01:00:56.495505 + UUID=14368604_1.5.2.3.1
11100 01:00:56.495592 + set +x
11101 01:00:56.511632 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_re<8>[ 13.898385] <LAVA_SIGNAL_TESTSET START core_auth>
11102 01:00:56.511894 Received signal: <TESTSET> START core_auth
11103 01:00:56.511972 Starting test_set core_auth
11104 01:00:56.521740 ad kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11105 01:00:56.530752 <14>[ 13.917688] [IGT] core_auth: executing
11106 01:00:56.537875 IGT-Version: 1.2<14>[ 13.922163] [IGT] core_auth: starting subtest getclient-simple
11107 01:00:56.547119 8-ga44ebfe (aarc<14>[ 13.929949] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11108 01:00:56.550663 h64) (Linux: 6.1<14>[ 13.938001] [IGT] core_auth: exiting, ret=0
11109 01:00:56.553654 .92-cip22 aarch64)
11110 01:00:56.557243 Using IGT_SRANDOM=1718499656 for randomisation
11111 01:00:56.566840 Starting sub<8>[ 13.950663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11112 01:00:56.566923 test: getclient-simple
11113 01:00:56.567162 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11115 01:00:56.570764 Opened device: /dev/dri/card0
11116 01:00:56.576715 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11117 01:00:56.595402 <14>[ 13.982271] [IGT] core_auth: executing
11118 01:00:56.601620 IGT-Version: 1.2<14>[ 13.986912] [IGT] core_auth: starting subtest getclient-master-drop
11119 01:00:56.612146 8-ga44ebfe (aarc<14>[ 13.994984] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11120 01:00:56.618532 h64) (Linux: 6.1<14>[ 14.003643] [IGT] core_auth: exiting, ret=0
11121 01:00:56.618617 .92-cip22 aarch64)
11122 01:00:56.631532 Using IGT_SRANDOM=1718499656 for randomisati<8>[ 14.014993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11123 01:00:56.631617 on
11124 01:00:56.631875 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11126 01:00:56.634993 Starting subtest: getclient-master-drop
11127 01:00:56.638220 Opened device: /dev/dri/card0
11128 01:00:56.641588 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11129 01:00:56.649837 <14>[ 14.036869] [IGT] core_auth: executing
11130 01:00:56.656641 IGT-Version: 1.2<14>[ 14.041437] [IGT] core_auth: starting subtest basic-auth
11131 01:00:56.663026 8-ga44ebfe (aarc<14>[ 14.048427] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11132 01:00:56.669409 h64) (Linux: 6.1<14>[ 14.056274] [IGT] core_auth: exiting, ret=0
11133 01:00:56.672947 .92-cip22 aarch64)
11134 01:00:56.683050 Using IGT_SRANDOM=1718499656 for randomisati<8>[ 14.066380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11135 01:00:56.683136 on
11136 01:00:56.683393 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11138 01:00:56.686550 Opened device: /dev/dri/card0
11139 01:00:56.689444 Starting subtest: basic-auth
11140 01:00:56.692750 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11141 01:00:56.703046 <14>[ 14.090078] [IGT] core_auth: executing
11142 01:00:56.709826 IGT-Version: 1.2<14>[ 14.094500] [IGT] core_auth: starting subtest many-magics
11143 01:00:56.713031 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11144 01:00:56.723140 Using IGT_SRANDOM=1718499656<14>[ 14.108209] [IGT] core_auth: finished subtest many-magics, SUCCESS
11145 01:00:56.729436 <6>[ 14.108910] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11146 01:00:56.732598 <14>[ 14.115146] [IGT] core_auth: exiting, ret=0
11147 01:00:56.735917 for randomisation
11148 01:00:56.739469 Opened device: /dev/dri/card0
11149 01:00:56.746972 Starting subtest: many-magics<8>[ 14.131056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11150 01:00:56.747056
11151 01:00:56.747293 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11153 01:00:56.752570 Reopening device failed after <8>[ 14.141481] <LAVA_SIGNAL_TESTSET STOP>
11154 01:00:56.752822 Received signal: <TESTSET> STOP
11155 01:00:56.752893 Closing test_set core_auth
11156 01:00:56.755821 1020 opens
11157 01:00:56.759136 [1mSubtest many-magics: SUCCESS (0.007s)[0m
11158 01:00:56.793890 <14>[ 14.180782] [IGT] core_getclient: executing
11159 01:00:56.800332 IGT-Version: 1.2<14>[ 14.185663] [IGT] core_getclient: exiting, ret=0
11160 01:00:56.803616 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11161 01:00:56.813795 Using IGT_SR<8>[ 14.196068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11162 01:00:56.814068 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11164 01:00:56.816742 ANDOM=1718499656 for randomisation
11165 01:00:56.816832 Opened device: /dev/dri/card0
11166 01:00:56.820394 SUCCESS (0.006s)
11167 01:00:56.844887 <14>[ 14.231762] [IGT] core_getstats: executing
11168 01:00:56.851249 IGT-Version: 1.2<14>[ 14.236578] [IGT] core_getstats: exiting, ret=0
11169 01:00:56.854429 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11170 01:00:56.864559 Using IGT_SR<8>[ 14.247853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11171 01:00:56.864819 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11173 01:00:56.867761 ANDOM=1718499656 for randomisation
11174 01:00:56.867843 Opened device: /dev/dri/card0
11175 01:00:56.871130 SUCCESS (0.006s)
11176 01:00:56.911922 <14>[ 14.298779] [IGT] core_getversion: executing
11177 01:00:56.918604 IGT-Version: 1.2<14>[ 14.304123] [IGT] core_getversion: exiting, ret=0
11178 01:00:56.922078 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11179 01:00:56.931865 Using IGT_SRANDOM=1718499656<8>[ 14.315826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11180 01:00:56.932122 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11182 01:00:56.934975 for randomisation
11183 01:00:56.938108 Opened device: /dev/dri/card0
11184 01:00:56.938191 SUCCESS (0.006s)
11185 01:00:56.966365 <14>[ 14.353255] [IGT] core_setmaster_vs_auth: executing
11186 01:00:56.972664 IGT-Version: 1.2<14>[ 14.358920] [IGT] core_setmaster_vs_auth: exiting, ret=0
11187 01:00:56.979219 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11188 01:00:56.989526 Using IGT_SRANDOM=1718499656<8>[ 14.371456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11189 01:00:56.989611 for randomisation
11190 01:00:56.989851 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11192 01:00:56.992410 Opened device: /dev/dri/card0
11193 01:00:56.996218 SUCCESS (0.007s)
11194 01:00:57.011436 <8>[ 14.398148] <LAVA_SIGNAL_TESTSET START drm_read>
11195 01:00:57.011692 Received signal: <TESTSET> START drm_read
11196 01:00:57.011796 Starting test_set drm_read
11197 01:00:57.028907 <14>[ 14.416148] [IGT] drm_read: executing
11198 01:00:57.035503 IGT-Version: 1.2<14>[ 14.420774] [IGT] drm_read: exiting, ret=77
11199 01:00:57.038998 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11200 01:00:57.045538 Using IGT_SR<8>[ 14.431585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11201 01:00:57.045791 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11203 01:00:57.048818 ANDOM=1718499657 for randomisation
11204 01:00:57.052261 Opened device: /dev/dri/card0
11205 01:00:57.058524 No KMS driver or no outputs, pipes: 16, outputs: 0
11206 01:00:57.065511 [1mSubtest invalid-buffer: SKIP (0.000s)<14>[ 14.452484] [IGT] drm_read: executing
11207 01:00:57.065597 [0m
11208 01:00:57.072105 IGT-Version: 1.2<14>[ 14.457545] [IGT] drm_read: exiting, ret=77
11209 01:00:57.075436 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11210 01:00:57.085111 Using IGT_SRANDOM=1718499657<8>[ 14.469908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11211 01:00:57.085400 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11213 01:00:57.089110 for randomisation
11214 01:00:57.089219 Opened device: /dev/dri/card0
11215 01:00:57.095327 No KMS driver or no outputs, pipes: 16, outputs: 0
11216 01:00:57.098269 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11217 01:00:57.101972 <14>[ 14.490733] [IGT] drm_read: executing
11218 01:00:57.108732 IGT-Version: 1.2<14>[ 14.495238] [IGT] drm_read: exiting, ret=77
11219 01:00:57.115134 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11220 01:00:57.121793 Using IGT_SRANDOM=1718499657<8>[ 14.507047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11221 01:00:57.122050 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11223 01:00:57.124845 for randomisation
11224 01:00:57.128122 Opened device: /dev/dri/card0
11225 01:00:57.131365 No KMS driver or no outputs, pipes: 16, outputs: 0
11226 01:00:57.134931 [1mSubtest empty-block: SKIP (0.000s)[0m
11227 01:00:57.141353 <14>[ 14.528357] [IGT] drm_read: executing
11228 01:00:57.148214 IGT-Version: 1.2<14>[ 14.533035] [IGT] drm_read: exiting, ret=77
11229 01:00:57.151475 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11230 01:00:57.158135 Using IGT_SR<8>[ 14.543752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11231 01:00:57.158392 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11233 01:00:57.161228 ANDOM=1718499657 for randomisation
11234 01:00:57.164466 Opened device: /dev/dri/card0
11235 01:00:57.170921 No KMS driver or no outputs, pipes: 16, outputs: 0
11236 01:00:57.177877 [1mSubtest empty-nonblock: SKIP (0.000s)<14>[ 14.564939] [IGT] drm_read: executing
11237 01:00:57.177961 [0m
11238 01:00:57.181933 <14>[ 14.569604] [IGT] drm_read: exiting, ret=77
11239 01:00:57.195086 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<8>[ 14.579531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11240 01:00:57.195172 4)
11241 01:00:57.195430 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11243 01:00:57.201145 Using IGT_SRANDOM=1718499657 for randomisation
11244 01:00:57.204091 Opened device: /dev/dri/card0
11245 01:00:57.207228 No KMS driver or no outputs, pipes: 16, outputs: 0
11246 01:00:57.214420 [1mSubtest short-buffer-<14>[ 14.600872] [IGT] drm_read: executing
11247 01:00:57.220678 block: SKIP (0.0<14>[ 14.605711] [IGT] drm_read: exiting, ret=77
11248 01:00:57.220763 00s)[0m
11249 01:00:57.233759 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-ci<8>[ 14.616284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11250 01:00:57.233844 p22 aarch64)
11251 01:00:57.234100 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11253 01:00:57.237163 Using IGT_SRANDOM=1718499657 for randomisation
11254 01:00:57.240090 Opened device: /dev/dri/card0
11255 01:00:57.243556 No KMS driver or no outputs, pipes: 16, outputs: 0
11256 01:00:57.253530 [1mSubtest short-buffer-nonblock: SKIP (0.000s<14>[ 14.640968] [IGT] drm_read: executing
11257 01:00:57.253615 )[0m
11258 01:00:57.259727 IGT-Version: 1.2<14>[ 14.645952] [IGT] drm_read: exiting, ret=77
11259 01:00:57.263315 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11260 01:00:57.273413 Using IGT_SR<8>[ 14.657279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11261 01:00:57.273668 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11263 01:00:57.279407 ANDOM=1718499657 for randomisati<8>[ 14.666666] <LAVA_SIGNAL_TESTSET STOP>
11264 01:00:57.279490 on
11265 01:00:57.279726 Received signal: <TESTSET> STOP
11266 01:00:57.279795 Closing test_set drm_read
11267 01:00:57.283026 Opened device: /dev/dri/card0
11268 01:00:57.286166 No KMS driver or no outputs, pipes: 16, outputs: 0
11269 01:00:57.292923 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11270 01:00:57.311562 <8>[ 14.698751] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11271 01:00:57.311817 Received signal: <TESTSET> START kms_addfb_basic
11272 01:00:57.311889 Starting test_set kms_addfb_basic
11273 01:00:57.340093 <14>[ 14.727026] [IGT] kms_addfb_basic: executing
11274 01:00:57.353082 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<14>[ 14.736210] [IGT] kms_addfb_basic: starting subtest unused-handle
11275 01:00:57.353192 4)
11276 01:00:57.359789 Using IGT_SR<14>[ 14.744116] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11277 01:00:57.363445 ANDOM=1718499657 for randomisation
11278 01:00:57.366287 Opened device: /dev/dri/card0
11279 01:00:57.369660 Starting subtest: unused-handle
11280 01:00:57.376557 [1mSubtest <14>[ 14.761610] [IGT] kms_addfb_basic: exiting, ret=0
11281 01:00:57.379291 unused-handle: SUCCESS (0.000s)[0m
11282 01:00:57.386441 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11284 01:00:57.389745 Test requirement not met in<8>[ 14.772461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11285 01:00:57.392799 function igt_require_intel, file ../lib/drmtest.c:880:
11286 01:00:57.396045 Test requirement: is_intel_device(fd)
11287 01:00:57.402488 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11288 01:00:57.406146 Test requirement: is_intel_device(fd)
11289 01:00:57.413514 No KMS driver or no outputs, pipes: 16, outputs: 0
11290 01:00:57.415715 <14>[ 14.804150] [IGT] kms_addfb_basic: executing
11291 01:00:57.429107 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<14>[ 14.813661] [IGT] kms_addfb_basic: starting subtest unused-pitches
11292 01:00:57.429216 4)
11293 01:00:57.439409 Using IGT_SR<14>[ 14.821250] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11294 01:00:57.442532 ANDOM=1718499657 for randomisation
11295 01:00:57.442614 Opened device: /dev/dri/card0
11296 01:00:57.445474 Starting subtest: unused-pitches
11297 01:00:57.452060 [1mSubtest<14>[ 14.839073] [IGT] kms_addfb_basic: exiting, ret=0
11298 01:00:57.455752 unused-pitches: SUCCESS (0.000s)[0m
11299 01:00:57.465140 Test requirement not met in function igt_<8>[ 14.851089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11300 01:00:57.465423 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11302 01:00:57.472483 require_intel, file ../lib/drmtest.c:880:
11303 01:00:57.474949 Test requirement: is_intel_device(fd)
11304 01:00:57.481702 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11305 01:00:57.488253 Test requi<14>[ 14.873264] [IGT] kms_addfb_basic: executing
11306 01:00:57.488337 rement: is_intel_device(fd)
11307 01:00:57.498591 No KMS driver or no outputs, pipes:<14>[ 14.883277] [IGT] kms_addfb_basic: starting subtest unused-offsets
11308 01:00:57.501852 16, outputs: 0
11309 01:00:57.508160 <14>[ 14.891171] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11310 01:00:57.508243
11311 01:00:57.514946 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11312 01:00:57.521715 Using IGT_SRANDOM=171849965<14>[ 14.907793] [IGT] kms_addfb_basic: exiting, ret=0
11313 01:00:57.521798 7 for randomisation
11314 01:00:57.525138 Opened device: /dev/dri/card0
11315 01:00:57.534343 Starting subtest: unused-off<8>[ 14.919160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11316 01:00:57.534427 sets
11317 01:00:57.534665 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11319 01:00:57.541414 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11320 01:00:57.547601 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11321 01:00:57.554268 Test requirement: is_intel_device(fd<14>[ 14.941694] [IGT] kms_addfb_basic: executing
11322 01:00:57.554352 )
11323 01:00:57.567963 Test requirement not met in function igt_require_intel, file <14>[ 14.951822] [IGT] kms_addfb_basic: starting subtest unused-modifier
11324 01:00:57.577470 ../lib/drmtest.c<14>[ 14.959613] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11325 01:00:57.577556 :880:
11326 01:00:57.580684 Test requirement: is_intel_device(fd)
11327 01:00:57.590845 No KMS driver or no outputs, pipes: 16, outputs: 0<14>[ 14.976419] [IGT] kms_addfb_basic: exiting, ret=0
11328 01:00:57.590930
11329 01:00:57.597578 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11330 01:00:57.603918 Using IGT_<8>[ 14.987944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11331 01:00:57.604174 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11333 01:00:57.607040 SRANDOM=1718499657 for randomisation
11334 01:00:57.610601 Opened device: /dev/dri/card0
11335 01:00:57.613967 Starting subtest: unused-modifier
11336 01:00:57.616838 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11337 01:00:57.624424 Test requirement not <14>[ 15.010165] [IGT] kms_addfb_basic: executing
11338 01:00:57.630672 met in function igt_require_intel, file ../lib/drmtest.c:880:
11339 01:00:57.636669 T<14>[ 15.020335] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11340 01:00:57.646588 est requirement:<14>[ 15.028696] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11341 01:00:57.646671 is_intel_device(fd)
11342 01:00:57.660014 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 15.045324] [IGT] kms_addfb_basic: exiting, ret=77
11343 01:00:57.660101 t.c:880:
11344 01:00:57.663193 Test requirement: is_intel_device(fd)
11345 01:00:57.672988 No KMS driver or no outputs, pi<8>[ 15.057024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11346 01:00:57.673249 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11348 01:00:57.676673 pes: 16, outputs: 0
11349 01:00:57.679773 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11350 01:00:57.686996 Using IGT_SRANDOM=1718499657 for randomisation
11351 01:00:57.687078 Opened device: /dev/dri/card0
11352 01:00:57.693162 Starting<14>[ 15.080066] [IGT] kms_addfb_basic: executing
11353 01:00:57.696595 subtest: clobberred-modifier
11354 01:00:57.706252 Test requirement not met in funct<14>[ 15.089901] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11355 01:00:57.715990 ion igt_require_<14>[ 15.098829] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11356 01:00:57.719649 i915, file ../lib/drmtest.c:885:
11357 01:00:57.722954 Test requirement: is_i915_device(fd)
11358 01:00:57.729485 [1mSubtest clobberred-m<14>[ 15.116459] [IGT] kms_addfb_basic: exiting, ret=77
11359 01:00:57.732591 odifier: SKIP (0.000s)[0m
11360 01:00:57.746433 Test requirement not met in function igt_require_int<8>[ 15.127970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11361 01:00:57.746693 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11363 01:00:57.749685 el, file ../lib/drmtest.c:880:
11364 01:00:57.752561 Test requirement: is_intel_device(fd)
11365 01:00:57.759418 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11366 01:00:57.765994 Test requirement: is_<14>[ 15.151534] [IGT] kms_addfb_basic: executing
11367 01:00:57.766077 intel_device(fd)
11368 01:00:57.775546 No KMS driver or no outputs, pipes: 16, output<14>[ 15.161545] [IGT] kms_addfb_basic: starting subtest legacy-format
11369 01:00:57.779229 s: 0
11370 01:00:57.782052 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11371 01:00:57.792438 Using <14>[ 15.174866] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11372 01:00:57.795683 IGT_SRANDOM=1718499657 for randomisation
11373 01:00:57.798525 Opened device: /dev/dri/card0
11374 01:00:57.805584 Starting subtest: inval<14>[ 15.191179] [IGT] kms_addfb_basic: exiting, ret=0
11375 01:00:57.805670 id-smem-bo-on-discrete
11376 01:00:57.818703 Test requirement not met in function igt_require_intel, <8>[ 15.203051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11377 01:00:57.819019 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11379 01:00:57.821757 file ../lib/drmtest.c:880:
11380 01:00:57.825096 Test requirement: is_intel_device(fd)
11381 01:00:57.829136 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11382 01:00:57.838590 Test requirement not met in function igt_require_<14>[ 15.225038] [IGT] kms_addfb_basic: executing
11383 01:00:57.841796 intel, file ../lib/drmtest.c:880:
11384 01:00:57.844754 Test requirement: is_intel_device(fd)
11385 01:00:57.851646 Test r<14>[ 15.237362] [IGT] kms_addfb_basic: starting subtest no-handle
11386 01:00:57.861407 equirement not m<14>[ 15.243895] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11387 01:00:57.864910 et in function igt_require_intel, file ../lib/drmtest.c:880:
11388 01:00:57.871446 Test requirement: <14>[ 15.258135] [IGT] kms_addfb_basic: exiting, ret=0
11389 01:00:57.874810 is_intel_device(fd)
11390 01:00:57.877901 No KMS driver or no outputs, pipes: 16, outputs: 0
11391 01:00:57.884634 IGT-Ver<8>[ 15.270213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11392 01:00:57.884889 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11394 01:00:57.891197 sion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11395 01:00:57.894835 Using IGT_SRANDOM=1718499657 for randomisation
11396 01:00:57.897520 Opened device: /dev/dri/card0
11397 01:00:57.901168 Starting subtest: legacy-format
11398 01:00:57.904235 Suc<14>[ 15.292094] [IGT] kms_addfb_basic: executing
11399 01:00:57.911157 cessfully fuzzed 10000 {bpp, depth} variations
11400 01:00:57.917185 [1mSubtest legacy-format: SUCCE<14>[ 15.304425] [IGT] kms_addfb_basic: starting subtest basic
11401 01:00:57.920924 SS (0.006s)[0m
11402 01:00:57.927561 <14>[ 15.310799] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11403 01:00:57.927644
11404 01:00:57.937351 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 15.324395] [IGT] kms_addfb_basic: exiting, ret=0
11405 01:00:57.940277 80:
11406 01:00:57.944072 Test requirement: is_intel_device(fd)
11407 01:00:57.950458 Test requirement not met in function<8>[ 15.336772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11408 01:00:57.950713 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11410 01:00:57.957085 igt_require_intel, file ../lib/drmtest.c:880:
11411 01:00:57.960236 Test requirement: is_intel_device(fd)
11412 01:00:57.963670 No KMS driver or no outputs, pipes: 16, outputs: 0
11413 01:00:57.970298 IGT-Version: 1.28-ga44ebfe (aarch64) <14>[ 15.357889] [IGT] kms_addfb_basic: executing
11414 01:00:57.973506 (Linux: 6.1.92-cip22 aarch64)
11415 01:00:57.979838 Using IGT_SRANDOM=1718499657 for randomisation
11416 01:00:57.986575 O<14>[ 15.370421] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11417 01:00:57.992823 pened device: /d<14>[ 15.377348] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11418 01:00:57.996403 ev/dri/card0
11419 01:00:57.996475 Starting subtest: no-handle
11420 01:00:58.006453 [1mSubtest no-handle: SUCCESS (0.000<14>[ 15.391491] [IGT] kms_addfb_basic: exiting, ret=0
11421 01:00:58.006539 s)[0m
11422 01:00:58.019601 Test requirement not met in function igt_require_intel, file ../lib/drmt<8>[ 15.403987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11423 01:00:58.019702 est.c:880:
11424 01:00:58.019943 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11426 01:00:58.022811 Test requirement: is_intel_device(fd)
11427 01:00:58.032501 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11428 01:00:58.036006 Test requirement: is_intel_device(fd)
11429 01:00:58.039763 No<14>[ 15.425740] [IGT] kms_addfb_basic: executing
11430 01:00:58.042882 KMS driver or no outputs, pipes: 16, outputs: 0
11431 01:00:58.052138 IGT-Version: 1.28-ga44ebfe (aa<14>[ 15.438124] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11432 01:00:58.062219 rch64) (Linux: 6<14>[ 15.445009] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11433 01:00:58.062304 .1.92-cip22 aarch64)
11434 01:00:58.068551 Using IGT_SRANDOM=1718499657 for randomisation
11435 01:00:58.072168 Opened dev<14>[ 15.459290] [IGT] kms_addfb_basic: exiting, ret=0
11436 01:00:58.075313 ice: /dev/dri/card0
11437 01:00:58.078996 Starting subtest: basic
11438 01:00:58.088560 [1mSubtest basic: SUCCESS (0.000s<8>[ 15.471617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11439 01:00:58.088646 )[0m
11440 01:00:58.088887 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11442 01:00:58.095459 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11443 01:00:58.098495 Test requirement: is_intel_device(fd)
11444 01:00:58.108331 Test requirement not met in function igt_requi<14>[ 15.493441] [IGT] kms_addfb_basic: executing
11445 01:00:58.112060 re_intel, file ../lib/drmtest.c:880:
11446 01:00:58.115252 Test requirement: is_intel_device(fd)
11447 01:00:58.121500 No <14>[ 15.506100] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11448 01:00:58.127895 KMS driver or no<14>[ 15.512801] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11449 01:00:58.131546 outputs, pipes: 16, outputs: 0
11450 01:00:58.141242 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.<14>[ 15.527174] [IGT] kms_addfb_basic: exiting, ret=0
11451 01:00:58.145250 1.92-cip22 aarch64)
11452 01:00:58.147724 Using IGT_SRANDOM=1718499657 for randomisation
11453 01:00:58.154778 Opened devi<8>[ 15.539207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11454 01:00:58.155036 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11456 01:00:58.158023 ce: /dev/dri/card0
11457 01:00:58.161711 Starting subtest: bad-pitch-0
11458 01:00:58.164948 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11459 01:00:58.174430 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:<14>[ 15.561699] [IGT] kms_addfb_basic: executing
11460 01:00:58.174516 880:
11461 01:00:58.177931 Test requirement: is_intel_device(fd)
11462 01:00:58.187711 Test requirement not met in functio<14>[ 15.573840] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11463 01:00:58.197765 n igt_require_in<14>[ 15.580934] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11464 01:00:58.201052 tel, file ../lib/drmtest.c:880:
11465 01:00:58.204347 Test requirement: is_intel_device(fd)
11466 01:00:58.210733 No KMS d<14>[ 15.595276] [IGT] kms_addfb_basic: exiting, ret=0
11467 01:00:58.213702 river or no outputs, pipes: 16, outputs: 0
11468 01:00:58.223745 IGT-Version: 1.28-ga44ebfe (aarch64)<8>[ 15.607718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11469 01:00:58.224004 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11471 01:00:58.227078 (Linux: 6.1.92-cip22 aarch64)
11472 01:00:58.230824 Using IGT_SRANDOM=1718499658 for randomisation
11473 01:00:58.234007 Opened device: /dev/dri/card0
11474 01:00:58.237321 Starting subtest: bad-pitch-32
11475 01:00:58.243884 [1mSubtest bad-pitch-32: SUCCESS<14>[ 15.630206] [IGT] kms_addfb_basic: executing
11476 01:00:58.243968 (0.000s)[0m
11477 01:00:58.257241 Test requirement not met in function igt_require_intel, file ../l<14>[ 15.642137] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11478 01:00:58.266672 ib/drmtest.c:880<14>[ 15.649112] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11479 01:00:58.266756 :
11480 01:00:58.270119 Test requirement: is_intel_device(fd)
11481 01:00:58.277144 Test requirement not met in function i<14>[ 15.663414] [IGT] kms_addfb_basic: exiting, ret=0
11482 01:00:58.280560 gt_require_intel, file ../lib/drmtest.c:880:
11483 01:00:58.289990 Test requirement: is_intel_device(<8>[ 15.675841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11484 01:00:58.290251 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11486 01:00:58.293571 fd)
11487 01:00:58.296689 No KMS driver or no outputs, pipes: 16, outputs: 0
11488 01:00:58.303175 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11489 01:00:58.306433 Using IGT_SRANDOM=1718499658 for randomisation
11490 01:00:58.313350 Ope<14>[ 15.697703] [IGT] kms_addfb_basic: executing
11491 01:00:58.313435 ned device: /dev/dri/card0
11492 01:00:58.316364 Starting subtest: bad-pitch-63
11493 01:00:58.326303 [1mSubtest bad-pitc<14>[ 15.710340] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11494 01:00:58.332678 h-63: SUCCESS (0<14>[ 15.717246] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11495 01:00:58.336086 .000s)[0m
11496 01:00:58.346181 Test requirement not met in function igt_require_intel, file ../lib/<14>[ 15.731735] [IGT] kms_addfb_basic: exiting, ret=0
11497 01:00:58.346295 drmtest.c:880:
11498 01:00:58.349586 Test requirement: is_intel_device(fd)
11499 01:00:58.359558 Test requirement not met <8>[ 15.743994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11500 01:00:58.359877 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11502 01:00:58.366003 in function igt_require_intel, file ../lib/drmtest.c:880:
11503 01:00:58.368870 Test requirement: is_intel_device(fd)
11504 01:00:58.372389 No KMS driver or no outputs, pipes: 16, outputs: 0
11505 01:00:58.379030 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11506 01:00:58.382142 Using IGT_SRANDOM=1718499658 for randomisation
11507 01:00:58.389581 Opened<14>[ 15.775492] [IGT] kms_addfb_basic: executing
11508 01:00:58.389696 device: /dev/dri/card0
11509 01:00:58.392152 Starting subtest: bad-pitch-128
11510 01:00:58.402451 [1mSubtest bad-pitch-128: SUCCESS (0.<14>[ 15.787812] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11511 01:00:58.405325 000s)[0m
11512 01:00:58.411800 Test <14>[ 15.795228] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11513 01:00:58.418769 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11514 01:00:58.425473 T<14>[ 15.810440] [IGT] kms_addfb_basic: exiting, ret=0
11515 01:00:58.428513 est requirement: is_intel_device(fd)
11516 01:00:58.438229 Test requirement not met in function igt_r<8>[ 15.821707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11517 01:00:58.438484 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11519 01:00:58.441908 equire_intel, file ../lib/drmtest.c:880:
11520 01:00:58.446619 Test requirement: is_intel_device(fd)
11521 01:00:58.448530 No KMS driver or no outputs, pipes: 16, outputs: 0
11522 01:00:58.458415 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 15.843821] [IGT] kms_addfb_basic: executing
11523 01:00:58.461655 : 6.1.92-cip22 aarch64)
11524 01:00:58.464941 Using IGT_SRANDOM=1718499658 for randomisation
11525 01:00:58.471427 Opened <14>[ 15.856411] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11526 01:00:58.481149 device: /dev/dri<14>[ 15.863609] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11527 01:00:58.481283 /card0
11528 01:00:58.484690 Starting subtest: bad-pitch-256
11529 01:00:58.491487 [1mSubtest bad-pitch-256: SUCCESS (0.0<14>[ 15.878235] [IGT] kms_addfb_basic: exiting, ret=0
11530 01:00:58.494927 00s)[0m
11531 01:00:58.508257 Test requirement not met in function igt_require_intel, file ../lib/dr<8>[ 15.890251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11532 01:00:58.508341 mtest.c:880:
11533 01:00:58.508580 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11535 01:00:58.510944 Test requirement: is_intel_device(fd)
11536 01:00:58.517474 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11537 01:00:58.521381 Test requirement: is_intel_device(fd)
11538 01:00:58.527800 <14>[ 15.913639] [IGT] kms_addfb_basic: executing
11539 01:00:58.530781 No KMS driver or no outputs, pipes: 16, outputs: 0
11540 01:00:58.544013 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aa<14>[ 15.926935] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11541 01:00:58.544097 rch64)
11542 01:00:58.553901 Using IG<14>[ 15.935493] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11543 01:00:58.557407 T_SRANDOM=1718499658 for randomisation
11544 01:00:58.560503 Opened d<14>[ 15.948627] [IGT] kms_addfb_basic: exiting, ret=0
11545 01:00:58.564013 evice: /dev/dri/card0
11546 01:00:58.567110 Starting subtest: bad-pitch-1024
11547 01:00:58.577669 [1mSubtest bad-pitch-1<8>[ 15.960049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11548 01:00:58.577753 024: SUCCESS (0.000s)[0m
11549 01:00:58.578000 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11551 01:00:58.587087 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11552 01:00:58.590013 Test requirement: is_intel_device(fd)
11553 01:00:58.597118 Test requirement not met i<14>[ 15.983221] [IGT] kms_addfb_basic: executing
11554 01:00:58.600090 n function igt_require_intel, file ../lib/drmtest.c:880:
11555 01:00:58.604107 Test requirement: is_intel_device(fd)
11556 01:00:58.613023 No KMS driver o<14>[ 15.997152] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11557 01:00:58.623401 r no outputs, pi<14>[ 16.005055] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11558 01:00:58.623503 pes: 16, outputs: 0
11559 01:00:58.629669 IGT-Version: 1.28-ga44ebfe <14>[ 16.017839] [IGT] kms_addfb_basic: exiting, ret=0
11560 01:00:58.633061 (aarch64) (Linux: 6.1.92-cip22 aarch64)
11561 01:00:58.646405 Using IGT_SRANDOM=1718499658 for random<8>[ 16.028991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11562 01:00:58.646485 isation
11563 01:00:58.646723 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11565 01:00:58.649591 Opened device: /dev/dri/card0
11566 01:00:58.652731 Starting subtest: bad-pitch-999
11567 01:00:58.656312 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11568 01:00:58.666568 Test requirement not met in function igt_require_intel<14>[ 16.051851] [IGT] kms_addfb_basic: executing
11569 01:00:58.666676 , file ../lib/drmtest.c:880:
11570 01:00:58.672876 Test requirement: is_intel_device(fd)
11571 01:00:58.682773 Test requirement not met in function igt_re<14>[ 16.066003] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11572 01:00:58.692561 quire_intel, fil<14>[ 16.074219] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11573 01:00:58.692671 e ../lib/drmtest.c:880:
11574 01:00:58.699208 Test requirement: is_in<14>[ 16.087435] [IGT] kms_addfb_basic: exiting, ret=0
11575 01:00:58.702376 tel_device(fd)
11576 01:00:58.705855 No KMS driver or no outputs, pipes: 16, outputs: 0
11577 01:00:58.715712 IGT-Version:<8>[ 16.098851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11578 01:00:58.715995 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11580 01:00:58.718895 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11581 01:00:58.725907 Using IGT_SRANDOM=1718499658 for randomisation
11582 01:00:58.725982 Opened device: /dev/dri/card0
11583 01:00:58.729100 Starting subtest: bad-pitch-65536
11584 01:00:58.735940 [1mSu<14>[ 16.121413] [IGT] kms_addfb_basic: executing
11585 01:00:58.739351 btest bad-pitch-65536: SUCCESS (0.000s)[0m
11586 01:00:58.752570 Test requirement not met in function igt_require_intel, file ../lib<14>[ 16.135759] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11587 01:00:58.752679 /drmtest.c:880:
11588 01:00:58.762157 <14>[ 16.143986] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11589 01:00:58.762236
11590 01:00:58.765436 Test requirement: is_intel_device(fd)
11591 01:00:58.769524 Test req<14>[ 16.156706] [IGT] kms_addfb_basic: exiting, ret=0
11592 01:00:58.775427 uirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11593 01:00:58.784971 Test<8>[ 16.168018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11594 01:00:58.785230 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11596 01:00:58.788469 requirement: is_intel_device(fd)
11597 01:00:58.792410 No KMS driver or no outputs, pipes: 16, outputs: 0
11598 01:00:58.798304 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11599 01:00:58.804818 Using IGT_SRANDOM=171<14>[ 16.191027] [IGT] kms_addfb_basic: executing
11600 01:00:58.804927 8499658 for randomisation
11601 01:00:58.808214 Opened device: /dev/dri/card0
11602 01:00:58.811710 Starting subtest: invalid-get-prop-any
11603 01:00:58.821405 [1mSubtest invalid-get-prop-a<14>[ 16.206584] [IGT] kms_addfb_basic: starting subtest master-rmfb
11604 01:00:58.831399 ny: SUCCESS (0.0<14>[ 16.213871] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11605 01:00:58.831483 00s)[0m
11606 01:00:58.838258 Test requirement not m<14>[ 16.224278] [IGT] kms_addfb_basic: exiting, ret=0
11607 01:00:58.844839 et in function igt_require_intel, file ../lib/drmtest.c:880:
11608 01:00:58.851059 Te<8>[ 16.235344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11609 01:00:58.851332 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11611 01:00:58.853910 st requirement: is_intel_device(fd)
11612 01:00:58.860639 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11613 01:00:58.864082 Test requirement: is_intel_device(fd)
11614 01:00:58.867391 <14>[ 16.255513] [IGT] kms_addfb_basic: executing
11615 01:00:58.873850 No KMS driver or no outputs, pipes: 16, outputs: 0
11616 01:00:58.880910 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11617 01:00:58.887172 Using IGT_SRANDOM=171849<14>[ 16.273294] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11618 01:00:58.897052 9658 for randomi<14>[ 16.281208] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11619 01:00:58.900642 sation
11620 01:00:58.903382 Opened d<14>[ 16.290845] [IGT] kms_addfb_basic: exiting, ret=0
11621 01:00:58.907239 evice: /dev/dri/card0
11622 01:00:58.910352 Starting subtest: invalid-get-prop
11623 01:00:58.920105 [1mSubtest invalid-g<8>[ 16.302989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11624 01:00:58.920360 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11626 01:00:58.923495 et-prop: SUCCESS (0.000s)[0m
11627 01:00:58.929888 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11628 01:00:58.933316 Test requirement: is_intel_device(fd)
11629 01:00:58.939735 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11630 01:00:58.946541 Test requirement: is_intel_device(<14>[ 16.335367] [IGT] kms_addfb_basic: executing
11631 01:00:58.950288 fd)
11632 01:00:58.953049 No KMS driver or no outputs, pipes: 16, outputs: 0
11633 01:00:58.959683 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11634 01:00:58.969975 Using IGT_SRANDOM=1718499658 for ra<14>[ 16.353963] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11635 01:00:58.970059 ndomisation
11636 01:00:58.973064 Opened device: /dev/dri/card0
11637 01:00:58.975870 Starting subtest: invalid-set-prop-any
11638 01:00:58.985844 [1mSubtest <14>[ 16.369611] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11639 01:00:58.989426 invalid-set-prop-any: SUCCESS (0.000s)[0m
11640 01:00:58.995765 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11641 01:00:58.998894 Test requirement: is_intel_device(fd)
11642 01:00:59.005842 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11643 01:00:59.008844 Test requirement: is_intel_device(fd)
11644 01:00:59.015637 No KMS driver or no outputs, pipes: 16, outputs: 0
11645 01:00:59.022567 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11646 01:00:59.025479 Using IGT_SRANDOM=1718499658 for randomisation
11647 01:00:59.028738 Opened device: /dev/dri/card0
11648 01:00:59.032118 Starting subtest: invalid-set-prop
11649 01:00:59.034927 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11650 01:00:59.041600 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11651 01:00:59.045140 Test requirement: is_intel_device(fd)
11652 01:00:59.051765 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11653 01:00:59.055076 Test requirement: is_intel_device(fd)
11654 01:00:59.061302 No KMS driver or no outputs, pipes: 16, outputs: 0
11655 01:00:59.068223 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11656 01:00:59.071216 Using IGT_SRANDOM=1718499658 for randomisation
11657 01:00:59.074433 Opened device: /dev/dri/card0
11658 01:00:59.077984 Starting subtest: master-rmfb
11659 01:00:59.081043 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11660 01:00:59.087740 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11661 01:00:59.091285 Test requirement: is_intel_device(fd)
11662 01:00:59.097830 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11663 01:00:59.101499 Test requirement: is_intel_device(fd)
11664 01:00:59.107743 No KMS driver or no outputs, pipes: 16, outputs: 0
11665 01:00:59.110938 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11666 01:00:59.117471 Using IGT_SRANDOM=1718499658 for randomisation
11667 01:00:59.120742 Opened device: /dev/dri/card0
11668 01:00:59.123910 Starting subtest: addfb25-modifier-no-flag
11669 01:00:59.127383 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11670 01:00:59.133861 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11671 01:00:59.140256 Test requirement: is_intel_device(fd)
11672 01:00:59.147485 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11673 01:00:59.150245 Test requirement: is_intel_device(fd)
11674 01:00:59.154163 No KMS driver or no outputs, pipes: 16, outputs: 0
11675 01:00:59.160642 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11676 01:00:59.163726 Using IGT_SRANDOM=1718499658 for randomisation
11677 01:00:59.167361 Opened device: /dev/dri/card0
11678 01:00:59.170600 Starting subtest: addfb25-bad-modifier
11679 01:00:59.180357 (kms_addfb_basic:433) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11680 01:00:59.199594 (kms_addfb_basic:433) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11681 01:00:59.203047 (kms_addfb_basic:433) CRITICAL: error: 0 != -1
11682 01:00:59.203130 Stack trace:
11683 01:00:59.207148 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11684 01:00:59.209416 #1 [<unknown>+0xe08a4358]
11685 01:00:59.212738 #2 [<unknown>+0xe08a5fbc]
11686 01:00:59.216102 #3 [<unknown>+0xe08a156c]
11687 01:00:59.220167 #4 [__libc_init_first+0x80]
11688 01:00:59.220250 #5 [__libc_start_main+0x98]
11689 01:00:59.222489 #6 [<unknown>+0xe08a15b0]
11690 01:00:59.226446 Subtest addfb25-bad-modifier failed.
11691 01:00:59.229189 **** DEBUG ****
11692 01:00:59.235725 (kms_addfb_basic:433) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11693 01:00:59.245739 (kms_addfb_basic:433) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11694 01:00:59.265905 (kms_addfb_basic:433) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11695 01:00:59.269360 (kms_addfb_basic:433) CRITICAL: error: 0 != -1
11696 01:00:59.271913 (kms_addfb_basic:433) igt_core-INFO: Stack trace:
11697 01:00:59.282012 (kms_addfb_basic:433) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11698 01:00:59.285483 (kms_addfb_basic:433) igt_core-INFO: #1 [<unknown>+0xe08a4358]
11699 01:00:59.291870 (kms_addfb_basic:433) igt_core-INFO: #2 [<unknown>+0xe08a5fbc]
11700 01:00:59.298500 (kms_addfb_basic:433) igt_core-INFO: #3 [<unknown>+0xe08a156c]
11701 01:00:59.304970 (kms_addfb_basic:433) igt_core-INFO: #4 [__libc_init_first+0x80]
11702 01:00:59.308405 (kms_addfb_basic:433) igt_core-INFO: #5 [__libc_start_main+0x98]
11703 01:00:59.314903 (kms_addfb_basic:433) igt_core-INFO: #6 [<unknown>+0xe08a15b0]
11704 01:00:59.318175 **** END ****
11705 01:00:59.325139 [1mSubtest addfb25-bad-modifier: F<14>[ 16.711231] [IGT] kms_addfb_basic: exiting, ret=98
11706 01:00:59.328030 AIL (0.008s)[0m
11707 01:00:59.338170 Test requirement not met in function igt_require_intel, file .<8>[ 16.723403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11708 01:00:59.338437 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11710 01:00:59.341470 ./lib/drmtest.c:880:
11711 01:00:59.344499 Test requirement: is_intel_device(fd)
11712 01:00:59.351300 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11713 01:00:59.357543 Test requiremen<14>[ 16.745402] [IGT] kms_addfb_basic: executing
11714 01:00:59.361329 t: is_intel_device(fd)
11715 01:00:59.364338 No KMS driver or no outputs, pipes: 16, outputs: 0
11716 01:00:59.370720 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11717 01:00:59.377430 Using IGT_SRANDO<14>[ 16.763007] [IGT] kms_addfb_basic: exiting, ret=77
11718 01:00:59.381100 M=1718499659 for randomisation
11719 01:00:59.384576 Opened device: /dev/dri/card0
11720 01:00:59.391152 T<8>[ 16.774873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11721 01:00:59.391410 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11723 01:00:59.397293 est requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11724 01:00:59.400269 Test requirement: is_intel_device(fd)
11725 01:00:59.407428 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11726 01:00:59.413956 Test r<14>[ 16.799121] [IGT] kms_addfb_basic: executing
11727 01:00:59.420162 equirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11728 01:00:59.423711 Test requirement: is_intel_device(fd)
11729 01:00:59.430145 No KMS driver or no outputs, pipes: 16, out<14>[ 16.817960] [IGT] kms_addfb_basic: exiting, ret=77
11730 01:00:59.433458 puts: 0
11731 01:00:59.443819 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11733 01:00:59.446642 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip<8>[ 16.829534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11734 01:00:59.446726 22 aarch64)
11735 01:00:59.449707 Using IGT_SRANDOM=1718499659 for randomisation
11736 01:00:59.453146 Opened device: /dev/dri/card0
11737 01:00:59.462996 Test requirement not met in function igt_require_intel, file ../lib/<14>[ 16.850324] [IGT] kms_addfb_basic: executing
11738 01:00:59.467114 drmtest.c:880:
11739 01:00:59.469584 Test requirement: is_intel_device(fd)
11740 01:00:59.472892 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11741 01:00:59.483090 Test requirement not met in function igt_require_i<14>[ 16.868949] [IGT] kms_addfb_basic: exiting, ret=77
11742 01:00:59.486593 ntel, file ../lib/drmtest.c:880:
11743 01:00:59.496362 Test requirement: is_intel_dev<8>[ 16.880273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11744 01:00:59.496621 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11746 01:00:59.499462 ice(fd)
11747 01:00:59.502726 No KMS driver or no outputs, pipes: 16, outputs: 0
11748 01:00:59.509489 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11749 01:00:59.516361 Using IGT_SRANDOM=1718499659 fo<14>[ 16.903223] [IGT] kms_addfb_basic: executing
11750 01:00:59.516444 r randomisation
11751 01:00:59.519112 Opened device: /dev/dri/card0
11752 01:00:59.525701 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11753 01:00:59.536364 Test requirement: is_intel_d<14>[ 16.920790] [IGT] kms_addfb_basic: exiting, ret=77
11754 01:00:59.536448 evice(fd)
11755 01:00:59.549012 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (<8>[ 16.932464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11756 01:00:59.549097 0.000s)[0m
11757 01:00:59.549338 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11759 01:00:59.555606 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11760 01:00:59.559673 Test requirement: is_intel_device(fd)
11761 01:00:59.565494 No KMS driver or no outp<14>[ 16.954057] [IGT] kms_addfb_basic: executing
11762 01:00:59.568754 uts, pipes: 16, outputs: 0
11763 01:00:59.576083 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11764 01:00:59.578621 Using IGT_SRANDOM=1718499659 for randomisation
11765 01:00:59.585450 Opened device: /<14>[ 16.971772] [IGT] kms_addfb_basic: exiting, ret=77
11766 01:00:59.589052 dev/dri/card0
11767 01:00:59.598759 Test requirement not met in function igt_require_<8>[ 16.983597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11768 01:00:59.599016 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11770 01:00:59.601814 intel, file ../lib/drmtest.c:880:
11771 01:00:59.605287 Test requirement: is_intel_device(fd)
11772 01:00:59.612061 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11773 01:00:59.618265 Te<14>[ 17.005483] [IGT] kms_addfb_basic: executing
11774 01:00:59.621895 st requirement: is_intel_device(fd)
11775 01:00:59.625453 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11776 01:00:59.632021 No KMS driver or no outputs, pipes: 16, outputs: 0
11777 01:00:59.638173 IGT-Version: 1.28-<14>[ 17.023081] [IGT] kms_addfb_basic: exiting, ret=77
11778 01:00:59.641711 ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11779 01:00:59.651325 Using IGT_SRANDOM=1718499659 f<8>[ 17.035166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11780 01:00:59.651583 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11782 01:00:59.655119 or randomisation
11783 01:00:59.655203 Opened device: /dev/dri/card0
11784 01:00:59.664674 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11785 01:00:59.667848 Test requirement: is_intel_device(fd)
11786 01:00:59.671709 Test<14>[ 17.058064] [IGT] kms_addfb_basic: executing
11787 01:00:59.677857 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11788 01:00:59.681488 Test requirement: is_intel_device(fd)
11789 01:00:59.691181 [1mSubtest framebuffer-vs-set-tiling: SK<14>[ 17.076545] [IGT] kms_addfb_basic: exiting, ret=77
11790 01:00:59.691265 IP (0.000s)[0m
11791 01:00:59.704311 No KMS driver or no outputs, pipes: 16, outputs<8>[ 17.088132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11792 01:00:59.704396 : 0
11793 01:00:59.704636 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11795 01:00:59.710890 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11796 01:00:59.714182 Using IGT_SRANDOM=1718499659 for randomisation
11797 01:00:59.717282 Opened device: /dev/dri/card0
11798 01:00:59.724042 Test requirement not met in function igt<14>[ 17.112667] [IGT] kms_addfb_basic: executing
11799 01:00:59.730662 _require_intel, file ../lib/drmtest.c:880:
11800 01:00:59.734096 Test requirement: is_intel_device(fd)
11801 01:00:59.743740 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c<14>[ 17.130426] [IGT] kms_addfb_basic: exiting, ret=77
11802 01:00:59.743824 :880:
11803 01:00:59.747524 Test requirement: is_intel_device(fd)
11804 01:00:59.757339 [1mSubtest tile-p<8>[ 17.142164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11805 01:00:59.757594 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11807 01:00:59.760431 itch-mismatch: SKIP (0.000s)[0m
11808 01:00:59.763908 No KMS driver or no outputs, pipes: 16, outputs: 0
11809 01:00:59.770204 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11810 01:00:59.773795 Using <14>[ 17.162728] [IGT] kms_addfb_basic: executing
11811 01:00:59.780565 IGT_SRANDOM=1718499659 for randomisation
11812 01:00:59.780652 Opened device: /dev/dri/card0
11813 01:00:59.790088 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11814 01:00:59.794049 Tes<14>[ 17.180127] [IGT] kms_addfb_basic: exiting, ret=77
11815 01:00:59.797117 t requirement: is_intel_device(fd)
11816 01:00:59.806640 Test requirement not met in <8>[ 17.191734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11817 01:00:59.806893 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11819 01:00:59.810044 function igt_require_intel, file ../lib/drmtest.c:880:
11820 01:00:59.813174 Test requirement: is_intel_device(fd)
11821 01:00:59.820157 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11822 01:00:59.826863 No KMS drive<14>[ 17.212204] [IGT] kms_addfb_basic: executing
11823 01:00:59.829807 r or no outputs, pipes: 16, outputs: 0
11824 01:00:59.833168 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11825 01:00:59.839844 Using IGT_SRANDOM=1718499659 for randomisation
11826 01:00:59.844135 Open<14>[ 17.229961] [IGT] kms_addfb_basic: exiting, ret=77
11827 01:00:59.846835 ed device: /dev/dri/card0
11828 01:00:59.856774 Test requirement not met in function igt_require_inte<8>[ 17.242108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11829 01:00:59.857032 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11831 01:00:59.860450 l, file ../lib/drmtest.c:880:
11832 01:00:59.863580 Test requirement: is_intel_device(fd)
11833 01:00:59.869609 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11834 01:00:59.876440 Test r<14>[ 17.263205] [IGT] kms_addfb_basic: executing
11835 01:00:59.879326 equirement: is_intel_device(fd)
11836 01:00:59.883101 No KMS driver or no outputs, pipes: 16, outputs: 0
11837 01:00:59.885893 [1mSubtest size-max: SKIP (0.000s)[0m
11838 01:00:59.896101 IGT-Version: 1.28-ga44ebfe (aarch6<14>[ 17.281199] [IGT] kms_addfb_basic: exiting, ret=77
11839 01:00:59.899337 4) (Linux: 6.1.92-cip22 aarch64)
11840 01:00:59.909178 Using IGT_SRANDOM=1718499659 for randomisation<8>[ 17.293188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11841 01:00:59.909325
11842 01:00:59.909580 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11844 01:00:59.912532 Opened device: /dev/dri/card0
11845 01:00:59.919465 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11846 01:00:59.922484 Test requirement: is_intel_device(fd)
11847 01:00:59.929077 Test<14>[ 17.315206] [IGT] kms_addfb_basic: executing
11848 01:00:59.935812 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11849 01:00:59.938846 Test requirement: is_intel_device(fd)
11850 01:00:59.945886 No KMS driver or no outputs, pipes: 16, o<14>[ 17.333034] [IGT] kms_addfb_basic: exiting, ret=77
11851 01:00:59.948630 utputs: 0
11852 01:00:59.952117 [1mSubtest too-wide: SKIP (0.000s)[0m
11853 01:00:59.959007 IGT-Version:<8>[ 17.344434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11854 01:00:59.959281 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11856 01:00:59.966344 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11857 01:00:59.968542 Using IGT_SRANDOM=1718499659 for randomisation
11858 01:00:59.971737 Opened device: /dev/dri/card0
11859 01:00:59.978590 Test requirement not met <14>[ 17.365004] [IGT] kms_addfb_basic: executing
11860 01:00:59.982302 in function igt_require_intel, file ../lib/drmtest.c:880:
11861 01:00:59.985457 Test requirement: is_intel_device(fd)
11862 01:00:59.998473 Test requirement not met in function igt_require_intel, file .<14>[ 17.382662] [IGT] kms_addfb_basic: exiting, ret=77
11863 01:00:59.998557 ./lib/drmtest.c:880:
11864 01:01:00.001400 Test requirement: is_intel_device(fd)
11865 01:01:00.011906 No <8>[ 17.394620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11866 01:01:00.012163 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11868 01:01:00.014931 KMS driver or no outputs, pipes: 16, outputs: 0
11869 01:01:00.018050 [1mSubtest too-high: SKIP (0.000s)[0m
11870 01:01:00.025206 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11871 01:01:00.028180 Us<14>[ 17.416336] [IGT] kms_addfb_basic: executing
11872 01:01:00.034952 ing IGT_SRANDOM=1718499659 for randomisation
11873 01:01:00.035034 Opened device: /dev/dri/card0
11874 01:01:00.044376 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11875 01:01:00.048257 <14>[ 17.434270] [IGT] kms_addfb_basic: exiting, ret=77
11876 01:01:00.048339
11877 01:01:00.051333 Test requirement: is_intel_device(fd)
11878 01:01:00.060985 Test requirement not met<8>[ 17.445859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11879 01:01:00.061239 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11881 01:01:00.067698 in function igt_require_intel, file ../lib/drmtest.c:880:
11882 01:01:00.071610 Test requirement: is_intel_device(fd)
11883 01:01:00.074439 No KMS driver or no outputs, pipes: 16, outputs: 0
11884 01:01:00.084144 [1mSubtest bo-too-small: SKIP (0.000s)[<14>[ 17.469934] [IGT] kms_addfb_basic: executing
11885 01:01:00.084227 0m
11886 01:01:00.091019 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11887 01:01:00.094757 Using IGT_SRANDOM=1718499659 for randomisation
11888 01:01:00.097498 Opened device: /dev/dri/card0
11889 01:01:00.101146 Test requ<14>[ 17.488082] [IGT] kms_addfb_basic: exiting, ret=77
11890 01:01:00.114002 irement not met in function igt_require_intel, file ../lib/drmte<8>[ 17.499706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11891 01:01:00.114258 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11893 01:01:00.117227 st.c:880:
11894 01:01:00.120848 Test requirement: is_intel_device(fd)
11895 01:01:00.127182 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11896 01:01:00.133975 Test requirement: is_intel<14>[ 17.521037] [IGT] kms_addfb_basic: executing
11897 01:01:00.134058 _device(fd)
11898 01:01:00.140537 No KMS driver or no outputs, pipes: 16, outputs: 0
11899 01:01:00.143974 [1mSubtest small-bo: SKIP (0.000s)[0m
11900 01:01:00.154071 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-ci<14>[ 17.539120] [IGT] kms_addfb_basic: exiting, ret=77
11901 01:01:00.154154 p22 aarch64)
11902 01:01:00.160076 Using IGT_SRANDOM=1718499659 for randomisation
11903 01:01:00.167117 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11905 01:01:00.170122 Opened device: /de<8>[ 17.551193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11906 01:01:00.170205 v/dri/card0
11907 01:01:00.176801 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11908 01:01:00.180429 Test requirement: is_intel_device(fd)
11909 01:01:00.189875 Test requirement not met in function igt_require_intel, <14>[ 17.577237] [IGT] kms_addfb_basic: executing
11910 01:01:00.193625 file ../lib/drmtest.c:880:
11911 01:01:00.196451 Test requirement: is_intel_device(fd)
11912 01:01:00.199730 No KMS driver or no outputs, pipes: 16, outputs: 0
11913 01:01:00.206554 [1mSubtest bo-too-small-<14>[ 17.594722] [IGT] kms_addfb_basic: exiting, ret=77
11914 01:01:00.209796 due-to-tiling: SKIP (0.000s)[0m
11915 01:01:00.222884 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6<8>[ 17.605587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11916 01:01:00.222967 .1.92-cip22 aarch64)
11917 01:01:00.223206 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11919 01:01:00.229898 Using IGT_<8>[ 17.615698] <LAVA_SIGNAL_TESTSET STOP>
11920 01:01:00.230150 Received signal: <TESTSET> STOP
11921 01:01:00.230220 Closing test_set kms_addfb_basic
11922 01:01:00.232726 SRANDOM=1718499660 for randomisation
11923 01:01:00.236130 Opened device: /dev/dri/card0
11924 01:01:00.243039 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11925 01:01:00.246001 Test requirement: is_intel_device(fd)
11926 01:01:00.252810 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11927 01:01:00.255802 Test requirement: is_intel_device(fd)
11928 01:01:00.262694 No KM<8>[ 17.648672] <LAVA_SIGNAL_TESTSET START kms_atomic>
11929 01:01:00.262948 Received signal: <TESTSET> START kms_atomic
11930 01:01:00.263017 Starting test_set kms_atomic
11931 01:01:00.265927 S driver or no outputs, pipes: 16, outputs: 0
11932 01:01:00.269108 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11933 01:01:00.275636 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11934 01:01:00.278717 Using IGT_SRANDOM=1718499660 for randomisation
11935 01:01:00.282224 Opened device: /dev/dri/card0
11936 01:01:00.288690 Test re<14>[ 17.675296] [IGT] kms_atomic: executing
11937 01:01:00.295584 quirement not me<14>[ 17.681199] [IGT] kms_atomic: exiting, ret=77
11938 01:01:00.298560 t in function igt_require_intel, file ../lib/drmtest.c:880:
11939 01:01:00.308422 Test requirement: i<8>[ 17.691985] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11940 01:01:00.308677 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11942 01:01:00.311987 s_intel_device(fd)
11943 01:01:00.318867 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11944 01:01:00.322249 Test requirement: is_intel_device(fd)
11945 01:01:00.328149 No KMS driver or <14>[ 17.714842] [IGT] kms_atomic: executing
11946 01:01:00.331465 no outputs, pipe<14>[ 17.719751] [IGT] kms_atomic: exiting, ret=77
11947 01:01:00.334822 s: 16, outputs: 0
11948 01:01:00.344574 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.<8>[ 17.730876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11949 01:01:00.344858 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11951 01:01:00.347938 000s)[0m
11952 01:01:00.354751 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11953 01:01:00.357789 Using IGT_SRANDOM=1718499660 for randomisation
11954 01:01:00.361830 Opened device: /dev/dri/card0
11955 01:01:00.367848 Test requirement not met in functi<14>[ 17.754533] [IGT] kms_atomic: executing
11956 01:01:00.374310 on igt_require_i<14>[ 17.760029] [IGT] kms_atomic: exiting, ret=77
11957 01:01:00.377994 ntel, file ../lib/drmtest.c:880:
11958 01:01:00.381040 Test requirement: is_intel_device(fd)
11959 01:01:00.387567 Test re<8>[ 17.771433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11960 01:01:00.387822 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11962 01:01:00.394668 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11963 01:01:00.400748 Test requirement: is_intel_device(fd)
11964 01:01:00.407276 No KMS driver or no outputs, pipes: 16, outp<14>[ 17.795097] [IGT] kms_atomic: executing
11965 01:01:00.407389 uts: 0
11966 01:01:00.413747 [1mSubt<14>[ 17.799996] [IGT] kms_atomic: exiting, ret=77
11967 01:01:00.417122 est addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11968 01:01:00.427097 IGT-Version: 1.28-ga44ebfe <8>[ 17.811540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11969 01:01:00.427348 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11971 01:01:00.430586 (aarch64) (Linux: 6.1.92-cip22 aarch64)
11972 01:01:00.436921 Using IGT_SRANDOM=1718499660 for randomisation
11973 01:01:00.437029 Opened device: /dev/dri/card0
11974 01:01:00.447112 Test requirement not met in function igt<14>[ 17.833983] [IGT] kms_atomic: executing
11975 01:01:00.453222 _require_intel, <14>[ 17.839148] [IGT] kms_atomic: exiting, ret=77
11976 01:01:00.453359 file ../lib/drmtest.c:880:
11977 01:01:00.456602 Test requirement: is_intel_device(fd)
11978 01:01:00.466398 Test requirem<8>[ 17.850548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11979 01:01:00.466670 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11981 01:01:00.473283 ent not met in function igt_require_intel, file ../lib/drmtest.c:880:
11982 01:01:00.476660 Test requirement: is_intel_device(fd)
11983 01:01:00.479705 No KMS driver or no outputs, pipes: 16, outputs: 0
11984 01:01:00.486436 [1mSubtest addfb25-4-tiled: S<14>[ 17.874335] [IGT] kms_atomic: executing
11985 01:01:00.493475 KIP (0.000s)[0m<14>[ 17.879755] [IGT] kms_atomic: exiting, ret=77
11986 01:01:00.493578
11987 01:01:00.506484 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarc<8>[ 17.890833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11988 01:01:00.506589 h64)
11989 01:01:00.506855 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11991 01:01:00.509428 Using IGT_SRANDOM=1718499660 for randomisation
11992 01:01:00.512707 Opened device: /dev/dri/card0
11993 01:01:00.519275 No KMS driver or no outputs, pipes: 16, outputs: 0
11994 01:01:00.526016 [1mSubtest plane-overlay-legacy: SKIP <14>[ 17.912495] [IGT] kms_atomic: executing
11995 01:01:00.526093 (0.000s)[0m
11996 01:01:00.532898 IG<14>[ 17.918457] [IGT] kms_atomic: exiting, ret=77
11997 01:01:00.545839 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)<8>[ 17.929607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11998 01:01:00.545918
11999 01:01:00.546170 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12001 01:01:00.549383 Using IGT_SRANDOM=1718499660 for randomisation
12002 01:01:00.552877 Opened device: /dev/dri/card0
12003 01:01:00.555743 No KMS driver or no outputs, pipes: 16, outputs: 0
12004 01:01:00.562241 [1mSubtest plane-primary-l<14>[ 17.950779] [IGT] kms_atomic: executing
12005 01:01:00.568871 egacy: SKIP (0.0<14>[ 17.955937] [IGT] kms_atomic: exiting, ret=77
12006 01:01:00.568982 00s)[0m
12007 01:01:00.582129 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-ci<8>[ 17.966838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12008 01:01:00.582402 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12010 01:01:00.585197 p22 aarch64)
12011 01:01:00.588939 Using IGT_SRANDOM=1718499660 for randomisation
12012 01:01:00.592504 Opened device: /dev/dri/card0
12013 01:01:00.595417 No KMS driver or no outputs, pipes: 16, outputs: 0
12014 01:01:00.601686 [1mSubtest pla<14>[ 17.989209] [IGT] kms_atomic: executing
12015 01:01:00.608336 ne-primary-overl<14>[ 17.993966] [IGT] kms_atomic: exiting, ret=77
12016 01:01:00.611806 ay-mutable-zpos: SKIP (0.000s)[0m
12017 01:01:00.621714 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 18.005212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12018 01:01:00.621970 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12020 01:01:00.625221 6.1.92-cip22 aarch64)
12021 01:01:00.628268 Using IGT_SRANDOM=1718499660 for randomisation
12022 01:01:00.631705 Opened device: /dev/dri/card0
12023 01:01:00.634996 No KMS driver or no outputs, pipes: 16, outputs: 0
12024 01:01:00.641295 [1mS<14>[ 18.027989] [IGT] kms_atomic: executing
12025 01:01:00.644884 ubtest plane-imm<14>[ 18.032903] [IGT] kms_atomic: exiting, ret=77
12026 01:01:00.648415 utable-zpos: SKIP (0.000s)[0m
12027 01:01:00.661271 IGT-Version: 1.28-ga44ebfe (aarc<8>[ 18.043751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12028 01:01:00.661544 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12030 01:01:00.665229 h64) (Linux: 6.1.92-cip22 aarch64)
12031 01:01:00.668100 Using IGT_SRANDOM=1718499660 for randomisation
12032 01:01:00.671152 Opened device: /dev/dri/card0
12033 01:01:00.674175 No KMS driver or no outputs, pipes: 16, outputs: 0
12034 01:01:00.678009 [1mSubtest test-only: SKIP (0.000s)[0m
12035 01:01:00.687656 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch<14>[ 18.075679] [IGT] kms_atomic: executing
12036 01:01:00.687741 64)
12037 01:01:00.694091 Using IGT_S<14>[ 18.080854] [IGT] kms_atomic: exiting, ret=77
12038 01:01:00.697907 RANDOM=1718499660 for randomisation
12039 01:01:00.707578 Opened device: /dev/dri/car<8>[ 18.091584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12040 01:01:00.707664 d0
12041 01:01:00.707902 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12043 01:01:00.710516 No KMS driver or no outputs, pipes: 16, outputs: 0
12044 01:01:00.717161 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12045 01:01:00.723752 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12046 01:01:00.727641 <14>[ 18.113757] [IGT] kms_atomic: executing
12047 01:01:00.734137 Using IGT_SRANDO<14>[ 18.119415] [IGT] kms_atomic: exiting, ret=77
12048 01:01:00.737133 M=1718499660 for randomisation
12049 01:01:00.737242 Opened device: /dev/dri/card0
12050 01:01:00.747024 N<8>[ 18.130509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12051 01:01:00.747279 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12053 01:01:00.753929 o KMS driver or no outputs, pipe<8>[ 18.139921] <LAVA_SIGNAL_TESTSET STOP>
12054 01:01:00.754012 s: 16, outputs: 0
12055 01:01:00.754246 Received signal: <TESTSET> STOP
12056 01:01:00.754311 Closing test_set kms_atomic
12057 01:01:00.760428 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
12058 01:01:00.763361 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12059 01:01:00.770124 Using IGT_SRANDOM=1718499660 for randomisation
12060 01:01:00.770205 Opened device: /dev/dri/card0
12061 01:01:00.776669 No KMS driver or no outputs, pipes: 16, outputs: 0
12062 01:01:00.780246 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
12063 01:01:00.786566 IGT-Ve<8>[ 18.172901] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12064 01:01:00.786819 Received signal: <TESTSET> START kms_flip_event_leak
12065 01:01:00.786887 Starting test_set kms_flip_event_leak
12066 01:01:00.793885 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12067 01:01:00.796306 Using IGT_SRANDOM=1718499660 for randomisation
12068 01:01:00.799475 Opened device: /dev/dri/card0
12069 01:01:00.802957 No KMS driver or no outputs, pipes: 16, outputs: 0
12070 01:01:00.809461 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12071 01:01:00.816376 IGT-Version<14>[ 18.202090] [IGT] kms_flip_event_leak: executing
12072 01:01:00.822753 : 1.28-ga44ebfe <14>[ 18.208060] [IGT] kms_flip_event_leak: exiting, ret=77
12073 01:01:00.826590 (aarch64) (Linux: 6.1.92-cip22 aarch64)
12074 01:01:00.835959 Using IGT_SRANDOM=1718499660 for random<8>[ 18.219830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12075 01:01:00.836042 isation
12076 01:01:00.836278 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12078 01:01:00.842570 Opened device: /dev/dri<8>[ 18.229435] <LAVA_SIGNAL_TESTSET STOP>
12079 01:01:00.842652 /card0
12080 01:01:00.842886 Received signal: <TESTSET> STOP
12081 01:01:00.842950 Closing test_set kms_flip_event_leak
12082 01:01:00.846140 No KMS driver or no outputs, pipes: 16, outputs: 0
12083 01:01:00.852712 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12084 01:01:00.859006 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12085 01:01:00.865711 Using IGT_SRANDOM=1718<8>[ 18.251830] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12086 01:01:00.865963 Received signal: <TESTSET> START kms_prop_blob
12087 01:01:00.866033 Starting test_set kms_prop_blob
12088 01:01:00.868811 499660 for randomisation
12089 01:01:00.868895 Opened device: /dev/dri/card0
12090 01:01:00.875554 No KMS driver or no outputs, pipes: 16, outputs: 0
12091 01:01:00.882599 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0<14>[ 18.270363] [IGT] kms_prop_blob: executing
12092 01:01:00.885546 m
12093 01:01:00.891935 IGT-Version: <14>[ 18.276836] [IGT] kms_prop_blob: starting subtest basic
12094 01:01:00.898820 1.28-ga44ebfe (a<14>[ 18.283435] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12095 01:01:00.905448 arch64) (Linux: <14>[ 18.291133] [IGT] kms_prop_blob: exiting, ret=0
12096 01:01:00.905564 6.1.92-cip22 aarch64)
12097 01:01:00.912364 Using IGT_SRANDOM=1718499660 for randomisation
12098 01:01:00.918423 Opened de<8>[ 18.303005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12099 01:01:00.918507 vice: /dev/dri/card0
12100 01:01:00.918745 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12102 01:01:00.925227 No KMS driver or no outputs, pipes: 16, outputs: 0
12103 01:01:00.928545 [1mSubtest atomic-plane-damage: SKIP (0.000s)[0m
12104 01:01:00.938317 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.9<14>[ 18.324772] [IGT] kms_prop_blob: executing
12105 01:01:00.945267 2-cip22 aarch64)<14>[ 18.330835] [IGT] kms_prop_blob: starting subtest blob-prop-core
12106 01:01:00.945366
12107 01:01:00.954873 Using IGT_SRAN<14>[ 18.338306] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12108 01:01:00.961684 DOM=1718499660 f<14>[ 18.347003] [IGT] kms_prop_blob: exiting, ret=0
12109 01:01:00.961767 or randomisation
12110 01:01:00.964813 Opened device: /dev/dri/card0
12111 01:01:00.974960 No KMS driver o<8>[ 18.358443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12112 01:01:00.975215 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12114 01:01:00.978266 r no outputs, pipes: 16, outputs: 0
12115 01:01:00.982022 [1mSubtest basic: SKIP (0.000s)[0m
12116 01:01:00.984872 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12117 01:01:00.991438 Using IGT_SRANDOM=1718499660 for randomisation
12118 01:01:00.994667 O<14>[ 18.382242] [IGT] kms_prop_blob: executing
12119 01:01:01.001294 pened device: /d<14>[ 18.387337] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12120 01:01:01.004611 ev/dri/card0
12121 01:01:01.011163 St<14>[ 18.395366] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12122 01:01:01.017812 arting subtest: <14>[ 18.404153] [IGT] kms_prop_blob: exiting, ret=0
12123 01:01:01.017895 basic
12124 01:01:01.020988 [1mSubtest basic: SUCCESS (0.000s)[0m
12125 01:01:01.031275 IGT-Version: 1.2<8>[ 18.415531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12126 01:01:01.031530 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12128 01:01:01.034448 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12129 01:01:01.040843 Using IGT_SRANDOM=1718499660 for randomisation
12130 01:01:01.040925 Opened device: /dev/dri/card0
12131 01:01:01.050895 Starting subtest: blob-prop-c<14>[ 18.437016] [IGT] kms_prop_blob: executing
12132 01:01:01.050978 ore
12133 01:01:01.057947 [1mSubtest<14>[ 18.442125] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12134 01:01:01.067571 blob-prop-core:<14>[ 18.450075] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12135 01:01:01.074021 SUCCESS (0.000s<14>[ 18.458912] [IGT] kms_prop_blob: exiting, ret=0
12136 01:01:01.074104 )[0m
12137 01:01:01.080456 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12138 01:01:01.086868 Using<8>[ 18.470739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12139 01:01:01.087124 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12141 01:01:01.090442 IGT_SRANDOM=1718499660 for randomisation
12142 01:01:01.093452 Opened device: /dev/dri/card0
12143 01:01:01.097293 Starting subtest: blob-prop-validate
12144 01:01:01.100715 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12145 01:01:01.107020 IGT-Versio<14>[ 18.493673] [IGT] kms_prop_blob: executing
12146 01:01:01.113314 n: 1.28-ga44ebfe<14>[ 18.499706] [IGT] kms_prop_blob: starting subtest blob-multiple
12147 01:01:01.123284 (aarch64) (Linu<14>[ 18.507255] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12148 01:01:01.130315 x: 6.1.92-cip22 <14>[ 18.515604] [IGT] kms_prop_blob: exiting, ret=0
12149 01:01:01.130398 aarch64)
12150 01:01:01.133717 Using IGT_SRANDOM=1718499661 for randomisation
12151 01:01:01.143498 Opened<8>[ 18.526745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12152 01:01:01.143582 device: /dev/dri/card0
12153 01:01:01.143821 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12155 01:01:01.146486 Starting subtest: blob-prop-lifetime
12156 01:01:01.153175 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12157 01:01:01.160065 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 18.548173] [IGT] kms_prop_blob: executing
12158 01:01:01.169655 : 6.1.92-cip22 a<14>[ 18.553216] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12159 01:01:01.169738 arch64)
12160 01:01:01.179641 Using I<14>[ 18.561239] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12161 01:01:01.182685 GT_SRANDOM=17184<14>[ 18.570337] [IGT] kms_prop_blob: exiting, ret=0
12162 01:01:01.185888 99661 for randomisation
12163 01:01:01.189589 Opened device: /dev/dri/card0
12164 01:01:01.195655 Starting<8>[ 18.581871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12165 01:01:01.195911 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12167 01:01:01.199278 subtest: blob-multiple
12168 01:01:01.202304 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12169 01:01:01.209139 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12170 01:01:01.215552 Using IGT_SRANDOM=1718499661 for r<14>[ 18.603981] [IGT] kms_prop_blob: executing
12171 01:01:01.219318 andomisation
12172 01:01:01.225356 Op<14>[ 18.609948] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12173 01:01:01.235146 ened device: /de<14>[ 18.617626] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12174 01:01:01.235230 v/dri/card0
12175 01:01:01.239271 Sta<14>[ 18.626392] [IGT] kms_prop_blob: exiting, ret=0
12176 01:01:01.242112 rting subtest: invalid-get-prop-any
12177 01:01:01.251658 [1mSubtest invalid-get-pro<8>[ 18.637759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12178 01:01:01.251946 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12180 01:01:01.255559 p-any: SUCCESS (0.000s)[0m
12181 01:01:01.261641 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12182 01:01:01.265154 Using IGT_SRANDOM=1718499661 for randomisation
12183 01:01:01.268864 Opened device: /dev/dri/card0
12184 01:01:01.272011 <14>[ 18.659557] [IGT] kms_prop_blob: executing
12185 01:01:01.281700 Starting subtest<14>[ 18.665784] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12186 01:01:01.291290 : invalid-get-pr<14>[ 18.673646] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12187 01:01:01.291406 op
12188 01:01:01.295212 [1mSubtest <14>[ 18.682891] [IGT] kms_prop_blob: exiting, ret=0
12189 01:01:01.301646 invalid-get-prop: SUCCESS (0.000s)[0m
12190 01:01:01.308244 IGT-Version: 1.28-ga44eb<8>[ 18.694400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12191 01:01:01.308525 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12193 01:01:01.314589 fe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12194 01:01:01.318051 Using IGT_SRANDOM=1718499661 for randomisation
12195 01:01:01.321777 Opened device: /dev/dri/card0
12196 01:01:01.327888 Starting subtest: invalid-set-prop-an<14>[ 18.715947] [IGT] kms_prop_blob: executing
12197 01:01:01.327997 y
12198 01:01:01.334969 [1mSubtest i<14>[ 18.720963] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12199 01:01:01.344348 nvalid-set-prop-<14>[ 18.728876] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12200 01:01:01.351030 any: SUCCESS (0.<14>[ 18.737422] [IGT] kms_prop_blob: exiting, ret=0
12201 01:01:01.351113 000s)[0m
12202 01:01:01.364224 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-c<8>[ 18.748881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12203 01:01:01.364335 ip22 aarch64)
12204 01:01:01.364590 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12206 01:01:01.371352 Using IGT_SRANDOM<8>[ 18.758025] <LAVA_SIGNAL_TESTSET STOP>
12207 01:01:01.371606 Received signal: <TESTSET> STOP
12208 01:01:01.371674 Closing test_set kms_prop_blob
12209 01:01:01.375037 =1718499661 for randomisation
12210 01:01:01.377656 Opened device: /dev/dri/card0
12211 01:01:01.380522 Starting subtest: invalid-set-prop
12212 01:01:01.384332 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12213 01:01:01.403507 <8>[ 18.790799] <LAVA_SIGNAL_TESTSET START kms_setmode>
12214 01:01:01.403762 Received signal: <TESTSET> START kms_setmode
12215 01:01:01.403834 Starting test_set kms_setmode
12216 01:01:01.432072 <14>[ 18.819536] [IGT] kms_setmode: executing
12217 01:01:01.438443 IGT-Version: 1.2<14>[ 18.824472] [IGT] kms_setmode: starting subtest basic
12218 01:01:01.445049 8-ga44ebfe (aarc<14>[ 18.830978] [IGT] kms_setmode: finished subtest basic, SKIP
12219 01:01:01.451913 h64) (Linux: 6.1<14>[ 18.838335] [IGT] kms_setmode: exiting, ret=77
12220 01:01:01.455337 .92-cip22 aarch64)
12221 01:01:01.464997 Using IGT_SRANDOM=1718499661 for randomisati<8>[ 18.849840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12222 01:01:01.465081 on
12223 01:01:01.465302 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12225 01:01:01.468294 Opened device: /dev/dri/card0
12226 01:01:01.468376 Starting subtest: basic
12227 01:01:01.471664 No dynamic tests executed.
12228 01:01:01.475193 [1mSubtest basic: SKIP (0.000s)[0m
12229 01:01:01.483161 <14>[ 18.870273] [IGT] kms_setmode: executing
12230 01:01:01.489460 IGT-Version: 1.2<14>[ 18.874936] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12231 01:01:01.499385 8-ga44ebfe (aarc<14>[ 18.883187] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12232 01:01:01.505946 h64) (Linux: 6.1<14>[ 18.892013] [IGT] kms_setmode: exiting, ret=77
12233 01:01:01.506037 .92-cip22 aarch64)
12234 01:01:01.519159 Using IGT_SRANDOM=1718499661 for randomisati<8>[ 18.903558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12235 01:01:01.519243 on
12236 01:01:01.519481 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12238 01:01:01.522592 Opened device: /dev/dri/card0
12239 01:01:01.525912 Starting subtest: basic-clone-single-crtc
12240 01:01:01.529128 No dynamic tests executed.
12241 01:01:01.536091 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m<14>[ 18.925454] [IGT] kms_setmode: executing
12242 01:01:01.539584
12243 01:01:01.545915 IGT-Version: 1.2<14>[ 18.930307] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12244 01:01:01.555494 8-ga44ebfe (aarc<14>[ 18.938746] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12245 01:01:01.562281 h64) (Linux: 6.1<14>[ 18.947747] [IGT] kms_setmode: exiting, ret=77
12246 01:01:01.562364 .92-cip22 aarch64)
12247 01:01:01.575629 Using IGT_SRANDOM=1718499661 for randomisati<8>[ 18.958892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12248 01:01:01.575714 on
12249 01:01:01.575951 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12251 01:01:01.579138 Opened device: /dev/dri/card0
12252 01:01:01.582482 Starting subtest: invalid-clone-single-crtc
12253 01:01:01.585437 No dynamic tests executed.
12254 01:01:01.592048 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)<14>[ 18.981241] [IGT] kms_setmode: executing
12255 01:01:01.595241 [0m
12256 01:01:01.601950 <14>[ 18.986131] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12257 01:01:01.611483 IGT-Version: 1.2<14>[ 18.993776] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12258 01:01:01.618126 8-ga44ebfe (aarc<14>[ 19.003125] [IGT] kms_setmode: exiting, ret=77
12259 01:01:01.621351 h64) (Linux: 6.1.92-cip22 aarch64)
12260 01:01:01.631725 Using IGT_SRANDOM=1718499661<8>[ 19.014670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12261 01:01:01.631808 for randomisation
12262 01:01:01.632046 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12264 01:01:01.634742 Opened device: /dev/dri/card0
12265 01:01:01.638217 Starting subtest: invalid-clone-exclusive-crtc
12266 01:01:01.641309 No dynamic tests executed.
12267 01:01:01.651141 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0<14>[ 19.037146] [IGT] kms_setmode: executing
12268 01:01:01.651225 .000s)[0m
12269 01:01:01.658550 <14>[ 19.043211] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12270 01:01:01.667743 IGT-Version: 1.2<14>[ 19.050768] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12271 01:01:01.674091 8-ga44ebfe (aarc<14>[ 19.059356] [IGT] kms_setmode: exiting, ret=77
12272 01:01:01.677438 h64) (Linux: 6.1.92-cip22 aarch64)
12273 01:01:01.687554 Using IGT_SRANDOM=1718499661<8>[ 19.070755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12274 01:01:01.687638 for randomisation
12275 01:01:01.687876 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12277 01:01:01.691037 Opened device: /dev/dri/card0
12278 01:01:01.693860 Starting subtest: clone-exclusive-crtc
12279 01:01:01.697504 No dynamic tests executed.
12280 01:01:01.700575 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12281 01:01:01.704228 <14>[ 19.092636] [IGT] kms_setmode: executing
12282 01:01:01.714445 IGT-Version: 1.2<14>[ 19.098421] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12283 01:01:01.723777 8-ga44ebfe (aarc<14>[ 19.107567] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12284 01:01:01.730391 h64) (Linux: 6.1<14>[ 19.117375] [IGT] kms_setmode: exiting, ret=77
12285 01:01:01.733673 .92-cip22 aarch64)
12286 01:01:01.746848 Using IGT_SRANDOM=1718499661 for randomisati<8>[ 19.128370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12287 01:01:01.746934 on
12288 01:01:01.747175 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12290 01:01:01.753482 Opened device: /dev/dri/card<8>[ 19.139410] <LAVA_SIGNAL_TESTSET STOP>
12291 01:01:01.753565 0
12292 01:01:01.753801 Received signal: <TESTSET> STOP
12293 01:01:01.753867 Closing test_set kms_setmode
12294 01:01:01.756572 Starting subtest: invalid-clone-single-crtc-stealing
12295 01:01:01.760305 No dynamic tests executed.
12296 01:01:01.766747 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12297 01:01:01.773023 <8>[ 19.160548] <LAVA_SIGNAL_TESTSET START kms_vblank>
12298 01:01:01.773293 Received signal: <TESTSET> START kms_vblank
12299 01:01:01.773380 Starting test_set kms_vblank
12300 01:01:01.791441 <14>[ 19.178529] [IGT] kms_vblank: executing
12301 01:01:01.798028 IGT-Version: 1.2<14>[ 19.183331] [IGT] kms_vblank: exiting, ret=77
12302 01:01:01.801119 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12303 01:01:01.807575 Using IGT_SR<8>[ 19.194505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12304 01:01:01.807830 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12306 01:01:01.810702 ANDOM=1718499661 for randomisation
12307 01:01:01.814045 Opened device: /dev/dri/card0
12308 01:01:01.817266 No KMS driver or no outputs, pipes: 16, outputs: 0
12309 01:01:01.824431 [1mSubtest invalid: SKIP (0.000s)[0m
12310 01:01:01.827515 <14>[ 19.214877] [IGT] kms_vblank: executing
12311 01:01:01.833820 IGT-Version: 1.2<14>[ 19.219670] [IGT] kms_vblank: exiting, ret=77
12312 01:01:01.837196 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12313 01:01:01.847490 Using IGT_SRANDOM=1718499661<8>[ 19.231059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12314 01:01:01.847574 for randomisation
12315 01:01:01.847810 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12317 01:01:01.850729 Opened device: /dev/dri/card0
12318 01:01:01.853898 No KMS driver or no outputs, pipes: 16, outputs: 0
12319 01:01:01.857197 [1mSubtest crtc-id: SKIP (0.000s)[0m
12320 01:01:01.865021 <14>[ 19.252555] [IGT] kms_vblank: executing
12321 01:01:01.871809 IGT-Version: 1.2<14>[ 19.257200] [IGT] kms_vblank: exiting, ret=77
12322 01:01:01.875261 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12323 01:01:01.881262 Using IGT_SR<8>[ 19.268472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12324 01:01:01.881532 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12326 01:01:01.885359 ANDOM=1718499661 for randomisation
12327 01:01:01.888284 Opened device: /dev/dri/card0
12328 01:01:01.895078 No KMS driver or no outputs, pipes: 16, outputs: 0
12329 01:01:01.897675 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12330 01:01:01.905912 <14>[ 19.293545] [IGT] kms_vblank: executing
12331 01:01:01.912669 IGT-Version: 1.2<14>[ 19.298458] [IGT] kms_vblank: exiting, ret=77
12332 01:01:01.916036 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12333 01:01:01.926391 Using IGT_SRANDOM=1718499661 for randomisati<8>[ 19.311272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12334 01:01:01.926474 on
12335 01:01:01.926711 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12337 01:01:01.929750 Opened device: /dev/dri/card0
12338 01:01:01.935440 No KMS driver or no outputs, pipes: 16, outputs: 0
12339 01:01:01.938732 [1mSubtest query-idle: SKIP (0.000s)[0m
12340 01:01:01.955948 <14>[ 19.343670] [IGT] kms_vblank: executing
12341 01:01:01.962608 IGT-Version: 1.2<14>[ 19.348761] [IGT] kms_vblank: exiting, ret=77
12342 01:01:01.966016 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12343 01:01:01.975815 Using IGT_SRANDOM=1718499661<8>[ 19.360191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12344 01:01:01.976071 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12346 01:01:01.979036 for randomisation
12347 01:01:01.979118 Opened device: /dev/dri/card0
12348 01:01:01.985717 No KMS driver or no outputs, pipes: 16, outputs: 0
12349 01:01:01.989170 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12350 01:01:01.995678 <14>[ 19.382401] [IGT] kms_vblank: executing
12351 01:01:01.998750 IGT-Version: 1.2<14>[ 19.387033] [IGT] kms_vblank: exiting, ret=77
12352 01:01:02.005613 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12353 01:01:02.011976 Using IGT_SR<8>[ 19.397403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12354 01:01:02.012231 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12356 01:01:02.015544 ANDOM=1718499661 for randomisation
12357 01:01:02.018666 Opened device: /dev/dri/card0
12358 01:01:02.022441 No KMS driver or no outputs, pipes: 16, outputs: 0
12359 01:01:02.031582 [1mSubtest query-forked: SKIP (0.000s)[<14>[ 19.418835] [IGT] kms_vblank: executing
12360 01:01:02.031666 0m
12361 01:01:02.038551 IGT-Version: 1.2<14>[ 19.423985] [IGT] kms_vblank: exiting, ret=77
12362 01:01:02.042085 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12363 01:01:02.051533 Using IGT_SR<8>[ 19.434645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12364 01:01:02.051787 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12366 01:01:02.054777 ANDOM=1718499662 for randomisation
12367 01:01:02.054859 Opened device: /dev/dri/card0
12368 01:01:02.061517 No KMS driver or no outputs, pipes: 16, outputs: 0
12369 01:01:02.068066 [1mSubtest query-forked-hang: SKIP (0.00<14>[ 19.456191] [IGT] kms_vblank: executing
12370 01:01:02.068148 0s)[0m
12371 01:01:02.074564 <14>[ 19.461621] [IGT] kms_vblank: exiting, ret=77
12372 01:01:02.087699 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<8>[ 19.471493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12373 01:01:02.087808 4)
12374 01:01:02.088079 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12376 01:01:02.090901 Using IGT_SRANDOM=1718499662 for randomisation
12377 01:01:02.094202 Opened device: /dev/dri/card0
12378 01:01:02.097488 No KMS driver or no outputs, pipes: 16, outputs: 0
12379 01:01:02.104292 [1mSubtest query-busy: S<14>[ 19.492786] [IGT] kms_vblank: executing
12380 01:01:02.110853 KIP (0.000s)[0m<14>[ 19.497697] [IGT] kms_vblank: exiting, ret=77
12381 01:01:02.110956
12382 01:01:02.124325 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarc<8>[ 19.508132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12383 01:01:02.124409 h64)
12384 01:01:02.124660 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12386 01:01:02.127158 Using IGT_SRANDOM=1718499662 for randomisation
12387 01:01:02.130896 Opened device: /dev/dri/card0
12388 01:01:02.134096 No KMS driver or no outputs, pipes: 16, outputs: 0
12389 01:01:02.140589 [1mSubtest query-busy-<14>[ 19.529691] [IGT] kms_vblank: executing
12390 01:01:02.146951 hang: SKIP (0.00<14>[ 19.534935] [IGT] kms_vblank: exiting, ret=77
12391 01:01:02.147054 0s)[0m
12392 01:01:02.160145 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip<8>[ 19.545563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12393 01:01:02.160256 22 aarch64)
12394 01:01:02.160525 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12396 01:01:02.166967 Using IGT_SRANDOM=1718499662 for randomisation
12397 01:01:02.170969 Opened device: /dev/dri/card0
12398 01:01:02.173633 No KMS driver or no outputs, pipes: 16, outputs: 0
12399 01:01:02.180720 [1mSubtest quer<14>[ 19.566512] [IGT] kms_vblank: executing
12400 01:01:02.183846 y-forked-busy: S<14>[ 19.571984] [IGT] kms_vblank: exiting, ret=77
12401 01:01:02.186892 KIP (0.000s)[0m
12402 01:01:02.197049 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12404 01:01:02.200584 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6<8>[ 19.582448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12405 01:01:02.200689 .1.92-cip22 aarch64)
12406 01:01:02.203441 Using IGT_SRANDOM=1718499662 for randomisation
12407 01:01:02.206602 Opened device: /dev/dri/card0
12408 01:01:02.213480 No KMS driver or no outputs, pipes: 16, outputs: 0
12409 01:01:02.216469 [1mSub<14>[ 19.604572] [IGT] kms_vblank: executing
12410 01:01:02.223054 test query-forke<14>[ 19.609663] [IGT] kms_vblank: exiting, ret=77
12411 01:01:02.226602 d-busy-hang: SKIP (0.000s)[0m
12412 01:01:02.236724 IGT-Version: 1.28-ga44ebfe (aarc<8>[ 19.620086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12413 01:01:02.237004 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12415 01:01:02.239671 h64) (Linux: 6.1.92-cip22 aarch64)
12416 01:01:02.243099 Using IGT_SRANDOM=1718499662 for randomisation
12417 01:01:02.246788 Opened device: /dev/dri/card0
12418 01:01:02.249887 No KMS driver or no outputs, pipes: 16, outputs: 0
12419 01:01:02.252710 [1mSubtest wait-idle: SKIP (0.000s)[0m
12420 01:01:02.264533 <14>[ 19.651736] [IGT] kms_vblank: executing
12421 01:01:02.271393 IGT-Version: 1.2<14>[ 19.656738] [IGT] kms_vblank: exiting, ret=77
12422 01:01:02.274060 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12423 01:01:02.283947 Using IGT_SRANDOM=1718499662<8>[ 19.667970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12424 01:01:02.284053 for randomisation
12425 01:01:02.284329 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12427 01:01:02.287399 Opened device: /dev/dri/card0
12428 01:01:02.293807 No KMS driver or no outputs, pipes: 16, outputs: 0
12429 01:01:02.297055 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12430 01:01:02.300484 <14>[ 19.690175] [IGT] kms_vblank: executing
12431 01:01:02.307164 IGT-Version: 1.2<14>[ 19.694903] [IGT] kms_vblank: exiting, ret=77
12432 01:01:02.314099 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12433 01:01:02.320222 Using IGT_SR<8>[ 19.705517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12434 01:01:02.320470 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12436 01:01:02.323720 ANDOM=1718499662 for randomisation
12437 01:01:02.327569 Opened device: /dev/dri/card0
12438 01:01:02.330542 No KMS driver or no outputs, pipes: 16, outputs: 0
12439 01:01:02.340295 [1mSubtest wait-forked: SKIP (0.000s)[0<14>[ 19.726560] [IGT] kms_vblank: executing
12440 01:01:02.340378 m
12441 01:01:02.346572 IGT-Version: 1.2<14>[ 19.731782] [IGT] kms_vblank: exiting, ret=77
12442 01:01:02.350183 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12443 01:01:02.356854 Using IGT_SR<8>[ 19.742184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12444 01:01:02.357121 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12446 01:01:02.359631 ANDOM=1718499662 for randomisation
12447 01:01:02.363035 Opened device: /dev/dri/card0
12448 01:01:02.369890 No KMS driver or no outputs, pipes: 16, outputs: 0
12449 01:01:02.376392 [1mSubtest wait-forked-hang: SKIP (0.000<14>[ 19.763941] [IGT] kms_vblank: executing
12450 01:01:02.376476 s)[0m
12451 01:01:02.383074 <14>[ 19.769315] [IGT] kms_vblank: exiting, ret=77
12452 01:01:02.392888 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<8>[ 19.778721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12453 01:01:02.392972 4)
12454 01:01:02.393210 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12456 01:01:02.399316 Using IGT_SRANDOM=1718499662 for randomisation
12457 01:01:02.403034 Opened device: /dev/dri/card0
12458 01:01:02.406395 No KMS driver or no outputs, pipes: 16, outputs: 0
12459 01:01:02.409768 [1mSubtest wait-busy: SKIP (0.000s)[0m
12460 01:01:02.413189 <14>[ 19.800548] [IGT] kms_vblank: executing
12461 01:01:02.413294
12462 01:01:02.419547 IGT-Version: 1.2<14>[ 19.806511] [IGT] kms_vblank: exiting, ret=77
12463 01:01:02.422568 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12464 01:01:02.433089 Using IGT_SR<8>[ 19.816984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12465 01:01:02.433356 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12467 01:01:02.436426 ANDOM=1718499662 for randomisation
12468 01:01:02.439416 Opened device: /dev/dri/card0
12469 01:01:02.442455 No KMS driver or no outputs, pipes: 16, outputs: 0
12470 01:01:02.449366 [1mSubtest wait-busy-hang: SKIP (0.000s)<14>[ 19.838940] [IGT] kms_vblank: executing
12471 01:01:02.452773 [0m
12472 01:01:02.456121 <14>[ 19.843675] [IGT] kms_vblank: exiting, ret=77
12473 01:01:02.469479 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<8>[ 19.853070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12474 01:01:02.469564 4)
12475 01:01:02.469800 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12477 01:01:02.472430 Using IGT_SRANDOM=1718499662 for randomisation
12478 01:01:02.475703 Opened device: /dev/dri/card0
12479 01:01:02.479013 No KMS driver or no outputs, pipes: 16, outputs: 0
12480 01:01:02.485447 [1mSubtest wait-forked-b<14>[ 19.874887] [IGT] kms_vblank: executing
12481 01:01:02.492623 usy: SKIP (0.000<14>[ 19.879935] [IGT] kms_vblank: exiting, ret=77
12482 01:01:02.492705 s)[0m
12483 01:01:02.505919 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip2<8>[ 19.890182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12484 01:01:02.506176 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12486 01:01:02.508759 2 aarch64)
12487 01:01:02.512360 Using IGT_SRANDOM=1718499662 for randomisation
12488 01:01:02.515274 Opened device: /dev/dri/card0
12489 01:01:02.519010 No KMS driver or no outputs, pipes: 16, outputs: 0
12490 01:01:02.525371 [1mSubtest wait-forked-busy-hang<14>[ 19.913005] [IGT] kms_vblank: executing
12491 01:01:02.531744 : SKIP (0.000s)<14>[ 19.919042] [IGT] kms_vblank: exiting, ret=77
12492 01:01:02.531827 [0m
12493 01:01:02.545216 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 a<8>[ 19.929602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12494 01:01:02.545342 arch64)
12495 01:01:02.545580 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12497 01:01:02.551544 Using IGT_SRANDOM=1718499662 for randomisation
12498 01:01:02.551653 Opened device: /dev/dri/card0
12499 01:01:02.558582 No KMS driver or no outputs, pipes: 16, outputs: 0
12500 01:01:02.564949 [1mSubtest ts-conti<14>[ 19.951143] [IGT] kms_vblank: executing
12501 01:01:02.568136 nuation-idle: SK<14>[ 19.956489] [IGT] kms_vblank: exiting, ret=77
12502 01:01:02.572201 IP (0.000s)[0m
12503 01:01:02.584765 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.<8>[ 19.967031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12504 01:01:02.584849 1.92-cip22 aarch64)
12505 01:01:02.585089 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12507 01:01:02.588199 Using IGT_SRANDOM=1718499662 for randomisation
12508 01:01:02.591651 Opened device: /dev/dri/card0
12509 01:01:02.597812 No KMS driver or no outputs, pipes: 16, outputs: 0
12510 01:01:02.601485 [1mSubt<14>[ 19.989774] [IGT] kms_vblank: executing
12511 01:01:02.608308 est ts-continuat<14>[ 19.994501] [IGT] kms_vblank: exiting, ret=77
12512 01:01:02.611414 ion-idle-hang: SKIP (0.000s)[0m
12513 01:01:02.621011 IGT-Version: 1.28-ga44ebfe (aa<8>[ 20.005095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12514 01:01:02.621273 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12516 01:01:02.624157 rch64) (Linux: 6.1.92-cip22 aarch64)
12517 01:01:02.628072 Using IGT_SRANDOM=1718499662 for randomisation
12518 01:01:02.630871 Opened device: /dev/dri/card0
12519 01:01:02.640661 No KMS driver or no outputs, pipes: 16, out<14>[ 20.027296] [IGT] kms_vblank: executing
12520 01:01:02.640746 puts: 0
12521 01:01:02.644188 [1mSub<14>[ 20.032385] [IGT] kms_vblank: exiting, ret=77
12522 01:01:02.650813 test ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12523 01:01:02.660430 IGT-Version: 1<8>[ 20.042898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12524 01:01:02.660685 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12526 01:01:02.664046 .28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12527 01:01:02.667650 Using IGT_SRANDOM=1718499662 for randomisation
12528 01:01:02.671047 Opened device: /dev/dri/card0
12529 01:01:02.680563 No KMS driver or no outputs, pipes: 16, out<14>[ 20.066231] [IGT] kms_vblank: executing
12530 01:01:02.680648 puts: 0
12531 01:01:02.683669 [1mSub<14>[ 20.072015] [IGT] kms_vblank: exiting, ret=77
12532 01:01:02.691395 test ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12533 01:01:02.696878 IGT-Versio<8>[ 20.082256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12534 01:01:02.697132 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12536 01:01:02.703576 n: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12537 01:01:02.707370 Using IGT_SRANDOM=1718499662 for randomisation
12538 01:01:02.710182 Opened device: /dev/dri/card0
12539 01:01:02.716789 No KMS driver or no out<14>[ 20.105066] [IGT] kms_vblank: executing
12540 01:01:02.723191 puts, pipes: 16,<14>[ 20.109804] [IGT] kms_vblank: exiting, ret=77
12541 01:01:02.723276 outputs: 0
12542 01:01:02.737098 [1mSubtest ts-continuation-suspend: SKIP (0.000s)<8>[ 20.120010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12543 01:01:02.737182 [0m
12544 01:01:02.737420 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12546 01:01:02.743394 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12547 01:01:02.746412 Using IGT_SRANDOM=1718499662 for randomisation
12548 01:01:02.749572 Opened device: /dev/dri/card0
12549 01:01:02.753029 No KMS d<14>[ 20.142322] [IGT] kms_vblank: executing
12550 01:01:02.759628 river or no outp<14>[ 20.147631] [IGT] kms_vblank: exiting, ret=77
12551 01:01:02.762921 uts, pipes: 16, outputs: 0
12552 01:01:02.772909 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12554 01:01:02.776226 [1mSubtest ts-continuation-modeset:<8>[ 20.157705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12555 01:01:02.776310 SKIP (0.000s)[0m
12556 01:01:02.782671 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12557 01:01:02.785860 Using IGT_SRANDOM=1718499662 for randomisation
12558 01:01:02.792461 Opened device: /dev/dri/<14>[ 20.180247] [IGT] kms_vblank: executing
12559 01:01:02.792572 card0
12560 01:01:02.799171 No KMS dr<14>[ 20.185816] [IGT] kms_vblank: exiting, ret=77
12561 01:01:02.803004 iver or no outputs, pipes: 16, outputs: 0
12562 01:01:02.812392 [1mSubtest ts-contin<8>[ 20.196195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12563 01:01:02.812647 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12565 01:01:02.818738 uation-modeset-h<8>[ 20.206635] <LAVA_SIGNAL_TESTSET STOP>
12566 01:01:02.818991 Received signal: <TESTSET> STOP
12567 01:01:02.819061 Closing test_set kms_vblank
12568 01:01:02.825156 ang: SKIP (0.000<8>[ 20.212013] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14368604_1.5.2.3.1>
12569 01:01:02.825240 s)[0m
12570 01:01:02.825513 Received signal: <ENDRUN> 0_igt-kms-mediatek 14368604_1.5.2.3.1
12571 01:01:02.825597 Ending use of test pattern.
12572 01:01:02.825658 Ending test lava.0_igt-kms-mediatek (14368604_1.5.2.3.1), duration 6.34
12574 01:01:02.831819 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12575 01:01:02.838725 Using IGT_SRANDOM=1718499662 for randomisation
12576 01:01:02.838808 Opened device: /dev/dri/card0
12577 01:01:02.845403 No KMS driver or no outputs, pipes: 16, outputs: 0
12578 01:01:02.848448 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12579 01:01:02.851660 + set +x
12580 01:01:02.851743 <LAVA_TEST_RUNNER EXIT>
12581 01:01:02.851980 ok: lava_test_shell seems to have completed
12582 01:01:02.853820 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12583 01:01:02.853971 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12584 01:01:02.854058 end: 3 lava-test-retry (duration 00:00:07) [common]
12585 01:01:02.854148 start: 4 finalize (timeout 00:07:04) [common]
12586 01:01:02.854238 start: 4.1 power-off (timeout 00:00:30) [common]
12587 01:01:02.854387 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
12588 01:01:03.053747 >> Command sent successfully.
12589 01:01:03.056114 Returned 0 in 0 seconds
12590 01:01:03.156493 end: 4.1 power-off (duration 00:00:00) [common]
12592 01:01:03.156810 start: 4.2 read-feedback (timeout 00:07:03) [common]
12593 01:01:03.157124 Listened to connection for namespace 'common' for up to 1s
12594 01:01:04.157374 Finalising connection for namespace 'common'
12595 01:01:04.157546 Disconnecting from shell: Finalise
12596 01:01:04.157623 / #
12597 01:01:04.257941 end: 4.2 read-feedback (duration 00:00:01) [common]
12598 01:01:04.258105 end: 4 finalize (duration 00:00:01) [common]
12599 01:01:04.258223 Cleaning after the job
12600 01:01:04.258320 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/ramdisk
12601 01:01:04.264896 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/kernel
12602 01:01:04.280743 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/dtb
12603 01:01:04.280946 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368604/tftp-deploy-t37rlqdm/modules
12604 01:01:04.286567 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368604
12605 01:01:04.401221 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368604
12606 01:01:04.401752 Job finished correctly