Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 52
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 89
1 00:54:47.092511 lava-dispatcher, installed at version: 2024.03
2 00:54:47.092773 start: 0 validate
3 00:54:47.092971 Start time: 2024-06-16 00:54:47.092950+00:00 (UTC)
4 00:54:47.093249 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:54:47.093430 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:54:47.346392 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:54:47.347167 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:55:13.113867 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:55:13.114810 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 00:55:13.371242 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:55:13.371968 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:55:13.623321 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:55:13.624003 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:55:16.129822 validate duration: 29.04
16 00:55:16.130062 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:55:16.130161 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:55:16.130280 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:55:16.130442 Not decompressing ramdisk as can be used compressed.
20 00:55:16.130531 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:55:16.130595 saving as /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/ramdisk/initrd.cpio.gz
22 00:55:16.130656 total size: 5628169 (5 MB)
23 00:55:16.131704 progress 0 % (0 MB)
24 00:55:16.133228 progress 5 % (0 MB)
25 00:55:16.134802 progress 10 % (0 MB)
26 00:55:16.136195 progress 15 % (0 MB)
27 00:55:16.137717 progress 20 % (1 MB)
28 00:55:16.139121 progress 25 % (1 MB)
29 00:55:16.140640 progress 30 % (1 MB)
30 00:55:16.142135 progress 35 % (1 MB)
31 00:55:16.143510 progress 40 % (2 MB)
32 00:55:16.144998 progress 45 % (2 MB)
33 00:55:16.146341 progress 50 % (2 MB)
34 00:55:16.147858 progress 55 % (2 MB)
35 00:55:16.149341 progress 60 % (3 MB)
36 00:55:16.150714 progress 65 % (3 MB)
37 00:55:16.152283 progress 70 % (3 MB)
38 00:55:16.153616 progress 75 % (4 MB)
39 00:55:16.155153 progress 80 % (4 MB)
40 00:55:16.156486 progress 85 % (4 MB)
41 00:55:16.158085 progress 90 % (4 MB)
42 00:55:16.159718 progress 95 % (5 MB)
43 00:55:16.161073 progress 100 % (5 MB)
44 00:55:16.161277 5 MB downloaded in 0.03 s (175.34 MB/s)
45 00:55:16.161421 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:55:16.161641 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:55:16.161721 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:55:16.161796 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:55:16.161924 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:55:16.161985 saving as /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/kernel/Image
52 00:55:16.162039 total size: 54813184 (52 MB)
53 00:55:16.162093 No compression specified
54 00:55:16.163137 progress 0 % (0 MB)
55 00:55:16.176714 progress 5 % (2 MB)
56 00:55:16.190470 progress 10 % (5 MB)
57 00:55:16.204153 progress 15 % (7 MB)
58 00:55:16.217880 progress 20 % (10 MB)
59 00:55:16.231877 progress 25 % (13 MB)
60 00:55:16.246271 progress 30 % (15 MB)
61 00:55:16.260318 progress 35 % (18 MB)
62 00:55:16.274723 progress 40 % (20 MB)
63 00:55:16.288511 progress 45 % (23 MB)
64 00:55:16.302465 progress 50 % (26 MB)
65 00:55:16.316547 progress 55 % (28 MB)
66 00:55:16.330704 progress 60 % (31 MB)
67 00:55:16.344752 progress 65 % (34 MB)
68 00:55:16.358741 progress 70 % (36 MB)
69 00:55:16.372860 progress 75 % (39 MB)
70 00:55:16.386848 progress 80 % (41 MB)
71 00:55:16.400717 progress 85 % (44 MB)
72 00:55:16.414664 progress 90 % (47 MB)
73 00:55:16.428497 progress 95 % (49 MB)
74 00:55:16.442024 progress 100 % (52 MB)
75 00:55:16.442276 52 MB downloaded in 0.28 s (186.54 MB/s)
76 00:55:16.442428 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:55:16.442638 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:55:16.442720 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:55:16.442798 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:55:16.442932 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 00:55:16.442996 saving as /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 00:55:16.443050 total size: 57695 (0 MB)
84 00:55:16.443105 No compression specified
85 00:55:16.444265 progress 56 % (0 MB)
86 00:55:16.444533 progress 100 % (0 MB)
87 00:55:16.444728 0 MB downloaded in 0.00 s (32.85 MB/s)
88 00:55:16.444840 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:55:16.445045 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:55:16.445127 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:55:16.445216 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:55:16.445325 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:55:16.445385 saving as /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/nfsrootfs/full.rootfs.tar
95 00:55:16.445438 total size: 120894716 (115 MB)
96 00:55:16.445492 Using unxz to decompress xz
97 00:55:16.446688 progress 0 % (0 MB)
98 00:55:16.798989 progress 5 % (5 MB)
99 00:55:17.152809 progress 10 % (11 MB)
100 00:55:17.504898 progress 15 % (17 MB)
101 00:55:17.843483 progress 20 % (23 MB)
102 00:55:18.162120 progress 25 % (28 MB)
103 00:55:18.517206 progress 30 % (34 MB)
104 00:55:18.854083 progress 35 % (40 MB)
105 00:55:19.030566 progress 40 % (46 MB)
106 00:55:19.220261 progress 45 % (51 MB)
107 00:55:19.534886 progress 50 % (57 MB)
108 00:55:19.901953 progress 55 % (63 MB)
109 00:55:20.256617 progress 60 % (69 MB)
110 00:55:20.621437 progress 65 % (74 MB)
111 00:55:20.968626 progress 70 % (80 MB)
112 00:55:21.331803 progress 75 % (86 MB)
113 00:55:21.675866 progress 80 % (92 MB)
114 00:55:22.034823 progress 85 % (98 MB)
115 00:55:22.443975 progress 90 % (103 MB)
116 00:55:22.813873 progress 95 % (109 MB)
117 00:55:23.199215 progress 100 % (115 MB)
118 00:55:23.205048 115 MB downloaded in 6.76 s (17.06 MB/s)
119 00:55:23.205295 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:55:23.205641 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:55:23.205760 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:55:23.205877 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:55:23.206055 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:55:23.206153 saving as /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/modules/modules.tar
126 00:55:23.206254 total size: 8617404 (8 MB)
127 00:55:23.206347 Using unxz to decompress xz
128 00:55:23.208038 progress 0 % (0 MB)
129 00:55:23.227188 progress 5 % (0 MB)
130 00:55:23.254536 progress 10 % (0 MB)
131 00:55:23.282830 progress 15 % (1 MB)
132 00:55:23.306942 progress 20 % (1 MB)
133 00:55:23.330927 progress 25 % (2 MB)
134 00:55:23.355255 progress 30 % (2 MB)
135 00:55:23.382678 progress 35 % (2 MB)
136 00:55:23.408615 progress 40 % (3 MB)
137 00:55:23.432803 progress 45 % (3 MB)
138 00:55:23.458313 progress 50 % (4 MB)
139 00:55:23.488699 progress 55 % (4 MB)
140 00:55:23.522777 progress 60 % (4 MB)
141 00:55:23.546879 progress 65 % (5 MB)
142 00:55:23.573738 progress 70 % (5 MB)
143 00:55:23.597857 progress 75 % (6 MB)
144 00:55:23.623634 progress 80 % (6 MB)
145 00:55:23.648811 progress 85 % (7 MB)
146 00:55:23.673687 progress 90 % (7 MB)
147 00:55:23.698919 progress 95 % (7 MB)
148 00:55:23.723450 progress 100 % (8 MB)
149 00:55:23.729207 8 MB downloaded in 0.52 s (15.72 MB/s)
150 00:55:23.729381 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:55:23.729591 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:55:23.729668 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 00:55:23.729744 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 00:55:27.393341 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368556/extract-nfsrootfs-cgeyw8ut
156 00:55:27.393522 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:55:27.393622 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:55:27.393791 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1
159 00:55:27.393906 makedir: /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin
160 00:55:27.393996 makedir: /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/tests
161 00:55:27.394082 makedir: /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/results
162 00:55:27.394165 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-add-keys
163 00:55:27.394337 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-add-sources
164 00:55:27.394452 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-background-process-start
165 00:55:27.394566 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-background-process-stop
166 00:55:27.394689 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-common-functions
167 00:55:27.394810 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-echo-ipv4
168 00:55:27.394938 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-install-packages
169 00:55:27.395094 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-installed-packages
170 00:55:27.395210 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-os-build
171 00:55:27.395321 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-probe-channel
172 00:55:27.395432 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-probe-ip
173 00:55:27.395546 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-target-ip
174 00:55:27.395664 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-target-mac
175 00:55:27.395775 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-target-storage
176 00:55:27.395887 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-test-case
177 00:55:27.395997 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-test-event
178 00:55:27.396105 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-test-feedback
179 00:55:27.396214 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-test-raise
180 00:55:27.396323 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-test-reference
181 00:55:27.396431 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-test-runner
182 00:55:27.396537 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-test-set
183 00:55:27.396646 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-test-shell
184 00:55:27.396756 Updating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-add-keys (debian)
185 00:55:27.396891 Updating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-add-sources (debian)
186 00:55:27.397020 Updating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-install-packages (debian)
187 00:55:27.397145 Updating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-installed-packages (debian)
188 00:55:27.397269 Updating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/bin/lava-os-build (debian)
189 00:55:27.397378 Creating /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/environment
190 00:55:27.397467 LAVA metadata
191 00:55:27.397531 - LAVA_JOB_ID=14368556
192 00:55:27.397586 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:55:27.397679 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:55:27.397735 skipped lava-vland-overlay
195 00:55:27.397801 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:55:27.397870 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:55:27.397922 skipped lava-multinode-overlay
198 00:55:27.397983 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:55:27.398051 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:55:27.398115 Loading test definitions
201 00:55:27.398190 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:55:27.398291 Using /lava-14368556 at stage 0
203 00:55:27.398568 uuid=14368556_1.6.2.3.1 testdef=None
204 00:55:27.398647 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:55:27.398721 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:55:27.399106 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:55:27.399299 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:55:27.399830 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:55:27.400043 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:55:27.400593 runner path: /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/0/tests/0_timesync-off test_uuid 14368556_1.6.2.3.1
213 00:55:27.400737 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:55:27.400939 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:55:27.401003 Using /lava-14368556 at stage 0
217 00:55:27.401089 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:55:27.401164 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/0/tests/1_kselftest-alsa'
219 00:55:30.886824 Running '/usr/bin/git checkout kernelci.org
220 00:55:31.039177 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 00:55:31.039535 uuid=14368556_1.6.2.3.5 testdef=None
222 00:55:31.039635 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 00:55:31.039855 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 00:55:31.040502 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:55:31.040703 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 00:55:31.041561 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:55:31.041807 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 00:55:31.042691 runner path: /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/0/tests/1_kselftest-alsa test_uuid 14368556_1.6.2.3.5
232 00:55:31.042770 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 00:55:31.042829 BRANCH='cip-gitlab'
234 00:55:31.042882 SKIPFILE='/dev/null'
235 00:55:31.042932 SKIP_INSTALL='True'
236 00:55:31.043017 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:55:31.043115 TST_CASENAME=''
238 00:55:31.043165 TST_CMDFILES='alsa'
239 00:55:31.043312 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:55:31.043506 Creating lava-test-runner.conf files
242 00:55:31.043559 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368556/lava-overlay-b4vnmrg1/lava-14368556/0 for stage 0
243 00:55:31.043640 - 0_timesync-off
244 00:55:31.043698 - 1_kselftest-alsa
245 00:55:31.043783 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 00:55:31.043858 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 00:55:38.301151 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:55:38.301286 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 00:55:38.301369 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:55:38.301451 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 00:55:38.301531 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 00:55:38.460673 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:55:38.460814 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 00:55:38.460889 extracting modules file /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368556/extract-nfsrootfs-cgeyw8ut
255 00:55:38.683550 extracting modules file /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368556/extract-overlay-ramdisk-kp5us93b/ramdisk
256 00:55:38.912017 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:55:38.912165 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 00:55:38.912254 [common] Applying overlay to NFS
259 00:55:38.912314 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368556/compress-overlay-u2h9pt73/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368556/extract-nfsrootfs-cgeyw8ut
260 00:55:39.768264 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:55:39.768399 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 00:55:39.768482 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:55:39.768560 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 00:55:39.768631 Building ramdisk /var/lib/lava/dispatcher/tmp/14368556/extract-overlay-ramdisk-kp5us93b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368556/extract-overlay-ramdisk-kp5us93b/ramdisk
265 00:55:40.096057 >> 130405 blocks
266 00:55:42.220974 rename /var/lib/lava/dispatcher/tmp/14368556/extract-overlay-ramdisk-kp5us93b/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/ramdisk/ramdisk.cpio.gz
267 00:55:42.221147 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:55:42.221238 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 00:55:42.221315 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 00:55:42.221386 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/kernel/Image']
271 00:55:56.755951 Returned 0 in 14 seconds
272 00:55:56.856517 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/kernel/image.itb
273 00:55:57.248780 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:55:57.248914 output: Created: Sun Jun 16 01:55:57 2024
275 00:55:57.248979 output: Image 0 (kernel-1)
276 00:55:57.249033 output: Description:
277 00:55:57.249084 output: Created: Sun Jun 16 01:55:57 2024
278 00:55:57.249138 output: Type: Kernel Image
279 00:55:57.249191 output: Compression: lzma compressed
280 00:55:57.249246 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
281 00:55:57.249299 output: Architecture: AArch64
282 00:55:57.249349 output: OS: Linux
283 00:55:57.249399 output: Load Address: 0x00000000
284 00:55:57.249449 output: Entry Point: 0x00000000
285 00:55:57.249501 output: Hash algo: crc32
286 00:55:57.249555 output: Hash value: f6f06660
287 00:55:57.249611 output: Image 1 (fdt-1)
288 00:55:57.249664 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 00:55:57.249717 output: Created: Sun Jun 16 01:55:57 2024
290 00:55:57.249774 output: Type: Flat Device Tree
291 00:55:57.249830 output: Compression: uncompressed
292 00:55:57.249883 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 00:55:57.249939 output: Architecture: AArch64
294 00:55:57.249993 output: Hash algo: crc32
295 00:55:57.250044 output: Hash value: a9713552
296 00:55:57.250096 output: Image 2 (ramdisk-1)
297 00:55:57.250199 output: Description: unavailable
298 00:55:57.250338 output: Created: Sun Jun 16 01:55:57 2024
299 00:55:57.250417 output: Type: RAMDisk Image
300 00:55:57.250467 output: Compression: uncompressed
301 00:55:57.250515 output: Data Size: 18732254 Bytes = 18293.22 KiB = 17.86 MiB
302 00:55:57.250563 output: Architecture: AArch64
303 00:55:57.250611 output: OS: Linux
304 00:55:57.250658 output: Load Address: unavailable
305 00:55:57.250706 output: Entry Point: unavailable
306 00:55:57.250753 output: Hash algo: crc32
307 00:55:57.250800 output: Hash value: 5f9652bc
308 00:55:57.250847 output: Default Configuration: 'conf-1'
309 00:55:57.250893 output: Configuration 0 (conf-1)
310 00:55:57.250940 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 00:55:57.250987 output: Kernel: kernel-1
312 00:55:57.251034 output: Init Ramdisk: ramdisk-1
313 00:55:57.251080 output: FDT: fdt-1
314 00:55:57.251127 output: Loadables: kernel-1
315 00:55:57.251173 output:
316 00:55:57.251306 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 00:55:57.251396 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 00:55:57.251486 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 00:55:57.251567 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 00:55:57.251633 No LXC device requested
321 00:55:57.251702 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:55:57.251778 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 00:55:57.251848 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:55:57.251909 Checking files for TFTP limit of 4294967296 bytes.
325 00:55:57.252371 end: 1 tftp-deploy (duration 00:00:41) [common]
326 00:55:57.252473 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:55:57.252556 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:55:57.252667 substitutions:
329 00:55:57.252728 - {DTB}: 14368556/tftp-deploy-bd1jyqqo/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 00:55:57.252785 - {INITRD}: 14368556/tftp-deploy-bd1jyqqo/ramdisk/ramdisk.cpio.gz
331 00:55:57.252837 - {KERNEL}: 14368556/tftp-deploy-bd1jyqqo/kernel/Image
332 00:55:57.252888 - {LAVA_MAC}: None
333 00:55:57.252937 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368556/extract-nfsrootfs-cgeyw8ut
334 00:55:57.252987 - {NFS_SERVER_IP}: 192.168.201.1
335 00:55:57.253036 - {PRESEED_CONFIG}: None
336 00:55:57.253092 - {PRESEED_LOCAL}: None
337 00:55:57.253141 - {RAMDISK}: 14368556/tftp-deploy-bd1jyqqo/ramdisk/ramdisk.cpio.gz
338 00:55:57.253190 - {ROOT_PART}: None
339 00:55:57.253238 - {ROOT}: None
340 00:55:57.253286 - {SERVER_IP}: 192.168.201.1
341 00:55:57.253334 - {TEE}: None
342 00:55:57.253383 Parsed boot commands:
343 00:55:57.253430 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:55:57.253583 Parsed boot commands: tftpboot 192.168.201.1 14368556/tftp-deploy-bd1jyqqo/kernel/image.itb 14368556/tftp-deploy-bd1jyqqo/kernel/cmdline
345 00:55:57.253666 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:55:57.253743 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:55:57.253822 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:55:57.253897 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:55:57.253958 Not connected, no need to disconnect.
350 00:55:57.254023 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:55:57.254093 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:55:57.254183 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-5'
353 00:55:57.257704 Setting prompt string to ['lava-test: # ']
354 00:55:57.258102 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:55:57.258257 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:55:57.258424 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:55:57.258559 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:55:57.258767 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-5']
359 00:56:19.230399 Returned 0 in 21 seconds
360 00:56:19.330891 end: 2.2.2.1 pdu-reboot (duration 00:00:22) [common]
362 00:56:19.331175 end: 2.2.2 reset-device (duration 00:00:22) [common]
363 00:56:19.331275 start: 2.2.3 depthcharge-start (timeout 00:04:38) [common]
364 00:56:19.331360 Setting prompt string to 'Starting depthcharge on Juniper...'
365 00:56:19.331422 Changing prompt to 'Starting depthcharge on Juniper...'
366 00:56:19.331490 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
367 00:56:19.331844 [Enter `^Ec?' for help]
368 00:56:19.331913 [DL] 00000000 00000000 010701
369 00:56:19.331977
370 00:56:19.332032
371 00:56:19.332087 F0: 102B 0000
372 00:56:19.332143
373 00:56:19.332201 F3: 1006 0033 [0200]
374 00:56:19.332261
375 00:56:19.332316 F3: 4001 00E0 [0200]
376 00:56:19.332371
377 00:56:19.332427 F3: 0000 0000
378 00:56:19.332489
379 00:56:19.332543 V0: 0000 0000 [0001]
380 00:56:19.332598
381 00:56:19.332652 00: 1027 0002
382 00:56:19.332712
383 00:56:19.332766 01: 0000 0000
384 00:56:19.332818
385 00:56:19.332868 BP: 0C00 0251 [0000]
386 00:56:19.332916
387 00:56:19.332969 G0: 1182 0000
388 00:56:19.333017
389 00:56:19.333064 EC: 0004 0000 [0001]
390 00:56:19.333111
391 00:56:19.333158 S7: 0000 0000 [0000]
392 00:56:19.333210
393 00:56:19.333257 CC: 0000 0000 [0001]
394 00:56:19.333304
395 00:56:19.333352 T0: 0000 00DB [000F]
396 00:56:19.333399
397 00:56:19.333451 Jump to BL
398 00:56:19.333498
399 00:56:19.333544
400 00:56:19.333593
401 00:56:19.333642 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
402 00:56:19.333724 ARM64: Exception handlers installed.
403 00:56:19.333800 ARM64: Testing exception
404 00:56:19.333886 ARM64: Done test exception
405 00:56:19.333965 WDT: Last reset was cold boot
406 00:56:19.334041 SPI0(PAD0) initialized at 992727 Hz
407 00:56:19.334117 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
408 00:56:19.334196 Manufacturer: ef
409 00:56:19.334314 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
410 00:56:19.334400 Probing TPM: . done!
411 00:56:19.334451 TPM ready after 0 ms
412 00:56:19.334500 Connected to device vid:did:rid of 1ae0:0028:00
413 00:56:19.334548 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b81dc66
414 00:56:19.334597 Initialized TPM device CR50 revision 0
415 00:56:19.334653 tlcl_send_startup: Startup return code is 0
416 00:56:19.334703 TPM: setup succeeded
417 00:56:19.334751 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
418 00:56:19.334799 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
419 00:56:19.334847 in-header: 03 19 00 00 08 00 00 00
420 00:56:19.334902 in-data: a2 e0 47 00 13 00 00 00
421 00:56:19.334950 Chrome EC: UHEPI supported
422 00:56:19.334998 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
423 00:56:19.335047 in-header: 03 a1 00 00 08 00 00 00
424 00:56:19.335095 in-data: 84 60 60 10 00 00 00 00
425 00:56:19.335148 Phase 1
426 00:56:19.335195 FMAP: area GBB found @ 3f5000 (12032 bytes)
427 00:56:19.335243 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
428 00:56:19.335292 VB2:vb2_check_recovery() Recovery was requested manually
429 00:56:19.335350 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
430 00:56:19.335405 Recovery requested (1009000e)
431 00:56:19.335454 tlcl_extend: response is 0
432 00:56:19.335502 tlcl_extend: response is 0
433 00:56:19.335550
434 00:56:19.335596
435 00:56:19.335675 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
436 00:56:19.335752 ARM64: Exception handlers installed.
437 00:56:19.335827 ARM64: Testing exception
438 00:56:19.335906 ARM64: Done test exception
439 00:56:19.335982 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xaa70, sec=0x2019
440 00:56:19.336058 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
441 00:56:19.336137 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
442 00:56:19.336213 [RTC]rtc_get_frequency_meter,134: input=0xf, output=778
443 00:56:19.336290 [RTC]rtc_get_frequency_meter,134: input=0x17, output=959
444 00:56:19.336368 [RTC]rtc_get_frequency_meter,134: input=0x13, output=869
445 00:56:19.336445 [RTC]rtc_get_frequency_meter,134: input=0x11, output=823
446 00:56:19.336522 [RTC]rtc_get_frequency_meter,134: input=0x10, output=799
447 00:56:19.336599 [RTC]rtc_get_frequency_meter,134: input=0xf, output=777
448 00:56:19.336651 [RTC]rtc_get_frequency_meter,134: input=0x10, output=800
449 00:56:19.336700 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xaa70
450 00:56:19.336748 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
451 00:56:19.336796 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
452 00:56:19.336847 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
453 00:56:19.336925 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
454 00:56:19.337011 in-header: 03 19 00 00 08 00 00 00
455 00:56:19.337107 in-data: a2 e0 47 00 13 00 00 00
456 00:56:19.337187 Chrome EC: UHEPI supported
457 00:56:19.337265 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
458 00:56:19.337344 in-header: 03 a1 00 00 08 00 00 00
459 00:56:19.337420 in-data: 84 60 60 10 00 00 00 00
460 00:56:19.337495 Skip loading cached calibration data
461 00:56:19.337581 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
462 00:56:19.337660 in-header: 03 a1 00 00 08 00 00 00
463 00:56:19.337736 in-data: 84 60 60 10 00 00 00 00
464 00:56:19.337812 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
465 00:56:19.337892 in-header: 03 a1 00 00 08 00 00 00
466 00:56:19.337968 in-data: 84 60 60 10 00 00 00 00
467 00:56:19.338042 ADC[3]: Raw value=1043509 ID=8
468 00:56:19.338121 Manufacturer: ef
469 00:56:19.338197 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
470 00:56:19.338315 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
471 00:56:19.338368 CBFS @ 21000 size 3d4000
472 00:56:19.338416 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
473 00:56:19.338464 CBFS: Locating 'sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB'
474 00:56:19.338512 CBFS: Found @ offset 3c880 size 4b
475 00:56:19.338567 DRAM-K: Full Calibration
476 00:56:19.338616 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
477 00:56:19.338664 CBFS @ 21000 size 3d4000
478 00:56:19.338711 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
479 00:56:19.338759 CBFS: Locating 'fallback/dram'
480 00:56:19.338813 CBFS: Found @ offset 24b00 size 12268
481 00:56:19.338861 read SPI 0x45b44 0x1224c: 22773 us, 3263 KB/s, 26.104 Mbps
482 00:56:19.338908 ddr_geometry: 1, config: 0x0
483 00:56:19.338966 header.status = 0x0
484 00:56:19.339016 header.magic = 0x44524d4b (expected: 0x44524d4b)
485 00:56:19.339072 header.version = 0x5 (expected: 0x5)
486 00:56:19.339318 header.size = 0x8f0 (expected: 0x8f0)
487 00:56:19.339430 header.config = 0x0
488 00:56:19.339538 header.flags = 0x0
489 00:56:19.339647 header.checksum = 0x0
490 00:56:19.339756 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
491 00:56:19.339864 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
492 00:56:19.339973 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
493 00:56:19.340083 ddr_geometry:1
494 00:56:19.340189 [EMI] new MDL number = 1
495 00:56:19.340299 dram_cbt_mode_extern: 0
496 00:56:19.340406 dram_cbt_mode [RK0]: 0, [RK1]: 0
497 00:56:19.340514 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
498 00:56:19.340570
499 00:56:19.340619
500 00:56:19.340678 [Bianco] ETT version 0.0.0.1
501 00:56:19.340728 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
502 00:56:19.340784
503 00:56:19.340832 vSetVcoreByFreq with vcore:762500, freq=1600
504 00:56:19.340881
505 00:56:19.340928 [DramcInit]
506 00:56:19.340975 AutoRefreshCKEOff AutoREF OFF
507 00:56:19.341030 DDRPhyPLLSetting-CKEOFF
508 00:56:19.341078 DDRPhyPLLSetting-CKEON
509 00:56:19.341138
510 00:56:19.341202 Enable WDQS
511 00:56:19.341289 [ModeRegInit_LP4] CH0 RK0
512 00:56:19.341361 Write Rank0 MR13 =0x18
513 00:56:19.341412 Write Rank0 MR12 =0x5d
514 00:56:19.341460 Write Rank0 MR1 =0x56
515 00:56:19.341514 Write Rank0 MR2 =0x1a
516 00:56:19.341562 Write Rank0 MR11 =0x0
517 00:56:19.341610 Write Rank0 MR22 =0x38
518 00:56:19.341658 Write Rank0 MR14 =0x5d
519 00:56:19.341705 Write Rank0 MR3 =0x30
520 00:56:19.341759 Write Rank0 MR13 =0x58
521 00:56:19.341807 Write Rank0 MR12 =0x5d
522 00:56:19.341854 Write Rank0 MR1 =0x56
523 00:56:19.341901 Write Rank0 MR2 =0x2d
524 00:56:19.341948 Write Rank0 MR11 =0x23
525 00:56:19.342002 Write Rank0 MR22 =0x34
526 00:56:19.342050 Write Rank0 MR14 =0x10
527 00:56:19.342098 Write Rank0 MR3 =0x30
528 00:56:19.342145 Write Rank0 MR13 =0xd8
529 00:56:19.342192 [ModeRegInit_LP4] CH0 RK1
530 00:56:19.342290 Write Rank1 MR13 =0x18
531 00:56:19.342340 Write Rank1 MR12 =0x5d
532 00:56:19.342387 Write Rank1 MR1 =0x56
533 00:56:19.342434 Write Rank1 MR2 =0x1a
534 00:56:19.342482 Write Rank1 MR11 =0x0
535 00:56:19.342536 Write Rank1 MR22 =0x38
536 00:56:19.342585 Write Rank1 MR14 =0x5d
537 00:56:19.342633 Write Rank1 MR3 =0x30
538 00:56:19.342681 Write Rank1 MR13 =0x58
539 00:56:19.342728 Write Rank1 MR12 =0x5d
540 00:56:19.342782 Write Rank1 MR1 =0x56
541 00:56:19.342840 Write Rank1 MR2 =0x2d
542 00:56:19.342888 Write Rank1 MR11 =0x23
543 00:56:19.342936 Write Rank1 MR22 =0x34
544 00:56:19.342984 Write Rank1 MR14 =0x10
545 00:56:19.343037 Write Rank1 MR3 =0x30
546 00:56:19.343085 Write Rank1 MR13 =0xd8
547 00:56:19.343142 [ModeRegInit_LP4] CH1 RK0
548 00:56:19.343197 Write Rank0 MR13 =0x18
549 00:56:19.343245 Write Rank0 MR12 =0x5d
550 00:56:19.343296 Write Rank0 MR1 =0x56
551 00:56:19.343343 Write Rank0 MR2 =0x1a
552 00:56:19.343389 Write Rank0 MR11 =0x0
553 00:56:19.343436 Write Rank0 MR22 =0x38
554 00:56:19.343483 Write Rank0 MR14 =0x5d
555 00:56:19.343554 Write Rank0 MR3 =0x30
556 00:56:19.343629 Write Rank0 MR13 =0x58
557 00:56:19.343704 Write Rank0 MR12 =0x5d
558 00:56:19.343793 Write Rank0 MR1 =0x56
559 00:56:19.343869 Write Rank0 MR2 =0x2d
560 00:56:19.343944 Write Rank0 MR11 =0x23
561 00:56:19.344022 Write Rank0 MR22 =0x34
562 00:56:19.344097 Write Rank0 MR14 =0x10
563 00:56:19.344171 Write Rank0 MR3 =0x30
564 00:56:19.344248 Write Rank0 MR13 =0xd8
565 00:56:19.344323 [ModeRegInit_LP4] CH1 RK1
566 00:56:19.344398 Write Rank1 MR13 =0x18
567 00:56:19.344484 Write Rank1 MR12 =0x5d
568 00:56:19.344560 Write Rank1 MR1 =0x56
569 00:56:19.344635 Write Rank1 MR2 =0x1a
570 00:56:19.344709 Write Rank1 MR11 =0x0
571 00:56:19.344787 Write Rank1 MR22 =0x38
572 00:56:19.344862 Write Rank1 MR14 =0x5d
573 00:56:19.344939 Write Rank1 MR3 =0x30
574 00:56:19.345017 Write Rank1 MR13 =0x58
575 00:56:19.345092 Write Rank1 MR12 =0x5d
576 00:56:19.345167 Write Rank1 MR1 =0x56
577 00:56:19.345244 Write Rank1 MR2 =0x2d
578 00:56:19.345319 Write Rank1 MR11 =0x23
579 00:56:19.345393 Write Rank1 MR22 =0x34
580 00:56:19.345468 Write Rank1 MR14 =0x10
581 00:56:19.345545 Write Rank1 MR3 =0x30
582 00:56:19.345619 Write Rank1 MR13 =0xd8
583 00:56:19.345694 match AC timing 3
584 00:56:19.345775 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
585 00:56:19.345851 [MiockJmeterHQA]
586 00:56:19.345927 vSetVcoreByFreq with vcore:762500, freq=1600
587 00:56:19.346005
588 00:56:19.346080 MIOCK jitter meter ch=0
589 00:56:19.346155
590 00:56:19.346258 1T = (101-18) = 83 dly cells
591 00:56:19.346352 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 753/100 ps
592 00:56:19.346429 vSetVcoreByFreq with vcore:725000, freq=1200
593 00:56:19.346507
594 00:56:19.346582 MIOCK jitter meter ch=0
595 00:56:19.346656
596 00:56:19.346733 1T = (96-17) = 79 dly cells
597 00:56:19.346812 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 791/100 ps
598 00:56:19.346888 vSetVcoreByFreq with vcore:725000, freq=800
599 00:56:19.346970
600 00:56:19.347058 MIOCK jitter meter ch=0
601 00:56:19.347144
602 00:56:19.347222 1T = (96-17) = 79 dly cells
603 00:56:19.347301 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 791/100 ps
604 00:56:19.347386 vSetVcoreByFreq with vcore:762500, freq=1600
605 00:56:19.347465 vSetVcoreByFreq with vcore:762500, freq=1600
606 00:56:19.347540
607 00:56:19.347614 K DRVP
608 00:56:19.347691 1. OCD DRVP=0 CALOUT=0
609 00:56:19.347770 1. OCD DRVP=1 CALOUT=0
610 00:56:19.347856 1. OCD DRVP=2 CALOUT=0
611 00:56:19.347936 1. OCD DRVP=3 CALOUT=0
612 00:56:19.348015 1. OCD DRVP=4 CALOUT=0
613 00:56:19.348092 1. OCD DRVP=5 CALOUT=0
614 00:56:19.348169 1. OCD DRVP=6 CALOUT=0
615 00:56:19.348249 1. OCD DRVP=7 CALOUT=0
616 00:56:19.348326 1. OCD DRVP=8 CALOUT=1
617 00:56:19.348403
618 00:56:19.348481 1. OCD DRVP calibration OK! DRVP=8
619 00:56:19.348559
620 00:56:19.348633
621 00:56:19.348711
622 00:56:19.348786 K ODTN
623 00:56:19.348861 3. OCD ODTN=0 ,CALOUT=1
624 00:56:19.348944 3. OCD ODTN=1 ,CALOUT=1
625 00:56:19.349033 3. OCD ODTN=2 ,CALOUT=1
626 00:56:19.349148 3. OCD ODTN=3 ,CALOUT=1
627 00:56:19.349229 3. OCD ODTN=4 ,CALOUT=1
628 00:56:19.349306 3. OCD ODTN=5 ,CALOUT=1
629 00:56:19.349389 3. OCD ODTN=6 ,CALOUT=1
630 00:56:19.349448 3. OCD ODTN=7 ,CALOUT=0
631 00:56:19.349497
632 00:56:19.349545 3. OCD ODTN calibration OK! ODTN=7
633 00:56:19.349594
634 00:56:19.349642 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
635 00:56:19.349695 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
636 00:56:19.349744 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
637 00:56:19.349791
638 00:56:19.349838 K DRVP
639 00:56:19.349885 1. OCD DRVP=0 CALOUT=0
640 00:56:19.349939 1. OCD DRVP=1 CALOUT=0
641 00:56:19.349987 1. OCD DRVP=2 CALOUT=0
642 00:56:19.350035 1. OCD DRVP=3 CALOUT=0
643 00:56:19.350083 1. OCD DRVP=4 CALOUT=0
644 00:56:19.350132 1. OCD DRVP=5 CALOUT=0
645 00:56:19.350249 1. OCD DRVP=6 CALOUT=0
646 00:56:19.350318 1. OCD DRVP=7 CALOUT=0
647 00:56:19.350368 1. OCD DRVP=8 CALOUT=0
648 00:56:19.350423 1. OCD DRVP=9 CALOUT=0
649 00:56:19.350482 1. OCD DRVP=10 CALOUT=1
650 00:56:19.350531
651 00:56:19.350769 1. OCD DRVP calibration OK! DRVP=10
652 00:56:19.350896
653 00:56:19.351025
654 00:56:19.351133
655 00:56:19.351242 K ODTN
656 00:56:19.351350 3. OCD ODTN=0 ,CALOUT=1
657 00:56:19.351434 3. OCD ODTN=1 ,CALOUT=1
658 00:56:19.351486 3. OCD ODTN=2 ,CALOUT=1
659 00:56:19.351536 3. OCD ODTN=3 ,CALOUT=1
660 00:56:19.351584 3. OCD ODTN=4 ,CALOUT=1
661 00:56:19.351640 3. OCD ODTN=5 ,CALOUT=1
662 00:56:19.351689 3. OCD ODTN=6 ,CALOUT=1
663 00:56:19.351737 3. OCD ODTN=7 ,CALOUT=1
664 00:56:19.351785 3. OCD ODTN=8 ,CALOUT=1
665 00:56:19.351833 3. OCD ODTN=9 ,CALOUT=1
666 00:56:19.351887 3. OCD ODTN=10 ,CALOUT=1
667 00:56:19.351936 3. OCD ODTN=11 ,CALOUT=1
668 00:56:19.351985 3. OCD ODTN=12 ,CALOUT=1
669 00:56:19.352034 3. OCD ODTN=13 ,CALOUT=1
670 00:56:19.352086 3. OCD ODTN=14 ,CALOUT=1
671 00:56:19.352136 3. OCD ODTN=15 ,CALOUT=0
672 00:56:19.352184
673 00:56:19.352232 3. OCD ODTN calibration OK! ODTN=15
674 00:56:19.352281
675 00:56:19.352332 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=15
676 00:56:19.352382 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15
677 00:56:19.352430 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15 (After Adjust)
678 00:56:19.352477
679 00:56:19.352524 [DramcInit]
680 00:56:19.352572 AutoRefreshCKEOff AutoREF OFF
681 00:56:19.352623 DDRPhyPLLSetting-CKEOFF
682 00:56:19.352670 DDRPhyPLLSetting-CKEON
683 00:56:19.352717
684 00:56:19.352765 Enable WDQS
685 00:56:19.352812 ==
686 00:56:19.352867 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
687 00:56:19.352915 fsp= 1, odt_onoff= 1, Byte mode= 0
688 00:56:19.352967 ==
689 00:56:19.353024 [Duty_Offset_Calibration]
690 00:56:19.353086
691 00:56:19.353162 ===========================
692 00:56:19.353238 B0:1 B1:0 CA:0
693 00:56:19.353315 ==
694 00:56:19.353392 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
695 00:56:19.353468 fsp= 1, odt_onoff= 1, Byte mode= 0
696 00:56:19.353545 ==
697 00:56:19.353622 [Duty_Offset_Calibration]
698 00:56:19.353697
699 00:56:19.353771 ===========================
700 00:56:19.353859 B0:1 B1:0 CA:-1
701 00:56:19.353934 [ModeRegInit_LP4] CH0 RK0
702 00:56:19.354010 Write Rank0 MR13 =0x18
703 00:56:19.354088 Write Rank0 MR12 =0x5d
704 00:56:19.354163 Write Rank0 MR1 =0x56
705 00:56:19.354289 Write Rank0 MR2 =0x1a
706 00:56:19.354366 Write Rank0 MR11 =0x0
707 00:56:19.354440 Write Rank0 MR22 =0x38
708 00:56:19.354515 Write Rank0 MR14 =0x5d
709 00:56:19.354593 Write Rank0 MR3 =0x30
710 00:56:19.354668 Write Rank0 MR13 =0x58
711 00:56:19.354743 Write Rank0 MR12 =0x5d
712 00:56:19.354807 Write Rank0 MR1 =0x56
713 00:56:19.354856 Write Rank0 MR2 =0x2d
714 00:56:19.354904 Write Rank0 MR11 =0x23
715 00:56:19.354952 Write Rank0 MR22 =0x34
716 00:56:19.355010 Write Rank0 MR14 =0x10
717 00:56:19.355062 Write Rank0 MR3 =0x30
718 00:56:19.355110 Write Rank0 MR13 =0xd8
719 00:56:19.355157 [ModeRegInit_LP4] CH0 RK1
720 00:56:19.355204 Write Rank1 MR13 =0x18
721 00:56:19.355251 Write Rank1 MR12 =0x5d
722 00:56:19.355328 Write Rank1 MR1 =0x56
723 00:56:19.355413 Write Rank1 MR2 =0x1a
724 00:56:19.355488 Write Rank1 MR11 =0x0
725 00:56:19.355566 Write Rank1 MR22 =0x38
726 00:56:19.355642 Write Rank1 MR14 =0x5d
727 00:56:19.355716 Write Rank1 MR3 =0x30
728 00:56:19.355797 Write Rank1 MR13 =0x58
729 00:56:19.355849 Write Rank1 MR12 =0x5d
730 00:56:19.355897 Write Rank1 MR1 =0x56
731 00:56:19.355944 Write Rank1 MR2 =0x2d
732 00:56:19.355993 Write Rank1 MR11 =0x23
733 00:56:19.356043 Write Rank1 MR22 =0x34
734 00:56:19.356089 Write Rank1 MR14 =0x10
735 00:56:19.356136 Write Rank1 MR3 =0x30
736 00:56:19.356183 Write Rank1 MR13 =0xd8
737 00:56:19.356230 [ModeRegInit_LP4] CH1 RK0
738 00:56:19.356307 Write Rank0 MR13 =0x18
739 00:56:19.356382 Write Rank0 MR12 =0x5d
740 00:56:19.356457 Write Rank0 MR1 =0x56
741 00:56:19.356535 Write Rank0 MR2 =0x1a
742 00:56:19.356607 Write Rank0 MR11 =0x0
743 00:56:19.356657 Write Rank0 MR22 =0x38
744 00:56:19.356705 Write Rank0 MR14 =0x5d
745 00:56:19.356760 Write Rank0 MR3 =0x30
746 00:56:19.356808 Write Rank0 MR13 =0x58
747 00:56:19.356855 Write Rank0 MR12 =0x5d
748 00:56:19.356902 Write Rank0 MR1 =0x56
749 00:56:19.356949 Write Rank0 MR2 =0x2d
750 00:56:19.357014 Write Rank0 MR11 =0x23
751 00:56:19.357070 Write Rank0 MR22 =0x34
752 00:56:19.357129 Write Rank0 MR14 =0x10
753 00:56:19.357194 Write Rank0 MR3 =0x30
754 00:56:19.357275 Write Rank0 MR13 =0xd8
755 00:56:19.357326 [ModeRegInit_LP4] CH1 RK1
756 00:56:19.357374 Write Rank1 MR13 =0x18
757 00:56:19.357422 Write Rank1 MR12 =0x5d
758 00:56:19.357473 Write Rank1 MR1 =0x56
759 00:56:19.357523 Write Rank1 MR2 =0x1a
760 00:56:19.357580 Write Rank1 MR11 =0x0
761 00:56:19.357638 Write Rank1 MR22 =0x38
762 00:56:19.357687 Write Rank1 MR14 =0x5d
763 00:56:19.357739 Write Rank1 MR3 =0x30
764 00:56:19.357788 Write Rank1 MR13 =0x58
765 00:56:19.357835 Write Rank1 MR12 =0x5d
766 00:56:19.357882 Write Rank1 MR1 =0x56
767 00:56:19.357930 Write Rank1 MR2 =0x2d
768 00:56:19.357983 Write Rank1 MR11 =0x23
769 00:56:19.358059 Write Rank1 MR22 =0x34
770 00:56:19.358134 Write Rank1 MR14 =0x10
771 00:56:19.358215 Write Rank1 MR3 =0x30
772 00:56:19.358310 Write Rank1 MR13 =0xd8
773 00:56:19.358358 match AC timing 3
774 00:56:19.358406 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
775 00:56:19.358457 DramC Write-DBI off
776 00:56:19.358508 DramC Read-DBI off
777 00:56:19.358555 Write Rank0 MR13 =0x59
778 00:56:19.358601 ==
779 00:56:19.358649 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
780 00:56:19.358697 fsp= 1, odt_onoff= 1, Byte mode= 0
781 00:56:19.358751 ==
782 00:56:19.358799 === u2Vref_new: 0x56 --> 0x2d
783 00:56:19.358846 === u2Vref_new: 0x58 --> 0x38
784 00:56:19.358894 === u2Vref_new: 0x5a --> 0x39
785 00:56:19.358941 === u2Vref_new: 0x5c --> 0x3c
786 00:56:19.358994 === u2Vref_new: 0x5e --> 0x3d
787 00:56:19.359042 === u2Vref_new: 0x60 --> 0xa0
788 00:56:19.359089 [CA 0] Center 33 (4~63) winsize 60
789 00:56:19.359137 [CA 1] Center 34 (6~63) winsize 58
790 00:56:19.359197 [CA 2] Center 27 (-1~56) winsize 58
791 00:56:19.359275 [CA 3] Center 23 (-4~51) winsize 56
792 00:56:19.359350 [CA 4] Center 24 (-3~51) winsize 55
793 00:56:19.359426 [CA 5] Center 28 (-1~58) winsize 60
794 00:56:19.359515
795 00:56:19.359592 [CATrainingPosCal] consider 1 rank data
796 00:56:19.359667 u2DelayCellTimex100 = 753/100 ps
797 00:56:19.359746 CA0 delay=33 (4~63),Diff = 10 PI (12 cell)
798 00:56:19.359822 CA1 delay=34 (6~63),Diff = 11 PI (14 cell)
799 00:56:19.359898 CA2 delay=27 (-1~56),Diff = 4 PI (5 cell)
800 00:56:19.359977 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
801 00:56:19.360053 CA4 delay=24 (-3~51),Diff = 1 PI (1 cell)
802 00:56:19.360128 CA5 delay=28 (-1~58),Diff = 5 PI (6 cell)
803 00:56:19.360206
804 00:56:19.360282 CA PerBit enable=1, Macro0, CA PI delay=23
805 00:56:19.360357 === u2Vref_new: 0x56 --> 0x2d
806 00:56:19.360434
807 00:56:19.360520 Vref(ca) range 1: 22
808 00:56:19.360595
809 00:56:19.360671 CS Dly= 10 (41-0-32)
810 00:56:19.360747 Write Rank0 MR13 =0xd8
811 00:56:19.360822 Write Rank0 MR13 =0xd8
812 00:56:19.360897 Write Rank0 MR12 =0x56
813 00:56:19.360975 Write Rank1 MR13 =0x59
814 00:56:19.361049 ==
815 00:56:19.361330 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
816 00:56:19.361444 fsp= 1, odt_onoff= 1, Byte mode= 0
817 00:56:19.361554 ==
818 00:56:19.361662 === u2Vref_new: 0x56 --> 0x2d
819 00:56:19.361771 === u2Vref_new: 0x58 --> 0x38
820 00:56:19.361882 === u2Vref_new: 0x5a --> 0x39
821 00:56:19.361982 === u2Vref_new: 0x5c --> 0x3c
822 00:56:19.362060 === u2Vref_new: 0x5e --> 0x3d
823 00:56:19.362138 === u2Vref_new: 0x60 --> 0xa0
824 00:56:19.362223 [CA 0] Center 33 (4~63) winsize 60
825 00:56:19.362276 [CA 1] Center 34 (5~63) winsize 59
826 00:56:19.362324 [CA 2] Center 28 (0~56) winsize 57
827 00:56:19.362373 [CA 3] Center 23 (-4~51) winsize 56
828 00:56:19.362426 [CA 4] Center 24 (-3~52) winsize 56
829 00:56:19.362473 [CA 5] Center 29 (0~58) winsize 59
830 00:56:19.362521
831 00:56:19.362568 [CATrainingPosCal] consider 2 rank data
832 00:56:19.362616 u2DelayCellTimex100 = 753/100 ps
833 00:56:19.362669 CA0 delay=33 (4~63),Diff = 10 PI (12 cell)
834 00:56:19.362717 CA1 delay=34 (6~63),Diff = 11 PI (14 cell)
835 00:56:19.362766 CA2 delay=28 (0~56),Diff = 5 PI (6 cell)
836 00:56:19.362813 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
837 00:56:19.362861 CA4 delay=24 (-3~51),Diff = 1 PI (1 cell)
838 00:56:19.362914 CA5 delay=29 (0~58),Diff = 6 PI (7 cell)
839 00:56:19.362961
840 00:56:19.363008 CA PerBit enable=1, Macro0, CA PI delay=23
841 00:56:19.363055 === u2Vref_new: 0x56 --> 0x2d
842 00:56:19.363102
843 00:56:19.363188 Vref(ca) range 1: 22
844 00:56:19.363264
845 00:56:19.363338 CS Dly= 7 (38-0-32)
846 00:56:19.363416 Write Rank1 MR13 =0xd8
847 00:56:19.363491 Write Rank1 MR13 =0xd8
848 00:56:19.363566 Write Rank1 MR12 =0x56
849 00:56:19.363631 [RankSwap] Rank num 2, (Multi 1), Rank 0
850 00:56:19.363691 Write Rank0 MR2 =0xad
851 00:56:19.363740 [Write Leveling]
852 00:56:19.363788 delay byte0 byte1 byte2 byte3
853 00:56:19.363836
854 00:56:19.363889 10 0 0
855 00:56:19.363939 11 0 0
856 00:56:19.363987 12 0 0
857 00:56:19.364035 13 0 0
858 00:56:19.364083 14 0 0
859 00:56:19.364161 15 0 0
860 00:56:19.364238 16 0 0
861 00:56:19.364315 17 0 0
862 00:56:19.364404 18 0 0
863 00:56:19.364482 19 0 0
864 00:56:19.364559 20 0 0
865 00:56:19.364639 21 0 0
866 00:56:19.364725 22 0 0
867 00:56:19.364802 23 0 0
868 00:56:19.364882 24 0 0
869 00:56:19.364960 25 0 0
870 00:56:19.365037 26 0 0
871 00:56:19.365117 27 0 ff
872 00:56:19.365194 28 0 ff
873 00:56:19.365271 29 0 ff
874 00:56:19.365351 30 0 ff
875 00:56:19.365428 31 0 ff
876 00:56:19.365506 32 0 ff
877 00:56:19.365585 33 ff ff
878 00:56:19.365663 34 ff ff
879 00:56:19.365740 35 ff ff
880 00:56:19.365819 36 ff ff
881 00:56:19.365897 37 ff ff
882 00:56:19.365974 38 ff ff
883 00:56:19.366051 39 ff ff
884 00:56:19.366132 pass bytecount = 0xff (0xff: all bytes pass)
885 00:56:19.366208
886 00:56:19.366289 DQS0 dly: 33
887 00:56:19.366347 DQS1 dly: 27
888 00:56:19.366395 Write Rank0 MR2 =0x2d
889 00:56:19.366443 [RankSwap] Rank num 2, (Multi 1), Rank 0
890 00:56:19.366491 Write Rank0 MR1 =0xd6
891 00:56:19.366540 [Gating]
892 00:56:19.366592 ==
893 00:56:19.366640 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
894 00:56:19.366688 fsp= 1, odt_onoff= 1, Byte mode= 0
895 00:56:19.366736 ==
896 00:56:19.366784 3 1 0 |3534 1c1b |(11 11)(11 11) |(1 1)(1 1)| 0
897 00:56:19.366839 3 1 4 |3534 1615 |(11 11)(11 11) |(0 0)(1 1)| 0
898 00:56:19.366889 3 1 8 |3534 f0e |(11 11)(11 11) |(0 0)(1 0)| 0
899 00:56:19.366948 3 1 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
900 00:56:19.367006 3 1 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
901 00:56:19.367060 3 1 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
902 00:56:19.367110 3 1 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
903 00:56:19.367190 3 1 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
904 00:56:19.367238 3 2 0 |3d3d c0b |(11 11)(11 11) |(1 1)(1 1)| 0
905 00:56:19.367290 3 2 4 |3d3d 505 |(11 11)(11 11) |(1 1)(1 1)| 0
906 00:56:19.367341 3 2 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
907 00:56:19.367389 [Byte 1] Lead/lag Transition tap number (1)
908 00:56:19.367437 3 2 12 |3d3d 707 |(11 11)(11 11) |(1 1)(0 0)| 0
909 00:56:19.367485 3 2 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
910 00:56:19.367536 3 2 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
911 00:56:19.367586 3 2 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
912 00:56:19.367635 3 2 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
913 00:56:19.367683 3 3 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
914 00:56:19.367730 3 3 4 |3d3d 0 |(11 11)(11 11) |(1 1)(1 1)| 0
915 00:56:19.367783 3 3 8 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
916 00:56:19.367833 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
917 00:56:19.367881 [Byte 0] Lead/lag Transition tap number (1)
918 00:56:19.367928 [Byte 1] Lead/lag falling Transition (3, 3, 12)
919 00:56:19.367976 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
920 00:56:19.368027 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
921 00:56:19.368078 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
922 00:56:19.368136 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
923 00:56:19.368185 3 4 0 |2e2d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
924 00:56:19.368234 3 4 4 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
925 00:56:19.368290 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
926 00:56:19.368368 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 00:56:19.368446 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 00:56:19.368527 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 00:56:19.368605 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 00:56:19.368683 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 00:56:19.368762 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 00:56:19.368841 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 00:56:19.368919 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 00:56:19.368998 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
935 00:56:19.369078 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
936 00:56:19.369156 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
937 00:56:19.369234 [Byte 0] Lead/lag falling Transition (3, 5, 20)
938 00:56:19.369313 [Byte 1] Lead/lag falling Transition (3, 5, 20)
939 00:56:19.369583 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
940 00:56:19.369642 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
941 00:56:19.369693 [Byte 0] Lead/lag Transition tap number (3)
942 00:56:19.369746 [Byte 1] Lead/lag Transition tap number (3)
943 00:56:19.369795 3 6 0 |404 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
944 00:56:19.369845 3 6 4 |4646 404 |(0 0)(11 11) |(0 0)(0 0)| 0
945 00:56:19.369894 [Byte 0]First pass (3, 6, 4)
946 00:56:19.369942 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
947 00:56:19.369994 [Byte 1]First pass (3, 6, 8)
948 00:56:19.370043 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 00:56:19.370092 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 00:56:19.370142 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 00:56:19.370191 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 00:56:19.370273 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 00:56:19.370337 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
954 00:56:19.370385 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
955 00:56:19.370433 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
956 00:56:19.370482 All bytes gating window > 1UI, Early break!
957 00:56:19.370537
958 00:56:19.370595 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 26)
959 00:56:19.370644
960 00:56:19.370690 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 26)
961 00:56:19.370742
962 00:56:19.370790
963 00:56:19.370837
964 00:56:19.370883 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
965 00:56:19.370930
966 00:56:19.370976 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
967 00:56:19.371029
968 00:56:19.371087
969 00:56:19.371166 Write Rank0 MR1 =0x56
970 00:56:19.371259
971 00:56:19.371308 best RODT dly(2T, 0.5T) = (2, 2)
972 00:56:19.371355
973 00:56:19.371403 best RODT dly(2T, 0.5T) = (2, 2)
974 00:56:19.371449 ==
975 00:56:19.371497 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
976 00:56:19.371550 fsp= 1, odt_onoff= 1, Byte mode= 0
977 00:56:19.371599 ==
978 00:56:19.371646 Start DQ dly to find pass range UseTestEngine =0
979 00:56:19.371694 x-axis: bit #, y-axis: DQ dly (-127~63)
980 00:56:19.371745 RX Vref Scan = 0
981 00:56:19.371794 -26, [0] xxxxxxxx xxxxxxxx [MSB]
982 00:56:19.371843 -25, [0] xxxxxxxx xxxxxxxx [MSB]
983 00:56:19.371892 -24, [0] xxxxxxxx xxxxxxxx [MSB]
984 00:56:19.371940 -23, [0] xxxxxxxx xxxxxxxx [MSB]
985 00:56:19.371990 -22, [0] xxxxxxxx xxxxxxxx [MSB]
986 00:56:19.372041 -21, [0] xxxxxxxx xxxxxxxx [MSB]
987 00:56:19.372089 -20, [0] xxxxxxxx xxxxxxxx [MSB]
988 00:56:19.372137 -19, [0] xxxxxxxx xxxxxxxx [MSB]
989 00:56:19.372186 -18, [0] xxxxxxxx xxxxxxxx [MSB]
990 00:56:19.372238 -17, [0] xxxxxxxx xxxxxxxx [MSB]
991 00:56:19.372316 -16, [0] xxxxxxxx xxxxxxxx [MSB]
992 00:56:19.372393 -15, [0] xxxxxxxx xxxxxxxx [MSB]
993 00:56:19.372470 -14, [0] xxxxxxxx xxxxxxxx [MSB]
994 00:56:19.372551 -13, [0] xxxxxxxx xxxxxxxx [MSB]
995 00:56:19.372628 -12, [0] xxxxxxxx xxxxxxxx [MSB]
996 00:56:19.372705 -11, [0] xxxxxxxx xxxxxxxx [MSB]
997 00:56:19.372785 -10, [0] xxxxxxxx xxxxxxxx [MSB]
998 00:56:19.372862 -9, [0] xxxxxxxx xxxxxxxx [MSB]
999 00:56:19.372939 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1000 00:56:19.373019 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1001 00:56:19.373096 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1002 00:56:19.373172 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1003 00:56:19.373253 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1004 00:56:19.373331 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1005 00:56:19.373408 -2, [0] xxxoxxxx xxxxxxxx [MSB]
1006 00:56:19.373489 -1, [0] xxxoxoxx xxxxxxxx [MSB]
1007 00:56:19.373566 0, [0] xxxoxooo xxxxxoxx [MSB]
1008 00:56:19.373643 1, [0] xxxoxooo xxxxxoxx [MSB]
1009 00:56:19.373725 2, [0] xxxoxooo ooxoooxx [MSB]
1010 00:56:19.373802 3, [0] xxxoxooo ooxooooo [MSB]
1011 00:56:19.373880 4, [0] xxxoxooo ooxooooo [MSB]
1012 00:56:19.374000 5, [0] xxxooooo oooooooo [MSB]
1013 00:56:19.374078 6, [0] xooooooo oooooooo [MSB]
1014 00:56:19.374155 7, [0] xooooooo oooooooo [MSB]
1015 00:56:19.374242 31, [0] oooxoooo oooooooo [MSB]
1016 00:56:19.374321 32, [0] oooxoooo oooooooo [MSB]
1017 00:56:19.374409 33, [0] oooxoxxo oooooooo [MSB]
1018 00:56:19.374566 34, [0] oooxoxxo ooooooxo [MSB]
1019 00:56:19.374644 35, [0] oooxoxxo xooxooxo [MSB]
1020 00:56:19.374725 36, [0] oooxoxxx xooxooxo [MSB]
1021 00:56:19.374803 37, [0] oooxoxxx xooxoxxo [MSB]
1022 00:56:19.374883 38, [0] oooxoxxx xooxxxxo [MSB]
1023 00:56:19.374964 39, [0] oooxxxxx xxoxxxxx [MSB]
1024 00:56:19.375042 40, [0] oxoxxxxx xxoxxxxx [MSB]
1025 00:56:19.375119 41, [0] oxxxxxxx xxxxxxxx [MSB]
1026 00:56:19.375198 42, [0] xxxxxxxx xxxxxxxx [MSB]
1027 00:56:19.375276 iDelay=42, Bit 0, Center 24 (8 ~ 41) 34
1028 00:56:19.375352 iDelay=42, Bit 1, Center 22 (6 ~ 39) 34
1029 00:56:19.375427 iDelay=42, Bit 2, Center 23 (6 ~ 40) 35
1030 00:56:19.375505 iDelay=42, Bit 3, Center 14 (-2 ~ 30) 33
1031 00:56:19.375581 iDelay=42, Bit 4, Center 21 (5 ~ 38) 34
1032 00:56:19.375657 iDelay=42, Bit 5, Center 15 (-1 ~ 32) 34
1033 00:56:19.375736 iDelay=42, Bit 6, Center 16 (0 ~ 32) 33
1034 00:56:19.375812 iDelay=42, Bit 7, Center 17 (0 ~ 35) 36
1035 00:56:19.375887 iDelay=42, Bit 8, Center 18 (2 ~ 34) 33
1036 00:56:19.375965 iDelay=42, Bit 9, Center 20 (2 ~ 38) 37
1037 00:56:19.376041 iDelay=42, Bit 10, Center 22 (5 ~ 40) 36
1038 00:56:19.376117 iDelay=42, Bit 11, Center 18 (2 ~ 34) 33
1039 00:56:19.376195 iDelay=42, Bit 12, Center 19 (2 ~ 37) 36
1040 00:56:19.376270 iDelay=42, Bit 13, Center 18 (0 ~ 36) 37
1041 00:56:19.376345 iDelay=42, Bit 14, Center 18 (3 ~ 33) 31
1042 00:56:19.376422 iDelay=42, Bit 15, Center 20 (3 ~ 38) 36
1043 00:56:19.376498 ==
1044 00:56:19.376574 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1045 00:56:19.376650 fsp= 1, odt_onoff= 1, Byte mode= 0
1046 00:56:19.376729 ==
1047 00:56:19.376804 DQS Delay:
1048 00:56:19.376879 DQS0 = 0, DQS1 = 0
1049 00:56:19.376957 DQM Delay:
1050 00:56:19.377032 DQM0 = 19, DQM1 = 19
1051 00:56:19.377106 DQ Delay:
1052 00:56:19.377185 DQ0 =24, DQ1 =22, DQ2 =23, DQ3 =14
1053 00:56:19.377261 DQ4 =21, DQ5 =15, DQ6 =16, DQ7 =17
1054 00:56:19.377336 DQ8 =18, DQ9 =20, DQ10 =22, DQ11 =18
1055 00:56:19.377413 DQ12 =19, DQ13 =18, DQ14 =18, DQ15 =20
1056 00:56:19.377499
1057 00:56:19.377573
1058 00:56:19.377650 DramC Write-DBI off
1059 00:56:19.377734 ==
1060 00:56:19.377811 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1061 00:56:19.377887 fsp= 1, odt_onoff= 1, Byte mode= 0
1062 00:56:19.377965 ==
1063 00:56:19.378040 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1064 00:56:19.378115
1065 00:56:19.378194 Begin, DQ Scan Range 923~1179
1066 00:56:19.378277
1067 00:56:19.378352
1068 00:56:19.378417 TX Vref Scan disable
1069 00:56:19.378466 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1070 00:56:19.378749 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1071 00:56:19.378878 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1072 00:56:19.378990 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1073 00:56:19.379107 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1074 00:56:19.379237 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1075 00:56:19.379348 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1076 00:56:19.379458 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1077 00:56:19.379570 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1078 00:56:19.379681 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1079 00:56:19.379791 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1080 00:56:19.379901 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1081 00:56:19.380012 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1082 00:56:19.380075 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1083 00:56:19.380128 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1084 00:56:19.380180 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1085 00:56:19.380228 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1086 00:56:19.380277 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1087 00:56:19.380327 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1088 00:56:19.380380 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1089 00:56:19.380430 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1090 00:56:19.380479 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1091 00:56:19.380528 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1092 00:56:19.380576 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1093 00:56:19.380629 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1094 00:56:19.380679 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1095 00:56:19.380728 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1096 00:56:19.380776 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1097 00:56:19.380835 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1098 00:56:19.380890 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1099 00:56:19.380939 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1100 00:56:19.380989 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1101 00:56:19.381039 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1102 00:56:19.381088 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1103 00:56:19.381143 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1104 00:56:19.381193 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1105 00:56:19.381241 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1106 00:56:19.381290 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1107 00:56:19.381339 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1108 00:56:19.381393 962 |3 6 2|[0] xxxxxxxx oxxxxxxx [MSB]
1109 00:56:19.381441 963 |3 6 3|[0] xxxxxxxx oxxoxxxx [MSB]
1110 00:56:19.381498 964 |3 6 4|[0] xxxxxxxx oxxoxoox [MSB]
1111 00:56:19.381548 965 |3 6 5|[0] xxxxxxxx ooxoooox [MSB]
1112 00:56:19.381600 966 |3 6 6|[0] xxxxxxxx ooxoooox [MSB]
1113 00:56:19.381651 967 |3 6 7|[0] xxxxxxxx ooxooooo [MSB]
1114 00:56:19.381699 968 |3 6 8|[0] xxxxxxxx oooooooo [MSB]
1115 00:56:19.381748 969 |3 6 9|[0] xxxxxxxx oooooooo [MSB]
1116 00:56:19.381796 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
1117 00:56:19.381849 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
1118 00:56:19.381898 972 |3 6 12|[0] xxxoxoox oooooooo [MSB]
1119 00:56:19.381947 973 |3 6 13|[0] xxxoxooo oooooooo [MSB]
1120 00:56:19.381995 974 |3 6 14|[0] xxxoxooo oooooooo [MSB]
1121 00:56:19.382044 975 |3 6 15|[0] xxoooooo oooooooo [MSB]
1122 00:56:19.382099 988 |3 6 28|[0] oooooooo xooooooo [MSB]
1123 00:56:19.382178 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1124 00:56:19.382297 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1125 00:56:19.382365 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1126 00:56:19.382415 992 |3 6 32|[0] oooxoxoo xxxxxxxx [MSB]
1127 00:56:19.382464 993 |3 6 33|[0] oooxoxoo xxxxxxxx [MSB]
1128 00:56:19.382523 994 |3 6 34|[0] oooxoxxo xxxxxxxx [MSB]
1129 00:56:19.382577 995 |3 6 35|[0] xxxxxxxx xxxxxxxx [MSB]
1130 00:56:19.382627 Byte0, DQ PI dly=983, DQM PI dly= 983
1131 00:56:19.382676 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
1132 00:56:19.382724
1133 00:56:19.382772 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
1134 00:56:19.382824
1135 00:56:19.382873 Byte1, DQ PI dly=976, DQM PI dly= 976
1136 00:56:19.382922 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
1137 00:56:19.382970
1138 00:56:19.383017 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
1139 00:56:19.383067
1140 00:56:19.383116 ==
1141 00:56:19.383163 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1142 00:56:19.383211 fsp= 1, odt_onoff= 1, Byte mode= 0
1143 00:56:19.383259 ==
1144 00:56:19.383309 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1145 00:56:19.383358
1146 00:56:19.383405 Begin, DQ Scan Range 952~1016
1147 00:56:19.383452 Write Rank0 MR14 =0x0
1148 00:56:19.383499
1149 00:56:19.383548 CH=0, VrefRange= 0, VrefLevel = 0
1150 00:56:19.383597 TX Bit0 (977~995) 19 986, Bit8 (966~983) 18 974,
1151 00:56:19.383654 TX Bit1 (977~992) 16 984, Bit9 (967~984) 18 975,
1152 00:56:19.383704 TX Bit2 (977~994) 18 985, Bit10 (970~989) 20 979,
1153 00:56:19.383752 TX Bit3 (970~988) 19 979, Bit11 (966~983) 18 974,
1154 00:56:19.383804 TX Bit4 (976~994) 19 985, Bit12 (967~985) 19 976,
1155 00:56:19.383853 TX Bit5 (974~989) 16 981, Bit13 (967~983) 17 975,
1156 00:56:19.383901 TX Bit6 (975~990) 16 982, Bit14 (967~983) 17 975,
1157 00:56:19.383949 TX Bit7 (975~992) 18 983, Bit15 (968~987) 20 977,
1158 00:56:19.383996
1159 00:56:19.384046 Write Rank0 MR14 =0x2
1160 00:56:19.384095
1161 00:56:19.384142 CH=0, VrefRange= 0, VrefLevel = 2
1162 00:56:19.384190 TX Bit0 (977~994) 18 985, Bit8 (966~983) 18 974,
1163 00:56:19.384238 TX Bit1 (977~993) 17 985, Bit9 (967~985) 19 976,
1164 00:56:19.384291 TX Bit2 (977~994) 18 985, Bit10 (969~989) 21 979,
1165 00:56:19.384369 TX Bit3 (970~989) 20 979, Bit11 (966~984) 19 975,
1166 00:56:19.384445 TX Bit4 (976~994) 19 985, Bit12 (967~986) 20 976,
1167 00:56:19.384521 TX Bit5 (974~989) 16 981, Bit13 (966~983) 18 974,
1168 00:56:19.384600 TX Bit6 (974~990) 17 982, Bit14 (967~984) 18 975,
1169 00:56:19.384676 TX Bit7 (975~992) 18 983, Bit15 (968~988) 21 978,
1170 00:56:19.384751
1171 00:56:19.384838 Write Rank0 MR14 =0x4
1172 00:56:19.384914
1173 00:56:19.384990 CH=0, VrefRange= 0, VrefLevel = 4
1174 00:56:19.385069 TX Bit0 (977~995) 19 986, Bit8 (964~983) 20 973,
1175 00:56:19.385145 TX Bit1 (977~993) 17 985, Bit9 (966~986) 21 976,
1176 00:56:19.385416 TX Bit2 (976~994) 19 985, Bit10 (969~990) 22 979,
1177 00:56:19.385529 TX Bit3 (970~989) 20 979, Bit11 (966~985) 20 975,
1178 00:56:19.385640 TX Bit4 (976~996) 21 986, Bit12 (967~986) 20 976,
1179 00:56:19.385749 TX Bit5 (974~990) 17 982, Bit13 (966~984) 19 975,
1180 00:56:19.385858 TX Bit6 (974~990) 17 982, Bit14 (967~985) 19 976,
1181 00:56:19.385966 TX Bit7 (975~992) 18 983, Bit15 (968~988) 21 978,
1182 00:56:19.386059
1183 00:56:19.386135 Write Rank0 MR14 =0x6
1184 00:56:19.386215
1185 00:56:19.386307 CH=0, VrefRange= 0, VrefLevel = 6
1186 00:56:19.386356 TX Bit0 (977~996) 20 986, Bit8 (964~984) 21 974,
1187 00:56:19.386415 TX Bit1 (977~994) 18 985, Bit9 (966~986) 21 976,
1188 00:56:19.386465 TX Bit2 (976~995) 20 985, Bit10 (969~989) 21 979,
1189 00:56:19.386517 TX Bit3 (969~990) 22 979, Bit11 (965~986) 22 975,
1190 00:56:19.386567 TX Bit4 (976~996) 21 986, Bit12 (966~987) 22 976,
1191 00:56:19.386614 TX Bit5 (973~990) 18 981, Bit13 (966~985) 20 975,
1192 00:56:19.386662 TX Bit6 (973~991) 19 982, Bit14 (967~985) 19 976,
1193 00:56:19.386710 TX Bit7 (974~993) 20 983, Bit15 (968~988) 21 978,
1194 00:56:19.386759
1195 00:56:19.386808 Write Rank0 MR14 =0x8
1196 00:56:19.386856
1197 00:56:19.386904 CH=0, VrefRange= 0, VrefLevel = 8
1198 00:56:19.386960 TX Bit0 (976~997) 22 986, Bit8 (963~984) 22 973,
1199 00:56:19.387013 TX Bit1 (976~994) 19 985, Bit9 (965~987) 23 976,
1200 00:56:19.387063 TX Bit2 (976~996) 21 986, Bit10 (969~990) 22 979,
1201 00:56:19.387110 TX Bit3 (969~990) 22 979, Bit11 (965~986) 22 975,
1202 00:56:19.387158 TX Bit4 (975~997) 23 986, Bit12 (966~988) 23 977,
1203 00:56:19.387205 TX Bit5 (973~990) 18 981, Bit13 (966~985) 20 975,
1204 00:56:19.387257 TX Bit6 (974~991) 18 982, Bit14 (966~986) 21 976,
1205 00:56:19.387306 TX Bit7 (974~993) 20 983, Bit15 (968~989) 22 978,
1206 00:56:19.387353
1207 00:56:19.387400 Write Rank0 MR14 =0xa
1208 00:56:19.387446
1209 00:56:19.387496 CH=0, VrefRange= 0, VrefLevel = 10
1210 00:56:19.387545 TX Bit0 (976~997) 22 986, Bit8 (964~985) 22 974,
1211 00:56:19.387593 TX Bit1 (976~995) 20 985, Bit9 (965~987) 23 976,
1212 00:56:19.387641 TX Bit2 (976~996) 21 986, Bit10 (969~990) 22 979,
1213 00:56:19.387688 TX Bit3 (969~990) 22 979, Bit11 (965~987) 23 976,
1214 00:56:19.387739 TX Bit4 (975~997) 23 986, Bit12 (966~988) 23 977,
1215 00:56:19.387789 TX Bit5 (972~991) 20 981, Bit13 (965~986) 22 975,
1216 00:56:19.387837 TX Bit6 (973~991) 19 982, Bit14 (966~987) 22 976,
1217 00:56:19.387885 TX Bit7 (974~994) 21 984, Bit15 (968~989) 22 978,
1218 00:56:19.387933
1219 00:56:19.387984 Write Rank0 MR14 =0xc
1220 00:56:19.388033
1221 00:56:19.388079 CH=0, VrefRange= 0, VrefLevel = 12
1222 00:56:19.388127 TX Bit0 (976~998) 23 987, Bit8 (963~986) 24 974,
1223 00:56:19.388175 TX Bit1 (976~995) 20 985, Bit9 (965~988) 24 976,
1224 00:56:19.388227 TX Bit2 (976~996) 21 986, Bit10 (969~990) 22 979,
1225 00:56:19.388314 TX Bit3 (969~990) 22 979, Bit11 (964~988) 25 976,
1226 00:56:19.388391 TX Bit4 (975~997) 23 986, Bit12 (965~988) 24 976,
1227 00:56:19.388468 TX Bit5 (971~991) 21 981, Bit13 (965~987) 23 976,
1228 00:56:19.388547 TX Bit6 (973~992) 20 982, Bit14 (966~988) 23 977,
1229 00:56:19.388623 TX Bit7 (973~994) 22 983, Bit15 (968~989) 22 978,
1230 00:56:19.388698
1231 00:56:19.388775 Write Rank0 MR14 =0xe
1232 00:56:19.388850
1233 00:56:19.388925 CH=0, VrefRange= 0, VrefLevel = 14
1234 00:56:19.389004 TX Bit0 (976~998) 23 987, Bit8 (962~986) 25 974,
1235 00:56:19.389081 TX Bit1 (976~996) 21 986, Bit9 (965~989) 25 977,
1236 00:56:19.389157 TX Bit2 (975~997) 23 986, Bit10 (969~991) 23 980,
1237 00:56:19.389235 TX Bit3 (968~991) 24 979, Bit11 (963~988) 26 975,
1238 00:56:19.389313 TX Bit4 (975~998) 24 986, Bit12 (965~989) 25 977,
1239 00:56:19.389389 TX Bit5 (971~991) 21 981, Bit13 (965~987) 23 976,
1240 00:56:19.389467 TX Bit6 (972~992) 21 982, Bit14 (965~988) 24 976,
1241 00:56:19.389545 TX Bit7 (973~995) 23 984, Bit15 (967~989) 23 978,
1242 00:56:19.389620
1243 00:56:19.389694 Write Rank0 MR14 =0x10
1244 00:56:19.389772
1245 00:56:19.389847 CH=0, VrefRange= 0, VrefLevel = 16
1246 00:56:19.389923 TX Bit0 (976~998) 23 987, Bit8 (962~987) 26 974,
1247 00:56:19.390002 TX Bit1 (975~997) 23 986, Bit9 (964~989) 26 976,
1248 00:56:19.390078 TX Bit2 (975~997) 23 986, Bit10 (968~991) 24 979,
1249 00:56:19.390155 TX Bit3 (968~991) 24 979, Bit11 (963~988) 26 975,
1250 00:56:19.390273 TX Bit4 (974~998) 25 986, Bit12 (965~989) 25 977,
1251 00:56:19.390348 TX Bit5 (971~992) 22 981, Bit13 (964~988) 25 976,
1252 00:56:19.390396 TX Bit6 (972~993) 22 982, Bit14 (965~989) 25 977,
1253 00:56:19.390448 TX Bit7 (973~995) 23 984, Bit15 (967~990) 24 978,
1254 00:56:19.390524
1255 00:56:19.390599 Write Rank0 MR14 =0x12
1256 00:56:19.390674
1257 00:56:19.390752 CH=0, VrefRange= 0, VrefLevel = 18
1258 00:56:19.390831 TX Bit0 (976~998) 23 987, Bit8 (962~987) 26 974,
1259 00:56:19.390892 TX Bit1 (975~997) 23 986, Bit9 (964~989) 26 976,
1260 00:56:19.390941 TX Bit2 (975~997) 23 986, Bit10 (968~991) 24 979,
1261 00:56:19.391016 TX Bit3 (968~991) 24 979, Bit11 (963~988) 26 975,
1262 00:56:19.391085 TX Bit4 (974~998) 25 986, Bit12 (965~989) 25 977,
1263 00:56:19.391134 TX Bit5 (971~992) 22 981, Bit13 (964~988) 25 976,
1264 00:56:19.391182 TX Bit6 (972~993) 22 982, Bit14 (965~989) 25 977,
1265 00:56:19.391230 TX Bit7 (973~995) 23 984, Bit15 (967~990) 24 978,
1266 00:56:19.391278
1267 00:56:19.391331 Write Rank0 MR14 =0x14
1268 00:56:19.391379
1269 00:56:19.391427 CH=0, VrefRange= 0, VrefLevel = 20
1270 00:56:19.391485 TX Bit0 (976~999) 24 987, Bit8 (961~988) 28 974,
1271 00:56:19.391541 TX Bit1 (976~997) 22 986, Bit9 (964~988) 25 976,
1272 00:56:19.391591 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1273 00:56:19.391639 TX Bit3 (968~992) 25 980, Bit11 (962~989) 28 975,
1274 00:56:19.391687 TX Bit4 (974~998) 25 986, Bit12 (965~989) 25 977,
1275 00:56:19.391736 TX Bit5 (970~992) 23 981, Bit13 (963~989) 27 976,
1276 00:56:19.391980 TX Bit6 (970~993) 24 981, Bit14 (964~989) 26 976,
1277 00:56:19.392092 TX Bit7 (971~997) 27 984, Bit15 (967~990) 24 978,
1278 00:56:19.392203
1279 00:56:19.392310 Write Rank0 MR14 =0x16
1280 00:56:19.392418
1281 00:56:19.392524 CH=0, VrefRange= 0, VrefLevel = 22
1282 00:56:19.392625 TX Bit0 (975~999) 25 987, Bit8 (961~988) 28 974,
1283 00:56:19.392703 TX Bit1 (975~998) 24 986, Bit9 (963~989) 27 976,
1284 00:56:19.392776 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1285 00:56:19.392827 TX Bit3 (968~991) 24 979, Bit11 (963~989) 27 976,
1286 00:56:19.392875 TX Bit4 (974~999) 26 986, Bit12 (964~989) 26 976,
1287 00:56:19.392923 TX Bit5 (970~993) 24 981, Bit13 (963~988) 26 975,
1288 00:56:19.392972 TX Bit6 (971~995) 25 983, Bit14 (963~989) 27 976,
1289 00:56:19.393026 TX Bit7 (971~996) 26 983, Bit15 (966~991) 26 978,
1290 00:56:19.393075
1291 00:56:19.393122 Write Rank0 MR14 =0x18
1292 00:56:19.393170
1293 00:56:19.393218 CH=0, VrefRange= 0, VrefLevel = 24
1294 00:56:19.393272 TX Bit0 (975~999) 25 987, Bit8 (961~988) 28 974,
1295 00:56:19.393321 TX Bit1 (975~998) 24 986, Bit9 (963~989) 27 976,
1296 00:56:19.393369 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1297 00:56:19.393417 TX Bit3 (968~991) 24 979, Bit11 (963~989) 27 976,
1298 00:56:19.393464 TX Bit4 (974~999) 26 986, Bit12 (964~989) 26 976,
1299 00:56:19.393519 TX Bit5 (970~993) 24 981, Bit13 (963~988) 26 975,
1300 00:56:19.393567 TX Bit6 (971~995) 25 983, Bit14 (963~989) 27 976,
1301 00:56:19.393614 TX Bit7 (971~996) 26 983, Bit15 (966~991) 26 978,
1302 00:56:19.393661
1303 00:56:19.393709 Write Rank0 MR14 =0x1a
1304 00:56:19.393763
1305 00:56:19.393811 CH=0, VrefRange= 0, VrefLevel = 26
1306 00:56:19.393859 TX Bit0 (975~999) 25 987, Bit8 (961~988) 28 974,
1307 00:56:19.393908 TX Bit1 (975~998) 24 986, Bit9 (963~989) 27 976,
1308 00:56:19.393957 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1309 00:56:19.394011 TX Bit3 (968~991) 24 979, Bit11 (963~989) 27 976,
1310 00:56:19.394068 TX Bit4 (974~999) 26 986, Bit12 (964~989) 26 976,
1311 00:56:19.394119 TX Bit5 (970~993) 24 981, Bit13 (963~988) 26 975,
1312 00:56:19.394195 TX Bit6 (971~995) 25 983, Bit14 (963~989) 27 976,
1313 00:56:19.394265 TX Bit7 (971~996) 26 983, Bit15 (966~991) 26 978,
1314 00:56:19.394315
1315 00:56:19.394363 Write Rank0 MR14 =0x1c
1316 00:56:19.394411
1317 00:56:19.394460 CH=0, VrefRange= 0, VrefLevel = 28
1318 00:56:19.394527 TX Bit0 (975~999) 25 987, Bit8 (961~988) 28 974,
1319 00:56:19.394576 TX Bit1 (975~998) 24 986, Bit9 (963~989) 27 976,
1320 00:56:19.394623 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1321 00:56:19.394671 TX Bit3 (968~991) 24 979, Bit11 (963~989) 27 976,
1322 00:56:19.394719 TX Bit4 (974~999) 26 986, Bit12 (964~989) 26 976,
1323 00:56:19.394783 TX Bit5 (970~993) 24 981, Bit13 (963~988) 26 975,
1324 00:56:19.394833 TX Bit6 (971~995) 25 983, Bit14 (963~989) 27 976,
1325 00:56:19.394881 TX Bit7 (971~996) 26 983, Bit15 (966~991) 26 978,
1326 00:56:19.394929
1327 00:56:19.394978 Write Rank0 MR14 =0x1e
1328 00:56:19.395027
1329 00:56:19.395074 CH=0, VrefRange= 0, VrefLevel = 30
1330 00:56:19.395122 TX Bit0 (975~999) 25 987, Bit8 (961~988) 28 974,
1331 00:56:19.395170 TX Bit1 (975~998) 24 986, Bit9 (963~989) 27 976,
1332 00:56:19.395218 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1333 00:56:19.395271 TX Bit3 (968~991) 24 979, Bit11 (963~989) 27 976,
1334 00:56:19.395318 TX Bit4 (974~999) 26 986, Bit12 (964~989) 26 976,
1335 00:56:19.395365 TX Bit5 (970~993) 24 981, Bit13 (963~988) 26 975,
1336 00:56:19.395412 TX Bit6 (971~995) 25 983, Bit14 (963~989) 27 976,
1337 00:56:19.395459 TX Bit7 (971~996) 26 983, Bit15 (966~991) 26 978,
1338 00:56:19.395512
1339 00:56:19.395560
1340 00:56:19.395608 TX Vref found, early break! 379< 388
1341 00:56:19.395656 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
1342 00:56:19.395704 u1DelayCellOfst[0]=10 cells (8 PI)
1343 00:56:19.395756 u1DelayCellOfst[1]=9 cells (7 PI)
1344 00:56:19.395803 u1DelayCellOfst[2]=9 cells (7 PI)
1345 00:56:19.395850 u1DelayCellOfst[3]=0 cells (0 PI)
1346 00:56:19.395897 u1DelayCellOfst[4]=9 cells (7 PI)
1347 00:56:19.395944 u1DelayCellOfst[5]=2 cells (2 PI)
1348 00:56:19.395996 u1DelayCellOfst[6]=5 cells (4 PI)
1349 00:56:19.396043 u1DelayCellOfst[7]=5 cells (4 PI)
1350 00:56:19.396091 Byte0, DQ PI dly=979, DQM PI dly= 983
1351 00:56:19.396139 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1352 00:56:19.396187
1353 00:56:19.396263 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1354 00:56:19.396338
1355 00:56:19.396413 u1DelayCellOfst[8]=0 cells (0 PI)
1356 00:56:19.396491 u1DelayCellOfst[9]=2 cells (2 PI)
1357 00:56:19.396567 u1DelayCellOfst[10]=6 cells (5 PI)
1358 00:56:19.396642 u1DelayCellOfst[11]=2 cells (2 PI)
1359 00:56:19.396720 u1DelayCellOfst[12]=2 cells (2 PI)
1360 00:56:19.396796 u1DelayCellOfst[13]=1 cells (1 PI)
1361 00:56:19.396881 u1DelayCellOfst[14]=2 cells (2 PI)
1362 00:56:19.396959 u1DelayCellOfst[15]=5 cells (4 PI)
1363 00:56:19.397034 Byte1, DQ PI dly=974, DQM PI dly= 976
1364 00:56:19.397110 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 14)
1365 00:56:19.397184
1366 00:56:19.397255 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 14)
1367 00:56:19.397304
1368 00:56:19.397351 Write Rank0 MR14 =0x16
1369 00:56:19.397398
1370 00:56:19.397447 Final TX Range 0 Vref 22
1371 00:56:19.397496
1372 00:56:19.397543 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1373 00:56:19.397591
1374 00:56:19.397638 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1375 00:56:19.397690 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1376 00:56:19.397740 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1377 00:56:19.397788 Write Rank0 MR3 =0xb0
1378 00:56:19.397835 DramC Write-DBI on
1379 00:56:19.397881 ==
1380 00:56:19.397941 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1381 00:56:19.397991 fsp= 1, odt_onoff= 1, Byte mode= 0
1382 00:56:19.398038 ==
1383 00:56:19.398085 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1384 00:56:19.398131
1385 00:56:19.398181 Begin, DQ Scan Range 696~760
1386 00:56:19.398279
1387 00:56:19.398327
1388 00:56:19.398374 TX Vref Scan disable
1389 00:56:19.398629 696 |2 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1390 00:56:19.398744 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1391 00:56:19.398857 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1392 00:56:19.398969 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1393 00:56:19.399080 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1394 00:56:19.399215 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1395 00:56:19.399284 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1396 00:56:19.399334 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1397 00:56:19.399383 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1398 00:56:19.399437 705 |2 6 1|[0] xxxxxxxx oooooooo [MSB]
1399 00:56:19.399485 706 |2 6 2|[0] xxxxxxxx oooooooo [MSB]
1400 00:56:19.399534 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
1401 00:56:19.399582 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
1402 00:56:19.399631 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
1403 00:56:19.399685 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1404 00:56:19.399733 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1405 00:56:19.399780 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1406 00:56:19.399828 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1407 00:56:19.399878 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1408 00:56:19.399928 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB]
1409 00:56:19.399976 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1410 00:56:19.400024 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1411 00:56:19.400072 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1412 00:56:19.400123 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1413 00:56:19.400173 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1414 00:56:19.400230 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1415 00:56:19.400279 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1416 00:56:19.400326 742 |2 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1417 00:56:19.400378 Byte0, DQ PI dly=728, DQM PI dly= 728
1418 00:56:19.400426 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
1419 00:56:19.400473
1420 00:56:19.400521 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
1421 00:56:19.400568
1422 00:56:19.400617 Byte1, DQ PI dly=719, DQM PI dly= 719
1423 00:56:19.400667 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 15)
1424 00:56:19.400713
1425 00:56:19.400760 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 15)
1426 00:56:19.400808
1427 00:56:19.400855 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1428 00:56:19.400935 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1429 00:56:19.401013 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1430 00:56:19.401092 Write Rank0 MR3 =0x30
1431 00:56:19.401179 DramC Write-DBI off
1432 00:56:19.401253
1433 00:56:19.401327 [DATLAT]
1434 00:56:19.401414 Freq=1600, CH0 RK0, use_rxtx_scan=0
1435 00:56:19.401490
1436 00:56:19.401564 DATLAT Default: 0xf
1437 00:56:19.401642 7, 0xFFFF, sum=0
1438 00:56:19.401720 8, 0xFFFF, sum=0
1439 00:56:19.401796 9, 0xFFFF, sum=0
1440 00:56:19.401876 10, 0xFFFF, sum=0
1441 00:56:19.401953 11, 0xFFFF, sum=0
1442 00:56:19.402029 12, 0xFFFF, sum=0
1443 00:56:19.402109 13, 0xFFFF, sum=0
1444 00:56:19.402186 14, 0x0, sum=1
1445 00:56:19.402319 15, 0x0, sum=2
1446 00:56:19.402376 16, 0x0, sum=3
1447 00:56:19.402425 17, 0x0, sum=4
1448 00:56:19.402472 pattern=2 first_step=14 total pass=5 best_step=16
1449 00:56:19.402520 ==
1450 00:56:19.402570 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1451 00:56:19.402620 fsp= 1, odt_onoff= 1, Byte mode= 0
1452 00:56:19.402668 ==
1453 00:56:19.402714 Start DQ dly to find pass range UseTestEngine =1
1454 00:56:19.402761 x-axis: bit #, y-axis: DQ dly (-127~63)
1455 00:56:19.402810 RX Vref Scan = 1
1456 00:56:19.402886
1457 00:56:19.402961 RX Vref found, early break!
1458 00:56:19.403035
1459 00:56:19.403117 Final RX Vref 12, apply to both rank0 and 1
1460 00:56:19.403205 ==
1461 00:56:19.403262 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1462 00:56:19.403316 fsp= 1, odt_onoff= 1, Byte mode= 0
1463 00:56:19.403392 ==
1464 00:56:19.403466 DQS Delay:
1465 00:56:19.403540 DQS0 = 0, DQS1 = 0
1466 00:56:19.403628 DQM Delay:
1467 00:56:19.403703 DQM0 = 19, DQM1 = 18
1468 00:56:19.403781 DQ Delay:
1469 00:56:19.403860 DQ0 =24, DQ1 =23, DQ2 =23, DQ3 =13
1470 00:56:19.403936 DQ4 =22, DQ5 =14, DQ6 =16, DQ7 =18
1471 00:56:19.404011 DQ8 =18, DQ9 =19, DQ10 =22, DQ11 =17
1472 00:56:19.404092 DQ12 =19, DQ13 =16, DQ14 =17, DQ15 =20
1473 00:56:19.404168
1474 00:56:19.404242
1475 00:56:19.404321
1476 00:56:19.404395 [DramC_TX_OE_Calibration] TA2
1477 00:56:19.404470 Original DQ_B0 (3 6) =30, OEN = 27
1478 00:56:19.404547 Original DQ_B1 (3 6) =30, OEN = 27
1479 00:56:19.404624 23, 0x0, End_B0=23 End_B1=23
1480 00:56:19.404701 24, 0x0, End_B0=24 End_B1=24
1481 00:56:19.404779 25, 0x0, End_B0=25 End_B1=25
1482 00:56:19.404859 26, 0x0, End_B0=26 End_B1=26
1483 00:56:19.404945 27, 0x0, End_B0=27 End_B1=27
1484 00:56:19.405023 28, 0x0, End_B0=28 End_B1=28
1485 00:56:19.405079 29, 0x0, End_B0=29 End_B1=29
1486 00:56:19.405137 30, 0x0, End_B0=30 End_B1=30
1487 00:56:19.405186 31, 0xFFFF, End_B0=30 End_B1=30
1488 00:56:19.405234 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1489 00:56:19.405286 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1490 00:56:19.405334
1491 00:56:19.405381
1492 00:56:19.405427 Write Rank0 MR23 =0x3f
1493 00:56:19.405474 [DQSOSC]
1494 00:56:19.405526 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c, (MSB)MR19= 0x3, tDQSOscB0 = 340 ps tDQSOscB1 = 0 ps
1495 00:56:19.405604 CH0_RK0: MR19=0x3, MR18=0x9C, DQSOSC=340, MR23=63, INC=21, DEC=31
1496 00:56:19.405679 Write Rank0 MR23 =0x3f
1497 00:56:19.405753 [DQSOSC]
1498 00:56:19.405832 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d, (MSB)MR19= 0x3, tDQSOscB0 = 340 ps tDQSOscB1 = 0 ps
1499 00:56:19.405884 CH0 RK0: MR19=3, MR18=9D
1500 00:56:19.405932 [RankSwap] Rank num 2, (Multi 1), Rank 1
1501 00:56:19.405979 Write Rank0 MR2 =0xad
1502 00:56:19.406033 [Write Leveling]
1503 00:56:19.406080 delay byte0 byte1 byte2 byte3
1504 00:56:19.406127
1505 00:56:19.406173 10 0 0
1506 00:56:19.406248 11 0 0
1507 00:56:19.406330 12 0 0
1508 00:56:19.406379 13 0 0
1509 00:56:19.406427 14 0 0
1510 00:56:19.406474 15 0 0
1511 00:56:19.406526 16 0 0
1512 00:56:19.406576 17 0 0
1513 00:56:19.406624 18 0 0
1514 00:56:19.406671 19 0 0
1515 00:56:19.406719 20 0 0
1516 00:56:19.406770 21 0 0
1517 00:56:19.406830 22 0 0
1518 00:56:19.406877 23 0 0
1519 00:56:19.406925 24 0 0
1520 00:56:19.406972 25 0 0
1521 00:56:19.407027 26 0 0
1522 00:56:19.407075 27 0 0
1523 00:56:19.407137 28 0 0
1524 00:56:19.407230 29 0 0
1525 00:56:19.407284 30 0 ff
1526 00:56:19.407332 31 0 ff
1527 00:56:19.407379 32 0 ff
1528 00:56:19.407427 33 0 ff
1529 00:56:19.407474 34 0 ff
1530 00:56:19.407527 35 ff ff
1531 00:56:19.407575 36 ff ff
1532 00:56:19.407623 37 ff ff
1533 00:56:19.407670 38 ff ff
1534 00:56:19.407717 39 ff ff
1535 00:56:19.407962 40 ff ff
1536 00:56:19.408024 41 ff ff
1537 00:56:19.408075 pass bytecount = 0xff (0xff: all bytes pass)
1538 00:56:19.408134
1539 00:56:19.408183 DQS0 dly: 35
1540 00:56:19.408230 DQS1 dly: 30
1541 00:56:19.408283 Write Rank0 MR2 =0x2d
1542 00:56:19.408331 [RankSwap] Rank num 2, (Multi 1), Rank 0
1543 00:56:19.408378 Write Rank1 MR1 =0xd6
1544 00:56:19.408425 [Gating]
1545 00:56:19.408471 ==
1546 00:56:19.408524 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1547 00:56:19.408572 fsp= 1, odt_onoff= 1, Byte mode= 0
1548 00:56:19.408620 ==
1549 00:56:19.408668 3 1 0 |3534 807 |(11 11)(11 11) |(0 0)(0 0)| 0
1550 00:56:19.408716 3 1 4 |3534 3535 |(11 11)(11 11) |(0 0)(1 1)| 0
1551 00:56:19.408771 3 1 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1552 00:56:19.408819 3 1 12 |3534 706 |(11 11)(11 11) |(1 1)(1 1)| 0
1553 00:56:19.408867 3 1 16 |3534 3635 |(11 11)(11 11) |(0 0)(0 1)| 0
1554 00:56:19.408915 3 1 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1555 00:56:19.408963 3 1 24 |3534 3535 |(11 11)(11 11) |(0 0)(0 1)| 0
1556 00:56:19.409017 3 1 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1557 00:56:19.409066 3 2 0 |3534 b0b |(11 11)(11 11) |(0 0)(0 1)| 0
1558 00:56:19.409119 3 2 4 |3534 e0e |(11 11)(11 11) |(0 1)(1 0)| 0
1559 00:56:19.409223 3 2 8 |908 1616 |(11 11)(11 11) |(1 1)(1 1)| 0
1560 00:56:19.409279 3 2 12 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
1561 00:56:19.409346 3 2 16 |3d3d 3d3d |(11 11)(0 0) |(1 1)(1 1)| 0
1562 00:56:19.409398 3 2 20 |3d3d 2323 |(11 11)(11 11) |(1 1)(1 1)| 0
1563 00:56:19.409467 3 2 24 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
1564 00:56:19.409518 3 2 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1565 00:56:19.409567 3 3 0 |3d3d 3c3c |(11 11)(11 11) |(1 1)(1 1)| 0
1566 00:56:19.409615 3 3 4 |3d3d 1211 |(11 11)(11 11) |(1 1)(1 1)| 0
1567 00:56:19.409663 3 3 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1568 00:56:19.409731 3 3 12 |3d3d 3c3c |(11 11)(11 11) |(1 1)(1 1)| 0
1569 00:56:19.409781 3 3 16 |1413 201 |(11 11)(11 11) |(1 1)(1 1)| 0
1570 00:56:19.409829 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1571 00:56:19.409877 [Byte 0] Lead/lag Transition tap number (1)
1572 00:56:19.409924 [Byte 1] Lead/lag falling Transition (3, 3, 20)
1573 00:56:19.409990 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1574 00:56:19.410079 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1575 00:56:19.410166 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1576 00:56:19.410274 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1577 00:56:19.410324 3 4 8 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1578 00:56:19.410373 3 4 12 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
1579 00:56:19.410422 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1580 00:56:19.410476 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1581 00:56:19.410525 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1582 00:56:19.410573 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1583 00:56:19.410621 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1584 00:56:19.410669 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1585 00:56:19.410722 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1586 00:56:19.410771 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1587 00:56:19.410820 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1588 00:56:19.410867 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1589 00:56:19.410916 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1590 00:56:19.410969 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1591 00:56:19.411019 [Byte 0] Lead/lag falling Transition (3, 5, 28)
1592 00:56:19.411067 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1593 00:56:19.411120 [Byte 1] Lead/lag falling Transition (3, 6, 0)
1594 00:56:19.411174 3 6 4 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1595 00:56:19.411247 [Byte 0] Lead/lag Transition tap number (3)
1596 00:56:19.411334 [Byte 1] Lead/lag Transition tap number (2)
1597 00:56:19.411410 3 6 8 |403 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0
1598 00:56:19.411491 3 6 12 |4646 202 |(10 10)(11 11) |(0 0)(0 0)| 0
1599 00:56:19.411568 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1600 00:56:19.411645 [Byte 0]First pass (3, 6, 16)
1601 00:56:19.411723 [Byte 1]First pass (3, 6, 16)
1602 00:56:19.411798 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1603 00:56:19.411875 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1604 00:56:19.411955 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1605 00:56:19.412033 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1606 00:56:19.412110 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1607 00:56:19.412187 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1608 00:56:19.412267 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1609 00:56:19.412344 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1610 00:56:19.412423 All bytes gating window > 1UI, Early break!
1611 00:56:19.412498
1612 00:56:19.412573 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 2)
1613 00:56:19.412647
1614 00:56:19.412725 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 4)
1615 00:56:19.412799
1616 00:56:19.412872
1617 00:56:19.412949
1618 00:56:19.413024 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 2)
1619 00:56:19.413102
1620 00:56:19.413228 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1621 00:56:19.413302
1622 00:56:19.413376
1623 00:56:19.413452 Write Rank1 MR1 =0x56
1624 00:56:19.413527
1625 00:56:19.413612 best RODT dly(2T, 0.5T) = (2, 3)
1626 00:56:19.413686
1627 00:56:19.413764 best RODT dly(2T, 0.5T) = (2, 3)
1628 00:56:19.413838 ==
1629 00:56:19.413923 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1630 00:56:19.414002 fsp= 1, odt_onoff= 1, Byte mode= 0
1631 00:56:19.414077 ==
1632 00:56:19.414162 Start DQ dly to find pass range UseTestEngine =0
1633 00:56:19.414284 x-axis: bit #, y-axis: DQ dly (-127~63)
1634 00:56:19.414363 RX Vref Scan = 0
1635 00:56:19.414445 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1636 00:56:19.414525 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1637 00:56:19.414606 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1638 00:56:19.414701 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1639 00:56:19.414783 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1640 00:56:19.414861 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1641 00:56:19.414937 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1642 00:56:19.415014 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1643 00:56:19.415287 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1644 00:56:19.415401 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1645 00:56:19.415512 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1646 00:56:19.415620 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1647 00:56:19.415730 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1648 00:56:19.415840 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1649 00:56:19.415940 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1650 00:56:19.416019 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1651 00:56:19.416096 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1652 00:56:19.416173 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1653 00:56:19.416238 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1654 00:56:19.416287 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1655 00:56:19.416336 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1656 00:56:19.416384 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1657 00:56:19.416431 -4, [0] xxxoxxxx xxxxxxxx [MSB]
1658 00:56:19.416479 -3, [0] xxxoxxxx xxxxxxxx [MSB]
1659 00:56:19.416535 -2, [0] xxxoxxxx xxxxxxxx [MSB]
1660 00:56:19.416583 -1, [0] xxxoxooo oxxxxxxx [MSB]
1661 00:56:19.416631 0, [0] xxxoxooo ooxoxoxx [MSB]
1662 00:56:19.416679 1, [0] xxxoxooo ooxoooox [MSB]
1663 00:56:19.416727 2, [0] xxxoxooo ooxooooo [MSB]
1664 00:56:19.416775 3, [0] xxxoxooo ooxooooo [MSB]
1665 00:56:19.416829 4, [0] xxxoxooo ooxooooo [MSB]
1666 00:56:19.416917 5, [0] xooooooo oooooooo [MSB]
1667 00:56:19.416993 6, [0] xooooooo oooooooo [MSB]
1668 00:56:19.417070 32, [0] oooxoooo oooooooo [MSB]
1669 00:56:19.417183 33, [0] oooxoooo oooooooo [MSB]
1670 00:56:19.417270 34, [0] oooxoxoo oooooooo [MSB]
1671 00:56:19.417321 35, [0] oooxoxoo oooxooxo [MSB]
1672 00:56:19.417370 36, [0] oooxoxxx xooxooxo [MSB]
1673 00:56:19.417418 37, [0] oooxoxxx xooxoxxo [MSB]
1674 00:56:19.417472 38, [0] oooxoxxx xooxoxxo [MSB]
1675 00:56:19.417525 39, [0] oooxoxxx xxoxxxxo [MSB]
1676 00:56:19.417574 40, [0] oxoxxxxx xxoxxxxx [MSB]
1677 00:56:19.417622 41, [0] oxxxxxxx xxoxxxxx [MSB]
1678 00:56:19.417670 42, [0] xxxxxxxx xxoxxxxx [MSB]
1679 00:56:19.417717 43, [0] xxxxxxxx xxxxxxxx [MSB]
1680 00:56:19.417793 iDelay=43, Bit 0, Center 24 (7 ~ 41) 35
1681 00:56:19.417869 iDelay=43, Bit 1, Center 22 (5 ~ 39) 35
1682 00:56:19.417944 iDelay=43, Bit 2, Center 22 (5 ~ 40) 36
1683 00:56:19.418018 iDelay=43, Bit 3, Center 13 (-4 ~ 31) 36
1684 00:56:19.418112 iDelay=43, Bit 4, Center 22 (5 ~ 39) 35
1685 00:56:19.418200 iDelay=43, Bit 5, Center 16 (-1 ~ 33) 35
1686 00:56:19.418262 iDelay=43, Bit 6, Center 17 (-1 ~ 35) 37
1687 00:56:19.418315 iDelay=43, Bit 7, Center 17 (-1 ~ 35) 37
1688 00:56:19.418363 iDelay=43, Bit 8, Center 17 (-1 ~ 35) 37
1689 00:56:19.418410 iDelay=43, Bit 9, Center 19 (0 ~ 38) 39
1690 00:56:19.418457 iDelay=43, Bit 10, Center 23 (5 ~ 42) 38
1691 00:56:19.418504 iDelay=43, Bit 11, Center 17 (0 ~ 34) 35
1692 00:56:19.418552 iDelay=43, Bit 12, Center 19 (1 ~ 38) 38
1693 00:56:19.418605 iDelay=43, Bit 13, Center 18 (0 ~ 36) 37
1694 00:56:19.418654 iDelay=43, Bit 14, Center 17 (1 ~ 34) 34
1695 00:56:19.418701 iDelay=43, Bit 15, Center 20 (2 ~ 39) 38
1696 00:56:19.418748 ==
1697 00:56:19.418796 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1698 00:56:19.418843 fsp= 1, odt_onoff= 1, Byte mode= 0
1699 00:56:19.418894 ==
1700 00:56:19.418943 DQS Delay:
1701 00:56:19.418989 DQS0 = 0, DQS1 = 0
1702 00:56:19.419037 DQM Delay:
1703 00:56:19.419084 DQM0 = 19, DQM1 = 18
1704 00:56:19.419147 DQ Delay:
1705 00:56:19.419247 DQ0 =24, DQ1 =22, DQ2 =22, DQ3 =13
1706 00:56:19.419297 DQ4 =22, DQ5 =16, DQ6 =17, DQ7 =17
1707 00:56:19.419346 DQ8 =17, DQ9 =19, DQ10 =23, DQ11 =17
1708 00:56:19.419393 DQ12 =19, DQ13 =18, DQ14 =17, DQ15 =20
1709 00:56:19.419440
1710 00:56:19.419489
1711 00:56:19.419538 DramC Write-DBI off
1712 00:56:19.419586 ==
1713 00:56:19.419633 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1714 00:56:19.419681 fsp= 1, odt_onoff= 1, Byte mode= 0
1715 00:56:19.419728 ==
1716 00:56:19.419776 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1717 00:56:19.419831
1718 00:56:19.419878 Begin, DQ Scan Range 926~1182
1719 00:56:19.419925
1720 00:56:19.419971
1721 00:56:19.420017 TX Vref Scan disable
1722 00:56:19.420075 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1723 00:56:19.420130 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1724 00:56:19.420180 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1725 00:56:19.420228 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1726 00:56:19.420276 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1727 00:56:19.420325 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1728 00:56:19.420379 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1729 00:56:19.420428 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1730 00:56:19.420476 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1731 00:56:19.420525 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1732 00:56:19.420573 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1733 00:56:19.420621 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1734 00:56:19.420682 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1735 00:56:19.420760 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1736 00:56:19.420837 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1737 00:56:19.420914 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1738 00:56:19.420994 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1739 00:56:19.421072 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1740 00:56:19.421189 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1741 00:56:19.421292 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1742 00:56:19.421381 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1743 00:56:19.421469 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1744 00:56:19.421551 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1745 00:56:19.421630 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1746 00:56:19.421707 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1747 00:56:19.421786 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1748 00:56:19.421864 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1749 00:56:19.421942 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1750 00:56:19.422019 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1751 00:56:19.422100 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1752 00:56:19.422177 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1753 00:56:19.422284 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1754 00:56:19.422334 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1755 00:56:19.422415 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1756 00:56:19.422493 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1757 00:56:19.422570 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1758 00:56:19.422649 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1759 00:56:19.422728 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1760 00:56:19.422816 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1761 00:56:19.422898 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1762 00:56:19.423150 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1763 00:56:19.423209 967 |3 6 7|[0] xxxxxxxx oxxoxxxx [MSB]
1764 00:56:19.423260 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB]
1765 00:56:19.423308 969 |3 6 9|[0] xxxxxxxx ooxoooox [MSB]
1766 00:56:19.423357 970 |3 6 10|[0] xxxxxxxx ooxooooo [MSB]
1767 00:56:19.423406 971 |3 6 11|[0] xxxxxxxx ooxooooo [MSB]
1768 00:56:19.423454 972 |3 6 12|[0] xxxxxxxx ooxooooo [MSB]
1769 00:56:19.423519 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
1770 00:56:19.423589 974 |3 6 14|[0] xxxoxoox oooooooo [MSB]
1771 00:56:19.423651 975 |3 6 15|[0] xxxoxoox oooooooo [MSB]
1772 00:56:19.423698 976 |3 6 16|[0] xxxoooox oooooooo [MSB]
1773 00:56:19.423747 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1774 00:56:19.423800 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1775 00:56:19.423849 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1776 00:56:19.423897 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1777 00:56:19.423945 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1778 00:56:19.423993 995 |3 6 35|[0] oooxoxoo xxxxxxxx [MSB]
1779 00:56:19.424040 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1780 00:56:19.424094 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1781 00:56:19.424143 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1782 00:56:19.424191 Byte0, DQ PI dly=985, DQM PI dly= 985
1783 00:56:19.424238 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
1784 00:56:19.424285
1785 00:56:19.424333 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
1786 00:56:19.424385
1787 00:56:19.424433 Byte1, DQ PI dly=979, DQM PI dly= 979
1788 00:56:19.424480 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1789 00:56:19.424528
1790 00:56:19.424574 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1791 00:56:19.424623
1792 00:56:19.424674 ==
1793 00:56:19.424733 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1794 00:56:19.424781 fsp= 1, odt_onoff= 1, Byte mode= 0
1795 00:56:19.424829 ==
1796 00:56:19.424876 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1797 00:56:19.424927
1798 00:56:19.424975 Begin, DQ Scan Range 955~1019
1799 00:56:19.425021 Write Rank1 MR14 =0x0
1800 00:56:19.425068
1801 00:56:19.425118 CH=0, VrefRange= 0, VrefLevel = 0
1802 00:56:19.425194 TX Bit0 (979~997) 19 988, Bit8 (968~987) 20 977,
1803 00:56:19.425315 TX Bit1 (978~996) 19 987, Bit9 (970~988) 19 979,
1804 00:56:19.425391 TX Bit2 (978~997) 20 987, Bit10 (975~991) 17 983,
1805 00:56:19.425467 TX Bit3 (975~990) 16 982, Bit11 (970~988) 19 979,
1806 00:56:19.425545 TX Bit4 (978~997) 20 987, Bit12 (971~989) 19 980,
1807 00:56:19.425622 TX Bit5 (976~990) 15 983, Bit13 (970~986) 17 978,
1808 00:56:19.425697 TX Bit6 (976~991) 16 983, Bit14 (972~988) 17 980,
1809 00:56:19.425773 TX Bit7 (978~992) 15 985, Bit15 (973~990) 18 981,
1810 00:56:19.425850
1811 00:56:19.425925 wait MRW command Rank1 MR14 =0x2 fired (1)
1812 00:56:19.426000 Write Rank1 MR14 =0x2
1813 00:56:19.426073
1814 00:56:19.426151 CH=0, VrefRange= 0, VrefLevel = 2
1815 00:56:19.426249 TX Bit0 (979~998) 20 988, Bit8 (968~988) 21 978,
1816 00:56:19.426314 TX Bit1 (978~996) 19 987, Bit9 (970~989) 20 979,
1817 00:56:19.426362 TX Bit2 (978~997) 20 987, Bit10 (975~991) 17 983,
1818 00:56:19.426415 TX Bit3 (974~990) 17 982, Bit11 (969~988) 20 978,
1819 00:56:19.426463 TX Bit4 (978~997) 20 987, Bit12 (971~989) 19 980,
1820 00:56:19.426511 TX Bit5 (976~991) 16 983, Bit13 (970~987) 18 978,
1821 00:56:19.426559 TX Bit6 (976~992) 17 984, Bit14 (972~989) 18 980,
1822 00:56:19.426606 TX Bit7 (978~993) 16 985, Bit15 (973~990) 18 981,
1823 00:56:19.426653
1824 00:56:19.426703 Write Rank1 MR14 =0x4
1825 00:56:19.426751
1826 00:56:19.426797 CH=0, VrefRange= 0, VrefLevel = 4
1827 00:56:19.426843 TX Bit0 (978~998) 21 988, Bit8 (968~988) 21 978,
1828 00:56:19.426890 TX Bit1 (978~997) 20 987, Bit9 (969~989) 21 979,
1829 00:56:19.426938 TX Bit2 (978~998) 21 988, Bit10 (975~992) 18 983,
1830 00:56:19.426989 TX Bit3 (974~990) 17 982, Bit11 (968~989) 22 978,
1831 00:56:19.427037 TX Bit4 (977~997) 21 987, Bit12 (970~989) 20 979,
1832 00:56:19.427094 TX Bit5 (975~991) 17 983, Bit13 (969~987) 19 978,
1833 00:56:19.427180 TX Bit6 (976~992) 17 984, Bit14 (971~989) 19 980,
1834 00:56:19.427248 TX Bit7 (977~994) 18 985, Bit15 (973~990) 18 981,
1835 00:56:19.427336
1836 00:56:19.427404 Write Rank1 MR14 =0x6
1837 00:56:19.427453
1838 00:56:19.427500 CH=0, VrefRange= 0, VrefLevel = 6
1839 00:56:19.427554 TX Bit0 (978~998) 21 988, Bit8 (968~989) 22 978,
1840 00:56:19.427602 TX Bit1 (978~997) 20 987, Bit9 (969~989) 21 979,
1841 00:56:19.427650 TX Bit2 (978~998) 21 988, Bit10 (974~992) 19 983,
1842 00:56:19.427697 TX Bit3 (974~990) 17 982, Bit11 (969~989) 21 979,
1843 00:56:19.427745 TX Bit4 (977~998) 22 987, Bit12 (969~989) 21 979,
1844 00:56:19.427793 TX Bit5 (975~992) 18 983, Bit13 (969~988) 20 978,
1845 00:56:19.427846 TX Bit6 (976~993) 18 984, Bit14 (971~989) 19 980,
1846 00:56:19.427894 TX Bit7 (977~994) 18 985, Bit15 (972~991) 20 981,
1847 00:56:19.427941
1848 00:56:19.427987 Write Rank1 MR14 =0x8
1849 00:56:19.428034
1850 00:56:19.428081 CH=0, VrefRange= 0, VrefLevel = 8
1851 00:56:19.428144 TX Bit0 (978~999) 22 988, Bit8 (968~989) 22 978,
1852 00:56:19.428193 TX Bit1 (977~997) 21 987, Bit9 (969~990) 22 979,
1853 00:56:19.428240 TX Bit2 (978~998) 21 988, Bit10 (974~992) 19 983,
1854 00:56:19.428289 TX Bit3 (973~991) 19 982, Bit11 (968~989) 22 978,
1855 00:56:19.428337 TX Bit4 (977~998) 22 987, Bit12 (969~990) 22 979,
1856 00:56:19.428390 TX Bit5 (975~992) 18 983, Bit13 (969~988) 20 978,
1857 00:56:19.428438 TX Bit6 (975~993) 19 984, Bit14 (970~989) 20 979,
1858 00:56:19.428486 TX Bit7 (977~995) 19 986, Bit15 (972~991) 20 981,
1859 00:56:19.428533
1860 00:56:19.428579 Write Rank1 MR14 =0xa
1861 00:56:19.428632
1862 00:56:19.428679 CH=0, VrefRange= 0, VrefLevel = 10
1863 00:56:19.428727 TX Bit0 (978~999) 22 988, Bit8 (967~989) 23 978,
1864 00:56:19.428774 TX Bit1 (977~998) 22 987, Bit9 (968~990) 23 979,
1865 00:56:19.428822 TX Bit2 (977~998) 22 987, Bit10 (974~993) 20 983,
1866 00:56:19.428876 TX Bit3 (973~991) 19 982, Bit11 (968~989) 22 978,
1867 00:56:19.428924 TX Bit4 (977~998) 22 987, Bit12 (971~990) 20 980,
1868 00:56:19.429166 TX Bit5 (975~992) 18 983, Bit13 (968~989) 22 978,
1869 00:56:19.429227 TX Bit6 (975~994) 20 984, Bit14 (970~990) 21 980,
1870 00:56:19.429276 TX Bit7 (977~995) 19 986, Bit15 (971~991) 21 981,
1871 00:56:19.429324
1872 00:56:19.429371 Write Rank1 MR14 =0xc
1873 00:56:19.429422
1874 00:56:19.429471 CH=0, VrefRange= 0, VrefLevel = 12
1875 00:56:19.429518 TX Bit0 (978~999) 22 988, Bit8 (967~989) 23 978,
1876 00:56:19.429565 TX Bit1 (977~998) 22 987, Bit9 (968~990) 23 979,
1877 00:56:19.429613 TX Bit2 (977~999) 23 988, Bit10 (974~993) 20 983,
1878 00:56:19.429660 TX Bit3 (973~991) 19 982, Bit11 (968~990) 23 979,
1879 00:56:19.429740 TX Bit4 (977~999) 23 988, Bit12 (969~990) 22 979,
1880 00:56:19.429815 TX Bit5 (974~993) 20 983, Bit13 (968~989) 22 978,
1881 00:56:19.429891 TX Bit6 (975~994) 20 984, Bit14 (968~990) 23 979,
1882 00:56:19.429970 TX Bit7 (977~996) 20 986, Bit15 (972~992) 21 982,
1883 00:56:19.430044
1884 00:56:19.430119 Write Rank1 MR14 =0xe
1885 00:56:19.430207
1886 00:56:19.430323 CH=0, VrefRange= 0, VrefLevel = 14
1887 00:56:19.430398 TX Bit0 (977~1000) 24 988, Bit8 (967~989) 23 978,
1888 00:56:19.430478 TX Bit1 (977~998) 22 987, Bit9 (968~990) 23 979,
1889 00:56:19.430554 TX Bit2 (977~999) 23 988, Bit10 (974~993) 20 983,
1890 00:56:19.430630 TX Bit3 (972~992) 21 982, Bit11 (967~990) 24 978,
1891 00:56:19.430709 TX Bit4 (977~999) 23 988, Bit12 (969~990) 22 979,
1892 00:56:19.430785 TX Bit5 (974~993) 20 983, Bit13 (968~989) 22 978,
1893 00:56:19.430861 TX Bit6 (974~995) 22 984, Bit14 (968~990) 23 979,
1894 00:56:19.430940 TX Bit7 (977~997) 21 987, Bit15 (972~992) 21 982,
1895 00:56:19.431014
1896 00:56:19.431091 Write Rank1 MR14 =0x10
1897 00:56:19.431175
1898 00:56:19.431250 CH=0, VrefRange= 0, VrefLevel = 16
1899 00:56:19.431325 TX Bit0 (977~1000) 24 988, Bit8 (967~990) 24 978,
1900 00:56:19.431414 TX Bit1 (977~998) 22 987, Bit9 (968~990) 23 979,
1901 00:56:19.431492 TX Bit2 (977~999) 23 988, Bit10 (974~994) 21 984,
1902 00:56:19.431568 TX Bit3 (971~992) 22 981, Bit11 (967~990) 24 978,
1903 00:56:19.431645 TX Bit4 (976~999) 24 987, Bit12 (968~990) 23 979,
1904 00:56:19.431723 TX Bit5 (973~994) 22 983, Bit13 (968~989) 22 978,
1905 00:56:19.431799 TX Bit6 (974~995) 22 984, Bit14 (968~990) 23 979,
1906 00:56:19.431876 TX Bit7 (976~997) 22 986, Bit15 (970~993) 24 981,
1907 00:56:19.431952
1908 00:56:19.432026 Write Rank1 MR14 =0x12
1909 00:56:19.432099
1910 00:56:19.432186 CH=0, VrefRange= 0, VrefLevel = 18
1911 00:56:19.432263 TX Bit0 (977~1001) 25 989, Bit8 (967~990) 24 978,
1912 00:56:19.432338 TX Bit1 (977~999) 23 988, Bit9 (968~991) 24 979,
1913 00:56:19.432416 TX Bit2 (977~999) 23 988, Bit10 (973~995) 23 984,
1914 00:56:19.432493 TX Bit3 (971~993) 23 982, Bit11 (967~990) 24 978,
1915 00:56:19.432569 TX Bit4 (976~1000) 25 988, Bit12 (969~991) 23 980,
1916 00:56:19.432645 TX Bit5 (973~995) 23 984, Bit13 (968~990) 23 979,
1917 00:56:19.432724 TX Bit6 (973~996) 24 984, Bit14 (968~991) 24 979,
1918 00:56:19.432799 TX Bit7 (976~997) 22 986, Bit15 (970~993) 24 981,
1919 00:56:19.432874
1920 00:56:19.432951 Write Rank1 MR14 =0x14
1921 00:56:19.433025
1922 00:56:19.433104 CH=0, VrefRange= 0, VrefLevel = 20
1923 00:56:19.433199 TX Bit0 (977~1001) 25 989, Bit8 (967~990) 24 978,
1924 00:56:19.433251 TX Bit1 (977~999) 23 988, Bit9 (968~991) 24 979,
1925 00:56:19.433300 TX Bit2 (977~1000) 24 988, Bit10 (973~994) 22 983,
1926 00:56:19.433346 TX Bit3 (971~993) 23 982, Bit11 (967~991) 25 979,
1927 00:56:19.433399 TX Bit4 (976~1000) 25 988, Bit12 (968~991) 24 979,
1928 00:56:19.433449 TX Bit5 (972~995) 24 983, Bit13 (967~990) 24 978,
1929 00:56:19.433496 TX Bit6 (973~997) 25 985, Bit14 (968~991) 24 979,
1930 00:56:19.433544 TX Bit7 (976~998) 23 987, Bit15 (970~994) 25 982,
1931 00:56:19.433601
1932 00:56:19.433654 Write Rank1 MR14 =0x16
1933 00:56:19.433702
1934 00:56:19.433749 CH=0, VrefRange= 0, VrefLevel = 22
1935 00:56:19.433795 TX Bit0 (977~1002) 26 989, Bit8 (966~990) 25 978,
1936 00:56:19.433843 TX Bit1 (977~999) 23 988, Bit9 (967~991) 25 979,
1937 00:56:19.433897 TX Bit2 (976~1000) 25 988, Bit10 (973~996) 24 984,
1938 00:56:19.433946 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1939 00:56:19.433994 TX Bit4 (976~1001) 26 988, Bit12 (968~991) 24 979,
1940 00:56:19.434041 TX Bit5 (971~996) 26 983, Bit13 (967~990) 24 978,
1941 00:56:19.434089 TX Bit6 (973~997) 25 985, Bit14 (967~991) 25 979,
1942 00:56:19.434136 TX Bit7 (976~998) 23 987, Bit15 (969~993) 25 981,
1943 00:56:19.434214
1944 00:56:19.434326 Write Rank1 MR14 =0x18
1945 00:56:19.434374
1946 00:56:19.434429 CH=0, VrefRange= 0, VrefLevel = 24
1947 00:56:19.434477 TX Bit0 (977~1002) 26 989, Bit8 (966~990) 25 978,
1948 00:56:19.434525 TX Bit1 (977~999) 23 988, Bit9 (967~991) 25 979,
1949 00:56:19.434572 TX Bit2 (976~1000) 25 988, Bit10 (973~996) 24 984,
1950 00:56:19.434619 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1951 00:56:19.434667 TX Bit4 (976~1001) 26 988, Bit12 (968~991) 24 979,
1952 00:56:19.434719 TX Bit5 (971~996) 26 983, Bit13 (967~990) 24 978,
1953 00:56:19.434767 TX Bit6 (973~997) 25 985, Bit14 (967~991) 25 979,
1954 00:56:19.434824 TX Bit7 (976~998) 23 987, Bit15 (969~993) 25 981,
1955 00:56:19.434873
1956 00:56:19.434925 Write Rank1 MR14 =0x1a
1957 00:56:19.434972
1958 00:56:19.435019 CH=0, VrefRange= 0, VrefLevel = 26
1959 00:56:19.435067 TX Bit0 (977~1002) 26 989, Bit8 (966~990) 25 978,
1960 00:56:19.435114 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1961 00:56:19.435165 TX Bit2 (976~999) 24 987, Bit10 (972~995) 24 983,
1962 00:56:19.435213 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1963 00:56:19.435260 TX Bit4 (976~1001) 26 988, Bit12 (967~991) 25 979,
1964 00:56:19.435307 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1965 00:56:19.435355 TX Bit6 (972~996) 25 984, Bit14 (967~990) 24 978,
1966 00:56:19.435406 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
1967 00:56:19.435482
1968 00:56:19.435556 Write Rank1 MR14 =0x1c
1969 00:56:19.435631
1970 00:56:19.435872 CH=0, VrefRange= 0, VrefLevel = 28
1971 00:56:19.435952 TX Bit0 (977~1002) 26 989, Bit8 (966~990) 25 978,
1972 00:56:19.436029 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1973 00:56:19.580902 TX Bit2 (976~999) 24 987, Bit10 (972~995) 24 983,
1974 00:56:19.581031 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1975 00:56:19.581118 TX Bit4 (976~1001) 26 988, Bit12 (967~991) 25 979,
1976 00:56:19.581205 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1977 00:56:19.581285 TX Bit6 (972~996) 25 984, Bit14 (967~990) 24 978,
1978 00:56:19.581364 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
1979 00:56:19.581445
1980 00:56:19.581522 Write Rank1 MR14 =0x1e
1981 00:56:19.581597
1982 00:56:19.581676 CH=0, VrefRange= 0, VrefLevel = 30
1983 00:56:19.581754 TX Bit0 (977~1002) 26 989, Bit8 (966~990) 25 978,
1984 00:56:19.581831 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1985 00:56:19.581910 TX Bit2 (976~999) 24 987, Bit10 (972~995) 24 983,
1986 00:56:19.581998 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1987 00:56:19.582077 TX Bit4 (976~1001) 26 988, Bit12 (967~991) 25 979,
1988 00:56:19.582171 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
1989 00:56:19.582302 TX Bit6 (972~996) 25 984, Bit14 (967~990) 24 978,
1990 00:56:19.582380 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
1991 00:56:19.582433
1992 00:56:19.582482 Write Rank1 MR14 =0x20
1993 00:56:19.582529
1994 00:56:19.582577 CH=0, VrefRange= 0, VrefLevel = 32
1995 00:56:19.582629 TX Bit0 (977~1002) 26 989, Bit8 (966~990) 25 978,
1996 00:56:19.582679 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1997 00:56:19.582728 TX Bit2 (976~999) 24 987, Bit10 (972~995) 24 983,
1998 00:56:19.582776 TX Bit3 (970~994) 25 982, Bit11 (967~991) 25 979,
1999 00:56:19.582823 TX Bit4 (976~1001) 26 988, Bit12 (967~991) 25 979,
2000 00:56:19.582874 TX Bit5 (971~995) 25 983, Bit13 (967~990) 24 978,
2001 00:56:19.582923 TX Bit6 (972~996) 25 984, Bit14 (967~990) 24 978,
2002 00:56:19.582970 TX Bit7 (975~998) 24 986, Bit15 (968~992) 25 980,
2003 00:56:19.583017
2004 00:56:19.583064
2005 00:56:19.583114 TX Vref found, early break! 368< 376
2006 00:56:19.583164 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
2007 00:56:19.583212 u1DelayCellOfst[0]=9 cells (7 PI)
2008 00:56:19.583259 u1DelayCellOfst[1]=7 cells (6 PI)
2009 00:56:19.583306 u1DelayCellOfst[2]=6 cells (5 PI)
2010 00:56:19.583360 u1DelayCellOfst[3]=0 cells (0 PI)
2011 00:56:19.583415 u1DelayCellOfst[4]=7 cells (6 PI)
2012 00:56:19.583470 u1DelayCellOfst[5]=1 cells (1 PI)
2013 00:56:19.583518 u1DelayCellOfst[6]=2 cells (2 PI)
2014 00:56:19.583565 u1DelayCellOfst[7]=5 cells (4 PI)
2015 00:56:19.583618 Byte0, DQ PI dly=982, DQM PI dly= 985
2016 00:56:19.583667 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
2017 00:56:19.583714
2018 00:56:19.583761 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
2019 00:56:19.583809
2020 00:56:19.583861 u1DelayCellOfst[8]=0 cells (0 PI)
2021 00:56:19.583909 u1DelayCellOfst[9]=0 cells (0 PI)
2022 00:56:19.583956 u1DelayCellOfst[10]=6 cells (5 PI)
2023 00:56:19.584003 u1DelayCellOfst[11]=1 cells (1 PI)
2024 00:56:19.584050 u1DelayCellOfst[12]=1 cells (1 PI)
2025 00:56:19.584111 u1DelayCellOfst[13]=0 cells (0 PI)
2026 00:56:19.584186 u1DelayCellOfst[14]=0 cells (0 PI)
2027 00:56:19.584261 u1DelayCellOfst[15]=2 cells (2 PI)
2028 00:56:19.584338 Byte1, DQ PI dly=978, DQM PI dly= 980
2029 00:56:19.584415 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2030 00:56:19.584489
2031 00:56:19.584564 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2032 00:56:19.584643
2033 00:56:19.584718 Write Rank1 MR14 =0x1a
2034 00:56:19.584793
2035 00:56:19.584870 Final TX Range 0 Vref 26
2036 00:56:19.584945
2037 00:56:19.585020 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2038 00:56:19.585098
2039 00:56:19.585175 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2040 00:56:19.585252 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2041 00:56:19.585332 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2042 00:56:19.585408 Write Rank1 MR3 =0xb0
2043 00:56:19.585492 DramC Write-DBI on
2044 00:56:19.585581 ==
2045 00:56:19.585671 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2046 00:56:19.585749 fsp= 1, odt_onoff= 1, Byte mode= 0
2047 00:56:19.585828 ==
2048 00:56:19.585905 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2049 00:56:19.585980
2050 00:56:19.586059 Begin, DQ Scan Range 700~764
2051 00:56:19.586134
2052 00:56:19.586208
2053 00:56:19.586304 TX Vref Scan disable
2054 00:56:19.586354 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2055 00:56:19.586415 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2056 00:56:19.586465 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2057 00:56:19.586525 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2058 00:56:19.586608 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2059 00:56:19.586690 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2060 00:56:19.586770 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2061 00:56:19.586829 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2062 00:56:19.586880 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2063 00:56:19.586928 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2064 00:56:19.586977 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
2065 00:56:19.587026 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2066 00:56:19.587079 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2067 00:56:19.587129 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2068 00:56:19.587177 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2069 00:56:19.587225 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2070 00:56:19.587274 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2071 00:56:19.587327 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2072 00:56:19.587377 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2073 00:56:19.587425 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2074 00:56:19.587474 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2075 00:56:19.587525 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2076 00:56:19.587575 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2077 00:56:19.587623 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2078 00:56:19.587671 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2079 00:56:19.587719 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
2080 00:56:19.587770 Byte0, DQ PI dly=730, DQM PI dly= 730
2081 00:56:19.588015 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
2082 00:56:19.588070
2083 00:56:19.588118 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
2084 00:56:19.588167
2085 00:56:19.588215 Byte1, DQ PI dly=722, DQM PI dly= 722
2086 00:56:19.588268 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 18)
2087 00:56:19.588345
2088 00:56:19.588421 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 18)
2089 00:56:19.588496
2090 00:56:19.588576 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2091 00:56:19.588653 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2092 00:56:19.588731 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2093 00:56:19.588809 Write Rank1 MR3 =0x30
2094 00:56:19.588895 DramC Write-DBI off
2095 00:56:19.588981
2096 00:56:19.589067 [DATLAT]
2097 00:56:19.589144 Freq=1600, CH0 RK1, use_rxtx_scan=0
2098 00:56:19.589219
2099 00:56:19.589297 DATLAT Default: 0x10
2100 00:56:19.589372 7, 0xFFFF, sum=0
2101 00:56:19.589449 8, 0xFFFF, sum=0
2102 00:56:19.589530 9, 0xFFFF, sum=0
2103 00:56:19.589616 10, 0xFFFF, sum=0
2104 00:56:19.589696 11, 0xFFFF, sum=0
2105 00:56:19.589781 12, 0xFFFF, sum=0
2106 00:56:19.589860 13, 0xFFFF, sum=0
2107 00:56:19.589936 14, 0x0, sum=1
2108 00:56:19.590023 15, 0x0, sum=2
2109 00:56:19.590101 16, 0x0, sum=3
2110 00:56:19.590178 17, 0x0, sum=4
2111 00:56:19.590274 pattern=2 first_step=14 total pass=5 best_step=16
2112 00:56:19.590337 ==
2113 00:56:19.590386 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2114 00:56:19.590435 fsp= 1, odt_onoff= 1, Byte mode= 0
2115 00:56:19.590487 ==
2116 00:56:19.590537 Start DQ dly to find pass range UseTestEngine =1
2117 00:56:19.590585 x-axis: bit #, y-axis: DQ dly (-127~63)
2118 00:56:19.590633 RX Vref Scan = 0
2119 00:56:19.590680 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2120 00:56:19.590740 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2121 00:56:19.590818 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2122 00:56:19.590894 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2123 00:56:19.590974 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2124 00:56:19.591052 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2125 00:56:19.591121 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2126 00:56:19.591171 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2127 00:56:19.591227 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2128 00:56:19.591276 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2129 00:56:19.591325 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2130 00:56:19.591375 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2131 00:56:19.591424 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2132 00:56:19.591479 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2133 00:56:19.591528 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2134 00:56:19.591577 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2135 00:56:19.591624 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2136 00:56:19.591672 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2137 00:56:19.591727 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2138 00:56:19.591776 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2139 00:56:19.591825 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2140 00:56:19.591874 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2141 00:56:19.591922 -4, [0] xxxoxxxx xxxxxxxx [MSB]
2142 00:56:19.591976 -3, [0] xxxoxxxx xxxxxxxx [MSB]
2143 00:56:19.592025 -2, [0] xxxoxoxx xxxxxxxx [MSB]
2144 00:56:19.592073 -1, [0] xxxoxoxx xxxxxxxx [MSB]
2145 00:56:19.592122 0, [0] xxxoxoxx oxxoxxxx [MSB]
2146 00:56:19.592181 1, [0] xxxoxoox oxxoxoxx [MSB]
2147 00:56:19.592237 2, [0] xxxoxooo ooxoooox [MSB]
2148 00:56:19.592302 3, [0] xxxoxooo ooxooooo [MSB]
2149 00:56:19.592361 4, [0] xxxoxooo ooxooooo [MSB]
2150 00:56:19.592410 5, [0] xoxoxooo ooxooooo [MSB]
2151 00:56:19.592466 6, [0] xoxooooo oooooooo [MSB]
2152 00:56:19.592515 32, [0] oooxoooo oooooooo [MSB]
2153 00:56:19.592564 33, [0] oooxoooo oooooooo [MSB]
2154 00:56:19.592612 34, [0] oooxoxoo oooooxoo [MSB]
2155 00:56:19.592660 35, [0] oooxoxox oooxoxxo [MSB]
2156 00:56:19.592714 36, [0] oooxoxxx xooxoxxo [MSB]
2157 00:56:19.592763 37, [0] oooxoxxx xxoxoxxo [MSB]
2158 00:56:19.592812 38, [0] oooxoxxx xxoxxxxo [MSB]
2159 00:56:19.592860 39, [0] oooxoxxx xxoxxxxx [MSB]
2160 00:56:19.592908 40, [0] ooxxoxxx xxoxxxxx [MSB]
2161 00:56:19.592979 41, [0] oxxxxxxx xxxxxxxx [MSB]
2162 00:56:19.593056 42, [0] oxxxxxxx xxxxxxxx [MSB]
2163 00:56:19.593133 43, [0] xxxxxxxx xxxxxxxx [MSB]
2164 00:56:19.593213 iDelay=43, Bit 0, Center 24 (7 ~ 42) 36
2165 00:56:19.593290 iDelay=43, Bit 1, Center 22 (5 ~ 40) 36
2166 00:56:19.593365 iDelay=43, Bit 2, Center 23 (7 ~ 39) 33
2167 00:56:19.593443 iDelay=43, Bit 3, Center 13 (-4 ~ 31) 36
2168 00:56:19.593519 iDelay=43, Bit 4, Center 23 (6 ~ 40) 35
2169 00:56:19.593594 iDelay=43, Bit 5, Center 15 (-2 ~ 33) 36
2170 00:56:19.593669 iDelay=43, Bit 6, Center 18 (1 ~ 35) 35
2171 00:56:19.593719 iDelay=43, Bit 7, Center 18 (2 ~ 34) 33
2172 00:56:19.593777 iDelay=43, Bit 8, Center 17 (0 ~ 35) 36
2173 00:56:19.593825 iDelay=43, Bit 9, Center 19 (2 ~ 36) 35
2174 00:56:19.593881 iDelay=43, Bit 10, Center 23 (6 ~ 40) 35
2175 00:56:19.593962 iDelay=43, Bit 11, Center 17 (0 ~ 34) 35
2176 00:56:19.594039 iDelay=43, Bit 12, Center 19 (2 ~ 37) 36
2177 00:56:19.594115 iDelay=43, Bit 13, Center 17 (1 ~ 33) 33
2178 00:56:19.594199 iDelay=43, Bit 14, Center 18 (2 ~ 34) 33
2179 00:56:19.594296 iDelay=43, Bit 15, Center 20 (3 ~ 38) 36
2180 00:56:19.594344 ==
2181 00:56:19.594397 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2182 00:56:19.594448 fsp= 1, odt_onoff= 1, Byte mode= 0
2183 00:56:19.594497 ==
2184 00:56:19.594544 DQS Delay:
2185 00:56:19.594591 DQS0 = 0, DQS1 = 0
2186 00:56:19.594641 DQM Delay:
2187 00:56:19.594691 DQM0 = 19, DQM1 = 18
2188 00:56:19.594738 DQ Delay:
2189 00:56:19.594785 DQ0 =24, DQ1 =22, DQ2 =23, DQ3 =13
2190 00:56:19.594832 DQ4 =23, DQ5 =15, DQ6 =18, DQ7 =18
2191 00:56:19.594879 DQ8 =17, DQ9 =19, DQ10 =23, DQ11 =17
2192 00:56:19.594932 DQ12 =19, DQ13 =17, DQ14 =18, DQ15 =20
2193 00:56:19.594980
2194 00:56:19.595027
2195 00:56:19.595074
2196 00:56:19.595121 [DramC_TX_OE_Calibration] TA2
2197 00:56:19.595174 Original DQ_B0 (3 6) =30, OEN = 27
2198 00:56:19.595222 Original DQ_B1 (3 6) =30, OEN = 27
2199 00:56:19.595269 23, 0x0, End_B0=23 End_B1=23
2200 00:56:19.595317 24, 0x0, End_B0=24 End_B1=24
2201 00:56:19.595366 25, 0x0, End_B0=25 End_B1=25
2202 00:56:19.595419 26, 0x0, End_B0=26 End_B1=26
2203 00:56:19.595467 27, 0x0, End_B0=27 End_B1=27
2204 00:56:19.595515 28, 0x0, End_B0=28 End_B1=28
2205 00:56:19.595574 29, 0x0, End_B0=29 End_B1=29
2206 00:56:19.595625 30, 0x0, End_B0=30 End_B1=30
2207 00:56:19.595684 31, 0xFFFF, End_B0=30 End_B1=30
2208 00:56:19.595733 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2209 00:56:19.595800 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2210 00:56:19.595849
2211 00:56:19.595903
2212 00:56:19.595951 Write Rank1 MR23 =0x3f
2213 00:56:19.595999 [DQSOSC]
2214 00:56:19.596235 [DQSOSCAuto] RK1, (LSB)MR18= 0x8d, (MSB)MR19= 0x3, tDQSOscB0 = 346 ps tDQSOscB1 = 0 ps
2215 00:56:19.596291 CH0_RK1: MR19=0x3, MR18=0x8D, DQSOSC=346, MR23=63, INC=20, DEC=30
2216 00:56:19.596340 Write Rank1 MR23 =0x3f
2217 00:56:19.596395 [DQSOSC]
2218 00:56:19.596444 [DQSOSCAuto] RK1, (LSB)MR18= 0x8c, (MSB)MR19= 0x3, tDQSOscB0 = 346 ps tDQSOscB1 = 0 ps
2219 00:56:19.596492 CH0 RK1: MR19=3, MR18=8C
2220 00:56:19.596539 [RxdqsGatingPostProcess] freq 1600
2221 00:56:19.596587 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2222 00:56:19.596641 Rank: 0
2223 00:56:19.596689 best DQS0 dly(2T, 0.5T) = (2, 5)
2224 00:56:19.596737 best DQS1 dly(2T, 0.5T) = (2, 5)
2225 00:56:19.596784 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2226 00:56:19.596832 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2227 00:56:19.596885 Rank: 1
2228 00:56:19.596933 best DQS0 dly(2T, 0.5T) = (2, 6)
2229 00:56:19.596981 best DQS1 dly(2T, 0.5T) = (2, 6)
2230 00:56:19.597029 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2231 00:56:19.597076 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2232 00:56:19.597129 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2233 00:56:19.597178 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2234 00:56:19.597225 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2235 00:56:19.597274 Write Rank0 MR13 =0x59
2236 00:56:19.597321 ==
2237 00:56:19.597375 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2238 00:56:19.597424 fsp= 1, odt_onoff= 1, Byte mode= 0
2239 00:56:19.597472 ==
2240 00:56:19.597520 === u2Vref_new: 0x56 --> 0x3a
2241 00:56:19.597568 === u2Vref_new: 0x58 --> 0x58
2242 00:56:19.597619 === u2Vref_new: 0x5a --> 0x5a
2243 00:56:19.597667 === u2Vref_new: 0x5c --> 0x78
2244 00:56:19.597714 === u2Vref_new: 0x5e --> 0x7a
2245 00:56:19.597762 === u2Vref_new: 0x60 --> 0x90
2246 00:56:19.597809
2247 00:56:19.597861 CBT Vref found, early break!
2248 00:56:19.597937 [CA 0] Center 37 (11~63) winsize 53
2249 00:56:19.598012 [CA 1] Center 36 (9~63) winsize 55
2250 00:56:19.598087 [CA 2] Center 33 (4~63) winsize 60
2251 00:56:19.598165 [CA 3] Center 34 (5~63) winsize 59
2252 00:56:19.598283 [CA 4] Center 34 (6~63) winsize 58
2253 00:56:19.598381 [CA 5] Center 28 (-1~57) winsize 59
2254 00:56:19.598457
2255 00:56:19.598534 [CATrainingPosCal] consider 1 rank data
2256 00:56:19.598610 u2DelayCellTimex100 = 753/100 ps
2257 00:56:19.598662 CA0 delay=37 (11~63),Diff = 9 PI (11 cell)
2258 00:56:19.598710 CA1 delay=36 (9~63),Diff = 8 PI (10 cell)
2259 00:56:19.598770 CA2 delay=33 (4~63),Diff = 5 PI (6 cell)
2260 00:56:19.598817 CA3 delay=34 (5~63),Diff = 6 PI (7 cell)
2261 00:56:19.598871 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2262 00:56:19.598919 CA5 delay=28 (-1~57),Diff = 0 PI (0 cell)
2263 00:56:19.598967
2264 00:56:19.599014 CA PerBit enable=1, Macro0, CA PI delay=28
2265 00:56:19.599063 === u2Vref_new: 0x56 --> 0x3a
2266 00:56:19.599117
2267 00:56:19.599164 Vref(ca) range 1: 22
2268 00:56:19.599506
2269 00:56:19.599564 CS Dly= 12 (43-0-32)
2270 00:56:19.602722 Write Rank0 MR13 =0xd8
2271 00:56:19.602800 Write Rank0 MR13 =0xd8
2272 00:56:19.606142 Write Rank0 MR12 =0x56
2273 00:56:19.609665 Write Rank1 MR13 =0x59
2274 00:56:19.609743 ==
2275 00:56:19.612994 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2276 00:56:19.616460 fsp= 1, odt_onoff= 1, Byte mode= 0
2277 00:56:19.616551 ==
2278 00:56:19.619916 === u2Vref_new: 0x56 --> 0x3a
2279 00:56:19.622719 === u2Vref_new: 0x58 --> 0x58
2280 00:56:19.625963 === u2Vref_new: 0x5a --> 0x5a
2281 00:56:19.629281 === u2Vref_new: 0x5c --> 0x78
2282 00:56:19.632669 === u2Vref_new: 0x5e --> 0x7a
2283 00:56:19.635995 === u2Vref_new: 0x60 --> 0x90
2284 00:56:19.639338 [CA 0] Center 37 (12~63) winsize 52
2285 00:56:19.642787 [CA 1] Center 35 (8~63) winsize 56
2286 00:56:19.642879 [CA 2] Center 33 (4~63) winsize 60
2287 00:56:19.646687 [CA 3] Center 34 (5~63) winsize 59
2288 00:56:19.649436 [CA 4] Center 35 (7~63) winsize 57
2289 00:56:19.652875 [CA 5] Center 27 (-1~56) winsize 58
2290 00:56:19.652968
2291 00:56:19.656542 [CATrainingPosCal] consider 2 rank data
2292 00:56:19.659370 u2DelayCellTimex100 = 753/100 ps
2293 00:56:19.662781 CA0 delay=37 (12~63),Diff = 10 PI (12 cell)
2294 00:56:19.669620 CA1 delay=36 (9~63),Diff = 9 PI (11 cell)
2295 00:56:19.673000 CA2 delay=33 (4~63),Diff = 6 PI (7 cell)
2296 00:56:19.676607 CA3 delay=34 (5~63),Diff = 7 PI (9 cell)
2297 00:56:19.679733 CA4 delay=35 (7~63),Diff = 8 PI (10 cell)
2298 00:56:19.683564 CA5 delay=27 (-1~56),Diff = 0 PI (0 cell)
2299 00:56:19.683692
2300 00:56:19.686682 CA PerBit enable=1, Macro0, CA PI delay=27
2301 00:56:19.689972 === u2Vref_new: 0x56 --> 0x3a
2302 00:56:19.690068
2303 00:56:19.690150 Vref(ca) range 1: 22
2304 00:56:19.693259
2305 00:56:19.693349 CS Dly= 11 (42-0-32)
2306 00:56:19.696513 Write Rank1 MR13 =0xd8
2307 00:56:19.696603 Write Rank1 MR13 =0xd8
2308 00:56:19.699934 Write Rank1 MR12 =0x56
2309 00:56:19.703328 [RankSwap] Rank num 2, (Multi 1), Rank 0
2310 00:56:19.706858 Write Rank0 MR2 =0xad
2311 00:56:19.706927 [Write Leveling]
2312 00:56:19.710376 delay byte0 byte1 byte2 byte3
2313 00:56:19.710445
2314 00:56:19.710500 10 0 0
2315 00:56:19.713826 11 0 0
2316 00:56:19.713917 12 0 0
2317 00:56:19.716927 13 0 0
2318 00:56:19.717017 14 0 0
2319 00:56:19.719868 15 0 0
2320 00:56:19.719958 16 0 0
2321 00:56:19.720039 17 0 0
2322 00:56:19.723885 18 0 0
2323 00:56:19.723947 19 0 0
2324 00:56:19.727079 20 0 0
2325 00:56:19.727144 21 0 0
2326 00:56:19.727203 22 0 0
2327 00:56:19.730195 23 0 0
2328 00:56:19.730316 24 0 0
2329 00:56:19.733728 25 0 0
2330 00:56:19.733804 26 0 0
2331 00:56:19.733864 27 0 0
2332 00:56:19.736870 28 0 0
2333 00:56:19.736953 29 0 0
2334 00:56:19.740130 30 0 0
2335 00:56:19.740208 31 0 0
2336 00:56:19.740268 32 0 0
2337 00:56:19.743450 33 0 ff
2338 00:56:19.743527 34 0 ff
2339 00:56:19.747138 35 0 ff
2340 00:56:19.747253 36 0 ff
2341 00:56:19.750147 37 0 ff
2342 00:56:19.750244 38 ff ff
2343 00:56:19.753532 39 ff ff
2344 00:56:19.753640 40 ff ff
2345 00:56:19.757295 41 ff ff
2346 00:56:19.757376 42 ff ff
2347 00:56:19.757434 43 ff ff
2348 00:56:19.760453 44 ff ff
2349 00:56:19.763946 pass bytecount = 0xff (0xff: all bytes pass)
2350 00:56:19.764016
2351 00:56:19.767385 DQS0 dly: 38
2352 00:56:19.767521 DQS1 dly: 33
2353 00:56:19.767597 Write Rank0 MR2 =0x2d
2354 00:56:19.774112 [RankSwap] Rank num 2, (Multi 1), Rank 0
2355 00:56:19.774238 Write Rank0 MR1 =0xd6
2356 00:56:19.774362 [Gating]
2357 00:56:19.776951 ==
2358 00:56:19.780478 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2359 00:56:19.783822 fsp= 1, odt_onoff= 1, Byte mode= 0
2360 00:56:19.783920 ==
2361 00:56:19.787593 3 1 0 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2362 00:56:19.794110 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2363 00:56:19.797519 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2364 00:56:19.800703 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2365 00:56:19.803863 3 1 16 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2366 00:56:19.811029 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2367 00:56:19.814448 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2368 00:56:19.817776 3 1 28 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2369 00:56:19.823947 3 2 0 |1a1a 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2370 00:56:19.827497 3 2 4 |3d3d 1818 |(11 11)(11 11) |(1 1)(0 0)| 0
2371 00:56:19.830716 3 2 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2372 00:56:19.837335 3 2 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2373 00:56:19.841283 3 2 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2374 00:56:19.844072 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2375 00:56:19.847471 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2376 00:56:19.854556 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2377 00:56:19.857614 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2378 00:56:19.861326 3 3 4 |202 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2379 00:56:19.867763 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2380 00:56:19.870998 [Byte 0] Lead/lag Transition tap number (1)
2381 00:56:19.874469 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2382 00:56:19.877638 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2383 00:56:19.884745 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2384 00:56:19.887988 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2385 00:56:19.891358 3 3 28 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2386 00:56:19.897667 3 4 0 |c0c 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2387 00:56:19.901167 3 4 4 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2388 00:56:19.904653 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2389 00:56:19.908068 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2390 00:56:19.914571 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2391 00:56:19.917988 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2392 00:56:19.920985 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2393 00:56:19.927943 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2394 00:56:19.931376 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2395 00:56:19.934334 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2396 00:56:19.941565 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2397 00:56:19.944721 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2398 00:56:19.947824 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2399 00:56:19.954650 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2400 00:56:19.958024 [Byte 0] Lead/lag falling Transition (3, 5, 20)
2401 00:56:19.961581 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2402 00:56:19.964315 [Byte 0] Lead/lag Transition tap number (2)
2403 00:56:19.971076 [Byte 1] Lead/lag falling Transition (3, 5, 24)
2404 00:56:19.974556 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2405 00:56:19.977929 3 6 0 |606 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2406 00:56:19.981291 [Byte 1] Lead/lag Transition tap number (3)
2407 00:56:19.988187 3 6 4 |4646 404 |(0 0)(11 11) |(0 0)(0 0)| 0
2408 00:56:19.988264 [Byte 0]First pass (3, 6, 4)
2409 00:56:19.994783 3 6 8 |4646 4646 |(0 0)(10 10) |(0 0)(0 0)| 0
2410 00:56:19.998014 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2411 00:56:20.001504 [Byte 1]First pass (3, 6, 12)
2412 00:56:20.004868 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2413 00:56:20.008224 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2414 00:56:20.011745 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2415 00:56:20.014579 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2416 00:56:20.021560 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2417 00:56:20.025008 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2418 00:56:20.028123 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2419 00:56:20.031718 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2420 00:56:20.034737 All bytes gating window > 1UI, Early break!
2421 00:56:20.034812
2422 00:56:20.038428 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 24)
2423 00:56:20.038495
2424 00:56:20.045227 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 30)
2425 00:56:20.045302
2426 00:56:20.045361
2427 00:56:20.045415
2428 00:56:20.048384 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 24)
2429 00:56:20.048460
2430 00:56:20.051713 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
2431 00:56:20.051804
2432 00:56:20.051864
2433 00:56:20.054868 Write Rank0 MR1 =0x56
2434 00:56:20.054968
2435 00:56:20.058079 best RODT dly(2T, 0.5T) = (2, 2)
2436 00:56:20.058155
2437 00:56:20.061554 best RODT dly(2T, 0.5T) = (2, 2)
2438 00:56:20.061630 ==
2439 00:56:20.065146 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2440 00:56:20.068512 fsp= 1, odt_onoff= 1, Byte mode= 0
2441 00:56:20.068578 ==
2442 00:56:20.074860 Start DQ dly to find pass range UseTestEngine =0
2443 00:56:20.078390 x-axis: bit #, y-axis: DQ dly (-127~63)
2444 00:56:20.078466 RX Vref Scan = 0
2445 00:56:20.081779 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2446 00:56:20.085139 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2447 00:56:20.088413 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2448 00:56:20.091915 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2449 00:56:20.092013 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2450 00:56:20.095082 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2451 00:56:20.098111 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2452 00:56:20.101544 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2453 00:56:20.105113 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2454 00:56:20.108162 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2455 00:56:20.111902 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2456 00:56:20.114783 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2457 00:56:20.114862 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2458 00:56:20.118152 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2459 00:56:20.122039 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2460 00:56:20.124832 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2461 00:56:20.128504 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2462 00:56:20.131716 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2463 00:56:20.135121 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2464 00:56:20.138562 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2465 00:56:20.138631 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2466 00:56:20.141755 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2467 00:56:20.145255 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2468 00:56:20.148434 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2469 00:56:20.151994 -2, [0] xxxxxxxx xxxxxxxo [MSB]
2470 00:56:20.154896 -1, [0] xxxxxxxx xxxxxxxo [MSB]
2471 00:56:20.154974 0, [0] xxxoxxxx xxxxxxxo [MSB]
2472 00:56:20.158661 1, [0] xxxoxxxx xxoxxxxo [MSB]
2473 00:56:20.161678 2, [0] xxooxxxo oxoxxxxo [MSB]
2474 00:56:20.165048 3, [0] xxoooxxo ooooxxoo [MSB]
2475 00:56:20.168639 4, [0] xxoooxxo ooooxooo [MSB]
2476 00:56:20.172389 5, [0] xooooxxo oooooooo [MSB]
2477 00:56:20.172467 6, [0] xooooooo oooooooo [MSB]
2478 00:56:20.175640 31, [0] oooooooo oooooooo [MSB]
2479 00:56:20.178685 32, [0] oooxoooo oooooooo [MSB]
2480 00:56:20.182117 33, [0] ooxxoooo ooooooox [MSB]
2481 00:56:20.185471 34, [0] ooxxoooo oxooooox [MSB]
2482 00:56:20.188396 35, [0] ooxxoooo oxxxooox [MSB]
2483 00:56:20.192280 36, [0] ooxxoooo xxxxooxx [MSB]
2484 00:56:20.192357 37, [0] ooxxxoox xxxxoxxx [MSB]
2485 00:56:20.195074 38, [0] ooxxxoox xxxxoxxx [MSB]
2486 00:56:20.198426 39, [0] ooxxxoox xxxxxxxx [MSB]
2487 00:56:20.201884 40, [0] ooxxxoox xxxxxxxx [MSB]
2488 00:56:20.205479 41, [0] oxxxxoxx xxxxxxxx [MSB]
2489 00:56:20.208691 42, [0] xxxxxxxx xxxxxxxx [MSB]
2490 00:56:20.211850 iDelay=42, Bit 0, Center 24 (7 ~ 41) 35
2491 00:56:20.215486 iDelay=42, Bit 1, Center 22 (5 ~ 40) 36
2492 00:56:20.218583 iDelay=42, Bit 2, Center 17 (2 ~ 32) 31
2493 00:56:20.222092 iDelay=42, Bit 3, Center 15 (0 ~ 31) 32
2494 00:56:20.225401 iDelay=42, Bit 4, Center 19 (3 ~ 36) 34
2495 00:56:20.228811 iDelay=42, Bit 5, Center 23 (6 ~ 41) 36
2496 00:56:20.232153 iDelay=42, Bit 6, Center 23 (6 ~ 40) 35
2497 00:56:20.235732 iDelay=42, Bit 7, Center 19 (2 ~ 36) 35
2498 00:56:20.239157 iDelay=42, Bit 8, Center 18 (2 ~ 35) 34
2499 00:56:20.242082 iDelay=42, Bit 9, Center 18 (3 ~ 33) 31
2500 00:56:20.245549 iDelay=42, Bit 10, Center 17 (1 ~ 34) 34
2501 00:56:20.248784 iDelay=42, Bit 11, Center 18 (3 ~ 34) 32
2502 00:56:20.252060 iDelay=42, Bit 12, Center 21 (5 ~ 38) 34
2503 00:56:20.255620 iDelay=42, Bit 13, Center 20 (4 ~ 36) 33
2504 00:56:20.262166 iDelay=42, Bit 14, Center 19 (3 ~ 35) 33
2505 00:56:20.265652 iDelay=42, Bit 15, Center 15 (-2 ~ 32) 35
2506 00:56:20.265727 ==
2507 00:56:20.269085 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2508 00:56:20.272203 fsp= 1, odt_onoff= 1, Byte mode= 0
2509 00:56:20.272298 ==
2510 00:56:20.275725 DQS Delay:
2511 00:56:20.275800 DQS0 = 0, DQS1 = 0
2512 00:56:20.275884 DQM Delay:
2513 00:56:20.279125 DQM0 = 20, DQM1 = 18
2514 00:56:20.279201 DQ Delay:
2515 00:56:20.282218 DQ0 =24, DQ1 =22, DQ2 =17, DQ3 =15
2516 00:56:20.285629 DQ4 =19, DQ5 =23, DQ6 =23, DQ7 =19
2517 00:56:20.289022 DQ8 =18, DQ9 =18, DQ10 =17, DQ11 =18
2518 00:56:20.292433 DQ12 =21, DQ13 =20, DQ14 =19, DQ15 =15
2519 00:56:20.292522
2520 00:56:20.292582
2521 00:56:20.295999 DramC Write-DBI off
2522 00:56:20.296075 ==
2523 00:56:20.299048 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2524 00:56:20.302311 fsp= 1, odt_onoff= 1, Byte mode= 0
2525 00:56:20.302387 ==
2526 00:56:20.309293 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2527 00:56:20.309369
2528 00:56:20.309428 Begin, DQ Scan Range 929~1185
2529 00:56:20.312855
2530 00:56:20.312930
2531 00:56:20.312989 TX Vref Scan disable
2532 00:56:20.315524 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2533 00:56:20.319302 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2534 00:56:20.322415 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2535 00:56:20.325996 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2536 00:56:20.329225 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2537 00:56:20.335662 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2538 00:56:20.339267 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2539 00:56:20.342413 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2540 00:56:20.345928 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2541 00:56:20.349151 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2542 00:56:20.352408 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2543 00:56:20.355725 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2544 00:56:20.359205 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2545 00:56:20.362675 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2546 00:56:20.365961 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2547 00:56:20.369195 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2548 00:56:20.372507 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2549 00:56:20.375939 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2550 00:56:20.379479 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2551 00:56:20.382753 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2552 00:56:20.386215 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2553 00:56:20.389215 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2554 00:56:20.392579 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2555 00:56:20.399364 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2556 00:56:20.402820 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2557 00:56:20.406125 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2558 00:56:20.409591 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2559 00:56:20.412938 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2560 00:56:20.416135 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2561 00:56:20.419447 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2562 00:56:20.423003 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2563 00:56:20.426432 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2564 00:56:20.429842 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2565 00:56:20.433142 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2566 00:56:20.436420 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2567 00:56:20.439821 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2568 00:56:20.442763 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2569 00:56:20.446049 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2570 00:56:20.449625 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2571 00:56:20.452799 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2572 00:56:20.456179 969 |3 6 9|[0] xxxxxxxx xxxxxxxo [MSB]
2573 00:56:20.459491 970 |3 6 10|[0] xxxxxxxx ooxxxxxo [MSB]
2574 00:56:20.462716 971 |3 6 11|[0] xxxxxxxx ooooxxoo [MSB]
2575 00:56:20.466281 972 |3 6 12|[0] xxxxxxxx oooooxoo [MSB]
2576 00:56:20.469562 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
2577 00:56:20.476175 974 |3 6 14|[0] xxxoxxxx oooooooo [MSB]
2578 00:56:20.479435 975 |3 6 15|[0] xxooxxxx oooooooo [MSB]
2579 00:56:20.483080 976 |3 6 16|[0] xxoooxxx oooooooo [MSB]
2580 00:56:20.486029 977 |3 6 17|[0] xooooxxo oooooooo [MSB]
2581 00:56:20.489564 978 |3 6 18|[0] xooooooo oooooooo [MSB]
2582 00:56:20.492837 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2583 00:56:20.496413 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2584 00:56:20.502821 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2585 00:56:20.505950 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
2586 00:56:20.509861 996 |3 6 36|[0] ooxxoooo xxxxxxxx [MSB]
2587 00:56:20.512968 997 |3 6 37|[0] ooxxoooo xxxxxxxx [MSB]
2588 00:56:20.516546 998 |3 6 38|[0] ooxxoooo xxxxxxxx [MSB]
2589 00:56:20.519330 999 |3 6 39|[0] ooxxxoox xxxxxxxx [MSB]
2590 00:56:20.522891 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
2591 00:56:20.526060 Byte0, DQ PI dly=986, DQM PI dly= 986
2592 00:56:20.529424 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
2593 00:56:20.529515
2594 00:56:20.536368 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
2595 00:56:20.536436
2596 00:56:20.539795 Byte1, DQ PI dly=981, DQM PI dly= 981
2597 00:56:20.543304 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
2598 00:56:20.543374
2599 00:56:20.546565 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
2600 00:56:20.546654
2601 00:56:20.546737 ==
2602 00:56:20.553257 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2603 00:56:20.556211 fsp= 1, odt_onoff= 1, Byte mode= 0
2604 00:56:20.556291 ==
2605 00:56:20.559636 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2606 00:56:20.559711
2607 00:56:20.563415 Begin, DQ Scan Range 957~1021
2608 00:56:20.566407 Write Rank0 MR14 =0x0
2609 00:56:20.573456
2610 00:56:20.573529 CH=1, VrefRange= 0, VrefLevel = 0
2611 00:56:20.580398 TX Bit0 (981~998) 18 989, Bit8 (971~989) 19 980,
2612 00:56:20.583767 TX Bit1 (979~997) 19 988, Bit9 (971~988) 18 979,
2613 00:56:20.587160 TX Bit2 (977~991) 15 984, Bit10 (974~989) 16 981,
2614 00:56:20.593323 TX Bit3 (976~991) 16 983, Bit11 (975~991) 17 983,
2615 00:56:20.596830 TX Bit4 (977~994) 18 985, Bit12 (975~992) 18 983,
2616 00:56:20.603822 TX Bit5 (981~998) 18 989, Bit13 (976~991) 16 983,
2617 00:56:20.606940 TX Bit6 (982~998) 17 990, Bit14 (975~990) 16 982,
2618 00:56:20.610052 TX Bit7 (979~993) 15 986, Bit15 (970~987) 18 978,
2619 00:56:20.610128
2620 00:56:20.613425 Write Rank0 MR14 =0x2
2621 00:56:20.621680
2622 00:56:20.621757 CH=1, VrefRange= 0, VrefLevel = 2
2623 00:56:20.628498 TX Bit0 (981~998) 18 989, Bit8 (971~991) 21 981,
2624 00:56:20.632136 TX Bit1 (980~997) 18 988, Bit9 (971~989) 19 980,
2625 00:56:20.635100 TX Bit2 (977~992) 16 984, Bit10 (974~990) 17 982,
2626 00:56:20.641762 TX Bit3 (976~991) 16 983, Bit11 (974~991) 18 982,
2627 00:56:20.645460 TX Bit4 (978~994) 17 986, Bit12 (975~992) 18 983,
2628 00:56:20.652056 TX Bit5 (981~998) 18 989, Bit13 (976~991) 16 983,
2629 00:56:20.655271 TX Bit6 (981~998) 18 989, Bit14 (974~991) 18 982,
2630 00:56:20.658554 TX Bit7 (979~993) 15 986, Bit15 (970~988) 19 979,
2631 00:56:20.658631
2632 00:56:20.662339 Write Rank0 MR14 =0x4
2633 00:56:20.670446
2634 00:56:20.670522 CH=1, VrefRange= 0, VrefLevel = 4
2635 00:56:20.677017 TX Bit0 (981~999) 19 990, Bit8 (971~991) 21 981,
2636 00:56:20.680790 TX Bit1 (979~998) 20 988, Bit9 (971~989) 19 980,
2637 00:56:20.687137 TX Bit2 (977~992) 16 984, Bit10 (973~990) 18 981,
2638 00:56:20.690752 TX Bit3 (975~991) 17 983, Bit11 (974~992) 19 983,
2639 00:56:20.693604 TX Bit4 (977~995) 19 986, Bit12 (975~992) 18 983,
2640 00:56:20.700524 TX Bit5 (980~998) 19 989, Bit13 (975~991) 17 983,
2641 00:56:20.704088 TX Bit6 (981~999) 19 990, Bit14 (974~991) 18 982,
2642 00:56:20.707483 TX Bit7 (978~994) 17 986, Bit15 (969~989) 21 979,
2643 00:56:20.707551
2644 00:56:20.710693 Write Rank0 MR14 =0x6
2645 00:56:20.719032
2646 00:56:20.719130 CH=1, VrefRange= 0, VrefLevel = 6
2647 00:56:20.725595 TX Bit0 (981~999) 19 990, Bit8 (970~991) 22 980,
2648 00:56:20.728836 TX Bit1 (979~998) 20 988, Bit9 (971~991) 21 981,
2649 00:56:20.735461 TX Bit2 (977~993) 17 985, Bit10 (972~991) 20 981,
2650 00:56:20.739077 TX Bit3 (975~992) 18 983, Bit11 (973~991) 19 982,
2651 00:56:20.742434 TX Bit4 (977~995) 19 986, Bit12 (974~992) 19 983,
2652 00:56:20.749280 TX Bit5 (980~999) 20 989, Bit13 (975~992) 18 983,
2653 00:56:20.752626 TX Bit6 (980~999) 20 989, Bit14 (973~991) 19 982,
2654 00:56:20.755779 TX Bit7 (978~994) 17 986, Bit15 (969~989) 21 979,
2655 00:56:20.755846
2656 00:56:20.758919 Write Rank0 MR14 =0x8
2657 00:56:20.767541
2658 00:56:20.767618 CH=1, VrefRange= 0, VrefLevel = 8
2659 00:56:20.774690 TX Bit0 (981~999) 19 990, Bit8 (970~991) 22 980,
2660 00:56:20.777771 TX Bit1 (978~998) 21 988, Bit9 (970~991) 22 980,
2661 00:56:20.781180 TX Bit2 (976~993) 18 984, Bit10 (973~991) 19 982,
2662 00:56:20.787940 TX Bit3 (975~992) 18 983, Bit11 (973~992) 20 982,
2663 00:56:20.791113 TX Bit4 (977~996) 20 986, Bit12 (973~993) 21 983,
2664 00:56:20.797646 TX Bit5 (979~999) 21 989, Bit13 (974~992) 19 983,
2665 00:56:20.801006 TX Bit6 (980~999) 20 989, Bit14 (973~991) 19 982,
2666 00:56:20.804232 TX Bit7 (978~995) 18 986, Bit15 (969~990) 22 979,
2667 00:56:20.804299
2668 00:56:20.807537 Write Rank0 MR14 =0xa
2669 00:56:20.815972
2670 00:56:20.819221 CH=1, VrefRange= 0, VrefLevel = 10
2671 00:56:20.822438 TX Bit0 (980~999) 20 989, Bit8 (970~992) 23 981,
2672 00:56:20.826197 TX Bit1 (978~998) 21 988, Bit9 (970~991) 22 980,
2673 00:56:20.832723 TX Bit2 (976~993) 18 984, Bit10 (971~992) 22 981,
2674 00:56:20.836031 TX Bit3 (975~993) 19 984, Bit11 (973~992) 20 982,
2675 00:56:20.839436 TX Bit4 (977~997) 21 987, Bit12 (973~993) 21 983,
2676 00:56:20.846183 TX Bit5 (979~999) 21 989, Bit13 (974~992) 19 983,
2677 00:56:20.849207 TX Bit6 (979~999) 21 989, Bit14 (972~992) 21 982,
2678 00:56:20.852664 TX Bit7 (977~996) 20 986, Bit15 (969~990) 22 979,
2679 00:56:20.852754
2680 00:56:20.856338 Write Rank0 MR14 =0xc
2681 00:56:20.865007
2682 00:56:20.868190 CH=1, VrefRange= 0, VrefLevel = 12
2683 00:56:20.871506 TX Bit0 (979~1000) 22 989, Bit8 (970~992) 23 981,
2684 00:56:20.875016 TX Bit1 (978~998) 21 988, Bit9 (970~991) 22 980,
2685 00:56:20.881865 TX Bit2 (976~994) 19 985, Bit10 (971~992) 22 981,
2686 00:56:20.885014 TX Bit3 (975~993) 19 984, Bit11 (972~992) 21 982,
2687 00:56:20.888408 TX Bit4 (976~997) 22 986, Bit12 (972~993) 22 982,
2688 00:56:20.895126 TX Bit5 (978~999) 22 988, Bit13 (973~992) 20 982,
2689 00:56:20.898498 TX Bit6 (979~999) 21 989, Bit14 (972~992) 21 982,
2690 00:56:20.901740 TX Bit7 (977~997) 21 987, Bit15 (969~990) 22 979,
2691 00:56:20.901815
2692 00:56:20.904901 Write Rank0 MR14 =0xe
2693 00:56:20.913790
2694 00:56:20.917160 CH=1, VrefRange= 0, VrefLevel = 14
2695 00:56:20.920203 TX Bit0 (979~1000) 22 989, Bit8 (970~992) 23 981,
2696 00:56:20.923474 TX Bit1 (977~999) 23 988, Bit9 (970~992) 23 981,
2697 00:56:20.930153 TX Bit2 (976~994) 19 985, Bit10 (971~992) 22 981,
2698 00:56:20.934032 TX Bit3 (974~994) 21 984, Bit11 (972~992) 21 982,
2699 00:56:20.937098 TX Bit4 (976~998) 23 987, Bit12 (973~993) 21 983,
2700 00:56:20.943647 TX Bit5 (978~1000) 23 989, Bit13 (973~993) 21 983,
2701 00:56:20.947318 TX Bit6 (978~1000) 23 989, Bit14 (972~992) 21 982,
2702 00:56:20.953690 TX Bit7 (977~997) 21 987, Bit15 (969~991) 23 980,
2703 00:56:20.953765
2704 00:56:20.953825 Write Rank0 MR14 =0x10
2705 00:56:20.962773
2706 00:56:20.966386 CH=1, VrefRange= 0, VrefLevel = 16
2707 00:56:20.969763 TX Bit0 (979~1000) 22 989, Bit8 (970~992) 23 981,
2708 00:56:20.973186 TX Bit1 (977~999) 23 988, Bit9 (970~992) 23 981,
2709 00:56:20.979285 TX Bit2 (975~995) 21 985, Bit10 (970~992) 23 981,
2710 00:56:20.982824 TX Bit3 (974~995) 22 984, Bit11 (971~993) 23 982,
2711 00:56:20.986090 TX Bit4 (976~998) 23 987, Bit12 (972~994) 23 983,
2712 00:56:20.992638 TX Bit5 (978~1000) 23 989, Bit13 (973~993) 21 983,
2713 00:56:20.996101 TX Bit6 (979~1000) 22 989, Bit14 (971~992) 22 981,
2714 00:56:21.002652 TX Bit7 (977~998) 22 987, Bit15 (969~991) 23 980,
2715 00:56:21.002729
2716 00:56:21.002795 Write Rank0 MR14 =0x12
2717 00:56:21.012250
2718 00:56:21.015425 CH=1, VrefRange= 0, VrefLevel = 18
2719 00:56:21.018812 TX Bit0 (978~1000) 23 989, Bit8 (969~992) 24 980,
2720 00:56:21.022289 TX Bit1 (977~999) 23 988, Bit9 (970~992) 23 981,
2721 00:56:21.028923 TX Bit2 (975~996) 22 985, Bit10 (970~993) 24 981,
2722 00:56:21.032036 TX Bit3 (974~995) 22 984, Bit11 (971~993) 23 982,
2723 00:56:21.035416 TX Bit4 (976~998) 23 987, Bit12 (971~994) 24 982,
2724 00:56:21.042022 TX Bit5 (977~1000) 24 988, Bit13 (972~993) 22 982,
2725 00:56:21.045571 TX Bit6 (977~1000) 24 988, Bit14 (971~992) 22 981,
2726 00:56:21.048793 TX Bit7 (976~998) 23 987, Bit15 (968~991) 24 979,
2727 00:56:21.052064
2728 00:56:21.052141 Write Rank0 MR14 =0x14
2729 00:56:21.061431
2730 00:56:21.064559 CH=1, VrefRange= 0, VrefLevel = 20
2731 00:56:21.068217 TX Bit0 (979~1001) 23 990, Bit8 (969~993) 25 981,
2732 00:56:21.071089 TX Bit1 (977~999) 23 988, Bit9 (969~992) 24 980,
2733 00:56:21.078107 TX Bit2 (975~997) 23 986, Bit10 (970~993) 24 981,
2734 00:56:21.081663 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2735 00:56:21.084638 TX Bit4 (976~998) 23 987, Bit12 (972~994) 23 983,
2736 00:56:21.091574 TX Bit5 (977~1000) 24 988, Bit13 (972~994) 23 983,
2737 00:56:21.094829 TX Bit6 (978~1001) 24 989, Bit14 (971~993) 23 982,
2738 00:56:21.098455 TX Bit7 (976~998) 23 987, Bit15 (968~992) 25 980,
2739 00:56:21.098533
2740 00:56:21.101546 Write Rank0 MR14 =0x16
2741 00:56:21.110544
2742 00:56:21.113816 CH=1, VrefRange= 0, VrefLevel = 22
2743 00:56:21.117303 TX Bit0 (977~1001) 25 989, Bit8 (969~992) 24 980,
2744 00:56:21.120738 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
2745 00:56:21.127591 TX Bit2 (975~997) 23 986, Bit10 (970~993) 24 981,
2746 00:56:21.131117 TX Bit3 (973~997) 25 985, Bit11 (970~994) 25 982,
2747 00:56:21.134409 TX Bit4 (976~999) 24 987, Bit12 (971~995) 25 983,
2748 00:56:21.140980 TX Bit5 (977~1000) 24 988, Bit13 (972~994) 23 983,
2749 00:56:21.144194 TX Bit6 (977~1001) 25 989, Bit14 (970~993) 24 981,
2750 00:56:21.147924 TX Bit7 (976~999) 24 987, Bit15 (968~992) 25 980,
2751 00:56:21.148004
2752 00:56:21.150681 Write Rank0 MR14 =0x18
2753 00:56:21.160635
2754 00:56:21.163897 CH=1, VrefRange= 0, VrefLevel = 24
2755 00:56:21.166725 TX Bit0 (978~1002) 25 990, Bit8 (969~992) 24 980,
2756 00:56:21.170444 TX Bit1 (977~1000) 24 988, Bit9 (969~992) 24 980,
2757 00:56:21.177064 TX Bit2 (975~998) 24 986, Bit10 (969~993) 25 981,
2758 00:56:21.180370 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2759 00:56:21.183566 TX Bit4 (975~999) 25 987, Bit12 (971~994) 24 982,
2760 00:56:21.190315 TX Bit5 (977~1000) 24 988, Bit13 (971~993) 23 982,
2761 00:56:21.193694 TX Bit6 (977~1001) 25 989, Bit14 (970~993) 24 981,
2762 00:56:21.200145 TX Bit7 (976~999) 24 987, Bit15 (968~992) 25 980,
2763 00:56:21.200250
2764 00:56:21.200342 Write Rank0 MR14 =0x1a
2765 00:56:21.209666
2766 00:56:21.213325 CH=1, VrefRange= 0, VrefLevel = 26
2767 00:56:21.216475 TX Bit0 (977~1002) 26 989, Bit8 (969~992) 24 980,
2768 00:56:21.220155 TX Bit1 (976~1000) 25 988, Bit9 (969~992) 24 980,
2769 00:56:21.226621 TX Bit2 (974~998) 25 986, Bit10 (969~993) 25 981,
2770 00:56:21.229681 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2771 00:56:21.233297 TX Bit4 (976~999) 24 987, Bit12 (971~994) 24 982,
2772 00:56:21.239900 TX Bit5 (977~1000) 24 988, Bit13 (971~993) 23 982,
2773 00:56:21.243377 TX Bit6 (977~1001) 25 989, Bit14 (970~992) 23 981,
2774 00:56:21.250082 TX Bit7 (976~999) 24 987, Bit15 (968~992) 25 980,
2775 00:56:21.250178
2776 00:56:21.250264 Write Rank0 MR14 =0x1c
2777 00:56:21.259489
2778 00:56:21.262635 CH=1, VrefRange= 0, VrefLevel = 28
2779 00:56:21.266450 TX Bit0 (977~1002) 26 989, Bit8 (969~992) 24 980,
2780 00:56:21.269244 TX Bit1 (976~1000) 25 988, Bit9 (969~992) 24 980,
2781 00:56:21.276212 TX Bit2 (974~998) 25 986, Bit10 (969~993) 25 981,
2782 00:56:21.279479 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2783 00:56:21.282860 TX Bit4 (976~999) 24 987, Bit12 (971~994) 24 982,
2784 00:56:21.289677 TX Bit5 (977~1000) 24 988, Bit13 (971~993) 23 982,
2785 00:56:21.292746 TX Bit6 (977~1001) 25 989, Bit14 (970~992) 23 981,
2786 00:56:21.296142 TX Bit7 (976~999) 24 987, Bit15 (968~992) 25 980,
2787 00:56:21.299687
2788 00:56:21.299764 Write Rank0 MR14 =0x1e
2789 00:56:21.308872
2790 00:56:21.312206 CH=1, VrefRange= 0, VrefLevel = 30
2791 00:56:21.315631 TX Bit0 (977~1002) 26 989, Bit8 (969~992) 24 980,
2792 00:56:21.318944 TX Bit1 (976~1000) 25 988, Bit9 (969~992) 24 980,
2793 00:56:21.325700 TX Bit2 (974~998) 25 986, Bit10 (969~993) 25 981,
2794 00:56:21.329018 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2795 00:56:21.332253 TX Bit4 (976~999) 24 987, Bit12 (971~994) 24 982,
2796 00:56:21.339006 TX Bit5 (977~1000) 24 988, Bit13 (971~993) 23 982,
2797 00:56:21.342494 TX Bit6 (977~1001) 25 989, Bit14 (970~992) 23 981,
2798 00:56:21.345889 TX Bit7 (976~999) 24 987, Bit15 (968~992) 25 980,
2799 00:56:21.349027
2800 00:56:21.349104 Write Rank0 MR14 =0x20
2801 00:56:21.358195
2802 00:56:21.361823 CH=1, VrefRange= 0, VrefLevel = 32
2803 00:56:21.364740 TX Bit0 (977~1002) 26 989, Bit8 (969~992) 24 980,
2804 00:56:21.368286 TX Bit1 (976~1000) 25 988, Bit9 (969~992) 24 980,
2805 00:56:21.375017 TX Bit2 (974~998) 25 986, Bit10 (969~993) 25 981,
2806 00:56:21.378167 TX Bit3 (973~996) 24 984, Bit11 (970~994) 25 982,
2807 00:56:21.381305 TX Bit4 (976~999) 24 987, Bit12 (971~994) 24 982,
2808 00:56:21.388269 TX Bit5 (977~1000) 24 988, Bit13 (971~993) 23 982,
2809 00:56:21.391511 TX Bit6 (977~1001) 25 989, Bit14 (970~992) 23 981,
2810 00:56:21.397996 TX Bit7 (976~999) 24 987, Bit15 (968~992) 25 980,
2811 00:56:21.398075
2812 00:56:21.398135
2813 00:56:21.401476 TX Vref found, early break! 369< 370
2814 00:56:21.404647 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
2815 00:56:21.407846 u1DelayCellOfst[0]=6 cells (5 PI)
2816 00:56:21.411272 u1DelayCellOfst[1]=5 cells (4 PI)
2817 00:56:21.414965 u1DelayCellOfst[2]=2 cells (2 PI)
2818 00:56:21.418471 u1DelayCellOfst[3]=0 cells (0 PI)
2819 00:56:21.421560 u1DelayCellOfst[4]=3 cells (3 PI)
2820 00:56:21.421637 u1DelayCellOfst[5]=5 cells (4 PI)
2821 00:56:21.424745 u1DelayCellOfst[6]=6 cells (5 PI)
2822 00:56:21.427899 u1DelayCellOfst[7]=3 cells (3 PI)
2823 00:56:21.431335 Byte0, DQ PI dly=984, DQM PI dly= 986
2824 00:56:21.437957 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
2825 00:56:21.438035
2826 00:56:21.441633 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
2827 00:56:21.441710
2828 00:56:21.444806 u1DelayCellOfst[8]=0 cells (0 PI)
2829 00:56:21.448190 u1DelayCellOfst[9]=0 cells (0 PI)
2830 00:56:21.451611 u1DelayCellOfst[10]=1 cells (1 PI)
2831 00:56:21.454966 u1DelayCellOfst[11]=2 cells (2 PI)
2832 00:56:21.458101 u1DelayCellOfst[12]=2 cells (2 PI)
2833 00:56:21.458178 u1DelayCellOfst[13]=2 cells (2 PI)
2834 00:56:21.461806 u1DelayCellOfst[14]=1 cells (1 PI)
2835 00:56:21.464914 u1DelayCellOfst[15]=0 cells (0 PI)
2836 00:56:21.468389 Byte1, DQ PI dly=980, DQM PI dly= 981
2837 00:56:21.475119 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2838 00:56:21.475196
2839 00:56:21.478251 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2840 00:56:21.478328
2841 00:56:21.481495 Write Rank0 MR14 =0x1a
2842 00:56:21.481572
2843 00:56:21.481631 Final TX Range 0 Vref 26
2844 00:56:21.481687
2845 00:56:21.488389 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2846 00:56:21.488467
2847 00:56:21.494970 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2848 00:56:21.501489 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2849 00:56:21.511976 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2850 00:56:21.512054 Write Rank0 MR3 =0xb0
2851 00:56:21.515061 DramC Write-DBI on
2852 00:56:21.515139 ==
2853 00:56:21.518269 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2854 00:56:21.521814 fsp= 1, odt_onoff= 1, Byte mode= 0
2855 00:56:21.521892 ==
2856 00:56:21.528551 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2857 00:56:21.528628
2858 00:56:21.528688 Begin, DQ Scan Range 701~765
2859 00:56:21.528744
2860 00:56:21.528797
2861 00:56:21.531858 TX Vref Scan disable
2862 00:56:21.534933 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2863 00:56:21.538771 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2864 00:56:21.541714 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2865 00:56:21.544982 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2866 00:56:21.548395 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2867 00:56:21.551764 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2868 00:56:21.555472 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2869 00:56:21.558412 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2870 00:56:21.561811 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2871 00:56:21.565678 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2872 00:56:21.568548 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2873 00:56:21.572209 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2874 00:56:21.575534 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2875 00:56:21.581907 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2876 00:56:21.585156 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2877 00:56:21.588589 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2878 00:56:21.591831 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2879 00:56:21.594948 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2880 00:56:21.602483 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2881 00:56:21.605797 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2882 00:56:21.609433 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2883 00:56:21.612582 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2884 00:56:21.615615 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2885 00:56:21.619163 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2886 00:56:21.622340 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2887 00:56:21.625775 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2888 00:56:21.629225 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
2889 00:56:21.632571 Byte0, DQ PI dly=731, DQM PI dly= 731
2890 00:56:21.635693 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
2891 00:56:21.635771
2892 00:56:21.642292 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
2893 00:56:21.642384
2894 00:56:21.646095 Byte1, DQ PI dly=724, DQM PI dly= 724
2895 00:56:21.649011 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
2896 00:56:21.649087
2897 00:56:21.652257 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
2898 00:56:21.652335
2899 00:56:21.658951 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2900 00:56:21.665953 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2901 00:56:21.675876 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2902 00:56:21.675953 Write Rank0 MR3 =0x30
2903 00:56:21.678972 DramC Write-DBI off
2904 00:56:21.679048
2905 00:56:21.679106 [DATLAT]
2906 00:56:21.682547 Freq=1600, CH1 RK0, use_rxtx_scan=0
2907 00:56:21.682647
2908 00:56:21.685814 DATLAT Default: 0xf
2909 00:56:21.685889 7, 0xFFFF, sum=0
2910 00:56:21.688945 8, 0xFFFF, sum=0
2911 00:56:21.689023 9, 0xFFFF, sum=0
2912 00:56:21.689083 10, 0xFFFF, sum=0
2913 00:56:21.692533 11, 0xFFFF, sum=0
2914 00:56:21.692611 12, 0xFFFF, sum=0
2915 00:56:21.696009 13, 0xFFFF, sum=0
2916 00:56:21.696087 14, 0x0, sum=1
2917 00:56:21.699405 15, 0x0, sum=2
2918 00:56:21.699483 16, 0x0, sum=3
2919 00:56:21.702778 17, 0x0, sum=4
2920 00:56:21.706063 pattern=2 first_step=14 total pass=5 best_step=16
2921 00:56:21.706155 ==
2922 00:56:21.709250 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2923 00:56:21.712608 fsp= 1, odt_onoff= 1, Byte mode= 0
2924 00:56:21.712685 ==
2925 00:56:21.719279 Start DQ dly to find pass range UseTestEngine =1
2926 00:56:21.722407 x-axis: bit #, y-axis: DQ dly (-127~63)
2927 00:56:21.722479 RX Vref Scan = 1
2928 00:56:21.838285
2929 00:56:21.838403 RX Vref found, early break!
2930 00:56:21.838492
2931 00:56:21.845143 Final RX Vref 12, apply to both rank0 and 1
2932 00:56:21.845215 ==
2933 00:56:21.848476 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2934 00:56:21.851624 fsp= 1, odt_onoff= 1, Byte mode= 0
2935 00:56:21.851695 ==
2936 00:56:21.851755 DQS Delay:
2937 00:56:21.855443 DQS0 = 0, DQS1 = 0
2938 00:56:21.855506 DQM Delay:
2939 00:56:21.858713 DQM0 = 20, DQM1 = 18
2940 00:56:21.858780 DQ Delay:
2941 00:56:21.862130 DQ0 =24, DQ1 =23, DQ2 =17, DQ3 =15
2942 00:56:21.865083 DQ4 =19, DQ5 =24, DQ6 =24, DQ7 =19
2943 00:56:21.868642 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =19
2944 00:56:21.871812 DQ12 =21, DQ13 =19, DQ14 =20, DQ15 =15
2945 00:56:21.871879
2946 00:56:21.871932
2947 00:56:21.871983
2948 00:56:21.875270 [DramC_TX_OE_Calibration] TA2
2949 00:56:21.878471 Original DQ_B0 (3 6) =30, OEN = 27
2950 00:56:21.881861 Original DQ_B1 (3 6) =30, OEN = 27
2951 00:56:21.885331 23, 0x0, End_B0=23 End_B1=23
2952 00:56:21.885397 24, 0x0, End_B0=24 End_B1=24
2953 00:56:21.888686 25, 0x0, End_B0=25 End_B1=25
2954 00:56:21.891895 26, 0x0, End_B0=26 End_B1=26
2955 00:56:21.895375 27, 0x0, End_B0=27 End_B1=27
2956 00:56:21.895465 28, 0x0, End_B0=28 End_B1=28
2957 00:56:21.898429 29, 0x0, End_B0=29 End_B1=29
2958 00:56:21.901810 30, 0x0, End_B0=30 End_B1=30
2959 00:56:21.905168 31, 0xFFFF, End_B0=30 End_B1=30
2960 00:56:21.908379 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2961 00:56:21.915432 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2962 00:56:21.915510
2963 00:56:21.915589
2964 00:56:21.918671 Write Rank0 MR23 =0x3f
2965 00:56:21.918745 [DQSOSC]
2966 00:56:21.925218 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1, (MSB)MR19= 0x3, tDQSOscB0 = 339 ps tDQSOscB1 = 0 ps
2967 00:56:21.931888 CH1_RK0: MR19=0x3, MR18=0xA1, DQSOSC=339, MR23=63, INC=21, DEC=32
2968 00:56:21.935591 Write Rank0 MR23 =0x3f
2969 00:56:21.935659 [DQSOSC]
2970 00:56:21.942396 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1, (MSB)MR19= 0x3, tDQSOscB0 = 339 ps tDQSOscB1 = 0 ps
2971 00:56:21.945052 CH1 RK0: MR19=3, MR18=A1
2972 00:56:21.948535 [RankSwap] Rank num 2, (Multi 1), Rank 1
2973 00:56:21.951955 Write Rank0 MR2 =0xad
2974 00:56:21.952023 [Write Leveling]
2975 00:56:21.955192 delay byte0 byte1 byte2 byte3
2976 00:56:21.955253
2977 00:56:21.955307 10 0 0
2978 00:56:21.958685 11 0 0
2979 00:56:21.958750 12 0 0
2980 00:56:21.961921 13 0 0
2981 00:56:21.961983 14 0 0
2982 00:56:21.965496 15 0 0
2983 00:56:21.965562 16 0 0
2984 00:56:21.965620 17 0 0
2985 00:56:21.968741 18 0 0
2986 00:56:21.968801 19 0 0
2987 00:56:21.972277 20 0 0
2988 00:56:21.972338 21 0 0
2989 00:56:21.972389 22 0 0
2990 00:56:21.975523 23 0 0
2991 00:56:21.975585 24 0 0
2992 00:56:21.978713 25 0 0
2993 00:56:21.978772 26 0 0
2994 00:56:21.978826 27 0 0
2995 00:56:21.982199 28 0 0
2996 00:56:21.982296 29 0 0
2997 00:56:21.985689 30 0 0
2998 00:56:21.985748 31 0 0
2999 00:56:21.989020 32 0 ff
3000 00:56:21.989080 33 0 ff
3001 00:56:21.989130 34 0 ff
3002 00:56:21.992392 35 0 ff
3003 00:56:21.992452 36 0 ff
3004 00:56:21.995395 37 0 ff
3005 00:56:21.995463 38 ff ff
3006 00:56:21.998893 39 ff ff
3007 00:56:21.998955 40 ff ff
3008 00:56:22.002245 41 ff ff
3009 00:56:22.002321 42 ff ff
3010 00:56:22.005498 43 ff ff
3011 00:56:22.005560 44 ff ff
3012 00:56:22.008633 pass bytecount = 0xff (0xff: all bytes pass)
3013 00:56:22.008695
3014 00:56:22.012360 DQS0 dly: 38
3015 00:56:22.012426 DQS1 dly: 32
3016 00:56:22.015819 Write Rank0 MR2 =0x2d
3017 00:56:22.019155 [RankSwap] Rank num 2, (Multi 1), Rank 0
3018 00:56:22.019214 Write Rank1 MR1 =0xd6
3019 00:56:22.022174 [Gating]
3020 00:56:22.022271 ==
3021 00:56:22.025275 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3022 00:56:22.028801 fsp= 1, odt_onoff= 1, Byte mode= 0
3023 00:56:22.028862 ==
3024 00:56:22.032388 3 1 0 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3025 00:56:22.039015 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3026 00:56:22.042402 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3027 00:56:22.045578 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3028 00:56:22.052257 3 1 16 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3029 00:56:22.055644 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
3030 00:56:22.059121 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3031 00:56:22.065611 3 1 28 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3032 00:56:22.068937 3 2 0 |1514 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3033 00:56:22.072496 3 2 4 |3d3d 504 |(11 11)(11 11) |(1 1)(0 0)| 0
3034 00:56:22.075690 3 2 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3035 00:56:22.082505 3 2 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3036 00:56:22.085623 3 2 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3037 00:56:22.089340 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3038 00:56:22.095574 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3039 00:56:22.099295 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3040 00:56:22.102774 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3041 00:56:22.109395 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3042 00:56:22.112311 3 3 8 |706 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3043 00:56:22.115810 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3044 00:56:22.119389 [Byte 0] Lead/lag Transition tap number (1)
3045 00:56:22.126094 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3046 00:56:22.129446 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3047 00:56:22.132598 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3048 00:56:22.139315 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3049 00:56:22.142746 3 4 0 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3050 00:56:22.146187 3 4 4 |3d3d 807 |(11 11)(11 11) |(1 1)(1 1)| 0
3051 00:56:22.149038 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3052 00:56:22.155772 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3053 00:56:22.159307 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3054 00:56:22.162496 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3055 00:56:22.169153 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3056 00:56:22.172535 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3057 00:56:22.175836 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3058 00:56:22.182679 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3059 00:56:22.186256 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3060 00:56:22.189469 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3061 00:56:22.192586 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3062 00:56:22.199642 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3063 00:56:22.202841 [Byte 0] Lead/lag falling Transition (3, 5, 20)
3064 00:56:22.206131 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3065 00:56:22.209762 [Byte 0] Lead/lag Transition tap number (2)
3066 00:56:22.216348 [Byte 1] Lead/lag falling Transition (3, 5, 24)
3067 00:56:22.219518 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3068 00:56:22.222910 3 6 0 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3069 00:56:22.226545 [Byte 1] Lead/lag Transition tap number (3)
3070 00:56:22.233153 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
3071 00:56:22.233224 [Byte 0]First pass (3, 6, 4)
3072 00:56:22.239708 3 6 8 |4646 4646 |(0 0)(10 10) |(0 0)(0 0)| 0
3073 00:56:22.242870 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3074 00:56:22.246367 [Byte 1]First pass (3, 6, 12)
3075 00:56:22.250001 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3076 00:56:22.252866 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3077 00:56:22.256293 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3078 00:56:22.259697 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3079 00:56:22.266349 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3080 00:56:22.269554 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3081 00:56:22.272913 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3082 00:56:22.276450 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3083 00:56:22.279634 All bytes gating window > 1UI, Early break!
3084 00:56:22.279701
3085 00:56:22.286283 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 24)
3086 00:56:22.286358
3087 00:56:22.289491 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 30)
3088 00:56:22.289560
3089 00:56:22.289618
3090 00:56:22.289670
3091 00:56:22.293341 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 24)
3092 00:56:22.293406
3093 00:56:22.296598 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
3094 00:56:22.296666
3095 00:56:22.296724
3096 00:56:22.299843 Write Rank1 MR1 =0x56
3097 00:56:22.299907
3098 00:56:22.303590 best RODT dly(2T, 0.5T) = (2, 2)
3099 00:56:22.303689
3100 00:56:22.306358 best RODT dly(2T, 0.5T) = (2, 2)
3101 00:56:22.306436 ==
3102 00:56:22.309957 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3103 00:56:22.313274 fsp= 1, odt_onoff= 1, Byte mode= 0
3104 00:56:22.313351 ==
3105 00:56:22.319916 Start DQ dly to find pass range UseTestEngine =0
3106 00:56:22.323044 x-axis: bit #, y-axis: DQ dly (-127~63)
3107 00:56:22.323113 RX Vref Scan = 0
3108 00:56:22.326315 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3109 00:56:22.330138 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3110 00:56:22.332966 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3111 00:56:22.336538 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3112 00:56:22.339999 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3113 00:56:22.340066 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3114 00:56:22.343395 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3115 00:56:22.346774 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3116 00:56:22.350032 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3117 00:56:22.353265 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3118 00:56:22.360465 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3119 00:56:22.360554 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3120 00:56:22.363482 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3121 00:56:22.366758 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3122 00:56:22.366836 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3123 00:56:22.370059 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3124 00:56:22.373331 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3125 00:56:22.376424 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3126 00:56:22.380514 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3127 00:56:22.383052 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3128 00:56:22.386985 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3129 00:56:22.387067 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3130 00:56:22.390127 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3131 00:56:22.393119 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3132 00:56:22.396538 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3133 00:56:22.399898 -1, [0] xxooxxxx xxxxxxxo [MSB]
3134 00:56:22.403148 0, [0] xxooxxxx xxoxxxxo [MSB]
3135 00:56:22.403241 1, [0] xxooxxxo oxoxxxxo [MSB]
3136 00:56:22.406781 2, [0] xxoooxxo oooxxxxo [MSB]
3137 00:56:22.409875 3, [0] xxoooxxo oooxxxxo [MSB]
3138 00:56:22.413435 4, [0] xxoooxxo ooooxxoo [MSB]
3139 00:56:22.416617 5, [0] xoooooxo oooooooo [MSB]
3140 00:56:22.420021 6, [0] xoooooxo oooooooo [MSB]
3141 00:56:22.420091 33, [0] oooxoooo oooooooo [MSB]
3142 00:56:22.423398 34, [0] oooxoooo ooooooox [MSB]
3143 00:56:22.426701 35, [0] ooxxoooo ooooooox [MSB]
3144 00:56:22.430428 36, [0] ooxxoooo oxooooox [MSB]
3145 00:56:22.433219 37, [0] ooxxoooo xxxxooox [MSB]
3146 00:56:22.437247 38, [0] ooxxoooo xxxxooox [MSB]
3147 00:56:22.439756 39, [0] ooxxxoox xxxxooxx [MSB]
3148 00:56:22.439818 40, [0] ooxxxoox xxxxoxxx [MSB]
3149 00:56:22.443344 41, [0] ooxxxoox xxxxxxxx [MSB]
3150 00:56:22.446684 42, [0] ooxxxoox xxxxxxxx [MSB]
3151 00:56:22.450028 43, [0] oxxxxxxx xxxxxxxx [MSB]
3152 00:56:22.453281 44, [0] xxxxxxxx xxxxxxxx [MSB]
3153 00:56:22.456564 iDelay=44, Bit 0, Center 25 (7 ~ 43) 37
3154 00:56:22.459697 iDelay=44, Bit 1, Center 23 (5 ~ 42) 38
3155 00:56:22.463475 iDelay=44, Bit 2, Center 16 (-1 ~ 34) 36
3156 00:56:22.466780 iDelay=44, Bit 3, Center 15 (-2 ~ 32) 35
3157 00:56:22.469917 iDelay=44, Bit 4, Center 20 (2 ~ 38) 37
3158 00:56:22.473350 iDelay=44, Bit 5, Center 23 (5 ~ 42) 38
3159 00:56:22.476681 iDelay=44, Bit 6, Center 24 (7 ~ 42) 36
3160 00:56:22.480043 iDelay=44, Bit 7, Center 19 (1 ~ 38) 38
3161 00:56:22.483585 iDelay=44, Bit 8, Center 18 (1 ~ 36) 36
3162 00:56:22.486874 iDelay=44, Bit 9, Center 18 (2 ~ 35) 34
3163 00:56:22.493185 iDelay=44, Bit 10, Center 18 (0 ~ 36) 37
3164 00:56:22.497065 iDelay=44, Bit 11, Center 20 (4 ~ 36) 33
3165 00:56:22.500100 iDelay=44, Bit 12, Center 22 (5 ~ 40) 36
3166 00:56:22.503346 iDelay=44, Bit 13, Center 22 (5 ~ 39) 35
3167 00:56:22.506811 iDelay=44, Bit 14, Center 21 (4 ~ 38) 35
3168 00:56:22.510302 iDelay=44, Bit 15, Center 15 (-2 ~ 33) 36
3169 00:56:22.510370 ==
3170 00:56:22.516483 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3171 00:56:22.516553 fsp= 1, odt_onoff= 1, Byte mode= 0
3172 00:56:22.520111 ==
3173 00:56:22.520178 DQS Delay:
3174 00:56:22.520233 DQS0 = 0, DQS1 = 0
3175 00:56:22.523539 DQM Delay:
3176 00:56:22.523607 DQM0 = 20, DQM1 = 19
3177 00:56:22.526871 DQ Delay:
3178 00:56:22.529885 DQ0 =25, DQ1 =23, DQ2 =16, DQ3 =15
3179 00:56:22.529953 DQ4 =20, DQ5 =23, DQ6 =24, DQ7 =19
3180 00:56:22.533130 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =20
3181 00:56:22.536416 DQ12 =22, DQ13 =22, DQ14 =21, DQ15 =15
3182 00:56:22.539696
3183 00:56:22.539760
3184 00:56:22.539816 DramC Write-DBI off
3185 00:56:22.539870 ==
3186 00:56:22.546770 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3187 00:56:22.550272 fsp= 1, odt_onoff= 1, Byte mode= 0
3188 00:56:22.550337 ==
3189 00:56:22.553403 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3190 00:56:22.553467
3191 00:56:22.556872 Begin, DQ Scan Range 928~1184
3192 00:56:22.556936
3193 00:56:22.556989
3194 00:56:22.560088 TX Vref Scan disable
3195 00:56:22.563132 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3196 00:56:22.566926 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3197 00:56:22.569861 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3198 00:56:22.573790 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3199 00:56:22.576698 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3200 00:56:22.580170 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3201 00:56:22.583240 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3202 00:56:22.587050 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3203 00:56:22.590032 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3204 00:56:22.593327 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3205 00:56:22.596926 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3206 00:56:22.600060 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3207 00:56:22.603217 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3208 00:56:22.606596 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3209 00:56:22.610061 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3210 00:56:22.613604 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3211 00:56:22.620106 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3212 00:56:22.623786 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3213 00:56:22.627145 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3214 00:56:22.630189 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3215 00:56:22.633899 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3216 00:56:22.636790 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3217 00:56:22.640250 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3218 00:56:22.643449 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3219 00:56:22.647031 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3220 00:56:22.650145 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3221 00:56:22.654052 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3222 00:56:22.657373 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3223 00:56:22.660486 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3224 00:56:22.664060 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3225 00:56:22.667269 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3226 00:56:22.670638 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3227 00:56:22.674055 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3228 00:56:22.677340 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3229 00:56:22.680877 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3230 00:56:22.684224 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3231 00:56:22.687178 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3232 00:56:22.690742 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3233 00:56:22.697383 966 |3 6 6|[0] xxxxxxxx xxxxxxxo [MSB]
3234 00:56:22.700688 967 |3 6 7|[0] xxxxxxxx xxxxxxxo [MSB]
3235 00:56:22.704232 968 |3 6 8|[0] xxxxxxxx xxxxxxxo [MSB]
3236 00:56:22.707374 969 |3 6 9|[0] xxxxxxxx ooxxxxxo [MSB]
3237 00:56:22.710944 970 |3 6 10|[0] xxxxxxxx ooooxooo [MSB]
3238 00:56:22.714421 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
3239 00:56:22.717374 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
3240 00:56:22.720571 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
3241 00:56:22.723766 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
3242 00:56:22.727022 975 |3 6 15|[0] xxooxxxx oooooooo [MSB]
3243 00:56:22.730521 976 |3 6 16|[0] xxoooxxo oooooooo [MSB]
3244 00:56:22.737845 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3245 00:56:22.741508 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3246 00:56:22.745011 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3247 00:56:22.747993 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3248 00:56:22.751502 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3249 00:56:22.754870 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3250 00:56:22.758183 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
3251 00:56:22.761617 998 |3 6 38|[0] ooxxoooo xxxxxxxx [MSB]
3252 00:56:22.764649 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
3253 00:56:22.767978 Byte0, DQ PI dly=986, DQM PI dly= 986
3254 00:56:22.771693 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
3255 00:56:22.771771
3256 00:56:22.778186 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
3257 00:56:22.778305
3258 00:56:22.781802 Byte1, DQ PI dly=979, DQM PI dly= 979
3259 00:56:22.785246 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
3260 00:56:22.785324
3261 00:56:22.788939 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
3262 00:56:22.789026
3263 00:56:22.789086 ==
3264 00:56:22.795034 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3265 00:56:22.798194 fsp= 1, odt_onoff= 1, Byte mode= 0
3266 00:56:22.798313 ==
3267 00:56:22.801644 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3268 00:56:22.801721
3269 00:56:22.805236 Begin, DQ Scan Range 955~1019
3270 00:56:22.808128 Write Rank1 MR14 =0x0
3271 00:56:22.816163
3272 00:56:22.816243 CH=1, VrefRange= 0, VrefLevel = 0
3273 00:56:22.822637 TX Bit0 (980~999) 20 989, Bit8 (970~988) 19 979,
3274 00:56:22.826035 TX Bit1 (978~997) 20 987, Bit9 (970~986) 17 978,
3275 00:56:22.832645 TX Bit2 (976~993) 18 984, Bit10 (971~986) 16 978,
3276 00:56:22.835917 TX Bit3 (976~992) 17 984, Bit11 (971~990) 20 980,
3277 00:56:22.839393 TX Bit4 (977~995) 19 986, Bit12 (972~991) 20 981,
3278 00:56:22.845973 TX Bit5 (979~998) 20 988, Bit13 (972~988) 17 980,
3279 00:56:22.849699 TX Bit6 (980~999) 20 989, Bit14 (972~988) 17 980,
3280 00:56:22.853249 TX Bit7 (978~995) 18 986, Bit15 (968~985) 18 976,
3281 00:56:22.853326
3282 00:56:22.855982 Write Rank1 MR14 =0x2
3283 00:56:22.865049
3284 00:56:22.865126 CH=1, VrefRange= 0, VrefLevel = 2
3285 00:56:22.871869 TX Bit0 (979~999) 21 989, Bit8 (970~988) 19 979,
3286 00:56:22.874921 TX Bit1 (977~998) 22 987, Bit9 (970~987) 18 978,
3287 00:56:22.881646 TX Bit2 (976~993) 18 984, Bit10 (970~987) 18 978,
3288 00:56:22.885326 TX Bit3 (975~992) 18 983, Bit11 (971~989) 19 980,
3289 00:56:22.888419 TX Bit4 (977~995) 19 986, Bit12 (972~991) 20 981,
3290 00:56:22.895401 TX Bit5 (979~998) 20 988, Bit13 (972~988) 17 980,
3291 00:56:22.898340 TX Bit6 (979~999) 21 989, Bit14 (971~988) 18 979,
3292 00:56:22.901754 TX Bit7 (978~996) 19 987, Bit15 (968~986) 19 977,
3293 00:56:22.901832
3294 00:56:22.905262 Write Rank1 MR14 =0x4
3295 00:56:22.914082
3296 00:56:22.914160 CH=1, VrefRange= 0, VrefLevel = 4
3297 00:56:22.920712 TX Bit0 (979~999) 21 989, Bit8 (970~989) 20 979,
3298 00:56:22.924142 TX Bit1 (978~998) 21 988, Bit9 (970~988) 19 979,
3299 00:56:22.930642 TX Bit2 (976~994) 19 985, Bit10 (970~987) 18 978,
3300 00:56:22.933934 TX Bit3 (975~992) 18 983, Bit11 (971~991) 21 981,
3301 00:56:22.937686 TX Bit4 (977~996) 20 986, Bit12 (972~991) 20 981,
3302 00:56:22.944113 TX Bit5 (979~999) 21 989, Bit13 (971~989) 19 980,
3303 00:56:22.947182 TX Bit6 (979~999) 21 989, Bit14 (971~989) 19 980,
3304 00:56:22.950889 TX Bit7 (977~997) 21 987, Bit15 (968~986) 19 977,
3305 00:56:22.950967
3306 00:56:22.954144 Write Rank1 MR14 =0x6
3307 00:56:22.962778
3308 00:56:22.962855 CH=1, VrefRange= 0, VrefLevel = 6
3309 00:56:22.969637 TX Bit0 (979~999) 21 989, Bit8 (970~990) 21 980,
3310 00:56:22.972953 TX Bit1 (977~998) 22 987, Bit9 (969~989) 21 979,
3311 00:56:22.979807 TX Bit2 (975~994) 20 984, Bit10 (970~988) 19 979,
3312 00:56:22.982914 TX Bit3 (975~993) 19 984, Bit11 (971~991) 21 981,
3313 00:56:22.986183 TX Bit4 (977~996) 20 986, Bit12 (972~991) 20 981,
3314 00:56:22.993108 TX Bit5 (978~999) 22 988, Bit13 (971~990) 20 980,
3315 00:56:22.996446 TX Bit6 (978~999) 22 988, Bit14 (971~990) 20 980,
3316 00:56:22.999573 TX Bit7 (977~997) 21 987, Bit15 (968~987) 20 977,
3317 00:56:22.999673
3318 00:56:23.006218 wait MRW command Rank1 MR14 =0x8 fired (1)
3319 00:56:23.006331 Write Rank1 MR14 =0x8
3320 00:56:23.016223
3321 00:56:23.016300 CH=1, VrefRange= 0, VrefLevel = 8
3322 00:56:23.022488 TX Bit0 (978~1000) 23 989, Bit8 (969~990) 22 979,
3323 00:56:23.025621 TX Bit1 (977~998) 22 987, Bit9 (969~989) 21 979,
3324 00:56:23.032295 TX Bit2 (975~995) 21 985, Bit10 (970~988) 19 979,
3325 00:56:23.035796 TX Bit3 (975~993) 19 984, Bit11 (970~991) 22 980,
3326 00:56:23.039163 TX Bit4 (976~997) 22 986, Bit12 (971~992) 22 981,
3327 00:56:23.045772 TX Bit5 (978~999) 22 988, Bit13 (971~990) 20 980,
3328 00:56:23.049203 TX Bit6 (978~1000) 23 989, Bit14 (971~990) 20 980,
3329 00:56:23.052428 TX Bit7 (977~997) 21 987, Bit15 (967~987) 21 977,
3330 00:56:23.055664
3331 00:56:23.055740 Write Rank1 MR14 =0xa
3332 00:56:23.064987
3333 00:56:23.068256 CH=1, VrefRange= 0, VrefLevel = 10
3334 00:56:23.071598 TX Bit0 (979~1000) 22 989, Bit8 (969~991) 23 980,
3335 00:56:23.075086 TX Bit1 (977~998) 22 987, Bit9 (969~990) 22 979,
3336 00:56:23.081738 TX Bit2 (975~995) 21 985, Bit10 (970~989) 20 979,
3337 00:56:23.085452 TX Bit3 (974~994) 21 984, Bit11 (970~992) 23 981,
3338 00:56:23.088396 TX Bit4 (976~997) 22 986, Bit12 (971~992) 22 981,
3339 00:56:23.095327 TX Bit5 (978~1000) 23 989, Bit13 (971~991) 21 981,
3340 00:56:23.098325 TX Bit6 (977~1000) 24 988, Bit14 (970~991) 22 980,
3341 00:56:23.101686 TX Bit7 (977~997) 21 987, Bit15 (967~988) 22 977,
3342 00:56:23.105043
3343 00:56:23.105120 Write Rank1 MR14 =0xc
3344 00:56:23.114787
3345 00:56:23.117979 CH=1, VrefRange= 0, VrefLevel = 12
3346 00:56:23.121351 TX Bit0 (977~1000) 24 988, Bit8 (969~991) 23 980,
3347 00:56:23.124763 TX Bit1 (977~999) 23 988, Bit9 (969~990) 22 979,
3348 00:56:23.131408 TX Bit2 (975~996) 22 985, Bit10 (970~990) 21 980,
3349 00:56:23.134499 TX Bit3 (974~995) 22 984, Bit11 (970~992) 23 981,
3350 00:56:23.137987 TX Bit4 (976~997) 22 986, Bit12 (971~992) 22 981,
3351 00:56:23.144934 TX Bit5 (978~1000) 23 989, Bit13 (970~991) 22 980,
3352 00:56:23.148054 TX Bit6 (977~1000) 24 988, Bit14 (970~991) 22 980,
3353 00:56:23.151303 TX Bit7 (977~998) 22 987, Bit15 (967~989) 23 978,
3354 00:56:23.151381
3355 00:56:23.154757 Write Rank1 MR14 =0xe
3356 00:56:23.164322
3357 00:56:23.167573 CH=1, VrefRange= 0, VrefLevel = 14
3358 00:56:23.170807 TX Bit0 (977~1001) 25 989, Bit8 (969~991) 23 980,
3359 00:56:23.174364 TX Bit1 (977~999) 23 988, Bit9 (969~991) 23 980,
3360 00:56:23.180975 TX Bit2 (974~997) 24 985, Bit10 (970~991) 22 980,
3361 00:56:23.184314 TX Bit3 (974~996) 23 985, Bit11 (970~992) 23 981,
3362 00:56:23.187746 TX Bit4 (976~998) 23 987, Bit12 (970~992) 23 981,
3363 00:56:23.194311 TX Bit5 (977~1000) 24 988, Bit13 (970~991) 22 980,
3364 00:56:23.197895 TX Bit6 (978~1001) 24 989, Bit14 (970~991) 22 980,
3365 00:56:23.201133 TX Bit7 (977~998) 22 987, Bit15 (966~989) 24 977,
3366 00:56:23.201210
3367 00:56:23.204355 Write Rank1 MR14 =0x10
3368 00:56:23.214031
3369 00:56:23.217467 CH=1, VrefRange= 0, VrefLevel = 16
3370 00:56:23.220642 TX Bit0 (977~1001) 25 989, Bit8 (969~991) 23 980,
3371 00:56:23.224104 TX Bit1 (976~999) 24 987, Bit9 (969~991) 23 980,
3372 00:56:23.230614 TX Bit2 (974~997) 24 985, Bit10 (969~991) 23 980,
3373 00:56:23.234153 TX Bit3 (974~996) 23 985, Bit11 (970~992) 23 981,
3374 00:56:23.237432 TX Bit4 (976~998) 23 987, Bit12 (971~992) 22 981,
3375 00:56:23.244284 TX Bit5 (977~1000) 24 988, Bit13 (970~991) 22 980,
3376 00:56:23.247490 TX Bit6 (977~1001) 25 989, Bit14 (969~991) 23 980,
3377 00:56:23.250869 TX Bit7 (976~998) 23 987, Bit15 (966~990) 25 978,
3378 00:56:23.250946
3379 00:56:23.257433 wait MRW command Rank1 MR14 =0x12 fired (1)
3380 00:56:23.257511 Write Rank1 MR14 =0x12
3381 00:56:23.267664
3382 00:56:23.271092 CH=1, VrefRange= 0, VrefLevel = 18
3383 00:56:23.274483 TX Bit0 (977~1002) 26 989, Bit8 (968~991) 24 979,
3384 00:56:23.277546 TX Bit1 (976~999) 24 987, Bit9 (968~991) 24 979,
3385 00:56:23.284161 TX Bit2 (974~997) 24 985, Bit10 (969~991) 23 980,
3386 00:56:23.287795 TX Bit3 (973~997) 25 985, Bit11 (970~992) 23 981,
3387 00:56:23.290742 TX Bit4 (975~998) 24 986, Bit12 (970~992) 23 981,
3388 00:56:23.297399 TX Bit5 (977~1001) 25 989, Bit13 (970~992) 23 981,
3389 00:56:23.300874 TX Bit6 (977~1001) 25 989, Bit14 (969~992) 24 980,
3390 00:56:23.304304 TX Bit7 (976~998) 23 987, Bit15 (966~990) 25 978,
3391 00:56:23.307554
3392 00:56:23.307629 Write Rank1 MR14 =0x14
3393 00:56:23.317743
3394 00:56:23.320648 CH=1, VrefRange= 0, VrefLevel = 20
3395 00:56:23.324272 TX Bit0 (977~1002) 26 989, Bit8 (968~991) 24 979,
3396 00:56:23.327547 TX Bit1 (976~1000) 25 988, Bit9 (968~991) 24 979,
3397 00:56:23.334176 TX Bit2 (974~998) 25 986, Bit10 (969~991) 23 980,
3398 00:56:23.337820 TX Bit3 (973~997) 25 985, Bit11 (969~993) 25 981,
3399 00:56:23.340941 TX Bit4 (975~998) 24 986, Bit12 (970~993) 24 981,
3400 00:56:23.347283 TX Bit5 (977~1001) 25 989, Bit13 (970~992) 23 981,
3401 00:56:23.350818 TX Bit6 (977~1002) 26 989, Bit14 (969~992) 24 980,
3402 00:56:23.357352 TX Bit7 (976~998) 23 987, Bit15 (965~990) 26 977,
3403 00:56:23.357453
3404 00:56:23.357540 Write Rank1 MR14 =0x16
3405 00:56:23.367686
3406 00:56:23.371260 CH=1, VrefRange= 0, VrefLevel = 22
3407 00:56:23.374479 TX Bit0 (977~1003) 27 990, Bit8 (968~992) 25 980,
3408 00:56:23.377554 TX Bit1 (976~1000) 25 988, Bit9 (968~991) 24 979,
3409 00:56:23.384391 TX Bit2 (974~998) 25 986, Bit10 (968~992) 25 980,
3410 00:56:23.387751 TX Bit3 (973~997) 25 985, Bit11 (969~993) 25 981,
3411 00:56:23.391152 TX Bit4 (975~998) 24 986, Bit12 (970~993) 24 981,
3412 00:56:23.397898 TX Bit5 (977~1001) 25 989, Bit13 (970~992) 23 981,
3413 00:56:23.401039 TX Bit6 (977~1002) 26 989, Bit14 (969~992) 24 980,
3414 00:56:23.404305 TX Bit7 (976~999) 24 987, Bit15 (965~991) 27 978,
3415 00:56:23.407766
3416 00:56:23.407867 Write Rank1 MR14 =0x18
3417 00:56:23.417626
3418 00:56:23.420983 CH=1, VrefRange= 0, VrefLevel = 24
3419 00:56:23.424561 TX Bit0 (977~1003) 27 990, Bit8 (968~992) 25 980,
3420 00:56:23.427933 TX Bit1 (976~1000) 25 988, Bit9 (968~992) 25 980,
3421 00:56:23.434499 TX Bit2 (974~998) 25 986, Bit10 (968~992) 25 980,
3422 00:56:23.437775 TX Bit3 (973~997) 25 985, Bit11 (969~993) 25 981,
3423 00:56:23.441183 TX Bit4 (975~999) 25 987, Bit12 (970~992) 23 981,
3424 00:56:23.448155 TX Bit5 (977~1002) 26 989, Bit13 (969~992) 24 980,
3425 00:56:23.451218 TX Bit6 (977~1002) 26 989, Bit14 (969~992) 24 980,
3426 00:56:23.454591 TX Bit7 (975~999) 25 987, Bit15 (965~991) 27 978,
3427 00:56:23.457812
3428 00:56:23.457889 Write Rank1 MR14 =0x1a
3429 00:56:23.468059
3430 00:56:23.471411 CH=1, VrefRange= 0, VrefLevel = 26
3431 00:56:23.474230 TX Bit0 (976~1002) 27 989, Bit8 (968~992) 25 980,
3432 00:56:23.477943 TX Bit1 (976~1000) 25 988, Bit9 (968~992) 25 980,
3433 00:56:23.484446 TX Bit2 (973~998) 26 985, Bit10 (968~992) 25 980,
3434 00:56:23.487516 TX Bit3 (972~997) 26 984, Bit11 (969~993) 25 981,
3435 00:56:23.491215 TX Bit4 (975~999) 25 987, Bit12 (970~992) 23 981,
3436 00:56:23.497712 TX Bit5 (977~1002) 26 989, Bit13 (969~992) 24 980,
3437 00:56:23.500872 TX Bit6 (977~1002) 26 989, Bit14 (969~992) 24 980,
3438 00:56:23.507424 TX Bit7 (975~999) 25 987, Bit15 (965~991) 27 978,
3439 00:56:23.507504
3440 00:56:23.507565 Write Rank1 MR14 =0x1c
3441 00:56:23.517890
3442 00:56:23.520921 CH=1, VrefRange= 0, VrefLevel = 28
3443 00:56:23.524404 TX Bit0 (977~1003) 27 990, Bit8 (968~991) 24 979,
3444 00:56:23.527626 TX Bit1 (976~1000) 25 988, Bit9 (968~991) 24 979,
3445 00:56:23.534777 TX Bit2 (973~997) 25 985, Bit10 (968~991) 24 979,
3446 00:56:23.537933 TX Bit3 (972~997) 26 984, Bit11 (969~992) 24 980,
3447 00:56:23.541273 TX Bit4 (975~999) 25 987, Bit12 (969~992) 24 980,
3448 00:56:23.547828 TX Bit5 (977~1001) 25 989, Bit13 (969~992) 24 980,
3449 00:56:23.551248 TX Bit6 (977~1002) 26 989, Bit14 (969~992) 24 980,
3450 00:56:23.554944 TX Bit7 (975~998) 24 986, Bit15 (965~990) 26 977,
3451 00:56:23.557960
3452 00:56:23.558037 Write Rank1 MR14 =0x1e
3453 00:56:23.567845
3454 00:56:23.570896 CH=1, VrefRange= 0, VrefLevel = 30
3455 00:56:23.574315 TX Bit0 (977~1003) 27 990, Bit8 (968~991) 24 979,
3456 00:56:23.577500 TX Bit1 (976~1000) 25 988, Bit9 (968~991) 24 979,
3457 00:56:23.584314 TX Bit2 (973~997) 25 985, Bit10 (968~991) 24 979,
3458 00:56:23.587633 TX Bit3 (972~997) 26 984, Bit11 (969~992) 24 980,
3459 00:56:23.591162 TX Bit4 (975~999) 25 987, Bit12 (969~992) 24 980,
3460 00:56:23.598062 TX Bit5 (977~1001) 25 989, Bit13 (969~992) 24 980,
3461 00:56:23.601208 TX Bit6 (977~1002) 26 989, Bit14 (969~992) 24 980,
3462 00:56:23.607627 TX Bit7 (975~998) 24 986, Bit15 (965~990) 26 977,
3463 00:56:23.607697
3464 00:56:23.607755 Write Rank1 MR14 =0x20
3465 00:56:23.617495
3466 00:56:23.620892 CH=1, VrefRange= 0, VrefLevel = 32
3467 00:56:23.624421 TX Bit0 (977~1003) 27 990, Bit8 (968~991) 24 979,
3468 00:56:23.627856 TX Bit1 (976~1000) 25 988, Bit9 (968~991) 24 979,
3469 00:56:23.634302 TX Bit2 (973~997) 25 985, Bit10 (968~991) 24 979,
3470 00:56:23.637745 TX Bit3 (972~997) 26 984, Bit11 (969~992) 24 980,
3471 00:56:23.641036 TX Bit4 (975~999) 25 987, Bit12 (969~992) 24 980,
3472 00:56:23.647981 TX Bit5 (977~1001) 25 989, Bit13 (969~992) 24 980,
3473 00:56:23.651078 TX Bit6 (977~1002) 26 989, Bit14 (969~992) 24 980,
3474 00:56:23.654458 TX Bit7 (975~998) 24 986, Bit15 (965~990) 26 977,
3475 00:56:23.657835
3476 00:56:23.657911 Write Rank1 MR14 =0x22
3477 00:56:23.667528
3478 00:56:23.670884 CH=1, VrefRange= 0, VrefLevel = 34
3479 00:56:23.674506 TX Bit0 (977~1003) 27 990, Bit8 (968~991) 24 979,
3480 00:56:23.677732 TX Bit1 (976~1000) 25 988, Bit9 (968~991) 24 979,
3481 00:56:23.684527 TX Bit2 (973~997) 25 985, Bit10 (968~991) 24 979,
3482 00:56:23.687634 TX Bit3 (972~997) 26 984, Bit11 (969~992) 24 980,
3483 00:56:23.691294 TX Bit4 (975~999) 25 987, Bit12 (969~992) 24 980,
3484 00:56:23.697740 TX Bit5 (977~1001) 25 989, Bit13 (969~992) 24 980,
3485 00:56:23.700888 TX Bit6 (977~1002) 26 989, Bit14 (969~992) 24 980,
3486 00:56:23.707399 TX Bit7 (975~998) 24 986, Bit15 (965~990) 26 977,
3487 00:56:23.707470
3488 00:56:23.707532 Write Rank1 MR14 =0x24
3489 00:56:23.717170
3490 00:56:23.720563 CH=1, VrefRange= 0, VrefLevel = 36
3491 00:56:23.723919 TX Bit0 (977~1003) 27 990, Bit8 (968~991) 24 979,
3492 00:56:23.727611 TX Bit1 (976~1000) 25 988, Bit9 (968~991) 24 979,
3493 00:56:23.734350 TX Bit2 (973~997) 25 985, Bit10 (968~991) 24 979,
3494 00:56:23.737437 TX Bit3 (972~997) 26 984, Bit11 (969~992) 24 980,
3495 00:56:23.740977 TX Bit4 (975~999) 25 987, Bit12 (969~992) 24 980,
3496 00:56:23.747660 TX Bit5 (977~1001) 25 989, Bit13 (969~992) 24 980,
3497 00:56:23.750874 TX Bit6 (977~1002) 26 989, Bit14 (969~992) 24 980,
3498 00:56:23.754524 TX Bit7 (975~998) 24 986, Bit15 (965~990) 26 977,
3499 00:56:23.754592
3500 00:56:23.757504
3501 00:56:23.760867 TX Vref found, early break! 365< 377
3502 00:56:23.764310 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
3503 00:56:23.767905 u1DelayCellOfst[0]=7 cells (6 PI)
3504 00:56:23.771159 u1DelayCellOfst[1]=5 cells (4 PI)
3505 00:56:23.774444 u1DelayCellOfst[2]=1 cells (1 PI)
3506 00:56:23.777811 u1DelayCellOfst[3]=0 cells (0 PI)
3507 00:56:23.777880 u1DelayCellOfst[4]=3 cells (3 PI)
3508 00:56:23.781233 u1DelayCellOfst[5]=6 cells (5 PI)
3509 00:56:23.784427 u1DelayCellOfst[6]=6 cells (5 PI)
3510 00:56:23.787885 u1DelayCellOfst[7]=2 cells (2 PI)
3511 00:56:23.791691 Byte0, DQ PI dly=984, DQM PI dly= 987
3512 00:56:23.794638 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
3513 00:56:23.794731
3514 00:56:23.801455 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
3515 00:56:23.801528
3516 00:56:23.804782 u1DelayCellOfst[8]=2 cells (2 PI)
3517 00:56:23.807936 u1DelayCellOfst[9]=2 cells (2 PI)
3518 00:56:23.808013 u1DelayCellOfst[10]=2 cells (2 PI)
3519 00:56:23.811561 u1DelayCellOfst[11]=3 cells (3 PI)
3520 00:56:23.814676 u1DelayCellOfst[12]=3 cells (3 PI)
3521 00:56:23.818194 u1DelayCellOfst[13]=3 cells (3 PI)
3522 00:56:23.821159 u1DelayCellOfst[14]=3 cells (3 PI)
3523 00:56:23.824696 u1DelayCellOfst[15]=0 cells (0 PI)
3524 00:56:23.827972 Byte1, DQ PI dly=977, DQM PI dly= 978
3525 00:56:23.831676 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3526 00:56:23.834820
3527 00:56:23.837937 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3528 00:56:23.838013
3529 00:56:23.838072 Write Rank1 MR14 =0x1c
3530 00:56:23.841639
3531 00:56:23.841715 Final TX Range 0 Vref 28
3532 00:56:23.841775
3533 00:56:23.848043 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3534 00:56:23.848120
3535 00:56:23.854649 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3536 00:56:23.861164 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3537 00:56:23.867997 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3538 00:56:23.871145 Write Rank1 MR3 =0xb0
3539 00:56:23.871221 DramC Write-DBI on
3540 00:56:23.874623 ==
3541 00:56:23.878140 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3542 00:56:23.881490 fsp= 1, odt_onoff= 1, Byte mode= 0
3543 00:56:23.881567 ==
3544 00:56:23.884623 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3545 00:56:23.884701
3546 00:56:23.888053 Begin, DQ Scan Range 698~762
3547 00:56:23.888129
3548 00:56:23.888187
3549 00:56:23.891078 TX Vref Scan disable
3550 00:56:23.894433 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3551 00:56:23.898349 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3552 00:56:23.901363 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3553 00:56:23.904652 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3554 00:56:23.908198 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3555 00:56:23.911458 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3556 00:56:23.914874 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3557 00:56:23.918185 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3558 00:56:23.921547 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3559 00:56:23.924879 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3560 00:56:23.927972 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3561 00:56:23.931446 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
3562 00:56:23.934785 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
3563 00:56:23.938481 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3564 00:56:23.945227 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3565 00:56:23.948352 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3566 00:56:23.951484 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3567 00:56:23.954925 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3568 00:56:23.957980 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3569 00:56:23.961802 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3570 00:56:23.968648 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3571 00:56:23.972232 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3572 00:56:23.975649 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3573 00:56:23.978543 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3574 00:56:23.982135 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3575 00:56:23.985134 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3576 00:56:23.988680 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3577 00:56:23.992084 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3578 00:56:23.995454 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3579 00:56:23.998694 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
3580 00:56:24.002287 Byte0, DQ PI dly=731, DQM PI dly= 731
3581 00:56:24.005261 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
3582 00:56:24.005338
3583 00:56:24.012514 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
3584 00:56:24.012592
3585 00:56:24.015407 Byte1, DQ PI dly=722, DQM PI dly= 722
3586 00:56:24.019173 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 18)
3587 00:56:24.019250
3588 00:56:24.022301 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 18)
3589 00:56:24.022378
3590 00:56:24.029032 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3591 00:56:24.035521 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3592 00:56:24.045537 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3593 00:56:24.045615 Write Rank1 MR3 =0x30
3594 00:56:24.049317 DramC Write-DBI off
3595 00:56:24.049394
3596 00:56:24.049453 [DATLAT]
3597 00:56:24.052624 Freq=1600, CH1 RK1, use_rxtx_scan=0
3598 00:56:24.052700
3599 00:56:24.055717 DATLAT Default: 0x10
3600 00:56:24.055793 7, 0xFFFF, sum=0
3601 00:56:24.055853 8, 0xFFFF, sum=0
3602 00:56:24.059154 9, 0xFFFF, sum=0
3603 00:56:24.059231 10, 0xFFFF, sum=0
3604 00:56:24.062570 11, 0xFFFF, sum=0
3605 00:56:24.062648 12, 0xFFFF, sum=0
3606 00:56:24.065995 13, 0xFFFF, sum=0
3607 00:56:24.066073 14, 0x0, sum=1
3608 00:56:24.069086 15, 0x0, sum=2
3609 00:56:24.069164 16, 0x0, sum=3
3610 00:56:24.072719 17, 0x0, sum=4
3611 00:56:24.075812 pattern=2 first_step=14 total pass=5 best_step=16
3612 00:56:24.075889 ==
3613 00:56:24.079389 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3614 00:56:24.082561 fsp= 1, odt_onoff= 1, Byte mode= 0
3615 00:56:24.082638 ==
3616 00:56:24.089450 Start DQ dly to find pass range UseTestEngine =1
3617 00:56:24.092808 x-axis: bit #, y-axis: DQ dly (-127~63)
3618 00:56:24.092884 RX Vref Scan = 0
3619 00:56:24.096302 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3620 00:56:24.098918 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3621 00:56:24.102584 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3622 00:56:24.106032 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3623 00:56:24.109005 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3624 00:56:24.112508 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3625 00:56:24.112586 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3626 00:56:24.116146 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3627 00:56:24.119193 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3628 00:56:24.122483 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3629 00:56:24.125625 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3630 00:56:24.129131 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3631 00:56:24.132630 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3632 00:56:24.135602 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3633 00:56:24.135679 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3634 00:56:24.138960 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3635 00:56:24.142740 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3636 00:56:24.145987 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3637 00:56:24.149163 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3638 00:56:24.152501 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3639 00:56:24.156200 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3640 00:56:24.156278 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3641 00:56:24.159230 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3642 00:56:24.162746 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3643 00:56:24.166124 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3644 00:56:24.169266 -1, [0] xxxoxxxx xxxxxxxo [MSB]
3645 00:56:24.172609 0, [0] xxooxxxx xxxxxxxo [MSB]
3646 00:56:24.175930 1, [0] xxooxxxx oooxxxxo [MSB]
3647 00:56:24.176008 2, [0] xxooxxxx oooxxxxo [MSB]
3648 00:56:24.179195 3, [0] xxoooxxo ooooxxxo [MSB]
3649 00:56:24.182933 4, [0] xxoooxxo ooooxooo [MSB]
3650 00:56:24.185918 5, [0] xxoooxxo oooooooo [MSB]
3651 00:56:24.189225 6, [0] xooooxxo oooooooo [MSB]
3652 00:56:24.192708 33, [0] oooxoooo ooooooox [MSB]
3653 00:56:24.196157 34, [0] oooxoooo ooooooox [MSB]
3654 00:56:24.199430 35, [0] ooxxoooo ooooooox [MSB]
3655 00:56:24.202941 36, [0] ooxxoooo ooooooox [MSB]
3656 00:56:24.206081 37, [0] ooxxoooo xxxxooox [MSB]
3657 00:56:24.206178 38, [0] ooxxxooo xxxxooxx [MSB]
3658 00:56:24.209366 39, [0] ooxxxoox xxxxoxxx [MSB]
3659 00:56:24.213128 40, [0] ooxxxoox xxxxxxxx [MSB]
3660 00:56:24.216005 41, [0] ooxxxxox xxxxxxxx [MSB]
3661 00:56:24.219433 42, [0] oxxxxxox xxxxxxxx [MSB]
3662 00:56:24.222504 43, [0] xxxxxxxx xxxxxxxx [MSB]
3663 00:56:24.225970 iDelay=43, Bit 0, Center 24 (7 ~ 42) 36
3664 00:56:24.229299 iDelay=43, Bit 1, Center 23 (6 ~ 41) 36
3665 00:56:24.232995 iDelay=43, Bit 2, Center 17 (0 ~ 34) 35
3666 00:56:24.235990 iDelay=43, Bit 3, Center 15 (-2 ~ 32) 35
3667 00:56:24.239385 iDelay=43, Bit 4, Center 20 (3 ~ 37) 35
3668 00:56:24.242891 iDelay=43, Bit 5, Center 23 (7 ~ 40) 34
3669 00:56:24.246020 iDelay=43, Bit 6, Center 24 (7 ~ 42) 36
3670 00:56:24.249109 iDelay=43, Bit 7, Center 20 (3 ~ 38) 36
3671 00:56:24.252762 iDelay=43, Bit 8, Center 18 (1 ~ 36) 36
3672 00:56:24.256059 iDelay=43, Bit 9, Center 18 (1 ~ 36) 36
3673 00:56:24.259026 iDelay=43, Bit 10, Center 18 (1 ~ 36) 36
3674 00:56:24.262710 iDelay=43, Bit 11, Center 19 (3 ~ 36) 34
3675 00:56:24.269091 iDelay=43, Bit 12, Center 22 (5 ~ 39) 35
3676 00:56:24.272440 iDelay=43, Bit 13, Center 21 (4 ~ 38) 35
3677 00:56:24.275874 iDelay=43, Bit 14, Center 20 (4 ~ 37) 34
3678 00:56:24.279207 iDelay=43, Bit 15, Center 15 (-2 ~ 32) 35
3679 00:56:24.279272 ==
3680 00:56:24.282552 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3681 00:56:24.286128 fsp= 1, odt_onoff= 1, Byte mode= 0
3682 00:56:24.286193 ==
3683 00:56:24.289553 DQS Delay:
3684 00:56:24.289615 DQS0 = 0, DQS1 = 0
3685 00:56:24.292496 DQM Delay:
3686 00:56:24.292558 DQM0 = 20, DQM1 = 18
3687 00:56:24.292611 DQ Delay:
3688 00:56:24.295882 DQ0 =24, DQ1 =23, DQ2 =17, DQ3 =15
3689 00:56:24.299256 DQ4 =20, DQ5 =23, DQ6 =24, DQ7 =20
3690 00:56:24.302891 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =19
3691 00:56:24.306274 DQ12 =22, DQ13 =21, DQ14 =20, DQ15 =15
3692 00:56:24.306343
3693 00:56:24.306403
3694 00:56:24.306456
3695 00:56:24.309529 [DramC_TX_OE_Calibration] TA2
3696 00:56:24.312635 Original DQ_B0 (3 6) =30, OEN = 27
3697 00:56:24.316154 Original DQ_B1 (3 6) =30, OEN = 27
3698 00:56:24.319611 23, 0x0, End_B0=23 End_B1=23
3699 00:56:24.322893 24, 0x0, End_B0=24 End_B1=24
3700 00:56:24.322974 25, 0x0, End_B0=25 End_B1=25
3701 00:56:24.326046 26, 0x0, End_B0=26 End_B1=26
3702 00:56:24.329259 27, 0x0, End_B0=27 End_B1=27
3703 00:56:24.333087 28, 0x0, End_B0=28 End_B1=28
3704 00:56:24.335881 29, 0x0, End_B0=29 End_B1=29
3705 00:56:24.335959 30, 0x0, End_B0=30 End_B1=30
3706 00:56:24.339594 31, 0xFFFF, End_B0=30 End_B1=30
3707 00:56:24.346133 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3708 00:56:24.349275 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3709 00:56:24.353207
3710 00:56:24.353282
3711 00:56:24.353341 Write Rank1 MR23 =0x3f
3712 00:56:24.353396 [DQSOSC]
3713 00:56:24.362850 [DQSOSCAuto] RK1, (LSB)MR18= 0xa8, (MSB)MR19= 0x3, tDQSOscB0 = 336 ps tDQSOscB1 = 0 ps
3714 00:56:24.366171 CH1_RK1: MR19=0x3, MR18=0xA8, DQSOSC=336, MR23=63, INC=21, DEC=32
3715 00:56:24.369345 Write Rank1 MR23 =0x3f
3716 00:56:24.369420 [DQSOSC]
3717 00:56:24.379325 [DQSOSCAuto] RK1, (LSB)MR18= 0xa5, (MSB)MR19= 0x3, tDQSOscB0 = 337 ps tDQSOscB1 = 0 ps
3718 00:56:24.379402 CH1 RK1: MR19=3, MR18=A5
3719 00:56:24.382770 [RxdqsGatingPostProcess] freq 1600
3720 00:56:24.389716 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3721 00:56:24.389793 Rank: 0
3722 00:56:24.392702 best DQS0 dly(2T, 0.5T) = (2, 5)
3723 00:56:24.396070 best DQS1 dly(2T, 0.5T) = (2, 5)
3724 00:56:24.399389 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3725 00:56:24.403167 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3726 00:56:24.403244 Rank: 1
3727 00:56:24.406118 best DQS0 dly(2T, 0.5T) = (2, 5)
3728 00:56:24.409724 best DQS1 dly(2T, 0.5T) = (2, 5)
3729 00:56:24.413129 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3730 00:56:24.416652 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3731 00:56:24.419894 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3732 00:56:24.423055 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3733 00:56:24.426409 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3734 00:56:24.430287
3735 00:56:24.430353
3736 00:56:24.433090 [Calibration Summary] Freqency 1600
3737 00:56:24.433151 CH 0, Rank 0
3738 00:56:24.433204 All Pass.
3739 00:56:24.433257
3740 00:56:24.436598 CH 0, Rank 1
3741 00:56:24.436662 All Pass.
3742 00:56:24.436713
3743 00:56:24.436763 CH 1, Rank 0
3744 00:56:24.439623 All Pass.
3745 00:56:24.439683
3746 00:56:24.439734 CH 1, Rank 1
3747 00:56:24.439783 All Pass.
3748 00:56:24.439835
3749 00:56:24.446551 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3750 00:56:24.453080 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3751 00:56:24.459686 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3752 00:56:24.463104 Write Rank0 MR3 =0xb0
3753 00:56:24.469696 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3754 00:56:24.476669 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3755 00:56:24.482996 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3756 00:56:24.486656 Write Rank1 MR3 =0xb0
3757 00:56:24.493145 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3758 00:56:24.500090 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3759 00:56:24.506580 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3760 00:56:24.506651 Write Rank0 MR3 =0xb0
3761 00:56:24.513329 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3762 00:56:24.523216 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3763 00:56:24.530123 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3764 00:56:24.530258 Write Rank1 MR3 =0xb0
3765 00:56:24.533527 DramC Write-DBI on
3766 00:56:24.536661 [GetDramInforAfterCalByMRR] Vendor 1.
3767 00:56:24.539962 [GetDramInforAfterCalByMRR] Revision 7.
3768 00:56:24.540038 MR8 12
3769 00:56:24.543329 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3770 00:56:24.546659 MR8 12
3771 00:56:24.549956 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3772 00:56:24.550032 MR8 12
3773 00:56:24.556589 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3774 00:56:24.556666 MR8 12
3775 00:56:24.560007 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3776 00:56:24.570271 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3777 00:56:24.573494 Write Rank0 MR13 =0xd0
3778 00:56:24.573568 Write Rank1 MR13 =0xd0
3779 00:56:24.577074 Write Rank0 MR13 =0xd0
3780 00:56:24.580088 Write Rank1 MR13 =0xd0
3781 00:56:24.580171 Save calibration result to emmc
3782 00:56:24.580228
3783 00:56:24.580282
3784 00:56:24.583473 [DramcModeReg_Check] Freq_1600, FSP_1
3785 00:56:24.586773 FSP_1, CH_0, RK0
3786 00:56:24.590112 Write Rank0 MR13 =0xd8
3787 00:56:24.594124 MR12 = 0x56 (global = 0x56) match
3788 00:56:24.594203 MR14 = 0x16 (global = 0x16) match
3789 00:56:24.596780 FSP_1, CH_0, RK1
3790 00:56:24.600242 Write Rank1 MR13 =0xd8
3791 00:56:24.603600 MR12 = 0x56 (global = 0x56) match
3792 00:56:24.603678 MR14 = 0x1a (global = 0x1a) match
3793 00:56:24.606824 FSP_1, CH_1, RK0
3794 00:56:24.610146 Write Rank0 MR13 =0xd8
3795 00:56:24.613667 MR12 = 0x56 (global = 0x56) match
3796 00:56:24.613761 MR14 = 0x1a (global = 0x1a) match
3797 00:56:24.617044 FSP_1, CH_1, RK1
3798 00:56:24.617121 Write Rank1 MR13 =0xd8
3799 00:56:24.620455 MR12 = 0x56 (global = 0x56) match
3800 00:56:24.623553 MR14 = 0x1c (global = 0x1c) match
3801 00:56:24.623652
3802 00:56:24.630762 [MEM_TEST] 02: After DFS, before run time config
3803 00:56:24.640667 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3804 00:56:24.640746
3805 00:56:24.640805 [TA2_TEST]
3806 00:56:24.640861 === TA2 HW
3807 00:56:24.643966 TA2 PAT: XTALK
3808 00:56:24.647144 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3809 00:56:24.653739 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3810 00:56:24.656815 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3811 00:56:24.660495 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3812 00:56:24.663503
3813 00:56:24.663579
3814 00:56:24.663638 Settings after calibration
3815 00:56:24.663693
3816 00:56:24.667142 [DramcRunTimeConfig]
3817 00:56:24.670356 TransferPLLToSPMControl - MODE SW PHYPLL
3818 00:56:24.670433 TX_TRACKING: ON
3819 00:56:24.674042 RX_TRACKING: ON
3820 00:56:24.674118 HW_GATING: ON
3821 00:56:24.677180 HW_GATING DBG: OFF
3822 00:56:24.677257 ddr_geometry:1
3823 00:56:24.680599 ddr_geometry:1
3824 00:56:24.680692 ddr_geometry:1
3825 00:56:24.680784 ddr_geometry:1
3826 00:56:24.683274 ddr_geometry:1
3827 00:56:24.683365 ddr_geometry:1
3828 00:56:24.687152 ddr_geometry:1
3829 00:56:24.687255 ddr_geometry:1
3830 00:56:24.690549 High Freq DUMMY_READ_FOR_TRACKING: ON
3831 00:56:24.693517 ZQCS_ENABLE_LP4: OFF
3832 00:56:24.696958 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3833 00:56:24.700247 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3834 00:56:24.700323 SPM_CONTROL_AFTERK: ON
3835 00:56:24.704045 IMPEDANCE_TRACKING: ON
3836 00:56:24.704121 TEMP_SENSOR: ON
3837 00:56:24.707183 PER_BANK_REFRESH: ON
3838 00:56:24.707260 HW_SAVE_FOR_SR: ON
3839 00:56:24.710368 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3840 00:56:24.713503 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3841 00:56:24.716913 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3842 00:56:24.720488 Read ODT Tracking: ON
3843 00:56:24.723990 =========================
3844 00:56:24.724091
3845 00:56:24.724176 [TA2_TEST]
3846 00:56:24.724257 === TA2 HW
3847 00:56:24.730287 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3848 00:56:24.733752 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3849 00:56:24.740646 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3850 00:56:24.743825 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3851 00:56:24.743902
3852 00:56:24.746999 [MEM_TEST] 03: After run time config
3853 00:56:24.758530 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3854 00:56:24.761569 [complex_mem_test] start addr:0x40024000, len:131072
3855 00:56:24.965558 1st complex R/W mem test pass
3856 00:56:24.972620 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3857 00:56:24.975716 sync preloader write leveling
3858 00:56:24.979106 sync preloader cbt_mr12
3859 00:56:24.982574 sync preloader cbt_clk_dly
3860 00:56:24.982673 sync preloader cbt_cmd_dly
3861 00:56:24.985626 sync preloader cbt_cs
3862 00:56:24.988950 sync preloader cbt_ca_perbit_delay
3863 00:56:24.989028 sync preloader clk_delay
3864 00:56:24.992373 sync preloader dqs_delay
3865 00:56:24.995681 sync preloader u1Gating2T_Save
3866 00:56:24.998872 sync preloader u1Gating05T_Save
3867 00:56:25.002435 sync preloader u1Gatingfine_tune_Save
3868 00:56:25.005831 sync preloader u1Gatingucpass_count_Save
3869 00:56:25.009082 sync preloader u1TxWindowPerbitVref_Save
3870 00:56:25.012588 sync preloader u1TxCenter_min_Save
3871 00:56:25.015683 sync preloader u1TxCenter_max_Save
3872 00:56:25.019420 sync preloader u1Txwin_center_Save
3873 00:56:25.022422 sync preloader u1Txfirst_pass_Save
3874 00:56:25.025710 sync preloader u1Txlast_pass_Save
3875 00:56:25.025787 sync preloader u1RxDatlat_Save
3876 00:56:25.029015 sync preloader u1RxWinPerbitVref_Save
3877 00:56:25.035898 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3878 00:56:25.039260 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3879 00:56:25.042735 sync preloader delay_cell_unit
3880 00:56:25.049477 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3881 00:56:25.052782 sync preloader write leveling
3882 00:56:25.052859 sync preloader cbt_mr12
3883 00:56:25.055929 sync preloader cbt_clk_dly
3884 00:56:25.059350 sync preloader cbt_cmd_dly
3885 00:56:25.059427 sync preloader cbt_cs
3886 00:56:25.062592 sync preloader cbt_ca_perbit_delay
3887 00:56:25.065986 sync preloader clk_delay
3888 00:56:25.066063 sync preloader dqs_delay
3889 00:56:25.069252 sync preloader u1Gating2T_Save
3890 00:56:25.072605 sync preloader u1Gating05T_Save
3891 00:56:25.076097 sync preloader u1Gatingfine_tune_Save
3892 00:56:25.079231 sync preloader u1Gatingucpass_count_Save
3893 00:56:25.082516 sync preloader u1TxWindowPerbitVref_Save
3894 00:56:25.086131 sync preloader u1TxCenter_min_Save
3895 00:56:25.089636 sync preloader u1TxCenter_max_Save
3896 00:56:25.092688 sync preloader u1Txwin_center_Save
3897 00:56:25.096213 sync preloader u1Txfirst_pass_Save
3898 00:56:25.099800 sync preloader u1Txlast_pass_Save
3899 00:56:25.102789 sync preloader u1RxDatlat_Save
3900 00:56:25.106201 sync preloader u1RxWinPerbitVref_Save
3901 00:56:25.110003 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3902 00:56:25.112689 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3903 00:56:25.116080 sync preloader delay_cell_unit
3904 00:56:25.123462 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
3905 00:56:25.126000 sync preloader write leveling
3906 00:56:25.129479 sync preloader cbt_mr12
3907 00:56:25.129556 sync preloader cbt_clk_dly
3908 00:56:25.132617 sync preloader cbt_cmd_dly
3909 00:56:25.136109 sync preloader cbt_cs
3910 00:56:25.136186 sync preloader cbt_ca_perbit_delay
3911 00:56:25.139333 sync preloader clk_delay
3912 00:56:25.142956 sync preloader dqs_delay
3913 00:56:25.146496 sync preloader u1Gating2T_Save
3914 00:56:25.146572 sync preloader u1Gating05T_Save
3915 00:56:25.149417 sync preloader u1Gatingfine_tune_Save
3916 00:56:25.156286 sync preloader u1Gatingucpass_count_Save
3917 00:56:25.159839 sync preloader u1TxWindowPerbitVref_Save
3918 00:56:25.163060 sync preloader u1TxCenter_min_Save
3919 00:56:25.166242 sync preloader u1TxCenter_max_Save
3920 00:56:25.166333 sync preloader u1Txwin_center_Save
3921 00:56:25.169393 sync preloader u1Txfirst_pass_Save
3922 00:56:25.173304 sync preloader u1Txlast_pass_Save
3923 00:56:25.176380 sync preloader u1RxDatlat_Save
3924 00:56:25.179868 sync preloader u1RxWinPerbitVref_Save
3925 00:56:25.183373 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3926 00:56:25.189582 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3927 00:56:25.189660 sync preloader delay_cell_unit
3928 00:56:25.196559 just_for_test_dump_coreboot_params dump all params
3929 00:56:25.196637 dump source = 0x0
3930 00:56:25.199841 dump params frequency:1600
3931 00:56:25.203358 dump params rank number:2
3932 00:56:25.203435
3933 00:56:25.203493 dump params write leveling
3934 00:56:25.206574 write leveling[0][0][0] = 0x21
3935 00:56:25.210019 write leveling[0][0][1] = 0x1b
3936 00:56:25.213077 write leveling[0][1][0] = 0x23
3937 00:56:25.216589 write leveling[0][1][1] = 0x1e
3938 00:56:25.220030 write leveling[1][0][0] = 0x26
3939 00:56:25.220106 write leveling[1][0][1] = 0x21
3940 00:56:25.223162 write leveling[1][1][0] = 0x26
3941 00:56:25.226348 write leveling[1][1][1] = 0x20
3942 00:56:25.230132 dump params cbt_cs
3943 00:56:25.230228 cbt_cs[0][0] = 0x8
3944 00:56:25.233036 cbt_cs[0][1] = 0x8
3945 00:56:25.233112 cbt_cs[1][0] = 0xb
3946 00:56:25.236757 cbt_cs[1][1] = 0xb
3947 00:56:25.236834 dump params cbt_mr12
3948 00:56:25.239958 cbt_mr12[0][0] = 0x16
3949 00:56:25.240035 cbt_mr12[0][1] = 0x16
3950 00:56:25.243154 cbt_mr12[1][0] = 0x16
3951 00:56:25.246712 cbt_mr12[1][1] = 0x16
3952 00:56:25.246789 dump params tx window
3953 00:56:25.250375 tx_center_min[0][0][0] = 979
3954 00:56:25.253490 tx_center_max[0][0][0] = 987
3955 00:56:25.253567 tx_center_min[0][0][1] = 974
3956 00:56:25.256627 tx_center_max[0][0][1] = 979
3957 00:56:25.260273 tx_center_min[0][1][0] = 982
3958 00:56:25.263516 tx_center_max[0][1][0] = 989
3959 00:56:25.267133 tx_center_min[0][1][1] = 978
3960 00:56:25.267211 tx_center_max[0][1][1] = 983
3961 00:56:25.270246 tx_center_min[1][0][0] = 984
3962 00:56:25.273256 tx_center_max[1][0][0] = 989
3963 00:56:25.276874 tx_center_min[1][0][1] = 980
3964 00:56:25.279802 tx_center_max[1][0][1] = 982
3965 00:56:25.279879 tx_center_min[1][1][0] = 984
3966 00:56:25.283226 tx_center_max[1][1][0] = 990
3967 00:56:25.286568 tx_center_min[1][1][1] = 977
3968 00:56:25.290280 tx_center_max[1][1][1] = 980
3969 00:56:25.290358 dump params tx window
3970 00:56:25.293747 tx_win_center[0][0][0] = 987
3971 00:56:25.297013 tx_first_pass[0][0][0] = 975
3972 00:56:25.300007 tx_last_pass[0][0][0] = 999
3973 00:56:25.300083 tx_win_center[0][0][1] = 986
3974 00:56:25.303055 tx_first_pass[0][0][1] = 975
3975 00:56:25.307005 tx_last_pass[0][0][1] = 998
3976 00:56:25.310139 tx_win_center[0][0][2] = 986
3977 00:56:25.313495 tx_first_pass[0][0][2] = 975
3978 00:56:25.313573 tx_last_pass[0][0][2] = 998
3979 00:56:25.316953 tx_win_center[0][0][3] = 979
3980 00:56:25.319924 tx_first_pass[0][0][3] = 968
3981 00:56:25.323330 tx_last_pass[0][0][3] = 991
3982 00:56:25.323407 tx_win_center[0][0][4] = 986
3983 00:56:25.327019 tx_first_pass[0][0][4] = 974
3984 00:56:25.330050 tx_last_pass[0][0][4] = 999
3985 00:56:25.333709 tx_win_center[0][0][5] = 981
3986 00:56:25.333786 tx_first_pass[0][0][5] = 970
3987 00:56:25.336811 tx_last_pass[0][0][5] = 993
3988 00:56:25.340125 tx_win_center[0][0][6] = 983
3989 00:56:25.343534 tx_first_pass[0][0][6] = 971
3990 00:56:25.346587 tx_last_pass[0][0][6] = 995
3991 00:56:25.346664 tx_win_center[0][0][7] = 983
3992 00:56:25.350080 tx_first_pass[0][0][7] = 971
3993 00:56:25.353382 tx_last_pass[0][0][7] = 996
3994 00:56:25.356997 tx_win_center[0][0][8] = 974
3995 00:56:25.357074 tx_first_pass[0][0][8] = 961
3996 00:56:25.360197 tx_last_pass[0][0][8] = 988
3997 00:56:25.363751 tx_win_center[0][0][9] = 976
3998 00:56:25.367047 tx_first_pass[0][0][9] = 963
3999 00:56:25.367124 tx_last_pass[0][0][9] = 989
4000 00:56:25.370425 tx_win_center[0][0][10] = 979
4001 00:56:25.373894 tx_first_pass[0][0][10] = 968
4002 00:56:25.376778 tx_last_pass[0][0][10] = 991
4003 00:56:25.380540 tx_win_center[0][0][11] = 976
4004 00:56:25.383630 tx_first_pass[0][0][11] = 963
4005 00:56:25.383707 tx_last_pass[0][0][11] = 989
4006 00:56:25.386870 tx_win_center[0][0][12] = 976
4007 00:56:25.390430 tx_first_pass[0][0][12] = 964
4008 00:56:25.394024 tx_last_pass[0][0][12] = 989
4009 00:56:25.394100 tx_win_center[0][0][13] = 975
4010 00:56:25.396970 tx_first_pass[0][0][13] = 963
4011 00:56:25.400484 tx_last_pass[0][0][13] = 988
4012 00:56:25.403481 tx_win_center[0][0][14] = 976
4013 00:56:25.406961 tx_first_pass[0][0][14] = 963
4014 00:56:25.407037 tx_last_pass[0][0][14] = 989
4015 00:56:25.410393 tx_win_center[0][0][15] = 978
4016 00:56:25.413724 tx_first_pass[0][0][15] = 966
4017 00:56:25.417106 tx_last_pass[0][0][15] = 991
4018 00:56:25.420364 tx_win_center[0][1][0] = 989
4019 00:56:25.420440 tx_first_pass[0][1][0] = 977
4020 00:56:25.423934 tx_last_pass[0][1][0] = 1002
4021 00:56:25.427178 tx_win_center[0][1][1] = 988
4022 00:56:25.430487 tx_first_pass[0][1][1] = 976
4023 00:56:25.434087 tx_last_pass[0][1][1] = 1000
4024 00:56:25.434163 tx_win_center[0][1][2] = 987
4025 00:56:25.437019 tx_first_pass[0][1][2] = 976
4026 00:56:25.440543 tx_last_pass[0][1][2] = 999
4027 00:56:25.444011 tx_win_center[0][1][3] = 982
4028 00:56:25.444087 tx_first_pass[0][1][3] = 970
4029 00:56:25.447003 tx_last_pass[0][1][3] = 994
4030 00:56:25.450611 tx_win_center[0][1][4] = 988
4031 00:56:25.453655 tx_first_pass[0][1][4] = 976
4032 00:56:25.457308 tx_last_pass[0][1][4] = 1001
4033 00:56:25.457387 tx_win_center[0][1][5] = 983
4034 00:56:25.460302 tx_first_pass[0][1][5] = 971
4035 00:56:25.463812 tx_last_pass[0][1][5] = 995
4036 00:56:25.467319 tx_win_center[0][1][6] = 984
4037 00:56:25.467395 tx_first_pass[0][1][6] = 972
4038 00:56:25.470430 tx_last_pass[0][1][6] = 996
4039 00:56:25.473580 tx_win_center[0][1][7] = 986
4040 00:56:25.477210 tx_first_pass[0][1][7] = 975
4041 00:56:25.480451 tx_last_pass[0][1][7] = 998
4042 00:56:25.480527 tx_win_center[0][1][8] = 978
4043 00:56:25.483687 tx_first_pass[0][1][8] = 966
4044 00:56:25.487187 tx_last_pass[0][1][8] = 990
4045 00:56:25.490483 tx_win_center[0][1][9] = 978
4046 00:56:25.490560 tx_first_pass[0][1][9] = 967
4047 00:56:25.493897 tx_last_pass[0][1][9] = 990
4048 00:56:25.497301 tx_win_center[0][1][10] = 983
4049 00:56:25.500697 tx_first_pass[0][1][10] = 972
4050 00:56:25.504156 tx_last_pass[0][1][10] = 995
4051 00:56:25.504232 tx_win_center[0][1][11] = 979
4052 00:56:25.507602 tx_first_pass[0][1][11] = 967
4053 00:56:25.510752 tx_last_pass[0][1][11] = 991
4054 00:56:25.514243 tx_win_center[0][1][12] = 979
4055 00:56:25.517594 tx_first_pass[0][1][12] = 967
4056 00:56:25.517670 tx_last_pass[0][1][12] = 991
4057 00:56:25.520776 tx_win_center[0][1][13] = 978
4058 00:56:25.524202 tx_first_pass[0][1][13] = 967
4059 00:56:25.527306 tx_last_pass[0][1][13] = 990
4060 00:56:25.530805 tx_win_center[0][1][14] = 978
4061 00:56:25.530882 tx_first_pass[0][1][14] = 967
4062 00:56:25.534119 tx_last_pass[0][1][14] = 990
4063 00:56:25.537630 tx_win_center[0][1][15] = 980
4064 00:56:25.540936 tx_first_pass[0][1][15] = 968
4065 00:56:25.544147 tx_last_pass[0][1][15] = 992
4066 00:56:25.544223 tx_win_center[1][0][0] = 989
4067 00:56:25.548020 tx_first_pass[1][0][0] = 977
4068 00:56:25.551222 tx_last_pass[1][0][0] = 1002
4069 00:56:25.554372 tx_win_center[1][0][1] = 988
4070 00:56:25.554449 tx_first_pass[1][0][1] = 976
4071 00:56:25.557629 tx_last_pass[1][0][1] = 1000
4072 00:56:25.561023 tx_win_center[1][0][2] = 986
4073 00:56:25.564268 tx_first_pass[1][0][2] = 974
4074 00:56:25.567857 tx_last_pass[1][0][2] = 998
4075 00:56:25.567934 tx_win_center[1][0][3] = 984
4076 00:56:25.570743 tx_first_pass[1][0][3] = 973
4077 00:56:25.574261 tx_last_pass[1][0][3] = 996
4078 00:56:25.577618 tx_win_center[1][0][4] = 987
4079 00:56:25.577694 tx_first_pass[1][0][4] = 976
4080 00:56:25.580843 tx_last_pass[1][0][4] = 999
4081 00:56:25.584235 tx_win_center[1][0][5] = 988
4082 00:56:25.587460 tx_first_pass[1][0][5] = 977
4083 00:56:25.587536 tx_last_pass[1][0][5] = 1000
4084 00:56:25.591088 tx_win_center[1][0][6] = 989
4085 00:56:25.594703 tx_first_pass[1][0][6] = 977
4086 00:56:25.597825 tx_last_pass[1][0][6] = 1001
4087 00:56:25.601007 tx_win_center[1][0][7] = 987
4088 00:56:25.601084 tx_first_pass[1][0][7] = 976
4089 00:56:25.604532 tx_last_pass[1][0][7] = 999
4090 00:56:25.607861 tx_win_center[1][0][8] = 980
4091 00:56:25.610845 tx_first_pass[1][0][8] = 969
4092 00:56:25.610923 tx_last_pass[1][0][8] = 992
4093 00:56:25.614730 tx_win_center[1][0][9] = 980
4094 00:56:25.617542 tx_first_pass[1][0][9] = 969
4095 00:56:25.620817 tx_last_pass[1][0][9] = 992
4096 00:56:25.624530 tx_win_center[1][0][10] = 981
4097 00:56:25.624606 tx_first_pass[1][0][10] = 969
4098 00:56:25.627830 tx_last_pass[1][0][10] = 993
4099 00:56:25.630982 tx_win_center[1][0][11] = 982
4100 00:56:25.634424 tx_first_pass[1][0][11] = 970
4101 00:56:25.637561 tx_last_pass[1][0][11] = 994
4102 00:56:25.637638 tx_win_center[1][0][12] = 982
4103 00:56:25.641171 tx_first_pass[1][0][12] = 971
4104 00:56:25.644433 tx_last_pass[1][0][12] = 994
4105 00:56:25.647984 tx_win_center[1][0][13] = 982
4106 00:56:25.651004 tx_first_pass[1][0][13] = 971
4107 00:56:25.651080 tx_last_pass[1][0][13] = 993
4108 00:56:25.654529 tx_win_center[1][0][14] = 981
4109 00:56:25.657612 tx_first_pass[1][0][14] = 970
4110 00:56:25.661100 tx_last_pass[1][0][14] = 992
4111 00:56:25.664079 tx_win_center[1][0][15] = 980
4112 00:56:25.664155 tx_first_pass[1][0][15] = 968
4113 00:56:25.667952 tx_last_pass[1][0][15] = 992
4114 00:56:25.670925 tx_win_center[1][1][0] = 990
4115 00:56:25.674506 tx_first_pass[1][1][0] = 977
4116 00:56:25.677680 tx_last_pass[1][1][0] = 1003
4117 00:56:25.677775 tx_win_center[1][1][1] = 988
4118 00:56:25.681151 tx_first_pass[1][1][1] = 976
4119 00:56:25.684524 tx_last_pass[1][1][1] = 1000
4120 00:56:25.687702 tx_win_center[1][1][2] = 985
4121 00:56:25.687779 tx_first_pass[1][1][2] = 973
4122 00:56:25.691213 tx_last_pass[1][1][2] = 997
4123 00:56:25.694636 tx_win_center[1][1][3] = 984
4124 00:56:25.698110 tx_first_pass[1][1][3] = 972
4125 00:56:25.701159 tx_last_pass[1][1][3] = 997
4126 00:56:25.701236 tx_win_center[1][1][4] = 987
4127 00:56:25.704503 tx_first_pass[1][1][4] = 975
4128 00:56:25.708027 tx_last_pass[1][1][4] = 999
4129 00:56:25.711084 tx_win_center[1][1][5] = 989
4130 00:56:25.711161 tx_first_pass[1][1][5] = 977
4131 00:56:25.714851 tx_last_pass[1][1][5] = 1001
4132 00:56:25.717918 tx_win_center[1][1][6] = 989
4133 00:56:25.721148 tx_first_pass[1][1][6] = 977
4134 00:56:25.724473 tx_last_pass[1][1][6] = 1002
4135 00:56:25.724564 tx_win_center[1][1][7] = 986
4136 00:56:25.727787 tx_first_pass[1][1][7] = 975
4137 00:56:25.730944 tx_last_pass[1][1][7] = 998
4138 00:56:25.734561 tx_win_center[1][1][8] = 979
4139 00:56:25.734639 tx_first_pass[1][1][8] = 968
4140 00:56:25.738154 tx_last_pass[1][1][8] = 991
4141 00:56:25.741382 tx_win_center[1][1][9] = 979
4142 00:56:25.744491 tx_first_pass[1][1][9] = 968
4143 00:56:25.747919 tx_last_pass[1][1][9] = 991
4144 00:56:25.748030 tx_win_center[1][1][10] = 979
4145 00:56:25.751351 tx_first_pass[1][1][10] = 968
4146 00:56:25.754592 tx_last_pass[1][1][10] = 991
4147 00:56:25.757720 tx_win_center[1][1][11] = 980
4148 00:56:25.761105 tx_first_pass[1][1][11] = 969
4149 00:56:25.761183 tx_last_pass[1][1][11] = 992
4150 00:56:25.764554 tx_win_center[1][1][12] = 980
4151 00:56:25.767994 tx_first_pass[1][1][12] = 969
4152 00:56:25.771920 tx_last_pass[1][1][12] = 992
4153 00:56:25.774396 tx_win_center[1][1][13] = 980
4154 00:56:25.774473 tx_first_pass[1][1][13] = 969
4155 00:56:25.777735 tx_last_pass[1][1][13] = 992
4156 00:56:25.781109 tx_win_center[1][1][14] = 980
4157 00:56:25.784727 tx_first_pass[1][1][14] = 969
4158 00:56:25.787792 tx_last_pass[1][1][14] = 992
4159 00:56:25.787870 tx_win_center[1][1][15] = 977
4160 00:56:25.791319 tx_first_pass[1][1][15] = 965
4161 00:56:25.794487 tx_last_pass[1][1][15] = 990
4162 00:56:25.797608 dump params rx window
4163 00:56:25.797685 rx_firspass[0][0][0] = 8
4164 00:56:25.800936 rx_lastpass[0][0][0] = 40
4165 00:56:25.804595 rx_firspass[0][0][1] = 6
4166 00:56:25.804670 rx_lastpass[0][0][1] = 39
4167 00:56:25.807789 rx_firspass[0][0][2] = 8
4168 00:56:25.811545 rx_lastpass[0][0][2] = 38
4169 00:56:25.811645 rx_firspass[0][0][3] = -4
4170 00:56:25.814224 rx_lastpass[0][0][3] = 29
4171 00:56:25.817598 rx_firspass[0][0][4] = 6
4172 00:56:25.821169 rx_lastpass[0][0][4] = 38
4173 00:56:25.821245 rx_firspass[0][0][5] = -1
4174 00:56:25.824562 rx_lastpass[0][0][5] = 30
4175 00:56:25.827922 rx_firspass[0][0][6] = 1
4176 00:56:25.827998 rx_lastpass[0][0][6] = 32
4177 00:56:25.831064 rx_firspass[0][0][7] = 3
4178 00:56:25.834583 rx_lastpass[0][0][7] = 32
4179 00:56:25.834659 rx_firspass[0][0][8] = 0
4180 00:56:25.837722 rx_lastpass[0][0][8] = 34
4181 00:56:25.841175 rx_firspass[0][0][9] = 4
4182 00:56:25.844396 rx_lastpass[0][0][9] = 34
4183 00:56:25.844472 rx_firspass[0][0][10] = 6
4184 00:56:25.847961 rx_lastpass[0][0][10] = 38
4185 00:56:25.850947 rx_firspass[0][0][11] = 0
4186 00:56:25.851028 rx_lastpass[0][0][11] = 34
4187 00:56:25.854202 rx_firspass[0][0][12] = 1
4188 00:56:25.857588 rx_lastpass[0][0][12] = 36
4189 00:56:25.861042 rx_firspass[0][0][13] = 2
4190 00:56:25.861113 rx_lastpass[0][0][13] = 30
4191 00:56:25.864535 rx_firspass[0][0][14] = -1
4192 00:56:25.867890 rx_lastpass[0][0][14] = 36
4193 00:56:25.871140 rx_firspass[0][0][15] = 3
4194 00:56:25.871217 rx_lastpass[0][0][15] = 36
4195 00:56:25.874866 rx_firspass[0][1][0] = 7
4196 00:56:25.877849 rx_lastpass[0][1][0] = 42
4197 00:56:25.877949 rx_firspass[0][1][1] = 5
4198 00:56:25.881363 rx_lastpass[0][1][1] = 40
4199 00:56:25.884848 rx_firspass[0][1][2] = 7
4200 00:56:25.884925 rx_lastpass[0][1][2] = 39
4201 00:56:25.888039 rx_firspass[0][1][3] = -4
4202 00:56:25.891506 rx_lastpass[0][1][3] = 31
4203 00:56:25.894667 rx_firspass[0][1][4] = 6
4204 00:56:25.894743 rx_lastpass[0][1][4] = 40
4205 00:56:25.898028 rx_firspass[0][1][5] = -2
4206 00:56:25.901421 rx_lastpass[0][1][5] = 33
4207 00:56:25.901498 rx_firspass[0][1][6] = 1
4208 00:56:25.904679 rx_lastpass[0][1][6] = 35
4209 00:56:25.908141 rx_firspass[0][1][7] = 2
4210 00:56:25.908218 rx_lastpass[0][1][7] = 34
4211 00:56:25.911596 rx_firspass[0][1][8] = 0
4212 00:56:25.914558 rx_lastpass[0][1][8] = 35
4213 00:56:25.914632 rx_firspass[0][1][9] = 2
4214 00:56:25.918147 rx_lastpass[0][1][9] = 36
4215 00:56:25.921252 rx_firspass[0][1][10] = 6
4216 00:56:25.924688 rx_lastpass[0][1][10] = 40
4217 00:56:25.924758 rx_firspass[0][1][11] = 0
4218 00:56:25.928195 rx_lastpass[0][1][11] = 34
4219 00:56:25.931641 rx_firspass[0][1][12] = 2
4220 00:56:25.934664 rx_lastpass[0][1][12] = 37
4221 00:56:25.934741 rx_firspass[0][1][13] = 1
4222 00:56:25.938169 rx_lastpass[0][1][13] = 33
4223 00:56:25.941413 rx_firspass[0][1][14] = 2
4224 00:56:25.941490 rx_lastpass[0][1][14] = 34
4225 00:56:25.944951 rx_firspass[0][1][15] = 3
4226 00:56:25.948180 rx_lastpass[0][1][15] = 38
4227 00:56:25.951637 rx_firspass[1][0][0] = 7
4228 00:56:25.951714 rx_lastpass[1][0][0] = 40
4229 00:56:25.955102 rx_firspass[1][0][1] = 6
4230 00:56:25.958075 rx_lastpass[1][0][1] = 40
4231 00:56:25.958151 rx_firspass[1][0][2] = 0
4232 00:56:25.961605 rx_lastpass[1][0][2] = 34
4233 00:56:25.964851 rx_firspass[1][0][3] = -2
4234 00:56:25.964928 rx_lastpass[1][0][3] = 32
4235 00:56:25.968064 rx_firspass[1][0][4] = 4
4236 00:56:25.971644 rx_lastpass[1][0][4] = 35
4237 00:56:25.974574 rx_firspass[1][0][5] = 8
4238 00:56:25.974650 rx_lastpass[1][0][5] = 40
4239 00:56:25.978208 rx_firspass[1][0][6] = 9
4240 00:56:25.981363 rx_lastpass[1][0][6] = 40
4241 00:56:25.981439 rx_firspass[1][0][7] = 4
4242 00:56:25.984967 rx_lastpass[1][0][7] = 35
4243 00:56:25.988189 rx_firspass[1][0][8] = 1
4244 00:56:25.988266 rx_lastpass[1][0][8] = 35
4245 00:56:25.991553 rx_firspass[1][0][9] = 0
4246 00:56:25.995322 rx_lastpass[1][0][9] = 35
4247 00:56:25.995399 rx_firspass[1][0][10] = 1
4248 00:56:25.998319 rx_lastpass[1][0][10] = 33
4249 00:56:26.001644 rx_firspass[1][0][11] = 1
4250 00:56:26.005087 rx_lastpass[1][0][11] = 36
4251 00:56:26.005174 rx_firspass[1][0][12] = 4
4252 00:56:26.008270 rx_lastpass[1][0][12] = 37
4253 00:56:26.011869 rx_firspass[1][0][13] = 3
4254 00:56:26.014895 rx_lastpass[1][0][13] = 35
4255 00:56:26.014967 rx_firspass[1][0][14] = 3
4256 00:56:26.018425 rx_lastpass[1][0][14] = 35
4257 00:56:26.021812 rx_firspass[1][0][15] = -1
4258 00:56:26.021880 rx_lastpass[1][0][15] = 31
4259 00:56:26.025261 rx_firspass[1][1][0] = 7
4260 00:56:26.028583 rx_lastpass[1][1][0] = 42
4261 00:56:26.031751 rx_firspass[1][1][1] = 6
4262 00:56:26.031826 rx_lastpass[1][1][1] = 41
4263 00:56:26.034996 rx_firspass[1][1][2] = 0
4264 00:56:26.038349 rx_lastpass[1][1][2] = 34
4265 00:56:26.038414 rx_firspass[1][1][3] = -2
4266 00:56:26.041700 rx_lastpass[1][1][3] = 32
4267 00:56:26.045026 rx_firspass[1][1][4] = 3
4268 00:56:26.045096 rx_lastpass[1][1][4] = 37
4269 00:56:26.048492 rx_firspass[1][1][5] = 7
4270 00:56:26.051725 rx_lastpass[1][1][5] = 40
4271 00:56:26.055170 rx_firspass[1][1][6] = 7
4272 00:56:26.055244 rx_lastpass[1][1][6] = 42
4273 00:56:26.058669 rx_firspass[1][1][7] = 3
4274 00:56:26.062120 rx_lastpass[1][1][7] = 38
4275 00:56:26.062230 rx_firspass[1][1][8] = 1
4276 00:56:26.065398 rx_lastpass[1][1][8] = 36
4277 00:56:26.068521 rx_firspass[1][1][9] = 1
4278 00:56:26.068598 rx_lastpass[1][1][9] = 36
4279 00:56:26.071791 rx_firspass[1][1][10] = 1
4280 00:56:26.075467 rx_lastpass[1][1][10] = 36
4281 00:56:26.079138 rx_firspass[1][1][11] = 3
4282 00:56:26.079229 rx_lastpass[1][1][11] = 36
4283 00:56:26.081926 rx_firspass[1][1][12] = 5
4284 00:56:26.085338 rx_lastpass[1][1][12] = 39
4285 00:56:26.085403 rx_firspass[1][1][13] = 4
4286 00:56:26.088653 rx_lastpass[1][1][13] = 38
4287 00:56:26.091868 rx_firspass[1][1][14] = 4
4288 00:56:26.095556 rx_lastpass[1][1][14] = 37
4289 00:56:26.095624 rx_firspass[1][1][15] = -2
4290 00:56:26.098473 rx_lastpass[1][1][15] = 32
4291 00:56:26.102294 dump params clk_delay
4292 00:56:26.102371 clk_delay[0] = 0
4293 00:56:26.105447 clk_delay[1] = 0
4294 00:56:26.105524 dump params dqs_delay
4295 00:56:26.108666 dqs_delay[0][0] = -1
4296 00:56:26.108743 dqs_delay[0][1] = 2
4297 00:56:26.111942 dqs_delay[1][0] = 0
4298 00:56:26.112018 dqs_delay[1][1] = 0
4299 00:56:26.115138 dump params delay_cell_unit = 753
4300 00:56:26.118835 dump source = 0x0
4301 00:56:26.121952 dump params frequency:1200
4302 00:56:26.122028 dump params rank number:2
4303 00:56:26.122087
4304 00:56:26.125339 dump params write leveling
4305 00:56:26.128726 write leveling[0][0][0] = 0x0
4306 00:56:26.132275 write leveling[0][0][1] = 0x0
4307 00:56:26.132352 write leveling[0][1][0] = 0x0
4308 00:56:26.135677 write leveling[0][1][1] = 0x0
4309 00:56:26.139170 write leveling[1][0][0] = 0x0
4310 00:56:26.142526 write leveling[1][0][1] = 0x0
4311 00:56:26.145775 write leveling[1][1][0] = 0x0
4312 00:56:26.145852 write leveling[1][1][1] = 0x0
4313 00:56:26.149225 dump params cbt_cs
4314 00:56:26.149312 cbt_cs[0][0] = 0x0
4315 00:56:26.152581 cbt_cs[0][1] = 0x0
4316 00:56:26.152658 cbt_cs[1][0] = 0x0
4317 00:56:26.155704 cbt_cs[1][1] = 0x0
4318 00:56:26.155780 dump params cbt_mr12
4319 00:56:26.159204 cbt_mr12[0][0] = 0x0
4320 00:56:26.162591 cbt_mr12[0][1] = 0x0
4321 00:56:26.162668 cbt_mr12[1][0] = 0x0
4322 00:56:26.165692 cbt_mr12[1][1] = 0x0
4323 00:56:26.165768 dump params tx window
4324 00:56:26.169091 tx_center_min[0][0][0] = 0
4325 00:56:26.172569 tx_center_max[0][0][0] = 0
4326 00:56:26.175943 tx_center_min[0][0][1] = 0
4327 00:56:26.176045 tx_center_max[0][0][1] = 0
4328 00:56:26.179481 tx_center_min[0][1][0] = 0
4329 00:56:26.182507 tx_center_max[0][1][0] = 0
4330 00:56:26.182584 tx_center_min[0][1][1] = 0
4331 00:56:26.185983 tx_center_max[0][1][1] = 0
4332 00:56:26.188981 tx_center_min[1][0][0] = 0
4333 00:56:26.192862 tx_center_max[1][0][0] = 0
4334 00:56:26.192939 tx_center_min[1][0][1] = 0
4335 00:56:26.195813 tx_center_max[1][0][1] = 0
4336 00:56:26.199300 tx_center_min[1][1][0] = 0
4337 00:56:26.202532 tx_center_max[1][1][0] = 0
4338 00:56:26.202609 tx_center_min[1][1][1] = 0
4339 00:56:26.205883 tx_center_max[1][1][1] = 0
4340 00:56:26.209193 dump params tx window
4341 00:56:26.209270 tx_win_center[0][0][0] = 0
4342 00:56:26.212732 tx_first_pass[0][0][0] = 0
4343 00:56:26.215979 tx_last_pass[0][0][0] = 0
4344 00:56:26.219237 tx_win_center[0][0][1] = 0
4345 00:56:26.219314 tx_first_pass[0][0][1] = 0
4346 00:56:26.222475 tx_last_pass[0][0][1] = 0
4347 00:56:26.226147 tx_win_center[0][0][2] = 0
4348 00:56:26.229202 tx_first_pass[0][0][2] = 0
4349 00:56:26.229294 tx_last_pass[0][0][2] = 0
4350 00:56:26.232387 tx_win_center[0][0][3] = 0
4351 00:56:26.235903 tx_first_pass[0][0][3] = 0
4352 00:56:26.235969 tx_last_pass[0][0][3] = 0
4353 00:56:26.239304 tx_win_center[0][0][4] = 0
4354 00:56:26.242799 tx_first_pass[0][0][4] = 0
4355 00:56:26.246118 tx_last_pass[0][0][4] = 0
4356 00:56:26.246260 tx_win_center[0][0][5] = 0
4357 00:56:26.249261 tx_first_pass[0][0][5] = 0
4358 00:56:26.252744 tx_last_pass[0][0][5] = 0
4359 00:56:26.252837 tx_win_center[0][0][6] = 0
4360 00:56:26.255923 tx_first_pass[0][0][6] = 0
4361 00:56:26.259298 tx_last_pass[0][0][6] = 0
4362 00:56:26.262625 tx_win_center[0][0][7] = 0
4363 00:56:26.262702 tx_first_pass[0][0][7] = 0
4364 00:56:26.266116 tx_last_pass[0][0][7] = 0
4365 00:56:26.269116 tx_win_center[0][0][8] = 0
4366 00:56:26.272683 tx_first_pass[0][0][8] = 0
4367 00:56:26.272760 tx_last_pass[0][0][8] = 0
4368 00:56:26.276136 tx_win_center[0][0][9] = 0
4369 00:56:26.279437 tx_first_pass[0][0][9] = 0
4370 00:56:26.279513 tx_last_pass[0][0][9] = 0
4371 00:56:26.282895 tx_win_center[0][0][10] = 0
4372 00:56:26.285985 tx_first_pass[0][0][10] = 0
4373 00:56:26.289485 tx_last_pass[0][0][10] = 0
4374 00:56:26.289561 tx_win_center[0][0][11] = 0
4375 00:56:26.292612 tx_first_pass[0][0][11] = 0
4376 00:56:26.295861 tx_last_pass[0][0][11] = 0
4377 00:56:26.299366 tx_win_center[0][0][12] = 0
4378 00:56:26.299442 tx_first_pass[0][0][12] = 0
4379 00:56:26.302613 tx_last_pass[0][0][12] = 0
4380 00:56:26.306084 tx_win_center[0][0][13] = 0
4381 00:56:26.309392 tx_first_pass[0][0][13] = 0
4382 00:56:26.309468 tx_last_pass[0][0][13] = 0
4383 00:56:26.312862 tx_win_center[0][0][14] = 0
4384 00:56:26.316215 tx_first_pass[0][0][14] = 0
4385 00:56:26.319448 tx_last_pass[0][0][14] = 0
4386 00:56:26.319524 tx_win_center[0][0][15] = 0
4387 00:56:26.323068 tx_first_pass[0][0][15] = 0
4388 00:56:26.326110 tx_last_pass[0][0][15] = 0
4389 00:56:26.329447 tx_win_center[0][1][0] = 0
4390 00:56:26.329523 tx_first_pass[0][1][0] = 0
4391 00:56:26.333223 tx_last_pass[0][1][0] = 0
4392 00:56:26.336241 tx_win_center[0][1][1] = 0
4393 00:56:26.336318 tx_first_pass[0][1][1] = 0
4394 00:56:26.339574 tx_last_pass[0][1][1] = 0
4395 00:56:26.343064 tx_win_center[0][1][2] = 0
4396 00:56:26.346333 tx_first_pass[0][1][2] = 0
4397 00:56:26.346409 tx_last_pass[0][1][2] = 0
4398 00:56:26.349385 tx_win_center[0][1][3] = 0
4399 00:56:26.352817 tx_first_pass[0][1][3] = 0
4400 00:56:26.352893 tx_last_pass[0][1][3] = 0
4401 00:56:26.356570 tx_win_center[0][1][4] = 0
4402 00:56:26.359417 tx_first_pass[0][1][4] = 0
4403 00:56:26.363028 tx_last_pass[0][1][4] = 0
4404 00:56:26.363104 tx_win_center[0][1][5] = 0
4405 00:56:26.366102 tx_first_pass[0][1][5] = 0
4406 00:56:26.369627 tx_last_pass[0][1][5] = 0
4407 00:56:26.372986 tx_win_center[0][1][6] = 0
4408 00:56:26.373062 tx_first_pass[0][1][6] = 0
4409 00:56:26.376360 tx_last_pass[0][1][6] = 0
4410 00:56:26.379660 tx_win_center[0][1][7] = 0
4411 00:56:26.379737 tx_first_pass[0][1][7] = 0
4412 00:56:26.383004 tx_last_pass[0][1][7] = 0
4413 00:56:26.386473 tx_win_center[0][1][8] = 0
4414 00:56:26.389512 tx_first_pass[0][1][8] = 0
4415 00:56:26.389588 tx_last_pass[0][1][8] = 0
4416 00:56:26.393284 tx_win_center[0][1][9] = 0
4417 00:56:26.396550 tx_first_pass[0][1][9] = 0
4418 00:56:26.396626 tx_last_pass[0][1][9] = 0
4419 00:56:26.399927 tx_win_center[0][1][10] = 0
4420 00:56:26.403223 tx_first_pass[0][1][10] = 0
4421 00:56:26.406145 tx_last_pass[0][1][10] = 0
4422 00:56:26.406278 tx_win_center[0][1][11] = 0
4423 00:56:26.409727 tx_first_pass[0][1][11] = 0
4424 00:56:26.413190 tx_last_pass[0][1][11] = 0
4425 00:56:26.416255 tx_win_center[0][1][12] = 0
4426 00:56:26.416331 tx_first_pass[0][1][12] = 0
4427 00:56:26.419731 tx_last_pass[0][1][12] = 0
4428 00:56:26.423183 tx_win_center[0][1][13] = 0
4429 00:56:26.426409 tx_first_pass[0][1][13] = 0
4430 00:56:26.426485 tx_last_pass[0][1][13] = 0
4431 00:56:26.429573 tx_win_center[0][1][14] = 0
4432 00:56:26.433320 tx_first_pass[0][1][14] = 0
4433 00:56:26.436338 tx_last_pass[0][1][14] = 0
4434 00:56:26.436414 tx_win_center[0][1][15] = 0
4435 00:56:26.439743 tx_first_pass[0][1][15] = 0
4436 00:56:26.443100 tx_last_pass[0][1][15] = 0
4437 00:56:26.446406 tx_win_center[1][0][0] = 0
4438 00:56:26.446482 tx_first_pass[1][0][0] = 0
4439 00:56:26.449620 tx_last_pass[1][0][0] = 0
4440 00:56:26.452930 tx_win_center[1][0][1] = 0
4441 00:56:26.456389 tx_first_pass[1][0][1] = 0
4442 00:56:26.456465 tx_last_pass[1][0][1] = 0
4443 00:56:26.459818 tx_win_center[1][0][2] = 0
4444 00:56:26.463164 tx_first_pass[1][0][2] = 0
4445 00:56:26.463240 tx_last_pass[1][0][2] = 0
4446 00:56:26.466584 tx_win_center[1][0][3] = 0
4447 00:56:26.470300 tx_first_pass[1][0][3] = 0
4448 00:56:26.473220 tx_last_pass[1][0][3] = 0
4449 00:56:26.473296 tx_win_center[1][0][4] = 0
4450 00:56:26.476458 tx_first_pass[1][0][4] = 0
4451 00:56:26.480129 tx_last_pass[1][0][4] = 0
4452 00:56:26.480206 tx_win_center[1][0][5] = 0
4453 00:56:26.483224 tx_first_pass[1][0][5] = 0
4454 00:56:26.486650 tx_last_pass[1][0][5] = 0
4455 00:56:26.489970 tx_win_center[1][0][6] = 0
4456 00:56:26.490046 tx_first_pass[1][0][6] = 0
4457 00:56:26.493293 tx_last_pass[1][0][6] = 0
4458 00:56:26.496810 tx_win_center[1][0][7] = 0
4459 00:56:26.500003 tx_first_pass[1][0][7] = 0
4460 00:56:26.500079 tx_last_pass[1][0][7] = 0
4461 00:56:26.503343 tx_win_center[1][0][8] = 0
4462 00:56:26.506750 tx_first_pass[1][0][8] = 0
4463 00:56:26.506826 tx_last_pass[1][0][8] = 0
4464 00:56:26.510407 tx_win_center[1][0][9] = 0
4465 00:56:26.513522 tx_first_pass[1][0][9] = 0
4466 00:56:26.516931 tx_last_pass[1][0][9] = 0
4467 00:56:26.517008 tx_win_center[1][0][10] = 0
4468 00:56:26.520152 tx_first_pass[1][0][10] = 0
4469 00:56:26.523350 tx_last_pass[1][0][10] = 0
4470 00:56:26.527050 tx_win_center[1][0][11] = 0
4471 00:56:26.527126 tx_first_pass[1][0][11] = 0
4472 00:56:26.529927 tx_last_pass[1][0][11] = 0
4473 00:56:26.533491 tx_win_center[1][0][12] = 0
4474 00:56:26.536602 tx_first_pass[1][0][12] = 0
4475 00:56:26.536709 tx_last_pass[1][0][12] = 0
4476 00:56:26.540207 tx_win_center[1][0][13] = 0
4477 00:56:26.543237 tx_first_pass[1][0][13] = 0
4478 00:56:26.546548 tx_last_pass[1][0][13] = 0
4479 00:56:26.546620 tx_win_center[1][0][14] = 0
4480 00:56:26.549893 tx_first_pass[1][0][14] = 0
4481 00:56:26.553831 tx_last_pass[1][0][14] = 0
4482 00:56:26.556493 tx_win_center[1][0][15] = 0
4483 00:56:26.556584 tx_first_pass[1][0][15] = 0
4484 00:56:26.560164 tx_last_pass[1][0][15] = 0
4485 00:56:26.563223 tx_win_center[1][1][0] = 0
4486 00:56:26.566689 tx_first_pass[1][1][0] = 0
4487 00:56:26.566760 tx_last_pass[1][1][0] = 0
4488 00:56:26.570129 tx_win_center[1][1][1] = 0
4489 00:56:26.573614 tx_first_pass[1][1][1] = 0
4490 00:56:26.573711 tx_last_pass[1][1][1] = 0
4491 00:56:26.576678 tx_win_center[1][1][2] = 0
4492 00:56:26.580097 tx_first_pass[1][1][2] = 0
4493 00:56:26.583985 tx_last_pass[1][1][2] = 0
4494 00:56:26.584062 tx_win_center[1][1][3] = 0
4495 00:56:26.587052 tx_first_pass[1][1][3] = 0
4496 00:56:26.590289 tx_last_pass[1][1][3] = 0
4497 00:56:26.590366 tx_win_center[1][1][4] = 0
4498 00:56:26.593830 tx_first_pass[1][1][4] = 0
4499 00:56:26.596778 tx_last_pass[1][1][4] = 0
4500 00:56:26.600372 tx_win_center[1][1][5] = 0
4501 00:56:26.600449 tx_first_pass[1][1][5] = 0
4502 00:56:26.603496 tx_last_pass[1][1][5] = 0
4503 00:56:26.606949 tx_win_center[1][1][6] = 0
4504 00:56:26.610711 tx_first_pass[1][1][6] = 0
4505 00:56:26.610791 tx_last_pass[1][1][6] = 0
4506 00:56:26.613443 tx_win_center[1][1][7] = 0
4507 00:56:26.616662 tx_first_pass[1][1][7] = 0
4508 00:56:26.616763 tx_last_pass[1][1][7] = 0
4509 00:56:26.620603 tx_win_center[1][1][8] = 0
4510 00:56:26.623471 tx_first_pass[1][1][8] = 0
4511 00:56:26.626888 tx_last_pass[1][1][8] = 0
4512 00:56:26.626966 tx_win_center[1][1][9] = 0
4513 00:56:26.630600 tx_first_pass[1][1][9] = 0
4514 00:56:26.633766 tx_last_pass[1][1][9] = 0
4515 00:56:26.633843 tx_win_center[1][1][10] = 0
4516 00:56:26.636981 tx_first_pass[1][1][10] = 0
4517 00:56:26.639949 tx_last_pass[1][1][10] = 0
4518 00:56:26.643805 tx_win_center[1][1][11] = 0
4519 00:56:26.647130 tx_first_pass[1][1][11] = 0
4520 00:56:26.647207 tx_last_pass[1][1][11] = 0
4521 00:56:26.650162 tx_win_center[1][1][12] = 0
4522 00:56:26.653601 tx_first_pass[1][1][12] = 0
4523 00:56:26.653690 tx_last_pass[1][1][12] = 0
4524 00:56:26.657199 tx_win_center[1][1][13] = 0
4525 00:56:26.660008 tx_first_pass[1][1][13] = 0
4526 00:56:26.663694 tx_last_pass[1][1][13] = 0
4527 00:56:26.663771 tx_win_center[1][1][14] = 0
4528 00:56:26.666910 tx_first_pass[1][1][14] = 0
4529 00:56:26.670322 tx_last_pass[1][1][14] = 0
4530 00:56:26.673890 tx_win_center[1][1][15] = 0
4531 00:56:26.673967 tx_first_pass[1][1][15] = 0
4532 00:56:26.677076 tx_last_pass[1][1][15] = 0
4533 00:56:26.680581 dump params rx window
4534 00:56:26.680657 rx_firspass[0][0][0] = 0
4535 00:56:26.683757 rx_lastpass[0][0][0] = 0
4536 00:56:26.686943 rx_firspass[0][0][1] = 0
4537 00:56:26.690574 rx_lastpass[0][0][1] = 0
4538 00:56:26.690651 rx_firspass[0][0][2] = 0
4539 00:56:26.693501 rx_lastpass[0][0][2] = 0
4540 00:56:26.697340 rx_firspass[0][0][3] = 0
4541 00:56:26.697416 rx_lastpass[0][0][3] = 0
4542 00:56:26.700385 rx_firspass[0][0][4] = 0
4543 00:56:26.703864 rx_lastpass[0][0][4] = 0
4544 00:56:26.703941 rx_firspass[0][0][5] = 0
4545 00:56:26.706894 rx_lastpass[0][0][5] = 0
4546 00:56:26.710197 rx_firspass[0][0][6] = 0
4547 00:56:26.710333 rx_lastpass[0][0][6] = 0
4548 00:56:26.713617 rx_firspass[0][0][7] = 0
4549 00:56:26.716827 rx_lastpass[0][0][7] = 0
4550 00:56:26.716903 rx_firspass[0][0][8] = 0
4551 00:56:26.720570 rx_lastpass[0][0][8] = 0
4552 00:56:26.723565 rx_firspass[0][0][9] = 0
4553 00:56:26.723641 rx_lastpass[0][0][9] = 0
4554 00:56:26.727242 rx_firspass[0][0][10] = 0
4555 00:56:26.730617 rx_lastpass[0][0][10] = 0
4556 00:56:26.733824 rx_firspass[0][0][11] = 0
4557 00:56:26.733900 rx_lastpass[0][0][11] = 0
4558 00:56:26.737116 rx_firspass[0][0][12] = 0
4559 00:56:26.740350 rx_lastpass[0][0][12] = 0
4560 00:56:26.740426 rx_firspass[0][0][13] = 0
4561 00:56:26.743679 rx_lastpass[0][0][13] = 0
4562 00:56:26.747206 rx_firspass[0][0][14] = 0
4563 00:56:26.750318 rx_lastpass[0][0][14] = 0
4564 00:56:26.750413 rx_firspass[0][0][15] = 0
4565 00:56:26.753970 rx_lastpass[0][0][15] = 0
4566 00:56:26.757508 rx_firspass[0][1][0] = 0
4567 00:56:26.757600 rx_lastpass[0][1][0] = 0
4568 00:56:26.760687 rx_firspass[0][1][1] = 0
4569 00:56:26.763890 rx_lastpass[0][1][1] = 0
4570 00:56:26.763980 rx_firspass[0][1][2] = 0
4571 00:56:26.767088 rx_lastpass[0][1][2] = 0
4572 00:56:26.770424 rx_firspass[0][1][3] = 0
4573 00:56:26.770491 rx_lastpass[0][1][3] = 0
4574 00:56:26.773999 rx_firspass[0][1][4] = 0
4575 00:56:26.777394 rx_lastpass[0][1][4] = 0
4576 00:56:26.777483 rx_firspass[0][1][5] = 0
4577 00:56:26.780959 rx_lastpass[0][1][5] = 0
4578 00:56:26.783942 rx_firspass[0][1][6] = 0
4579 00:56:26.787468 rx_lastpass[0][1][6] = 0
4580 00:56:26.787544 rx_firspass[0][1][7] = 0
4581 00:56:26.790846 rx_lastpass[0][1][7] = 0
4582 00:56:26.794298 rx_firspass[0][1][8] = 0
4583 00:56:26.794395 rx_lastpass[0][1][8] = 0
4584 00:56:26.797309 rx_firspass[0][1][9] = 0
4585 00:56:26.800447 rx_lastpass[0][1][9] = 0
4586 00:56:26.800539 rx_firspass[0][1][10] = 0
4587 00:56:26.804415 rx_lastpass[0][1][10] = 0
4588 00:56:26.807531 rx_firspass[0][1][11] = 0
4589 00:56:26.807622 rx_lastpass[0][1][11] = 0
4590 00:56:26.810643 rx_firspass[0][1][12] = 0
4591 00:56:26.813810 rx_lastpass[0][1][12] = 0
4592 00:56:26.817277 rx_firspass[0][1][13] = 0
4593 00:56:26.817342 rx_lastpass[0][1][13] = 0
4594 00:56:26.820712 rx_firspass[0][1][14] = 0
4595 00:56:26.824123 rx_lastpass[0][1][14] = 0
4596 00:56:26.824210 rx_firspass[0][1][15] = 0
4597 00:56:26.827321 rx_lastpass[0][1][15] = 0
4598 00:56:26.831037 rx_firspass[1][0][0] = 0
4599 00:56:26.831112 rx_lastpass[1][0][0] = 0
4600 00:56:26.834401 rx_firspass[1][0][1] = 0
4601 00:56:26.837560 rx_lastpass[1][0][1] = 0
4602 00:56:26.837636 rx_firspass[1][0][2] = 0
4603 00:56:26.840875 rx_lastpass[1][0][2] = 0
4604 00:56:26.844131 rx_firspass[1][0][3] = 0
4605 00:56:26.847274 rx_lastpass[1][0][3] = 0
4606 00:56:26.847350 rx_firspass[1][0][4] = 0
4607 00:56:26.850682 rx_lastpass[1][0][4] = 0
4608 00:56:26.854078 rx_firspass[1][0][5] = 0
4609 00:56:26.854155 rx_lastpass[1][0][5] = 0
4610 00:56:26.857393 rx_firspass[1][0][6] = 0
4611 00:56:26.860959 rx_lastpass[1][0][6] = 0
4612 00:56:26.861035 rx_firspass[1][0][7] = 0
4613 00:56:26.864557 rx_lastpass[1][0][7] = 0
4614 00:56:26.867469 rx_firspass[1][0][8] = 0
4615 00:56:26.867545 rx_lastpass[1][0][8] = 0
4616 00:56:26.871085 rx_firspass[1][0][9] = 0
4617 00:56:26.874187 rx_lastpass[1][0][9] = 0
4618 00:56:26.874269 rx_firspass[1][0][10] = 0
4619 00:56:26.877572 rx_lastpass[1][0][10] = 0
4620 00:56:26.880893 rx_firspass[1][0][11] = 0
4621 00:56:26.884087 rx_lastpass[1][0][11] = 0
4622 00:56:26.884164 rx_firspass[1][0][12] = 0
4623 00:56:26.887814 rx_lastpass[1][0][12] = 0
4624 00:56:26.891008 rx_firspass[1][0][13] = 0
4625 00:56:26.891084 rx_lastpass[1][0][13] = 0
4626 00:56:26.894536 rx_firspass[1][0][14] = 0
4627 00:56:26.897497 rx_lastpass[1][0][14] = 0
4628 00:56:26.900891 rx_firspass[1][0][15] = 0
4629 00:56:26.900967 rx_lastpass[1][0][15] = 0
4630 00:56:26.903905 rx_firspass[1][1][0] = 0
4631 00:56:26.907202 rx_lastpass[1][1][0] = 0
4632 00:56:26.907295 rx_firspass[1][1][1] = 0
4633 00:56:26.911051 rx_lastpass[1][1][1] = 0
4634 00:56:26.914187 rx_firspass[1][1][2] = 0
4635 00:56:26.914304 rx_lastpass[1][1][2] = 0
4636 00:56:26.917344 rx_firspass[1][1][3] = 0
4637 00:56:26.920924 rx_lastpass[1][1][3] = 0
4638 00:56:26.921018 rx_firspass[1][1][4] = 0
4639 00:56:26.924118 rx_lastpass[1][1][4] = 0
4640 00:56:26.927763 rx_firspass[1][1][5] = 0
4641 00:56:26.931304 rx_lastpass[1][1][5] = 0
4642 00:56:26.931382 rx_firspass[1][1][6] = 0
4643 00:56:26.934539 rx_lastpass[1][1][6] = 0
4644 00:56:26.937681 rx_firspass[1][1][7] = 0
4645 00:56:26.937757 rx_lastpass[1][1][7] = 0
4646 00:56:26.940692 rx_firspass[1][1][8] = 0
4647 00:56:26.944041 rx_lastpass[1][1][8] = 0
4648 00:56:26.944129 rx_firspass[1][1][9] = 0
4649 00:56:26.947465 rx_lastpass[1][1][9] = 0
4650 00:56:26.950635 rx_firspass[1][1][10] = 0
4651 00:56:26.950712 rx_lastpass[1][1][10] = 0
4652 00:56:26.954320 rx_firspass[1][1][11] = 0
4653 00:56:26.957348 rx_lastpass[1][1][11] = 0
4654 00:56:26.960825 rx_firspass[1][1][12] = 0
4655 00:56:26.960902 rx_lastpass[1][1][12] = 0
4656 00:56:26.964428 rx_firspass[1][1][13] = 0
4657 00:56:26.967303 rx_lastpass[1][1][13] = 0
4658 00:56:26.967380 rx_firspass[1][1][14] = 0
4659 00:56:26.970659 rx_lastpass[1][1][14] = 0
4660 00:56:26.974281 rx_firspass[1][1][15] = 0
4661 00:56:26.977380 rx_lastpass[1][1][15] = 0
4662 00:56:26.977457 dump params clk_delay
4663 00:56:26.980861 clk_delay[0] = 0
4664 00:56:26.980961 clk_delay[1] = 0
4665 00:56:26.984379 dump params dqs_delay
4666 00:56:26.984469 dqs_delay[0][0] = 0
4667 00:56:26.987500 dqs_delay[0][1] = 0
4668 00:56:26.987588 dqs_delay[1][0] = 0
4669 00:56:26.991063 dqs_delay[1][1] = 0
4670 00:56:26.994768 dump params delay_cell_unit = 753
4671 00:56:26.994845 dump source = 0x0
4672 00:56:26.997867 dump params frequency:800
4673 00:56:27.000988 dump params rank number:2
4674 00:56:27.001065
4675 00:56:27.001124 dump params write leveling
4676 00:56:27.004087 write leveling[0][0][0] = 0x0
4677 00:56:27.007455 write leveling[0][0][1] = 0x0
4678 00:56:27.011094 write leveling[0][1][0] = 0x0
4679 00:56:27.014080 write leveling[0][1][1] = 0x0
4680 00:56:27.014157 write leveling[1][0][0] = 0x0
4681 00:56:27.017424 write leveling[1][0][1] = 0x0
4682 00:56:27.021003 write leveling[1][1][0] = 0x0
4683 00:56:27.024495 write leveling[1][1][1] = 0x0
4684 00:56:27.024572 dump params cbt_cs
4685 00:56:27.027727 cbt_cs[0][0] = 0x0
4686 00:56:27.027813 cbt_cs[0][1] = 0x0
4687 00:56:27.030964 cbt_cs[1][0] = 0x0
4688 00:56:27.031041 cbt_cs[1][1] = 0x0
4689 00:56:27.034529 dump params cbt_mr12
4690 00:56:27.034605 cbt_mr12[0][0] = 0x0
4691 00:56:27.037457 cbt_mr12[0][1] = 0x0
4692 00:56:27.041134 cbt_mr12[1][0] = 0x0
4693 00:56:27.041228 cbt_mr12[1][1] = 0x0
4694 00:56:27.044287 dump params tx window
4695 00:56:27.047515 tx_center_min[0][0][0] = 0
4696 00:56:27.047659 tx_center_max[0][0][0] = 0
4697 00:56:27.051251 tx_center_min[0][0][1] = 0
4698 00:56:27.054341 tx_center_max[0][0][1] = 0
4699 00:56:27.054489 tx_center_min[0][1][0] = 0
4700 00:56:27.057555 tx_center_max[0][1][0] = 0
4701 00:56:27.060959 tx_center_min[0][1][1] = 0
4702 00:56:27.064320 tx_center_max[0][1][1] = 0
4703 00:56:27.064398 tx_center_min[1][0][0] = 0
4704 00:56:27.067626 tx_center_max[1][0][0] = 0
4705 00:56:27.071367 tx_center_min[1][0][1] = 0
4706 00:56:27.074281 tx_center_max[1][0][1] = 0
4707 00:56:27.074365 tx_center_min[1][1][0] = 0
4708 00:56:27.077801 tx_center_max[1][1][0] = 0
4709 00:56:27.081220 tx_center_min[1][1][1] = 0
4710 00:56:27.084448 tx_center_max[1][1][1] = 0
4711 00:56:27.084525 dump params tx window
4712 00:56:27.087441 tx_win_center[0][0][0] = 0
4713 00:56:27.090692 tx_first_pass[0][0][0] = 0
4714 00:56:27.090769 tx_last_pass[0][0][0] = 0
4715 00:56:27.094265 tx_win_center[0][0][1] = 0
4716 00:56:27.097670 tx_first_pass[0][0][1] = 0
4717 00:56:27.100932 tx_last_pass[0][0][1] = 0
4718 00:56:27.101009 tx_win_center[0][0][2] = 0
4719 00:56:27.104511 tx_first_pass[0][0][2] = 0
4720 00:56:27.107964 tx_last_pass[0][0][2] = 0
4721 00:56:27.108041 tx_win_center[0][0][3] = 0
4722 00:56:27.111400 tx_first_pass[0][0][3] = 0
4723 00:56:27.114886 tx_last_pass[0][0][3] = 0
4724 00:56:27.114987 tx_win_center[0][0][4] = 0
4725 00:56:27.118321 tx_first_pass[0][0][4] = 0
4726 00:56:27.121377 tx_last_pass[0][0][4] = 0
4727 00:56:27.124762 tx_win_center[0][0][5] = 0
4728 00:56:27.124838 tx_first_pass[0][0][5] = 0
4729 00:56:27.128410 tx_last_pass[0][0][5] = 0
4730 00:56:27.131281 tx_win_center[0][0][6] = 0
4731 00:56:27.134967 tx_first_pass[0][0][6] = 0
4732 00:56:27.135044 tx_last_pass[0][0][6] = 0
4733 00:56:27.138345 tx_win_center[0][0][7] = 0
4734 00:56:27.141415 tx_first_pass[0][0][7] = 0
4735 00:56:27.141492 tx_last_pass[0][0][7] = 0
4736 00:56:27.145088 tx_win_center[0][0][8] = 0
4737 00:56:27.148399 tx_first_pass[0][0][8] = 0
4738 00:56:27.151524 tx_last_pass[0][0][8] = 0
4739 00:56:27.151601 tx_win_center[0][0][9] = 0
4740 00:56:27.154745 tx_first_pass[0][0][9] = 0
4741 00:56:27.158286 tx_last_pass[0][0][9] = 0
4742 00:56:27.158388 tx_win_center[0][0][10] = 0
4743 00:56:27.161509 tx_first_pass[0][0][10] = 0
4744 00:56:27.164800 tx_last_pass[0][0][10] = 0
4745 00:56:27.168360 tx_win_center[0][0][11] = 0
4746 00:56:27.171452 tx_first_pass[0][0][11] = 0
4747 00:56:27.171522 tx_last_pass[0][0][11] = 0
4748 00:56:27.174927 tx_win_center[0][0][12] = 0
4749 00:56:27.178103 tx_first_pass[0][0][12] = 0
4750 00:56:27.178214 tx_last_pass[0][0][12] = 0
4751 00:56:27.181755 tx_win_center[0][0][13] = 0
4752 00:56:27.184869 tx_first_pass[0][0][13] = 0
4753 00:56:27.188028 tx_last_pass[0][0][13] = 0
4754 00:56:27.188121 tx_win_center[0][0][14] = 0
4755 00:56:27.191645 tx_first_pass[0][0][14] = 0
4756 00:56:27.194902 tx_last_pass[0][0][14] = 0
4757 00:56:27.198442 tx_win_center[0][0][15] = 0
4758 00:56:27.198518 tx_first_pass[0][0][15] = 0
4759 00:56:27.201593 tx_last_pass[0][0][15] = 0
4760 00:56:27.204721 tx_win_center[0][1][0] = 0
4761 00:56:27.208539 tx_first_pass[0][1][0] = 0
4762 00:56:27.208616 tx_last_pass[0][1][0] = 0
4763 00:56:27.211289 tx_win_center[0][1][1] = 0
4764 00:56:27.214702 tx_first_pass[0][1][1] = 0
4765 00:56:27.218320 tx_last_pass[0][1][1] = 0
4766 00:56:27.218397 tx_win_center[0][1][2] = 0
4767 00:56:27.221745 tx_first_pass[0][1][2] = 0
4768 00:56:27.224792 tx_last_pass[0][1][2] = 0
4769 00:56:27.224869 tx_win_center[0][1][3] = 0
4770 00:56:27.228256 tx_first_pass[0][1][3] = 0
4771 00:56:27.231409 tx_last_pass[0][1][3] = 0
4772 00:56:27.235009 tx_win_center[0][1][4] = 0
4773 00:56:27.235087 tx_first_pass[0][1][4] = 0
4774 00:56:27.238376 tx_last_pass[0][1][4] = 0
4775 00:56:27.241670 tx_win_center[0][1][5] = 0
4776 00:56:27.244909 tx_first_pass[0][1][5] = 0
4777 00:56:27.244986 tx_last_pass[0][1][5] = 0
4778 00:56:27.248342 tx_win_center[0][1][6] = 0
4779 00:56:27.252028 tx_first_pass[0][1][6] = 0
4780 00:56:27.252127 tx_last_pass[0][1][6] = 0
4781 00:56:27.254808 tx_win_center[0][1][7] = 0
4782 00:56:27.258377 tx_first_pass[0][1][7] = 0
4783 00:56:27.261691 tx_last_pass[0][1][7] = 0
4784 00:56:27.261759 tx_win_center[0][1][8] = 0
4785 00:56:27.265004 tx_first_pass[0][1][8] = 0
4786 00:56:27.268479 tx_last_pass[0][1][8] = 0
4787 00:56:27.268556 tx_win_center[0][1][9] = 0
4788 00:56:27.271874 tx_first_pass[0][1][9] = 0
4789 00:56:27.274651 tx_last_pass[0][1][9] = 0
4790 00:56:27.278335 tx_win_center[0][1][10] = 0
4791 00:56:27.278412 tx_first_pass[0][1][10] = 0
4792 00:56:27.281594 tx_last_pass[0][1][10] = 0
4793 00:56:27.284969 tx_win_center[0][1][11] = 0
4794 00:56:27.288352 tx_first_pass[0][1][11] = 0
4795 00:56:27.288429 tx_last_pass[0][1][11] = 0
4796 00:56:27.291559 tx_win_center[0][1][12] = 0
4797 00:56:27.295056 tx_first_pass[0][1][12] = 0
4798 00:56:27.298251 tx_last_pass[0][1][12] = 0
4799 00:56:27.298344 tx_win_center[0][1][13] = 0
4800 00:56:27.301595 tx_first_pass[0][1][13] = 0
4801 00:56:27.305232 tx_last_pass[0][1][13] = 0
4802 00:56:27.308494 tx_win_center[0][1][14] = 0
4803 00:56:27.308573 tx_first_pass[0][1][14] = 0
4804 00:56:27.311797 tx_last_pass[0][1][14] = 0
4805 00:56:27.315198 tx_win_center[0][1][15] = 0
4806 00:56:27.318429 tx_first_pass[0][1][15] = 0
4807 00:56:27.318528 tx_last_pass[0][1][15] = 0
4808 00:56:27.321876 tx_win_center[1][0][0] = 0
4809 00:56:27.325432 tx_first_pass[1][0][0] = 0
4810 00:56:27.325508 tx_last_pass[1][0][0] = 0
4811 00:56:27.328511 tx_win_center[1][0][1] = 0
4812 00:56:27.331627 tx_first_pass[1][0][1] = 0
4813 00:56:27.335211 tx_last_pass[1][0][1] = 0
4814 00:56:27.335288 tx_win_center[1][0][2] = 0
4815 00:56:27.338779 tx_first_pass[1][0][2] = 0
4816 00:56:27.342334 tx_last_pass[1][0][2] = 0
4817 00:56:27.345488 tx_win_center[1][0][3] = 0
4818 00:56:27.345565 tx_first_pass[1][0][3] = 0
4819 00:56:27.348413 tx_last_pass[1][0][3] = 0
4820 00:56:27.352264 tx_win_center[1][0][4] = 0
4821 00:56:27.352341 tx_first_pass[1][0][4] = 0
4822 00:56:27.355465 tx_last_pass[1][0][4] = 0
4823 00:56:27.358757 tx_win_center[1][0][5] = 0
4824 00:56:27.362208 tx_first_pass[1][0][5] = 0
4825 00:56:27.362320 tx_last_pass[1][0][5] = 0
4826 00:56:27.365422 tx_win_center[1][0][6] = 0
4827 00:56:27.369067 tx_first_pass[1][0][6] = 0
4828 00:56:27.369144 tx_last_pass[1][0][6] = 0
4829 00:56:27.372322 tx_win_center[1][0][7] = 0
4830 00:56:27.375479 tx_first_pass[1][0][7] = 0
4831 00:56:27.378901 tx_last_pass[1][0][7] = 0
4832 00:56:27.378978 tx_win_center[1][0][8] = 0
4833 00:56:27.382030 tx_first_pass[1][0][8] = 0
4834 00:56:27.385281 tx_last_pass[1][0][8] = 0
4835 00:56:27.388626 tx_win_center[1][0][9] = 0
4836 00:56:27.388702 tx_first_pass[1][0][9] = 0
4837 00:56:27.392202 tx_last_pass[1][0][9] = 0
4838 00:56:27.395333 tx_win_center[1][0][10] = 0
4839 00:56:27.395410 tx_first_pass[1][0][10] = 0
4840 00:56:27.398855 tx_last_pass[1][0][10] = 0
4841 00:56:27.402487 tx_win_center[1][0][11] = 0
4842 00:56:27.405818 tx_first_pass[1][0][11] = 0
4843 00:56:27.405895 tx_last_pass[1][0][11] = 0
4844 00:56:27.409095 tx_win_center[1][0][12] = 0
4845 00:56:27.412470 tx_first_pass[1][0][12] = 0
4846 00:56:27.415889 tx_last_pass[1][0][12] = 0
4847 00:56:27.415966 tx_win_center[1][0][13] = 0
4848 00:56:27.419347 tx_first_pass[1][0][13] = 0
4849 00:56:27.422598 tx_last_pass[1][0][13] = 0
4850 00:56:27.425666 tx_win_center[1][0][14] = 0
4851 00:56:27.425743 tx_first_pass[1][0][14] = 0
4852 00:56:27.428995 tx_last_pass[1][0][14] = 0
4853 00:56:27.432535 tx_win_center[1][0][15] = 0
4854 00:56:27.435691 tx_first_pass[1][0][15] = 0
4855 00:56:27.435768 tx_last_pass[1][0][15] = 0
4856 00:56:27.439381 tx_win_center[1][1][0] = 0
4857 00:56:27.442662 tx_first_pass[1][1][0] = 0
4858 00:56:27.442738 tx_last_pass[1][1][0] = 0
4859 00:56:27.445613 tx_win_center[1][1][1] = 0
4860 00:56:27.449219 tx_first_pass[1][1][1] = 0
4861 00:56:27.452991 tx_last_pass[1][1][1] = 0
4862 00:56:27.453068 tx_win_center[1][1][2] = 0
4863 00:56:27.455946 tx_first_pass[1][1][2] = 0
4864 00:56:27.459244 tx_last_pass[1][1][2] = 0
4865 00:56:27.462548 tx_win_center[1][1][3] = 0
4866 00:56:27.462625 tx_first_pass[1][1][3] = 0
4867 00:56:27.465863 tx_last_pass[1][1][3] = 0
4868 00:56:27.469482 tx_win_center[1][1][4] = 0
4869 00:56:27.469559 tx_first_pass[1][1][4] = 0
4870 00:56:27.472582 tx_last_pass[1][1][4] = 0
4871 00:56:27.475807 tx_win_center[1][1][5] = 0
4872 00:56:27.479660 tx_first_pass[1][1][5] = 0
4873 00:56:27.479737 tx_last_pass[1][1][5] = 0
4874 00:56:27.482505 tx_win_center[1][1][6] = 0
4875 00:56:27.486142 tx_first_pass[1][1][6] = 0
4876 00:56:27.486226 tx_last_pass[1][1][6] = 0
4877 00:56:27.489391 tx_win_center[1][1][7] = 0
4878 00:56:27.492784 tx_first_pass[1][1][7] = 0
4879 00:56:27.496030 tx_last_pass[1][1][7] = 0
4880 00:56:27.496107 tx_win_center[1][1][8] = 0
4881 00:56:27.499280 tx_first_pass[1][1][8] = 0
4882 00:56:27.502671 tx_last_pass[1][1][8] = 0
4883 00:56:27.505903 tx_win_center[1][1][9] = 0
4884 00:56:27.505980 tx_first_pass[1][1][9] = 0
4885 00:56:27.509221 tx_last_pass[1][1][9] = 0
4886 00:56:27.512584 tx_win_center[1][1][10] = 0
4887 00:56:27.516024 tx_first_pass[1][1][10] = 0
4888 00:56:27.516101 tx_last_pass[1][1][10] = 0
4889 00:56:27.519290 tx_win_center[1][1][11] = 0
4890 00:56:27.522765 tx_first_pass[1][1][11] = 0
4891 00:56:27.522842 tx_last_pass[1][1][11] = 0
4892 00:56:27.526096 tx_win_center[1][1][12] = 0
4893 00:56:27.529564 tx_first_pass[1][1][12] = 0
4894 00:56:27.532749 tx_last_pass[1][1][12] = 0
4895 00:56:27.532827 tx_win_center[1][1][13] = 0
4896 00:56:27.536194 tx_first_pass[1][1][13] = 0
4897 00:56:27.539489 tx_last_pass[1][1][13] = 0
4898 00:56:27.542801 tx_win_center[1][1][14] = 0
4899 00:56:27.542878 tx_first_pass[1][1][14] = 0
4900 00:56:27.545950 tx_last_pass[1][1][14] = 0
4901 00:56:27.549616 tx_win_center[1][1][15] = 0
4902 00:56:27.552970 tx_first_pass[1][1][15] = 0
4903 00:56:27.553047 tx_last_pass[1][1][15] = 0
4904 00:56:27.556309 dump params rx window
4905 00:56:27.559625 rx_firspass[0][0][0] = 0
4906 00:56:27.559701 rx_lastpass[0][0][0] = 0
4907 00:56:27.562766 rx_firspass[0][0][1] = 0
4908 00:56:27.566378 rx_lastpass[0][0][1] = 0
4909 00:56:27.566455 rx_firspass[0][0][2] = 0
4910 00:56:27.569640 rx_lastpass[0][0][2] = 0
4911 00:56:27.572815 rx_firspass[0][0][3] = 0
4912 00:56:27.572892 rx_lastpass[0][0][3] = 0
4913 00:56:27.576361 rx_firspass[0][0][4] = 0
4914 00:56:27.579641 rx_lastpass[0][0][4] = 0
4915 00:56:27.582926 rx_firspass[0][0][5] = 0
4916 00:56:27.583002 rx_lastpass[0][0][5] = 0
4917 00:56:27.586447 rx_firspass[0][0][6] = 0
4918 00:56:27.589593 rx_lastpass[0][0][6] = 0
4919 00:56:27.589670 rx_firspass[0][0][7] = 0
4920 00:56:27.593178 rx_lastpass[0][0][7] = 0
4921 00:56:27.596090 rx_firspass[0][0][8] = 0
4922 00:56:27.596167 rx_lastpass[0][0][8] = 0
4923 00:56:27.599609 rx_firspass[0][0][9] = 0
4924 00:56:27.603124 rx_lastpass[0][0][9] = 0
4925 00:56:27.603200 rx_firspass[0][0][10] = 0
4926 00:56:27.606547 rx_lastpass[0][0][10] = 0
4927 00:56:27.610022 rx_firspass[0][0][11] = 0
4928 00:56:27.613166 rx_lastpass[0][0][11] = 0
4929 00:56:27.613243 rx_firspass[0][0][12] = 0
4930 00:56:27.616465 rx_lastpass[0][0][12] = 0
4931 00:56:27.619947 rx_firspass[0][0][13] = 0
4932 00:56:27.620024 rx_lastpass[0][0][13] = 0
4933 00:56:27.623467 rx_firspass[0][0][14] = 0
4934 00:56:27.626647 rx_lastpass[0][0][14] = 0
4935 00:56:27.626724 rx_firspass[0][0][15] = 0
4936 00:56:27.629851 rx_lastpass[0][0][15] = 0
4937 00:56:27.633226 rx_firspass[0][1][0] = 0
4938 00:56:27.636478 rx_lastpass[0][1][0] = 0
4939 00:56:27.636554 rx_firspass[0][1][1] = 0
4940 00:56:27.640178 rx_lastpass[0][1][1] = 0
4941 00:56:27.642979 rx_firspass[0][1][2] = 0
4942 00:56:27.643055 rx_lastpass[0][1][2] = 0
4943 00:56:27.646670 rx_firspass[0][1][3] = 0
4944 00:56:27.649693 rx_lastpass[0][1][3] = 0
4945 00:56:27.649791 rx_firspass[0][1][4] = 0
4946 00:56:27.653143 rx_lastpass[0][1][4] = 0
4947 00:56:27.656516 rx_firspass[0][1][5] = 0
4948 00:56:27.656593 rx_lastpass[0][1][5] = 0
4949 00:56:27.660018 rx_firspass[0][1][6] = 0
4950 00:56:27.663419 rx_lastpass[0][1][6] = 0
4951 00:56:27.663496 rx_firspass[0][1][7] = 0
4952 00:56:27.666689 rx_lastpass[0][1][7] = 0
4953 00:56:27.669610 rx_firspass[0][1][8] = 0
4954 00:56:27.669687 rx_lastpass[0][1][8] = 0
4955 00:56:27.673312 rx_firspass[0][1][9] = 0
4956 00:56:27.676425 rx_lastpass[0][1][9] = 0
4957 00:56:27.679894 rx_firspass[0][1][10] = 0
4958 00:56:27.679970 rx_lastpass[0][1][10] = 0
4959 00:56:27.683394 rx_firspass[0][1][11] = 0
4960 00:56:27.686570 rx_lastpass[0][1][11] = 0
4961 00:56:27.686647 rx_firspass[0][1][12] = 0
4962 00:56:27.690151 rx_lastpass[0][1][12] = 0
4963 00:56:27.693177 rx_firspass[0][1][13] = 0
4964 00:56:27.693269 rx_lastpass[0][1][13] = 0
4965 00:56:27.696799 rx_firspass[0][1][14] = 0
4966 00:56:27.700226 rx_lastpass[0][1][14] = 0
4967 00:56:27.703699 rx_firspass[0][1][15] = 0
4968 00:56:27.703776 rx_lastpass[0][1][15] = 0
4969 00:56:27.706887 rx_firspass[1][0][0] = 0
4970 00:56:27.710253 rx_lastpass[1][0][0] = 0
4971 00:56:27.710344 rx_firspass[1][0][1] = 0
4972 00:56:27.713723 rx_lastpass[1][0][1] = 0
4973 00:56:27.717036 rx_firspass[1][0][2] = 0
4974 00:56:27.717136 rx_lastpass[1][0][2] = 0
4975 00:56:27.720049 rx_firspass[1][0][3] = 0
4976 00:56:27.723343 rx_lastpass[1][0][3] = 0
4977 00:56:27.723419 rx_firspass[1][0][4] = 0
4978 00:56:27.727078 rx_lastpass[1][0][4] = 0
4979 00:56:27.730194 rx_firspass[1][0][5] = 0
4980 00:56:27.733264 rx_lastpass[1][0][5] = 0
4981 00:56:27.733340 rx_firspass[1][0][6] = 0
4982 00:56:27.736619 rx_lastpass[1][0][6] = 0
4983 00:56:27.739974 rx_firspass[1][0][7] = 0
4984 00:56:27.740051 rx_lastpass[1][0][7] = 0
4985 00:56:27.743446 rx_firspass[1][0][8] = 0
4986 00:56:27.746541 rx_lastpass[1][0][8] = 0
4987 00:56:27.746617 rx_firspass[1][0][9] = 0
4988 00:56:27.750409 rx_lastpass[1][0][9] = 0
4989 00:56:27.753409 rx_firspass[1][0][10] = 0
4990 00:56:27.753485 rx_lastpass[1][0][10] = 0
4991 00:56:27.756511 rx_firspass[1][0][11] = 0
4992 00:56:27.760248 rx_lastpass[1][0][11] = 0
4993 00:56:27.763401 rx_firspass[1][0][12] = 0
4994 00:56:27.763478 rx_lastpass[1][0][12] = 0
4995 00:56:27.766670 rx_firspass[1][0][13] = 0
4996 00:56:27.770073 rx_lastpass[1][0][13] = 0
4997 00:56:27.770177 rx_firspass[1][0][14] = 0
4998 00:56:27.773508 rx_lastpass[1][0][14] = 0
4999 00:56:27.776839 rx_firspass[1][0][15] = 0
5000 00:56:27.780231 rx_lastpass[1][0][15] = 0
5001 00:56:27.780308 rx_firspass[1][1][0] = 0
5002 00:56:27.783428 rx_lastpass[1][1][0] = 0
5003 00:56:27.786934 rx_firspass[1][1][1] = 0
5004 00:56:27.787010 rx_lastpass[1][1][1] = 0
5005 00:56:27.790276 rx_firspass[1][1][2] = 0
5006 00:56:27.793680 rx_lastpass[1][1][2] = 0
5007 00:56:27.793758 rx_firspass[1][1][3] = 0
5008 00:56:27.796920 rx_lastpass[1][1][3] = 0
5009 00:56:27.800417 rx_firspass[1][1][4] = 0
5010 00:56:27.800496 rx_lastpass[1][1][4] = 0
5011 00:56:27.803584 rx_firspass[1][1][5] = 0
5012 00:56:27.806910 rx_lastpass[1][1][5] = 0
5013 00:56:27.806987 rx_firspass[1][1][6] = 0
5014 00:56:27.810274 rx_lastpass[1][1][6] = 0
5015 00:56:27.813563 rx_firspass[1][1][7] = 0
5016 00:56:27.813641 rx_lastpass[1][1][7] = 0
5017 00:56:27.816963 rx_firspass[1][1][8] = 0
5018 00:56:27.820243 rx_lastpass[1][1][8] = 0
5019 00:56:27.823655 rx_firspass[1][1][9] = 0
5020 00:56:27.823751 rx_lastpass[1][1][9] = 0
5021 00:56:27.826936 rx_firspass[1][1][10] = 0
5022 00:56:27.830528 rx_lastpass[1][1][10] = 0
5023 00:56:27.830629 rx_firspass[1][1][11] = 0
5024 00:56:27.833496 rx_lastpass[1][1][11] = 0
5025 00:56:27.836809 rx_firspass[1][1][12] = 0
5026 00:56:27.836885 rx_lastpass[1][1][12] = 0
5027 00:56:27.840339 rx_firspass[1][1][13] = 0
5028 00:56:27.843563 rx_lastpass[1][1][13] = 0
5029 00:56:27.846957 rx_firspass[1][1][14] = 0
5030 00:56:27.847034 rx_lastpass[1][1][14] = 0
5031 00:56:27.850691 rx_firspass[1][1][15] = 0
5032 00:56:27.853819 rx_lastpass[1][1][15] = 0
5033 00:56:27.853895 dump params clk_delay
5034 00:56:27.857139 clk_delay[0] = 0
5035 00:56:27.857217 clk_delay[1] = 0
5036 00:56:27.860412 dump params dqs_delay
5037 00:56:27.860489 dqs_delay[0][0] = 0
5038 00:56:27.864099 dqs_delay[0][1] = 0
5039 00:56:27.864176 dqs_delay[1][0] = 0
5040 00:56:27.867385 dqs_delay[1][1] = 0
5041 00:56:27.870705 dump params delay_cell_unit = 753
5042 00:56:27.874167 mt_set_emi_preloader end
5043 00:56:27.877011 [mt_mem_init] dram size: 0x100000000, rank number: 2
5044 00:56:27.880371 [complex_mem_test] start addr:0x40000000, len:20480
5045 00:56:27.918320 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5046 00:56:27.924660 [complex_mem_test] start addr:0x80000000, len:20480
5047 00:56:27.960674 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5048 00:56:27.967131 [complex_mem_test] start addr:0xc0000000, len:20480
5049 00:56:28.003234 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5050 00:56:28.009581 [complex_mem_test] start addr:0x56000000, len:8192
5051 00:56:28.025974 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5052 00:56:28.026052 ddr_geometry:1
5053 00:56:28.032608 [complex_mem_test] start addr:0x80000000, len:8192
5054 00:56:28.049625 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5055 00:56:28.052917 dram_init: dram init end (result: 0)
5056 00:56:28.059695 Successfully loaded DRAM blobs and ran DRAM calibration
5057 00:56:28.069634 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5058 00:56:28.069713 CBMEM:
5059 00:56:28.072953 IMD: root @ 00000000fffff000 254 entries.
5060 00:56:28.076063 IMD: root @ 00000000ffffec00 62 entries.
5061 00:56:28.082873 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5062 00:56:28.089900 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5063 00:56:28.093099 in-header: 03 a1 00 00 08 00 00 00
5064 00:56:28.096398 in-data: 84 60 60 10 00 00 00 00
5065 00:56:28.099453 Chrome EC: clear events_b mask to 0x0000000020004000
5066 00:56:28.106680 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5067 00:56:28.109962 in-header: 03 fd 00 00 00 00 00 00
5068 00:56:28.110056 in-data:
5069 00:56:28.116605 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5070 00:56:28.116699 CBFS @ 21000 size 3d4000
5071 00:56:28.123530 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5072 00:56:28.126583 CBFS: Locating 'fallback/ramstage'
5073 00:56:28.130080 CBFS: Found @ offset 10d40 size d563
5074 00:56:28.151826 read SPI 0x31d94 0xd547: 16641 us, 3280 KB/s, 26.240 Mbps
5075 00:56:28.164019 Accumulated console time in romstage 12950 ms
5076 00:56:28.164114
5077 00:56:28.164210
5078 00:56:28.173812 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5079 00:56:28.176969 ARM64: Exception handlers installed.
5080 00:56:28.177035 ARM64: Testing exception
5081 00:56:28.180368 ARM64: Done test exception
5082 00:56:28.183766 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5083 00:56:28.187272 Manufacturer: ef
5084 00:56:28.191057 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5085 00:56:28.196980 WARNING: RO_VPD is uninitialized or empty.
5086 00:56:28.200743 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5087 00:56:28.203938 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5088 00:56:28.213263 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5089 00:56:28.216585 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5090 00:56:28.223621 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5091 00:56:28.223718 Enumerating buses...
5092 00:56:28.230542 Show all devs... Before device enumeration.
5093 00:56:28.230641 Root Device: enabled 1
5094 00:56:28.233772 CPU_CLUSTER: 0: enabled 1
5095 00:56:28.233861 CPU: 00: enabled 1
5096 00:56:28.236783 Compare with tree...
5097 00:56:28.240355 Root Device: enabled 1
5098 00:56:28.240446 CPU_CLUSTER: 0: enabled 1
5099 00:56:28.243880 CPU: 00: enabled 1
5100 00:56:28.243948 Root Device scanning...
5101 00:56:28.247125 root_dev_scan_bus for Root Device
5102 00:56:28.250462 CPU_CLUSTER: 0 enabled
5103 00:56:28.253969 root_dev_scan_bus for Root Device done
5104 00:56:28.257413 scan_bus: scanning of bus Root Device took 10690 usecs
5105 00:56:28.260372 done
5106 00:56:28.263582 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5107 00:56:28.267025 Allocating resources...
5108 00:56:28.267119 Reading resources...
5109 00:56:28.270500 Root Device read_resources bus 0 link: 0
5110 00:56:28.273848 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5111 00:56:28.276934 CPU: 00 missing read_resources
5112 00:56:28.283700 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5113 00:56:28.287005 Root Device read_resources bus 0 link: 0 done
5114 00:56:28.287095 Done reading resources.
5115 00:56:28.293586 Show resources in subtree (Root Device)...After reading.
5116 00:56:28.297197 Root Device child on link 0 CPU_CLUSTER: 0
5117 00:56:28.300250 CPU_CLUSTER: 0 child on link 0 CPU: 00
5118 00:56:28.310432 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5119 00:56:28.310540 CPU: 00
5120 00:56:28.313963 Setting resources...
5121 00:56:28.317111 Root Device assign_resources, bus 0 link: 0
5122 00:56:28.320540 CPU_CLUSTER: 0 missing set_resources
5123 00:56:28.323708 Root Device assign_resources, bus 0 link: 0
5124 00:56:28.327275 Done setting resources.
5125 00:56:28.330364 Show resources in subtree (Root Device)...After assigning values.
5126 00:56:28.337401 Root Device child on link 0 CPU_CLUSTER: 0
5127 00:56:28.340432 CPU_CLUSTER: 0 child on link 0 CPU: 00
5128 00:56:28.347169 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5129 00:56:28.350257 CPU: 00
5130 00:56:28.350334 Done allocating resources.
5131 00:56:28.357336 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5132 00:56:28.357413 Enabling resources...
5133 00:56:28.360746 done.
5134 00:56:28.364042 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5135 00:56:28.364126 Initializing devices...
5136 00:56:28.367451 Root Device init ...
5137 00:56:28.370844 mainboard_init: Starting display init.
5138 00:56:28.373767 ADC[4]: Raw value=77032 ID=0
5139 00:56:28.396249 anx7625_power_on_init: Init interface.
5140 00:56:28.399412 anx7625_disable_pd_protocol: Disabled PD feature.
5141 00:56:28.406070 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5142 00:56:28.463819 anx7625_start_dp_work: Secure OCM version=00
5143 00:56:28.466526 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5144 00:56:28.483530 sp_tx_get_edid_block: EDID Block = 1
5145 00:56:28.600657 Extracted contents:
5146 00:56:28.604051 header: 00 ff ff ff ff ff ff 00
5147 00:56:28.607526 serial number: 06 af 5c 14 00 00 00 00 00 1a
5148 00:56:28.610978 version: 01 04
5149 00:56:28.614208 basic params: 95 1a 0e 78 02
5150 00:56:28.617909 chroma info: 99 85 95 55 56 92 28 22 50 54
5151 00:56:28.621318 established: 00 00 00
5152 00:56:28.624165 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5153 00:56:28.630718 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5154 00:56:28.637460 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5155 00:56:28.644240 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5156 00:56:28.651051 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5157 00:56:28.651154 extensions: 00
5158 00:56:28.654340 checksum: ae
5159 00:56:28.654430
5160 00:56:28.658107 Manufacturer: AUO Model 145c Serial Number 0
5161 00:56:28.661076 Made week 0 of 2016
5162 00:56:28.661152 EDID version: 1.4
5163 00:56:28.664315 Digital display
5164 00:56:28.667717 6 bits per primary color channel
5165 00:56:28.667795 DisplayPort interface
5166 00:56:28.671367 Maximum image size: 26 cm x 14 cm
5167 00:56:28.671457 Gamma: 220%
5168 00:56:28.674990 Check DPMS levels
5169 00:56:28.677642 Supported color formats: RGB 4:4:4
5170 00:56:28.680953 First detailed timing is preferred timing
5171 00:56:28.684762 Established timings supported:
5172 00:56:28.687666 Standard timings supported:
5173 00:56:28.687743 Detailed timings
5174 00:56:28.690857 Hex of detail: ce1d56ea50001a3030204600009010000018
5175 00:56:28.697874 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5176 00:56:28.701368 0556 0586 05a6 0640 hborder 0
5177 00:56:28.704826 0300 0304 030a 031a vborder 0
5178 00:56:28.707657 -hsync -vsync
5179 00:56:28.711173 Did detailed timing
5180 00:56:28.715009 Hex of detail: 0000000f0000000000000000000000000020
5181 00:56:28.718255 Manufacturer-specified data, tag 15
5182 00:56:28.721310 Hex of detail: 000000fe0041554f0a202020202020202020
5183 00:56:28.725131 ASCII string: AUO
5184 00:56:28.728085 Hex of detail: 000000fe004231313658414230312e34200a
5185 00:56:28.731161 ASCII string: B116XAB01.4
5186 00:56:28.731227 Checksum
5187 00:56:28.734811 Checksum: 0xae (valid)
5188 00:56:28.737785 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5189 00:56:28.741474 DSI data_rate: 457800000 bps
5190 00:56:28.748197 anx7625_parse_edid: set default k value to 0x3d for panel
5191 00:56:28.751283 anx7625_parse_edid: pixelclock(76300).
5192 00:56:28.754718 hactive(1366), hsync(32), hfp(48), hbp(154)
5193 00:56:28.757859 vactive(768), vsync(6), vfp(4), vbp(16)
5194 00:56:28.761559 anx7625_dsi_config: config dsi.
5195 00:56:28.769252 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5196 00:56:28.790289 anx7625_dsi_config: success to config DSI
5197 00:56:28.793446 anx7625_dp_start: MIPI phy setup OK.
5198 00:56:28.797023 [SSUSB] Setting up USB HOST controller...
5199 00:56:28.800008 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5200 00:56:28.803516 [SSUSB] phy power-on done.
5201 00:56:28.807358 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5202 00:56:28.810511 in-header: 03 fc 01 00 00 00 00 00
5203 00:56:28.810590 in-data:
5204 00:56:28.814090 handle_proto3_response: EC response with error code: 1
5205 00:56:28.817476 SPM: pcm index = 1
5206 00:56:28.820497 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5207 00:56:28.823723 CBFS @ 21000 size 3d4000
5208 00:56:28.830456 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5209 00:56:28.833840 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5210 00:56:28.837422 CBFS: Found @ offset 1e7c0 size 1026
5211 00:56:28.843873 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5212 00:56:28.847585 SPM: binary array size = 2988
5213 00:56:28.850391 SPM: version = pcm_allinone_v1.17.2_20180829
5214 00:56:28.853630 SPM binary loaded in 32 msecs
5215 00:56:28.861233 spm_kick_im_to_fetch: ptr = 000000004021eec2
5216 00:56:28.864588 spm_kick_im_to_fetch: len = 2988
5217 00:56:28.864665 SPM: spm_kick_pcm_to_run
5218 00:56:28.868106 SPM: spm_kick_pcm_to_run done
5219 00:56:28.871336 SPM: spm_init done in 52 msecs
5220 00:56:28.874317 Root Device init finished in 505264 usecs
5221 00:56:28.877628 CPU_CLUSTER: 0 init ...
5222 00:56:28.887807 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5223 00:56:28.891083 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5224 00:56:28.894612 CBFS @ 21000 size 3d4000
5225 00:56:28.897943 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5226 00:56:28.900941 CBFS: Locating 'sspm.bin'
5227 00:56:28.904650 CBFS: Found @ offset 208c0 size 41cb
5228 00:56:28.914696 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5229 00:56:28.922351 CPU_CLUSTER: 0 init finished in 42802 usecs
5230 00:56:28.922430 Devices initialized
5231 00:56:28.926044 Show all devs... After init.
5232 00:56:28.929294 Root Device: enabled 1
5233 00:56:28.929371 CPU_CLUSTER: 0: enabled 1
5234 00:56:28.932884 CPU: 00: enabled 1
5235 00:56:28.935943 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5236 00:56:28.939409 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5237 00:56:28.942434 ELOG: NV offset 0x558000 size 0x1000
5238 00:56:28.949854 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5239 00:56:28.956709 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5240 00:56:28.959716 ELOG: Event(17) added with size 13 at 2024-06-16 00:56:28 UTC
5241 00:56:28.963425 out: cmd=0x121: 03 db 21 01 00 00 00 00
5242 00:56:28.966764 in-header: 03 b9 00 00 2c 00 00 00
5243 00:56:28.979936 in-data: 18 4a 00 00 00 00 00 00 02 10 00 00 06 80 00 00 43 37 01 00 06 80 00 00 f5 f2 01 00 06 80 00 00 fd 13 01 00 06 80 00 00 27 eb 06 00
5244 00:56:28.983444 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5245 00:56:28.986432 in-header: 03 19 00 00 08 00 00 00
5246 00:56:28.990181 in-data: a2 e0 47 00 13 00 00 00
5247 00:56:28.993623 Chrome EC: UHEPI supported
5248 00:56:29.000117 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5249 00:56:29.003676 in-header: 03 e1 00 00 08 00 00 00
5250 00:56:29.006746 in-data: 84 20 60 10 00 00 00 00
5251 00:56:29.010432 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5252 00:56:29.017002 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5253 00:56:29.020627 in-header: 03 e1 00 00 08 00 00 00
5254 00:56:29.023696 in-data: 84 20 60 10 00 00 00 00
5255 00:56:29.030265 ELOG: Event(A1) added with size 10 at 2024-06-16 00:56:28 UTC
5256 00:56:29.036866 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5257 00:56:29.040327 ELOG: Event(A0) added with size 9 at 2024-06-16 00:56:28 UTC
5258 00:56:29.043573 elog_add_boot_reason: Logged dev mode boot
5259 00:56:29.046937 Finalize devices...
5260 00:56:29.047014 Devices finalized
5261 00:56:29.053783 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5262 00:56:29.056830 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5263 00:56:29.063838 ELOG: Event(91) added with size 10 at 2024-06-16 00:56:28 UTC
5264 00:56:29.067080 Writing coreboot table at 0xffeda000
5265 00:56:29.070612 0. 0000000000114000-000000000011efff: RAMSTAGE
5266 00:56:29.073619 1. 0000000040000000-000000004023cfff: RAMSTAGE
5267 00:56:29.080275 2. 000000004023d000-00000000545fffff: RAM
5268 00:56:29.084096 3. 0000000054600000-000000005465ffff: BL31
5269 00:56:29.087319 4. 0000000054660000-00000000ffed9fff: RAM
5270 00:56:29.090657 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5271 00:56:29.097186 6. 0000000100000000-000000013fffffff: RAM
5272 00:56:29.097263 Passing 5 GPIOs to payload:
5273 00:56:29.103739 NAME | PORT | POLARITY | VALUE
5274 00:56:29.107179 write protect | 0x00000096 | low | high
5275 00:56:29.110491 EC in RW | 0x000000b1 | high | undefined
5276 00:56:29.117004 EC interrupt | 0x00000097 | low | undefined
5277 00:56:29.120606 TPM interrupt | 0x00000099 | high | undefined
5278 00:56:29.127317 speaker enable | 0x000000af | high | undefined
5279 00:56:29.130348 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5280 00:56:29.133677 in-header: 03 f7 00 00 02 00 00 00
5281 00:56:29.133755 in-data: 04 00
5282 00:56:29.133815 Board ID: 4
5283 00:56:29.137278 ADC[3]: Raw value=1040656 ID=8
5284 00:56:29.140450 RAM code: 8
5285 00:56:29.140527 SKU ID: 16
5286 00:56:29.143968 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5287 00:56:29.147348 CBFS @ 21000 size 3d4000
5288 00:56:29.154030 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5289 00:56:29.156931 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 5a2
5290 00:56:29.160258 coreboot table: 940 bytes.
5291 00:56:29.163735 IMD ROOT 0. 00000000fffff000 00001000
5292 00:56:29.166941 IMD SMALL 1. 00000000ffffe000 00001000
5293 00:56:29.170426 CONSOLE 2. 00000000fffde000 00020000
5294 00:56:29.174079 FMAP 3. 00000000fffdd000 0000047c
5295 00:56:29.177133 TIME STAMP 4. 00000000fffdc000 00000910
5296 00:56:29.183754 RAMOOPS 5. 00000000ffedc000 00100000
5297 00:56:29.187056 COREBOOT 6. 00000000ffeda000 00002000
5298 00:56:29.187133 IMD small region:
5299 00:56:29.190423 IMD ROOT 0. 00000000ffffec00 00000400
5300 00:56:29.194516 VBOOT WORK 1. 00000000ffffeb00 00000100
5301 00:56:29.200775 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5302 00:56:29.204051 VPD 3. 00000000ffffea60 0000006c
5303 00:56:29.207402 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5304 00:56:29.214468 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5305 00:56:29.217259 in-header: 03 e1 00 00 08 00 00 00
5306 00:56:29.220832 in-data: 84 20 60 10 00 00 00 00
5307 00:56:29.223881 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5308 00:56:29.227455 CBFS @ 21000 size 3d4000
5309 00:56:29.234094 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5310 00:56:29.237049 CBFS: Locating 'fallback/payload'
5311 00:56:29.243805 CBFS: Found @ offset dc040 size 439a0
5312 00:56:29.331845 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5313 00:56:29.335187 Checking segment from ROM address 0x0000000040003a00
5314 00:56:29.342003 Checking segment from ROM address 0x0000000040003a1c
5315 00:56:29.345256 Loading segment from ROM address 0x0000000040003a00
5316 00:56:29.348724 code (compression=0)
5317 00:56:29.355333 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5318 00:56:29.365354 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5319 00:56:29.365433 it's not compressed!
5320 00:56:29.371903 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5321 00:56:29.378506 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5322 00:56:29.386387 Loading segment from ROM address 0x0000000040003a1c
5323 00:56:29.389767 Entry Point 0x0000000080000000
5324 00:56:29.389844 Loaded segments
5325 00:56:29.396026 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5326 00:56:29.399573 Jumping to boot code at 0000000080000000(00000000ffeda000)
5327 00:56:29.409656 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5328 00:56:29.412839 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5329 00:56:29.416103 CBFS @ 21000 size 3d4000
5330 00:56:29.423054 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5331 00:56:29.426113 CBFS: Locating 'fallback/bl31'
5332 00:56:29.429235 CBFS: Found @ offset 36dc0 size 5820
5333 00:56:29.439876 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5334 00:56:29.443432 Checking segment from ROM address 0x0000000040003a00
5335 00:56:29.450097 Checking segment from ROM address 0x0000000040003a1c
5336 00:56:29.453689 Loading segment from ROM address 0x0000000040003a00
5337 00:56:29.456476 code (compression=1)
5338 00:56:29.463220 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5339 00:56:29.473409 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5340 00:56:29.473521 using LZMA
5341 00:56:29.481832 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5342 00:56:29.488592 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5343 00:56:29.491944 Loading segment from ROM address 0x0000000040003a1c
5344 00:56:29.495573 Entry Point 0x0000000054601000
5345 00:56:29.495651 Loaded segments
5346 00:56:29.498369 NOTICE: MT8183 bl31_setup
5347 00:56:29.505638 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5348 00:56:29.509227 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5349 00:56:29.512321 INFO: [DEVAPC] dump DEVAPC registers:
5350 00:56:29.522151 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5351 00:56:29.529413 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5352 00:56:29.539094 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5353 00:56:29.545746 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5354 00:56:29.555410 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5355 00:56:29.561992 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5356 00:56:29.568967 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5357 00:56:29.579155 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5358 00:56:29.585836 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5359 00:56:29.595790 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5360 00:56:29.602244 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5361 00:56:29.612547 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5362 00:56:29.619085 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5363 00:56:29.625685 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5364 00:56:29.635538 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5365 00:56:29.642659 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5366 00:56:29.649022 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5367 00:56:29.655776 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5368 00:56:29.662402 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5369 00:56:29.672608 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5370 00:56:29.679548 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5371 00:56:29.685932 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5372 00:56:29.689327 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5373 00:56:29.692575 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5374 00:56:29.696086 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5375 00:56:29.699457 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5376 00:56:29.702454 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5377 00:56:29.709264 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5378 00:56:29.712492 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5379 00:56:29.715870 WARNING: region 0:
5380 00:56:29.719372 WARNING: apc:0x168, sa:0x0, ea:0xfff
5381 00:56:29.719448 WARNING: region 1:
5382 00:56:29.722589 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5383 00:56:29.725990 WARNING: region 2:
5384 00:56:29.729750 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5385 00:56:29.729828 WARNING: region 3:
5386 00:56:29.736273 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5387 00:56:29.736349 WARNING: region 4:
5388 00:56:29.739595 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5389 00:56:29.742726 WARNING: region 5:
5390 00:56:29.746320 WARNING: apc:0x0, sa:0x0, ea:0x0
5391 00:56:29.746397 WARNING: region 6:
5392 00:56:29.749404 WARNING: apc:0x0, sa:0x0, ea:0x0
5393 00:56:29.752704 WARNING: region 7:
5394 00:56:29.756253 WARNING: apc:0x0, sa:0x0, ea:0x0
5395 00:56:29.762600 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5396 00:56:29.766467 INFO: SPM: enable SPMC mode
5397 00:56:29.766543 NOTICE: spm_boot_init() start
5398 00:56:29.769074 NOTICE: spm_boot_init() end
5399 00:56:29.772587 INFO: BL31: Initializing runtime services
5400 00:56:29.779351 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5401 00:56:29.783027 INFO: BL31: Preparing for EL3 exit to normal world
5402 00:56:29.789273 INFO: Entry point address = 0x80000000
5403 00:56:29.789350 INFO: SPSR = 0x8
5404 00:56:29.811811
5405 00:56:29.811889
5406 00:56:29.811948
5407 00:56:29.812354 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
5408 00:56:29.812454 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
5409 00:56:29.812534 Setting prompt string to ['jacuzzi:']
5410 00:56:29.812608 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:27)
5411 00:56:29.815368 Starting depthcharge on Juniper...
5412 00:56:29.815444
5413 00:56:29.818476 vboot_handoff: creating legacy vboot_handoff structure
5414 00:56:29.818556
5415 00:56:29.821912 ec_init(0): CrosEC protocol v3 supported (544, 544)
5416 00:56:29.821988
5417 00:56:29.825826 Wipe memory regions:
5418 00:56:29.825902
5419 00:56:29.828786 [0x00000040000000, 0x00000054600000)
5420 00:56:29.871155
5421 00:56:29.871233 [0x00000054660000, 0x00000080000000)
5422 00:56:29.962613
5423 00:56:29.962702 [0x000000811994a0, 0x000000ffeda000)
5424 00:56:30.223091
5425 00:56:30.223212 [0x00000100000000, 0x00000140000000)
5426 00:56:30.355624
5427 00:56:30.358608 Initializing XHCI USB controller at 0x11200000.
5428 00:56:30.381461
5429 00:56:30.384973 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5430 00:56:30.385051
5431 00:56:30.385113
5432 00:56:30.385383 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5434 00:56:30.485688 jacuzzi: tftpboot 192.168.201.1 14368556/tftp-deploy-bd1jyqqo/kernel/image.itb 14368556/tftp-deploy-bd1jyqqo/kernel/cmdline
5435 00:56:30.485884 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5436 00:56:30.485976 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:27)
5437 00:56:30.489882 tftpboot 192.168.201.1 14368556/tftp-deploy-bd1jyqqo/kernel/image.ittp-deploy-bd1jyqqo/kernel/cmdline
5438 00:56:30.489961
5439 00:56:30.490021 Waiting for link
5440 00:56:31.041490
5441 00:56:31.041608 R8152: Initializing
5442 00:56:31.041668
5443 00:56:31.044961 Version 9 (ocp_data = 6010)
5444 00:56:31.045037
5445 00:56:31.048172 R8152: Done initializing
5446 00:56:31.048249
5447 00:56:31.048309 Adding net device
5448 00:56:31.226898
5449 00:56:31.227008 R8152: Initializing
5450 00:56:31.227069
5451 00:56:31.230547 Version 9 (ocp_data = 6010)
5452 00:56:31.230623
5453 00:56:31.233810 R8152: Done initializing
5454 00:56:31.233886
5455 00:56:31.237269 net_add_device: Attemp to include the same device
5456 00:56:31.623615
5457 00:56:31.624126 done.
5458 00:56:31.624730
5459 00:56:31.625362 MAC: 00:e0:4c:68:03:2b
5460 00:56:31.625829
5461 00:56:31.628666 Sending DHCP discover... done.
5462 00:56:31.629103
5463 00:56:31.631010 Waiting for reply... done.
5464 00:56:31.631462
5465 00:56:31.633658 Sending DHCP request... done.
5466 00:56:31.634094
5467 00:56:31.634476 Waiting for reply... done.
5468 00:56:31.636655
5469 00:56:31.637090 My ip is 192.168.201.17
5470 00:56:31.637509
5471 00:56:31.640273 The DHCP server ip is 192.168.201.1
5472 00:56:31.640783
5473 00:56:31.643156 TFTP server IP predefined by user: 192.168.201.1
5474 00:56:31.643608
5475 00:56:31.650290 Bootfile predefined by user: 14368556/tftp-deploy-bd1jyqqo/kernel/image.itb
5476 00:56:31.650808
5477 00:56:31.653524 Sending tftp read request... done.
5478 00:56:31.654069
5479 00:56:31.660476 Waiting for the transfer...
5480 00:56:31.660918
5481 00:56:32.030715 00000000 ################################################################
5482 00:56:32.030841
5483 00:56:32.285183 00080000 ################################################################
5484 00:56:32.285302
5485 00:56:32.580803 00100000 ################################################################
5486 00:56:32.580925
5487 00:56:32.840568 00180000 ################################################################
5488 00:56:32.840692
5489 00:56:33.093549 00200000 ################################################################
5490 00:56:33.093679
5491 00:56:33.347101 00280000 ################################################################
5492 00:56:33.347216
5493 00:56:33.601871 00300000 ################################################################
5494 00:56:33.601981
5495 00:56:33.856332 00380000 ################################################################
5496 00:56:33.856443
5497 00:56:34.119422 00400000 ################################################################
5498 00:56:34.119561
5499 00:56:34.379906 00480000 ################################################################
5500 00:56:34.380082
5501 00:56:34.633877 00500000 ################################################################
5502 00:56:34.634017
5503 00:56:34.899242 00580000 ################################################################
5504 00:56:34.899356
5505 00:56:35.154264 00600000 ################################################################
5506 00:56:35.154375
5507 00:56:35.411478 00680000 ################################################################
5508 00:56:35.411596
5509 00:56:35.686423 00700000 ################################################################
5510 00:56:35.686539
5511 00:56:35.953718 00780000 ################################################################
5512 00:56:35.953830
5513 00:56:36.216875 00800000 ################################################################
5514 00:56:36.216986
5515 00:56:36.471711 00880000 ################################################################
5516 00:56:36.471826
5517 00:56:36.737177 00900000 ################################################################
5518 00:56:36.737298
5519 00:56:36.992687 00980000 ################################################################
5520 00:56:36.992806
5521 00:56:37.249995 00a00000 ################################################################
5522 00:56:37.250111
5523 00:56:37.504791 00a80000 ################################################################
5524 00:56:37.504912
5525 00:56:37.759380 00b00000 ################################################################
5526 00:56:37.759503
5527 00:56:38.013552 00b80000 ################################################################
5528 00:56:38.013674
5529 00:56:38.269276 00c00000 ################################################################
5530 00:56:38.269394
5531 00:56:38.523281 00c80000 ################################################################
5532 00:56:38.523393
5533 00:56:38.775522 00d00000 ################################################################
5534 00:56:38.775633
5535 00:56:39.029270 00d80000 ################################################################
5536 00:56:39.029383
5537 00:56:39.281456 00e00000 ################################################################
5538 00:56:39.281567
5539 00:56:39.536738 00e80000 ################################################################
5540 00:56:39.536852
5541 00:56:39.794096 00f00000 ################################################################
5542 00:56:39.794270
5543 00:56:40.057148 00f80000 ################################################################
5544 00:56:40.057267
5545 00:56:40.307318 01000000 ################################################################
5546 00:56:40.307431
5547 00:56:40.572485 01080000 ################################################################
5548 00:56:40.572624
5549 00:56:40.827412 01100000 ################################################################
5550 00:56:40.827520
5551 00:56:41.077787 01180000 ################################################################
5552 00:56:41.077901
5553 00:56:41.328449 01200000 ################################################################
5554 00:56:41.328592
5555 00:56:41.583428 01280000 ################################################################
5556 00:56:41.583565
5557 00:56:41.844819 01300000 ################################################################
5558 00:56:41.844960
5559 00:56:42.106739 01380000 ################################################################
5560 00:56:42.106858
5561 00:56:42.371631 01400000 ################################################################
5562 00:56:42.371777
5563 00:56:42.648729 01480000 ################################################################
5564 00:56:42.648872
5565 00:56:42.912730 01500000 ################################################################
5566 00:56:42.912862
5567 00:56:43.190770 01580000 ################################################################
5568 00:56:43.190900
5569 00:56:43.445441 01600000 ################################################################
5570 00:56:43.445566
5571 00:56:43.701212 01680000 ################################################################
5572 00:56:43.701362
5573 00:56:43.958783 01700000 ################################################################
5574 00:56:43.958903
5575 00:56:44.208397 01780000 ################################################################
5576 00:56:44.208513
5577 00:56:44.458231 01800000 ################################################################
5578 00:56:44.458345
5579 00:56:44.711371 01880000 ################################################################
5580 00:56:44.711490
5581 00:56:44.964397 01900000 ################################################################
5582 00:56:44.964513
5583 00:56:45.225092 01980000 ################################################################
5584 00:56:45.225209
5585 00:56:45.477087 01a00000 ################################################################
5586 00:56:45.477200
5587 00:56:45.752035 01a80000 ################################################################
5588 00:56:45.752154
5589 00:56:46.094322 01b00000 ################################################################
5590 00:56:46.094442
5591 00:56:46.451733 01b80000 ################################################################
5592 00:56:46.451982
5593 00:56:46.799013 01c00000 ################################################################
5594 00:56:46.799127
5595 00:56:47.136497 01c80000 ################################################################
5596 00:56:47.136644
5597 00:56:47.410850 01d00000 ################################################################
5598 00:56:47.410965
5599 00:56:47.680946 01d80000 ################################################################
5600 00:56:47.681065
5601 00:56:47.927701 01e00000 ######################################################### done.
5602 00:56:47.927818
5603 00:56:47.931167 The bootfile was 31917038 bytes long.
5604 00:56:47.931253
5605 00:56:47.933848 Sending tftp read request... done.
5606 00:56:47.933921
5607 00:56:47.937286 Waiting for the transfer...
5608 00:56:47.937355
5609 00:56:47.937419 00000000 # done.
5610 00:56:47.937476
5611 00:56:47.944029 Command line loaded dynamically from TFTP file: 14368556/tftp-deploy-bd1jyqqo/kernel/cmdline
5612 00:56:47.944101
5613 00:56:47.970477 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368556/extract-nfsrootfs-cgeyw8ut,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5614 00:56:47.970559
5615 00:56:47.970624 Loading FIT.
5616 00:56:47.970679
5617 00:56:47.973862 Image ramdisk-1 has 18732254 bytes.
5618 00:56:47.973926
5619 00:56:47.977391 Image fdt-1 has 57695 bytes.
5620 00:56:47.977459
5621 00:56:47.980689 Image kernel-1 has 13125045 bytes.
5622 00:56:47.980760
5623 00:56:47.991001 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5624 00:56:47.991098
5625 00:56:48.000833 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5626 00:56:48.000913
5627 00:56:48.007632 Choosing best match conf-1 for compat google,juniper-sku16.
5628 00:56:48.011553
5629 00:56:48.016176 Connected to device vid:did:rid of 1ae0:0028:00
5630 00:56:48.023248
5631 00:56:48.026457 tpm_get_response: command 0x17b, return code 0x0
5632 00:56:48.026525
5633 00:56:48.029990 tpm_cleanup: add release locality here.
5634 00:56:48.030080
5635 00:56:48.033226 Shutting down all USB controllers.
5636 00:56:48.033296
5637 00:56:48.036759 Removing current net device
5638 00:56:48.036830
5639 00:56:48.040172 Exiting depthcharge with code 4 at timestamp: 34757310
5640 00:56:48.040239
5641 00:56:48.043168 LZMA decompressing kernel-1 to 0x80193568
5642 00:56:48.043265
5643 00:56:48.046996 LZMA decompressing kernel-1 to 0x40000000
5644 00:56:49.913727
5645 00:56:49.913864 jumping to kernel
5646 00:56:49.914416 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
5647 00:56:49.914533 start: 2.2.5 auto-login-action (timeout 00:04:07) [common]
5648 00:56:49.914611 Setting prompt string to ['Linux version [0-9]']
5649 00:56:49.914696 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5650 00:56:49.914772 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5651 00:56:49.988913
5652 00:56:49.992292 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5653 00:56:49.995704 start: 2.2.5.1 login-action (timeout 00:04:07) [common]
5654 00:56:49.995793 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5655 00:56:49.995867 Setting prompt string to []
5656 00:56:49.995936 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5657 00:56:49.996008 Using line separator: #'\n'#
5658 00:56:49.996064 No login prompt set.
5659 00:56:49.996118 Parsing kernel messages
5660 00:56:49.996168 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5661 00:56:49.996261 [login-action] Waiting for messages, (timeout 00:04:07)
5662 00:56:49.996326 Waiting using forced prompt support (timeout 00:02:04)
5663 00:56:50.015709 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
5664 00:56:50.018868 [ 0.000000] random: crng init done
5665 00:56:50.022618 [ 0.000000] Machine model: Google juniper sku16 board
5666 00:56:50.025467 [ 0.000000] efi: UEFI not found.
5667 00:56:50.036092 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5668 00:56:50.042577 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5669 00:56:50.052173 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5670 00:56:50.055582 [ 0.000000] printk: bootconsole [mtk8250] enabled
5671 00:56:50.063637 [ 0.000000] NUMA: No NUMA configuration found
5672 00:56:50.070451 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5673 00:56:50.077109 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5674 00:56:50.077213 [ 0.000000] Zone ranges:
5675 00:56:50.083676 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5676 00:56:50.087244 [ 0.000000] DMA32 empty
5677 00:56:50.094117 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5678 00:56:50.097256 [ 0.000000] Movable zone start for each node
5679 00:56:50.100396 [ 0.000000] Early memory node ranges
5680 00:56:50.107068 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5681 00:56:50.113858 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5682 00:56:50.120623 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5683 00:56:50.127254 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5684 00:56:50.133810 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5685 00:56:50.140455 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5686 00:56:50.156407 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5687 00:56:50.162633 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5688 00:56:50.169461 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5689 00:56:50.172690 [ 0.000000] psci: probing for conduit method from DT.
5690 00:56:50.179489 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5691 00:56:50.182602 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5692 00:56:50.189469 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5693 00:56:50.192771 [ 0.000000] psci: SMC Calling Convention v1.1
5694 00:56:50.199216 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5695 00:56:50.202439 [ 0.000000] Detected VIPT I-cache on CPU0
5696 00:56:50.209941 [ 0.000000] CPU features: detected: GIC system register CPU interface
5697 00:56:50.216280 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5698 00:56:50.222683 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5699 00:56:50.229168 [ 0.000000] CPU features: detected: ARM erratum 845719
5700 00:56:50.232566 [ 0.000000] alternatives: applying boot alternatives
5701 00:56:50.235829 [ 0.000000] Fallback order for Node 0: 0
5702 00:56:50.242174 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5703 00:56:50.245958 [ 0.000000] Policy zone: Normal
5704 00:56:50.272551 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368556/extract-nfsrootfs-cgeyw8ut,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5705 00:56:50.286012 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5706 00:56:50.295567 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5707 00:56:50.302285 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5708 00:56:50.309401 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5709 00:56:50.312520 <6>[ 0.000000] software IO TLB: area num 8.
5710 00:56:50.339685 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5711 00:56:50.397773 <6>[ 0.000000] Memory: 3896780K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 261684K reserved, 32768K cma-reserved)
5712 00:56:50.404249 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5713 00:56:50.410805 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5714 00:56:50.414130 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5715 00:56:50.420862 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5716 00:56:50.427317 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5717 00:56:50.430627 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5718 00:56:50.440782 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5719 00:56:50.447310 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5720 00:56:50.450619 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5721 00:56:50.462392 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5722 00:56:50.469200 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5723 00:56:50.472595 <6>[ 0.000000] GICv3: 640 SPIs implemented
5724 00:56:50.476187 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5725 00:56:50.482997 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5726 00:56:50.486158 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5727 00:56:50.492626 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5728 00:56:50.502537 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5729 00:56:50.516031 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5730 00:56:50.522395 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5731 00:56:50.534598 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5732 00:56:50.548087 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5733 00:56:50.554189 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5734 00:56:50.561248 <6>[ 0.009469] Console: colour dummy device 80x25
5735 00:56:50.564548 <6>[ 0.014512] printk: console [tty1] enabled
5736 00:56:50.574406 <6>[ 0.018898] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5737 00:56:50.581086 <6>[ 0.029363] pid_max: default: 32768 minimum: 301
5738 00:56:50.584413 <6>[ 0.034245] LSM: Security Framework initializing
5739 00:56:50.594780 <6>[ 0.039161] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5740 00:56:50.601091 <6>[ 0.046785] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5741 00:56:50.607924 <4>[ 0.055657] cacheinfo: Unable to detect cache hierarchy for CPU 0
5742 00:56:50.617905 <6>[ 0.062288] cblist_init_generic: Setting adjustable number of callback queues.
5743 00:56:50.624429 <6>[ 0.069734] cblist_init_generic: Setting shift to 3 and lim to 1.
5744 00:56:50.630981 <6>[ 0.076087] cblist_init_generic: Setting adjustable number of callback queues.
5745 00:56:50.637623 <6>[ 0.083532] cblist_init_generic: Setting shift to 3 and lim to 1.
5746 00:56:50.641082 <6>[ 0.089930] rcu: Hierarchical SRCU implementation.
5747 00:56:50.647733 <6>[ 0.094956] rcu: Max phase no-delay instances is 1000.
5748 00:56:50.654565 <6>[ 0.102883] EFI services will not be available.
5749 00:56:50.658020 <6>[ 0.107830] smp: Bringing up secondary CPUs ...
5750 00:56:50.668117 <6>[ 0.113093] Detected VIPT I-cache on CPU1
5751 00:56:50.675275 <4>[ 0.113140] cacheinfo: Unable to detect cache hierarchy for CPU 1
5752 00:56:50.681666 <6>[ 0.113149] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5753 00:56:50.688687 <6>[ 0.113181] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5754 00:56:50.691686 <6>[ 0.113664] Detected VIPT I-cache on CPU2
5755 00:56:50.698526 <4>[ 0.113697] cacheinfo: Unable to detect cache hierarchy for CPU 2
5756 00:56:50.704850 <6>[ 0.113701] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5757 00:56:50.711737 <6>[ 0.113713] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5758 00:56:50.715353 <6>[ 0.114158] Detected VIPT I-cache on CPU3
5759 00:56:50.721704 <4>[ 0.114189] cacheinfo: Unable to detect cache hierarchy for CPU 3
5760 00:56:50.728585 <6>[ 0.114193] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5761 00:56:50.735237 <6>[ 0.114204] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5762 00:56:50.741871 <6>[ 0.114779] CPU features: detected: Spectre-v2
5763 00:56:50.745085 <6>[ 0.114789] CPU features: detected: Spectre-BHB
5764 00:56:50.751661 <6>[ 0.114793] CPU features: detected: ARM erratum 858921
5765 00:56:50.755213 <6>[ 0.114798] Detected VIPT I-cache on CPU4
5766 00:56:50.761808 <4>[ 0.114847] cacheinfo: Unable to detect cache hierarchy for CPU 4
5767 00:56:50.768494 <6>[ 0.114855] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5768 00:56:50.775217 <6>[ 0.114863] arch_timer: Enabling local workaround for ARM erratum 858921
5769 00:56:50.781935 <6>[ 0.114874] arch_timer: CPU4: Trapping CNTVCT access
5770 00:56:50.788318 <6>[ 0.114881] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5771 00:56:50.791735 <6>[ 0.115366] Detected VIPT I-cache on CPU5
5772 00:56:50.798389 <4>[ 0.115407] cacheinfo: Unable to detect cache hierarchy for CPU 5
5773 00:56:50.805481 <6>[ 0.115413] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5774 00:56:50.812115 <6>[ 0.115420] arch_timer: Enabling local workaround for ARM erratum 858921
5775 00:56:50.818656 <6>[ 0.115426] arch_timer: CPU5: Trapping CNTVCT access
5776 00:56:50.825329 <6>[ 0.115431] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5777 00:56:50.828586 <6>[ 0.115866] Detected VIPT I-cache on CPU6
5778 00:56:50.835127 <4>[ 0.115910] cacheinfo: Unable to detect cache hierarchy for CPU 6
5779 00:56:50.841863 <6>[ 0.115917] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5780 00:56:50.849027 <6>[ 0.115924] arch_timer: Enabling local workaround for ARM erratum 858921
5781 00:56:50.855455 <6>[ 0.115930] arch_timer: CPU6: Trapping CNTVCT access
5782 00:56:50.861877 <6>[ 0.115935] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5783 00:56:50.865408 <6>[ 0.116466] Detected VIPT I-cache on CPU7
5784 00:56:50.872030 <4>[ 0.116510] cacheinfo: Unable to detect cache hierarchy for CPU 7
5785 00:56:50.878579 <6>[ 0.116516] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5786 00:56:50.885578 <6>[ 0.116523] arch_timer: Enabling local workaround for ARM erratum 858921
5787 00:56:50.892386 <6>[ 0.116529] arch_timer: CPU7: Trapping CNTVCT access
5788 00:56:50.898577 <6>[ 0.116535] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5789 00:56:50.901977 <6>[ 0.116582] smp: Brought up 1 node, 8 CPUs
5790 00:56:50.908680 <6>[ 0.355489] SMP: Total of 8 processors activated.
5791 00:56:50.911901 <6>[ 0.360423] CPU features: detected: 32-bit EL0 Support
5792 00:56:50.918573 <6>[ 0.365801] CPU features: detected: 32-bit EL1 Support
5793 00:56:50.922423 <6>[ 0.371169] CPU features: detected: CRC32 instructions
5794 00:56:50.928688 <6>[ 0.376596] CPU: All CPU(s) started at EL2
5795 00:56:50.932018 <6>[ 0.380934] alternatives: applying system-wide alternatives
5796 00:56:50.940694 <6>[ 0.389085] devtmpfs: initialized
5797 00:56:50.953009 <6>[ 0.398032] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5798 00:56:50.962940 <6>[ 0.407981] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5799 00:56:50.966647 <6>[ 0.415710] pinctrl core: initialized pinctrl subsystem
5800 00:56:50.974773 <6>[ 0.422811] DMI not present or invalid.
5801 00:56:50.981180 <6>[ 0.427177] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5802 00:56:50.987797 <6>[ 0.434075] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5803 00:56:50.994572 <6>[ 0.441586] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5804 00:56:51.004915 <6>[ 0.449757] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5805 00:56:51.011265 <6>[ 0.457902] audit: initializing netlink subsys (disabled)
5806 00:56:51.018079 <5>[ 0.463583] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5807 00:56:51.024916 <6>[ 0.464537] thermal_sys: Registered thermal governor 'step_wise'
5808 00:56:51.031244 <6>[ 0.471534] thermal_sys: Registered thermal governor 'power_allocator'
5809 00:56:51.035047 <6>[ 0.477781] cpuidle: using governor menu
5810 00:56:51.041550 <6>[ 0.488728] NET: Registered PF_QIPCRTR protocol family
5811 00:56:51.048182 <6>[ 0.494215] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5812 00:56:51.054612 <6>[ 0.501308] ASID allocator initialised with 32768 entries
5813 00:56:51.058082 <6>[ 0.508078] Serial: AMBA PL011 UART driver
5814 00:56:51.070318 <4>[ 0.518460] Trying to register duplicate clock ID: 113
5815 00:56:51.129123 <6>[ 0.574121] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5816 00:56:51.143494 <6>[ 0.588459] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5817 00:56:51.146914 <6>[ 0.598209] KASLR enabled
5818 00:56:51.161375 <6>[ 0.606195] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5819 00:56:51.168073 <6>[ 0.613198] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5820 00:56:51.174625 <6>[ 0.619675] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5821 00:56:51.181336 <6>[ 0.626666] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5822 00:56:51.187851 <6>[ 0.633140] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5823 00:56:51.194599 <6>[ 0.640130] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5824 00:56:51.201278 <6>[ 0.646604] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5825 00:56:51.207951 <6>[ 0.653594] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5826 00:56:51.211082 <6>[ 0.661135] ACPI: Interpreter disabled.
5827 00:56:51.221162 <6>[ 0.669129] iommu: Default domain type: Translated
5828 00:56:51.227299 <6>[ 0.674286] iommu: DMA domain TLB invalidation policy: strict mode
5829 00:56:51.231182 <5>[ 0.680932] SCSI subsystem initialized
5830 00:56:51.237625 <6>[ 0.685390] usbcore: registered new interface driver usbfs
5831 00:56:51.244077 <6>[ 0.691119] usbcore: registered new interface driver hub
5832 00:56:51.247451 <6>[ 0.696663] usbcore: registered new device driver usb
5833 00:56:51.255106 <6>[ 0.702977] pps_core: LinuxPPS API ver. 1 registered
5834 00:56:51.264649 <6>[ 0.708162] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5835 00:56:51.267824 <6>[ 0.717487] PTP clock support registered
5836 00:56:51.270958 <6>[ 0.721741] EDAC MC: Ver: 3.0.0
5837 00:56:51.279071 <6>[ 0.727393] FPGA manager framework
5838 00:56:51.282585 <6>[ 0.731072] Advanced Linux Sound Architecture Driver Initialized.
5839 00:56:51.286473 <6>[ 0.737811] vgaarb: loaded
5840 00:56:51.292801 <6>[ 0.740937] clocksource: Switched to clocksource arch_sys_counter
5841 00:56:51.299350 <5>[ 0.747370] VFS: Disk quotas dquot_6.6.0
5842 00:56:51.306432 <6>[ 0.751548] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5843 00:56:51.309567 <6>[ 0.758720] pnp: PnP ACPI: disabled
5844 00:56:51.317165 <6>[ 0.765601] NET: Registered PF_INET protocol family
5845 00:56:51.323920 <6>[ 0.770826] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5846 00:56:51.335900 <6>[ 0.780738] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5847 00:56:51.342653 <6>[ 0.789491] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5848 00:56:51.352883 <6>[ 0.797442] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5849 00:56:51.359286 <6>[ 0.805673] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5850 00:56:51.365951 <6>[ 0.813767] TCP: Hash tables configured (established 32768 bind 32768)
5851 00:56:51.372653 <6>[ 0.820597] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5852 00:56:51.382729 <6>[ 0.827570] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5853 00:56:51.389220 <6>[ 0.835050] NET: Registered PF_UNIX/PF_LOCAL protocol family
5854 00:56:51.392804 <6>[ 0.841179] RPC: Registered named UNIX socket transport module.
5855 00:56:51.399177 <6>[ 0.847324] RPC: Registered udp transport module.
5856 00:56:51.402619 <6>[ 0.852249] RPC: Registered tcp transport module.
5857 00:56:51.409276 <6>[ 0.857173] RPC: Registered tcp NFSv4.1 backchannel transport module.
5858 00:56:51.415803 <6>[ 0.863828] PCI: CLS 0 bytes, default 64
5859 00:56:51.419175 <6>[ 0.868082] Unpacking initramfs...
5860 00:56:51.432544 <6>[ 0.877547] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5861 00:56:51.442458 <6>[ 0.886169] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5862 00:56:51.445618 <6>[ 0.895019] kvm [1]: IPA Size Limit: 40 bits
5863 00:56:51.453064 <6>[ 0.901343] kvm [1]: vgic-v2@c420000
5864 00:56:51.456219 <6>[ 0.905158] kvm [1]: GIC system register CPU interface enabled
5865 00:56:51.462913 <6>[ 0.911332] kvm [1]: vgic interrupt IRQ18
5866 00:56:51.466144 <6>[ 0.915694] kvm [1]: Hyp mode initialized successfully
5867 00:56:51.473751 <5>[ 0.922004] Initialise system trusted keyrings
5868 00:56:51.480224 <6>[ 0.926827] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5869 00:56:51.488709 <6>[ 0.936800] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5870 00:56:51.495333 <5>[ 0.943264] NFS: Registering the id_resolver key type
5871 00:56:51.498790 <5>[ 0.948578] Key type id_resolver registered
5872 00:56:51.505140 <5>[ 0.952992] Key type id_legacy registered
5873 00:56:51.512414 <6>[ 0.957305] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
5874 00:56:51.518418 <6>[ 0.964226] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
5875 00:56:51.525004 <6>[ 0.972000] 9p: Installing v9fs 9p2000 file system support
5876 00:56:51.552672 <5>[ 1.000762] Key type asymmetric registered
5877 00:56:51.556341 <5>[ 1.005110] Asymmetric key parser 'x509' registered
5878 00:56:51.565635 <6>[ 1.010265] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
5879 00:56:51.568998 <6>[ 1.017886] io scheduler mq-deadline registered
5880 00:56:51.572360 <6>[ 1.022644] io scheduler kyber registered
5881 00:56:51.595146 <6>[ 1.043433] EINJ: ACPI disabled.
5882 00:56:51.601316 <4>[ 1.047227] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
5883 00:56:51.639821 <6>[ 1.087910] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
5884 00:56:51.647691 <6>[ 1.096402] printk: console [ttyS0] disabled
5885 00:56:51.675732 <6>[ 1.121061] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
5886 00:56:51.682615 <6>[ 1.130538] printk: console [ttyS0] enabled
5887 00:56:51.686122 <6>[ 1.130538] printk: console [ttyS0] enabled
5888 00:56:51.692838 <6>[ 1.139458] printk: bootconsole [mtk8250] disabled
5889 00:56:51.695879 <6>[ 1.139458] printk: bootconsole [mtk8250] disabled
5890 00:56:51.705994 <3>[ 1.149999] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
5891 00:56:51.712510 <3>[ 1.158381] mt6577-uart 11003000.serial: Error applying setting, reverse things back
5892 00:56:51.741544 <6>[ 1.186793] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
5893 00:56:51.748451 <6>[ 1.196459] serial serial0: tty port ttyS1 registered
5894 00:56:51.755081 <6>[ 1.203029] SuperH (H)SCI(F) driver initialized
5895 00:56:51.758078 <6>[ 1.208540] msm_serial: driver initialized
5896 00:56:51.773744 <6>[ 1.218857] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
5897 00:56:51.783631 <6>[ 1.227453] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
5898 00:56:51.790535 <6>[ 1.236029] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
5899 00:56:51.800370 <6>[ 1.244598] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
5900 00:56:51.807431 <6>[ 1.253251] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
5901 00:56:51.817197 <6>[ 1.261912] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
5902 00:56:51.827131 <6>[ 1.270653] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
5903 00:56:51.833929 <6>[ 1.279394] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
5904 00:56:51.843861 <6>[ 1.287960] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
5905 00:56:51.850262 <6>[ 1.296761] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
5906 00:56:51.860935 <4>[ 1.309126] cacheinfo: Unable to detect cache hierarchy for CPU 0
5907 00:56:51.870215 <6>[ 1.318532] loop: module loaded
5908 00:56:51.882132 <6>[ 1.330456] vsim1: Bringing 1800000uV into 2700000-2700000uV
5909 00:56:51.900005 <6>[ 1.348472] megasas: 07.719.03.00-rc1
5910 00:56:51.908815 <6>[ 1.357239] spi-nor spi1.0: w25q64dw (8192 Kbytes)
5911 00:56:51.916003 <6>[ 1.364333] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
5912 00:56:51.932779 <6>[ 1.381008] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
5913 00:56:51.989231 <6>[ 1.431083] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b8
5914 00:56:52.030046 <6>[ 1.478431] Freeing initrd memory: 18288K
5915 00:56:52.045498 <4>[ 1.490239] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
5916 00:56:52.052551 <4>[ 1.499467] CPU: 6 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1
5917 00:56:52.058513 <4>[ 1.506165] Hardware name: Google juniper sku16 board (DT)
5918 00:56:52.062136 <4>[ 1.511903] Call trace:
5919 00:56:52.065808 <4>[ 1.514604] dump_backtrace.part.0+0xe0/0xf0
5920 00:56:52.068861 <4>[ 1.519140] show_stack+0x18/0x30
5921 00:56:52.071954 <4>[ 1.522712] dump_stack_lvl+0x68/0x84
5922 00:56:52.075475 <4>[ 1.526632] dump_stack+0x18/0x34
5923 00:56:52.082310 <4>[ 1.530202] sysfs_warn_dup+0x64/0x80
5924 00:56:52.085213 <4>[ 1.534124] sysfs_do_create_link_sd+0xf0/0x100
5925 00:56:52.088586 <4>[ 1.538911] sysfs_create_link+0x20/0x40
5926 00:56:52.095579 <4>[ 1.543091] bus_add_device+0x68/0x10c
5927 00:56:52.098671 <4>[ 1.547097] device_add+0x340/0x7ac
5928 00:56:52.101946 <4>[ 1.550840] of_device_add+0x44/0x60
5929 00:56:52.105667 <4>[ 1.554674] of_platform_device_create_pdata+0x90/0x120
5930 00:56:52.112273 <4>[ 1.560156] of_platform_bus_create+0x170/0x370
5931 00:56:52.115253 <4>[ 1.564942] of_platform_populate+0x50/0xfc
5932 00:56:52.122000 <4>[ 1.569382] parse_mtd_partitions+0x1dc/0x510
5933 00:56:52.125452 <4>[ 1.573995] mtd_device_parse_register+0xf8/0x2e0
5934 00:56:52.128698 <4>[ 1.578953] spi_nor_probe+0x21c/0x2f0
5935 00:56:52.131895 <4>[ 1.582960] spi_mem_probe+0x6c/0xb0
5936 00:56:52.135163 <4>[ 1.586792] spi_probe+0x84/0xe4
5937 00:56:52.141938 <4>[ 1.590274] really_probe+0xbc/0x2e0
5938 00:56:52.145391 <4>[ 1.594105] __driver_probe_device+0x78/0x11c
5939 00:56:52.148738 <4>[ 1.598717] driver_probe_device+0xd8/0x160
5940 00:56:52.155288 <4>[ 1.603155] __device_attach_driver+0xb8/0x134
5941 00:56:52.158575 <4>[ 1.607854] bus_for_each_drv+0x78/0xd0
5942 00:56:52.161611 <4>[ 1.611945] __device_attach+0xa8/0x1c0
5943 00:56:52.168313 <4>[ 1.616035] device_initial_probe+0x14/0x20
5944 00:56:52.171989 <4>[ 1.620473] bus_probe_device+0x9c/0xa4
5945 00:56:52.175503 <4>[ 1.624564] device_add+0x3ac/0x7ac
5946 00:56:52.178207 <4>[ 1.628306] __spi_add_device+0x78/0x120
5947 00:56:52.181894 <4>[ 1.632485] spi_add_device+0x40/0x7c
5948 00:56:52.188466 <4>[ 1.636402] spi_register_controller+0x610/0xad0
5949 00:56:52.192011 <4>[ 1.641276] devm_spi_register_controller+0x4c/0xa4
5950 00:56:52.198840 <4>[ 1.646409] mtk_spi_probe+0x3f8/0x650
5951 00:56:52.201827 <4>[ 1.650413] platform_probe+0x68/0xe0
5952 00:56:52.205354 <4>[ 1.654332] really_probe+0xbc/0x2e0
5953 00:56:52.209021 <4>[ 1.658162] __driver_probe_device+0x78/0x11c
5954 00:56:52.215207 <4>[ 1.662773] driver_probe_device+0xd8/0x160
5955 00:56:52.218665 <4>[ 1.667211] __driver_attach+0x94/0x19c
5956 00:56:52.221961 <4>[ 1.671302] bus_for_each_dev+0x70/0xd0
5957 00:56:52.225510 <4>[ 1.675392] driver_attach+0x24/0x30
5958 00:56:52.228564 <4>[ 1.679222] bus_add_driver+0x154/0x20c
5959 00:56:52.235267 <4>[ 1.683312] driver_register+0x78/0x130
5960 00:56:52.238811 <4>[ 1.687403] __platform_driver_register+0x28/0x34
5961 00:56:52.242015 <4>[ 1.692362] mtk_spi_driver_init+0x1c/0x28
5962 00:56:52.248850 <4>[ 1.696716] do_one_initcall+0x50/0x1d0
5963 00:56:52.251968 <4>[ 1.700806] kernel_init_freeable+0x21c/0x288
5964 00:56:52.255290 <4>[ 1.705420] kernel_init+0x24/0x12c
5965 00:56:52.258948 <4>[ 1.709165] ret_from_fork+0x10/0x20
5966 00:56:52.269853 <6>[ 1.718070] tun: Universal TUN/TAP device driver, 1.6
5967 00:56:52.273035 <6>[ 1.724350] thunder_xcv, ver 1.0
5968 00:56:52.276375 <6>[ 1.727866] thunder_bgx, ver 1.0
5969 00:56:52.279784 <6>[ 1.731371] nicpf, ver 1.0
5970 00:56:52.290768 <6>[ 1.735738] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
5971 00:56:52.294099 <6>[ 1.743223] hns3: Copyright (c) 2017 Huawei Corporation.
5972 00:56:52.297357 <6>[ 1.748821] hclge is initializing
5973 00:56:52.304407 <6>[ 1.752408] e1000: Intel(R) PRO/1000 Network Driver
5974 00:56:52.310983 <6>[ 1.757544] e1000: Copyright (c) 1999-2006 Intel Corporation.
5975 00:56:52.314214 <6>[ 1.763565] e1000e: Intel(R) PRO/1000 Network Driver
5976 00:56:52.321186 <6>[ 1.768786] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
5977 00:56:52.327881 <6>[ 1.774978] igb: Intel(R) Gigabit Ethernet Network Driver
5978 00:56:52.334312 <6>[ 1.780633] igb: Copyright (c) 2007-2014 Intel Corporation.
5979 00:56:52.340766 <6>[ 1.786477] igbvf: Intel(R) Gigabit Virtual Function Network Driver
5980 00:56:52.344303 <6>[ 1.793001] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
5981 00:56:52.351270 <6>[ 1.799550] sky2: driver version 1.30
5982 00:56:52.357909 <6>[ 1.804797] usbcore: registered new device driver r8152-cfgselector
5983 00:56:52.364808 <6>[ 1.811339] usbcore: registered new interface driver r8152
5984 00:56:52.367943 <6>[ 1.817165] VFIO - User Level meta-driver version: 0.3
5985 00:56:52.376860 <6>[ 1.824974] mtu3 11201000.usb: uwk - reg:0x420, version:101
5986 00:56:52.383369 <4>[ 1.830845] mtu3 11201000.usb: supply vbus not found, using dummy regulator
5987 00:56:52.390029 <6>[ 1.838116] mtu3 11201000.usb: dr_mode: 1, drd: auto
5988 00:56:52.397320 <6>[ 1.843341] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
5989 00:56:52.400132 <6>[ 1.849524] mtu3 11201000.usb: usb3-drd: 0
5990 00:56:52.410360 <6>[ 1.855076] mtu3 11201000.usb: xHCI platform device register success...
5991 00:56:52.417021 <4>[ 1.863686] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
5992 00:56:52.423915 <6>[ 1.871638] xhci-mtk 11200000.usb: xHCI Host Controller
5993 00:56:52.430315 <6>[ 1.877155] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
5994 00:56:52.436945 <6>[ 1.884875] xhci-mtk 11200000.usb: USB3 root hub has no ports
5995 00:56:52.447100 <6>[ 1.890883] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
5996 00:56:52.453897 <6>[ 1.900308] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
5997 00:56:52.456826 <6>[ 1.906381] xhci-mtk 11200000.usb: xHCI Host Controller
5998 00:56:52.467430 <6>[ 1.911871] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
5999 00:56:52.473662 <6>[ 1.919529] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6000 00:56:52.477040 <6>[ 1.926349] hub 1-0:1.0: USB hub found
6001 00:56:52.480268 <6>[ 1.930377] hub 1-0:1.0: 1 port detected
6002 00:56:52.490756 <6>[ 1.935734] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6003 00:56:52.493951 <6>[ 1.944345] hub 2-0:1.0: USB hub found
6004 00:56:52.500624 <3>[ 1.948372] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6005 00:56:52.507975 <6>[ 1.956261] usbcore: registered new interface driver usb-storage
6006 00:56:52.514885 <6>[ 1.962865] usbcore: registered new device driver onboard-usb-hub
6007 00:56:52.532197 <4>[ 1.977035] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6008 00:56:52.541129 <6>[ 1.989296] mt6397-rtc mt6358-rtc: registered as rtc0
6009 00:56:52.551265 <6>[ 1.994775] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-16T00:56:52 UTC (1718499412)
6010 00:56:52.554105 <6>[ 2.004661] i2c_dev: i2c /dev entries driver
6011 00:56:52.566154 <6>[ 2.011102] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6012 00:56:52.576131 <6>[ 2.019428] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6013 00:56:52.579236 <6>[ 2.028333] i2c 4-0058: Fixed dependency cycle(s) with /panel
6014 00:56:52.589266 <6>[ 2.034364] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6015 00:56:52.596314 <3>[ 2.041816] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
6016 00:56:52.613508 <6>[ 2.061720] cpu cpu0: EM: created perf domain
6017 00:56:52.623567 <6>[ 2.067153] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6018 00:56:52.630277 <6>[ 2.078428] cpu cpu4: EM: created perf domain
6019 00:56:52.637209 <6>[ 2.085502] sdhci: Secure Digital Host Controller Interface driver
6020 00:56:52.643727 <6>[ 2.091958] sdhci: Copyright(c) Pierre Ossman
6021 00:56:52.650932 <6>[ 2.097360] Synopsys Designware Multimedia Card Interface Driver
6022 00:56:52.657167 <6>[ 2.097820] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6023 00:56:52.660838 <6>[ 2.104391] sdhci-pltfm: SDHCI platform and OF driver helper
6024 00:56:52.669327 <6>[ 2.117722] ledtrig-cpu: registered to indicate activity on CPUs
6025 00:56:52.677196 <6>[ 2.125492] usbcore: registered new interface driver usbhid
6026 00:56:52.681036 <6>[ 2.131331] usbhid: USB HID core driver
6027 00:56:52.691055 <6>[ 2.135620] spi_master spi2: will run message pump with realtime priority
6028 00:56:52.697926 <4>[ 2.135688] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6029 00:56:52.704606 <4>[ 2.150243] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6030 00:56:52.728309 <6>[ 2.169720] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6031 00:56:52.746832 <6>[ 2.185032] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6032 00:56:52.753485 <4>[ 2.195880] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6033 00:56:52.756795 <6>[ 2.199964] cros-ec-spi spi2.0: Chrome EC device registered
6034 00:56:52.770099 <4>[ 2.214684] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6035 00:56:52.773089 <6>[ 2.221143] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14
6036 00:56:52.780543 <6>[ 2.228231] mmc0: new HS400 MMC card at address 0001
6037 00:56:52.786639 <6>[ 2.234767] mmcblk0: mmc0:0001 TB2932 29.2 GiB
6038 00:56:52.797081 <4>[ 2.241890] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6039 00:56:52.803689 <6>[ 2.243598] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6040 00:56:52.810435 <4>[ 2.256365] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6041 00:56:52.813380 <6>[ 2.259362] mmcblk0boot0: mmc0:0001 TB2932 4.00 MiB
6042 00:56:52.821642 <6>[ 2.269780] mmcblk0boot1: mmc0:0001 TB2932 4.00 MiB
6043 00:56:52.828379 <6>[ 2.275511] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6044 00:56:52.834947 <6>[ 2.276644] mmcblk0rpmb: mmc0:0001 TB2932 4.00 MiB, chardev (507:0)
6045 00:56:52.863818 <6>[ 2.305225] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6046 00:56:52.873739 <6>[ 2.317614] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6047 00:56:52.883529 <6>[ 2.319500] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6048 00:56:52.900574 <6>[ 2.342172] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6049 00:56:52.907346 <6>[ 2.353188] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6050 00:56:52.910937 <6>[ 2.354819] NET: Registered PF_PACKET protocol family
6051 00:56:52.917518 <6>[ 2.365446] 9pnet: Installing 9P2000 support
6052 00:56:52.920898 <5>[ 2.370032] Key type dns_resolver registered
6053 00:56:52.927336 <6>[ 2.375302] registered taskstats version 1
6054 00:56:52.930929 <5>[ 2.379689] Loading compiled-in X.509 certificates
6055 00:56:52.979788 <3>[ 2.424616] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6056 00:56:53.010758 <6>[ 2.452208] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6057 00:56:53.021031 <6>[ 2.466052] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6058 00:56:53.031008 <6>[ 2.474623] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6059 00:56:53.037556 <6>[ 2.483149] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6060 00:56:53.047564 <6>[ 2.491673] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6061 00:56:53.054326 <6>[ 2.500194] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6062 00:56:53.064566 <6>[ 2.508715] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6063 00:56:53.067377 <6>[ 2.508747] hub 1-1:1.0: USB hub found
6064 00:56:53.077807 <6>[ 2.517230] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6065 00:56:53.084262 <6>[ 2.517957] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6066 00:56:53.087466 <6>[ 2.521640] hub 1-1:1.0: 3 ports detected
6067 00:56:53.094050 <6>[ 2.530755] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6068 00:56:53.100760 <6>[ 2.547931] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6069 00:56:53.107518 <6>[ 2.555282] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6070 00:56:53.117499 <6>[ 2.562753] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6071 00:56:53.124175 <6>[ 2.571032] panfrost 13040000.gpu: clock rate = 511999970
6072 00:56:53.134392 <6>[ 2.576733] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6073 00:56:53.140949 <6>[ 2.587000] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6074 00:56:53.150767 <6>[ 2.595024] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6075 00:56:53.161075 <6>[ 2.603457] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6076 00:56:53.167489 <6>[ 2.615534] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6077 00:56:53.181663 <6>[ 2.626619] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6078 00:56:53.191578 <6>[ 2.635542] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6079 00:56:53.201623 <6>[ 2.644690] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6080 00:56:53.208182 <6>[ 2.653822] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6081 00:56:53.218424 <6>[ 2.662951] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6082 00:56:53.228687 <6>[ 2.672252] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6083 00:56:53.238588 <6>[ 2.681552] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6084 00:56:53.248298 <6>[ 2.691026] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6085 00:56:53.254918 <6>[ 2.700500] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6086 00:56:53.265169 <6>[ 2.709626] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6087 00:56:53.337246 <6>[ 2.781969] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6088 00:56:53.346765 <6>[ 2.790864] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6089 00:56:53.357349 <6>[ 2.802704] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6090 00:56:53.379625 <6>[ 2.824953] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
6091 00:56:53.484164 <6>[ 2.932541] hub 1-1.1:1.0: USB hub found
6092 00:56:53.487758 <6>[ 2.937016] hub 1-1.1:1.0: 4 ports detected
6093 00:56:54.055095 <6>[ 3.487134] Console: switching to colour frame buffer device 170x48
6094 00:56:54.065308 <6>[ 3.510368] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6095 00:56:54.085023 <6>[ 3.526737] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6096 00:56:54.103250 <6>[ 3.544784] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6097 00:56:54.109812 <6>[ 3.557016] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6098 00:56:54.120481 <6>[ 3.565322] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6099 00:56:54.130439 <6>[ 3.572202] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6100 00:56:54.149906 <6>[ 3.591632] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6101 00:56:54.156459 <6>[ 3.600980] usb 1-1.2: new high-speed USB device number 4 using xhci-mtk
6102 00:56:54.163006 <6>[ 3.602831] Trying to probe devices needed for running init ...
6103 00:56:54.176266 <3>[ 3.621418] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: could not get audiosys reset:-517
6104 00:56:54.192579 <6>[ 3.633717] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6105 00:56:54.352511 <6>[ 3.797274] r8152-cfgselector 1-1.2: reset high-speed USB device number 4 using xhci-mtk
6106 00:56:54.480134 <4>[ 3.924599] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6107 00:56:54.490039 <4>[ 3.933867] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6108 00:56:54.535245 <6>[ 3.983150] r8152 1-1.2:1.0 eth0: v1.12.13
6109 00:56:54.541762 <6>[ 3.984967] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
6110 00:56:54.563311 <6>[ 4.004087] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6111 00:56:54.747939 <6>[ 4.193112] usb 1-1.3: new high-speed USB device number 6 using xhci-mtk
6112 00:56:54.889028 <6>[ 4.330672] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6113 00:56:54.940412 <6>[ 4.385493] r8152-cfgselector 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
6114 00:56:55.069596 <4>[ 4.514657] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6115 00:56:55.081761 <4>[ 4.526598] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6116 00:56:55.125283 <6>[ 4.573771] r8152 1-1.1.1:1.0 eth1: v1.12.13
6117 00:56:55.146656 <6>[ 4.587907] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6118 00:56:55.165936 <6>[ 4.607112] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6119 00:56:56.132080 <6>[ 5.579751] r8152 1-1.2:1.0 eth0: carrier on
6120 00:56:58.169204 <5>[ 5.601110] Sending DHCP requests .., OK
6121 00:56:58.181950 <6>[ 7.626190] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.17
6122 00:56:58.191558 <6>[ 7.639438] IP-Config: Complete:
6123 00:56:58.206395 <6>[ 7.647780] device=eth0, hwaddr=00:e0:4c:68:03:2b, ipaddr=192.168.201.17, mask=255.255.255.0, gw=192.168.201.1
6124 00:56:58.219204 <6>[ 7.663503] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-5, domain=lava-rack, nis-domain=(none)
6125 00:56:58.232442 <6>[ 7.676755] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6126 00:56:58.239517 <6>[ 7.676764] nameserver0=192.168.201.1
6127 00:56:58.271224 <6>[ 7.719018] clk: Disabling unused clocks
6128 00:56:58.275973 <6>[ 7.727028] ALSA device list:
6129 00:56:58.284657 <6>[ 7.732478] No soundcards found.
6130 00:56:58.292866 <6>[ 7.740511] Freeing unused kernel memory: 8512K
6131 00:56:58.299193 <6>[ 7.747290] Run /init as init process
6132 00:56:58.310121 Loading, please wait...
6133 00:56:58.338474 Starting systemd-udevd version 252.22-1~deb12u1
6134 00:56:58.648093 <6>[ 8.092305] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6135 00:56:58.658075 <6>[ 8.097397] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6136 00:56:58.671379 <3>[ 8.112373] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6137 00:56:58.675062 <3>[ 8.114363] thermal_sys: Failed to find 'trips' node
6138 00:56:58.681669 <3>[ 8.122851] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6139 00:56:58.688220 <3>[ 8.128020] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6140 00:56:58.698111 <3>[ 8.128037] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6141 00:56:58.708282 <4>[ 8.128041] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6142 00:56:58.711633 <6>[ 8.128331] mc: Linux media interface: v0.10
6143 00:56:58.718359 <4>[ 8.128531] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6144 00:56:58.728822 <4>[ 8.128633] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6145 00:56:58.732419 <3>[ 8.129401] thermal_sys: Failed to find 'trips' node
6146 00:56:58.739430 <3>[ 8.129405] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6147 00:56:58.748856 <3>[ 8.129411] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6148 00:56:58.755986 <4>[ 8.129414] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6149 00:56:58.765735 <4>[ 8.131442] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6150 00:56:58.775491 <6>[ 8.132898] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6151 00:56:58.785582 <3>[ 8.135082] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6152 00:56:58.799268 <6>[ 8.136313] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6153 00:56:58.811887 <3>[ 8.136811] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6154 00:56:58.815399 <6>[ 8.151261] r8152 1-1.1.1:1.0 enx88541f0f7aca: renamed from eth1
6155 00:56:58.825572 <3>[ 8.152793] elan_i2c 2-0015: Error applying setting, reverse things back
6156 00:56:58.831926 <6>[ 8.160849] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6157 00:56:58.838203 <6>[ 8.165583] videodev: Linux video capture interface: v2.00
6158 00:56:58.845426 <3>[ 8.172319] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6159 00:56:58.852183 <6>[ 8.181823] cs_system_cfg: CoreSight Configuration manager initialised
6160 00:56:58.862285 <3>[ 8.185190] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6161 00:56:58.869231 <5>[ 8.198071] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6162 00:56:58.879264 <3>[ 8.200642] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6163 00:56:58.885590 <5>[ 8.220351] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6164 00:56:58.895709 <3>[ 8.229014] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6165 00:56:58.902354 <5>[ 8.240441] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6166 00:56:58.912428 <3>[ 8.250755] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6167 00:56:58.922416 <4>[ 8.263222] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6168 00:56:58.928852 <3>[ 8.269429] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6169 00:56:58.941849 <3>[ 8.269806] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6170 00:56:58.948811 <3>[ 8.270668] debugfs: File 'Playback' in directory 'dapm' already present!
6171 00:56:58.955636 <3>[ 8.270677] debugfs: File 'Capture' in directory 'dapm' already present!
6172 00:56:58.965844 <6>[ 8.272353] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6173 00:56:58.972023 <3>[ 8.275376] thermal_sys: Failed to find 'trips' node
6174 00:56:58.978917 <3>[ 8.275383] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6175 00:56:58.988827 <3>[ 8.275393] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6176 00:56:58.995476 <4>[ 8.275398] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6177 00:56:59.002634 <6>[ 8.276382] cfg80211: failed to load regulatory.db
6178 00:56:59.012487 <6>[ 8.289573] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6179 00:56:59.022391 <3>[ 8.290630] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6180 00:56:59.028856 <6>[ 8.306753] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6181 00:56:59.039424 <3>[ 8.306811] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6182 00:56:59.045894 <3>[ 8.306839] mtk-scp 10500000.scp: invalid resource
6183 00:56:59.052719 <6>[ 8.306885] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6184 00:56:59.059733 <6>[ 8.308673] remoteproc remoteproc0: scp is available
6185 00:56:59.069791 <4>[ 8.308747] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6186 00:56:59.075877 <6>[ 8.308754] remoteproc remoteproc0: powering up scp
6187 00:56:59.083410 <4>[ 8.308769] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6188 00:56:59.090253 <3>[ 8.308772] remoteproc remoteproc0: request_firmware failed: -2
6189 00:56:59.096783 <6>[ 8.315629] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6190 00:56:59.104360 <3>[ 8.323372] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6191 00:56:59.110848 <6>[ 8.324789] Bluetooth: Core ver 2.22
6192 00:56:59.114526 <6>[ 8.324851] NET: Registered PF_BLUETOOTH protocol family
6193 00:56:59.124466 Begin: Loading e<6>[ 8.324854] Bluetooth: HCI device and connection manager initialized
6194 00:56:59.130943 ssential drivers<6>[ 8.324869] Bluetooth: HCI socket layer initialized
6195 00:56:59.131384 ... done.
6196 00:56:59.137761 Begi<6>[ 8.324875] Bluetooth: L2CAP socket layer initialized
6197 00:56:59.143968 n: Running /scri<6>[ 8.324886] Bluetooth: SCO socket layer initialized
6198 00:56:59.151136 pts/init-premoun<6>[ 8.331983] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6199 00:56:59.154348 t ... done.
6200 00:56:59.160727 Begin: Mounting roo<6>[ 8.349737] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6201 00:56:59.173772 t file system ... Begin: Running /scripts/nfs-to<6>[ 8.357329] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6202 00:56:59.174260 p ... done.
6203 00:56:59.183660 Begin: Running /scripts/nfs-premoun<6>[ 8.364949] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6204 00:56:59.194074 t ... Waiting up to 60 secs for <6>[ 8.374242] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6205 00:56:59.200267 any ethernet to become available<6>[ 8.374368] Bluetooth: HCI UART driver ver 2.3
6206 00:56:59.200665
6207 00:56:59.210408 Device /sys/class/net/enx88541<6>[ 8.374376] Bluetooth: HCI UART protocol H4 registered
6208 00:56:59.210810 f0f7aca found
6209 00:56:59.211122 done.
6210 00:56:59.217341 Begin: Wai<6>[ 8.374438] Bluetooth: HCI UART protocol LL registered
6211 00:56:59.226948 ting up to 180 secs for any netw<6>[ 8.374476] Bluetooth: HCI UART protocol Three-wire (H5) registered
6212 00:56:59.237252 ork device to become available .<6>[ 8.374959] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video0
6213 00:56:59.237748 .. done.
6214 00:56:59.243875 <6>[ 8.375078] Bluetooth: HCI UART protocol Broadcom registered
6215 00:56:59.251764 <6>[ 8.375109] Bluetooth: HCI UART protocol QCA registered
6216 00:56:59.258971 <6>[ 8.375156] Bluetooth: HCI UART protocol Marvell registered
6217 00:56:59.267328 <6>[ 8.375867] Bluetooth: hci0: setting up ROME/QCA6390
6218 00:56:59.281289 <6>[ 8.383274] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6219 00:56:59.291553 <6>[ 8.394303] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6220 00:56:59.301276 <6>[ 8.394562] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video3 (81,3)
6221 00:56:59.308593 <6>[ 8.401493] usbcore: registered new interface driver uvcvideo
6222 00:56:59.320486 <6>[ 8.408392] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6223 00:56:59.329998 <6>[ 8.410666] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6224 00:56:59.341826 <6>[ 8.410673] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6225 00:56:59.355509 <6>[ 8.410994] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6226 00:56:59.365810 <4>[ 8.526121] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6227 00:56:59.372338 <4>[ 8.526121] Fallback method does not support PEC.
6228 00:56:59.382077 <6>[ 8.527509] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6229 00:56:59.392331 <3>[ 8.538642] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6230 00:56:59.402026 <6>[ 8.541958] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6231 00:56:59.412067 <3>[ 8.557623] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6232 00:56:59.421946 <6>[ 8.559133] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6233 00:56:59.428682 <3>[ 8.591367] Bluetooth: hci0: Frame reassembly failed (-84)
6234 00:56:59.496273 <6>[ 8.939374] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6235 00:56:59.502704 <6>[ 8.940983] Bluetooth: hci0: QCA Product ID :0x00000008
6236 00:56:59.515933 <6>[ 8.963639] Bluetooth: hci0: QCA SOC Version :0x00000044
6237 00:56:59.522023 <6>[ 8.970270] Bluetooth: hci0: QCA ROM Version :0x00000302
6238 00:56:59.528818 <6>[ 8.976878] Bluetooth: hci0: QCA Patch Version:0x00000111
6239 00:56:59.535261 IP-Config: enx88<6>[ 8.983459] Bluetooth: hci0: QCA controller version 0x00440302
6240 00:56:59.545254 541f0f7aca hardw<6>[ 8.990898] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6241 00:56:59.555454 are address 88:5<4>[ 8.999018] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6242 00:56:59.565146 4:1f:0f:7a:ca mt<3>[ 9.009632] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6243 00:56:59.572025 <4>[ 9.016839] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6244 00:56:59.572115 u 1500 DHCP
6245 00:56:59.581089 <3>[ 9.018509] Bluetooth: hci0: QCA Failed to download patch (-2)
6246 00:56:59.604576 IP-Config: eth0 hardware address<4>[ 9.051556] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6247 00:56:59.607648 00:e0:4c:68:03:2b mtu 1500 DHCP
6248 00:56:59.614224 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6249 00:56:59.621113 address:<4>[ 9.066766] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6250 00:56:59.634263 192.168.201.17 broadcast: 192.168.201.255 netmask: 255.255.2<4>[ 9.080453] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6251 00:56:59.634387 55.0
6252 00:56:59.641170 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6253 00:56:59.647576 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-5
6254 00:56:59.654367 domain : lava-rack
6255 00:56:59.657705 rootserver: 192.168.201.1 rootpath:
6256 00:56:59.660862 filename :
6257 00:56:59.676942 done.
6258 00:56:59.685188 Begin: Running /scripts/nfs-bottom ... done.
6259 00:56:59.697931 Begin: Running /scripts/init-bottom ... done.
6260 00:57:01.058510 <6>[ 10.506482] NET: Registered PF_INET6 protocol family
6261 00:57:01.070091 <6>[ 10.517970] Segment Routing with IPv6
6262 00:57:01.076702 <6>[ 10.524841] In-situ OAM (IOAM) with IPv6
6263 00:57:01.261108 <30>[ 10.682298] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6264 00:57:01.281469 <30>[ 10.729075] systemd[1]: Detected architecture arm64.
6265 00:57:01.293564
6266 00:57:01.297054 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6267 00:57:01.297572
6268 00:57:01.324277 <30>[ 10.771637] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6269 00:57:02.510654 <30>[ 11.954806] systemd[1]: Queued start job for default target graphical.target.
6270 00:57:02.549870 <30>[ 11.994168] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6271 00:57:02.562945 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6272 00:57:02.582815 <30>[ 12.027094] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6273 00:57:02.596303 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6274 00:57:02.615232 <30>[ 12.059486] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6275 00:57:02.629691 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6276 00:57:02.650369 <30>[ 12.094550] systemd[1]: Created slice user.slice - User and Session Slice.
6277 00:57:02.662633 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6278 00:57:02.684256 <30>[ 12.125531] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6279 00:57:02.697793 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6280 00:57:02.720559 <30>[ 12.161365] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6281 00:57:02.733153 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6282 00:57:02.759128 <30>[ 12.193297] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6283 00:57:02.778862 <30>[ 12.222792] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6284 00:57:02.786134 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6285 00:57:02.805012 <30>[ 12.249133] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6286 00:57:02.817998 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6287 00:57:02.837154 <30>[ 12.281196] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6288 00:57:02.851250 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6289 00:57:02.865734 <30>[ 12.313218] systemd[1]: Reached target paths.target - Path Units.
6290 00:57:02.880083 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6291 00:57:02.896921 <30>[ 12.341128] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6292 00:57:02.909329 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6293 00:57:02.921542 <30>[ 12.369111] systemd[1]: Reached target slices.target - Slice Units.
6294 00:57:02.936240 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6295 00:57:02.949801 <30>[ 12.397184] systemd[1]: Reached target swap.target - Swaps.
6296 00:57:02.960091 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6297 00:57:02.981085 <30>[ 12.425205] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6298 00:57:02.994492 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6299 00:57:03.013685 <30>[ 12.457598] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6300 00:57:03.027255 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6301 00:57:03.048243 <30>[ 12.492358] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6302 00:57:03.061876 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6303 00:57:03.082757 <30>[ 12.527018] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6304 00:57:03.096578 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6305 00:57:03.113331 <30>[ 12.557849] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6306 00:57:03.125806 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6307 00:57:03.147109 <30>[ 12.590976] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6308 00:57:03.160622 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6309 00:57:03.180508 <30>[ 12.624752] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6310 00:57:03.193592 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6311 00:57:03.213466 <30>[ 12.657743] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6312 00:57:03.226469 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6313 00:57:03.268666 <30>[ 12.713322] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6314 00:57:03.280937 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6315 00:57:03.294436 <30>[ 12.738707] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6316 00:57:03.307388 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6317 00:57:03.353480 <30>[ 12.798052] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6318 00:57:03.365700 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6319 00:57:03.392290 <30>[ 12.829795] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6320 00:57:03.417197 <30>[ 12.861366] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6321 00:57:03.431007 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6322 00:57:03.477926 <30>[ 12.922238] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6323 00:57:03.490051 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6324 00:57:03.514263 <30>[ 12.958512] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6325 00:57:03.524828 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6326 00:57:03.545489 <30>[ 12.989779] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6327 00:57:03.560500 Starting [0;1;39mmodprobe@drm.service<6>[ 13.005348] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6328 00:57:03.564241 [0m - Load Kernel Module drm...
6329 00:57:03.589247 <30>[ 13.033733] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6330 00:57:03.603587 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6331 00:57:03.645917 <30>[ 13.089888] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6332 00:57:03.658911 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6333 00:57:03.682259 <30>[ 13.127130] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6334 00:57:03.694978 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6335 00:57:03.712837 <6>[ 13.160926] fuse: init (API version 7.37)
6336 00:57:03.726620 <30>[ 13.171460] systemd[1]: Starting systemd-journald.service - Journal Service...
6337 00:57:03.738283 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6338 00:57:03.785314 <30>[ 13.229810] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6339 00:57:03.797205 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6340 00:57:03.820056 <30>[ 13.261143] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6341 00:57:03.831271 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6342 00:57:03.853439 <30>[ 13.297603] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6343 00:57:03.865793 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6344 00:57:03.909584 <30>[ 13.354038] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6345 00:57:03.920547 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6346 00:57:03.931056 <3>[ 13.374547] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6347 00:57:03.945998 <3>[ 13.389857] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6348 00:57:03.952734 <30>[ 13.390414] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6349 00:57:03.964631 <3>[ 13.407202] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6350 00:57:03.978924 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - H<3>[ 13.424420] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6351 00:57:03.982243 uge Pages File System.
6352 00:57:03.995662 <3>[ 13.439529] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6353 00:57:04.003561 <30>[ 13.448838] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6354 00:57:04.013723 <3>[ 13.454643] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6355 00:57:04.028047 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSI<3>[ 13.472615] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6356 00:57:04.031040 X Message Queue File System.
6357 00:57:04.044999 <3>[ 13.488959] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6358 00:57:04.069205 <30>[ 13.513651] systemd[1]: Started systemd-journald.service - Journal Service.
6359 00:57:04.093316 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6360 00:57:04.111928 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6361 00:57:04.129977 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6362 00:57:04.151839 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6363 00:57:04.176153 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6364 00:57:04.196027 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6365 00:57:04.215588 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6366 00:57:04.235752 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6367 00:57:04.260054 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6368 00:57:04.279054 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6369 00:57:04.302884 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6370 00:57:04.322845 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6371 00:57:04.342561 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6372 00:57:04.393622 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6373 00:57:04.408561 <4>[ 13.855739] power_supply_show_property: 2 callbacks suppressed
6374 00:57:04.419771 <3>[ 13.855748] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6375 00:57:04.426240 <3>[ 13.867993] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6376 00:57:04.443470 <4>[ 13.870762] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6377 00:57:04.450535 <3>[ 13.884907] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6378 00:57:04.460313 <3>[ 13.895329] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6379 00:57:04.479892 Mounting [0;1;39msys-kernel-config…ernel Configuration File System..<3>[ 13.922677] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6380 00:57:04.480430 .
6381 00:57:04.498564 <3>[ 13.942552] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6382 00:57:04.515596 <3>[ 13.959628] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6383 00:57:04.532584 <3>[ 13.976564] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6384 00:57:04.550254 Starting [0;1;39msystemd-journal-f…h<3>[ 13.994342] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6385 00:57:04.553683 Journal to Persistent Storage...
6386 00:57:04.567090 <3>[ 14.011026] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6387 00:57:04.582909 Startin<3>[ 14.027715] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6388 00:57:04.589657 g [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6389 00:57:04.612995 <46>[ 14.057392] systemd-journald[318]: Received client request to flush runtime journal.
6390 00:57:04.638256 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6391 00:57:04.861982 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6392 00:57:05.201241 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6393 00:57:05.218828 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6394 00:57:05.238521 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6395 00:57:05.259542 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6396 00:57:05.728184 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6397 00:57:06.054995 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6398 00:57:06.075220 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6399 00:57:06.121587 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6400 00:57:06.225441 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6401 00:57:06.249203 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6402 00:57:06.272793 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6403 00:57:06.317816 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6404 00:57:06.342313 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6405 00:57:06.604882 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6406 00:57:06.660972 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6407 00:57:06.702018 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6408 00:57:06.970546 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6409 00:57:06.988470 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6410 00:57:07.033156 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6411 00:57:07.054487 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6412 00:57:07.110168 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6413 00:57:07.189757 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6414 00:57:07.222458 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6415 00:57:07.243809 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6416 00:57:07.305713 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6417 00:57:07.450183 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6418 00:57:07.471040 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6419 00:57:07.536971 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6420 00:57:07.583488 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6421 00:57:07.609454 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6422 00:57:07.632762 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6423 00:57:07.656602 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6424 00:57:07.678511 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6425 00:57:07.702339 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6426 00:57:07.722275 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6427 00:57:07.742724 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6428 00:57:07.764899 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6429 00:57:07.787759 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6430 00:57:07.812994 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6431 00:57:07.837255 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6432 00:57:07.853497 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6433 00:57:07.874549 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6434 00:57:07.900845 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6435 00:57:07.918028 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6436 00:57:07.937809 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6437 00:57:07.956682 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6438 00:57:07.973698 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6439 00:57:07.994385 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6440 00:57:08.059441 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6441 00:57:08.083242 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6442 00:57:08.118556 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6443 00:57:08.246845 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6444 00:57:08.273270 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6445 00:57:08.297171 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6446 00:57:08.314109 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6447 00:57:08.420966 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6448 00:57:08.468768 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6449 00:57:08.491349 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6450 00:57:08.508847 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6451 00:57:08.533345 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6452 00:57:08.575434 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6453 00:57:08.600050 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6454 00:57:08.622773 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6455 00:57:08.641597 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6456 00:57:08.689958 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6457 00:57:08.751431 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6458 00:57:08.850538
6459 00:57:08.853756 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6460 00:57:08.853830
6461 00:57:08.856800 debian-bookworm-arm64 login: root (automatic login)
6462 00:57:08.856876
6463 00:57:09.177210 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
6464 00:57:09.177460
6465 00:57:09.184059 The programs included with the Debian GNU/Linux system are free software;
6466 00:57:09.190993 the exact distribution terms for each program are described in the
6467 00:57:09.193850 individual files in /usr/share/doc/*/copyright.
6468 00:57:09.194258
6469 00:57:09.200566 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6470 00:57:09.204242 permitted by applicable law.
6471 00:57:10.426762 Matched prompt #10: / #
6473 00:57:10.427023 Setting prompt string to ['/ #']
6474 00:57:10.427122 end: 2.2.5.1 login-action (duration 00:00:20) [common]
6476 00:57:10.427306 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
6477 00:57:10.427388 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
6478 00:57:10.427454 Setting prompt string to ['/ #']
6479 00:57:10.427513 Forcing a shell prompt, looking for ['/ #']
6481 00:57:10.477686 / #
6482 00:57:10.477844 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6483 00:57:10.477932 Waiting using forced prompt support (timeout 00:02:30)
6484 00:57:10.482651
6485 00:57:10.482913 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6486 00:57:10.483005 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
6488 00:57:10.583342 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368556/extract-nfsrootfs-cgeyw8ut'
6489 00:57:10.588315 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368556/extract-nfsrootfs-cgeyw8ut'
6491 00:57:10.688825 / # export NFS_SERVER_IP='192.168.201.1'
6492 00:57:10.693849 export NFS_SERVER_IP='192.168.201.1'
6493 00:57:10.694130 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6494 00:57:10.694289 end: 2.2 depthcharge-retry (duration 00:01:13) [common]
6495 00:57:10.694381 end: 2 depthcharge-action (duration 00:01:13) [common]
6496 00:57:10.694469 start: 3 lava-test-retry (timeout 00:08:05) [common]
6497 00:57:10.694550 start: 3.1 lava-test-shell (timeout 00:08:05) [common]
6498 00:57:10.694617 Using namespace: common
6500 00:57:10.794973 / # #
6501 00:57:10.795171 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6502 00:57:10.799739 #
6503 00:57:10.800004 Using /lava-14368556
6505 00:57:10.900335 / # export SHELL=/bin/bash
6506 00:57:10.905467 export SHELL=/bin/bash
6508 00:57:11.005984 / # . /lava-14368556/environment
6509 00:57:11.010895 . /lava-14368556/environment
6511 00:57:11.116892 / # /lava-14368556/bin/lava-test-runner /lava-14368556/0
6512 00:57:11.117078 Test shell timeout: 10s (minimum of the action and connection timeout)
6513 00:57:11.122001 /lava-14368556/bin/lava-test-runner /lava-14368556/0
6514 00:57:11.335876 + export TESTRUN_ID=0_timesync-off
6515 00:57:11.339415 + TESTRUN_ID=0_timesync-off
6516 00:57:11.342454 + cd /lava-14368556/0/tests/0_timesync-off
6517 00:57:11.345789 ++ cat uuid
6518 00:57:11.345860 + UUID=14368556_1.6.2.3.1
6519 00:57:11.348982 + set +x
6520 00:57:11.352676 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368556_1.6.2.3.1>
6521 00:57:11.352920 Received signal: <STARTRUN> 0_timesync-off 14368556_1.6.2.3.1
6522 00:57:11.352983 Starting test lava.0_timesync-off (14368556_1.6.2.3.1)
6523 00:57:11.353064 Skipping test definition patterns.
6524 00:57:11.355859 + systemctl stop systemd-timesyncd
6525 00:57:11.408826 + set +x
6526 00:57:11.412296 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368556_1.6.2.3.1>
6527 00:57:11.412570 Received signal: <ENDRUN> 0_timesync-off 14368556_1.6.2.3.1
6528 00:57:11.412671 Ending use of test pattern.
6529 00:57:11.412737 Ending test lava.0_timesync-off (14368556_1.6.2.3.1), duration 0.06
6531 00:57:11.471998 + export TESTRUN_ID=1_kselftest-alsa
6532 00:57:11.475430 + TESTRUN_ID=1_kselftest-alsa
6533 00:57:11.481803 + cd /lava-14368556/0/tests/1_kselftest-alsa
6534 00:57:11.481879 ++ cat uuid
6535 00:57:11.485431 + UUID=14368556_1.6.2.3.5
6536 00:57:11.485497 + set +x
6537 00:57:11.488835 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14368556_1.6.2.3.5>
6538 00:57:11.489066 Received signal: <STARTRUN> 1_kselftest-alsa 14368556_1.6.2.3.5
6539 00:57:11.489126 Starting test lava.1_kselftest-alsa (14368556_1.6.2.3.5)
6540 00:57:11.489196 Skipping test definition patterns.
6541 00:57:11.492026 + cd ./automated/linux/kselftest/
6542 00:57:11.521976 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
6543 00:57:11.543341 INFO: install_deps skipped
6544 00:57:12.033871 --2024-06-16 00:57:11-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
6545 00:57:12.040435 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6546 00:57:12.159942 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6547 00:57:12.288332 HTTP request sent, awaiting response... 200 OK
6548 00:57:12.291631 Length: 1647948 (1.6M) [application/octet-stream]
6549 00:57:12.295288 Saving to: 'kselftest_armhf.tar.gz'
6550 00:57:12.295383
6551 00:57:12.295466
6552 00:57:12.548680 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6553 00:57:12.804528 kselftest_armhf.tar 2%[ ] 46.39K 179KB/s
6554 00:57:13.238202 kselftest_armhf.tar 13%[=> ] 214.67K 416KB/s
6555 00:57:13.341817 kselftest_armhf.tar 50%[=========> ] 814.23K 856KB/s
6556 00:57:13.348548 kselftest_armhf.tar 100%[===================>] 1.57M 1.49MB/s in 1.1s
6557 00:57:13.349115
6558 00:57:13.492894 2024-06-16 00:57:13 (1.49 MB/s) - 'kselftest_armhf.tar.gz' saved [1647948/1647948]
6559 00:57:13.493021
6560 00:57:18.114080 skiplist:
6561 00:57:18.117196 ========================================
6562 00:57:18.120419 ========================================
6563 00:57:18.164669 alsa:mixer-test
6564 00:57:18.184166 ============== Tests to run ===============
6565 00:57:18.184253 alsa:mixer-test
6566 00:57:18.187727 ===========End Tests to run ===============
6567 00:57:18.190787 shardfile-alsa pass
6568 00:57:18.290574 <12>[ 27.738524] kselftest: Running tests in alsa
6569 00:57:18.300553 TAP version 13
6570 00:57:18.314982 1..1
6571 00:57:18.330931 # selftests: alsa: mixer-test
6572 00:57:18.436860 <6>[ 27.878090] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6573 00:57:18.450324 <6>[ 27.890385] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6574 00:57:18.460443 <6>[ 27.902563] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 1
6575 00:57:18.473430 <6>[ 27.914724] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6576 00:57:18.486975 <6>[ 27.926873] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6577 00:57:18.496580 <6>[ 27.939022] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6578 00:57:18.509922 <6>[ 27.950379] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6579 00:57:18.520110 <6>[ 27.961726] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 1
6580 00:57:18.530079 <6>[ 27.973063] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6581 00:57:18.543149 <6>[ 27.984400] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6582 00:57:18.553561 <6>[ 27.995735] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6583 00:57:18.566611 <6>[ 28.007066] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6584 00:57:18.576571 <6>[ 28.018397] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 1
6585 00:57:18.586467 <6>[ 28.029726] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6586 00:57:18.599807 <6>[ 28.041061] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6587 00:57:18.609878 <6>[ 28.052400] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6588 00:57:18.623167 <6>[ 28.063732] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6589 00:57:18.633072 <6>[ 28.075064] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 1
6590 00:57:18.646565 <6>[ 28.086401] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6591 00:57:18.656471 <6>[ 28.097737] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6592 00:57:18.666339 <6>[ 28.109088] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6593 00:57:18.679734 <6>[ 28.120418] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6594 00:57:18.689700 <6>[ 28.131747] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 1
6595 00:57:18.702789 <6>[ 28.143075] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6596 00:57:18.712816 <6>[ 28.154410] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6597 00:57:18.722636 <6>[ 28.165763] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6598 00:57:18.736012 <6>[ 28.177092] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6599 00:57:18.746176 <6>[ 28.188421] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 1
6600 00:57:18.759582 <6>[ 28.199756] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6601 00:57:18.769489 <6>[ 28.211093] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6602 00:57:18.772767 # TAP version 13
6603 00:57:18.772832 # 1..658
6604 00:57:18.776396 # ok 1 get_value.0.93
6605 00:57:18.776460 # ok 2 name.0.93
6606 00:57:18.779471 # ok 3 write_default.0.93
6607 00:57:18.779533 # ok 4 write_valid.0.93
6608 00:57:18.782761 # ok 5 write_invalid.0.93
6609 00:57:18.786159 # ok 6 event_missing.0.93
6610 00:57:18.789419 # ok 7 event_spurious.0.93
6611 00:57:18.789494 # ok 8 get_value.0.92
6612 00:57:18.792602 # ok 9 name.0.92
6613 00:57:18.792668 # ok 10 write_default.0.92
6614 00:57:18.796016 # ok 11 write_valid.0.92
6615 00:57:18.799143 # ok 12 write_invalid.0.92
6616 00:57:18.802653 # ok 13 event_missing.0.92
6617 00:57:18.802715 # ok 14 event_spurious.0.92
6618 00:57:18.805758 # ok 15 get_value.0.91
6619 00:57:18.809272 # ok 16 name.0.91
6620 00:57:18.809365 # ok 17 write_default.0.91
6621 00:57:18.812628 # ok 18 write_valid.0.91
6622 00:57:18.816047 # ok 19 write_invalid.0.91
6623 00:57:18.816116 # ok 20 event_missing.0.91
6624 00:57:18.819147 # ok 21 event_spurious.0.91
6625 00:57:18.822419 # ok 22 get_value.0.90
6626 00:57:18.822488 # ok 23 name.0.90
6627 00:57:18.826194 # ok 24 write_default.0.90
6628 00:57:18.829354 # ok 25 write_valid.0.90
6629 00:57:18.829416 # ok 26 write_invalid.0.90
6630 00:57:18.832381 # ok 27 event_missing.0.90
6631 00:57:18.835642 # ok 28 event_spurious.0.90
6632 00:57:18.839093 # ok 29 get_value.0.89
6633 00:57:18.839161 # ok 30 name.0.89
6634 00:57:18.842404 # ok 31 write_default.0.89
6635 00:57:18.845554 # ok 32 write_valid.0.89
6636 00:57:18.845623 # ok 33 write_invalid.0.89
6637 00:57:18.848835 # ok 34 event_missing.0.89
6638 00:57:18.852452 # ok 35 event_spurious.0.89
6639 00:57:18.852516 # ok 36 get_value.0.88
6640 00:57:18.855579 # ok 37 name.0.88
6641 00:57:18.858932 # ok 38 write_default.0.88
6642 00:57:18.862504 # # Spurious event generated for AIF Out Mux
6643 00:57:18.865557 # # AIF Out Mux.0 expected 1 but read 0, is_volatile 0
6644 00:57:18.868935 # # Spurious event generated for AIF Out Mux
6645 00:57:18.872429 # not ok 39 write_valid.0.88
6646 00:57:18.875472 # ok 40 write_invalid.0.88
6647 00:57:18.878834 # ok 41 event_missing.0.88
6648 00:57:18.882368 # not ok 42 event_spurious.0.88
6649 00:57:18.882428 # ok 43 get_value.0.87
6650 00:57:18.885425 # ok 44 name.0.87
6651 00:57:18.888786 # ok 45 write_default.0.87
6652 00:57:18.888844 # ok 46 write_valid.0.87
6653 00:57:18.892158 # ok 47 write_invalid.0.87
6654 00:57:18.895878 # ok 48 event_missing.0.87
6655 00:57:18.898966 # ok 49 event_spurious.0.87
6656 00:57:18.899024 # ok 50 get_value.0.86
6657 00:57:18.902144 # ok 51 name.0.86
6658 00:57:18.905493 # ok 52 write_default.0.86
6659 00:57:18.908923 # # HPR Mux.0 expected 5 but read 0, is_volatile 0
6660 00:57:18.915422 # # HPR Mux.0 expected 6 but read 0, is_volatile 0
6661 00:57:18.919092 # # HPR Mux.0 expected 7 but read 0, is_volatile 0
6662 00:57:18.922118 # not ok 53 write_valid.0.86
6663 00:57:18.925381 # ok 54 write_invalid.0.86
6664 00:57:18.925461 # ok 55 event_missing.0.86
6665 00:57:18.928680 # ok 56 event_spurious.0.86
6666 00:57:18.932079 # ok 57 get_value.0.85
6667 00:57:18.932159 # ok 58 name.0.85
6668 00:57:18.935409 # ok 59 write_default.0.85
6669 00:57:18.938717 # # HPL Mux.0 expected 5 but read 0, is_volatile 0
6670 00:57:18.945519 # # HPL Mux.0 expected 6 but read 0, is_volatile 0
6671 00:57:18.949067 # # HPL Mux.0 expected 7 but read 0, is_volatile 0
6672 00:57:18.952093 # not ok 60 write_valid.0.85
6673 00:57:18.955404 # ok 61 write_invalid.0.85
6674 00:57:18.958731 # ok 62 event_missing.0.85
6675 00:57:18.958826 # ok 63 event_spurious.0.85
6676 00:57:18.961828 # ok 64 get_value.0.84
6677 00:57:18.965169 # ok 65 name.0.84
6678 00:57:18.965270 # ok 66 write_default.0.84
6679 00:57:18.968466 # ok 67 write_valid.0.84
6680 00:57:18.971756 # ok 68 write_invalid.0.84
6681 00:57:18.975006 # ok 69 event_missing.0.84
6682 00:57:18.975082 # ok 70 event_spurious.0.84
6683 00:57:18.978408 # ok 71 get_value.0.83
6684 00:57:18.981605 # ok 72 name.0.83
6685 00:57:18.981694 # ok 73 write_default.0.83
6686 00:57:18.985177 # ok 74 write_valid.0.83
6687 00:57:18.988567 # ok 75 write_invalid.0.83
6688 00:57:18.988693 # ok 76 event_missing.0.83
6689 00:57:18.991883 # ok 77 event_spurious.0.83
6690 00:57:18.995055 # ok 78 get_value.0.82
6691 00:57:18.995158 # ok 79 name.0.82
6692 00:57:18.998270 # # Headset Jack is not writeable
6693 00:57:19.001675 # ok 80 # SKIP write_default.0.82
6694 00:57:19.004905 # # Headset Jack is not writeable
6695 00:57:19.008435 # ok 81 # SKIP write_valid.0.82
6696 00:57:19.011976 # # Headset Jack is not writeable
6697 00:57:19.015015 # ok 82 # SKIP write_invalid.0.82
6698 00:57:19.018700 # ok 83 event_missing.0.82
6699 00:57:19.022034 # ok 84 event_spurious.0.82
6700 00:57:19.022603 # ok 85 get_value.0.81
6701 00:57:19.025239 # ok 86 name.0.81
6702 00:57:19.025631 # ok 87 write_default.0.81
6703 00:57:19.031810 # # No event generated for Wake-on-Voice Phase2 Switch
6704 00:57:19.035449 # # No event generated for Wake-on-Voice Phase2 Switch
6705 00:57:19.038566 # ok 88 write_valid.0.81
6706 00:57:19.045288 # # Wake-on-Voice Phase2 Switch.0 Invalid boolean value 2
6707 00:57:19.048491 # # No event generated for Wake-on-Voice Phase2 Switch
6708 00:57:19.051870 # not ok 89 write_invalid.0.81
6709 00:57:19.055504 # not ok 90 event_missing.0.81
6710 00:57:19.058694 # ok 91 event_spurious.0.81
6711 00:57:19.059088 # ok 92 get_value.0.80
6712 00:57:19.061953 # ok 93 name.0.80
6713 00:57:19.062405 # ok 94 write_default.0.80
6714 00:57:19.065386 # ok 95 write_valid.0.80
6715 00:57:19.068497 # ok 96 write_invalid.0.80
6716 00:57:19.071946 # ok 97 event_missing.0.80
6717 00:57:19.072360 # ok 98 event_spurious.0.80
6718 00:57:19.078399 # # Handset Volume.0 value -13 less than minimum 0
6719 00:57:19.078842 # not ok 99 get_value.0.79
6720 00:57:19.081653 # ok 100 name.0.79
6721 00:57:19.085163 # # snd_ctl_elem_write() failed: Invalid argument
6722 00:57:19.088580 # not ok 101 write_default.0.79
6723 00:57:19.091996 # # snd_ctl_elem_write() failed: Invalid argument
6724 00:57:19.095226 # not ok 102 write_valid.0.79
6725 00:57:19.101732 # # snd_ctl_elem_write() failed: Invalid argument
6726 00:57:19.102169 # not ok 103 write_invalid.0.79
6727 00:57:19.105063 # ok 104 event_missing.0.79
6728 00:57:19.108434 # ok 105 event_spurious.0.79
6729 00:57:19.111819 # # Lineout Volume.0 value -13 less than minimum 0
6730 00:57:19.118337 # # Lineout Volume.1 value -13 less than minimum 0
6731 00:57:19.118738 # not ok 106 get_value.0.78
6732 00:57:19.121739 # ok 107 name.0.78
6733 00:57:19.125172 # # snd_ctl_elem_write() failed: Invalid argument
6734 00:57:19.128429 # not ok 108 write_default.0.78
6735 00:57:19.135091 # # snd_ctl_elem_write() failed: Invalid argument
6736 00:57:19.135480 # not ok 109 write_valid.0.78
6737 00:57:19.141867 # # snd_ctl_elem_write() failed: Invalid argument
6738 00:57:19.144754 # not ok 110 write_invalid.0.78
6739 00:57:19.145140 # ok 111 event_missing.0.78
6740 00:57:19.148172 # ok 112 event_spurious.0.78
6741 00:57:19.154770 # # Headphone Volume.0 value -13 less than minimum 0
6742 00:57:19.158131 # # Headphone Volume.1 value -13 less than minimum 0
6743 00:57:19.161185 # not ok 113 get_value.0.77
6744 00:57:19.161762 # ok 114 name.0.77
6745 00:57:19.168202 # # snd_ctl_elem_write() failed: Invalid argument
6746 00:57:19.168634 # not ok 115 write_default.0.77
6747 00:57:19.174429 # # snd_ctl_elem_write() failed: Invalid argument
6748 00:57:19.177817 # not ok 116 write_valid.0.77
6749 00:57:19.181065 # # snd_ctl_elem_write() failed: Invalid argument
6750 00:57:19.184185 # not ok 117 write_invalid.0.77
6751 00:57:19.187679 # ok 118 event_missing.0.77
6752 00:57:19.187778 # ok 119 event_spurious.0.77
6753 00:57:19.190855 # ok 120 get_value.0.76
6754 00:57:19.197609 # # 0.76 ADDA_DL_CH2 PCM_2_CAP_CH2 is a writeable boolean but not a Switch
6755 00:57:19.201111 # not ok 121 name.0.76
6756 00:57:19.201187 # ok 122 write_default.0.76
6757 00:57:19.204695 # ok 123 write_valid.0.76
6758 00:57:19.207548 # ok 124 write_invalid.0.76
6759 00:57:19.210775 # ok 125 event_missing.0.76
6760 00:57:19.210852 # ok 126 event_spurious.0.76
6761 00:57:19.214165 # ok 127 get_value.0.75
6762 00:57:19.221007 # # 0.75 ADDA_DL_CH2 PCM_1_CAP_CH2 is a writeable boolean but not a Switch
6763 00:57:19.224268 # not ok 128 name.0.75
6764 00:57:19.224345 # ok 129 write_default.0.75
6765 00:57:19.227669 # ok 130 write_valid.0.75
6766 00:57:19.230858 # ok 131 write_invalid.0.75
6767 00:57:19.234097 # ok 132 event_missing.0.75
6768 00:57:19.234197 # ok 133 event_spurious.0.75
6769 00:57:19.237210 # ok 134 get_value.0.74
6770 00:57:19.243988 # # 0.74 ADDA_DL_CH2 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6771 00:57:19.247256 # not ok 135 name.0.74
6772 00:57:19.247332 # ok 136 write_default.0.74
6773 00:57:19.250783 # ok 137 write_valid.0.74
6774 00:57:19.254038 # ok 138 write_invalid.0.74
6775 00:57:19.257314 # ok 139 event_missing.0.74
6776 00:57:19.257389 # ok 140 event_spurious.0.74
6777 00:57:19.260632 # ok 141 get_value.0.73
6778 00:57:19.267332 # # 0.73 ADDA_DL_CH2 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6779 00:57:19.270498 # not ok 142 name.0.73
6780 00:57:19.270574 # ok 143 write_default.0.73
6781 00:57:19.273851 # ok 144 write_valid.0.73
6782 00:57:19.277626 # ok 145 write_invalid.0.73
6783 00:57:19.280811 # ok 146 event_missing.0.73
6784 00:57:19.280882 # ok 147 event_spurious.0.73
6785 00:57:19.283867 # ok 148 get_value.0.72
6786 00:57:19.290526 # # 0.72 ADDA_DL_CH2 ADDA_UL_CH1 is a writeable boolean but not a Switch
6787 00:57:19.293843 # not ok 149 name.0.72
6788 00:57:19.293910 # ok 150 write_default.0.72
6789 00:57:19.297338 # ok 151 write_valid.0.72
6790 00:57:19.300591 # ok 152 write_invalid.0.72
6791 00:57:19.304133 # ok 153 event_missing.0.72
6792 00:57:19.304199 # ok 154 event_spurious.0.72
6793 00:57:19.307466 # ok 155 get_value.0.71
6794 00:57:19.313910 # # 0.71 ADDA_DL_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6795 00:57:19.317022 # not ok 156 name.0.71
6796 00:57:19.317110 # ok 157 write_default.0.71
6797 00:57:19.320337 # ok 158 write_valid.0.71
6798 00:57:19.323664 # ok 159 write_invalid.0.71
6799 00:57:19.326980 # ok 160 event_missing.0.71
6800 00:57:19.330375 # ok 161 event_spurious.0.71
6801 00:57:19.330479 # ok 162 get_value.0.70
6802 00:57:19.337195 # # 0.70 ADDA_DL_CH2 DL3_CH2 is a writeable boolean but not a Switch
6803 00:57:19.340581 # not ok 163 name.0.70
6804 00:57:19.343870 # ok 164 write_default.0.70
6805 00:57:19.344011 # ok 165 write_valid.0.70
6806 00:57:19.346978 # ok 166 write_invalid.0.70
6807 00:57:19.350413 # ok 167 event_missing.0.70
6808 00:57:19.353899 # ok 168 event_spurious.0.70
6809 00:57:19.354085 # ok 169 get_value.0.69
6810 00:57:19.360036 # # 0.69 ADDA_DL_CH2 DL3_CH1 is a writeable boolean but not a Switch
6811 00:57:19.363687 # not ok 170 name.0.69
6812 00:57:19.367128 # ok 171 write_default.0.69
6813 00:57:19.367204 # ok 172 write_valid.0.69
6814 00:57:19.370156 # ok 173 write_invalid.0.69
6815 00:57:19.373625 # ok 174 event_missing.0.69
6816 00:57:19.376842 # ok 175 event_spurious.0.69
6817 00:57:19.380193 # ok 176 get_value.0.68
6818 00:57:19.384125 # # 0.68 ADDA_DL_CH2 DL2_CH2 is a writeable boolean but not a Switch
6819 00:57:19.387366 # not ok 177 name.0.68
6820 00:57:19.390392 # ok 178 write_default.0.68
6821 00:57:19.394091 # ok 179 write_valid.0.68
6822 00:57:19.394632 # ok 180 write_invalid.0.68
6823 00:57:19.397319 # ok 181 event_missing.0.68
6824 00:57:19.400681 # ok 182 event_spurious.0.68
6825 00:57:19.404019 # ok 183 get_value.0.67
6826 00:57:19.410777 # # 0.67 ADDA_DL_CH2 DL2_CH1 is a writeable boolean but not a Switch
6827 00:57:19.411213 # not ok 184 name.0.67
6828 00:57:19.414014 # ok 185 write_default.0.67
6829 00:57:19.417464 # ok 186 write_valid.0.67
6830 00:57:19.417993 # ok 187 write_invalid.0.67
6831 00:57:19.420506 # ok 188 event_missing.0.67
6832 00:57:19.423690 # ok 189 event_spurious.0.67
6833 00:57:19.427068 # ok 190 get_value.0.66
6834 00:57:19.433592 # # 0.66 ADDA_DL_CH2 DL1_CH2 is a writeable boolean but not a Switch
6835 00:57:19.434112 # not ok 191 name.0.66
6836 00:57:19.437058 # ok 192 write_default.0.66
6837 00:57:19.440032 # ok 193 write_valid.0.66
6838 00:57:19.443545 # ok 194 write_invalid.0.66
6839 00:57:19.444023 # ok 195 event_missing.0.66
6840 00:57:19.446733 # ok 196 event_spurious.0.66
6841 00:57:19.450427 # ok 197 get_value.0.65
6842 00:57:19.456938 # # 0.65 ADDA_DL_CH2 DL1_CH1 is a writeable boolean but not a Switch
6843 00:57:19.457387 # not ok 198 name.0.65
6844 00:57:19.460097 # ok 199 write_default.0.65
6845 00:57:19.463482 # ok 200 write_valid.0.65
6846 00:57:19.467005 # ok 201 write_invalid.0.65
6847 00:57:19.470231 # ok 202 event_missing.0.65
6848 00:57:19.470635 # ok 203 event_spurious.0.65
6849 00:57:19.473459 # ok 204 get_value.0.64
6850 00:57:19.480031 # # 0.64 ADDA_DL_CH1 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6851 00:57:19.483184 # not ok 205 name.0.64
6852 00:57:19.486529 # ok 206 write_default.0.64
6853 00:57:19.486906 # ok 207 write_valid.0.64
6854 00:57:19.489888 # ok 208 write_invalid.0.64
6855 00:57:19.493341 # ok 209 event_missing.0.64
6856 00:57:19.496859 # ok 210 event_spurious.0.64
6857 00:57:19.497263 # ok 211 get_value.0.63
6858 00:57:19.503011 # # 0.63 ADDA_DL_CH1 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6859 00:57:19.506305 # not ok 212 name.0.63
6860 00:57:19.509793 # ok 213 write_default.0.63
6861 00:57:19.512958 # ok 214 write_valid.0.63
6862 00:57:19.513465 # ok 215 write_invalid.0.63
6863 00:57:19.516354 # ok 216 event_missing.0.63
6864 00:57:19.519717 # ok 217 event_spurious.0.63
6865 00:57:19.523228 # ok 218 get_value.0.62
6866 00:57:19.529871 # # 0.62 ADDA_DL_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
6867 00:57:19.530312 # not ok 219 name.0.62
6868 00:57:19.532958 # ok 220 write_default.0.62
6869 00:57:19.536247 # ok 221 write_valid.0.62
6870 00:57:19.539821 # ok 222 write_invalid.0.62
6871 00:57:19.540211 # ok 223 event_missing.0.62
6872 00:57:19.543024 # ok 224 event_spurious.0.62
6873 00:57:19.546207 # ok 225 get_value.0.61
6874 00:57:19.552980 # # 0.61 ADDA_DL_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
6875 00:57:19.553569 # not ok 226 name.0.61
6876 00:57:19.556331 # ok 227 write_default.0.61
6877 00:57:19.559476 # ok 228 write_valid.0.61
6878 00:57:19.562966 # ok 229 write_invalid.0.61
6879 00:57:19.566382 # ok 230 event_missing.0.61
6880 00:57:19.567012 # ok 231 event_spurious.0.61
6881 00:57:19.569433 # ok 232 get_value.0.60
6882 00:57:19.576293 # # 0.60 ADDA_DL_CH1 DL3_CH1 is a writeable boolean but not a Switch
6883 00:57:19.579328 # not ok 233 name.0.60
6884 00:57:19.579773 # ok 234 write_default.0.60
6885 00:57:19.582926 # ok 235 write_valid.0.60
6886 00:57:19.586252 # ok 236 write_invalid.0.60
6887 00:57:19.589671 # ok 237 event_missing.0.60
6888 00:57:19.592795 # ok 238 event_spurious.0.60
6889 00:57:19.593135 # ok 239 get_value.0.59
6890 00:57:19.599528 # # 0.59 ADDA_DL_CH1 DL2_CH1 is a writeable boolean but not a Switch
6891 00:57:19.602854 # not ok 240 name.0.59
6892 00:57:19.606239 # ok 241 write_default.0.59
6893 00:57:19.606611 # ok 242 write_valid.0.59
6894 00:57:19.609726 # ok 243 write_invalid.0.59
6895 00:57:19.612826 # ok 244 event_missing.0.59
6896 00:57:19.616414 # ok 245 event_spurious.0.59
6897 00:57:19.616660 # ok 246 get_value.0.58
6898 00:57:19.622805 # # 0.58 ADDA_DL_CH1 DL1_CH1 is a writeable boolean but not a Switch
6899 00:57:19.626035 # not ok 247 name.0.58
6900 00:57:19.629315 # ok 248 write_default.0.58
6901 00:57:19.629597 # ok 249 write_valid.0.58
6902 00:57:19.632782 # ok 250 write_invalid.0.58
6903 00:57:19.636441 # ok 251 event_missing.0.58
6904 00:57:19.639235 # ok 252 event_spurious.0.58
6905 00:57:19.639515 # ok 253 get_value.0.57
6906 00:57:19.645798 # # 0.57 I2S5_CH2 DL3_CH2 is a writeable boolean but not a Switch
6907 00:57:19.649233 # not ok 254 name.0.57
6908 00:57:19.652461 # ok 255 write_default.0.57
6909 00:57:19.652862 # ok 256 write_valid.0.57
6910 00:57:19.656038 # ok 257 write_invalid.0.57
6911 00:57:19.659288 # ok 258 event_missing.0.57
6912 00:57:19.662587 # ok 259 event_spurious.0.57
6913 00:57:19.663020 # ok 260 get_value.0.56
6914 00:57:19.669177 # # 0.56 I2S5_CH2 DL2_CH2 is a writeable boolean but not a Switch
6915 00:57:19.672781 # not ok 261 name.0.56
6916 00:57:19.675761 # ok 262 write_default.0.56
6917 00:57:19.676082 # ok 263 write_valid.0.56
6918 00:57:19.679209 # ok 264 write_invalid.0.56
6919 00:57:19.682568 # ok 265 event_missing.0.56
6920 00:57:19.685786 # ok 266 event_spurious.0.56
6921 00:57:19.686287 # ok 267 get_value.0.55
6922 00:57:19.692391 # # 0.55 I2S5_CH2 DL1_CH2 is a writeable boolean but not a Switch
6923 00:57:19.695669 # not ok 268 name.0.55
6924 00:57:19.699159 # ok 269 write_default.0.55
6925 00:57:19.699391 # ok 270 write_valid.0.55
6926 00:57:19.702471 # ok 271 write_invalid.0.55
6927 00:57:19.705752 # ok 272 event_missing.0.55
6928 00:57:19.708877 # ok 273 event_spurious.0.55
6929 00:57:19.712174 # ok 274 get_value.0.54
6930 00:57:19.716116 # # 0.54 I2S5_CH1 DL3_CH1 is a writeable boolean but not a Switch
6931 00:57:19.718927 # not ok 275 name.0.54
6932 00:57:19.722316 # ok 276 write_default.0.54
6933 00:57:19.722525 # ok 277 write_valid.0.54
6934 00:57:19.725755 # ok 278 write_invalid.0.54
6935 00:57:19.728753 # ok 279 event_missing.0.54
6936 00:57:19.732070 # ok 280 event_spurious.0.54
6937 00:57:19.735549 # ok 281 get_value.0.53
6938 00:57:19.738858 # # 0.53 I2S5_CH1 DL2_CH1 is a writeable boolean but not a Switch
6939 00:57:19.741904 # not ok 282 name.0.53
6940 00:57:19.745302 # ok 283 write_default.0.53
6941 00:57:19.748553 # ok 284 write_valid.0.53
6942 00:57:19.748663 # ok 285 write_invalid.0.53
6943 00:57:19.751813 # ok 286 event_missing.0.53
6944 00:57:19.755182 # ok 287 event_spurious.0.53
6945 00:57:19.758833 # ok 288 get_value.0.52
6946 00:57:19.761748 # # 0.52 I2S5_CH1 DL1_CH1 is a writeable boolean but not a Switch
6947 00:57:19.765439 # not ok 289 name.0.52
6948 00:57:19.768486 # ok 290 write_default.0.52
6949 00:57:19.771748 # ok 291 write_valid.0.52
6950 00:57:19.771847 # ok 292 write_invalid.0.52
6951 00:57:19.775513 # ok 293 event_missing.0.52
6952 00:57:19.778700 # ok 294 event_spurious.0.52
6953 00:57:19.781726 # ok 295 get_value.0.51
6954 00:57:19.785315 # # 0.51 I2S3_CH2 DL3_CH2 is a writeable boolean but not a Switch
6955 00:57:19.788486 # not ok 296 name.0.51
6956 00:57:19.791845 # ok 297 write_default.0.51
6957 00:57:19.795175 # ok 298 write_valid.0.51
6958 00:57:19.795253 # ok 299 write_invalid.0.51
6959 00:57:19.798448 # ok 300 event_missing.0.51
6960 00:57:19.801857 # ok 301 event_spurious.0.51
6961 00:57:19.804956 # ok 302 get_value.0.50
6962 00:57:19.808490 # # 0.50 I2S3_CH2 DL2_CH2 is a writeable boolean but not a Switch
6963 00:57:19.811785 # not ok 303 name.0.50
6964 00:57:19.815102 # ok 304 write_default.0.50
6965 00:57:19.815179 # ok 305 write_valid.0.50
6966 00:57:19.818536 # ok 306 write_invalid.0.50
6967 00:57:19.821749 # ok 307 event_missing.0.50
6968 00:57:19.825157 # ok 308 event_spurious.0.50
6969 00:57:19.825234 # ok 309 get_value.0.49
6970 00:57:19.831685 # # 0.49 I2S3_CH2 DL1_CH2 is a writeable boolean but not a Switch
6971 00:57:19.835134 # not ok 310 name.0.49
6972 00:57:19.838254 # ok 311 write_default.0.49
6973 00:57:19.838331 # ok 312 write_valid.0.49
6974 00:57:19.841707 # ok 313 write_invalid.0.49
6975 00:57:19.844935 # ok 314 event_missing.0.49
6976 00:57:19.848290 # ok 315 event_spurious.0.49
6977 00:57:19.848368 # ok 316 get_value.0.48
6978 00:57:19.854907 # # 0.48 I2S3_CH1 DL3_CH1 is a writeable boolean but not a Switch
6979 00:57:19.858522 # not ok 317 name.0.48
6980 00:57:19.861964 # ok 318 write_default.0.48
6981 00:57:19.862393 # ok 319 write_valid.0.48
6982 00:57:19.865241 # ok 320 write_invalid.0.48
6983 00:57:19.868596 # ok 321 event_missing.0.48
6984 00:57:19.872071 # ok 322 event_spurious.0.48
6985 00:57:19.872463 # ok 323 get_value.0.47
6986 00:57:19.878403 # # 0.47 I2S3_CH1 DL2_CH1 is a writeable boolean but not a Switch
6987 00:57:19.881808 # not ok 324 name.0.47
6988 00:57:19.885100 # ok 325 write_default.0.47
6989 00:57:19.885176 # ok 326 write_valid.0.47
6990 00:57:19.888151 # ok 327 write_invalid.0.47
6991 00:57:19.891754 # ok 328 event_missing.0.47
6992 00:57:19.894928 # ok 329 event_spurious.0.47
6993 00:57:19.898159 # ok 330 get_value.0.46
6994 00:57:19.901498 # # 0.46 I2S3_CH1 DL1_CH1 is a writeable boolean but not a Switch
6995 00:57:19.904967 # not ok 331 name.0.46
6996 00:57:19.908122 # ok 332 write_default.0.46
6997 00:57:19.911642 # ok 333 write_valid.0.46
6998 00:57:19.911719 # ok 334 write_invalid.0.46
6999 00:57:19.914786 # ok 335 event_missing.0.46
7000 00:57:19.918535 # ok 336 event_spurious.0.46
7001 00:57:19.921406 # ok 337 get_value.0.45
7002 00:57:19.924873 # # 0.45 I2S1_CH2 DL3_CH2 is a writeable boolean but not a Switch
7003 00:57:19.928087 # not ok 338 name.0.45
7004 00:57:19.931580 # ok 339 write_default.0.45
7005 00:57:19.934754 # ok 340 write_valid.0.45
7006 00:57:19.934855 # ok 341 write_invalid.0.45
7007 00:57:19.938055 # ok 342 event_missing.0.45
7008 00:57:19.941515 # ok 343 event_spurious.0.45
7009 00:57:19.944754 # ok 344 get_value.0.44
7010 00:57:19.948184 # # 0.44 I2S1_CH2 DL2_CH2 is a writeable boolean but not a Switch
7011 00:57:19.951623 # not ok 345 name.0.44
7012 00:57:19.954761 # ok 346 write_default.0.44
7013 00:57:19.954838 # ok 347 write_valid.0.44
7014 00:57:19.958150 # ok 348 write_invalid.0.44
7015 00:57:19.961426 # ok 349 event_missing.0.44
7016 00:57:19.964998 # ok 350 event_spurious.0.44
7017 00:57:19.965075 # ok 351 get_value.0.43
7018 00:57:19.971425 # # 0.43 I2S1_CH2 DL1_CH2 is a writeable boolean but not a Switch
7019 00:57:19.974694 # not ok 352 name.0.43
7020 00:57:19.974774 # ok 353 write_default.0.43
7021 00:57:19.977911 # ok 354 write_valid.0.43
7022 00:57:19.981225 # ok 355 write_invalid.0.43
7023 00:57:19.984754 # ok 356 event_missing.0.43
7024 00:57:19.984834 # ok 357 event_spurious.0.43
7025 00:57:19.987877 # ok 358 get_value.0.42
7026 00:57:19.994470 # # 0.42 I2S1_CH1 DL3_CH1 is a writeable boolean but not a Switch
7027 00:57:19.994547 # not ok 359 name.0.42
7028 00:57:19.997791 # ok 360 write_default.0.42
7029 00:57:20.001515 # ok 361 write_valid.0.42
7030 00:57:20.004600 # ok 362 write_invalid.0.42
7031 00:57:20.004677 # ok 363 event_missing.0.42
7032 00:57:20.007811 # ok 364 event_spurious.0.42
7033 00:57:20.011091 # ok 365 get_value.0.41
7034 00:57:20.017690 # # 0.41 I2S1_CH1 DL2_CH1 is a writeable boolean but not a Switch
7035 00:57:20.017767 # not ok 366 name.0.41
7036 00:57:20.021108 # ok 367 write_default.0.41
7037 00:57:20.024827 # ok 368 write_valid.0.41
7038 00:57:20.027842 # ok 369 write_invalid.0.41
7039 00:57:20.027930 # ok 370 event_missing.0.41
7040 00:57:20.031123 # ok 371 event_spurious.0.41
7041 00:57:20.034674 # ok 372 get_value.0.40
7042 00:57:20.041437 # # 0.40 I2S1_CH1 DL1_CH1 is a writeable boolean but not a Switch
7043 00:57:20.041553 # not ok 373 name.0.40
7044 00:57:20.044367 # ok 374 write_default.0.40
7045 00:57:20.047669 # ok 375 write_valid.0.40
7046 00:57:20.051199 # ok 376 write_invalid.0.40
7047 00:57:20.051342 # ok 377 event_missing.0.40
7048 00:57:20.054400 # ok 378 event_spurious.0.40
7049 00:57:20.057860 # ok 379 get_value.0.39
7050 00:57:20.064480 # # 0.39 PCM_2_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7051 00:57:20.064681 # not ok 380 name.0.39
7052 00:57:20.067900 # ok 381 write_default.0.39
7053 00:57:20.071219 # ok 382 write_valid.0.39
7054 00:57:20.074746 # ok 383 write_invalid.0.39
7055 00:57:20.077995 # ok 384 event_missing.0.39
7056 00:57:20.078419 # ok 385 event_spurious.0.39
7057 00:57:20.081328 # ok 386 get_value.0.38
7058 00:57:20.087880 # # 0.38 PCM_2_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7059 00:57:20.091170 # not ok 387 name.0.38
7060 00:57:20.091565 # ok 388 write_default.0.38
7061 00:57:20.094681 # ok 389 write_valid.0.38
7062 00:57:20.097632 # ok 390 write_invalid.0.38
7063 00:57:20.101357 # ok 391 event_missing.0.38
7064 00:57:20.104584 # ok 392 event_spurious.0.38
7065 00:57:20.104983 # ok 393 get_value.0.37
7066 00:57:20.111247 # # 0.37 PCM_2_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7067 00:57:20.114331 # not ok 394 name.0.37
7068 00:57:20.117806 # ok 395 write_default.0.37
7069 00:57:20.118264 # ok 396 write_valid.0.37
7070 00:57:20.120904 # ok 397 write_invalid.0.37
7071 00:57:20.124498 # ok 398 event_missing.0.37
7072 00:57:20.127873 # ok 399 event_spurious.0.37
7073 00:57:20.128269 # ok 400 get_value.0.36
7074 00:57:20.134706 # # 0.36 PCM_2_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7075 00:57:20.137726 # not ok 401 name.0.36
7076 00:57:20.140827 # ok 402 write_default.0.36
7077 00:57:20.144434 # ok 403 write_valid.0.36
7078 00:57:20.144842 # ok 404 write_invalid.0.36
7079 00:57:20.147698 # ok 405 event_missing.0.36
7080 00:57:20.150529 # ok 406 event_spurious.0.36
7081 00:57:20.154183 # ok 407 get_value.0.35
7082 00:57:20.160533 # # 0.35 PCM_2_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7083 00:57:20.160672 # not ok 408 name.0.35
7084 00:57:20.164182 # ok 409 write_default.0.35
7085 00:57:20.167325 # ok 410 write_valid.0.35
7086 00:57:20.170641 # ok 411 write_invalid.0.35
7087 00:57:20.170737 # ok 412 event_missing.0.35
7088 00:57:20.174091 # ok 413 event_spurious.0.35
7089 00:57:20.177288 # ok 414 get_value.0.34
7090 00:57:20.183795 # # 0.34 PCM_1_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7091 00:57:20.183923 # not ok 415 name.0.34
7092 00:57:20.187024 # ok 416 write_default.0.34
7093 00:57:20.190453 # ok 417 write_valid.0.34
7094 00:57:20.193737 # ok 418 write_invalid.0.34
7095 00:57:20.197033 # ok 419 event_missing.0.34
7096 00:57:20.197110 # ok 420 event_spurious.0.34
7097 00:57:20.200466 # ok 421 get_value.0.33
7098 00:57:20.207096 # # 0.33 PCM_1_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7099 00:57:20.210313 # not ok 422 name.0.33
7100 00:57:20.210391 # ok 423 write_default.0.33
7101 00:57:20.213873 # ok 424 write_valid.0.33
7102 00:57:20.216936 # ok 425 write_invalid.0.33
7103 00:57:20.220227 # ok 426 event_missing.0.33
7104 00:57:20.223723 # ok 427 event_spurious.0.33
7105 00:57:20.223802 # ok 428 get_value.0.32
7106 00:57:20.230664 # # 0.32 PCM_1_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7107 00:57:20.233737 # not ok 429 name.0.32
7108 00:57:20.237119 # ok 430 write_default.0.32
7109 00:57:20.237196 # ok 431 write_valid.0.32
7110 00:57:20.240668 # ok 432 write_invalid.0.32
7111 00:57:20.243901 # ok 433 event_missing.0.32
7112 00:57:20.247498 # ok 434 event_spurious.0.32
7113 00:57:20.247593 # ok 435 get_value.0.31
7114 00:57:20.253985 # # 0.31 PCM_1_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7115 00:57:20.256973 # not ok 436 name.0.31
7116 00:57:20.260463 # ok 437 write_default.0.31
7117 00:57:20.260539 # ok 438 write_valid.0.31
7118 00:57:20.263883 # ok 439 write_invalid.0.31
7119 00:57:20.267328 # ok 440 event_missing.0.31
7120 00:57:20.270311 # ok 441 event_spurious.0.31
7121 00:57:20.273885 # ok 442 get_value.0.30
7122 00:57:20.280388 # # 0.30 PCM_1_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7123 00:57:20.280464 # not ok 443 name.0.30
7124 00:57:20.284006 # ok 444 write_default.0.30
7125 00:57:20.286974 # ok 445 write_valid.0.30
7126 00:57:20.287056 # ok 446 write_invalid.0.30
7127 00:57:20.290439 # ok 447 event_missing.0.30
7128 00:57:20.294139 # ok 448 event_spurious.0.30
7129 00:57:20.296821 # ok 449 get_value.0.29
7130 00:57:20.296897 # ok 450 name.0.29
7131 00:57:20.300189 # ok 451 write_default.0.29
7132 00:57:20.303630 # ok 452 write_valid.0.29
7133 00:57:20.306947 # ok 453 write_invalid.0.29
7134 00:57:20.307024 # ok 454 event_missing.0.29
7135 00:57:20.310259 # ok 455 event_spurious.0.29
7136 00:57:20.313487 # ok 456 get_value.0.28
7137 00:57:20.313564 # ok 457 name.0.28
7138 00:57:20.316711 # ok 458 write_default.0.28
7139 00:57:20.320009 # ok 459 write_valid.0.28
7140 00:57:20.323610 # ok 460 write_invalid.0.28
7141 00:57:20.326606 # ok 461 event_missing.0.28
7142 00:57:20.326683 # ok 462 event_spurious.0.28
7143 00:57:20.329978 # ok 463 get_value.0.27
7144 00:57:20.333447 # ok 464 name.0.27
7145 00:57:20.333523 # ok 465 write_default.0.27
7146 00:57:20.336616 # ok 466 write_valid.0.27
7147 00:57:20.340171 # ok 467 write_invalid.0.27
7148 00:57:20.343420 # ok 468 event_missing.0.27
7149 00:57:20.343497 # ok 469 event_spurious.0.27
7150 00:57:20.346585 # ok 470 get_value.0.26
7151 00:57:20.349885 # ok 471 name.0.26
7152 00:57:20.349962 # ok 472 write_default.0.26
7153 00:57:20.353432 # ok 473 write_valid.0.26
7154 00:57:20.356817 # ok 474 write_invalid.0.26
7155 00:57:20.359795 # ok 475 event_missing.0.26
7156 00:57:20.363656 # ok 476 event_spurious.0.26
7157 00:57:20.363732 # ok 477 get_value.0.25
7158 00:57:20.366511 # ok 478 name.0.25
7159 00:57:20.369808 # ok 479 write_default.0.25
7160 00:57:20.369888 # ok 480 write_valid.0.25
7161 00:57:20.372992 # ok 481 write_invalid.0.25
7162 00:57:20.376584 # ok 482 event_missing.0.25
7163 00:57:20.379792 # ok 483 event_spurious.0.25
7164 00:57:20.379869 # ok 484 get_value.0.24
7165 00:57:20.383216 # ok 485 name.0.24
7166 00:57:20.386708 # ok 486 write_default.0.24
7167 00:57:20.386785 # ok 487 write_valid.0.24
7168 00:57:20.389745 # ok 488 write_invalid.0.24
7169 00:57:20.393056 # ok 489 event_missing.0.24
7170 00:57:20.396523 # ok 490 event_spurious.0.24
7171 00:57:20.399628 # ok 491 get_value.0.23
7172 00:57:20.399705 # ok 492 name.0.23
7173 00:57:20.403020 # ok 493 write_default.0.23
7174 00:57:20.406383 # ok 494 write_valid.0.23
7175 00:57:20.406460 # ok 495 write_invalid.0.23
7176 00:57:20.409656 # ok 496 event_missing.0.23
7177 00:57:20.413112 # ok 497 event_spurious.0.23
7178 00:57:20.416372 # ok 498 get_value.0.22
7179 00:57:20.416448 # ok 499 name.0.22
7180 00:57:20.419642 # ok 500 write_default.0.22
7181 00:57:20.423241 # ok 501 write_valid.0.22
7182 00:57:20.423317 # ok 502 write_invalid.0.22
7183 00:57:20.426546 # ok 503 event_missing.0.22
7184 00:57:20.429703 # ok 504 event_spurious.0.22
7185 00:57:20.432949 # ok 505 get_value.0.21
7186 00:57:20.439866 # # 0.21 UL_MONO_1_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7187 00:57:20.439944 # not ok 506 name.0.21
7188 00:57:20.442838 # ok 507 write_default.0.21
7189 00:57:20.446148 # ok 508 write_valid.0.21
7190 00:57:20.449441 # ok 509 write_invalid.0.21
7191 00:57:20.449517 # ok 510 event_missing.0.21
7192 00:57:20.452769 # ok 511 event_spurious.0.21
7193 00:57:20.456054 # ok 512 get_value.0.20
7194 00:57:20.463030 # # 0.20 UL_MONO_1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7195 00:57:20.463112 # not ok 513 name.0.20
7196 00:57:20.466168 # ok 514 write_default.0.20
7197 00:57:20.469418 # ok 515 write_valid.0.20
7198 00:57:20.472822 # ok 516 write_invalid.0.20
7199 00:57:20.472899 # ok 517 event_missing.0.20
7200 00:57:20.475958 # ok 518 event_spurious.0.20
7201 00:57:20.479465 # ok 519 get_value.0.19
7202 00:57:20.485890 # # 0.19 UL4_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7203 00:57:20.485968 # not ok 520 name.0.19
7204 00:57:20.489093 # ok 521 write_default.0.19
7205 00:57:20.492622 # ok 522 write_valid.0.19
7206 00:57:20.495670 # ok 523 write_invalid.0.19
7207 00:57:20.495747 # ok 524 event_missing.0.19
7208 00:57:20.499058 # ok 525 event_spurious.0.19
7209 00:57:20.502719 # ok 526 get_value.0.18
7210 00:57:20.509250 # # 0.18 UL4_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7211 00:57:20.509328 # not ok 527 name.0.18
7212 00:57:20.512343 # ok 528 write_default.0.18
7213 00:57:20.515785 # ok 529 write_valid.0.18
7214 00:57:20.519026 # ok 530 write_invalid.0.18
7215 00:57:20.519103 # ok 531 event_missing.0.18
7216 00:57:20.522744 # ok 532 event_spurious.0.18
7217 00:57:20.525796 # ok 533 get_value.0.17
7218 00:57:20.529014 # # 0.17 UL3_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7219 00:57:20.532287 # not ok 534 name.0.17
7220 00:57:20.535577 # ok 535 write_default.0.17
7221 00:57:20.538826 # ok 536 write_valid.0.17
7222 00:57:20.538903 # ok 537 write_invalid.0.17
7223 00:57:20.542159 # ok 538 event_missing.0.17
7224 00:57:20.545458 # ok 539 event_spurious.0.17
7225 00:57:20.548718 # ok 540 get_value.0.16
7226 00:57:20.552056 # # 0.16 UL3_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7227 00:57:20.555331 # not ok 541 name.0.16
7228 00:57:20.558656 # ok 542 write_default.0.16
7229 00:57:20.558733 # ok 543 write_valid.0.16
7230 00:57:20.562114 # ok 544 write_invalid.0.16
7231 00:57:20.565291 # ok 545 event_missing.0.16
7232 00:57:20.568808 # ok 546 event_spurious.0.16
7233 00:57:20.568885 # ok 547 get_value.0.15
7234 00:57:20.575477 # # 0.15 UL3_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7235 00:57:20.578836 # not ok 548 name.0.15
7236 00:57:20.581924 # ok 549 write_default.0.15
7237 00:57:20.582001 # ok 550 write_valid.0.15
7238 00:57:20.585578 # ok 551 write_invalid.0.15
7239 00:57:20.588533 # ok 552 event_missing.0.15
7240 00:57:20.592026 # ok 553 event_spurious.0.15
7241 00:57:20.592104 # ok 554 get_value.0.14
7242 00:57:20.598847 # # 0.14 UL3_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7243 00:57:20.602073 # not ok 555 name.0.14
7244 00:57:20.605209 # ok 556 write_default.0.14
7245 00:57:20.605286 # ok 557 write_valid.0.14
7246 00:57:20.608544 # ok 558 write_invalid.0.14
7247 00:57:20.612068 # ok 559 event_missing.0.14
7248 00:57:20.615434 # ok 560 event_spurious.0.14
7249 00:57:20.615511 # ok 561 get_value.0.13
7250 00:57:20.621850 # # 0.13 UL2_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7251 00:57:20.625455 # not ok 562 name.0.13
7252 00:57:20.628522 # ok 563 write_default.0.13
7253 00:57:20.628600 # ok 564 write_valid.0.13
7254 00:57:20.631856 # ok 565 write_invalid.0.13
7255 00:57:20.635394 # ok 566 event_missing.0.13
7256 00:57:20.638646 # ok 567 event_spurious.0.13
7257 00:57:20.638723 # ok 568 get_value.0.12
7258 00:57:20.645090 # # 0.12 UL2_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7259 00:57:20.648415 # not ok 569 name.0.12
7260 00:57:20.651760 # ok 570 write_default.0.12
7261 00:57:20.654978 # ok 571 write_valid.0.12
7262 00:57:20.655055 # ok 572 write_invalid.0.12
7263 00:57:20.658685 # ok 573 event_missing.0.12
7264 00:57:20.661688 # ok 574 event_spurious.0.12
7265 00:57:20.664931 # ok 575 get_value.0.11
7266 00:57:20.668339 # # 0.11 UL2_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7267 00:57:20.671858 # not ok 576 name.0.11
7268 00:57:20.675098 # ok 577 write_default.0.11
7269 00:57:20.678709 # ok 578 write_valid.0.11
7270 00:57:20.678785 # ok 579 write_invalid.0.11
7271 00:57:20.681757 # ok 580 event_missing.0.11
7272 00:57:20.685127 # ok 581 event_spurious.0.11
7273 00:57:20.688495 # ok 582 get_value.0.10
7274 00:57:20.691978 # # 0.10 UL2_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7275 00:57:20.695364 # not ok 583 name.0.10
7276 00:57:20.698747 # ok 584 write_default.0.10
7277 00:57:20.701763 # ok 585 write_valid.0.10
7278 00:57:20.701845 # ok 586 write_invalid.0.10
7279 00:57:20.705377 # ok 587 event_missing.0.10
7280 00:57:20.708721 # ok 588 event_spurious.0.10
7281 00:57:20.711790 # ok 589 get_value.0.9
7282 00:57:20.715181 # # 0.9 UL1_CH2 I2S0_CH2 is a writeable boolean but not a Switch
7283 00:57:20.718416 # not ok 590 name.0.9
7284 00:57:20.721720 # ok 591 write_default.0.9
7285 00:57:20.725083 # ok 592 write_valid.0.9
7286 00:57:20.725159 # ok 593 write_invalid.0.9
7287 00:57:20.728184 # ok 594 event_missing.0.9
7288 00:57:20.731675 # ok 595 event_spurious.0.9
7289 00:57:20.735040 # ok 596 get_value.0.8
7290 00:57:20.738531 # # 0.8 UL1_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7291 00:57:20.742524 # not ok 597 name.0.8
7292 00:57:20.745679 # ok 598 write_default.0.8
7293 00:57:20.746075 # ok 599 write_valid.0.8
7294 00:57:20.748767 # ok 600 write_invalid.0.8
7295 00:57:20.752038 # ok 601 event_missing.0.8
7296 00:57:20.755381 # ok 602 event_spurious.0.8
7297 00:57:20.755775 # ok 603 get_value.0.7
7298 00:57:20.761880 # # 0.7 UL1_CH1 I2S0_CH1 is a writeable boolean but not a Switch
7299 00:57:20.765241 # not ok 604 name.0.7
7300 00:57:20.768706 # ok 605 write_default.0.7
7301 00:57:20.769103 # ok 606 write_valid.0.7
7302 00:57:20.772078 # ok 607 write_invalid.0.7
7303 00:57:20.775465 # ok 608 event_missing.0.7
7304 00:57:20.778706 # ok 609 event_spurious.0.7
7305 00:57:20.779118 # ok 610 get_value.0.6
7306 00:57:20.785138 # # 0.6 UL1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7307 00:57:20.788503 # not ok 611 name.0.6
7308 00:57:20.789002 # ok 612 write_default.0.6
7309 00:57:20.792287 # ok 613 write_valid.0.6
7310 00:57:20.795280 # ok 614 write_invalid.0.6
7311 00:57:20.798496 # ok 615 event_missing.0.6
7312 00:57:20.799011 # ok 616 event_spurious.0.6
7313 00:57:20.802015 # ok 617 get_value.0.5
7314 00:57:20.805015 # ok 618 name.0.5
7315 00:57:20.805354 # ok 619 write_default.0.5
7316 00:57:20.808691 # # No event generated for MTKAIF_DMIC
7317 00:57:20.811709 # # No event generated for MTKAIF_DMIC
7318 00:57:20.815092 # ok 620 write_valid.0.5
7319 00:57:20.818436 # ok 621 write_invalid.0.5
7320 00:57:20.821777 # not ok 622 event_missing.0.5
7321 00:57:20.822203 # ok 623 event_spurious.0.5
7322 00:57:20.825179 # ok 624 get_value.0.4
7323 00:57:20.828515 # ok 625 name.0.4
7324 00:57:20.828938 # ok 626 write_default.0.4
7325 00:57:20.831579 # # No event generated for I2S5_HD_Mux
7326 00:57:20.835049 # # No event generated for I2S5_HD_Mux
7327 00:57:20.838135 # ok 627 write_valid.0.4
7328 00:57:20.841799 # ok 628 write_invalid.0.4
7329 00:57:20.844774 # not ok 629 event_missing.0.4
7330 00:57:20.845203 # ok 630 event_spurious.0.4
7331 00:57:20.848356 # ok 631 get_value.0.3
7332 00:57:20.851438 # ok 632 name.0.3
7333 00:57:20.851900 # ok 633 write_default.0.3
7334 00:57:20.854775 # # No event generated for I2S3_HD_Mux
7335 00:57:20.858282 # # No event generated for I2S3_HD_Mux
7336 00:57:20.861729 # ok 634 write_valid.0.3
7337 00:57:20.864738 # ok 635 write_invalid.0.3
7338 00:57:20.868153 # not ok 636 event_missing.0.3
7339 00:57:20.868689 # ok 637 event_spurious.0.3
7340 00:57:20.871666 # ok 638 get_value.0.2
7341 00:57:20.874861 # ok 639 name.0.2
7342 00:57:20.875260 # ok 640 write_default.0.2
7343 00:57:20.878125 # # No event generated for I2S2_HD_Mux
7344 00:57:20.881613 # # No event generated for I2S2_HD_Mux
7345 00:57:20.884660 # ok 641 write_valid.0.2
7346 00:57:20.887951 # ok 642 write_invalid.0.2
7347 00:57:20.891431 # not ok 643 event_missing.0.2
7348 00:57:20.891834 # ok 644 event_spurious.0.2
7349 00:57:20.894491 # ok 645 get_value.0.1
7350 00:57:20.897957 # ok 646 name.0.1
7351 00:57:20.898034 # ok 647 write_default.0.1
7352 00:57:20.901245 # # No event generated for I2S1_HD_Mux
7353 00:57:20.904549 # # No event generated for I2S1_HD_Mux
7354 00:57:20.907971 # ok 648 write_valid.0.1
7355 00:57:20.910852 # ok 649 write_invalid.0.1
7356 00:57:20.914285 # not ok 650 event_missing.0.1
7357 00:57:20.914363 # ok 651 event_spurious.0.1
7358 00:57:20.917560 # ok 652 get_value.0.0
7359 00:57:20.917636 # ok 653 name.0.0
7360 00:57:20.921102 # ok 654 write_default.0.0
7361 00:57:20.924415 # # No event generated for I2S0_HD_Mux
7362 00:57:20.927677 # # No event generated for I2S0_HD_Mux
7363 00:57:20.931103 # ok 655 write_valid.0.0
7364 00:57:20.934458 # ok 656 write_invalid.0.0
7365 00:57:20.937911 # not ok 657 event_missing.0.0
7366 00:57:20.937987 # ok 658 event_spurious.0.0
7367 00:57:20.944541 # # Totals: pass:568 fail:87 xfail:0 xpass:0 skip:3 error:0
7368 00:57:20.947937 ok 1 selftests: alsa: mixer-test
7369 00:57:22.521972 alsa_mixer-test_get_value_0_93 pass
7370 00:57:22.525268 alsa_mixer-test_name_0_93 pass
7371 00:57:22.528210 alsa_mixer-test_write_default_0_93 pass
7372 00:57:22.531678 alsa_mixer-test_write_valid_0_93 pass
7373 00:57:22.538159 alsa_mixer-test_write_invalid_0_93 pass
7374 00:57:22.541670 alsa_mixer-test_event_missing_0_93 pass
7375 00:57:22.545061 alsa_mixer-test_event_spurious_0_93 pass
7376 00:57:22.548476 alsa_mixer-test_get_value_0_92 pass
7377 00:57:22.551419 alsa_mixer-test_name_0_92 pass
7378 00:57:22.554910 alsa_mixer-test_write_default_0_92 pass
7379 00:57:22.558587 alsa_mixer-test_write_valid_0_92 pass
7380 00:57:22.561719 alsa_mixer-test_write_invalid_0_92 pass
7381 00:57:22.564905 alsa_mixer-test_event_missing_0_92 pass
7382 00:57:22.568282 alsa_mixer-test_event_spurious_0_92 pass
7383 00:57:22.571608 alsa_mixer-test_get_value_0_91 pass
7384 00:57:22.574968 alsa_mixer-test_name_0_91 pass
7385 00:57:22.578456 alsa_mixer-test_write_default_0_91 pass
7386 00:57:22.581843 alsa_mixer-test_write_valid_0_91 pass
7387 00:57:22.585012 alsa_mixer-test_write_invalid_0_91 pass
7388 00:57:22.588338 alsa_mixer-test_event_missing_0_91 pass
7389 00:57:22.591597 alsa_mixer-test_event_spurious_0_91 pass
7390 00:57:22.595223 alsa_mixer-test_get_value_0_90 pass
7391 00:57:22.598359 alsa_mixer-test_name_0_90 pass
7392 00:57:22.601462 alsa_mixer-test_write_default_0_90 pass
7393 00:57:22.605162 alsa_mixer-test_write_valid_0_90 pass
7394 00:57:22.611694 alsa_mixer-test_write_invalid_0_90 pass
7395 00:57:22.614708 alsa_mixer-test_event_missing_0_90 pass
7396 00:57:22.618504 alsa_mixer-test_event_spurious_0_90 pass
7397 00:57:22.621563 alsa_mixer-test_get_value_0_89 pass
7398 00:57:22.625161 alsa_mixer-test_name_0_89 pass
7399 00:57:22.628147 alsa_mixer-test_write_default_0_89 pass
7400 00:57:22.631444 alsa_mixer-test_write_valid_0_89 pass
7401 00:57:22.635261 alsa_mixer-test_write_invalid_0_89 pass
7402 00:57:22.638075 alsa_mixer-test_event_missing_0_89 pass
7403 00:57:22.641477 alsa_mixer-test_event_spurious_0_89 pass
7404 00:57:22.644728 alsa_mixer-test_get_value_0_88 pass
7405 00:57:22.648019 alsa_mixer-test_name_0_88 pass
7406 00:57:22.651406 alsa_mixer-test_write_default_0_88 pass
7407 00:57:22.654719 alsa_mixer-test_write_valid_0_88 fail
7408 00:57:22.658132 alsa_mixer-test_write_invalid_0_88 pass
7409 00:57:22.661398 alsa_mixer-test_event_missing_0_88 pass
7410 00:57:22.668273 alsa_mixer-test_event_spurious_0_88 fail
7411 00:57:22.671381 alsa_mixer-test_get_value_0_87 pass
7412 00:57:22.671777 alsa_mixer-test_name_0_87 pass
7413 00:57:22.677900 alsa_mixer-test_write_default_0_87 pass
7414 00:57:22.681366 alsa_mixer-test_write_valid_0_87 pass
7415 00:57:22.684529 alsa_mixer-test_write_invalid_0_87 pass
7416 00:57:22.688113 alsa_mixer-test_event_missing_0_87 pass
7417 00:57:22.691437 alsa_mixer-test_event_spurious_0_87 pass
7418 00:57:22.694548 alsa_mixer-test_get_value_0_86 pass
7419 00:57:22.697914 alsa_mixer-test_name_0_86 pass
7420 00:57:22.701650 alsa_mixer-test_write_default_0_86 pass
7421 00:57:22.704961 alsa_mixer-test_write_valid_0_86 fail
7422 00:57:22.707923 alsa_mixer-test_write_invalid_0_86 pass
7423 00:57:22.711665 alsa_mixer-test_event_missing_0_86 pass
7424 00:57:22.714727 alsa_mixer-test_event_spurious_0_86 pass
7425 00:57:22.718532 alsa_mixer-test_get_value_0_85 pass
7426 00:57:22.721747 alsa_mixer-test_name_0_85 pass
7427 00:57:22.724690 alsa_mixer-test_write_default_0_85 pass
7428 00:57:22.728364 alsa_mixer-test_write_valid_0_85 fail
7429 00:57:22.734514 alsa_mixer-test_write_invalid_0_85 pass
7430 00:57:22.737872 alsa_mixer-test_event_missing_0_85 pass
7431 00:57:22.741177 alsa_mixer-test_event_spurious_0_85 pass
7432 00:57:22.744466 alsa_mixer-test_get_value_0_84 pass
7433 00:57:22.748009 alsa_mixer-test_name_0_84 pass
7434 00:57:22.751349 alsa_mixer-test_write_default_0_84 pass
7435 00:57:22.754716 alsa_mixer-test_write_valid_0_84 pass
7436 00:57:22.758017 alsa_mixer-test_write_invalid_0_84 pass
7437 00:57:22.761247 alsa_mixer-test_event_missing_0_84 pass
7438 00:57:22.764443 alsa_mixer-test_event_spurious_0_84 pass
7439 00:57:22.767937 alsa_mixer-test_get_value_0_83 pass
7440 00:57:22.771202 alsa_mixer-test_name_0_83 pass
7441 00:57:22.774515 alsa_mixer-test_write_default_0_83 pass
7442 00:57:22.777926 alsa_mixer-test_write_valid_0_83 pass
7443 00:57:22.781520 alsa_mixer-test_write_invalid_0_83 pass
7444 00:57:22.784580 alsa_mixer-test_event_missing_0_83 pass
7445 00:57:22.791126 alsa_mixer-test_event_spurious_0_83 pass
7446 00:57:22.794597 alsa_mixer-test_get_value_0_82 pass
7447 00:57:22.795189 alsa_mixer-test_name_0_82 pass
7448 00:57:22.797826 alsa_mixer-test_write_default_0_82 skip
7449 00:57:22.804547 alsa_mixer-test_write_valid_0_82 skip
7450 00:57:22.807537 alsa_mixer-test_write_invalid_0_82 skip
7451 00:57:22.810825 alsa_mixer-test_event_missing_0_82 pass
7452 00:57:22.814708 alsa_mixer-test_event_spurious_0_82 pass
7453 00:57:22.817722 alsa_mixer-test_get_value_0_81 pass
7454 00:57:22.821248 alsa_mixer-test_name_0_81 pass
7455 00:57:22.824609 alsa_mixer-test_write_default_0_81 pass
7456 00:57:22.827779 alsa_mixer-test_write_valid_0_81 pass
7457 00:57:22.831062 alsa_mixer-test_write_invalid_0_81 fail
7458 00:57:22.834325 alsa_mixer-test_event_missing_0_81 fail
7459 00:57:22.837614 alsa_mixer-test_event_spurious_0_81 pass
7460 00:57:22.841325 alsa_mixer-test_get_value_0_80 pass
7461 00:57:22.844210 alsa_mixer-test_name_0_80 pass
7462 00:57:22.847649 alsa_mixer-test_write_default_0_80 pass
7463 00:57:22.850888 alsa_mixer-test_write_valid_0_80 pass
7464 00:57:22.854309 alsa_mixer-test_write_invalid_0_80 pass
7465 00:57:22.860944 alsa_mixer-test_event_missing_0_80 pass
7466 00:57:22.864452 alsa_mixer-test_event_spurious_0_80 pass
7467 00:57:22.867762 alsa_mixer-test_get_value_0_79 fail
7468 00:57:22.868163 alsa_mixer-test_name_0_79 pass
7469 00:57:22.874167 alsa_mixer-test_write_default_0_79 fail
7470 00:57:22.877459 alsa_mixer-test_write_valid_0_79 fail
7471 00:57:22.881040 alsa_mixer-test_write_invalid_0_79 fail
7472 00:57:22.884391 alsa_mixer-test_event_missing_0_79 pass
7473 00:57:22.887557 alsa_mixer-test_event_spurious_0_79 pass
7474 00:57:22.890930 alsa_mixer-test_get_value_0_78 fail
7475 00:57:22.894248 alsa_mixer-test_name_0_78 pass
7476 00:57:22.897506 alsa_mixer-test_write_default_0_78 fail
7477 00:57:22.900850 alsa_mixer-test_write_valid_0_78 fail
7478 00:57:22.904360 alsa_mixer-test_write_invalid_0_78 fail
7479 00:57:22.907704 alsa_mixer-test_event_missing_0_78 pass
7480 00:57:22.910811 alsa_mixer-test_event_spurious_0_78 pass
7481 00:57:22.914199 alsa_mixer-test_get_value_0_77 fail
7482 00:57:22.917330 alsa_mixer-test_name_0_77 pass
7483 00:57:22.920854 alsa_mixer-test_write_default_0_77 fail
7484 00:57:22.924349 alsa_mixer-test_write_valid_0_77 fail
7485 00:57:22.927678 alsa_mixer-test_write_invalid_0_77 fail
7486 00:57:22.934247 alsa_mixer-test_event_missing_0_77 pass
7487 00:57:22.937872 alsa_mixer-test_event_spurious_0_77 pass
7488 00:57:22.940878 alsa_mixer-test_get_value_0_76 pass
7489 00:57:22.944134 alsa_mixer-test_name_0_76 fail
7490 00:57:22.947346 alsa_mixer-test_write_default_0_76 pass
7491 00:57:22.950614 alsa_mixer-test_write_valid_0_76 pass
7492 00:57:22.954066 alsa_mixer-test_write_invalid_0_76 pass
7493 00:57:22.957328 alsa_mixer-test_event_missing_0_76 pass
7494 00:57:22.960562 alsa_mixer-test_event_spurious_0_76 pass
7495 00:57:22.964019 alsa_mixer-test_get_value_0_75 pass
7496 00:57:22.967258 alsa_mixer-test_name_0_75 fail
7497 00:57:22.970550 alsa_mixer-test_write_default_0_75 pass
7498 00:57:22.974100 alsa_mixer-test_write_valid_0_75 pass
7499 00:57:22.977245 alsa_mixer-test_write_invalid_0_75 pass
7500 00:57:22.980857 alsa_mixer-test_event_missing_0_75 pass
7501 00:57:22.987240 alsa_mixer-test_event_spurious_0_75 pass
7502 00:57:22.990532 alsa_mixer-test_get_value_0_74 pass
7503 00:57:22.991126 alsa_mixer-test_name_0_74 fail
7504 00:57:22.994131 alsa_mixer-test_write_default_0_74 pass
7505 00:57:23.000495 alsa_mixer-test_write_valid_0_74 pass
7506 00:57:23.003947 alsa_mixer-test_write_invalid_0_74 pass
7507 00:57:23.007224 alsa_mixer-test_event_missing_0_74 pass
7508 00:57:23.010831 alsa_mixer-test_event_spurious_0_74 pass
7509 00:57:23.014076 alsa_mixer-test_get_value_0_73 pass
7510 00:57:23.017224 alsa_mixer-test_name_0_73 fail
7511 00:57:23.020588 alsa_mixer-test_write_default_0_73 pass
7512 00:57:23.023747 alsa_mixer-test_write_valid_0_73 pass
7513 00:57:23.027086 alsa_mixer-test_write_invalid_0_73 pass
7514 00:57:23.030418 alsa_mixer-test_event_missing_0_73 pass
7515 00:57:23.033649 alsa_mixer-test_event_spurious_0_73 pass
7516 00:57:23.037174 alsa_mixer-test_get_value_0_72 pass
7517 00:57:23.040444 alsa_mixer-test_name_0_72 fail
7518 00:57:23.043485 alsa_mixer-test_write_default_0_72 pass
7519 00:57:23.047081 alsa_mixer-test_write_valid_0_72 pass
7520 00:57:23.050254 alsa_mixer-test_write_invalid_0_72 pass
7521 00:57:23.056866 alsa_mixer-test_event_missing_0_72 pass
7522 00:57:23.060609 alsa_mixer-test_event_spurious_0_72 pass
7523 00:57:23.063569 alsa_mixer-test_get_value_0_71 pass
7524 00:57:23.066802 alsa_mixer-test_name_0_71 fail
7525 00:57:23.070420 alsa_mixer-test_write_default_0_71 pass
7526 00:57:23.073683 alsa_mixer-test_write_valid_0_71 pass
7527 00:57:23.076761 alsa_mixer-test_write_invalid_0_71 pass
7528 00:57:23.080402 alsa_mixer-test_event_missing_0_71 pass
7529 00:57:23.083699 alsa_mixer-test_event_spurious_0_71 pass
7530 00:57:23.086983 alsa_mixer-test_get_value_0_70 pass
7531 00:57:23.090131 alsa_mixer-test_name_0_70 fail
7532 00:57:23.093459 alsa_mixer-test_write_default_0_70 pass
7533 00:57:23.096789 alsa_mixer-test_write_valid_0_70 pass
7534 00:57:23.100072 alsa_mixer-test_write_invalid_0_70 pass
7535 00:57:23.103632 alsa_mixer-test_event_missing_0_70 pass
7536 00:57:23.106678 alsa_mixer-test_event_spurious_0_70 pass
7537 00:57:23.110169 alsa_mixer-test_get_value_0_69 pass
7538 00:57:23.113746 alsa_mixer-test_name_0_69 fail
7539 00:57:23.117059 alsa_mixer-test_write_default_0_69 pass
7540 00:57:23.120281 alsa_mixer-test_write_valid_0_69 pass
7541 00:57:23.123614 alsa_mixer-test_write_invalid_0_69 pass
7542 00:57:23.127377 alsa_mixer-test_event_missing_0_69 pass
7543 00:57:23.133548 alsa_mixer-test_event_spurious_0_69 pass
7544 00:57:23.136807 alsa_mixer-test_get_value_0_68 pass
7545 00:57:23.137198 alsa_mixer-test_name_0_68 fail
7546 00:57:23.143507 alsa_mixer-test_write_default_0_68 pass
7547 00:57:23.146632 alsa_mixer-test_write_valid_0_68 pass
7548 00:57:23.149830 alsa_mixer-test_write_invalid_0_68 pass
7549 00:57:23.153359 alsa_mixer-test_event_missing_0_68 pass
7550 00:57:23.156826 alsa_mixer-test_event_spurious_0_68 pass
7551 00:57:23.159921 alsa_mixer-test_get_value_0_67 pass
7552 00:57:23.163412 alsa_mixer-test_name_0_67 fail
7553 00:57:23.166653 alsa_mixer-test_write_default_0_67 pass
7554 00:57:23.170012 alsa_mixer-test_write_valid_0_67 pass
7555 00:57:23.173259 alsa_mixer-test_write_invalid_0_67 pass
7556 00:57:23.176596 alsa_mixer-test_event_missing_0_67 pass
7557 00:57:23.179898 alsa_mixer-test_event_spurious_0_67 pass
7558 00:57:23.183443 alsa_mixer-test_get_value_0_66 pass
7559 00:57:23.186523 alsa_mixer-test_name_0_66 fail
7560 00:57:23.189773 alsa_mixer-test_write_default_0_66 pass
7561 00:57:23.192778 alsa_mixer-test_write_valid_0_66 pass
7562 00:57:23.199382 alsa_mixer-test_write_invalid_0_66 pass
7563 00:57:23.202713 alsa_mixer-test_event_missing_0_66 pass
7564 00:57:23.206307 alsa_mixer-test_event_spurious_0_66 pass
7565 00:57:23.209618 alsa_mixer-test_get_value_0_65 pass
7566 00:57:23.212811 alsa_mixer-test_name_0_65 fail
7567 00:57:23.216335 alsa_mixer-test_write_default_0_65 pass
7568 00:57:23.219542 alsa_mixer-test_write_valid_0_65 pass
7569 00:57:23.222887 alsa_mixer-test_write_invalid_0_65 pass
7570 00:57:23.226187 alsa_mixer-test_event_missing_0_65 pass
7571 00:57:23.229464 alsa_mixer-test_event_spurious_0_65 pass
7572 00:57:23.232708 alsa_mixer-test_get_value_0_64 pass
7573 00:57:23.235981 alsa_mixer-test_name_0_64 fail
7574 00:57:23.239465 alsa_mixer-test_write_default_0_64 pass
7575 00:57:23.242950 alsa_mixer-test_write_valid_0_64 pass
7576 00:57:23.246087 alsa_mixer-test_write_invalid_0_64 pass
7577 00:57:23.249713 alsa_mixer-test_event_missing_0_64 pass
7578 00:57:23.252761 alsa_mixer-test_event_spurious_0_64 pass
7579 00:57:23.256068 alsa_mixer-test_get_value_0_63 pass
7580 00:57:23.259807 alsa_mixer-test_name_0_63 fail
7581 00:57:23.262994 alsa_mixer-test_write_default_0_63 pass
7582 00:57:23.266025 alsa_mixer-test_write_valid_0_63 pass
7583 00:57:23.272828 alsa_mixer-test_write_invalid_0_63 pass
7584 00:57:23.276059 alsa_mixer-test_event_missing_0_63 pass
7585 00:57:23.279452 alsa_mixer-test_event_spurious_0_63 pass
7586 00:57:23.282942 alsa_mixer-test_get_value_0_62 pass
7587 00:57:23.286024 alsa_mixer-test_name_0_62 fail
7588 00:57:23.289464 alsa_mixer-test_write_default_0_62 pass
7589 00:57:23.292973 alsa_mixer-test_write_valid_0_62 pass
7590 00:57:23.296364 alsa_mixer-test_write_invalid_0_62 pass
7591 00:57:23.299854 alsa_mixer-test_event_missing_0_62 pass
7592 00:57:23.303004 alsa_mixer-test_event_spurious_0_62 pass
7593 00:57:23.306072 alsa_mixer-test_get_value_0_61 pass
7594 00:57:23.309402 alsa_mixer-test_name_0_61 fail
7595 00:57:23.312839 alsa_mixer-test_write_default_0_61 pass
7596 00:57:23.316319 alsa_mixer-test_write_valid_0_61 pass
7597 00:57:23.319504 alsa_mixer-test_write_invalid_0_61 pass
7598 00:57:23.322586 alsa_mixer-test_event_missing_0_61 pass
7599 00:57:23.329195 alsa_mixer-test_event_spurious_0_61 pass
7600 00:57:23.332929 alsa_mixer-test_get_value_0_60 pass
7601 00:57:23.335922 alsa_mixer-test_name_0_60 fail
7602 00:57:23.339476 alsa_mixer-test_write_default_0_60 pass
7603 00:57:23.342989 alsa_mixer-test_write_valid_0_60 pass
7604 00:57:23.346141 alsa_mixer-test_write_invalid_0_60 pass
7605 00:57:23.349549 alsa_mixer-test_event_missing_0_60 pass
7606 00:57:23.353122 alsa_mixer-test_event_spurious_0_60 pass
7607 00:57:23.356175 alsa_mixer-test_get_value_0_59 pass
7608 00:57:23.359617 alsa_mixer-test_name_0_59 fail
7609 00:57:23.362800 alsa_mixer-test_write_default_0_59 pass
7610 00:57:23.366090 alsa_mixer-test_write_valid_0_59 pass
7611 00:57:23.369413 alsa_mixer-test_write_invalid_0_59 pass
7612 00:57:23.373168 alsa_mixer-test_event_missing_0_59 pass
7613 00:57:23.376304 alsa_mixer-test_event_spurious_0_59 pass
7614 00:57:23.379572 alsa_mixer-test_get_value_0_58 pass
7615 00:57:23.382985 alsa_mixer-test_name_0_58 fail
7616 00:57:23.386244 alsa_mixer-test_write_default_0_58 pass
7617 00:57:23.389657 alsa_mixer-test_write_valid_0_58 pass
7618 00:57:23.392949 alsa_mixer-test_write_invalid_0_58 pass
7619 00:57:23.396371 alsa_mixer-test_event_missing_0_58 pass
7620 00:57:23.403024 alsa_mixer-test_event_spurious_0_58 pass
7621 00:57:23.406816 alsa_mixer-test_get_value_0_57 pass
7622 00:57:23.407337 alsa_mixer-test_name_0_57 fail
7623 00:57:23.412920 alsa_mixer-test_write_default_0_57 pass
7624 00:57:23.416431 alsa_mixer-test_write_valid_0_57 pass
7625 00:57:23.419665 alsa_mixer-test_write_invalid_0_57 pass
7626 00:57:23.422910 alsa_mixer-test_event_missing_0_57 pass
7627 00:57:23.426153 alsa_mixer-test_event_spurious_0_57 pass
7628 00:57:23.429478 alsa_mixer-test_get_value_0_56 pass
7629 00:57:23.433027 alsa_mixer-test_name_0_56 fail
7630 00:57:23.436364 alsa_mixer-test_write_default_0_56 pass
7631 00:57:23.439823 alsa_mixer-test_write_valid_0_56 pass
7632 00:57:23.446317 alsa_mixer-test_write_invalid_0_56 pass
7633 00:57:23.449699 alsa_mixer-test_event_missing_0_56 pass
7634 00:57:23.452765 alsa_mixer-test_event_spurious_0_56 pass
7635 00:57:23.456200 alsa_mixer-test_get_value_0_55 pass
7636 00:57:23.459587 alsa_mixer-test_name_0_55 fail
7637 00:57:23.462800 alsa_mixer-test_write_default_0_55 pass
7638 00:57:23.466203 alsa_mixer-test_write_valid_0_55 pass
7639 00:57:23.469520 alsa_mixer-test_write_invalid_0_55 pass
7640 00:57:23.472614 alsa_mixer-test_event_missing_0_55 pass
7641 00:57:23.479485 alsa_mixer-test_event_spurious_0_55 pass
7642 00:57:23.482974 alsa_mixer-test_get_value_0_54 pass
7643 00:57:23.486404 alsa_mixer-test_name_0_54 fail
7644 00:57:23.489725 alsa_mixer-test_write_default_0_54 pass
7645 00:57:23.492893 alsa_mixer-test_write_valid_0_54 pass
7646 00:57:23.496475 alsa_mixer-test_write_invalid_0_54 pass
7647 00:57:23.499791 alsa_mixer-test_event_missing_0_54 pass
7648 00:57:23.502658 alsa_mixer-test_event_spurious_0_54 pass
7649 00:57:23.506034 alsa_mixer-test_get_value_0_53 pass
7650 00:57:23.509298 alsa_mixer-test_name_0_53 fail
7651 00:57:23.516278 alsa_mixer-test_write_default_0_53 pass
7652 00:57:23.519454 alsa_mixer-test_write_valid_0_53 pass
7653 00:57:23.522534 alsa_mixer-test_write_invalid_0_53 pass
7654 00:57:23.526122 alsa_mixer-test_event_missing_0_53 pass
7655 00:57:23.529385 alsa_mixer-test_event_spurious_0_53 pass
7656 00:57:23.532681 alsa_mixer-test_get_value_0_52 pass
7657 00:57:23.536213 alsa_mixer-test_name_0_52 fail
7658 00:57:23.539596 alsa_mixer-test_write_default_0_52 pass
7659 00:57:23.542959 alsa_mixer-test_write_valid_0_52 pass
7660 00:57:23.546034 alsa_mixer-test_write_invalid_0_52 pass
7661 00:57:23.552811 alsa_mixer-test_event_missing_0_52 pass
7662 00:57:23.555985 alsa_mixer-test_event_spurious_0_52 pass
7663 00:57:23.559460 alsa_mixer-test_get_value_0_51 pass
7664 00:57:23.562880 alsa_mixer-test_name_0_51 fail
7665 00:57:23.566077 alsa_mixer-test_write_default_0_51 pass
7666 00:57:23.569477 alsa_mixer-test_write_valid_0_51 pass
7667 00:57:23.572722 alsa_mixer-test_write_invalid_0_51 pass
7668 00:57:23.576095 alsa_mixer-test_event_missing_0_51 pass
7669 00:57:23.582951 alsa_mixer-test_event_spurious_0_51 pass
7670 00:57:23.586069 alsa_mixer-test_get_value_0_50 pass
7671 00:57:23.586535 alsa_mixer-test_name_0_50 fail
7672 00:57:23.592813 alsa_mixer-test_write_default_0_50 pass
7673 00:57:23.596354 alsa_mixer-test_write_valid_0_50 pass
7674 00:57:23.599527 alsa_mixer-test_write_invalid_0_50 pass
7675 00:57:23.602784 alsa_mixer-test_event_missing_0_50 pass
7676 00:57:23.606204 alsa_mixer-test_event_spurious_0_50 pass
7677 00:57:23.609501 alsa_mixer-test_get_value_0_49 pass
7678 00:57:23.612811 alsa_mixer-test_name_0_49 fail
7679 00:57:23.616232 alsa_mixer-test_write_default_0_49 pass
7680 00:57:23.622779 alsa_mixer-test_write_valid_0_49 pass
7681 00:57:23.626485 alsa_mixer-test_write_invalid_0_49 pass
7682 00:57:23.629594 alsa_mixer-test_event_missing_0_49 pass
7683 00:57:23.633207 alsa_mixer-test_event_spurious_0_49 pass
7684 00:57:23.636441 alsa_mixer-test_get_value_0_48 pass
7685 00:57:23.639949 alsa_mixer-test_name_0_48 fail
7686 00:57:23.643135 alsa_mixer-test_write_default_0_48 pass
7687 00:57:23.646316 alsa_mixer-test_write_valid_0_48 pass
7688 00:57:23.649523 alsa_mixer-test_write_invalid_0_48 pass
7689 00:57:23.656058 alsa_mixer-test_event_missing_0_48 pass
7690 00:57:23.659676 alsa_mixer-test_event_spurious_0_48 pass
7691 00:57:23.663011 alsa_mixer-test_get_value_0_47 pass
7692 00:57:23.666280 alsa_mixer-test_name_0_47 fail
7693 00:57:23.669708 alsa_mixer-test_write_default_0_47 pass
7694 00:57:23.673059 alsa_mixer-test_write_valid_0_47 pass
7695 00:57:23.676003 alsa_mixer-test_write_invalid_0_47 pass
7696 00:57:23.682773 alsa_mixer-test_event_missing_0_47 pass
7697 00:57:23.686197 alsa_mixer-test_event_spurious_0_47 pass
7698 00:57:23.689496 alsa_mixer-test_get_value_0_46 pass
7699 00:57:23.692578 alsa_mixer-test_name_0_46 fail
7700 00:57:23.695881 alsa_mixer-test_write_default_0_46 pass
7701 00:57:23.699595 alsa_mixer-test_write_valid_0_46 pass
7702 00:57:23.702485 alsa_mixer-test_write_invalid_0_46 pass
7703 00:57:23.705873 alsa_mixer-test_event_missing_0_46 pass
7704 00:57:23.712914 alsa_mixer-test_event_spurious_0_46 pass
7705 00:57:23.715549 alsa_mixer-test_get_value_0_45 pass
7706 00:57:23.719113 alsa_mixer-test_name_0_45 fail
7707 00:57:23.722309 alsa_mixer-test_write_default_0_45 pass
7708 00:57:23.725717 alsa_mixer-test_write_valid_0_45 pass
7709 00:57:23.729239 alsa_mixer-test_write_invalid_0_45 pass
7710 00:57:23.732257 alsa_mixer-test_event_missing_0_45 pass
7711 00:57:23.735842 alsa_mixer-test_event_spurious_0_45 pass
7712 00:57:23.739613 alsa_mixer-test_get_value_0_44 pass
7713 00:57:23.742357 alsa_mixer-test_name_0_44 fail
7714 00:57:23.745838 alsa_mixer-test_write_default_0_44 pass
7715 00:57:23.748943 alsa_mixer-test_write_valid_0_44 pass
7716 00:57:23.752300 alsa_mixer-test_write_invalid_0_44 pass
7717 00:57:23.755746 alsa_mixer-test_event_missing_0_44 pass
7718 00:57:23.758955 alsa_mixer-test_event_spurious_0_44 pass
7719 00:57:23.762333 alsa_mixer-test_get_value_0_43 pass
7720 00:57:23.765470 alsa_mixer-test_name_0_43 fail
7721 00:57:23.768948 alsa_mixer-test_write_default_0_43 pass
7722 00:57:23.772390 alsa_mixer-test_write_valid_0_43 pass
7723 00:57:23.775763 alsa_mixer-test_write_invalid_0_43 pass
7724 00:57:23.778777 alsa_mixer-test_event_missing_0_43 pass
7725 00:57:23.782728 alsa_mixer-test_event_spurious_0_43 pass
7726 00:57:23.785576 alsa_mixer-test_get_value_0_42 pass
7727 00:57:23.788901 alsa_mixer-test_name_0_42 fail
7728 00:57:23.792498 alsa_mixer-test_write_default_0_42 pass
7729 00:57:23.795466 alsa_mixer-test_write_valid_0_42 pass
7730 00:57:23.798701 alsa_mixer-test_write_invalid_0_42 pass
7731 00:57:23.802533 alsa_mixer-test_event_missing_0_42 pass
7732 00:57:23.805447 alsa_mixer-test_event_spurious_0_42 pass
7733 00:57:23.808930 alsa_mixer-test_get_value_0_41 pass
7734 00:57:23.812412 alsa_mixer-test_name_0_41 fail
7735 00:57:23.815565 alsa_mixer-test_write_default_0_41 pass
7736 00:57:23.819236 alsa_mixer-test_write_valid_0_41 pass
7737 00:57:23.822320 alsa_mixer-test_write_invalid_0_41 pass
7738 00:57:23.825802 alsa_mixer-test_event_missing_0_41 pass
7739 00:57:23.828845 alsa_mixer-test_event_spurious_0_41 pass
7740 00:57:23.832364 alsa_mixer-test_get_value_0_40 pass
7741 00:57:23.835371 alsa_mixer-test_name_0_40 fail
7742 00:57:23.838652 alsa_mixer-test_write_default_0_40 pass
7743 00:57:23.842072 alsa_mixer-test_write_valid_0_40 pass
7744 00:57:23.846041 alsa_mixer-test_write_invalid_0_40 pass
7745 00:57:23.848997 alsa_mixer-test_event_missing_0_40 pass
7746 00:57:23.855710 alsa_mixer-test_event_spurious_0_40 pass
7747 00:57:23.858797 alsa_mixer-test_get_value_0_39 pass
7748 00:57:23.859226 alsa_mixer-test_name_0_39 fail
7749 00:57:23.862118 alsa_mixer-test_write_default_0_39 pass
7750 00:57:23.865384 alsa_mixer-test_write_valid_0_39 pass
7751 00:57:23.872131 alsa_mixer-test_write_invalid_0_39 pass
7752 00:57:23.875262 alsa_mixer-test_event_missing_0_39 pass
7753 00:57:23.879128 alsa_mixer-test_event_spurious_0_39 pass
7754 00:57:23.882028 alsa_mixer-test_get_value_0_38 pass
7755 00:57:23.885132 alsa_mixer-test_name_0_38 fail
7756 00:57:23.888492 alsa_mixer-test_write_default_0_38 pass
7757 00:57:23.892071 alsa_mixer-test_write_valid_0_38 pass
7758 00:57:23.895377 alsa_mixer-test_write_invalid_0_38 pass
7759 00:57:23.898686 alsa_mixer-test_event_missing_0_38 pass
7760 00:57:23.901982 alsa_mixer-test_event_spurious_0_38 pass
7761 00:57:23.905379 alsa_mixer-test_get_value_0_37 pass
7762 00:57:23.908756 alsa_mixer-test_name_0_37 fail
7763 00:57:23.911817 alsa_mixer-test_write_default_0_37 pass
7764 00:57:23.915305 alsa_mixer-test_write_valid_0_37 pass
7765 00:57:23.918544 alsa_mixer-test_write_invalid_0_37 pass
7766 00:57:23.922005 alsa_mixer-test_event_missing_0_37 pass
7767 00:57:23.925276 alsa_mixer-test_event_spurious_0_37 pass
7768 00:57:23.928460 alsa_mixer-test_get_value_0_36 pass
7769 00:57:23.931877 alsa_mixer-test_name_0_36 fail
7770 00:57:23.935123 alsa_mixer-test_write_default_0_36 pass
7771 00:57:23.938565 alsa_mixer-test_write_valid_0_36 pass
7772 00:57:23.941843 alsa_mixer-test_write_invalid_0_36 pass
7773 00:57:23.944981 alsa_mixer-test_event_missing_0_36 pass
7774 00:57:23.948526 alsa_mixer-test_event_spurious_0_36 pass
7775 00:57:23.951841 alsa_mixer-test_get_value_0_35 pass
7776 00:57:23.955061 alsa_mixer-test_name_0_35 fail
7777 00:57:23.958426 alsa_mixer-test_write_default_0_35 pass
7778 00:57:23.962009 alsa_mixer-test_write_valid_0_35 pass
7779 00:57:23.965149 alsa_mixer-test_write_invalid_0_35 pass
7780 00:57:23.968393 alsa_mixer-test_event_missing_0_35 pass
7781 00:57:23.972143 alsa_mixer-test_event_spurious_0_35 pass
7782 00:57:23.975005 alsa_mixer-test_get_value_0_34 pass
7783 00:57:23.978280 alsa_mixer-test_name_0_34 fail
7784 00:57:23.981833 alsa_mixer-test_write_default_0_34 pass
7785 00:57:23.985141 alsa_mixer-test_write_valid_0_34 pass
7786 00:57:23.988480 alsa_mixer-test_write_invalid_0_34 pass
7787 00:57:23.994760 alsa_mixer-test_event_missing_0_34 pass
7788 00:57:23.998602 alsa_mixer-test_event_spurious_0_34 pass
7789 00:57:24.001964 alsa_mixer-test_get_value_0_33 pass
7790 00:57:24.004929 alsa_mixer-test_name_0_33 fail
7791 00:57:24.008332 alsa_mixer-test_write_default_0_33 pass
7792 00:57:24.011393 alsa_mixer-test_write_valid_0_33 pass
7793 00:57:24.014754 alsa_mixer-test_write_invalid_0_33 pass
7794 00:57:24.018568 alsa_mixer-test_event_missing_0_33 pass
7795 00:57:24.021628 alsa_mixer-test_event_spurious_0_33 pass
7796 00:57:24.024725 alsa_mixer-test_get_value_0_32 pass
7797 00:57:24.028428 alsa_mixer-test_name_0_32 fail
7798 00:57:24.031575 alsa_mixer-test_write_default_0_32 pass
7799 00:57:24.034939 alsa_mixer-test_write_valid_0_32 pass
7800 00:57:24.038134 alsa_mixer-test_write_invalid_0_32 pass
7801 00:57:24.041459 alsa_mixer-test_event_missing_0_32 pass
7802 00:57:24.045026 alsa_mixer-test_event_spurious_0_32 pass
7803 00:57:24.048223 alsa_mixer-test_get_value_0_31 pass
7804 00:57:24.051417 alsa_mixer-test_name_0_31 fail
7805 00:57:24.055217 alsa_mixer-test_write_default_0_31 pass
7806 00:57:24.061680 alsa_mixer-test_write_valid_0_31 pass
7807 00:57:24.064756 alsa_mixer-test_write_invalid_0_31 pass
7808 00:57:24.068058 alsa_mixer-test_event_missing_0_31 pass
7809 00:57:24.071062 alsa_mixer-test_event_spurious_0_31 pass
7810 00:57:24.074629 alsa_mixer-test_get_value_0_30 pass
7811 00:57:24.077803 alsa_mixer-test_name_0_30 fail
7812 00:57:24.081113 alsa_mixer-test_write_default_0_30 pass
7813 00:57:24.084650 alsa_mixer-test_write_valid_0_30 pass
7814 00:57:24.087715 alsa_mixer-test_write_invalid_0_30 pass
7815 00:57:24.091159 alsa_mixer-test_event_missing_0_30 pass
7816 00:57:24.094584 alsa_mixer-test_event_spurious_0_30 pass
7817 00:57:24.097726 alsa_mixer-test_get_value_0_29 pass
7818 00:57:24.101509 alsa_mixer-test_name_0_29 pass
7819 00:57:24.104456 alsa_mixer-test_write_default_0_29 pass
7820 00:57:24.107898 alsa_mixer-test_write_valid_0_29 pass
7821 00:57:24.111074 alsa_mixer-test_write_invalid_0_29 pass
7822 00:57:24.114278 alsa_mixer-test_event_missing_0_29 pass
7823 00:57:24.117665 alsa_mixer-test_event_spurious_0_29 pass
7824 00:57:24.121126 alsa_mixer-test_get_value_0_28 pass
7825 00:57:24.124382 alsa_mixer-test_name_0_28 pass
7826 00:57:24.127543 alsa_mixer-test_write_default_0_28 pass
7827 00:57:24.130921 alsa_mixer-test_write_valid_0_28 pass
7828 00:57:24.134609 alsa_mixer-test_write_invalid_0_28 pass
7829 00:57:24.137582 alsa_mixer-test_event_missing_0_28 pass
7830 00:57:24.144215 alsa_mixer-test_event_spurious_0_28 pass
7831 00:57:24.144606 alsa_mixer-test_get_value_0_27 pass
7832 00:57:24.147791 alsa_mixer-test_name_0_27 pass
7833 00:57:24.151105 alsa_mixer-test_write_default_0_27 pass
7834 00:57:24.154187 alsa_mixer-test_write_valid_0_27 pass
7835 00:57:24.158002 alsa_mixer-test_write_invalid_0_27 pass
7836 00:57:24.164319 alsa_mixer-test_event_missing_0_27 pass
7837 00:57:24.167693 alsa_mixer-test_event_spurious_0_27 pass
7838 00:57:24.170966 alsa_mixer-test_get_value_0_26 pass
7839 00:57:24.171388 alsa_mixer-test_name_0_26 pass
7840 00:57:24.177439 alsa_mixer-test_write_default_0_26 pass
7841 00:57:24.181020 alsa_mixer-test_write_valid_0_26 pass
7842 00:57:24.184267 alsa_mixer-test_write_invalid_0_26 pass
7843 00:57:24.187501 alsa_mixer-test_event_missing_0_26 pass
7844 00:57:24.190722 alsa_mixer-test_event_spurious_0_26 pass
7845 00:57:24.193994 alsa_mixer-test_get_value_0_25 pass
7846 00:57:24.197483 alsa_mixer-test_name_0_25 pass
7847 00:57:24.200802 alsa_mixer-test_write_default_0_25 pass
7848 00:57:24.204122 alsa_mixer-test_write_valid_0_25 pass
7849 00:57:24.207247 alsa_mixer-test_write_invalid_0_25 pass
7850 00:57:24.210432 alsa_mixer-test_event_missing_0_25 pass
7851 00:57:24.213957 alsa_mixer-test_event_spurious_0_25 pass
7852 00:57:24.217243 alsa_mixer-test_get_value_0_24 pass
7853 00:57:24.220697 alsa_mixer-test_name_0_24 pass
7854 00:57:24.223782 alsa_mixer-test_write_default_0_24 pass
7855 00:57:24.227195 alsa_mixer-test_write_valid_0_24 pass
7856 00:57:24.230966 alsa_mixer-test_write_invalid_0_24 pass
7857 00:57:24.233747 alsa_mixer-test_event_missing_0_24 pass
7858 00:57:24.236990 alsa_mixer-test_event_spurious_0_24 pass
7859 00:57:24.240326 alsa_mixer-test_get_value_0_23 pass
7860 00:57:24.243837 alsa_mixer-test_name_0_23 pass
7861 00:57:24.246995 alsa_mixer-test_write_default_0_23 pass
7862 00:57:24.250324 alsa_mixer-test_write_valid_0_23 pass
7863 00:57:24.253625 alsa_mixer-test_write_invalid_0_23 pass
7864 00:57:24.257131 alsa_mixer-test_event_missing_0_23 pass
7865 00:57:24.260736 alsa_mixer-test_event_spurious_0_23 pass
7866 00:57:24.263878 alsa_mixer-test_get_value_0_22 pass
7867 00:57:24.267337 alsa_mixer-test_name_0_22 pass
7868 00:57:24.270295 alsa_mixer-test_write_default_0_22 pass
7869 00:57:24.273676 alsa_mixer-test_write_valid_0_22 pass
7870 00:57:24.277109 alsa_mixer-test_write_invalid_0_22 pass
7871 00:57:24.280447 alsa_mixer-test_event_missing_0_22 pass
7872 00:57:24.284118 alsa_mixer-test_event_spurious_0_22 pass
7873 00:57:24.287150 alsa_mixer-test_get_value_0_21 pass
7874 00:57:24.290631 alsa_mixer-test_name_0_21 fail
7875 00:57:24.293697 alsa_mixer-test_write_default_0_21 pass
7876 00:57:24.297167 alsa_mixer-test_write_valid_0_21 pass
7877 00:57:24.300248 alsa_mixer-test_write_invalid_0_21 pass
7878 00:57:24.303725 alsa_mixer-test_event_missing_0_21 pass
7879 00:57:24.307022 alsa_mixer-test_event_spurious_0_21 pass
7880 00:57:24.310574 alsa_mixer-test_get_value_0_20 pass
7881 00:57:24.313762 alsa_mixer-test_name_0_20 fail
7882 00:57:24.317208 alsa_mixer-test_write_default_0_20 pass
7883 00:57:24.320340 alsa_mixer-test_write_valid_0_20 pass
7884 00:57:24.323650 alsa_mixer-test_write_invalid_0_20 pass
7885 00:57:24.326951 alsa_mixer-test_event_missing_0_20 pass
7886 00:57:24.333709 alsa_mixer-test_event_spurious_0_20 pass
7887 00:57:24.336895 alsa_mixer-test_get_value_0_19 pass
7888 00:57:24.337283 alsa_mixer-test_name_0_19 fail
7889 00:57:24.340417 alsa_mixer-test_write_default_0_19 pass
7890 00:57:24.343904 alsa_mixer-test_write_valid_0_19 pass
7891 00:57:24.350089 alsa_mixer-test_write_invalid_0_19 pass
7892 00:57:24.353636 alsa_mixer-test_event_missing_0_19 pass
7893 00:57:24.357000 alsa_mixer-test_event_spurious_0_19 pass
7894 00:57:24.360587 alsa_mixer-test_get_value_0_18 pass
7895 00:57:24.360975 alsa_mixer-test_name_0_18 fail
7896 00:57:24.367028 alsa_mixer-test_write_default_0_18 pass
7897 00:57:24.370308 alsa_mixer-test_write_valid_0_18 pass
7898 00:57:24.373998 alsa_mixer-test_write_invalid_0_18 pass
7899 00:57:24.377577 alsa_mixer-test_event_missing_0_18 pass
7900 00:57:24.380506 alsa_mixer-test_event_spurious_0_18 pass
7901 00:57:24.384092 alsa_mixer-test_get_value_0_17 pass
7902 00:57:24.386837 alsa_mixer-test_name_0_17 fail
7903 00:57:24.390341 alsa_mixer-test_write_default_0_17 pass
7904 00:57:24.393734 alsa_mixer-test_write_valid_0_17 pass
7905 00:57:24.397305 alsa_mixer-test_write_invalid_0_17 pass
7906 00:57:24.400619 alsa_mixer-test_event_missing_0_17 pass
7907 00:57:24.403696 alsa_mixer-test_event_spurious_0_17 pass
7908 00:57:24.407500 alsa_mixer-test_get_value_0_16 pass
7909 00:57:24.410752 alsa_mixer-test_name_0_16 fail
7910 00:57:24.413907 alsa_mixer-test_write_default_0_16 pass
7911 00:57:24.417133 alsa_mixer-test_write_valid_0_16 pass
7912 00:57:24.420132 alsa_mixer-test_write_invalid_0_16 pass
7913 00:57:24.423739 alsa_mixer-test_event_missing_0_16 pass
7914 00:57:24.427173 alsa_mixer-test_event_spurious_0_16 pass
7915 00:57:24.430312 alsa_mixer-test_get_value_0_15 pass
7916 00:57:24.433539 alsa_mixer-test_name_0_15 fail
7917 00:57:24.436995 alsa_mixer-test_write_default_0_15 pass
7918 00:57:24.440473 alsa_mixer-test_write_valid_0_15 pass
7919 00:57:24.443328 alsa_mixer-test_write_invalid_0_15 pass
7920 00:57:24.446910 alsa_mixer-test_event_missing_0_15 pass
7921 00:57:24.450320 alsa_mixer-test_event_spurious_0_15 pass
7922 00:57:24.453436 alsa_mixer-test_get_value_0_14 pass
7923 00:57:24.456921 alsa_mixer-test_name_0_14 fail
7924 00:57:24.460051 alsa_mixer-test_write_default_0_14 pass
7925 00:57:24.463289 alsa_mixer-test_write_valid_0_14 pass
7926 00:57:24.466853 alsa_mixer-test_write_invalid_0_14 pass
7927 00:57:24.470373 alsa_mixer-test_event_missing_0_14 pass
7928 00:57:24.473637 alsa_mixer-test_event_spurious_0_14 pass
7929 00:57:24.476731 alsa_mixer-test_get_value_0_13 pass
7930 00:57:24.480028 alsa_mixer-test_name_0_13 fail
7931 00:57:24.483248 alsa_mixer-test_write_default_0_13 pass
7932 00:57:24.486708 alsa_mixer-test_write_valid_0_13 pass
7933 00:57:24.490053 alsa_mixer-test_write_invalid_0_13 pass
7934 00:57:24.493270 alsa_mixer-test_event_missing_0_13 pass
7935 00:57:24.497016 alsa_mixer-test_event_spurious_0_13 pass
7936 00:57:24.500068 alsa_mixer-test_get_value_0_12 pass
7937 00:57:24.503411 alsa_mixer-test_name_0_12 fail
7938 00:57:24.506480 alsa_mixer-test_write_default_0_12 pass
7939 00:57:24.509797 alsa_mixer-test_write_valid_0_12 pass
7940 00:57:24.513172 alsa_mixer-test_write_invalid_0_12 pass
7941 00:57:24.516595 alsa_mixer-test_event_missing_0_12 pass
7942 00:57:24.523124 alsa_mixer-test_event_spurious_0_12 pass
7943 00:57:24.526683 alsa_mixer-test_get_value_0_11 pass
7944 00:57:24.527042 alsa_mixer-test_name_0_11 fail
7945 00:57:24.529693 alsa_mixer-test_write_default_0_11 pass
7946 00:57:24.533089 alsa_mixer-test_write_valid_0_11 pass
7947 00:57:24.539923 alsa_mixer-test_write_invalid_0_11 pass
7948 00:57:24.543303 alsa_mixer-test_event_missing_0_11 pass
7949 00:57:24.546625 alsa_mixer-test_event_spurious_0_11 pass
7950 00:57:24.550101 alsa_mixer-test_get_value_0_10 pass
7951 00:57:24.550520 alsa_mixer-test_name_0_10 fail
7952 00:57:24.556542 alsa_mixer-test_write_default_0_10 pass
7953 00:57:24.559893 alsa_mixer-test_write_valid_0_10 pass
7954 00:57:24.563124 alsa_mixer-test_write_invalid_0_10 pass
7955 00:57:24.566303 alsa_mixer-test_event_missing_0_10 pass
7956 00:57:24.569590 alsa_mixer-test_event_spurious_0_10 pass
7957 00:57:24.573052 alsa_mixer-test_get_value_0_9 pass
7958 00:57:24.576720 alsa_mixer-test_name_0_9 fail
7959 00:57:24.579691 alsa_mixer-test_write_default_0_9 pass
7960 00:57:24.583154 alsa_mixer-test_write_valid_0_9 pass
7961 00:57:24.586545 alsa_mixer-test_write_invalid_0_9 pass
7962 00:57:24.589827 alsa_mixer-test_event_missing_0_9 pass
7963 00:57:24.593147 alsa_mixer-test_event_spurious_0_9 pass
7964 00:57:24.596389 alsa_mixer-test_get_value_0_8 pass
7965 00:57:24.596783 alsa_mixer-test_name_0_8 fail
7966 00:57:24.603085 alsa_mixer-test_write_default_0_8 pass
7967 00:57:24.606477 alsa_mixer-test_write_valid_0_8 pass
7968 00:57:24.609908 alsa_mixer-test_write_invalid_0_8 pass
7969 00:57:24.613265 alsa_mixer-test_event_missing_0_8 pass
7970 00:57:24.616363 alsa_mixer-test_event_spurious_0_8 pass
7971 00:57:24.619713 alsa_mixer-test_get_value_0_7 pass
7972 00:57:24.622971 alsa_mixer-test_name_0_7 fail
7973 00:57:24.626136 alsa_mixer-test_write_default_0_7 pass
7974 00:57:24.629416 alsa_mixer-test_write_valid_0_7 pass
7975 00:57:24.632832 alsa_mixer-test_write_invalid_0_7 pass
7976 00:57:24.635846 alsa_mixer-test_event_missing_0_7 pass
7977 00:57:24.639440 alsa_mixer-test_event_spurious_0_7 pass
7978 00:57:24.642235 alsa_mixer-test_get_value_0_6 pass
7979 00:57:24.645873 alsa_mixer-test_name_0_6 fail
7980 00:57:24.649069 alsa_mixer-test_write_default_0_6 pass
7981 00:57:24.652562 alsa_mixer-test_write_valid_0_6 pass
7982 00:57:24.656002 alsa_mixer-test_write_invalid_0_6 pass
7983 00:57:24.659391 alsa_mixer-test_event_missing_0_6 pass
7984 00:57:24.662428 alsa_mixer-test_event_spurious_0_6 pass
7985 00:57:24.665888 alsa_mixer-test_get_value_0_5 pass
7986 00:57:24.665977 alsa_mixer-test_name_0_5 pass
7987 00:57:24.672448 alsa_mixer-test_write_default_0_5 pass
7988 00:57:24.675676 alsa_mixer-test_write_valid_0_5 pass
7989 00:57:24.679016 alsa_mixer-test_write_invalid_0_5 pass
7990 00:57:24.682281 alsa_mixer-test_event_missing_0_5 fail
7991 00:57:24.685653 alsa_mixer-test_event_spurious_0_5 pass
7992 00:57:24.689114 alsa_mixer-test_get_value_0_4 pass
7993 00:57:24.689223 alsa_mixer-test_name_0_4 pass
7994 00:57:24.695632 alsa_mixer-test_write_default_0_4 pass
7995 00:57:24.698800 alsa_mixer-test_write_valid_0_4 pass
7996 00:57:24.702252 alsa_mixer-test_write_invalid_0_4 pass
7997 00:57:24.705467 alsa_mixer-test_event_missing_0_4 fail
7998 00:57:24.708962 alsa_mixer-test_event_spurious_0_4 pass
7999 00:57:24.712276 alsa_mixer-test_get_value_0_3 pass
8000 00:57:24.712484 alsa_mixer-test_name_0_3 pass
8001 00:57:24.718783 alsa_mixer-test_write_default_0_3 pass
8002 00:57:24.722186 alsa_mixer-test_write_valid_0_3 pass
8003 00:57:24.725580 alsa_mixer-test_write_invalid_0_3 pass
8004 00:57:24.728846 alsa_mixer-test_event_missing_0_3 fail
8005 00:57:24.732180 alsa_mixer-test_event_spurious_0_3 pass
8006 00:57:24.735550 alsa_mixer-test_get_value_0_2 pass
8007 00:57:24.735937 alsa_mixer-test_name_0_2 pass
8008 00:57:24.742271 alsa_mixer-test_write_default_0_2 pass
8009 00:57:24.745427 alsa_mixer-test_write_valid_0_2 pass
8010 00:57:24.748844 alsa_mixer-test_write_invalid_0_2 pass
8011 00:57:24.752468 alsa_mixer-test_event_missing_0_2 fail
8012 00:57:24.755804 alsa_mixer-test_event_spurious_0_2 pass
8013 00:57:24.759018 alsa_mixer-test_get_value_0_1 pass
8014 00:57:24.759411 alsa_mixer-test_name_0_1 pass
8015 00:57:24.762392 alsa_mixer-test_write_default_0_1 pass
8016 00:57:24.765813 alsa_mixer-test_write_valid_0_1 pass
8017 00:57:24.772137 alsa_mixer-test_write_invalid_0_1 pass
8018 00:57:24.775472 alsa_mixer-test_event_missing_0_1 fail
8019 00:57:24.779073 alsa_mixer-test_event_spurious_0_1 pass
8020 00:57:24.782273 alsa_mixer-test_get_value_0_0 pass
8021 00:57:24.782671 alsa_mixer-test_name_0_0 pass
8022 00:57:24.785598 alsa_mixer-test_write_default_0_0 pass
8023 00:57:24.788718 alsa_mixer-test_write_valid_0_0 pass
8024 00:57:24.795529 alsa_mixer-test_write_invalid_0_0 pass
8025 00:57:24.798797 alsa_mixer-test_event_missing_0_0 fail
8026 00:57:24.802131 alsa_mixer-test_event_spurious_0_0 pass
8027 00:57:24.802578 alsa_mixer-test pass
8028 00:57:24.808889 + ../../utils/send-to-lava.sh ./output/result.txt
8029 00:57:24.812251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
8030 00:57:24.813245 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
8032 00:57:24.818682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass>
8033 00:57:24.819316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass
8035 00:57:24.825264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass>
8036 00:57:24.825931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass
8038 00:57:24.832655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass
8040 00:57:24.835288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass>
8041 00:57:24.866612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass>
8042 00:57:24.867320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass
8044 00:57:24.919089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass>
8045 00:57:24.919761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass
8047 00:57:24.973868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass>
8048 00:57:24.974119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass
8050 00:57:25.025493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass>
8051 00:57:25.025812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass
8053 00:57:25.078576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass>
8054 00:57:25.078913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass
8056 00:57:25.127440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass>
8057 00:57:25.127900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass
8059 00:57:25.187373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass>
8060 00:57:25.188020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass
8062 00:57:25.244477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass>
8063 00:57:25.245154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass
8065 00:57:25.302007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass>
8066 00:57:25.302908 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass
8068 00:57:25.358841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass>
8069 00:57:25.359588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass
8071 00:57:25.417518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass>
8072 00:57:25.418188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass
8074 00:57:25.475511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass>
8075 00:57:25.476198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass
8077 00:57:25.531532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass>
8078 00:57:25.532192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass
8080 00:57:25.591559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass>
8081 00:57:25.592225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass
8083 00:57:25.646410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass>
8084 00:57:25.647107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass
8086 00:57:25.703288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass>
8087 00:57:25.704040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass
8089 00:57:25.753867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass>
8090 00:57:25.754801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass
8092 00:57:25.808031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass>
8093 00:57:25.808818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass
8095 00:57:25.867177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass>
8096 00:57:25.868040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass
8098 00:57:25.915785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass>
8099 00:57:25.916466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass
8101 00:57:25.972258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass>
8102 00:57:25.973015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass
8104 00:57:26.018573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass>
8105 00:57:26.019208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass
8107 00:57:26.071093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass>
8108 00:57:26.071781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass
8110 00:57:26.119637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass>
8111 00:57:26.119926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass
8113 00:57:26.162774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass>
8114 00:57:26.163074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass
8116 00:57:26.204801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass>
8117 00:57:26.205095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass
8119 00:57:26.248431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass>
8120 00:57:26.248724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass
8122 00:57:26.296215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass>
8123 00:57:26.296541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass
8125 00:57:26.341280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass>
8126 00:57:26.341575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass
8128 00:57:26.387547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass>
8129 00:57:26.387841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass
8131 00:57:26.432629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass>
8132 00:57:26.432938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass
8134 00:57:26.476766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass>
8135 00:57:26.477062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass
8137 00:57:26.520400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass>
8138 00:57:26.520775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass
8140 00:57:26.559921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass>
8141 00:57:26.560290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass
8143 00:57:26.607779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass>
8144 00:57:26.608078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass
8146 00:57:26.652930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail>
8147 00:57:26.653228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail
8149 00:57:26.697521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass>
8150 00:57:26.697820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass
8152 00:57:26.742007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass>
8153 00:57:26.742286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass
8155 00:57:26.794504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail>
8156 00:57:26.794770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail
8158 00:57:26.840180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass>
8159 00:57:26.840480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass
8161 00:57:26.882470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass>
8162 00:57:26.882768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass
8164 00:57:26.938483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass>
8165 00:57:26.939216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass
8167 00:57:26.999358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass>
8168 00:57:27.000112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass
8170 00:57:27.053736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass>
8171 00:57:27.054435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass
8173 00:57:27.107484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass>
8174 00:57:27.108150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass
8176 00:57:27.159841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass>
8177 00:57:27.160529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass
8179 00:57:27.211948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass>
8180 00:57:27.212581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass
8182 00:57:27.260583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass>
8183 00:57:27.261270 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass
8185 00:57:27.314321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass>
8186 00:57:27.315018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass
8188 00:57:27.367006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail>
8189 00:57:27.367645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail
8191 00:57:27.417584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass>
8192 00:57:27.418239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass
8194 00:57:27.470374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass>
8195 00:57:27.471017 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass
8197 00:57:27.522987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass>
8198 00:57:27.523632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass
8200 00:57:27.572136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass>
8201 00:57:27.572453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass
8203 00:57:27.618284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass>
8204 00:57:27.619061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass
8206 00:57:27.675571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass>
8207 00:57:27.675824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass
8209 00:57:27.727590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail>
8210 00:57:27.727854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail
8212 00:57:27.777351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass>
8213 00:57:27.777809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass
8215 00:57:27.827076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass>
8216 00:57:27.827734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass
8218 00:57:27.879109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass>
8219 00:57:27.879917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass
8221 00:57:27.929285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass>
8222 00:57:27.929575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass
8224 00:57:27.969566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass>
8225 00:57:27.969844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass
8227 00:57:28.025255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass>
8228 00:57:28.025906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass
8230 00:57:28.077983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass>
8231 00:57:28.078320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass
8233 00:57:28.135000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass>
8234 00:57:28.135797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass
8236 00:57:28.188504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass>
8237 00:57:28.188777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass
8239 00:57:28.241938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass>
8240 00:57:28.242249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass
8242 00:57:28.292422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass>
8243 00:57:28.292726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass
8245 00:57:28.341048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass>
8246 00:57:28.341349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass
8248 00:57:28.393257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass>
8249 00:57:28.393610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass
8251 00:57:28.451007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass>
8252 00:57:28.451748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass
8254 00:57:28.502773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass>
8255 00:57:28.503046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass
8257 00:57:28.510014 <6>[ 37.960899] vaux18: disabling
8258 00:57:28.513834 <6>[ 37.964704] vio28: disabling
8259 00:57:28.562008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass>
8260 00:57:28.562319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass
8262 00:57:28.611823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass>
8263 00:57:28.612162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass
8265 00:57:28.662290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass>
8266 00:57:28.663108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass
8268 00:57:28.719862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass>
8269 00:57:28.720546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass
8271 00:57:28.778559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip>
8272 00:57:28.779217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip
8274 00:57:28.841039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip>
8275 00:57:28.841790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip
8277 00:57:28.895827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip>
8278 00:57:28.896466 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip
8280 00:57:28.948551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass>
8281 00:57:28.949201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass
8283 00:57:28.997310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass>
8284 00:57:28.997959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass
8286 00:57:29.052042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass>
8287 00:57:29.052742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass
8289 00:57:29.102540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass>
8290 00:57:29.103203 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass
8292 00:57:29.157116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass>
8293 00:57:29.157939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass
8295 00:57:29.218853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass>
8296 00:57:29.219649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass
8298 00:57:29.274872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail>
8299 00:57:29.275642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail
8301 00:57:29.333634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail>
8302 00:57:29.334302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail
8304 00:57:29.388880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass>
8305 00:57:29.389539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass
8307 00:57:29.439934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass>
8308 00:57:29.440570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass
8310 00:57:29.492032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass>
8311 00:57:29.492691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass
8313 00:57:29.547263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass>
8314 00:57:29.547893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass
8316 00:57:29.599864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass>
8317 00:57:29.600533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass
8319 00:57:29.654889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass>
8320 00:57:29.655539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass
8322 00:57:29.711630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass>
8323 00:57:29.712283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass
8325 00:57:29.770105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass>
8326 00:57:29.770915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass
8328 00:57:29.831162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail>
8329 00:57:29.831935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail
8331 00:57:29.887635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass>
8332 00:57:29.888292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass
8334 00:57:29.946074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail>
8335 00:57:29.946757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail
8337 00:57:29.999559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail>
8338 00:57:30.000217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail
8340 00:57:30.053576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail>
8341 00:57:30.054354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail
8343 00:57:30.105009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass>
8344 00:57:30.105658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass
8346 00:57:30.160758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass>
8347 00:57:30.161584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass
8349 00:57:30.219800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail>
8350 00:57:30.220556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail
8352 00:57:30.272584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass>
8353 00:57:30.273290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass
8355 00:57:30.338106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail>
8356 00:57:30.338790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail
8358 00:57:30.393194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail>
8359 00:57:30.393861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail
8361 00:57:30.445106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail>
8362 00:57:30.445743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail
8364 00:57:30.500030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass>
8365 00:57:30.500672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass
8367 00:57:30.552369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass>
8368 00:57:30.553149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass
8370 00:57:30.609190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail>
8371 00:57:30.609898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail
8373 00:57:30.661481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass>
8374 00:57:30.662140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass
8376 00:57:30.724171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail>
8377 00:57:30.724825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail
8379 00:57:30.781534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail>
8380 00:57:30.782346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail
8382 00:57:30.843951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail>
8383 00:57:30.844734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail
8385 00:57:30.903154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass>
8386 00:57:30.904098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass
8388 00:57:30.963940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass>
8389 00:57:30.964710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass
8391 00:57:31.016731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass>
8392 00:57:31.017380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass
8394 00:57:31.067694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail>
8395 00:57:31.068377 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail
8397 00:57:31.127885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass>
8398 00:57:31.128671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass
8400 00:57:31.183760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass>
8401 00:57:31.184462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass
8403 00:57:31.241208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass>
8404 00:57:31.241982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass
8406 00:57:31.298572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass>
8407 00:57:31.299347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass
8409 00:57:31.354294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass>
8410 00:57:31.354948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass
8412 00:57:31.415898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass>
8413 00:57:31.416671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass
8415 00:57:31.476422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail>
8416 00:57:31.477307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail
8418 00:57:31.534470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass>
8419 00:57:31.535170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass
8421 00:57:31.589760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass>
8422 00:57:31.590442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass
8424 00:57:31.647617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass>
8425 00:57:31.648506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass
8427 00:57:31.701614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass>
8428 00:57:31.702307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass
8430 00:57:31.758692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass>
8431 00:57:31.759504 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass
8433 00:57:31.810182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass>
8434 00:57:31.810880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass
8436 00:57:31.857381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail>
8437 00:57:31.858025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail
8439 00:57:31.911432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass>
8440 00:57:31.912085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass
8442 00:57:31.962942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass>
8443 00:57:31.963590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass
8445 00:57:32.013899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass>
8446 00:57:32.014573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass
8448 00:57:32.066124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass>
8449 00:57:32.066816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass
8451 00:57:32.116162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass>
8452 00:57:32.116425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass
8454 00:57:32.165892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass>
8455 00:57:32.166149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass
8457 00:57:32.208942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail>
8458 00:57:32.209243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail
8460 00:57:32.256580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass>
8461 00:57:32.256909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass
8463 00:57:32.308405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass>
8464 00:57:32.309083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass
8466 00:57:32.361551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass>
8467 00:57:32.362206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass
8469 00:57:32.416265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass>
8470 00:57:32.416979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass
8472 00:57:32.468236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass>
8473 00:57:32.468950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass
8475 00:57:32.520481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass>
8476 00:57:32.521135 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass
8478 00:57:32.575543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail>
8479 00:57:32.576313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail
8481 00:57:32.632879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass>
8482 00:57:32.633529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass
8484 00:57:32.685523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass>
8485 00:57:32.686184 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass
8487 00:57:32.740031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass>
8488 00:57:32.740764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass
8490 00:57:32.791483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass>
8491 00:57:32.792190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass
8493 00:57:32.843610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass>
8494 00:57:32.844249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass
8496 00:57:32.896621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass>
8497 00:57:32.897269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass
8499 00:57:32.948298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail>
8500 00:57:32.948934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail
8502 00:57:33.011761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass>
8503 00:57:33.012512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass
8505 00:57:33.070057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass>
8506 00:57:33.070850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass
8508 00:57:33.130566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass>
8509 00:57:33.131356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass
8511 00:57:33.186240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass>
8512 00:57:33.187032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass
8514 00:57:33.244924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass>
8515 00:57:33.245670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass
8517 00:57:33.298283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass>
8518 00:57:33.298971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass
8520 00:57:33.348924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail>
8521 00:57:33.349553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail
8523 00:57:33.407050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass>
8524 00:57:33.407703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass
8526 00:57:33.464821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass>
8527 00:57:33.465452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass
8529 00:57:33.518028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass>
8530 00:57:33.518706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass
8532 00:57:33.571265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass>
8533 00:57:33.571888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass
8535 00:57:33.624048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass>
8536 00:57:33.624692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass
8538 00:57:33.673597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass>
8539 00:57:33.673886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass
8541 00:57:33.719041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail>
8542 00:57:33.719569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail
8544 00:57:33.774104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass>
8545 00:57:33.774976 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass
8547 00:57:33.833247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass>
8548 00:57:33.834003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass
8550 00:57:33.881942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass>
8551 00:57:33.882625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass
8553 00:57:33.930201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass>
8554 00:57:33.930489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass
8556 00:57:33.976009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass>
8557 00:57:33.976283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass
8559 00:57:34.027036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass>
8560 00:57:34.027688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass
8562 00:57:34.074930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail>
8563 00:57:34.075197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail
8565 00:57:34.125278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass>
8566 00:57:34.125536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass
8568 00:57:34.173361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass>
8569 00:57:34.173636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass
8571 00:57:34.221211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass>
8572 00:57:34.221477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass
8574 00:57:34.268261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass>
8575 00:57:34.268510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass
8577 00:57:34.316910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass>
8578 00:57:34.317231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass
8580 00:57:34.364911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass>
8581 00:57:34.365575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass
8583 00:57:34.412124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail>
8584 00:57:34.412762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail
8586 00:57:34.466773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass>
8587 00:57:34.467405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass
8589 00:57:34.515983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass>
8590 00:57:34.516612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass
8592 00:57:34.576059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass>
8593 00:57:34.576808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass
8595 00:57:34.628503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass>
8596 00:57:34.628798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass
8598 00:57:34.674204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass>
8599 00:57:34.674555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass
8601 00:57:34.725641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass>
8602 00:57:34.726322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass
8604 00:57:34.773319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail>
8605 00:57:34.773574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail
8607 00:57:34.826182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass>
8608 00:57:34.826957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass
8610 00:57:34.877887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass>
8611 00:57:34.878157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass
8613 00:57:34.927900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass>
8614 00:57:34.928149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass
8616 00:57:34.971148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass>
8617 00:57:34.971443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass
8619 00:57:35.021928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass>
8620 00:57:35.022196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass
8622 00:57:35.077088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass>
8623 00:57:35.077773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass
8625 00:57:35.133452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail>
8626 00:57:35.134264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail
8628 00:57:35.187095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass>
8629 00:57:35.187363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass
8631 00:57:35.234197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass>
8632 00:57:35.234501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass
8634 00:57:35.278523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass>
8635 00:57:35.278785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass
8637 00:57:35.330706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass>
8638 00:57:35.331474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass
8640 00:57:35.383357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass>
8641 00:57:35.383629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass
8643 00:57:35.434914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass>
8644 00:57:35.435686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass
8646 00:57:35.492641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail>
8647 00:57:35.492951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail
8649 00:57:35.545587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass>
8650 00:57:35.545891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass
8652 00:57:35.597416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass>
8653 00:57:35.598201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass
8655 00:57:35.645703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass>
8656 00:57:35.645963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass
8658 00:57:35.694776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass>
8659 00:57:35.695095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass
8661 00:57:35.744291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass>
8662 00:57:35.744969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass
8664 00:57:35.799947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass>
8665 00:57:35.800678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass
8667 00:57:35.847887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail>
8668 00:57:35.848213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail
8670 00:57:35.900804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass>
8671 00:57:35.901130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass
8673 00:57:35.954299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass>
8674 00:57:35.954999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass
8676 00:57:36.001764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass>
8677 00:57:36.002036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass
8679 00:57:36.055399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass>
8680 00:57:36.056146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass
8682 00:57:36.109810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass>
8683 00:57:36.110647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass
8685 00:57:36.162196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass>
8686 00:57:36.162555 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass
8688 00:57:36.204725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail>
8689 00:57:36.205000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail
8691 00:57:36.258052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass>
8692 00:57:36.258405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass
8694 00:57:36.309196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass>
8695 00:57:36.309514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass
8697 00:57:36.364845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass>
8698 00:57:36.365619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass
8700 00:57:36.418646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass>
8701 00:57:36.418909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass
8703 00:57:36.466329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass>
8704 00:57:36.466646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass
8706 00:57:36.516345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass>
8707 00:57:36.516622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass
8709 00:57:36.565118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail>
8710 00:57:36.565773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail
8712 00:57:36.620314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass>
8713 00:57:36.620579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass
8715 00:57:36.670560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass>
8716 00:57:36.671285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass
8718 00:57:36.722600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass>
8719 00:57:36.723250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass
8721 00:57:36.772958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass>
8722 00:57:36.773221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass
8724 00:57:36.819813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass>
8725 00:57:36.820074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass
8727 00:57:36.868204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass
8729 00:57:36.871177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass>
8730 00:57:36.917067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail>
8731 00:57:36.917325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail
8733 00:57:36.972977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass>
8734 00:57:36.973226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass
8736 00:57:37.021136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass>
8737 00:57:37.021390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass
8739 00:57:37.071553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass>
8740 00:57:37.071854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass
8742 00:57:37.115574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass>
8743 00:57:37.115909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass
8745 00:57:37.167484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass>
8746 00:57:37.168132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass
8748 00:57:37.218541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass>
8749 00:57:37.218814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass
8751 00:57:37.269929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail>
8752 00:57:37.270615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail
8754 00:57:37.320845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass>
8755 00:57:37.321179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass
8757 00:57:37.371491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass>
8758 00:57:37.371807 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass
8760 00:57:37.416394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass>
8761 00:57:37.416664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass
8763 00:57:37.463900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass>
8764 00:57:37.464179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass
8766 00:57:37.511171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass>
8767 00:57:37.511478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass
8769 00:57:37.558866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass>
8770 00:57:37.559619 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass
8772 00:57:37.605916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail>
8773 00:57:37.606601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail
8775 00:57:37.657471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass>
8776 00:57:37.657722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass
8778 00:57:37.703797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass>
8779 00:57:37.704095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass
8781 00:57:37.754059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass>
8782 00:57:37.754820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass
8784 00:57:37.808454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass>
8785 00:57:37.809179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass
8787 00:57:37.858737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass>
8788 00:57:37.859069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass
8790 00:57:37.904121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass>
8791 00:57:37.904378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass
8793 00:57:37.952145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail>
8794 00:57:37.952455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail
8796 00:57:38.010863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass>
8797 00:57:38.011232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass
8799 00:57:38.066176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass>
8800 00:57:38.066496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass
8802 00:57:38.114123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass>
8803 00:57:38.114437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass
8805 00:57:38.159780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass>
8806 00:57:38.160030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass
8808 00:57:38.215243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass>
8809 00:57:38.216025 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass
8811 00:57:38.263716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass>
8812 00:57:38.263971 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass
8814 00:57:38.312487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail>
8815 00:57:38.312792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail
8817 00:57:38.366331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass>
8818 00:57:38.366588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass
8820 00:57:38.414678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass>
8821 00:57:38.414983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass
8823 00:57:38.458581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass>
8824 00:57:38.458831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass
8826 00:57:38.503119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass>
8827 00:57:38.503368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass
8829 00:57:38.549953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass>
8830 00:57:38.550235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass
8832 00:57:38.599621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass>
8833 00:57:38.599920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass
8835 00:57:38.643295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail>
8836 00:57:38.643725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail
8838 00:57:38.699880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass>
8839 00:57:38.700170 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass
8841 00:57:38.745015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass>
8842 00:57:38.745360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass
8844 00:57:38.790933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass>
8845 00:57:38.791202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass
8847 00:57:38.836508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass>
8848 00:57:38.836776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass
8850 00:57:38.884473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass>
8851 00:57:38.885124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass
8853 00:57:38.938071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass>
8854 00:57:38.938742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass
8856 00:57:38.983351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail>
8857 00:57:38.983643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail
8859 00:57:39.036548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass>
8860 00:57:39.036813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass
8862 00:57:39.084970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass>
8863 00:57:39.085218 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass
8865 00:57:39.132394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass>
8866 00:57:39.132645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass
8868 00:57:39.184243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass>
8869 00:57:39.184992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass
8871 00:57:39.236811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass>
8872 00:57:39.237144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass
8874 00:57:39.285414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass>
8875 00:57:39.285714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass
8877 00:57:39.327253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail>
8878 00:57:39.327569 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail
8880 00:57:39.386497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass>
8881 00:57:39.386763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass
8883 00:57:39.437750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass>
8884 00:57:39.438086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass
8886 00:57:39.486746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass>
8887 00:57:39.487146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass
8889 00:57:39.539538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass>
8890 00:57:39.540264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass
8892 00:57:39.593108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass>
8893 00:57:39.593477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass
8895 00:57:39.643930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass>
8896 00:57:39.644582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass
8898 00:57:39.693794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail>
8899 00:57:39.694103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail
8901 00:57:39.746125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass>
8902 00:57:39.746476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass
8904 00:57:39.797574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass>
8905 00:57:39.797904 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass
8907 00:57:39.850811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass>
8908 00:57:39.851124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass
8910 00:57:39.902157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass>
8911 00:57:39.902482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass
8913 00:57:39.946390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass>
8914 00:57:39.946658 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass
8916 00:57:39.994057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass>
8917 00:57:39.994310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass
8919 00:57:40.035517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail>
8920 00:57:40.036181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail
8922 00:57:40.084406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass>
8923 00:57:40.084660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass
8925 00:57:40.129929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass>
8926 00:57:40.130248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass
8928 00:57:40.170793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass>
8929 00:57:40.171046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass
8931 00:57:40.210145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass>
8932 00:57:40.210421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass
8934 00:57:40.251909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass>
8935 00:57:40.252160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass
8937 00:57:40.295051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass>
8938 00:57:40.295322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass
8940 00:57:40.335602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail>
8941 00:57:40.335864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail
8943 00:57:40.383650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass>
8944 00:57:40.383899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass
8946 00:57:40.440499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass>
8947 00:57:40.441278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass
8949 00:57:40.495354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass>
8950 00:57:40.496059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass
8952 00:57:40.548183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass>
8953 00:57:40.548963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass
8955 00:57:40.607654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass>
8956 00:57:40.608342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass
8958 00:57:40.660308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass>
8959 00:57:40.660941 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass
8961 00:57:40.709611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail>
8962 00:57:40.710284 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail
8964 00:57:40.767208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass>
8965 00:57:40.767842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass
8967 00:57:40.823848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass>
8968 00:57:40.824489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass
8970 00:57:40.878860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass>
8971 00:57:40.879497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass
8973 00:57:40.938772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass>
8974 00:57:40.939409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass
8976 00:57:40.999302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass>
8977 00:57:40.999938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass
8979 00:57:41.053369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass>
8980 00:57:41.054001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass
8982 00:57:41.108244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail>
8983 00:57:41.108881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail
8985 00:57:41.169520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass>
8986 00:57:41.170325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass
8988 00:57:41.228353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass>
8989 00:57:41.229109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass
8991 00:57:41.284607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass>
8992 00:57:41.285212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass
8994 00:57:41.332206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass>
8995 00:57:41.332477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass
8997 00:57:41.380020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass>
8998 00:57:41.380657 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass
9000 00:57:41.438325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass>
9001 00:57:41.439100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass
9003 00:57:41.491141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail>
9004 00:57:41.491791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail
9006 00:57:41.553141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass>
9007 00:57:41.553801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass
9009 00:57:41.608753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass>
9010 00:57:41.609524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass
9012 00:57:41.667963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass>
9013 00:57:41.668621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass
9015 00:57:41.728150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass>
9016 00:57:41.728805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass
9018 00:57:41.780251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass>
9019 00:57:41.780501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass
9021 00:57:41.829276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass>
9022 00:57:41.829527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass
9024 00:57:41.872260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail>
9025 00:57:41.872586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail
9027 00:57:41.924723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass>
9028 00:57:41.925015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass
9030 00:57:41.972275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass>
9031 00:57:41.972611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass
9033 00:57:42.022850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass>
9034 00:57:42.023260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass
9036 00:57:42.076697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass>
9037 00:57:42.077332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass
9039 00:57:42.133474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass>
9040 00:57:42.134113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass
9042 00:57:42.183865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass>
9043 00:57:42.184493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass
9045 00:57:42.236962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail>
9046 00:57:42.237689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail
9048 00:57:42.297936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass>
9049 00:57:42.298682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass
9051 00:57:42.347010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass>
9052 00:57:42.347263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass
9054 00:57:42.398778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass>
9055 00:57:42.399432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass
9057 00:57:42.443653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass>
9058 00:57:42.443909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass
9060 00:57:42.487182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass>
9061 00:57:42.487433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass
9063 00:57:42.533169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass>
9064 00:57:42.533447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass
9066 00:57:42.575340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail>
9067 00:57:42.575735 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail
9069 00:57:42.621474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass>
9070 00:57:42.621741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass
9072 00:57:42.672467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass>
9073 00:57:42.672770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass
9075 00:57:42.721855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass>
9076 00:57:42.722123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass
9078 00:57:42.778744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass>
9079 00:57:42.779513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass
9081 00:57:42.836546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass>
9082 00:57:42.837200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass
9084 00:57:42.887763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass>
9085 00:57:42.888014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass
9087 00:57:42.931804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail>
9088 00:57:42.932128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail
9090 00:57:42.991094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass>
9091 00:57:42.991426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass
9093 00:57:43.043918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass>
9094 00:57:43.044716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass
9096 00:57:43.098627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass>
9097 00:57:43.098964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass
9099 00:57:43.148457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass>
9100 00:57:43.149246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass
9102 00:57:43.205316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass>
9103 00:57:43.205579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass
9105 00:57:43.259649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass>
9106 00:57:43.259947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass
9108 00:57:43.304241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail>
9109 00:57:43.304547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail
9111 00:57:43.354368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass>
9112 00:57:43.354756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass
9114 00:57:43.405744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass>
9115 00:57:43.406014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass
9117 00:57:43.456017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass>
9118 00:57:43.456405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass
9120 00:57:43.503567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass>
9121 00:57:43.504265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass
9123 00:57:43.558930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass>
9124 00:57:43.559570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass
9126 00:57:43.614750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass>
9127 00:57:43.615009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass
9129 00:57:43.654010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail>
9130 00:57:43.654265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail
9132 00:57:43.700568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass>
9133 00:57:43.700838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass
9135 00:57:43.747956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass>
9136 00:57:43.748255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass
9138 00:57:43.795129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass>
9139 00:57:43.795399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass
9141 00:57:43.847429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass>
9142 00:57:43.847762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass
9144 00:57:43.901364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass>
9145 00:57:43.901673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass
9147 00:57:43.953696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass>
9148 00:57:43.954032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass
9150 00:57:43.998328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail>
9151 00:57:43.998640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail
9153 00:57:44.052434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass>
9154 00:57:44.052688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass
9156 00:57:44.101327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass>
9157 00:57:44.101629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass
9159 00:57:44.149051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass>
9160 00:57:44.149796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass
9162 00:57:44.201073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass>
9163 00:57:44.201331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass
9165 00:57:44.250466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass>
9166 00:57:44.250732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass
9168 00:57:44.298330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass>
9169 00:57:44.298962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass
9171 00:57:44.345473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail>
9172 00:57:44.345868 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail
9174 00:57:44.397588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass>
9175 00:57:44.397851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass
9177 00:57:44.442914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass>
9178 00:57:44.443248 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass
9180 00:57:44.494611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass>
9181 00:57:44.494911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass
9183 00:57:44.541508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass>
9184 00:57:44.541849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass
9186 00:57:44.594133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass>
9187 00:57:44.595080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass
9189 00:57:44.649828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass>
9190 00:57:44.650612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass
9192 00:57:44.696871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail>
9193 00:57:44.697179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail
9195 00:57:44.747500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass>
9196 00:57:44.747840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass
9198 00:57:44.798171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass>
9199 00:57:44.799156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass
9201 00:57:44.855031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass>
9202 00:57:44.855691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass
9204 00:57:44.907549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass>
9205 00:57:44.907823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass
9207 00:57:44.956196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass>
9208 00:57:44.956464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass
9210 00:57:45.003148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass>
9211 00:57:45.003464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass
9213 00:57:45.054655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail>
9214 00:57:45.055285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail
9216 00:57:45.107605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass>
9217 00:57:45.108243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass
9219 00:57:45.161636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass>
9220 00:57:45.161895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass
9222 00:57:45.208732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass>
9223 00:57:45.208988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass
9225 00:57:45.254755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass>
9226 00:57:45.255077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass
9228 00:57:45.310200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass>
9229 00:57:45.310953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass
9231 00:57:45.368163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass>
9232 00:57:45.368804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass
9234 00:57:45.422277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail>
9235 00:57:45.422985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail
9237 00:57:45.477504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass>
9238 00:57:45.477803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass
9240 00:57:45.522828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass>
9241 00:57:45.523119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass
9243 00:57:45.571792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass>
9244 00:57:45.572096 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass
9246 00:57:45.622175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass>
9247 00:57:45.622483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass
9249 00:57:45.671469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass>
9250 00:57:45.671837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass
9252 00:57:45.721848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass>
9253 00:57:45.722101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass
9255 00:57:45.767433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail>
9256 00:57:45.767741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail
9258 00:57:45.820293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass>
9259 00:57:45.820575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass
9261 00:57:45.872597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass>
9262 00:57:45.873189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass
9264 00:57:45.928488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass>
9265 00:57:45.929177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass
9267 00:57:45.984256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass>
9268 00:57:45.984915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass
9270 00:57:46.038582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass>
9271 00:57:46.039225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass
9273 00:57:46.092136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass>
9274 00:57:46.092851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass
9276 00:57:46.143516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail>
9277 00:57:46.144201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail
9279 00:57:46.206058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass>
9280 00:57:46.206817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass
9282 00:57:46.261671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass>
9283 00:57:46.262371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass
9285 00:57:46.316104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass>
9286 00:57:46.316781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass
9288 00:57:46.372207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass>
9289 00:57:46.372871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass
9291 00:57:46.425002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass>
9292 00:57:46.425640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass
9294 00:57:46.487397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass>
9295 00:57:46.488162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass
9297 00:57:46.542911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail>
9298 00:57:46.543653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail
9300 00:57:46.600412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass>
9301 00:57:46.601092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass
9303 00:57:46.649536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass>
9304 00:57:46.649806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass
9306 00:57:46.693300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass>
9307 00:57:46.693653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass
9309 00:57:46.743566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass>
9310 00:57:46.744413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass
9312 00:57:46.797217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass>
9313 00:57:46.797985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass
9315 00:57:46.852853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass>
9316 00:57:46.853554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass
9318 00:57:46.906890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail>
9319 00:57:46.907529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail
9321 00:57:46.971103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass>
9322 00:57:46.971915 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass
9324 00:57:47.025673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass>
9325 00:57:47.026329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass
9327 00:57:47.076439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass>
9328 00:57:47.077222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass
9330 00:57:47.127695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass>
9331 00:57:47.128337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass
9333 00:57:47.181805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass>
9334 00:57:47.182545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass
9336 00:57:47.235996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass>
9337 00:57:47.236695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass
9339 00:57:47.289600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail>
9340 00:57:47.290309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail
9342 00:57:47.344312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass>
9343 00:57:47.344962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass
9345 00:57:47.400417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass>
9346 00:57:47.401159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass
9348 00:57:47.451959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass>
9349 00:57:47.452608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass
9351 00:57:47.502691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass>
9352 00:57:47.503330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass
9354 00:57:47.556209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass>
9355 00:57:47.556676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass
9357 00:57:47.612284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass>
9358 00:57:47.613159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass
9360 00:57:47.668935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail>
9361 00:57:47.669673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail
9363 00:57:47.729995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass>
9364 00:57:47.730758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass
9366 00:57:47.778727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass>
9367 00:57:47.779468 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass
9369 00:57:47.829277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass>
9370 00:57:47.829581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass
9372 00:57:47.879602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass>
9373 00:57:47.879875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass
9375 00:57:47.930620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass>
9376 00:57:47.930953 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass
9378 00:57:47.982070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass>
9379 00:57:47.982796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass
9381 00:57:48.037929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass>
9382 00:57:48.038689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass
9384 00:57:48.098494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass>
9385 00:57:48.099214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass
9387 00:57:48.152886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass>
9388 00:57:48.153727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass
9390 00:57:48.213058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass>
9391 00:57:48.213887 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass
9393 00:57:48.276159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass>
9394 00:57:48.276850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass
9396 00:57:48.334663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass>
9397 00:57:48.335412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass
9399 00:57:48.393075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass>
9400 00:57:48.393713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass
9402 00:57:48.445207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass>
9403 00:57:48.445846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass
9405 00:57:48.503340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass>
9406 00:57:48.504232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass
9408 00:57:48.555081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass>
9409 00:57:48.555794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass
9411 00:57:48.606494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass>
9412 00:57:48.607240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass
9414 00:57:48.661799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass>
9415 00:57:48.662539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass
9417 00:57:48.715922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass>
9418 00:57:48.716702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass
9420 00:57:48.768193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass>
9421 00:57:48.768966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass
9423 00:57:48.820148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass>
9424 00:57:48.820923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass
9426 00:57:48.872620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass>
9427 00:57:48.872883 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass
9429 00:57:48.925176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass>
9430 00:57:48.925858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass
9432 00:57:48.979254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass>
9433 00:57:48.980011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass
9435 00:57:49.038346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass>
9436 00:57:49.039098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass
9438 00:57:49.094559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass>
9439 00:57:49.095237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass
9441 00:57:49.150003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass>
9442 00:57:49.150668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass
9444 00:57:49.196461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass>
9445 00:57:49.197095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass
9447 00:57:49.253612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass>
9448 00:57:49.254317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass
9450 00:57:49.311846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass>
9451 00:57:49.312476 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass
9453 00:57:49.367517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass>
9454 00:57:49.368151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass
9456 00:57:49.418968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass>
9457 00:57:49.419673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass
9459 00:57:49.471063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass>
9460 00:57:49.471698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass
9462 00:57:49.528238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass>
9463 00:57:49.528867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass
9465 00:57:49.582729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass>
9466 00:57:49.583392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass
9468 00:57:49.638990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass>
9469 00:57:49.639764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass
9471 00:57:49.700047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass>
9472 00:57:49.700701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass
9474 00:57:49.754711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass>
9475 00:57:49.755367 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass
9477 00:57:49.809484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass>
9478 00:57:49.810123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass
9480 00:57:49.862966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass>
9481 00:57:49.863600 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass
9483 00:57:49.915771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass>
9484 00:57:49.916406 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass
9486 00:57:49.966665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass>
9487 00:57:49.967301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass
9489 00:57:50.025157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass>
9490 00:57:50.025869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass
9492 00:57:50.085227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass>
9493 00:57:50.086070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass
9495 00:57:50.137968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass>
9496 00:57:50.138936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass
9498 00:57:50.195146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass>
9499 00:57:50.195777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass
9501 00:57:50.245869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass>
9502 00:57:50.246121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass
9504 00:57:50.292002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass>
9505 00:57:50.292261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass
9507 00:57:50.334851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass>
9508 00:57:50.335106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass
9510 00:57:50.392304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass>
9511 00:57:50.392728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass
9513 00:57:50.452853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass>
9514 00:57:50.453489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass
9516 00:57:50.514303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass>
9517 00:57:50.515051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass
9519 00:57:50.575070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass>
9520 00:57:50.575763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass
9522 00:57:50.633705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass>
9523 00:57:50.634016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass
9525 00:57:50.681971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass>
9526 00:57:50.682613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass
9528 00:57:50.726068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass>
9529 00:57:50.726412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass
9531 00:57:50.779993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass>
9532 00:57:50.780623 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass
9534 00:57:50.834476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass>
9535 00:57:50.834780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass
9537 00:57:50.877046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass>
9538 00:57:50.877296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass
9540 00:57:50.920445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass>
9541 00:57:50.920732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass
9543 00:57:50.962122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass>
9544 00:57:50.962425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass
9546 00:57:51.010960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass>
9547 00:57:51.011209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass
9549 00:57:51.051008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail>
9550 00:57:51.051439 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail
9552 00:57:51.105950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass>
9553 00:57:51.106776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass
9555 00:57:51.160098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass>
9556 00:57:51.160733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass
9558 00:57:51.213161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass>
9559 00:57:51.213899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass
9561 00:57:51.264483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass>
9562 00:57:51.264792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass
9564 00:57:51.316751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass>
9565 00:57:51.316998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass
9567 00:57:51.369038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass>
9568 00:57:51.369677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass
9570 00:57:51.422434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail>
9571 00:57:51.423066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail
9573 00:57:51.477865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass>
9574 00:57:51.478129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass
9576 00:57:51.524360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass>
9577 00:57:51.524687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass
9579 00:57:51.574311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass>
9580 00:57:51.574952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass
9582 00:57:51.624670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass>
9583 00:57:51.624922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass
9585 00:57:51.666002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass>
9586 00:57:51.666656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass
9588 00:57:51.720032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass>
9589 00:57:51.720655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass
9591 00:57:51.778022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail>
9592 00:57:51.778696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail
9594 00:57:51.837481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass>
9595 00:57:51.838336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass
9597 00:57:51.894813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass>
9598 00:57:51.895447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass
9600 00:57:51.945211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass>
9601 00:57:51.945874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass
9603 00:57:51.994718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass>
9604 00:57:51.995478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass
9606 00:57:52.044170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass>
9607 00:57:52.044874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass
9609 00:57:52.098119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass>
9610 00:57:52.098874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass
9612 00:57:52.154531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail>
9613 00:57:52.155378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail
9615 00:57:52.213308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass>
9616 00:57:52.214116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass
9618 00:57:52.271400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass>
9619 00:57:52.272190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass
9621 00:57:52.327166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass>
9622 00:57:52.327871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass
9624 00:57:52.379125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass>
9625 00:57:52.379768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass
9627 00:57:52.427862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass>
9628 00:57:52.428148 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass
9630 00:57:52.479207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass>
9631 00:57:52.479472 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass
9633 00:57:52.525268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail>
9634 00:57:52.525519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail
9636 00:57:52.574440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass>
9637 00:57:52.574696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass
9639 00:57:52.624248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass>
9640 00:57:52.624557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass
9642 00:57:52.671582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass>
9643 00:57:52.672255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass
9645 00:57:52.720439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass>
9646 00:57:52.720733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass
9648 00:57:52.767582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass>
9649 00:57:52.767847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass
9651 00:57:52.817608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass>
9652 00:57:52.817852 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass
9654 00:57:52.866278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail>
9655 00:57:52.866914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail
9657 00:57:52.927798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass>
9658 00:57:52.928544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass
9660 00:57:52.986685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass>
9661 00:57:52.987322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass
9663 00:57:53.042885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass>
9664 00:57:53.043525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass
9666 00:57:53.100064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass>
9667 00:57:53.100704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass
9669 00:57:53.147572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass>
9670 00:57:53.147886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass
9672 00:57:53.201877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass>
9673 00:57:53.202605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass
9675 00:57:53.256080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail>
9676 00:57:53.256782 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail
9678 00:57:53.312247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass>
9679 00:57:53.312511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass
9681 00:57:53.364085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass>
9682 00:57:53.364397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass
9684 00:57:53.413944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass>
9685 00:57:53.414236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass
9687 00:57:53.459531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass>
9688 00:57:53.459826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass
9690 00:57:53.506475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass>
9691 00:57:53.506730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass
9693 00:57:53.561697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass>
9694 00:57:53.562318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass
9696 00:57:53.611887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail>
9697 00:57:53.612556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail
9699 00:57:53.663047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass>
9700 00:57:53.663309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass
9702 00:57:53.711477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass>
9703 00:57:53.711776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass
9705 00:57:53.755818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass>
9706 00:57:53.756321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass
9708 00:57:53.802734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass>
9709 00:57:53.803039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass
9711 00:57:53.850679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass>
9712 00:57:53.851307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass
9714 00:57:53.906413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass>
9715 00:57:53.907147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass
9717 00:57:53.954261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail>
9718 00:57:53.954938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail
9720 00:57:54.015906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass>
9721 00:57:54.016533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass
9723 00:57:54.071653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass>
9724 00:57:54.071936 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass
9726 00:57:54.125478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass>
9727 00:57:54.126106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass
9729 00:57:54.176237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass>
9730 00:57:54.176493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass
9732 00:57:54.225059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass>
9733 00:57:54.225357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass
9735 00:57:54.270808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass>
9736 00:57:54.271069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass
9738 00:57:54.316763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail>
9739 00:57:54.317020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail
9741 00:57:54.363165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass>
9742 00:57:54.363413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass
9744 00:57:54.407396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass>
9745 00:57:54.407661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass
9747 00:57:54.454473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass>
9748 00:57:54.454785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass
9750 00:57:54.495346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass>
9751 00:57:54.495592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass
9753 00:57:54.537845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass>
9754 00:57:54.538091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass
9756 00:57:54.581925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass>
9757 00:57:54.582204 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass
9759 00:57:54.624283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail>
9760 00:57:54.624573 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail
9762 00:57:54.675989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass>
9763 00:57:54.676633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass
9765 00:57:54.725303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass>
9766 00:57:54.725931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass
9768 00:57:54.773824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass>
9769 00:57:54.774494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass
9771 00:57:54.824654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass>
9772 00:57:54.825286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass
9774 00:57:54.874910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass>
9775 00:57:54.875565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass
9777 00:57:54.928570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass>
9778 00:57:54.929261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass
9780 00:57:54.973672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail>
9781 00:57:54.973926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail
9783 00:57:55.023441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass>
9784 00:57:55.023939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass
9786 00:57:55.076371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass>
9787 00:57:55.076633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass
9789 00:57:55.124386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass>
9790 00:57:55.124645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass
9792 00:57:55.174029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass>
9793 00:57:55.174653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass
9795 00:57:55.228758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass>
9796 00:57:55.229392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass
9798 00:57:55.283840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass>
9799 00:57:55.284522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass
9801 00:57:55.331931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail>
9802 00:57:55.332205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail
9804 00:57:55.385223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass>
9805 00:57:55.385489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass
9807 00:57:55.431492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass>
9808 00:57:55.431750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass
9810 00:57:55.479291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass>
9811 00:57:55.479616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass
9813 00:57:55.529341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass>
9814 00:57:55.529614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass
9816 00:57:55.582735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass>
9817 00:57:55.583016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass
9819 00:57:55.630891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass>
9820 00:57:55.631197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass
9822 00:57:55.678589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail>
9823 00:57:55.678846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail
9825 00:57:55.730006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass>
9826 00:57:55.730491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass
9828 00:57:55.783127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass>
9829 00:57:55.783803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass
9831 00:57:55.836612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass>
9832 00:57:55.837253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass
9834 00:57:55.886814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass>
9835 00:57:55.887071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass
9837 00:57:55.938933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass>
9838 00:57:55.939680 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass
9840 00:57:55.989806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass
9842 00:57:55.992545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass>
9843 00:57:56.042812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail>
9844 00:57:56.043520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail
9846 00:57:56.105438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass>
9847 00:57:56.106182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass
9849 00:57:56.164760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass>
9850 00:57:56.165394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass
9852 00:57:56.221523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass>
9853 00:57:56.222149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass
9855 00:57:56.279815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass>
9856 00:57:56.280442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass
9858 00:57:56.340094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass>
9859 00:57:56.340865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass
9861 00:57:56.397754 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass
9863 00:57:56.400436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass>
9864 00:57:56.458125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail>
9865 00:57:56.458900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail
9867 00:57:56.515210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass>
9868 00:57:56.515639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass
9870 00:57:56.565961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass>
9871 00:57:56.566630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass
9873 00:57:56.621107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass>
9874 00:57:56.621739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass
9876 00:57:56.675013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass>
9877 00:57:56.675641 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass
9879 00:57:56.726131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass>
9880 00:57:56.726792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass
9882 00:57:56.779448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass>
9883 00:57:56.780109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass
9885 00:57:56.828799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass>
9886 00:57:56.829465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass
9888 00:57:56.886870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass>
9889 00:57:56.887547 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass
9891 00:57:56.946425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass>
9892 00:57:56.947061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass
9894 00:57:56.999562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass>
9895 00:57:57.000220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass
9897 00:57:57.054239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail>
9898 00:57:57.054906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail
9900 00:57:57.110236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass>
9901 00:57:57.110988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass
9903 00:57:57.162909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass>
9904 00:57:57.163571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass
9906 00:57:57.209624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass>
9907 00:57:57.210314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass
9909 00:57:57.266276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass>
9910 00:57:57.266571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass
9912 00:57:57.311114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass>
9913 00:57:57.311906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass
9915 00:57:57.365204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass>
9916 00:57:57.365895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass
9918 00:57:57.412240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail>
9919 00:57:57.412487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail
9921 00:57:57.459394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass>
9922 00:57:57.459723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass
9924 00:57:57.503997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass>
9925 00:57:57.504269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass
9927 00:57:57.548215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass>
9928 00:57:57.548644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass
9930 00:57:57.597630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass>
9931 00:57:57.598215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass
9933 00:57:57.642791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass>
9934 00:57:57.643038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass
9936 00:57:57.684751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass>
9937 00:57:57.685013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass
9939 00:57:57.733341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail>
9940 00:57:57.733670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail
9942 00:57:57.776028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass>
9943 00:57:57.776361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass
9945 00:57:57.821634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass
9947 00:57:57.824663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass>
9948 00:57:57.871039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass>
9949 00:57:57.871427 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass
9951 00:57:57.919157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass>
9952 00:57:57.919503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass
9954 00:57:57.970456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass>
9955 00:57:57.971137 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass
9957 00:57:58.021768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass>
9958 00:57:58.022537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass
9960 00:57:58.064163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail>
9961 00:57:58.064421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail
9963 00:57:58.115029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass>
9964 00:57:58.115664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass
9966 00:57:58.156397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass>
9967 00:57:58.156649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass
9969 00:57:58.206123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass>
9970 00:57:58.206898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass
9972 00:57:58.263641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass>
9973 00:57:58.264457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass
9975 00:57:58.318521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass>
9976 00:57:58.319334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass
9978 00:57:58.373198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass>
9979 00:57:58.373846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass
9981 00:57:58.421153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail>
9982 00:57:58.421781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail
9984 00:57:58.474075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass>
9985 00:57:58.474814 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass
9987 00:57:58.525388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass
9989 00:57:58.528295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass>
9990 00:57:58.582191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass>
9991 00:57:58.582892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass
9993 00:57:58.641833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass>
9994 00:57:58.642689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass
9996 00:57:58.697573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass>
9997 00:57:58.698329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass
9999 00:57:58.752003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass>
10000 00:57:58.752649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass
10002 00:57:58.810859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail>
10003 00:57:58.811493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail
10005 00:57:58.866688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass>
10006 00:57:58.867322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass
10008 00:57:58.921049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10009 00:57:58.921447 + set +x
10010 00:57:58.921984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10012 00:57:58.927724 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14368556_1.6.2.3.5>
10013 00:57:58.928343 Received signal: <ENDRUN> 1_kselftest-alsa 14368556_1.6.2.3.5
10014 00:57:58.928687 Ending use of test pattern.
10015 00:57:58.928977 Ending test lava.1_kselftest-alsa (14368556_1.6.2.3.5), duration 47.44
10017 00:57:58.930782 <LAVA_TEST_RUNNER EXIT>
10018 00:57:58.931397 ok: lava_test_shell seems to have completed
10019 00:57:58.946633 alsa_mixer-test: pass
alsa_mixer-test_event_missing_0_0: fail
alsa_mixer-test_event_missing_0_1: fail
alsa_mixer-test_event_missing_0_10: pass
alsa_mixer-test_event_missing_0_11: pass
alsa_mixer-test_event_missing_0_12: pass
alsa_mixer-test_event_missing_0_13: pass
alsa_mixer-test_event_missing_0_14: pass
alsa_mixer-test_event_missing_0_15: pass
alsa_mixer-test_event_missing_0_16: pass
alsa_mixer-test_event_missing_0_17: pass
alsa_mixer-test_event_missing_0_18: pass
alsa_mixer-test_event_missing_0_19: pass
alsa_mixer-test_event_missing_0_2: fail
alsa_mixer-test_event_missing_0_20: pass
alsa_mixer-test_event_missing_0_21: pass
alsa_mixer-test_event_missing_0_22: pass
alsa_mixer-test_event_missing_0_23: pass
alsa_mixer-test_event_missing_0_24: pass
alsa_mixer-test_event_missing_0_25: pass
alsa_mixer-test_event_missing_0_26: pass
alsa_mixer-test_event_missing_0_27: pass
alsa_mixer-test_event_missing_0_28: pass
alsa_mixer-test_event_missing_0_29: pass
alsa_mixer-test_event_missing_0_3: fail
alsa_mixer-test_event_missing_0_30: pass
alsa_mixer-test_event_missing_0_31: pass
alsa_mixer-test_event_missing_0_32: pass
alsa_mixer-test_event_missing_0_33: pass
alsa_mixer-test_event_missing_0_34: pass
alsa_mixer-test_event_missing_0_35: pass
alsa_mixer-test_event_missing_0_36: pass
alsa_mixer-test_event_missing_0_37: pass
alsa_mixer-test_event_missing_0_38: pass
alsa_mixer-test_event_missing_0_39: pass
alsa_mixer-test_event_missing_0_4: fail
alsa_mixer-test_event_missing_0_40: pass
alsa_mixer-test_event_missing_0_41: pass
alsa_mixer-test_event_missing_0_42: pass
alsa_mixer-test_event_missing_0_43: pass
alsa_mixer-test_event_missing_0_44: pass
alsa_mixer-test_event_missing_0_45: pass
alsa_mixer-test_event_missing_0_46: pass
alsa_mixer-test_event_missing_0_47: pass
alsa_mixer-test_event_missing_0_48: pass
alsa_mixer-test_event_missing_0_49: pass
alsa_mixer-test_event_missing_0_5: fail
alsa_mixer-test_event_missing_0_50: pass
alsa_mixer-test_event_missing_0_51: pass
alsa_mixer-test_event_missing_0_52: pass
alsa_mixer-test_event_missing_0_53: pass
alsa_mixer-test_event_missing_0_54: pass
alsa_mixer-test_event_missing_0_55: pass
alsa_mixer-test_event_missing_0_56: pass
alsa_mixer-test_event_missing_0_57: pass
alsa_mixer-test_event_missing_0_58: pass
alsa_mixer-test_event_missing_0_59: pass
alsa_mixer-test_event_missing_0_6: pass
alsa_mixer-test_event_missing_0_60: pass
alsa_mixer-test_event_missing_0_61: pass
alsa_mixer-test_event_missing_0_62: pass
alsa_mixer-test_event_missing_0_63: pass
alsa_mixer-test_event_missing_0_64: pass
alsa_mixer-test_event_missing_0_65: pass
alsa_mixer-test_event_missing_0_66: pass
alsa_mixer-test_event_missing_0_67: pass
alsa_mixer-test_event_missing_0_68: pass
alsa_mixer-test_event_missing_0_69: pass
alsa_mixer-test_event_missing_0_7: pass
alsa_mixer-test_event_missing_0_70: pass
alsa_mixer-test_event_missing_0_71: pass
alsa_mixer-test_event_missing_0_72: pass
alsa_mixer-test_event_missing_0_73: pass
alsa_mixer-test_event_missing_0_74: pass
alsa_mixer-test_event_missing_0_75: pass
alsa_mixer-test_event_missing_0_76: pass
alsa_mixer-test_event_missing_0_77: pass
alsa_mixer-test_event_missing_0_78: pass
alsa_mixer-test_event_missing_0_79: pass
alsa_mixer-test_event_missing_0_8: pass
alsa_mixer-test_event_missing_0_80: pass
alsa_mixer-test_event_missing_0_81: fail
alsa_mixer-test_event_missing_0_82: pass
alsa_mixer-test_event_missing_0_83: pass
alsa_mixer-test_event_missing_0_84: pass
alsa_mixer-test_event_missing_0_85: pass
alsa_mixer-test_event_missing_0_86: pass
alsa_mixer-test_event_missing_0_87: pass
alsa_mixer-test_event_missing_0_88: pass
alsa_mixer-test_event_missing_0_89: pass
alsa_mixer-test_event_missing_0_9: pass
alsa_mixer-test_event_missing_0_90: pass
alsa_mixer-test_event_missing_0_91: pass
alsa_mixer-test_event_missing_0_92: pass
alsa_mixer-test_event_missing_0_93: pass
alsa_mixer-test_event_spurious_0_0: pass
alsa_mixer-test_event_spurious_0_1: pass
alsa_mixer-test_event_spurious_0_10: pass
alsa_mixer-test_event_spurious_0_11: pass
alsa_mixer-test_event_spurious_0_12: pass
alsa_mixer-test_event_spurious_0_13: pass
alsa_mixer-test_event_spurious_0_14: pass
alsa_mixer-test_event_spurious_0_15: pass
alsa_mixer-test_event_spurious_0_16: pass
alsa_mixer-test_event_spurious_0_17: pass
alsa_mixer-test_event_spurious_0_18: pass
alsa_mixer-test_event_spurious_0_19: pass
alsa_mixer-test_event_spurious_0_2: pass
alsa_mixer-test_event_spurious_0_20: pass
alsa_mixer-test_event_spurious_0_21: pass
alsa_mixer-test_event_spurious_0_22: pass
alsa_mixer-test_event_spurious_0_23: pass
alsa_mixer-test_event_spurious_0_24: pass
alsa_mixer-test_event_spurious_0_25: pass
alsa_mixer-test_event_spurious_0_26: pass
alsa_mixer-test_event_spurious_0_27: pass
alsa_mixer-test_event_spurious_0_28: pass
alsa_mixer-test_event_spurious_0_29: pass
alsa_mixer-test_event_spurious_0_3: pass
alsa_mixer-test_event_spurious_0_30: pass
alsa_mixer-test_event_spurious_0_31: pass
alsa_mixer-test_event_spurious_0_32: pass
alsa_mixer-test_event_spurious_0_33: pass
alsa_mixer-test_event_spurious_0_34: pass
alsa_mixer-test_event_spurious_0_35: pass
alsa_mixer-test_event_spurious_0_36: pass
alsa_mixer-test_event_spurious_0_37: pass
alsa_mixer-test_event_spurious_0_38: pass
alsa_mixer-test_event_spurious_0_39: pass
alsa_mixer-test_event_spurious_0_4: pass
alsa_mixer-test_event_spurious_0_40: pass
alsa_mixer-test_event_spurious_0_41: pass
alsa_mixer-test_event_spurious_0_42: pass
alsa_mixer-test_event_spurious_0_43: pass
alsa_mixer-test_event_spurious_0_44: pass
alsa_mixer-test_event_spurious_0_45: pass
alsa_mixer-test_event_spurious_0_46: pass
alsa_mixer-test_event_spurious_0_47: pass
alsa_mixer-test_event_spurious_0_48: pass
alsa_mixer-test_event_spurious_0_49: pass
alsa_mixer-test_event_spurious_0_5: pass
alsa_mixer-test_event_spurious_0_50: pass
alsa_mixer-test_event_spurious_0_51: pass
alsa_mixer-test_event_spurious_0_52: pass
alsa_mixer-test_event_spurious_0_53: pass
alsa_mixer-test_event_spurious_0_54: pass
alsa_mixer-test_event_spurious_0_55: pass
alsa_mixer-test_event_spurious_0_56: pass
alsa_mixer-test_event_spurious_0_57: pass
alsa_mixer-test_event_spurious_0_58: pass
alsa_mixer-test_event_spurious_0_59: pass
alsa_mixer-test_event_spurious_0_6: pass
alsa_mixer-test_event_spurious_0_60: pass
alsa_mixer-test_event_spurious_0_61: pass
alsa_mixer-test_event_spurious_0_62: pass
alsa_mixer-test_event_spurious_0_63: pass
alsa_mixer-test_event_spurious_0_64: pass
alsa_mixer-test_event_spurious_0_65: pass
alsa_mixer-test_event_spurious_0_66: pass
alsa_mixer-test_event_spurious_0_67: pass
alsa_mixer-test_event_spurious_0_68: pass
alsa_mixer-test_event_spurious_0_69: pass
alsa_mixer-test_event_spurious_0_7: pass
alsa_mixer-test_event_spurious_0_70: pass
alsa_mixer-test_event_spurious_0_71: pass
alsa_mixer-test_event_spurious_0_72: pass
alsa_mixer-test_event_spurious_0_73: pass
alsa_mixer-test_event_spurious_0_74: pass
alsa_mixer-test_event_spurious_0_75: pass
alsa_mixer-test_event_spurious_0_76: pass
alsa_mixer-test_event_spurious_0_77: pass
alsa_mixer-test_event_spurious_0_78: pass
alsa_mixer-test_event_spurious_0_79: pass
alsa_mixer-test_event_spurious_0_8: pass
alsa_mixer-test_event_spurious_0_80: pass
alsa_mixer-test_event_spurious_0_81: pass
alsa_mixer-test_event_spurious_0_82: pass
alsa_mixer-test_event_spurious_0_83: pass
alsa_mixer-test_event_spurious_0_84: pass
alsa_mixer-test_event_spurious_0_85: pass
alsa_mixer-test_event_spurious_0_86: pass
alsa_mixer-test_event_spurious_0_87: pass
alsa_mixer-test_event_spurious_0_88: fail
alsa_mixer-test_event_spurious_0_89: pass
alsa_mixer-test_event_spurious_0_9: pass
alsa_mixer-test_event_spurious_0_90: pass
alsa_mixer-test_event_spurious_0_91: pass
alsa_mixer-test_event_spurious_0_92: pass
alsa_mixer-test_event_spurious_0_93: pass
alsa_mixer-test_get_value_0_0: pass
alsa_mixer-test_get_value_0_1: pass
alsa_mixer-test_get_value_0_10: pass
alsa_mixer-test_get_value_0_11: pass
alsa_mixer-test_get_value_0_12: pass
alsa_mixer-test_get_value_0_13: pass
alsa_mixer-test_get_value_0_14: pass
alsa_mixer-test_get_value_0_15: pass
alsa_mixer-test_get_value_0_16: pass
alsa_mixer-test_get_value_0_17: pass
alsa_mixer-test_get_value_0_18: pass
alsa_mixer-test_get_value_0_19: pass
alsa_mixer-test_get_value_0_2: pass
alsa_mixer-test_get_value_0_20: pass
alsa_mixer-test_get_value_0_21: pass
alsa_mixer-test_get_value_0_22: pass
alsa_mixer-test_get_value_0_23: pass
alsa_mixer-test_get_value_0_24: pass
alsa_mixer-test_get_value_0_25: pass
alsa_mixer-test_get_value_0_26: pass
alsa_mixer-test_get_value_0_27: pass
alsa_mixer-test_get_value_0_28: pass
alsa_mixer-test_get_value_0_29: pass
alsa_mixer-test_get_value_0_3: pass
alsa_mixer-test_get_value_0_30: pass
alsa_mixer-test_get_value_0_31: pass
alsa_mixer-test_get_value_0_32: pass
alsa_mixer-test_get_value_0_33: pass
alsa_mixer-test_get_value_0_34: pass
alsa_mixer-test_get_value_0_35: pass
alsa_mixer-test_get_value_0_36: pass
alsa_mixer-test_get_value_0_37: pass
alsa_mixer-test_get_value_0_38: pass
alsa_mixer-test_get_value_0_39: pass
alsa_mixer-test_get_value_0_4: pass
alsa_mixer-test_get_value_0_40: pass
alsa_mixer-test_get_value_0_41: pass
alsa_mixer-test_get_value_0_42: pass
alsa_mixer-test_get_value_0_43: pass
alsa_mixer-test_get_value_0_44: pass
alsa_mixer-test_get_value_0_45: pass
alsa_mixer-test_get_value_0_46: pass
alsa_mixer-test_get_value_0_47: pass
alsa_mixer-test_get_value_0_48: pass
alsa_mixer-test_get_value_0_49: pass
alsa_mixer-test_get_value_0_5: pass
alsa_mixer-test_get_value_0_50: pass
alsa_mixer-test_get_value_0_51: pass
alsa_mixer-test_get_value_0_52: pass
alsa_mixer-test_get_value_0_53: pass
alsa_mixer-test_get_value_0_54: pass
alsa_mixer-test_get_value_0_55: pass
alsa_mixer-test_get_value_0_56: pass
alsa_mixer-test_get_value_0_57: pass
alsa_mixer-test_get_value_0_58: pass
alsa_mixer-test_get_value_0_59: pass
alsa_mixer-test_get_value_0_6: pass
alsa_mixer-test_get_value_0_60: pass
alsa_mixer-test_get_value_0_61: pass
alsa_mixer-test_get_value_0_62: pass
alsa_mixer-test_get_value_0_63: pass
alsa_mixer-test_get_value_0_64: pass
alsa_mixer-test_get_value_0_65: pass
alsa_mixer-test_get_value_0_66: pass
alsa_mixer-test_get_value_0_67: pass
alsa_mixer-test_get_value_0_68: pass
alsa_mixer-test_get_value_0_69: pass
alsa_mixer-test_get_value_0_7: pass
alsa_mixer-test_get_value_0_70: pass
alsa_mixer-test_get_value_0_71: pass
alsa_mixer-test_get_value_0_72: pass
alsa_mixer-test_get_value_0_73: pass
alsa_mixer-test_get_value_0_74: pass
alsa_mixer-test_get_value_0_75: pass
alsa_mixer-test_get_value_0_76: pass
alsa_mixer-test_get_value_0_77: fail
alsa_mixer-test_get_value_0_78: fail
alsa_mixer-test_get_value_0_79: fail
alsa_mixer-test_get_value_0_8: pass
alsa_mixer-test_get_value_0_80: pass
alsa_mixer-test_get_value_0_81: pass
alsa_mixer-test_get_value_0_82: pass
alsa_mixer-test_get_value_0_83: pass
alsa_mixer-test_get_value_0_84: pass
alsa_mixer-test_get_value_0_85: pass
alsa_mixer-test_get_value_0_86: pass
alsa_mixer-test_get_value_0_87: pass
alsa_mixer-test_get_value_0_88: pass
alsa_mixer-test_get_value_0_89: pass
alsa_mixer-test_get_value_0_9: pass
alsa_mixer-test_get_value_0_90: pass
alsa_mixer-test_get_value_0_91: pass
alsa_mixer-test_get_value_0_92: pass
alsa_mixer-test_get_value_0_93: pass
alsa_mixer-test_name_0_0: pass
alsa_mixer-test_name_0_1: pass
alsa_mixer-test_name_0_10: fail
alsa_mixer-test_name_0_11: fail
alsa_mixer-test_name_0_12: fail
alsa_mixer-test_name_0_13: fail
alsa_mixer-test_name_0_14: fail
alsa_mixer-test_name_0_15: fail
alsa_mixer-test_name_0_16: fail
alsa_mixer-test_name_0_17: fail
alsa_mixer-test_name_0_18: fail
alsa_mixer-test_name_0_19: fail
alsa_mixer-test_name_0_2: pass
alsa_mixer-test_name_0_20: fail
alsa_mixer-test_name_0_21: fail
alsa_mixer-test_name_0_22: pass
alsa_mixer-test_name_0_23: pass
alsa_mixer-test_name_0_24: pass
alsa_mixer-test_name_0_25: pass
alsa_mixer-test_name_0_26: pass
alsa_mixer-test_name_0_27: pass
alsa_mixer-test_name_0_28: pass
alsa_mixer-test_name_0_29: pass
alsa_mixer-test_name_0_3: pass
alsa_mixer-test_name_0_30: fail
alsa_mixer-test_name_0_31: fail
alsa_mixer-test_name_0_32: fail
alsa_mixer-test_name_0_33: fail
alsa_mixer-test_name_0_34: fail
alsa_mixer-test_name_0_35: fail
alsa_mixer-test_name_0_36: fail
alsa_mixer-test_name_0_37: fail
alsa_mixer-test_name_0_38: fail
alsa_mixer-test_name_0_39: fail
alsa_mixer-test_name_0_4: pass
alsa_mixer-test_name_0_40: fail
alsa_mixer-test_name_0_41: fail
alsa_mixer-test_name_0_42: fail
alsa_mixer-test_name_0_43: fail
alsa_mixer-test_name_0_44: fail
alsa_mixer-test_name_0_45: fail
alsa_mixer-test_name_0_46: fail
alsa_mixer-test_name_0_47: fail
alsa_mixer-test_name_0_48: fail
alsa_mixer-test_name_0_49: fail
alsa_mixer-test_name_0_5: pass
alsa_mixer-test_name_0_50: fail
alsa_mixer-test_name_0_51: fail
alsa_mixer-test_name_0_52: fail
alsa_mixer-test_name_0_53: fail
alsa_mixer-test_name_0_54: fail
alsa_mixer-test_name_0_55: fail
alsa_mixer-test_name_0_56: fail
alsa_mixer-test_name_0_57: fail
alsa_mixer-test_name_0_58: fail
alsa_mixer-test_name_0_59: fail
alsa_mixer-test_name_0_6: fail
alsa_mixer-test_name_0_60: fail
alsa_mixer-test_name_0_61: fail
alsa_mixer-test_name_0_62: fail
alsa_mixer-test_name_0_63: fail
alsa_mixer-test_name_0_64: fail
alsa_mixer-test_name_0_65: fail
alsa_mixer-test_name_0_66: fail
alsa_mixer-test_name_0_67: fail
alsa_mixer-test_name_0_68: fail
alsa_mixer-test_name_0_69: fail
alsa_mixer-test_name_0_7: fail
alsa_mixer-test_name_0_70: fail
alsa_mixer-test_name_0_71: fail
alsa_mixer-test_name_0_72: fail
alsa_mixer-test_name_0_73: fail
alsa_mixer-test_name_0_74: fail
alsa_mixer-test_name_0_75: fail
alsa_mixer-test_name_0_76: fail
alsa_mixer-test_name_0_77: pass
alsa_mixer-test_name_0_78: pass
alsa_mixer-test_name_0_79: pass
alsa_mixer-test_name_0_8: fail
alsa_mixer-test_name_0_80: pass
alsa_mixer-test_name_0_81: pass
alsa_mixer-test_name_0_82: pass
alsa_mixer-test_name_0_83: pass
alsa_mixer-test_name_0_84: pass
alsa_mixer-test_name_0_85: pass
alsa_mixer-test_name_0_86: pass
alsa_mixer-test_name_0_87: pass
alsa_mixer-test_name_0_88: pass
alsa_mixer-test_name_0_89: pass
alsa_mixer-test_name_0_9: fail
alsa_mixer-test_name_0_90: pass
alsa_mixer-test_name_0_91: pass
alsa_mixer-test_name_0_92: pass
alsa_mixer-test_name_0_93: pass
alsa_mixer-test_write_default_0_0: pass
alsa_mixer-test_write_default_0_1: pass
alsa_mixer-test_write_default_0_10: pass
alsa_mixer-test_write_default_0_11: pass
alsa_mixer-test_write_default_0_12: pass
alsa_mixer-test_write_default_0_13: pass
alsa_mixer-test_write_default_0_14: pass
alsa_mixer-test_write_default_0_15: pass
alsa_mixer-test_write_default_0_16: pass
alsa_mixer-test_write_default_0_17: pass
alsa_mixer-test_write_default_0_18: pass
alsa_mixer-test_write_default_0_19: pass
alsa_mixer-test_write_default_0_2: pass
alsa_mixer-test_write_default_0_20: pass
alsa_mixer-test_write_default_0_21: pass
alsa_mixer-test_write_default_0_22: pass
alsa_mixer-test_write_default_0_23: pass
alsa_mixer-test_write_default_0_24: pass
alsa_mixer-test_write_default_0_25: pass
alsa_mixer-test_write_default_0_26: pass
alsa_mixer-test_write_default_0_27: pass
alsa_mixer-test_write_default_0_28: pass
alsa_mixer-test_write_default_0_29: pass
alsa_mixer-test_write_default_0_3: pass
alsa_mixer-test_write_default_0_30: pass
alsa_mixer-test_write_default_0_31: pass
alsa_mixer-test_write_default_0_32: pass
alsa_mixer-test_write_default_0_33: pass
alsa_mixer-test_write_default_0_34: pass
alsa_mixer-test_write_default_0_35: pass
alsa_mixer-test_write_default_0_36: pass
alsa_mixer-test_write_default_0_37: pass
alsa_mixer-test_write_default_0_38: pass
alsa_mixer-test_write_default_0_39: pass
alsa_mixer-test_write_default_0_4: pass
alsa_mixer-test_write_default_0_40: pass
alsa_mixer-test_write_default_0_41: pass
alsa_mixer-test_write_default_0_42: pass
alsa_mixer-test_write_default_0_43: pass
alsa_mixer-test_write_default_0_44: pass
alsa_mixer-test_write_default_0_45: pass
alsa_mixer-test_write_default_0_46: pass
alsa_mixer-test_write_default_0_47: pass
alsa_mixer-test_write_default_0_48: pass
alsa_mixer-test_write_default_0_49: pass
alsa_mixer-test_write_default_0_5: pass
alsa_mixer-test_write_default_0_50: pass
alsa_mixer-test_write_default_0_51: pass
alsa_mixer-test_write_default_0_52: pass
alsa_mixer-test_write_default_0_53: pass
alsa_mixer-test_write_default_0_54: pass
alsa_mixer-test_write_default_0_55: pass
alsa_mixer-test_write_default_0_56: pass
alsa_mixer-test_write_default_0_57: pass
alsa_mixer-test_write_default_0_58: pass
alsa_mixer-test_write_default_0_59: pass
alsa_mixer-test_write_default_0_6: pass
alsa_mixer-test_write_default_0_60: pass
alsa_mixer-test_write_default_0_61: pass
alsa_mixer-test_write_default_0_62: pass
alsa_mixer-test_write_default_0_63: pass
alsa_mixer-test_write_default_0_64: pass
alsa_mixer-test_write_default_0_65: pass
alsa_mixer-test_write_default_0_66: pass
alsa_mixer-test_write_default_0_67: pass
alsa_mixer-test_write_default_0_68: pass
alsa_mixer-test_write_default_0_69: pass
alsa_mixer-test_write_default_0_7: pass
alsa_mixer-test_write_default_0_70: pass
alsa_mixer-test_write_default_0_71: pass
alsa_mixer-test_write_default_0_72: pass
alsa_mixer-test_write_default_0_73: pass
alsa_mixer-test_write_default_0_74: pass
alsa_mixer-test_write_default_0_75: pass
alsa_mixer-test_write_default_0_76: pass
alsa_mixer-test_write_default_0_77: fail
alsa_mixer-test_write_default_0_78: fail
alsa_mixer-test_write_default_0_79: fail
alsa_mixer-test_write_default_0_8: pass
alsa_mixer-test_write_default_0_80: pass
alsa_mixer-test_write_default_0_81: pass
alsa_mixer-test_write_default_0_82: skip
alsa_mixer-test_write_default_0_83: pass
alsa_mixer-test_write_default_0_84: pass
alsa_mixer-test_write_default_0_85: pass
alsa_mixer-test_write_default_0_86: pass
alsa_mixer-test_write_default_0_87: pass
alsa_mixer-test_write_default_0_88: pass
alsa_mixer-test_write_default_0_89: pass
alsa_mixer-test_write_default_0_9: pass
alsa_mixer-test_write_default_0_90: pass
alsa_mixer-test_write_default_0_91: pass
alsa_mixer-test_write_default_0_92: pass
alsa_mixer-test_write_default_0_93: pass
alsa_mixer-test_write_invalid_0_0: pass
alsa_mixer-test_write_invalid_0_1: pass
alsa_mixer-test_write_invalid_0_10: pass
alsa_mixer-test_write_invalid_0_11: pass
alsa_mixer-test_write_invalid_0_12: pass
alsa_mixer-test_write_invalid_0_13: pass
alsa_mixer-test_write_invalid_0_14: pass
alsa_mixer-test_write_invalid_0_15: pass
alsa_mixer-test_write_invalid_0_16: pass
alsa_mixer-test_write_invalid_0_17: pass
alsa_mixer-test_write_invalid_0_18: pass
alsa_mixer-test_write_invalid_0_19: pass
alsa_mixer-test_write_invalid_0_2: pass
alsa_mixer-test_write_invalid_0_20: pass
alsa_mixer-test_write_invalid_0_21: pass
alsa_mixer-test_write_invalid_0_22: pass
alsa_mixer-test_write_invalid_0_23: pass
alsa_mixer-test_write_invalid_0_24: pass
alsa_mixer-test_write_invalid_0_25: pass
alsa_mixer-test_write_invalid_0_26: pass
alsa_mixer-test_write_invalid_0_27: pass
alsa_mixer-test_write_invalid_0_28: pass
alsa_mixer-test_write_invalid_0_29: pass
alsa_mixer-test_write_invalid_0_3: pass
alsa_mixer-test_write_invalid_0_30: pass
alsa_mixer-test_write_invalid_0_31: pass
alsa_mixer-test_write_invalid_0_32: pass
alsa_mixer-test_write_invalid_0_33: pass
alsa_mixer-test_write_invalid_0_34: pass
alsa_mixer-test_write_invalid_0_35: pass
alsa_mixer-test_write_invalid_0_36: pass
alsa_mixer-test_write_invalid_0_37: pass
alsa_mixer-test_write_invalid_0_38: pass
alsa_mixer-test_write_invalid_0_39: pass
alsa_mixer-test_write_invalid_0_4: pass
alsa_mixer-test_write_invalid_0_40: pass
alsa_mixer-test_write_invalid_0_41: pass
alsa_mixer-test_write_invalid_0_42: pass
alsa_mixer-test_write_invalid_0_43: pass
alsa_mixer-test_write_invalid_0_44: pass
alsa_mixer-test_write_invalid_0_45: pass
alsa_mixer-test_write_invalid_0_46: pass
alsa_mixer-test_write_invalid_0_47: pass
alsa_mixer-test_write_invalid_0_48: pass
alsa_mixer-test_write_invalid_0_49: pass
alsa_mixer-test_write_invalid_0_5: pass
alsa_mixer-test_write_invalid_0_50: pass
alsa_mixer-test_write_invalid_0_51: pass
alsa_mixer-test_write_invalid_0_52: pass
alsa_mixer-test_write_invalid_0_53: pass
alsa_mixer-test_write_invalid_0_54: pass
alsa_mixer-test_write_invalid_0_55: pass
alsa_mixer-test_write_invalid_0_56: pass
alsa_mixer-test_write_invalid_0_57: pass
alsa_mixer-test_write_invalid_0_58: pass
alsa_mixer-test_write_invalid_0_59: pass
alsa_mixer-test_write_invalid_0_6: pass
alsa_mixer-test_write_invalid_0_60: pass
alsa_mixer-test_write_invalid_0_61: pass
alsa_mixer-test_write_invalid_0_62: pass
alsa_mixer-test_write_invalid_0_63: pass
alsa_mixer-test_write_invalid_0_64: pass
alsa_mixer-test_write_invalid_0_65: pass
alsa_mixer-test_write_invalid_0_66: pass
alsa_mixer-test_write_invalid_0_67: pass
alsa_mixer-test_write_invalid_0_68: pass
alsa_mixer-test_write_invalid_0_69: pass
alsa_mixer-test_write_invalid_0_7: pass
alsa_mixer-test_write_invalid_0_70: pass
alsa_mixer-test_write_invalid_0_71: pass
alsa_mixer-test_write_invalid_0_72: pass
alsa_mixer-test_write_invalid_0_73: pass
alsa_mixer-test_write_invalid_0_74: pass
alsa_mixer-test_write_invalid_0_75: pass
alsa_mixer-test_write_invalid_0_76: pass
alsa_mixer-test_write_invalid_0_77: fail
alsa_mixer-test_write_invalid_0_78: fail
alsa_mixer-test_write_invalid_0_79: fail
alsa_mixer-test_write_invalid_0_8: pass
alsa_mixer-test_write_invalid_0_80: pass
alsa_mixer-test_write_invalid_0_81: fail
alsa_mixer-test_write_invalid_0_82: skip
alsa_mixer-test_write_invalid_0_83: pass
alsa_mixer-test_write_invalid_0_84: pass
alsa_mixer-test_write_invalid_0_85: pass
alsa_mixer-test_write_invalid_0_86: pass
alsa_mixer-test_write_invalid_0_87: pass
alsa_mixer-test_write_invalid_0_88: pass
alsa_mixer-test_write_invalid_0_89: pass
alsa_mixer-test_write_invalid_0_9: pass
alsa_mixer-test_write_invalid_0_90: pass
alsa_mixer-test_write_invalid_0_91: pass
alsa_mixer-test_write_invalid_0_92: pass
alsa_mixer-test_write_invalid_0_93: pass
alsa_mixer-test_write_valid_0_0: pass
alsa_mixer-test_write_valid_0_1: pass
alsa_mixer-test_write_valid_0_10: pass
alsa_mixer-test_write_valid_0_11: pass
alsa_mixer-test_write_valid_0_12: pass
alsa_mixer-test_write_valid_0_13: pass
alsa_mixer-test_write_valid_0_14: pass
alsa_mixer-test_write_valid_0_15: pass
alsa_mixer-test_write_valid_0_16: pass
alsa_mixer-test_write_valid_0_17: pass
alsa_mixer-test_write_valid_0_18: pass
alsa_mixer-test_write_valid_0_19: pass
alsa_mixer-test_write_valid_0_2: pass
alsa_mixer-test_write_valid_0_20: pass
alsa_mixer-test_write_valid_0_21: pass
alsa_mixer-test_write_valid_0_22: pass
alsa_mixer-test_write_valid_0_23: pass
alsa_mixer-test_write_valid_0_24: pass
alsa_mixer-test_write_valid_0_25: pass
alsa_mixer-test_write_valid_0_26: pass
alsa_mixer-test_write_valid_0_27: pass
alsa_mixer-test_write_valid_0_28: pass
alsa_mixer-test_write_valid_0_29: pass
alsa_mixer-test_write_valid_0_3: pass
alsa_mixer-test_write_valid_0_30: pass
alsa_mixer-test_write_valid_0_31: pass
alsa_mixer-test_write_valid_0_32: pass
alsa_mixer-test_write_valid_0_33: pass
alsa_mixer-test_write_valid_0_34: pass
alsa_mixer-test_write_valid_0_35: pass
alsa_mixer-test_write_valid_0_36: pass
alsa_mixer-test_write_valid_0_37: pass
alsa_mixer-test_write_valid_0_38: pass
alsa_mixer-test_write_valid_0_39: pass
alsa_mixer-test_write_valid_0_4: pass
alsa_mixer-test_write_valid_0_40: pass
alsa_mixer-test_write_valid_0_41: pass
alsa_mixer-test_write_valid_0_42: pass
alsa_mixer-test_write_valid_0_43: pass
alsa_mixer-test_write_valid_0_44: pass
alsa_mixer-test_write_valid_0_45: pass
alsa_mixer-test_write_valid_0_46: pass
alsa_mixer-test_write_valid_0_47: pass
alsa_mixer-test_write_valid_0_48: pass
alsa_mixer-test_write_valid_0_49: pass
alsa_mixer-test_write_valid_0_5: pass
alsa_mixer-test_write_valid_0_50: pass
alsa_mixer-test_write_valid_0_51: pass
alsa_mixer-test_write_valid_0_52: pass
alsa_mixer-test_write_valid_0_53: pass
alsa_mixer-test_write_valid_0_54: pass
alsa_mixer-test_write_valid_0_55: pass
alsa_mixer-test_write_valid_0_56: pass
alsa_mixer-test_write_valid_0_57: pass
alsa_mixer-test_write_valid_0_58: pass
alsa_mixer-test_write_valid_0_59: pass
alsa_mixer-test_write_valid_0_6: pass
alsa_mixer-test_write_valid_0_60: pass
alsa_mixer-test_write_valid_0_61: pass
alsa_mixer-test_write_valid_0_62: pass
alsa_mixer-test_write_valid_0_63: pass
alsa_mixer-test_write_valid_0_64: pass
alsa_mixer-test_write_valid_0_65: pass
alsa_mixer-test_write_valid_0_66: pass
alsa_mixer-test_write_valid_0_67: pass
alsa_mixer-test_write_valid_0_68: pass
alsa_mixer-test_write_valid_0_69: pass
alsa_mixer-test_write_valid_0_7: pass
alsa_mixer-test_write_valid_0_70: pass
alsa_mixer-test_write_valid_0_71: pass
alsa_mixer-test_write_valid_0_72: pass
alsa_mixer-test_write_valid_0_73: pass
alsa_mixer-test_write_valid_0_74: pass
alsa_mixer-test_write_valid_0_75: pass
alsa_mixer-test_write_valid_0_76: pass
alsa_mixer-test_write_valid_0_77: fail
alsa_mixer-test_write_valid_0_78: fail
alsa_mixer-test_write_valid_0_79: fail
alsa_mixer-test_write_valid_0_8: pass
alsa_mixer-test_write_valid_0_80: pass
alsa_mixer-test_write_valid_0_81: pass
alsa_mixer-test_write_valid_0_82: skip
alsa_mixer-test_write_valid_0_83: pass
alsa_mixer-test_write_valid_0_84: pass
alsa_mixer-test_write_valid_0_85: fail
alsa_mixer-test_write_valid_0_86: fail
alsa_mixer-test_write_valid_0_87: pass
alsa_mixer-test_write_valid_0_88: fail
alsa_mixer-test_write_valid_0_89: pass
alsa_mixer-test_write_valid_0_9: pass
alsa_mixer-test_write_valid_0_90: pass
alsa_mixer-test_write_valid_0_91: pass
alsa_mixer-test_write_valid_0_92: pass
alsa_mixer-test_write_valid_0_93: pass
shardfile-alsa: pass
10020 00:57:58.948462 end: 3.1 lava-test-shell (duration 00:00:48) [common]
10021 00:57:58.948877 end: 3 lava-test-retry (duration 00:00:48) [common]
10022 00:57:58.949300 start: 4 finalize (timeout 00:07:17) [common]
10023 00:57:58.949727 start: 4.1 power-off (timeout 00:00:30) [common]
10024 00:57:58.950441 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-5', '--port=1', '--command=off']
10025 00:58:00.152459 >> Command sent successfully.
10026 00:58:00.158988 Returned 0 in 1 seconds
10027 00:58:00.259798 end: 4.1 power-off (duration 00:00:01) [common]
10029 00:58:00.261280 start: 4.2 read-feedback (timeout 00:07:16) [common]
10030 00:58:00.262536 Listened to connection for namespace 'common' for up to 1s
10031 00:58:01.262633 Finalising connection for namespace 'common'
10032 00:58:01.263301 Disconnecting from shell: Finalise
10033 00:58:01.263719 / #
10034 00:58:01.364787 end: 4.2 read-feedback (duration 00:00:01) [common]
10035 00:58:01.365716 end: 4 finalize (duration 00:00:02) [common]
10036 00:58:01.366410 Cleaning after the job
10037 00:58:01.366952 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/ramdisk
10038 00:58:01.371594 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/kernel
10039 00:58:01.382083 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/dtb
10040 00:58:01.382299 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/nfsrootfs
10041 00:58:01.445666 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368556/tftp-deploy-bd1jyqqo/modules
10042 00:58:01.451272 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368556
10043 00:58:02.011064 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368556
10044 00:58:02.011242 Job finished correctly