Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 40
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 00:54:46.954057 lava-dispatcher, installed at version: 2024.03
2 00:54:46.954285 start: 0 validate
3 00:54:46.954408 Start time: 2024-06-16 00:54:46.954402+00:00 (UTC)
4 00:54:46.954557 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:54:46.954736 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:54:47.205645 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:54:47.205815 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:55:13.220844 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:55:13.221663 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:55:13.475651 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:55:13.476286 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:55:13.724073 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:55:13.724712 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:55:15.737204 validate duration: 28.78
16 00:55:15.738493 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:55:15.739289 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:55:15.739801 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:55:15.740522 Not decompressing ramdisk as can be used compressed.
20 00:55:15.741022 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:55:15.741389 saving as /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/ramdisk/initrd.cpio.gz
22 00:55:15.741743 total size: 5628169 (5 MB)
23 00:55:15.994162 progress 0 % (0 MB)
24 00:55:15.995787 progress 5 % (0 MB)
25 00:55:15.997328 progress 10 % (0 MB)
26 00:55:15.998742 progress 15 % (0 MB)
27 00:55:16.000288 progress 20 % (1 MB)
28 00:55:16.001668 progress 25 % (1 MB)
29 00:55:16.003195 progress 30 % (1 MB)
30 00:55:16.004703 progress 35 % (1 MB)
31 00:55:16.006061 progress 40 % (2 MB)
32 00:55:16.007605 progress 45 % (2 MB)
33 00:55:16.008954 progress 50 % (2 MB)
34 00:55:16.010509 progress 55 % (2 MB)
35 00:55:16.012010 progress 60 % (3 MB)
36 00:55:16.013344 progress 65 % (3 MB)
37 00:55:16.014862 progress 70 % (3 MB)
38 00:55:16.016226 progress 75 % (4 MB)
39 00:55:16.017715 progress 80 % (4 MB)
40 00:55:16.019091 progress 85 % (4 MB)
41 00:55:16.020591 progress 90 % (4 MB)
42 00:55:16.022094 progress 95 % (5 MB)
43 00:55:16.023458 progress 100 % (5 MB)
44 00:55:16.023664 5 MB downloaded in 0.28 s (19.04 MB/s)
45 00:55:16.023806 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:55:16.024029 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:55:16.024111 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:55:16.024188 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:55:16.024316 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:55:16.024380 saving as /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/kernel/Image
52 00:55:16.024433 total size: 54813184 (52 MB)
53 00:55:16.024487 No compression specified
54 00:55:16.025484 progress 0 % (0 MB)
55 00:55:16.039081 progress 5 % (2 MB)
56 00:55:16.052772 progress 10 % (5 MB)
57 00:55:16.066574 progress 15 % (7 MB)
58 00:55:16.080501 progress 20 % (10 MB)
59 00:55:16.094429 progress 25 % (13 MB)
60 00:55:16.108290 progress 30 % (15 MB)
61 00:55:16.122193 progress 35 % (18 MB)
62 00:55:16.136562 progress 40 % (20 MB)
63 00:55:16.150434 progress 45 % (23 MB)
64 00:55:16.164982 progress 50 % (26 MB)
65 00:55:16.179095 progress 55 % (28 MB)
66 00:55:16.193049 progress 60 % (31 MB)
67 00:55:16.207227 progress 65 % (34 MB)
68 00:55:16.221213 progress 70 % (36 MB)
69 00:55:16.235795 progress 75 % (39 MB)
70 00:55:16.250194 progress 80 % (41 MB)
71 00:55:16.265250 progress 85 % (44 MB)
72 00:55:16.279535 progress 90 % (47 MB)
73 00:55:16.293558 progress 95 % (49 MB)
74 00:55:16.307709 progress 100 % (52 MB)
75 00:55:16.307951 52 MB downloaded in 0.28 s (184.38 MB/s)
76 00:55:16.308100 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:55:16.308309 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:55:16.308406 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:55:16.308540 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:55:16.308694 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:55:16.308774 saving as /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/dtb/mt8192-asurada-spherion-r0.dtb
83 00:55:16.308830 total size: 47258 (0 MB)
84 00:55:16.308888 No compression specified
85 00:55:16.309960 progress 69 % (0 MB)
86 00:55:16.310242 progress 100 % (0 MB)
87 00:55:16.310406 0 MB downloaded in 0.00 s (28.63 MB/s)
88 00:55:16.310519 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:55:16.310718 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:55:16.310795 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:55:16.310872 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:55:16.310974 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:55:16.311035 saving as /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/nfsrootfs/full.rootfs.tar
95 00:55:16.311088 total size: 120894716 (115 MB)
96 00:55:16.311142 Using unxz to decompress xz
97 00:55:16.312414 progress 0 % (0 MB)
98 00:55:16.660557 progress 5 % (5 MB)
99 00:55:17.019828 progress 10 % (11 MB)
100 00:55:17.373807 progress 15 % (17 MB)
101 00:55:17.702740 progress 20 % (23 MB)
102 00:55:18.011014 progress 25 % (28 MB)
103 00:55:18.358439 progress 30 % (34 MB)
104 00:55:18.682704 progress 35 % (40 MB)
105 00:55:18.859623 progress 40 % (46 MB)
106 00:55:19.047006 progress 45 % (51 MB)
107 00:55:19.357673 progress 50 % (57 MB)
108 00:55:19.716269 progress 55 % (63 MB)
109 00:55:20.057127 progress 60 % (69 MB)
110 00:55:20.403589 progress 65 % (74 MB)
111 00:55:20.749444 progress 70 % (80 MB)
112 00:55:21.113894 progress 75 % (86 MB)
113 00:55:21.461323 progress 80 % (92 MB)
114 00:55:21.806589 progress 85 % (98 MB)
115 00:55:22.188932 progress 90 % (103 MB)
116 00:55:22.531160 progress 95 % (109 MB)
117 00:55:22.904995 progress 100 % (115 MB)
118 00:55:22.910789 115 MB downloaded in 6.60 s (17.47 MB/s)
119 00:55:22.910993 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:55:22.911213 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:55:22.911295 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:55:22.911376 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:55:22.911506 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:55:22.911570 saving as /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/modules/modules.tar
126 00:55:22.911625 total size: 8617404 (8 MB)
127 00:55:22.911683 Using unxz to decompress xz
128 00:55:22.913045 progress 0 % (0 MB)
129 00:55:22.932304 progress 5 % (0 MB)
130 00:55:22.959921 progress 10 % (0 MB)
131 00:55:22.988224 progress 15 % (1 MB)
132 00:55:23.012286 progress 20 % (1 MB)
133 00:55:23.036120 progress 25 % (2 MB)
134 00:55:23.059947 progress 30 % (2 MB)
135 00:55:23.086322 progress 35 % (2 MB)
136 00:55:23.111014 progress 40 % (3 MB)
137 00:55:23.134380 progress 45 % (3 MB)
138 00:55:23.159886 progress 50 % (4 MB)
139 00:55:23.186127 progress 55 % (4 MB)
140 00:55:23.212515 progress 60 % (4 MB)
141 00:55:23.237906 progress 65 % (5 MB)
142 00:55:23.265981 progress 70 % (5 MB)
143 00:55:23.291414 progress 75 % (6 MB)
144 00:55:23.318190 progress 80 % (6 MB)
145 00:55:23.343706 progress 85 % (7 MB)
146 00:55:23.370374 progress 90 % (7 MB)
147 00:55:23.395920 progress 95 % (7 MB)
148 00:55:23.420540 progress 100 % (8 MB)
149 00:55:23.426342 8 MB downloaded in 0.51 s (15.97 MB/s)
150 00:55:23.426538 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:55:23.426763 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:55:23.426843 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 00:55:23.426920 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 00:55:27.025719 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368566/extract-nfsrootfs-k6gbqes9
156 00:55:27.025976 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:55:27.026069 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:55:27.026251 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x
159 00:55:27.026387 makedir: /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin
160 00:55:27.026495 makedir: /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/tests
161 00:55:27.026614 makedir: /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/results
162 00:55:27.026726 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-add-keys
163 00:55:27.026898 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-add-sources
164 00:55:27.027047 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-background-process-start
165 00:55:27.027181 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-background-process-stop
166 00:55:27.027309 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-common-functions
167 00:55:27.027429 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-echo-ipv4
168 00:55:27.027550 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-install-packages
169 00:55:27.027666 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-installed-packages
170 00:55:27.027780 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-os-build
171 00:55:27.027908 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-probe-channel
172 00:55:27.028066 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-probe-ip
173 00:55:27.028204 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-target-ip
174 00:55:27.028376 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-target-mac
175 00:55:27.028553 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-target-storage
176 00:55:27.028707 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-test-case
177 00:55:27.028913 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-test-event
178 00:55:27.029090 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-test-feedback
179 00:55:27.029249 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-test-raise
180 00:55:27.029395 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-test-reference
181 00:55:27.029540 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-test-runner
182 00:55:27.029685 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-test-set
183 00:55:27.029831 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-test-shell
184 00:55:27.030010 Updating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-add-keys (debian)
185 00:55:27.030202 Updating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-add-sources (debian)
186 00:55:27.030400 Updating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-install-packages (debian)
187 00:55:27.030559 Updating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-installed-packages (debian)
188 00:55:27.030719 Updating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/bin/lava-os-build (debian)
189 00:55:27.030865 Creating /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/environment
190 00:55:27.030972 LAVA metadata
191 00:55:27.031039 - LAVA_JOB_ID=14368566
192 00:55:27.031098 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:55:27.031204 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:55:27.031263 skipped lava-vland-overlay
195 00:55:27.031333 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:55:27.031408 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:55:27.031463 skipped lava-multinode-overlay
198 00:55:27.031529 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:55:27.031600 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:55:27.031665 Loading test definitions
201 00:55:27.031742 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:55:27.031803 Using /lava-14368566 at stage 0
203 00:55:27.032089 uuid=14368566_1.6.2.3.1 testdef=None
204 00:55:27.032173 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:55:27.032249 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:55:27.032656 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:55:27.032859 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:55:27.033378 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:55:27.033589 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:55:27.034193 runner path: /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/0/tests/0_timesync-off test_uuid 14368566_1.6.2.3.1
213 00:55:27.034379 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:55:27.034592 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:55:27.034657 Using /lava-14368566 at stage 0
217 00:55:27.034745 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:55:27.034822 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/0/tests/1_kselftest-alsa'
219 00:55:30.401292 Running '/usr/bin/git checkout kernelci.org
220 00:55:30.567258 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 00:55:30.567848 uuid=14368566_1.6.2.3.5 testdef=None
222 00:55:30.568020 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 00:55:30.568319 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 00:55:30.569323 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:55:30.569641 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 00:55:30.571043 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:55:30.571468 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 00:55:30.572840 runner path: /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/0/tests/1_kselftest-alsa test_uuid 14368566_1.6.2.3.5
232 00:55:30.572962 BOARD='mt8192-asurada-spherion-r0'
233 00:55:30.573057 BRANCH='cip-gitlab'
234 00:55:30.573144 SKIPFILE='/dev/null'
235 00:55:30.573227 SKIP_INSTALL='True'
236 00:55:30.573309 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:55:30.573395 TST_CASENAME=''
238 00:55:30.573476 TST_CMDFILES='alsa'
239 00:55:30.573673 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:55:30.573976 Creating lava-test-runner.conf files
242 00:55:30.574065 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368566/lava-overlay-e66pr87x/lava-14368566/0 for stage 0
243 00:55:30.574191 - 0_timesync-off
244 00:55:30.574291 - 1_kselftest-alsa
245 00:55:30.574424 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 00:55:30.574542 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 00:55:37.815821 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:55:37.815956 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 00:55:37.816037 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:55:37.816117 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 00:55:37.816196 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 00:55:37.974736 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:55:37.974885 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 00:55:37.974959 extracting modules file /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368566/extract-nfsrootfs-k6gbqes9
255 00:55:38.211833 extracting modules file /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368566/extract-overlay-ramdisk-13x5is92/ramdisk
256 00:55:38.439496 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:55:38.439643 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 00:55:38.439726 [common] Applying overlay to NFS
259 00:55:38.439785 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368566/compress-overlay-6si19by6/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368566/extract-nfsrootfs-k6gbqes9
260 00:55:39.279251 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:55:39.279390 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 00:55:39.279476 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:55:39.279555 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 00:55:39.279622 Building ramdisk /var/lib/lava/dispatcher/tmp/14368566/extract-overlay-ramdisk-13x5is92/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368566/extract-overlay-ramdisk-13x5is92/ramdisk
265 00:55:39.722518 >> 130405 blocks
266 00:55:41.838589 rename /var/lib/lava/dispatcher/tmp/14368566/extract-overlay-ramdisk-13x5is92/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/ramdisk/ramdisk.cpio.gz
267 00:55:41.838762 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 00:55:41.838853 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 00:55:41.838932 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 00:55:41.839006 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/kernel/Image']
271 00:55:56.447185 Returned 0 in 14 seconds
272 00:55:56.547699 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/kernel/image.itb
273 00:55:56.970609 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:55:56.970761 output: Created: Sun Jun 16 01:55:56 2024
275 00:55:56.970862 output: Image 0 (kernel-1)
276 00:55:56.970946 output: Description:
277 00:55:56.971027 output: Created: Sun Jun 16 01:55:56 2024
278 00:55:56.971114 output: Type: Kernel Image
279 00:55:56.971206 output: Compression: lzma compressed
280 00:55:56.971311 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
281 00:55:56.971407 output: Architecture: AArch64
282 00:55:56.971483 output: OS: Linux
283 00:55:56.971563 output: Load Address: 0x00000000
284 00:55:56.971644 output: Entry Point: 0x00000000
285 00:55:56.971730 output: Hash algo: crc32
286 00:55:56.971811 output: Hash value: f6f06660
287 00:55:56.971897 output: Image 1 (fdt-1)
288 00:55:56.971980 output: Description: mt8192-asurada-spherion-r0
289 00:55:56.972063 output: Created: Sun Jun 16 01:55:56 2024
290 00:55:56.972151 output: Type: Flat Device Tree
291 00:55:56.972237 output: Compression: uncompressed
292 00:55:56.972328 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:55:56.972414 output: Architecture: AArch64
294 00:55:56.972496 output: Hash algo: crc32
295 00:55:56.972558 output: Hash value: 0f8e4d2e
296 00:55:56.972642 output: Image 2 (ramdisk-1)
297 00:55:56.972724 output: Description: unavailable
298 00:55:56.972808 output: Created: Sun Jun 16 01:55:56 2024
299 00:55:56.972887 output: Type: RAMDisk Image
300 00:55:56.972963 output: Compression: uncompressed
301 00:55:56.973041 output: Data Size: 18732631 Bytes = 18293.58 KiB = 17.86 MiB
302 00:55:56.973119 output: Architecture: AArch64
303 00:55:56.973194 output: OS: Linux
304 00:55:56.973272 output: Load Address: unavailable
305 00:55:56.973354 output: Entry Point: unavailable
306 00:55:56.973429 output: Hash algo: crc32
307 00:55:56.973507 output: Hash value: 489bd00c
308 00:55:56.973585 output: Default Configuration: 'conf-1'
309 00:55:56.973663 output: Configuration 0 (conf-1)
310 00:55:56.973741 output: Description: mt8192-asurada-spherion-r0
311 00:55:56.973822 output: Kernel: kernel-1
312 00:55:56.973910 output: Init Ramdisk: ramdisk-1
313 00:55:56.973989 output: FDT: fdt-1
314 00:55:56.974066 output: Loadables: kernel-1
315 00:55:56.974140 output:
316 00:55:56.974371 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 00:55:56.974495 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 00:55:56.974615 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 00:55:56.974729 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 00:55:56.974824 No LXC device requested
321 00:55:56.974923 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:55:56.975027 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 00:55:56.975124 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:55:56.975214 Checking files for TFTP limit of 4294967296 bytes.
325 00:55:56.975800 end: 1 tftp-deploy (duration 00:00:41) [common]
326 00:55:56.975928 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:55:56.976164 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:55:56.976369 substitutions:
329 00:55:56.976462 - {DTB}: 14368566/tftp-deploy-3k9xqh2p/dtb/mt8192-asurada-spherion-r0.dtb
330 00:55:56.976555 - {INITRD}: 14368566/tftp-deploy-3k9xqh2p/ramdisk/ramdisk.cpio.gz
331 00:55:56.976638 - {KERNEL}: 14368566/tftp-deploy-3k9xqh2p/kernel/Image
332 00:55:56.976721 - {LAVA_MAC}: None
333 00:55:56.976800 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368566/extract-nfsrootfs-k6gbqes9
334 00:55:56.976889 - {NFS_SERVER_IP}: 192.168.201.1
335 00:55:56.976982 - {PRESEED_CONFIG}: None
336 00:55:56.977067 - {PRESEED_LOCAL}: None
337 00:55:56.977153 - {RAMDISK}: 14368566/tftp-deploy-3k9xqh2p/ramdisk/ramdisk.cpio.gz
338 00:55:56.977231 - {ROOT_PART}: None
339 00:55:56.977313 - {ROOT}: None
340 00:55:56.977393 - {SERVER_IP}: 192.168.201.1
341 00:55:56.977471 - {TEE}: None
342 00:55:56.977548 Parsed boot commands:
343 00:55:56.977626 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:55:56.977854 Parsed boot commands: tftpboot 192.168.201.1 14368566/tftp-deploy-3k9xqh2p/kernel/image.itb 14368566/tftp-deploy-3k9xqh2p/kernel/cmdline
345 00:55:56.977962 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:55:56.978068 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:55:56.978183 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:55:56.978308 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:55:56.978374 Not connected, no need to disconnect.
350 00:55:56.978468 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:55:56.978568 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:55:56.978634 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 00:55:56.982185 Setting prompt string to ['lava-test: # ']
354 00:55:56.982619 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:55:56.982746 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:55:56.982874 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:55:56.983032 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:55:56.983296 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-4']
359 00:56:10.624664 Returned 0 in 13 seconds
360 00:56:10.725490 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 00:56:10.726516 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 00:56:10.726832 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 00:56:10.727104 Setting prompt string to 'Starting depthcharge on Spherion...'
365 00:56:10.727316 Changing prompt to 'Starting depthcharge on Spherion...'
366 00:56:10.727537 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 00:56:10.728608 [Enter `^Ec?' for help]
368 00:56:10.728792
369 00:56:10.728943
370 00:56:10.729146 F0: 102B 0000
371 00:56:10.729358
372 00:56:10.729599 F3: 1001 0000 [0200]
373 00:56:10.729779
374 00:56:10.729924 F3: 1001 0000
375 00:56:10.730065
376 00:56:10.730229 F7: 102D 0000
377 00:56:10.730388
378 00:56:10.730538 F1: 0000 0000
379 00:56:10.730690
380 00:56:10.730838 V0: 0000 0000 [0001]
381 00:56:10.730984
382 00:56:10.731125 00: 0007 8000
383 00:56:10.731276
384 00:56:10.731421 01: 0000 0000
385 00:56:10.731556
386 00:56:10.731682 BP: 0C00 0209 [0000]
387 00:56:10.731808
388 00:56:10.731932 G0: 1182 0000
389 00:56:10.732057
390 00:56:10.732181 EC: 0000 0021 [4000]
391 00:56:10.732306
392 00:56:10.732509 S7: 0000 0000 [0000]
393 00:56:10.732708
394 00:56:10.732845 CC: 0000 0000 [0001]
395 00:56:10.732975
396 00:56:10.733102 T0: 0000 0040 [010F]
397 00:56:10.733230
398 00:56:10.733353 Jump to BL
399 00:56:10.733476
400 00:56:10.733582
401 00:56:10.733684
402 00:56:10.733787 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 00:56:10.733898 ARM64: Exception handlers installed.
404 00:56:10.734002 ARM64: Testing exception
405 00:56:10.734104 ARM64: Done test exception
406 00:56:10.734207 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 00:56:10.734335 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 00:56:10.734446 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 00:56:10.734552 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 00:56:10.734658 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 00:56:10.734763 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 00:56:10.734867 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 00:56:10.734971 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 00:56:10.735075 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 00:56:10.735180 WDT: Last reset was cold boot
416 00:56:10.735284 SPI1(PAD0) initialized at 2873684 Hz
417 00:56:10.735389 SPI5(PAD0) initialized at 992727 Hz
418 00:56:10.735492 VBOOT: Loading verstage.
419 00:56:10.735594 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 00:56:10.735749 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 00:56:10.735913 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 00:56:10.736090 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 00:56:10.736245 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 00:56:10.736357 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 00:56:10.736462 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 00:56:10.736565
427 00:56:10.736667
428 00:56:10.736767 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 00:56:10.736872 ARM64: Exception handlers installed.
430 00:56:10.736974 ARM64: Testing exception
431 00:56:10.737077 ARM64: Done test exception
432 00:56:10.737179 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 00:56:10.737282 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 00:56:10.737386 Probing TPM: . done!
435 00:56:10.737489 TPM ready after 0 ms
436 00:56:10.737593 Connected to device vid:did:rid of 1ae0:0028:00
437 00:56:10.737697 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
438 00:56:10.737801 Initialized TPM device CR50 revision 0
439 00:56:10.737904 tlcl_send_startup: Startup return code is 0
440 00:56:10.738007 TPM: setup succeeded
441 00:56:10.738109 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 00:56:10.738234 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 00:56:10.738345 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 00:56:10.738453 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:56:10.738539 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 00:56:10.738626 in-header: 03 07 00 00 08 00 00 00
447 00:56:10.738712 in-data: aa e4 47 04 13 02 00 00
448 00:56:10.738798 Chrome EC: UHEPI supported
449 00:56:10.738885 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 00:56:10.738972 in-header: 03 a9 00 00 08 00 00 00
451 00:56:10.739059 in-data: 84 60 60 08 00 00 00 00
452 00:56:10.739144 Phase 1
453 00:56:10.739231 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 00:56:10.739375 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 00:56:10.739520 VB2:vb2_check_recovery() Recovery was requested manually
456 00:56:10.739625 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 00:56:10.739715 Recovery requested (1009000e)
458 00:56:10.739804 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 00:56:10.739892 tlcl_extend: response is 0
460 00:56:10.739979 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 00:56:10.740065 tlcl_extend: response is 0
462 00:56:10.740152 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 00:56:10.740241 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 00:56:10.740327 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 00:56:10.740416
466 00:56:10.740502
467 00:56:10.740587 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 00:56:10.740675 ARM64: Exception handlers installed.
469 00:56:10.740762 ARM64: Testing exception
470 00:56:10.740848 ARM64: Done test exception
471 00:56:10.740935 pmic_efuse_setting: Set efuses in 11 msecs
472 00:56:10.741021 pmwrap_interface_init: Select PMIF_VLD_RDY
473 00:56:10.741106 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 00:56:10.741193 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 00:56:10.741508 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 00:56:10.741618 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 00:56:10.741709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 00:56:10.741798 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 00:56:10.741887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 00:56:10.741976 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 00:56:10.742063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 00:56:10.742151 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 00:56:10.742304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 00:56:10.742447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 00:56:10.742599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 00:56:10.742723 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 00:56:10.742815 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 00:56:10.742904 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 00:56:10.742992 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 00:56:10.743080 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 00:56:10.743168 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 00:56:10.743254 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 00:56:10.743341 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 00:56:10.743436 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 00:56:10.743512 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 00:56:10.743586 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 00:56:10.743661 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 00:56:10.743737 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 00:56:10.743814 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 00:56:10.743891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 00:56:10.743967 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 00:56:10.744042 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 00:56:10.744116 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 00:56:10.744190 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 00:56:10.744264 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 00:56:10.744338 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 00:56:10.744412 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 00:56:10.744487 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 00:56:10.744560 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 00:56:10.744635 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 00:56:10.744713 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 00:56:10.744788 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 00:56:10.744863 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 00:56:10.744937 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 00:56:10.745012 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 00:56:10.745087 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 00:56:10.745161 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 00:56:10.745235 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 00:56:10.745309 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 00:56:10.745384 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 00:56:10.745470 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 00:56:10.745593 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 00:56:10.745714 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 00:56:10.745797 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 00:56:10.745873 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 00:56:10.745949 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 00:56:10.746025 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 00:56:10.746101 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 00:56:10.746177 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 00:56:10.746268 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:56:10.746344 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:56:10.746419 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x4
533 00:56:10.746493 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 00:56:10.746568 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 00:56:10.746643 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 00:56:10.746719 [RTC]rtc_get_frequency_meter,154: input=15, output=764
537 00:56:10.746794 [RTC]rtc_get_frequency_meter,154: input=23, output=949
538 00:56:10.746869 [RTC]rtc_get_frequency_meter,154: input=19, output=857
539 00:56:10.746944 [RTC]rtc_get_frequency_meter,154: input=17, output=811
540 00:56:10.747019 [RTC]rtc_get_frequency_meter,154: input=16, output=789
541 00:56:10.747093 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 00:56:10.747176 [RTC]rtc_get_frequency_meter,154: input=17, output=811
543 00:56:10.747260 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 00:56:10.747336 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 00:56:10.747644 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 00:56:10.747806 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 00:56:10.747963 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 00:56:10.748117 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 00:56:10.748271 ADC[4]: Raw value=670432 ID=5
550 00:56:10.748436 ADC[3]: Raw value=212917 ID=1
551 00:56:10.748569 RAM Code: 0x51
552 00:56:10.748705 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 00:56:10.748845 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 00:56:10.748989 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
555 00:56:10.749135 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
556 00:56:10.749275 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 00:56:10.749416 in-header: 03 07 00 00 08 00 00 00
558 00:56:10.749559 in-data: aa e4 47 04 13 02 00 00
559 00:56:10.749637 Chrome EC: UHEPI supported
560 00:56:10.749707 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 00:56:10.749777 in-header: 03 a9 00 00 08 00 00 00
562 00:56:10.749844 in-data: 84 60 60 08 00 00 00 00
563 00:56:10.749910 MRC: failed to locate region type 0.
564 00:56:10.749977 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 00:56:10.750044 DRAM-K: Running full calibration
566 00:56:10.750109 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
567 00:56:10.750175 header.status = 0x0
568 00:56:10.750257 header.version = 0x6 (expected: 0x6)
569 00:56:10.750325 header.size = 0xd00 (expected: 0xd00)
570 00:56:10.750391 header.flags = 0x0
571 00:56:10.750457 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 00:56:10.750524 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 00:56:10.750590 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 00:56:10.750657 dram_init: ddr_geometry: 0
575 00:56:10.750722 [EMI] MDL number = 0
576 00:56:10.750786 [EMI] Get MDL freq = 0
577 00:56:10.750851 dram_init: ddr_type: 0
578 00:56:10.750916 is_discrete_lpddr4: 1
579 00:56:10.750981 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 00:56:10.751047
581 00:56:10.751131
582 00:56:10.751202 [Bian_co] ETT version 0.0.0.1
583 00:56:10.751270 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
584 00:56:10.751337
585 00:56:10.751402 dramc_set_vcore_voltage set vcore to 650000
586 00:56:10.751469 Read voltage for 800, 4
587 00:56:10.751534 Vio18 = 0
588 00:56:10.751599 Vcore = 650000
589 00:56:10.751665 Vdram = 0
590 00:56:10.751730 Vddq = 0
591 00:56:10.751796 Vmddr = 0
592 00:56:10.751860 dram_init: config_dvfs: 1
593 00:56:10.751926 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 00:56:10.751992 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 00:56:10.752058 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 00:56:10.752123 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 00:56:10.752190 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 00:56:10.752254 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 00:56:10.752320 MEM_TYPE=3, freq_sel=18
600 00:56:10.752385 sv_algorithm_assistance_LP4_1600
601 00:56:10.752450 ============ PULL DRAM RESETB DOWN ============
602 00:56:10.752521 ========== PULL DRAM RESETB DOWN end =========
603 00:56:10.752588 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 00:56:10.752653 ===================================
605 00:56:10.752719 LPDDR4 DRAM CONFIGURATION
606 00:56:10.752800 ===================================
607 00:56:10.752925 EX_ROW_EN[0] = 0x0
608 00:56:10.752995 EX_ROW_EN[1] = 0x0
609 00:56:10.753061 LP4Y_EN = 0x0
610 00:56:10.753126 WORK_FSP = 0x0
611 00:56:10.753191 WL = 0x2
612 00:56:10.753256 RL = 0x2
613 00:56:10.753322 BL = 0x2
614 00:56:10.753387 RPST = 0x0
615 00:56:10.753460 RD_PRE = 0x0
616 00:56:10.753519 WR_PRE = 0x1
617 00:56:10.753577 WR_PST = 0x0
618 00:56:10.753635 DBI_WR = 0x0
619 00:56:10.753694 DBI_RD = 0x0
620 00:56:10.753752 OTF = 0x1
621 00:56:10.753811 ===================================
622 00:56:10.753870 ===================================
623 00:56:10.753929 ANA top config
624 00:56:10.753987 ===================================
625 00:56:10.754045 DLL_ASYNC_EN = 0
626 00:56:10.754104 ALL_SLAVE_EN = 1
627 00:56:10.754162 NEW_RANK_MODE = 1
628 00:56:10.754230 DLL_IDLE_MODE = 1
629 00:56:10.754290 LP45_APHY_COMB_EN = 1
630 00:56:10.754349 TX_ODT_DIS = 1
631 00:56:10.754408 NEW_8X_MODE = 1
632 00:56:10.754466 ===================================
633 00:56:10.754525 ===================================
634 00:56:10.754583 data_rate = 1600
635 00:56:10.754642 CKR = 1
636 00:56:10.754700 DQ_P2S_RATIO = 8
637 00:56:10.754759 ===================================
638 00:56:10.754818 CA_P2S_RATIO = 8
639 00:56:10.754876 DQ_CA_OPEN = 0
640 00:56:10.754934 DQ_SEMI_OPEN = 0
641 00:56:10.754992 CA_SEMI_OPEN = 0
642 00:56:10.755051 CA_FULL_RATE = 0
643 00:56:10.755108 DQ_CKDIV4_EN = 1
644 00:56:10.755166 CA_CKDIV4_EN = 1
645 00:56:10.755224 CA_PREDIV_EN = 0
646 00:56:10.755282 PH8_DLY = 0
647 00:56:10.755340 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 00:56:10.755398 DQ_AAMCK_DIV = 4
649 00:56:10.755456 CA_AAMCK_DIV = 4
650 00:56:10.755513 CA_ADMCK_DIV = 4
651 00:56:10.755571 DQ_TRACK_CA_EN = 0
652 00:56:10.755629 CA_PICK = 800
653 00:56:10.755687 CA_MCKIO = 800
654 00:56:10.755744 MCKIO_SEMI = 0
655 00:56:10.755802 PLL_FREQ = 3068
656 00:56:10.755860 DQ_UI_PI_RATIO = 32
657 00:56:10.755920 CA_UI_PI_RATIO = 0
658 00:56:10.755978 ===================================
659 00:56:10.756037 ===================================
660 00:56:10.756095 memory_type:LPDDR4
661 00:56:10.756154 GP_NUM : 10
662 00:56:10.756212 SRAM_EN : 1
663 00:56:10.756269 MD32_EN : 0
664 00:56:10.756327 ===================================
665 00:56:10.756612 [ANA_INIT] >>>>>>>>>>>>>>
666 00:56:10.756682 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 00:56:10.756746 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 00:56:10.756806 ===================================
669 00:56:10.756865 data_rate = 1600,PCW = 0X7600
670 00:56:10.756924 ===================================
671 00:56:10.756983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 00:56:10.757042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 00:56:10.757100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 00:56:10.757160 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 00:56:10.757219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 00:56:10.757278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 00:56:10.757336 [ANA_INIT] flow start
678 00:56:10.757393 [ANA_INIT] PLL >>>>>>>>
679 00:56:10.757450 [ANA_INIT] PLL <<<<<<<<
680 00:56:10.757508 [ANA_INIT] MIDPI >>>>>>>>
681 00:56:10.757566 [ANA_INIT] MIDPI <<<<<<<<
682 00:56:10.757623 [ANA_INIT] DLL >>>>>>>>
683 00:56:10.757680 [ANA_INIT] flow end
684 00:56:10.757738 ============ LP4 DIFF to SE enter ============
685 00:56:10.757796 ============ LP4 DIFF to SE exit ============
686 00:56:10.757854 [ANA_INIT] <<<<<<<<<<<<<
687 00:56:10.757912 [Flow] Enable top DCM control >>>>>
688 00:56:10.757970 [Flow] Enable top DCM control <<<<<
689 00:56:10.758028 Enable DLL master slave shuffle
690 00:56:10.758086 ==============================================================
691 00:56:10.758145 Gating Mode config
692 00:56:10.758202 ==============================================================
693 00:56:10.758273 Config description:
694 00:56:10.758332 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 00:56:10.758393 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 00:56:10.758461 SELPH_MODE 0: By rank 1: By Phase
697 00:56:10.758514 ==============================================================
698 00:56:10.758565 GAT_TRACK_EN = 1
699 00:56:10.758618 RX_GATING_MODE = 2
700 00:56:10.758670 RX_GATING_TRACK_MODE = 2
701 00:56:10.758723 SELPH_MODE = 1
702 00:56:10.758776 PICG_EARLY_EN = 1
703 00:56:10.758848 VALID_LAT_VALUE = 1
704 00:56:10.758902 ==============================================================
705 00:56:10.758956 Enter into Gating configuration >>>>
706 00:56:10.759010 Exit from Gating configuration <<<<
707 00:56:10.759062 Enter into DVFS_PRE_config >>>>>
708 00:56:10.759115 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 00:56:10.759172 Exit from DVFS_PRE_config <<<<<
710 00:56:10.759225 Enter into PICG configuration >>>>
711 00:56:10.759278 Exit from PICG configuration <<<<
712 00:56:10.759330 [RX_INPUT] configuration >>>>>
713 00:56:10.759383 [RX_INPUT] configuration <<<<<
714 00:56:10.759435 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 00:56:10.759489 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 00:56:10.759542 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 00:56:10.759595 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 00:56:10.759649 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 00:56:10.759703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 00:56:10.759758 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 00:56:10.759810 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 00:56:10.759863 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 00:56:10.759916 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 00:56:10.759967 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 00:56:10.760019 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 00:56:10.760072 ===================================
727 00:56:10.760124 LPDDR4 DRAM CONFIGURATION
728 00:56:10.760177 ===================================
729 00:56:10.760229 EX_ROW_EN[0] = 0x0
730 00:56:10.760281 EX_ROW_EN[1] = 0x0
731 00:56:10.760332 LP4Y_EN = 0x0
732 00:56:10.760384 WORK_FSP = 0x0
733 00:56:10.760436 WL = 0x2
734 00:56:10.760487 RL = 0x2
735 00:56:10.760538 BL = 0x2
736 00:56:10.760590 RPST = 0x0
737 00:56:10.760642 RD_PRE = 0x0
738 00:56:10.760694 WR_PRE = 0x1
739 00:56:10.760746 WR_PST = 0x0
740 00:56:10.760797 DBI_WR = 0x0
741 00:56:10.760849 DBI_RD = 0x0
742 00:56:10.760900 OTF = 0x1
743 00:56:10.760953 ===================================
744 00:56:10.761006 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 00:56:10.761058 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 00:56:10.761111 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 00:56:10.761164 ===================================
748 00:56:10.761216 LPDDR4 DRAM CONFIGURATION
749 00:56:10.761269 ===================================
750 00:56:10.761321 EX_ROW_EN[0] = 0x10
751 00:56:10.761374 EX_ROW_EN[1] = 0x0
752 00:56:10.761427 LP4Y_EN = 0x0
753 00:56:10.761479 WORK_FSP = 0x0
754 00:56:10.761532 WL = 0x2
755 00:56:10.761584 RL = 0x2
756 00:56:10.761635 BL = 0x2
757 00:56:10.761687 RPST = 0x0
758 00:56:10.761739 RD_PRE = 0x0
759 00:56:10.761800 WR_PRE = 0x1
760 00:56:10.761886 WR_PST = 0x0
761 00:56:10.761976 DBI_WR = 0x0
762 00:56:10.762061 DBI_RD = 0x0
763 00:56:10.762146 OTF = 0x1
764 00:56:10.762236 ===================================
765 00:56:10.762294 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 00:56:10.762349 nWR fixed to 40
767 00:56:10.762403 [ModeRegInit_LP4] CH0 RK0
768 00:56:10.762455 [ModeRegInit_LP4] CH0 RK1
769 00:56:10.762507 [ModeRegInit_LP4] CH1 RK0
770 00:56:10.762559 [ModeRegInit_LP4] CH1 RK1
771 00:56:10.762611 match AC timing 12
772 00:56:10.762665 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
773 00:56:10.762718 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 00:56:10.763007 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 00:56:10.763121 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 00:56:10.763216 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 00:56:10.763308 [EMI DOE] emi_dcm 0
778 00:56:10.763422 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 00:56:10.763483 ==
780 00:56:10.763535 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:56:10.763585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 00:56:10.763635 ==
783 00:56:10.763684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 00:56:10.763733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 00:56:10.763782 [CA 0] Center 37 (7~68) winsize 62
786 00:56:10.763831 [CA 1] Center 37 (6~68) winsize 63
787 00:56:10.763880 [CA 2] Center 35 (5~66) winsize 62
788 00:56:10.763928 [CA 3] Center 35 (5~66) winsize 62
789 00:56:10.763976 [CA 4] Center 34 (3~65) winsize 63
790 00:56:10.764025 [CA 5] Center 33 (3~64) winsize 62
791 00:56:10.764072
792 00:56:10.764120 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 00:56:10.764168
794 00:56:10.764216 [CATrainingPosCal] consider 1 rank data
795 00:56:10.764264 u2DelayCellTimex100 = 270/100 ps
796 00:56:10.764312 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 00:56:10.764360 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 00:56:10.764408 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
799 00:56:10.764456 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
800 00:56:10.764504 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
801 00:56:10.764553 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 00:56:10.764600
803 00:56:10.764648 CA PerBit enable=1, Macro0, CA PI delay=33
804 00:56:10.764695
805 00:56:10.764742 [CBTSetCACLKResult] CA Dly = 33
806 00:56:10.764793 CS Dly: 6 (0~37)
807 00:56:10.764870 ==
808 00:56:10.764937 Dram Type= 6, Freq= 0, CH_0, rank 1
809 00:56:10.764986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
810 00:56:10.765035 ==
811 00:56:10.765083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 00:56:10.765132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 00:56:10.765181 [CA 0] Center 37 (6~68) winsize 63
814 00:56:10.765229 [CA 1] Center 36 (6~67) winsize 62
815 00:56:10.765277 [CA 2] Center 35 (4~66) winsize 63
816 00:56:10.765325 [CA 3] Center 34 (4~65) winsize 62
817 00:56:10.765373 [CA 4] Center 33 (3~64) winsize 62
818 00:56:10.765421 [CA 5] Center 33 (3~64) winsize 62
819 00:56:10.765468
820 00:56:10.765515 [CmdBusTrainingLP45] Vref(ca) range 1: 30
821 00:56:10.765563
822 00:56:10.765611 [CATrainingPosCal] consider 2 rank data
823 00:56:10.765659 u2DelayCellTimex100 = 270/100 ps
824 00:56:10.765707 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 00:56:10.765755 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
826 00:56:10.765803 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
827 00:56:10.765851 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
828 00:56:10.765899 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 00:56:10.765947 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 00:56:10.766021
831 00:56:10.766099 CA PerBit enable=1, Macro0, CA PI delay=33
832 00:56:10.766174
833 00:56:10.766280 [CBTSetCACLKResult] CA Dly = 33
834 00:56:10.766331 CS Dly: 6 (0~38)
835 00:56:10.766379
836 00:56:10.766427 ----->DramcWriteLeveling(PI) begin...
837 00:56:10.766476 ==
838 00:56:10.766525 Dram Type= 6, Freq= 0, CH_0, rank 0
839 00:56:10.766574 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
840 00:56:10.766622 ==
841 00:56:10.766670 Write leveling (Byte 0): 31 => 31
842 00:56:10.766718 Write leveling (Byte 1): 27 => 27
843 00:56:10.766766 DramcWriteLeveling(PI) end<-----
844 00:56:10.766814
845 00:56:10.766861 ==
846 00:56:10.766908 Dram Type= 6, Freq= 0, CH_0, rank 0
847 00:56:10.766956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
848 00:56:10.767004 ==
849 00:56:10.767052 [Gating] SW mode calibration
850 00:56:10.767101 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 00:56:10.767150 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 00:56:10.767199 0 6 0 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
853 00:56:10.767248 0 6 4 | B1->B0 | 2727 2323 | 0 0 | (1 1) (1 0)
854 00:56:10.767306 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:56:10.767378 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:56:10.767429 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:56:10.767478 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:56:10.767525 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:56:10.767574 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:56:10.767622 0 7 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
861 00:56:10.767671 0 7 4 | B1->B0 | 3b3b 4242 | 1 0 | (0 0) (0 0)
862 00:56:10.767719 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 00:56:10.767767 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 00:56:10.767815 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 00:56:10.767863 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 00:56:10.767911 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 00:56:10.767959 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 00:56:10.768007 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
869 00:56:10.768056 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
870 00:56:10.768104 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 00:56:10.768152 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 00:56:10.768200 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 00:56:10.768249 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 00:56:10.768296 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 00:56:10.768344 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 00:56:10.768393 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 00:56:10.768441 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 00:56:10.768489 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 00:56:10.768536 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 00:56:10.768585 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 00:56:10.768833 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 00:56:10.768890 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 00:56:10.768941 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 00:56:10.768990 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 00:56:10.769039 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 00:56:10.769108 Total UI for P1: 0, mck2ui 16
887 00:56:10.769161 best dqsien dly found for B0: ( 0, 10, 2)
888 00:56:10.769210 Total UI for P1: 0, mck2ui 16
889 00:56:10.769258 best dqsien dly found for B1: ( 0, 10, 2)
890 00:56:10.769306 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
891 00:56:10.769355 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
892 00:56:10.769402
893 00:56:10.769449 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
894 00:56:10.769497 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
895 00:56:10.769544 [Gating] SW calibration Done
896 00:56:10.769592 ==
897 00:56:10.769640 Dram Type= 6, Freq= 0, CH_0, rank 0
898 00:56:10.769688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 00:56:10.769736 ==
900 00:56:10.769783 RX Vref Scan: 0
901 00:56:10.769831
902 00:56:10.769878 RX Vref 0 -> 0, step: 1
903 00:56:10.769924
904 00:56:10.769971 RX Delay -130 -> 252, step: 16
905 00:56:10.770019 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
906 00:56:10.770067 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
907 00:56:10.770115 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
908 00:56:10.770163 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
909 00:56:10.770217 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
910 00:56:10.770302 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
911 00:56:10.770350 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
912 00:56:10.770396 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
913 00:56:10.770444 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
914 00:56:10.770491 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
915 00:56:10.770539 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
916 00:56:10.770587 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
917 00:56:10.770634 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
918 00:56:10.770681 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
919 00:56:10.770759 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
920 00:56:10.770810 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
921 00:56:10.770858 ==
922 00:56:10.770907 Dram Type= 6, Freq= 0, CH_0, rank 0
923 00:56:10.770956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
924 00:56:10.771004 ==
925 00:56:10.771052 DQS Delay:
926 00:56:10.771099 DQS0 = 0, DQS1 = 0
927 00:56:10.771147 DQM Delay:
928 00:56:10.771195 DQM0 = 84, DQM1 = 74
929 00:56:10.771243 DQ Delay:
930 00:56:10.771290 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
931 00:56:10.771338 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
932 00:56:10.771386 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
933 00:56:10.771434 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
934 00:56:10.771481
935 00:56:10.771528
936 00:56:10.771575 ==
937 00:56:10.771623 Dram Type= 6, Freq= 0, CH_0, rank 0
938 00:56:10.771670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
939 00:56:10.771719 ==
940 00:56:10.771766
941 00:56:10.771813
942 00:56:10.771860 TX Vref Scan disable
943 00:56:10.771907 == TX Byte 0 ==
944 00:56:10.771955 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
945 00:56:10.772003 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
946 00:56:10.772056 == TX Byte 1 ==
947 00:56:10.772120 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
948 00:56:10.772169 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
949 00:56:10.772217 ==
950 00:56:10.772265 Dram Type= 6, Freq= 0, CH_0, rank 0
951 00:56:10.772313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
952 00:56:10.772362 ==
953 00:56:10.772409 TX Vref=22, minBit 3, minWin=27, winSum=444
954 00:56:10.772458 TX Vref=24, minBit 3, minWin=27, winSum=445
955 00:56:10.772506 TX Vref=26, minBit 4, minWin=27, winSum=451
956 00:56:10.772554 TX Vref=28, minBit 0, minWin=27, winSum=451
957 00:56:10.772602 TX Vref=30, minBit 5, minWin=27, winSum=453
958 00:56:10.772650 TX Vref=32, minBit 4, minWin=27, winSum=447
959 00:56:10.772698 [TxChooseVref] Worse bit 5, Min win 27, Win sum 453, Final Vref 30
960 00:56:10.772746
961 00:56:10.772794 Final TX Range 1 Vref 30
962 00:56:10.772842
963 00:56:10.772889 ==
964 00:56:10.772937 Dram Type= 6, Freq= 0, CH_0, rank 0
965 00:56:10.772985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
966 00:56:10.773033 ==
967 00:56:10.773080
968 00:56:10.773127
969 00:56:10.773174 TX Vref Scan disable
970 00:56:10.773222 == TX Byte 0 ==
971 00:56:10.773270 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
972 00:56:10.773318 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
973 00:56:10.773366 == TX Byte 1 ==
974 00:56:10.773413 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
975 00:56:10.773461 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
976 00:56:10.773509
977 00:56:10.773556 [DATLAT]
978 00:56:10.773603 Freq=800, CH0 RK0
979 00:56:10.773650
980 00:56:10.773697 DATLAT Default: 0xa
981 00:56:10.773745 0, 0xFFFF, sum = 0
982 00:56:10.773794 1, 0xFFFF, sum = 0
983 00:56:10.773843 2, 0xFFFF, sum = 0
984 00:56:10.773915 3, 0xFFFF, sum = 0
985 00:56:10.773998 4, 0xFFFF, sum = 0
986 00:56:10.774076 5, 0xFFFF, sum = 0
987 00:56:10.774153 6, 0xFFFF, sum = 0
988 00:56:10.774250 7, 0xFFFF, sum = 0
989 00:56:10.774315 8, 0x0, sum = 1
990 00:56:10.774365 9, 0x0, sum = 2
991 00:56:10.774414 10, 0x0, sum = 3
992 00:56:10.774462 11, 0x0, sum = 4
993 00:56:10.774511 best_step = 9
994 00:56:10.774559
995 00:56:10.774606 ==
996 00:56:10.774653 Dram Type= 6, Freq= 0, CH_0, rank 0
997 00:56:10.774701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
998 00:56:10.774749 ==
999 00:56:10.774796 RX Vref Scan: 1
1000 00:56:10.774842
1001 00:56:10.774889 Set Vref Range= 32 -> 127
1002 00:56:10.774936
1003 00:56:10.774984 RX Vref 32 -> 127, step: 1
1004 00:56:10.775032
1005 00:56:10.775079 RX Delay -111 -> 252, step: 8
1006 00:56:10.775127
1007 00:56:10.775174 Set Vref, RX VrefLevel [Byte0]: 32
1008 00:56:10.775222 [Byte1]: 32
1009 00:56:10.775270
1010 00:56:10.775317 Set Vref, RX VrefLevel [Byte0]: 33
1011 00:56:10.775366 [Byte1]: 33
1012 00:56:10.775417
1013 00:56:10.775484 Set Vref, RX VrefLevel [Byte0]: 34
1014 00:56:10.775534 [Byte1]: 34
1015 00:56:10.775582
1016 00:56:10.775629 Set Vref, RX VrefLevel [Byte0]: 35
1017 00:56:10.775678 [Byte1]: 35
1018 00:56:10.775726
1019 00:56:10.775773 Set Vref, RX VrefLevel [Byte0]: 36
1020 00:56:10.775821 [Byte1]: 36
1021 00:56:10.775869
1022 00:56:10.775919 Set Vref, RX VrefLevel [Byte0]: 37
1023 00:56:10.775968 [Byte1]: 37
1024 00:56:10.776016
1025 00:56:10.776063 Set Vref, RX VrefLevel [Byte0]: 38
1026 00:56:10.776111 [Byte1]: 38
1027 00:56:10.776159
1028 00:56:10.776207 Set Vref, RX VrefLevel [Byte0]: 39
1029 00:56:10.776255 [Byte1]: 39
1030 00:56:10.776301
1031 00:56:10.776541 Set Vref, RX VrefLevel [Byte0]: 40
1032 00:56:10.776596 [Byte1]: 40
1033 00:56:10.776645
1034 00:56:10.776692 Set Vref, RX VrefLevel [Byte0]: 41
1035 00:56:10.776741 [Byte1]: 41
1036 00:56:10.776789
1037 00:56:10.776836 Set Vref, RX VrefLevel [Byte0]: 42
1038 00:56:10.776884 [Byte1]: 42
1039 00:56:10.776932
1040 00:56:10.776979 Set Vref, RX VrefLevel [Byte0]: 43
1041 00:56:10.777028 [Byte1]: 43
1042 00:56:10.777076
1043 00:56:10.777124 Set Vref, RX VrefLevel [Byte0]: 44
1044 00:56:10.777171 [Byte1]: 44
1045 00:56:10.777219
1046 00:56:10.777266 Set Vref, RX VrefLevel [Byte0]: 45
1047 00:56:10.777314 [Byte1]: 45
1048 00:56:10.777362
1049 00:56:10.777408 Set Vref, RX VrefLevel [Byte0]: 46
1050 00:56:10.777456 [Byte1]: 46
1051 00:56:10.777512
1052 00:56:10.777577 Set Vref, RX VrefLevel [Byte0]: 47
1053 00:56:10.777627 [Byte1]: 47
1054 00:56:10.777675
1055 00:56:10.777723 Set Vref, RX VrefLevel [Byte0]: 48
1056 00:56:10.777771 [Byte1]: 48
1057 00:56:10.777818
1058 00:56:10.777865 Set Vref, RX VrefLevel [Byte0]: 49
1059 00:56:10.777913 [Byte1]: 49
1060 00:56:10.777961
1061 00:56:10.778009 Set Vref, RX VrefLevel [Byte0]: 50
1062 00:56:10.778056 [Byte1]: 50
1063 00:56:10.778134
1064 00:56:10.778262 Set Vref, RX VrefLevel [Byte0]: 51
1065 00:56:10.778332 [Byte1]: 51
1066 00:56:10.778380
1067 00:56:10.778428 Set Vref, RX VrefLevel [Byte0]: 52
1068 00:56:10.778477 [Byte1]: 52
1069 00:56:10.778525
1070 00:56:10.778573 Set Vref, RX VrefLevel [Byte0]: 53
1071 00:56:10.778621 [Byte1]: 53
1072 00:56:10.778668
1073 00:56:10.778716 Set Vref, RX VrefLevel [Byte0]: 54
1074 00:56:10.778764 [Byte1]: 54
1075 00:56:10.778811
1076 00:56:10.778858 Set Vref, RX VrefLevel [Byte0]: 55
1077 00:56:10.778914 [Byte1]: 55
1078 00:56:10.778974
1079 00:56:10.779022 Set Vref, RX VrefLevel [Byte0]: 56
1080 00:56:10.779070 [Byte1]: 56
1081 00:56:10.779118
1082 00:56:10.779166 Set Vref, RX VrefLevel [Byte0]: 57
1083 00:56:10.779214 [Byte1]: 57
1084 00:56:10.779261
1085 00:56:10.779307 Set Vref, RX VrefLevel [Byte0]: 58
1086 00:56:10.779354 [Byte1]: 58
1087 00:56:10.779402
1088 00:56:10.779451 Set Vref, RX VrefLevel [Byte0]: 59
1089 00:56:10.779499 [Byte1]: 59
1090 00:56:10.779547
1091 00:56:10.779595 Set Vref, RX VrefLevel [Byte0]: 60
1092 00:56:10.779642 [Byte1]: 60
1093 00:56:10.779690
1094 00:56:10.779736 Set Vref, RX VrefLevel [Byte0]: 61
1095 00:56:10.779784 [Byte1]: 61
1096 00:56:10.779831
1097 00:56:10.779878 Set Vref, RX VrefLevel [Byte0]: 62
1098 00:56:10.779926 [Byte1]: 62
1099 00:56:10.779973
1100 00:56:10.780020 Set Vref, RX VrefLevel [Byte0]: 63
1101 00:56:10.780069 [Byte1]: 63
1102 00:56:10.780116
1103 00:56:10.780164 Set Vref, RX VrefLevel [Byte0]: 64
1104 00:56:10.780212 [Byte1]: 64
1105 00:56:10.780259
1106 00:56:10.780306 Set Vref, RX VrefLevel [Byte0]: 65
1107 00:56:10.780353 [Byte1]: 65
1108 00:56:10.780400
1109 00:56:10.780448 Set Vref, RX VrefLevel [Byte0]: 66
1110 00:56:10.780495 [Byte1]: 66
1111 00:56:10.780542
1112 00:56:10.780590 Set Vref, RX VrefLevel [Byte0]: 67
1113 00:56:10.780637 [Byte1]: 67
1114 00:56:10.780684
1115 00:56:10.780732 Set Vref, RX VrefLevel [Byte0]: 68
1116 00:56:10.780779 [Byte1]: 68
1117 00:56:10.780826
1118 00:56:10.780874 Set Vref, RX VrefLevel [Byte0]: 69
1119 00:56:10.780922 [Byte1]: 69
1120 00:56:10.780969
1121 00:56:10.781030 Set Vref, RX VrefLevel [Byte0]: 70
1122 00:56:10.781091 [Byte1]: 70
1123 00:56:10.781139
1124 00:56:10.781187 Set Vref, RX VrefLevel [Byte0]: 71
1125 00:56:10.781235 [Byte1]: 71
1126 00:56:10.781282
1127 00:56:10.781330 Set Vref, RX VrefLevel [Byte0]: 72
1128 00:56:10.781378 [Byte1]: 72
1129 00:56:10.781425
1130 00:56:10.781473 Set Vref, RX VrefLevel [Byte0]: 73
1131 00:56:10.781521 [Byte1]: 73
1132 00:56:10.781568
1133 00:56:10.781615 Final RX Vref Byte 0 = 53 to rank0
1134 00:56:10.781664 Final RX Vref Byte 1 = 54 to rank0
1135 00:56:10.781711 Final RX Vref Byte 0 = 53 to rank1
1136 00:56:10.781760 Final RX Vref Byte 1 = 54 to rank1==
1137 00:56:10.781808 Dram Type= 6, Freq= 0, CH_0, rank 0
1138 00:56:10.781856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1139 00:56:10.781904 ==
1140 00:56:10.781951 DQS Delay:
1141 00:56:10.781999 DQS0 = 0, DQS1 = 0
1142 00:56:10.782047 DQM Delay:
1143 00:56:10.782095 DQM0 = 83, DQM1 = 73
1144 00:56:10.782142 DQ Delay:
1145 00:56:10.782189 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1146 00:56:10.782267 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1147 00:56:10.782330 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1148 00:56:10.782404 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1149 00:56:10.782454
1150 00:56:10.782503
1151 00:56:10.782551 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1152 00:56:10.782600 CH0 RK0: MR19=606, MR18=3F3F
1153 00:56:10.782648 CH0_RK0: MR19=0x606, MR18=0x3F3F, DQSOSC=393, MR23=63, INC=95, DEC=63
1154 00:56:10.782696
1155 00:56:10.782744 ----->DramcWriteLeveling(PI) begin...
1156 00:56:10.782793 ==
1157 00:56:10.782842 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 00:56:10.782890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1159 00:56:10.782938 ==
1160 00:56:10.782986 Write leveling (Byte 0): 30 => 30
1161 00:56:10.783034 Write leveling (Byte 1): 30 => 30
1162 00:56:10.783081 DramcWriteLeveling(PI) end<-----
1163 00:56:10.783129
1164 00:56:10.783176 ==
1165 00:56:10.783224 Dram Type= 6, Freq= 0, CH_0, rank 1
1166 00:56:10.783272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1167 00:56:10.783320 ==
1168 00:56:10.783367 [Gating] SW mode calibration
1169 00:56:10.783415 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1170 00:56:10.783464 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1171 00:56:10.783513 0 6 0 | B1->B0 | 3232 3030 | 0 1 | (0 1) (1 1)
1172 00:56:10.783562 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1173 00:56:10.783610 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:56:10.783658 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:56:10.783705 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:56:10.783753 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:56:10.783801 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:56:10.784042 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:56:10.784096 0 7 0 | B1->B0 | 2929 3232 | 0 1 | (0 0) (0 0)
1180 00:56:10.784146 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1181 00:56:10.784195 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1182 00:56:10.784244 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 00:56:10.784292 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 00:56:10.784340 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 00:56:10.784393 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 00:56:10.784485 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 00:56:10.784537 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1188 00:56:10.784601 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1189 00:56:10.784649 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 00:56:10.784698 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 00:56:10.784746 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 00:56:10.784794 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 00:56:10.784843 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 00:56:10.784891 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 00:56:10.784939 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 00:56:10.784987 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 00:56:10.785035 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 00:56:10.785083 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 00:56:10.785132 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 00:56:10.785180 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 00:56:10.785228 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 00:56:10.785275 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1203 00:56:10.785337 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1204 00:56:10.785391 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 00:56:10.785440 Total UI for P1: 0, mck2ui 16
1206 00:56:10.785490 best dqsien dly found for B0: ( 0, 9, 30)
1207 00:56:10.785538 Total UI for P1: 0, mck2ui 16
1208 00:56:10.785587 best dqsien dly found for B1: ( 0, 10, 0)
1209 00:56:10.785635 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1210 00:56:10.785682 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1211 00:56:10.785730
1212 00:56:10.785778 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1213 00:56:10.785827 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1214 00:56:10.785876 [Gating] SW calibration Done
1215 00:56:10.785924 ==
1216 00:56:10.785972 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 00:56:10.786020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1218 00:56:10.786068 ==
1219 00:56:10.786115 RX Vref Scan: 0
1220 00:56:10.786162
1221 00:56:10.786216 RX Vref 0 -> 0, step: 1
1222 00:56:10.786309
1223 00:56:10.786358 RX Delay -130 -> 252, step: 16
1224 00:56:10.786406 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1225 00:56:10.786455 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1226 00:56:10.786502 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1227 00:56:10.786550 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1228 00:56:10.786598 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1229 00:56:10.786645 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1230 00:56:10.786693 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1231 00:56:10.786741 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1232 00:56:10.786789 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1233 00:56:10.786837 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1234 00:56:10.786885 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1235 00:56:10.786933 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1236 00:56:10.786981 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1237 00:56:10.787029 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1238 00:56:10.787102 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1239 00:56:10.787155 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1240 00:56:10.787204 ==
1241 00:56:10.787253 Dram Type= 6, Freq= 0, CH_0, rank 1
1242 00:56:10.787301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1243 00:56:10.787350 ==
1244 00:56:10.787398 DQS Delay:
1245 00:56:10.787446 DQS0 = 0, DQS1 = 0
1246 00:56:10.787493 DQM Delay:
1247 00:56:10.787540 DQM0 = 85, DQM1 = 73
1248 00:56:10.787587 DQ Delay:
1249 00:56:10.787635 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1250 00:56:10.787684 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1251 00:56:10.787732 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1252 00:56:10.787780 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1253 00:56:10.787828
1254 00:56:10.787875
1255 00:56:10.787923 ==
1256 00:56:10.787970 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 00:56:10.788018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1258 00:56:10.788066 ==
1259 00:56:10.788114
1260 00:56:10.788161
1261 00:56:10.788208 TX Vref Scan disable
1262 00:56:10.788255 == TX Byte 0 ==
1263 00:56:10.788303 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1264 00:56:10.788352 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1265 00:56:10.788400 == TX Byte 1 ==
1266 00:56:10.788451 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1267 00:56:10.788505 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1268 00:56:10.788553 ==
1269 00:56:10.788602 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 00:56:10.788650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1271 00:56:10.788699 ==
1272 00:56:10.788747 TX Vref=22, minBit 9, minWin=27, winSum=450
1273 00:56:10.788795 TX Vref=24, minBit 0, minWin=28, winSum=451
1274 00:56:10.788843 TX Vref=26, minBit 0, minWin=28, winSum=456
1275 00:56:10.788891 TX Vref=28, minBit 4, minWin=28, winSum=459
1276 00:56:10.788939 TX Vref=30, minBit 2, minWin=28, winSum=459
1277 00:56:10.789010 TX Vref=32, minBit 1, minWin=28, winSum=458
1278 00:56:10.789061 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 28
1279 00:56:10.789109
1280 00:56:10.789157 Final TX Range 1 Vref 28
1281 00:56:10.789205
1282 00:56:10.789252 ==
1283 00:56:10.789300 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 00:56:10.789347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1285 00:56:10.789396 ==
1286 00:56:10.789443
1287 00:56:10.789490
1288 00:56:10.789537 TX Vref Scan disable
1289 00:56:10.789585 == TX Byte 0 ==
1290 00:56:10.789633 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1291 00:56:10.789682 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1292 00:56:10.789730 == TX Byte 1 ==
1293 00:56:10.789777 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1294 00:56:10.790019 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1295 00:56:10.790073
1296 00:56:10.790121 [DATLAT]
1297 00:56:10.790170 Freq=800, CH0 RK1
1298 00:56:10.790243
1299 00:56:10.790307 DATLAT Default: 0x9
1300 00:56:10.790356 0, 0xFFFF, sum = 0
1301 00:56:10.790405 1, 0xFFFF, sum = 0
1302 00:56:10.790454 2, 0xFFFF, sum = 0
1303 00:56:10.790503 3, 0xFFFF, sum = 0
1304 00:56:10.790552 4, 0xFFFF, sum = 0
1305 00:56:10.790601 5, 0xFFFF, sum = 0
1306 00:56:10.790649 6, 0xFFFF, sum = 0
1307 00:56:10.790697 7, 0xFFFF, sum = 0
1308 00:56:10.790746 8, 0x0, sum = 1
1309 00:56:10.790794 9, 0x0, sum = 2
1310 00:56:10.790842 10, 0x0, sum = 3
1311 00:56:10.790892 11, 0x0, sum = 4
1312 00:56:10.790953 best_step = 9
1313 00:56:10.791014
1314 00:56:10.791062 ==
1315 00:56:10.791110 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 00:56:10.791158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1317 00:56:10.791205 ==
1318 00:56:10.791253 RX Vref Scan: 0
1319 00:56:10.791301
1320 00:56:10.791348 RX Vref 0 -> 0, step: 1
1321 00:56:10.791395
1322 00:56:10.791442 RX Delay -111 -> 252, step: 8
1323 00:56:10.791490 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1324 00:56:10.791538 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1325 00:56:10.791586 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1326 00:56:10.791633 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1327 00:56:10.791680 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1328 00:56:10.791728 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1329 00:56:10.791775 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1330 00:56:10.791823 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1331 00:56:10.791870 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1332 00:56:10.791917 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1333 00:56:10.791965 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1334 00:56:10.792013 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1335 00:56:10.792063 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1336 00:56:10.792110 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1337 00:56:10.792157 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1338 00:56:10.792204 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1339 00:56:10.792252 ==
1340 00:56:10.792300 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 00:56:10.792349 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1342 00:56:10.792417 ==
1343 00:56:10.792470 DQS Delay:
1344 00:56:10.792518 DQS0 = 0, DQS1 = 0
1345 00:56:10.792566 DQM Delay:
1346 00:56:10.792614 DQM0 = 86, DQM1 = 74
1347 00:56:10.792662 DQ Delay:
1348 00:56:10.792710 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =84
1349 00:56:10.792759 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1350 00:56:10.792806 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1351 00:56:10.792853 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1352 00:56:10.792902
1353 00:56:10.792949
1354 00:56:10.792996 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e4e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1355 00:56:10.793045 CH0 RK1: MR19=606, MR18=4E4E
1356 00:56:10.793093 CH0_RK1: MR19=0x606, MR18=0x4E4E, DQSOSC=390, MR23=63, INC=97, DEC=64
1357 00:56:10.793141 [RxdqsGatingPostProcess] freq 800
1358 00:56:10.793189 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1359 00:56:10.793237 Pre-setting of DQS Precalculation
1360 00:56:10.793285 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1361 00:56:10.793333 ==
1362 00:56:10.793381 Dram Type= 6, Freq= 0, CH_1, rank 0
1363 00:56:10.793428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1364 00:56:10.793475 ==
1365 00:56:10.793523 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1366 00:56:10.793571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1367 00:56:10.793619 [CA 0] Center 36 (6~67) winsize 62
1368 00:56:10.793666 [CA 1] Center 36 (5~67) winsize 63
1369 00:56:10.793713 [CA 2] Center 34 (4~65) winsize 62
1370 00:56:10.793761 [CA 3] Center 34 (4~64) winsize 61
1371 00:56:10.793808 [CA 4] Center 33 (2~64) winsize 63
1372 00:56:10.793854 [CA 5] Center 33 (3~64) winsize 62
1373 00:56:10.793901
1374 00:56:10.793947 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1375 00:56:10.793996
1376 00:56:10.794042 [CATrainingPosCal] consider 1 rank data
1377 00:56:10.794090 u2DelayCellTimex100 = 270/100 ps
1378 00:56:10.794137 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1379 00:56:10.794184 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1380 00:56:10.794275 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1381 00:56:10.794323 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1382 00:56:10.794369 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1383 00:56:10.794416 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1384 00:56:10.794478
1385 00:56:10.794537 CA PerBit enable=1, Macro0, CA PI delay=33
1386 00:56:10.794585
1387 00:56:10.794632 [CBTSetCACLKResult] CA Dly = 33
1388 00:56:10.794681 CS Dly: 4 (0~35)
1389 00:56:10.794728 ==
1390 00:56:10.794775 Dram Type= 6, Freq= 0, CH_1, rank 1
1391 00:56:10.794823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1392 00:56:10.794870 ==
1393 00:56:10.794918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1394 00:56:10.794966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1395 00:56:10.795015 [CA 0] Center 36 (5~67) winsize 63
1396 00:56:10.795062 [CA 1] Center 36 (5~67) winsize 63
1397 00:56:10.795109 [CA 2] Center 34 (4~65) winsize 62
1398 00:56:10.795155 [CA 3] Center 34 (3~65) winsize 63
1399 00:56:10.795201 [CA 4] Center 33 (3~64) winsize 62
1400 00:56:10.795249 [CA 5] Center 33 (2~64) winsize 63
1401 00:56:10.795296
1402 00:56:10.795343 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1403 00:56:10.795391
1404 00:56:10.795437 [CATrainingPosCal] consider 2 rank data
1405 00:56:10.795484 u2DelayCellTimex100 = 270/100 ps
1406 00:56:10.795531 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1407 00:56:10.795578 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1408 00:56:10.795647 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1409 00:56:10.795698 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1410 00:56:10.795745 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1411 00:56:10.795792 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1412 00:56:10.795839
1413 00:56:10.795885 CA PerBit enable=1, Macro0, CA PI delay=33
1414 00:56:10.795931
1415 00:56:10.795977 [CBTSetCACLKResult] CA Dly = 33
1416 00:56:10.796024 CS Dly: 4 (0~36)
1417 00:56:10.796070
1418 00:56:10.796116 ----->DramcWriteLeveling(PI) begin...
1419 00:56:10.796164 ==
1420 00:56:10.796212 Dram Type= 6, Freq= 0, CH_1, rank 0
1421 00:56:10.796259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1422 00:56:10.796307 ==
1423 00:56:10.796355 Write leveling (Byte 0): 23 => 23
1424 00:56:10.796402 Write leveling (Byte 1): 23 => 23
1425 00:56:10.796449 DramcWriteLeveling(PI) end<-----
1426 00:56:10.796496
1427 00:56:10.796543 ==
1428 00:56:10.796589 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 00:56:10.796827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1430 00:56:10.796882 ==
1431 00:56:10.796930 [Gating] SW mode calibration
1432 00:56:10.796978 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1433 00:56:10.797030 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1434 00:56:10.797091 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (1 0)
1435 00:56:10.797139 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1436 00:56:10.797187 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1437 00:56:10.797235 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 00:56:10.797283 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 00:56:10.797331 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 00:56:10.797378 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 00:56:10.797425 0 6 28 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
1442 00:56:10.797473 0 7 0 | B1->B0 | 2929 4343 | 0 0 | (0 0) (0 0)
1443 00:56:10.797520 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1444 00:56:10.797567 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1445 00:56:10.797645 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1446 00:56:10.797696 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 00:56:10.797744 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 00:56:10.797791 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 00:56:10.797839 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1450 00:56:10.797887 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1451 00:56:10.797934 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1452 00:56:10.797981 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 00:56:10.798028 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 00:56:10.798075 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 00:56:10.798122 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 00:56:10.798170 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 00:56:10.798227 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 00:56:10.798309 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 00:56:10.798357 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 00:56:10.798404 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 00:56:10.798452 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 00:56:10.798499 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 00:56:10.798546 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 00:56:10.798593 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 00:56:10.798641 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1466 00:56:10.798710 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1467 00:56:10.798760 Total UI for P1: 0, mck2ui 16
1468 00:56:10.798808 best dqsien dly found for B0: ( 0, 9, 28)
1469 00:56:10.798856 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1470 00:56:10.798904 Total UI for P1: 0, mck2ui 16
1471 00:56:10.798952 best dqsien dly found for B1: ( 0, 10, 0)
1472 00:56:10.798999 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1473 00:56:10.799053 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1474 00:56:10.799113
1475 00:56:10.799161 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1476 00:56:10.799208 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1477 00:56:10.799255 [Gating] SW calibration Done
1478 00:56:10.799302 ==
1479 00:56:10.799350 Dram Type= 6, Freq= 0, CH_1, rank 0
1480 00:56:10.799398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1481 00:56:10.799445 ==
1482 00:56:10.799492 RX Vref Scan: 0
1483 00:56:10.799539
1484 00:56:10.799586 RX Vref 0 -> 0, step: 1
1485 00:56:10.799633
1486 00:56:10.799679 RX Delay -130 -> 252, step: 16
1487 00:56:10.799726 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1488 00:56:10.799774 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1489 00:56:10.799821 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1490 00:56:10.799868 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1491 00:56:10.799915 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1492 00:56:10.799962 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1493 00:56:10.800010 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1494 00:56:10.800058 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1495 00:56:10.800104 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1496 00:56:10.800151 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1497 00:56:10.800198 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1498 00:56:10.800246 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1499 00:56:10.800293 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1500 00:56:10.800340 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1501 00:56:10.800387 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1502 00:56:10.800434 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1503 00:56:10.800481 ==
1504 00:56:10.800528 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 00:56:10.800575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1506 00:56:10.800622 ==
1507 00:56:10.800670 DQS Delay:
1508 00:56:10.800717 DQS0 = 0, DQS1 = 0
1509 00:56:10.800792 DQM Delay:
1510 00:56:10.800844 DQM0 = 81, DQM1 = 71
1511 00:56:10.800892 DQ Delay:
1512 00:56:10.800940 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1513 00:56:10.800989 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1514 00:56:10.801036 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1515 00:56:10.801112 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1516 00:56:10.801201
1517 00:56:10.801280
1518 00:56:10.801355 ==
1519 00:56:10.801430 Dram Type= 6, Freq= 0, CH_1, rank 0
1520 00:56:10.801506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1521 00:56:10.801580 ==
1522 00:56:10.801631
1523 00:56:10.801678
1524 00:56:10.801725 TX Vref Scan disable
1525 00:56:10.801773 == TX Byte 0 ==
1526 00:56:10.801820 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1527 00:56:10.801867 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1528 00:56:10.801914 == TX Byte 1 ==
1529 00:56:10.801962 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1530 00:56:10.802041 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1531 00:56:10.802117 ==
1532 00:56:10.802193 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 00:56:10.802294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1534 00:56:10.802343 ==
1535 00:56:10.802391 TX Vref=22, minBit 0, minWin=28, winSum=452
1536 00:56:10.802439 TX Vref=24, minBit 0, minWin=28, winSum=461
1537 00:56:10.802677 TX Vref=26, minBit 3, minWin=28, winSum=462
1538 00:56:10.802733 TX Vref=28, minBit 0, minWin=28, winSum=459
1539 00:56:10.802783 TX Vref=30, minBit 9, minWin=28, winSum=462
1540 00:56:10.802830 TX Vref=32, minBit 9, minWin=28, winSum=462
1541 00:56:10.802878 [TxChooseVref] Worse bit 3, Min win 28, Win sum 462, Final Vref 26
1542 00:56:10.802926
1543 00:56:10.802974 Final TX Range 1 Vref 26
1544 00:56:10.803021
1545 00:56:10.803068 ==
1546 00:56:10.803115 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 00:56:10.803163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1548 00:56:10.803210 ==
1549 00:56:10.803257
1550 00:56:10.803303
1551 00:56:10.803350 TX Vref Scan disable
1552 00:56:10.803397 == TX Byte 0 ==
1553 00:56:10.803445 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1554 00:56:10.803493 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1555 00:56:10.803541 == TX Byte 1 ==
1556 00:56:10.803588 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1557 00:56:10.803636 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1558 00:56:10.803683
1559 00:56:10.803729 [DATLAT]
1560 00:56:10.803776 Freq=800, CH1 RK0
1561 00:56:10.803822
1562 00:56:10.803869 DATLAT Default: 0xa
1563 00:56:10.803916 0, 0xFFFF, sum = 0
1564 00:56:10.803965 1, 0xFFFF, sum = 0
1565 00:56:10.804013 2, 0xFFFF, sum = 0
1566 00:56:10.804061 3, 0xFFFF, sum = 0
1567 00:56:10.804109 4, 0xFFFF, sum = 0
1568 00:56:10.804156 5, 0xFFFF, sum = 0
1569 00:56:10.804224 6, 0xFFFF, sum = 0
1570 00:56:10.804280 7, 0xFFFF, sum = 0
1571 00:56:10.804329 8, 0x0, sum = 1
1572 00:56:10.804378 9, 0x0, sum = 2
1573 00:56:10.804425 10, 0x0, sum = 3
1574 00:56:10.804473 11, 0x0, sum = 4
1575 00:56:10.804521 best_step = 9
1576 00:56:10.804568
1577 00:56:10.804615 ==
1578 00:56:10.804662 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 00:56:10.804710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1580 00:56:10.804758 ==
1581 00:56:10.804805 RX Vref Scan: 1
1582 00:56:10.804852
1583 00:56:10.804900 Set Vref Range= 32 -> 127
1584 00:56:10.804947
1585 00:56:10.804994 RX Vref 32 -> 127, step: 1
1586 00:56:10.805040
1587 00:56:10.805087 RX Delay -111 -> 252, step: 8
1588 00:56:10.805133
1589 00:56:10.805179 Set Vref, RX VrefLevel [Byte0]: 32
1590 00:56:10.805252 [Byte1]: 32
1591 00:56:10.805303
1592 00:56:10.805351 Set Vref, RX VrefLevel [Byte0]: 33
1593 00:56:10.805399 [Byte1]: 33
1594 00:56:10.805445
1595 00:56:10.805492 Set Vref, RX VrefLevel [Byte0]: 34
1596 00:56:10.805540 [Byte1]: 34
1597 00:56:10.805587
1598 00:56:10.805634 Set Vref, RX VrefLevel [Byte0]: 35
1599 00:56:10.805682 [Byte1]: 35
1600 00:56:10.805730
1601 00:56:10.805777 Set Vref, RX VrefLevel [Byte0]: 36
1602 00:56:10.805825 [Byte1]: 36
1603 00:56:10.805871
1604 00:56:10.805918 Set Vref, RX VrefLevel [Byte0]: 37
1605 00:56:10.805966 [Byte1]: 37
1606 00:56:10.806013
1607 00:56:10.806059 Set Vref, RX VrefLevel [Byte0]: 38
1608 00:56:10.806106 [Byte1]: 38
1609 00:56:10.806154
1610 00:56:10.806200 Set Vref, RX VrefLevel [Byte0]: 39
1611 00:56:10.806281 [Byte1]: 39
1612 00:56:10.806343
1613 00:56:10.806390 Set Vref, RX VrefLevel [Byte0]: 40
1614 00:56:10.806437 [Byte1]: 40
1615 00:56:10.806483
1616 00:56:10.806530 Set Vref, RX VrefLevel [Byte0]: 41
1617 00:56:10.806577 [Byte1]: 41
1618 00:56:10.806624
1619 00:56:10.806671 Set Vref, RX VrefLevel [Byte0]: 42
1620 00:56:10.806718 [Byte1]: 42
1621 00:56:10.806765
1622 00:56:10.806812 Set Vref, RX VrefLevel [Byte0]: 43
1623 00:56:10.806859 [Byte1]: 43
1624 00:56:10.806906
1625 00:56:10.806953 Set Vref, RX VrefLevel [Byte0]: 44
1626 00:56:10.807000 [Byte1]: 44
1627 00:56:10.807047
1628 00:56:10.807094 Set Vref, RX VrefLevel [Byte0]: 45
1629 00:56:10.807172 [Byte1]: 45
1630 00:56:10.807223
1631 00:56:10.807270 Set Vref, RX VrefLevel [Byte0]: 46
1632 00:56:10.807318 [Byte1]: 46
1633 00:56:10.807366
1634 00:56:10.807413 Set Vref, RX VrefLevel [Byte0]: 47
1635 00:56:10.807461 [Byte1]: 47
1636 00:56:10.807509
1637 00:56:10.807556 Set Vref, RX VrefLevel [Byte0]: 48
1638 00:56:10.807603 [Byte1]: 48
1639 00:56:10.807650
1640 00:56:10.807697 Set Vref, RX VrefLevel [Byte0]: 49
1641 00:56:10.807745 [Byte1]: 49
1642 00:56:10.807793
1643 00:56:10.807840 Set Vref, RX VrefLevel [Byte0]: 50
1644 00:56:10.807887 [Byte1]: 50
1645 00:56:10.807933
1646 00:56:10.807980 Set Vref, RX VrefLevel [Byte0]: 51
1647 00:56:10.808027 [Byte1]: 51
1648 00:56:10.808074
1649 00:56:10.808121 Set Vref, RX VrefLevel [Byte0]: 52
1650 00:56:10.808169 [Byte1]: 52
1651 00:56:10.808216
1652 00:56:10.808263 Set Vref, RX VrefLevel [Byte0]: 53
1653 00:56:10.808310 [Byte1]: 53
1654 00:56:10.808356
1655 00:56:10.808402 Set Vref, RX VrefLevel [Byte0]: 54
1656 00:56:10.808450 [Byte1]: 54
1657 00:56:10.808500
1658 00:56:10.808566 Set Vref, RX VrefLevel [Byte0]: 55
1659 00:56:10.808615 [Byte1]: 55
1660 00:56:10.808662
1661 00:56:10.808709 Set Vref, RX VrefLevel [Byte0]: 56
1662 00:56:10.808757 [Byte1]: 56
1663 00:56:10.808803
1664 00:56:10.808849 Set Vref, RX VrefLevel [Byte0]: 57
1665 00:56:10.808897 [Byte1]: 57
1666 00:56:10.808944
1667 00:56:10.808991 Set Vref, RX VrefLevel [Byte0]: 58
1668 00:56:10.809038 [Byte1]: 58
1669 00:56:10.809085
1670 00:56:10.809132 Set Vref, RX VrefLevel [Byte0]: 59
1671 00:56:10.809179 [Byte1]: 59
1672 00:56:10.809227
1673 00:56:10.809274 Set Vref, RX VrefLevel [Byte0]: 60
1674 00:56:10.809321 [Byte1]: 60
1675 00:56:10.809368
1676 00:56:10.809415 Set Vref, RX VrefLevel [Byte0]: 61
1677 00:56:10.809481 [Byte1]: 61
1678 00:56:10.809531
1679 00:56:10.809579 Set Vref, RX VrefLevel [Byte0]: 62
1680 00:56:10.809627 [Byte1]: 62
1681 00:56:10.809675
1682 00:56:10.809722 Set Vref, RX VrefLevel [Byte0]: 63
1683 00:56:10.809769 [Byte1]: 63
1684 00:56:10.809818
1685 00:56:10.809865 Set Vref, RX VrefLevel [Byte0]: 64
1686 00:56:10.809912 [Byte1]: 64
1687 00:56:10.809962
1688 00:56:10.810017 Set Vref, RX VrefLevel [Byte0]: 65
1689 00:56:10.810065 [Byte1]: 65
1690 00:56:10.810113
1691 00:56:10.810160 Set Vref, RX VrefLevel [Byte0]: 66
1692 00:56:10.810208 [Byte1]: 66
1693 00:56:10.810299
1694 00:56:10.810346 Set Vref, RX VrefLevel [Byte0]: 67
1695 00:56:10.810393 [Byte1]: 67
1696 00:56:10.810448
1697 00:56:10.810515 Set Vref, RX VrefLevel [Byte0]: 68
1698 00:56:10.810565 [Byte1]: 68
1699 00:56:10.810612
1700 00:56:10.810659 Set Vref, RX VrefLevel [Byte0]: 69
1701 00:56:10.810707 [Byte1]: 69
1702 00:56:10.810754
1703 00:56:10.810801 Set Vref, RX VrefLevel [Byte0]: 70
1704 00:56:10.810849 [Byte1]: 70
1705 00:56:10.810896
1706 00:56:10.811132 Set Vref, RX VrefLevel [Byte0]: 71
1707 00:56:10.811186 [Byte1]: 71
1708 00:56:10.811235
1709 00:56:10.811283 Set Vref, RX VrefLevel [Byte0]: 72
1710 00:56:10.811330 [Byte1]: 72
1711 00:56:10.811378
1712 00:56:10.811426 Set Vref, RX VrefLevel [Byte0]: 73
1713 00:56:10.811474 [Byte1]: 73
1714 00:56:10.811521
1715 00:56:10.811568 Set Vref, RX VrefLevel [Byte0]: 74
1716 00:56:10.811616 [Byte1]: 74
1717 00:56:10.811663
1718 00:56:10.811711 Final RX Vref Byte 0 = 60 to rank0
1719 00:56:10.811758 Final RX Vref Byte 1 = 52 to rank0
1720 00:56:10.811806 Final RX Vref Byte 0 = 60 to rank1
1721 00:56:10.811853 Final RX Vref Byte 1 = 52 to rank1==
1722 00:56:10.811901 Dram Type= 6, Freq= 0, CH_1, rank 0
1723 00:56:10.811949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1724 00:56:10.811997 ==
1725 00:56:10.812044 DQS Delay:
1726 00:56:10.812092 DQS0 = 0, DQS1 = 0
1727 00:56:10.812140 DQM Delay:
1728 00:56:10.812191 DQM0 = 79, DQM1 = 71
1729 00:56:10.812247 DQ Delay:
1730 00:56:10.812294 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1731 00:56:10.812342 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1732 00:56:10.812390 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1733 00:56:10.812438 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1734 00:56:10.812485
1735 00:56:10.812557
1736 00:56:10.812607 [DQSOSCAuto] RK0, (LSB)MR18= 0x5959, (MSB)MR19= 0x606, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
1737 00:56:10.812656 CH1 RK0: MR19=606, MR18=5959
1738 00:56:10.812703 CH1_RK0: MR19=0x606, MR18=0x5959, DQSOSC=387, MR23=63, INC=98, DEC=65
1739 00:56:10.812751
1740 00:56:10.812799 ----->DramcWriteLeveling(PI) begin...
1741 00:56:10.812847 ==
1742 00:56:10.812895 Dram Type= 6, Freq= 0, CH_1, rank 1
1743 00:56:10.812942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1744 00:56:10.812989 ==
1745 00:56:10.813037 Write leveling (Byte 0): 26 => 26
1746 00:56:10.813084 Write leveling (Byte 1): 25 => 25
1747 00:56:10.813130 DramcWriteLeveling(PI) end<-----
1748 00:56:10.813177
1749 00:56:10.813223 ==
1750 00:56:10.813270 Dram Type= 6, Freq= 0, CH_1, rank 1
1751 00:56:10.813318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1752 00:56:10.813366 ==
1753 00:56:10.813413 [Gating] SW mode calibration
1754 00:56:10.813460 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1755 00:56:10.813509 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1756 00:56:10.813557 0 6 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
1757 00:56:10.813604 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1758 00:56:10.813651 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1759 00:56:10.813699 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1760 00:56:10.813747 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1761 00:56:10.813795 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1762 00:56:10.813842 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1763 00:56:10.813889 0 6 28 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
1764 00:56:10.813936 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1765 00:56:10.813984 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1766 00:56:10.814031 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1767 00:56:10.814078 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1768 00:56:10.814126 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1769 00:56:10.814174 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1770 00:56:10.814258 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1771 00:56:10.814352 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1772 00:56:10.814403 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1773 00:56:10.814451 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1774 00:56:10.814499 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1775 00:56:10.814547 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1776 00:56:10.814595 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1777 00:56:10.814642 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 00:56:10.814690 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1779 00:56:10.814738 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 00:56:10.814801 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 00:56:10.814849 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 00:56:10.814897 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 00:56:10.814944 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 00:56:10.814992 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 00:56:10.815040 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 00:56:10.815088 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 00:56:10.815136 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1788 00:56:10.815184 Total UI for P1: 0, mck2ui 16
1789 00:56:10.815232 best dqsien dly found for B0: ( 0, 9, 26)
1790 00:56:10.815279 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1791 00:56:10.815326 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1792 00:56:10.815373 Total UI for P1: 0, mck2ui 16
1793 00:56:10.815421 best dqsien dly found for B1: ( 0, 9, 30)
1794 00:56:10.815469 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1795 00:56:10.815517 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1796 00:56:10.815564
1797 00:56:10.815632 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1798 00:56:10.815684 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1799 00:56:10.815733 [Gating] SW calibration Done
1800 00:56:10.815780 ==
1801 00:56:10.815828 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 00:56:10.815876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1803 00:56:10.815924 ==
1804 00:56:10.815972 RX Vref Scan: 0
1805 00:56:10.816019
1806 00:56:10.816065 RX Vref 0 -> 0, step: 1
1807 00:56:10.816113
1808 00:56:10.816160 RX Delay -130 -> 252, step: 16
1809 00:56:10.816207 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1810 00:56:10.816254 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1811 00:56:10.816302 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1812 00:56:10.816349 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1813 00:56:10.816397 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1814 00:56:10.816444 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1815 00:56:10.816491 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1816 00:56:10.816538 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1817 00:56:10.816776 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1818 00:56:10.816829 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1819 00:56:10.816902 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1820 00:56:10.816955 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1821 00:56:10.817004 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1822 00:56:10.817052 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1823 00:56:10.817099 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1824 00:56:10.817146 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1825 00:56:10.817193 ==
1826 00:56:10.817241 Dram Type= 6, Freq= 0, CH_1, rank 1
1827 00:56:10.817289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1828 00:56:10.817337 ==
1829 00:56:10.817384 DQS Delay:
1830 00:56:10.817431 DQS0 = 0, DQS1 = 0
1831 00:56:10.817478 DQM Delay:
1832 00:56:10.817525 DQM0 = 84, DQM1 = 75
1833 00:56:10.817573 DQ Delay:
1834 00:56:10.817619 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1835 00:56:10.817666 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1836 00:56:10.817713 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1837 00:56:10.817761 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1838 00:56:10.817809
1839 00:56:10.817856
1840 00:56:10.817903 ==
1841 00:56:10.817950 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 00:56:10.817998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1843 00:56:10.818046 ==
1844 00:56:10.818093
1845 00:56:10.818139
1846 00:56:10.818185 TX Vref Scan disable
1847 00:56:10.818264 == TX Byte 0 ==
1848 00:56:10.818327 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1849 00:56:10.818375 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1850 00:56:10.818453 == TX Byte 1 ==
1851 00:56:10.818531 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1852 00:56:10.818607 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1853 00:56:10.818683 ==
1854 00:56:10.818748 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 00:56:10.818798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1856 00:56:10.818846 ==
1857 00:56:10.818894 TX Vref=22, minBit 13, minWin=27, winSum=449
1858 00:56:10.818942 TX Vref=24, minBit 1, minWin=28, winSum=453
1859 00:56:10.818990 TX Vref=26, minBit 1, minWin=28, winSum=458
1860 00:56:10.819037 TX Vref=28, minBit 6, minWin=28, winSum=459
1861 00:56:10.819084 TX Vref=30, minBit 0, minWin=28, winSum=458
1862 00:56:10.819131 TX Vref=32, minBit 0, minWin=28, winSum=456
1863 00:56:10.819179 [TxChooseVref] Worse bit 6, Min win 28, Win sum 459, Final Vref 28
1864 00:56:10.819228
1865 00:56:10.819274 Final TX Range 1 Vref 28
1866 00:56:10.819321
1867 00:56:10.819367 ==
1868 00:56:10.819414 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 00:56:10.819461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1870 00:56:10.819508 ==
1871 00:56:10.819555
1872 00:56:10.819602
1873 00:56:10.819649 TX Vref Scan disable
1874 00:56:10.819696 == TX Byte 0 ==
1875 00:56:10.819743 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1876 00:56:10.819790 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1877 00:56:10.819838 == TX Byte 1 ==
1878 00:56:10.819885 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1879 00:56:10.819933 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1880 00:56:10.819980
1881 00:56:10.820027 [DATLAT]
1882 00:56:10.820074 Freq=800, CH1 RK1
1883 00:56:10.820122
1884 00:56:10.820168 DATLAT Default: 0x9
1885 00:56:10.820216 0, 0xFFFF, sum = 0
1886 00:56:10.820270 1, 0xFFFF, sum = 0
1887 00:56:10.820341 2, 0xFFFF, sum = 0
1888 00:56:10.820391 3, 0xFFFF, sum = 0
1889 00:56:10.820439 4, 0xFFFF, sum = 0
1890 00:56:10.820487 5, 0xFFFF, sum = 0
1891 00:56:10.820536 6, 0xFFFF, sum = 0
1892 00:56:10.820584 7, 0xFFFF, sum = 0
1893 00:56:10.820633 8, 0x0, sum = 1
1894 00:56:10.820681 9, 0x0, sum = 2
1895 00:56:10.820729 10, 0x0, sum = 3
1896 00:56:10.820777 11, 0x0, sum = 4
1897 00:56:10.820825 best_step = 9
1898 00:56:10.820872
1899 00:56:10.820920 ==
1900 00:56:10.820968 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 00:56:10.821015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1902 00:56:10.821063 ==
1903 00:56:10.821111 RX Vref Scan: 0
1904 00:56:10.821158
1905 00:56:10.821205 RX Vref 0 -> 0, step: 1
1906 00:56:10.821252
1907 00:56:10.821299 RX Delay -111 -> 252, step: 8
1908 00:56:10.821346 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1909 00:56:10.821394 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1910 00:56:10.821441 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1911 00:56:10.821488 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1912 00:56:10.821535 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1913 00:56:10.821583 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1914 00:56:10.821630 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1915 00:56:10.821676 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1916 00:56:10.821723 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1917 00:56:10.821770 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1918 00:56:10.821817 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1919 00:56:10.821865 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1920 00:56:10.821912 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1921 00:56:10.821968 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1922 00:56:10.822027 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1923 00:56:10.822075 iDelay=217, Bit 15, Center 76 (-39 ~ 192) 232
1924 00:56:10.822122 ==
1925 00:56:10.822170 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 00:56:10.822224 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1927 00:56:10.822314 ==
1928 00:56:10.822361 DQS Delay:
1929 00:56:10.822408 DQS0 = 0, DQS1 = 0
1930 00:56:10.822456 DQM Delay:
1931 00:56:10.822503 DQM0 = 82, DQM1 = 72
1932 00:56:10.822550 DQ Delay:
1933 00:56:10.822597 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1934 00:56:10.822644 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1935 00:56:10.822691 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =68
1936 00:56:10.822739 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =76
1937 00:56:10.822787
1938 00:56:10.822833
1939 00:56:10.822880 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1940 00:56:10.822929 CH1 RK1: MR19=606, MR18=3E3E
1941 00:56:10.822977 CH1_RK1: MR19=0x606, MR18=0x3E3E, DQSOSC=394, MR23=63, INC=95, DEC=63
1942 00:56:10.823024 [RxdqsGatingPostProcess] freq 800
1943 00:56:10.823071 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1944 00:56:10.823119 Pre-setting of DQS Precalculation
1945 00:56:10.823166 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1946 00:56:10.823214 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1947 00:56:10.823262 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1948 00:56:10.823310
1949 00:56:10.823359
1950 00:56:10.823405 [Calibration Summary] 1600 Mbps
1951 00:56:10.823452 CH 0, Rank 0
1952 00:56:10.823499 SW Impedance : PASS
1953 00:56:10.823547 DUTY Scan : NO K
1954 00:56:10.823594 ZQ Calibration : PASS
1955 00:56:10.823642 Jitter Meter : NO K
1956 00:56:10.823878 CBT Training : PASS
1957 00:56:10.823934 Write leveling : PASS
1958 00:56:10.823983 RX DQS gating : PASS
1959 00:56:10.824031 RX DQ/DQS(RDDQC) : PASS
1960 00:56:10.824080 TX DQ/DQS : PASS
1961 00:56:10.824128 RX DATLAT : PASS
1962 00:56:10.824177 RX DQ/DQS(Engine): PASS
1963 00:56:10.824224 TX OE : NO K
1964 00:56:10.824271 All Pass.
1965 00:56:10.824318
1966 00:56:10.824365 CH 0, Rank 1
1967 00:56:10.824413 SW Impedance : PASS
1968 00:56:10.824459 DUTY Scan : NO K
1969 00:56:10.824507 ZQ Calibration : PASS
1970 00:56:10.824554 Jitter Meter : NO K
1971 00:56:10.824600 CBT Training : PASS
1972 00:56:10.824648 Write leveling : PASS
1973 00:56:10.824701 RX DQS gating : PASS
1974 00:56:10.824749 RX DQ/DQS(RDDQC) : PASS
1975 00:56:10.824796 TX DQ/DQS : PASS
1976 00:56:10.824844 RX DATLAT : PASS
1977 00:56:10.824892 RX DQ/DQS(Engine): PASS
1978 00:56:10.824939 TX OE : NO K
1979 00:56:10.824987 All Pass.
1980 00:56:10.825034
1981 00:56:10.825080 CH 1, Rank 0
1982 00:56:10.825127 SW Impedance : PASS
1983 00:56:10.825176 DUTY Scan : NO K
1984 00:56:10.825223 ZQ Calibration : PASS
1985 00:56:10.825269 Jitter Meter : NO K
1986 00:56:10.825316 CBT Training : PASS
1987 00:56:10.825368 Write leveling : PASS
1988 00:56:10.825433 RX DQS gating : PASS
1989 00:56:10.825481 RX DQ/DQS(RDDQC) : PASS
1990 00:56:10.825529 TX DQ/DQS : PASS
1991 00:56:10.825577 RX DATLAT : PASS
1992 00:56:10.825624 RX DQ/DQS(Engine): PASS
1993 00:56:10.825671 TX OE : NO K
1994 00:56:10.825719 All Pass.
1995 00:56:10.825765
1996 00:56:10.825811 CH 1, Rank 1
1997 00:56:10.825858 SW Impedance : PASS
1998 00:56:10.825904 DUTY Scan : NO K
1999 00:56:10.825957 ZQ Calibration : PASS
2000 00:56:10.826007 Jitter Meter : NO K
2001 00:56:10.826054 CBT Training : PASS
2002 00:56:10.826101 Write leveling : PASS
2003 00:56:10.826148 RX DQS gating : PASS
2004 00:56:11.084095 RX DQ/DQS(RDDQC) : PASS
2005 00:56:11.084556 TX DQ/DQS : PASS
2006 00:56:11.084886 RX DATLAT : PASS
2007 00:56:11.085193 RX DQ/DQS(Engine): PASS
2008 00:56:11.085488 TX OE : NO K
2009 00:56:11.085772 All Pass.
2010 00:56:11.086167
2011 00:56:11.086508 DramC Write-DBI off
2012 00:56:11.086792 PER_BANK_REFRESH: Hybrid Mode
2013 00:56:11.087071 TX_TRACKING: ON
2014 00:56:11.087347 [GetDramInforAfterCalByMRR] Vendor 6.
2015 00:56:11.087625 [GetDramInforAfterCalByMRR] Revision 606.
2016 00:56:11.087900 [GetDramInforAfterCalByMRR] Revision 2 0.
2017 00:56:11.088172 MR0 0x3939
2018 00:56:11.088443 MR8 0x1111
2019 00:56:11.088716 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2020 00:56:11.088994
2021 00:56:11.089259 MR0 0x3939
2022 00:56:11.089526 MR8 0x1111
2023 00:56:11.089795 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2024 00:56:11.090115
2025 00:56:11.090559 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2026 00:56:11.090979 [FAST_K] Save calibration result to emmc
2027 00:56:11.091275 [FAST_K] Save calibration result to emmc
2028 00:56:11.091551 dram_init: config_dvfs: 1
2029 00:56:11.091841 dramc_set_vcore_voltage set vcore to 662500
2030 00:56:11.092122 Read voltage for 1200, 2
2031 00:56:11.092397 Vio18 = 0
2032 00:56:11.092681 Vcore = 662500
2033 00:56:11.092955 Vdram = 0
2034 00:56:11.093229 Vddq = 0
2035 00:56:11.093500 Vmddr = 0
2036 00:56:11.093769 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2037 00:56:11.094040 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2038 00:56:11.094342 MEM_TYPE=3, freq_sel=15
2039 00:56:11.094623 sv_algorithm_assistance_LP4_1600
2040 00:56:11.094897 ============ PULL DRAM RESETB DOWN ============
2041 00:56:11.095176 ========== PULL DRAM RESETB DOWN end =========
2042 00:56:11.095449 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2043 00:56:11.095720 ===================================
2044 00:56:11.095994 LPDDR4 DRAM CONFIGURATION
2045 00:56:11.096278 ===================================
2046 00:56:11.096551 EX_ROW_EN[0] = 0x0
2047 00:56:11.096821 EX_ROW_EN[1] = 0x0
2048 00:56:11.097091 LP4Y_EN = 0x0
2049 00:56:11.097358 WORK_FSP = 0x0
2050 00:56:11.097626 WL = 0x4
2051 00:56:11.097894 RL = 0x4
2052 00:56:11.098160 BL = 0x2
2053 00:56:11.098463 RPST = 0x0
2054 00:56:11.098705 RD_PRE = 0x0
2055 00:56:11.098949 WR_PRE = 0x1
2056 00:56:11.099192 WR_PST = 0x0
2057 00:56:11.099431 DBI_WR = 0x0
2058 00:56:11.099674 DBI_RD = 0x0
2059 00:56:11.099915 OTF = 0x1
2060 00:56:11.100163 ===================================
2061 00:56:11.100411 ===================================
2062 00:56:11.100654 ANA top config
2063 00:56:11.100900 ===================================
2064 00:56:11.101145 DLL_ASYNC_EN = 0
2065 00:56:11.101387 ALL_SLAVE_EN = 0
2066 00:56:11.101627 NEW_RANK_MODE = 1
2067 00:56:11.101873 DLL_IDLE_MODE = 1
2068 00:56:11.102116 LP45_APHY_COMB_EN = 1
2069 00:56:11.102382 TX_ODT_DIS = 1
2070 00:56:11.102631 NEW_8X_MODE = 1
2071 00:56:11.102877 ===================================
2072 00:56:11.103218 ===================================
2073 00:56:11.103504 data_rate = 2400
2074 00:56:11.103791 CKR = 1
2075 00:56:11.104040 DQ_P2S_RATIO = 8
2076 00:56:11.104286 ===================================
2077 00:56:11.104532 CA_P2S_RATIO = 8
2078 00:56:11.104778 DQ_CA_OPEN = 0
2079 00:56:11.105021 DQ_SEMI_OPEN = 0
2080 00:56:11.105263 CA_SEMI_OPEN = 0
2081 00:56:11.105507 CA_FULL_RATE = 0
2082 00:56:11.105750 DQ_CKDIV4_EN = 0
2083 00:56:11.105994 CA_CKDIV4_EN = 0
2084 00:56:11.106257 CA_PREDIV_EN = 0
2085 00:56:11.106615 PH8_DLY = 17
2086 00:56:11.106909 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2087 00:56:11.107160 DQ_AAMCK_DIV = 4
2088 00:56:11.107409 CA_AAMCK_DIV = 4
2089 00:56:11.107658 CA_ADMCK_DIV = 4
2090 00:56:11.107905 DQ_TRACK_CA_EN = 0
2091 00:56:11.108151 CA_PICK = 1200
2092 00:56:11.108397 CA_MCKIO = 1200
2093 00:56:11.108595 MCKIO_SEMI = 0
2094 00:56:11.108772 PLL_FREQ = 2366
2095 00:56:11.108962 DQ_UI_PI_RATIO = 32
2096 00:56:11.109141 CA_UI_PI_RATIO = 0
2097 00:56:11.109317 ===================================
2098 00:56:11.109494 ===================================
2099 00:56:11.109670 memory_type:LPDDR4
2100 00:56:11.109846 GP_NUM : 10
2101 00:56:11.110018 SRAM_EN : 1
2102 00:56:11.110191 MD32_EN : 0
2103 00:56:11.110453 ===================================
2104 00:56:11.110729 [ANA_INIT] >>>>>>>>>>>>>>
2105 00:56:11.110982 <<<<<< [CONFIGURE PHASE]: ANA_TX
2106 00:56:11.111483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2107 00:56:11.111692 ===================================
2108 00:56:11.111880 data_rate = 2400,PCW = 0X5b00
2109 00:56:11.112061 ===================================
2110 00:56:11.112240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2111 00:56:11.112441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2112 00:56:11.112632 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2113 00:56:11.112813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2114 00:56:11.112995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2115 00:56:11.113172 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2116 00:56:11.113349 [ANA_INIT] flow start
2117 00:56:11.113502 [ANA_INIT] PLL >>>>>>>>
2118 00:56:11.113712 [ANA_INIT] PLL <<<<<<<<
2119 00:56:11.113916 [ANA_INIT] MIDPI >>>>>>>>
2120 00:56:11.114103 [ANA_INIT] MIDPI <<<<<<<<
2121 00:56:11.114266 [ANA_INIT] DLL >>>>>>>>
2122 00:56:11.114406 [ANA_INIT] DLL <<<<<<<<
2123 00:56:11.114588 [ANA_INIT] flow end
2124 00:56:11.114808 ============ LP4 DIFF to SE enter ============
2125 00:56:11.114963 ============ LP4 DIFF to SE exit ============
2126 00:56:11.115101 [ANA_INIT] <<<<<<<<<<<<<
2127 00:56:11.115235 [Flow] Enable top DCM control >>>>>
2128 00:56:11.115369 [Flow] Enable top DCM control <<<<<
2129 00:56:11.115505 Enable DLL master slave shuffle
2130 00:56:11.115641 ==============================================================
2131 00:56:11.115778 Gating Mode config
2132 00:56:11.115912 ==============================================================
2133 00:56:11.116046 Config description:
2134 00:56:11.116179 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2135 00:56:11.116317 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2136 00:56:11.116452 SELPH_MODE 0: By rank 1: By Phase
2137 00:56:11.116588 ==============================================================
2138 00:56:11.116724 GAT_TRACK_EN = 1
2139 00:56:11.116858 RX_GATING_MODE = 2
2140 00:56:11.116991 RX_GATING_TRACK_MODE = 2
2141 00:56:11.117125 SELPH_MODE = 1
2142 00:56:11.117316 PICG_EARLY_EN = 1
2143 00:56:11.117539 VALID_LAT_VALUE = 1
2144 00:56:11.117732 ==============================================================
2145 00:56:11.117875 Enter into Gating configuration >>>>
2146 00:56:11.118011 Exit from Gating configuration <<<<
2147 00:56:11.118147 Enter into DVFS_PRE_config >>>>>
2148 00:56:11.118301 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2149 00:56:11.118451 Exit from DVFS_PRE_config <<<<<
2150 00:56:11.118559 Enter into PICG configuration >>>>
2151 00:56:11.118668 Exit from PICG configuration <<<<
2152 00:56:11.118775 [RX_INPUT] configuration >>>>>
2153 00:56:11.118881 [RX_INPUT] configuration <<<<<
2154 00:56:11.118986 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2155 00:56:11.119095 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2156 00:56:11.119203 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2157 00:56:11.119311 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2158 00:56:11.119419 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2159 00:56:11.119527 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2160 00:56:11.119635 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2161 00:56:11.119741 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2162 00:56:11.119847 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2163 00:56:11.119952 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2164 00:56:11.120059 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2165 00:56:11.120167 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2166 00:56:11.120290 ===================================
2167 00:56:11.120473 LPDDR4 DRAM CONFIGURATION
2168 00:56:11.120662 ===================================
2169 00:56:11.120831 EX_ROW_EN[0] = 0x0
2170 00:56:11.120959 EX_ROW_EN[1] = 0x0
2171 00:56:11.121068 LP4Y_EN = 0x0
2172 00:56:11.121175 WORK_FSP = 0x0
2173 00:56:11.121281 WL = 0x4
2174 00:56:11.121388 RL = 0x4
2175 00:56:11.121494 BL = 0x2
2176 00:56:11.121601 RPST = 0x0
2177 00:56:11.121706 RD_PRE = 0x0
2178 00:56:11.121812 WR_PRE = 0x1
2179 00:56:11.121920 WR_PST = 0x0
2180 00:56:11.122027 DBI_WR = 0x0
2181 00:56:11.122134 DBI_RD = 0x0
2182 00:56:11.122254 OTF = 0x1
2183 00:56:11.122365 ===================================
2184 00:56:11.122472 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2185 00:56:11.122580 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2186 00:56:11.122687 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 00:56:11.122796 ===================================
2188 00:56:11.122903 LPDDR4 DRAM CONFIGURATION
2189 00:56:11.123009 ===================================
2190 00:56:11.123116 EX_ROW_EN[0] = 0x10
2191 00:56:11.123222 EX_ROW_EN[1] = 0x0
2192 00:56:11.123328 LP4Y_EN = 0x0
2193 00:56:11.123440 WORK_FSP = 0x0
2194 00:56:11.123587 WL = 0x4
2195 00:56:11.123730 RL = 0x4
2196 00:56:11.123865 BL = 0x2
2197 00:56:11.123960 RPST = 0x0
2198 00:56:11.124051 RD_PRE = 0x0
2199 00:56:11.124140 WR_PRE = 0x1
2200 00:56:11.124229 WR_PST = 0x0
2201 00:56:11.124319 DBI_WR = 0x0
2202 00:56:11.124408 DBI_RD = 0x0
2203 00:56:11.124496 OTF = 0x1
2204 00:56:11.124585 ===================================
2205 00:56:11.124675 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2206 00:56:11.124765 ==
2207 00:56:11.124855 Dram Type= 6, Freq= 0, CH_0, rank 0
2208 00:56:11.124945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2209 00:56:11.125036 ==
2210 00:56:11.125124 [Duty_Offset_Calibration]
2211 00:56:11.125214 B0:0 B1:2 CA:1
2212 00:56:11.125303
2213 00:56:11.125393 [DutyScan_Calibration_Flow] k_type=0
2214 00:56:11.125482
2215 00:56:11.125570 ==CLK 0==
2216 00:56:11.125660 Final CLK duty delay cell = 0
2217 00:56:11.125750 [0] MAX Duty = 5093%(X100), DQS PI = 12
2218 00:56:11.126066 [0] MIN Duty = 4938%(X100), DQS PI = 52
2219 00:56:11.126168 [0] AVG Duty = 5015%(X100)
2220 00:56:11.126332
2221 00:56:11.126481 CH0 CLK Duty spec in!! Max-Min= 155%
2222 00:56:11.126624 [DutyScan_Calibration_Flow] ====Done====
2223 00:56:11.126775
2224 00:56:11.126922 [DutyScan_Calibration_Flow] k_type=1
2225 00:56:11.127077
2226 00:56:11.127215 ==DQS 0 ==
2227 00:56:11.127373 Final DQS duty delay cell = 0
2228 00:56:11.127521 [0] MAX Duty = 5125%(X100), DQS PI = 32
2229 00:56:11.127666 [0] MIN Duty = 5000%(X100), DQS PI = 6
2230 00:56:11.127808 [0] AVG Duty = 5062%(X100)
2231 00:56:11.127949
2232 00:56:11.128091 ==DQS 1 ==
2233 00:56:11.128192 Final DQS duty delay cell = 0
2234 00:56:11.128283 [0] MAX Duty = 5031%(X100), DQS PI = 52
2235 00:56:11.128385 [0] MIN Duty = 4875%(X100), DQS PI = 20
2236 00:56:11.128463 [0] AVG Duty = 4953%(X100)
2237 00:56:11.128539
2238 00:56:11.128615 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2239 00:56:11.128692
2240 00:56:11.128769 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2241 00:56:11.128846 [DutyScan_Calibration_Flow] ====Done====
2242 00:56:11.128923
2243 00:56:11.128999 [DutyScan_Calibration_Flow] k_type=3
2244 00:56:11.129075
2245 00:56:11.129151 ==DQM 0 ==
2246 00:56:11.129227 Final DQM duty delay cell = 0
2247 00:56:11.129305 [0] MAX Duty = 5156%(X100), DQS PI = 22
2248 00:56:11.129380 [0] MIN Duty = 4969%(X100), DQS PI = 40
2249 00:56:11.129457 [0] AVG Duty = 5062%(X100)
2250 00:56:11.129533
2251 00:56:11.129609 ==DQM 1 ==
2252 00:56:11.129686 Final DQM duty delay cell = 4
2253 00:56:11.129763 [4] MAX Duty = 5187%(X100), DQS PI = 54
2254 00:56:11.129840 [4] MIN Duty = 5000%(X100), DQS PI = 18
2255 00:56:11.129916 [4] AVG Duty = 5093%(X100)
2256 00:56:11.129992
2257 00:56:11.130068 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2258 00:56:11.130144
2259 00:56:11.130226 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2260 00:56:11.130309 [DutyScan_Calibration_Flow] ====Done====
2261 00:56:11.130440
2262 00:56:11.130561 [DutyScan_Calibration_Flow] k_type=2
2263 00:56:11.130678
2264 00:56:11.130759 ==DQ 0 ==
2265 00:56:11.130840 Final DQ duty delay cell = -4
2266 00:56:11.130918 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2267 00:56:11.130997 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2268 00:56:11.131074 [-4] AVG Duty = 4937%(X100)
2269 00:56:11.131151
2270 00:56:11.131227 ==DQ 1 ==
2271 00:56:11.131304 Final DQ duty delay cell = -4
2272 00:56:11.131381 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2273 00:56:11.131458 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2274 00:56:11.131536 [-4] AVG Duty = 4969%(X100)
2275 00:56:11.131612
2276 00:56:11.131688 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2277 00:56:11.131765
2278 00:56:11.131841 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2279 00:56:11.131918 [DutyScan_Calibration_Flow] ====Done====
2280 00:56:11.131993 ==
2281 00:56:11.132069 Dram Type= 6, Freq= 0, CH_1, rank 0
2282 00:56:11.132146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2283 00:56:11.132224 ==
2284 00:56:11.132301 [Duty_Offset_Calibration]
2285 00:56:11.132377 B0:0 B1:5 CA:-5
2286 00:56:11.132453
2287 00:56:11.132528 [DutyScan_Calibration_Flow] k_type=0
2288 00:56:11.132604
2289 00:56:11.132680 ==CLK 0==
2290 00:56:11.132755 Final CLK duty delay cell = 0
2291 00:56:11.132832 [0] MAX Duty = 5094%(X100), DQS PI = 24
2292 00:56:11.132909 [0] MIN Duty = 4907%(X100), DQS PI = 44
2293 00:56:11.132986 [0] AVG Duty = 5000%(X100)
2294 00:56:11.133062
2295 00:56:11.133138 CH1 CLK Duty spec in!! Max-Min= 187%
2296 00:56:11.133213 [DutyScan_Calibration_Flow] ====Done====
2297 00:56:11.133290
2298 00:56:11.133366 [DutyScan_Calibration_Flow] k_type=1
2299 00:56:11.133449
2300 00:56:11.133514 ==DQS 0 ==
2301 00:56:11.133581 Final DQS duty delay cell = 0
2302 00:56:11.133648 [0] MAX Duty = 5125%(X100), DQS PI = 16
2303 00:56:11.133715 [0] MIN Duty = 4875%(X100), DQS PI = 40
2304 00:56:11.133783 [0] AVG Duty = 5000%(X100)
2305 00:56:11.133860
2306 00:56:11.133973 ==DQS 1 ==
2307 00:56:11.134091 Final DQS duty delay cell = -4
2308 00:56:11.134200 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2309 00:56:11.134312 [-4] MIN Duty = 4876%(X100), DQS PI = 58
2310 00:56:11.134385 [-4] AVG Duty = 4938%(X100)
2311 00:56:11.134454
2312 00:56:11.134523 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2313 00:56:11.134592
2314 00:56:11.134660 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2315 00:56:11.134728 [DutyScan_Calibration_Flow] ====Done====
2316 00:56:11.134796
2317 00:56:11.134862 [DutyScan_Calibration_Flow] k_type=3
2318 00:56:11.134929
2319 00:56:11.134996 ==DQM 0 ==
2320 00:56:11.135063 Final DQM duty delay cell = -4
2321 00:56:11.135130 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2322 00:56:11.135198 [-4] MIN Duty = 4844%(X100), DQS PI = 42
2323 00:56:11.135266 [-4] AVG Duty = 4968%(X100)
2324 00:56:11.135333
2325 00:56:11.135400 ==DQM 1 ==
2326 00:56:11.135467 Final DQM duty delay cell = -4
2327 00:56:11.135534 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2328 00:56:11.135602 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2329 00:56:11.135668 [-4] AVG Duty = 4968%(X100)
2330 00:56:11.135733
2331 00:56:11.135800 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2332 00:56:11.135867
2333 00:56:11.135934 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2334 00:56:11.136001 [DutyScan_Calibration_Flow] ====Done====
2335 00:56:11.136068
2336 00:56:11.136134 [DutyScan_Calibration_Flow] k_type=2
2337 00:56:11.136200
2338 00:56:11.136267 ==DQ 0 ==
2339 00:56:11.136334 Final DQ duty delay cell = 0
2340 00:56:11.136402 [0] MAX Duty = 5062%(X100), DQS PI = 0
2341 00:56:11.136469 [0] MIN Duty = 4938%(X100), DQS PI = 44
2342 00:56:11.136535 [0] AVG Duty = 5000%(X100)
2343 00:56:11.136601
2344 00:56:11.136668 ==DQ 1 ==
2345 00:56:11.136735 Final DQ duty delay cell = 0
2346 00:56:11.136802 [0] MAX Duty = 5031%(X100), DQS PI = 8
2347 00:56:11.136870 [0] MIN Duty = 4907%(X100), DQS PI = 0
2348 00:56:11.136937 [0] AVG Duty = 4969%(X100)
2349 00:56:11.137005
2350 00:56:11.137071 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2351 00:56:11.137137
2352 00:56:11.137203 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2353 00:56:11.137274 [DutyScan_Calibration_Flow] ====Done====
2354 00:56:11.137390 nWR fixed to 30
2355 00:56:11.137501 [ModeRegInit_LP4] CH0 RK0
2356 00:56:11.137606 [ModeRegInit_LP4] CH0 RK1
2357 00:56:11.137679 [ModeRegInit_LP4] CH1 RK0
2358 00:56:11.137749 [ModeRegInit_LP4] CH1 RK1
2359 00:56:11.137817 match AC timing 6
2360 00:56:11.137884 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2361 00:56:11.137952 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2362 00:56:11.138019 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2363 00:56:11.138087 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2364 00:56:11.138154 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2365 00:56:11.138230 ==
2366 00:56:11.138299 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 00:56:11.138367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2368 00:56:11.138441 ==
2369 00:56:11.138499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2370 00:56:11.138558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2371 00:56:11.138617 [CA 0] Center 39 (9~70) winsize 62
2372 00:56:11.138676 [CA 1] Center 39 (8~70) winsize 63
2373 00:56:11.138936 [CA 2] Center 36 (5~67) winsize 63
2374 00:56:11.139027 [CA 3] Center 35 (4~66) winsize 63
2375 00:56:11.139094 [CA 4] Center 34 (3~65) winsize 63
2376 00:56:11.139154 [CA 5] Center 34 (3~65) winsize 63
2377 00:56:11.139214
2378 00:56:11.139273 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2379 00:56:11.139333
2380 00:56:11.139392 [CATrainingPosCal] consider 1 rank data
2381 00:56:11.139452 u2DelayCellTimex100 = 270/100 ps
2382 00:56:11.139511 CA0 delay=39 (9~70),Diff = 5 PI (24 cell)
2383 00:56:11.139571 CA1 delay=39 (8~70),Diff = 5 PI (24 cell)
2384 00:56:11.139631 CA2 delay=36 (5~67),Diff = 2 PI (9 cell)
2385 00:56:11.139690 CA3 delay=35 (4~66),Diff = 1 PI (4 cell)
2386 00:56:11.139749 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
2387 00:56:11.139807 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
2388 00:56:11.139867
2389 00:56:11.139926 CA PerBit enable=1, Macro0, CA PI delay=34
2390 00:56:11.139985
2391 00:56:11.140044 [CBTSetCACLKResult] CA Dly = 34
2392 00:56:11.140103 CS Dly: 7 (0~38)
2393 00:56:11.140162 ==
2394 00:56:11.140220 Dram Type= 6, Freq= 0, CH_0, rank 1
2395 00:56:11.140279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2396 00:56:11.140339 ==
2397 00:56:11.140414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2398 00:56:11.140513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2399 00:56:11.140610 [CA 0] Center 39 (9~69) winsize 61
2400 00:56:11.140704 [CA 1] Center 38 (8~69) winsize 62
2401 00:56:11.140768 [CA 2] Center 35 (5~66) winsize 62
2402 00:56:11.140828 [CA 3] Center 35 (4~66) winsize 63
2403 00:56:11.140889 [CA 4] Center 33 (3~64) winsize 62
2404 00:56:11.140948 [CA 5] Center 33 (3~64) winsize 62
2405 00:56:11.141007
2406 00:56:11.141065 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2407 00:56:11.141125
2408 00:56:11.141184 [CATrainingPosCal] consider 2 rank data
2409 00:56:11.141244 u2DelayCellTimex100 = 270/100 ps
2410 00:56:11.141303 CA0 delay=39 (9~69),Diff = 6 PI (28 cell)
2411 00:56:11.141364 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2412 00:56:11.141423 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2413 00:56:11.141482 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2414 00:56:11.141540 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2415 00:56:11.141598 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2416 00:56:11.141656
2417 00:56:11.141716 CA PerBit enable=1, Macro0, CA PI delay=33
2418 00:56:11.141775
2419 00:56:11.141834 [CBTSetCACLKResult] CA Dly = 33
2420 00:56:11.141893 CS Dly: 7 (0~39)
2421 00:56:11.141951
2422 00:56:11.142010 ----->DramcWriteLeveling(PI) begin...
2423 00:56:11.142071 ==
2424 00:56:11.142131 Dram Type= 6, Freq= 0, CH_0, rank 0
2425 00:56:11.142195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2426 00:56:11.142286 ==
2427 00:56:11.142348 Write leveling (Byte 0): 27 => 27
2428 00:56:11.142408 Write leveling (Byte 1): 26 => 26
2429 00:56:11.142467 DramcWriteLeveling(PI) end<-----
2430 00:56:11.142526
2431 00:56:11.142586 ==
2432 00:56:11.142645 Dram Type= 6, Freq= 0, CH_0, rank 0
2433 00:56:11.142704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2434 00:56:11.142763 ==
2435 00:56:11.142822 [Gating] SW mode calibration
2436 00:56:11.142881 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2437 00:56:11.142942 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2438 00:56:11.143001 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2439 00:56:11.143062 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2440 00:56:11.143123 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2441 00:56:11.143183 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2442 00:56:11.143242 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2443 00:56:11.143301 0 11 20 | B1->B0 | 2e2e 2828 | 1 0 | (1 0) (0 1)
2444 00:56:11.143360 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2445 00:56:11.143433 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2446 00:56:11.143486 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2447 00:56:11.143539 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2448 00:56:11.143593 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2449 00:56:11.143646 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2450 00:56:11.143699 0 12 16 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
2451 00:56:11.143752 0 12 20 | B1->B0 | 3e3e 4545 | 1 0 | (0 0) (0 0)
2452 00:56:11.143806 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2453 00:56:11.143867 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2454 00:56:11.143928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2455 00:56:11.143987 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2456 00:56:11.144074 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2457 00:56:11.144166 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2458 00:56:11.144260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2459 00:56:11.144346 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2460 00:56:11.144438 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2461 00:56:11.144527 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2462 00:56:11.144615 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2463 00:56:11.144701 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2464 00:56:11.144789 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 00:56:11.144876 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 00:56:11.144962 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 00:56:11.145047 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 00:56:11.145133 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 00:56:11.145218 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 00:56:11.145304 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 00:56:11.145390 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 00:56:11.145476 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 00:56:11.145563 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 00:56:11.145649 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 00:56:11.145734 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2476 00:56:11.145819 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2477 00:56:11.145904 Total UI for P1: 0, mck2ui 16
2478 00:56:11.146190 best dqsien dly found for B0: ( 0, 15, 20)
2479 00:56:11.146269 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2480 00:56:11.146326 Total UI for P1: 0, mck2ui 16
2481 00:56:11.146381 best dqsien dly found for B1: ( 0, 15, 22)
2482 00:56:11.146435 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2483 00:56:11.146490 best DQS1 dly(MCK, UI, PI) = (0, 15, 22)
2484 00:56:11.146544
2485 00:56:11.146629 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2486 00:56:11.146716 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 22)
2487 00:56:11.146800 [Gating] SW calibration Done
2488 00:56:11.146890 ==
2489 00:56:11.146977 Dram Type= 6, Freq= 0, CH_0, rank 0
2490 00:56:11.147063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2491 00:56:11.147149 ==
2492 00:56:11.147234 RX Vref Scan: 0
2493 00:56:11.147318
2494 00:56:11.147402 RX Vref 0 -> 0, step: 1
2495 00:56:11.147485
2496 00:56:11.147569 RX Delay -40 -> 252, step: 8
2497 00:56:11.147654 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2498 00:56:11.147739 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2499 00:56:11.147824 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2500 00:56:11.147910 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2501 00:56:11.147974 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2502 00:56:11.148028 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2503 00:56:11.148100 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2504 00:56:11.148176 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2505 00:56:11.148258 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2506 00:56:11.148314 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2507 00:56:11.148367 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2508 00:56:11.148432 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2509 00:56:11.148481 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2510 00:56:11.148531 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2511 00:56:11.148580 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2512 00:56:11.148628 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2513 00:56:11.148676 ==
2514 00:56:11.148724 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 00:56:11.148774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2516 00:56:11.148823 ==
2517 00:56:11.148871 DQS Delay:
2518 00:56:11.148920 DQS0 = 0, DQS1 = 0
2519 00:56:11.148968 DQM Delay:
2520 00:56:11.149016 DQM0 = 115, DQM1 = 105
2521 00:56:11.149065 DQ Delay:
2522 00:56:11.149113 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2523 00:56:11.149162 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2524 00:56:11.149211 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2525 00:56:11.149260 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2526 00:56:11.149308
2527 00:56:11.149355
2528 00:56:11.149403 ==
2529 00:56:11.149451 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 00:56:11.149500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2531 00:56:11.149549 ==
2532 00:56:11.149598
2533 00:56:11.149645
2534 00:56:11.149693 TX Vref Scan disable
2535 00:56:11.149741 == TX Byte 0 ==
2536 00:56:11.149789 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2537 00:56:11.149838 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2538 00:56:11.149886 == TX Byte 1 ==
2539 00:56:11.149934 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2540 00:56:11.149982 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2541 00:56:11.150030 ==
2542 00:56:11.150079 Dram Type= 6, Freq= 0, CH_0, rank 0
2543 00:56:11.150128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2544 00:56:11.150176 ==
2545 00:56:11.150228 TX Vref=22, minBit 8, minWin=25, winSum=414
2546 00:56:11.150279 TX Vref=24, minBit 10, minWin=25, winSum=423
2547 00:56:11.150327 TX Vref=26, minBit 15, minWin=25, winSum=426
2548 00:56:11.150375 TX Vref=28, minBit 10, minWin=25, winSum=432
2549 00:56:11.150424 TX Vref=30, minBit 5, minWin=26, winSum=432
2550 00:56:11.150473 TX Vref=32, minBit 8, minWin=26, winSum=431
2551 00:56:11.150523 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 30
2552 00:56:11.150572
2553 00:56:11.150620 Final TX Range 1 Vref 30
2554 00:56:11.150695
2555 00:56:11.150776 ==
2556 00:56:11.150856 Dram Type= 6, Freq= 0, CH_0, rank 0
2557 00:56:11.150937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2558 00:56:11.151014 ==
2559 00:56:11.151069
2560 00:56:11.151118
2561 00:56:11.151167 TX Vref Scan disable
2562 00:56:11.151216 == TX Byte 0 ==
2563 00:56:11.151264 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2564 00:56:11.151314 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2565 00:56:11.151363 == TX Byte 1 ==
2566 00:56:11.151411 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2567 00:56:11.151460 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2568 00:56:11.151508
2569 00:56:11.151556 [DATLAT]
2570 00:56:11.151604 Freq=1200, CH0 RK0
2571 00:56:11.151653
2572 00:56:11.151701 DATLAT Default: 0xd
2573 00:56:11.151750 0, 0xFFFF, sum = 0
2574 00:56:11.151800 1, 0xFFFF, sum = 0
2575 00:56:11.151849 2, 0xFFFF, sum = 0
2576 00:56:11.151898 3, 0xFFFF, sum = 0
2577 00:56:11.151948 4, 0xFFFF, sum = 0
2578 00:56:11.151998 5, 0xFFFF, sum = 0
2579 00:56:11.152046 6, 0xFFFF, sum = 0
2580 00:56:11.152095 7, 0xFFFF, sum = 0
2581 00:56:11.152144 8, 0xFFFF, sum = 0
2582 00:56:11.152193 9, 0xFFFF, sum = 0
2583 00:56:11.152241 10, 0xFFFF, sum = 0
2584 00:56:11.152290 11, 0x0, sum = 1
2585 00:56:11.152339 12, 0x0, sum = 2
2586 00:56:11.152388 13, 0x0, sum = 3
2587 00:56:11.152437 14, 0x0, sum = 4
2588 00:56:11.152486 best_step = 12
2589 00:56:11.152534
2590 00:56:11.152582 ==
2591 00:56:11.152629 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 00:56:11.152677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2593 00:56:11.152727 ==
2594 00:56:11.152775 RX Vref Scan: 1
2595 00:56:11.152825
2596 00:56:11.152874 Set Vref Range= 32 -> 127
2597 00:56:11.152921
2598 00:56:11.152969 RX Vref 32 -> 127, step: 1
2599 00:56:11.153017
2600 00:56:11.153065 RX Delay -21 -> 252, step: 4
2601 00:56:11.153114
2602 00:56:11.153161 Set Vref, RX VrefLevel [Byte0]: 32
2603 00:56:11.153210 [Byte1]: 32
2604 00:56:11.153258
2605 00:56:11.153305 Set Vref, RX VrefLevel [Byte0]: 33
2606 00:56:11.153354 [Byte1]: 33
2607 00:56:11.153415
2608 00:56:11.153462 Set Vref, RX VrefLevel [Byte0]: 34
2609 00:56:11.153530 [Byte1]: 34
2610 00:56:11.153609
2611 00:56:11.153687 Set Vref, RX VrefLevel [Byte0]: 35
2612 00:56:11.153766 [Byte1]: 35
2613 00:56:11.153840
2614 00:56:11.153898 Set Vref, RX VrefLevel [Byte0]: 36
2615 00:56:11.153947 [Byte1]: 36
2616 00:56:11.153995
2617 00:56:11.154042 Set Vref, RX VrefLevel [Byte0]: 37
2618 00:56:11.154089 [Byte1]: 37
2619 00:56:11.154136
2620 00:56:11.154183 Set Vref, RX VrefLevel [Byte0]: 38
2621 00:56:11.154262 [Byte1]: 38
2622 00:56:11.154324
2623 00:56:11.154371 Set Vref, RX VrefLevel [Byte0]: 39
2624 00:56:11.154418 [Byte1]: 39
2625 00:56:11.154465
2626 00:56:11.154512 Set Vref, RX VrefLevel [Byte0]: 40
2627 00:56:11.154560 [Byte1]: 40
2628 00:56:11.154607
2629 00:56:11.154654 Set Vref, RX VrefLevel [Byte0]: 41
2630 00:56:11.154701 [Byte1]: 41
2631 00:56:11.154748
2632 00:56:11.154983 Set Vref, RX VrefLevel [Byte0]: 42
2633 00:56:11.155037 [Byte1]: 42
2634 00:56:11.155086
2635 00:56:11.155133 Set Vref, RX VrefLevel [Byte0]: 43
2636 00:56:11.155182 [Byte1]: 43
2637 00:56:11.155229
2638 00:56:11.155277 Set Vref, RX VrefLevel [Byte0]: 44
2639 00:56:11.155325 [Byte1]: 44
2640 00:56:11.155372
2641 00:56:11.155419 Set Vref, RX VrefLevel [Byte0]: 45
2642 00:56:11.155466 [Byte1]: 45
2643 00:56:11.155514
2644 00:56:11.155561 Set Vref, RX VrefLevel [Byte0]: 46
2645 00:56:11.155609 [Byte1]: 46
2646 00:56:11.155656
2647 00:56:11.155702 Set Vref, RX VrefLevel [Byte0]: 47
2648 00:56:11.155751 [Byte1]: 47
2649 00:56:11.155798
2650 00:56:11.155845 Set Vref, RX VrefLevel [Byte0]: 48
2651 00:56:11.155892 [Byte1]: 48
2652 00:56:11.155940
2653 00:56:11.155986 Set Vref, RX VrefLevel [Byte0]: 49
2654 00:56:11.156034 [Byte1]: 49
2655 00:56:11.156081
2656 00:56:11.156127 Set Vref, RX VrefLevel [Byte0]: 50
2657 00:56:11.156174 [Byte1]: 50
2658 00:56:11.156221
2659 00:56:11.156267 Set Vref, RX VrefLevel [Byte0]: 51
2660 00:56:11.156314 [Byte1]: 51
2661 00:56:11.156361
2662 00:56:11.156408 Set Vref, RX VrefLevel [Byte0]: 52
2663 00:56:11.156459 [Byte1]: 52
2664 00:56:11.156507
2665 00:56:11.156554 Set Vref, RX VrefLevel [Byte0]: 53
2666 00:56:11.156601 [Byte1]: 53
2667 00:56:11.156657
2668 00:56:11.156706 Set Vref, RX VrefLevel [Byte0]: 54
2669 00:56:11.156755 [Byte1]: 54
2670 00:56:11.156802
2671 00:56:11.156871 Set Vref, RX VrefLevel [Byte0]: 55
2672 00:56:11.156950 [Byte1]: 55
2673 00:56:11.157028
2674 00:56:11.157101 Set Vref, RX VrefLevel [Byte0]: 56
2675 00:56:11.157162 [Byte1]: 56
2676 00:56:11.157216
2677 00:56:11.157265 Set Vref, RX VrefLevel [Byte0]: 57
2678 00:56:11.157314 [Byte1]: 57
2679 00:56:11.157361
2680 00:56:11.157411 Set Vref, RX VrefLevel [Byte0]: 58
2681 00:56:11.157460 [Byte1]: 58
2682 00:56:11.157508
2683 00:56:11.157556 Set Vref, RX VrefLevel [Byte0]: 59
2684 00:56:11.157604 [Byte1]: 59
2685 00:56:11.157652
2686 00:56:11.157699 Set Vref, RX VrefLevel [Byte0]: 60
2687 00:56:11.157746 [Byte1]: 60
2688 00:56:11.157794
2689 00:56:11.157840 Set Vref, RX VrefLevel [Byte0]: 61
2690 00:56:11.157887 [Byte1]: 61
2691 00:56:11.157934
2692 00:56:11.157982 Set Vref, RX VrefLevel [Byte0]: 62
2693 00:56:11.158029 [Byte1]: 62
2694 00:56:11.158076
2695 00:56:11.158123 Set Vref, RX VrefLevel [Byte0]: 63
2696 00:56:11.158171 [Byte1]: 63
2697 00:56:11.158225
2698 00:56:11.158314 Set Vref, RX VrefLevel [Byte0]: 64
2699 00:56:11.158362 [Byte1]: 64
2700 00:56:11.158409
2701 00:56:11.158456 Set Vref, RX VrefLevel [Byte0]: 65
2702 00:56:11.158503 [Byte1]: 65
2703 00:56:11.158551
2704 00:56:11.158599 Set Vref, RX VrefLevel [Byte0]: 66
2705 00:56:11.158646 [Byte1]: 66
2706 00:56:11.158694
2707 00:56:11.158740 Final RX Vref Byte 0 = 46 to rank0
2708 00:56:11.158789 Final RX Vref Byte 1 = 54 to rank0
2709 00:56:11.158836 Final RX Vref Byte 0 = 46 to rank1
2710 00:56:11.158883 Final RX Vref Byte 1 = 54 to rank1==
2711 00:56:11.158931 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 00:56:11.158978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2713 00:56:11.159026 ==
2714 00:56:11.159073 DQS Delay:
2715 00:56:11.159120 DQS0 = 0, DQS1 = 0
2716 00:56:11.159167 DQM Delay:
2717 00:56:11.159214 DQM0 = 114, DQM1 = 106
2718 00:56:11.159261 DQ Delay:
2719 00:56:11.159308 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2720 00:56:11.159356 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2721 00:56:11.159403 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =100
2722 00:56:11.159451 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =118
2723 00:56:11.159499
2724 00:56:11.159546
2725 00:56:11.159593 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2726 00:56:11.159643 CH0 RK0: MR19=404, MR18=B0B
2727 00:56:11.159692 CH0_RK0: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
2728 00:56:11.159739
2729 00:56:11.159787 ----->DramcWriteLeveling(PI) begin...
2730 00:56:11.159835 ==
2731 00:56:11.159883 Dram Type= 6, Freq= 0, CH_0, rank 1
2732 00:56:11.159931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2733 00:56:11.159979 ==
2734 00:56:11.160026 Write leveling (Byte 0): 27 => 27
2735 00:56:11.160074 Write leveling (Byte 1): 25 => 25
2736 00:56:11.160122 DramcWriteLeveling(PI) end<-----
2737 00:56:11.160169
2738 00:56:11.160215 ==
2739 00:56:11.160262 Dram Type= 6, Freq= 0, CH_0, rank 1
2740 00:56:11.160331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2741 00:56:11.160412 ==
2742 00:56:11.160493 [Gating] SW mode calibration
2743 00:56:11.160573 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2744 00:56:11.160650 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2745 00:56:11.160705 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2746 00:56:11.160754 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2747 00:56:11.160803 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2748 00:56:11.160851 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2749 00:56:11.160899 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
2750 00:56:11.160947 0 11 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
2751 00:56:11.160994 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2752 00:56:11.161041 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2753 00:56:11.161089 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2754 00:56:11.161137 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2755 00:56:11.161184 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2756 00:56:11.161231 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2757 00:56:11.161279 0 12 16 | B1->B0 | 2727 3838 | 0 1 | (0 0) (0 0)
2758 00:56:11.161327 0 12 20 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2759 00:56:11.161374 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2760 00:56:11.161423 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2761 00:56:11.161470 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2762 00:56:11.161518 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2763 00:56:11.161565 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2764 00:56:11.161612 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2765 00:56:11.161847 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2766 00:56:11.161902 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2767 00:56:11.161951 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2768 00:56:11.162000 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2769 00:56:11.162048 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2770 00:56:11.162096 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2771 00:56:11.162144 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 00:56:11.162192 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 00:56:11.162276 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 00:56:11.162338 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 00:56:11.162386 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 00:56:11.162434 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 00:56:11.162481 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 00:56:11.162528 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 00:56:11.162576 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 00:56:11.162623 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 00:56:11.162671 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2782 00:56:11.162718 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2783 00:56:11.162765 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2784 00:56:11.162812 Total UI for P1: 0, mck2ui 16
2785 00:56:11.162859 best dqsien dly found for B0: ( 0, 15, 18)
2786 00:56:11.162907 Total UI for P1: 0, mck2ui 16
2787 00:56:11.162954 best dqsien dly found for B1: ( 0, 15, 18)
2788 00:56:11.163000 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2789 00:56:11.163047 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2790 00:56:11.163095
2791 00:56:11.163142 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2792 00:56:11.163190 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2793 00:56:11.163237 [Gating] SW calibration Done
2794 00:56:11.163285 ==
2795 00:56:11.163333 Dram Type= 6, Freq= 0, CH_0, rank 1
2796 00:56:11.163381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2797 00:56:11.163434 ==
2798 00:56:11.163515 RX Vref Scan: 0
2799 00:56:11.163591
2800 00:56:11.163664 RX Vref 0 -> 0, step: 1
2801 00:56:11.163731
2802 00:56:11.163781 RX Delay -40 -> 252, step: 8
2803 00:56:11.163830 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2804 00:56:11.163879 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2805 00:56:11.163926 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2806 00:56:11.163973 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2807 00:56:11.164020 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2808 00:56:11.164067 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2809 00:56:11.164115 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2810 00:56:11.164163 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2811 00:56:11.164211 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2812 00:56:11.164258 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2813 00:56:11.164312 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2814 00:56:11.164399 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2815 00:56:11.164460 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2816 00:56:11.164510 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2817 00:56:11.164557 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2818 00:56:11.164605 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2819 00:56:11.164653 ==
2820 00:56:11.164700 Dram Type= 6, Freq= 0, CH_0, rank 1
2821 00:56:11.164748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2822 00:56:11.164795 ==
2823 00:56:11.164844 DQS Delay:
2824 00:56:11.164892 DQS0 = 0, DQS1 = 0
2825 00:56:11.164939 DQM Delay:
2826 00:56:11.164986 DQM0 = 113, DQM1 = 105
2827 00:56:11.165034 DQ Delay:
2828 00:56:11.165081 DQ0 =107, DQ1 =115, DQ2 =111, DQ3 =111
2829 00:56:11.165129 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2830 00:56:11.165176 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2831 00:56:11.165223 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =111
2832 00:56:11.165270
2833 00:56:11.165316
2834 00:56:11.165363 ==
2835 00:56:11.165411 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 00:56:11.165459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2837 00:56:11.165507 ==
2838 00:56:11.165554
2839 00:56:11.165601
2840 00:56:11.165647 TX Vref Scan disable
2841 00:56:11.165694 == TX Byte 0 ==
2842 00:56:11.165740 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2843 00:56:11.165787 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2844 00:56:11.165835 == TX Byte 1 ==
2845 00:56:11.165883 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2846 00:56:11.165930 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2847 00:56:11.165977 ==
2848 00:56:11.166023 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 00:56:11.166071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2850 00:56:11.166118 ==
2851 00:56:11.166166 TX Vref=22, minBit 8, minWin=25, winSum=418
2852 00:56:11.166222 TX Vref=24, minBit 8, minWin=25, winSum=422
2853 00:56:11.166307 TX Vref=26, minBit 9, minWin=25, winSum=429
2854 00:56:11.166356 TX Vref=28, minBit 1, minWin=26, winSum=431
2855 00:56:11.166405 TX Vref=30, minBit 8, minWin=26, winSum=432
2856 00:56:11.166452 TX Vref=32, minBit 8, minWin=26, winSum=429
2857 00:56:11.166500 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
2858 00:56:11.166547
2859 00:56:11.166594 Final TX Range 1 Vref 30
2860 00:56:11.166642
2861 00:56:11.166688 ==
2862 00:56:11.166751 Dram Type= 6, Freq= 0, CH_0, rank 1
2863 00:56:11.166829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2864 00:56:11.166908 ==
2865 00:56:11.166983
2866 00:56:11.167039
2867 00:56:11.167088 TX Vref Scan disable
2868 00:56:11.167137 == TX Byte 0 ==
2869 00:56:11.167184 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2870 00:56:11.167232 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2871 00:56:11.167280 == TX Byte 1 ==
2872 00:56:11.167328 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2873 00:56:11.167376 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2874 00:56:11.167423
2875 00:56:11.167470 [DATLAT]
2876 00:56:11.167518 Freq=1200, CH0 RK1
2877 00:56:11.167565
2878 00:56:11.167612 DATLAT Default: 0xc
2879 00:56:11.167660 0, 0xFFFF, sum = 0
2880 00:56:11.167709 1, 0xFFFF, sum = 0
2881 00:56:11.167757 2, 0xFFFF, sum = 0
2882 00:56:11.167806 3, 0xFFFF, sum = 0
2883 00:56:11.167854 4, 0xFFFF, sum = 0
2884 00:56:11.167903 5, 0xFFFF, sum = 0
2885 00:56:11.167951 6, 0xFFFF, sum = 0
2886 00:56:11.168000 7, 0xFFFF, sum = 0
2887 00:56:11.168047 8, 0xFFFF, sum = 0
2888 00:56:11.168095 9, 0xFFFF, sum = 0
2889 00:56:11.168144 10, 0xFFFF, sum = 0
2890 00:56:11.168192 11, 0x0, sum = 1
2891 00:56:11.168240 12, 0x0, sum = 2
2892 00:56:11.168289 13, 0x0, sum = 3
2893 00:56:11.168337 14, 0x0, sum = 4
2894 00:56:11.168576 best_step = 12
2895 00:56:11.168632
2896 00:56:11.168680 ==
2897 00:56:11.168728 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 00:56:11.168776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2899 00:56:11.168824 ==
2900 00:56:11.168872 RX Vref Scan: 0
2901 00:56:11.168919
2902 00:56:11.168966 RX Vref 0 -> 0, step: 1
2903 00:56:11.169013
2904 00:56:11.169060 RX Delay -21 -> 252, step: 4
2905 00:56:11.169108 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2906 00:56:11.169156 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2907 00:56:11.169204 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2908 00:56:11.169252 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2909 00:56:11.169299 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2910 00:56:11.169347 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2911 00:56:11.169394 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
2912 00:56:11.169442 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2913 00:56:11.169489 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2914 00:56:11.169537 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2915 00:56:11.169585 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
2916 00:56:11.169633 iDelay=195, Bit 11, Center 100 (39 ~ 162) 124
2917 00:56:11.169680 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
2918 00:56:11.169729 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
2919 00:56:11.169777 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2920 00:56:11.169823 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
2921 00:56:11.169870 ==
2922 00:56:11.169918 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 00:56:11.169965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2924 00:56:11.170013 ==
2925 00:56:11.170060 DQS Delay:
2926 00:56:11.170107 DQS0 = 0, DQS1 = 0
2927 00:56:11.170154 DQM Delay:
2928 00:56:11.170201 DQM0 = 114, DQM1 = 107
2929 00:56:11.170332 DQ Delay:
2930 00:56:11.170413 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2931 00:56:11.170499 DQ4 =118, DQ5 =106, DQ6 =122, DQ7 =122
2932 00:56:11.170575 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =100
2933 00:56:11.170649 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
2934 00:56:11.170717
2935 00:56:11.170768
2936 00:56:11.170817 [DQSOSCAuto] RK1, (LSB)MR18= 0x1616, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
2937 00:56:11.170867 CH0 RK1: MR19=404, MR18=1616
2938 00:56:11.170916 CH0_RK1: MR19=0x404, MR18=0x1616, DQSOSC=401, MR23=63, INC=40, DEC=27
2939 00:56:11.170965 [RxdqsGatingPostProcess] freq 1200
2940 00:56:11.171013 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2941 00:56:11.171062 Pre-setting of DQS Precalculation
2942 00:56:11.171110 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2943 00:56:11.171158 ==
2944 00:56:11.171206 Dram Type= 6, Freq= 0, CH_1, rank 0
2945 00:56:11.171254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2946 00:56:11.171302 ==
2947 00:56:11.171349 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2948 00:56:11.171397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2949 00:56:11.171446 [CA 0] Center 37 (7~68) winsize 62
2950 00:56:11.171495 [CA 1] Center 37 (7~68) winsize 62
2951 00:56:11.171542 [CA 2] Center 34 (4~65) winsize 62
2952 00:56:11.171590 [CA 3] Center 33 (3~64) winsize 62
2953 00:56:11.171637 [CA 4] Center 32 (1~63) winsize 63
2954 00:56:11.171684 [CA 5] Center 32 (1~63) winsize 63
2955 00:56:11.171730
2956 00:56:11.171777 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2957 00:56:11.171826
2958 00:56:11.171874 [CATrainingPosCal] consider 1 rank data
2959 00:56:11.171921 u2DelayCellTimex100 = 270/100 ps
2960 00:56:11.171968 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2961 00:56:11.172016 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2962 00:56:11.172063 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2963 00:56:11.172110 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2964 00:56:11.172157 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2965 00:56:11.172203 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2966 00:56:11.172250
2967 00:56:11.172298 CA PerBit enable=1, Macro0, CA PI delay=32
2968 00:56:11.172345
2969 00:56:11.172393 [CBTSetCACLKResult] CA Dly = 32
2970 00:56:11.172441 CS Dly: 6 (0~37)
2971 00:56:11.172488 ==
2972 00:56:11.172536 Dram Type= 6, Freq= 0, CH_1, rank 1
2973 00:56:11.172584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2974 00:56:11.172631 ==
2975 00:56:11.172679 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2976 00:56:11.172727 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2977 00:56:11.172776 [CA 0] Center 37 (7~68) winsize 62
2978 00:56:11.172823 [CA 1] Center 37 (6~68) winsize 63
2979 00:56:11.172870 [CA 2] Center 34 (3~65) winsize 63
2980 00:56:11.172918 [CA 3] Center 33 (3~64) winsize 62
2981 00:56:11.172965 [CA 4] Center 32 (2~63) winsize 62
2982 00:56:11.173012 [CA 5] Center 32 (1~63) winsize 63
2983 00:56:11.173059
2984 00:56:11.173106 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2985 00:56:11.173154
2986 00:56:11.173201 [CATrainingPosCal] consider 2 rank data
2987 00:56:11.173249 u2DelayCellTimex100 = 270/100 ps
2988 00:56:11.173319 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2989 00:56:11.173396 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2990 00:56:11.173473 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2991 00:56:11.173548 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2992 00:56:11.173600 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2993 00:56:11.173648 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2994 00:56:11.173695
2995 00:56:11.173743 CA PerBit enable=1, Macro0, CA PI delay=32
2996 00:56:11.291249
2997 00:56:11.291712 [CBTSetCACLKResult] CA Dly = 32
2998 00:56:11.292047 CS Dly: 6 (0~38)
2999 00:56:11.292358
3000 00:56:11.292657 ----->DramcWriteLeveling(PI) begin...
3001 00:56:11.292951 ==
3002 00:56:11.293233 Dram Type= 6, Freq= 0, CH_1, rank 0
3003 00:56:11.293513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3004 00:56:11.293793 ==
3005 00:56:11.294071 Write leveling (Byte 0): 19 => 19
3006 00:56:11.294373 Write leveling (Byte 1): 25 => 25
3007 00:56:11.294651 DramcWriteLeveling(PI) end<-----
3008 00:56:11.294923
3009 00:56:11.295195 ==
3010 00:56:11.295469 Dram Type= 6, Freq= 0, CH_1, rank 0
3011 00:56:11.295744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3012 00:56:11.296020 ==
3013 00:56:11.296291 [Gating] SW mode calibration
3014 00:56:11.296563 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3015 00:56:11.296841 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3016 00:56:11.297117 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3017 00:56:11.297392 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3018 00:56:11.298053 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3019 00:56:11.298401 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
3020 00:56:11.298685 0 11 16 | B1->B0 | 3434 2929 | 0 0 | (0 1) (0 0)
3021 00:56:11.298962 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3022 00:56:11.299237 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3023 00:56:11.299511 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3024 00:56:11.299786 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3025 00:56:11.300055 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3026 00:56:11.300325 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3027 00:56:11.300618 0 12 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3028 00:56:11.301091 0 12 16 | B1->B0 | 3838 4444 | 0 1 | (0 0) (0 0)
3029 00:56:11.301517 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3030 00:56:11.301834 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3031 00:56:11.302113 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3032 00:56:11.302435 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3033 00:56:11.302720 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3034 00:56:11.302993 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 00:56:11.303267 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3036 00:56:11.303625 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3037 00:56:11.303932 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3038 00:56:11.304335 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3039 00:56:11.304768 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3040 00:56:11.305233 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3041 00:56:11.305668 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3042 00:56:11.305971 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 00:56:11.306272 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 00:56:11.306553 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 00:56:11.306846 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 00:56:11.307147 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 00:56:11.307422 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 00:56:11.307784 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 00:56:11.308214 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 00:56:11.308625 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 00:56:11.308891 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 00:56:11.309142 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3053 00:56:11.309391 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3054 00:56:11.309636 Total UI for P1: 0, mck2ui 16
3055 00:56:11.309885 best dqsien dly found for B0: ( 0, 15, 16)
3056 00:56:11.310132 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3057 00:56:11.310403 Total UI for P1: 0, mck2ui 16
3058 00:56:11.310653 best dqsien dly found for B1: ( 0, 15, 18)
3059 00:56:11.311013 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3060 00:56:11.311405 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3061 00:56:11.311828
3062 00:56:11.312216 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3063 00:56:11.312529 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3064 00:56:11.312808 [Gating] SW calibration Done
3065 00:56:11.313079 ==
3066 00:56:11.313351 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 00:56:11.313627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3068 00:56:11.313904 ==
3069 00:56:11.314299 RX Vref Scan: 0
3070 00:56:11.314730
3071 00:56:11.315151 RX Vref 0 -> 0, step: 1
3072 00:56:11.315446
3073 00:56:11.315726 RX Delay -40 -> 252, step: 8
3074 00:56:11.316007 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3075 00:56:11.316290 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3076 00:56:11.316568 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3077 00:56:11.316817 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3078 00:56:11.317069 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3079 00:56:11.317333 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3080 00:56:11.317746 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3081 00:56:11.318203 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3082 00:56:11.318616 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3083 00:56:11.319006 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3084 00:56:11.319428 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3085 00:56:11.319731 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3086 00:56:11.319994 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3087 00:56:11.320255 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3088 00:56:11.320512 iDelay=208, Bit 14, Center 115 (48 ~ 183) 136
3089 00:56:11.320896 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3090 00:56:11.321280 ==
3091 00:56:11.321638 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 00:56:11.321909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3093 00:56:11.322169 ==
3094 00:56:11.322469 DQS Delay:
3095 00:56:11.322726 DQS0 = 0, DQS1 = 0
3096 00:56:11.322976 DQM Delay:
3097 00:56:11.323227 DQM0 = 116, DQM1 = 107
3098 00:56:11.323462 DQ Delay:
3099 00:56:11.323658 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3100 00:56:11.323963 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3101 00:56:11.324282 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =95
3102 00:56:11.324552 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3103 00:56:11.324777
3104 00:56:11.324962
3105 00:56:11.325144 ==
3106 00:56:11.325324 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 00:56:11.325506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3108 00:56:11.325684 ==
3109 00:56:11.325860
3110 00:56:11.326033
3111 00:56:11.326208 TX Vref Scan disable
3112 00:56:11.326420 == TX Byte 0 ==
3113 00:56:11.326598 Update DQ dly =835 (3 ,1, 35) DQ OEN =(2 ,6)
3114 00:56:11.326777 Update DQM dly =835 (3 ,1, 35) DQM OEN =(2 ,6)
3115 00:56:11.326967 == TX Byte 1 ==
3116 00:56:11.327263 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3117 00:56:11.327594 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3118 00:56:11.327866 ==
3119 00:56:11.328095 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 00:56:11.328280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3121 00:56:11.328461 ==
3122 00:56:11.328596 TX Vref=22, minBit 4, minWin=25, winSum=409
3123 00:56:11.328734 TX Vref=24, minBit 9, minWin=25, winSum=418
3124 00:56:11.328869 TX Vref=26, minBit 15, minWin=25, winSum=422
3125 00:56:11.329264 TX Vref=28, minBit 8, minWin=26, winSum=426
3126 00:56:11.329419 TX Vref=30, minBit 8, minWin=26, winSum=431
3127 00:56:11.329555 TX Vref=32, minBit 3, minWin=26, winSum=428
3128 00:56:11.329690 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 30
3129 00:56:11.329827
3130 00:56:11.329960 Final TX Range 1 Vref 30
3131 00:56:11.330098
3132 00:56:11.330257 ==
3133 00:56:11.330431 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 00:56:11.330655 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3135 00:56:11.330859 ==
3136 00:56:11.331020
3137 00:56:11.331158
3138 00:56:11.331290 TX Vref Scan disable
3139 00:56:11.331423 == TX Byte 0 ==
3140 00:56:11.331557 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3141 00:56:11.331692 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3142 00:56:11.331827 == TX Byte 1 ==
3143 00:56:11.331961 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3144 00:56:11.332094 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3145 00:56:11.332228
3146 00:56:11.332360 [DATLAT]
3147 00:56:11.332494 Freq=1200, CH1 RK0
3148 00:56:11.332626
3149 00:56:11.332758 DATLAT Default: 0xd
3150 00:56:11.332891 0, 0xFFFF, sum = 0
3151 00:56:11.333028 1, 0xFFFF, sum = 0
3152 00:56:11.333166 2, 0xFFFF, sum = 0
3153 00:56:11.333302 3, 0xFFFF, sum = 0
3154 00:56:11.333435 4, 0xFFFF, sum = 0
3155 00:56:11.333544 5, 0xFFFF, sum = 0
3156 00:56:11.333654 6, 0xFFFF, sum = 0
3157 00:56:11.333761 7, 0xFFFF, sum = 0
3158 00:56:11.333882 8, 0xFFFF, sum = 0
3159 00:56:11.334073 9, 0xFFFF, sum = 0
3160 00:56:11.334277 10, 0xFFFF, sum = 0
3161 00:56:11.334443 11, 0x0, sum = 1
3162 00:56:11.334591 12, 0x0, sum = 2
3163 00:56:11.334707 13, 0x0, sum = 3
3164 00:56:11.334818 14, 0x0, sum = 4
3165 00:56:11.334929 best_step = 12
3166 00:56:11.335034
3167 00:56:11.335141 ==
3168 00:56:11.335248 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 00:56:11.335355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3170 00:56:11.335461 ==
3171 00:56:11.335565 RX Vref Scan: 1
3172 00:56:11.335671
3173 00:56:11.335778 Set Vref Range= 32 -> 127
3174 00:56:11.335885
3175 00:56:11.335991 RX Vref 32 -> 127, step: 1
3176 00:56:11.336098
3177 00:56:11.336203 RX Delay -29 -> 252, step: 4
3178 00:56:11.336309
3179 00:56:11.336415 Set Vref, RX VrefLevel [Byte0]: 32
3180 00:56:11.336522 [Byte1]: 32
3181 00:56:11.336629
3182 00:56:11.336735 Set Vref, RX VrefLevel [Byte0]: 33
3183 00:56:11.336908 [Byte1]: 33
3184 00:56:11.337074
3185 00:56:11.337240 Set Vref, RX VrefLevel [Byte0]: 34
3186 00:56:11.337359 [Byte1]: 34
3187 00:56:11.337471
3188 00:56:11.337579 Set Vref, RX VrefLevel [Byte0]: 35
3189 00:56:11.337686 [Byte1]: 35
3190 00:56:11.337793
3191 00:56:11.337899 Set Vref, RX VrefLevel [Byte0]: 36
3192 00:56:11.338006 [Byte1]: 36
3193 00:56:11.338113
3194 00:56:11.338230 Set Vref, RX VrefLevel [Byte0]: 37
3195 00:56:11.338342 [Byte1]: 37
3196 00:56:11.338457
3197 00:56:11.338545 Set Vref, RX VrefLevel [Byte0]: 38
3198 00:56:11.338634 [Byte1]: 38
3199 00:56:11.338720
3200 00:56:11.338808 Set Vref, RX VrefLevel [Byte0]: 39
3201 00:56:11.338897 [Byte1]: 39
3202 00:56:11.338986
3203 00:56:11.339074 Set Vref, RX VrefLevel [Byte0]: 40
3204 00:56:11.339164 [Byte1]: 40
3205 00:56:11.339254
3206 00:56:11.339342 Set Vref, RX VrefLevel [Byte0]: 41
3207 00:56:11.339432 [Byte1]: 41
3208 00:56:11.339521
3209 00:56:11.339609 Set Vref, RX VrefLevel [Byte0]: 42
3210 00:56:11.339699 [Byte1]: 42
3211 00:56:11.339787
3212 00:56:11.339877 Set Vref, RX VrefLevel [Byte0]: 43
3213 00:56:11.339967 [Byte1]: 43
3214 00:56:11.340060
3215 00:56:11.340214 Set Vref, RX VrefLevel [Byte0]: 44
3216 00:56:11.340351 [Byte1]: 44
3217 00:56:11.340487
3218 00:56:11.340584 Set Vref, RX VrefLevel [Byte0]: 45
3219 00:56:11.340676 [Byte1]: 45
3220 00:56:11.340766
3221 00:56:11.340855 Set Vref, RX VrefLevel [Byte0]: 46
3222 00:56:11.340945 [Byte1]: 46
3223 00:56:11.341035
3224 00:56:11.341123 Set Vref, RX VrefLevel [Byte0]: 47
3225 00:56:11.341213 [Byte1]: 47
3226 00:56:11.341300
3227 00:56:11.341388 Set Vref, RX VrefLevel [Byte0]: 48
3228 00:56:11.341476 [Byte1]: 48
3229 00:56:11.341565
3230 00:56:11.341654 Set Vref, RX VrefLevel [Byte0]: 49
3231 00:56:11.341743 [Byte1]: 49
3232 00:56:11.341831
3233 00:56:11.341921 Set Vref, RX VrefLevel [Byte0]: 50
3234 00:56:11.342040 [Byte1]: 50
3235 00:56:11.342132
3236 00:56:11.342231 Set Vref, RX VrefLevel [Byte0]: 51
3237 00:56:11.342324 [Byte1]: 51
3238 00:56:11.342413
3239 00:56:11.342502 Set Vref, RX VrefLevel [Byte0]: 52
3240 00:56:11.342592 [Byte1]: 52
3241 00:56:11.342681
3242 00:56:11.342770 Set Vref, RX VrefLevel [Byte0]: 53
3243 00:56:11.342860 [Byte1]: 53
3244 00:56:11.342949
3245 00:56:11.343037 Set Vref, RX VrefLevel [Byte0]: 54
3246 00:56:11.343125 [Byte1]: 54
3247 00:56:11.343214
3248 00:56:11.343303 Set Vref, RX VrefLevel [Byte0]: 55
3249 00:56:11.343402 [Byte1]: 55
3250 00:56:11.343478
3251 00:56:11.343588 Set Vref, RX VrefLevel [Byte0]: 56
3252 00:56:11.343718 [Byte1]: 56
3253 00:56:11.343845
3254 00:56:11.343962 Set Vref, RX VrefLevel [Byte0]: 57
3255 00:56:11.344080 [Byte1]: 57
3256 00:56:11.344164
3257 00:56:11.344243 Set Vref, RX VrefLevel [Byte0]: 58
3258 00:56:11.344322 [Byte1]: 58
3259 00:56:11.344399
3260 00:56:11.344476 Set Vref, RX VrefLevel [Byte0]: 59
3261 00:56:11.344553 [Byte1]: 59
3262 00:56:11.344629
3263 00:56:11.344705 Set Vref, RX VrefLevel [Byte0]: 60
3264 00:56:11.344780 [Byte1]: 60
3265 00:56:11.344857
3266 00:56:11.344933 Set Vref, RX VrefLevel [Byte0]: 61
3267 00:56:11.345010 [Byte1]: 61
3268 00:56:11.345085
3269 00:56:11.345160 Set Vref, RX VrefLevel [Byte0]: 62
3270 00:56:11.345237 [Byte1]: 62
3271 00:56:11.345315
3272 00:56:11.345391 Set Vref, RX VrefLevel [Byte0]: 63
3273 00:56:11.345467 [Byte1]: 63
3274 00:56:11.345544
3275 00:56:11.345621 Set Vref, RX VrefLevel [Byte0]: 64
3276 00:56:11.345698 [Byte1]: 64
3277 00:56:11.345774
3278 00:56:11.345851 Set Vref, RX VrefLevel [Byte0]: 65
3279 00:56:11.345928 [Byte1]: 65
3280 00:56:11.346005
3281 00:56:11.346081 Set Vref, RX VrefLevel [Byte0]: 66
3282 00:56:11.346158 [Byte1]: 66
3283 00:56:11.346253
3284 00:56:11.346334 Final RX Vref Byte 0 = 53 to rank0
3285 00:56:11.346413 Final RX Vref Byte 1 = 49 to rank0
3286 00:56:11.346490 Final RX Vref Byte 0 = 53 to rank1
3287 00:56:11.346618 Final RX Vref Byte 1 = 49 to rank1==
3288 00:56:11.346753 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 00:56:11.346883 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3290 00:56:11.347000 ==
3291 00:56:11.347099 DQS Delay:
3292 00:56:11.347180 DQS0 = 0, DQS1 = 0
3293 00:56:11.347259 DQM Delay:
3294 00:56:11.347336 DQM0 = 115, DQM1 = 105
3295 00:56:11.347624 DQ Delay:
3296 00:56:11.347711 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3297 00:56:11.347793 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3298 00:56:11.347870 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3299 00:56:11.347950 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =112
3300 00:56:11.348027
3301 00:56:11.348103
3302 00:56:11.348180 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x404, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
3303 00:56:11.348260 CH1 RK0: MR19=404, MR18=1D1D
3304 00:56:11.348337 CH1_RK0: MR19=0x404, MR18=0x1D1D, DQSOSC=398, MR23=63, INC=41, DEC=27
3305 00:56:11.348423
3306 00:56:11.348489 ----->DramcWriteLeveling(PI) begin...
3307 00:56:11.348558 ==
3308 00:56:11.348626 Dram Type= 6, Freq= 0, CH_1, rank 1
3309 00:56:11.348694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3310 00:56:11.348761 ==
3311 00:56:11.348829 Write leveling (Byte 0): 22 => 22
3312 00:56:11.348896 Write leveling (Byte 1): 24 => 24
3313 00:56:11.348964 DramcWriteLeveling(PI) end<-----
3314 00:56:11.349030
3315 00:56:11.349096 ==
3316 00:56:11.349163 Dram Type= 6, Freq= 0, CH_1, rank 1
3317 00:56:11.349231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3318 00:56:11.349298 ==
3319 00:56:11.349365 [Gating] SW mode calibration
3320 00:56:11.349433 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3321 00:56:11.349502 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3322 00:56:11.349570 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3323 00:56:11.349639 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3324 00:56:11.349705 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3325 00:56:11.349773 0 11 12 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
3326 00:56:11.349845 0 11 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
3327 00:56:11.349962 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3328 00:56:11.350072 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3329 00:56:11.350174 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3330 00:56:11.350277 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3331 00:56:11.350349 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3332 00:56:11.350418 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3333 00:56:11.350485 0 12 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
3334 00:56:11.350553 0 12 16 | B1->B0 | 3636 4646 | 1 0 | (1 1) (0 0)
3335 00:56:11.350620 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3336 00:56:11.350688 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3337 00:56:11.350754 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3338 00:56:11.350822 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3339 00:56:11.350889 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3340 00:56:11.350957 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3341 00:56:11.351026 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3342 00:56:11.351093 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3343 00:56:11.351161 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3344 00:56:11.351229 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3345 00:56:11.351296 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3346 00:56:11.351363 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3347 00:56:11.351430 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 00:56:11.351498 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 00:56:11.351566 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 00:56:11.351634 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 00:56:11.351702 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 00:56:11.351770 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 00:56:11.351837 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 00:56:11.351904 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 00:56:11.351973 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 00:56:11.352041 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 00:56:11.352108 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3358 00:56:11.352176 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3359 00:56:11.352243 Total UI for P1: 0, mck2ui 16
3360 00:56:11.352311 best dqsien dly found for B0: ( 0, 15, 12)
3361 00:56:11.352380 Total UI for P1: 0, mck2ui 16
3362 00:56:11.352447 best dqsien dly found for B1: ( 0, 15, 14)
3363 00:56:11.352514 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3364 00:56:11.352582 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3365 00:56:11.352648
3366 00:56:11.352714 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3367 00:56:11.352781 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3368 00:56:11.352848 [Gating] SW calibration Done
3369 00:56:11.352914 ==
3370 00:56:11.352980 Dram Type= 6, Freq= 0, CH_1, rank 1
3371 00:56:11.353047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3372 00:56:11.353113 ==
3373 00:56:11.353179 RX Vref Scan: 0
3374 00:56:11.353244
3375 00:56:11.353309 RX Vref 0 -> 0, step: 1
3376 00:56:11.353375
3377 00:56:11.353450 RX Delay -40 -> 252, step: 8
3378 00:56:11.353508 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3379 00:56:11.353577 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3380 00:56:11.353679 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3381 00:56:11.353782 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3382 00:56:11.353879 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3383 00:56:11.353969 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3384 00:56:11.354046 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3385 00:56:11.354109 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3386 00:56:11.354169 iDelay=200, Bit 8, Center 87 (8 ~ 167) 160
3387 00:56:11.354238 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3388 00:56:11.354300 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3389 00:56:11.354360 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3390 00:56:11.354420 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3391 00:56:11.354479 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3392 00:56:11.354540 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3393 00:56:11.354599 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3394 00:56:11.354658 ==
3395 00:56:11.354728 Dram Type= 6, Freq= 0, CH_1, rank 1
3396 00:56:11.354987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3397 00:56:11.355059 ==
3398 00:56:11.355120 DQS Delay:
3399 00:56:11.355180 DQS0 = 0, DQS1 = 0
3400 00:56:11.355242 DQM Delay:
3401 00:56:11.355302 DQM0 = 116, DQM1 = 104
3402 00:56:11.355362 DQ Delay:
3403 00:56:11.355421 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3404 00:56:11.355481 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3405 00:56:11.355541 DQ8 =87, DQ9 =91, DQ10 =103, DQ11 =99
3406 00:56:11.355601 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3407 00:56:11.355662
3408 00:56:11.355720
3409 00:56:11.355779 ==
3410 00:56:11.355838 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 00:56:11.355898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3412 00:56:11.355958 ==
3413 00:56:11.356017
3414 00:56:11.356075
3415 00:56:11.356134 TX Vref Scan disable
3416 00:56:11.356195 == TX Byte 0 ==
3417 00:56:11.356254 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3418 00:56:11.356314 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3419 00:56:11.356374 == TX Byte 1 ==
3420 00:56:11.356455 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3421 00:56:11.356552 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3422 00:56:11.356644 ==
3423 00:56:11.356737 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 00:56:11.356805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3425 00:56:11.356868 ==
3426 00:56:11.356928 TX Vref=22, minBit 9, minWin=25, winSum=419
3427 00:56:11.356989 TX Vref=24, minBit 1, minWin=26, winSum=423
3428 00:56:11.357049 TX Vref=26, minBit 3, minWin=26, winSum=428
3429 00:56:11.357108 TX Vref=28, minBit 3, minWin=26, winSum=428
3430 00:56:11.357168 TX Vref=30, minBit 8, minWin=26, winSum=429
3431 00:56:11.357228 TX Vref=32, minBit 0, minWin=26, winSum=428
3432 00:56:11.357288 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
3433 00:56:11.357347
3434 00:56:11.357406 Final TX Range 1 Vref 30
3435 00:56:11.357466
3436 00:56:11.357524 ==
3437 00:56:11.357584 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 00:56:11.357642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3439 00:56:11.357703 ==
3440 00:56:11.357762
3441 00:56:11.357822
3442 00:56:11.357882 TX Vref Scan disable
3443 00:56:11.357941 == TX Byte 0 ==
3444 00:56:11.358000 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3445 00:56:11.358069 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3446 00:56:11.358170 == TX Byte 1 ==
3447 00:56:11.358262 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3448 00:56:11.358325 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3449 00:56:11.358384
3450 00:56:11.358462 [DATLAT]
3451 00:56:11.358517 Freq=1200, CH1 RK1
3452 00:56:11.358571
3453 00:56:11.358628 DATLAT Default: 0xc
3454 00:56:11.358682 0, 0xFFFF, sum = 0
3455 00:56:11.358738 1, 0xFFFF, sum = 0
3456 00:56:11.358795 2, 0xFFFF, sum = 0
3457 00:56:11.358855 3, 0xFFFF, sum = 0
3458 00:56:11.358910 4, 0xFFFF, sum = 0
3459 00:56:11.358964 5, 0xFFFF, sum = 0
3460 00:56:11.359021 6, 0xFFFF, sum = 0
3461 00:56:11.359076 7, 0xFFFF, sum = 0
3462 00:56:11.359130 8, 0xFFFF, sum = 0
3463 00:56:11.359189 9, 0xFFFF, sum = 0
3464 00:56:11.359244 10, 0xFFFF, sum = 0
3465 00:56:11.359298 11, 0x0, sum = 1
3466 00:56:11.359356 12, 0x0, sum = 2
3467 00:56:11.359416 13, 0x0, sum = 3
3468 00:56:11.359471 14, 0x0, sum = 4
3469 00:56:11.359525 best_step = 12
3470 00:56:11.359581
3471 00:56:11.359634 ==
3472 00:56:11.359687 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 00:56:11.359757 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3474 00:56:11.359842 ==
3475 00:56:11.359929 RX Vref Scan: 0
3476 00:56:11.360013
3477 00:56:11.360097 RX Vref 0 -> 0, step: 1
3478 00:56:11.360184
3479 00:56:11.360274 RX Delay -37 -> 252, step: 4
3480 00:56:11.360371 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3481 00:56:11.360460 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3482 00:56:11.360542 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3483 00:56:11.360633 iDelay=199, Bit 3, Center 110 (39 ~ 182) 144
3484 00:56:11.360722 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3485 00:56:11.360809 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3486 00:56:11.360896 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3487 00:56:11.360981 iDelay=199, Bit 7, Center 110 (39 ~ 182) 144
3488 00:56:11.361067 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3489 00:56:11.361153 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3490 00:56:11.361238 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3491 00:56:11.361324 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3492 00:56:11.361409 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3493 00:56:11.361495 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3494 00:56:11.361580 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3495 00:56:11.361666 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3496 00:56:11.361750 ==
3497 00:56:11.361835 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 00:56:11.361921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3499 00:56:11.362006 ==
3500 00:56:11.362091 DQS Delay:
3501 00:56:11.362175 DQS0 = 0, DQS1 = 0
3502 00:56:11.362255 DQM Delay:
3503 00:56:11.362311 DQM0 = 114, DQM1 = 104
3504 00:56:11.362365 DQ Delay:
3505 00:56:11.362420 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =110
3506 00:56:11.362474 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3507 00:56:11.362528 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3508 00:56:11.362581 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =110
3509 00:56:11.362636
3510 00:56:11.362689
3511 00:56:11.362742 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3512 00:56:11.362798 CH1 RK1: MR19=404, MR18=D0D
3513 00:56:11.362852 CH1_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3514 00:56:11.362932 [RxdqsGatingPostProcess] freq 1200
3515 00:56:11.363024 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3516 00:56:11.363112 Pre-setting of DQS Precalculation
3517 00:56:11.363199 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3518 00:56:11.363279 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3519 00:56:11.363348 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3520 00:56:11.363405
3521 00:56:11.363468
3522 00:56:11.363517 [Calibration Summary] 2400 Mbps
3523 00:56:11.363567 CH 0, Rank 0
3524 00:56:11.363616 SW Impedance : PASS
3525 00:56:11.363665 DUTY Scan : NO K
3526 00:56:11.363714 ZQ Calibration : PASS
3527 00:56:11.363763 Jitter Meter : NO K
3528 00:56:11.363812 CBT Training : PASS
3529 00:56:11.363860 Write leveling : PASS
3530 00:56:11.363909 RX DQS gating : PASS
3531 00:56:11.363958 RX DQ/DQS(RDDQC) : PASS
3532 00:56:11.364006 TX DQ/DQS : PASS
3533 00:56:11.364055 RX DATLAT : PASS
3534 00:56:11.364104 RX DQ/DQS(Engine): PASS
3535 00:56:11.364152 TX OE : NO K
3536 00:56:11.364201 All Pass.
3537 00:56:11.364250
3538 00:56:11.364298 CH 0, Rank 1
3539 00:56:11.364347 SW Impedance : PASS
3540 00:56:11.364396 DUTY Scan : NO K
3541 00:56:11.364444 ZQ Calibration : PASS
3542 00:56:11.364492 Jitter Meter : NO K
3543 00:56:11.364732 CBT Training : PASS
3544 00:56:11.364787 Write leveling : PASS
3545 00:56:11.364840 RX DQS gating : PASS
3546 00:56:11.364929 RX DQ/DQS(RDDQC) : PASS
3547 00:56:11.364995 TX DQ/DQS : PASS
3548 00:56:11.365046 RX DATLAT : PASS
3549 00:56:11.365095 RX DQ/DQS(Engine): PASS
3550 00:56:11.365144 TX OE : NO K
3551 00:56:11.365194 All Pass.
3552 00:56:11.365243
3553 00:56:11.365291 CH 1, Rank 0
3554 00:56:11.365339 SW Impedance : PASS
3555 00:56:11.365388 DUTY Scan : NO K
3556 00:56:11.365437 ZQ Calibration : PASS
3557 00:56:11.365485 Jitter Meter : NO K
3558 00:56:11.365534 CBT Training : PASS
3559 00:56:11.365582 Write leveling : PASS
3560 00:56:11.365630 RX DQS gating : PASS
3561 00:56:11.365679 RX DQ/DQS(RDDQC) : PASS
3562 00:56:11.365728 TX DQ/DQS : PASS
3563 00:56:11.365777 RX DATLAT : PASS
3564 00:56:11.365825 RX DQ/DQS(Engine): PASS
3565 00:56:11.365873 TX OE : NO K
3566 00:56:11.365923 All Pass.
3567 00:56:11.365972
3568 00:56:11.366020 CH 1, Rank 1
3569 00:56:11.366068 SW Impedance : PASS
3570 00:56:11.366116 DUTY Scan : NO K
3571 00:56:11.366165 ZQ Calibration : PASS
3572 00:56:11.366219 Jitter Meter : NO K
3573 00:56:11.366271 CBT Training : PASS
3574 00:56:11.366319 Write leveling : PASS
3575 00:56:11.366377 RX DQS gating : PASS
3576 00:56:11.366457 RX DQ/DQS(RDDQC) : PASS
3577 00:56:11.366537 TX DQ/DQS : PASS
3578 00:56:11.366611 RX DATLAT : PASS
3579 00:56:11.366687 RX DQ/DQS(Engine): PASS
3580 00:56:11.366740 TX OE : NO K
3581 00:56:11.366790 All Pass.
3582 00:56:11.366839
3583 00:56:11.366887 DramC Write-DBI off
3584 00:56:11.366936 PER_BANK_REFRESH: Hybrid Mode
3585 00:56:11.366984 TX_TRACKING: ON
3586 00:56:11.367033 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3587 00:56:11.367083 [FAST_K] Save calibration result to emmc
3588 00:56:11.367132 dramc_set_vcore_voltage set vcore to 650000
3589 00:56:11.367180 Read voltage for 600, 5
3590 00:56:11.367229 Vio18 = 0
3591 00:56:11.367277 Vcore = 650000
3592 00:56:11.367325 Vdram = 0
3593 00:56:11.367373 Vddq = 0
3594 00:56:11.367420 Vmddr = 0
3595 00:56:11.367468 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3596 00:56:11.367516 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3597 00:56:11.367566 MEM_TYPE=3, freq_sel=19
3598 00:56:11.367614 sv_algorithm_assistance_LP4_1600
3599 00:56:11.367662 ============ PULL DRAM RESETB DOWN ============
3600 00:56:11.367711 ========== PULL DRAM RESETB DOWN end =========
3601 00:56:11.367760 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3602 00:56:11.367809 ===================================
3603 00:56:11.367857 LPDDR4 DRAM CONFIGURATION
3604 00:56:11.367905 ===================================
3605 00:56:11.367953 EX_ROW_EN[0] = 0x0
3606 00:56:11.368001 EX_ROW_EN[1] = 0x0
3607 00:56:11.368051 LP4Y_EN = 0x0
3608 00:56:11.368100 WORK_FSP = 0x0
3609 00:56:11.368148 WL = 0x2
3610 00:56:11.368196 RL = 0x2
3611 00:56:11.368244 BL = 0x2
3612 00:56:11.368293 RPST = 0x0
3613 00:56:11.368340 RD_PRE = 0x0
3614 00:56:11.368387 WR_PRE = 0x1
3615 00:56:11.368447 WR_PST = 0x0
3616 00:56:11.368494 DBI_WR = 0x0
3617 00:56:11.368542 DBI_RD = 0x0
3618 00:56:11.368589 OTF = 0x1
3619 00:56:11.368636 ===================================
3620 00:56:11.368684 ===================================
3621 00:56:11.368732 ANA top config
3622 00:56:11.368780 ===================================
3623 00:56:11.368827 DLL_ASYNC_EN = 0
3624 00:56:11.368874 ALL_SLAVE_EN = 1
3625 00:56:11.368921 NEW_RANK_MODE = 1
3626 00:56:11.368969 DLL_IDLE_MODE = 1
3627 00:56:11.369017 LP45_APHY_COMB_EN = 1
3628 00:56:11.369064 TX_ODT_DIS = 1
3629 00:56:11.369112 NEW_8X_MODE = 1
3630 00:56:11.369160 ===================================
3631 00:56:11.369207 ===================================
3632 00:56:11.369255 data_rate = 1200
3633 00:56:11.369302 CKR = 1
3634 00:56:11.369349 DQ_P2S_RATIO = 8
3635 00:56:11.369396 ===================================
3636 00:56:11.369463 CA_P2S_RATIO = 8
3637 00:56:11.369633 DQ_CA_OPEN = 0
3638 00:56:11.369736 DQ_SEMI_OPEN = 0
3639 00:56:11.369822 CA_SEMI_OPEN = 0
3640 00:56:11.369907 CA_FULL_RATE = 0
3641 00:56:11.369991 DQ_CKDIV4_EN = 1
3642 00:56:11.370070 CA_CKDIV4_EN = 1
3643 00:56:11.370144 CA_PREDIV_EN = 0
3644 00:56:11.370250 PH8_DLY = 0
3645 00:56:11.370318 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3646 00:56:11.370367 DQ_AAMCK_DIV = 4
3647 00:56:11.370415 CA_AAMCK_DIV = 4
3648 00:56:11.370463 CA_ADMCK_DIV = 4
3649 00:56:11.370512 DQ_TRACK_CA_EN = 0
3650 00:56:11.370560 CA_PICK = 600
3651 00:56:11.370607 CA_MCKIO = 600
3652 00:56:11.370655 MCKIO_SEMI = 0
3653 00:56:11.370703 PLL_FREQ = 2288
3654 00:56:11.370750 DQ_UI_PI_RATIO = 32
3655 00:56:11.370798 CA_UI_PI_RATIO = 0
3656 00:56:11.370846 ===================================
3657 00:56:11.370894 ===================================
3658 00:56:11.370943 memory_type:LPDDR4
3659 00:56:11.370990 GP_NUM : 10
3660 00:56:11.371037 SRAM_EN : 1
3661 00:56:11.371084 MD32_EN : 0
3662 00:56:11.371131 ===================================
3663 00:56:11.371179 [ANA_INIT] >>>>>>>>>>>>>>
3664 00:56:11.371227 <<<<<< [CONFIGURE PHASE]: ANA_TX
3665 00:56:11.371276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3666 00:56:11.371323 ===================================
3667 00:56:11.371374 data_rate = 1200,PCW = 0X5800
3668 00:56:11.371423 ===================================
3669 00:56:11.371470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3670 00:56:11.371523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3671 00:56:11.371574 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3672 00:56:11.371623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3673 00:56:11.371671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3674 00:56:11.371718 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3675 00:56:11.371765 [ANA_INIT] flow start
3676 00:56:11.371812 [ANA_INIT] PLL >>>>>>>>
3677 00:56:11.371860 [ANA_INIT] PLL <<<<<<<<
3678 00:56:11.371911 [ANA_INIT] MIDPI >>>>>>>>
3679 00:56:11.371963 [ANA_INIT] MIDPI <<<<<<<<
3680 00:56:11.372013 [ANA_INIT] DLL >>>>>>>>
3681 00:56:11.372089 [ANA_INIT] flow end
3682 00:56:11.372166 ============ LP4 DIFF to SE enter ============
3683 00:56:11.372434 ============ LP4 DIFF to SE exit ============
3684 00:56:11.372515 [ANA_INIT] <<<<<<<<<<<<<
3685 00:56:11.372592 [Flow] Enable top DCM control >>>>>
3686 00:56:11.372668 [Flow] Enable top DCM control <<<<<
3687 00:56:11.372745 Enable DLL master slave shuffle
3688 00:56:11.372822 ==============================================================
3689 00:56:11.372900 Gating Mode config
3690 00:56:11.372983 ==============================================================
3691 00:56:11.373061 Config description:
3692 00:56:11.373136 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3693 00:56:11.373217 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3694 00:56:11.373297 SELPH_MODE 0: By rank 1: By Phase
3695 00:56:11.373375 ==============================================================
3696 00:56:11.373452 GAT_TRACK_EN = 1
3697 00:56:11.373528 RX_GATING_MODE = 2
3698 00:56:11.373604 RX_GATING_TRACK_MODE = 2
3699 00:56:11.373680 SELPH_MODE = 1
3700 00:56:11.373756 PICG_EARLY_EN = 1
3701 00:56:11.373831 VALID_LAT_VALUE = 1
3702 00:56:11.373908 ==============================================================
3703 00:56:11.373984 Enter into Gating configuration >>>>
3704 00:56:11.374060 Exit from Gating configuration <<<<
3705 00:56:11.374137 Enter into DVFS_PRE_config >>>>>
3706 00:56:11.374218 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3707 00:56:11.374309 Exit from DVFS_PRE_config <<<<<
3708 00:56:11.374358 Enter into PICG configuration >>>>
3709 00:56:11.374406 Exit from PICG configuration <<<<
3710 00:56:11.374454 [RX_INPUT] configuration >>>>>
3711 00:56:11.374502 [RX_INPUT] configuration <<<<<
3712 00:56:11.374550 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3713 00:56:11.374598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3714 00:56:11.374646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3715 00:56:11.374694 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3716 00:56:11.374742 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3717 00:56:11.374791 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3718 00:56:11.374840 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3719 00:56:11.374887 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3720 00:56:11.374937 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3721 00:56:11.374985 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3722 00:56:11.375033 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3723 00:56:11.375080 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3724 00:56:11.375128 ===================================
3725 00:56:11.375177 LPDDR4 DRAM CONFIGURATION
3726 00:56:11.375225 ===================================
3727 00:56:11.375272 EX_ROW_EN[0] = 0x0
3728 00:56:11.375319 EX_ROW_EN[1] = 0x0
3729 00:56:11.375366 LP4Y_EN = 0x0
3730 00:56:11.375414 WORK_FSP = 0x0
3731 00:56:11.375460 WL = 0x2
3732 00:56:11.375507 RL = 0x2
3733 00:56:11.375554 BL = 0x2
3734 00:56:11.375602 RPST = 0x0
3735 00:56:11.375649 RD_PRE = 0x0
3736 00:56:11.375696 WR_PRE = 0x1
3737 00:56:11.375743 WR_PST = 0x0
3738 00:56:11.375790 DBI_WR = 0x0
3739 00:56:11.375837 DBI_RD = 0x0
3740 00:56:11.375884 OTF = 0x1
3741 00:56:11.375932 ===================================
3742 00:56:11.375980 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3743 00:56:11.376027 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3744 00:56:11.376075 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3745 00:56:11.376150 ===================================
3746 00:56:11.376232 LPDDR4 DRAM CONFIGURATION
3747 00:56:11.376310 ===================================
3748 00:56:11.376389 EX_ROW_EN[0] = 0x10
3749 00:56:11.376460 EX_ROW_EN[1] = 0x0
3750 00:56:11.376526 LP4Y_EN = 0x0
3751 00:56:11.376575 WORK_FSP = 0x0
3752 00:56:11.376624 WL = 0x2
3753 00:56:11.376671 RL = 0x2
3754 00:56:11.376718 BL = 0x2
3755 00:56:11.376765 RPST = 0x0
3756 00:56:11.376812 RD_PRE = 0x0
3757 00:56:11.376860 WR_PRE = 0x1
3758 00:56:11.376907 WR_PST = 0x0
3759 00:56:11.376954 DBI_WR = 0x0
3760 00:56:11.377001 DBI_RD = 0x0
3761 00:56:11.377050 OTF = 0x1
3762 00:56:11.377098 ===================================
3763 00:56:11.377146 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3764 00:56:11.377195 nWR fixed to 30
3765 00:56:11.377242 [ModeRegInit_LP4] CH0 RK0
3766 00:56:11.377290 [ModeRegInit_LP4] CH0 RK1
3767 00:56:11.377337 [ModeRegInit_LP4] CH1 RK0
3768 00:56:11.377384 [ModeRegInit_LP4] CH1 RK1
3769 00:56:11.377431 match AC timing 16
3770 00:56:11.377495 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3771 00:56:11.377556 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3772 00:56:11.377704 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3773 00:56:11.377803 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3774 00:56:11.377871 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3775 00:56:11.377923 ==
3776 00:56:11.377999 Dram Type= 6, Freq= 0, CH_0, rank 0
3777 00:56:11.378078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3778 00:56:11.378154 ==
3779 00:56:11.378234 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3780 00:56:11.378351 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3781 00:56:11.378400 [CA 0] Center 35 (5~66) winsize 62
3782 00:56:11.378448 [CA 1] Center 35 (5~66) winsize 62
3783 00:56:11.378497 [CA 2] Center 34 (4~65) winsize 62
3784 00:56:11.378544 [CA 3] Center 34 (4~65) winsize 62
3785 00:56:11.378592 [CA 4] Center 33 (3~64) winsize 62
3786 00:56:11.378639 [CA 5] Center 33 (3~64) winsize 62
3787 00:56:11.378686
3788 00:56:11.378733 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3789 00:56:11.378781
3790 00:56:11.378829 [CATrainingPosCal] consider 1 rank data
3791 00:56:11.378877 u2DelayCellTimex100 = 270/100 ps
3792 00:56:11.379113 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3793 00:56:11.379166 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3794 00:56:11.379215 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3795 00:56:11.379263 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3796 00:56:11.379311 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3797 00:56:11.379359 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3798 00:56:11.379407
3799 00:56:11.379455 CA PerBit enable=1, Macro0, CA PI delay=33
3800 00:56:11.379503
3801 00:56:11.379550 [CBTSetCACLKResult] CA Dly = 33
3802 00:56:11.379598 CS Dly: 5 (0~36)
3803 00:56:11.379646 ==
3804 00:56:11.379693 Dram Type= 6, Freq= 0, CH_0, rank 1
3805 00:56:11.379746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3806 00:56:11.379909 ==
3807 00:56:11.380003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3808 00:56:11.380068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3809 00:56:11.380119 [CA 0] Center 36 (6~66) winsize 61
3810 00:56:11.380168 [CA 1] Center 35 (5~66) winsize 62
3811 00:56:11.380216 [CA 2] Center 34 (4~65) winsize 62
3812 00:56:11.380265 [CA 3] Center 34 (4~65) winsize 62
3813 00:56:11.380312 [CA 4] Center 33 (3~64) winsize 62
3814 00:56:11.380360 [CA 5] Center 33 (3~64) winsize 62
3815 00:56:11.380408
3816 00:56:11.380455 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3817 00:56:11.380503
3818 00:56:11.380550 [CATrainingPosCal] consider 2 rank data
3819 00:56:11.380597 u2DelayCellTimex100 = 270/100 ps
3820 00:56:11.380646 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3821 00:56:11.380694 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3822 00:56:11.380741 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3823 00:56:11.380789 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3824 00:56:11.380836 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3825 00:56:11.380884 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3826 00:56:11.380931
3827 00:56:11.380979 CA PerBit enable=1, Macro0, CA PI delay=33
3828 00:56:11.381026
3829 00:56:11.381073 [CBTSetCACLKResult] CA Dly = 33
3830 00:56:11.381120 CS Dly: 5 (0~37)
3831 00:56:11.381167
3832 00:56:11.381214 ----->DramcWriteLeveling(PI) begin...
3833 00:56:11.381262 ==
3834 00:56:11.381310 Dram Type= 6, Freq= 0, CH_0, rank 0
3835 00:56:11.381357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3836 00:56:11.381405 ==
3837 00:56:11.381452 Write leveling (Byte 0): 33 => 33
3838 00:56:11.381499 Write leveling (Byte 1): 29 => 29
3839 00:56:11.381546 DramcWriteLeveling(PI) end<-----
3840 00:56:11.381594
3841 00:56:11.381641 ==
3842 00:56:11.381688 Dram Type= 6, Freq= 0, CH_0, rank 0
3843 00:56:11.381735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3844 00:56:11.381783 ==
3845 00:56:11.381830 [Gating] SW mode calibration
3846 00:56:11.381878 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3847 00:56:11.381926 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3848 00:56:11.381974 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3849 00:56:11.382022 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3850 00:56:11.382069 0 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
3851 00:56:11.382117 0 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
3852 00:56:11.382164 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3853 00:56:11.382221 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3854 00:56:11.382305 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3855 00:56:11.382353 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3856 00:56:11.382415 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3857 00:56:11.382583 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3858 00:56:11.382678 0 6 8 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
3859 00:56:11.382734 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3860 00:56:11.382784 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3861 00:56:11.382833 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3862 00:56:11.382880 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3863 00:56:11.382928 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3864 00:56:11.382975 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3865 00:56:11.383023 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3866 00:56:11.383071 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3867 00:56:11.383118 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3868 00:56:11.383166 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3869 00:56:11.383213 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3870 00:56:11.383261 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3871 00:56:11.383308 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3872 00:56:11.383356 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 00:56:11.383404 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 00:56:11.383451 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 00:56:11.383500 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 00:56:11.383548 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 00:56:11.383596 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 00:56:11.383643 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 00:56:11.383691 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 00:56:11.383738 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 00:56:11.383785 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 00:56:11.383833 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 00:56:11.383881 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3884 00:56:11.383929 Total UI for P1: 0, mck2ui 16
3885 00:56:11.383977 best dqsien dly found for B0: ( 0, 9, 10)
3886 00:56:11.384024 Total UI for P1: 0, mck2ui 16
3887 00:56:11.384072 best dqsien dly found for B1: ( 0, 9, 10)
3888 00:56:11.384119 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3889 00:56:11.384166 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3890 00:56:11.384213
3891 00:56:11.384260 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3892 00:56:11.384308 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3893 00:56:11.384355 [Gating] SW calibration Done
3894 00:56:11.384403 ==
3895 00:56:11.384451 Dram Type= 6, Freq= 0, CH_0, rank 0
3896 00:56:11.384498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3897 00:56:11.384546 ==
3898 00:56:11.384593 RX Vref Scan: 0
3899 00:56:11.384639
3900 00:56:11.384685 RX Vref 0 -> 0, step: 1
3901 00:56:11.384732
3902 00:56:11.384966 RX Delay -230 -> 252, step: 16
3903 00:56:11.385023 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3904 00:56:11.385073 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3905 00:56:11.385121 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3906 00:56:11.385169 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3907 00:56:11.385217 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3908 00:56:11.385265 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3909 00:56:11.385312 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3910 00:56:11.385360 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3911 00:56:11.385408 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3912 00:56:11.385456 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3913 00:56:11.385503 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3914 00:56:11.385551 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3915 00:56:11.385599 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3916 00:56:11.385646 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3917 00:56:11.385744 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3918 00:56:11.385881 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3919 00:56:11.385970 ==
3920 00:56:11.386050 Dram Type= 6, Freq= 0, CH_0, rank 0
3921 00:56:11.386127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3922 00:56:11.386206 ==
3923 00:56:11.386303 DQS Delay:
3924 00:56:11.386351 DQS0 = 0, DQS1 = 0
3925 00:56:11.386399 DQM Delay:
3926 00:56:11.386446 DQM0 = 38, DQM1 = 33
3927 00:56:11.386493 DQ Delay:
3928 00:56:11.386540 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3929 00:56:11.386588 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3930 00:56:11.386635 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3931 00:56:11.386682 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3932 00:56:11.386730
3933 00:56:11.386776
3934 00:56:11.386823 ==
3935 00:56:11.386871 Dram Type= 6, Freq= 0, CH_0, rank 0
3936 00:56:11.386918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3937 00:56:11.386966 ==
3938 00:56:11.387013
3939 00:56:11.387060
3940 00:56:11.387107 TX Vref Scan disable
3941 00:56:11.387154 == TX Byte 0 ==
3942 00:56:11.387200 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
3943 00:56:11.387249 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
3944 00:56:11.387297 == TX Byte 1 ==
3945 00:56:11.387344 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3946 00:56:11.387391 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3947 00:56:11.387439 ==
3948 00:56:11.387486 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 00:56:11.387534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 00:56:11.387581 ==
3951 00:56:11.387628
3952 00:56:11.387675
3953 00:56:11.387722 TX Vref Scan disable
3954 00:56:11.387770 == TX Byte 0 ==
3955 00:56:11.387817 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
3956 00:56:11.387865 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
3957 00:56:11.387913 == TX Byte 1 ==
3958 00:56:11.388069 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3959 00:56:11.388172 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3960 00:56:11.388238
3961 00:56:11.388287 [DATLAT]
3962 00:56:11.388335 Freq=600, CH0 RK0
3963 00:56:11.388383
3964 00:56:11.388431 DATLAT Default: 0x9
3965 00:56:11.388479 0, 0xFFFF, sum = 0
3966 00:56:11.388527 1, 0xFFFF, sum = 0
3967 00:56:11.388575 2, 0xFFFF, sum = 0
3968 00:56:11.388623 3, 0xFFFF, sum = 0
3969 00:56:11.388671 4, 0xFFFF, sum = 0
3970 00:56:11.388718 5, 0xFFFF, sum = 0
3971 00:56:11.388766 6, 0xFFFF, sum = 0
3972 00:56:11.388814 7, 0x0, sum = 1
3973 00:56:11.388862 8, 0x0, sum = 2
3974 00:56:11.388909 9, 0x0, sum = 3
3975 00:56:11.388957 10, 0x0, sum = 4
3976 00:56:11.389004 best_step = 8
3977 00:56:11.389052
3978 00:56:11.389099 ==
3979 00:56:11.389146 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 00:56:11.389194 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3981 00:56:11.389242 ==
3982 00:56:11.389289 RX Vref Scan: 1
3983 00:56:11.389335
3984 00:56:11.389381 RX Vref 0 -> 0, step: 1
3985 00:56:11.389428
3986 00:56:11.389474 RX Delay -195 -> 252, step: 8
3987 00:56:11.389522
3988 00:56:11.389569 Set Vref, RX VrefLevel [Byte0]: 46
3989 00:56:11.389616 [Byte1]: 54
3990 00:56:11.389663
3991 00:56:11.389709 Final RX Vref Byte 0 = 46 to rank0
3992 00:56:11.389757 Final RX Vref Byte 1 = 54 to rank0
3993 00:56:11.389804 Final RX Vref Byte 0 = 46 to rank1
3994 00:56:11.389850 Final RX Vref Byte 1 = 54 to rank1==
3995 00:56:11.389898 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 00:56:11.389945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3997 00:56:11.389992 ==
3998 00:56:11.603627 DQS Delay:
3999 00:56:11.604179 DQS0 = 0, DQS1 = 0
4000 00:56:11.604699 DQM Delay:
4001 00:56:11.605033 DQM0 = 39, DQM1 = 30
4002 00:56:11.605327 DQ Delay:
4003 00:56:11.605613 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
4004 00:56:11.605895 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =44
4005 00:56:11.606174 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
4006 00:56:11.606573 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =40
4007 00:56:11.606883
4008 00:56:11.607204
4009 00:56:11.607516 [DQSOSCAuto] RK0, (LSB)MR18= 0x6363, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4010 00:56:11.607806 CH0 RK0: MR19=808, MR18=6363
4011 00:56:11.608118 CH0_RK0: MR19=0x808, MR18=0x6363, DQSOSC=391, MR23=63, INC=171, DEC=114
4012 00:56:11.608434
4013 00:56:11.608717 ----->DramcWriteLeveling(PI) begin...
4014 00:56:11.609003 ==
4015 00:56:11.609276 Dram Type= 6, Freq= 0, CH_0, rank 1
4016 00:56:11.609550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4017 00:56:11.609825 ==
4018 00:56:11.610122 Write leveling (Byte 0): 30 => 30
4019 00:56:11.610436 Write leveling (Byte 1): 30 => 30
4020 00:56:11.610727 DramcWriteLeveling(PI) end<-----
4021 00:56:11.610995
4022 00:56:11.611260 ==
4023 00:56:11.611528 Dram Type= 6, Freq= 0, CH_0, rank 1
4024 00:56:11.611799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4025 00:56:11.612070 ==
4026 00:56:11.612335 [Gating] SW mode calibration
4027 00:56:11.612665 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4028 00:56:11.612952 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4029 00:56:11.613229 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 00:56:11.613501 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 00:56:11.613795 0 5 8 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 1)
4032 00:56:11.614125 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4033 00:56:11.614482 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 00:56:11.614900 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 00:56:11.615344 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 00:56:11.615639 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 00:56:11.615920 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 00:56:11.616196 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 00:56:11.616467 0 6 8 | B1->B0 | 2626 3131 | 0 1 | (0 0) (0 0)
4040 00:56:11.617087 0 6 12 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
4041 00:56:11.617427 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 00:56:11.617732 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 00:56:11.618016 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 00:56:11.618429 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 00:56:11.618716 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 00:56:11.618992 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 00:56:11.619264 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4048 00:56:11.619535 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 00:56:11.619805 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 00:56:11.620101 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 00:56:11.620405 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 00:56:11.620688 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 00:56:11.620983 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 00:56:11.621252 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 00:56:11.621524 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 00:56:11.621795 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 00:56:11.622067 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 00:56:11.622382 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 00:56:11.622658 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 00:56:11.622927 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 00:56:11.623199 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 00:56:11.623470 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 00:56:11.623782 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4064 00:56:11.624098 Total UI for P1: 0, mck2ui 16
4065 00:56:11.624381 best dqsien dly found for B0: ( 0, 9, 6)
4066 00:56:11.624653 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 00:56:11.624982 Total UI for P1: 0, mck2ui 16
4068 00:56:11.625285 best dqsien dly found for B1: ( 0, 9, 8)
4069 00:56:11.625565 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4070 00:56:11.627373 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4071 00:56:11.627816
4072 00:56:11.634103 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4073 00:56:11.637667 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4074 00:56:11.640296 [Gating] SW calibration Done
4075 00:56:11.640753 ==
4076 00:56:11.643750 Dram Type= 6, Freq= 0, CH_0, rank 1
4077 00:56:11.647423 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4078 00:56:11.647859 ==
4079 00:56:11.648200 RX Vref Scan: 0
4080 00:56:11.648508
4081 00:56:11.650805 RX Vref 0 -> 0, step: 1
4082 00:56:11.651319
4083 00:56:11.653936 RX Delay -230 -> 252, step: 16
4084 00:56:11.657693 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4085 00:56:11.661148 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4086 00:56:11.666997 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4087 00:56:11.670552 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4088 00:56:11.673555 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4089 00:56:11.676919 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4090 00:56:11.683597 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4091 00:56:11.686510 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4092 00:56:11.689892 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4093 00:56:11.693143 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4094 00:56:11.699976 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4095 00:56:11.703435 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4096 00:56:11.706989 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4097 00:56:11.709652 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4098 00:56:11.713510 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4099 00:56:11.719968 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4100 00:56:11.720429 ==
4101 00:56:11.723480 Dram Type= 6, Freq= 0, CH_0, rank 1
4102 00:56:11.726441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4103 00:56:11.726834 ==
4104 00:56:11.727137 DQS Delay:
4105 00:56:11.729749 DQS0 = 0, DQS1 = 0
4106 00:56:11.730138 DQM Delay:
4107 00:56:11.733724 DQM0 = 41, DQM1 = 34
4108 00:56:11.734193 DQ Delay:
4109 00:56:11.736217 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4110 00:56:11.739640 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4111 00:56:11.743262 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4112 00:56:11.746207 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4113 00:56:11.746629
4114 00:56:11.746964
4115 00:56:11.747256 ==
4116 00:56:11.749460 Dram Type= 6, Freq= 0, CH_0, rank 1
4117 00:56:11.752824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4118 00:56:11.756260 ==
4119 00:56:11.756715
4120 00:56:11.757020
4121 00:56:11.757300 TX Vref Scan disable
4122 00:56:11.759502 == TX Byte 0 ==
4123 00:56:11.762984 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4124 00:56:11.769837 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4125 00:56:11.770262 == TX Byte 1 ==
4126 00:56:11.773080 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4127 00:56:11.776350 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4128 00:56:11.779332 ==
4129 00:56:11.782940 Dram Type= 6, Freq= 0, CH_0, rank 1
4130 00:56:11.785979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4131 00:56:11.786400 ==
4132 00:56:11.786704
4133 00:56:11.786979
4134 00:56:11.789302 TX Vref Scan disable
4135 00:56:11.789695 == TX Byte 0 ==
4136 00:56:11.796171 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4137 00:56:11.799323 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4138 00:56:11.802458 == TX Byte 1 ==
4139 00:56:11.805870 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4140 00:56:11.809159 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4141 00:56:11.809558
4142 00:56:11.809864 [DATLAT]
4143 00:56:11.812458 Freq=600, CH0 RK1
4144 00:56:11.812848
4145 00:56:11.813152 DATLAT Default: 0x8
4146 00:56:11.815940 0, 0xFFFF, sum = 0
4147 00:56:11.819627 1, 0xFFFF, sum = 0
4148 00:56:11.820023 2, 0xFFFF, sum = 0
4149 00:56:11.822449 3, 0xFFFF, sum = 0
4150 00:56:11.822845 4, 0xFFFF, sum = 0
4151 00:56:11.826027 5, 0xFFFF, sum = 0
4152 00:56:11.826461 6, 0xFFFF, sum = 0
4153 00:56:11.829304 7, 0x0, sum = 1
4154 00:56:11.829727 8, 0x0, sum = 2
4155 00:56:11.830040 9, 0x0, sum = 3
4156 00:56:11.832851 10, 0x0, sum = 4
4157 00:56:11.833326 best_step = 8
4158 00:56:11.833632
4159 00:56:11.833911 ==
4160 00:56:11.835817 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 00:56:11.842523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4162 00:56:11.843025 ==
4163 00:56:11.843340 RX Vref Scan: 0
4164 00:56:11.843619
4165 00:56:11.845841 RX Vref 0 -> 0, step: 1
4166 00:56:11.846270
4167 00:56:11.849097 RX Delay -179 -> 252, step: 8
4168 00:56:11.852795 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4169 00:56:11.858813 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4170 00:56:11.862477 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4171 00:56:11.865982 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4172 00:56:11.868686 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4173 00:56:11.875721 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4174 00:56:11.878936 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4175 00:56:11.882005 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4176 00:56:11.885841 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4177 00:56:11.889035 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4178 00:56:11.895177 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4179 00:56:11.898676 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4180 00:56:11.901898 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4181 00:56:11.905376 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4182 00:56:11.912106 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4183 00:56:11.915152 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4184 00:56:11.915570 ==
4185 00:56:11.918522 Dram Type= 6, Freq= 0, CH_0, rank 1
4186 00:56:11.922135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4187 00:56:11.922567 ==
4188 00:56:11.925273 DQS Delay:
4189 00:56:11.925676 DQS0 = 0, DQS1 = 0
4190 00:56:11.925979 DQM Delay:
4191 00:56:11.928414 DQM0 = 41, DQM1 = 31
4192 00:56:11.928870 DQ Delay:
4193 00:56:11.931854 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4194 00:56:11.935247 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4195 00:56:11.938560 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =20
4196 00:56:11.941815 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4197 00:56:11.942204
4198 00:56:11.942554
4199 00:56:11.952358 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b6b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4200 00:56:11.954976 CH0 RK1: MR19=808, MR18=6B6B
4201 00:56:11.958594 CH0_RK1: MR19=0x808, MR18=0x6B6B, DQSOSC=389, MR23=63, INC=173, DEC=115
4202 00:56:11.961424 [RxdqsGatingPostProcess] freq 600
4203 00:56:11.968090 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4204 00:56:11.971901 Pre-setting of DQS Precalculation
4205 00:56:11.975121 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4206 00:56:11.975513 ==
4207 00:56:11.978759 Dram Type= 6, Freq= 0, CH_1, rank 0
4208 00:56:11.984829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4209 00:56:11.985292 ==
4210 00:56:11.988381 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4211 00:56:11.994826 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4212 00:56:11.998350 [CA 0] Center 35 (5~66) winsize 62
4213 00:56:12.001443 [CA 1] Center 35 (5~66) winsize 62
4214 00:56:12.005128 [CA 2] Center 33 (3~64) winsize 62
4215 00:56:12.008345 [CA 3] Center 33 (3~64) winsize 62
4216 00:56:12.011719 [CA 4] Center 33 (2~64) winsize 63
4217 00:56:12.015072 [CA 5] Center 33 (2~64) winsize 63
4218 00:56:12.015503
4219 00:56:12.018277 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4220 00:56:12.018708
4221 00:56:12.021620 [CATrainingPosCal] consider 1 rank data
4222 00:56:12.025449 u2DelayCellTimex100 = 270/100 ps
4223 00:56:12.028220 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4224 00:56:12.031276 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4225 00:56:12.038562 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4226 00:56:12.041433 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4227 00:56:12.044987 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4228 00:56:12.048386 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4229 00:56:12.048837
4230 00:56:12.051558 CA PerBit enable=1, Macro0, CA PI delay=33
4231 00:56:12.052090
4232 00:56:12.054736 [CBTSetCACLKResult] CA Dly = 33
4233 00:56:12.055183 CS Dly: 4 (0~35)
4234 00:56:12.058071 ==
4235 00:56:12.061117 Dram Type= 6, Freq= 0, CH_1, rank 1
4236 00:56:12.064702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4237 00:56:12.065235 ==
4238 00:56:12.067952 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4239 00:56:12.074209 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4240 00:56:12.077972 [CA 0] Center 35 (5~66) winsize 62
4241 00:56:12.081775 [CA 1] Center 35 (4~66) winsize 63
4242 00:56:12.084885 [CA 2] Center 33 (3~64) winsize 62
4243 00:56:12.088311 [CA 3] Center 33 (3~64) winsize 62
4244 00:56:12.091585 [CA 4] Center 32 (2~63) winsize 62
4245 00:56:12.094770 [CA 5] Center 32 (2~63) winsize 62
4246 00:56:12.095158
4247 00:56:12.098421 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4248 00:56:12.098812
4249 00:56:12.101636 [CATrainingPosCal] consider 2 rank data
4250 00:56:12.104904 u2DelayCellTimex100 = 270/100 ps
4251 00:56:12.107924 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4252 00:56:12.115043 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4253 00:56:12.118102 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4254 00:56:12.121561 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4255 00:56:12.124935 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4256 00:56:12.127988 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4257 00:56:12.128422
4258 00:56:12.131408 CA PerBit enable=1, Macro0, CA PI delay=32
4259 00:56:12.131840
4260 00:56:12.135099 [CBTSetCACLKResult] CA Dly = 32
4261 00:56:12.138057 CS Dly: 4 (0~35)
4262 00:56:12.138613
4263 00:56:12.141321 ----->DramcWriteLeveling(PI) begin...
4264 00:56:12.141751 ==
4265 00:56:12.144287 Dram Type= 6, Freq= 0, CH_1, rank 0
4266 00:56:12.147805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4267 00:56:12.148322 ==
4268 00:56:12.151215 Write leveling (Byte 0): 27 => 27
4269 00:56:12.154341 Write leveling (Byte 1): 27 => 27
4270 00:56:12.157690 DramcWriteLeveling(PI) end<-----
4271 00:56:12.158194
4272 00:56:12.158566 ==
4273 00:56:12.160775 Dram Type= 6, Freq= 0, CH_1, rank 0
4274 00:56:12.164723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4275 00:56:12.165291 ==
4276 00:56:12.167574 [Gating] SW mode calibration
4277 00:56:12.174052 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4278 00:56:12.180844 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4279 00:56:12.184273 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4280 00:56:12.187484 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4281 00:56:12.193748 0 5 8 | B1->B0 | 3030 2424 | 0 0 | (1 1) (0 0)
4282 00:56:12.197138 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 00:56:12.200866 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 00:56:12.206900 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 00:56:12.210500 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 00:56:12.213915 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 00:56:12.221194 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4288 00:56:12.223838 0 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4289 00:56:12.226833 0 6 8 | B1->B0 | 3636 3f3f | 0 1 | (0 0) (0 0)
4290 00:56:12.233711 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 00:56:12.237350 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 00:56:12.240300 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 00:56:12.247231 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 00:56:12.250749 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 00:56:12.253578 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4296 00:56:12.260145 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4297 00:56:12.263554 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4298 00:56:12.266883 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 00:56:12.273129 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 00:56:12.276299 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 00:56:12.279984 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 00:56:12.286491 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 00:56:12.290106 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 00:56:12.293417 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 00:56:12.299824 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 00:56:12.302718 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 00:56:12.306236 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 00:56:12.312760 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 00:56:12.316399 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 00:56:12.319836 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 00:56:12.326105 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 00:56:12.329368 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4313 00:56:12.333252 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4314 00:56:12.335974 Total UI for P1: 0, mck2ui 16
4315 00:56:12.339357 best dqsien dly found for B0: ( 0, 9, 4)
4316 00:56:12.342854 Total UI for P1: 0, mck2ui 16
4317 00:56:12.346317 best dqsien dly found for B1: ( 0, 9, 6)
4318 00:56:12.349513 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4319 00:56:12.353004 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4320 00:56:12.353522
4321 00:56:12.356367 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4322 00:56:12.362896 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4323 00:56:12.363419 [Gating] SW calibration Done
4324 00:56:12.363763 ==
4325 00:56:12.366077 Dram Type= 6, Freq= 0, CH_1, rank 0
4326 00:56:12.372811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4327 00:56:12.373331 ==
4328 00:56:12.373695 RX Vref Scan: 0
4329 00:56:12.374011
4330 00:56:12.375639 RX Vref 0 -> 0, step: 1
4331 00:56:12.376089
4332 00:56:12.378882 RX Delay -230 -> 252, step: 16
4333 00:56:12.382668 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4334 00:56:12.385623 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4335 00:56:12.392261 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4336 00:56:12.395491 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4337 00:56:12.398714 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4338 00:56:12.402208 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4339 00:56:12.405632 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4340 00:56:12.411720 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4341 00:56:12.415622 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4342 00:56:12.418287 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4343 00:56:12.421439 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4344 00:56:12.428210 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4345 00:56:12.431707 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4346 00:56:12.434835 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4347 00:56:12.438195 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4348 00:56:12.444755 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4349 00:56:12.444972 ==
4350 00:56:12.448264 Dram Type= 6, Freq= 0, CH_1, rank 0
4351 00:56:12.451546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4352 00:56:12.451763 ==
4353 00:56:12.451929 DQS Delay:
4354 00:56:12.454990 DQS0 = 0, DQS1 = 0
4355 00:56:12.455204 DQM Delay:
4356 00:56:12.457937 DQM0 = 39, DQM1 = 31
4357 00:56:12.458150 DQ Delay:
4358 00:56:12.461453 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4359 00:56:12.464574 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4360 00:56:12.467971 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4361 00:56:12.470923 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =41
4362 00:56:12.471095
4363 00:56:12.471228
4364 00:56:12.471349 ==
4365 00:56:12.474297 Dram Type= 6, Freq= 0, CH_1, rank 0
4366 00:56:12.477623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4367 00:56:12.480943 ==
4368 00:56:12.481065
4369 00:56:12.481158
4370 00:56:12.481245 TX Vref Scan disable
4371 00:56:12.484603 == TX Byte 0 ==
4372 00:56:12.487590 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4373 00:56:12.491284 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4374 00:56:12.494355 == TX Byte 1 ==
4375 00:56:12.497599 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4376 00:56:12.501004 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4377 00:56:12.504502 ==
4378 00:56:12.507803 Dram Type= 6, Freq= 0, CH_1, rank 0
4379 00:56:12.511015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4380 00:56:12.511325 ==
4381 00:56:12.511583
4382 00:56:12.511763
4383 00:56:12.514118 TX Vref Scan disable
4384 00:56:12.514437 == TX Byte 0 ==
4385 00:56:12.520806 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4386 00:56:12.524126 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4387 00:56:12.524311 == TX Byte 1 ==
4388 00:56:12.530730 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4389 00:56:12.533754 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4390 00:56:12.533889
4391 00:56:12.534036 [DATLAT]
4392 00:56:12.537342 Freq=600, CH1 RK0
4393 00:56:12.537519
4394 00:56:12.537668 DATLAT Default: 0x9
4395 00:56:12.540788 0, 0xFFFF, sum = 0
4396 00:56:12.540961 1, 0xFFFF, sum = 0
4397 00:56:12.543628 2, 0xFFFF, sum = 0
4398 00:56:12.543757 3, 0xFFFF, sum = 0
4399 00:56:12.547666 4, 0xFFFF, sum = 0
4400 00:56:12.550377 5, 0xFFFF, sum = 0
4401 00:56:12.550783 6, 0xFFFF, sum = 0
4402 00:56:12.553651 7, 0x0, sum = 1
4403 00:56:12.554053 8, 0x0, sum = 2
4404 00:56:12.554426 9, 0x0, sum = 3
4405 00:56:12.557513 10, 0x0, sum = 4
4406 00:56:12.557971 best_step = 8
4407 00:56:12.558461
4408 00:56:12.558901 ==
4409 00:56:12.560355 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 00:56:12.567266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4411 00:56:12.567712 ==
4412 00:56:12.568199 RX Vref Scan: 1
4413 00:56:12.568625
4414 00:56:12.570480 RX Vref 0 -> 0, step: 1
4415 00:56:12.570797
4416 00:56:12.573438 RX Delay -195 -> 252, step: 8
4417 00:56:12.573715
4418 00:56:12.576891 Set Vref, RX VrefLevel [Byte0]: 53
4419 00:56:12.580293 [Byte1]: 49
4420 00:56:12.580542
4421 00:56:12.583373 Final RX Vref Byte 0 = 53 to rank0
4422 00:56:12.586804 Final RX Vref Byte 1 = 49 to rank0
4423 00:56:12.589744 Final RX Vref Byte 0 = 53 to rank1
4424 00:56:12.593129 Final RX Vref Byte 1 = 49 to rank1==
4425 00:56:12.596793 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 00:56:12.600053 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4427 00:56:12.600216 ==
4428 00:56:12.603118 DQS Delay:
4429 00:56:12.603261 DQS0 = 0, DQS1 = 0
4430 00:56:12.606321 DQM Delay:
4431 00:56:12.606474 DQM0 = 37, DQM1 = 30
4432 00:56:12.606594 DQ Delay:
4433 00:56:12.609941 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4434 00:56:12.613130 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4435 00:56:12.616572 DQ8 =8, DQ9 =20, DQ10 =32, DQ11 =24
4436 00:56:12.620236 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4437 00:56:12.620844
4438 00:56:12.621324
4439 00:56:12.630109 [DQSOSCAuto] RK0, (LSB)MR18= 0x7777, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4440 00:56:12.633180 CH1 RK0: MR19=808, MR18=7777
4441 00:56:12.639732 CH1_RK0: MR19=0x808, MR18=0x7777, DQSOSC=387, MR23=63, INC=175, DEC=116
4442 00:56:12.640241
4443 00:56:12.643148 ----->DramcWriteLeveling(PI) begin...
4444 00:56:12.643430 ==
4445 00:56:12.646187 Dram Type= 6, Freq= 0, CH_1, rank 1
4446 00:56:12.649362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4447 00:56:12.649580 ==
4448 00:56:12.652870 Write leveling (Byte 0): 30 => 30
4449 00:56:12.656300 Write leveling (Byte 1): 30 => 30
4450 00:56:12.659358 DramcWriteLeveling(PI) end<-----
4451 00:56:12.659503
4452 00:56:12.659613 ==
4453 00:56:12.662917 Dram Type= 6, Freq= 0, CH_1, rank 1
4454 00:56:12.666407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4455 00:56:12.666516 ==
4456 00:56:12.669608 [Gating] SW mode calibration
4457 00:56:12.676187 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4458 00:56:12.682869 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4459 00:56:12.686049 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 00:56:12.689225 0 5 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
4461 00:56:12.696228 0 5 8 | B1->B0 | 2e2e 2525 | 1 0 | (0 0) (0 0)
4462 00:56:12.699794 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 00:56:12.702981 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 00:56:12.709622 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 00:56:12.712901 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 00:56:12.715988 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 00:56:12.722711 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 00:56:12.726032 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4469 00:56:12.729293 0 6 8 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
4470 00:56:12.736132 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 00:56:12.739615 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 00:56:12.742435 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 00:56:12.748941 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 00:56:12.752707 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 00:56:12.756008 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 00:56:12.762122 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4477 00:56:12.766241 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4478 00:56:12.769491 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 00:56:12.776074 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 00:56:12.779119 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 00:56:12.782738 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 00:56:12.785740 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 00:56:12.792408 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 00:56:12.795538 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 00:56:12.798703 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 00:56:12.805865 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 00:56:12.808856 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 00:56:12.812618 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 00:56:12.818907 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 00:56:12.822084 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 00:56:12.825391 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 00:56:12.832347 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4493 00:56:12.835690 Total UI for P1: 0, mck2ui 16
4494 00:56:12.838877 best dqsien dly found for B0: ( 0, 9, 2)
4495 00:56:12.841794 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 00:56:12.845787 Total UI for P1: 0, mck2ui 16
4497 00:56:12.848821 best dqsien dly found for B1: ( 0, 9, 6)
4498 00:56:12.851865 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4499 00:56:12.855096 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4500 00:56:12.855416
4501 00:56:12.858479 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4502 00:56:12.861710 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4503 00:56:12.864957 [Gating] SW calibration Done
4504 00:56:12.865138 ==
4505 00:56:12.868641 Dram Type= 6, Freq= 0, CH_1, rank 1
4506 00:56:12.871493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4507 00:56:12.875070 ==
4508 00:56:12.875199 RX Vref Scan: 0
4509 00:56:12.875299
4510 00:56:12.878172 RX Vref 0 -> 0, step: 1
4511 00:56:12.878300
4512 00:56:12.881581 RX Delay -230 -> 252, step: 16
4513 00:56:12.885073 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4514 00:56:12.888215 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4515 00:56:12.891581 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4516 00:56:12.898461 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4517 00:56:12.901988 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4518 00:56:12.905279 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4519 00:56:12.908355 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4520 00:56:12.911600 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4521 00:56:12.918288 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4522 00:56:12.921469 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4523 00:56:12.925500 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4524 00:56:12.928547 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4525 00:56:12.935203 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4526 00:56:12.938055 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4527 00:56:12.942040 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4528 00:56:12.944941 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4529 00:56:12.945165 ==
4530 00:56:12.948312 Dram Type= 6, Freq= 0, CH_1, rank 1
4531 00:56:12.955067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4532 00:56:12.955249 ==
4533 00:56:12.955408 DQS Delay:
4534 00:56:12.958227 DQS0 = 0, DQS1 = 0
4535 00:56:12.958445 DQM Delay:
4536 00:56:12.958612 DQM0 = 42, DQM1 = 35
4537 00:56:12.961329 DQ Delay:
4538 00:56:12.964981 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4539 00:56:12.968028 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4540 00:56:12.971321 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4541 00:56:12.974712 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4542 00:56:12.975093
4543 00:56:12.975358
4544 00:56:12.975662 ==
4545 00:56:12.978466 Dram Type= 6, Freq= 0, CH_1, rank 1
4546 00:56:12.981777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4547 00:56:12.982184 ==
4548 00:56:12.982526
4549 00:56:12.982818
4550 00:56:12.984619 TX Vref Scan disable
4551 00:56:12.988345 == TX Byte 0 ==
4552 00:56:12.991581 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4553 00:56:12.994929 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4554 00:56:12.998190 == TX Byte 1 ==
4555 00:56:13.001529 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4556 00:56:13.004535 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4557 00:56:13.005096 ==
4558 00:56:13.007915 Dram Type= 6, Freq= 0, CH_1, rank 1
4559 00:56:13.011387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4560 00:56:13.011931 ==
4561 00:56:13.014285
4562 00:56:13.014691
4563 00:56:13.015166 TX Vref Scan disable
4564 00:56:13.018402 == TX Byte 0 ==
4565 00:56:13.021537 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4566 00:56:13.028405 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4567 00:56:13.028977 == TX Byte 1 ==
4568 00:56:13.031616 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4569 00:56:13.038583 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4570 00:56:13.038977
4571 00:56:13.039280 [DATLAT]
4572 00:56:13.039561 Freq=600, CH1 RK1
4573 00:56:13.039837
4574 00:56:13.041898 DATLAT Default: 0x8
4575 00:56:13.042350 0, 0xFFFF, sum = 0
4576 00:56:13.044520 1, 0xFFFF, sum = 0
4577 00:56:13.044954 2, 0xFFFF, sum = 0
4578 00:56:13.048233 3, 0xFFFF, sum = 0
4579 00:56:13.051519 4, 0xFFFF, sum = 0
4580 00:56:13.051988 5, 0xFFFF, sum = 0
4581 00:56:13.054670 6, 0xFFFF, sum = 0
4582 00:56:13.055089 7, 0x0, sum = 1
4583 00:56:13.055404 8, 0x0, sum = 2
4584 00:56:13.057912 9, 0x0, sum = 3
4585 00:56:13.058367 10, 0x0, sum = 4
4586 00:56:13.061218 best_step = 8
4587 00:56:13.061616
4588 00:56:13.061921 ==
4589 00:56:13.064733 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 00:56:13.067806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4591 00:56:13.068101 ==
4592 00:56:13.070802 RX Vref Scan: 0
4593 00:56:13.071015
4594 00:56:13.071179 RX Vref 0 -> 0, step: 1
4595 00:56:13.071332
4596 00:56:13.074506 RX Delay -195 -> 252, step: 8
4597 00:56:13.081875 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4598 00:56:13.084969 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4599 00:56:13.088590 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4600 00:56:13.091317 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4601 00:56:13.097831 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4602 00:56:13.101490 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4603 00:56:13.104605 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4604 00:56:13.108153 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4605 00:56:13.114867 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4606 00:56:13.118051 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4607 00:56:13.121686 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4608 00:56:13.125007 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4609 00:56:13.127912 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4610 00:56:13.134461 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4611 00:56:13.138040 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4612 00:56:13.141345 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4613 00:56:13.141502 ==
4614 00:56:13.144881 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 00:56:13.151479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4616 00:56:13.151668 ==
4617 00:56:13.151815 DQS Delay:
4618 00:56:13.154367 DQS0 = 0, DQS1 = 0
4619 00:56:13.154553 DQM Delay:
4620 00:56:13.154698 DQM0 = 36, DQM1 = 29
4621 00:56:13.158014 DQ Delay:
4622 00:56:13.161488 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4623 00:56:13.164280 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4624 00:56:13.167722 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4625 00:56:13.171147 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4626 00:56:13.171694
4627 00:56:13.172035
4628 00:56:13.177993 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4629 00:56:13.181274 CH1 RK1: MR19=808, MR18=5E5E
4630 00:56:13.188029 CH1_RK1: MR19=0x808, MR18=0x5E5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4631 00:56:13.191198 [RxdqsGatingPostProcess] freq 600
4632 00:56:13.194386 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4633 00:56:13.198003 Pre-setting of DQS Precalculation
4634 00:56:13.204614 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4635 00:56:13.210920 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4636 00:56:13.217578 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4637 00:56:13.217975
4638 00:56:13.218315
4639 00:56:13.221085 [Calibration Summary] 1200 Mbps
4640 00:56:13.221526 CH 0, Rank 0
4641 00:56:13.224369 SW Impedance : PASS
4642 00:56:13.227341 DUTY Scan : NO K
4643 00:56:13.227732 ZQ Calibration : PASS
4644 00:56:13.230942 Jitter Meter : NO K
4645 00:56:13.234306 CBT Training : PASS
4646 00:56:13.234801 Write leveling : PASS
4647 00:56:13.237671 RX DQS gating : PASS
4648 00:56:13.241100 RX DQ/DQS(RDDQC) : PASS
4649 00:56:13.241534 TX DQ/DQS : PASS
4650 00:56:13.244276 RX DATLAT : PASS
4651 00:56:13.247503 RX DQ/DQS(Engine): PASS
4652 00:56:13.247897 TX OE : NO K
4653 00:56:13.248203 All Pass.
4654 00:56:13.251036
4655 00:56:13.251495 CH 0, Rank 1
4656 00:56:13.254280 SW Impedance : PASS
4657 00:56:13.254676 DUTY Scan : NO K
4658 00:56:13.257482 ZQ Calibration : PASS
4659 00:56:13.257946 Jitter Meter : NO K
4660 00:56:13.260620 CBT Training : PASS
4661 00:56:13.263943 Write leveling : PASS
4662 00:56:13.264333 RX DQS gating : PASS
4663 00:56:13.267247 RX DQ/DQS(RDDQC) : PASS
4664 00:56:13.270648 TX DQ/DQS : PASS
4665 00:56:13.271114 RX DATLAT : PASS
4666 00:56:13.273767 RX DQ/DQS(Engine): PASS
4667 00:56:13.277398 TX OE : NO K
4668 00:56:13.277786 All Pass.
4669 00:56:13.278085
4670 00:56:13.278450 CH 1, Rank 0
4671 00:56:13.280598 SW Impedance : PASS
4672 00:56:13.283727 DUTY Scan : NO K
4673 00:56:13.284117 ZQ Calibration : PASS
4674 00:56:13.287227 Jitter Meter : NO K
4675 00:56:13.290700 CBT Training : PASS
4676 00:56:13.291162 Write leveling : PASS
4677 00:56:13.293893 RX DQS gating : PASS
4678 00:56:13.297255 RX DQ/DQS(RDDQC) : PASS
4679 00:56:13.297648 TX DQ/DQS : PASS
4680 00:56:13.300433 RX DATLAT : PASS
4681 00:56:13.303627 RX DQ/DQS(Engine): PASS
4682 00:56:13.304014 TX OE : NO K
4683 00:56:13.304320 All Pass.
4684 00:56:13.306971
4685 00:56:13.307360 CH 1, Rank 1
4686 00:56:13.309998 SW Impedance : PASS
4687 00:56:13.310468 DUTY Scan : NO K
4688 00:56:13.313296 ZQ Calibration : PASS
4689 00:56:13.317030 Jitter Meter : NO K
4690 00:56:13.317420 CBT Training : PASS
4691 00:56:13.320269 Write leveling : PASS
4692 00:56:13.320738 RX DQS gating : PASS
4693 00:56:13.323392 RX DQ/DQS(RDDQC) : PASS
4694 00:56:13.327146 TX DQ/DQS : PASS
4695 00:56:13.327552 RX DATLAT : PASS
4696 00:56:13.330152 RX DQ/DQS(Engine): PASS
4697 00:56:13.333635 TX OE : NO K
4698 00:56:13.334023 All Pass.
4699 00:56:13.334456
4700 00:56:13.336822 DramC Write-DBI off
4701 00:56:13.337297 PER_BANK_REFRESH: Hybrid Mode
4702 00:56:13.340239 TX_TRACKING: ON
4703 00:56:13.349986 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4704 00:56:13.353250 [FAST_K] Save calibration result to emmc
4705 00:56:13.356306 dramc_set_vcore_voltage set vcore to 662500
4706 00:56:13.356817 Read voltage for 933, 3
4707 00:56:13.359698 Vio18 = 0
4708 00:56:13.360185 Vcore = 662500
4709 00:56:13.360492 Vdram = 0
4710 00:56:13.363355 Vddq = 0
4711 00:56:13.363743 Vmddr = 0
4712 00:56:13.369902 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4713 00:56:13.373173 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4714 00:56:13.376720 MEM_TYPE=3, freq_sel=17
4715 00:56:13.379831 sv_algorithm_assistance_LP4_1600
4716 00:56:13.382803 ============ PULL DRAM RESETB DOWN ============
4717 00:56:13.386868 ========== PULL DRAM RESETB DOWN end =========
4718 00:56:13.393115 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4719 00:56:13.396153 ===================================
4720 00:56:13.396550 LPDDR4 DRAM CONFIGURATION
4721 00:56:13.399578 ===================================
4722 00:56:13.402796 EX_ROW_EN[0] = 0x0
4723 00:56:13.406638 EX_ROW_EN[1] = 0x0
4724 00:56:13.407130 LP4Y_EN = 0x0
4725 00:56:13.409133 WORK_FSP = 0x0
4726 00:56:13.409605 WL = 0x3
4727 00:56:13.412497 RL = 0x3
4728 00:56:13.412902 BL = 0x2
4729 00:56:13.416282 RPST = 0x0
4730 00:56:13.416753 RD_PRE = 0x0
4731 00:56:13.419493 WR_PRE = 0x1
4732 00:56:13.419972 WR_PST = 0x0
4733 00:56:13.422626 DBI_WR = 0x0
4734 00:56:13.423045 DBI_RD = 0x0
4735 00:56:13.425836 OTF = 0x1
4736 00:56:13.429284 ===================================
4737 00:56:13.432495 ===================================
4738 00:56:13.432940 ANA top config
4739 00:56:13.436335 ===================================
4740 00:56:13.439087 DLL_ASYNC_EN = 0
4741 00:56:13.442270 ALL_SLAVE_EN = 1
4742 00:56:13.445850 NEW_RANK_MODE = 1
4743 00:56:13.446293 DLL_IDLE_MODE = 1
4744 00:56:13.449034 LP45_APHY_COMB_EN = 1
4745 00:56:13.452360 TX_ODT_DIS = 1
4746 00:56:13.455817 NEW_8X_MODE = 1
4747 00:56:13.459317 ===================================
4748 00:56:13.462366 ===================================
4749 00:56:13.465699 data_rate = 1866
4750 00:56:13.466187 CKR = 1
4751 00:56:13.469073 DQ_P2S_RATIO = 8
4752 00:56:13.472130 ===================================
4753 00:56:13.475576 CA_P2S_RATIO = 8
4754 00:56:13.478789 DQ_CA_OPEN = 0
4755 00:56:13.482301 DQ_SEMI_OPEN = 0
4756 00:56:13.485449 CA_SEMI_OPEN = 0
4757 00:56:13.485836 CA_FULL_RATE = 0
4758 00:56:13.489199 DQ_CKDIV4_EN = 1
4759 00:56:13.492188 CA_CKDIV4_EN = 1
4760 00:56:13.495551 CA_PREDIV_EN = 0
4761 00:56:13.498854 PH8_DLY = 0
4762 00:56:13.502283 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4763 00:56:13.502713 DQ_AAMCK_DIV = 4
4764 00:56:13.505417 CA_AAMCK_DIV = 4
4765 00:56:13.508885 CA_ADMCK_DIV = 4
4766 00:56:13.511941 DQ_TRACK_CA_EN = 0
4767 00:56:13.515226 CA_PICK = 933
4768 00:56:13.518597 CA_MCKIO = 933
4769 00:56:13.518994 MCKIO_SEMI = 0
4770 00:56:13.522044 PLL_FREQ = 3732
4771 00:56:13.525276 DQ_UI_PI_RATIO = 32
4772 00:56:13.528522 CA_UI_PI_RATIO = 0
4773 00:56:13.532007 ===================================
4774 00:56:13.535151 ===================================
4775 00:56:13.538797 memory_type:LPDDR4
4776 00:56:13.539190 GP_NUM : 10
4777 00:56:13.541647 SRAM_EN : 1
4778 00:56:13.545279 MD32_EN : 0
4779 00:56:13.548406 ===================================
4780 00:56:13.548801 [ANA_INIT] >>>>>>>>>>>>>>
4781 00:56:13.551962 <<<<<< [CONFIGURE PHASE]: ANA_TX
4782 00:56:13.555014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4783 00:56:13.558273 ===================================
4784 00:56:13.561729 data_rate = 1866,PCW = 0X8f00
4785 00:56:13.564975 ===================================
4786 00:56:13.568129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4787 00:56:13.574952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4788 00:56:13.577957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4789 00:56:13.584831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4790 00:56:13.588252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4791 00:56:13.591308 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4792 00:56:13.591804 [ANA_INIT] flow start
4793 00:56:13.594846 [ANA_INIT] PLL >>>>>>>>
4794 00:56:13.598430 [ANA_INIT] PLL <<<<<<<<
4795 00:56:13.601580 [ANA_INIT] MIDPI >>>>>>>>
4796 00:56:13.601970 [ANA_INIT] MIDPI <<<<<<<<
4797 00:56:13.604538 [ANA_INIT] DLL >>>>>>>>
4798 00:56:13.607920 [ANA_INIT] flow end
4799 00:56:13.611266 ============ LP4 DIFF to SE enter ============
4800 00:56:13.614523 ============ LP4 DIFF to SE exit ============
4801 00:56:13.617857 [ANA_INIT] <<<<<<<<<<<<<
4802 00:56:13.621241 [Flow] Enable top DCM control >>>>>
4803 00:56:13.624048 [Flow] Enable top DCM control <<<<<
4804 00:56:13.627909 Enable DLL master slave shuffle
4805 00:56:13.631254 ==============================================================
4806 00:56:13.634515 Gating Mode config
4807 00:56:13.641170 ==============================================================
4808 00:56:13.641629 Config description:
4809 00:56:13.650725 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4810 00:56:13.657904 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4811 00:56:13.660864 SELPH_MODE 0: By rank 1: By Phase
4812 00:56:13.667551 ==============================================================
4813 00:56:13.670604 GAT_TRACK_EN = 1
4814 00:56:13.674209 RX_GATING_MODE = 2
4815 00:56:13.677461 RX_GATING_TRACK_MODE = 2
4816 00:56:13.680898 SELPH_MODE = 1
4817 00:56:13.683655 PICG_EARLY_EN = 1
4818 00:56:13.687195 VALID_LAT_VALUE = 1
4819 00:56:13.690686 ==============================================================
4820 00:56:13.693862 Enter into Gating configuration >>>>
4821 00:56:13.697001 Exit from Gating configuration <<<<
4822 00:56:13.700614 Enter into DVFS_PRE_config >>>>>
4823 00:56:13.713664 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4824 00:56:13.717209 Exit from DVFS_PRE_config <<<<<
4825 00:56:13.720309 Enter into PICG configuration >>>>
4826 00:56:13.720724 Exit from PICG configuration <<<<
4827 00:56:13.723627 [RX_INPUT] configuration >>>>>
4828 00:56:13.726935 [RX_INPUT] configuration <<<<<
4829 00:56:13.733608 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4830 00:56:13.736817 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4831 00:56:13.743288 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4832 00:56:13.749994 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4833 00:56:13.756526 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4834 00:56:13.763390 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4835 00:56:13.766266 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4836 00:56:13.769708 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4837 00:56:13.776377 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4838 00:56:13.779528 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4839 00:56:13.783046 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4840 00:56:13.786638 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4841 00:56:13.789632 ===================================
4842 00:56:13.792723 LPDDR4 DRAM CONFIGURATION
4843 00:56:13.795998 ===================================
4844 00:56:13.799175 EX_ROW_EN[0] = 0x0
4845 00:56:13.799574 EX_ROW_EN[1] = 0x0
4846 00:56:13.802530 LP4Y_EN = 0x0
4847 00:56:13.802954 WORK_FSP = 0x0
4848 00:56:13.805961 WL = 0x3
4849 00:56:13.806402 RL = 0x3
4850 00:56:13.809626 BL = 0x2
4851 00:56:13.810265 RPST = 0x0
4852 00:56:13.812738 RD_PRE = 0x0
4853 00:56:13.813323 WR_PRE = 0x1
4854 00:56:13.815694 WR_PST = 0x0
4855 00:56:13.819092 DBI_WR = 0x0
4856 00:56:13.819514 DBI_RD = 0x0
4857 00:56:13.822462 OTF = 0x1
4858 00:56:13.825841 ===================================
4859 00:56:13.829226 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4860 00:56:13.832472 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4861 00:56:13.835613 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 00:56:13.838918 ===================================
4863 00:56:13.842327 LPDDR4 DRAM CONFIGURATION
4864 00:56:13.846111 ===================================
4865 00:56:13.848830 EX_ROW_EN[0] = 0x10
4866 00:56:13.849240 EX_ROW_EN[1] = 0x0
4867 00:56:13.852519 LP4Y_EN = 0x0
4868 00:56:13.852987 WORK_FSP = 0x0
4869 00:56:13.855412 WL = 0x3
4870 00:56:13.855845 RL = 0x3
4871 00:56:13.859198 BL = 0x2
4872 00:56:13.859587 RPST = 0x0
4873 00:56:13.862377 RD_PRE = 0x0
4874 00:56:13.862768 WR_PRE = 0x1
4875 00:56:13.865603 WR_PST = 0x0
4876 00:56:13.869069 DBI_WR = 0x0
4877 00:56:13.869536 DBI_RD = 0x0
4878 00:56:13.872135 OTF = 0x1
4879 00:56:13.875411 ===================================
4880 00:56:13.878810 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4881 00:56:13.884231 nWR fixed to 30
4882 00:56:13.887466 [ModeRegInit_LP4] CH0 RK0
4883 00:56:13.887857 [ModeRegInit_LP4] CH0 RK1
4884 00:56:13.890816 [ModeRegInit_LP4] CH1 RK0
4885 00:56:13.894248 [ModeRegInit_LP4] CH1 RK1
4886 00:56:13.894641 match AC timing 8
4887 00:56:13.900409 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4888 00:56:13.903796 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4889 00:56:13.907124 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4890 00:56:13.913665 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4891 00:56:13.917537 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4892 00:56:13.918012 ==
4893 00:56:13.920303 Dram Type= 6, Freq= 0, CH_0, rank 0
4894 00:56:13.923635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4895 00:56:13.924079 ==
4896 00:56:13.930590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4897 00:56:13.936761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4898 00:56:13.940134 [CA 0] Center 39 (8~70) winsize 63
4899 00:56:13.943766 [CA 1] Center 38 (8~69) winsize 62
4900 00:56:13.947216 [CA 2] Center 36 (6~67) winsize 62
4901 00:56:13.950240 [CA 3] Center 36 (6~67) winsize 62
4902 00:56:13.953646 [CA 4] Center 34 (4~65) winsize 62
4903 00:56:13.956514 [CA 5] Center 34 (4~65) winsize 62
4904 00:56:13.956910
4905 00:56:13.960807 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4906 00:56:13.961287
4907 00:56:13.963595 [CATrainingPosCal] consider 1 rank data
4908 00:56:13.966773 u2DelayCellTimex100 = 270/100 ps
4909 00:56:13.970033 CA0 delay=39 (8~70),Diff = 5 PI (31 cell)
4910 00:56:13.973091 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4911 00:56:13.976478 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4912 00:56:13.979969 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4913 00:56:13.983520 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4914 00:56:13.989917 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4915 00:56:13.990598
4916 00:56:13.992976 CA PerBit enable=1, Macro0, CA PI delay=34
4917 00:56:13.993489
4918 00:56:13.996534 [CBTSetCACLKResult] CA Dly = 34
4919 00:56:13.997014 CS Dly: 7 (0~38)
4920 00:56:13.997410 ==
4921 00:56:13.999612 Dram Type= 6, Freq= 0, CH_0, rank 1
4922 00:56:14.003173 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4923 00:56:14.006805 ==
4924 00:56:14.009960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4925 00:56:14.016554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4926 00:56:14.020128 [CA 0] Center 38 (8~69) winsize 62
4927 00:56:14.022962 [CA 1] Center 38 (8~69) winsize 62
4928 00:56:14.026622 [CA 2] Center 36 (6~67) winsize 62
4929 00:56:14.029852 [CA 3] Center 35 (5~66) winsize 62
4930 00:56:14.033109 [CA 4] Center 34 (4~64) winsize 61
4931 00:56:14.036543 [CA 5] Center 34 (4~64) winsize 61
4932 00:56:14.036931
4933 00:56:14.039459 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4934 00:56:14.039871
4935 00:56:14.043268 [CATrainingPosCal] consider 2 rank data
4936 00:56:14.046494 u2DelayCellTimex100 = 270/100 ps
4937 00:56:14.049611 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4938 00:56:14.052956 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4939 00:56:14.055986 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4940 00:56:14.062877 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4941 00:56:14.065934 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4942 00:56:14.069794 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4943 00:56:14.070322
4944 00:56:14.072746 CA PerBit enable=1, Macro0, CA PI delay=34
4945 00:56:14.073135
4946 00:56:14.076533 [CBTSetCACLKResult] CA Dly = 34
4947 00:56:14.076943 CS Dly: 7 (0~38)
4948 00:56:14.077470
4949 00:56:14.080208 ----->DramcWriteLeveling(PI) begin...
4950 00:56:14.080683 ==
4951 00:56:14.083104 Dram Type= 6, Freq= 0, CH_0, rank 0
4952 00:56:14.089422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4953 00:56:14.089898 ==
4954 00:56:14.092824 Write leveling (Byte 0): 27 => 27
4955 00:56:14.096251 Write leveling (Byte 1): 26 => 26
4956 00:56:14.096822 DramcWriteLeveling(PI) end<-----
4957 00:56:14.100102
4958 00:56:14.100487 ==
4959 00:56:14.102710 Dram Type= 6, Freq= 0, CH_0, rank 0
4960 00:56:14.106194 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4961 00:56:14.106640 ==
4962 00:56:14.109387 [Gating] SW mode calibration
4963 00:56:14.115880 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4964 00:56:14.119786 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4965 00:56:14.126170 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4966 00:56:14.129426 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4967 00:56:14.133125 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4968 00:56:14.139297 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4969 00:56:14.143110 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4970 00:56:14.146359 0 10 20 | B1->B0 | 3333 3131 | 0 0 | (0 1) (1 0)
4971 00:56:14.152934 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4972 00:56:14.155744 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4973 00:56:14.159510 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4974 00:56:14.166055 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4975 00:56:14.169101 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4976 00:56:14.172682 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4977 00:56:14.179088 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4978 00:56:14.182682 0 11 20 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 0)
4979 00:56:14.185873 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4980 00:56:14.192638 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4981 00:56:14.195742 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4982 00:56:14.199186 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4983 00:56:14.205614 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4984 00:56:14.208935 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4985 00:56:14.212529 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4986 00:56:14.219023 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4987 00:56:14.222517 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4988 00:56:14.225702 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4989 00:56:14.232190 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4990 00:56:14.235490 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4991 00:56:14.238883 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 00:56:14.242167 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4993 00:56:14.248622 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4994 00:56:14.252316 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 00:56:14.255524 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 00:56:14.262178 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 00:56:14.265494 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 00:56:14.268666 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 00:56:14.275289 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 00:56:14.278475 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 00:56:14.281998 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5002 00:56:14.288766 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5003 00:56:14.292007 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5004 00:56:14.295096 Total UI for P1: 0, mck2ui 16
5005 00:56:14.298617 best dqsien dly found for B0: ( 0, 14, 18)
5006 00:56:14.301472 Total UI for P1: 0, mck2ui 16
5007 00:56:14.304891 best dqsien dly found for B1: ( 0, 14, 18)
5008 00:56:14.308722 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5009 00:56:14.311629 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5010 00:56:14.312076
5011 00:56:14.314771 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5012 00:56:14.321751 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5013 00:56:14.322306 [Gating] SW calibration Done
5014 00:56:14.322750 ==
5015 00:56:14.324659 Dram Type= 6, Freq= 0, CH_0, rank 0
5016 00:56:14.331553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5017 00:56:14.332086 ==
5018 00:56:14.332556 RX Vref Scan: 0
5019 00:56:14.333091
5020 00:56:14.334787 RX Vref 0 -> 0, step: 1
5021 00:56:14.335234
5022 00:56:14.337959 RX Delay -80 -> 252, step: 8
5023 00:56:14.341748 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5024 00:56:14.344641 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5025 00:56:14.348153 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5026 00:56:14.354386 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5027 00:56:14.358002 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5028 00:56:14.361127 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5029 00:56:14.364230 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5030 00:56:14.368537 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5031 00:56:14.371160 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5032 00:56:14.377812 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5033 00:56:14.381019 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5034 00:56:14.384158 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5035 00:56:14.387777 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5036 00:56:14.391122 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5037 00:56:14.397744 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5038 00:56:14.400655 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5039 00:56:14.401090 ==
5040 00:56:14.404421 Dram Type= 6, Freq= 0, CH_0, rank 0
5041 00:56:14.407521 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5042 00:56:14.407954 ==
5043 00:56:14.408291 DQS Delay:
5044 00:56:14.410443 DQS0 = 0, DQS1 = 0
5045 00:56:14.410886 DQM Delay:
5046 00:56:14.414396 DQM0 = 96, DQM1 = 85
5047 00:56:14.414828 DQ Delay:
5048 00:56:14.417033 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5049 00:56:14.420900 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5050 00:56:14.424178 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5051 00:56:14.427077 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5052 00:56:14.427642
5053 00:56:14.428078
5054 00:56:14.428392 ==
5055 00:56:14.430437 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 00:56:14.437284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5057 00:56:14.437790 ==
5058 00:56:14.438186
5059 00:56:14.438591
5060 00:56:14.438893 TX Vref Scan disable
5061 00:56:14.440614 == TX Byte 0 ==
5062 00:56:14.443878 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5063 00:56:14.450372 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5064 00:56:14.450982 == TX Byte 1 ==
5065 00:56:14.453973 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5066 00:56:14.460785 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5067 00:56:14.461318 ==
5068 00:56:14.463533 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 00:56:14.466819 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5070 00:56:14.467266 ==
5071 00:56:14.467701
5072 00:56:14.468104
5073 00:56:14.470793 TX Vref Scan disable
5074 00:56:14.471331 == TX Byte 0 ==
5075 00:56:14.476972 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5076 00:56:14.480156 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5077 00:56:14.480633 == TX Byte 1 ==
5078 00:56:14.486745 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5079 00:56:14.490113 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5080 00:56:14.490635
5081 00:56:14.491066 [DATLAT]
5082 00:56:14.493390 Freq=933, CH0 RK0
5083 00:56:14.493834
5084 00:56:14.494396 DATLAT Default: 0xd
5085 00:56:14.496752 0, 0xFFFF, sum = 0
5086 00:56:14.497200 1, 0xFFFF, sum = 0
5087 00:56:14.499987 2, 0xFFFF, sum = 0
5088 00:56:14.500435 3, 0xFFFF, sum = 0
5089 00:56:14.503469 4, 0xFFFF, sum = 0
5090 00:56:14.506763 5, 0xFFFF, sum = 0
5091 00:56:14.507219 6, 0xFFFF, sum = 0
5092 00:56:14.510035 7, 0xFFFF, sum = 0
5093 00:56:14.510576 8, 0xFFFF, sum = 0
5094 00:56:14.513289 9, 0xFFFF, sum = 0
5095 00:56:14.513745 10, 0x0, sum = 1
5096 00:56:14.516286 11, 0x0, sum = 2
5097 00:56:14.516822 12, 0x0, sum = 3
5098 00:56:14.517258 13, 0x0, sum = 4
5099 00:56:14.519969 best_step = 11
5100 00:56:14.520405
5101 00:56:14.520860 ==
5102 00:56:14.523618 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 00:56:14.526649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5104 00:56:14.527089 ==
5105 00:56:14.529955 RX Vref Scan: 1
5106 00:56:14.530461
5107 00:56:14.532838 RX Vref 0 -> 0, step: 1
5108 00:56:14.533267
5109 00:56:14.533605 RX Delay -69 -> 252, step: 4
5110 00:56:14.533916
5111 00:56:14.536956 Set Vref, RX VrefLevel [Byte0]: 46
5112 00:56:14.540200 [Byte1]: 54
5113 00:56:14.544473
5114 00:56:14.545023 Final RX Vref Byte 0 = 46 to rank0
5115 00:56:14.547705 Final RX Vref Byte 1 = 54 to rank0
5116 00:56:14.551055 Final RX Vref Byte 0 = 46 to rank1
5117 00:56:14.554095 Final RX Vref Byte 1 = 54 to rank1==
5118 00:56:14.557805 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 00:56:14.564367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5120 00:56:14.564882 ==
5121 00:56:14.565227 DQS Delay:
5122 00:56:14.565537 DQS0 = 0, DQS1 = 0
5123 00:56:14.567763 DQM Delay:
5124 00:56:14.568190 DQM0 = 97, DQM1 = 88
5125 00:56:14.571202 DQ Delay:
5126 00:56:14.573862 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5127 00:56:14.577609 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =104
5128 00:56:14.580457 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5129 00:56:14.583906 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =98
5130 00:56:14.584373
5131 00:56:14.584821
5132 00:56:14.590719 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5133 00:56:14.593742 CH0 RK0: MR19=505, MR18=2323
5134 00:56:14.601128 CH0_RK0: MR19=0x505, MR18=0x2323, DQSOSC=410, MR23=63, INC=64, DEC=42
5135 00:56:14.601663
5136 00:56:14.604106 ----->DramcWriteLeveling(PI) begin...
5137 00:56:14.604678 ==
5138 00:56:14.607484 Dram Type= 6, Freq= 0, CH_0, rank 1
5139 00:56:14.610872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5140 00:56:14.611369 ==
5141 00:56:14.614003 Write leveling (Byte 0): 30 => 30
5142 00:56:14.617514 Write leveling (Byte 1): 25 => 25
5143 00:56:14.620757 DramcWriteLeveling(PI) end<-----
5144 00:56:14.621198
5145 00:56:14.621651 ==
5146 00:56:14.624266 Dram Type= 6, Freq= 0, CH_0, rank 1
5147 00:56:14.627448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5148 00:56:14.630373 ==
5149 00:56:14.630819 [Gating] SW mode calibration
5150 00:56:14.637522 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5151 00:56:14.643705 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5152 00:56:14.647208 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 00:56:14.653819 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 00:56:14.657246 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 00:56:14.660602 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 00:56:14.667078 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 00:56:14.670341 0 10 20 | B1->B0 | 2f2f 2f2f | 1 0 | (1 1) (0 0)
5158 00:56:14.673503 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 00:56:14.680508 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 00:56:14.683738 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 00:56:14.686560 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 00:56:14.693278 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 00:56:14.696706 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 00:56:14.699877 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5165 00:56:14.706573 0 11 20 | B1->B0 | 2a2a 3737 | 0 0 | (0 0) (0 0)
5166 00:56:14.710136 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 00:56:14.713422 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 00:56:14.719766 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 00:56:14.723319 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 00:56:14.726979 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 00:56:14.732922 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 00:56:14.736525 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5173 00:56:14.739672 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5174 00:56:14.746584 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5175 00:56:14.749653 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 00:56:14.752989 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 00:56:14.756477 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 00:56:14.763133 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 00:56:14.766830 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 00:56:14.769714 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 00:56:14.776874 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 00:56:14.779609 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 00:56:14.782779 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 00:56:14.790270 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 00:56:14.793038 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 00:56:14.795905 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 00:56:14.802801 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 00:56:14.806124 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 00:56:14.809673 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 00:56:14.815826 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 00:56:14.819096 Total UI for P1: 0, mck2ui 16
5192 00:56:14.822588 best dqsien dly found for B0: ( 0, 14, 22)
5193 00:56:14.825720 Total UI for P1: 0, mck2ui 16
5194 00:56:14.829146 best dqsien dly found for B1: ( 0, 14, 22)
5195 00:56:14.832247 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5196 00:56:14.836148 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5197 00:56:14.836599
5198 00:56:14.838963 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5199 00:56:14.842368 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5200 00:56:14.845969 [Gating] SW calibration Done
5201 00:56:14.846449 ==
5202 00:56:14.849522 Dram Type= 6, Freq= 0, CH_0, rank 1
5203 00:56:14.852416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5204 00:56:14.852957 ==
5205 00:56:14.855496 RX Vref Scan: 0
5206 00:56:14.856009
5207 00:56:14.856384 RX Vref 0 -> 0, step: 1
5208 00:56:14.858985
5209 00:56:14.859417 RX Delay -80 -> 252, step: 8
5210 00:56:14.865795 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5211 00:56:14.868722 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5212 00:56:14.872806 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5213 00:56:14.875935 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5214 00:56:14.878907 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5215 00:56:14.882279 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5216 00:56:14.888941 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5217 00:56:14.892362 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5218 00:56:14.895500 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5219 00:56:14.898939 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5220 00:56:14.902144 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5221 00:56:14.908946 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5222 00:56:14.911977 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5223 00:56:14.915104 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5224 00:56:14.918901 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5225 00:56:14.922158 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5226 00:56:14.922853 ==
5227 00:56:14.925479 Dram Type= 6, Freq= 0, CH_0, rank 1
5228 00:56:14.931910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5229 00:56:14.932366 ==
5230 00:56:14.932770 DQS Delay:
5231 00:56:14.935287 DQS0 = 0, DQS1 = 0
5232 00:56:14.935879 DQM Delay:
5233 00:56:14.936370 DQM0 = 97, DQM1 = 85
5234 00:56:14.938189 DQ Delay:
5235 00:56:14.942066 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5236 00:56:14.945315 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =107
5237 00:56:14.948408 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5238 00:56:14.951582 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =91
5239 00:56:14.952079
5240 00:56:14.952395
5241 00:56:14.952709 ==
5242 00:56:14.955208 Dram Type= 6, Freq= 0, CH_0, rank 1
5243 00:56:14.958831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5244 00:56:14.959227 ==
5245 00:56:14.959533
5246 00:56:14.959813
5247 00:56:14.961911 TX Vref Scan disable
5248 00:56:14.964856 == TX Byte 0 ==
5249 00:56:14.968253 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5250 00:56:14.971768 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5251 00:56:14.975404 == TX Byte 1 ==
5252 00:56:14.978541 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5253 00:56:14.981649 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5254 00:56:14.982300 ==
5255 00:56:14.984747 Dram Type= 6, Freq= 0, CH_0, rank 1
5256 00:56:14.988470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5257 00:56:14.988868 ==
5258 00:56:14.991708
5259 00:56:14.992153
5260 00:56:14.992460 TX Vref Scan disable
5261 00:56:14.995062 == TX Byte 0 ==
5262 00:56:14.998306 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5263 00:56:15.005197 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5264 00:56:15.005589 == TX Byte 1 ==
5265 00:56:15.008397 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5266 00:56:15.014835 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5267 00:56:15.015234
5268 00:56:15.015535 [DATLAT]
5269 00:56:15.015816 Freq=933, CH0 RK1
5270 00:56:15.016084
5271 00:56:15.018476 DATLAT Default: 0xb
5272 00:56:15.018901 0, 0xFFFF, sum = 0
5273 00:56:15.021449 1, 0xFFFF, sum = 0
5274 00:56:15.021928 2, 0xFFFF, sum = 0
5275 00:56:15.024967 3, 0xFFFF, sum = 0
5276 00:56:15.028339 4, 0xFFFF, sum = 0
5277 00:56:15.028736 5, 0xFFFF, sum = 0
5278 00:56:15.031816 6, 0xFFFF, sum = 0
5279 00:56:15.032217 7, 0xFFFF, sum = 0
5280 00:56:15.035006 8, 0xFFFF, sum = 0
5281 00:56:15.035405 9, 0xFFFF, sum = 0
5282 00:56:15.038491 10, 0x0, sum = 1
5283 00:56:15.038970 11, 0x0, sum = 2
5284 00:56:15.041308 12, 0x0, sum = 3
5285 00:56:15.041710 13, 0x0, sum = 4
5286 00:56:15.042018 best_step = 11
5287 00:56:15.042351
5288 00:56:15.044668 ==
5289 00:56:15.048184 Dram Type= 6, Freq= 0, CH_0, rank 1
5290 00:56:15.051875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5291 00:56:15.052315 ==
5292 00:56:15.052623 RX Vref Scan: 0
5293 00:56:15.052908
5294 00:56:15.055181 RX Vref 0 -> 0, step: 1
5295 00:56:15.055666
5296 00:56:15.057875 RX Delay -69 -> 252, step: 4
5297 00:56:15.061426 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5298 00:56:15.068115 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5299 00:56:15.071647 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5300 00:56:15.074739 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5301 00:56:15.077847 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5302 00:56:15.081150 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5303 00:56:15.084615 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5304 00:56:15.091747 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5305 00:56:15.094374 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5306 00:56:15.097814 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5307 00:56:15.101399 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5308 00:56:15.104443 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5309 00:56:15.110779 iDelay=199, Bit 12, Center 94 (3 ~ 186) 184
5310 00:56:15.114472 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5311 00:56:15.118028 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5312 00:56:15.121105 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5313 00:56:15.121496 ==
5314 00:56:15.124505 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 00:56:15.127997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5316 00:56:15.130810 ==
5317 00:56:15.131204 DQS Delay:
5318 00:56:15.131509 DQS0 = 0, DQS1 = 0
5319 00:56:15.134469 DQM Delay:
5320 00:56:15.135126 DQM0 = 97, DQM1 = 86
5321 00:56:15.137390 DQ Delay:
5322 00:56:15.137780 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5323 00:56:15.140804 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =108
5324 00:56:15.144831 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =80
5325 00:56:15.150802 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5326 00:56:15.151313
5327 00:56:15.151749
5328 00:56:15.157734 [DQSOSCAuto] RK1, (LSB)MR18= 0x3333, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5329 00:56:15.160936 CH0 RK1: MR19=505, MR18=3333
5330 00:56:15.167497 CH0_RK1: MR19=0x505, MR18=0x3333, DQSOSC=405, MR23=63, INC=66, DEC=44
5331 00:56:15.170931 [RxdqsGatingPostProcess] freq 933
5332 00:56:15.174020 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5333 00:56:15.177704 Pre-setting of DQS Precalculation
5334 00:56:15.183888 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5335 00:56:15.184310 ==
5336 00:56:15.187624 Dram Type= 6, Freq= 0, CH_1, rank 0
5337 00:56:15.190862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5338 00:56:15.191258 ==
5339 00:56:15.197393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5340 00:56:15.200374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5341 00:56:15.204954 [CA 0] Center 37 (7~68) winsize 62
5342 00:56:15.208708 [CA 1] Center 37 (6~68) winsize 63
5343 00:56:15.211522 [CA 2] Center 35 (5~65) winsize 61
5344 00:56:15.214946 [CA 3] Center 34 (3~65) winsize 63
5345 00:56:15.218068 [CA 4] Center 33 (3~64) winsize 62
5346 00:56:15.221147 [CA 5] Center 33 (3~64) winsize 62
5347 00:56:15.221659
5348 00:56:15.225016 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5349 00:56:15.225642
5350 00:56:15.228420 [CATrainingPosCal] consider 1 rank data
5351 00:56:15.231595 u2DelayCellTimex100 = 270/100 ps
5352 00:56:15.234706 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5353 00:56:15.241424 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5354 00:56:15.244863 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5355 00:56:15.247806 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5356 00:56:15.251482 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5357 00:56:15.254710 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5358 00:56:15.255144
5359 00:56:15.257975 CA PerBit enable=1, Macro0, CA PI delay=33
5360 00:56:15.258457
5361 00:56:15.261030 [CBTSetCACLKResult] CA Dly = 33
5362 00:56:15.264889 CS Dly: 5 (0~36)
5363 00:56:15.265277 ==
5364 00:56:15.267914 Dram Type= 6, Freq= 0, CH_1, rank 1
5365 00:56:15.271424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5366 00:56:15.271816 ==
5367 00:56:15.277796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5368 00:56:15.280997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5369 00:56:15.284587 [CA 0] Center 37 (6~68) winsize 63
5370 00:56:15.288061 [CA 1] Center 37 (6~68) winsize 63
5371 00:56:15.291786 [CA 2] Center 34 (4~65) winsize 62
5372 00:56:15.294737 [CA 3] Center 34 (4~64) winsize 61
5373 00:56:15.297718 [CA 4] Center 33 (3~64) winsize 62
5374 00:56:15.301461 [CA 5] Center 33 (2~64) winsize 63
5375 00:56:15.301852
5376 00:56:15.305007 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5377 00:56:15.305395
5378 00:56:15.308172 [CATrainingPosCal] consider 2 rank data
5379 00:56:15.311248 u2DelayCellTimex100 = 270/100 ps
5380 00:56:15.314656 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5381 00:56:15.318292 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5382 00:56:15.324964 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5383 00:56:15.327852 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5384 00:56:15.331402 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5385 00:56:15.335027 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5386 00:56:15.335609
5387 00:56:15.337967 CA PerBit enable=1, Macro0, CA PI delay=33
5388 00:56:15.338491
5389 00:56:15.341251 [CBTSetCACLKResult] CA Dly = 33
5390 00:56:15.341680 CS Dly: 5 (0~37)
5391 00:56:15.344970
5392 00:56:15.348329 ----->DramcWriteLeveling(PI) begin...
5393 00:56:15.348841 ==
5394 00:56:15.351082 Dram Type= 6, Freq= 0, CH_1, rank 0
5395 00:56:15.355123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5396 00:56:15.355636 ==
5397 00:56:15.358146 Write leveling (Byte 0): 27 => 27
5398 00:56:15.361701 Write leveling (Byte 1): 27 => 27
5399 00:56:15.364886 DramcWriteLeveling(PI) end<-----
5400 00:56:15.365392
5401 00:56:15.365735 ==
5402 00:56:15.367840 Dram Type= 6, Freq= 0, CH_1, rank 0
5403 00:56:15.371418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5404 00:56:15.371931 ==
5405 00:56:15.374755 [Gating] SW mode calibration
5406 00:56:15.381160 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5407 00:56:15.387839 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5408 00:56:15.391611 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 00:56:15.394436 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 00:56:15.401044 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 00:56:15.404903 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
5412 00:56:15.407553 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5413 00:56:15.414595 0 10 20 | B1->B0 | 3232 2525 | 1 0 | (1 0) (0 0)
5414 00:56:15.417835 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 00:56:15.420889 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 00:56:15.424415 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 00:56:15.431201 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 00:56:15.434784 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 00:56:15.437635 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 00:56:15.444359 0 11 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5421 00:56:15.447880 0 11 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
5422 00:56:15.451210 0 11 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5423 00:56:15.457686 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 00:56:15.460962 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 00:56:15.464646 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 00:56:15.470981 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 00:56:15.474462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 00:56:15.477695 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5429 00:56:15.483997 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5430 00:56:15.487607 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 00:56:15.490526 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 00:56:15.497304 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 00:56:15.500563 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 00:56:15.504186 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 00:56:15.510876 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 00:56:15.513613 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 00:56:15.517267 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 00:56:15.523846 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 00:56:15.527077 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 00:56:15.530324 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 00:56:15.536915 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 00:56:15.539909 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 00:56:15.543169 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 00:56:15.549825 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5445 00:56:15.553323 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5446 00:56:15.556483 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5447 00:56:15.559956 Total UI for P1: 0, mck2ui 16
5448 00:56:15.563315 best dqsien dly found for B0: ( 0, 14, 18)
5449 00:56:15.566564 Total UI for P1: 0, mck2ui 16
5450 00:56:15.569638 best dqsien dly found for B1: ( 0, 14, 20)
5451 00:56:15.573323 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5452 00:56:15.576455 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5453 00:56:15.580084
5454 00:56:15.582969 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5455 00:56:15.586657 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5456 00:56:15.589607 [Gating] SW calibration Done
5457 00:56:15.590046 ==
5458 00:56:15.593134 Dram Type= 6, Freq= 0, CH_1, rank 0
5459 00:56:15.596209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5460 00:56:15.596652 ==
5461 00:56:15.596998 RX Vref Scan: 0
5462 00:56:15.599461
5463 00:56:15.599901 RX Vref 0 -> 0, step: 1
5464 00:56:15.600248
5465 00:56:15.602812 RX Delay -80 -> 252, step: 8
5466 00:56:15.606598 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5467 00:56:15.609550 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5468 00:56:15.616117 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5469 00:56:15.619257 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5470 00:56:15.622736 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5471 00:56:15.625948 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5472 00:56:15.629654 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5473 00:56:15.632549 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5474 00:56:15.638905 iDelay=208, Bit 8, Center 67 (-32 ~ 167) 200
5475 00:56:15.642545 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5476 00:56:15.645619 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5477 00:56:15.649299 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5478 00:56:15.652319 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5479 00:56:15.659199 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5480 00:56:15.662607 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5481 00:56:15.665667 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5482 00:56:15.666107 ==
5483 00:56:15.668977 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 00:56:15.672411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5485 00:56:15.672948 ==
5486 00:56:15.675432 DQS Delay:
5487 00:56:15.675873 DQS0 = 0, DQS1 = 0
5488 00:56:15.676298 DQM Delay:
5489 00:56:15.679273 DQM0 = 94, DQM1 = 88
5490 00:56:15.679793 DQ Delay:
5491 00:56:15.682292 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5492 00:56:15.685445 DQ4 =95, DQ5 =103, DQ6 =99, DQ7 =91
5493 00:56:15.688715 DQ8 =67, DQ9 =79, DQ10 =91, DQ11 =79
5494 00:56:15.692558 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5495 00:56:15.693105
5496 00:56:15.693448
5497 00:56:15.695071 ==
5498 00:56:15.695509 Dram Type= 6, Freq= 0, CH_1, rank 0
5499 00:56:15.702266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5500 00:56:15.702711 ==
5501 00:56:15.703054
5502 00:56:15.703362
5503 00:56:15.705104 TX Vref Scan disable
5504 00:56:15.705630 == TX Byte 0 ==
5505 00:56:15.708578 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5506 00:56:15.715018 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5507 00:56:15.715458 == TX Byte 1 ==
5508 00:56:15.718904 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5509 00:56:15.725003 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5510 00:56:15.725494 ==
5511 00:56:15.728261 Dram Type= 6, Freq= 0, CH_1, rank 0
5512 00:56:15.731712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5513 00:56:15.732151 ==
5514 00:56:15.732491
5515 00:56:15.732800
5516 00:56:15.735252 TX Vref Scan disable
5517 00:56:15.738646 == TX Byte 0 ==
5518 00:56:15.741531 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5519 00:56:15.745107 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5520 00:56:15.748583 == TX Byte 1 ==
5521 00:56:15.751646 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5522 00:56:15.754992 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5523 00:56:15.755444
5524 00:56:15.755879 [DATLAT]
5525 00:56:15.758162 Freq=933, CH1 RK0
5526 00:56:15.758653
5527 00:56:15.761594 DATLAT Default: 0xd
5528 00:56:15.762041 0, 0xFFFF, sum = 0
5529 00:56:15.765046 1, 0xFFFF, sum = 0
5530 00:56:15.765498 2, 0xFFFF, sum = 0
5531 00:56:15.768204 3, 0xFFFF, sum = 0
5532 00:56:15.768656 4, 0xFFFF, sum = 0
5533 00:56:15.771320 5, 0xFFFF, sum = 0
5534 00:56:15.771773 6, 0xFFFF, sum = 0
5535 00:56:15.774497 7, 0xFFFF, sum = 0
5536 00:56:15.774953 8, 0xFFFF, sum = 0
5537 00:56:15.778378 9, 0xFFFF, sum = 0
5538 00:56:15.778833 10, 0x0, sum = 1
5539 00:56:15.781234 11, 0x0, sum = 2
5540 00:56:15.781498 12, 0x0, sum = 3
5541 00:56:15.784414 13, 0x0, sum = 4
5542 00:56:15.784495 best_step = 11
5543 00:56:15.784571
5544 00:56:15.784642 ==
5545 00:56:15.787250 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 00:56:15.790746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5547 00:56:15.794228 ==
5548 00:56:15.794321 RX Vref Scan: 1
5549 00:56:15.794397
5550 00:56:15.797532 RX Vref 0 -> 0, step: 1
5551 00:56:15.797610
5552 00:56:15.800955 RX Delay -77 -> 252, step: 4
5553 00:56:15.801034
5554 00:56:15.804031 Set Vref, RX VrefLevel [Byte0]: 53
5555 00:56:15.807654 [Byte1]: 49
5556 00:56:15.807731
5557 00:56:15.811091 Final RX Vref Byte 0 = 53 to rank0
5558 00:56:15.813937 Final RX Vref Byte 1 = 49 to rank0
5559 00:56:15.817400 Final RX Vref Byte 0 = 53 to rank1
5560 00:56:15.820508 Final RX Vref Byte 1 = 49 to rank1==
5561 00:56:15.824018 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 00:56:15.827067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5563 00:56:15.827144 ==
5564 00:56:15.830569 DQS Delay:
5565 00:56:15.830646 DQS0 = 0, DQS1 = 0
5566 00:56:15.830706 DQM Delay:
5567 00:56:15.834268 DQM0 = 93, DQM1 = 87
5568 00:56:15.834345 DQ Delay:
5569 00:56:15.837116 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5570 00:56:15.840654 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5571 00:56:15.844222 DQ8 =70, DQ9 =76, DQ10 =88, DQ11 =80
5572 00:56:15.847511 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5573 00:56:15.847588
5574 00:56:15.847649
5575 00:56:15.857175 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d3d, (MSB)MR19= 0x505, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
5576 00:56:15.860824 CH1 RK0: MR19=505, MR18=3D3D
5577 00:56:15.863684 CH1_RK0: MR19=0x505, MR18=0x3D3D, DQSOSC=402, MR23=63, INC=67, DEC=44
5578 00:56:15.863761
5579 00:56:15.866939 ----->DramcWriteLeveling(PI) begin...
5580 00:56:15.870527 ==
5581 00:56:15.870605 Dram Type= 6, Freq= 0, CH_1, rank 1
5582 00:56:15.877104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5583 00:56:15.877181 ==
5584 00:56:15.880305 Write leveling (Byte 0): 28 => 28
5585 00:56:15.883796 Write leveling (Byte 1): 27 => 27
5586 00:56:15.887197 DramcWriteLeveling(PI) end<-----
5587 00:56:15.887275
5588 00:56:15.887335 ==
5589 00:56:15.890483 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 00:56:15.893513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5591 00:56:15.893591 ==
5592 00:56:15.897093 [Gating] SW mode calibration
5593 00:56:15.903433 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5594 00:56:15.910144 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5595 00:56:15.913396 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 00:56:15.916612 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 00:56:15.923170 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 00:56:15.926386 0 10 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5599 00:56:15.929917 0 10 16 | B1->B0 | 3434 2626 | 1 1 | (1 0) (1 0)
5600 00:56:15.936712 0 10 20 | B1->B0 | 2e2e 2323 | 1 0 | (0 1) (0 0)
5601 00:56:15.939933 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 00:56:15.943292 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 00:56:15.946617 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 00:56:15.953139 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 00:56:15.956617 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 00:56:15.959634 0 11 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5607 00:56:15.966261 0 11 16 | B1->B0 | 2525 3f3f | 0 0 | (0 0) (0 0)
5608 00:56:15.970106 0 11 20 | B1->B0 | 3736 4646 | 1 0 | (1 1) (0 0)
5609 00:56:15.973451 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 00:56:15.979488 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 00:56:15.982998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 00:56:15.986313 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 00:56:15.993324 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 00:56:15.996742 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 00:56:15.999814 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5616 00:56:16.006387 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5617 00:56:16.010058 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 00:56:16.012885 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 00:56:16.019368 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 00:56:16.022895 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 00:56:16.025768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 00:56:16.032465 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 00:56:16.035814 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 00:56:16.039279 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 00:56:16.045793 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 00:56:16.049013 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 00:56:16.052316 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 00:56:16.059296 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 00:56:16.062275 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 00:56:16.065795 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 00:56:16.072725 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5632 00:56:16.075613 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5633 00:56:16.079313 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 00:56:16.082195 Total UI for P1: 0, mck2ui 16
5635 00:56:16.085938 best dqsien dly found for B0: ( 0, 14, 18)
5636 00:56:16.089072 Total UI for P1: 0, mck2ui 16
5637 00:56:16.092446 best dqsien dly found for B1: ( 0, 14, 20)
5638 00:56:16.095866 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5639 00:56:16.099085 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5640 00:56:16.099171
5641 00:56:16.105458 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5642 00:56:16.108861 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5643 00:56:16.108938 [Gating] SW calibration Done
5644 00:56:16.112351 ==
5645 00:56:16.115357 Dram Type= 6, Freq= 0, CH_1, rank 1
5646 00:56:16.118837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5647 00:56:16.118916 ==
5648 00:56:16.118976 RX Vref Scan: 0
5649 00:56:16.119031
5650 00:56:16.122090 RX Vref 0 -> 0, step: 1
5651 00:56:16.122167
5652 00:56:16.125745 RX Delay -80 -> 252, step: 8
5653 00:56:16.128751 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5654 00:56:16.132062 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5655 00:56:16.135256 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5656 00:56:16.141963 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5657 00:56:16.145784 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5658 00:56:16.148689 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5659 00:56:16.152025 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5660 00:56:16.155412 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5661 00:56:16.159112 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5662 00:56:16.165796 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5663 00:56:16.168775 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5664 00:56:16.172005 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5665 00:56:16.175415 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5666 00:56:16.178787 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5667 00:56:16.185473 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5668 00:56:16.188773 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5669 00:56:16.188851 ==
5670 00:56:16.191948 Dram Type= 6, Freq= 0, CH_1, rank 1
5671 00:56:16.195308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5672 00:56:16.195385 ==
5673 00:56:16.195445 DQS Delay:
5674 00:56:16.198779 DQS0 = 0, DQS1 = 0
5675 00:56:16.198856 DQM Delay:
5676 00:56:16.202376 DQM0 = 96, DQM1 = 87
5677 00:56:16.202453 DQ Delay:
5678 00:56:16.205396 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =91
5679 00:56:16.208706 DQ4 =99, DQ5 =107, DQ6 =107, DQ7 =91
5680 00:56:16.211893 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5681 00:56:16.215519 DQ12 =91, DQ13 =99, DQ14 =95, DQ15 =99
5682 00:56:16.215595
5683 00:56:16.215654
5684 00:56:16.215708 ==
5685 00:56:16.218733 Dram Type= 6, Freq= 0, CH_1, rank 1
5686 00:56:16.221903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5687 00:56:16.225342 ==
5688 00:56:16.225425
5689 00:56:16.225484
5690 00:56:16.225539 TX Vref Scan disable
5691 00:56:16.228587 == TX Byte 0 ==
5692 00:56:16.231685 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5693 00:56:16.235003 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5694 00:56:16.238155 == TX Byte 1 ==
5695 00:56:16.241861 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5696 00:56:16.244833 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5697 00:56:16.248174 ==
5698 00:56:16.251878 Dram Type= 6, Freq= 0, CH_1, rank 1
5699 00:56:16.254803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5700 00:56:16.254881 ==
5701 00:56:16.254941
5702 00:56:16.254995
5703 00:56:16.258181 TX Vref Scan disable
5704 00:56:16.258303 == TX Byte 0 ==
5705 00:56:16.265075 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5706 00:56:16.267871 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5707 00:56:16.267952 == TX Byte 1 ==
5708 00:56:16.274576 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5709 00:56:16.278509 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5710 00:56:16.278601
5711 00:56:16.278661 [DATLAT]
5712 00:56:16.281689 Freq=933, CH1 RK1
5713 00:56:16.281767
5714 00:56:16.281827 DATLAT Default: 0xb
5715 00:56:16.284870 0, 0xFFFF, sum = 0
5716 00:56:16.284949 1, 0xFFFF, sum = 0
5717 00:56:16.288341 2, 0xFFFF, sum = 0
5718 00:56:16.288420 3, 0xFFFF, sum = 0
5719 00:56:16.291758 4, 0xFFFF, sum = 0
5720 00:56:16.291836 5, 0xFFFF, sum = 0
5721 00:56:16.295126 6, 0xFFFF, sum = 0
5722 00:56:16.295214 7, 0xFFFF, sum = 0
5723 00:56:16.298183 8, 0xFFFF, sum = 0
5724 00:56:16.301582 9, 0xFFFF, sum = 0
5725 00:56:16.301660 10, 0x0, sum = 1
5726 00:56:16.301721 11, 0x0, sum = 2
5727 00:56:16.304562 12, 0x0, sum = 3
5728 00:56:16.304641 13, 0x0, sum = 4
5729 00:56:16.308274 best_step = 11
5730 00:56:16.308351
5731 00:56:16.308411 ==
5732 00:56:16.311158 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 00:56:16.314958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5734 00:56:16.315035 ==
5735 00:56:16.318028 RX Vref Scan: 0
5736 00:56:16.318104
5737 00:56:16.318164 RX Vref 0 -> 0, step: 1
5738 00:56:16.318245
5739 00:56:16.321105 RX Delay -69 -> 252, step: 4
5740 00:56:16.328497 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5741 00:56:16.331719 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5742 00:56:16.335064 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5743 00:56:16.338441 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5744 00:56:16.341583 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5745 00:56:16.348556 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5746 00:56:16.352050 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5747 00:56:16.355131 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5748 00:56:16.358826 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5749 00:56:16.361796 iDelay=203, Bit 9, Center 76 (-13 ~ 166) 180
5750 00:56:16.365047 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5751 00:56:16.371987 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5752 00:56:16.375073 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5753 00:56:16.378947 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5754 00:56:16.381697 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5755 00:56:16.385391 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5756 00:56:16.385489 ==
5757 00:56:16.388437 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 00:56:16.395115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5759 00:56:16.395188 ==
5760 00:56:16.395248 DQS Delay:
5761 00:56:16.398420 DQS0 = 0, DQS1 = 0
5762 00:56:16.398509 DQM Delay:
5763 00:56:16.398592 DQM0 = 95, DQM1 = 87
5764 00:56:16.401773 DQ Delay:
5765 00:56:16.405032 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =92
5766 00:56:16.408310 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5767 00:56:16.411303 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
5768 00:56:16.414554 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
5769 00:56:16.414643
5770 00:56:16.414717
5771 00:56:16.421234 [DQSOSCAuto] RK1, (LSB)MR18= 0x2727, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5772 00:56:16.424471 CH1 RK1: MR19=505, MR18=2727
5773 00:56:16.431650 CH1_RK1: MR19=0x505, MR18=0x2727, DQSOSC=409, MR23=63, INC=64, DEC=43
5774 00:56:16.434427 [RxdqsGatingPostProcess] freq 933
5775 00:56:16.437729 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5776 00:56:16.441560 Pre-setting of DQS Precalculation
5777 00:56:16.448109 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5778 00:56:16.454450 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5779 00:56:16.460914 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5780 00:56:16.461007
5781 00:56:16.461092
5782 00:56:16.464621 [Calibration Summary] 1866 Mbps
5783 00:56:16.468030 CH 0, Rank 0
5784 00:56:16.468118 SW Impedance : PASS
5785 00:56:16.471124 DUTY Scan : NO K
5786 00:56:16.471201 ZQ Calibration : PASS
5787 00:56:16.474708 Jitter Meter : NO K
5788 00:56:16.477888 CBT Training : PASS
5789 00:56:16.477965 Write leveling : PASS
5790 00:56:16.481007 RX DQS gating : PASS
5791 00:56:16.484218 RX DQ/DQS(RDDQC) : PASS
5792 00:56:16.484295 TX DQ/DQS : PASS
5793 00:56:16.487963 RX DATLAT : PASS
5794 00:56:16.491227 RX DQ/DQS(Engine): PASS
5795 00:56:16.491304 TX OE : NO K
5796 00:56:16.494410 All Pass.
5797 00:56:16.494488
5798 00:56:16.494547 CH 0, Rank 1
5799 00:56:16.497482 SW Impedance : PASS
5800 00:56:16.497559 DUTY Scan : NO K
5801 00:56:16.501173 ZQ Calibration : PASS
5802 00:56:16.504549 Jitter Meter : NO K
5803 00:56:16.504642 CBT Training : PASS
5804 00:56:16.507912 Write leveling : PASS
5805 00:56:16.510790 RX DQS gating : PASS
5806 00:56:16.510867 RX DQ/DQS(RDDQC) : PASS
5807 00:56:16.514200 TX DQ/DQS : PASS
5808 00:56:16.517545 RX DATLAT : PASS
5809 00:56:16.517621 RX DQ/DQS(Engine): PASS
5810 00:56:16.520912 TX OE : NO K
5811 00:56:16.520990 All Pass.
5812 00:56:16.521050
5813 00:56:16.524492 CH 1, Rank 0
5814 00:56:16.524568 SW Impedance : PASS
5815 00:56:16.527466 DUTY Scan : NO K
5816 00:56:16.527543 ZQ Calibration : PASS
5817 00:56:16.530622 Jitter Meter : NO K
5818 00:56:16.534251 CBT Training : PASS
5819 00:56:16.534343 Write leveling : PASS
5820 00:56:16.537560 RX DQS gating : PASS
5821 00:56:16.540835 RX DQ/DQS(RDDQC) : PASS
5822 00:56:16.540911 TX DQ/DQS : PASS
5823 00:56:16.544395 RX DATLAT : PASS
5824 00:56:16.547795 RX DQ/DQS(Engine): PASS
5825 00:56:16.547874 TX OE : NO K
5826 00:56:16.551129 All Pass.
5827 00:56:16.551206
5828 00:56:16.551266 CH 1, Rank 1
5829 00:56:16.554248 SW Impedance : PASS
5830 00:56:16.554326 DUTY Scan : NO K
5831 00:56:16.557637 ZQ Calibration : PASS
5832 00:56:16.560842 Jitter Meter : NO K
5833 00:56:16.560919 CBT Training : PASS
5834 00:56:16.564393 Write leveling : PASS
5835 00:56:16.567612 RX DQS gating : PASS
5836 00:56:16.567689 RX DQ/DQS(RDDQC) : PASS
5837 00:56:16.570734 TX DQ/DQS : PASS
5838 00:56:16.570811 RX DATLAT : PASS
5839 00:56:16.574281 RX DQ/DQS(Engine): PASS
5840 00:56:16.577328 TX OE : NO K
5841 00:56:16.577407 All Pass.
5842 00:56:16.577480
5843 00:56:16.580537 DramC Write-DBI off
5844 00:56:16.580615 PER_BANK_REFRESH: Hybrid Mode
5845 00:56:16.583998 TX_TRACKING: ON
5846 00:56:16.594174 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5847 00:56:16.597521 [FAST_K] Save calibration result to emmc
5848 00:56:16.600780 dramc_set_vcore_voltage set vcore to 650000
5849 00:56:16.600858 Read voltage for 400, 6
5850 00:56:16.604206 Vio18 = 0
5851 00:56:16.604283 Vcore = 650000
5852 00:56:16.604343 Vdram = 0
5853 00:56:16.607598 Vddq = 0
5854 00:56:16.607674 Vmddr = 0
5855 00:56:16.614134 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5856 00:56:16.617070 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5857 00:56:16.620456 MEM_TYPE=3, freq_sel=20
5858 00:56:16.623849 sv_algorithm_assistance_LP4_800
5859 00:56:16.627158 ============ PULL DRAM RESETB DOWN ============
5860 00:56:16.630450 ========== PULL DRAM RESETB DOWN end =========
5861 00:56:16.637290 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5862 00:56:16.640449 ===================================
5863 00:56:16.640526 LPDDR4 DRAM CONFIGURATION
5864 00:56:16.643651 ===================================
5865 00:56:16.647249 EX_ROW_EN[0] = 0x0
5866 00:56:16.650146 EX_ROW_EN[1] = 0x0
5867 00:56:16.650283 LP4Y_EN = 0x0
5868 00:56:16.653497 WORK_FSP = 0x0
5869 00:56:16.653574 WL = 0x2
5870 00:56:16.657266 RL = 0x2
5871 00:56:16.657343 BL = 0x2
5872 00:56:16.660382 RPST = 0x0
5873 00:56:16.660459 RD_PRE = 0x0
5874 00:56:16.663674 WR_PRE = 0x1
5875 00:56:16.663751 WR_PST = 0x0
5876 00:56:16.666744 DBI_WR = 0x0
5877 00:56:16.666821 DBI_RD = 0x0
5878 00:56:16.670493 OTF = 0x1
5879 00:56:16.673622 ===================================
5880 00:56:16.676770 ===================================
5881 00:56:16.676847 ANA top config
5882 00:56:16.680237 ===================================
5883 00:56:16.683313 DLL_ASYNC_EN = 0
5884 00:56:16.686681 ALL_SLAVE_EN = 1
5885 00:56:16.689669 NEW_RANK_MODE = 1
5886 00:56:16.689747 DLL_IDLE_MODE = 1
5887 00:56:16.693202 LP45_APHY_COMB_EN = 1
5888 00:56:16.696355 TX_ODT_DIS = 1
5889 00:56:16.699770 NEW_8X_MODE = 1
5890 00:56:16.702958 ===================================
5891 00:56:16.706676 ===================================
5892 00:56:16.709891 data_rate = 800
5893 00:56:16.709969 CKR = 1
5894 00:56:16.712878 DQ_P2S_RATIO = 4
5895 00:56:16.716628 ===================================
5896 00:56:16.719877 CA_P2S_RATIO = 4
5897 00:56:16.723183 DQ_CA_OPEN = 0
5898 00:56:16.726059 DQ_SEMI_OPEN = 1
5899 00:56:16.730115 CA_SEMI_OPEN = 1
5900 00:56:16.730192 CA_FULL_RATE = 0
5901 00:56:16.733383 DQ_CKDIV4_EN = 0
5902 00:56:16.736002 CA_CKDIV4_EN = 1
5903 00:56:16.739288 CA_PREDIV_EN = 0
5904 00:56:16.743026 PH8_DLY = 0
5905 00:56:16.746035 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5906 00:56:16.746139 DQ_AAMCK_DIV = 0
5907 00:56:16.749851 CA_AAMCK_DIV = 0
5908 00:56:16.752902 CA_ADMCK_DIV = 4
5909 00:56:16.756009 DQ_TRACK_CA_EN = 0
5910 00:56:16.759314 CA_PICK = 800
5911 00:56:16.762500 CA_MCKIO = 400
5912 00:56:16.766316 MCKIO_SEMI = 400
5913 00:56:16.766394 PLL_FREQ = 3016
5914 00:56:16.769786 DQ_UI_PI_RATIO = 32
5915 00:56:16.772890 CA_UI_PI_RATIO = 32
5916 00:56:16.775873 ===================================
5917 00:56:16.779468 ===================================
5918 00:56:16.782733 memory_type:LPDDR4
5919 00:56:16.786078 GP_NUM : 10
5920 00:56:16.786183 SRAM_EN : 1
5921 00:56:16.789521 MD32_EN : 0
5922 00:56:16.792450 ===================================
5923 00:56:16.792528 [ANA_INIT] >>>>>>>>>>>>>>
5924 00:56:16.795666 <<<<<< [CONFIGURE PHASE]: ANA_TX
5925 00:56:16.799184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5926 00:56:16.802652 ===================================
5927 00:56:16.805726 data_rate = 800,PCW = 0X7400
5928 00:56:16.808868 ===================================
5929 00:56:16.812151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5930 00:56:16.818807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5931 00:56:16.829439 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5932 00:56:16.835691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5933 00:56:16.839042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5934 00:56:16.842458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5935 00:56:16.842536 [ANA_INIT] flow start
5936 00:56:16.845943 [ANA_INIT] PLL >>>>>>>>
5937 00:56:16.848823 [ANA_INIT] PLL <<<<<<<<
5938 00:56:16.848900 [ANA_INIT] MIDPI >>>>>>>>
5939 00:56:16.852484 [ANA_INIT] MIDPI <<<<<<<<
5940 00:56:16.855429 [ANA_INIT] DLL >>>>>>>>
5941 00:56:16.855506 [ANA_INIT] flow end
5942 00:56:16.862090 ============ LP4 DIFF to SE enter ============
5943 00:56:16.865465 ============ LP4 DIFF to SE exit ============
5944 00:56:16.868799 [ANA_INIT] <<<<<<<<<<<<<
5945 00:56:16.872079 [Flow] Enable top DCM control >>>>>
5946 00:56:16.872183 [Flow] Enable top DCM control <<<<<
5947 00:56:16.875393 Enable DLL master slave shuffle
5948 00:56:16.882033 ==============================================================
5949 00:56:16.885820 Gating Mode config
5950 00:56:16.888709 ==============================================================
5951 00:56:16.891856 Config description:
5952 00:56:16.901852 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5953 00:56:16.908564 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5954 00:56:16.911869 SELPH_MODE 0: By rank 1: By Phase
5955 00:56:16.918637 ==============================================================
5956 00:56:16.921971 GAT_TRACK_EN = 0
5957 00:56:16.925234 RX_GATING_MODE = 2
5958 00:56:16.928376 RX_GATING_TRACK_MODE = 2
5959 00:56:16.932036 SELPH_MODE = 1
5960 00:56:16.932113 PICG_EARLY_EN = 1
5961 00:56:16.935155 VALID_LAT_VALUE = 1
5962 00:56:16.941516 ==============================================================
5963 00:56:16.945219 Enter into Gating configuration >>>>
5964 00:56:16.948555 Exit from Gating configuration <<<<
5965 00:56:16.951592 Enter into DVFS_PRE_config >>>>>
5966 00:56:16.961484 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5967 00:56:16.964805 Exit from DVFS_PRE_config <<<<<
5968 00:56:16.968537 Enter into PICG configuration >>>>
5969 00:56:16.971997 Exit from PICG configuration <<<<
5970 00:56:16.974933 [RX_INPUT] configuration >>>>>
5971 00:56:16.978227 [RX_INPUT] configuration <<<<<
5972 00:56:16.981555 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5973 00:56:16.988302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5974 00:56:16.994782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5975 00:56:17.001228 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5976 00:56:17.008017 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5977 00:56:17.011234 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5978 00:56:17.018156 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5979 00:56:17.021236 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5980 00:56:17.024811 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5981 00:56:17.028443 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5982 00:56:17.034698 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5983 00:56:17.037900 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5984 00:56:17.041310 ===================================
5985 00:56:17.044934 LPDDR4 DRAM CONFIGURATION
5986 00:56:17.048100 ===================================
5987 00:56:17.048168 EX_ROW_EN[0] = 0x0
5988 00:56:17.051087 EX_ROW_EN[1] = 0x0
5989 00:56:17.051180 LP4Y_EN = 0x0
5990 00:56:17.054372 WORK_FSP = 0x0
5991 00:56:17.054439 WL = 0x2
5992 00:56:17.057869 RL = 0x2
5993 00:56:17.057934 BL = 0x2
5994 00:56:17.061141 RPST = 0x0
5995 00:56:17.061234 RD_PRE = 0x0
5996 00:56:17.064401 WR_PRE = 0x1
5997 00:56:17.067586 WR_PST = 0x0
5998 00:56:17.067651 DBI_WR = 0x0
5999 00:56:17.070900 DBI_RD = 0x0
6000 00:56:17.070996 OTF = 0x1
6001 00:56:17.074266 ===================================
6002 00:56:17.077792 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6003 00:56:17.084184 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6004 00:56:17.088001 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6005 00:56:17.090810 ===================================
6006 00:56:17.094178 LPDDR4 DRAM CONFIGURATION
6007 00:56:17.097466 ===================================
6008 00:56:17.097568 EX_ROW_EN[0] = 0x10
6009 00:56:17.100794 EX_ROW_EN[1] = 0x0
6010 00:56:17.100881 LP4Y_EN = 0x0
6011 00:56:17.104052 WORK_FSP = 0x0
6012 00:56:17.104127 WL = 0x2
6013 00:56:17.107484 RL = 0x2
6014 00:56:17.107556 BL = 0x2
6015 00:56:17.111000 RPST = 0x0
6016 00:56:17.111087 RD_PRE = 0x0
6017 00:56:17.113944 WR_PRE = 0x1
6018 00:56:17.114030 WR_PST = 0x0
6019 00:56:17.117718 DBI_WR = 0x0
6020 00:56:17.120620 DBI_RD = 0x0
6021 00:56:17.120716 OTF = 0x1
6022 00:56:17.124065 ===================================
6023 00:56:17.130544 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6024 00:56:17.134674 nWR fixed to 30
6025 00:56:17.137684 [ModeRegInit_LP4] CH0 RK0
6026 00:56:17.137774 [ModeRegInit_LP4] CH0 RK1
6027 00:56:17.140664 [ModeRegInit_LP4] CH1 RK0
6028 00:56:17.144187 [ModeRegInit_LP4] CH1 RK1
6029 00:56:17.144255 match AC timing 18
6030 00:56:17.150802 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6031 00:56:17.154268 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6032 00:56:17.157690 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6033 00:56:17.163900 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6034 00:56:17.167869 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6035 00:56:17.167958 ==
6036 00:56:17.170523 Dram Type= 6, Freq= 0, CH_0, rank 0
6037 00:56:17.173985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6038 00:56:17.174071 ==
6039 00:56:17.180922 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6040 00:56:17.187359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6041 00:56:17.190726 [CA 0] Center 36 (8~64) winsize 57
6042 00:56:17.193804 [CA 1] Center 36 (8~64) winsize 57
6043 00:56:17.197610 [CA 2] Center 36 (8~64) winsize 57
6044 00:56:17.197704 [CA 3] Center 36 (8~64) winsize 57
6045 00:56:17.200449 [CA 4] Center 36 (8~64) winsize 57
6046 00:56:17.203641 [CA 5] Center 36 (8~64) winsize 57
6047 00:56:17.203709
6048 00:56:17.207235 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6049 00:56:17.210760
6050 00:56:17.214285 [CATrainingPosCal] consider 1 rank data
6051 00:56:17.214375 u2DelayCellTimex100 = 270/100 ps
6052 00:56:17.220832 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6053 00:56:17.223748 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6054 00:56:17.227395 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6055 00:56:17.230443 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6056 00:56:17.233715 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6057 00:56:17.237504 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6058 00:56:17.237601
6059 00:56:17.240293 CA PerBit enable=1, Macro0, CA PI delay=36
6060 00:56:17.240379
6061 00:56:17.243720 [CBTSetCACLKResult] CA Dly = 36
6062 00:56:17.247203 CS Dly: 1 (0~32)
6063 00:56:17.247269 ==
6064 00:56:17.250431 Dram Type= 6, Freq= 0, CH_0, rank 1
6065 00:56:17.253791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6066 00:56:17.253858 ==
6067 00:56:17.260282 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6068 00:56:17.263621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6069 00:56:17.267272 [CA 0] Center 36 (8~64) winsize 57
6070 00:56:17.270470 [CA 1] Center 36 (8~64) winsize 57
6071 00:56:17.273751 [CA 2] Center 36 (8~64) winsize 57
6072 00:56:17.276973 [CA 3] Center 36 (8~64) winsize 57
6073 00:56:17.280180 [CA 4] Center 36 (8~64) winsize 57
6074 00:56:17.283522 [CA 5] Center 36 (8~64) winsize 57
6075 00:56:17.283599
6076 00:56:17.287064 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6077 00:56:17.287141
6078 00:56:17.290045 [CATrainingPosCal] consider 2 rank data
6079 00:56:17.293326 u2DelayCellTimex100 = 270/100 ps
6080 00:56:17.296985 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6081 00:56:17.300223 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6082 00:56:17.303560 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6083 00:56:17.309978 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6084 00:56:17.313158 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6085 00:56:17.316672 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6086 00:56:17.316750
6087 00:56:17.319670 CA PerBit enable=1, Macro0, CA PI delay=36
6088 00:56:17.319746
6089 00:56:17.323005 [CBTSetCACLKResult] CA Dly = 36
6090 00:56:17.323082 CS Dly: 1 (0~32)
6091 00:56:17.323142
6092 00:56:17.326494 ----->DramcWriteLeveling(PI) begin...
6093 00:56:17.329672 ==
6094 00:56:17.333269 Dram Type= 6, Freq= 0, CH_0, rank 0
6095 00:56:17.336575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6096 00:56:17.336653 ==
6097 00:56:17.339775 Write leveling (Byte 0): 32 => 0
6098 00:56:17.342994 Write leveling (Byte 1): 32 => 0
6099 00:56:17.346169 DramcWriteLeveling(PI) end<-----
6100 00:56:17.346263
6101 00:56:17.346324 ==
6102 00:56:17.349472 Dram Type= 6, Freq= 0, CH_0, rank 0
6103 00:56:17.353181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6104 00:56:17.353258 ==
6105 00:56:17.356254 [Gating] SW mode calibration
6106 00:56:17.362848 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6107 00:56:17.369353 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6108 00:56:17.372949 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6109 00:56:17.376129 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6110 00:56:17.379415 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6111 00:56:17.385949 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6112 00:56:17.389755 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6113 00:56:17.392971 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6114 00:56:17.399446 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6115 00:56:17.403098 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6116 00:56:17.405828 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6117 00:56:17.409484 Total UI for P1: 0, mck2ui 16
6118 00:56:17.412544 best dqsien dly found for B0: ( 0, 10, 16)
6119 00:56:17.415982 Total UI for P1: 0, mck2ui 16
6120 00:56:17.419383 best dqsien dly found for B1: ( 0, 10, 16)
6121 00:56:17.422333 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6122 00:56:17.428998 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6123 00:56:17.429109
6124 00:56:17.432226 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6125 00:56:17.435810 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6126 00:56:17.438696 [Gating] SW calibration Done
6127 00:56:17.438774 ==
6128 00:56:17.442339 Dram Type= 6, Freq= 0, CH_0, rank 0
6129 00:56:17.445497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6130 00:56:17.445575 ==
6131 00:56:17.448643 RX Vref Scan: 0
6132 00:56:17.448720
6133 00:56:17.448780 RX Vref 0 -> 0, step: 1
6134 00:56:17.448836
6135 00:56:17.452008 RX Delay -410 -> 252, step: 16
6136 00:56:17.458402 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6137 00:56:17.461757 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6138 00:56:17.465603 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6139 00:56:17.468406 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6140 00:56:17.475370 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6141 00:56:17.478355 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6142 00:56:17.482036 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6143 00:56:17.485140 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6144 00:56:17.491868 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6145 00:56:17.495032 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6146 00:56:17.498564 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6147 00:56:17.501632 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6148 00:56:17.508218 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6149 00:56:17.511921 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6150 00:56:17.514805 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6151 00:56:17.518538 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6152 00:56:17.521376 ==
6153 00:56:17.524755 Dram Type= 6, Freq= 0, CH_0, rank 0
6154 00:56:17.528477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6155 00:56:17.528610 ==
6156 00:56:17.528670 DQS Delay:
6157 00:56:17.531493 DQS0 = 51, DQS1 = 59
6158 00:56:17.531570 DQM Delay:
6159 00:56:17.535322 DQM0 = 11, DQM1 = 13
6160 00:56:17.535400 DQ Delay:
6161 00:56:17.538111 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6162 00:56:17.541445 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6163 00:56:17.544899 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6164 00:56:17.548158 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6165 00:56:17.548236
6166 00:56:17.548296
6167 00:56:17.548351 ==
6168 00:56:17.551394 Dram Type= 6, Freq= 0, CH_0, rank 0
6169 00:56:17.554576 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6170 00:56:17.554668 ==
6171 00:56:17.554731
6172 00:56:17.554786
6173 00:56:17.558011 TX Vref Scan disable
6174 00:56:17.558087 == TX Byte 0 ==
6175 00:56:17.565017 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6176 00:56:17.567889 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6177 00:56:17.567989 == TX Byte 1 ==
6178 00:56:17.574751 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6179 00:56:17.578003 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6180 00:56:17.578095 ==
6181 00:56:17.581296 Dram Type= 6, Freq= 0, CH_0, rank 0
6182 00:56:17.584568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6183 00:56:17.584662 ==
6184 00:56:17.584743
6185 00:56:17.584822
6186 00:56:17.588106 TX Vref Scan disable
6187 00:56:17.591180 == TX Byte 0 ==
6188 00:56:17.594285 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6189 00:56:17.597616 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6190 00:56:17.601086 == TX Byte 1 ==
6191 00:56:17.604297 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6192 00:56:17.607176 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6193 00:56:17.607262
6194 00:56:17.610761 [DATLAT]
6195 00:56:17.610838 Freq=400, CH0 RK0
6196 00:56:17.610898
6197 00:56:17.613826 DATLAT Default: 0xf
6198 00:56:17.613902 0, 0xFFFF, sum = 0
6199 00:56:17.617624 1, 0xFFFF, sum = 0
6200 00:56:17.617702 2, 0xFFFF, sum = 0
6201 00:56:17.620443 3, 0xFFFF, sum = 0
6202 00:56:17.620521 4, 0xFFFF, sum = 0
6203 00:56:17.623822 5, 0xFFFF, sum = 0
6204 00:56:17.623899 6, 0xFFFF, sum = 0
6205 00:56:17.627402 7, 0xFFFF, sum = 0
6206 00:56:17.627508 8, 0xFFFF, sum = 0
6207 00:56:17.630830 9, 0xFFFF, sum = 0
6208 00:56:17.630908 10, 0xFFFF, sum = 0
6209 00:56:17.633794 11, 0xFFFF, sum = 0
6210 00:56:17.633872 12, 0x0, sum = 1
6211 00:56:17.637027 13, 0x0, sum = 2
6212 00:56:17.637105 14, 0x0, sum = 3
6213 00:56:17.640407 15, 0x0, sum = 4
6214 00:56:17.640485 best_step = 13
6215 00:56:17.640545
6216 00:56:17.640599 ==
6217 00:56:17.643760 Dram Type= 6, Freq= 0, CH_0, rank 0
6218 00:56:17.650458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6219 00:56:17.650571 ==
6220 00:56:17.650663 RX Vref Scan: 1
6221 00:56:17.650736
6222 00:56:17.653455 RX Vref 0 -> 0, step: 1
6223 00:56:17.653562
6224 00:56:17.656944 RX Delay -359 -> 252, step: 8
6225 00:56:17.657022
6226 00:56:17.660523 Set Vref, RX VrefLevel [Byte0]: 46
6227 00:56:17.663562 [Byte1]: 54
6228 00:56:17.663639
6229 00:56:17.666940 Final RX Vref Byte 0 = 46 to rank0
6230 00:56:17.670346 Final RX Vref Byte 1 = 54 to rank0
6231 00:56:17.673725 Final RX Vref Byte 0 = 46 to rank1
6232 00:56:17.676873 Final RX Vref Byte 1 = 54 to rank1==
6233 00:56:17.680309 Dram Type= 6, Freq= 0, CH_0, rank 0
6234 00:56:17.683780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6235 00:56:17.686803 ==
6236 00:56:17.686880 DQS Delay:
6237 00:56:17.686941 DQS0 = 52, DQS1 = 64
6238 00:56:17.690152 DQM Delay:
6239 00:56:17.690266 DQM0 = 9, DQM1 = 14
6240 00:56:17.693524 DQ Delay:
6241 00:56:17.693602 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6242 00:56:17.696555 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6243 00:56:17.700025 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =4
6244 00:56:17.703566 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6245 00:56:17.703643
6246 00:56:17.703703
6247 00:56:17.713308 [DQSOSCAuto] RK0, (LSB)MR18= 0xb5b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6248 00:56:17.716510 CH0 RK0: MR19=C0C, MR18=B5B5
6249 00:56:17.723260 CH0_RK0: MR19=0xC0C, MR18=0xB5B5, DQSOSC=387, MR23=63, INC=394, DEC=262
6250 00:56:17.723342 ==
6251 00:56:17.726491 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 00:56:17.729830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6253 00:56:17.729908 ==
6254 00:56:17.733199 [Gating] SW mode calibration
6255 00:56:17.740167 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6256 00:56:17.743171 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6257 00:56:17.749567 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6258 00:56:17.753038 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 00:56:17.756582 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6260 00:56:17.763472 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6261 00:56:17.766317 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6262 00:56:17.770322 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 00:56:17.776670 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 00:56:17.779857 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6265 00:56:17.783241 Total UI for P1: 0, mck2ui 16
6266 00:56:17.786560 best dqsien dly found for B0: ( 0, 10, 8)
6267 00:56:17.789856 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 00:56:17.793351 Total UI for P1: 0, mck2ui 16
6269 00:56:17.796413 best dqsien dly found for B1: ( 0, 10, 16)
6270 00:56:17.799636 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6271 00:56:17.803048 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6272 00:56:17.803126
6273 00:56:17.809973 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6274 00:56:17.813221 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6275 00:56:17.813298 [Gating] SW calibration Done
6276 00:56:17.816441 ==
6277 00:56:17.820054 Dram Type= 6, Freq= 0, CH_0, rank 1
6278 00:56:17.823044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6279 00:56:17.823122 ==
6280 00:56:17.823182 RX Vref Scan: 0
6281 00:56:17.823239
6282 00:56:17.826726 RX Vref 0 -> 0, step: 1
6283 00:56:17.826803
6284 00:56:17.830143 RX Delay -410 -> 252, step: 16
6285 00:56:17.833096 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6286 00:56:17.836222 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6287 00:56:17.843115 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6288 00:56:17.846168 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6289 00:56:17.849471 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6290 00:56:17.852758 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6291 00:56:17.859453 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6292 00:56:17.863092 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6293 00:56:17.866507 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6294 00:56:17.869450 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6295 00:56:17.876099 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6296 00:56:17.879346 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6297 00:56:17.882813 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6298 00:56:17.889253 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6299 00:56:17.892732 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6300 00:56:17.896082 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6301 00:56:17.896159 ==
6302 00:56:17.899169 Dram Type= 6, Freq= 0, CH_0, rank 1
6303 00:56:17.902760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6304 00:56:17.906003 ==
6305 00:56:17.906080 DQS Delay:
6306 00:56:17.906140 DQS0 = 43, DQS1 = 59
6307 00:56:17.909692 DQM Delay:
6308 00:56:17.909769 DQM0 = 7, DQM1 = 14
6309 00:56:17.912608 DQ Delay:
6310 00:56:17.912684 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6311 00:56:17.915839 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6312 00:56:17.919084 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6313 00:56:17.922559 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6314 00:56:17.922660
6315 00:56:17.922748
6316 00:56:17.922808 ==
6317 00:56:17.925923 Dram Type= 6, Freq= 0, CH_0, rank 1
6318 00:56:17.932684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6319 00:56:17.932761 ==
6320 00:56:17.932821
6321 00:56:17.932875
6322 00:56:17.932927 TX Vref Scan disable
6323 00:56:17.936127 == TX Byte 0 ==
6324 00:56:17.939849 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6325 00:56:17.942527 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6326 00:56:17.945741 == TX Byte 1 ==
6327 00:56:17.949084 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6328 00:56:17.952397 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6329 00:56:17.952475 ==
6330 00:56:17.955784 Dram Type= 6, Freq= 0, CH_0, rank 1
6331 00:56:17.962539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6332 00:56:17.962617 ==
6333 00:56:17.962676
6334 00:56:17.962731
6335 00:56:17.962784 TX Vref Scan disable
6336 00:56:17.965847 == TX Byte 0 ==
6337 00:56:17.969006 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6338 00:56:17.972640 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6339 00:56:17.975856 == TX Byte 1 ==
6340 00:56:17.979075 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6341 00:56:17.982156 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6342 00:56:17.982238
6343 00:56:17.985500 [DATLAT]
6344 00:56:17.985576 Freq=400, CH0 RK1
6345 00:56:17.985636
6346 00:56:17.988951 DATLAT Default: 0xd
6347 00:56:17.989028 0, 0xFFFF, sum = 0
6348 00:56:17.992374 1, 0xFFFF, sum = 0
6349 00:56:17.992452 2, 0xFFFF, sum = 0
6350 00:56:17.996088 3, 0xFFFF, sum = 0
6351 00:56:17.996196 4, 0xFFFF, sum = 0
6352 00:56:17.998861 5, 0xFFFF, sum = 0
6353 00:56:17.998941 6, 0xFFFF, sum = 0
6354 00:56:18.002557 7, 0xFFFF, sum = 0
6355 00:56:18.002636 8, 0xFFFF, sum = 0
6356 00:56:18.005370 9, 0xFFFF, sum = 0
6357 00:56:18.008688 10, 0xFFFF, sum = 0
6358 00:56:18.008766 11, 0xFFFF, sum = 0
6359 00:56:18.012359 12, 0x0, sum = 1
6360 00:56:18.012437 13, 0x0, sum = 2
6361 00:56:18.012498 14, 0x0, sum = 3
6362 00:56:18.015582 15, 0x0, sum = 4
6363 00:56:18.015659 best_step = 13
6364 00:56:18.015717
6365 00:56:18.018919 ==
6366 00:56:18.019012 Dram Type= 6, Freq= 0, CH_0, rank 1
6367 00:56:18.025745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6368 00:56:18.025822 ==
6369 00:56:18.025881 RX Vref Scan: 0
6370 00:56:18.025936
6371 00:56:18.029020 RX Vref 0 -> 0, step: 1
6372 00:56:18.029095
6373 00:56:18.031883 RX Delay -359 -> 252, step: 8
6374 00:56:18.038977 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6375 00:56:18.042104 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6376 00:56:18.045366 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6377 00:56:18.048572 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6378 00:56:18.055355 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6379 00:56:18.059117 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6380 00:56:18.062118 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6381 00:56:18.065607 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6382 00:56:18.071943 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6383 00:56:18.075416 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6384 00:56:18.078532 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6385 00:56:18.085238 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6386 00:56:18.088537 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6387 00:56:18.092034 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6388 00:56:18.095391 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6389 00:56:18.101786 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6390 00:56:18.101922 ==
6391 00:56:18.105455 Dram Type= 6, Freq= 0, CH_0, rank 1
6392 00:56:18.108672 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6393 00:56:18.108750 ==
6394 00:56:18.108809 DQS Delay:
6395 00:56:18.111957 DQS0 = 52, DQS1 = 64
6396 00:56:18.112034 DQM Delay:
6397 00:56:18.115079 DQM0 = 9, DQM1 = 14
6398 00:56:18.115155 DQ Delay:
6399 00:56:18.118370 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6400 00:56:18.121697 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6401 00:56:18.124990 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6402 00:56:18.128620 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6403 00:56:18.128718
6404 00:56:18.128781
6405 00:56:18.135176 [DQSOSCAuto] RK1, (LSB)MR18= 0xc9c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6406 00:56:18.138168 CH0 RK1: MR19=C0C, MR18=C9C9
6407 00:56:18.145093 CH0_RK1: MR19=0xC0C, MR18=0xC9C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6408 00:56:18.148200 [RxdqsGatingPostProcess] freq 400
6409 00:56:18.154904 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6410 00:56:18.154999 Pre-setting of DQS Precalculation
6411 00:56:18.161742 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6412 00:56:18.161819 ==
6413 00:56:18.165159 Dram Type= 6, Freq= 0, CH_1, rank 0
6414 00:56:18.168482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6415 00:56:18.168559 ==
6416 00:56:18.174677 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6417 00:56:18.181401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6418 00:56:18.184700 [CA 0] Center 36 (8~64) winsize 57
6419 00:56:18.188082 [CA 1] Center 36 (8~64) winsize 57
6420 00:56:18.191203 [CA 2] Center 36 (8~64) winsize 57
6421 00:56:18.194829 [CA 3] Center 36 (8~64) winsize 57
6422 00:56:18.194905 [CA 4] Center 36 (8~64) winsize 57
6423 00:56:18.198379 [CA 5] Center 36 (8~64) winsize 57
6424 00:56:18.198456
6425 00:56:18.204656 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6426 00:56:18.204733
6427 00:56:18.208078 [CATrainingPosCal] consider 1 rank data
6428 00:56:18.211537 u2DelayCellTimex100 = 270/100 ps
6429 00:56:18.214931 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6430 00:56:18.218184 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6431 00:56:18.221418 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6432 00:56:18.224668 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6433 00:56:18.228032 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6434 00:56:18.231327 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6435 00:56:18.231404
6436 00:56:18.234744 CA PerBit enable=1, Macro0, CA PI delay=36
6437 00:56:18.234820
6438 00:56:18.237872 [CBTSetCACLKResult] CA Dly = 36
6439 00:56:18.241057 CS Dly: 1 (0~32)
6440 00:56:18.241138 ==
6441 00:56:18.244693 Dram Type= 6, Freq= 0, CH_1, rank 1
6442 00:56:18.248076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6443 00:56:18.248153 ==
6444 00:56:18.254637 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6445 00:56:18.257876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6446 00:56:18.261279 [CA 0] Center 36 (8~64) winsize 57
6447 00:56:18.264327 [CA 1] Center 36 (8~64) winsize 57
6448 00:56:18.267596 [CA 2] Center 36 (8~64) winsize 57
6449 00:56:18.271039 [CA 3] Center 36 (8~64) winsize 57
6450 00:56:18.274354 [CA 4] Center 36 (8~64) winsize 57
6451 00:56:18.277525 [CA 5] Center 36 (8~64) winsize 57
6452 00:56:18.277602
6453 00:56:18.281191 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6454 00:56:18.281294
6455 00:56:18.284397 [CATrainingPosCal] consider 2 rank data
6456 00:56:18.287627 u2DelayCellTimex100 = 270/100 ps
6457 00:56:18.291319 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6458 00:56:18.294177 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6459 00:56:18.300851 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6460 00:56:18.303944 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6461 00:56:18.307545 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6462 00:56:18.310777 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6463 00:56:18.310855
6464 00:56:18.314049 CA PerBit enable=1, Macro0, CA PI delay=36
6465 00:56:18.314126
6466 00:56:18.317362 [CBTSetCACLKResult] CA Dly = 36
6467 00:56:18.317442 CS Dly: 1 (0~32)
6468 00:56:18.317501
6469 00:56:18.320861 ----->DramcWriteLeveling(PI) begin...
6470 00:56:18.324095 ==
6471 00:56:18.327210 Dram Type= 6, Freq= 0, CH_1, rank 0
6472 00:56:18.330660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6473 00:56:18.330738 ==
6474 00:56:18.334110 Write leveling (Byte 0): 32 => 0
6475 00:56:18.337019 Write leveling (Byte 1): 32 => 0
6476 00:56:18.340777 DramcWriteLeveling(PI) end<-----
6477 00:56:18.340854
6478 00:56:18.340912 ==
6479 00:56:18.343930 Dram Type= 6, Freq= 0, CH_1, rank 0
6480 00:56:18.347156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6481 00:56:18.347233 ==
6482 00:56:18.350696 [Gating] SW mode calibration
6483 00:56:18.357099 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 00:56:18.363746 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6485 00:56:18.367042 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 00:56:18.370046 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 00:56:18.376994 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 00:56:18.379767 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6489 00:56:18.383280 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 00:56:18.390217 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 00:56:18.393562 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 00:56:18.396682 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6493 00:56:18.403217 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 00:56:18.403295 Total UI for P1: 0, mck2ui 16
6495 00:56:18.406480 best dqsien dly found for B0: ( 0, 10, 16)
6496 00:56:18.410031 Total UI for P1: 0, mck2ui 16
6497 00:56:18.412916 best dqsien dly found for B1: ( 0, 10, 16)
6498 00:56:18.420076 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6499 00:56:18.422895 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6500 00:56:18.422972
6501 00:56:18.426433 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6502 00:56:18.429662 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6503 00:56:18.432722 [Gating] SW calibration Done
6504 00:56:18.432799 ==
6505 00:56:18.435957 Dram Type= 6, Freq= 0, CH_1, rank 0
6506 00:56:18.439732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6507 00:56:18.439809 ==
6508 00:56:18.443089 RX Vref Scan: 0
6509 00:56:18.443165
6510 00:56:18.443225 RX Vref 0 -> 0, step: 1
6511 00:56:18.443280
6512 00:56:18.446002 RX Delay -410 -> 252, step: 16
6513 00:56:18.452638 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6514 00:56:18.455946 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6515 00:56:18.459403 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6516 00:56:18.462558 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6517 00:56:18.469569 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6518 00:56:18.472484 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6519 00:56:18.476077 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6520 00:56:18.479416 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6521 00:56:18.485990 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6522 00:56:18.489092 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6523 00:56:18.492506 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6524 00:56:18.495765 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6525 00:56:18.502480 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6526 00:56:18.505548 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6527 00:56:18.508872 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6528 00:56:18.515364 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6529 00:56:18.515442 ==
6530 00:56:18.518712 Dram Type= 6, Freq= 0, CH_1, rank 0
6531 00:56:18.522395 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6532 00:56:18.522473 ==
6533 00:56:18.522533 DQS Delay:
6534 00:56:18.525450 DQS0 = 43, DQS1 = 59
6535 00:56:18.525527 DQM Delay:
6536 00:56:18.528854 DQM0 = 6, DQM1 = 16
6537 00:56:18.528930 DQ Delay:
6538 00:56:18.532229 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6539 00:56:18.535490 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6540 00:56:18.539138 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6541 00:56:18.542077 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6542 00:56:18.542177
6543 00:56:18.542257
6544 00:56:18.542313 ==
6545 00:56:18.545327 Dram Type= 6, Freq= 0, CH_1, rank 0
6546 00:56:18.548697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6547 00:56:18.548776 ==
6548 00:56:18.548836
6549 00:56:18.548891
6550 00:56:18.551977 TX Vref Scan disable
6551 00:56:18.552054 == TX Byte 0 ==
6552 00:56:18.558723 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6553 00:56:18.561778 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6554 00:56:18.561854 == TX Byte 1 ==
6555 00:56:18.568792 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6556 00:56:18.571858 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6557 00:56:18.571935 ==
6558 00:56:18.575181 Dram Type= 6, Freq= 0, CH_1, rank 0
6559 00:56:18.578769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6560 00:56:18.578846 ==
6561 00:56:18.578906
6562 00:56:18.581480
6563 00:56:18.581556 TX Vref Scan disable
6564 00:56:18.584814 == TX Byte 0 ==
6565 00:56:18.588257 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6566 00:56:18.591504 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6567 00:56:18.594829 == TX Byte 1 ==
6568 00:56:18.598159 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6569 00:56:18.601374 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6570 00:56:18.601450
6571 00:56:18.604721 [DATLAT]
6572 00:56:18.604797 Freq=400, CH1 RK0
6573 00:56:18.604857
6574 00:56:18.608138 DATLAT Default: 0xf
6575 00:56:18.608232 0, 0xFFFF, sum = 0
6576 00:56:18.611207 1, 0xFFFF, sum = 0
6577 00:56:18.611286 2, 0xFFFF, sum = 0
6578 00:56:18.614800 3, 0xFFFF, sum = 0
6579 00:56:18.614879 4, 0xFFFF, sum = 0
6580 00:56:18.618197 5, 0xFFFF, sum = 0
6581 00:56:18.618323 6, 0xFFFF, sum = 0
6582 00:56:18.621437 7, 0xFFFF, sum = 0
6583 00:56:18.621515 8, 0xFFFF, sum = 0
6584 00:56:18.624437 9, 0xFFFF, sum = 0
6585 00:56:18.624515 10, 0xFFFF, sum = 0
6586 00:56:18.627813 11, 0xFFFF, sum = 0
6587 00:56:18.627892 12, 0x0, sum = 1
6588 00:56:18.631243 13, 0x0, sum = 2
6589 00:56:18.631347 14, 0x0, sum = 3
6590 00:56:18.634690 15, 0x0, sum = 4
6591 00:56:18.634768 best_step = 13
6592 00:56:18.634828
6593 00:56:18.634883 ==
6594 00:56:18.637979 Dram Type= 6, Freq= 0, CH_1, rank 0
6595 00:56:18.644634 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6596 00:56:18.644711 ==
6597 00:56:18.644772 RX Vref Scan: 1
6598 00:56:18.644826
6599 00:56:18.647757 RX Vref 0 -> 0, step: 1
6600 00:56:18.647832
6601 00:56:18.651772 RX Delay -359 -> 252, step: 8
6602 00:56:18.651849
6603 00:56:18.654672 Set Vref, RX VrefLevel [Byte0]: 53
6604 00:56:18.657955 [Byte1]: 49
6605 00:56:18.658032
6606 00:56:18.660940 Final RX Vref Byte 0 = 53 to rank0
6607 00:56:18.664269 Final RX Vref Byte 1 = 49 to rank0
6608 00:56:18.667597 Final RX Vref Byte 0 = 53 to rank1
6609 00:56:18.670985 Final RX Vref Byte 1 = 49 to rank1==
6610 00:56:18.674414 Dram Type= 6, Freq= 0, CH_1, rank 0
6611 00:56:18.677645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6612 00:56:18.681052 ==
6613 00:56:18.681153 DQS Delay:
6614 00:56:18.681239 DQS0 = 48, DQS1 = 64
6615 00:56:18.684563 DQM Delay:
6616 00:56:18.684639 DQM0 = 8, DQM1 = 16
6617 00:56:18.687409 DQ Delay:
6618 00:56:18.687485 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6619 00:56:18.690683 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6620 00:56:18.694405 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6621 00:56:18.697315 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =28
6622 00:56:18.697392
6623 00:56:18.697451
6624 00:56:18.707263 [DQSOSCAuto] RK0, (LSB)MR18= 0xe3e3, (MSB)MR19= 0xc0c, tDQSOscB0 = 381 ps tDQSOscB1 = 381 ps
6625 00:56:18.710647 CH1 RK0: MR19=C0C, MR18=E3E3
6626 00:56:18.717407 CH1_RK0: MR19=0xC0C, MR18=0xE3E3, DQSOSC=381, MR23=63, INC=406, DEC=271
6627 00:56:18.717484 ==
6628 00:56:18.720659 Dram Type= 6, Freq= 0, CH_1, rank 1
6629 00:56:18.724057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6630 00:56:18.724134 ==
6631 00:56:18.727421 [Gating] SW mode calibration
6632 00:56:18.733620 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6633 00:56:18.737249 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6634 00:56:18.743890 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6635 00:56:18.747237 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6636 00:56:18.750219 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6637 00:56:18.757056 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6638 00:56:18.760322 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6639 00:56:18.763578 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6640 00:56:18.770358 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6641 00:56:18.773660 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6642 00:56:18.776952 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6643 00:56:18.780401 Total UI for P1: 0, mck2ui 16
6644 00:56:18.783496 best dqsien dly found for B0: ( 0, 10, 16)
6645 00:56:18.786753 Total UI for P1: 0, mck2ui 16
6646 00:56:18.790117 best dqsien dly found for B1: ( 0, 10, 16)
6647 00:56:18.793202 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6648 00:56:18.796945 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6649 00:56:18.800183
6650 00:56:18.803157 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6651 00:56:18.806377 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6652 00:56:18.809566 [Gating] SW calibration Done
6653 00:56:18.809643 ==
6654 00:56:18.813345 Dram Type= 6, Freq= 0, CH_1, rank 1
6655 00:56:18.816670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6656 00:56:18.816747 ==
6657 00:56:18.819511 RX Vref Scan: 0
6658 00:56:18.819587
6659 00:56:18.819647 RX Vref 0 -> 0, step: 1
6660 00:56:18.819703
6661 00:56:18.822866 RX Delay -410 -> 252, step: 16
6662 00:56:18.826481 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6663 00:56:18.832912 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6664 00:56:18.836496 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6665 00:56:18.839661 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6666 00:56:18.842950 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6667 00:56:18.849443 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6668 00:56:18.853327 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6669 00:56:18.856108 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6670 00:56:18.859285 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6671 00:56:18.866067 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6672 00:56:18.869360 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6673 00:56:18.873138 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6674 00:56:18.879559 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6675 00:56:18.882766 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6676 00:56:18.886087 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6677 00:56:18.889495 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6678 00:56:18.889572 ==
6679 00:56:18.892357 Dram Type= 6, Freq= 0, CH_1, rank 1
6680 00:56:18.899371 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6681 00:56:18.899448 ==
6682 00:56:18.899508 DQS Delay:
6683 00:56:18.902107 DQS0 = 43, DQS1 = 59
6684 00:56:18.902183 DQM Delay:
6685 00:56:18.905804 DQM0 = 9, DQM1 = 18
6686 00:56:18.905880 DQ Delay:
6687 00:56:18.908979 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6688 00:56:18.912081 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6689 00:56:18.912159 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6690 00:56:18.919209 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6691 00:56:18.919286
6692 00:56:18.919345
6693 00:56:18.919400 ==
6694 00:56:18.922512 Dram Type= 6, Freq= 0, CH_1, rank 1
6695 00:56:18.925307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6696 00:56:18.925384 ==
6697 00:56:18.925443
6698 00:56:18.925498
6699 00:56:18.928573 TX Vref Scan disable
6700 00:56:18.928649 == TX Byte 0 ==
6701 00:56:18.935208 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6702 00:56:18.938708 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6703 00:56:18.938785 == TX Byte 1 ==
6704 00:56:18.942023 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6705 00:56:18.948908 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6706 00:56:18.948984 ==
6707 00:56:18.951611 Dram Type= 6, Freq= 0, CH_1, rank 1
6708 00:56:18.955026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6709 00:56:18.955104 ==
6710 00:56:18.955163
6711 00:56:18.955219
6712 00:56:18.958532 TX Vref Scan disable
6713 00:56:18.958609 == TX Byte 0 ==
6714 00:56:18.964998 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6715 00:56:18.968598 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6716 00:56:18.968676 == TX Byte 1 ==
6717 00:56:18.974822 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6718 00:56:18.978183 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6719 00:56:18.978297
6720 00:56:18.978357 [DATLAT]
6721 00:56:18.981924 Freq=400, CH1 RK1
6722 00:56:18.982005
6723 00:56:18.982064 DATLAT Default: 0xd
6724 00:56:18.985119 0, 0xFFFF, sum = 0
6725 00:56:18.985197 1, 0xFFFF, sum = 0
6726 00:56:18.988365 2, 0xFFFF, sum = 0
6727 00:56:18.988442 3, 0xFFFF, sum = 0
6728 00:56:18.991496 4, 0xFFFF, sum = 0
6729 00:56:18.991575 5, 0xFFFF, sum = 0
6730 00:56:18.994673 6, 0xFFFF, sum = 0
6731 00:56:18.994750 7, 0xFFFF, sum = 0
6732 00:56:18.998532 8, 0xFFFF, sum = 0
6733 00:56:18.998610 9, 0xFFFF, sum = 0
6734 00:56:19.001350 10, 0xFFFF, sum = 0
6735 00:56:19.005157 11, 0xFFFF, sum = 0
6736 00:56:19.005235 12, 0x0, sum = 1
6737 00:56:19.005296 13, 0x0, sum = 2
6738 00:56:19.008309 14, 0x0, sum = 3
6739 00:56:19.008386 15, 0x0, sum = 4
6740 00:56:19.011300 best_step = 13
6741 00:56:19.011376
6742 00:56:19.011435 ==
6743 00:56:19.014766 Dram Type= 6, Freq= 0, CH_1, rank 1
6744 00:56:19.018283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6745 00:56:19.018376 ==
6746 00:56:19.021474 RX Vref Scan: 0
6747 00:56:19.021552
6748 00:56:19.021610 RX Vref 0 -> 0, step: 1
6749 00:56:19.021665
6750 00:56:19.024774 RX Delay -359 -> 252, step: 8
6751 00:56:19.032738 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6752 00:56:19.036400 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6753 00:56:19.040257 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6754 00:56:19.043103 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6755 00:56:19.049336 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6756 00:56:19.052667 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6757 00:56:19.056296 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6758 00:56:19.059162 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6759 00:56:19.066479 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6760 00:56:19.069491 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6761 00:56:19.072693 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6762 00:56:19.079190 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6763 00:56:19.082588 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6764 00:56:19.085647 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6765 00:56:19.089253 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6766 00:56:19.095672 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6767 00:56:19.095750 ==
6768 00:56:19.098950 Dram Type= 6, Freq= 0, CH_1, rank 1
6769 00:56:19.102246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6770 00:56:19.102324 ==
6771 00:56:19.102385 DQS Delay:
6772 00:56:19.106368 DQS0 = 48, DQS1 = 64
6773 00:56:19.106445 DQM Delay:
6774 00:56:19.109134 DQM0 = 9, DQM1 = 15
6775 00:56:19.109210 DQ Delay:
6776 00:56:19.112697 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6777 00:56:19.115689 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6778 00:56:19.118915 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6779 00:56:19.122656 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6780 00:56:19.122733
6781 00:56:19.122792
6782 00:56:19.129096 [DQSOSCAuto] RK1, (LSB)MR18= 0xb3b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6783 00:56:19.132808 CH1 RK1: MR19=C0C, MR18=B3B3
6784 00:56:19.139226 CH1_RK1: MR19=0xC0C, MR18=0xB3B3, DQSOSC=387, MR23=63, INC=394, DEC=262
6785 00:56:19.142230 [RxdqsGatingPostProcess] freq 400
6786 00:56:19.148619 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6787 00:56:19.148697 Pre-setting of DQS Precalculation
6788 00:56:19.155787 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6789 00:56:19.162590 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6790 00:56:19.168429 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6791 00:56:19.168507
6792 00:56:19.168567
6793 00:56:19.172128 [Calibration Summary] 800 Mbps
6794 00:56:19.175209 CH 0, Rank 0
6795 00:56:19.175285 SW Impedance : PASS
6796 00:56:19.178474 DUTY Scan : NO K
6797 00:56:19.181913 ZQ Calibration : PASS
6798 00:56:19.181991 Jitter Meter : NO K
6799 00:56:19.185570 CBT Training : PASS
6800 00:56:19.188397 Write leveling : PASS
6801 00:56:19.188475 RX DQS gating : PASS
6802 00:56:19.192263 RX DQ/DQS(RDDQC) : PASS
6803 00:56:19.192366 TX DQ/DQS : PASS
6804 00:56:19.195491 RX DATLAT : PASS
6805 00:56:19.198340 RX DQ/DQS(Engine): PASS
6806 00:56:19.198417 TX OE : NO K
6807 00:56:19.201932 All Pass.
6808 00:56:19.202008
6809 00:56:19.202068 CH 0, Rank 1
6810 00:56:19.205197 SW Impedance : PASS
6811 00:56:19.205275 DUTY Scan : NO K
6812 00:56:19.208238 ZQ Calibration : PASS
6813 00:56:19.211836 Jitter Meter : NO K
6814 00:56:19.211972 CBT Training : PASS
6815 00:56:19.214909 Write leveling : NO K
6816 00:56:19.218524 RX DQS gating : PASS
6817 00:56:19.218651 RX DQ/DQS(RDDQC) : PASS
6818 00:56:19.221572 TX DQ/DQS : PASS
6819 00:56:19.224892 RX DATLAT : PASS
6820 00:56:19.225009 RX DQ/DQS(Engine): PASS
6821 00:56:19.228283 TX OE : NO K
6822 00:56:19.228406 All Pass.
6823 00:56:19.228469
6824 00:56:19.231284 CH 1, Rank 0
6825 00:56:19.231467 SW Impedance : PASS
6826 00:56:19.235053 DUTY Scan : NO K
6827 00:56:19.238429 ZQ Calibration : PASS
6828 00:56:19.238506 Jitter Meter : NO K
6829 00:56:19.241561 CBT Training : PASS
6830 00:56:19.244814 Write leveling : PASS
6831 00:56:19.244891 RX DQS gating : PASS
6832 00:56:19.247868 RX DQ/DQS(RDDQC) : PASS
6833 00:56:19.251510 TX DQ/DQS : PASS
6834 00:56:19.251587 RX DATLAT : PASS
6835 00:56:19.255068 RX DQ/DQS(Engine): PASS
6836 00:56:19.255145 TX OE : NO K
6837 00:56:19.258265 All Pass.
6838 00:56:19.258358
6839 00:56:19.258419 CH 1, Rank 1
6840 00:56:19.261513 SW Impedance : PASS
6841 00:56:19.261591 DUTY Scan : NO K
6842 00:56:19.264657 ZQ Calibration : PASS
6843 00:56:19.268144 Jitter Meter : NO K
6844 00:56:19.268222 CBT Training : PASS
6845 00:56:19.271557 Write leveling : NO K
6846 00:56:19.274512 RX DQS gating : PASS
6847 00:56:19.274589 RX DQ/DQS(RDDQC) : PASS
6848 00:56:19.277875 TX DQ/DQS : PASS
6849 00:56:19.281378 RX DATLAT : PASS
6850 00:56:19.281455 RX DQ/DQS(Engine): PASS
6851 00:56:19.284518 TX OE : NO K
6852 00:56:19.284595 All Pass.
6853 00:56:19.284654
6854 00:56:19.287638 DramC Write-DBI off
6855 00:56:19.291304 PER_BANK_REFRESH: Hybrid Mode
6856 00:56:19.291381 TX_TRACKING: ON
6857 00:56:19.300935 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6858 00:56:19.304059 [FAST_K] Save calibration result to emmc
6859 00:56:19.307358 dramc_set_vcore_voltage set vcore to 725000
6860 00:56:19.310929 Read voltage for 1600, 0
6861 00:56:19.311006 Vio18 = 0
6862 00:56:19.311066 Vcore = 725000
6863 00:56:19.314004 Vdram = 0
6864 00:56:19.314080 Vddq = 0
6865 00:56:19.314139 Vmddr = 0
6866 00:56:19.320582 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6867 00:56:19.324349 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6868 00:56:19.327591 MEM_TYPE=3, freq_sel=13
6869 00:56:19.330722 sv_algorithm_assistance_LP4_3733
6870 00:56:19.333946 ============ PULL DRAM RESETB DOWN ============
6871 00:56:19.340766 ========== PULL DRAM RESETB DOWN end =========
6872 00:56:19.343823 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6873 00:56:19.347427 ===================================
6874 00:56:19.350564 LPDDR4 DRAM CONFIGURATION
6875 00:56:19.353914 ===================================
6876 00:56:19.353991 EX_ROW_EN[0] = 0x0
6877 00:56:19.357717 EX_ROW_EN[1] = 0x0
6878 00:56:19.357794 LP4Y_EN = 0x0
6879 00:56:19.360604 WORK_FSP = 0x1
6880 00:56:19.360681 WL = 0x5
6881 00:56:19.363801 RL = 0x5
6882 00:56:19.363879 BL = 0x2
6883 00:56:19.367057 RPST = 0x0
6884 00:56:19.367178 RD_PRE = 0x0
6885 00:56:19.370719 WR_PRE = 0x1
6886 00:56:19.370796 WR_PST = 0x1
6887 00:56:19.374060 DBI_WR = 0x0
6888 00:56:19.377557 DBI_RD = 0x0
6889 00:56:19.377634 OTF = 0x1
6890 00:56:19.380926 ===================================
6891 00:56:19.383771 ===================================
6892 00:56:19.383848 ANA top config
6893 00:56:19.387074 ===================================
6894 00:56:19.390364 DLL_ASYNC_EN = 0
6895 00:56:19.394180 ALL_SLAVE_EN = 0
6896 00:56:19.396981 NEW_RANK_MODE = 1
6897 00:56:19.400330 DLL_IDLE_MODE = 1
6898 00:56:19.400407 LP45_APHY_COMB_EN = 1
6899 00:56:19.403755 TX_ODT_DIS = 0
6900 00:56:19.406957 NEW_8X_MODE = 1
6901 00:56:19.410244 ===================================
6902 00:56:19.413681 ===================================
6903 00:56:19.416928 data_rate = 3200
6904 00:56:19.420147 CKR = 1
6905 00:56:19.420225 DQ_P2S_RATIO = 8
6906 00:56:19.423599 ===================================
6907 00:56:19.427186 CA_P2S_RATIO = 8
6908 00:56:19.430287 DQ_CA_OPEN = 0
6909 00:56:19.433690 DQ_SEMI_OPEN = 0
6910 00:56:19.437073 CA_SEMI_OPEN = 0
6911 00:56:19.440586 CA_FULL_RATE = 0
6912 00:56:19.440664 DQ_CKDIV4_EN = 0
6913 00:56:19.443804 CA_CKDIV4_EN = 0
6914 00:56:19.446758 CA_PREDIV_EN = 0
6915 00:56:19.449904 PH8_DLY = 12
6916 00:56:19.453575 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6917 00:56:19.456740 DQ_AAMCK_DIV = 4
6918 00:56:19.456820 CA_AAMCK_DIV = 4
6919 00:56:19.460433 CA_ADMCK_DIV = 4
6920 00:56:19.463889 DQ_TRACK_CA_EN = 0
6921 00:56:19.466722 CA_PICK = 1600
6922 00:56:19.470468 CA_MCKIO = 1600
6923 00:56:19.473219 MCKIO_SEMI = 0
6924 00:56:19.476730 PLL_FREQ = 3068
6925 00:56:19.476808 DQ_UI_PI_RATIO = 32
6926 00:56:19.480009 CA_UI_PI_RATIO = 0
6927 00:56:19.483289 ===================================
6928 00:56:19.486599 ===================================
6929 00:56:19.489988 memory_type:LPDDR4
6930 00:56:19.493362 GP_NUM : 10
6931 00:56:19.493440 SRAM_EN : 1
6932 00:56:19.496603 MD32_EN : 0
6933 00:56:19.499905 ===================================
6934 00:56:19.503475 [ANA_INIT] >>>>>>>>>>>>>>
6935 00:56:19.506361 <<<<<< [CONFIGURE PHASE]: ANA_TX
6936 00:56:19.509542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6937 00:56:19.512814 ===================================
6938 00:56:19.512891 data_rate = 3200,PCW = 0X7600
6939 00:56:19.516666 ===================================
6940 00:56:19.519467 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6941 00:56:19.526028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6942 00:56:19.532967 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6943 00:56:19.535863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6944 00:56:19.539440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6945 00:56:19.542853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6946 00:56:19.546124 [ANA_INIT] flow start
6947 00:56:19.546201 [ANA_INIT] PLL >>>>>>>>
6948 00:56:19.549213 [ANA_INIT] PLL <<<<<<<<
6949 00:56:19.552444 [ANA_INIT] MIDPI >>>>>>>>
6950 00:56:19.555708 [ANA_INIT] MIDPI <<<<<<<<
6951 00:56:19.555785 [ANA_INIT] DLL >>>>>>>>
6952 00:56:19.559147 [ANA_INIT] DLL <<<<<<<<
6953 00:56:19.562648 [ANA_INIT] flow end
6954 00:56:19.565598 ============ LP4 DIFF to SE enter ============
6955 00:56:19.569258 ============ LP4 DIFF to SE exit ============
6956 00:56:19.572491 [ANA_INIT] <<<<<<<<<<<<<
6957 00:56:19.575942 [Flow] Enable top DCM control >>>>>
6958 00:56:19.579261 [Flow] Enable top DCM control <<<<<
6959 00:56:19.582291 Enable DLL master slave shuffle
6960 00:56:19.585627 ==============================================================
6961 00:56:19.588981 Gating Mode config
6962 00:56:19.595694 ==============================================================
6963 00:56:19.595773 Config description:
6964 00:56:19.605484 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6965 00:56:19.612471 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6966 00:56:19.615748 SELPH_MODE 0: By rank 1: By Phase
6967 00:56:19.622116 ==============================================================
6968 00:56:19.625263 GAT_TRACK_EN = 1
6969 00:56:19.628623 RX_GATING_MODE = 2
6970 00:56:19.632072 RX_GATING_TRACK_MODE = 2
6971 00:56:19.635372 SELPH_MODE = 1
6972 00:56:19.638805 PICG_EARLY_EN = 1
6973 00:56:19.642013 VALID_LAT_VALUE = 1
6974 00:56:19.645568 ==============================================================
6975 00:56:19.648569 Enter into Gating configuration >>>>
6976 00:56:19.651524 Exit from Gating configuration <<<<
6977 00:56:19.655426 Enter into DVFS_PRE_config >>>>>
6978 00:56:19.668128 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6979 00:56:19.671651 Exit from DVFS_PRE_config <<<<<
6980 00:56:19.671728 Enter into PICG configuration >>>>
6981 00:56:19.674752 Exit from PICG configuration <<<<
6982 00:56:19.678196 [RX_INPUT] configuration >>>>>
6983 00:56:19.681909 [RX_INPUT] configuration <<<<<
6984 00:56:19.688381 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6985 00:56:19.691307 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6986 00:56:19.698177 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6987 00:56:19.704541 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6988 00:56:19.711361 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6989 00:56:19.717996 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6990 00:56:19.721638 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6991 00:56:19.724316 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6992 00:56:19.727942 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6993 00:56:19.734335 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6994 00:56:19.738026 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6995 00:56:19.741414 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6996 00:56:19.744457 ===================================
6997 00:56:19.747644 LPDDR4 DRAM CONFIGURATION
6998 00:56:19.750901 ===================================
6999 00:56:19.754070 EX_ROW_EN[0] = 0x0
7000 00:56:19.754180 EX_ROW_EN[1] = 0x0
7001 00:56:19.757466 LP4Y_EN = 0x0
7002 00:56:19.757534 WORK_FSP = 0x1
7003 00:56:19.760959 WL = 0x5
7004 00:56:19.761048 RL = 0x5
7005 00:56:19.764562 BL = 0x2
7006 00:56:19.764647 RPST = 0x0
7007 00:56:19.767740 RD_PRE = 0x0
7008 00:56:19.767830 WR_PRE = 0x1
7009 00:56:19.770372 WR_PST = 0x1
7010 00:56:19.770494 DBI_WR = 0x0
7011 00:56:19.773949 DBI_RD = 0x0
7012 00:56:19.777384 OTF = 0x1
7013 00:56:19.780911 ===================================
7014 00:56:19.783776 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7015 00:56:19.786897 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7016 00:56:19.790521 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7017 00:56:19.793875 ===================================
7018 00:56:19.796947 LPDDR4 DRAM CONFIGURATION
7019 00:56:19.800259 ===================================
7020 00:56:19.803827 EX_ROW_EN[0] = 0x10
7021 00:56:19.803905 EX_ROW_EN[1] = 0x0
7022 00:56:19.807183 LP4Y_EN = 0x0
7023 00:56:19.807260 WORK_FSP = 0x1
7024 00:56:19.810333 WL = 0x5
7025 00:56:19.810410 RL = 0x5
7026 00:56:19.813409 BL = 0x2
7027 00:56:19.813486 RPST = 0x0
7028 00:56:19.817006 RD_PRE = 0x0
7029 00:56:19.817083 WR_PRE = 0x1
7030 00:56:19.820375 WR_PST = 0x1
7031 00:56:19.820477 DBI_WR = 0x0
7032 00:56:19.823287 DBI_RD = 0x0
7033 00:56:19.826733 OTF = 0x1
7034 00:56:19.830031 ===================================
7035 00:56:19.833155 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7036 00:56:19.833256 ==
7037 00:56:19.836683 Dram Type= 6, Freq= 0, CH_0, rank 0
7038 00:56:19.843783 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7039 00:56:19.843904 ==
7040 00:56:19.843993 [Duty_Offset_Calibration]
7041 00:56:19.846921 B0:0 B1:2 CA:1
7042 00:56:19.847000
7043 00:56:19.849792 [DutyScan_Calibration_Flow] k_type=0
7044 00:56:19.859458
7045 00:56:19.859534 ==CLK 0==
7046 00:56:19.862888 Final CLK duty delay cell = 0
7047 00:56:19.866319 [0] MAX Duty = 5156%(X100), DQS PI = 22
7048 00:56:19.869739 [0] MIN Duty = 4938%(X100), DQS PI = 50
7049 00:56:19.873102 [0] AVG Duty = 5047%(X100)
7050 00:56:19.873176
7051 00:56:19.876246 CH0 CLK Duty spec in!! Max-Min= 218%
7052 00:56:19.879667 [DutyScan_Calibration_Flow] ====Done====
7053 00:56:19.879750
7054 00:56:19.883038 [DutyScan_Calibration_Flow] k_type=1
7055 00:56:19.899938
7056 00:56:19.900024 ==DQS 0 ==
7057 00:56:19.903073 Final DQS duty delay cell = 0
7058 00:56:19.906584 [0] MAX Duty = 5156%(X100), DQS PI = 34
7059 00:56:19.909398 [0] MIN Duty = 5000%(X100), DQS PI = 8
7060 00:56:19.909467 [0] AVG Duty = 5078%(X100)
7061 00:56:19.913178
7062 00:56:19.913265 ==DQS 1 ==
7063 00:56:19.916433 Final DQS duty delay cell = 0
7064 00:56:19.919326 [0] MAX Duty = 5031%(X100), DQS PI = 46
7065 00:56:19.923212 [0] MIN Duty = 4844%(X100), DQS PI = 18
7066 00:56:19.926172 [0] AVG Duty = 4937%(X100)
7067 00:56:19.926273
7068 00:56:19.929558 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7069 00:56:19.929636
7070 00:56:19.932841 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7071 00:56:19.936354 [DutyScan_Calibration_Flow] ====Done====
7072 00:56:19.936432
7073 00:56:19.939245 [DutyScan_Calibration_Flow] k_type=3
7074 00:56:19.956825
7075 00:56:19.956903 ==DQM 0 ==
7076 00:56:19.960205 Final DQM duty delay cell = 0
7077 00:56:19.963427 [0] MAX Duty = 5187%(X100), DQS PI = 24
7078 00:56:19.966725 [0] MIN Duty = 4876%(X100), DQS PI = 56
7079 00:56:19.970231 [0] AVG Duty = 5031%(X100)
7080 00:56:19.970321
7081 00:56:19.970380 ==DQM 1 ==
7082 00:56:19.973345 Final DQM duty delay cell = 0
7083 00:56:19.976738 [0] MAX Duty = 5031%(X100), DQS PI = 50
7084 00:56:19.980165 [0] MIN Duty = 4782%(X100), DQS PI = 16
7085 00:56:19.983330 [0] AVG Duty = 4906%(X100)
7086 00:56:19.983407
7087 00:56:19.986627 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7088 00:56:19.986704
7089 00:56:19.989732 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7090 00:56:19.993627 [DutyScan_Calibration_Flow] ====Done====
7091 00:56:19.993725
7092 00:56:19.996254 [DutyScan_Calibration_Flow] k_type=2
7093 00:56:20.013376
7094 00:56:20.013455 ==DQ 0 ==
7095 00:56:20.016725 Final DQ duty delay cell = 0
7096 00:56:20.020048 [0] MAX Duty = 5218%(X100), DQS PI = 18
7097 00:56:20.023245 [0] MIN Duty = 4938%(X100), DQS PI = 56
7098 00:56:20.023324 [0] AVG Duty = 5078%(X100)
7099 00:56:20.026442
7100 00:56:20.026566 ==DQ 1 ==
7101 00:56:20.030080 Final DQ duty delay cell = -4
7102 00:56:20.033499 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7103 00:56:20.036433 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7104 00:56:20.039715 [-4] AVG Duty = 4953%(X100)
7105 00:56:20.039792
7106 00:56:20.043097 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7107 00:56:20.043174
7108 00:56:20.046597 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7109 00:56:20.050237 [DutyScan_Calibration_Flow] ====Done====
7110 00:56:20.050328 ==
7111 00:56:20.053099 Dram Type= 6, Freq= 0, CH_1, rank 0
7112 00:56:20.056269 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7113 00:56:20.056348 ==
7114 00:56:20.060019 [Duty_Offset_Calibration]
7115 00:56:20.060096 B0:0 B1:4 CA:-5
7116 00:56:20.060156
7117 00:56:20.063308 [DutyScan_Calibration_Flow] k_type=0
7118 00:56:20.073600
7119 00:56:20.073677 ==CLK 0==
7120 00:56:20.077103 Final CLK duty delay cell = 0
7121 00:56:20.080846 [0] MAX Duty = 5156%(X100), DQS PI = 22
7122 00:56:20.083819 [0] MIN Duty = 4906%(X100), DQS PI = 50
7123 00:56:20.087225 [0] AVG Duty = 5031%(X100)
7124 00:56:20.087302
7125 00:56:20.090523 CH1 CLK Duty spec in!! Max-Min= 250%
7126 00:56:20.093853 [DutyScan_Calibration_Flow] ====Done====
7127 00:56:20.093930
7128 00:56:20.096789 [DutyScan_Calibration_Flow] k_type=1
7129 00:56:20.112901
7130 00:56:20.112977 ==DQS 0 ==
7131 00:56:20.115791 Final DQS duty delay cell = 0
7132 00:56:20.119142 [0] MAX Duty = 5156%(X100), DQS PI = 18
7133 00:56:20.122481 [0] MIN Duty = 4876%(X100), DQS PI = 42
7134 00:56:20.126009 [0] AVG Duty = 5016%(X100)
7135 00:56:20.126086
7136 00:56:20.126146 ==DQS 1 ==
7137 00:56:20.128979 Final DQS duty delay cell = -4
7138 00:56:20.132657 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7139 00:56:20.136143 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7140 00:56:20.139693 [-4] AVG Duty = 4922%(X100)
7141 00:56:20.139769
7142 00:56:20.142697 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7143 00:56:20.142775
7144 00:56:20.146081 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7145 00:56:20.149516 [DutyScan_Calibration_Flow] ====Done====
7146 00:56:20.149593
7147 00:56:20.152279 [DutyScan_Calibration_Flow] k_type=3
7148 00:56:20.168638
7149 00:56:20.168731 ==DQM 0 ==
7150 00:56:20.171670 Final DQM duty delay cell = -4
7151 00:56:20.174962 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7152 00:56:20.178709 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7153 00:56:20.182136 [-4] AVG Duty = 4922%(X100)
7154 00:56:20.182250
7155 00:56:20.182342 ==DQM 1 ==
7156 00:56:20.184756 Final DQM duty delay cell = -4
7157 00:56:20.188238 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7158 00:56:20.191501 [-4] MIN Duty = 4876%(X100), DQS PI = 38
7159 00:56:20.194917 [-4] AVG Duty = 4969%(X100)
7160 00:56:20.194995
7161 00:56:20.198364 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7162 00:56:20.198441
7163 00:56:20.201716 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7164 00:56:20.204922 [DutyScan_Calibration_Flow] ====Done====
7165 00:56:20.204999
7166 00:56:20.208035 [DutyScan_Calibration_Flow] k_type=2
7167 00:56:20.225826
7168 00:56:20.225902 ==DQ 0 ==
7169 00:56:20.229219 Final DQ duty delay cell = 0
7170 00:56:20.232552 [0] MAX Duty = 5093%(X100), DQS PI = 4
7171 00:56:20.236116 [0] MIN Duty = 4938%(X100), DQS PI = 46
7172 00:56:20.236193 [0] AVG Duty = 5015%(X100)
7173 00:56:20.236253
7174 00:56:20.239425 ==DQ 1 ==
7175 00:56:20.242651 Final DQ duty delay cell = 0
7176 00:56:20.246112 [0] MAX Duty = 5031%(X100), DQS PI = 4
7177 00:56:20.249292 [0] MIN Duty = 4875%(X100), DQS PI = 26
7178 00:56:20.249370 [0] AVG Duty = 4953%(X100)
7179 00:56:20.249429
7180 00:56:20.252533 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7181 00:56:20.255870
7182 00:56:20.258886 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7183 00:56:20.262233 [DutyScan_Calibration_Flow] ====Done====
7184 00:56:20.265821 nWR fixed to 30
7185 00:56:20.265913 [ModeRegInit_LP4] CH0 RK0
7186 00:56:20.268992 [ModeRegInit_LP4] CH0 RK1
7187 00:56:20.272089 [ModeRegInit_LP4] CH1 RK0
7188 00:56:20.275660 [ModeRegInit_LP4] CH1 RK1
7189 00:56:20.275738 match AC timing 4
7190 00:56:20.278880 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7191 00:56:20.285647 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7192 00:56:20.289039 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7193 00:56:20.295746 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7194 00:56:20.298943 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7195 00:56:20.299021 [MiockJmeterHQA]
7196 00:56:20.299081
7197 00:56:20.302125 [DramcMiockJmeter] u1RxGatingPI = 0
7198 00:56:20.305634 0 : 4257, 4029
7199 00:56:20.305730 4 : 4257, 4029
7200 00:56:20.308715 8 : 4252, 4027
7201 00:56:20.308793 12 : 4253, 4026
7202 00:56:20.308854 16 : 4363, 4137
7203 00:56:20.312104 20 : 4253, 4026
7204 00:56:20.312181 24 : 4252, 4027
7205 00:56:20.315438 28 : 4252, 4027
7206 00:56:20.315516 32 : 4255, 4029
7207 00:56:20.318582 36 : 4252, 4027
7208 00:56:20.318661 40 : 4253, 4026
7209 00:56:20.318722 44 : 4365, 4140
7210 00:56:20.322104 48 : 4252, 4027
7211 00:56:20.322183 52 : 4253, 4027
7212 00:56:20.325347 56 : 4251, 4027
7213 00:56:20.325426 60 : 4360, 4137
7214 00:56:20.328732 64 : 4250, 4026
7215 00:56:20.328810 68 : 4361, 4138
7216 00:56:20.332175 72 : 4250, 4026
7217 00:56:20.332253 76 : 4250, 4027
7218 00:56:20.332314 80 : 4252, 4027
7219 00:56:20.335516 84 : 4253, 4029
7220 00:56:20.335634 88 : 4250, 4027
7221 00:56:20.339043 92 : 4253, 4026
7222 00:56:20.339121 96 : 4363, 4140
7223 00:56:20.341973 100 : 4250, 1979
7224 00:56:20.342051 104 : 4364, 0
7225 00:56:20.342112 108 : 4252, 0
7226 00:56:20.345289 112 : 4250, 0
7227 00:56:20.345367 116 : 4252, 0
7228 00:56:20.348633 120 : 4361, 0
7229 00:56:20.348711 124 : 4361, 0
7230 00:56:20.348772 128 : 4363, 0
7231 00:56:20.351680 132 : 4252, 0
7232 00:56:20.351757 136 : 4250, 0
7233 00:56:20.355107 140 : 4253, 0
7234 00:56:20.355185 144 : 4251, 0
7235 00:56:20.355246 148 : 4250, 0
7236 00:56:20.358596 152 : 4253, 0
7237 00:56:20.358688 156 : 4250, 0
7238 00:56:20.361979 160 : 4252, 0
7239 00:56:20.362057 164 : 4250, 0
7240 00:56:20.362118 168 : 4252, 0
7241 00:56:20.365327 172 : 4250, 0
7242 00:56:20.365405 176 : 4361, 0
7243 00:56:20.365466 180 : 4360, 0
7244 00:56:20.368607 184 : 4249, 0
7245 00:56:20.368685 188 : 4250, 0
7246 00:56:20.371826 192 : 4250, 0
7247 00:56:20.371904 196 : 4360, 0
7248 00:56:20.371965 200 : 4250, 0
7249 00:56:20.374848 204 : 4250, 0
7250 00:56:20.374926 208 : 4252, 0
7251 00:56:20.378176 212 : 4250, 0
7252 00:56:20.378298 216 : 4361, 0
7253 00:56:20.378360 220 : 4250, 378
7254 00:56:20.381604 224 : 4250, 3953
7255 00:56:20.381682 228 : 4364, 4140
7256 00:56:20.385039 232 : 4360, 4137
7257 00:56:20.385117 236 : 4248, 4024
7258 00:56:20.387996 240 : 4363, 4140
7259 00:56:20.388074 244 : 4361, 4137
7260 00:56:20.391405 248 : 4250, 4027
7261 00:56:20.391484 252 : 4250, 4026
7262 00:56:20.394615 256 : 4253, 4029
7263 00:56:20.394695 260 : 4250, 4027
7264 00:56:20.398091 264 : 4250, 4027
7265 00:56:20.398170 268 : 4250, 4026
7266 00:56:20.401136 272 : 4253, 4029
7267 00:56:20.401214 276 : 4250, 4027
7268 00:56:20.404737 280 : 4361, 4138
7269 00:56:20.404816 284 : 4363, 4140
7270 00:56:20.404877 288 : 4250, 4026
7271 00:56:20.407921 292 : 4363, 4140
7272 00:56:20.407999 296 : 4360, 4137
7273 00:56:20.411304 300 : 4252, 4030
7274 00:56:20.411382 304 : 4253, 4026
7275 00:56:20.414536 308 : 4252, 4029
7276 00:56:20.414614 312 : 4249, 4027
7277 00:56:20.417672 316 : 4250, 4027
7278 00:56:20.417750 320 : 4250, 4026
7279 00:56:20.421092 324 : 4253, 4029
7280 00:56:20.421170 328 : 4250, 4027
7281 00:56:20.424655 332 : 4361, 4138
7282 00:56:20.424734 336 : 4360, 4095
7283 00:56:20.428101 340 : 4250, 2324
7284 00:56:20.428179 344 : 4363, 3
7285 00:56:20.428240
7286 00:56:20.431153 MIOCK jitter meter ch=0
7287 00:56:20.431230
7288 00:56:20.434490 1T = (344-100) = 244 dly cells
7289 00:56:20.437604 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 266/100 ps
7290 00:56:20.437681 ==
7291 00:56:20.440761 Dram Type= 6, Freq= 0, CH_0, rank 0
7292 00:56:20.447985 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7293 00:56:20.448063 ==
7294 00:56:20.450986 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7295 00:56:20.457682 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7296 00:56:20.461104 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7297 00:56:20.467230 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7298 00:56:20.474379 [CA 0] Center 43 (13~73) winsize 61
7299 00:56:20.477840 [CA 1] Center 42 (12~73) winsize 62
7300 00:56:20.480987 [CA 2] Center 39 (9~69) winsize 61
7301 00:56:20.484260 [CA 3] Center 38 (9~68) winsize 60
7302 00:56:20.487646 [CA 4] Center 37 (7~67) winsize 61
7303 00:56:20.491098 [CA 5] Center 36 (6~66) winsize 61
7304 00:56:20.491175
7305 00:56:20.494288 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7306 00:56:20.494366
7307 00:56:20.497684 [CATrainingPosCal] consider 1 rank data
7308 00:56:20.500818 u2DelayCellTimex100 = 266/100 ps
7309 00:56:20.504050 CA0 delay=43 (13~73),Diff = 7 PI (25 cell)
7310 00:56:20.510643 CA1 delay=42 (12~73),Diff = 6 PI (22 cell)
7311 00:56:20.514112 CA2 delay=39 (9~69),Diff = 3 PI (11 cell)
7312 00:56:20.517524 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7313 00:56:20.520772 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7314 00:56:20.524011 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7315 00:56:20.524088
7316 00:56:20.527437 CA PerBit enable=1, Macro0, CA PI delay=36
7317 00:56:20.527515
7318 00:56:20.530922 [CBTSetCACLKResult] CA Dly = 36
7319 00:56:20.534392 CS Dly: 10 (0~41)
7320 00:56:20.537215 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7321 00:56:20.540836 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7322 00:56:20.540913 ==
7323 00:56:20.544116 Dram Type= 6, Freq= 0, CH_0, rank 1
7324 00:56:20.550375 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7325 00:56:20.550453 ==
7326 00:56:20.553994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7327 00:56:20.557286 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7328 00:56:20.563897 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7329 00:56:20.570145 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7330 00:56:20.577176 [CA 0] Center 42 (12~73) winsize 62
7331 00:56:20.580963 [CA 1] Center 42 (12~73) winsize 62
7332 00:56:20.583805 [CA 2] Center 38 (9~68) winsize 60
7333 00:56:20.587290 [CA 3] Center 37 (8~67) winsize 60
7334 00:56:20.590277 [CA 4] Center 36 (6~66) winsize 61
7335 00:56:20.593834 [CA 5] Center 36 (6~66) winsize 61
7336 00:56:20.593943
7337 00:56:20.597263 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7338 00:56:20.597373
7339 00:56:20.600658 [CATrainingPosCal] consider 2 rank data
7340 00:56:20.603859 u2DelayCellTimex100 = 266/100 ps
7341 00:56:20.606921 CA0 delay=43 (13~73),Diff = 7 PI (25 cell)
7342 00:56:20.613788 CA1 delay=42 (12~73),Diff = 6 PI (22 cell)
7343 00:56:20.617113 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7344 00:56:20.620356 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7345 00:56:20.623781 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7346 00:56:20.627393 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7347 00:56:20.627470
7348 00:56:20.630717 CA PerBit enable=1, Macro0, CA PI delay=36
7349 00:56:20.630832
7350 00:56:20.633570 [CBTSetCACLKResult] CA Dly = 36
7351 00:56:20.637176 CS Dly: 10 (0~42)
7352 00:56:20.640177 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7353 00:56:20.643944 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7354 00:56:20.644021
7355 00:56:20.647100 ----->DramcWriteLeveling(PI) begin...
7356 00:56:20.647178 ==
7357 00:56:20.650220 Dram Type= 6, Freq= 0, CH_0, rank 0
7358 00:56:20.653406 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7359 00:56:20.656722 ==
7360 00:56:20.656798 Write leveling (Byte 0): 29 => 29
7361 00:56:20.660067 Write leveling (Byte 1): 26 => 26
7362 00:56:20.663149 DramcWriteLeveling(PI) end<-----
7363 00:56:20.663226
7364 00:56:20.663285 ==
7365 00:56:20.666854 Dram Type= 6, Freq= 0, CH_0, rank 0
7366 00:56:20.673283 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7367 00:56:20.673360 ==
7368 00:56:20.676979 [Gating] SW mode calibration
7369 00:56:20.683173 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7370 00:56:20.686501 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7371 00:56:20.693377 0 12 0 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
7372 00:56:20.697022 0 12 4 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
7373 00:56:20.699810 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7374 00:56:20.706891 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7375 00:56:20.709881 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7376 00:56:20.713169 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7377 00:56:20.720027 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7378 00:56:20.722822 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7379 00:56:20.726409 0 13 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7380 00:56:20.733111 0 13 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
7381 00:56:20.736535 0 13 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7382 00:56:20.739752 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7383 00:56:20.742888 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7384 00:56:20.749700 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7385 00:56:20.753100 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7386 00:56:20.756287 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7387 00:56:20.762666 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7388 00:56:20.766025 0 14 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7389 00:56:20.769487 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7390 00:56:20.776083 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7391 00:56:20.779502 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7392 00:56:20.783037 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7393 00:56:20.789551 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7394 00:56:20.792693 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7395 00:56:20.796034 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7396 00:56:20.802657 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7397 00:56:20.805624 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7398 00:56:20.809105 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7399 00:56:20.815844 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7400 00:56:20.819056 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7401 00:56:20.822429 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7402 00:56:20.828928 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7403 00:56:20.832374 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7404 00:56:20.835519 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7405 00:56:20.842257 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 00:56:20.845629 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 00:56:20.848897 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 00:56:20.855694 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 00:56:20.859077 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 00:56:20.862479 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7411 00:56:20.868919 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7412 00:56:20.871836 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7413 00:56:20.875364 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7414 00:56:20.878838 Total UI for P1: 0, mck2ui 16
7415 00:56:20.881834 best dqsien dly found for B0: ( 1, 1, 0)
7416 00:56:20.888729 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7417 00:56:20.888807 Total UI for P1: 0, mck2ui 16
7418 00:56:20.895441 best dqsien dly found for B1: ( 1, 1, 6)
7419 00:56:20.898974 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7420 00:56:20.902106 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7421 00:56:20.902208
7422 00:56:20.905668 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7423 00:56:20.908752 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7424 00:56:20.911847 [Gating] SW calibration Done
7425 00:56:20.911924 ==
7426 00:56:20.915678 Dram Type= 6, Freq= 0, CH_0, rank 0
7427 00:56:20.918731 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7428 00:56:20.918809 ==
7429 00:56:20.921801 RX Vref Scan: 0
7430 00:56:20.921878
7431 00:56:20.921938 RX Vref 0 -> 0, step: 1
7432 00:56:20.921994
7433 00:56:20.925153 RX Delay 0 -> 252, step: 8
7434 00:56:20.928869 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7435 00:56:20.931756 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7436 00:56:20.938284 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7437 00:56:20.941712 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7438 00:56:20.945193 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7439 00:56:20.948419 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7440 00:56:20.951627 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7441 00:56:20.958604 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7442 00:56:20.961560 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7443 00:56:20.964793 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7444 00:56:20.968673 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7445 00:56:20.971978 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7446 00:56:20.978099 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7447 00:56:20.981840 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7448 00:56:20.985156 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7449 00:56:20.988052 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7450 00:56:20.988133 ==
7451 00:56:20.991328 Dram Type= 6, Freq= 0, CH_0, rank 0
7452 00:56:20.998052 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7453 00:56:20.998142 ==
7454 00:56:20.998205 DQS Delay:
7455 00:56:21.002008 DQS0 = 0, DQS1 = 0
7456 00:56:21.002102 DQM Delay:
7457 00:56:21.002165 DQM0 = 130, DQM1 = 124
7458 00:56:21.004930 DQ Delay:
7459 00:56:21.008345 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7460 00:56:21.011620 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7461 00:56:21.015077 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7462 00:56:21.018378 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7463 00:56:21.018456
7464 00:56:21.018515
7465 00:56:21.018570 ==
7466 00:56:21.021577 Dram Type= 6, Freq= 0, CH_0, rank 0
7467 00:56:21.024882 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7468 00:56:21.028253 ==
7469 00:56:21.028329
7470 00:56:21.028389
7471 00:56:21.028446 TX Vref Scan disable
7472 00:56:21.031652 == TX Byte 0 ==
7473 00:56:21.034883 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7474 00:56:21.038330 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7475 00:56:21.041532 == TX Byte 1 ==
7476 00:56:21.044792 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7477 00:56:21.048009 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7478 00:56:21.051063 ==
7479 00:56:21.054390 Dram Type= 6, Freq= 0, CH_0, rank 0
7480 00:56:21.057643 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7481 00:56:21.057720 ==
7482 00:56:21.069997
7483 00:56:21.073255 TX Vref early break, caculate TX vref
7484 00:56:21.076747 TX Vref=16, minBit 8, minWin=21, winSum=373
7485 00:56:21.079936 TX Vref=18, minBit 8, minWin=21, winSum=375
7486 00:56:21.083101 TX Vref=20, minBit 8, minWin=23, winSum=387
7487 00:56:21.086799 TX Vref=22, minBit 4, minWin=24, winSum=397
7488 00:56:21.090072 TX Vref=24, minBit 8, minWin=24, winSum=408
7489 00:56:21.096654 TX Vref=26, minBit 10, minWin=24, winSum=408
7490 00:56:21.100301 TX Vref=28, minBit 1, minWin=25, winSum=416
7491 00:56:21.103847 TX Vref=30, minBit 1, minWin=25, winSum=412
7492 00:56:21.106683 TX Vref=32, minBit 1, minWin=24, winSum=403
7493 00:56:21.109596 TX Vref=34, minBit 0, minWin=24, winSum=391
7494 00:56:21.116765 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 28
7495 00:56:21.116843
7496 00:56:21.120297 Final TX Range 0 Vref 28
7497 00:56:21.120375
7498 00:56:21.120434 ==
7499 00:56:21.123449 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 00:56:21.126523 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7501 00:56:21.126618 ==
7502 00:56:21.126713
7503 00:56:21.126783
7504 00:56:21.129809 TX Vref Scan disable
7505 00:56:21.136244 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
7506 00:56:21.136323 == TX Byte 0 ==
7507 00:56:21.139744 u2DelayCellOfst[0]=11 cells (3 PI)
7508 00:56:21.143068 u2DelayCellOfst[1]=18 cells (5 PI)
7509 00:56:21.146398 u2DelayCellOfst[2]=11 cells (3 PI)
7510 00:56:21.150120 u2DelayCellOfst[3]=14 cells (4 PI)
7511 00:56:21.152902 u2DelayCellOfst[4]=7 cells (2 PI)
7512 00:56:21.156244 u2DelayCellOfst[5]=0 cells (0 PI)
7513 00:56:21.159401 u2DelayCellOfst[6]=18 cells (5 PI)
7514 00:56:21.162807 u2DelayCellOfst[7]=18 cells (5 PI)
7515 00:56:21.166057 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7516 00:56:21.169970 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7517 00:56:21.172713 == TX Byte 1 ==
7518 00:56:21.172790 u2DelayCellOfst[8]=3 cells (1 PI)
7519 00:56:21.176046 u2DelayCellOfst[9]=0 cells (0 PI)
7520 00:56:21.179545 u2DelayCellOfst[10]=11 cells (3 PI)
7521 00:56:21.182673 u2DelayCellOfst[11]=3 cells (1 PI)
7522 00:56:21.185823 u2DelayCellOfst[12]=14 cells (4 PI)
7523 00:56:21.189548 u2DelayCellOfst[13]=14 cells (4 PI)
7524 00:56:21.192630 u2DelayCellOfst[14]=18 cells (5 PI)
7525 00:56:21.195754 u2DelayCellOfst[15]=14 cells (4 PI)
7526 00:56:21.199359 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7527 00:56:21.205961 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7528 00:56:21.206039 DramC Write-DBI on
7529 00:56:21.206099 ==
7530 00:56:21.208994 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 00:56:21.215639 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7532 00:56:21.215718 ==
7533 00:56:21.215779
7534 00:56:21.215834
7535 00:56:21.215887 TX Vref Scan disable
7536 00:56:21.219430 == TX Byte 0 ==
7537 00:56:21.222584 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7538 00:56:21.226044 == TX Byte 1 ==
7539 00:56:21.229572 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7540 00:56:21.232765 DramC Write-DBI off
7541 00:56:21.232864
7542 00:56:21.232951 [DATLAT]
7543 00:56:21.233033 Freq=1600, CH0 RK0
7544 00:56:21.233113
7545 00:56:21.236362 DATLAT Default: 0xf
7546 00:56:21.236439 0, 0xFFFF, sum = 0
7547 00:56:21.239515 1, 0xFFFF, sum = 0
7548 00:56:21.242720 2, 0xFFFF, sum = 0
7549 00:56:21.242799 3, 0xFFFF, sum = 0
7550 00:56:21.246116 4, 0xFFFF, sum = 0
7551 00:56:21.246194 5, 0xFFFF, sum = 0
7552 00:56:21.249339 6, 0xFFFF, sum = 0
7553 00:56:21.249417 7, 0xFFFF, sum = 0
7554 00:56:21.252746 8, 0xFFFF, sum = 0
7555 00:56:21.252836 9, 0xFFFF, sum = 0
7556 00:56:21.256006 10, 0xFFFF, sum = 0
7557 00:56:21.256087 11, 0xFFFF, sum = 0
7558 00:56:21.259381 12, 0xBFF, sum = 0
7559 00:56:21.259460 13, 0x0, sum = 1
7560 00:56:21.262600 14, 0x0, sum = 2
7561 00:56:21.262679 15, 0x0, sum = 3
7562 00:56:21.265797 16, 0x0, sum = 4
7563 00:56:21.265876 best_step = 14
7564 00:56:21.265936
7565 00:56:21.265992 ==
7566 00:56:21.268978 Dram Type= 6, Freq= 0, CH_0, rank 0
7567 00:56:21.272590 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7568 00:56:21.275684 ==
7569 00:56:21.275761 RX Vref Scan: 1
7570 00:56:21.275825
7571 00:56:21.279384 Set Vref Range= 24 -> 127
7572 00:56:21.279462
7573 00:56:21.282482 RX Vref 24 -> 127, step: 1
7574 00:56:21.282559
7575 00:56:21.282619 RX Delay 11 -> 252, step: 4
7576 00:56:21.282675
7577 00:56:21.285841 Set Vref, RX VrefLevel [Byte0]: 24
7578 00:56:21.289333 [Byte1]: 24
7579 00:56:21.292776
7580 00:56:21.292869 Set Vref, RX VrefLevel [Byte0]: 25
7581 00:56:21.295978 [Byte1]: 25
7582 00:56:21.300739
7583 00:56:21.300817 Set Vref, RX VrefLevel [Byte0]: 26
7584 00:56:21.306649 [Byte1]: 26
7585 00:56:21.306725
7586 00:56:21.309961 Set Vref, RX VrefLevel [Byte0]: 27
7587 00:56:21.313402 [Byte1]: 27
7588 00:56:21.313478
7589 00:56:21.316871 Set Vref, RX VrefLevel [Byte0]: 28
7590 00:56:21.320099 [Byte1]: 28
7591 00:56:21.320176
7592 00:56:21.323845 Set Vref, RX VrefLevel [Byte0]: 29
7593 00:56:21.327199 [Byte1]: 29
7594 00:56:21.331089
7595 00:56:21.331165 Set Vref, RX VrefLevel [Byte0]: 30
7596 00:56:21.333947 [Byte1]: 30
7597 00:56:21.338284
7598 00:56:21.338361 Set Vref, RX VrefLevel [Byte0]: 31
7599 00:56:21.341742 [Byte1]: 31
7600 00:56:21.346233
7601 00:56:21.346323 Set Vref, RX VrefLevel [Byte0]: 32
7602 00:56:21.349458 [Byte1]: 32
7603 00:56:21.353924
7604 00:56:21.354000 Set Vref, RX VrefLevel [Byte0]: 33
7605 00:56:21.357139 [Byte1]: 33
7606 00:56:21.361137
7607 00:56:21.361213 Set Vref, RX VrefLevel [Byte0]: 34
7608 00:56:21.364614 [Byte1]: 34
7609 00:56:21.368993
7610 00:56:21.369069 Set Vref, RX VrefLevel [Byte0]: 35
7611 00:56:21.372490 [Byte1]: 35
7612 00:56:21.376655
7613 00:56:21.376731 Set Vref, RX VrefLevel [Byte0]: 36
7614 00:56:21.379964 [Byte1]: 36
7615 00:56:21.384263
7616 00:56:21.384339 Set Vref, RX VrefLevel [Byte0]: 37
7617 00:56:21.387508 [Byte1]: 37
7618 00:56:21.391779
7619 00:56:21.391856 Set Vref, RX VrefLevel [Byte0]: 38
7620 00:56:21.394832 [Byte1]: 38
7621 00:56:21.399361
7622 00:56:21.399437 Set Vref, RX VrefLevel [Byte0]: 39
7623 00:56:21.405919 [Byte1]: 39
7624 00:56:21.405995
7625 00:56:21.408926 Set Vref, RX VrefLevel [Byte0]: 40
7626 00:56:21.412196 [Byte1]: 40
7627 00:56:21.412273
7628 00:56:21.415418 Set Vref, RX VrefLevel [Byte0]: 41
7629 00:56:21.419315 [Byte1]: 41
7630 00:56:21.422435
7631 00:56:21.422511 Set Vref, RX VrefLevel [Byte0]: 42
7632 00:56:21.425608 [Byte1]: 42
7633 00:56:21.429781
7634 00:56:21.429855 Set Vref, RX VrefLevel [Byte0]: 43
7635 00:56:21.433183 [Byte1]: 43
7636 00:56:21.437229
7637 00:56:21.437323 Set Vref, RX VrefLevel [Byte0]: 44
7638 00:56:21.440426 [Byte1]: 44
7639 00:56:21.445253
7640 00:56:21.445322 Set Vref, RX VrefLevel [Byte0]: 45
7641 00:56:21.448530 [Byte1]: 45
7642 00:56:21.452751
7643 00:56:21.452818 Set Vref, RX VrefLevel [Byte0]: 46
7644 00:56:21.455956 [Byte1]: 46
7645 00:56:21.460535
7646 00:56:21.460607 Set Vref, RX VrefLevel [Byte0]: 47
7647 00:56:21.463676 [Byte1]: 47
7648 00:56:21.467626
7649 00:56:21.467693 Set Vref, RX VrefLevel [Byte0]: 48
7650 00:56:21.471083 [Byte1]: 48
7651 00:56:21.475225
7652 00:56:21.475292 Set Vref, RX VrefLevel [Byte0]: 49
7653 00:56:21.478663 [Byte1]: 49
7654 00:56:21.482874
7655 00:56:21.482947 Set Vref, RX VrefLevel [Byte0]: 50
7656 00:56:21.486496 [Byte1]: 50
7657 00:56:21.490730
7658 00:56:21.490797 Set Vref, RX VrefLevel [Byte0]: 51
7659 00:56:21.494009 [Byte1]: 51
7660 00:56:21.498054
7661 00:56:21.498152 Set Vref, RX VrefLevel [Byte0]: 52
7662 00:56:21.501807 [Byte1]: 52
7663 00:56:21.506092
7664 00:56:21.506184 Set Vref, RX VrefLevel [Byte0]: 53
7665 00:56:21.508947 [Byte1]: 53
7666 00:56:21.513559
7667 00:56:21.513626 Set Vref, RX VrefLevel [Byte0]: 54
7668 00:56:21.517199 [Byte1]: 54
7669 00:56:21.521000
7670 00:56:21.521071 Set Vref, RX VrefLevel [Byte0]: 55
7671 00:56:21.524440 [Byte1]: 55
7672 00:56:21.529223
7673 00:56:21.529293 Set Vref, RX VrefLevel [Byte0]: 56
7674 00:56:21.532076 [Byte1]: 56
7675 00:56:21.536311
7676 00:56:21.536379 Set Vref, RX VrefLevel [Byte0]: 57
7677 00:56:21.539559 [Byte1]: 57
7678 00:56:21.544114
7679 00:56:21.544185 Set Vref, RX VrefLevel [Byte0]: 58
7680 00:56:21.547411 [Byte1]: 58
7681 00:56:21.551660
7682 00:56:21.551730 Set Vref, RX VrefLevel [Byte0]: 59
7683 00:56:21.554876 [Byte1]: 59
7684 00:56:21.559407
7685 00:56:21.559477 Set Vref, RX VrefLevel [Byte0]: 60
7686 00:56:21.562305 [Byte1]: 60
7687 00:56:21.567157
7688 00:56:21.567233 Set Vref, RX VrefLevel [Byte0]: 61
7689 00:56:21.570393 [Byte1]: 61
7690 00:56:21.574367
7691 00:56:21.574443 Set Vref, RX VrefLevel [Byte0]: 62
7692 00:56:21.577822 [Byte1]: 62
7693 00:56:21.582285
7694 00:56:21.582360 Set Vref, RX VrefLevel [Byte0]: 63
7695 00:56:21.585420 [Byte1]: 63
7696 00:56:21.589556
7697 00:56:21.589619 Set Vref, RX VrefLevel [Byte0]: 64
7698 00:56:21.593007 [Byte1]: 64
7699 00:56:21.597160
7700 00:56:21.597230 Set Vref, RX VrefLevel [Byte0]: 65
7701 00:56:21.600772 [Byte1]: 65
7702 00:56:21.604983
7703 00:56:21.605048 Set Vref, RX VrefLevel [Byte0]: 66
7704 00:56:21.608148 [Byte1]: 66
7705 00:56:21.612462
7706 00:56:21.612539 Set Vref, RX VrefLevel [Byte0]: 67
7707 00:56:21.615999 [Byte1]: 67
7708 00:56:21.619986
7709 00:56:21.620062 Set Vref, RX VrefLevel [Byte0]: 68
7710 00:56:21.623255 [Byte1]: 68
7711 00:56:21.628037
7712 00:56:21.628113 Set Vref, RX VrefLevel [Byte0]: 69
7713 00:56:21.630886 [Byte1]: 69
7714 00:56:21.635591
7715 00:56:21.635667 Set Vref, RX VrefLevel [Byte0]: 70
7716 00:56:21.639020 [Byte1]: 70
7717 00:56:21.643207
7718 00:56:21.643285 Set Vref, RX VrefLevel [Byte0]: 71
7719 00:56:21.646017 [Byte1]: 71
7720 00:56:21.650596
7721 00:56:21.650672 Set Vref, RX VrefLevel [Byte0]: 72
7722 00:56:21.654422 [Byte1]: 72
7723 00:56:21.658467
7724 00:56:21.658543 Set Vref, RX VrefLevel [Byte0]: 73
7725 00:56:21.661480 [Byte1]: 73
7726 00:56:21.665724
7727 00:56:21.665800 Set Vref, RX VrefLevel [Byte0]: 74
7728 00:56:21.669002 [Byte1]: 74
7729 00:56:21.673599
7730 00:56:21.673676 Final RX Vref Byte 0 = 52 to rank0
7731 00:56:21.676988 Final RX Vref Byte 1 = 55 to rank0
7732 00:56:21.680431 Final RX Vref Byte 0 = 52 to rank1
7733 00:56:21.683503 Final RX Vref Byte 1 = 55 to rank1==
7734 00:56:21.686667 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 00:56:21.693575 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7736 00:56:21.693652 ==
7737 00:56:21.693713 DQS Delay:
7738 00:56:21.693768 DQS0 = 0, DQS1 = 0
7739 00:56:21.697099 DQM Delay:
7740 00:56:21.697175 DQM0 = 126, DQM1 = 121
7741 00:56:21.699835 DQ Delay:
7742 00:56:21.703103 DQ0 =122, DQ1 =126, DQ2 =124, DQ3 =124
7743 00:56:21.706419 DQ4 =130, DQ5 =116, DQ6 =136, DQ7 =134
7744 00:56:21.709691 DQ8 =112, DQ9 =104, DQ10 =122, DQ11 =112
7745 00:56:21.713403 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =134
7746 00:56:21.713478
7747 00:56:21.713536
7748 00:56:21.713590
7749 00:56:21.716347 [DramC_TX_OE_Calibration] TA2
7750 00:56:21.719928 Original DQ_B0 (3 6) =30, OEN = 27
7751 00:56:21.723453 Original DQ_B1 (3 6) =30, OEN = 27
7752 00:56:21.726480 24, 0x0, End_B0=24 End_B1=24
7753 00:56:21.726573 25, 0x0, End_B0=25 End_B1=25
7754 00:56:21.729761 26, 0x0, End_B0=26 End_B1=26
7755 00:56:21.732860 27, 0x0, End_B0=27 End_B1=27
7756 00:56:21.736769 28, 0x0, End_B0=28 End_B1=28
7757 00:56:21.739530 29, 0x0, End_B0=29 End_B1=29
7758 00:56:21.739609 30, 0x0, End_B0=30 End_B1=30
7759 00:56:21.742928 31, 0x4141, End_B0=30 End_B1=30
7760 00:56:21.746063 Byte0 end_step=30 best_step=27
7761 00:56:21.749497 Byte1 end_step=30 best_step=27
7762 00:56:21.753007 Byte0 TX OE(2T, 0.5T) = (3, 3)
7763 00:56:21.756303 Byte1 TX OE(2T, 0.5T) = (3, 3)
7764 00:56:21.756366
7765 00:56:21.756427
7766 00:56:21.762726 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7767 00:56:21.766293 CH0 RK0: MR19=303, MR18=1F1F
7768 00:56:21.772776 CH0_RK0: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
7769 00:56:21.772844
7770 00:56:21.776467 ----->DramcWriteLeveling(PI) begin...
7771 00:56:21.776536 ==
7772 00:56:21.779784 Dram Type= 6, Freq= 0, CH_0, rank 1
7773 00:56:21.782956 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7774 00:56:21.783019 ==
7775 00:56:21.786577 Write leveling (Byte 0): 29 => 29
7776 00:56:21.789720 Write leveling (Byte 1): 27 => 27
7777 00:56:21.792617 DramcWriteLeveling(PI) end<-----
7778 00:56:21.792679
7779 00:56:21.792733 ==
7780 00:56:21.796493 Dram Type= 6, Freq= 0, CH_0, rank 1
7781 00:56:21.799678 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7782 00:56:21.799749 ==
7783 00:56:21.802835 [Gating] SW mode calibration
7784 00:56:21.809348 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7785 00:56:21.815951 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7786 00:56:21.819199 0 12 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7787 00:56:21.825854 0 12 4 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
7788 00:56:21.829418 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7789 00:56:21.832362 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7790 00:56:21.836230 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7791 00:56:21.842899 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7792 00:56:21.845741 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7793 00:56:21.849411 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7794 00:56:21.856464 0 13 0 | B1->B0 | 3434 2c2c | 1 1 | (1 0) (1 0)
7795 00:56:21.859232 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
7796 00:56:21.862736 0 13 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7797 00:56:21.868968 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7798 00:56:21.872846 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7799 00:56:21.875828 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7800 00:56:21.882663 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7801 00:56:21.885929 0 13 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7802 00:56:21.889094 0 14 0 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
7803 00:56:21.895761 0 14 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7804 00:56:21.898817 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7805 00:56:21.902179 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7806 00:56:21.908886 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7807 00:56:21.912279 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7808 00:56:21.915653 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7809 00:56:21.922512 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7810 00:56:21.925702 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7811 00:56:21.929102 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7812 00:56:21.935355 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7813 00:56:21.938752 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 00:56:21.942399 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 00:56:21.949152 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 00:56:21.952119 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 00:56:21.955340 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 00:56:21.962820 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 00:56:21.965323 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 00:56:21.968722 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 00:56:21.972139 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 00:56:21.978613 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 00:56:21.982062 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 00:56:21.985574 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 00:56:21.992194 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7826 00:56:21.995531 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7827 00:56:21.998894 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7828 00:56:22.002096 Total UI for P1: 0, mck2ui 16
7829 00:56:22.005332 best dqsien dly found for B0: ( 1, 0, 30)
7830 00:56:22.012278 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7831 00:56:22.012352 Total UI for P1: 0, mck2ui 16
7832 00:56:22.018516 best dqsien dly found for B1: ( 1, 1, 2)
7833 00:56:22.022058 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7834 00:56:22.025180 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7835 00:56:22.025268
7836 00:56:22.028699 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7837 00:56:22.032269 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7838 00:56:22.035415 [Gating] SW calibration Done
7839 00:56:22.035485 ==
7840 00:56:22.038414 Dram Type= 6, Freq= 0, CH_0, rank 1
7841 00:56:22.041706 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7842 00:56:22.041804 ==
7843 00:56:22.044989 RX Vref Scan: 0
7844 00:56:22.045076
7845 00:56:22.045156 RX Vref 0 -> 0, step: 1
7846 00:56:22.045241
7847 00:56:22.048382 RX Delay 0 -> 252, step: 8
7848 00:56:22.051595 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7849 00:56:22.058465 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7850 00:56:22.061924 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7851 00:56:22.065094 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7852 00:56:22.068241 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7853 00:56:22.071782 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7854 00:56:22.078861 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7855 00:56:22.081470 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7856 00:56:22.085127 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7857 00:56:22.088297 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7858 00:56:22.091897 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7859 00:56:22.098259 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7860 00:56:22.101496 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7861 00:56:22.104749 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7862 00:56:22.108022 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7863 00:56:22.111192 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7864 00:56:22.114678 ==
7865 00:56:22.118064 Dram Type= 6, Freq= 0, CH_0, rank 1
7866 00:56:22.121203 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7867 00:56:22.121299 ==
7868 00:56:22.121382 DQS Delay:
7869 00:56:22.124793 DQS0 = 0, DQS1 = 0
7870 00:56:22.124865 DQM Delay:
7871 00:56:22.128188 DQM0 = 130, DQM1 = 124
7872 00:56:22.128255 DQ Delay:
7873 00:56:22.131337 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7874 00:56:22.134739 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7875 00:56:22.138024 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7876 00:56:22.141353 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7877 00:56:22.141428
7878 00:56:22.141484
7879 00:56:22.144316 ==
7880 00:56:22.144380 Dram Type= 6, Freq= 0, CH_0, rank 1
7881 00:56:22.151272 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7882 00:56:22.151341 ==
7883 00:56:22.151404
7884 00:56:22.151455
7885 00:56:22.154589 TX Vref Scan disable
7886 00:56:22.154649 == TX Byte 0 ==
7887 00:56:22.157500 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7888 00:56:22.164136 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7889 00:56:22.164214 == TX Byte 1 ==
7890 00:56:22.167526 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7891 00:56:22.174230 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7892 00:56:22.174322 ==
7893 00:56:22.177196 Dram Type= 6, Freq= 0, CH_0, rank 1
7894 00:56:22.180965 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7895 00:56:22.181042 ==
7896 00:56:22.194619
7897 00:56:22.197962 TX Vref early break, caculate TX vref
7898 00:56:22.201377 TX Vref=16, minBit 1, minWin=23, winSum=377
7899 00:56:22.204749 TX Vref=18, minBit 1, minWin=23, winSum=388
7900 00:56:22.207848 TX Vref=20, minBit 8, minWin=23, winSum=394
7901 00:56:22.211253 TX Vref=22, minBit 8, minWin=23, winSum=401
7902 00:56:22.214585 TX Vref=24, minBit 8, minWin=24, winSum=408
7903 00:56:22.221618 TX Vref=26, minBit 8, minWin=24, winSum=409
7904 00:56:22.224760 TX Vref=28, minBit 8, minWin=24, winSum=414
7905 00:56:22.228096 TX Vref=30, minBit 0, minWin=25, winSum=410
7906 00:56:22.231141 TX Vref=32, minBit 1, minWin=24, winSum=403
7907 00:56:22.234506 TX Vref=34, minBit 8, minWin=23, winSum=398
7908 00:56:22.238421 TX Vref=36, minBit 8, minWin=22, winSum=386
7909 00:56:22.244503 [TxChooseVref] Worse bit 0, Min win 25, Win sum 410, Final Vref 30
7910 00:56:22.244584
7911 00:56:22.247962 Final TX Range 0 Vref 30
7912 00:56:22.248040
7913 00:56:22.248099 ==
7914 00:56:22.251568 Dram Type= 6, Freq= 0, CH_0, rank 1
7915 00:56:22.254459 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7916 00:56:22.254537 ==
7917 00:56:22.254597
7918 00:56:22.254651
7919 00:56:22.257803 TX Vref Scan disable
7920 00:56:22.264545 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
7921 00:56:22.264622 == TX Byte 0 ==
7922 00:56:22.267770 u2DelayCellOfst[0]=11 cells (3 PI)
7923 00:56:22.271242 u2DelayCellOfst[1]=18 cells (5 PI)
7924 00:56:22.274497 u2DelayCellOfst[2]=14 cells (4 PI)
7925 00:56:22.278068 u2DelayCellOfst[3]=14 cells (4 PI)
7926 00:56:22.281290 u2DelayCellOfst[4]=11 cells (3 PI)
7927 00:56:22.284622 u2DelayCellOfst[5]=0 cells (0 PI)
7928 00:56:22.287807 u2DelayCellOfst[6]=22 cells (6 PI)
7929 00:56:22.291032 u2DelayCellOfst[7]=18 cells (5 PI)
7930 00:56:22.294410 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7931 00:56:22.297541 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7932 00:56:22.300790 == TX Byte 1 ==
7933 00:56:22.304154 u2DelayCellOfst[8]=0 cells (0 PI)
7934 00:56:22.307690 u2DelayCellOfst[9]=0 cells (0 PI)
7935 00:56:22.310780 u2DelayCellOfst[10]=11 cells (3 PI)
7936 00:56:22.310856 u2DelayCellOfst[11]=3 cells (1 PI)
7937 00:56:22.314513 u2DelayCellOfst[12]=14 cells (4 PI)
7938 00:56:22.317586 u2DelayCellOfst[13]=14 cells (4 PI)
7939 00:56:22.321003 u2DelayCellOfst[14]=18 cells (5 PI)
7940 00:56:22.323930 u2DelayCellOfst[15]=14 cells (4 PI)
7941 00:56:22.330700 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7942 00:56:22.333856 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7943 00:56:22.333933 DramC Write-DBI on
7944 00:56:22.337256 ==
7945 00:56:22.340316 Dram Type= 6, Freq= 0, CH_0, rank 1
7946 00:56:22.343613 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7947 00:56:22.343690 ==
7948 00:56:22.343749
7949 00:56:22.343803
7950 00:56:22.347024 TX Vref Scan disable
7951 00:56:22.347102 == TX Byte 0 ==
7952 00:56:22.353789 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7953 00:56:22.353877 == TX Byte 1 ==
7954 00:56:22.360512 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7955 00:56:22.360598 DramC Write-DBI off
7956 00:56:22.360658
7957 00:56:22.360713 [DATLAT]
7958 00:56:22.363548 Freq=1600, CH0 RK1
7959 00:56:22.363625
7960 00:56:22.363684 DATLAT Default: 0xe
7961 00:56:22.366962 0, 0xFFFF, sum = 0
7962 00:56:22.367039 1, 0xFFFF, sum = 0
7963 00:56:22.370517 2, 0xFFFF, sum = 0
7964 00:56:22.370594 3, 0xFFFF, sum = 0
7965 00:56:22.373626 4, 0xFFFF, sum = 0
7966 00:56:22.373707 5, 0xFFFF, sum = 0
7967 00:56:22.376797 6, 0xFFFF, sum = 0
7968 00:56:22.376879 7, 0xFFFF, sum = 0
7969 00:56:22.380014 8, 0xFFFF, sum = 0
7970 00:56:22.383234 9, 0xFFFF, sum = 0
7971 00:56:22.383310 10, 0xFFFF, sum = 0
7972 00:56:22.386756 11, 0xFFFF, sum = 0
7973 00:56:22.386857 12, 0x8FFF, sum = 0
7974 00:56:22.390074 13, 0x0, sum = 1
7975 00:56:22.390177 14, 0x0, sum = 2
7976 00:56:22.393458 15, 0x0, sum = 3
7977 00:56:22.393540 16, 0x0, sum = 4
7978 00:56:22.393612 best_step = 14
7979 00:56:22.396545
7980 00:56:22.396613 ==
7981 00:56:22.399898 Dram Type= 6, Freq= 0, CH_0, rank 1
7982 00:56:22.403020 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7983 00:56:22.403092 ==
7984 00:56:22.403168 RX Vref Scan: 0
7985 00:56:22.403259
7986 00:56:22.407156 RX Vref 0 -> 0, step: 1
7987 00:56:22.407219
7988 00:56:22.409723 RX Delay 11 -> 252, step: 4
7989 00:56:22.413175 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7990 00:56:22.419762 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7991 00:56:22.423400 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7992 00:56:22.426165 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7993 00:56:22.429558 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7994 00:56:22.432671 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7995 00:56:22.439736 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7996 00:56:22.442876 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7997 00:56:22.446199 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7998 00:56:22.449802 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7999 00:56:22.453105 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8000 00:56:22.459398 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8001 00:56:22.462445 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8002 00:56:22.465816 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8003 00:56:22.469144 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8004 00:56:22.476191 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8005 00:56:22.476271 ==
8006 00:56:22.478978 Dram Type= 6, Freq= 0, CH_0, rank 1
8007 00:56:22.482340 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8008 00:56:22.482417 ==
8009 00:56:22.482477 DQS Delay:
8010 00:56:22.485548 DQS0 = 0, DQS1 = 0
8011 00:56:22.485625 DQM Delay:
8012 00:56:22.488977 DQM0 = 128, DQM1 = 120
8013 00:56:22.489054 DQ Delay:
8014 00:56:22.492343 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
8015 00:56:22.495510 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
8016 00:56:22.499210 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8017 00:56:22.502384 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
8018 00:56:22.502459
8019 00:56:22.502520
8020 00:56:22.502575
8021 00:56:22.506008 [DramC_TX_OE_Calibration] TA2
8022 00:56:22.509262 Original DQ_B0 (3 6) =30, OEN = 27
8023 00:56:22.512283 Original DQ_B1 (3 6) =30, OEN = 27
8024 00:56:22.515416 24, 0x0, End_B0=24 End_B1=24
8025 00:56:22.518912 25, 0x0, End_B0=25 End_B1=25
8026 00:56:22.519005 26, 0x0, End_B0=26 End_B1=26
8027 00:56:22.522411 27, 0x0, End_B0=27 End_B1=27
8028 00:56:22.525483 28, 0x0, End_B0=28 End_B1=28
8029 00:56:22.528745 29, 0x0, End_B0=29 End_B1=29
8030 00:56:22.532084 30, 0x0, End_B0=30 End_B1=30
8031 00:56:22.532153 31, 0x4141, End_B0=30 End_B1=30
8032 00:56:22.535371 Byte0 end_step=30 best_step=27
8033 00:56:22.538582 Byte1 end_step=30 best_step=27
8034 00:56:22.542029 Byte0 TX OE(2T, 0.5T) = (3, 3)
8035 00:56:22.545624 Byte1 TX OE(2T, 0.5T) = (3, 3)
8036 00:56:22.545689
8037 00:56:22.545744
8038 00:56:22.551936 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8039 00:56:22.555504 CH0 RK1: MR19=303, MR18=2222
8040 00:56:22.561757 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
8041 00:56:22.565038 [RxdqsGatingPostProcess] freq 1600
8042 00:56:22.571895 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8043 00:56:22.575102 Pre-setting of DQS Precalculation
8044 00:56:22.578198 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8045 00:56:22.578307 ==
8046 00:56:22.581821 Dram Type= 6, Freq= 0, CH_1, rank 0
8047 00:56:22.585043 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8048 00:56:22.585109 ==
8049 00:56:22.591412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8050 00:56:22.594912 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8051 00:56:22.601419 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8052 00:56:22.604659 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8053 00:56:22.613988 [CA 0] Center 41 (11~71) winsize 61
8054 00:56:22.617257 [CA 1] Center 40 (10~70) winsize 61
8055 00:56:22.620769 [CA 2] Center 36 (7~66) winsize 60
8056 00:56:22.624159 [CA 3] Center 35 (6~65) winsize 60
8057 00:56:22.627471 [CA 4] Center 33 (3~63) winsize 61
8058 00:56:22.630647 [CA 5] Center 33 (4~63) winsize 60
8059 00:56:22.630714
8060 00:56:22.633954 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8061 00:56:22.634035
8062 00:56:22.637665 [CATrainingPosCal] consider 1 rank data
8063 00:56:22.640542 u2DelayCellTimex100 = 266/100 ps
8064 00:56:22.646920 CA0 delay=41 (11~71),Diff = 8 PI (29 cell)
8065 00:56:22.650544 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8066 00:56:22.654041 CA2 delay=36 (7~66),Diff = 3 PI (11 cell)
8067 00:56:22.657137 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8068 00:56:22.660271 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
8069 00:56:22.663622 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8070 00:56:22.663691
8071 00:56:22.667131 CA PerBit enable=1, Macro0, CA PI delay=33
8072 00:56:22.667194
8073 00:56:22.670186 [CBTSetCACLKResult] CA Dly = 33
8074 00:56:22.673529 CS Dly: 8 (0~39)
8075 00:56:22.677036 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8076 00:56:22.680352 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8077 00:56:22.680416 ==
8078 00:56:22.683804 Dram Type= 6, Freq= 0, CH_1, rank 1
8079 00:56:22.690057 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8080 00:56:22.690126 ==
8081 00:56:22.693408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8082 00:56:22.696730 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8083 00:56:22.703794 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8084 00:56:22.709898 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8085 00:56:22.716587 [CA 0] Center 41 (11~71) winsize 61
8086 00:56:22.720199 [CA 1] Center 41 (11~71) winsize 61
8087 00:56:22.723165 [CA 2] Center 36 (7~66) winsize 60
8088 00:56:22.726501 [CA 3] Center 36 (7~65) winsize 59
8089 00:56:22.729769 [CA 4] Center 34 (5~64) winsize 60
8090 00:56:22.733247 [CA 5] Center 34 (4~64) winsize 61
8091 00:56:22.733313
8092 00:56:22.736760 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8093 00:56:22.736826
8094 00:56:22.739951 [CATrainingPosCal] consider 2 rank data
8095 00:56:22.743165 u2DelayCellTimex100 = 266/100 ps
8096 00:56:22.746457 CA0 delay=41 (11~71),Diff = 8 PI (29 cell)
8097 00:56:22.753501 CA1 delay=40 (11~70),Diff = 7 PI (25 cell)
8098 00:56:22.756479 CA2 delay=36 (7~66),Diff = 3 PI (11 cell)
8099 00:56:22.759997 CA3 delay=36 (7~65),Diff = 3 PI (11 cell)
8100 00:56:22.763221 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8101 00:56:22.766477 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8102 00:56:22.766553
8103 00:56:22.769745 CA PerBit enable=1, Macro0, CA PI delay=33
8104 00:56:22.769821
8105 00:56:22.773237 [CBTSetCACLKResult] CA Dly = 33
8106 00:56:22.776577 CS Dly: 9 (0~41)
8107 00:56:22.779541 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8108 00:56:22.783329 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8109 00:56:22.783407
8110 00:56:22.786712 ----->DramcWriteLeveling(PI) begin...
8111 00:56:22.786790 ==
8112 00:56:22.789632 Dram Type= 6, Freq= 0, CH_1, rank 0
8113 00:56:22.796392 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8114 00:56:22.796469 ==
8115 00:56:22.799668 Write leveling (Byte 0): 22 => 22
8116 00:56:22.799744 Write leveling (Byte 1): 22 => 22
8117 00:56:22.802967 DramcWriteLeveling(PI) end<-----
8118 00:56:22.803043
8119 00:56:22.803102 ==
8120 00:56:22.806497 Dram Type= 6, Freq= 0, CH_1, rank 0
8121 00:56:22.813153 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8122 00:56:22.813233 ==
8123 00:56:22.816476 [Gating] SW mode calibration
8124 00:56:22.822545 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8125 00:56:22.826302 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8126 00:56:22.833073 0 12 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
8127 00:56:22.835824 0 12 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8128 00:56:22.839285 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8129 00:56:22.845972 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8130 00:56:22.849687 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8131 00:56:22.852528 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8132 00:56:22.859043 0 12 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8133 00:56:22.862267 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8134 00:56:22.865535 0 13 0 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8135 00:56:22.872160 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8136 00:56:22.875788 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8137 00:56:22.879262 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8138 00:56:22.885546 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8139 00:56:22.889062 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8140 00:56:22.893018 0 13 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8141 00:56:22.899063 0 13 28 | B1->B0 | 2323 4545 | 0 1 | (0 0) (0 0)
8142 00:56:22.902234 0 14 0 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
8143 00:56:22.905696 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8144 00:56:22.912139 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8145 00:56:22.915529 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 00:56:22.919201 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8147 00:56:22.922200 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8148 00:56:22.928733 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8149 00:56:22.932072 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8150 00:56:22.935577 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8151 00:56:22.941904 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8152 00:56:22.945294 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 00:56:22.948658 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 00:56:22.955450 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 00:56:22.959061 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 00:56:22.961883 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 00:56:22.968489 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 00:56:22.971852 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 00:56:22.975077 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 00:56:22.981832 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 00:56:22.985192 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 00:56:22.988034 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 00:56:22.994876 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 00:56:22.998520 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 00:56:23.001513 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8166 00:56:23.008459 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8167 00:56:23.011833 Total UI for P1: 0, mck2ui 16
8168 00:56:23.014761 best dqsien dly found for B0: ( 1, 0, 28)
8169 00:56:23.018146 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8170 00:56:23.021387 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8171 00:56:23.025198 Total UI for P1: 0, mck2ui 16
8172 00:56:23.028381 best dqsien dly found for B1: ( 1, 1, 2)
8173 00:56:23.031705 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8174 00:56:23.034800 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8175 00:56:23.034877
8176 00:56:23.041330 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8177 00:56:23.044883 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8178 00:56:23.044959 [Gating] SW calibration Done
8179 00:56:23.048108 ==
8180 00:56:23.051375 Dram Type= 6, Freq= 0, CH_1, rank 0
8181 00:56:23.054422 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8182 00:56:23.054499 ==
8183 00:56:23.054558 RX Vref Scan: 0
8184 00:56:23.054613
8185 00:56:23.058094 RX Vref 0 -> 0, step: 1
8186 00:56:23.058170
8187 00:56:23.061309 RX Delay 0 -> 252, step: 8
8188 00:56:23.064939 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8189 00:56:23.068134 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8190 00:56:23.071474 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8191 00:56:23.078046 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8192 00:56:23.081106 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8193 00:56:23.084407 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8194 00:56:23.087524 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8195 00:56:23.091208 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8196 00:56:23.097800 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8197 00:56:23.100765 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8198 00:56:23.104053 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8199 00:56:23.107688 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8200 00:56:23.110802 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8201 00:56:23.117935 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8202 00:56:23.121056 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8203 00:56:23.124384 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8204 00:56:23.124452 ==
8205 00:56:23.127724 Dram Type= 6, Freq= 0, CH_1, rank 0
8206 00:56:23.130733 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8207 00:56:23.134011 ==
8208 00:56:23.134087 DQS Delay:
8209 00:56:23.134146 DQS0 = 0, DQS1 = 0
8210 00:56:23.137359 DQM Delay:
8211 00:56:23.137435 DQM0 = 130, DQM1 = 125
8212 00:56:23.141665 DQ Delay:
8213 00:56:23.144223 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8214 00:56:23.147510 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8215 00:56:23.150783 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8216 00:56:23.154060 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8217 00:56:23.154136
8218 00:56:23.154195
8219 00:56:23.154290 ==
8220 00:56:23.157345 Dram Type= 6, Freq= 0, CH_1, rank 0
8221 00:56:23.161055 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8222 00:56:23.161132 ==
8223 00:56:23.161191
8224 00:56:23.164232
8225 00:56:23.164308 TX Vref Scan disable
8226 00:56:23.167142 == TX Byte 0 ==
8227 00:56:23.170558 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8228 00:56:23.173944 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8229 00:56:23.177405 == TX Byte 1 ==
8230 00:56:23.180513 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8231 00:56:23.183973 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8232 00:56:23.184049 ==
8233 00:56:23.187192 Dram Type= 6, Freq= 0, CH_1, rank 0
8234 00:56:23.193753 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8235 00:56:23.193830 ==
8236 00:56:23.204871
8237 00:56:23.208043 TX Vref early break, caculate TX vref
8238 00:56:23.211638 TX Vref=16, minBit 3, minWin=21, winSum=369
8239 00:56:23.214987 TX Vref=18, minBit 0, minWin=22, winSum=375
8240 00:56:23.217940 TX Vref=20, minBit 0, minWin=23, winSum=384
8241 00:56:23.221167 TX Vref=22, minBit 1, minWin=23, winSum=394
8242 00:56:23.224706 TX Vref=24, minBit 3, minWin=23, winSum=399
8243 00:56:23.231072 TX Vref=26, minBit 3, minWin=24, winSum=413
8244 00:56:23.234423 TX Vref=28, minBit 0, minWin=25, winSum=412
8245 00:56:23.237804 TX Vref=30, minBit 3, minWin=23, winSum=403
8246 00:56:23.241322 TX Vref=32, minBit 0, minWin=24, winSum=397
8247 00:56:23.244653 TX Vref=34, minBit 1, minWin=22, winSum=387
8248 00:56:23.251224 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 28
8249 00:56:23.251300
8250 00:56:23.254623 Final TX Range 0 Vref 28
8251 00:56:23.254690
8252 00:56:23.254750 ==
8253 00:56:23.258331 Dram Type= 6, Freq= 0, CH_1, rank 0
8254 00:56:23.261224 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8255 00:56:23.261291 ==
8256 00:56:23.261349
8257 00:56:23.261401
8258 00:56:23.265074 TX Vref Scan disable
8259 00:56:23.271518 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
8260 00:56:23.271590 == TX Byte 0 ==
8261 00:56:23.274882 u2DelayCellOfst[0]=18 cells (5 PI)
8262 00:56:23.278346 u2DelayCellOfst[1]=14 cells (4 PI)
8263 00:56:23.281544 u2DelayCellOfst[2]=0 cells (0 PI)
8264 00:56:23.285144 u2DelayCellOfst[3]=11 cells (3 PI)
8265 00:56:23.288347 u2DelayCellOfst[4]=11 cells (3 PI)
8266 00:56:23.291051 u2DelayCellOfst[5]=18 cells (5 PI)
8267 00:56:23.294440 u2DelayCellOfst[6]=18 cells (5 PI)
8268 00:56:23.294507 u2DelayCellOfst[7]=11 cells (3 PI)
8269 00:56:23.301324 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8270 00:56:23.304551 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8271 00:56:23.304627 == TX Byte 1 ==
8272 00:56:23.307878 u2DelayCellOfst[8]=0 cells (0 PI)
8273 00:56:23.311151 u2DelayCellOfst[9]=7 cells (2 PI)
8274 00:56:23.314364 u2DelayCellOfst[10]=11 cells (3 PI)
8275 00:56:23.317582 u2DelayCellOfst[11]=3 cells (1 PI)
8276 00:56:23.320954 u2DelayCellOfst[12]=18 cells (5 PI)
8277 00:56:23.324112 u2DelayCellOfst[13]=22 cells (6 PI)
8278 00:56:23.327982 u2DelayCellOfst[14]=18 cells (5 PI)
8279 00:56:23.330850 u2DelayCellOfst[15]=18 cells (5 PI)
8280 00:56:23.334095 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8281 00:56:23.341011 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8282 00:56:23.341080 DramC Write-DBI on
8283 00:56:23.341136 ==
8284 00:56:23.344574 Dram Type= 6, Freq= 0, CH_1, rank 0
8285 00:56:23.347711 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8286 00:56:23.350765 ==
8287 00:56:23.350828
8288 00:56:23.350882
8289 00:56:23.350933 TX Vref Scan disable
8290 00:56:23.353956 == TX Byte 0 ==
8291 00:56:23.357622 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8292 00:56:23.360850 == TX Byte 1 ==
8293 00:56:23.364090 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8294 00:56:23.367638 DramC Write-DBI off
8295 00:56:23.367705
8296 00:56:23.367762 [DATLAT]
8297 00:56:23.367818 Freq=1600, CH1 RK0
8298 00:56:23.367870
8299 00:56:23.370619 DATLAT Default: 0xf
8300 00:56:23.370680 0, 0xFFFF, sum = 0
8301 00:56:23.374159 1, 0xFFFF, sum = 0
8302 00:56:23.374277 2, 0xFFFF, sum = 0
8303 00:56:23.377151 3, 0xFFFF, sum = 0
8304 00:56:23.380479 4, 0xFFFF, sum = 0
8305 00:56:23.380546 5, 0xFFFF, sum = 0
8306 00:56:23.383954 6, 0xFFFF, sum = 0
8307 00:56:23.384020 7, 0xFFFF, sum = 0
8308 00:56:23.387360 8, 0xFFFF, sum = 0
8309 00:56:23.387424 9, 0xFFFF, sum = 0
8310 00:56:23.391129 10, 0xFFFF, sum = 0
8311 00:56:23.391196 11, 0xFFFF, sum = 0
8312 00:56:23.394168 12, 0xF7F, sum = 0
8313 00:56:23.394284 13, 0x0, sum = 1
8314 00:56:23.397753 14, 0x0, sum = 2
8315 00:56:23.397821 15, 0x0, sum = 3
8316 00:56:23.400887 16, 0x0, sum = 4
8317 00:56:23.400951 best_step = 14
8318 00:56:23.401005
8319 00:56:23.401057 ==
8320 00:56:23.404037 Dram Type= 6, Freq= 0, CH_1, rank 0
8321 00:56:23.407265 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8322 00:56:23.407330 ==
8323 00:56:23.410705 RX Vref Scan: 1
8324 00:56:23.410771
8325 00:56:23.413798 Set Vref Range= 24 -> 127
8326 00:56:23.413859
8327 00:56:23.413917 RX Vref 24 -> 127, step: 1
8328 00:56:23.417486
8329 00:56:23.417547 RX Delay 3 -> 252, step: 4
8330 00:56:23.417599
8331 00:56:23.420382 Set Vref, RX VrefLevel [Byte0]: 24
8332 00:56:23.423912 [Byte1]: 24
8333 00:56:23.427259
8334 00:56:23.427321 Set Vref, RX VrefLevel [Byte0]: 25
8335 00:56:23.430520 [Byte1]: 25
8336 00:56:23.435151
8337 00:56:23.435213 Set Vref, RX VrefLevel [Byte0]: 26
8338 00:56:23.438429 [Byte1]: 26
8339 00:56:23.442658
8340 00:56:23.442719 Set Vref, RX VrefLevel [Byte0]: 27
8341 00:56:23.445760 [Byte1]: 27
8342 00:56:23.450318
8343 00:56:23.450380 Set Vref, RX VrefLevel [Byte0]: 28
8344 00:56:23.453873 [Byte1]: 28
8345 00:56:23.458042
8346 00:56:23.458128 Set Vref, RX VrefLevel [Byte0]: 29
8347 00:56:23.461548 [Byte1]: 29
8348 00:56:23.465451
8349 00:56:23.465519 Set Vref, RX VrefLevel [Byte0]: 30
8350 00:56:23.469053 [Byte1]: 30
8351 00:56:23.473114
8352 00:56:23.473181 Set Vref, RX VrefLevel [Byte0]: 31
8353 00:56:23.476942 [Byte1]: 31
8354 00:56:23.481249
8355 00:56:23.481322 Set Vref, RX VrefLevel [Byte0]: 32
8356 00:56:23.484280 [Byte1]: 32
8357 00:56:23.488837
8358 00:56:23.488906 Set Vref, RX VrefLevel [Byte0]: 33
8359 00:56:23.491726 [Byte1]: 33
8360 00:56:23.496215
8361 00:56:23.496287 Set Vref, RX VrefLevel [Byte0]: 34
8362 00:56:23.499468 [Byte1]: 34
8363 00:56:23.503599
8364 00:56:23.503677 Set Vref, RX VrefLevel [Byte0]: 35
8365 00:56:23.506997 [Byte1]: 35
8366 00:56:23.511646
8367 00:56:23.511722 Set Vref, RX VrefLevel [Byte0]: 36
8368 00:56:23.515085 [Byte1]: 36
8369 00:56:23.519059
8370 00:56:23.519135 Set Vref, RX VrefLevel [Byte0]: 37
8371 00:56:23.522698 [Byte1]: 37
8372 00:56:23.526945
8373 00:56:23.527021 Set Vref, RX VrefLevel [Byte0]: 38
8374 00:56:23.530097 [Byte1]: 38
8375 00:56:23.534716
8376 00:56:23.534792 Set Vref, RX VrefLevel [Byte0]: 39
8377 00:56:23.537760 [Byte1]: 39
8378 00:56:23.542314
8379 00:56:23.542390 Set Vref, RX VrefLevel [Byte0]: 40
8380 00:56:23.545502 [Byte1]: 40
8381 00:56:23.549659
8382 00:56:23.549735 Set Vref, RX VrefLevel [Byte0]: 41
8383 00:56:23.553175 [Byte1]: 41
8384 00:56:23.557526
8385 00:56:23.557603 Set Vref, RX VrefLevel [Byte0]: 42
8386 00:56:23.560931 [Byte1]: 42
8387 00:56:23.565015
8388 00:56:23.565090 Set Vref, RX VrefLevel [Byte0]: 43
8389 00:56:23.568404 [Byte1]: 43
8390 00:56:23.572630
8391 00:56:23.572705 Set Vref, RX VrefLevel [Byte0]: 44
8392 00:56:23.575895 [Byte1]: 44
8393 00:56:23.580210
8394 00:56:23.580285 Set Vref, RX VrefLevel [Byte0]: 45
8395 00:56:23.583488 [Byte1]: 45
8396 00:56:23.588055
8397 00:56:23.588131 Set Vref, RX VrefLevel [Byte0]: 46
8398 00:56:23.591105 [Byte1]: 46
8399 00:56:23.595898
8400 00:56:23.595972 Set Vref, RX VrefLevel [Byte0]: 47
8401 00:56:23.599054 [Byte1]: 47
8402 00:56:23.603207
8403 00:56:23.603283 Set Vref, RX VrefLevel [Byte0]: 48
8404 00:56:23.606673 [Byte1]: 48
8405 00:56:23.611094
8406 00:56:23.611170 Set Vref, RX VrefLevel [Byte0]: 49
8407 00:56:23.614110 [Byte1]: 49
8408 00:56:23.618655
8409 00:56:23.618731 Set Vref, RX VrefLevel [Byte0]: 50
8410 00:56:23.622059 [Byte1]: 50
8411 00:56:23.626399
8412 00:56:23.626474 Set Vref, RX VrefLevel [Byte0]: 51
8413 00:56:23.629410 [Byte1]: 51
8414 00:56:23.634108
8415 00:56:23.634184 Set Vref, RX VrefLevel [Byte0]: 52
8416 00:56:23.637361 [Byte1]: 52
8417 00:56:23.641996
8418 00:56:23.642071 Set Vref, RX VrefLevel [Byte0]: 53
8419 00:56:23.645200 [Byte1]: 53
8420 00:56:23.649531
8421 00:56:23.649606 Set Vref, RX VrefLevel [Byte0]: 54
8422 00:56:23.653009 [Byte1]: 54
8423 00:56:23.657183
8424 00:56:23.657258 Set Vref, RX VrefLevel [Byte0]: 55
8425 00:56:23.660416 [Byte1]: 55
8426 00:56:23.664555
8427 00:56:23.664631 Set Vref, RX VrefLevel [Byte0]: 56
8428 00:56:23.667682 [Byte1]: 56
8429 00:56:23.672126
8430 00:56:23.672202 Set Vref, RX VrefLevel [Byte0]: 57
8431 00:56:23.675814 [Byte1]: 57
8432 00:56:23.679901
8433 00:56:23.679985 Set Vref, RX VrefLevel [Byte0]: 58
8434 00:56:23.683096 [Byte1]: 58
8435 00:56:23.687851
8436 00:56:23.687927 Set Vref, RX VrefLevel [Byte0]: 59
8437 00:56:23.690957 [Byte1]: 59
8438 00:56:23.695217
8439 00:56:23.695293 Set Vref, RX VrefLevel [Byte0]: 60
8440 00:56:23.698483 [Byte1]: 60
8441 00:56:23.702926
8442 00:56:23.703002 Set Vref, RX VrefLevel [Byte0]: 61
8443 00:56:23.706146 [Byte1]: 61
8444 00:56:23.710397
8445 00:56:23.710473 Set Vref, RX VrefLevel [Byte0]: 62
8446 00:56:23.713967 [Byte1]: 62
8447 00:56:23.717896
8448 00:56:23.717972 Set Vref, RX VrefLevel [Byte0]: 63
8449 00:56:23.721304 [Byte1]: 63
8450 00:56:23.725898
8451 00:56:23.725974 Set Vref, RX VrefLevel [Byte0]: 64
8452 00:56:23.729345 [Byte1]: 64
8453 00:56:23.733372
8454 00:56:23.733447 Set Vref, RX VrefLevel [Byte0]: 65
8455 00:56:23.736899 [Byte1]: 65
8456 00:56:23.741127
8457 00:56:23.741203 Set Vref, RX VrefLevel [Byte0]: 66
8458 00:56:23.744411 [Byte1]: 66
8459 00:56:23.748962
8460 00:56:23.749038 Set Vref, RX VrefLevel [Byte0]: 67
8461 00:56:23.752045 [Byte1]: 67
8462 00:56:23.756401
8463 00:56:23.756469 Set Vref, RX VrefLevel [Byte0]: 68
8464 00:56:23.759956 [Byte1]: 68
8465 00:56:23.764054
8466 00:56:23.764121 Set Vref, RX VrefLevel [Byte0]: 69
8467 00:56:23.767212 [Byte1]: 69
8468 00:56:23.771467
8469 00:56:23.771533 Set Vref, RX VrefLevel [Byte0]: 70
8470 00:56:23.775058 [Byte1]: 70
8471 00:56:23.779406
8472 00:56:23.779471 Set Vref, RX VrefLevel [Byte0]: 71
8473 00:56:23.782881 [Byte1]: 71
8474 00:56:23.786907
8475 00:56:23.786972 Set Vref, RX VrefLevel [Byte0]: 72
8476 00:56:23.790481 [Byte1]: 72
8477 00:56:23.794549
8478 00:56:23.794611 Set Vref, RX VrefLevel [Byte0]: 73
8479 00:56:23.798118 [Byte1]: 73
8480 00:56:23.802280
8481 00:56:23.802349 Set Vref, RX VrefLevel [Byte0]: 74
8482 00:56:23.805434 [Byte1]: 74
8483 00:56:23.810065
8484 00:56:23.810161 Set Vref, RX VrefLevel [Byte0]: 75
8485 00:56:23.813439 [Byte1]: 75
8486 00:56:23.817463
8487 00:56:23.817527 Set Vref, RX VrefLevel [Byte0]: 76
8488 00:56:23.821127 [Byte1]: 76
8489 00:56:23.825615
8490 00:56:23.825676 Final RX Vref Byte 0 = 60 to rank0
8491 00:56:23.828976 Final RX Vref Byte 1 = 56 to rank0
8492 00:56:23.832111 Final RX Vref Byte 0 = 60 to rank1
8493 00:56:23.835051 Final RX Vref Byte 1 = 56 to rank1==
8494 00:56:23.838294 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 00:56:23.845167 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8496 00:56:23.845241 ==
8497 00:56:23.845299 DQS Delay:
8498 00:56:23.848258 DQS0 = 0, DQS1 = 0
8499 00:56:23.848325 DQM Delay:
8500 00:56:23.848380 DQM0 = 129, DQM1 = 122
8501 00:56:23.852020 DQ Delay:
8502 00:56:23.854959 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8503 00:56:23.858453 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8504 00:56:23.861539 DQ8 =106, DQ9 =112, DQ10 =124, DQ11 =110
8505 00:56:23.864708 DQ12 =132, DQ13 =134, DQ14 =132, DQ15 =132
8506 00:56:23.864773
8507 00:56:23.864829
8508 00:56:23.864883
8509 00:56:23.868276 [DramC_TX_OE_Calibration] TA2
8510 00:56:23.871488 Original DQ_B0 (3 6) =30, OEN = 27
8511 00:56:23.874886 Original DQ_B1 (3 6) =30, OEN = 27
8512 00:56:23.878280 24, 0x0, End_B0=24 End_B1=24
8513 00:56:23.878347 25, 0x0, End_B0=25 End_B1=25
8514 00:56:23.881622 26, 0x0, End_B0=26 End_B1=26
8515 00:56:23.884630 27, 0x0, End_B0=27 End_B1=27
8516 00:56:23.888439 28, 0x0, End_B0=28 End_B1=28
8517 00:56:23.891502 29, 0x0, End_B0=29 End_B1=29
8518 00:56:23.891583 30, 0x0, End_B0=30 End_B1=30
8519 00:56:23.894831 31, 0x4141, End_B0=30 End_B1=30
8520 00:56:23.898160 Byte0 end_step=30 best_step=27
8521 00:56:23.901370 Byte1 end_step=30 best_step=27
8522 00:56:23.904686 Byte0 TX OE(2T, 0.5T) = (3, 3)
8523 00:56:23.907875 Byte1 TX OE(2T, 0.5T) = (3, 3)
8524 00:56:23.907941
8525 00:56:23.907997
8526 00:56:23.914771 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8527 00:56:23.918109 CH1 RK0: MR19=303, MR18=2929
8528 00:56:23.924471 CH1_RK0: MR19=0x303, MR18=0x2929, DQSOSC=389, MR23=63, INC=24, DEC=16
8529 00:56:23.924544
8530 00:56:23.927931 ----->DramcWriteLeveling(PI) begin...
8531 00:56:23.928000 ==
8532 00:56:23.930905 Dram Type= 6, Freq= 0, CH_1, rank 1
8533 00:56:23.934160 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8534 00:56:23.934236 ==
8535 00:56:23.937909 Write leveling (Byte 0): 24 => 24
8536 00:56:23.941116 Write leveling (Byte 1): 22 => 22
8537 00:56:23.944108 DramcWriteLeveling(PI) end<-----
8538 00:56:23.944173
8539 00:56:23.944229 ==
8540 00:56:23.947785 Dram Type= 6, Freq= 0, CH_1, rank 1
8541 00:56:23.950794 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8542 00:56:23.950862 ==
8543 00:56:23.954346 [Gating] SW mode calibration
8544 00:56:23.960715 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8545 00:56:23.967464 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8546 00:56:23.970688 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8547 00:56:23.977887 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8548 00:56:23.980611 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8549 00:56:23.983936 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8550 00:56:23.990613 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8551 00:56:23.993845 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8552 00:56:23.997436 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8553 00:56:24.004050 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8554 00:56:24.007016 0 13 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
8555 00:56:24.010417 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8556 00:56:24.016826 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8557 00:56:24.020316 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8558 00:56:24.023944 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8559 00:56:24.030838 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8560 00:56:24.033651 0 13 24 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8561 00:56:24.037139 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8562 00:56:24.043592 0 14 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8563 00:56:24.047051 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8564 00:56:24.050521 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8565 00:56:24.053709 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8566 00:56:24.060123 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8567 00:56:24.063575 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8568 00:56:24.067081 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8569 00:56:24.073432 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8570 00:56:24.076765 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8571 00:56:24.080109 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 00:56:24.086653 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 00:56:24.089887 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 00:56:24.093312 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 00:56:24.099913 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 00:56:24.103106 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 00:56:24.106444 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 00:56:24.113361 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8579 00:56:24.116662 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8580 00:56:24.119826 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 00:56:24.126665 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 00:56:24.129522 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 00:56:24.133084 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 00:56:24.139649 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8585 00:56:24.142847 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8586 00:56:24.146477 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8587 00:56:24.149593 Total UI for P1: 0, mck2ui 16
8588 00:56:24.153346 best dqsien dly found for B0: ( 1, 0, 26)
8589 00:56:24.159637 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8590 00:56:24.159712 Total UI for P1: 0, mck2ui 16
8591 00:56:24.166577 best dqsien dly found for B1: ( 1, 1, 0)
8592 00:56:24.169691 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8593 00:56:24.173061 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8594 00:56:24.173131
8595 00:56:24.176246 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8596 00:56:24.179778 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8597 00:56:24.182818 [Gating] SW calibration Done
8598 00:56:24.182889 ==
8599 00:56:24.186306 Dram Type= 6, Freq= 0, CH_1, rank 1
8600 00:56:24.189411 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8601 00:56:24.189498 ==
8602 00:56:24.192584 RX Vref Scan: 0
8603 00:56:24.192651
8604 00:56:24.192705 RX Vref 0 -> 0, step: 1
8605 00:56:24.192757
8606 00:56:24.196026 RX Delay 0 -> 252, step: 8
8607 00:56:24.199381 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8608 00:56:24.205936 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8609 00:56:24.209130 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8610 00:56:24.212976 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8611 00:56:24.215933 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8612 00:56:24.219450 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8613 00:56:24.225983 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8614 00:56:24.229327 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8615 00:56:24.232325 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8616 00:56:24.236064 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8617 00:56:24.239228 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8618 00:56:24.245493 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8619 00:56:24.249140 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8620 00:56:24.252181 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8621 00:56:24.255545 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8622 00:56:24.259313 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8623 00:56:24.262358 ==
8624 00:56:24.265594 Dram Type= 6, Freq= 0, CH_1, rank 1
8625 00:56:24.268716 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8626 00:56:24.268795 ==
8627 00:56:24.268873 DQS Delay:
8628 00:56:24.272367 DQS0 = 0, DQS1 = 0
8629 00:56:24.272445 DQM Delay:
8630 00:56:24.275587 DQM0 = 132, DQM1 = 125
8631 00:56:24.275666 DQ Delay:
8632 00:56:24.278681 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8633 00:56:24.282095 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8634 00:56:24.285449 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8635 00:56:24.288696 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8636 00:56:24.288774
8637 00:56:24.288851
8638 00:56:24.288922 ==
8639 00:56:24.292394 Dram Type= 6, Freq= 0, CH_1, rank 1
8640 00:56:24.299173 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8641 00:56:24.299289 ==
8642 00:56:24.299384
8643 00:56:24.299443
8644 00:56:24.299497 TX Vref Scan disable
8645 00:56:24.302315 == TX Byte 0 ==
8646 00:56:24.305905 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8647 00:56:24.309425 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8648 00:56:24.312559 == TX Byte 1 ==
8649 00:56:24.316168 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8650 00:56:24.319390 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8651 00:56:24.322735 ==
8652 00:56:24.326013 Dram Type= 6, Freq= 0, CH_1, rank 1
8653 00:56:24.329108 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8654 00:56:24.329175 ==
8655 00:56:24.340917
8656 00:56:24.344382 TX Vref early break, caculate TX vref
8657 00:56:24.347804 TX Vref=16, minBit 0, minWin=22, winSum=378
8658 00:56:24.351405 TX Vref=18, minBit 0, minWin=23, winSum=388
8659 00:56:24.354219 TX Vref=20, minBit 0, minWin=22, winSum=390
8660 00:56:24.358192 TX Vref=22, minBit 0, minWin=23, winSum=399
8661 00:56:24.361433 TX Vref=24, minBit 0, minWin=24, winSum=408
8662 00:56:24.367770 TX Vref=26, minBit 0, minWin=25, winSum=421
8663 00:56:24.371272 TX Vref=28, minBit 0, minWin=25, winSum=423
8664 00:56:24.374405 TX Vref=30, minBit 0, minWin=23, winSum=417
8665 00:56:24.377757 TX Vref=32, minBit 0, minWin=24, winSum=408
8666 00:56:24.381215 TX Vref=34, minBit 0, minWin=22, winSum=397
8667 00:56:24.387740 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8668 00:56:24.387806
8669 00:56:24.391443 Final TX Range 0 Vref 28
8670 00:56:24.391512
8671 00:56:24.391568 ==
8672 00:56:24.394785 Dram Type= 6, Freq= 0, CH_1, rank 1
8673 00:56:24.397604 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8674 00:56:24.397668 ==
8675 00:56:24.397725
8676 00:56:24.397775
8677 00:56:24.401260 TX Vref Scan disable
8678 00:56:24.407703 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
8679 00:56:24.407770 == TX Byte 0 ==
8680 00:56:24.410808 u2DelayCellOfst[0]=14 cells (4 PI)
8681 00:56:24.414338 u2DelayCellOfst[1]=7 cells (2 PI)
8682 00:56:24.417448 u2DelayCellOfst[2]=0 cells (0 PI)
8683 00:56:24.420852 u2DelayCellOfst[3]=7 cells (2 PI)
8684 00:56:24.424142 u2DelayCellOfst[4]=7 cells (2 PI)
8685 00:56:24.427635 u2DelayCellOfst[5]=18 cells (5 PI)
8686 00:56:24.427714 u2DelayCellOfst[6]=14 cells (4 PI)
8687 00:56:24.431202 u2DelayCellOfst[7]=3 cells (1 PI)
8688 00:56:24.437543 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8689 00:56:24.440982 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8690 00:56:24.441060 == TX Byte 1 ==
8691 00:56:24.444123 u2DelayCellOfst[8]=0 cells (0 PI)
8692 00:56:24.447368 u2DelayCellOfst[9]=7 cells (2 PI)
8693 00:56:24.450578 u2DelayCellOfst[10]=14 cells (4 PI)
8694 00:56:24.454026 u2DelayCellOfst[11]=3 cells (1 PI)
8695 00:56:24.457220 u2DelayCellOfst[12]=18 cells (5 PI)
8696 00:56:24.460574 u2DelayCellOfst[13]=22 cells (6 PI)
8697 00:56:24.464248 u2DelayCellOfst[14]=22 cells (6 PI)
8698 00:56:24.467213 u2DelayCellOfst[15]=18 cells (5 PI)
8699 00:56:24.470763 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8700 00:56:24.477013 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8701 00:56:24.477089 DramC Write-DBI on
8702 00:56:24.477148 ==
8703 00:56:24.480311 Dram Type= 6, Freq= 0, CH_1, rank 1
8704 00:56:24.483753 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8705 00:56:24.483831 ==
8706 00:56:24.487056
8707 00:56:24.487131
8708 00:56:24.487190 TX Vref Scan disable
8709 00:56:24.490357 == TX Byte 0 ==
8710 00:56:24.493820 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8711 00:56:24.496902 == TX Byte 1 ==
8712 00:56:24.500304 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8713 00:56:24.500395 DramC Write-DBI off
8714 00:56:24.503525
8715 00:56:24.503593 [DATLAT]
8716 00:56:24.503648 Freq=1600, CH1 RK1
8717 00:56:24.503701
8718 00:56:24.507121 DATLAT Default: 0xe
8719 00:56:24.507187 0, 0xFFFF, sum = 0
8720 00:56:24.510545 1, 0xFFFF, sum = 0
8721 00:56:24.510613 2, 0xFFFF, sum = 0
8722 00:56:24.513841 3, 0xFFFF, sum = 0
8723 00:56:24.513931 4, 0xFFFF, sum = 0
8724 00:56:24.517263 5, 0xFFFF, sum = 0
8725 00:56:24.517331 6, 0xFFFF, sum = 0
8726 00:56:24.520573 7, 0xFFFF, sum = 0
8727 00:56:24.523590 8, 0xFFFF, sum = 0
8728 00:56:24.523657 9, 0xFFFF, sum = 0
8729 00:56:24.526982 10, 0xFFFF, sum = 0
8730 00:56:24.527049 11, 0xFFFF, sum = 0
8731 00:56:24.530359 12, 0xF7F, sum = 0
8732 00:56:24.530441 13, 0x0, sum = 1
8733 00:56:24.533730 14, 0x0, sum = 2
8734 00:56:24.533793 15, 0x0, sum = 3
8735 00:56:24.536965 16, 0x0, sum = 4
8736 00:56:24.537028 best_step = 14
8737 00:56:24.537084
8738 00:56:24.537137 ==
8739 00:56:24.540421 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 00:56:24.544052 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8741 00:56:24.544112 ==
8742 00:56:24.546771 RX Vref Scan: 0
8743 00:56:24.546831
8744 00:56:24.550509 RX Vref 0 -> 0, step: 1
8745 00:56:24.550569
8746 00:56:24.550620 RX Delay 3 -> 252, step: 4
8747 00:56:24.557286 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8748 00:56:24.560836 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8749 00:56:24.563670 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8750 00:56:24.566935 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8751 00:56:24.570440 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8752 00:56:24.577235 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8753 00:56:24.580568 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8754 00:56:24.583752 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8755 00:56:24.587076 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8756 00:56:24.590413 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8757 00:56:24.597138 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8758 00:56:24.599995 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8759 00:56:24.603600 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8760 00:56:24.606642 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8761 00:56:24.613146 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8762 00:56:24.616457 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8763 00:56:24.616535 ==
8764 00:56:24.619995 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 00:56:24.623517 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8766 00:56:24.623598 ==
8767 00:56:24.627199 DQS Delay:
8768 00:56:24.627278 DQS0 = 0, DQS1 = 0
8769 00:56:24.627339 DQM Delay:
8770 00:56:24.630097 DQM0 = 127, DQM1 = 122
8771 00:56:24.630197 DQ Delay:
8772 00:56:24.633299 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8773 00:56:24.636469 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8774 00:56:24.639648 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8775 00:56:24.646508 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8776 00:56:24.646608
8777 00:56:24.646693
8778 00:56:24.646775
8779 00:56:24.649827 [DramC_TX_OE_Calibration] TA2
8780 00:56:24.653749 Original DQ_B0 (3 6) =30, OEN = 27
8781 00:56:24.653842 Original DQ_B1 (3 6) =30, OEN = 27
8782 00:56:24.656540 24, 0x0, End_B0=24 End_B1=24
8783 00:56:24.659979 25, 0x0, End_B0=25 End_B1=25
8784 00:56:24.662961 26, 0x0, End_B0=26 End_B1=26
8785 00:56:24.666411 27, 0x0, End_B0=27 End_B1=27
8786 00:56:24.666489 28, 0x0, End_B0=28 End_B1=28
8787 00:56:24.669792 29, 0x0, End_B0=29 End_B1=29
8788 00:56:24.673299 30, 0x0, End_B0=30 End_B1=30
8789 00:56:24.676348 31, 0x4141, End_B0=30 End_B1=30
8790 00:56:24.679900 Byte0 end_step=30 best_step=27
8791 00:56:24.680000 Byte1 end_step=30 best_step=27
8792 00:56:24.683180 Byte0 TX OE(2T, 0.5T) = (3, 3)
8793 00:56:24.686489 Byte1 TX OE(2T, 0.5T) = (3, 3)
8794 00:56:24.686567
8795 00:56:24.686626
8796 00:56:24.696338 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8797 00:56:24.696417 CH1 RK1: MR19=303, MR18=1D1D
8798 00:56:24.702796 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8799 00:56:24.706116 [RxdqsGatingPostProcess] freq 1600
8800 00:56:24.712904 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8801 00:56:24.715947 Pre-setting of DQS Precalculation
8802 00:56:24.719505 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8803 00:56:24.729355 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8804 00:56:24.736202 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8805 00:56:24.736280
8806 00:56:24.736340
8807 00:56:24.739423 [Calibration Summary] 3200 Mbps
8808 00:56:24.739500 CH 0, Rank 0
8809 00:56:24.742788 SW Impedance : PASS
8810 00:56:24.742865 DUTY Scan : NO K
8811 00:56:24.746108 ZQ Calibration : PASS
8812 00:56:24.749267 Jitter Meter : NO K
8813 00:56:24.749372 CBT Training : PASS
8814 00:56:24.752621 Write leveling : PASS
8815 00:56:24.755970 RX DQS gating : PASS
8816 00:56:24.756048 RX DQ/DQS(RDDQC) : PASS
8817 00:56:24.759242 TX DQ/DQS : PASS
8818 00:56:24.759319 RX DATLAT : PASS
8819 00:56:24.762502 RX DQ/DQS(Engine): PASS
8820 00:56:24.766059 TX OE : PASS
8821 00:56:24.766136 All Pass.
8822 00:56:24.766196
8823 00:56:24.768983 CH 0, Rank 1
8824 00:56:24.769060 SW Impedance : PASS
8825 00:56:24.772585 DUTY Scan : NO K
8826 00:56:24.772663 ZQ Calibration : PASS
8827 00:56:24.775623 Jitter Meter : NO K
8828 00:56:24.778990 CBT Training : PASS
8829 00:56:24.779068 Write leveling : PASS
8830 00:56:24.782575 RX DQS gating : PASS
8831 00:56:24.785776 RX DQ/DQS(RDDQC) : PASS
8832 00:56:24.785853 TX DQ/DQS : PASS
8833 00:56:24.789282 RX DATLAT : PASS
8834 00:56:24.792135 RX DQ/DQS(Engine): PASS
8835 00:56:24.792212 TX OE : PASS
8836 00:56:24.795862 All Pass.
8837 00:56:24.795938
8838 00:56:24.795997 CH 1, Rank 0
8839 00:56:24.799158 SW Impedance : PASS
8840 00:56:24.799235 DUTY Scan : NO K
8841 00:56:24.802440 ZQ Calibration : PASS
8842 00:56:24.805403 Jitter Meter : NO K
8843 00:56:24.805481 CBT Training : PASS
8844 00:56:24.808919 Write leveling : PASS
8845 00:56:24.812176 RX DQS gating : PASS
8846 00:56:24.812253 RX DQ/DQS(RDDQC) : PASS
8847 00:56:24.815789 TX DQ/DQS : PASS
8848 00:56:24.819093 RX DATLAT : PASS
8849 00:56:24.819171 RX DQ/DQS(Engine): PASS
8850 00:56:24.822085 TX OE : PASS
8851 00:56:24.822186 All Pass.
8852 00:56:24.822296
8853 00:56:24.825826 CH 1, Rank 1
8854 00:56:24.825925 SW Impedance : PASS
8855 00:56:24.828732 DUTY Scan : NO K
8856 00:56:24.828809 ZQ Calibration : PASS
8857 00:56:24.832093 Jitter Meter : NO K
8858 00:56:24.835812 CBT Training : PASS
8859 00:56:24.835890 Write leveling : PASS
8860 00:56:24.838863 RX DQS gating : PASS
8861 00:56:24.842580 RX DQ/DQS(RDDQC) : PASS
8862 00:56:24.842657 TX DQ/DQS : PASS
8863 00:56:24.845822 RX DATLAT : PASS
8864 00:56:24.848764 RX DQ/DQS(Engine): PASS
8865 00:56:24.848842 TX OE : PASS
8866 00:56:24.852279 All Pass.
8867 00:56:24.852355
8868 00:56:24.852414 DramC Write-DBI on
8869 00:56:24.855304 PER_BANK_REFRESH: Hybrid Mode
8870 00:56:24.855381 TX_TRACKING: ON
8871 00:56:24.865285 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8872 00:56:24.875741 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8873 00:56:24.882174 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8874 00:56:24.885522 [FAST_K] Save calibration result to emmc
8875 00:56:24.888601 sync common calibartion params.
8876 00:56:24.888678 sync cbt_mode0:0, 1:0
8877 00:56:24.892045 dram_init: ddr_geometry: 0
8878 00:56:24.895355 dram_init: ddr_geometry: 0
8879 00:56:24.895432 dram_init: ddr_geometry: 0
8880 00:56:24.898967 0:dram_rank_size:80000000
8881 00:56:24.902164 1:dram_rank_size:80000000
8882 00:56:24.905432 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8883 00:56:24.908736 DFS_SHUFFLE_HW_MODE: ON
8884 00:56:24.911635 dramc_set_vcore_voltage set vcore to 725000
8885 00:56:24.915077 Read voltage for 1600, 0
8886 00:56:24.915153 Vio18 = 0
8887 00:56:24.918250 Vcore = 725000
8888 00:56:24.918342 Vdram = 0
8889 00:56:24.918402 Vddq = 0
8890 00:56:24.922045 Vmddr = 0
8891 00:56:24.922121 switch to 3200 Mbps bootup
8892 00:56:24.924902 [DramcRunTimeConfig]
8893 00:56:24.924978 PHYPLL
8894 00:56:24.928127 DPM_CONTROL_AFTERK: ON
8895 00:56:24.928204 PER_BANK_REFRESH: ON
8896 00:56:24.931492 REFRESH_OVERHEAD_REDUCTION: ON
8897 00:56:24.934669 CMD_PICG_NEW_MODE: OFF
8898 00:56:24.934746 XRTWTW_NEW_MODE: ON
8899 00:56:24.938117 XRTRTR_NEW_MODE: ON
8900 00:56:24.938193 TX_TRACKING: ON
8901 00:56:24.941996 RDSEL_TRACKING: OFF
8902 00:56:24.944855 DQS Precalculation for DVFS: ON
8903 00:56:24.944932 RX_TRACKING: OFF
8904 00:56:24.948193 HW_GATING DBG: ON
8905 00:56:24.948270 ZQCS_ENABLE_LP4: ON
8906 00:56:24.951750 RX_PICG_NEW_MODE: ON
8907 00:56:24.951828 TX_PICG_NEW_MODE: ON
8908 00:56:24.955073 ENABLE_RX_DCM_DPHY: ON
8909 00:56:24.958399 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8910 00:56:24.961441 DUMMY_READ_FOR_TRACKING: OFF
8911 00:56:24.961518 !!! SPM_CONTROL_AFTERK: OFF
8912 00:56:24.964963 !!! SPM could not control APHY
8913 00:56:24.967941 IMPEDANCE_TRACKING: ON
8914 00:56:24.968018 TEMP_SENSOR: ON
8915 00:56:24.971495 HW_SAVE_FOR_SR: OFF
8916 00:56:24.974920 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8917 00:56:24.978168 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8918 00:56:24.978281 Read ODT Tracking: ON
8919 00:56:24.981578 Refresh Rate DeBounce: ON
8920 00:56:24.984763 DFS_NO_QUEUE_FLUSH: ON
8921 00:56:24.987935 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8922 00:56:24.988012 ENABLE_DFS_RUNTIME_MRW: OFF
8923 00:56:24.990940 DDR_RESERVE_NEW_MODE: ON
8924 00:56:24.994395 MR_CBT_SWITCH_FREQ: ON
8925 00:56:24.994472 =========================
8926 00:56:25.015077 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8927 00:56:25.017924 dram_init: ddr_geometry: 0
8928 00:56:25.035810 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8929 00:56:25.039261 dram_init: dram init end (result: 0)
8930 00:56:25.046215 DRAM-K: Full calibration passed in 23420 msecs
8931 00:56:25.049176 MRC: failed to locate region type 0.
8932 00:56:25.049253 DRAM rank0 size:0x80000000,
8933 00:56:25.052442 DRAM rank1 size=0x80000000
8934 00:56:25.062500 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8935 00:56:25.069071 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8936 00:56:25.076191 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8937 00:56:25.082902 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8938 00:56:25.086103 DRAM rank0 size:0x80000000,
8939 00:56:25.088954 DRAM rank1 size=0x80000000
8940 00:56:25.089030 CBMEM:
8941 00:56:25.092594 IMD: root @ 0xfffff000 254 entries.
8942 00:56:25.095633 IMD: root @ 0xffffec00 62 entries.
8943 00:56:25.099048 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8944 00:56:25.102590 WARNING: RO_VPD is uninitialized or empty.
8945 00:56:25.109104 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8946 00:56:25.115844 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8947 00:56:25.128556 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
8948 00:56:25.140122 BS: romstage times (exec / console): total (unknown) / 22957 ms
8949 00:56:25.140201
8950 00:56:25.140261
8951 00:56:25.150236 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8952 00:56:25.153334 ARM64: Exception handlers installed.
8953 00:56:25.156322 ARM64: Testing exception
8954 00:56:25.159934 ARM64: Done test exception
8955 00:56:25.160011 Enumerating buses...
8956 00:56:25.163061 Show all devs... Before device enumeration.
8957 00:56:25.166238 Root Device: enabled 1
8958 00:56:25.169394 CPU_CLUSTER: 0: enabled 1
8959 00:56:25.169471 CPU: 00: enabled 1
8960 00:56:25.173278 Compare with tree...
8961 00:56:25.173355 Root Device: enabled 1
8962 00:56:25.176422 CPU_CLUSTER: 0: enabled 1
8963 00:56:25.179548 CPU: 00: enabled 1
8964 00:56:25.179625 Root Device scanning...
8965 00:56:25.182666 scan_static_bus for Root Device
8966 00:56:25.186124 CPU_CLUSTER: 0 enabled
8967 00:56:25.189460 scan_static_bus for Root Device done
8968 00:56:25.192727 scan_bus: bus Root Device finished in 8 msecs
8969 00:56:25.192805 done
8970 00:56:25.199279 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8971 00:56:25.202572 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8972 00:56:25.209079 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8973 00:56:25.212775 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8974 00:56:25.215812 Allocating resources...
8975 00:56:25.219279 Reading resources...
8976 00:56:25.222734 Root Device read_resources bus 0 link: 0
8977 00:56:25.222812 DRAM rank0 size:0x80000000,
8978 00:56:25.226099 DRAM rank1 size=0x80000000
8979 00:56:25.229261 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8980 00:56:25.232741 CPU: 00 missing read_resources
8981 00:56:25.239133 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8982 00:56:25.242409 Root Device read_resources bus 0 link: 0 done
8983 00:56:25.242486 Done reading resources.
8984 00:56:25.249335 Show resources in subtree (Root Device)...After reading.
8985 00:56:25.252515 Root Device child on link 0 CPU_CLUSTER: 0
8986 00:56:25.255618 CPU_CLUSTER: 0 child on link 0 CPU: 00
8987 00:56:25.265685 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8988 00:56:25.265763 CPU: 00
8989 00:56:25.268859 Root Device assign_resources, bus 0 link: 0
8990 00:56:25.272471 CPU_CLUSTER: 0 missing set_resources
8991 00:56:25.279002 Root Device assign_resources, bus 0 link: 0 done
8992 00:56:25.279079 Done setting resources.
8993 00:56:25.285298 Show resources in subtree (Root Device)...After assigning values.
8994 00:56:25.288962 Root Device child on link 0 CPU_CLUSTER: 0
8995 00:56:25.292460 CPU_CLUSTER: 0 child on link 0 CPU: 00
8996 00:56:25.301814 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8997 00:56:25.301893 CPU: 00
8998 00:56:25.305325 Done allocating resources.
8999 00:56:25.311831 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9000 00:56:25.311908 Enabling resources...
9001 00:56:25.311968 done.
9002 00:56:25.318385 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9003 00:56:25.318462 Initializing devices...
9004 00:56:25.321685 Root Device init
9005 00:56:25.321761 init hardware done!
9006 00:56:25.324945 0x00000018: ctrlr->caps
9007 00:56:25.328593 52.000 MHz: ctrlr->f_max
9008 00:56:25.328672 0.400 MHz: ctrlr->f_min
9009 00:56:25.331499 0x40ff8080: ctrlr->voltages
9010 00:56:25.335057 sclk: 390625
9011 00:56:25.335156 Bus Width = 1
9012 00:56:25.335218 sclk: 390625
9013 00:56:25.338545 Bus Width = 1
9014 00:56:25.338622 Early init status = 3
9015 00:56:25.344908 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9016 00:56:25.348077 in-header: 03 fc 00 00 01 00 00 00
9017 00:56:25.352046 in-data: 00
9018 00:56:25.354828 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9019 00:56:25.358453 in-header: 03 fd 00 00 00 00 00 00
9020 00:56:25.362136 in-data:
9021 00:56:25.365534 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9022 00:56:25.368333 in-header: 03 fc 00 00 01 00 00 00
9023 00:56:25.371681 in-data: 00
9024 00:56:25.374941 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9025 00:56:25.379795 in-header: 03 fd 00 00 00 00 00 00
9026 00:56:25.382978 in-data:
9027 00:56:25.386501 [SSUSB] Setting up USB HOST controller...
9028 00:56:25.389955 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9029 00:56:25.393232 [SSUSB] phy power-on done.
9030 00:56:25.396832 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9031 00:56:25.402909 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9032 00:56:25.406365 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9033 00:56:25.412792 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9034 00:56:25.419864 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9035 00:56:25.426121 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9036 00:56:25.432749 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9037 00:56:25.439509 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9038 00:56:25.442442 SPM: binary array size = 0x9dc
9039 00:56:25.445736 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9040 00:56:25.452285 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9041 00:56:25.458950 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9042 00:56:25.465677 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9043 00:56:25.468809 configure_display: Starting display init
9044 00:56:25.503329 anx7625_power_on_init: Init interface.
9045 00:56:25.506107 anx7625_disable_pd_protocol: Disabled PD feature.
9046 00:56:25.509605 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9047 00:56:25.537608 anx7625_start_dp_work: Secure OCM version=00
9048 00:56:25.540583 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9049 00:56:25.555651 sp_tx_get_edid_block: EDID Block = 1
9050 00:56:25.657976 Extracted contents:
9051 00:56:25.661292 header: 00 ff ff ff ff ff ff 00
9052 00:56:25.664558 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9053 00:56:25.668355 version: 01 04
9054 00:56:25.671184 basic params: 95 1f 11 78 0a
9055 00:56:25.674812 chroma info: 76 90 94 55 54 90 27 21 50 54
9056 00:56:25.678082 established: 00 00 00
9057 00:56:25.684673 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9058 00:56:25.688038 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9059 00:56:25.694435 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9060 00:56:25.700954 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9061 00:56:25.707902 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9062 00:56:25.711095 extensions: 00
9063 00:56:25.711173 checksum: fb
9064 00:56:25.711233
9065 00:56:25.714604 Manufacturer: IVO Model 57d Serial Number 0
9066 00:56:25.717488 Made week 0 of 2020
9067 00:56:25.717600 EDID version: 1.4
9068 00:56:25.720778 Digital display
9069 00:56:25.724377 6 bits per primary color channel
9070 00:56:25.724495 DisplayPort interface
9071 00:56:25.727776 Maximum image size: 31 cm x 17 cm
9072 00:56:25.730818 Gamma: 220%
9073 00:56:25.730926 Check DPMS levels
9074 00:56:25.734382 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9075 00:56:25.740680 First detailed timing is preferred timing
9076 00:56:25.740758 Established timings supported:
9077 00:56:25.744308 Standard timings supported:
9078 00:56:25.747810 Detailed timings
9079 00:56:25.750822 Hex of detail: 383680a07038204018303c0035ae10000019
9080 00:56:25.754408 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9081 00:56:25.760967 0780 0798 07c8 0820 hborder 0
9082 00:56:25.764174 0438 043b 0447 0458 vborder 0
9083 00:56:25.767514 -hsync -vsync
9084 00:56:25.767590 Did detailed timing
9085 00:56:25.770924 Hex of detail: 000000000000000000000000000000000000
9086 00:56:25.774435 Manufacturer-specified data, tag 0
9087 00:56:25.781062 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9088 00:56:25.781141 ASCII string: InfoVision
9089 00:56:25.787541 Hex of detail: 000000fe00523134304e574635205248200a
9090 00:56:25.791018 ASCII string: R140NWF5 RH
9091 00:56:25.791095 Checksum
9092 00:56:25.791155 Checksum: 0xfb (valid)
9093 00:56:25.797498 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9094 00:56:25.800888 DSI data_rate: 832800000 bps
9095 00:56:25.804078 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9096 00:56:25.810952 anx7625_parse_edid: pixelclock(138800).
9097 00:56:25.814302 hactive(1920), hsync(48), hfp(24), hbp(88)
9098 00:56:25.817299 vactive(1080), vsync(12), vfp(3), vbp(17)
9099 00:56:25.820911 anx7625_dsi_config: config dsi.
9100 00:56:25.827159 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9101 00:56:25.840159 anx7625_dsi_config: success to config DSI
9102 00:56:25.843280 anx7625_dp_start: MIPI phy setup OK.
9103 00:56:25.846759 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9104 00:56:25.850252 mtk_ddp_mode_set invalid vrefresh 60
9105 00:56:25.853560 main_disp_path_setup
9106 00:56:25.853655 ovl_layer_smi_id_en
9107 00:56:25.856637 ovl_layer_smi_id_en
9108 00:56:25.856728 ccorr_config
9109 00:56:25.856811 aal_config
9110 00:56:25.860519 gamma_config
9111 00:56:25.860619 postmask_config
9112 00:56:25.863556 dither_config
9113 00:56:25.866745 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9114 00:56:25.873567 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9115 00:56:25.876674 Root Device init finished in 551 msecs
9116 00:56:25.876746 CPU_CLUSTER: 0 init
9117 00:56:25.886685 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9118 00:56:25.890194 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9119 00:56:25.893212 APU_MBOX 0x190000b0 = 0x10001
9120 00:56:25.896421 APU_MBOX 0x190001b0 = 0x10001
9121 00:56:25.899946 APU_MBOX 0x190005b0 = 0x10001
9122 00:56:25.903154 APU_MBOX 0x190006b0 = 0x10001
9123 00:56:25.906655 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9124 00:56:25.919152 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9125 00:56:25.931539 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9126 00:56:25.937953 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9127 00:56:25.949620 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9128 00:56:25.959079 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9129 00:56:25.962075 CPU_CLUSTER: 0 init finished in 81 msecs
9130 00:56:25.965396 Devices initialized
9131 00:56:25.968433 Show all devs... After init.
9132 00:56:25.968511 Root Device: enabled 1
9133 00:56:25.972044 CPU_CLUSTER: 0: enabled 1
9134 00:56:25.975575 CPU: 00: enabled 1
9135 00:56:25.978725 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9136 00:56:25.982333 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9137 00:56:25.985356 ELOG: NV offset 0x57f000 size 0x1000
9138 00:56:25.992351 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9139 00:56:25.998434 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9140 00:56:26.001906 ELOG: Event(17) added with size 13 at 2024-06-16 00:56:26 UTC
9141 00:56:26.005224 out: cmd=0x121: 03 db 21 01 00 00 00 00
9142 00:56:26.009173 in-header: 03 2e 00 00 2c 00 00 00
9143 00:56:26.022023 in-data: 14 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9144 00:56:26.029213 ELOG: Event(A1) added with size 10 at 2024-06-16 00:56:26 UTC
9145 00:56:26.035384 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9146 00:56:26.042170 ELOG: Event(A0) added with size 9 at 2024-06-16 00:56:26 UTC
9147 00:56:26.045639 elog_add_boot_reason: Logged dev mode boot
9148 00:56:26.048938 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9149 00:56:26.052052 Finalize devices...
9150 00:56:26.052130 Devices finalized
9151 00:56:26.058585 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9152 00:56:26.062197 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9153 00:56:26.065527 in-header: 03 07 00 00 08 00 00 00
9154 00:56:26.068755 in-data: aa e4 47 04 13 02 00 00
9155 00:56:26.068831 Chrome EC: UHEPI supported
9156 00:56:26.075314 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9157 00:56:26.079188 in-header: 03 a9 00 00 08 00 00 00
9158 00:56:26.082477 in-data: 84 60 60 08 00 00 00 00
9159 00:56:26.089034 ELOG: Event(91) added with size 10 at 2024-06-16 00:56:26 UTC
9160 00:56:26.092776 Chrome EC: clear events_b mask to 0x0000000020004000
9161 00:56:26.098935 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9162 00:56:26.103665 in-header: 03 fd 00 00 00 00 00 00
9163 00:56:26.106898 in-data:
9164 00:56:26.110397 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9165 00:56:26.113643 Writing coreboot table at 0xffe64000
9166 00:56:26.117207 0. 000000000010a000-0000000000113fff: RAMSTAGE
9167 00:56:26.123553 1. 0000000040000000-00000000400fffff: RAM
9168 00:56:26.127319 2. 0000000040100000-000000004032afff: RAMSTAGE
9169 00:56:26.130440 3. 000000004032b000-00000000545fffff: RAM
9170 00:56:26.133647 4. 0000000054600000-000000005465ffff: BL31
9171 00:56:26.137101 5. 0000000054660000-00000000ffe63fff: RAM
9172 00:56:26.143609 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9173 00:56:26.146774 7. 0000000100000000-000000013fffffff: RAM
9174 00:56:26.150242 Passing 5 GPIOs to payload:
9175 00:56:26.153717 NAME | PORT | POLARITY | VALUE
9176 00:56:26.160311 EC in RW | 0x000000aa | low | undefined
9177 00:56:26.163500 EC interrupt | 0x00000005 | low | undefined
9178 00:56:26.167033 TPM interrupt | 0x000000ab | high | undefined
9179 00:56:26.173831 SD card detect | 0x00000011 | high | undefined
9180 00:56:26.176969 speaker enable | 0x00000093 | high | undefined
9181 00:56:26.180064 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9182 00:56:26.183259 in-header: 03 f8 00 00 02 00 00 00
9183 00:56:26.186911 in-data: 03 00
9184 00:56:26.190187 ADC[4]: Raw value=668590 ID=5
9185 00:56:26.190289 ADC[3]: Raw value=212549 ID=1
9186 00:56:26.193950 RAM Code: 0x51
9187 00:56:26.196619 ADC[6]: Raw value=74778 ID=0
9188 00:56:26.196688 ADC[5]: Raw value=211444 ID=1
9189 00:56:26.199951 SKU Code: 0x1
9190 00:56:26.206597 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7daf
9191 00:56:26.206675 coreboot table: 964 bytes.
9192 00:56:26.210089 IMD ROOT 0. 0xfffff000 0x00001000
9193 00:56:26.213135 IMD SMALL 1. 0xffffe000 0x00001000
9194 00:56:26.216458 RO MCACHE 2. 0xffffc000 0x00001104
9195 00:56:26.219736 CONSOLE 3. 0xfff7c000 0x00080000
9196 00:56:26.223006 FMAP 4. 0xfff7b000 0x00000452
9197 00:56:26.226207 TIME STAMP 5. 0xfff7a000 0x00000910
9198 00:56:26.229758 VBOOT WORK 6. 0xfff66000 0x00014000
9199 00:56:26.232981 RAMOOPS 7. 0xffe66000 0x00100000
9200 00:56:26.236328 COREBOOT 8. 0xffe64000 0x00002000
9201 00:56:26.239517 IMD small region:
9202 00:56:26.243197 IMD ROOT 0. 0xffffec00 0x00000400
9203 00:56:26.246643 VPD 1. 0xffffeb80 0x0000006c
9204 00:56:26.249672 MMC STATUS 2. 0xffffeb60 0x00000004
9205 00:56:26.253131 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9206 00:56:26.259309 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9207 00:56:26.300871 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9208 00:56:26.304189 Checking segment from ROM address 0x40100000
9209 00:56:26.307417 Checking segment from ROM address 0x4010001c
9210 00:56:26.313947 Loading segment from ROM address 0x40100000
9211 00:56:26.314024 code (compression=0)
9212 00:56:26.324028 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9213 00:56:26.330650 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9214 00:56:26.330727 it's not compressed!
9215 00:56:26.337414 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9216 00:56:26.340833 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9217 00:56:26.361135 Loading segment from ROM address 0x4010001c
9218 00:56:26.361213 Entry Point 0x80000000
9219 00:56:26.364533 Loaded segments
9220 00:56:26.367972 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9221 00:56:26.374408 Jumping to boot code at 0x80000000(0xffe64000)
9222 00:56:26.381100 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9223 00:56:26.387905 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9224 00:56:26.395254 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9225 00:56:26.398948 Checking segment from ROM address 0x40100000
9226 00:56:26.402341 Checking segment from ROM address 0x4010001c
9227 00:56:26.408787 Loading segment from ROM address 0x40100000
9228 00:56:26.408864 code (compression=1)
9229 00:56:26.415377 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9230 00:56:26.425238 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9231 00:56:26.425315 using LZMA
9232 00:56:26.433908 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9233 00:56:26.440354 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9234 00:56:26.443956 Loading segment from ROM address 0x4010001c
9235 00:56:26.444033 Entry Point 0x54601000
9236 00:56:26.447286 Loaded segments
9237 00:56:26.450473 NOTICE: MT8192 bl31_setup
9238 00:56:26.457246 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9239 00:56:26.460611 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9240 00:56:26.464109 WARNING: region 0:
9241 00:56:26.467416 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9242 00:56:26.467493 WARNING: region 1:
9243 00:56:26.473977 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9244 00:56:26.477280 WARNING: region 2:
9245 00:56:26.480631 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9246 00:56:26.484218 WARNING: region 3:
9247 00:56:26.487441 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9248 00:56:26.491109 WARNING: region 4:
9249 00:56:26.494251 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9250 00:56:26.498083 WARNING: region 5:
9251 00:56:26.501205 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9252 00:56:26.504629 WARNING: region 6:
9253 00:56:26.507613 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9254 00:56:26.507689 WARNING: region 7:
9255 00:56:26.514459 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9256 00:56:26.520897 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9257 00:56:26.524109 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9258 00:56:26.527389 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9259 00:56:26.534196 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9260 00:56:26.537689 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9261 00:56:26.541153 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9262 00:56:26.547429 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9263 00:56:26.550941 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9264 00:56:26.557377 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9265 00:56:26.560668 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9266 00:56:26.564106 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9267 00:56:26.570473 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9268 00:56:26.574013 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9269 00:56:26.577560 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9270 00:56:26.583972 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9271 00:56:26.587536 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9272 00:56:26.594443 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9273 00:56:26.597173 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9274 00:56:26.600870 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9275 00:56:26.607138 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9276 00:56:26.610423 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9277 00:56:26.613881 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9278 00:56:26.620796 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9279 00:56:26.623894 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9280 00:56:26.630251 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9281 00:56:26.633977 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9282 00:56:26.637144 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9283 00:56:26.644288 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9284 00:56:26.647191 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9285 00:56:26.653592 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9286 00:56:26.656944 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9287 00:56:26.660403 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9288 00:56:26.667346 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9289 00:56:26.670564 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9290 00:56:26.673875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9291 00:56:26.676894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9292 00:56:26.683891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9293 00:56:26.687420 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9294 00:56:26.690416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9295 00:56:26.694005 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9296 00:56:26.700235 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9297 00:56:26.703598 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9298 00:56:26.706882 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9299 00:56:26.710149 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9300 00:56:26.716715 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9301 00:56:26.720437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9302 00:56:26.723430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9303 00:56:26.726834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9304 00:56:26.733690 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9305 00:56:26.737115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9306 00:56:26.743210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9307 00:56:26.746997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9308 00:56:26.753314 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9309 00:56:26.756685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9310 00:56:26.760093 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9311 00:56:26.766948 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9312 00:56:26.769909 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9313 00:56:26.776546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9314 00:56:26.780151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9315 00:56:26.786794 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9316 00:56:26.789877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9317 00:56:26.796554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9318 00:56:26.799972 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9319 00:56:26.803424 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9320 00:56:26.810139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9321 00:56:26.812909 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9322 00:56:26.820082 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9323 00:56:26.823396 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9324 00:56:26.829874 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9325 00:56:26.832885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9326 00:56:26.839697 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9327 00:56:26.842784 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9328 00:56:26.846245 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9329 00:56:26.853006 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9330 00:56:26.856269 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9331 00:56:26.862733 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9332 00:56:26.866034 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9333 00:56:26.873115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9334 00:56:26.876708 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9335 00:56:26.879519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9336 00:56:26.886353 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9337 00:56:26.889857 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9338 00:56:26.896262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9339 00:56:26.899796 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9340 00:56:26.906426 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9341 00:56:26.909310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9342 00:56:26.912932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9343 00:56:26.919282 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9344 00:56:26.922624 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9345 00:56:26.929166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9346 00:56:26.932865 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9347 00:56:26.939473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9348 00:56:26.942909 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9349 00:56:26.949196 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9350 00:56:26.952997 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9351 00:56:26.956202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9352 00:56:26.962850 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9353 00:56:26.966165 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9354 00:56:26.969405 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9355 00:56:26.972947 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9356 00:56:26.979329 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9357 00:56:26.983055 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9358 00:56:26.986241 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9359 00:56:26.992760 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9360 00:56:26.996060 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9361 00:56:27.002762 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9362 00:56:27.005889 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9363 00:56:27.009165 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9364 00:56:27.015996 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9365 00:56:27.019062 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9366 00:56:27.025674 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9367 00:56:27.029573 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9368 00:56:27.032775 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9369 00:56:27.039398 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9370 00:56:27.042452 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9371 00:56:27.049104 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9372 00:56:27.052348 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9373 00:56:27.056070 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9374 00:56:27.062846 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9375 00:56:27.066047 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9376 00:56:27.069320 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9377 00:56:27.072612 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9378 00:56:27.075832 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9379 00:56:27.082539 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9380 00:56:27.086162 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9381 00:56:27.093041 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9382 00:56:27.095849 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9383 00:56:27.098953 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9384 00:56:27.105637 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9385 00:56:27.109121 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9386 00:56:27.112991 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9387 00:56:27.119193 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9388 00:56:27.122242 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9389 00:56:27.129042 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9390 00:56:27.132404 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9391 00:56:27.135825 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9392 00:56:27.142325 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9393 00:56:27.145847 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9394 00:56:27.152748 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9395 00:56:27.155483 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9396 00:56:27.159155 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9397 00:56:27.166088 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9398 00:56:27.169021 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9399 00:56:27.175606 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9400 00:56:27.178832 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9401 00:56:27.182156 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9402 00:56:27.188712 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9403 00:56:27.192067 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9404 00:56:27.198738 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9405 00:56:27.202224 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9406 00:56:27.205557 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9407 00:56:27.212012 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9408 00:56:27.215335 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9409 00:56:27.219144 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9410 00:56:27.225572 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9411 00:56:27.228850 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9412 00:56:27.235286 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9413 00:56:27.238525 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9414 00:56:27.242086 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9415 00:56:27.248558 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9416 00:56:27.252037 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9417 00:56:27.258819 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9418 00:56:27.261970 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9419 00:56:27.265651 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9420 00:56:27.272119 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9421 00:56:27.275135 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9422 00:56:27.278680 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9423 00:56:27.284976 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9424 00:56:27.288682 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9425 00:56:27.294890 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9426 00:56:27.298223 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9427 00:56:27.305222 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9428 00:56:27.308582 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9429 00:56:27.311404 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9430 00:56:27.318422 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9431 00:56:27.321460 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9432 00:56:27.324913 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9433 00:56:27.331572 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9434 00:56:27.334849 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9435 00:56:27.341615 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9436 00:56:27.344892 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9437 00:56:27.348403 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9438 00:56:27.355041 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9439 00:56:27.358376 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9440 00:56:27.364806 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9441 00:56:27.367890 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9442 00:56:27.371279 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9443 00:56:27.378343 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9444 00:56:27.381337 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9445 00:56:27.388117 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9446 00:56:27.391306 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9447 00:56:27.394793 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9448 00:56:27.401481 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9449 00:56:27.404575 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9450 00:56:27.411541 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9451 00:56:27.414878 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9452 00:56:27.417909 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9453 00:56:27.424470 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9454 00:56:27.428139 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9455 00:56:27.434455 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9456 00:56:27.438247 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9457 00:56:27.441607 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9458 00:56:27.447862 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9459 00:56:27.451436 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9460 00:56:27.457808 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9461 00:56:27.461414 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9462 00:56:27.467922 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9463 00:56:27.471040 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9464 00:56:27.474383 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9465 00:56:27.480943 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9466 00:56:27.484536 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9467 00:56:27.491205 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9468 00:56:27.494854 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9469 00:56:27.501571 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9470 00:56:27.504665 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9471 00:56:27.507736 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9472 00:56:27.514376 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9473 00:56:27.517685 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9474 00:56:27.524326 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9475 00:56:27.527589 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9476 00:56:27.530771 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9477 00:56:27.537530 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9478 00:56:27.540977 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9479 00:56:27.547377 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9480 00:56:27.551106 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9481 00:56:27.557732 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9482 00:56:27.561131 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9483 00:56:27.564241 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9484 00:56:27.570620 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9485 00:56:27.573981 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9486 00:56:27.577724 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9487 00:56:27.580925 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9488 00:56:27.587440 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9489 00:56:27.590933 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9490 00:56:27.594106 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9491 00:56:27.600769 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9492 00:56:27.604195 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9493 00:56:27.607223 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9494 00:56:27.613907 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9495 00:56:27.617508 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9496 00:56:27.620563 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9497 00:56:27.627499 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9498 00:56:27.630600 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9499 00:56:27.634157 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9500 00:56:27.640529 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9501 00:56:27.644312 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9502 00:56:27.650863 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9503 00:56:27.653928 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9504 00:56:27.657161 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9505 00:56:27.663996 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9506 00:56:27.667426 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9507 00:56:27.671148 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9508 00:56:27.677052 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9509 00:56:27.680589 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9510 00:56:27.684000 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9511 00:56:27.690588 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9512 00:56:27.694013 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9513 00:56:27.700626 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9514 00:56:27.703652 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9515 00:56:27.707171 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9516 00:56:27.713819 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9517 00:56:27.717498 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9518 00:56:27.720276 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9519 00:56:27.727222 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9520 00:56:27.730818 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9521 00:56:27.733750 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9522 00:56:27.740422 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9523 00:56:27.743886 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9524 00:56:27.750448 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9525 00:56:27.753916 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9526 00:56:27.756900 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9527 00:56:27.760685 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9528 00:56:27.763593 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9529 00:56:27.770091 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9530 00:56:27.773546 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9531 00:56:27.777083 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9532 00:56:27.780423 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9533 00:56:27.786789 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9534 00:56:27.790666 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9535 00:56:27.793732 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9536 00:56:27.796838 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9537 00:56:27.803620 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9538 00:56:27.806690 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9539 00:56:27.813514 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9540 00:56:27.817006 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9541 00:56:27.820243 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9542 00:56:27.827109 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9543 00:56:27.830338 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9544 00:56:27.836756 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9545 00:56:27.839839 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9546 00:56:27.843417 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9547 00:56:27.850400 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9548 00:56:27.853283 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9549 00:56:27.860241 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9550 00:56:27.863452 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9551 00:56:27.870051 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9552 00:56:27.873403 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9553 00:56:27.876907 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9554 00:56:27.883182 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9555 00:56:27.887361 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9556 00:56:27.890399 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9557 00:56:27.896598 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9558 00:56:27.900262 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9559 00:56:27.906691 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9560 00:56:27.910167 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9561 00:56:27.913367 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9562 00:56:27.920119 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9563 00:56:27.923238 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9564 00:56:27.929758 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9565 00:56:27.933626 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9566 00:56:27.939849 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9567 00:56:27.942948 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9568 00:56:27.946781 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9569 00:56:27.953029 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9570 00:56:27.956274 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9571 00:56:27.963088 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9572 00:56:27.966615 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9573 00:56:27.969923 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9574 00:56:27.976533 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9575 00:56:27.979530 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9576 00:56:27.986014 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9577 00:56:27.989581 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9578 00:56:27.992719 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9579 00:56:27.999854 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9580 00:56:28.003234 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9581 00:56:28.009514 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9582 00:56:28.012858 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9583 00:56:28.019404 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9584 00:56:28.022774 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9585 00:56:28.025848 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9586 00:56:28.032760 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9587 00:56:28.036275 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9588 00:56:28.042561 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9589 00:56:28.045647 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9590 00:56:28.049095 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9591 00:56:28.055954 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9592 00:56:28.059144 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9593 00:56:28.066177 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9594 00:56:28.068999 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9595 00:56:28.072372 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9596 00:56:28.079287 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9597 00:56:28.082498 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9598 00:56:28.089147 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9599 00:56:28.092313 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9600 00:56:28.099047 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9601 00:56:28.102453 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9602 00:56:28.105767 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9603 00:56:28.112775 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9604 00:56:28.115813 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9605 00:56:28.122244 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9606 00:56:28.125906 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9607 00:56:28.129218 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9608 00:56:28.135755 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9609 00:56:28.139059 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9610 00:56:28.142586 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9611 00:56:28.149183 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9612 00:56:28.152569 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9613 00:56:28.159088 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9614 00:56:28.162203 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9615 00:56:28.169323 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9616 00:56:28.172509 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9617 00:56:28.175993 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9618 00:56:28.182732 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9619 00:56:28.185951 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9620 00:56:28.192302 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9621 00:56:28.195818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9622 00:56:28.202054 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9623 00:56:28.205745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9624 00:56:28.212403 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9625 00:56:28.215630 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9626 00:56:28.218846 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9627 00:56:28.225419 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9628 00:56:28.228909 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9629 00:56:28.235575 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9630 00:56:28.238816 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9631 00:56:28.245412 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9632 00:56:28.248781 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9633 00:56:28.252107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9634 00:56:28.259054 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9635 00:56:28.261997 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9636 00:56:28.268342 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9637 00:56:28.271925 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9638 00:56:28.278807 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9639 00:56:28.282143 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9640 00:56:28.289057 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9641 00:56:28.291932 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9642 00:56:28.295284 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9643 00:56:28.301683 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9644 00:56:28.304976 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9645 00:56:28.312142 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9646 00:56:28.315255 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9647 00:56:28.321673 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9648 00:56:28.325016 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9649 00:56:28.328188 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9650 00:56:28.334922 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9651 00:56:28.338153 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9652 00:56:28.345411 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9653 00:56:28.348460 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9654 00:56:28.355091 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9655 00:56:28.358519 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9656 00:56:28.364748 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9657 00:56:28.368227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9658 00:56:28.371306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9659 00:56:28.378077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9660 00:56:28.381909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9661 00:56:28.388048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9662 00:56:28.391790 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9663 00:56:28.395110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9664 00:56:28.401576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9665 00:56:28.404931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9666 00:56:28.411604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9667 00:56:28.414926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9668 00:56:28.421487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9669 00:56:28.424770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9670 00:56:28.431621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9671 00:56:28.434906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9672 00:56:28.441935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9673 00:56:28.444903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9674 00:56:28.451669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9675 00:56:28.454716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9676 00:56:28.461795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9677 00:56:28.464815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9678 00:56:28.471426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9679 00:56:28.475242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9680 00:56:28.481855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9681 00:56:28.484869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9682 00:56:28.491669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9683 00:56:28.494991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9684 00:56:28.501194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9685 00:56:28.504952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9686 00:56:28.511467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9687 00:56:28.514349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9688 00:56:28.521339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9689 00:56:28.524412 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9690 00:56:28.527803 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9691 00:56:28.530957 INFO: [APUAPC] vio 0
9692 00:56:28.537961 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9693 00:56:28.541410 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9694 00:56:28.544580 INFO: [APUAPC] D0_APC_0: 0x400510
9695 00:56:28.547819 INFO: [APUAPC] D0_APC_1: 0x0
9696 00:56:28.551085 INFO: [APUAPC] D0_APC_2: 0x1540
9697 00:56:28.554410 INFO: [APUAPC] D0_APC_3: 0x0
9698 00:56:28.558156 INFO: [APUAPC] D1_APC_0: 0xffffffff
9699 00:56:28.560875 INFO: [APUAPC] D1_APC_1: 0xffffffff
9700 00:56:28.564301 INFO: [APUAPC] D1_APC_2: 0x3fffff
9701 00:56:28.567503 INFO: [APUAPC] D1_APC_3: 0x0
9702 00:56:28.571105 INFO: [APUAPC] D2_APC_0: 0xffffffff
9703 00:56:28.573982 INFO: [APUAPC] D2_APC_1: 0xffffffff
9704 00:56:28.577699 INFO: [APUAPC] D2_APC_2: 0x3fffff
9705 00:56:28.577766 INFO: [APUAPC] D2_APC_3: 0x0
9706 00:56:28.584453 INFO: [APUAPC] D3_APC_0: 0xffffffff
9707 00:56:28.587614 INFO: [APUAPC] D3_APC_1: 0xffffffff
9708 00:56:28.590732 INFO: [APUAPC] D3_APC_2: 0x3fffff
9709 00:56:28.590794 INFO: [APUAPC] D3_APC_3: 0x0
9710 00:56:28.594044 INFO: [APUAPC] D4_APC_0: 0xffffffff
9711 00:56:28.597508 INFO: [APUAPC] D4_APC_1: 0xffffffff
9712 00:56:28.601066 INFO: [APUAPC] D4_APC_2: 0x3fffff
9713 00:56:28.604480 INFO: [APUAPC] D4_APC_3: 0x0
9714 00:56:28.607484 INFO: [APUAPC] D5_APC_0: 0xffffffff
9715 00:56:28.610950 INFO: [APUAPC] D5_APC_1: 0xffffffff
9716 00:56:28.614100 INFO: [APUAPC] D5_APC_2: 0x3fffff
9717 00:56:28.617735 INFO: [APUAPC] D5_APC_3: 0x0
9718 00:56:28.620984 INFO: [APUAPC] D6_APC_0: 0xffffffff
9719 00:56:28.624131 INFO: [APUAPC] D6_APC_1: 0xffffffff
9720 00:56:28.627728 INFO: [APUAPC] D6_APC_2: 0x3fffff
9721 00:56:28.630678 INFO: [APUAPC] D6_APC_3: 0x0
9722 00:56:28.634399 INFO: [APUAPC] D7_APC_0: 0xffffffff
9723 00:56:28.637408 INFO: [APUAPC] D7_APC_1: 0xffffffff
9724 00:56:28.640854 INFO: [APUAPC] D7_APC_2: 0x3fffff
9725 00:56:28.644195 INFO: [APUAPC] D7_APC_3: 0x0
9726 00:56:28.647905 INFO: [APUAPC] D8_APC_0: 0xffffffff
9727 00:56:28.650827 INFO: [APUAPC] D8_APC_1: 0xffffffff
9728 00:56:28.654115 INFO: [APUAPC] D8_APC_2: 0x3fffff
9729 00:56:28.657709 INFO: [APUAPC] D8_APC_3: 0x0
9730 00:56:28.661027 INFO: [APUAPC] D9_APC_0: 0xffffffff
9731 00:56:28.664202 INFO: [APUAPC] D9_APC_1: 0xffffffff
9732 00:56:28.667571 INFO: [APUAPC] D9_APC_2: 0x3fffff
9733 00:56:28.671252 INFO: [APUAPC] D9_APC_3: 0x0
9734 00:56:28.674037 INFO: [APUAPC] D10_APC_0: 0xffffffff
9735 00:56:28.677713 INFO: [APUAPC] D10_APC_1: 0xffffffff
9736 00:56:28.680904 INFO: [APUAPC] D10_APC_2: 0x3fffff
9737 00:56:28.684032 INFO: [APUAPC] D10_APC_3: 0x0
9738 00:56:28.687627 INFO: [APUAPC] D11_APC_0: 0xffffffff
9739 00:56:28.690810 INFO: [APUAPC] D11_APC_1: 0xffffffff
9740 00:56:28.694195 INFO: [APUAPC] D11_APC_2: 0x3fffff
9741 00:56:28.697587 INFO: [APUAPC] D11_APC_3: 0x0
9742 00:56:28.700708 INFO: [APUAPC] D12_APC_0: 0xffffffff
9743 00:56:28.704097 INFO: [APUAPC] D12_APC_1: 0xffffffff
9744 00:56:28.707563 INFO: [APUAPC] D12_APC_2: 0x3fffff
9745 00:56:28.710999 INFO: [APUAPC] D12_APC_3: 0x0
9746 00:56:28.713997 INFO: [APUAPC] D13_APC_0: 0xffffffff
9747 00:56:28.717515 INFO: [APUAPC] D13_APC_1: 0xffffffff
9748 00:56:28.721203 INFO: [APUAPC] D13_APC_2: 0x3fffff
9749 00:56:28.724280 INFO: [APUAPC] D13_APC_3: 0x0
9750 00:56:28.727493 INFO: [APUAPC] D14_APC_0: 0xffffffff
9751 00:56:28.731131 INFO: [APUAPC] D14_APC_1: 0xffffffff
9752 00:56:28.734158 INFO: [APUAPC] D14_APC_2: 0x3fffff
9753 00:56:28.737353 INFO: [APUAPC] D14_APC_3: 0x0
9754 00:56:28.740846 INFO: [APUAPC] D15_APC_0: 0xffffffff
9755 00:56:28.744263 INFO: [APUAPC] D15_APC_1: 0xffffffff
9756 00:56:28.747311 INFO: [APUAPC] D15_APC_2: 0x3fffff
9757 00:56:28.750584 INFO: [APUAPC] D15_APC_3: 0x0
9758 00:56:28.754583 INFO: [APUAPC] APC_CON: 0x4
9759 00:56:28.757275 INFO: [NOCDAPC] D0_APC_0: 0x0
9760 00:56:28.757357 INFO: [NOCDAPC] D0_APC_1: 0x0
9761 00:56:28.760753 INFO: [NOCDAPC] D1_APC_0: 0x0
9762 00:56:28.763782 INFO: [NOCDAPC] D1_APC_1: 0xfff
9763 00:56:28.767242 INFO: [NOCDAPC] D2_APC_0: 0x0
9764 00:56:28.770451 INFO: [NOCDAPC] D2_APC_1: 0xfff
9765 00:56:28.773743 INFO: [NOCDAPC] D3_APC_0: 0x0
9766 00:56:28.777241 INFO: [NOCDAPC] D3_APC_1: 0xfff
9767 00:56:28.780473 INFO: [NOCDAPC] D4_APC_0: 0x0
9768 00:56:28.784080 INFO: [NOCDAPC] D4_APC_1: 0xfff
9769 00:56:28.787691 INFO: [NOCDAPC] D5_APC_0: 0x0
9770 00:56:28.790248 INFO: [NOCDAPC] D5_APC_1: 0xfff
9771 00:56:28.790350 INFO: [NOCDAPC] D6_APC_0: 0x0
9772 00:56:28.793943 INFO: [NOCDAPC] D6_APC_1: 0xfff
9773 00:56:28.797215 INFO: [NOCDAPC] D7_APC_0: 0x0
9774 00:56:28.800406 INFO: [NOCDAPC] D7_APC_1: 0xfff
9775 00:56:28.803657 INFO: [NOCDAPC] D8_APC_0: 0x0
9776 00:56:28.806866 INFO: [NOCDAPC] D8_APC_1: 0xfff
9777 00:56:28.810510 INFO: [NOCDAPC] D9_APC_0: 0x0
9778 00:56:28.813746 INFO: [NOCDAPC] D9_APC_1: 0xfff
9779 00:56:28.816853 INFO: [NOCDAPC] D10_APC_0: 0x0
9780 00:56:28.820098 INFO: [NOCDAPC] D10_APC_1: 0xfff
9781 00:56:28.823514 INFO: [NOCDAPC] D11_APC_0: 0x0
9782 00:56:28.827479 INFO: [NOCDAPC] D11_APC_1: 0xfff
9783 00:56:28.830291 INFO: [NOCDAPC] D12_APC_0: 0x0
9784 00:56:28.830393 INFO: [NOCDAPC] D12_APC_1: 0xfff
9785 00:56:28.833668 INFO: [NOCDAPC] D13_APC_0: 0x0
9786 00:56:28.837411 INFO: [NOCDAPC] D13_APC_1: 0xfff
9787 00:56:28.840246 INFO: [NOCDAPC] D14_APC_0: 0x0
9788 00:56:28.843520 INFO: [NOCDAPC] D14_APC_1: 0xfff
9789 00:56:28.846864 INFO: [NOCDAPC] D15_APC_0: 0x0
9790 00:56:28.850282 INFO: [NOCDAPC] D15_APC_1: 0xfff
9791 00:56:28.853545 INFO: [NOCDAPC] APC_CON: 0x4
9792 00:56:28.856454 INFO: [APUAPC] set_apusys_apc done
9793 00:56:28.859883 INFO: [DEVAPC] devapc_init done
9794 00:56:28.863462 INFO: GICv3 without legacy support detected.
9795 00:56:28.866684 INFO: ARM GICv3 driver initialized in EL3
9796 00:56:28.873181 INFO: Maximum SPI INTID supported: 639
9797 00:56:28.876258 INFO: BL31: Initializing runtime services
9798 00:56:28.883326 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9799 00:56:28.883407 INFO: SPM: enable CPC mode
9800 00:56:28.889970 INFO: mcdi ready for mcusys-off-idle and system suspend
9801 00:56:28.892919 INFO: BL31: Preparing for EL3 exit to normal world
9802 00:56:28.896468 INFO: Entry point address = 0x80000000
9803 00:56:28.899624 INFO: SPSR = 0x8
9804 00:56:28.905700
9805 00:56:28.905780
9806 00:56:28.905858
9807 00:56:28.909000 Starting depthcharge on Spherion...
9808 00:56:28.909079
9809 00:56:28.909158 Wipe memory regions:
9810 00:56:28.909231
9811 00:56:28.909913 end: 2.2.3 depthcharge-start (duration 00:00:18) [common]
9812 00:56:28.910041 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
9813 00:56:28.910152 Setting prompt string to ['asurada:']
9814 00:56:28.910301 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:28)
9815 00:56:28.911915 [0x00000040000000, 0x00000054600000)
9816 00:56:29.034070
9817 00:56:29.034175 [0x00000054660000, 0x00000080000000)
9818 00:56:29.294721
9819 00:56:29.294833 [0x000000821a7280, 0x000000ffe64000)
9820 00:56:30.039098
9821 00:56:30.039215 [0x00000100000000, 0x00000140000000)
9822 00:56:30.419080
9823 00:56:30.422275 Initializing XHCI USB controller at 0x11200000.
9824 00:56:31.460569
9825 00:56:31.463828 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9826 00:56:31.463907
9827 00:56:31.463970
9828 00:56:31.464238 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9830 00:56:31.564692 asurada: tftpboot 192.168.201.1 14368566/tftp-deploy-3k9xqh2p/kernel/image.itb 14368566/tftp-deploy-3k9xqh2p/kernel/cmdline
9831 00:56:31.565411 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9832 00:56:31.565876 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:25)
9833 00:56:31.570388 tftpboot 192.168.201.1 14368566/tftp-deploy-3k9xqh2p/kernel/image.itp-deploy-3k9xqh2p/kernel/cmdline
9834 00:56:31.570830
9835 00:56:31.571169 Waiting for link
9836 00:56:31.728408
9837 00:56:31.728852 R8152: Initializing
9838 00:56:31.729161
9839 00:56:31.731306 Version 9 (ocp_data = 6010)
9840 00:56:31.731700
9841 00:56:31.734985 R8152: Done initializing
9842 00:56:31.735377
9843 00:56:31.735679 Adding net device
9844 00:56:33.622674
9845 00:56:33.622791 done.
9846 00:56:33.622852
9847 00:56:33.622908 MAC: 00:e0:4c:68:03:bd
9848 00:56:33.622960
9849 00:56:33.625327 Sending DHCP discover... done.
9850 00:56:33.625403
9851 00:56:38.478840 Waiting for reply... done.
9852 00:56:38.478956
9853 00:56:38.479018 Sending DHCP request... done.
9854 00:56:38.481721
9855 00:56:38.481811 Waiting for reply... done.
9856 00:56:38.481899
9857 00:56:38.485484 My ip is 192.168.201.16
9858 00:56:38.485575
9859 00:56:38.488547 The DHCP server ip is 192.168.201.1
9860 00:56:38.488651
9861 00:56:38.491834 TFTP server IP predefined by user: 192.168.201.1
9862 00:56:38.491962
9863 00:56:38.498453 Bootfile predefined by user: 14368566/tftp-deploy-3k9xqh2p/kernel/image.itb
9864 00:56:38.498567
9865 00:56:38.501764 Sending tftp read request... done.
9866 00:56:38.501854
9867 00:56:38.505120 Waiting for the transfer...
9868 00:56:38.505222
9869 00:56:38.769084 00000000 ################################################################
9870 00:56:38.769209
9871 00:56:39.019987 00080000 ################################################################
9872 00:56:39.020113
9873 00:56:39.267710 00100000 ################################################################
9874 00:56:39.267831
9875 00:56:39.515506 00180000 ################################################################
9876 00:56:39.515629
9877 00:56:39.765351 00200000 ################################################################
9878 00:56:39.765476
9879 00:56:40.013087 00280000 ################################################################
9880 00:56:40.013213
9881 00:56:40.263446 00300000 ################################################################
9882 00:56:40.263568
9883 00:56:40.510194 00380000 ################################################################
9884 00:56:40.510342
9885 00:56:40.761245 00400000 ################################################################
9886 00:56:40.761355
9887 00:56:41.011328 00480000 ################################################################
9888 00:56:41.011442
9889 00:56:41.262569 00500000 ################################################################
9890 00:56:41.262682
9891 00:56:41.511874 00580000 ################################################################
9892 00:56:41.511991
9893 00:56:41.766864 00600000 ################################################################
9894 00:56:41.766985
9895 00:56:42.018197 00680000 ################################################################
9896 00:56:42.018356
9897 00:56:42.271075 00700000 ################################################################
9898 00:56:42.271195
9899 00:56:42.523937 00780000 ################################################################
9900 00:56:42.524087
9901 00:56:42.773215 00800000 ################################################################
9902 00:56:42.773351
9903 00:56:43.023707 00880000 ################################################################
9904 00:56:43.023822
9905 00:56:43.272058 00900000 ################################################################
9906 00:56:43.272200
9907 00:56:43.520411 00980000 ################################################################
9908 00:56:43.520525
9909 00:56:43.767074 00a00000 ################################################################
9910 00:56:43.767192
9911 00:56:44.013884 00a80000 ################################################################
9912 00:56:44.014048
9913 00:56:44.263209 00b00000 ################################################################
9914 00:56:44.263330
9915 00:56:44.512944 00b80000 ################################################################
9916 00:56:44.513053
9917 00:56:44.767107 00c00000 ################################################################
9918 00:56:44.767217
9919 00:56:45.016591 00c80000 ################################################################
9920 00:56:45.016726
9921 00:56:45.267261 00d00000 ################################################################
9922 00:56:45.267402
9923 00:56:45.534564 00d80000 ################################################################
9924 00:56:45.534692
9925 00:56:45.797633 00e00000 ################################################################
9926 00:56:45.797788
9927 00:56:46.050195 00e80000 ################################################################
9928 00:56:46.050328
9929 00:56:46.303550 00f00000 ################################################################
9930 00:56:46.303703
9931 00:56:46.554471 00f80000 ################################################################
9932 00:56:46.554611
9933 00:56:46.797950 01000000 ################################################################
9934 00:56:46.798086
9935 00:56:47.042675 01080000 ################################################################
9936 00:56:47.042815
9937 00:56:47.288084 01100000 ################################################################
9938 00:56:47.288200
9939 00:56:47.534302 01180000 ################################################################
9940 00:56:47.534421
9941 00:56:47.782086 01200000 ################################################################
9942 00:56:47.782258
9943 00:56:48.032862 01280000 ################################################################
9944 00:56:48.032984
9945 00:56:48.280433 01300000 ################################################################
9946 00:56:48.280546
9947 00:56:48.531830 01380000 ################################################################
9948 00:56:48.531946
9949 00:56:48.782269 01400000 ################################################################
9950 00:56:48.782382
9951 00:56:49.042021 01480000 ################################################################
9952 00:56:49.042151
9953 00:56:49.293503 01500000 ################################################################
9954 00:56:49.293628
9955 00:56:49.542476 01580000 ################################################################
9956 00:56:49.542599
9957 00:56:49.791663 01600000 ################################################################
9958 00:56:49.791785
9959 00:56:50.047764 01680000 ################################################################
9960 00:56:50.047874
9961 00:56:50.321147 01700000 ################################################################
9962 00:56:50.321258
9963 00:56:50.621960 01780000 ################################################################
9964 00:56:50.622072
9965 00:56:50.917771 01800000 ################################################################
9966 00:56:50.917881
9967 00:56:51.205247 01880000 ################################################################
9968 00:56:51.205384
9969 00:56:51.481845 01900000 ################################################################
9970 00:56:51.481964
9971 00:56:51.773762 01980000 ################################################################
9972 00:56:51.773872
9973 00:56:52.071025 01a00000 ################################################################
9974 00:56:52.071138
9975 00:56:52.368281 01a80000 ################################################################
9976 00:56:52.368391
9977 00:56:52.657644 01b00000 ################################################################
9978 00:56:52.657761
9979 00:56:52.933661 01b80000 ################################################################
9980 00:56:52.933771
9981 00:56:53.182499 01c00000 ################################################################
9982 00:56:53.182617
9983 00:56:53.430577 01c80000 ################################################################
9984 00:56:53.430717
9985 00:56:53.676565 01d00000 ################################################################
9986 00:56:53.676694
9987 00:56:53.927592 01d80000 ################################################################
9988 00:56:53.927722
9989 00:56:54.139857 01e00000 ####################################################### done.
9990 00:56:54.139972
9991 00:56:54.142902 The bootfile was 31906962 bytes long.
9992 00:56:54.142990
9993 00:56:54.146572 Sending tftp read request... done.
9994 00:56:54.146704
9995 00:56:54.146777 Waiting for the transfer...
9996 00:56:54.146835
9997 00:56:54.149792 00000000 # done.
9998 00:56:54.149903
9999 00:56:54.156207 Command line loaded dynamically from TFTP file: 14368566/tftp-deploy-3k9xqh2p/kernel/cmdline
10000 00:56:54.156285
10001 00:56:54.179327 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368566/extract-nfsrootfs-k6gbqes9,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10002 00:56:54.179412
10003 00:56:54.179471 Loading FIT.
10004 00:56:54.179530
10005 00:56:54.183014 Image ramdisk-1 has 18732631 bytes.
10006 00:56:54.183098
10007 00:56:54.186648 Image fdt-1 has 47258 bytes.
10008 00:56:54.186735
10009 00:56:54.190114 Image kernel-1 has 13125045 bytes.
10010 00:56:54.190228
10011 00:56:54.199641 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10012 00:56:54.199787
10013 00:56:54.216272 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10014 00:56:54.216353
10015 00:56:54.222873 Choosing best match conf-1 for compat google,spherion-rev3.
10016 00:56:54.222950
10017 00:56:54.230409 Connected to device vid:did:rid of 1ae0:0028:00
10018 00:56:54.237208
10019 00:56:54.240733 tpm_get_response: command 0x17b, return code 0x0
10020 00:56:54.240834
10021 00:56:54.243801 ec_init: CrosEC protocol v3 supported (256, 248)
10022 00:56:54.247676
10023 00:56:54.250985 tpm_cleanup: add release locality here.
10024 00:56:54.251068
10025 00:56:54.251133 Shutting down all USB controllers.
10026 00:56:54.254144
10027 00:56:54.254244 Removing current net device
10028 00:56:54.254309
10029 00:56:54.260853 Exiting depthcharge with code 4 at timestamp: 53585001
10030 00:56:54.261010
10031 00:56:54.264325 LZMA decompressing kernel-1 to 0x821a6718
10032 00:56:54.264453
10033 00:56:54.267587 LZMA decompressing kernel-1 to 0x40000000
10034 00:56:55.883522
10035 00:56:55.883989 jumping to kernel
10036 00:56:55.885603 end: 2.2.4 bootloader-commands (duration 00:00:27) [common]
10037 00:56:55.886068 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10038 00:56:55.886451 Setting prompt string to ['Linux version [0-9]']
10039 00:56:55.886771 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10040 00:56:55.887088 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10041 00:56:55.933921
10042 00:56:55.937291 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10043 00:56:55.941047 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10044 00:56:55.941517 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10045 00:56:55.941858 Setting prompt string to []
10046 00:56:55.942206 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10047 00:56:55.942570 Using line separator: #'\n'#
10048 00:56:55.942848 No login prompt set.
10049 00:56:55.943134 Parsing kernel messages
10050 00:56:55.943422 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10051 00:56:55.943932 [login-action] Waiting for messages, (timeout 00:04:01)
10052 00:56:55.944236 Waiting using forced prompt support (timeout 00:02:01)
10053 00:56:55.960459 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
10054 00:56:55.964123 [ 0.000000] random: crng init done
10055 00:56:55.970189 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10056 00:56:55.973539 [ 0.000000] efi: UEFI not found.
10057 00:56:55.980013 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10058 00:56:55.986551 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10059 00:56:55.996661 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10060 00:56:56.006897 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10061 00:56:56.013137 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10062 00:56:56.019535 [ 0.000000] printk: bootconsole [mtk8250] enabled
10063 00:56:56.026656 [ 0.000000] NUMA: No NUMA configuration found
10064 00:56:56.033343 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10065 00:56:56.036287 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10066 00:56:56.040010 [ 0.000000] Zone ranges:
10067 00:56:56.046540 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10068 00:56:56.049613 [ 0.000000] DMA32 empty
10069 00:56:56.055989 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10070 00:56:56.059340 [ 0.000000] Movable zone start for each node
10071 00:56:56.062522 [ 0.000000] Early memory node ranges
10072 00:56:56.069517 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10073 00:56:56.075828 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10074 00:56:56.082516 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10075 00:56:56.089028 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10076 00:56:56.095945 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10077 00:56:56.102603 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10078 00:56:56.132610 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10079 00:56:56.139065 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10080 00:56:56.145681 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10081 00:56:56.149195 [ 0.000000] psci: probing for conduit method from DT.
10082 00:56:56.155594 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10083 00:56:56.158859 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10084 00:56:56.165367 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10085 00:56:56.168400 [ 0.000000] psci: SMC Calling Convention v1.2
10086 00:56:56.175344 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10087 00:56:56.178660 [ 0.000000] Detected VIPT I-cache on CPU0
10088 00:56:56.185001 [ 0.000000] CPU features: detected: GIC system register CPU interface
10089 00:56:56.191797 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10090 00:56:56.198252 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10091 00:56:56.205125 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10092 00:56:56.215155 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10093 00:56:56.221287 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10094 00:56:56.224490 [ 0.000000] alternatives: applying boot alternatives
10095 00:56:56.231423 [ 0.000000] Fallback order for Node 0: 0
10096 00:56:56.237631 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10097 00:56:56.241196 [ 0.000000] Policy zone: Normal
10098 00:56:56.264406 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368566/extract-nfsrootfs-k6gbqes9,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10099 00:56:56.274252 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10100 00:56:56.284250 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10101 00:56:56.293721 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10102 00:56:56.300397 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10103 00:56:56.303808 <6>[ 0.000000] software IO TLB: area num 8.
10104 00:56:56.360222 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10105 00:56:56.439800 <6>[ 0.000000] Memory: 3831356K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 327108K reserved, 32768K cma-reserved)
10106 00:56:56.446206 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10107 00:56:56.453112 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10108 00:56:56.456487 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10109 00:56:56.462713 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10110 00:56:56.469484 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10111 00:56:56.473282 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10112 00:56:56.483011 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10113 00:56:56.489317 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10114 00:56:56.496146 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10115 00:56:56.502724 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10116 00:56:56.505605 <6>[ 0.000000] GICv3: 608 SPIs implemented
10117 00:56:56.509150 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10118 00:56:56.515630 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10119 00:56:56.519127 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10120 00:56:56.525732 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10121 00:56:56.538890 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10122 00:56:56.548729 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10123 00:56:56.558847 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10124 00:56:56.565877 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10125 00:56:56.579405 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10126 00:56:56.586351 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10127 00:56:56.592415 <6>[ 0.009182] Console: colour dummy device 80x25
10128 00:56:56.602587 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10129 00:56:56.608504 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10130 00:56:56.611862 <6>[ 0.029220] LSM: Security Framework initializing
10131 00:56:56.618907 <6>[ 0.034134] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10132 00:56:56.628364 <6>[ 0.041742] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10133 00:56:56.634935 <6>[ 0.051025] cblist_init_generic: Setting adjustable number of callback queues.
10134 00:56:56.641735 <6>[ 0.058468] cblist_init_generic: Setting shift to 3 and lim to 1.
10135 00:56:56.651818 <6>[ 0.064807] cblist_init_generic: Setting adjustable number of callback queues.
10136 00:56:56.654855 <6>[ 0.072233] cblist_init_generic: Setting shift to 3 and lim to 1.
10137 00:56:56.661458 <6>[ 0.078632] rcu: Hierarchical SRCU implementation.
10138 00:56:56.667966 <6>[ 0.083678] rcu: Max phase no-delay instances is 1000.
10139 00:56:56.675209 <6>[ 0.090709] EFI services will not be available.
10140 00:56:56.677980 <6>[ 0.095664] smp: Bringing up secondary CPUs ...
10141 00:56:56.685983 <6>[ 0.100713] Detected VIPT I-cache on CPU1
10142 00:56:56.692616 <6>[ 0.100782] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10143 00:56:56.698937 <6>[ 0.100813] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10144 00:56:56.702497 <6>[ 0.101149] Detected VIPT I-cache on CPU2
10145 00:56:56.712542 <6>[ 0.101201] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10146 00:56:56.719074 <6>[ 0.101219] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10147 00:56:56.722340 <6>[ 0.101479] Detected VIPT I-cache on CPU3
10148 00:56:56.728997 <6>[ 0.101527] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10149 00:56:56.735430 <6>[ 0.101541] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10150 00:56:56.742094 <6>[ 0.101845] CPU features: detected: Spectre-v4
10151 00:56:56.745412 <6>[ 0.101851] CPU features: detected: Spectre-BHB
10152 00:56:56.748905 <6>[ 0.101856] Detected PIPT I-cache on CPU4
10153 00:56:56.755535 <6>[ 0.101916] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10154 00:56:56.761896 <6>[ 0.101933] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10155 00:56:56.768792 <6>[ 0.102224] Detected PIPT I-cache on CPU5
10156 00:56:56.775393 <6>[ 0.102286] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10157 00:56:56.781967 <6>[ 0.102301] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10158 00:56:56.784848 <6>[ 0.102576] Detected PIPT I-cache on CPU6
10159 00:56:56.791907 <6>[ 0.102638] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10160 00:56:56.798352 <6>[ 0.102654] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10161 00:56:56.805024 <6>[ 0.102954] Detected PIPT I-cache on CPU7
10162 00:56:56.811750 <6>[ 0.103020] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10163 00:56:56.818190 <6>[ 0.103035] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10164 00:56:56.821574 <6>[ 0.103083] smp: Brought up 1 node, 8 CPUs
10165 00:56:56.828007 <6>[ 0.244487] SMP: Total of 8 processors activated.
10166 00:56:56.831241 <6>[ 0.249439] CPU features: detected: 32-bit EL0 Support
10167 00:56:56.841092 <6>[ 0.254802] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10168 00:56:56.847706 <6>[ 0.263657] CPU features: detected: Common not Private translations
10169 00:56:56.854562 <6>[ 0.270133] CPU features: detected: CRC32 instructions
10170 00:56:56.861302 <6>[ 0.275518] CPU features: detected: RCpc load-acquire (LDAPR)
10171 00:56:56.864660 <6>[ 0.281515] CPU features: detected: LSE atomic instructions
10172 00:56:56.870849 <6>[ 0.287332] CPU features: detected: Privileged Access Never
10173 00:56:56.877376 <6>[ 0.293111] CPU features: detected: RAS Extension Support
10174 00:56:56.884573 <6>[ 0.298720] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10175 00:56:56.887475 <6>[ 0.305941] CPU: All CPU(s) started at EL2
10176 00:56:56.893721 <6>[ 0.310284] alternatives: applying system-wide alternatives
10177 00:56:56.902961 <6>[ 0.320316] devtmpfs: initialized
10178 00:56:56.914768 <6>[ 0.328521] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10179 00:56:56.924510 <6>[ 0.338480] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10180 00:56:56.931020 <6>[ 0.346652] pinctrl core: initialized pinctrl subsystem
10181 00:56:56.934482 <6>[ 0.353335] DMI not present or invalid.
10182 00:56:56.941597 <6>[ 0.357740] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10183 00:56:56.950758 <6>[ 0.364609] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10184 00:56:56.957633 <6>[ 0.372056] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10185 00:56:56.967862 <6>[ 0.380150] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10186 00:56:56.970991 <6>[ 0.388305] audit: initializing netlink subsys (disabled)
10187 00:56:56.980516 <5>[ 0.394002] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10188 00:56:56.987426 <6>[ 0.394705] thermal_sys: Registered thermal governor 'step_wise'
10189 00:56:56.994278 <6>[ 0.401970] thermal_sys: Registered thermal governor 'power_allocator'
10190 00:56:56.998001 <6>[ 0.408223] cpuidle: using governor menu
10191 00:56:57.004430 <6>[ 0.419180] NET: Registered PF_QIPCRTR protocol family
10192 00:56:57.010863 <6>[ 0.424665] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10193 00:56:57.014105 <6>[ 0.431768] ASID allocator initialised with 32768 entries
10194 00:56:57.021973 <6>[ 0.438338] Serial: AMBA PL011 UART driver
10195 00:56:57.029951 <4>[ 0.447168] Trying to register duplicate clock ID: 134
10196 00:56:57.088524 <6>[ 0.508715] KASLR enabled
10197 00:56:57.102582 <6>[ 0.516461] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10198 00:56:57.109640 <6>[ 0.523474] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10199 00:56:57.116151 <6>[ 0.529964] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10200 00:56:57.122323 <6>[ 0.536969] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10201 00:56:57.128846 <6>[ 0.543454] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10202 00:56:57.136272 <6>[ 0.550459] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10203 00:56:57.142049 <6>[ 0.556947] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10204 00:56:57.148858 <6>[ 0.563953] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10205 00:56:57.151827 <6>[ 0.571475] ACPI: Interpreter disabled.
10206 00:56:57.160421 <6>[ 0.577888] iommu: Default domain type: Translated
10207 00:56:57.167385 <6>[ 0.583001] iommu: DMA domain TLB invalidation policy: strict mode
10208 00:56:57.170463 <5>[ 0.589656] SCSI subsystem initialized
10209 00:56:57.177141 <6>[ 0.593818] usbcore: registered new interface driver usbfs
10210 00:56:57.183879 <6>[ 0.599550] usbcore: registered new interface driver hub
10211 00:56:57.187032 <6>[ 0.605104] usbcore: registered new device driver usb
10212 00:56:57.193840 <6>[ 0.611201] pps_core: LinuxPPS API ver. 1 registered
10213 00:56:57.204031 <6>[ 0.616394] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10214 00:56:57.207265 <6>[ 0.625743] PTP clock support registered
10215 00:56:57.210364 <6>[ 0.629986] EDAC MC: Ver: 3.0.0
10216 00:56:57.218119 <6>[ 0.635138] FPGA manager framework
10217 00:56:57.224484 <6>[ 0.638822] Advanced Linux Sound Architecture Driver Initialized.
10218 00:56:57.227903 <6>[ 0.645594] vgaarb: loaded
10219 00:56:57.234754 <6>[ 0.648756] clocksource: Switched to clocksource arch_sys_counter
10220 00:56:57.237935 <5>[ 0.655196] VFS: Disk quotas dquot_6.6.0
10221 00:56:57.245041 <6>[ 0.659380] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10222 00:56:57.247974 <6>[ 0.666569] pnp: PnP ACPI: disabled
10223 00:56:57.256303 <6>[ 0.673283] NET: Registered PF_INET protocol family
10224 00:56:57.263189 <6>[ 0.678664] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10225 00:56:57.275045 <6>[ 0.688677] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10226 00:56:57.285322 <6>[ 0.697467] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10227 00:56:57.291914 <6>[ 0.705433] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10228 00:56:57.298306 <6>[ 0.713836] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10229 00:56:57.308803 <6>[ 0.722492] TCP: Hash tables configured (established 32768 bind 32768)
10230 00:56:57.315993 <6>[ 0.729352] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10231 00:56:57.322143 <6>[ 0.736372] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10232 00:56:57.328702 <6>[ 0.743893] NET: Registered PF_UNIX/PF_LOCAL protocol family
10233 00:56:57.335447 <6>[ 0.750021] RPC: Registered named UNIX socket transport module.
10234 00:56:57.338632 <6>[ 0.756176] RPC: Registered udp transport module.
10235 00:56:57.345798 <6>[ 0.761108] RPC: Registered tcp transport module.
10236 00:56:57.351746 <6>[ 0.766036] RPC: Registered tcp NFSv4.1 backchannel transport module.
10237 00:56:57.355581 <6>[ 0.772698] PCI: CLS 0 bytes, default 64
10238 00:56:57.358473 <6>[ 0.777096] Unpacking initramfs...
10239 00:56:57.368384 <6>[ 0.780788] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10240 00:56:57.375434 <6>[ 0.789411] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10241 00:56:57.382310 <6>[ 0.798240] kvm [1]: IPA Size Limit: 40 bits
10242 00:56:57.385562 <6>[ 0.802765] kvm [1]: GICv3: no GICV resource entry
10243 00:56:57.391633 <6>[ 0.807785] kvm [1]: disabling GICv2 emulation
10244 00:56:57.395059 <6>[ 0.812474] kvm [1]: GIC system register CPU interface enabled
10245 00:56:57.401472 <6>[ 0.818642] kvm [1]: vgic interrupt IRQ18
10246 00:56:57.404876 <6>[ 0.822998] kvm [1]: VHE mode initialized successfully
10247 00:56:57.412142 <5>[ 0.829478] Initialise system trusted keyrings
10248 00:56:57.418720 <6>[ 0.834309] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10249 00:56:57.427594 <6>[ 0.844211] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10250 00:56:57.433962 <5>[ 0.850586] NFS: Registering the id_resolver key type
10251 00:56:57.437695 <5>[ 0.855887] Key type id_resolver registered
10252 00:56:57.444269 <5>[ 0.860301] Key type id_legacy registered
10253 00:56:57.450589 <6>[ 0.864596] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10254 00:56:57.457209 <6>[ 0.871519] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10255 00:56:57.463817 <6>[ 0.879227] 9p: Installing v9fs 9p2000 file system support
10256 00:56:57.500413 <5>[ 0.917133] Key type asymmetric registered
10257 00:56:57.503601 <5>[ 0.921463] Asymmetric key parser 'x509' registered
10258 00:56:57.513727 <6>[ 0.926596] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10259 00:56:57.516931 <6>[ 0.934210] io scheduler mq-deadline registered
10260 00:56:57.520607 <6>[ 0.938974] io scheduler kyber registered
10261 00:56:57.539101 <6>[ 0.955915] EINJ: ACPI disabled.
10262 00:56:57.572552 <4>[ 0.982509] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10263 00:56:57.582500 <4>[ 0.993173] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10264 00:56:57.597636 <6>[ 1.014313] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10265 00:56:57.605366 <6>[ 1.022316] printk: console [ttyS0] disabled
10266 00:56:57.633604 <6>[ 1.046947] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10267 00:56:57.640106 <6>[ 1.056421] printk: console [ttyS0] enabled
10268 00:56:57.643238 <6>[ 1.056421] printk: console [ttyS0] enabled
10269 00:56:57.650198 <6>[ 1.065315] printk: bootconsole [mtk8250] disabled
10270 00:56:57.652910 <6>[ 1.065315] printk: bootconsole [mtk8250] disabled
10271 00:56:57.660040 <6>[ 1.076550] SuperH (H)SCI(F) driver initialized
10272 00:56:57.663128 <6>[ 1.081839] msm_serial: driver initialized
10273 00:56:57.677421 <6>[ 1.090799] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10274 00:56:57.687290 <6>[ 1.099346] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10275 00:56:57.693594 <6>[ 1.107891] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10276 00:56:57.703717 <6>[ 1.116520] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10277 00:56:57.713651 <6>[ 1.125228] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10278 00:56:57.720486 <6>[ 1.133943] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10279 00:56:57.730518 <6>[ 1.142483] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10280 00:56:57.736755 <6>[ 1.151286] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10281 00:56:57.747069 <6>[ 1.159829] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10282 00:56:57.758693 <6>[ 1.175566] loop: module loaded
10283 00:56:57.765655 <6>[ 1.181572] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10284 00:56:57.787861 <4>[ 1.204919] mtk-pmic-keys: Failed to locate of_node [id: -1]
10285 00:56:57.794722 <6>[ 1.211820] megasas: 07.719.03.00-rc1
10286 00:56:57.804637 <6>[ 1.221758] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10287 00:56:57.811463 <6>[ 1.228150] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10288 00:56:57.828204 <6>[ 1.244714] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10289 00:56:57.883597 <6>[ 1.294060] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10290 00:56:58.143066 <6>[ 1.559725] Freeing initrd memory: 18288K
10291 00:56:58.154885 <6>[ 1.571400] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10292 00:56:58.165743 <6>[ 1.582431] tun: Universal TUN/TAP device driver, 1.6
10293 00:56:58.168847 <6>[ 1.588504] thunder_xcv, ver 1.0
10294 00:56:58.172222 <6>[ 1.592008] thunder_bgx, ver 1.0
10295 00:56:58.175250 <6>[ 1.595504] nicpf, ver 1.0
10296 00:56:58.186458 <6>[ 1.599528] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10297 00:56:58.189316 <6>[ 1.607004] hns3: Copyright (c) 2017 Huawei Corporation.
10298 00:56:58.196142 <6>[ 1.612591] hclge is initializing
10299 00:56:58.199000 <6>[ 1.616172] e1000: Intel(R) PRO/1000 Network Driver
10300 00:56:58.206325 <6>[ 1.621301] e1000: Copyright (c) 1999-2006 Intel Corporation.
10301 00:56:58.209320 <6>[ 1.627317] e1000e: Intel(R) PRO/1000 Network Driver
10302 00:56:58.215877 <6>[ 1.632532] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10303 00:56:58.222654 <6>[ 1.638720] igb: Intel(R) Gigabit Ethernet Network Driver
10304 00:56:58.229048 <6>[ 1.644369] igb: Copyright (c) 2007-2014 Intel Corporation.
10305 00:56:58.235653 <6>[ 1.650205] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10306 00:56:58.242153 <6>[ 1.656723] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10307 00:56:58.246099 <6>[ 1.663184] sky2: driver version 1.30
10308 00:56:58.252283 <6>[ 1.668106] usbcore: registered new device driver r8152-cfgselector
10309 00:56:58.258766 <6>[ 1.674642] usbcore: registered new interface driver r8152
10310 00:56:58.265221 <6>[ 1.680460] VFIO - User Level meta-driver version: 0.3
10311 00:56:58.271966 <6>[ 1.688719] usbcore: registered new interface driver usb-storage
10312 00:56:58.278709 <6>[ 1.695168] usbcore: registered new device driver onboard-usb-hub
10313 00:56:58.287615 <6>[ 1.704323] mt6397-rtc mt6359-rtc: registered as rtc0
10314 00:56:58.297537 <6>[ 1.709792] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:56:58 UTC (1718499418)
10315 00:56:58.300630 <6>[ 1.719360] i2c_dev: i2c /dev entries driver
10316 00:56:58.314792 <4>[ 1.731444] cpu cpu0: supply cpu not found, using dummy regulator
10317 00:56:58.321615 <4>[ 1.737870] cpu cpu1: supply cpu not found, using dummy regulator
10318 00:56:58.328697 <4>[ 1.744274] cpu cpu2: supply cpu not found, using dummy regulator
10319 00:56:58.334953 <4>[ 1.750676] cpu cpu3: supply cpu not found, using dummy regulator
10320 00:56:58.341408 <4>[ 1.757091] cpu cpu4: supply cpu not found, using dummy regulator
10321 00:56:58.347828 <4>[ 1.763486] cpu cpu5: supply cpu not found, using dummy regulator
10322 00:56:58.354380 <4>[ 1.769885] cpu cpu6: supply cpu not found, using dummy regulator
10323 00:56:58.361014 <4>[ 1.776280] cpu cpu7: supply cpu not found, using dummy regulator
10324 00:56:58.380449 <6>[ 1.796915] cpu cpu0: EM: created perf domain
10325 00:56:58.383417 <6>[ 1.801830] cpu cpu4: EM: created perf domain
10326 00:56:58.390767 <6>[ 1.807396] sdhci: Secure Digital Host Controller Interface driver
10327 00:56:58.397255 <6>[ 1.813826] sdhci: Copyright(c) Pierre Ossman
10328 00:56:58.404029 <6>[ 1.818742] Synopsys Designware Multimedia Card Interface Driver
10329 00:56:58.411150 <6>[ 1.825350] sdhci-pltfm: SDHCI platform and OF driver helper
10330 00:56:58.414096 <6>[ 1.825433] mmc0: CQHCI version 5.10
10331 00:56:58.420663 <6>[ 1.835288] ledtrig-cpu: registered to indicate activity on CPUs
10332 00:56:58.427528 <6>[ 1.842166] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10333 00:56:58.433924 <6>[ 1.849182] usbcore: registered new interface driver usbhid
10334 00:56:58.437177 <6>[ 1.855003] usbhid: USB HID core driver
10335 00:56:58.443682 <6>[ 1.859204] spi_master spi0: will run message pump with realtime priority
10336 00:56:58.485059 <6>[ 1.894872] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10337 00:56:58.503027 <6>[ 1.909852] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10338 00:56:58.506489 <6>[ 1.920592] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10339 00:56:58.513341 <6>[ 1.930047] cros-ec-spi spi0.0: Chrome EC device registered
10340 00:56:58.520152 <6>[ 1.936037] mmc0: Command Queue Engine enabled
10341 00:56:58.526715 <6>[ 1.940765] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10342 00:56:58.529958 <6>[ 1.948196] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10343 00:56:58.541054 <6>[ 1.957376] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10344 00:56:58.548608 <6>[ 1.964857] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10345 00:56:58.558150 <6>[ 1.968929] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10346 00:56:58.561471 <6>[ 1.970759] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10347 00:56:58.567844 <6>[ 1.980476] NET: Registered PF_PACKET protocol family
10348 00:56:58.574767 <6>[ 1.985248] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10349 00:56:58.577675 <6>[ 1.989991] 9pnet: Installing 9P2000 support
10350 00:56:58.584427 <5>[ 2.000992] Key type dns_resolver registered
10351 00:56:58.587666 <6>[ 2.005937] registered taskstats version 1
10352 00:56:58.594275 <5>[ 2.010312] Loading compiled-in X.509 certificates
10353 00:56:58.624042 <4>[ 2.034480] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10354 00:56:58.633970 <4>[ 2.045177] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10355 00:56:58.648216 <6>[ 2.065242] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10356 00:56:58.655206 <6>[ 2.072086] xhci-mtk 11200000.usb: xHCI Host Controller
10357 00:56:58.661567 <6>[ 2.077592] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10358 00:56:58.671746 <6>[ 2.085503] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10359 00:56:58.678422 <6>[ 2.094942] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10360 00:56:58.685279 <6>[ 2.101039] xhci-mtk 11200000.usb: xHCI Host Controller
10361 00:56:58.691849 <6>[ 2.106630] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10362 00:56:58.698470 <6>[ 2.114299] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10363 00:56:58.705374 <6>[ 2.122138] hub 1-0:1.0: USB hub found
10364 00:56:58.708763 <6>[ 2.126171] hub 1-0:1.0: 1 port detected
10365 00:56:58.718705 <6>[ 2.130464] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10366 00:56:58.721691 <6>[ 2.139211] hub 2-0:1.0: USB hub found
10367 00:56:58.725100 <6>[ 2.143230] hub 2-0:1.0: 1 port detected
10368 00:56:58.733161 <6>[ 2.150158] mtk-msdc 11f70000.mmc: Got CD GPIO
10369 00:56:58.752086 <6>[ 2.165673] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10370 00:56:58.762407 <6>[ 2.174051] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10371 00:56:58.768807 <6>[ 2.182393] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10372 00:56:58.778930 <6>[ 2.190732] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10373 00:56:58.785462 <6>[ 2.199072] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10374 00:56:58.795626 <6>[ 2.207411] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10375 00:56:58.801908 <6>[ 2.215748] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10376 00:56:58.811875 <6>[ 2.224086] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10377 00:56:58.818363 <6>[ 2.232424] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10378 00:56:58.828410 <6>[ 2.240762] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10379 00:56:58.835436 <6>[ 2.249111] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10380 00:56:58.845440 <6>[ 2.257448] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10381 00:56:58.851717 <6>[ 2.265785] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10382 00:56:58.861863 <6>[ 2.274121] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10383 00:56:58.869123 <6>[ 2.282458] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10384 00:56:58.874885 <6>[ 2.291133] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10385 00:56:58.881238 <6>[ 2.298295] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10386 00:56:58.888426 <6>[ 2.305050] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10387 00:56:58.898314 <6>[ 2.311794] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10388 00:56:58.905187 <6>[ 2.318749] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10389 00:56:58.911549 <6>[ 2.325594] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10390 00:56:58.921214 <6>[ 2.334726] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10391 00:56:58.930959 <6>[ 2.343846] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10392 00:56:58.941213 <6>[ 2.353138] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10393 00:56:58.950831 <6>[ 2.362604] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10394 00:56:58.960823 <6>[ 2.372070] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10395 00:56:58.967774 <6>[ 2.381190] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10396 00:56:58.977508 <6>[ 2.390656] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10397 00:56:58.987037 <6>[ 2.399774] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10398 00:56:58.997186 <6>[ 2.409071] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10399 00:56:59.007083 <6>[ 2.419231] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10400 00:56:59.017497 <6>[ 2.431372] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10401 00:56:59.025829 <6>[ 2.442407] Trying to probe devices needed for running init ...
10402 00:56:59.036320 <3>[ 2.449711] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10403 00:56:59.115935 <6>[ 2.529274] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10404 00:56:59.143190 <6>[ 2.560171] hub 2-1:1.0: USB hub found
10405 00:56:59.146540 <6>[ 2.564628] hub 2-1:1.0: 3 ports detected
10406 00:56:59.156137 <6>[ 2.572928] hub 2-1:1.0: USB hub found
10407 00:56:59.159186 <6>[ 2.577380] hub 2-1:1.0: 3 ports detected
10408 00:56:59.267478 <6>[ 2.681022] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10409 00:56:59.421961 <6>[ 2.839009] hub 1-1:1.0: USB hub found
10410 00:56:59.425225 <6>[ 2.843493] hub 1-1:1.0: 4 ports detected
10411 00:56:59.438555 <6>[ 2.855478] hub 1-1:1.0: USB hub found
10412 00:56:59.441651 <6>[ 2.859899] hub 1-1:1.0: 4 ports detected
10413 00:56:59.499543 <6>[ 2.913192] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10414 00:56:59.607160 <6>[ 3.021476] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10415 00:56:59.639502 <4>[ 3.053592] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10416 00:56:59.649427 <4>[ 3.062703] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10417 00:56:59.688067 <6>[ 3.105586] r8152 2-1.3:1.0 eth0: v1.12.13
10418 00:56:59.762720 <6>[ 3.177005] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10419 00:56:59.895682 <6>[ 3.313117] hub 1-1.4:1.0: USB hub found
10420 00:56:59.898984 <6>[ 3.317806] hub 1-1.4:1.0: 2 ports detected
10421 00:56:59.910736 <6>[ 3.328126] hub 1-1.4:1.0: USB hub found
10422 00:56:59.913885 <6>[ 3.332642] hub 1-1.4:1.0: 2 ports detected
10423 00:57:00.210935 <6>[ 3.624913] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10424 00:57:00.403059 <6>[ 3.816916] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10425 00:57:01.300733 <6>[ 4.717681] r8152 2-1.3:1.0 eth0: carrier on
10426 00:57:03.703044 <5>[ 4.744879] Sending DHCP requests .., OK
10427 00:57:03.709529 <6>[ 7.125243] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10428 00:57:03.713077 <6>[ 7.133556] IP-Config: Complete:
10429 00:57:03.726340 <6>[ 7.137053] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10430 00:57:03.733011 <6>[ 7.147778] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10431 00:57:03.739879 <6>[ 7.156403] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10432 00:57:03.746102 <6>[ 7.156413] nameserver0=192.168.201.1
10433 00:57:03.749508 <6>[ 7.168621] clk: Disabling unused clocks
10434 00:57:03.753276 <6>[ 7.174219] ALSA device list:
10435 00:57:03.760000 <6>[ 7.177488] No soundcards found.
10436 00:57:03.767320 <6>[ 7.184671] Freeing unused kernel memory: 8512K
10437 00:57:03.770501 <6>[ 7.189641] Run /init as init process
10438 00:57:03.780246 Loading, please wait...
10439 00:57:03.808198 Starting systemd-udevd version 252.22-1~deb12u1
10440 00:57:04.031059 <6>[ 7.445279] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10441 00:57:04.037482 <6>[ 7.451150] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10442 00:57:04.052287 <6>[ 7.466572] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10443 00:57:04.058701 <6>[ 7.471374] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10444 00:57:04.069210 <6>[ 7.474923] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10445 00:57:04.075841 <6>[ 7.482646] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10446 00:57:04.082401 <6>[ 7.490369] remoteproc remoteproc0: scp is available
10447 00:57:04.092527 <4>[ 7.490527] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10448 00:57:04.098520 <6>[ 7.491189] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10449 00:57:04.105300 <6>[ 7.491193] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10450 00:57:04.115036 <6>[ 7.499133] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10451 00:57:04.125059 <6>[ 7.501705] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10452 00:57:04.131684 <6>[ 7.501730] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10453 00:57:04.138679 <6>[ 7.501736] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10454 00:57:04.148582 <6>[ 7.501743] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10455 00:57:04.154761 <3>[ 7.502551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10456 00:57:04.164861 <3>[ 7.502564] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10457 00:57:04.171317 <3>[ 7.502568] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10458 00:57:04.178542 <6>[ 7.504472] remoteproc remoteproc0: powering up scp
10459 00:57:04.184830 <3>[ 7.516808] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10460 00:57:04.194603 <6>[ 7.521580] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10461 00:57:04.201049 <4>[ 7.526984] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10462 00:57:04.211195 <3>[ 7.529431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10463 00:57:04.214738 <6>[ 7.533988] mc: Linux media interface: v0.10
10464 00:57:04.221109 <4>[ 7.534193] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10465 00:57:04.228111 <6>[ 7.538110] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10466 00:57:04.234808 <3>[ 7.546020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10467 00:57:04.241606 <6>[ 7.565667] videodev: Linux video capture interface: v2.00
10468 00:57:04.247989 <3>[ 7.570869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10469 00:57:04.258332 <6>[ 7.575176] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10470 00:57:04.265294 <4>[ 7.598666] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10471 00:57:04.272024 <4>[ 7.598666] Fallback method does not support PEC.
10472 00:57:04.278384 <3>[ 7.600435] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10473 00:57:04.288304 <6>[ 7.618074] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10474 00:57:04.298237 <3>[ 7.624309] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10475 00:57:04.304663 <6>[ 7.632870] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10476 00:57:04.311882 <6>[ 7.634215] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10477 00:57:04.318292 <6>[ 7.634219] pci_bus 0000:00: root bus resource [bus 00-ff]
10478 00:57:04.324589 <6>[ 7.634223] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10479 00:57:04.334560 <6>[ 7.634225] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10480 00:57:04.341265 <6>[ 7.634253] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10481 00:57:04.347864 <6>[ 7.634266] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10482 00:57:04.354399 <6>[ 7.634335] pci 0000:00:00.0: supports D1 D2
10483 00:57:04.361143 <6>[ 7.634336] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10484 00:57:04.367304 <6>[ 7.635176] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10485 00:57:04.374575 <6>[ 7.635242] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10486 00:57:04.383993 <6>[ 7.635265] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10487 00:57:04.390600 <6>[ 7.635280] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10488 00:57:04.397294 <6>[ 7.635295] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10489 00:57:04.400508 <6>[ 7.635397] pci 0000:01:00.0: supports D1 D2
10490 00:57:04.410473 <6>[ 7.635398] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10491 00:57:04.416980 <3>[ 7.636854] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10492 00:57:04.427399 <3>[ 7.647850] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10493 00:57:04.433554 <6>[ 7.648907] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10494 00:57:04.440760 <6>[ 7.648935] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10495 00:57:04.450399 <6>[ 7.648942] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10496 00:57:04.456895 <6>[ 7.648955] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10497 00:57:04.463354 <6>[ 7.648971] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10498 00:57:04.473163 <6>[ 7.648987] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10499 00:57:04.476456 <6>[ 7.649003] pci 0000:00:00.0: PCI bridge to [bus 01]
10500 00:57:04.486393 <6>[ 7.649011] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10501 00:57:04.493019 <6>[ 7.649130] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10502 00:57:04.499468 <3>[ 7.649760] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10503 00:57:04.509629 <3>[ 7.649762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10504 00:57:04.516543 <3>[ 7.649815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10505 00:57:04.526316 <6>[ 7.650062] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10506 00:57:04.532589 <6>[ 7.650213] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10507 00:57:04.539099 <6>[ 7.650688] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10508 00:57:04.545553 <5>[ 7.674276] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10509 00:57:04.555669 <3>[ 7.677527] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10510 00:57:04.562092 <6>[ 7.678953] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10511 00:57:04.568638 <3>[ 7.679310] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10512 00:57:04.579033 <3>[ 7.679315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10513 00:57:04.585461 <6>[ 7.679320] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10514 00:57:04.595242 <3>[ 7.679327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10515 00:57:04.601935 <3>[ 7.679332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10516 00:57:04.611496 <3>[ 7.679360] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10517 00:57:04.615040 <6>[ 7.693946] Bluetooth: Core ver 2.22
10518 00:57:04.621658 <6>[ 7.695308] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10519 00:57:04.631440 <6>[ 7.697877] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10520 00:57:04.638342 <6>[ 7.701388] remoteproc remoteproc0: remote processor scp is now up
10521 00:57:04.645011 <5>[ 7.709533] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10522 00:57:04.651628 <5>[ 7.709986] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10523 00:57:04.661019 <4>[ 7.710067] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10524 00:57:04.664306 <6>[ 7.710075] cfg80211: failed to load regulatory.db
10525 00:57:04.671123 <6>[ 7.711268] NET: Registered PF_BLUETOOTH protocol family
10526 00:57:04.677691 <6>[ 7.720345] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10527 00:57:04.683951 <6>[ 7.728320] Bluetooth: HCI device and connection manager initialized
10528 00:57:04.690403 <6>[ 7.728344] Bluetooth: HCI socket layer initialized
10529 00:57:04.703695 <6>[ 7.736628] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10530 00:57:04.707048 <6>[ 7.740945] Bluetooth: L2CAP socket layer initialized
10531 00:57:04.713915 <6>[ 7.740952] Bluetooth: SCO socket layer initialized
10532 00:57:04.720059 <6>[ 7.748243] usbcore: registered new interface driver uvcvideo
10533 00:57:04.727009 <6>[ 7.758842] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10534 00:57:04.730123 <6>[ 7.812953] usbcore: registered new interface driver btusb
10535 00:57:04.740020 <4>[ 7.813990] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10536 00:57:04.746610 <3>[ 7.814008] Bluetooth: hci0: Failed to load firmware file (-2)
10537 00:57:04.753259 <3>[ 7.814016] Bluetooth: hci0: Failed to set up firmware (-2)
10538 00:57:04.763209 <4>[ 7.814024] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10539 00:57:04.769956 <6>[ 7.847307] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10540 00:57:04.776418 <6>[ 8.194486] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10541 00:57:04.803664 <6>[ 8.221692] mt7921e 0000:01:00.0: ASIC revision: 79610010
10542 00:57:04.905652 <6>[ 8.320315] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10543 00:57:04.908695 <6>[ 8.320315]
10544 00:57:04.923688 Begin: Loading essential drivers ... done.
10545 00:57:04.927102 Begin: Running /scripts/init-premount ... done.
10546 00:57:04.933649 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10547 00:57:04.943553 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10548 00:57:04.947125 Device /sys/class/net/eth0 found
10549 00:57:04.947203 done.
10550 00:57:04.953650 Begin: Waiting up to 180 secs for any network device to become available ... done.
10551 00:57:05.014874 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10552 00:57:05.021365 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10553 00:57:05.028041 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10554 00:57:05.034780 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10555 00:57:05.041264 host : mt8192-asurada-spherion-r0-cbg-4
10556 00:57:05.047983 domain : lava-rack
10557 00:57:05.051331 rootserver: 192.168.201.1 rootpath:
10558 00:57:05.051408 filename :
10559 00:57:05.077660 done.
10560 00:57:05.081045 Begin: Running /scripts/nfs-bottom ... done.
10561 00:57:05.102407 Begin: Running /scripts/init-bottom ... done.
10562 00:57:05.176041 <6>[ 8.590773] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10563 00:57:06.409095 <6>[ 9.826894] NET: Registered PF_INET6 protocol family
10564 00:57:06.416702 <6>[ 9.834769] Segment Routing with IPv6
10565 00:57:06.419914 <6>[ 9.838745] In-situ OAM (IOAM) with IPv6
10566 00:57:06.576780 <30>[ 9.968553] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10567 00:57:06.583149 <30>[ 10.001725] systemd[1]: Detected architecture arm64.
10568 00:57:06.589991
10569 00:57:06.593190 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10570 00:57:06.593282
10571 00:57:06.615897 <30>[ 10.034236] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10572 00:57:07.786605 <30>[ 11.201434] systemd[1]: Queued start job for default target graphical.target.
10573 00:57:07.824680 <30>[ 11.239050] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10574 00:57:07.831083 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10575 00:57:07.852157 <30>[ 11.267128] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10576 00:57:07.861784 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10577 00:57:07.880304 <30>[ 11.295091] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10578 00:57:07.890271 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10579 00:57:07.909059 <30>[ 11.323430] systemd[1]: Created slice user.slice - User and Session Slice.
10580 00:57:07.915642 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10581 00:57:07.938091 <30>[ 11.349452] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10582 00:57:07.945006 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10583 00:57:07.966087 <30>[ 11.377349] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10584 00:57:07.972638 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10585 00:57:08.001013 <30>[ 11.405657] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10586 00:57:08.010903 <30>[ 11.425581] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10587 00:57:08.017385 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10588 00:57:08.034645 <30>[ 11.449477] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10589 00:57:08.044929 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10590 00:57:08.062617 <30>[ 11.477227] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10591 00:57:08.072317 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10592 00:57:08.087474 <30>[ 11.505653] systemd[1]: Reached target paths.target - Path Units.
10593 00:57:08.097493 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10594 00:57:08.115053 <30>[ 11.529502] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10595 00:57:08.121074 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10596 00:57:08.134917 <30>[ 11.553079] systemd[1]: Reached target slices.target - Slice Units.
10597 00:57:08.145080 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10598 00:57:08.158989 <30>[ 11.577576] systemd[1]: Reached target swap.target - Swaps.
10599 00:57:08.165711 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10600 00:57:08.186466 <30>[ 11.601609] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10601 00:57:08.196263 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10602 00:57:08.214884 <30>[ 11.629979] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10603 00:57:08.224755 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10604 00:57:08.244905 <30>[ 11.660151] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10605 00:57:08.255060 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10606 00:57:08.271576 <30>[ 11.686488] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10607 00:57:08.281171 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10608 00:57:08.298764 <30>[ 11.713849] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10609 00:57:08.305049 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10610 00:57:08.323298 <30>[ 11.738576] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10611 00:57:08.333119 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10612 00:57:08.352953 <30>[ 11.767925] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10613 00:57:08.362811 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10614 00:57:08.378756 <30>[ 11.793628] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10615 00:57:08.388164 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10616 00:57:08.446303 <30>[ 11.861225] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10617 00:57:08.453079 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10618 00:57:08.475348 <30>[ 11.890306] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10619 00:57:08.482320 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10620 00:57:08.507769 <30>[ 11.922278] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10621 00:57:08.513482 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10622 00:57:08.541900 <30>[ 11.949669] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10623 00:57:08.557015 <30>[ 11.971947] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10624 00:57:08.567052 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10625 00:57:08.586204 <30>[ 12.000707] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10626 00:57:08.592741 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10627 00:57:08.620866 <30>[ 12.035559] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10628 00:57:08.627546 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10629 00:57:08.652708 <30>[ 12.067519] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10630 00:57:08.662749 Startin<6>[ 12.076513] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10631 00:57:08.669413 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10632 00:57:08.693086 <30>[ 12.107579] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10633 00:57:08.702762 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10634 00:57:08.724433 <30>[ 12.139347] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10635 00:57:08.731140 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10636 00:57:08.756116 <30>[ 12.171375] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10637 00:57:08.762717 Startin<6>[ 12.181084] fuse: init (API version 7.37)
10638 00:57:08.769640 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10639 00:57:08.838742 <30>[ 12.254103] systemd[1]: Starting systemd-journald.service - Journal Service...
10640 00:57:08.845291 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10641 00:57:08.878936 <30>[ 12.294215] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10642 00:57:08.885730 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10643 00:57:08.916160 <30>[ 12.328369] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10644 00:57:08.922760 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10645 00:57:08.946679 <30>[ 12.361755] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10646 00:57:08.956654 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10647 00:57:08.979773 <30>[ 12.395109] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10648 00:57:08.986297 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10649 00:57:09.008513 <3>[ 12.423630] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10650 00:57:09.015300 <30>[ 12.425522] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10651 00:57:09.024742 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10652 00:57:09.039468 <3>[ 12.454605] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10653 00:57:09.049389 <30>[ 12.464426] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10654 00:57:09.055863 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10655 00:57:09.074307 <3>[ 12.489682] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 00:57:09.084144 <30>[ 12.489894] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10657 00:57:09.090680 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10658 00:57:09.104032 <3>[ 12.519436] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10659 00:57:09.114069 <30>[ 12.529205] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10660 00:57:09.124910 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10661 00:57:09.131385 <3>[ 12.547555] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10662 00:57:09.143497 <30>[ 12.558615] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10663 00:57:09.150447 <30>[ 12.566703] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10664 00:57:09.163791 [[0;32m OK [0m] Finished [0<3>[ 12.577069] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10665 00:57:09.170524 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10666 00:57:09.184131 <30>[ 12.602112] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10667 00:57:09.194694 <3>[ 12.608356] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10668 00:57:09.204397 <30>[ 12.610631] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10669 00:57:09.210790 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10670 00:57:09.221902 <3>[ 12.637045] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10671 00:57:09.233292 <30>[ 12.648012] systemd[1]: modprobe@drm.service: Deactivated successfully.
10672 00:57:09.240142 <30>[ 12.655921] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10673 00:57:09.253414 [[0;32m OK [0m] Finished [0<3>[ 12.665878] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10674 00:57:09.256860 ;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10675 00:57:09.275857 <30>[ 12.689885] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10676 00:57:09.282110 <3>[ 12.694466] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10677 00:57:09.292524 <30>[ 12.697848] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10678 00:57:09.298874 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10679 00:57:09.313087 <3>[ 12.727656] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10680 00:57:09.323358 <30>[ 12.738053] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10681 00:57:09.330161 <30>[ 12.745469] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10682 00:57:09.339778 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10683 00:57:09.350604 <3>[ 12.764988] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10684 00:57:09.357182 <3>[ 12.765851] power_supply sbs-5-000b: driver failed to report `health' property: -6
10685 00:57:09.367445 <30>[ 12.774594] systemd[1]: modprobe@loop.service: Deactivated successfully.
10686 00:57:09.381149 <4>[ 12.781618] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10687 00:57:09.387863 <30>[ 12.788886] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10688 00:57:09.398265 <3>[ 12.796311] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10689 00:57:09.404842 <3>[ 12.804276] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10690 00:57:09.414869 <3>[ 12.819968] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10691 00:57:09.421744 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10692 00:57:09.439595 <30>[ 12.853855] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10693 00:57:09.446266 <3>[ 12.859562] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 00:57:09.456062 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10695 00:57:09.478481 <30>[ 12.889808] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10696 00:57:09.485672 <3>[ 12.895025] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10697 00:57:09.494942 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10698 00:57:09.515322 <30>[ 12.929706] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10699 00:57:09.525096 <3>[ 12.931920] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10700 00:57:09.531714 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10701 00:57:09.551138 <30>[ 12.965801] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10702 00:57:09.561077 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10703 00:57:09.578828 <30>[ 12.993786] systemd[1]: Reached target network-pre.target - Preparation for Network.
10704 00:57:09.585874 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10705 00:57:09.646889 <30>[ 13.061540] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10706 00:57:09.653085 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10707 00:57:09.679334 <30>[ 13.094468] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10708 00:57:09.689267 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10709 00:57:09.709370 <30>[ 13.121284] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10710 00:57:09.726627 <30>[ 13.134985] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10711 00:57:09.741512 <30>[ 13.156515] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10712 00:57:09.748147 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10713 00:57:09.775074 <30>[ 13.186977] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10714 00:57:09.823731 <30>[ 13.237892] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10715 00:57:09.829387 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10716 00:57:09.860667 <30>[ 13.274709] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10717 00:57:09.866591 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10718 00:57:09.893403 <30>[ 13.308138] systemd[1]: Started systemd-journald.service - Journal Service.
10719 00:57:09.899616 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10720 00:57:09.924708 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10721 00:57:09.943338 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10722 00:57:09.964457 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10723 00:57:09.984187 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10724 00:57:10.004062 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10725 00:57:10.062749 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10726 00:57:10.081189 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10727 00:57:10.129623 <46>[ 13.544688] systemd-journald[308]: Received client request to flush runtime journal.
10728 00:57:10.167185 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10729 00:57:10.186552 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10730 00:57:10.202115 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10731 00:57:10.935072 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10732 00:57:11.563563 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10733 00:57:11.602541 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10734 00:57:11.650818 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10735 00:57:11.723644 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10736 00:57:11.777113 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10737 00:57:12.076755 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10738 00:57:12.131409 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10739 00:57:12.140046 <6>[ 15.558868] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10740 00:57:12.170597 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10741 00:57:12.222506 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10742 00:57:12.255298 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10743 00:57:12.277408 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10744 00:57:12.321562 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10745 00:57:12.341835 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10746 00:57:12.355070 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10747 00:57:12.423203 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10748 00:57:12.498782 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10749 00:57:12.524480 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10750 00:57:12.582941 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10751 00:57:12.719219 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10752 00:57:12.742231 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10753 00:57:12.762615 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10754 00:57:12.778367 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10755 00:57:12.803351 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10756 00:57:12.824766 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10757 00:57:12.842784 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10758 00:57:12.861708 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10759 00:57:12.881653 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10760 00:57:12.897879 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10761 00:57:12.916184 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10762 00:57:12.933461 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10763 00:57:12.950102 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10764 00:57:12.988727 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10765 00:57:13.046614 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10766 00:57:13.167322 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10767 00:57:13.193664 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10768 00:57:13.341272 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10769 00:57:13.398014 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10770 00:57:13.419558 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10771 00:57:13.437857 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10772 00:57:13.454706 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10773 00:57:13.489778 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10774 00:57:13.509893 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10775 00:57:13.527770 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10776 00:57:13.546973 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10777 00:57:13.607372 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10778 00:57:13.658310 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10779 00:57:13.756540
10780 00:57:13.759728 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10781 00:57:13.759807
10782 00:57:13.762870 debian-bookworm-arm64 login: root (automatic login)
10783 00:57:13.762943
10784 00:57:14.049043 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
10785 00:57:14.049178
10786 00:57:14.055600 The programs included with the Debian GNU/Linux system are free software;
10787 00:57:14.062148 the exact distribution terms for each program are described in the
10788 00:57:14.065542 individual files in /usr/share/doc/*/copyright.
10789 00:57:14.065612
10790 00:57:14.072216 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10791 00:57:14.075546 permitted by applicable law.
10792 00:57:14.935946 Matched prompt #10: / #
10794 00:57:14.936205 Setting prompt string to ['/ #']
10795 00:57:14.936294 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10797 00:57:14.936469 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10798 00:57:14.936552 start: 2.2.6 expect-shell-connection (timeout 00:03:42) [common]
10799 00:57:14.936620 Setting prompt string to ['/ #']
10800 00:57:14.936675 Forcing a shell prompt, looking for ['/ #']
10802 00:57:14.986893 / #
10803 00:57:14.987111 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10804 00:57:14.987189 Waiting using forced prompt support (timeout 00:02:30)
10805 00:57:14.992131
10806 00:57:14.992399 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10807 00:57:14.992491 start: 2.2.7 export-device-env (timeout 00:03:42) [common]
10809 00:57:15.093142 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368566/extract-nfsrootfs-k6gbqes9'
10810 00:57:15.099427 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368566/extract-nfsrootfs-k6gbqes9'
10812 00:57:15.200635 / # export NFS_SERVER_IP='192.168.201.1'
10813 00:57:15.206118 export NFS_SERVER_IP='192.168.201.1'
10814 00:57:15.206399 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10815 00:57:15.206494 end: 2.2 depthcharge-retry (duration 00:01:18) [common]
10816 00:57:15.206580 end: 2 depthcharge-action (duration 00:01:18) [common]
10817 00:57:15.206666 start: 3 lava-test-retry (timeout 00:08:01) [common]
10818 00:57:15.206747 start: 3.1 lava-test-shell (timeout 00:08:01) [common]
10819 00:57:15.206815 Using namespace: common
10821 00:57:15.307177 / # #
10822 00:57:15.307386 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10823 00:57:15.312206 #
10824 00:57:15.312460 Using /lava-14368566
10826 00:57:15.412772 / # export SHELL=/bin/bash
10827 00:57:15.418118 export SHELL=/bin/bash
10829 00:57:15.518681 / # . /lava-14368566/environment
10830 00:57:15.523628 . /lava-14368566/environment
10832 00:57:15.629776 / # /lava-14368566/bin/lava-test-runner /lava-14368566/0
10833 00:57:15.629978 Test shell timeout: 10s (minimum of the action and connection timeout)
10834 00:57:15.634897 /lava-14368566/bin/lava-test-runner /lava-14368566/0
10835 00:57:15.843614 + export TESTRUN_ID=0_timesync-off
10836 00:57:15.846806 + TESTRUN_ID=0_timesync-off
10837 00:57:15.849909 + cd /lava-14368566/0/tests/0_timesync-off
10838 00:57:15.853298 ++ cat uuid
10839 00:57:15.853367 + UUID=14368566_1.6.2.3.1
10840 00:57:15.856911 + set +x
10841 00:57:15.859719 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368566_1.6.2.3.1>
10842 00:57:15.859964 Received signal: <STARTRUN> 0_timesync-off 14368566_1.6.2.3.1
10843 00:57:15.860031 Starting test lava.0_timesync-off (14368566_1.6.2.3.1)
10844 00:57:15.860112 Skipping test definition patterns.
10845 00:57:15.862943 + systemctl stop systemd-timesyncd
10846 00:57:15.929486 + set +x
10847 00:57:15.932675 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368566_1.6.2.3.1>
10848 00:57:15.932923 Received signal: <ENDRUN> 0_timesync-off 14368566_1.6.2.3.1
10849 00:57:15.933009 Ending use of test pattern.
10850 00:57:15.933068 Ending test lava.0_timesync-off (14368566_1.6.2.3.1), duration 0.07
10852 00:57:15.980056 + export TESTRUN_ID=1_kselftest-alsa
10853 00:57:15.983081 + TESTRUN_ID=1_kselftest-alsa
10854 00:57:15.990311 + cd /lava-14368566/0/tests/1_kselftest-alsa
10855 00:57:15.990388 ++ cat uuid
10856 00:57:15.993230 + UUID=14368566_1.6.2.3.5
10857 00:57:15.993307 + set +x
10858 00:57:15.996445 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14368566_1.6.2.3.5>
10859 00:57:15.996689 Received signal: <STARTRUN> 1_kselftest-alsa 14368566_1.6.2.3.5
10860 00:57:15.996753 Starting test lava.1_kselftest-alsa (14368566_1.6.2.3.5)
10861 00:57:15.996834 Skipping test definition patterns.
10862 00:57:15.999607 + cd ./automated/linux/kselftest/
10863 00:57:16.029303 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10864 00:57:16.055025 INFO: install_deps skipped
10865 00:57:16.554885 --2024-06-16 00:57:16-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10866 00:57:16.561484 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10867 00:57:16.683400 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10868 00:57:16.808424 HTTP request sent, awaiting response... 200 OK
10869 00:57:16.811138 Length: 1647948 (1.6M) [application/octet-stream]
10870 00:57:16.814741 Saving to: 'kselftest_armhf.tar.gz'
10871 00:57:16.814818
10872 00:57:16.814878
10873 00:57:17.057757 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
10874 00:57:17.307199 kselftest_armhf.tar 3%[ ] 49.22K 198KB/s
10875 00:57:17.726979 kselftest_armhf.tar 13%[=> ] 219.84K 441KB/s
10876 00:57:17.733476 kselftest_armhf.tar 45%[========> ] 727.97K 793KB/s
10877 00:57:17.743570 kselftest_armhf.tar 100%[===================>] 1.57M 1.69MB/s in 0.9s
10878 00:57:17.744026
10879 00:57:17.895104 2024-06-16 00:57:17 (1.69 MB/s) - 'kselftest_armhf.tar.gz' saved [1647948/1647948]
10880 00:57:17.895606
10881 00:57:22.085438 skiplist:
10882 00:57:22.088629 ========================================
10883 00:57:22.091977 ========================================
10884 00:57:22.140996 alsa:mixer-test
10885 00:57:22.161129 ============== Tests to run ===============
10886 00:57:22.161532 alsa:mixer-test
10887 00:57:22.164166 ===========End Tests to run ===============
10888 00:57:22.167565 shardfile-alsa pass
10889 00:57:22.271858 <12>[ 25.691521] kselftest: Running tests in alsa
10890 00:57:22.280857 TAP version 13
10891 00:57:22.295382 1..1
10892 00:57:22.308500 # selftests: alsa: mixer-test
10893 00:57:22.826537 # TAP version 13
10894 00:57:22.826984 # 1..0
10895 00:57:22.833627 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
10896 00:57:22.836804 ok 1 selftests: alsa: mixer-test
10897 00:57:24.373007 alsa_mixer-test pass
10898 00:57:24.452439 + ../../utils/send-to-lava.sh ./output/result.txt
10899 00:57:24.516661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
10900 00:57:24.517338 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
10902 00:57:24.566503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10903 00:57:24.566916 + set +x
10904 00:57:24.567467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10906 00:57:24.573412 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14368566_1.6.2.3.5>
10907 00:57:24.574045 Received signal: <ENDRUN> 1_kselftest-alsa 14368566_1.6.2.3.5
10908 00:57:24.574435 Ending use of test pattern.
10909 00:57:24.574727 Ending test lava.1_kselftest-alsa (14368566_1.6.2.3.5), duration 8.58
10911 00:57:24.576326 <LAVA_TEST_RUNNER EXIT>
10912 00:57:24.577037 ok: lava_test_shell seems to have completed
10913 00:57:24.577524 alsa_mixer-test: pass
shardfile-alsa: pass
10914 00:57:24.577930 end: 3.1 lava-test-shell (duration 00:00:09) [common]
10915 00:57:24.578362 end: 3 lava-test-retry (duration 00:00:09) [common]
10916 00:57:24.578786 start: 4 finalize (timeout 00:07:51) [common]
10917 00:57:24.579210 start: 4.1 power-off (timeout 00:00:30) [common]
10918 00:57:24.579977 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
10919 00:57:24.836823 >> Command sent successfully.
10920 00:57:24.850347 Returned 0 in 0 seconds
10921 00:57:24.951600 end: 4.1 power-off (duration 00:00:00) [common]
10923 00:57:24.952964 start: 4.2 read-feedback (timeout 00:07:51) [common]
10924 00:57:24.954238 Listened to connection for namespace 'common' for up to 1s
10925 00:57:25.954479 Finalising connection for namespace 'common'
10926 00:57:25.955032 Disconnecting from shell: Finalise
10927 00:57:25.955467 / #
10928 00:57:26.056301 end: 4.2 read-feedback (duration 00:00:01) [common]
10929 00:57:26.056938 end: 4 finalize (duration 00:00:01) [common]
10930 00:57:26.057534 Cleaning after the job
10931 00:57:26.058073 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/ramdisk
10932 00:57:26.068310 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/kernel
10933 00:57:26.101943 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/dtb
10934 00:57:26.102259 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/nfsrootfs
10935 00:57:26.167476 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368566/tftp-deploy-3k9xqh2p/modules
10936 00:57:26.173138 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368566
10937 00:57:26.718008 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368566
10938 00:57:26.718182 Job finished correctly