Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 40
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 00:54:56.489426 lava-dispatcher, installed at version: 2024.03
2 00:54:56.489649 start: 0 validate
3 00:54:56.489794 Start time: 2024-06-16 00:54:56.489785+00:00 (UTC)
4 00:54:56.489922 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:54:56.490050 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:54:56.743686 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:54:56.744745 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:54:56.997822 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:54:56.998585 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:55:36.963641 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:55:36.964315 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:55:37.461475 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:55:37.462247 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:55:37.724780 validate duration: 41.24
16 00:55:37.726111 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:55:37.726728 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:55:37.727209 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:55:37.727823 Not decompressing ramdisk as can be used compressed.
20 00:55:37.728349 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:55:37.728721 saving as /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/ramdisk/initrd.cpio.gz
22 00:55:37.729081 total size: 5628169 (5 MB)
23 00:55:40.860737 progress 0 % (0 MB)
24 00:55:40.870543 progress 5 % (0 MB)
25 00:55:40.879948 progress 10 % (0 MB)
26 00:55:40.888409 progress 15 % (0 MB)
27 00:55:40.894833 progress 20 % (1 MB)
28 00:55:40.898991 progress 25 % (1 MB)
29 00:55:40.902697 progress 30 % (1 MB)
30 00:55:40.905896 progress 35 % (1 MB)
31 00:55:40.908500 progress 40 % (2 MB)
32 00:55:40.911141 progress 45 % (2 MB)
33 00:55:40.913357 progress 50 % (2 MB)
34 00:55:40.915662 progress 55 % (2 MB)
35 00:55:40.917859 progress 60 % (3 MB)
36 00:55:40.919842 progress 65 % (3 MB)
37 00:55:40.921888 progress 70 % (3 MB)
38 00:55:40.923704 progress 75 % (4 MB)
39 00:55:40.925554 progress 80 % (4 MB)
40 00:55:40.927155 progress 85 % (4 MB)
41 00:55:40.928946 progress 90 % (4 MB)
42 00:55:40.930590 progress 95 % (5 MB)
43 00:55:40.932038 progress 100 % (5 MB)
44 00:55:40.932251 5 MB downloaded in 3.20 s (1.68 MB/s)
45 00:55:40.932405 end: 1.1.1 http-download (duration 00:00:03) [common]
47 00:55:40.932656 end: 1.1 download-retry (duration 00:00:03) [common]
48 00:55:40.932745 start: 1.2 download-retry (timeout 00:09:57) [common]
49 00:55:40.932832 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 00:55:40.932967 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:55:40.933038 saving as /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/kernel/Image
52 00:55:40.933100 total size: 54813184 (52 MB)
53 00:55:40.933164 No compression specified
54 00:55:40.934329 progress 0 % (0 MB)
55 00:55:40.948336 progress 5 % (2 MB)
56 00:55:40.962572 progress 10 % (5 MB)
57 00:55:40.976407 progress 15 % (7 MB)
58 00:55:40.990611 progress 20 % (10 MB)
59 00:55:41.004725 progress 25 % (13 MB)
60 00:55:41.018548 progress 30 % (15 MB)
61 00:55:41.032646 progress 35 % (18 MB)
62 00:55:41.046480 progress 40 % (20 MB)
63 00:55:41.060365 progress 45 % (23 MB)
64 00:55:41.074558 progress 50 % (26 MB)
65 00:55:41.088719 progress 55 % (28 MB)
66 00:55:41.102470 progress 60 % (31 MB)
67 00:55:41.116487 progress 65 % (34 MB)
68 00:55:41.130218 progress 70 % (36 MB)
69 00:55:41.144100 progress 75 % (39 MB)
70 00:55:41.157916 progress 80 % (41 MB)
71 00:55:41.171637 progress 85 % (44 MB)
72 00:55:41.185798 progress 90 % (47 MB)
73 00:55:41.199801 progress 95 % (49 MB)
74 00:55:41.213529 progress 100 % (52 MB)
75 00:55:41.213789 52 MB downloaded in 0.28 s (186.24 MB/s)
76 00:55:41.213989 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:55:41.214303 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:55:41.214391 start: 1.3 download-retry (timeout 00:09:57) [common]
80 00:55:41.214474 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 00:55:41.214609 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:55:41.214681 saving as /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/dtb/mt8192-asurada-spherion-r0.dtb
83 00:55:41.214743 total size: 47258 (0 MB)
84 00:55:41.214804 No compression specified
85 00:55:41.215898 progress 69 % (0 MB)
86 00:55:41.216223 progress 100 % (0 MB)
87 00:55:41.216381 0 MB downloaded in 0.00 s (27.55 MB/s)
88 00:55:41.216503 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:55:41.216721 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:55:41.216806 start: 1.4 download-retry (timeout 00:09:57) [common]
92 00:55:41.216888 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 00:55:41.216998 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:55:41.217064 saving as /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/nfsrootfs/full.rootfs.tar
95 00:55:41.217125 total size: 120894716 (115 MB)
96 00:55:41.217186 Using unxz to decompress xz
97 00:55:41.221218 progress 0 % (0 MB)
98 00:55:41.567440 progress 5 % (5 MB)
99 00:55:41.927027 progress 10 % (11 MB)
100 00:55:42.275269 progress 15 % (17 MB)
101 00:55:42.601141 progress 20 % (23 MB)
102 00:55:42.894692 progress 25 % (28 MB)
103 00:55:43.250419 progress 30 % (34 MB)
104 00:55:43.586063 progress 35 % (40 MB)
105 00:55:43.750123 progress 40 % (46 MB)
106 00:55:43.928489 progress 45 % (51 MB)
107 00:55:44.236924 progress 50 % (57 MB)
108 00:55:44.606538 progress 55 % (63 MB)
109 00:55:44.947272 progress 60 % (69 MB)
110 00:55:45.299310 progress 65 % (74 MB)
111 00:55:45.643016 progress 70 % (80 MB)
112 00:55:46.001764 progress 75 % (86 MB)
113 00:55:46.348432 progress 80 % (92 MB)
114 00:55:46.693834 progress 85 % (98 MB)
115 00:55:47.051401 progress 90 % (103 MB)
116 00:55:47.382400 progress 95 % (109 MB)
117 00:55:47.742154 progress 100 % (115 MB)
118 00:55:47.747569 115 MB downloaded in 6.53 s (17.65 MB/s)
119 00:55:47.747853 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:55:47.748130 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:55:47.748226 start: 1.5 download-retry (timeout 00:09:50) [common]
123 00:55:47.748310 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 00:55:47.748464 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:55:47.748535 saving as /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/modules/modules.tar
126 00:55:47.748596 total size: 8617404 (8 MB)
127 00:55:47.748660 Using unxz to decompress xz
128 00:55:47.752802 progress 0 % (0 MB)
129 00:55:47.771816 progress 5 % (0 MB)
130 00:55:47.800795 progress 10 % (0 MB)
131 00:55:47.831491 progress 15 % (1 MB)
132 00:55:47.855817 progress 20 % (1 MB)
133 00:55:47.879665 progress 25 % (2 MB)
134 00:55:47.904846 progress 30 % (2 MB)
135 00:55:47.932797 progress 35 % (2 MB)
136 00:55:47.959300 progress 40 % (3 MB)
137 00:55:47.983890 progress 45 % (3 MB)
138 00:55:48.009475 progress 50 % (4 MB)
139 00:55:48.036169 progress 55 % (4 MB)
140 00:55:48.062445 progress 60 % (4 MB)
141 00:55:48.088492 progress 65 % (5 MB)
142 00:55:48.117159 progress 70 % (5 MB)
143 00:55:48.142616 progress 75 % (6 MB)
144 00:55:48.170169 progress 80 % (6 MB)
145 00:55:48.196432 progress 85 % (7 MB)
146 00:55:48.223425 progress 90 % (7 MB)
147 00:55:48.250278 progress 95 % (7 MB)
148 00:55:48.277237 progress 100 % (8 MB)
149 00:55:48.283396 8 MB downloaded in 0.53 s (15.37 MB/s)
150 00:55:48.283676 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:55:48.283956 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:55:48.284055 start: 1.6 prepare-tftp-overlay (timeout 00:09:49) [common]
154 00:55:48.284151 start: 1.6.1 extract-nfsrootfs (timeout 00:09:49) [common]
155 00:55:51.740160 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368594/extract-nfsrootfs-bv0vk0cp
156 00:55:51.740376 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 00:55:51.740478 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 00:55:51.740654 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1
159 00:55:51.740785 makedir: /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin
160 00:55:51.740888 makedir: /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/tests
161 00:55:51.740987 makedir: /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/results
162 00:55:51.741091 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-add-keys
163 00:55:51.741236 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-add-sources
164 00:55:51.741367 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-background-process-start
165 00:55:51.741496 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-background-process-stop
166 00:55:51.741622 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-common-functions
167 00:55:51.741747 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-echo-ipv4
168 00:55:51.741874 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-install-packages
169 00:55:51.742001 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-installed-packages
170 00:55:51.742126 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-os-build
171 00:55:51.742298 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-probe-channel
172 00:55:51.742424 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-probe-ip
173 00:55:51.742549 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-target-ip
174 00:55:51.742672 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-target-mac
175 00:55:51.742820 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-target-storage
176 00:55:51.742963 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-test-case
177 00:55:51.743090 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-test-event
178 00:55:51.743216 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-test-feedback
179 00:55:51.743340 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-test-raise
180 00:55:51.743463 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-test-reference
181 00:55:51.743589 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-test-runner
182 00:55:51.743713 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-test-set
183 00:55:51.743839 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-test-shell
184 00:55:51.743966 Updating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-add-keys (debian)
185 00:55:51.744120 Updating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-add-sources (debian)
186 00:55:51.744262 Updating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-install-packages (debian)
187 00:55:51.744400 Updating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-installed-packages (debian)
188 00:55:51.744537 Updating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/bin/lava-os-build (debian)
189 00:55:51.744658 Creating /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/environment
190 00:55:51.744757 LAVA metadata
191 00:55:51.744886 - LAVA_JOB_ID=14368594
192 00:55:51.744964 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:55:51.745068 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 00:55:51.745136 skipped lava-vland-overlay
195 00:55:51.745212 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:55:51.745292 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 00:55:51.745365 skipped lava-multinode-overlay
198 00:55:51.745438 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:55:51.745516 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 00:55:51.745592 Loading test definitions
201 00:55:51.745679 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 00:55:51.745750 Using /lava-14368594 at stage 0
203 00:55:51.746041 uuid=14368594_1.6.2.3.1 testdef=None
204 00:55:51.746131 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:55:51.746221 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 00:55:51.746684 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:55:51.746910 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 00:55:51.747469 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:55:51.747702 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 00:55:51.748234 runner path: /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/0/tests/0_timesync-off test_uuid 14368594_1.6.2.3.1
213 00:55:51.748431 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:55:51.748699 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 00:55:51.748773 Using /lava-14368594 at stage 0
217 00:55:51.748872 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:55:51.748962 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/0/tests/1_kselftest-arm64'
219 00:55:53.697501 Running '/usr/bin/git checkout kernelci.org
220 00:55:53.843579 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 00:55:53.844330 uuid=14368594_1.6.2.3.5 testdef=None
222 00:55:53.844494 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 00:55:53.844742 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 00:55:53.845508 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:55:53.845750 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 00:55:53.846794 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:55:53.847038 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 00:55:53.847984 runner path: /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/0/tests/1_kselftest-arm64 test_uuid 14368594_1.6.2.3.5
232 00:55:53.848079 BOARD='mt8192-asurada-spherion-r0'
233 00:55:53.848145 BRANCH='cip-gitlab'
234 00:55:53.848205 SKIPFILE='/dev/null'
235 00:55:53.848264 SKIP_INSTALL='True'
236 00:55:53.848320 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:55:53.848378 TST_CASENAME=''
238 00:55:53.848434 TST_CMDFILES='arm64'
239 00:55:53.848581 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:55:53.848795 Creating lava-test-runner.conf files
242 00:55:53.848860 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368594/lava-overlay-feb2qlw1/lava-14368594/0 for stage 0
243 00:55:53.848954 - 0_timesync-off
244 00:55:53.849023 - 1_kselftest-arm64
245 00:55:53.849116 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 00:55:53.849205 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 00:56:01.320487 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:56:01.320646 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 00:56:01.320741 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:56:01.320844 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 00:56:01.320937 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 00:56:01.483774 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:56:01.484167 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 00:56:01.484278 extracting modules file /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368594/extract-nfsrootfs-bv0vk0cp
255 00:56:01.709198 extracting modules file /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368594/extract-overlay-ramdisk-xoc59a9v/ramdisk
256 00:56:01.928265 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:56:01.928439 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 00:56:01.928543 [common] Applying overlay to NFS
259 00:56:01.928619 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368594/compress-overlay-3ndtwmap/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368594/extract-nfsrootfs-bv0vk0cp
260 00:56:02.835094 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:56:02.835272 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 00:56:02.835368 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:56:02.835460 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 00:56:02.835541 Building ramdisk /var/lib/lava/dispatcher/tmp/14368594/extract-overlay-ramdisk-xoc59a9v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368594/extract-overlay-ramdisk-xoc59a9v/ramdisk
265 00:56:03.174801 >> 130405 blocks
266 00:56:05.238633 rename /var/lib/lava/dispatcher/tmp/14368594/extract-overlay-ramdisk-xoc59a9v/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/ramdisk/ramdisk.cpio.gz
267 00:56:05.239084 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:56:05.239198 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 00:56:05.239299 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 00:56:05.239405 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/kernel/Image']
271 00:56:18.767100 Returned 0 in 13 seconds
272 00:56:18.867737 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/kernel/image.itb
273 00:56:19.221961 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:56:19.222382 output: Created: Sun Jun 16 01:56:19 2024
275 00:56:19.222462 output: Image 0 (kernel-1)
276 00:56:19.222532 output: Description:
277 00:56:19.222599 output: Created: Sun Jun 16 01:56:19 2024
278 00:56:19.222665 output: Type: Kernel Image
279 00:56:19.222728 output: Compression: lzma compressed
280 00:56:19.222786 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
281 00:56:19.222846 output: Architecture: AArch64
282 00:56:19.222904 output: OS: Linux
283 00:56:19.222961 output: Load Address: 0x00000000
284 00:56:19.223020 output: Entry Point: 0x00000000
285 00:56:19.223081 output: Hash algo: crc32
286 00:56:19.223138 output: Hash value: f6f06660
287 00:56:19.223197 output: Image 1 (fdt-1)
288 00:56:19.223253 output: Description: mt8192-asurada-spherion-r0
289 00:56:19.223309 output: Created: Sun Jun 16 01:56:19 2024
290 00:56:19.223365 output: Type: Flat Device Tree
291 00:56:19.223419 output: Compression: uncompressed
292 00:56:19.223473 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:56:19.223527 output: Architecture: AArch64
294 00:56:19.223580 output: Hash algo: crc32
295 00:56:19.223634 output: Hash value: 0f8e4d2e
296 00:56:19.223687 output: Image 2 (ramdisk-1)
297 00:56:19.223740 output: Description: unavailable
298 00:56:19.223794 output: Created: Sun Jun 16 01:56:19 2024
299 00:56:19.223848 output: Type: RAMDisk Image
300 00:56:19.223901 output: Compression: Unknown Compression
301 00:56:19.223954 output: Data Size: 18742027 Bytes = 18302.76 KiB = 17.87 MiB
302 00:56:19.224022 output: Architecture: AArch64
303 00:56:19.224079 output: OS: Linux
304 00:56:19.224133 output: Load Address: unavailable
305 00:56:19.224186 output: Entry Point: unavailable
306 00:56:19.224238 output: Hash algo: crc32
307 00:56:19.224291 output: Hash value: e78ff59b
308 00:56:19.224345 output: Default Configuration: 'conf-1'
309 00:56:19.224398 output: Configuration 0 (conf-1)
310 00:56:19.224451 output: Description: mt8192-asurada-spherion-r0
311 00:56:19.224504 output: Kernel: kernel-1
312 00:56:19.224557 output: Init Ramdisk: ramdisk-1
313 00:56:19.224610 output: FDT: fdt-1
314 00:56:19.224663 output: Loadables: kernel-1
315 00:56:19.224715 output:
316 00:56:19.224923 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 00:56:19.225024 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 00:56:19.225127 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 00:56:19.225222 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 00:56:19.225299 No LXC device requested
321 00:56:19.225378 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:56:19.225469 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 00:56:19.225549 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:56:19.225619 Checking files for TFTP limit of 4294967296 bytes.
325 00:56:19.226233 end: 1 tftp-deploy (duration 00:00:42) [common]
326 00:56:19.226346 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:56:19.226440 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:56:19.226565 substitutions:
329 00:56:19.226635 - {DTB}: 14368594/tftp-deploy-t_vao4_5/dtb/mt8192-asurada-spherion-r0.dtb
330 00:56:19.226701 - {INITRD}: 14368594/tftp-deploy-t_vao4_5/ramdisk/ramdisk.cpio.gz
331 00:56:19.226762 - {KERNEL}: 14368594/tftp-deploy-t_vao4_5/kernel/Image
332 00:56:19.226821 - {LAVA_MAC}: None
333 00:56:19.226879 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368594/extract-nfsrootfs-bv0vk0cp
334 00:56:19.226944 - {NFS_SERVER_IP}: 192.168.201.1
335 00:56:19.227001 - {PRESEED_CONFIG}: None
336 00:56:19.227062 - {PRESEED_LOCAL}: None
337 00:56:19.227118 - {RAMDISK}: 14368594/tftp-deploy-t_vao4_5/ramdisk/ramdisk.cpio.gz
338 00:56:19.227174 - {ROOT_PART}: None
339 00:56:19.227229 - {ROOT}: None
340 00:56:19.227283 - {SERVER_IP}: 192.168.201.1
341 00:56:19.227338 - {TEE}: None
342 00:56:19.227392 Parsed boot commands:
343 00:56:19.227447 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:56:19.227628 Parsed boot commands: tftpboot 192.168.201.1 14368594/tftp-deploy-t_vao4_5/kernel/image.itb 14368594/tftp-deploy-t_vao4_5/kernel/cmdline
345 00:56:19.227717 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:56:19.227805 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:56:19.227897 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:56:19.227984 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:56:19.228072 Not connected, no need to disconnect.
350 00:56:19.228182 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:56:19.228271 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:56:19.228344 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 00:56:19.232081 Setting prompt string to ['lava-test: # ']
354 00:56:19.232449 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:56:19.232558 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:56:19.232654 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:56:19.232743 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:56:19.232920 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
359 00:56:33.223381 Returned 0 in 13 seconds
360 00:56:33.324541 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 00:56:33.326097 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 00:56:33.326688 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 00:56:33.327196 Setting prompt string to 'Starting depthcharge on Spherion...'
365 00:56:33.327607 Changing prompt to 'Starting depthcharge on Spherion...'
366 00:56:33.328006 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 00:56:33.330096 [Enter `^Ec?' for help]
368 00:56:33.330598
369 00:56:33.331000
370 00:56:33.331381 F0: 102B 0000
371 00:56:33.331745
372 00:56:33.332100 F3: 1001 0000 [0200]
373 00:56:33.332438
374 00:56:33.332775 F3: 1001 0000
375 00:56:33.333117
376 00:56:33.333451 F7: 102D 0000
377 00:56:33.333772
378 00:56:33.334210 F1: 0000 0000
379 00:56:33.334542
380 00:56:33.334858 V0: 0000 0000 [0001]
381 00:56:33.335170
382 00:56:33.335478 00: 0007 8000
383 00:56:33.335813
384 00:56:33.336125 01: 0000 0000
385 00:56:33.336442
386 00:56:33.336752 BP: 0C00 0209 [0000]
387 00:56:33.337060
388 00:56:33.337371 G0: 1182 0000
389 00:56:33.337682
390 00:56:33.337990 EC: 0000 0021 [4000]
391 00:56:33.338321
392 00:56:33.338698 S7: 0000 0000 [0000]
393 00:56:33.339018
394 00:56:33.339329 CC: 0000 0000 [0001]
395 00:56:33.339639
396 00:56:33.339947 T0: 0000 0040 [010F]
397 00:56:33.340258
398 00:56:33.340566 Jump to BL
399 00:56:33.340872
400 00:56:33.341253
401 00:56:33.341729
402 00:56:33.342122 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 00:56:33.342528 ARM64: Exception handlers installed.
404 00:56:33.342855 ARM64: Testing exception
405 00:56:33.343170 ARM64: Done test exception
406 00:56:33.343481 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 00:56:33.343800 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 00:56:33.344121 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 00:56:33.344437 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 00:56:33.344757 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 00:56:33.345072 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 00:56:33.345387 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 00:56:33.345697 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 00:56:33.346009 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 00:56:33.346358 WDT: Last reset was cold boot
416 00:56:33.346672 SPI1(PAD0) initialized at 2873684 Hz
417 00:56:33.347033 SPI5(PAD0) initialized at 992727 Hz
418 00:56:33.347354 VBOOT: Loading verstage.
419 00:56:33.347665 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 00:56:33.347980 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 00:56:33.348304 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 00:56:33.348660 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 00:56:33.349121 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 00:56:33.349343 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 00:56:33.349552 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 00:56:33.349759
427 00:56:33.349964
428 00:56:33.350204 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 00:56:33.350465 ARM64: Exception handlers installed.
430 00:56:33.350689 ARM64: Testing exception
431 00:56:33.350893 ARM64: Done test exception
432 00:56:33.351098 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 00:56:33.351403 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 00:56:33.351791 Probing TPM: . done!
435 00:56:33.352026 TPM ready after 0 ms
436 00:56:33.352240 Connected to device vid:did:rid of 1ae0:0028:00
437 00:56:33.352448 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
438 00:56:33.352667 Initialized TPM device CR50 revision 0
439 00:56:33.352873 tlcl_send_startup: Startup return code is 0
440 00:56:33.353079 TPM: setup succeeded
441 00:56:33.353282 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 00:56:33.353485 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 00:56:33.353691 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 00:56:33.353897 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:56:33.354121 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 00:56:33.354288 in-header: 03 07 00 00 08 00 00 00
447 00:56:33.354443 in-data: aa e4 47 04 13 02 00 00
448 00:56:33.354595 Chrome EC: UHEPI supported
449 00:56:33.354748 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 00:56:33.354902 in-header: 03 a9 00 00 08 00 00 00
451 00:56:33.355054 in-data: 84 60 60 08 00 00 00 00
452 00:56:33.355206 Phase 1
453 00:56:33.355358 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 00:56:33.355511 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 00:56:33.355665 VB2:vb2_check_recovery() Recovery was requested manually
456 00:56:33.355819 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 00:56:33.355971 Recovery requested (1009000e)
458 00:56:33.356125 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 00:56:33.356279 tlcl_extend: response is 0
460 00:56:33.356433 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 00:56:33.356587 tlcl_extend: response is 0
462 00:56:33.356739 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 00:56:33.356891 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 00:56:33.357045 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 00:56:33.357198
466 00:56:33.357349
467 00:56:33.357502 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 00:56:33.357656 ARM64: Exception handlers installed.
469 00:56:33.357808 ARM64: Testing exception
470 00:56:33.357959 ARM64: Done test exception
471 00:56:33.358111 pmic_efuse_setting: Set efuses in 11 msecs
472 00:56:33.358313 pmwrap_interface_init: Select PMIF_VLD_RDY
473 00:56:33.358470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 00:56:33.358622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 00:56:33.359039 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 00:56:33.359202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 00:56:33.359328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 00:56:33.359450 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 00:56:33.359573 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 00:56:33.359696 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 00:56:33.359819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 00:56:33.359941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 00:56:33.360063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 00:56:33.360186 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 00:56:33.360307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 00:56:33.360429 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 00:56:33.360552 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 00:56:33.360674 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 00:56:33.360796 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 00:56:33.360918 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 00:56:33.361039 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 00:56:33.361162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 00:56:33.361282 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 00:56:33.361405 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 00:56:33.361526 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 00:56:33.361647 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 00:56:33.361768 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 00:56:33.361891 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 00:56:33.362013 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 00:56:33.362136 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 00:56:33.362275 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 00:56:33.362396 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 00:56:33.362517 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 00:56:33.362640 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 00:56:33.362762 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 00:56:33.362885 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 00:56:33.363006 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 00:56:33.363129 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 00:56:33.363252 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 00:56:33.363374 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 00:56:33.363494 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 00:56:33.363615 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 00:56:33.363737 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 00:56:33.363858 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 00:56:33.363979 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 00:56:33.364107 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 00:56:33.364207 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 00:56:33.364308 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 00:56:33.364410 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 00:56:33.364510 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 00:56:33.364611 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 00:56:33.364712 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 00:56:33.364814 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 00:56:33.364916 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 00:56:33.365019 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 00:56:33.365121 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 00:56:33.365223 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 00:56:33.365326 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 00:56:33.365428 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 00:56:33.365529 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:56:33.365631 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:56:33.365734 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x29
533 00:56:33.365836 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 00:56:33.365938 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
535 00:56:33.366040 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 00:56:33.366140 [RTC]rtc_get_frequency_meter,154: input=15, output=836
537 00:56:33.366249 [RTC]rtc_get_frequency_meter,154: input=7, output=709
538 00:56:33.366351 [RTC]rtc_get_frequency_meter,154: input=11, output=772
539 00:56:33.366452 [RTC]rtc_get_frequency_meter,154: input=13, output=804
540 00:56:33.366553 [RTC]rtc_get_frequency_meter,154: input=12, output=789
541 00:56:33.366655 [RTC]rtc_get_frequency_meter,154: input=12, output=788
542 00:56:33.366757 [RTC]rtc_get_frequency_meter,154: input=13, output=804
543 00:56:33.366909 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
544 00:56:33.367106 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
545 00:56:33.367446 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 00:56:33.367563 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 00:56:33.367671 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 00:56:33.367776 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 00:56:33.367880 ADC[4]: Raw value=902291 ID=7
550 00:56:33.367983 ADC[3]: Raw value=213282 ID=1
551 00:56:33.368086 RAM Code: 0x71
552 00:56:33.368188 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 00:56:33.368291 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 00:56:33.368395 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 00:56:33.368499 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 00:56:33.368602 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 00:56:33.368705 in-header: 03 07 00 00 08 00 00 00
558 00:56:33.368873 in-data: aa e4 47 04 13 02 00 00
559 00:56:33.368987 Chrome EC: UHEPI supported
560 00:56:33.369103 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 00:56:33.369193 in-header: 03 a9 00 00 08 00 00 00
562 00:56:33.369281 in-data: 84 60 60 08 00 00 00 00
563 00:56:33.369368 MRC: failed to locate region type 0.
564 00:56:33.369456 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 00:56:33.369545 DRAM-K: Running full calibration
566 00:56:33.369634 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 00:56:33.369722 header.status = 0x0
568 00:56:33.369809 header.version = 0x6 (expected: 0x6)
569 00:56:33.369897 header.size = 0xd00 (expected: 0xd00)
570 00:56:33.369985 header.flags = 0x0
571 00:56:33.370072 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 00:56:33.370170 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
573 00:56:33.370267 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 00:56:33.370356 dram_init: ddr_geometry: 2
575 00:56:33.370444 [EMI] MDL number = 2
576 00:56:33.370531 [EMI] Get MDL freq = 0
577 00:56:33.370617 dram_init: ddr_type: 0
578 00:56:33.370705 is_discrete_lpddr4: 1
579 00:56:33.370791 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 00:56:33.370878
581 00:56:33.370965
582 00:56:33.371052 [Bian_co] ETT version 0.0.0.1
583 00:56:33.371140 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 00:56:33.371227
585 00:56:33.371314 dramc_set_vcore_voltage set vcore to 650000
586 00:56:33.371402 Read voltage for 800, 4
587 00:56:33.371488 Vio18 = 0
588 00:56:33.371575 Vcore = 650000
589 00:56:33.371662 Vdram = 0
590 00:56:33.371749 Vddq = 0
591 00:56:33.371842 Vmddr = 0
592 00:56:33.371999 dram_init: config_dvfs: 1
593 00:56:33.372122 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 00:56:33.372214 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 00:56:33.372303 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
596 00:56:33.372392 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
597 00:56:33.372480 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
598 00:56:33.372569 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
599 00:56:33.372655 MEM_TYPE=3, freq_sel=18
600 00:56:33.372742 sv_algorithm_assistance_LP4_1600
601 00:56:33.372829 ============ PULL DRAM RESETB DOWN ============
602 00:56:33.372922 ========== PULL DRAM RESETB DOWN end =========
603 00:56:33.373009 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 00:56:33.373097 ===================================
605 00:56:33.373185 LPDDR4 DRAM CONFIGURATION
606 00:56:33.373271 ===================================
607 00:56:33.373358 EX_ROW_EN[0] = 0x0
608 00:56:33.373449 EX_ROW_EN[1] = 0x0
609 00:56:33.373535 LP4Y_EN = 0x0
610 00:56:33.373620 WORK_FSP = 0x0
611 00:56:33.373706 WL = 0x2
612 00:56:33.373793 RL = 0x2
613 00:56:33.373879 BL = 0x2
614 00:56:33.373964 RPST = 0x0
615 00:56:33.374062 RD_PRE = 0x0
616 00:56:33.374137 WR_PRE = 0x1
617 00:56:33.374219 WR_PST = 0x0
618 00:56:33.374294 DBI_WR = 0x0
619 00:56:33.374369 DBI_RD = 0x0
620 00:56:33.374444 OTF = 0x1
621 00:56:33.374520 ===================================
622 00:56:33.374596 ===================================
623 00:56:33.374672 ANA top config
624 00:56:33.374748 ===================================
625 00:56:33.374824 DLL_ASYNC_EN = 0
626 00:56:33.374900 ALL_SLAVE_EN = 1
627 00:56:33.374976 NEW_RANK_MODE = 1
628 00:56:33.375053 DLL_IDLE_MODE = 1
629 00:56:33.375128 LP45_APHY_COMB_EN = 1
630 00:56:33.375205 TX_ODT_DIS = 1
631 00:56:33.375281 NEW_8X_MODE = 1
632 00:56:33.375358 ===================================
633 00:56:33.375434 ===================================
634 00:56:33.375509 data_rate = 1600
635 00:56:33.375585 CKR = 1
636 00:56:33.375661 DQ_P2S_RATIO = 8
637 00:56:33.375736 ===================================
638 00:56:33.375812 CA_P2S_RATIO = 8
639 00:56:33.375887 DQ_CA_OPEN = 0
640 00:56:33.375963 DQ_SEMI_OPEN = 0
641 00:56:33.376038 CA_SEMI_OPEN = 0
642 00:56:33.376113 CA_FULL_RATE = 0
643 00:56:33.376188 DQ_CKDIV4_EN = 1
644 00:56:33.376263 CA_CKDIV4_EN = 1
645 00:56:33.376338 CA_PREDIV_EN = 0
646 00:56:33.376414 PH8_DLY = 0
647 00:56:33.376489 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 00:56:33.376564 DQ_AAMCK_DIV = 4
649 00:56:33.376640 CA_AAMCK_DIV = 4
650 00:56:33.376716 CA_ADMCK_DIV = 4
651 00:56:33.376791 DQ_TRACK_CA_EN = 0
652 00:56:33.376866 CA_PICK = 800
653 00:56:33.376941 CA_MCKIO = 800
654 00:56:33.377017 MCKIO_SEMI = 0
655 00:56:33.377093 PLL_FREQ = 3068
656 00:56:33.377168 DQ_UI_PI_RATIO = 32
657 00:56:33.377244 CA_UI_PI_RATIO = 0
658 00:56:33.377319 ===================================
659 00:56:33.377395 ===================================
660 00:56:33.377470 memory_type:LPDDR4
661 00:56:33.377545 GP_NUM : 10
662 00:56:33.377621 SRAM_EN : 1
663 00:56:33.377696 MD32_EN : 0
664 00:56:33.378004 ===================================
665 00:56:33.378091 [ANA_INIT] >>>>>>>>>>>>>>
666 00:56:33.378182 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 00:56:33.378265 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 00:56:33.378343 ===================================
669 00:56:33.378420 data_rate = 1600,PCW = 0X7600
670 00:56:33.378496 ===================================
671 00:56:33.378573 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 00:56:33.378651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 00:56:33.378728 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 00:56:33.378805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 00:56:33.378882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 00:56:33.378959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 00:56:33.379036 [ANA_INIT] flow start
678 00:56:33.379120 [ANA_INIT] PLL >>>>>>>>
679 00:56:33.379187 [ANA_INIT] PLL <<<<<<<<
680 00:56:33.379255 [ANA_INIT] MIDPI >>>>>>>>
681 00:56:33.379322 [ANA_INIT] MIDPI <<<<<<<<
682 00:56:33.379390 [ANA_INIT] DLL >>>>>>>>
683 00:56:33.379457 [ANA_INIT] flow end
684 00:56:33.379525 ============ LP4 DIFF to SE enter ============
685 00:56:33.379594 ============ LP4 DIFF to SE exit ============
686 00:56:33.379662 [ANA_INIT] <<<<<<<<<<<<<
687 00:56:33.379730 [Flow] Enable top DCM control >>>>>
688 00:56:33.379798 [Flow] Enable top DCM control <<<<<
689 00:56:33.379865 Enable DLL master slave shuffle
690 00:56:33.379933 ==============================================================
691 00:56:33.380002 Gating Mode config
692 00:56:33.380070 ==============================================================
693 00:56:33.380137 Config description:
694 00:56:33.380205 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 00:56:33.380275 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 00:56:33.380344 SELPH_MODE 0: By rank 1: By Phase
697 00:56:33.380413 ==============================================================
698 00:56:33.380482 GAT_TRACK_EN = 1
699 00:56:33.380550 RX_GATING_MODE = 2
700 00:56:33.380618 RX_GATING_TRACK_MODE = 2
701 00:56:33.380686 SELPH_MODE = 1
702 00:56:33.380753 PICG_EARLY_EN = 1
703 00:56:33.380822 VALID_LAT_VALUE = 1
704 00:56:33.380889 ==============================================================
705 00:56:33.380958 Enter into Gating configuration >>>>
706 00:56:33.381026 Exit from Gating configuration <<<<
707 00:56:33.381094 Enter into DVFS_PRE_config >>>>>
708 00:56:33.381161 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 00:56:33.381233 Exit from DVFS_PRE_config <<<<<
710 00:56:33.381301 Enter into PICG configuration >>>>
711 00:56:33.381369 Exit from PICG configuration <<<<
712 00:56:33.381436 [RX_INPUT] configuration >>>>>
713 00:56:33.381504 [RX_INPUT] configuration <<<<<
714 00:56:33.381571 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 00:56:33.381639 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 00:56:33.381707 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 00:56:33.381776 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 00:56:33.381844 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 00:56:33.381911 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 00:56:33.381979 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 00:56:33.382047 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 00:56:33.382115 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 00:56:33.382190 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 00:56:33.382259 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 00:56:33.382327 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 00:56:33.382396 ===================================
727 00:56:33.382464 LPDDR4 DRAM CONFIGURATION
728 00:56:33.382531 ===================================
729 00:56:33.382599 EX_ROW_EN[0] = 0x0
730 00:56:33.382666 EX_ROW_EN[1] = 0x0
731 00:56:33.382734 LP4Y_EN = 0x0
732 00:56:33.382801 WORK_FSP = 0x0
733 00:56:33.382869 WL = 0x2
734 00:56:33.382936 RL = 0x2
735 00:56:33.383003 BL = 0x2
736 00:56:33.383070 RPST = 0x0
737 00:56:33.383137 RD_PRE = 0x0
738 00:56:33.383203 WR_PRE = 0x1
739 00:56:33.383270 WR_PST = 0x0
740 00:56:33.383337 DBI_WR = 0x0
741 00:56:33.383404 DBI_RD = 0x0
742 00:56:33.383471 OTF = 0x1
743 00:56:33.383539 ===================================
744 00:56:33.383608 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 00:56:33.383675 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 00:56:33.383743 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 00:56:33.383810 ===================================
748 00:56:33.383878 LPDDR4 DRAM CONFIGURATION
749 00:56:33.383946 ===================================
750 00:56:33.384014 EX_ROW_EN[0] = 0x10
751 00:56:33.384081 EX_ROW_EN[1] = 0x0
752 00:56:33.384155 LP4Y_EN = 0x0
753 00:56:33.384215 WORK_FSP = 0x0
754 00:56:33.384275 WL = 0x2
755 00:56:33.384336 RL = 0x2
756 00:56:33.384396 BL = 0x2
757 00:56:33.384456 RPST = 0x0
758 00:56:33.384517 RD_PRE = 0x0
759 00:56:33.384577 WR_PRE = 0x1
760 00:56:33.384638 WR_PST = 0x0
761 00:56:33.384699 DBI_WR = 0x0
762 00:56:33.384759 DBI_RD = 0x0
763 00:56:33.384820 OTF = 0x1
764 00:56:33.384881 ===================================
765 00:56:33.384942 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 00:56:33.385004 nWR fixed to 40
767 00:56:33.385065 [ModeRegInit_LP4] CH0 RK0
768 00:56:33.385126 [ModeRegInit_LP4] CH0 RK1
769 00:56:33.385187 [ModeRegInit_LP4] CH1 RK0
770 00:56:33.385247 [ModeRegInit_LP4] CH1 RK1
771 00:56:33.385307 match AC timing 13
772 00:56:33.385367 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 00:56:33.385627 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 00:56:33.385736 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 00:56:33.385848 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 00:56:33.385919 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 00:56:33.385983 [EMI DOE] emi_dcm 0
778 00:56:33.386046 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 00:56:33.386109 ==
780 00:56:33.386180 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:56:33.386245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 00:56:33.386307 ==
783 00:56:33.386368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 00:56:33.386433 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 00:56:33.386495 [CA 0] Center 37 (7~68) winsize 62
786 00:56:33.386556 [CA 1] Center 37 (7~68) winsize 62
787 00:56:33.386617 [CA 2] Center 34 (4~65) winsize 62
788 00:56:33.386679 [CA 3] Center 34 (4~65) winsize 62
789 00:56:33.386739 [CA 4] Center 33 (3~64) winsize 62
790 00:56:33.386800 [CA 5] Center 33 (3~64) winsize 62
791 00:56:33.386861
792 00:56:33.386922 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 00:56:33.386983
794 00:56:33.387044 [CATrainingPosCal] consider 1 rank data
795 00:56:33.387105 u2DelayCellTimex100 = 270/100 ps
796 00:56:33.387166 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 00:56:33.387227 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
798 00:56:33.387288 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 00:56:33.387349 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 00:56:33.387410 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 00:56:33.387470 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 00:56:33.387531
803 00:56:33.387592 CA PerBit enable=1, Macro0, CA PI delay=33
804 00:56:33.387653
805 00:56:33.387715 [CBTSetCACLKResult] CA Dly = 33
806 00:56:33.387776 CS Dly: 7 (0~38)
807 00:56:33.387836 ==
808 00:56:33.387898 Dram Type= 6, Freq= 0, CH_0, rank 1
809 00:56:33.387959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 00:56:33.388021 ==
811 00:56:33.388082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 00:56:33.388143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 00:56:33.388204 [CA 0] Center 37 (6~68) winsize 63
814 00:56:33.388265 [CA 1] Center 37 (7~68) winsize 62
815 00:56:33.388326 [CA 2] Center 34 (4~65) winsize 62
816 00:56:33.388388 [CA 3] Center 34 (4~65) winsize 62
817 00:56:33.388448 [CA 4] Center 33 (3~64) winsize 62
818 00:56:33.388509 [CA 5] Center 33 (3~64) winsize 62
819 00:56:33.388569
820 00:56:33.388630 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 00:56:33.388691
822 00:56:33.388752 [CATrainingPosCal] consider 2 rank data
823 00:56:33.388812 u2DelayCellTimex100 = 270/100 ps
824 00:56:33.388873 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 00:56:33.388935 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 00:56:33.389012 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 00:56:33.389132 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 00:56:33.389230 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 00:56:33.389293 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 00:56:33.389352
831 00:56:33.389409 CA PerBit enable=1, Macro0, CA PI delay=33
832 00:56:33.389466
833 00:56:33.389522 [CBTSetCACLKResult] CA Dly = 33
834 00:56:33.389578 CS Dly: 7 (0~38)
835 00:56:33.389635
836 00:56:33.389690 ----->DramcWriteLeveling(PI) begin...
837 00:56:33.389748 ==
838 00:56:33.389804 Dram Type= 6, Freq= 0, CH_0, rank 0
839 00:56:33.389861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 00:56:33.389917 ==
841 00:56:33.389973 Write leveling (Byte 0): 30 => 30
842 00:56:33.390029 Write leveling (Byte 1): 29 => 29
843 00:56:33.390085 DramcWriteLeveling(PI) end<-----
844 00:56:33.390140
845 00:56:33.390202 ==
846 00:56:33.390259 Dram Type= 6, Freq= 0, CH_0, rank 0
847 00:56:33.390315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 00:56:33.390371 ==
849 00:56:33.390426 [Gating] SW mode calibration
850 00:56:33.390483 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 00:56:33.390539 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 00:56:33.390595 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 00:56:33.390650 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 00:56:33.390706 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 00:56:33.390761 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:56:33.390817 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:56:33.390872 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:56:33.390928 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:56:33.390983 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:56:33.391039 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:56:33.391142 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:56:33.391214 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:56:33.391273 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:56:33.391330 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:56:33.391385 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:56:33.391441 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:56:33.391497 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:56:33.391552 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 00:56:33.391607 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 00:56:33.391663 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
871 00:56:33.391718 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:56:33.391774 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 00:56:33.391829 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:56:33.391884 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 00:56:33.391939 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 00:56:33.391995 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 00:56:33.392050 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 00:56:33.392105 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
879 00:56:33.392161 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
880 00:56:33.392216 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 00:56:33.392469 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:56:33.392536 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 00:56:33.392594 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 00:56:33.392650 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 00:56:33.392707 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 00:56:33.392762 0 10 8 | B1->B0 | 3434 2525 | 0 0 | (0 1) (1 1)
887 00:56:33.392818 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
888 00:56:33.392874 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 00:56:33.392930 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:56:33.392985 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 00:56:33.393041 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 00:56:33.393097 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 00:56:33.393152 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
894 00:56:33.393207 0 11 8 | B1->B0 | 2424 3939 | 0 0 | (0 0) (0 0)
895 00:56:33.393263 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
896 00:56:33.393318 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 00:56:33.393373 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 00:56:33.393428 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 00:56:33.393483 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 00:56:33.393538 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 00:56:33.393594 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 00:56:33.393649 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 00:56:33.393705 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:56:33.393760 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:56:33.393815 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:56:33.393870 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:56:33.393926 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:56:33.393981 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:56:33.394036 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:56:33.394103 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:56:33.394157 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:56:33.394295 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:56:33.394354 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:56:33.394410 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 00:56:33.394464 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 00:56:33.394519 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 00:56:33.394574 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 00:56:33.394628 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
919 00:56:33.394683 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 00:56:33.394737 Total UI for P1: 0, mck2ui 16
921 00:56:33.394793 best dqsien dly found for B0: ( 0, 14, 6)
922 00:56:33.394848 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 00:56:33.394903 Total UI for P1: 0, mck2ui 16
924 00:56:33.394958 best dqsien dly found for B1: ( 0, 14, 10)
925 00:56:33.395013 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 00:56:33.395068 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 00:56:33.395122
928 00:56:33.395177 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 00:56:33.395231 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 00:56:33.395285 [Gating] SW calibration Done
931 00:56:33.395339 ==
932 00:56:33.395393 Dram Type= 6, Freq= 0, CH_0, rank 0
933 00:56:33.395448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 00:56:33.395502 ==
935 00:56:33.395557 RX Vref Scan: 0
936 00:56:33.395611
937 00:56:33.395665 RX Vref 0 -> 0, step: 1
938 00:56:33.395720
939 00:56:33.395774 RX Delay -130 -> 252, step: 16
940 00:56:33.395828 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 00:56:33.395883 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 00:56:33.395937 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 00:56:33.395991 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 00:56:33.396046 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 00:56:33.396100 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 00:56:33.396154 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 00:56:33.396207 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 00:56:33.396261 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 00:56:33.396315 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 00:56:33.396368 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 00:56:33.396422 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 00:56:33.396477 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
953 00:56:33.396531 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 00:56:33.396584 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 00:56:33.396637 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 00:56:33.396691 ==
957 00:56:33.396746 Dram Type= 6, Freq= 0, CH_0, rank 0
958 00:56:33.396800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 00:56:33.396855 ==
960 00:56:33.396910 DQS Delay:
961 00:56:33.396964 DQS0 = 0, DQS1 = 0
962 00:56:33.397018 DQM Delay:
963 00:56:33.397073 DQM0 = 85, DQM1 = 71
964 00:56:33.397127 DQ Delay:
965 00:56:33.397181 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 00:56:33.397235 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
967 00:56:33.397289 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 00:56:33.397343 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
969 00:56:33.397397
970 00:56:33.397451
971 00:56:33.397504 ==
972 00:56:33.397558 Dram Type= 6, Freq= 0, CH_0, rank 0
973 00:56:33.397612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 00:56:33.397667 ==
975 00:56:33.397721
976 00:56:33.397774
977 00:56:33.397828 TX Vref Scan disable
978 00:56:33.397882 == TX Byte 0 ==
979 00:56:33.397937 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 00:56:33.397995 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 00:56:33.398085 == TX Byte 1 ==
982 00:56:33.398177 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 00:56:33.398317 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 00:56:33.398389 ==
985 00:56:33.398444 Dram Type= 6, Freq= 0, CH_0, rank 0
986 00:56:33.398511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 00:56:33.398612 ==
988 00:56:33.398685 TX Vref=22, minBit 2, minWin=27, winSum=439
989 00:56:33.398936 TX Vref=24, minBit 5, minWin=27, winSum=445
990 00:56:33.399000 TX Vref=26, minBit 8, minWin=27, winSum=445
991 00:56:33.399058 TX Vref=28, minBit 8, minWin=27, winSum=446
992 00:56:33.399114 TX Vref=30, minBit 10, minWin=27, winSum=448
993 00:56:33.399171 TX Vref=32, minBit 4, minWin=27, winSum=442
994 00:56:33.399226 [TxChooseVref] Worse bit 10, Min win 27, Win sum 448, Final Vref 30
995 00:56:33.399281
996 00:56:33.399337 Final TX Range 1 Vref 30
997 00:56:33.399393
998 00:56:33.399448 ==
999 00:56:33.399503 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 00:56:33.399558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 00:56:33.399613 ==
1002 00:56:33.399668
1003 00:56:33.399721
1004 00:56:33.399775 TX Vref Scan disable
1005 00:56:33.399829 == TX Byte 0 ==
1006 00:56:33.399883 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1007 00:56:33.399938 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1008 00:56:33.399993 == TX Byte 1 ==
1009 00:56:33.400047 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 00:56:33.400101 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 00:56:33.400157
1012 00:56:33.400213 [DATLAT]
1013 00:56:33.400268 Freq=800, CH0 RK0
1014 00:56:33.400324
1015 00:56:33.400378 DATLAT Default: 0xa
1016 00:56:33.400433 0, 0xFFFF, sum = 0
1017 00:56:33.400490 1, 0xFFFF, sum = 0
1018 00:56:33.400546 2, 0xFFFF, sum = 0
1019 00:56:33.400601 3, 0xFFFF, sum = 0
1020 00:56:33.400657 4, 0xFFFF, sum = 0
1021 00:56:33.400712 5, 0xFFFF, sum = 0
1022 00:56:33.400767 6, 0xFFFF, sum = 0
1023 00:56:33.400822 7, 0xFFFF, sum = 0
1024 00:56:33.400878 8, 0xFFFF, sum = 0
1025 00:56:33.400940 9, 0x0, sum = 1
1026 00:56:33.401002 10, 0x0, sum = 2
1027 00:56:33.401059 11, 0x0, sum = 3
1028 00:56:33.401115 12, 0x0, sum = 4
1029 00:56:33.401171 best_step = 10
1030 00:56:33.401226
1031 00:56:33.401280 ==
1032 00:56:33.401335 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 00:56:33.401391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 00:56:33.401447 ==
1035 00:56:33.401501 RX Vref Scan: 1
1036 00:56:33.401555
1037 00:56:33.401610 Set Vref Range= 32 -> 127
1038 00:56:33.401664
1039 00:56:33.401718 RX Vref 32 -> 127, step: 1
1040 00:56:33.401772
1041 00:56:33.401826 RX Delay -111 -> 252, step: 8
1042 00:56:33.401880
1043 00:56:33.401934 Set Vref, RX VrefLevel [Byte0]: 32
1044 00:56:33.401989 [Byte1]: 32
1045 00:56:33.402043
1046 00:56:33.402098 Set Vref, RX VrefLevel [Byte0]: 33
1047 00:56:33.402152 [Byte1]: 33
1048 00:56:33.402253
1049 00:56:33.402307 Set Vref, RX VrefLevel [Byte0]: 34
1050 00:56:33.402362 [Byte1]: 34
1051 00:56:33.402416
1052 00:56:33.402471 Set Vref, RX VrefLevel [Byte0]: 35
1053 00:56:33.402525 [Byte1]: 35
1054 00:56:33.402579
1055 00:56:33.402633 Set Vref, RX VrefLevel [Byte0]: 36
1056 00:56:33.402688 [Byte1]: 36
1057 00:56:33.402742
1058 00:56:33.402796 Set Vref, RX VrefLevel [Byte0]: 37
1059 00:56:33.402850 [Byte1]: 37
1060 00:56:33.402904
1061 00:56:33.402958 Set Vref, RX VrefLevel [Byte0]: 38
1062 00:56:33.403012 [Byte1]: 38
1063 00:56:33.403065
1064 00:56:33.403120 Set Vref, RX VrefLevel [Byte0]: 39
1065 00:56:33.403174 [Byte1]: 39
1066 00:56:33.403227
1067 00:56:33.403281 Set Vref, RX VrefLevel [Byte0]: 40
1068 00:56:33.403335 [Byte1]: 40
1069 00:56:33.403389
1070 00:56:33.403443 Set Vref, RX VrefLevel [Byte0]: 41
1071 00:56:33.403497 [Byte1]: 41
1072 00:56:33.403552
1073 00:56:33.403606 Set Vref, RX VrefLevel [Byte0]: 42
1074 00:56:33.403660 [Byte1]: 42
1075 00:56:33.403714
1076 00:56:33.403768 Set Vref, RX VrefLevel [Byte0]: 43
1077 00:56:33.403823 [Byte1]: 43
1078 00:56:33.403877
1079 00:56:33.403931 Set Vref, RX VrefLevel [Byte0]: 44
1080 00:56:33.403985 [Byte1]: 44
1081 00:56:33.404044
1082 00:56:33.404109 Set Vref, RX VrefLevel [Byte0]: 45
1083 00:56:33.404165 [Byte1]: 45
1084 00:56:33.404226
1085 00:56:33.404340 Set Vref, RX VrefLevel [Byte0]: 46
1086 00:56:33.404430 [Byte1]: 46
1087 00:56:33.404488
1088 00:56:33.404544 Set Vref, RX VrefLevel [Byte0]: 47
1089 00:56:33.404598 [Byte1]: 47
1090 00:56:33.404653
1091 00:56:33.404707 Set Vref, RX VrefLevel [Byte0]: 48
1092 00:56:33.404762 [Byte1]: 48
1093 00:56:33.404816
1094 00:56:33.404871 Set Vref, RX VrefLevel [Byte0]: 49
1095 00:56:33.404926 [Byte1]: 49
1096 00:56:33.404980
1097 00:56:33.405034 Set Vref, RX VrefLevel [Byte0]: 50
1098 00:56:33.405089 [Byte1]: 50
1099 00:56:33.405143
1100 00:56:33.405198 Set Vref, RX VrefLevel [Byte0]: 51
1101 00:56:33.405252 [Byte1]: 51
1102 00:56:33.405306
1103 00:56:33.405359 Set Vref, RX VrefLevel [Byte0]: 52
1104 00:56:33.405413 [Byte1]: 52
1105 00:56:33.405467
1106 00:56:33.405521 Set Vref, RX VrefLevel [Byte0]: 53
1107 00:56:33.405575 [Byte1]: 53
1108 00:56:33.405629
1109 00:56:33.405683 Set Vref, RX VrefLevel [Byte0]: 54
1110 00:56:33.405737 [Byte1]: 54
1111 00:56:33.405791
1112 00:56:33.405845 Set Vref, RX VrefLevel [Byte0]: 55
1113 00:56:33.405898 [Byte1]: 55
1114 00:56:33.405952
1115 00:56:33.406006 Set Vref, RX VrefLevel [Byte0]: 56
1116 00:56:33.406060 [Byte1]: 56
1117 00:56:33.406114
1118 00:56:33.406174 Set Vref, RX VrefLevel [Byte0]: 57
1119 00:56:33.406267 [Byte1]: 57
1120 00:56:33.406322
1121 00:56:33.406376 Set Vref, RX VrefLevel [Byte0]: 58
1122 00:56:33.406431 [Byte1]: 58
1123 00:56:33.406484
1124 00:56:33.406539 Set Vref, RX VrefLevel [Byte0]: 59
1125 00:56:33.406593 [Byte1]: 59
1126 00:56:33.406647
1127 00:56:33.406701 Set Vref, RX VrefLevel [Byte0]: 60
1128 00:56:33.406756 [Byte1]: 60
1129 00:56:33.406810
1130 00:56:33.406864 Set Vref, RX VrefLevel [Byte0]: 61
1131 00:56:33.406917 [Byte1]: 61
1132 00:56:33.406971
1133 00:56:33.407025 Set Vref, RX VrefLevel [Byte0]: 62
1134 00:56:33.407079 [Byte1]: 62
1135 00:56:33.407133
1136 00:56:33.407187 Set Vref, RX VrefLevel [Byte0]: 63
1137 00:56:33.407241 [Byte1]: 63
1138 00:56:33.407296
1139 00:56:33.407349 Set Vref, RX VrefLevel [Byte0]: 64
1140 00:56:33.407403 [Byte1]: 64
1141 00:56:33.407458
1142 00:56:33.407512 Set Vref, RX VrefLevel [Byte0]: 65
1143 00:56:33.407566 [Byte1]: 65
1144 00:56:33.407620
1145 00:56:33.407675 Set Vref, RX VrefLevel [Byte0]: 66
1146 00:56:33.407729 [Byte1]: 66
1147 00:56:33.407783
1148 00:56:33.407838 Set Vref, RX VrefLevel [Byte0]: 67
1149 00:56:33.407892 [Byte1]: 67
1150 00:56:33.407946
1151 00:56:33.408000 Set Vref, RX VrefLevel [Byte0]: 68
1152 00:56:33.408054 [Byte1]: 68
1153 00:56:33.408108
1154 00:56:33.408163 Set Vref, RX VrefLevel [Byte0]: 69
1155 00:56:33.408217 [Byte1]: 69
1156 00:56:33.408271
1157 00:56:33.408517 Set Vref, RX VrefLevel [Byte0]: 70
1158 00:56:33.408578 [Byte1]: 70
1159 00:56:33.408634
1160 00:56:33.408689 Set Vref, RX VrefLevel [Byte0]: 71
1161 00:56:33.408744 [Byte1]: 71
1162 00:56:33.408798
1163 00:56:33.408852 Set Vref, RX VrefLevel [Byte0]: 72
1164 00:56:33.408907 [Byte1]: 72
1165 00:56:33.408961
1166 00:56:33.409029 Set Vref, RX VrefLevel [Byte0]: 73
1167 00:56:33.409088 [Byte1]: 73
1168 00:56:33.409144
1169 00:56:33.409198 Set Vref, RX VrefLevel [Byte0]: 74
1170 00:56:33.409254 [Byte1]: 74
1171 00:56:33.409308
1172 00:56:33.409362 Set Vref, RX VrefLevel [Byte0]: 75
1173 00:56:33.409416 [Byte1]: 75
1174 00:56:33.409471
1175 00:56:33.409525 Set Vref, RX VrefLevel [Byte0]: 76
1176 00:56:33.409579 [Byte1]: 76
1177 00:56:33.409633
1178 00:56:33.409688 Set Vref, RX VrefLevel [Byte0]: 77
1179 00:56:33.409742 [Byte1]: 77
1180 00:56:33.409796
1181 00:56:33.409849 Set Vref, RX VrefLevel [Byte0]: 78
1182 00:56:33.409903 [Byte1]: 78
1183 00:56:33.409957
1184 00:56:33.410011 Set Vref, RX VrefLevel [Byte0]: 79
1185 00:56:33.410066 [Byte1]: 79
1186 00:56:33.410120
1187 00:56:33.410211 Set Vref, RX VrefLevel [Byte0]: 80
1188 00:56:33.410267 [Byte1]: 80
1189 00:56:33.410322
1190 00:56:33.410376 Set Vref, RX VrefLevel [Byte0]: 81
1191 00:56:33.410431 [Byte1]: 81
1192 00:56:33.410485
1193 00:56:33.410538 Set Vref, RX VrefLevel [Byte0]: 82
1194 00:56:33.410592 [Byte1]: 82
1195 00:56:33.410647
1196 00:56:33.410706 Final RX Vref Byte 0 = 62 to rank0
1197 00:56:33.410805 Final RX Vref Byte 1 = 52 to rank0
1198 00:56:33.410886 Final RX Vref Byte 0 = 62 to rank1
1199 00:56:33.410944 Final RX Vref Byte 1 = 52 to rank1==
1200 00:56:33.411000 Dram Type= 6, Freq= 0, CH_0, rank 0
1201 00:56:33.411055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 00:56:33.411110 ==
1203 00:56:33.411165 DQS Delay:
1204 00:56:33.411220 DQS0 = 0, DQS1 = 0
1205 00:56:33.411275 DQM Delay:
1206 00:56:33.411329 DQM0 = 85, DQM1 = 76
1207 00:56:33.411384 DQ Delay:
1208 00:56:33.411438 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1209 00:56:33.411493 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1210 00:56:33.411547 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1211 00:56:33.411601 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1212 00:56:33.411655
1213 00:56:33.411709
1214 00:56:33.411764 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
1215 00:56:33.411819 CH0 RK0: MR19=606, MR18=4A2B
1216 00:56:33.411873 CH0_RK0: MR19=0x606, MR18=0x4A2B, DQSOSC=391, MR23=63, INC=96, DEC=64
1217 00:56:33.411928
1218 00:56:33.411983 ----->DramcWriteLeveling(PI) begin...
1219 00:56:33.412038 ==
1220 00:56:33.412093 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 00:56:33.412148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1222 00:56:33.412203 ==
1223 00:56:33.412257 Write leveling (Byte 0): 33 => 33
1224 00:56:33.412312 Write leveling (Byte 1): 28 => 28
1225 00:56:33.412367 DramcWriteLeveling(PI) end<-----
1226 00:56:33.412421
1227 00:56:33.412475 ==
1228 00:56:33.412530 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 00:56:33.412584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 00:56:33.412639 ==
1231 00:56:33.412694 [Gating] SW mode calibration
1232 00:56:33.412749 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1233 00:56:33.412804 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1234 00:56:33.412859 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1235 00:56:33.412914 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1236 00:56:33.412969 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1237 00:56:33.413024 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1238 00:56:33.413078 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 00:56:33.413133 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 00:56:33.413187 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 00:56:33.413241 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 00:56:33.413296 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 00:56:33.413350 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 00:56:33.413405 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 00:56:33.413459 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 00:56:33.413514 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 00:56:33.413568 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 00:56:33.413623 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 00:56:33.413677 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 00:56:33.413731 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 00:56:33.413786 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 00:56:33.413840 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1253 00:56:33.413894 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 00:56:33.413948 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 00:56:33.414002 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 00:56:33.414056 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 00:56:33.414110 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 00:56:33.414173 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 00:56:33.414230 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 00:56:33.414284 0 9 8 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
1261 00:56:33.414339 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 00:56:33.414393 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 00:56:33.414447 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1264 00:56:33.414501 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1265 00:56:33.414555 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 00:56:33.414609 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 00:56:33.414663 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
1268 00:56:33.414717 0 10 8 | B1->B0 | 2e2e 2727 | 1 1 | (1 1) (1 0)
1269 00:56:33.414771 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1270 00:56:33.414826 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 00:56:33.414880 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1272 00:56:33.415126 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1273 00:56:33.415190 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 00:56:33.415246 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 00:56:33.415301 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1276 00:56:33.415356 0 11 8 | B1->B0 | 2d2d 3a3a | 0 0 | (0 0) (0 0)
1277 00:56:33.415410 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1278 00:56:33.415465 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 00:56:33.415519 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 00:56:33.415573 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 00:56:33.415627 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 00:56:33.415682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 00:56:33.415736 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 00:56:33.415790 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1285 00:56:33.415844 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1286 00:56:33.415899 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 00:56:33.415953 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 00:56:33.416008 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 00:56:33.416062 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 00:56:33.416117 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 00:56:33.416171 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 00:56:33.416226 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 00:56:33.416280 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 00:56:33.416334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 00:56:33.416388 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 00:56:33.416442 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 00:56:33.416496 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 00:56:33.416550 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 00:56:33.416604 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1300 00:56:33.416658 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1301 00:56:33.416712 Total UI for P1: 0, mck2ui 16
1302 00:56:33.416767 best dqsien dly found for B0: ( 0, 14, 4)
1303 00:56:33.416822 Total UI for P1: 0, mck2ui 16
1304 00:56:33.416877 best dqsien dly found for B1: ( 0, 14, 4)
1305 00:56:33.416931 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1306 00:56:33.416985 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1307 00:56:33.417039
1308 00:56:33.417094 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1309 00:56:33.417149 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1310 00:56:33.417203 [Gating] SW calibration Done
1311 00:56:33.417278 ==
1312 00:56:33.417335 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 00:56:33.417390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 00:56:33.417445 ==
1315 00:56:33.417499 RX Vref Scan: 0
1316 00:56:33.417554
1317 00:56:33.417608 RX Vref 0 -> 0, step: 1
1318 00:56:33.417663
1319 00:56:33.417717 RX Delay -130 -> 252, step: 16
1320 00:56:33.417772 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1321 00:56:33.417827 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1322 00:56:33.417881 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1323 00:56:33.417935 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1324 00:56:33.417990 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1325 00:56:33.418043 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1326 00:56:33.418097 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1327 00:56:33.418151 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1328 00:56:33.418249 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1329 00:56:33.418341 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1330 00:56:33.418395 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1331 00:56:33.418449 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1332 00:56:33.418503 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1333 00:56:33.418557 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1334 00:56:33.418611 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1335 00:56:33.418664 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1336 00:56:33.418718 ==
1337 00:56:33.418772 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 00:56:33.418827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 00:56:33.418881 ==
1340 00:56:33.418935 DQS Delay:
1341 00:56:33.418989 DQS0 = 0, DQS1 = 0
1342 00:56:33.419043 DQM Delay:
1343 00:56:33.419097 DQM0 = 83, DQM1 = 76
1344 00:56:33.419151 DQ Delay:
1345 00:56:33.419205 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1346 00:56:33.419260 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1347 00:56:33.419313 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1348 00:56:33.419368 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
1349 00:56:33.419422
1350 00:56:33.419476
1351 00:56:33.419529 ==
1352 00:56:33.419584 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 00:56:33.419638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 00:56:33.419693 ==
1355 00:56:33.419747
1356 00:56:33.419801
1357 00:56:33.419854 TX Vref Scan disable
1358 00:56:33.419909 == TX Byte 0 ==
1359 00:56:33.419963 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1360 00:56:33.420018 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1361 00:56:33.420072 == TX Byte 1 ==
1362 00:56:33.420125 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1363 00:56:33.420179 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1364 00:56:33.420233 ==
1365 00:56:33.420287 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 00:56:33.420341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 00:56:33.420395 ==
1368 00:56:33.420449 TX Vref=22, minBit 3, minWin=27, winSum=440
1369 00:56:33.420503 TX Vref=24, minBit 8, minWin=26, winSum=443
1370 00:56:33.420557 TX Vref=26, minBit 9, minWin=27, winSum=447
1371 00:56:33.420612 TX Vref=28, minBit 9, minWin=27, winSum=449
1372 00:56:33.420666 TX Vref=30, minBit 8, minWin=27, winSum=448
1373 00:56:33.420720 TX Vref=32, minBit 9, minWin=27, winSum=447
1374 00:56:33.420774 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 28
1375 00:56:33.420828
1376 00:56:33.420882 Final TX Range 1 Vref 28
1377 00:56:33.420936
1378 00:56:33.420989 ==
1379 00:56:33.421042 Dram Type= 6, Freq= 0, CH_0, rank 1
1380 00:56:33.421097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 00:56:33.421151 ==
1382 00:56:33.421204
1383 00:56:33.421258
1384 00:56:33.421310 TX Vref Scan disable
1385 00:56:33.421364 == TX Byte 0 ==
1386 00:56:33.421418 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1387 00:56:33.421668 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1388 00:56:33.421728 == TX Byte 1 ==
1389 00:56:33.421783 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1390 00:56:33.421838 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1391 00:56:33.421892
1392 00:56:33.421946 [DATLAT]
1393 00:56:33.421999 Freq=800, CH0 RK1
1394 00:56:33.422053
1395 00:56:33.422106 DATLAT Default: 0xa
1396 00:56:33.422159 0, 0xFFFF, sum = 0
1397 00:56:33.422251 1, 0xFFFF, sum = 0
1398 00:56:33.422305 2, 0xFFFF, sum = 0
1399 00:56:33.422359 3, 0xFFFF, sum = 0
1400 00:56:33.422414 4, 0xFFFF, sum = 0
1401 00:56:33.422468 5, 0xFFFF, sum = 0
1402 00:56:33.422522 6, 0xFFFF, sum = 0
1403 00:56:33.422577 7, 0xFFFF, sum = 0
1404 00:56:33.422632 8, 0xFFFF, sum = 0
1405 00:56:33.422686 9, 0x0, sum = 1
1406 00:56:33.422739 10, 0x0, sum = 2
1407 00:56:33.422793 11, 0x0, sum = 3
1408 00:56:33.422848 12, 0x0, sum = 4
1409 00:56:33.422901 best_step = 10
1410 00:56:33.422955
1411 00:56:33.423007 ==
1412 00:56:33.423061 Dram Type= 6, Freq= 0, CH_0, rank 1
1413 00:56:33.423115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 00:56:33.423170 ==
1415 00:56:33.423223 RX Vref Scan: 0
1416 00:56:33.423276
1417 00:56:33.423329 RX Vref 0 -> 0, step: 1
1418 00:56:33.423383
1419 00:56:33.423435 RX Delay -95 -> 252, step: 8
1420 00:56:33.423488 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1421 00:56:33.423542 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1422 00:56:33.423595 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1423 00:56:33.423649 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1424 00:56:33.423702 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1425 00:56:33.423756 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1426 00:56:33.423809 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1427 00:56:33.423862 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1428 00:56:33.423916 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1429 00:56:33.423969 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1430 00:56:33.424023 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1431 00:56:33.424106 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1432 00:56:33.424159 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1433 00:56:33.424212 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1434 00:56:33.424265 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1435 00:56:33.424318 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1436 00:56:33.424372 ==
1437 00:56:33.424425 Dram Type= 6, Freq= 0, CH_0, rank 1
1438 00:56:33.424479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 00:56:33.424532 ==
1440 00:56:33.424586 DQS Delay:
1441 00:56:33.424639 DQS0 = 0, DQS1 = 0
1442 00:56:33.424692 DQM Delay:
1443 00:56:33.424746 DQM0 = 85, DQM1 = 76
1444 00:56:33.424800 DQ Delay:
1445 00:56:33.424853 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1446 00:56:33.424907 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1447 00:56:33.424960 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1448 00:56:33.425014 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1449 00:56:33.425067
1450 00:56:33.425120
1451 00:56:33.425173 [DQSOSCAuto] RK1, (LSB)MR18= 0x4209, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1452 00:56:33.425228 CH0 RK1: MR19=606, MR18=4209
1453 00:56:33.425282 CH0_RK1: MR19=0x606, MR18=0x4209, DQSOSC=393, MR23=63, INC=95, DEC=63
1454 00:56:33.425337 [RxdqsGatingPostProcess] freq 800
1455 00:56:33.425390 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1456 00:56:33.425443 Pre-setting of DQS Precalculation
1457 00:56:33.425497 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1458 00:56:33.425551 ==
1459 00:56:33.425604 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 00:56:33.425657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 00:56:33.425711 ==
1462 00:56:33.425764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1463 00:56:33.425818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1464 00:56:33.425872 [CA 0] Center 36 (6~67) winsize 62
1465 00:56:33.425925 [CA 1] Center 36 (6~67) winsize 62
1466 00:56:33.425979 [CA 2] Center 34 (4~65) winsize 62
1467 00:56:33.426032 [CA 3] Center 34 (3~65) winsize 63
1468 00:56:33.426085 [CA 4] Center 34 (4~65) winsize 62
1469 00:56:33.426138 [CA 5] Center 34 (3~65) winsize 63
1470 00:56:33.426228
1471 00:56:33.426282 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1472 00:56:33.426335
1473 00:56:33.426388 [CATrainingPosCal] consider 1 rank data
1474 00:56:33.426442 u2DelayCellTimex100 = 270/100 ps
1475 00:56:33.426495 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1476 00:56:33.426549 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1477 00:56:33.426602 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1478 00:56:33.426656 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1479 00:56:33.426709 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1480 00:56:33.426763 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1481 00:56:33.426815
1482 00:56:33.426870 CA PerBit enable=1, Macro0, CA PI delay=34
1483 00:56:33.426923
1484 00:56:33.426976 [CBTSetCACLKResult] CA Dly = 34
1485 00:56:33.427029 CS Dly: 5 (0~36)
1486 00:56:33.427083 ==
1487 00:56:33.427136 Dram Type= 6, Freq= 0, CH_1, rank 1
1488 00:56:33.427190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1489 00:56:33.427243 ==
1490 00:56:33.427297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1491 00:56:33.427367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1492 00:56:33.427424 [CA 0] Center 36 (6~67) winsize 62
1493 00:56:33.427477 [CA 1] Center 36 (6~67) winsize 62
1494 00:56:33.427531 [CA 2] Center 34 (3~65) winsize 63
1495 00:56:33.427584 [CA 3] Center 34 (4~65) winsize 62
1496 00:56:33.427637 [CA 4] Center 34 (4~65) winsize 62
1497 00:56:33.427690 [CA 5] Center 34 (3~65) winsize 63
1498 00:56:33.427744
1499 00:56:33.427797 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1500 00:56:33.427850
1501 00:56:33.427911 [CATrainingPosCal] consider 2 rank data
1502 00:56:33.427974 u2DelayCellTimex100 = 270/100 ps
1503 00:56:33.428030 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1504 00:56:33.428084 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1505 00:56:33.428138 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1506 00:56:33.428192 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1507 00:56:33.428245 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1508 00:56:33.428299 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1509 00:56:33.428352
1510 00:56:33.428405 CA PerBit enable=1, Macro0, CA PI delay=34
1511 00:56:33.428459
1512 00:56:33.428512 [CBTSetCACLKResult] CA Dly = 34
1513 00:56:33.428565 CS Dly: 6 (0~38)
1514 00:56:33.428618
1515 00:56:33.428672 ----->DramcWriteLeveling(PI) begin...
1516 00:56:33.428726 ==
1517 00:56:33.428780 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 00:56:33.428834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1519 00:56:33.428887 ==
1520 00:56:33.428941 Write leveling (Byte 0): 26 => 26
1521 00:56:33.429185 Write leveling (Byte 1): 31 => 31
1522 00:56:33.429246 DramcWriteLeveling(PI) end<-----
1523 00:56:33.429302
1524 00:56:33.429357 ==
1525 00:56:33.429437 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 00:56:33.429521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 00:56:33.429578 ==
1528 00:56:33.429633 [Gating] SW mode calibration
1529 00:56:33.429688 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1530 00:56:33.429744 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1531 00:56:33.429798 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1532 00:56:33.429852 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1533 00:56:33.429906 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:56:33.429960 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:56:33.430013 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:56:33.430067 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 00:56:33.430120 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 00:56:33.430206 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 00:56:33.430275 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 00:56:33.430328 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 00:56:33.430382 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 00:56:33.430435 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 00:56:33.430489 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 00:56:33.430542 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 00:56:33.430595 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 00:56:33.430649 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 00:56:33.430702 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 00:56:33.430755 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1549 00:56:33.430808 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 00:56:33.430862 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 00:56:33.430915 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 00:56:33.430968 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 00:56:33.431021 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 00:56:33.431075 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 00:56:33.431128 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 00:56:33.431181 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 00:56:33.431234 0 9 8 | B1->B0 | 2c2c 2e2e | 0 1 | (0 0) (1 1)
1558 00:56:33.431289 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 00:56:33.431342 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 00:56:33.431395 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 00:56:33.431448 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1562 00:56:33.431502 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 00:56:33.431555 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 00:56:33.431608 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1565 00:56:33.431661 0 10 8 | B1->B0 | 2f2f 2929 | 0 0 | (1 0) (0 0)
1566 00:56:33.431714 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 00:56:33.431768 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 00:56:33.431821 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 00:56:33.431874 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 00:56:33.431927 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 00:56:33.431981 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 00:56:33.432034 0 11 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1573 00:56:33.432087 0 11 8 | B1->B0 | 3a3a 3b3b | 0 0 | (0 0) (1 1)
1574 00:56:33.432140 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 00:56:33.432194 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 00:56:33.432247 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 00:56:33.432300 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 00:56:33.432353 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 00:56:33.432407 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 00:56:33.432460 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1581 00:56:33.432513 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1582 00:56:33.432567 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 00:56:33.432620 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 00:56:33.432673 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 00:56:33.432726 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 00:56:33.432779 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 00:56:33.432833 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 00:56:33.432885 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 00:56:33.432939 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 00:56:33.432992 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 00:56:33.433045 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 00:56:33.433099 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 00:56:33.433152 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 00:56:33.433205 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 00:56:33.433258 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1596 00:56:33.433312 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1597 00:56:33.433365 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1598 00:56:33.433418 Total UI for P1: 0, mck2ui 16
1599 00:56:33.433472 best dqsien dly found for B0: ( 0, 14, 2)
1600 00:56:33.433526 Total UI for P1: 0, mck2ui 16
1601 00:56:33.433580 best dqsien dly found for B1: ( 0, 14, 6)
1602 00:56:33.433634 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1603 00:56:33.433687 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1604 00:56:33.433740
1605 00:56:33.433792 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1606 00:56:33.433846 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1607 00:56:33.433900 [Gating] SW calibration Done
1608 00:56:33.434148 ==
1609 00:56:33.434285 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 00:56:33.434341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 00:56:33.434396 ==
1612 00:56:33.434449 RX Vref Scan: 0
1613 00:56:33.434504
1614 00:56:33.434557 RX Vref 0 -> 0, step: 1
1615 00:56:33.434611
1616 00:56:33.434665 RX Delay -130 -> 252, step: 16
1617 00:56:33.434718 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1618 00:56:33.434772 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1619 00:56:33.434826 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1620 00:56:33.434880 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1621 00:56:33.434933 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1622 00:56:33.434987 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1623 00:56:33.435040 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1624 00:56:33.435093 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1625 00:56:33.435147 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1626 00:56:33.435200 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1627 00:56:33.435253 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1628 00:56:33.435307 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1629 00:56:33.435361 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1630 00:56:33.435414 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1631 00:56:33.435467 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1632 00:56:33.435521 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1633 00:56:33.435574 ==
1634 00:56:33.435627 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 00:56:33.435681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 00:56:33.435735 ==
1637 00:56:33.435788 DQS Delay:
1638 00:56:33.435842 DQS0 = 0, DQS1 = 0
1639 00:56:33.435896 DQM Delay:
1640 00:56:33.435949 DQM0 = 89, DQM1 = 78
1641 00:56:33.436002 DQ Delay:
1642 00:56:33.436055 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1643 00:56:33.436109 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1644 00:56:33.436163 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1645 00:56:33.436216 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1646 00:56:33.436270
1647 00:56:33.436322
1648 00:56:33.436375 ==
1649 00:56:33.436428 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 00:56:33.436481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 00:56:33.436535 ==
1652 00:56:33.436589
1653 00:56:33.436640
1654 00:56:33.436693 TX Vref Scan disable
1655 00:56:33.436747 == TX Byte 0 ==
1656 00:56:33.436800 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1657 00:56:33.436854 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1658 00:56:33.436907 == TX Byte 1 ==
1659 00:56:33.436960 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1660 00:56:33.437013 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1661 00:56:33.437067 ==
1662 00:56:33.437120 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 00:56:33.437174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 00:56:33.437227 ==
1665 00:56:33.437281 TX Vref=22, minBit 8, minWin=26, winSum=438
1666 00:56:33.437335 TX Vref=24, minBit 8, minWin=27, winSum=445
1667 00:56:33.437389 TX Vref=26, minBit 10, minWin=27, winSum=451
1668 00:56:33.437444 TX Vref=28, minBit 9, minWin=27, winSum=452
1669 00:56:33.437498 TX Vref=30, minBit 9, minWin=27, winSum=449
1670 00:56:33.437552 TX Vref=32, minBit 0, minWin=27, winSum=446
1671 00:56:33.437605 [TxChooseVref] Worse bit 9, Min win 27, Win sum 452, Final Vref 28
1672 00:56:33.437659
1673 00:56:33.437713 Final TX Range 1 Vref 28
1674 00:56:33.437767
1675 00:56:33.437819 ==
1676 00:56:33.437873 Dram Type= 6, Freq= 0, CH_1, rank 0
1677 00:56:33.437927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1678 00:56:33.437980 ==
1679 00:56:33.438033
1680 00:56:33.438086
1681 00:56:33.438138 TX Vref Scan disable
1682 00:56:33.438224 == TX Byte 0 ==
1683 00:56:33.438291 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1684 00:56:33.438346 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1685 00:56:33.438399 == TX Byte 1 ==
1686 00:56:33.438453 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1687 00:56:33.438506 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1688 00:56:33.438560
1689 00:56:33.438625 [DATLAT]
1690 00:56:33.438680 Freq=800, CH1 RK0
1691 00:56:33.438734
1692 00:56:33.438788 DATLAT Default: 0xa
1693 00:56:33.438841 0, 0xFFFF, sum = 0
1694 00:56:33.438906 1, 0xFFFF, sum = 0
1695 00:56:33.438962 2, 0xFFFF, sum = 0
1696 00:56:33.439054 3, 0xFFFF, sum = 0
1697 00:56:33.439118 4, 0xFFFF, sum = 0
1698 00:56:33.439174 5, 0xFFFF, sum = 0
1699 00:56:33.439229 6, 0xFFFF, sum = 0
1700 00:56:33.439284 7, 0xFFFF, sum = 0
1701 00:56:33.439338 8, 0xFFFF, sum = 0
1702 00:56:33.439392 9, 0x0, sum = 1
1703 00:56:33.439447 10, 0x0, sum = 2
1704 00:56:33.439502 11, 0x0, sum = 3
1705 00:56:33.439557 12, 0x0, sum = 4
1706 00:56:33.439612 best_step = 10
1707 00:56:33.439665
1708 00:56:33.439719 ==
1709 00:56:33.439773 Dram Type= 6, Freq= 0, CH_1, rank 0
1710 00:56:33.439827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1711 00:56:33.439881 ==
1712 00:56:33.439935 RX Vref Scan: 1
1713 00:56:33.439989
1714 00:56:33.440043 Set Vref Range= 32 -> 127
1715 00:56:33.440097
1716 00:56:33.440150 RX Vref 32 -> 127, step: 1
1717 00:56:33.440204
1718 00:56:33.440257 RX Delay -95 -> 252, step: 8
1719 00:56:33.440310
1720 00:56:33.440363 Set Vref, RX VrefLevel [Byte0]: 32
1721 00:56:33.440417 [Byte1]: 32
1722 00:56:33.440470
1723 00:56:33.440523 Set Vref, RX VrefLevel [Byte0]: 33
1724 00:56:33.440576 [Byte1]: 33
1725 00:56:33.440629
1726 00:56:33.440682 Set Vref, RX VrefLevel [Byte0]: 34
1727 00:56:33.440736 [Byte1]: 34
1728 00:56:33.440790
1729 00:56:33.440843 Set Vref, RX VrefLevel [Byte0]: 35
1730 00:56:33.440896 [Byte1]: 35
1731 00:56:33.440949
1732 00:56:33.441002 Set Vref, RX VrefLevel [Byte0]: 36
1733 00:56:33.441055 [Byte1]: 36
1734 00:56:33.441108
1735 00:56:33.441161 Set Vref, RX VrefLevel [Byte0]: 37
1736 00:56:33.441215 [Byte1]: 37
1737 00:56:33.441268
1738 00:56:33.441321 Set Vref, RX VrefLevel [Byte0]: 38
1739 00:56:33.441375 [Byte1]: 38
1740 00:56:33.441428
1741 00:56:33.441480 Set Vref, RX VrefLevel [Byte0]: 39
1742 00:56:33.441534 [Byte1]: 39
1743 00:56:33.441587
1744 00:56:33.441640 Set Vref, RX VrefLevel [Byte0]: 40
1745 00:56:33.441693 [Byte1]: 40
1746 00:56:33.441746
1747 00:56:33.441799 Set Vref, RX VrefLevel [Byte0]: 41
1748 00:56:33.441852 [Byte1]: 41
1749 00:56:33.441905
1750 00:56:33.441959 Set Vref, RX VrefLevel [Byte0]: 42
1751 00:56:33.442012 [Byte1]: 42
1752 00:56:33.442065
1753 00:56:33.442117 Set Vref, RX VrefLevel [Byte0]: 43
1754 00:56:33.442178 [Byte1]: 43
1755 00:56:33.442271
1756 00:56:33.442325 Set Vref, RX VrefLevel [Byte0]: 44
1757 00:56:33.442378 [Byte1]: 44
1758 00:56:33.442438
1759 00:56:33.442497 Set Vref, RX VrefLevel [Byte0]: 45
1760 00:56:33.442551 [Byte1]: 45
1761 00:56:33.442623
1762 00:56:33.442720 Set Vref, RX VrefLevel [Byte0]: 46
1763 00:56:33.442788 [Byte1]: 46
1764 00:56:33.442843
1765 00:56:33.443094 Set Vref, RX VrefLevel [Byte0]: 47
1766 00:56:33.443155 [Byte1]: 47
1767 00:56:33.443210
1768 00:56:33.443264 Set Vref, RX VrefLevel [Byte0]: 48
1769 00:56:33.443318 [Byte1]: 48
1770 00:56:33.443371
1771 00:56:33.443425 Set Vref, RX VrefLevel [Byte0]: 49
1772 00:56:33.443479 [Byte1]: 49
1773 00:56:33.443532
1774 00:56:33.443586 Set Vref, RX VrefLevel [Byte0]: 50
1775 00:56:33.443640 [Byte1]: 50
1776 00:56:33.443693
1777 00:56:33.443746 Set Vref, RX VrefLevel [Byte0]: 51
1778 00:56:33.443799 [Byte1]: 51
1779 00:56:33.443853
1780 00:56:33.443906 Set Vref, RX VrefLevel [Byte0]: 52
1781 00:56:33.443959 [Byte1]: 52
1782 00:56:33.444012
1783 00:56:33.444065 Set Vref, RX VrefLevel [Byte0]: 53
1784 00:56:33.444119 [Byte1]: 53
1785 00:56:33.444172
1786 00:56:33.444225 Set Vref, RX VrefLevel [Byte0]: 54
1787 00:56:33.444277 [Byte1]: 54
1788 00:56:33.444331
1789 00:56:33.444384 Set Vref, RX VrefLevel [Byte0]: 55
1790 00:56:33.444436 [Byte1]: 55
1791 00:56:33.444489
1792 00:56:33.444542 Set Vref, RX VrefLevel [Byte0]: 56
1793 00:56:33.444595 [Byte1]: 56
1794 00:56:33.444649
1795 00:56:33.444701 Set Vref, RX VrefLevel [Byte0]: 57
1796 00:56:33.444755 [Byte1]: 57
1797 00:56:33.444807
1798 00:56:33.444860 Set Vref, RX VrefLevel [Byte0]: 58
1799 00:56:33.444914 [Byte1]: 58
1800 00:56:33.444968
1801 00:56:33.445020 Set Vref, RX VrefLevel [Byte0]: 59
1802 00:56:33.445074 [Byte1]: 59
1803 00:56:33.445126
1804 00:56:33.445179 Set Vref, RX VrefLevel [Byte0]: 60
1805 00:56:33.445232 [Byte1]: 60
1806 00:56:33.445285
1807 00:56:33.445337 Set Vref, RX VrefLevel [Byte0]: 61
1808 00:56:33.445391 [Byte1]: 61
1809 00:56:33.445444
1810 00:56:33.445497 Set Vref, RX VrefLevel [Byte0]: 62
1811 00:56:33.445550 [Byte1]: 62
1812 00:56:33.445602
1813 00:56:33.445656 Set Vref, RX VrefLevel [Byte0]: 63
1814 00:56:33.445709 [Byte1]: 63
1815 00:56:33.445762
1816 00:56:33.445815 Set Vref, RX VrefLevel [Byte0]: 64
1817 00:56:33.445867 [Byte1]: 64
1818 00:56:33.445920
1819 00:56:33.445973 Set Vref, RX VrefLevel [Byte0]: 65
1820 00:56:33.446027 [Byte1]: 65
1821 00:56:33.446080
1822 00:56:33.446133 Set Vref, RX VrefLevel [Byte0]: 66
1823 00:56:33.446236 [Byte1]: 66
1824 00:56:33.446290
1825 00:56:33.446343 Set Vref, RX VrefLevel [Byte0]: 67
1826 00:56:33.446397 [Byte1]: 67
1827 00:56:33.446450
1828 00:56:33.446502 Set Vref, RX VrefLevel [Byte0]: 68
1829 00:56:33.446555 [Byte1]: 68
1830 00:56:33.446608
1831 00:56:33.446661 Set Vref, RX VrefLevel [Byte0]: 69
1832 00:56:33.446715 [Byte1]: 69
1833 00:56:33.446768
1834 00:56:33.446822 Set Vref, RX VrefLevel [Byte0]: 70
1835 00:56:33.446875 [Byte1]: 70
1836 00:56:33.446928
1837 00:56:33.446980 Set Vref, RX VrefLevel [Byte0]: 71
1838 00:56:33.447039 [Byte1]: 71
1839 00:56:33.447098
1840 00:56:33.447151 Set Vref, RX VrefLevel [Byte0]: 72
1841 00:56:33.447205 [Byte1]: 72
1842 00:56:33.447259
1843 00:56:33.447312 Set Vref, RX VrefLevel [Byte0]: 73
1844 00:56:33.447372 [Byte1]: 73
1845 00:56:33.447427
1846 00:56:33.447480 Set Vref, RX VrefLevel [Byte0]: 74
1847 00:56:33.447534 [Byte1]: 74
1848 00:56:33.447588
1849 00:56:33.447640 Set Vref, RX VrefLevel [Byte0]: 75
1850 00:56:33.447694 [Byte1]: 75
1851 00:56:33.447747
1852 00:56:33.447801 Set Vref, RX VrefLevel [Byte0]: 76
1853 00:56:33.447854 [Byte1]: 76
1854 00:56:33.447908
1855 00:56:33.447960 Set Vref, RX VrefLevel [Byte0]: 77
1856 00:56:33.448014 [Byte1]: 77
1857 00:56:33.448067
1858 00:56:33.448119 Final RX Vref Byte 0 = 52 to rank0
1859 00:56:33.448173 Final RX Vref Byte 1 = 66 to rank0
1860 00:56:33.448227 Final RX Vref Byte 0 = 52 to rank1
1861 00:56:33.448280 Final RX Vref Byte 1 = 66 to rank1==
1862 00:56:33.448333 Dram Type= 6, Freq= 0, CH_1, rank 0
1863 00:56:33.448387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 00:56:33.448441 ==
1865 00:56:33.448495 DQS Delay:
1866 00:56:33.448548 DQS0 = 0, DQS1 = 0
1867 00:56:33.448601 DQM Delay:
1868 00:56:33.448654 DQM0 = 86, DQM1 = 78
1869 00:56:33.448708 DQ Delay:
1870 00:56:33.448760 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1871 00:56:33.448814 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1872 00:56:33.448867 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1873 00:56:33.448921 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1874 00:56:33.448974
1875 00:56:33.449027
1876 00:56:33.449080 [DQSOSCAuto] RK0, (LSB)MR18= 0x301c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1877 00:56:33.449134 CH1 RK0: MR19=606, MR18=301C
1878 00:56:33.449188 CH1_RK0: MR19=0x606, MR18=0x301C, DQSOSC=397, MR23=63, INC=93, DEC=62
1879 00:56:33.449241
1880 00:56:33.449295 ----->DramcWriteLeveling(PI) begin...
1881 00:56:33.449349 ==
1882 00:56:33.449403 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 00:56:33.449457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1884 00:56:33.449511 ==
1885 00:56:33.449564 Write leveling (Byte 0): 27 => 27
1886 00:56:33.449618 Write leveling (Byte 1): 30 => 30
1887 00:56:33.449671 DramcWriteLeveling(PI) end<-----
1888 00:56:33.449724
1889 00:56:33.449777 ==
1890 00:56:33.449831 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 00:56:33.449884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1892 00:56:33.449938 ==
1893 00:56:33.449991 [Gating] SW mode calibration
1894 00:56:33.450044 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1895 00:56:33.450099 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1896 00:56:33.450153 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1897 00:56:33.450278 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1898 00:56:33.450396 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 00:56:33.450459 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:56:33.450514 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:56:33.450568 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:56:33.450622 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:56:33.450675 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:56:33.450729 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 00:56:33.450782 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 00:56:33.450836 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 00:56:33.451079 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 00:56:33.451139 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 00:56:33.451194 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 00:56:33.451247 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 00:56:33.451301 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 00:56:33.451354 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 00:56:33.451408 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1914 00:56:33.451461 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1915 00:56:33.451515 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 00:56:33.451569 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 00:56:33.451622 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 00:56:33.451677 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 00:56:33.451730 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 00:56:33.451783 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 00:56:33.451836 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 00:56:33.451890 0 9 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (1 0)
1923 00:56:33.451943 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1924 00:56:33.451996 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1925 00:56:33.452049 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1926 00:56:33.452102 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1927 00:56:33.452156 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1928 00:56:33.452209 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1929 00:56:33.452263 0 10 4 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 0)
1930 00:56:33.452316 0 10 8 | B1->B0 | 2525 2424 | 0 0 | (0 0) (1 0)
1931 00:56:33.452370 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1932 00:56:33.452424 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1933 00:56:33.452477 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1934 00:56:33.452530 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1935 00:56:33.452583 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1936 00:56:33.452636 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1937 00:56:33.452689 0 11 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
1938 00:56:33.452742 0 11 8 | B1->B0 | 4040 3a3a | 1 1 | (0 0) (0 0)
1939 00:56:33.452796 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 00:56:33.452849 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 00:56:33.452902 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 00:56:33.452956 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 00:56:33.453009 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 00:56:33.453063 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 00:56:33.453116 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 00:56:33.453170 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1947 00:56:33.453223 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 00:56:33.453277 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 00:56:33.453331 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 00:56:33.453402 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 00:56:33.453500 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 00:56:33.453561 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 00:56:33.453615 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 00:56:33.453670 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 00:56:33.453724 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 00:56:33.453778 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 00:56:33.453832 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 00:56:33.453886 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 00:56:33.453939 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 00:56:33.453993 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 00:56:33.454046 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1962 00:56:33.454100 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1963 00:56:33.454154 Total UI for P1: 0, mck2ui 16
1964 00:56:33.454250 best dqsien dly found for B1: ( 0, 14, 4)
1965 00:56:33.454304 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1966 00:56:33.454358 Total UI for P1: 0, mck2ui 16
1967 00:56:33.454412 best dqsien dly found for B0: ( 0, 14, 6)
1968 00:56:33.454466 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1969 00:56:33.454519 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1970 00:56:33.454573
1971 00:56:33.454626 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1972 00:56:33.454681 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1973 00:56:33.454734 [Gating] SW calibration Done
1974 00:56:33.454788 ==
1975 00:56:33.454840 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 00:56:33.454894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 00:56:33.454948 ==
1978 00:56:33.455001 RX Vref Scan: 0
1979 00:56:33.455054
1980 00:56:33.455108 RX Vref 0 -> 0, step: 1
1981 00:56:33.455161
1982 00:56:33.455214 RX Delay -130 -> 252, step: 16
1983 00:56:33.455268 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1984 00:56:33.455321 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1985 00:56:33.455375 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1986 00:56:33.455453 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1987 00:56:33.455520 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1988 00:56:33.725961 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1989 00:56:33.726524 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1990 00:56:33.726901 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1991 00:56:33.727248 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1992 00:56:33.727579 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1993 00:56:33.727905 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1994 00:56:33.728226 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1995 00:56:33.728590 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1996 00:56:33.728918 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1997 00:56:33.729627 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1998 00:56:33.729988 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1999 00:56:33.730368 ==
2000 00:56:33.730692 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 00:56:33.731208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 00:56:33.731781 ==
2003 00:56:33.732135 DQS Delay:
2004 00:56:33.732456 DQS0 = 0, DQS1 = 0
2005 00:56:33.732769 DQM Delay:
2006 00:56:33.733080 DQM0 = 87, DQM1 = 79
2007 00:56:33.733387 DQ Delay:
2008 00:56:33.733695 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =77
2009 00:56:33.734002 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2010 00:56:33.734464 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
2011 00:56:33.735017 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2012 00:56:33.735553
2013 00:56:33.735892
2014 00:56:33.736214 ==
2015 00:56:33.736497 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 00:56:33.736782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 00:56:33.737064 ==
2018 00:56:33.737343
2019 00:56:33.737617
2020 00:56:33.737889 TX Vref Scan disable
2021 00:56:33.738193 == TX Byte 0 ==
2022 00:56:33.738493 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2023 00:56:33.738775 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2024 00:56:33.739057 == TX Byte 1 ==
2025 00:56:33.739398 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2026 00:56:33.739685 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2027 00:56:33.739967 ==
2028 00:56:33.740244 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 00:56:33.740521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 00:56:33.740806 ==
2031 00:56:33.741083 TX Vref=22, minBit 8, minWin=26, winSum=441
2032 00:56:33.741365 TX Vref=24, minBit 8, minWin=26, winSum=445
2033 00:56:33.741646 TX Vref=26, minBit 10, minWin=27, winSum=449
2034 00:56:33.741929 TX Vref=28, minBit 8, minWin=27, winSum=451
2035 00:56:33.742261 TX Vref=30, minBit 13, minWin=27, winSum=450
2036 00:56:33.742585 TX Vref=32, minBit 13, minWin=27, winSum=448
2037 00:56:33.742867 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 28
2038 00:56:33.743147
2039 00:56:33.743420 Final TX Range 1 Vref 28
2040 00:56:33.743698
2041 00:56:33.743974 ==
2042 00:56:33.744249 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 00:56:33.744529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 00:56:33.744807 ==
2045 00:56:33.745086
2046 00:56:33.745358
2047 00:56:33.745631 TX Vref Scan disable
2048 00:56:33.745908 == TX Byte 0 ==
2049 00:56:33.746233 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2050 00:56:33.746560 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2051 00:56:33.746842 == TX Byte 1 ==
2052 00:56:33.747119 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2053 00:56:33.747394 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2054 00:56:33.747713
2055 00:56:33.747999 [DATLAT]
2056 00:56:33.748276 Freq=800, CH1 RK1
2057 00:56:33.748553
2058 00:56:33.748831 DATLAT Default: 0xa
2059 00:56:33.749116 0, 0xFFFF, sum = 0
2060 00:56:33.749320 1, 0xFFFF, sum = 0
2061 00:56:33.749521 2, 0xFFFF, sum = 0
2062 00:56:33.749725 3, 0xFFFF, sum = 0
2063 00:56:33.749925 4, 0xFFFF, sum = 0
2064 00:56:33.750126 5, 0xFFFF, sum = 0
2065 00:56:33.750357 6, 0xFFFF, sum = 0
2066 00:56:33.750561 7, 0xFFFF, sum = 0
2067 00:56:33.750761 8, 0xFFFF, sum = 0
2068 00:56:33.750963 9, 0x0, sum = 1
2069 00:56:33.751226 10, 0x0, sum = 2
2070 00:56:33.751446 11, 0x0, sum = 3
2071 00:56:33.751801 12, 0x0, sum = 4
2072 00:56:33.752143 best_step = 10
2073 00:56:33.752358
2074 00:56:33.752591 ==
2075 00:56:33.752802 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 00:56:33.753006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 00:56:33.753210 ==
2078 00:56:33.753412 RX Vref Scan: 0
2079 00:56:33.753610
2080 00:56:33.753808 RX Vref 0 -> 0, step: 1
2081 00:56:33.754036
2082 00:56:33.754270 RX Delay -95 -> 252, step: 8
2083 00:56:33.754437 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2084 00:56:33.754660 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2085 00:56:33.754934 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2086 00:56:33.755107 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2087 00:56:33.755264 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2088 00:56:33.755418 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2089 00:56:33.755572 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2090 00:56:33.755725 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2091 00:56:33.755877 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2092 00:56:33.756029 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2093 00:56:33.756180 iDelay=217, Bit 10, Center 80 (-31 ~ 192) 224
2094 00:56:33.756330 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2095 00:56:33.756480 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2096 00:56:33.756631 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2097 00:56:33.756782 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2098 00:56:33.756931 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2099 00:56:33.757081 ==
2100 00:56:33.757233 Dram Type= 6, Freq= 0, CH_1, rank 1
2101 00:56:33.757384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2102 00:56:33.757613 ==
2103 00:56:33.757875 DQS Delay:
2104 00:56:33.758041 DQS0 = 0, DQS1 = 0
2105 00:56:33.758217 DQM Delay:
2106 00:56:33.758375 DQM0 = 86, DQM1 = 79
2107 00:56:33.758526 DQ Delay:
2108 00:56:33.758688 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
2109 00:56:33.758841 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2110 00:56:33.758993 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
2111 00:56:33.759143 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2112 00:56:33.759264
2113 00:56:33.759385
2114 00:56:33.759505 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2115 00:56:33.759628 CH1 RK1: MR19=606, MR18=1A12
2116 00:56:33.759750 CH1_RK1: MR19=0x606, MR18=0x1A12, DQSOSC=403, MR23=63, INC=90, DEC=60
2117 00:56:33.759872 [RxdqsGatingPostProcess] freq 800
2118 00:56:33.759993 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2119 00:56:33.760113 Pre-setting of DQS Precalculation
2120 00:56:33.760234 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2121 00:56:33.760355 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2122 00:56:33.760477 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2123 00:56:33.760598
2124 00:56:33.760718
2125 00:56:33.760861 [Calibration Summary] 1600 Mbps
2126 00:56:33.760986 CH 0, Rank 0
2127 00:56:33.761108 SW Impedance : PASS
2128 00:56:33.761231 DUTY Scan : NO K
2129 00:56:33.761352 ZQ Calibration : PASS
2130 00:56:33.761472 Jitter Meter : NO K
2131 00:56:33.761592 CBT Training : PASS
2132 00:56:33.761712 Write leveling : PASS
2133 00:56:33.761830 RX DQS gating : PASS
2134 00:56:33.761951 RX DQ/DQS(RDDQC) : PASS
2135 00:56:33.762071 TX DQ/DQS : PASS
2136 00:56:33.762210 RX DATLAT : PASS
2137 00:56:33.762333 RX DQ/DQS(Engine): PASS
2138 00:56:33.762452 TX OE : NO K
2139 00:56:33.762572 All Pass.
2140 00:56:33.762691
2141 00:56:33.762811 CH 0, Rank 1
2142 00:56:33.762932 SW Impedance : PASS
2143 00:56:33.763052 DUTY Scan : NO K
2144 00:56:33.763487 ZQ Calibration : PASS
2145 00:56:33.763646 Jitter Meter : NO K
2146 00:56:33.763781 CBT Training : PASS
2147 00:56:33.763909 Write leveling : PASS
2148 00:56:33.764036 RX DQS gating : PASS
2149 00:56:33.764159 RX DQ/DQS(RDDQC) : PASS
2150 00:56:33.764262 TX DQ/DQS : PASS
2151 00:56:33.764365 RX DATLAT : PASS
2152 00:56:33.764467 RX DQ/DQS(Engine): PASS
2153 00:56:33.764575 TX OE : NO K
2154 00:56:33.764680 All Pass.
2155 00:56:33.764781
2156 00:56:33.764882 CH 1, Rank 0
2157 00:56:33.764984 SW Impedance : PASS
2158 00:56:33.765086 DUTY Scan : NO K
2159 00:56:33.765187 ZQ Calibration : PASS
2160 00:56:33.765288 Jitter Meter : NO K
2161 00:56:33.765388 CBT Training : PASS
2162 00:56:33.765489 Write leveling : PASS
2163 00:56:33.765589 RX DQS gating : PASS
2164 00:56:33.765689 RX DQ/DQS(RDDQC) : PASS
2165 00:56:33.765789 TX DQ/DQS : PASS
2166 00:56:33.765890 RX DATLAT : PASS
2167 00:56:33.765990 RX DQ/DQS(Engine): PASS
2168 00:56:33.766089 TX OE : NO K
2169 00:56:33.766199 All Pass.
2170 00:56:33.766302
2171 00:56:33.766401 CH 1, Rank 1
2172 00:56:33.766501 SW Impedance : PASS
2173 00:56:33.766602 DUTY Scan : NO K
2174 00:56:33.766723 ZQ Calibration : PASS
2175 00:56:33.766825 Jitter Meter : NO K
2176 00:56:33.766926 CBT Training : PASS
2177 00:56:33.767026 Write leveling : PASS
2178 00:56:33.767127 RX DQS gating : PASS
2179 00:56:33.767227 RX DQ/DQS(RDDQC) : PASS
2180 00:56:33.767328 TX DQ/DQS : PASS
2181 00:56:33.767427 RX DATLAT : PASS
2182 00:56:33.767528 RX DQ/DQS(Engine): PASS
2183 00:56:33.767628 TX OE : NO K
2184 00:56:33.767728 All Pass.
2185 00:56:33.767827
2186 00:56:33.767927 DramC Write-DBI off
2187 00:56:33.768027 PER_BANK_REFRESH: Hybrid Mode
2188 00:56:33.768128 TX_TRACKING: ON
2189 00:56:33.768228 [GetDramInforAfterCalByMRR] Vendor 6.
2190 00:56:33.768328 [GetDramInforAfterCalByMRR] Revision 606.
2191 00:56:33.768428 [GetDramInforAfterCalByMRR] Revision 2 0.
2192 00:56:33.768528 MR0 0x3b3b
2193 00:56:33.768627 MR8 0x5151
2194 00:56:33.768727 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2195 00:56:33.768828
2196 00:56:33.768927 MR0 0x3b3b
2197 00:56:33.769026 MR8 0x5151
2198 00:56:33.769127 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2199 00:56:33.769214
2200 00:56:33.769300 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2201 00:56:33.769388 [FAST_K] Save calibration result to emmc
2202 00:56:33.769474 [FAST_K] Save calibration result to emmc
2203 00:56:33.769560 dram_init: config_dvfs: 1
2204 00:56:33.769646 dramc_set_vcore_voltage set vcore to 662500
2205 00:56:33.769732 Read voltage for 1200, 2
2206 00:56:33.769818 Vio18 = 0
2207 00:56:33.769903 Vcore = 662500
2208 00:56:33.769989 Vdram = 0
2209 00:56:33.770074 Vddq = 0
2210 00:56:33.770164 Vmddr = 0
2211 00:56:33.770251 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2212 00:56:33.770339 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2213 00:56:33.770425 MEM_TYPE=3, freq_sel=15
2214 00:56:33.770511 sv_algorithm_assistance_LP4_1600
2215 00:56:33.770598 ============ PULL DRAM RESETB DOWN ============
2216 00:56:33.770685 ========== PULL DRAM RESETB DOWN end =========
2217 00:56:33.770772 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2218 00:56:33.770858 ===================================
2219 00:56:33.770945 LPDDR4 DRAM CONFIGURATION
2220 00:56:33.771030 ===================================
2221 00:56:33.771117 EX_ROW_EN[0] = 0x0
2222 00:56:33.771202 EX_ROW_EN[1] = 0x0
2223 00:56:33.771288 LP4Y_EN = 0x0
2224 00:56:33.771374 WORK_FSP = 0x0
2225 00:56:33.771460 WL = 0x4
2226 00:56:33.771545 RL = 0x4
2227 00:56:33.771630 BL = 0x2
2228 00:56:33.771716 RPST = 0x0
2229 00:56:33.771801 RD_PRE = 0x0
2230 00:56:33.771887 WR_PRE = 0x1
2231 00:56:33.771973 WR_PST = 0x0
2232 00:56:33.772058 DBI_WR = 0x0
2233 00:56:33.772144 DBI_RD = 0x0
2234 00:56:33.772230 OTF = 0x1
2235 00:56:33.772316 ===================================
2236 00:56:33.772403 ===================================
2237 00:56:33.772490 ANA top config
2238 00:56:33.772576 ===================================
2239 00:56:33.772662 DLL_ASYNC_EN = 0
2240 00:56:33.772749 ALL_SLAVE_EN = 0
2241 00:56:33.772834 NEW_RANK_MODE = 1
2242 00:56:33.772922 DLL_IDLE_MODE = 1
2243 00:56:33.773006 LP45_APHY_COMB_EN = 1
2244 00:56:33.773091 TX_ODT_DIS = 1
2245 00:56:33.773177 NEW_8X_MODE = 1
2246 00:56:33.773264 ===================================
2247 00:56:33.773350 ===================================
2248 00:56:33.773437 data_rate = 2400
2249 00:56:33.773523 CKR = 1
2250 00:56:33.773610 DQ_P2S_RATIO = 8
2251 00:56:33.773695 ===================================
2252 00:56:33.773783 CA_P2S_RATIO = 8
2253 00:56:33.773868 DQ_CA_OPEN = 0
2254 00:56:33.773954 DQ_SEMI_OPEN = 0
2255 00:56:33.774039 CA_SEMI_OPEN = 0
2256 00:56:33.774128 CA_FULL_RATE = 0
2257 00:56:33.774210 DQ_CKDIV4_EN = 0
2258 00:56:33.774287 CA_CKDIV4_EN = 0
2259 00:56:33.774362 CA_PREDIV_EN = 0
2260 00:56:33.774438 PH8_DLY = 17
2261 00:56:33.774515 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2262 00:56:33.774590 DQ_AAMCK_DIV = 4
2263 00:56:33.774665 CA_AAMCK_DIV = 4
2264 00:56:33.774740 CA_ADMCK_DIV = 4
2265 00:56:33.774815 DQ_TRACK_CA_EN = 0
2266 00:56:33.774890 CA_PICK = 1200
2267 00:56:33.774966 CA_MCKIO = 1200
2268 00:56:33.775041 MCKIO_SEMI = 0
2269 00:56:33.775116 PLL_FREQ = 2366
2270 00:56:33.775191 DQ_UI_PI_RATIO = 32
2271 00:56:33.775266 CA_UI_PI_RATIO = 0
2272 00:56:33.775341 ===================================
2273 00:56:33.775418 ===================================
2274 00:56:33.775493 memory_type:LPDDR4
2275 00:56:33.775568 GP_NUM : 10
2276 00:56:33.775643 SRAM_EN : 1
2277 00:56:33.775719 MD32_EN : 0
2278 00:56:33.775794 ===================================
2279 00:56:33.775921 [ANA_INIT] >>>>>>>>>>>>>>
2280 00:56:33.776051 <<<<<< [CONFIGURE PHASE]: ANA_TX
2281 00:56:33.776136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2282 00:56:33.776215 ===================================
2283 00:56:33.776292 data_rate = 2400,PCW = 0X5b00
2284 00:56:33.776368 ===================================
2285 00:56:33.776445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2286 00:56:33.776522 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2287 00:56:33.776807 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2288 00:56:33.776896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2289 00:56:33.776980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2290 00:56:33.777059 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2291 00:56:33.777136 [ANA_INIT] flow start
2292 00:56:33.777212 [ANA_INIT] PLL >>>>>>>>
2293 00:56:33.777289 [ANA_INIT] PLL <<<<<<<<
2294 00:56:33.777365 [ANA_INIT] MIDPI >>>>>>>>
2295 00:56:33.777441 [ANA_INIT] MIDPI <<<<<<<<
2296 00:56:33.777516 [ANA_INIT] DLL >>>>>>>>
2297 00:56:33.777592 [ANA_INIT] DLL <<<<<<<<
2298 00:56:33.777668 [ANA_INIT] flow end
2299 00:56:33.777742 ============ LP4 DIFF to SE enter ============
2300 00:56:33.777819 ============ LP4 DIFF to SE exit ============
2301 00:56:33.777896 [ANA_INIT] <<<<<<<<<<<<<
2302 00:56:33.777972 [Flow] Enable top DCM control >>>>>
2303 00:56:33.778048 [Flow] Enable top DCM control <<<<<
2304 00:56:33.778124 Enable DLL master slave shuffle
2305 00:56:33.778218 ==============================================================
2306 00:56:33.778297 Gating Mode config
2307 00:56:33.778373 ==============================================================
2308 00:56:33.778450 Config description:
2309 00:56:33.778526 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2310 00:56:33.778604 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2311 00:56:33.778681 SELPH_MODE 0: By rank 1: By Phase
2312 00:56:33.778757 ==============================================================
2313 00:56:33.778834 GAT_TRACK_EN = 1
2314 00:56:33.778910 RX_GATING_MODE = 2
2315 00:56:33.778986 RX_GATING_TRACK_MODE = 2
2316 00:56:33.779061 SELPH_MODE = 1
2317 00:56:33.779144 PICG_EARLY_EN = 1
2318 00:56:33.779211 VALID_LAT_VALUE = 1
2319 00:56:33.779278 ==============================================================
2320 00:56:33.779346 Enter into Gating configuration >>>>
2321 00:56:33.779413 Exit from Gating configuration <<<<
2322 00:56:33.779480 Enter into DVFS_PRE_config >>>>>
2323 00:56:33.779547 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2324 00:56:33.779617 Exit from DVFS_PRE_config <<<<<
2325 00:56:33.779685 Enter into PICG configuration >>>>
2326 00:56:33.779752 Exit from PICG configuration <<<<
2327 00:56:33.779820 [RX_INPUT] configuration >>>>>
2328 00:56:33.779888 [RX_INPUT] configuration <<<<<
2329 00:56:33.779956 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2330 00:56:33.780024 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2331 00:56:33.780091 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2332 00:56:33.780160 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2333 00:56:33.780227 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2334 00:56:33.780295 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2335 00:56:33.780362 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2336 00:56:33.780430 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2337 00:56:33.780497 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2338 00:56:33.780564 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2339 00:56:33.780631 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2340 00:56:33.780699 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2341 00:56:33.780766 ===================================
2342 00:56:33.780834 LPDDR4 DRAM CONFIGURATION
2343 00:56:33.780901 ===================================
2344 00:56:33.780969 EX_ROW_EN[0] = 0x0
2345 00:56:33.781036 EX_ROW_EN[1] = 0x0
2346 00:56:33.781103 LP4Y_EN = 0x0
2347 00:56:33.781170 WORK_FSP = 0x0
2348 00:56:33.781237 WL = 0x4
2349 00:56:33.781304 RL = 0x4
2350 00:56:33.781371 BL = 0x2
2351 00:56:33.781437 RPST = 0x0
2352 00:56:33.781504 RD_PRE = 0x0
2353 00:56:33.781571 WR_PRE = 0x1
2354 00:56:33.781638 WR_PST = 0x0
2355 00:56:33.781704 DBI_WR = 0x0
2356 00:56:33.781771 DBI_RD = 0x0
2357 00:56:33.781837 OTF = 0x1
2358 00:56:33.781904 ===================================
2359 00:56:33.781972 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2360 00:56:33.782039 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2361 00:56:33.782106 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2362 00:56:33.782181 ===================================
2363 00:56:33.782250 LPDDR4 DRAM CONFIGURATION
2364 00:56:33.782318 ===================================
2365 00:56:33.782385 EX_ROW_EN[0] = 0x10
2366 00:56:33.782452 EX_ROW_EN[1] = 0x0
2367 00:56:33.782518 LP4Y_EN = 0x0
2368 00:56:33.782584 WORK_FSP = 0x0
2369 00:56:33.782650 WL = 0x4
2370 00:56:33.782717 RL = 0x4
2371 00:56:33.782782 BL = 0x2
2372 00:56:33.782881 RPST = 0x0
2373 00:56:33.783002 RD_PRE = 0x0
2374 00:56:33.783076 WR_PRE = 0x1
2375 00:56:33.783142 WR_PST = 0x0
2376 00:56:33.783209 DBI_WR = 0x0
2377 00:56:33.783276 DBI_RD = 0x0
2378 00:56:33.783342 OTF = 0x1
2379 00:56:33.783408 ===================================
2380 00:56:33.783476 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2381 00:56:33.783545 ==
2382 00:56:33.783612 Dram Type= 6, Freq= 0, CH_0, rank 0
2383 00:56:33.783679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2384 00:56:33.783747 ==
2385 00:56:33.783814 [Duty_Offset_Calibration]
2386 00:56:33.783881 B0:1 B1:-1 CA:0
2387 00:56:33.783948
2388 00:56:33.784014 [DutyScan_Calibration_Flow] k_type=0
2389 00:56:33.784091
2390 00:56:33.784151 ==CLK 0==
2391 00:56:33.784212 Final CLK duty delay cell = 0
2392 00:56:33.784272 [0] MAX Duty = 5094%(X100), DQS PI = 16
2393 00:56:33.784333 [0] MIN Duty = 4875%(X100), DQS PI = 8
2394 00:56:33.784394 [0] AVG Duty = 4984%(X100)
2395 00:56:33.784455
2396 00:56:33.784515 CH0 CLK Duty spec in!! Max-Min= 219%
2397 00:56:33.784575 [DutyScan_Calibration_Flow] ====Done====
2398 00:56:33.784635
2399 00:56:33.784695 [DutyScan_Calibration_Flow] k_type=1
2400 00:56:33.784762
2401 00:56:33.784823 ==DQS 0 ==
2402 00:56:33.784884 Final DQS duty delay cell = -4
2403 00:56:33.784947 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2404 00:56:33.785208 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2405 00:56:33.785278 [-4] AVG Duty = 4968%(X100)
2406 00:56:33.785340
2407 00:56:33.785401 ==DQS 1 ==
2408 00:56:33.785462 Final DQS duty delay cell = 0
2409 00:56:33.785523 [0] MAX Duty = 5124%(X100), DQS PI = 4
2410 00:56:33.785584 [0] MIN Duty = 5000%(X100), DQS PI = 22
2411 00:56:33.785645 [0] AVG Duty = 5062%(X100)
2412 00:56:33.785705
2413 00:56:33.785765 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2414 00:56:33.785826
2415 00:56:33.785886 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2416 00:56:33.785947 [DutyScan_Calibration_Flow] ====Done====
2417 00:56:33.786007
2418 00:56:33.786067 [DutyScan_Calibration_Flow] k_type=3
2419 00:56:33.786128
2420 00:56:33.786199 ==DQM 0 ==
2421 00:56:33.786261 Final DQM duty delay cell = 0
2422 00:56:33.786324 [0] MAX Duty = 5062%(X100), DQS PI = 22
2423 00:56:33.786384 [0] MIN Duty = 4875%(X100), DQS PI = 8
2424 00:56:33.786445 [0] AVG Duty = 4968%(X100)
2425 00:56:33.786505
2426 00:56:33.786565 ==DQM 1 ==
2427 00:56:33.786626 Final DQM duty delay cell = 4
2428 00:56:33.786686 [4] MAX Duty = 5187%(X100), DQS PI = 56
2429 00:56:33.786757 [4] MIN Duty = 4969%(X100), DQS PI = 24
2430 00:56:33.786865 [4] AVG Duty = 5078%(X100)
2431 00:56:33.786933
2432 00:56:33.786994 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2433 00:56:33.787056
2434 00:56:33.787117 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2435 00:56:33.787178 [DutyScan_Calibration_Flow] ====Done====
2436 00:56:33.787239
2437 00:56:33.787299 [DutyScan_Calibration_Flow] k_type=2
2438 00:56:33.787360
2439 00:56:33.787420 ==DQ 0 ==
2440 00:56:33.787480 Final DQ duty delay cell = -4
2441 00:56:33.787542 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2442 00:56:33.787603 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2443 00:56:33.787663 [-4] AVG Duty = 4969%(X100)
2444 00:56:33.787723
2445 00:56:33.787784 ==DQ 1 ==
2446 00:56:33.787845 Final DQ duty delay cell = -4
2447 00:56:33.787905 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2448 00:56:33.787965 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2449 00:56:33.788025 [-4] AVG Duty = 4922%(X100)
2450 00:56:33.788085
2451 00:56:33.788144 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2452 00:56:33.788204
2453 00:56:33.788263 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2454 00:56:33.788324 [DutyScan_Calibration_Flow] ====Done====
2455 00:56:33.788383 ==
2456 00:56:33.788444 Dram Type= 6, Freq= 0, CH_1, rank 0
2457 00:56:33.788504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2458 00:56:33.788565 ==
2459 00:56:33.788625 [Duty_Offset_Calibration]
2460 00:56:33.788684 B0:-1 B1:1 CA:2
2461 00:56:33.788744
2462 00:56:33.788803 [DutyScan_Calibration_Flow] k_type=0
2463 00:56:33.788863
2464 00:56:33.788923 ==CLK 0==
2465 00:56:33.788983 Final CLK duty delay cell = 0
2466 00:56:33.789044 [0] MAX Duty = 5156%(X100), DQS PI = 22
2467 00:56:33.789113 [0] MIN Duty = 4969%(X100), DQS PI = 62
2468 00:56:33.789168 [0] AVG Duty = 5062%(X100)
2469 00:56:33.789222
2470 00:56:33.789276 CH1 CLK Duty spec in!! Max-Min= 187%
2471 00:56:33.789331 [DutyScan_Calibration_Flow] ====Done====
2472 00:56:33.789386
2473 00:56:33.789440 [DutyScan_Calibration_Flow] k_type=1
2474 00:56:33.789498
2475 00:56:33.789552 ==DQS 0 ==
2476 00:56:33.789607 Final DQS duty delay cell = 0
2477 00:56:33.789662 [0] MAX Duty = 5125%(X100), DQS PI = 48
2478 00:56:33.789717 [0] MIN Duty = 4875%(X100), DQS PI = 6
2479 00:56:33.789771 [0] AVG Duty = 5000%(X100)
2480 00:56:33.789826
2481 00:56:33.789880 ==DQS 1 ==
2482 00:56:33.789935 Final DQS duty delay cell = 0
2483 00:56:33.789990 [0] MAX Duty = 5062%(X100), DQS PI = 12
2484 00:56:33.790045 [0] MIN Duty = 4969%(X100), DQS PI = 56
2485 00:56:33.790099 [0] AVG Duty = 5015%(X100)
2486 00:56:33.790154
2487 00:56:33.790218 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2488 00:56:33.790275
2489 00:56:33.790330 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2490 00:56:33.790385 [DutyScan_Calibration_Flow] ====Done====
2491 00:56:33.790440
2492 00:56:33.790495 [DutyScan_Calibration_Flow] k_type=3
2493 00:56:33.790550
2494 00:56:33.790604 ==DQM 0 ==
2495 00:56:33.790660 Final DQM duty delay cell = -4
2496 00:56:33.790715 [-4] MAX Duty = 5031%(X100), DQS PI = 36
2497 00:56:33.790771 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2498 00:56:33.790825 [-4] AVG Duty = 4937%(X100)
2499 00:56:33.790880
2500 00:56:33.790934 ==DQM 1 ==
2501 00:56:33.790989 Final DQM duty delay cell = 0
2502 00:56:33.791044 [0] MAX Duty = 5156%(X100), DQS PI = 4
2503 00:56:33.791099 [0] MIN Duty = 4969%(X100), DQS PI = 28
2504 00:56:33.791154 [0] AVG Duty = 5062%(X100)
2505 00:56:33.791209
2506 00:56:33.791263 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2507 00:56:33.791317
2508 00:56:33.791372 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2509 00:56:33.791427 [DutyScan_Calibration_Flow] ====Done====
2510 00:56:33.791482
2511 00:56:33.791535 [DutyScan_Calibration_Flow] k_type=2
2512 00:56:33.791590
2513 00:56:33.791645 ==DQ 0 ==
2514 00:56:33.791701 Final DQ duty delay cell = 0
2515 00:56:33.791756 [0] MAX Duty = 5187%(X100), DQS PI = 30
2516 00:56:33.791811 [0] MIN Duty = 4907%(X100), DQS PI = 6
2517 00:56:33.791866 [0] AVG Duty = 5047%(X100)
2518 00:56:33.791920
2519 00:56:33.791975 ==DQ 1 ==
2520 00:56:33.792029 Final DQ duty delay cell = 0
2521 00:56:33.792084 [0] MAX Duty = 5124%(X100), DQS PI = 10
2522 00:56:33.792139 [0] MIN Duty = 4969%(X100), DQS PI = 34
2523 00:56:33.792194 [0] AVG Duty = 5046%(X100)
2524 00:56:33.792249
2525 00:56:33.792303 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2526 00:56:33.792358
2527 00:56:33.792413 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2528 00:56:33.792468 [DutyScan_Calibration_Flow] ====Done====
2529 00:56:33.792523 nWR fixed to 30
2530 00:56:33.792579 [ModeRegInit_LP4] CH0 RK0
2531 00:56:33.792634 [ModeRegInit_LP4] CH0 RK1
2532 00:56:33.792688 [ModeRegInit_LP4] CH1 RK0
2533 00:56:33.792743 [ModeRegInit_LP4] CH1 RK1
2534 00:56:33.792797 match AC timing 7
2535 00:56:33.792852 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2536 00:56:33.792945 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2537 00:56:33.793027 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2538 00:56:33.793085 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2539 00:56:33.793141 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2540 00:56:33.793196 ==
2541 00:56:33.793252 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 00:56:33.793308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 00:56:33.793362 ==
2544 00:56:33.793418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2545 00:56:33.793473 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2546 00:56:33.793529 [CA 0] Center 39 (9~70) winsize 62
2547 00:56:33.793584 [CA 1] Center 39 (9~69) winsize 61
2548 00:56:33.793639 [CA 2] Center 35 (5~66) winsize 62
2549 00:56:33.793694 [CA 3] Center 35 (4~66) winsize 63
2550 00:56:33.793750 [CA 4] Center 33 (4~63) winsize 60
2551 00:56:33.793804 [CA 5] Center 33 (3~63) winsize 61
2552 00:56:33.793860
2553 00:56:33.793915 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2554 00:56:33.793971
2555 00:56:33.794025 [CATrainingPosCal] consider 1 rank data
2556 00:56:33.794080 u2DelayCellTimex100 = 270/100 ps
2557 00:56:33.794346 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2558 00:56:33.794409 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2559 00:56:33.794465 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2560 00:56:33.794521 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2561 00:56:33.794575 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2562 00:56:33.794629 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2563 00:56:33.794683
2564 00:56:33.794737 CA PerBit enable=1, Macro0, CA PI delay=33
2565 00:56:33.794791
2566 00:56:33.794855 [CBTSetCACLKResult] CA Dly = 33
2567 00:56:33.794909 CS Dly: 8 (0~39)
2568 00:56:33.794963 ==
2569 00:56:33.795018 Dram Type= 6, Freq= 0, CH_0, rank 1
2570 00:56:33.795072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 00:56:33.795126 ==
2572 00:56:33.795180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2573 00:56:33.795235 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2574 00:56:33.795289 [CA 0] Center 39 (8~70) winsize 63
2575 00:56:33.795342 [CA 1] Center 39 (9~70) winsize 62
2576 00:56:33.795396 [CA 2] Center 35 (5~66) winsize 62
2577 00:56:33.795450 [CA 3] Center 34 (4~65) winsize 62
2578 00:56:33.795504 [CA 4] Center 33 (3~64) winsize 62
2579 00:56:33.795558 [CA 5] Center 33 (3~63) winsize 61
2580 00:56:33.795611
2581 00:56:33.795665 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2582 00:56:33.795719
2583 00:56:33.795772 [CATrainingPosCal] consider 2 rank data
2584 00:56:33.795826 u2DelayCellTimex100 = 270/100 ps
2585 00:56:33.795880 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2586 00:56:33.795934 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2587 00:56:33.795988 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2588 00:56:33.796042 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2589 00:56:33.796096 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2590 00:56:33.796149 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2591 00:56:33.796203
2592 00:56:33.796256 CA PerBit enable=1, Macro0, CA PI delay=33
2593 00:56:33.796310
2594 00:56:33.796364 [CBTSetCACLKResult] CA Dly = 33
2595 00:56:33.796418 CS Dly: 9 (0~41)
2596 00:56:33.796471
2597 00:56:33.796524 ----->DramcWriteLeveling(PI) begin...
2598 00:56:33.796579 ==
2599 00:56:33.796633 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 00:56:33.796687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 00:56:33.796742 ==
2602 00:56:33.796796 Write leveling (Byte 0): 32 => 32
2603 00:56:33.796850 Write leveling (Byte 1): 29 => 29
2604 00:56:33.796903 DramcWriteLeveling(PI) end<-----
2605 00:56:33.796975
2606 00:56:33.797067 ==
2607 00:56:33.797128 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 00:56:33.797184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 00:56:33.797240 ==
2610 00:56:33.797294 [Gating] SW mode calibration
2611 00:56:33.797348 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2612 00:56:33.797404 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2613 00:56:33.797458 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2614 00:56:33.797513 0 15 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2615 00:56:33.797567 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2616 00:56:33.797621 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2617 00:56:33.797674 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2618 00:56:33.797728 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2619 00:56:33.797782 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2620 00:56:33.797836 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2621 00:56:33.797889 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2622 00:56:33.797943 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2623 00:56:33.797997 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2624 00:56:33.798051 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2625 00:56:33.798104 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2626 00:56:33.798158 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2627 00:56:33.798261 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2628 00:56:33.798315 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
2629 00:56:33.798368 1 1 0 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2630 00:56:33.798422 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2631 00:56:33.798476 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 00:56:33.798530 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 00:56:33.798600 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2634 00:56:33.798656 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 00:56:33.798710 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2636 00:56:33.798764 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2637 00:56:33.798817 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2638 00:56:33.798871 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 00:56:33.798924 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 00:56:33.798979 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 00:56:33.799032 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 00:56:33.799086 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 00:56:33.799140 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 00:56:33.799194 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 00:56:33.799248 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 00:56:33.799302 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 00:56:33.799355 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 00:56:33.799410 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 00:56:33.799464 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 00:56:33.799517 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2651 00:56:33.799571 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2652 00:56:33.799625 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2653 00:56:33.799678 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2654 00:56:33.799732 Total UI for P1: 0, mck2ui 16
2655 00:56:33.799787 best dqsien dly found for B0: ( 1, 3, 26)
2656 00:56:33.799841 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2657 00:56:33.799895 Total UI for P1: 0, mck2ui 16
2658 00:56:33.799949 best dqsien dly found for B1: ( 1, 4, 0)
2659 00:56:33.800007 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2660 00:56:33.800263 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2661 00:56:33.800325
2662 00:56:33.800380 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2663 00:56:33.800435 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2664 00:56:33.800489 [Gating] SW calibration Done
2665 00:56:33.800543 ==
2666 00:56:33.800598 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 00:56:33.800653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 00:56:33.800707 ==
2669 00:56:33.800761 RX Vref Scan: 0
2670 00:56:33.800815
2671 00:56:33.800869 RX Vref 0 -> 0, step: 1
2672 00:56:33.800923
2673 00:56:33.800975 RX Delay -40 -> 252, step: 8
2674 00:56:33.801029 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2675 00:56:33.801083 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2676 00:56:33.801137 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2677 00:56:33.801190 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2678 00:56:33.801244 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2679 00:56:33.801298 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2680 00:56:33.801352 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2681 00:56:33.801406 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2682 00:56:33.801460 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2683 00:56:33.801514 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2684 00:56:33.801568 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2685 00:56:33.801621 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2686 00:56:33.801674 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2687 00:56:33.801728 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2688 00:56:33.801781 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2689 00:56:33.801834 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2690 00:56:33.801887 ==
2691 00:56:33.801940 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 00:56:33.801994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 00:56:33.802050 ==
2694 00:56:33.802138 DQS Delay:
2695 00:56:33.802249 DQS0 = 0, DQS1 = 0
2696 00:56:33.802305 DQM Delay:
2697 00:56:33.802359 DQM0 = 119, DQM1 = 107
2698 00:56:33.802413 DQ Delay:
2699 00:56:33.802467 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2700 00:56:33.802521 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2701 00:56:33.802575 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2702 00:56:33.802629 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2703 00:56:33.802682
2704 00:56:33.802736
2705 00:56:33.802789 ==
2706 00:56:33.802842 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 00:56:33.802896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 00:56:33.802950 ==
2709 00:56:33.803003
2710 00:56:33.803056
2711 00:56:33.803108 TX Vref Scan disable
2712 00:56:33.803162 == TX Byte 0 ==
2713 00:56:33.803216 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2714 00:56:33.803270 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2715 00:56:33.803324 == TX Byte 1 ==
2716 00:56:33.803378 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2717 00:56:33.803432 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2718 00:56:33.803485 ==
2719 00:56:33.803538 Dram Type= 6, Freq= 0, CH_0, rank 0
2720 00:56:33.803594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2721 00:56:33.803648 ==
2722 00:56:33.803702 TX Vref=22, minBit 1, minWin=25, winSum=415
2723 00:56:33.803756 TX Vref=24, minBit 13, minWin=25, winSum=420
2724 00:56:33.803811 TX Vref=26, minBit 4, minWin=26, winSum=425
2725 00:56:33.803865 TX Vref=28, minBit 4, minWin=26, winSum=430
2726 00:56:33.803919 TX Vref=30, minBit 4, minWin=26, winSum=431
2727 00:56:33.804010 TX Vref=32, minBit 1, minWin=26, winSum=428
2728 00:56:33.804099 [TxChooseVref] Worse bit 4, Min win 26, Win sum 431, Final Vref 30
2729 00:56:33.804191
2730 00:56:33.804264 Final TX Range 1 Vref 30
2731 00:56:33.804320
2732 00:56:33.804375 ==
2733 00:56:33.804428 Dram Type= 6, Freq= 0, CH_0, rank 0
2734 00:56:33.804483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2735 00:56:33.804537 ==
2736 00:56:33.804591
2737 00:56:33.804644
2738 00:56:33.804698 TX Vref Scan disable
2739 00:56:33.804752 == TX Byte 0 ==
2740 00:56:33.804806 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2741 00:56:33.804860 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2742 00:56:33.804932 == TX Byte 1 ==
2743 00:56:33.804989 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2744 00:56:33.805044 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2745 00:56:33.805098
2746 00:56:33.805152 [DATLAT]
2747 00:56:33.805205 Freq=1200, CH0 RK0
2748 00:56:33.805259
2749 00:56:33.805312 DATLAT Default: 0xd
2750 00:56:33.805366 0, 0xFFFF, sum = 0
2751 00:56:33.805422 1, 0xFFFF, sum = 0
2752 00:56:33.805477 2, 0xFFFF, sum = 0
2753 00:56:33.805532 3, 0xFFFF, sum = 0
2754 00:56:33.805587 4, 0xFFFF, sum = 0
2755 00:56:33.805641 5, 0xFFFF, sum = 0
2756 00:56:33.805696 6, 0xFFFF, sum = 0
2757 00:56:33.805750 7, 0xFFFF, sum = 0
2758 00:56:33.805804 8, 0xFFFF, sum = 0
2759 00:56:33.805858 9, 0xFFFF, sum = 0
2760 00:56:33.805912 10, 0xFFFF, sum = 0
2761 00:56:33.805966 11, 0xFFFF, sum = 0
2762 00:56:33.806022 12, 0x0, sum = 1
2763 00:56:33.806076 13, 0x0, sum = 2
2764 00:56:33.806131 14, 0x0, sum = 3
2765 00:56:33.806233 15, 0x0, sum = 4
2766 00:56:33.806303 best_step = 13
2767 00:56:33.806356
2768 00:56:33.806410 ==
2769 00:56:33.806464 Dram Type= 6, Freq= 0, CH_0, rank 0
2770 00:56:33.806519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2771 00:56:33.806574 ==
2772 00:56:33.806628 RX Vref Scan: 1
2773 00:56:33.806682
2774 00:56:33.806736 Set Vref Range= 32 -> 127
2775 00:56:33.806790
2776 00:56:33.806844 RX Vref 32 -> 127, step: 1
2777 00:56:33.806898
2778 00:56:33.806951 RX Delay -21 -> 252, step: 4
2779 00:56:33.807005
2780 00:56:33.807059 Set Vref, RX VrefLevel [Byte0]: 32
2781 00:56:33.807113 [Byte1]: 32
2782 00:56:33.807167
2783 00:56:33.807220 Set Vref, RX VrefLevel [Byte0]: 33
2784 00:56:33.807273 [Byte1]: 33
2785 00:56:33.807327
2786 00:56:33.807381 Set Vref, RX VrefLevel [Byte0]: 34
2787 00:56:33.807434 [Byte1]: 34
2788 00:56:33.807487
2789 00:56:33.807540 Set Vref, RX VrefLevel [Byte0]: 35
2790 00:56:33.807594 [Byte1]: 35
2791 00:56:33.807648
2792 00:56:33.807701 Set Vref, RX VrefLevel [Byte0]: 36
2793 00:56:33.807755 [Byte1]: 36
2794 00:56:33.807809
2795 00:56:33.807862 Set Vref, RX VrefLevel [Byte0]: 37
2796 00:56:33.807915 [Byte1]: 37
2797 00:56:33.807969
2798 00:56:33.808021 Set Vref, RX VrefLevel [Byte0]: 38
2799 00:56:33.808075 [Byte1]: 38
2800 00:56:33.808128
2801 00:56:33.808180 Set Vref, RX VrefLevel [Byte0]: 39
2802 00:56:33.808234 [Byte1]: 39
2803 00:56:33.808287
2804 00:56:33.808340 Set Vref, RX VrefLevel [Byte0]: 40
2805 00:56:33.808393 [Byte1]: 40
2806 00:56:33.808481
2807 00:56:33.808577 Set Vref, RX VrefLevel [Byte0]: 41
2808 00:56:33.808639 [Byte1]: 41
2809 00:56:33.808693
2810 00:56:33.808748 Set Vref, RX VrefLevel [Byte0]: 42
2811 00:56:33.808803 [Byte1]: 42
2812 00:56:33.808857
2813 00:56:33.808910 Set Vref, RX VrefLevel [Byte0]: 43
2814 00:56:33.808964 [Byte1]: 43
2815 00:56:33.809018
2816 00:56:33.809266 Set Vref, RX VrefLevel [Byte0]: 44
2817 00:56:33.809328 [Byte1]: 44
2818 00:56:33.809384
2819 00:56:33.809439 Set Vref, RX VrefLevel [Byte0]: 45
2820 00:56:33.809494 [Byte1]: 45
2821 00:56:33.809548
2822 00:56:33.809602 Set Vref, RX VrefLevel [Byte0]: 46
2823 00:56:33.809656 [Byte1]: 46
2824 00:56:33.809710
2825 00:56:33.809783 Set Vref, RX VrefLevel [Byte0]: 47
2826 00:56:33.809868 [Byte1]: 47
2827 00:56:33.809956
2828 00:56:33.810041 Set Vref, RX VrefLevel [Byte0]: 48
2829 00:56:33.810124 [Byte1]: 48
2830 00:56:33.810267
2831 00:56:33.810363 Set Vref, RX VrefLevel [Byte0]: 49
2832 00:56:33.810448 [Byte1]: 49
2833 00:56:33.810531
2834 00:56:33.810614 Set Vref, RX VrefLevel [Byte0]: 50
2835 00:56:33.810698 [Byte1]: 50
2836 00:56:33.810780
2837 00:56:33.810863 Set Vref, RX VrefLevel [Byte0]: 51
2838 00:56:33.810947 [Byte1]: 51
2839 00:56:33.811029
2840 00:56:33.811112 Set Vref, RX VrefLevel [Byte0]: 52
2841 00:56:33.811195 [Byte1]: 52
2842 00:56:33.811277
2843 00:56:33.811360 Set Vref, RX VrefLevel [Byte0]: 53
2844 00:56:33.811443 [Byte1]: 53
2845 00:56:33.811525
2846 00:56:33.811608 Set Vref, RX VrefLevel [Byte0]: 54
2847 00:56:33.811691 [Byte1]: 54
2848 00:56:33.811774
2849 00:56:33.811857 Set Vref, RX VrefLevel [Byte0]: 55
2850 00:56:33.811940 [Byte1]: 55
2851 00:56:33.812022
2852 00:56:33.812105 Set Vref, RX VrefLevel [Byte0]: 56
2853 00:56:33.812188 [Byte1]: 56
2854 00:56:33.812270
2855 00:56:33.812353 Set Vref, RX VrefLevel [Byte0]: 57
2856 00:56:33.812435 [Byte1]: 57
2857 00:56:33.812517
2858 00:56:33.812600 Set Vref, RX VrefLevel [Byte0]: 58
2859 00:56:33.812683 [Byte1]: 58
2860 00:56:33.812765
2861 00:56:33.812848 Set Vref, RX VrefLevel [Byte0]: 59
2862 00:56:33.812931 [Byte1]: 59
2863 00:56:33.813013
2864 00:56:33.813095 Set Vref, RX VrefLevel [Byte0]: 60
2865 00:56:33.813178 [Byte1]: 60
2866 00:56:33.813261
2867 00:56:33.813343 Set Vref, RX VrefLevel [Byte0]: 61
2868 00:56:33.813426 [Byte1]: 61
2869 00:56:33.813508
2870 00:56:33.813591 Set Vref, RX VrefLevel [Byte0]: 62
2871 00:56:33.813674 [Byte1]: 62
2872 00:56:33.813756
2873 00:56:33.813838 Set Vref, RX VrefLevel [Byte0]: 63
2874 00:56:33.813922 [Byte1]: 63
2875 00:56:33.814004
2876 00:56:33.814086 Set Vref, RX VrefLevel [Byte0]: 64
2877 00:56:33.814174 [Byte1]: 64
2878 00:56:33.814269
2879 00:56:33.814323 Set Vref, RX VrefLevel [Byte0]: 65
2880 00:56:33.814377 [Byte1]: 65
2881 00:56:33.814431
2882 00:56:33.814484 Set Vref, RX VrefLevel [Byte0]: 66
2883 00:56:33.814538 [Byte1]: 66
2884 00:56:33.814592
2885 00:56:33.814645 Set Vref, RX VrefLevel [Byte0]: 67
2886 00:56:33.814698 [Byte1]: 67
2887 00:56:33.814752
2888 00:56:33.814805 Set Vref, RX VrefLevel [Byte0]: 68
2889 00:56:33.814858 [Byte1]: 68
2890 00:56:33.814912
2891 00:56:33.814966 Set Vref, RX VrefLevel [Byte0]: 69
2892 00:56:33.815019 [Byte1]: 69
2893 00:56:33.815072
2894 00:56:33.815125 Set Vref, RX VrefLevel [Byte0]: 70
2895 00:56:33.815179 [Byte1]: 70
2896 00:56:33.815232
2897 00:56:33.815286 Set Vref, RX VrefLevel [Byte0]: 71
2898 00:56:33.815339 [Byte1]: 71
2899 00:56:33.815392
2900 00:56:33.815446 Set Vref, RX VrefLevel [Byte0]: 72
2901 00:56:33.815499 [Byte1]: 72
2902 00:56:33.815552
2903 00:56:33.815605 Set Vref, RX VrefLevel [Byte0]: 73
2904 00:56:33.815659 [Byte1]: 73
2905 00:56:33.815712
2906 00:56:33.815765 Set Vref, RX VrefLevel [Byte0]: 74
2907 00:56:33.815818 [Byte1]: 74
2908 00:56:33.815872
2909 00:56:33.815926 Set Vref, RX VrefLevel [Byte0]: 75
2910 00:56:33.815979 [Byte1]: 75
2911 00:56:33.816032
2912 00:56:33.816085 Set Vref, RX VrefLevel [Byte0]: 76
2913 00:56:33.816139 [Byte1]: 76
2914 00:56:33.816192
2915 00:56:33.816245 Set Vref, RX VrefLevel [Byte0]: 77
2916 00:56:33.816299 [Byte1]: 77
2917 00:56:33.816352
2918 00:56:33.816406 Set Vref, RX VrefLevel [Byte0]: 78
2919 00:56:33.816460 [Byte1]: 78
2920 00:56:33.816514
2921 00:56:33.816567 Final RX Vref Byte 0 = 59 to rank0
2922 00:56:33.816621 Final RX Vref Byte 1 = 58 to rank0
2923 00:56:33.816675 Final RX Vref Byte 0 = 59 to rank1
2924 00:56:33.816729 Final RX Vref Byte 1 = 58 to rank1==
2925 00:56:33.816788 Dram Type= 6, Freq= 0, CH_0, rank 0
2926 00:56:33.816843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 00:56:33.816902 ==
2928 00:56:33.816957 DQS Delay:
2929 00:56:33.817011 DQS0 = 0, DQS1 = 0
2930 00:56:33.817065 DQM Delay:
2931 00:56:33.817118 DQM0 = 119, DQM1 = 108
2932 00:56:33.817172 DQ Delay:
2933 00:56:33.817226 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2934 00:56:33.817280 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =126
2935 00:56:33.817334 DQ8 =96, DQ9 =96, DQ10 =110, DQ11 =104
2936 00:56:33.817388 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2937 00:56:33.817441
2938 00:56:33.817495
2939 00:56:33.817548 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2940 00:56:33.817603 CH0 RK0: MR19=403, MR18=11FD
2941 00:56:33.817656 CH0_RK0: MR19=0x403, MR18=0x11FD, DQSOSC=403, MR23=63, INC=40, DEC=26
2942 00:56:33.817711
2943 00:56:33.817764 ----->DramcWriteLeveling(PI) begin...
2944 00:56:33.817820 ==
2945 00:56:33.817874 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 00:56:33.817928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 00:56:33.817983 ==
2948 00:56:33.818036 Write leveling (Byte 0): 33 => 33
2949 00:56:33.818121 Write leveling (Byte 1): 31 => 31
2950 00:56:33.818201 DramcWriteLeveling(PI) end<-----
2951 00:56:33.818293
2952 00:56:33.818347 ==
2953 00:56:33.818402 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 00:56:33.818456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 00:56:33.818511 ==
2956 00:56:33.818564 [Gating] SW mode calibration
2957 00:56:33.818618 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2958 00:56:33.818673 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2959 00:56:33.818726 0 15 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
2960 00:56:33.818780 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2961 00:56:33.818834 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2962 00:56:33.818888 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2963 00:56:33.818942 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2964 00:56:33.819190 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2965 00:56:33.819283 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2966 00:56:33.819391 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
2967 00:56:33.819499 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2968 00:56:33.819607 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2969 00:56:33.819699 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2970 00:56:33.819785 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 00:56:33.819870 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 00:56:33.819954 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 00:56:33.820038 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 00:56:33.820121 1 0 28 | B1->B0 | 2423 3030 | 1 0 | (0 0) (1 1)
2975 00:56:33.820205 1 1 0 | B1->B0 | 3736 4646 | 1 0 | (0 0) (0 0)
2976 00:56:33.820288 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 00:56:33.820375 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 00:56:33.820461 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 00:56:33.820546 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 00:56:33.820630 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 00:56:33.820714 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2982 00:56:33.820797 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2983 00:56:33.820880 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2984 00:56:33.820964 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 00:56:33.821047 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 00:56:33.821130 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 00:56:33.821213 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 00:56:33.821297 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 00:56:33.821380 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 00:56:33.821466 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 00:56:33.821549 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 00:56:33.821635 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 00:56:33.821728 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 00:56:33.821830 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 00:56:33.821922 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 00:56:33.822007 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 00:56:33.822091 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 00:56:33.822180 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2999 00:56:33.822276 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3000 00:56:33.822331 Total UI for P1: 0, mck2ui 16
3001 00:56:33.822387 best dqsien dly found for B0: ( 1, 3, 28)
3002 00:56:33.822442 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3003 00:56:33.822496 Total UI for P1: 0, mck2ui 16
3004 00:56:33.954090 best dqsien dly found for B1: ( 1, 4, 0)
3005 00:56:33.954654 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3006 00:56:33.955035 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3007 00:56:33.955385
3008 00:56:33.955724 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3009 00:56:33.956055 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3010 00:56:33.956380 [Gating] SW calibration Done
3011 00:56:33.956704 ==
3012 00:56:33.957021 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 00:56:33.957336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 00:56:33.957652 ==
3015 00:56:33.957963 RX Vref Scan: 0
3016 00:56:33.958303
3017 00:56:33.958619 RX Vref 0 -> 0, step: 1
3018 00:56:33.959000
3019 00:56:33.959517 RX Delay -40 -> 252, step: 8
3020 00:56:33.960100 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3021 00:56:33.960514 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3022 00:56:33.960844 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3023 00:56:33.961157 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3024 00:56:33.961469 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3025 00:56:33.961775 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3026 00:56:33.962083 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3027 00:56:33.962575 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
3028 00:56:33.962907 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3029 00:56:33.963219 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3030 00:56:33.963532 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3031 00:56:33.963839 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3032 00:56:33.964147 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3033 00:56:33.964454 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3034 00:56:33.964778 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3035 00:56:33.965083 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3036 00:56:33.965389 ==
3037 00:56:33.965694 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 00:56:33.966004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 00:56:33.966359 ==
3040 00:56:33.966672 DQS Delay:
3041 00:56:33.966974 DQS0 = 0, DQS1 = 0
3042 00:56:33.967279 DQM Delay:
3043 00:56:33.967584 DQM0 = 117, DQM1 = 108
3044 00:56:33.967890 DQ Delay:
3045 00:56:33.968195 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3046 00:56:33.968504 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
3047 00:56:33.968811 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3048 00:56:33.969134 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
3049 00:56:33.969445
3050 00:56:33.969749
3051 00:56:33.970052 ==
3052 00:56:33.970382 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 00:56:33.970691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 00:56:33.970999 ==
3055 00:56:33.971302
3056 00:56:33.971604
3057 00:56:33.971905 TX Vref Scan disable
3058 00:56:33.972211 == TX Byte 0 ==
3059 00:56:33.972514 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3060 00:56:33.972887 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3061 00:56:33.973197 == TX Byte 1 ==
3062 00:56:33.973504 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3063 00:56:33.973808 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3064 00:56:33.974111 ==
3065 00:56:33.974470 Dram Type= 6, Freq= 0, CH_0, rank 1
3066 00:56:33.974844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 00:56:33.975159 ==
3068 00:56:33.975464 TX Vref=22, minBit 11, minWin=25, winSum=418
3069 00:56:33.975772 TX Vref=24, minBit 1, minWin=26, winSum=423
3070 00:56:33.976094 TX Vref=26, minBit 13, minWin=25, winSum=425
3071 00:56:33.976766 TX Vref=28, minBit 13, minWin=25, winSum=431
3072 00:56:33.977086 TX Vref=30, minBit 1, minWin=27, winSum=437
3073 00:56:33.977377 TX Vref=32, minBit 2, minWin=26, winSum=428
3074 00:56:33.977665 [TxChooseVref] Worse bit 1, Min win 27, Win sum 437, Final Vref 30
3075 00:56:33.977944
3076 00:56:33.978260 Final TX Range 1 Vref 30
3077 00:56:33.978551
3078 00:56:33.978828 ==
3079 00:56:33.979114 Dram Type= 6, Freq= 0, CH_0, rank 1
3080 00:56:33.979317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 00:56:33.979518 ==
3082 00:56:33.979718
3083 00:56:33.979913
3084 00:56:33.980110 TX Vref Scan disable
3085 00:56:33.980309 == TX Byte 0 ==
3086 00:56:33.980508 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3087 00:56:33.980709 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3088 00:56:33.980909 == TX Byte 1 ==
3089 00:56:33.981108 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3090 00:56:33.981308 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3091 00:56:33.981509
3092 00:56:33.981708 [DATLAT]
3093 00:56:33.981906 Freq=1200, CH0 RK1
3094 00:56:33.982106
3095 00:56:33.982344 DATLAT Default: 0xd
3096 00:56:33.982546 0, 0xFFFF, sum = 0
3097 00:56:33.982751 1, 0xFFFF, sum = 0
3098 00:56:33.982953 2, 0xFFFF, sum = 0
3099 00:56:33.983155 3, 0xFFFF, sum = 0
3100 00:56:33.983449 4, 0xFFFF, sum = 0
3101 00:56:33.983754 5, 0xFFFF, sum = 0
3102 00:56:33.983966 6, 0xFFFF, sum = 0
3103 00:56:33.984159 7, 0xFFFF, sum = 0
3104 00:56:33.984311 8, 0xFFFF, sum = 0
3105 00:56:33.984463 9, 0xFFFF, sum = 0
3106 00:56:33.984614 10, 0xFFFF, sum = 0
3107 00:56:33.984768 11, 0xFFFF, sum = 0
3108 00:56:33.984920 12, 0x0, sum = 1
3109 00:56:33.985073 13, 0x0, sum = 2
3110 00:56:33.985228 14, 0x0, sum = 3
3111 00:56:33.985380 15, 0x0, sum = 4
3112 00:56:33.985533 best_step = 13
3113 00:56:33.985682
3114 00:56:33.985887 ==
3115 00:56:33.986189 Dram Type= 6, Freq= 0, CH_0, rank 1
3116 00:56:33.986386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 00:56:33.986547 ==
3118 00:56:33.986704 RX Vref Scan: 0
3119 00:56:33.986857
3120 00:56:33.987009 RX Vref 0 -> 0, step: 1
3121 00:56:33.987159
3122 00:56:33.987311 RX Delay -21 -> 252, step: 4
3123 00:56:33.987463 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3124 00:56:33.987617 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3125 00:56:33.987769 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3126 00:56:33.987922 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3127 00:56:33.988073 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3128 00:56:33.988225 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3129 00:56:33.988376 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3130 00:56:33.988529 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3131 00:56:33.988680 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3132 00:56:33.988832 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3133 00:56:33.988982 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3134 00:56:33.989140 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3135 00:56:33.989260 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3136 00:56:33.989381 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3137 00:56:33.989502 iDelay=199, Bit 14, Center 122 (59 ~ 186) 128
3138 00:56:33.989716 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3139 00:56:33.989940 ==
3140 00:56:33.990157 Dram Type= 6, Freq= 0, CH_0, rank 1
3141 00:56:33.990309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 00:56:33.990437 ==
3143 00:56:33.990562 DQS Delay:
3144 00:56:33.990685 DQS0 = 0, DQS1 = 0
3145 00:56:33.990808 DQM Delay:
3146 00:56:33.990929 DQM0 = 116, DQM1 = 109
3147 00:56:33.991051 DQ Delay:
3148 00:56:33.991172 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3149 00:56:33.991295 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3150 00:56:33.991417 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3151 00:56:33.991538 DQ12 =116, DQ13 =114, DQ14 =122, DQ15 =116
3152 00:56:33.991658
3153 00:56:33.991779
3154 00:56:33.991901 [DQSOSCAuto] RK1, (LSB)MR18= 0xde8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3155 00:56:33.992024 CH0 RK1: MR19=403, MR18=DE8
3156 00:56:33.992146 CH0_RK1: MR19=0x403, MR18=0xDE8, DQSOSC=405, MR23=63, INC=39, DEC=26
3157 00:56:33.992269 [RxdqsGatingPostProcess] freq 1200
3158 00:56:33.992391 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3159 00:56:33.992512 best DQS0 dly(2T, 0.5T) = (0, 11)
3160 00:56:33.992631 best DQS1 dly(2T, 0.5T) = (0, 12)
3161 00:56:33.992751 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3162 00:56:33.992872 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3163 00:56:33.992992 best DQS0 dly(2T, 0.5T) = (0, 11)
3164 00:56:33.993130 best DQS1 dly(2T, 0.5T) = (0, 12)
3165 00:56:33.993255 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3166 00:56:33.993377 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3167 00:56:33.993498 Pre-setting of DQS Precalculation
3168 00:56:33.993618 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3169 00:56:33.993740 ==
3170 00:56:33.993861 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 00:56:33.993983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 00:56:33.994115 ==
3173 00:56:33.994233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3174 00:56:33.994339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3175 00:56:33.994441 [CA 0] Center 37 (7~68) winsize 62
3176 00:56:33.994541 [CA 1] Center 37 (7~68) winsize 62
3177 00:56:33.994642 [CA 2] Center 34 (4~64) winsize 61
3178 00:56:33.994744 [CA 3] Center 33 (3~64) winsize 62
3179 00:56:33.994846 [CA 4] Center 34 (4~64) winsize 61
3180 00:56:33.994947 [CA 5] Center 33 (3~64) winsize 62
3181 00:56:33.995047
3182 00:56:33.995149 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3183 00:56:33.995250
3184 00:56:33.995350 [CATrainingPosCal] consider 1 rank data
3185 00:56:33.995451 u2DelayCellTimex100 = 270/100 ps
3186 00:56:33.995552 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3187 00:56:33.995653 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3188 00:56:33.995755 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3189 00:56:33.995856 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3190 00:56:33.995957 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3191 00:56:33.996057 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3192 00:56:33.996158
3193 00:56:33.996258 CA PerBit enable=1, Macro0, CA PI delay=33
3194 00:56:33.996359
3195 00:56:33.996458 [CBTSetCACLKResult] CA Dly = 33
3196 00:56:33.996561 CS Dly: 5 (0~36)
3197 00:56:33.996661 ==
3198 00:56:33.996762 Dram Type= 6, Freq= 0, CH_1, rank 1
3199 00:56:33.996864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 00:56:33.996967 ==
3201 00:56:33.997067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3202 00:56:33.997233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3203 00:56:33.997361 [CA 0] Center 37 (7~68) winsize 62
3204 00:56:33.997465 [CA 1] Center 38 (8~68) winsize 61
3205 00:56:33.997799 [CA 2] Center 34 (4~65) winsize 62
3206 00:56:33.997915 [CA 3] Center 33 (3~64) winsize 62
3207 00:56:33.998020 [CA 4] Center 34 (4~65) winsize 62
3208 00:56:33.998123 [CA 5] Center 33 (3~64) winsize 62
3209 00:56:33.998248
3210 00:56:33.998353 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3211 00:56:33.998456
3212 00:56:33.998559 [CATrainingPosCal] consider 2 rank data
3213 00:56:33.998661 u2DelayCellTimex100 = 270/100 ps
3214 00:56:33.998763 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3215 00:56:33.998865 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3216 00:56:33.998967 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3217 00:56:33.999081 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3218 00:56:33.999169 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3219 00:56:33.999257 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3220 00:56:33.999345
3221 00:56:33.999431 CA PerBit enable=1, Macro0, CA PI delay=33
3222 00:56:33.999519
3223 00:56:33.999604 [CBTSetCACLKResult] CA Dly = 33
3224 00:56:33.999690 CS Dly: 7 (0~40)
3225 00:56:33.999777
3226 00:56:33.999866 ----->DramcWriteLeveling(PI) begin...
3227 00:56:33.999955 ==
3228 00:56:34.000042 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 00:56:34.000129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 00:56:34.000218 ==
3231 00:56:34.000304 Write leveling (Byte 0): 24 => 24
3232 00:56:34.000393 Write leveling (Byte 1): 26 => 26
3233 00:56:34.000480 DramcWriteLeveling(PI) end<-----
3234 00:56:34.000566
3235 00:56:34.000652 ==
3236 00:56:34.000739 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 00:56:34.000826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 00:56:34.000913 ==
3239 00:56:34.001000 [Gating] SW mode calibration
3240 00:56:34.001087 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3241 00:56:34.001176 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3242 00:56:34.001264 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3243 00:56:34.001351 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3244 00:56:34.001439 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3245 00:56:34.001526 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3246 00:56:34.001614 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3247 00:56:34.001700 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3248 00:56:34.001787 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
3249 00:56:34.001874 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (1 0)
3250 00:56:34.001962 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3251 00:56:34.002048 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3252 00:56:34.002136 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3253 00:56:34.002238 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3254 00:56:34.002326 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3255 00:56:34.002412 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3256 00:56:34.002498 1 0 24 | B1->B0 | 2424 3b3b | 0 1 | (0 0) (0 0)
3257 00:56:34.002585 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3258 00:56:34.002671 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3259 00:56:34.002757 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3260 00:56:34.002844 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3261 00:56:34.002931 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3262 00:56:34.003018 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3263 00:56:34.003104 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3264 00:56:34.003190 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3265 00:56:34.003277 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3266 00:56:34.003363 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 00:56:34.003449 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 00:56:34.003536 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 00:56:34.003622 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 00:56:34.003709 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 00:56:34.003795 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 00:56:34.003883 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 00:56:34.003969 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 00:56:34.004056 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 00:56:34.004148 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 00:56:34.004224 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 00:56:34.004300 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 00:56:34.004376 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 00:56:34.004452 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 00:56:34.004528 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3281 00:56:34.004604 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3282 00:56:34.004680 Total UI for P1: 0, mck2ui 16
3283 00:56:34.004756 best dqsien dly found for B0: ( 1, 3, 24)
3284 00:56:34.004833 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3285 00:56:34.004910 Total UI for P1: 0, mck2ui 16
3286 00:56:34.004987 best dqsien dly found for B1: ( 1, 3, 28)
3287 00:56:34.005063 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3288 00:56:34.005139 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3289 00:56:34.005215
3290 00:56:34.005318 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3291 00:56:34.005397 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3292 00:56:34.005475 [Gating] SW calibration Done
3293 00:56:34.005551 ==
3294 00:56:34.005628 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 00:56:34.005704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 00:56:34.005781 ==
3297 00:56:34.005858 RX Vref Scan: 0
3298 00:56:34.005934
3299 00:56:34.006009 RX Vref 0 -> 0, step: 1
3300 00:56:34.006086
3301 00:56:34.006168 RX Delay -40 -> 252, step: 8
3302 00:56:34.006250 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3303 00:56:34.006327 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3304 00:56:34.006405 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3305 00:56:34.006481 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3306 00:56:34.006558 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3307 00:56:34.006634 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3308 00:56:34.006712 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3309 00:56:34.006788 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3310 00:56:34.007080 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3311 00:56:34.007167 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3312 00:56:34.007246 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3313 00:56:34.007340 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3314 00:56:34.007419 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3315 00:56:34.007496 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3316 00:56:34.007573 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3317 00:56:34.007649 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3318 00:56:34.007725 ==
3319 00:56:34.007802 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 00:56:34.007879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 00:56:34.007955 ==
3322 00:56:34.008031 DQS Delay:
3323 00:56:34.008107 DQS0 = 0, DQS1 = 0
3324 00:56:34.008184 DQM Delay:
3325 00:56:34.008260 DQM0 = 118, DQM1 = 109
3326 00:56:34.008337 DQ Delay:
3327 00:56:34.008413 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3328 00:56:34.008490 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3329 00:56:34.008566 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3330 00:56:34.008642 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3331 00:56:34.008718
3332 00:56:34.008793
3333 00:56:34.008868 ==
3334 00:56:34.008944 Dram Type= 6, Freq= 0, CH_1, rank 0
3335 00:56:34.009021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3336 00:56:34.009105 ==
3337 00:56:34.009172
3338 00:56:34.009240
3339 00:56:34.009306 TX Vref Scan disable
3340 00:56:34.009373 == TX Byte 0 ==
3341 00:56:34.009441 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3342 00:56:34.009509 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3343 00:56:34.009577 == TX Byte 1 ==
3344 00:56:34.009644 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3345 00:56:34.009712 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3346 00:56:34.009780 ==
3347 00:56:34.009846 Dram Type= 6, Freq= 0, CH_1, rank 0
3348 00:56:34.009914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3349 00:56:34.009982 ==
3350 00:56:34.010050 TX Vref=22, minBit 9, minWin=25, winSum=417
3351 00:56:34.010118 TX Vref=24, minBit 9, minWin=25, winSum=422
3352 00:56:34.010211 TX Vref=26, minBit 11, minWin=25, winSum=429
3353 00:56:34.010285 TX Vref=28, minBit 11, minWin=25, winSum=433
3354 00:56:34.010354 TX Vref=30, minBit 7, minWin=26, winSum=432
3355 00:56:34.010424 TX Vref=32, minBit 13, minWin=25, winSum=428
3356 00:56:34.010492 [TxChooseVref] Worse bit 7, Min win 26, Win sum 432, Final Vref 30
3357 00:56:34.010561
3358 00:56:34.010628 Final TX Range 1 Vref 30
3359 00:56:34.010696
3360 00:56:34.010764 ==
3361 00:56:34.010831 Dram Type= 6, Freq= 0, CH_1, rank 0
3362 00:56:34.010899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3363 00:56:34.010966 ==
3364 00:56:34.011033
3365 00:56:34.011099
3366 00:56:34.011166 TX Vref Scan disable
3367 00:56:34.011233 == TX Byte 0 ==
3368 00:56:34.011300 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3369 00:56:34.011368 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3370 00:56:34.011435 == TX Byte 1 ==
3371 00:56:34.011502 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3372 00:56:34.011570 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3373 00:56:34.011637
3374 00:56:34.011704 [DATLAT]
3375 00:56:34.011770 Freq=1200, CH1 RK0
3376 00:56:34.011837
3377 00:56:34.011904 DATLAT Default: 0xd
3378 00:56:34.011971 0, 0xFFFF, sum = 0
3379 00:56:34.012040 1, 0xFFFF, sum = 0
3380 00:56:34.012109 2, 0xFFFF, sum = 0
3381 00:56:34.012178 3, 0xFFFF, sum = 0
3382 00:56:34.012246 4, 0xFFFF, sum = 0
3383 00:56:34.012314 5, 0xFFFF, sum = 0
3384 00:56:34.012382 6, 0xFFFF, sum = 0
3385 00:56:34.012450 7, 0xFFFF, sum = 0
3386 00:56:34.012519 8, 0xFFFF, sum = 0
3387 00:56:34.012586 9, 0xFFFF, sum = 0
3388 00:56:34.012654 10, 0xFFFF, sum = 0
3389 00:56:34.012722 11, 0xFFFF, sum = 0
3390 00:56:34.012790 12, 0x0, sum = 1
3391 00:56:34.012858 13, 0x0, sum = 2
3392 00:56:34.012926 14, 0x0, sum = 3
3393 00:56:34.012992 15, 0x0, sum = 4
3394 00:56:34.013060 best_step = 13
3395 00:56:34.013135
3396 00:56:34.013204 ==
3397 00:56:34.013271 Dram Type= 6, Freq= 0, CH_1, rank 0
3398 00:56:34.013339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3399 00:56:34.013407 ==
3400 00:56:34.013474 RX Vref Scan: 1
3401 00:56:34.013541
3402 00:56:34.013608 Set Vref Range= 32 -> 127
3403 00:56:34.013675
3404 00:56:34.013742 RX Vref 32 -> 127, step: 1
3405 00:56:34.013808
3406 00:56:34.013876 RX Delay -21 -> 252, step: 4
3407 00:56:34.013943
3408 00:56:34.014010 Set Vref, RX VrefLevel [Byte0]: 32
3409 00:56:34.014086 [Byte1]: 32
3410 00:56:34.014147
3411 00:56:34.014218 Set Vref, RX VrefLevel [Byte0]: 33
3412 00:56:34.014280 [Byte1]: 33
3413 00:56:34.014340
3414 00:56:34.014400 Set Vref, RX VrefLevel [Byte0]: 34
3415 00:56:34.014460 [Byte1]: 34
3416 00:56:34.014520
3417 00:56:34.014579 Set Vref, RX VrefLevel [Byte0]: 35
3418 00:56:34.014639 [Byte1]: 35
3419 00:56:34.014699
3420 00:56:34.014760 Set Vref, RX VrefLevel [Byte0]: 36
3421 00:56:34.014820 [Byte1]: 36
3422 00:56:34.014880
3423 00:56:34.014940 Set Vref, RX VrefLevel [Byte0]: 37
3424 00:56:34.015000 [Byte1]: 37
3425 00:56:34.015061
3426 00:56:34.015148 Set Vref, RX VrefLevel [Byte0]: 38
3427 00:56:34.015240 [Byte1]: 38
3428 00:56:34.015304
3429 00:56:34.015365 Set Vref, RX VrefLevel [Byte0]: 39
3430 00:56:34.015426 [Byte1]: 39
3431 00:56:34.015486
3432 00:56:34.015547 Set Vref, RX VrefLevel [Byte0]: 40
3433 00:56:34.015607 [Byte1]: 40
3434 00:56:34.015667
3435 00:56:34.015726 Set Vref, RX VrefLevel [Byte0]: 41
3436 00:56:34.015786 [Byte1]: 41
3437 00:56:34.015846
3438 00:56:34.015906 Set Vref, RX VrefLevel [Byte0]: 42
3439 00:56:34.015967 [Byte1]: 42
3440 00:56:34.016027
3441 00:56:34.016086 Set Vref, RX VrefLevel [Byte0]: 43
3442 00:56:34.016147 [Byte1]: 43
3443 00:56:34.016207
3444 00:56:34.016267 Set Vref, RX VrefLevel [Byte0]: 44
3445 00:56:34.016327 [Byte1]: 44
3446 00:56:34.016387
3447 00:56:34.016447 Set Vref, RX VrefLevel [Byte0]: 45
3448 00:56:34.016508 [Byte1]: 45
3449 00:56:34.016569
3450 00:56:34.016629 Set Vref, RX VrefLevel [Byte0]: 46
3451 00:56:34.016689 [Byte1]: 46
3452 00:56:34.016748
3453 00:56:34.016808 Set Vref, RX VrefLevel [Byte0]: 47
3454 00:56:34.016869 [Byte1]: 47
3455 00:56:34.016929
3456 00:56:34.016989 Set Vref, RX VrefLevel [Byte0]: 48
3457 00:56:34.017049 [Byte1]: 48
3458 00:56:34.017109
3459 00:56:34.017169 Set Vref, RX VrefLevel [Byte0]: 49
3460 00:56:34.017230 [Byte1]: 49
3461 00:56:34.017290
3462 00:56:34.017351 Set Vref, RX VrefLevel [Byte0]: 50
3463 00:56:34.017410 [Byte1]: 50
3464 00:56:34.017471
3465 00:56:34.017530 Set Vref, RX VrefLevel [Byte0]: 51
3466 00:56:34.017591 [Byte1]: 51
3467 00:56:34.017651
3468 00:56:34.017711 Set Vref, RX VrefLevel [Byte0]: 52
3469 00:56:34.017771 [Byte1]: 52
3470 00:56:34.017831
3471 00:56:34.018092 Set Vref, RX VrefLevel [Byte0]: 53
3472 00:56:34.018172 [Byte1]: 53
3473 00:56:34.018269
3474 00:56:34.018363 Set Vref, RX VrefLevel [Byte0]: 54
3475 00:56:34.018464 [Byte1]: 54
3476 00:56:34.018532
3477 00:56:34.018593 Set Vref, RX VrefLevel [Byte0]: 55
3478 00:56:34.018654 [Byte1]: 55
3479 00:56:34.018715
3480 00:56:34.018776 Set Vref, RX VrefLevel [Byte0]: 56
3481 00:56:34.018836 [Byte1]: 56
3482 00:56:34.018897
3483 00:56:34.018957 Set Vref, RX VrefLevel [Byte0]: 57
3484 00:56:34.019017 [Byte1]: 57
3485 00:56:34.019077
3486 00:56:34.019146 Set Vref, RX VrefLevel [Byte0]: 58
3487 00:56:34.019201 [Byte1]: 58
3488 00:56:34.019255
3489 00:56:34.019309 Set Vref, RX VrefLevel [Byte0]: 59
3490 00:56:34.019364 [Byte1]: 59
3491 00:56:34.019420
3492 00:56:34.019474 Set Vref, RX VrefLevel [Byte0]: 60
3493 00:56:34.019528 [Byte1]: 60
3494 00:56:34.019583
3495 00:56:34.019638 Set Vref, RX VrefLevel [Byte0]: 61
3496 00:56:34.019693 [Byte1]: 61
3497 00:56:34.019747
3498 00:56:34.019802 Set Vref, RX VrefLevel [Byte0]: 62
3499 00:56:34.019856 [Byte1]: 62
3500 00:56:34.019911
3501 00:56:34.019965 Set Vref, RX VrefLevel [Byte0]: 63
3502 00:56:34.020021 [Byte1]: 63
3503 00:56:34.020076
3504 00:56:34.020131 Set Vref, RX VrefLevel [Byte0]: 64
3505 00:56:34.020185 [Byte1]: 64
3506 00:56:34.020239
3507 00:56:34.020293 Set Vref, RX VrefLevel [Byte0]: 65
3508 00:56:34.020348 [Byte1]: 65
3509 00:56:34.020402
3510 00:56:34.020456 Set Vref, RX VrefLevel [Byte0]: 66
3511 00:56:34.020511 [Byte1]: 66
3512 00:56:34.020566
3513 00:56:34.020620 Set Vref, RX VrefLevel [Byte0]: 67
3514 00:56:34.020674 [Byte1]: 67
3515 00:56:34.020729
3516 00:56:34.020783 Set Vref, RX VrefLevel [Byte0]: 68
3517 00:56:34.020838 [Byte1]: 68
3518 00:56:34.020893
3519 00:56:34.020947 Final RX Vref Byte 0 = 52 to rank0
3520 00:56:34.021002 Final RX Vref Byte 1 = 54 to rank0
3521 00:56:34.021058 Final RX Vref Byte 0 = 52 to rank1
3522 00:56:34.021113 Final RX Vref Byte 1 = 54 to rank1==
3523 00:56:34.021168 Dram Type= 6, Freq= 0, CH_1, rank 0
3524 00:56:34.021223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 00:56:34.021278 ==
3526 00:56:34.021332 DQS Delay:
3527 00:56:34.021387 DQS0 = 0, DQS1 = 0
3528 00:56:34.021442 DQM Delay:
3529 00:56:34.021496 DQM0 = 116, DQM1 = 110
3530 00:56:34.021551 DQ Delay:
3531 00:56:34.021605 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =114
3532 00:56:34.021661 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3533 00:56:34.021717 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3534 00:56:34.021772 DQ12 =118, DQ13 =116, DQ14 =120, DQ15 =118
3535 00:56:34.021827
3536 00:56:34.021881
3537 00:56:34.021936 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3538 00:56:34.021992 CH1 RK0: MR19=403, MR18=4F7
3539 00:56:34.022047 CH1_RK0: MR19=0x403, MR18=0x4F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3540 00:56:34.022103
3541 00:56:34.022158 ----->DramcWriteLeveling(PI) begin...
3542 00:56:34.022219 ==
3543 00:56:34.022274 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 00:56:34.022329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 00:56:34.022384 ==
3546 00:56:34.022439 Write leveling (Byte 0): 25 => 25
3547 00:56:34.022494 Write leveling (Byte 1): 29 => 29
3548 00:56:34.022549 DramcWriteLeveling(PI) end<-----
3549 00:56:34.022603
3550 00:56:34.022658 ==
3551 00:56:34.022712 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 00:56:34.022767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 00:56:34.022822 ==
3554 00:56:34.022878 [Gating] SW mode calibration
3555 00:56:34.022932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3556 00:56:34.022989 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3557 00:56:34.023044 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3558 00:56:34.023099 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3559 00:56:34.023154 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3560 00:56:34.023209 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3561 00:56:34.023263 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3562 00:56:34.023318 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3563 00:56:34.023372 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3564 00:56:34.023427 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
3565 00:56:34.023481 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3566 00:56:34.023537 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3567 00:56:34.023591 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3568 00:56:34.023645 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3569 00:56:34.023699 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3570 00:56:34.023755 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3571 00:56:34.023809 1 0 24 | B1->B0 | 3939 2a2a | 1 0 | (0 0) (0 0)
3572 00:56:34.023865 1 0 28 | B1->B0 | 4545 4545 | 0 1 | (0 0) (0 0)
3573 00:56:34.023919 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3574 00:56:34.023974 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3575 00:56:34.024028 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3576 00:56:34.024094 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3577 00:56:34.024148 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3578 00:56:34.024201 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3579 00:56:34.024253 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3580 00:56:34.024323 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3581 00:56:34.024391 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 00:56:34.024444 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 00:56:34.024497 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 00:56:34.024550 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 00:56:34.024603 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 00:56:34.024657 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 00:56:34.024710 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 00:56:34.024764 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 00:56:34.024817 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 00:56:34.025062 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3591 00:56:34.025122 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3592 00:56:34.025177 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3593 00:56:34.025231 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3594 00:56:34.025284 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3595 00:56:34.025337 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3596 00:56:34.025391 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3597 00:56:34.025444 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3598 00:56:34.025498 Total UI for P1: 0, mck2ui 16
3599 00:56:34.025552 best dqsien dly found for B0: ( 1, 3, 26)
3600 00:56:34.025607 Total UI for P1: 0, mck2ui 16
3601 00:56:34.025661 best dqsien dly found for B1: ( 1, 3, 26)
3602 00:56:34.025716 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3603 00:56:34.025770 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3604 00:56:34.025825
3605 00:56:34.025879 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3606 00:56:34.025933 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3607 00:56:34.025986 [Gating] SW calibration Done
3608 00:56:34.026041 ==
3609 00:56:34.026095 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 00:56:34.026149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 00:56:34.026244 ==
3612 00:56:34.026298 RX Vref Scan: 0
3613 00:56:34.026352
3614 00:56:34.026406 RX Vref 0 -> 0, step: 1
3615 00:56:34.026459
3616 00:56:34.026513 RX Delay -40 -> 252, step: 8
3617 00:56:34.026566 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3618 00:56:34.026621 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3619 00:56:34.026674 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3620 00:56:34.026728 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3621 00:56:34.026781 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3622 00:56:34.026835 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3623 00:56:34.026888 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3624 00:56:34.026942 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3625 00:56:34.026995 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3626 00:56:34.027049 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3627 00:56:34.027103 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3628 00:56:34.027156 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3629 00:56:34.027210 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3630 00:56:34.027264 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3631 00:56:34.027317 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3632 00:56:34.027371 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3633 00:56:34.027424 ==
3634 00:56:34.027478 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 00:56:34.027532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 00:56:34.027586 ==
3637 00:56:34.027640 DQS Delay:
3638 00:56:34.027693 DQS0 = 0, DQS1 = 0
3639 00:56:34.027747 DQM Delay:
3640 00:56:34.027800 DQM0 = 116, DQM1 = 109
3641 00:56:34.027854 DQ Delay:
3642 00:56:34.027907 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3643 00:56:34.027961 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3644 00:56:34.028015 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3645 00:56:34.028069 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3646 00:56:34.028122
3647 00:56:34.028176
3648 00:56:34.028228 ==
3649 00:56:34.028282 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 00:56:34.028336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 00:56:34.028390 ==
3652 00:56:34.028443
3653 00:56:34.028497
3654 00:56:34.028550 TX Vref Scan disable
3655 00:56:34.028603 == TX Byte 0 ==
3656 00:56:34.028657 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3657 00:56:34.028710 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3658 00:56:34.028765 == TX Byte 1 ==
3659 00:56:34.028818 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3660 00:56:34.028873 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3661 00:56:34.028926 ==
3662 00:56:34.028979 Dram Type= 6, Freq= 0, CH_1, rank 1
3663 00:56:34.029042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3664 00:56:34.029100 ==
3665 00:56:34.029153 TX Vref=22, minBit 11, minWin=24, winSum=422
3666 00:56:34.029208 TX Vref=24, minBit 9, minWin=25, winSum=432
3667 00:56:34.029262 TX Vref=26, minBit 9, minWin=26, winSum=434
3668 00:56:34.029316 TX Vref=28, minBit 9, minWin=26, winSum=435
3669 00:56:34.029370 TX Vref=30, minBit 9, minWin=26, winSum=433
3670 00:56:34.029423 TX Vref=32, minBit 7, minWin=26, winSum=431
3671 00:56:34.029477 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 28
3672 00:56:34.029531
3673 00:56:34.029584 Final TX Range 1 Vref 28
3674 00:56:34.029639
3675 00:56:34.029692 ==
3676 00:56:34.029745 Dram Type= 6, Freq= 0, CH_1, rank 1
3677 00:56:34.029799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3678 00:56:34.029853 ==
3679 00:56:34.029907
3680 00:56:34.029960
3681 00:56:34.030013 TX Vref Scan disable
3682 00:56:34.030067 == TX Byte 0 ==
3683 00:56:34.030121 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3684 00:56:34.030209 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3685 00:56:34.030278 == TX Byte 1 ==
3686 00:56:34.030332 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3687 00:56:34.030386 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3688 00:56:34.030439
3689 00:56:34.030492 [DATLAT]
3690 00:56:34.030545 Freq=1200, CH1 RK1
3691 00:56:34.030599
3692 00:56:34.030652 DATLAT Default: 0xd
3693 00:56:34.030706 0, 0xFFFF, sum = 0
3694 00:56:34.030760 1, 0xFFFF, sum = 0
3695 00:56:34.030815 2, 0xFFFF, sum = 0
3696 00:56:34.030869 3, 0xFFFF, sum = 0
3697 00:56:34.030923 4, 0xFFFF, sum = 0
3698 00:56:34.030978 5, 0xFFFF, sum = 0
3699 00:56:34.031032 6, 0xFFFF, sum = 0
3700 00:56:34.031087 7, 0xFFFF, sum = 0
3701 00:56:34.031141 8, 0xFFFF, sum = 0
3702 00:56:34.031196 9, 0xFFFF, sum = 0
3703 00:56:34.031250 10, 0xFFFF, sum = 0
3704 00:56:34.031305 11, 0xFFFF, sum = 0
3705 00:56:34.031359 12, 0x0, sum = 1
3706 00:56:34.031414 13, 0x0, sum = 2
3707 00:56:34.031468 14, 0x0, sum = 3
3708 00:56:34.031522 15, 0x0, sum = 4
3709 00:56:34.031576 best_step = 13
3710 00:56:34.031630
3711 00:56:34.031682 ==
3712 00:56:34.031736 Dram Type= 6, Freq= 0, CH_1, rank 1
3713 00:56:34.031790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3714 00:56:34.031844 ==
3715 00:56:34.031897 RX Vref Scan: 0
3716 00:56:34.031951
3717 00:56:34.032004 RX Vref 0 -> 0, step: 1
3718 00:56:34.032057
3719 00:56:34.032110 RX Delay -21 -> 252, step: 4
3720 00:56:34.032164 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3721 00:56:34.032217 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3722 00:56:34.032271 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3723 00:56:34.032325 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3724 00:56:34.032378 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3725 00:56:34.032431 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3726 00:56:34.032485 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3727 00:56:34.032538 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3728 00:56:34.032791 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3729 00:56:34.032854 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3730 00:56:34.032910 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3731 00:56:34.032964 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3732 00:56:34.033018 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3733 00:56:34.033072 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3734 00:56:34.033125 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3735 00:56:34.033179 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3736 00:56:34.033233 ==
3737 00:56:34.033286 Dram Type= 6, Freq= 0, CH_1, rank 1
3738 00:56:34.033341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3739 00:56:34.033395 ==
3740 00:56:34.033449 DQS Delay:
3741 00:56:34.033502 DQS0 = 0, DQS1 = 0
3742 00:56:34.033556 DQM Delay:
3743 00:56:34.033610 DQM0 = 117, DQM1 = 109
3744 00:56:34.033663 DQ Delay:
3745 00:56:34.033716 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3746 00:56:34.033771 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =116
3747 00:56:34.033824 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3748 00:56:34.033878 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3749 00:56:34.033931
3750 00:56:34.033984
3751 00:56:34.034038 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 414 ps
3752 00:56:34.034093 CH1 RK1: MR19=303, MR18=F5EF
3753 00:56:34.034147 CH1_RK1: MR19=0x303, MR18=0xF5EF, DQSOSC=414, MR23=63, INC=38, DEC=25
3754 00:56:34.034207 [RxdqsGatingPostProcess] freq 1200
3755 00:56:34.034261 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3756 00:56:34.034315 best DQS0 dly(2T, 0.5T) = (0, 11)
3757 00:56:34.034369 best DQS1 dly(2T, 0.5T) = (0, 11)
3758 00:56:34.034423 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3759 00:56:34.034477 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3760 00:56:34.034531 best DQS0 dly(2T, 0.5T) = (0, 11)
3761 00:56:34.034584 best DQS1 dly(2T, 0.5T) = (0, 11)
3762 00:56:34.034638 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3763 00:56:34.034691 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3764 00:56:34.034745 Pre-setting of DQS Precalculation
3765 00:56:34.034798 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3766 00:56:34.034853 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3767 00:56:34.034908 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3768 00:56:34.034961
3769 00:56:34.035014
3770 00:56:34.035067 [Calibration Summary] 2400 Mbps
3771 00:56:34.035121 CH 0, Rank 0
3772 00:56:34.035175 SW Impedance : PASS
3773 00:56:34.035229 DUTY Scan : NO K
3774 00:56:34.035282 ZQ Calibration : PASS
3775 00:56:34.035336 Jitter Meter : NO K
3776 00:56:34.035390 CBT Training : PASS
3777 00:56:34.035444 Write leveling : PASS
3778 00:56:34.035497 RX DQS gating : PASS
3779 00:56:34.035550 RX DQ/DQS(RDDQC) : PASS
3780 00:56:34.035603 TX DQ/DQS : PASS
3781 00:56:34.035657 RX DATLAT : PASS
3782 00:56:34.035711 RX DQ/DQS(Engine): PASS
3783 00:56:34.035764 TX OE : NO K
3784 00:56:34.035818 All Pass.
3785 00:56:34.035871
3786 00:56:34.035924 CH 0, Rank 1
3787 00:56:34.035977 SW Impedance : PASS
3788 00:56:34.036032 DUTY Scan : NO K
3789 00:56:34.036085 ZQ Calibration : PASS
3790 00:56:34.036138 Jitter Meter : NO K
3791 00:56:34.036192 CBT Training : PASS
3792 00:56:34.036245 Write leveling : PASS
3793 00:56:34.036299 RX DQS gating : PASS
3794 00:56:34.036352 RX DQ/DQS(RDDQC) : PASS
3795 00:56:34.036405 TX DQ/DQS : PASS
3796 00:56:34.036459 RX DATLAT : PASS
3797 00:56:34.036512 RX DQ/DQS(Engine): PASS
3798 00:56:34.036565 TX OE : NO K
3799 00:56:34.036618 All Pass.
3800 00:56:34.036672
3801 00:56:34.036725 CH 1, Rank 0
3802 00:56:34.036779 SW Impedance : PASS
3803 00:56:34.036832 DUTY Scan : NO K
3804 00:56:34.036886 ZQ Calibration : PASS
3805 00:56:34.036940 Jitter Meter : NO K
3806 00:56:34.036993 CBT Training : PASS
3807 00:56:34.037046 Write leveling : PASS
3808 00:56:34.037100 RX DQS gating : PASS
3809 00:56:34.037154 RX DQ/DQS(RDDQC) : PASS
3810 00:56:34.037208 TX DQ/DQS : PASS
3811 00:56:34.037262 RX DATLAT : PASS
3812 00:56:34.037316 RX DQ/DQS(Engine): PASS
3813 00:56:34.037369 TX OE : NO K
3814 00:56:34.037423 All Pass.
3815 00:56:34.037477
3816 00:56:34.037530 CH 1, Rank 1
3817 00:56:34.037583 SW Impedance : PASS
3818 00:56:34.037637 DUTY Scan : NO K
3819 00:56:34.037690 ZQ Calibration : PASS
3820 00:56:34.037743 Jitter Meter : NO K
3821 00:56:34.037796 CBT Training : PASS
3822 00:56:34.037850 Write leveling : PASS
3823 00:56:34.037902 RX DQS gating : PASS
3824 00:56:34.037956 RX DQ/DQS(RDDQC) : PASS
3825 00:56:34.038009 TX DQ/DQS : PASS
3826 00:56:34.038064 RX DATLAT : PASS
3827 00:56:34.038117 RX DQ/DQS(Engine): PASS
3828 00:56:34.038174 TX OE : NO K
3829 00:56:34.038262 All Pass.
3830 00:56:34.038316
3831 00:56:34.038370 DramC Write-DBI off
3832 00:56:34.038423 PER_BANK_REFRESH: Hybrid Mode
3833 00:56:34.038477 TX_TRACKING: ON
3834 00:56:34.038531 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3835 00:56:34.038586 [FAST_K] Save calibration result to emmc
3836 00:56:34.038641 dramc_set_vcore_voltage set vcore to 650000
3837 00:56:34.038694 Read voltage for 600, 5
3838 00:56:34.038748 Vio18 = 0
3839 00:56:34.038802 Vcore = 650000
3840 00:56:34.038876 Vdram = 0
3841 00:56:34.038944 Vddq = 0
3842 00:56:34.039017 Vmddr = 0
3843 00:56:34.039108 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3844 00:56:34.039205 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3845 00:56:34.039267 MEM_TYPE=3, freq_sel=19
3846 00:56:34.039323 sv_algorithm_assistance_LP4_1600
3847 00:56:34.039379 ============ PULL DRAM RESETB DOWN ============
3848 00:56:34.039434 ========== PULL DRAM RESETB DOWN end =========
3849 00:56:34.039489 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3850 00:56:34.039544 ===================================
3851 00:56:34.039599 LPDDR4 DRAM CONFIGURATION
3852 00:56:34.039653 ===================================
3853 00:56:34.039711 EX_ROW_EN[0] = 0x0
3854 00:56:34.039771 EX_ROW_EN[1] = 0x0
3855 00:56:34.039826 LP4Y_EN = 0x0
3856 00:56:34.039879 WORK_FSP = 0x0
3857 00:56:34.039932 WL = 0x2
3858 00:56:34.039986 RL = 0x2
3859 00:56:34.040039 BL = 0x2
3860 00:56:34.040092 RPST = 0x0
3861 00:56:34.040145 RD_PRE = 0x0
3862 00:56:34.040199 WR_PRE = 0x1
3863 00:56:34.040252 WR_PST = 0x0
3864 00:56:34.040305 DBI_WR = 0x0
3865 00:56:34.040358 DBI_RD = 0x0
3866 00:56:34.040412 OTF = 0x1
3867 00:56:34.040466 ===================================
3868 00:56:34.040521 ===================================
3869 00:56:34.040575 ANA top config
3870 00:56:34.040629 ===================================
3871 00:56:34.040683 DLL_ASYNC_EN = 0
3872 00:56:34.040929 ALL_SLAVE_EN = 1
3873 00:56:34.040989 NEW_RANK_MODE = 1
3874 00:56:34.041045 DLL_IDLE_MODE = 1
3875 00:56:34.041099 LP45_APHY_COMB_EN = 1
3876 00:56:34.041152 TX_ODT_DIS = 1
3877 00:56:34.041206 NEW_8X_MODE = 1
3878 00:56:34.041260 ===================================
3879 00:56:34.041314 ===================================
3880 00:56:34.041368 data_rate = 1200
3881 00:56:34.041421 CKR = 1
3882 00:56:34.041475 DQ_P2S_RATIO = 8
3883 00:56:34.041528 ===================================
3884 00:56:34.041582 CA_P2S_RATIO = 8
3885 00:56:34.041636 DQ_CA_OPEN = 0
3886 00:56:34.041689 DQ_SEMI_OPEN = 0
3887 00:56:34.041742 CA_SEMI_OPEN = 0
3888 00:56:34.041795 CA_FULL_RATE = 0
3889 00:56:34.041848 DQ_CKDIV4_EN = 1
3890 00:56:34.041902 CA_CKDIV4_EN = 1
3891 00:56:34.041956 CA_PREDIV_EN = 0
3892 00:56:34.042009 PH8_DLY = 0
3893 00:56:34.042062 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3894 00:56:34.042115 DQ_AAMCK_DIV = 4
3895 00:56:34.042178 CA_AAMCK_DIV = 4
3896 00:56:34.042274 CA_ADMCK_DIV = 4
3897 00:56:34.042328 DQ_TRACK_CA_EN = 0
3898 00:56:34.042407 CA_PICK = 600
3899 00:56:34.042508 CA_MCKIO = 600
3900 00:56:34.042597 MCKIO_SEMI = 0
3901 00:56:34.042682 PLL_FREQ = 2288
3902 00:56:34.042765 DQ_UI_PI_RATIO = 32
3903 00:56:34.042822 CA_UI_PI_RATIO = 0
3904 00:56:34.042878 ===================================
3905 00:56:34.042932 ===================================
3906 00:56:34.042987 memory_type:LPDDR4
3907 00:56:34.043041 GP_NUM : 10
3908 00:56:34.043095 SRAM_EN : 1
3909 00:56:34.043148 MD32_EN : 0
3910 00:56:34.043202 ===================================
3911 00:56:34.043256 [ANA_INIT] >>>>>>>>>>>>>>
3912 00:56:34.043310 <<<<<< [CONFIGURE PHASE]: ANA_TX
3913 00:56:34.043365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3914 00:56:34.043420 ===================================
3915 00:56:34.043473 data_rate = 1200,PCW = 0X5800
3916 00:56:34.043527 ===================================
3917 00:56:34.043581 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3918 00:56:34.043635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3919 00:56:34.043689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3920 00:56:34.043744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3921 00:56:34.043798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3922 00:56:34.043852 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3923 00:56:34.043905 [ANA_INIT] flow start
3924 00:56:34.043959 [ANA_INIT] PLL >>>>>>>>
3925 00:56:34.044012 [ANA_INIT] PLL <<<<<<<<
3926 00:56:34.044066 [ANA_INIT] MIDPI >>>>>>>>
3927 00:56:34.044119 [ANA_INIT] MIDPI <<<<<<<<
3928 00:56:34.044172 [ANA_INIT] DLL >>>>>>>>
3929 00:56:34.044226 [ANA_INIT] flow end
3930 00:56:34.044280 ============ LP4 DIFF to SE enter ============
3931 00:56:34.044334 ============ LP4 DIFF to SE exit ============
3932 00:56:34.044389 [ANA_INIT] <<<<<<<<<<<<<
3933 00:56:34.044442 [Flow] Enable top DCM control >>>>>
3934 00:56:34.044496 [Flow] Enable top DCM control <<<<<
3935 00:56:34.044549 Enable DLL master slave shuffle
3936 00:56:34.044603 ==============================================================
3937 00:56:34.044656 Gating Mode config
3938 00:56:34.044710 ==============================================================
3939 00:56:34.044763 Config description:
3940 00:56:34.044816 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3941 00:56:34.044870 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3942 00:56:34.044924 SELPH_MODE 0: By rank 1: By Phase
3943 00:56:34.044978 ==============================================================
3944 00:56:34.045032 GAT_TRACK_EN = 1
3945 00:56:34.045085 RX_GATING_MODE = 2
3946 00:56:34.045138 RX_GATING_TRACK_MODE = 2
3947 00:56:34.045191 SELPH_MODE = 1
3948 00:56:34.045245 PICG_EARLY_EN = 1
3949 00:56:34.045298 VALID_LAT_VALUE = 1
3950 00:56:34.045352 ==============================================================
3951 00:56:34.045406 Enter into Gating configuration >>>>
3952 00:56:34.045460 Exit from Gating configuration <<<<
3953 00:56:34.045514 Enter into DVFS_PRE_config >>>>>
3954 00:56:34.047908 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3955 00:56:34.051022 Exit from DVFS_PRE_config <<<<<
3956 00:56:34.054466 Enter into PICG configuration >>>>
3957 00:56:34.057812 Exit from PICG configuration <<<<
3958 00:56:34.060986 [RX_INPUT] configuration >>>>>
3959 00:56:34.061147 [RX_INPUT] configuration <<<<<
3960 00:56:34.067366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3961 00:56:34.074098 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3962 00:56:34.081226 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3963 00:56:34.084106 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3964 00:56:34.090430 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3965 00:56:34.097547 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3966 00:56:34.100569 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3967 00:56:34.104327 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3968 00:56:34.110468 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3969 00:56:34.114062 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3970 00:56:34.117435 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3971 00:56:34.123695 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3972 00:56:34.127181 ===================================
3973 00:56:34.127438 LPDDR4 DRAM CONFIGURATION
3974 00:56:34.130811 ===================================
3975 00:56:34.133823 EX_ROW_EN[0] = 0x0
3976 00:56:34.137037 EX_ROW_EN[1] = 0x0
3977 00:56:34.137503 LP4Y_EN = 0x0
3978 00:56:34.140552 WORK_FSP = 0x0
3979 00:56:34.140857 WL = 0x2
3980 00:56:34.143854 RL = 0x2
3981 00:56:34.144202 BL = 0x2
3982 00:56:34.147413 RPST = 0x0
3983 00:56:34.147901 RD_PRE = 0x0
3984 00:56:34.150405 WR_PRE = 0x1
3985 00:56:34.150972 WR_PST = 0x0
3986 00:56:34.153710 DBI_WR = 0x0
3987 00:56:34.154267 DBI_RD = 0x0
3988 00:56:34.157288 OTF = 0x1
3989 00:56:34.160435 ===================================
3990 00:56:34.163584 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3991 00:56:34.166817 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3992 00:56:34.173642 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3993 00:56:34.176660 ===================================
3994 00:56:34.177136 LPDDR4 DRAM CONFIGURATION
3995 00:56:34.180593 ===================================
3996 00:56:34.183464 EX_ROW_EN[0] = 0x10
3997 00:56:34.186796 EX_ROW_EN[1] = 0x0
3998 00:56:34.187383 LP4Y_EN = 0x0
3999 00:56:34.189927 WORK_FSP = 0x0
4000 00:56:34.190375 WL = 0x2
4001 00:56:34.193322 RL = 0x2
4002 00:56:34.193787 BL = 0x2
4003 00:56:34.277214 RPST = 0x0
4004 00:56:34.277697 RD_PRE = 0x0
4005 00:56:34.278038 WR_PRE = 0x1
4006 00:56:34.278411 WR_PST = 0x0
4007 00:56:34.278724 DBI_WR = 0x0
4008 00:56:34.279020 DBI_RD = 0x0
4009 00:56:34.279311 OTF = 0x1
4010 00:56:34.279601 ===================================
4011 00:56:34.279893 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4012 00:56:34.280180 nWR fixed to 30
4013 00:56:34.280522 [ModeRegInit_LP4] CH0 RK0
4014 00:56:34.280938 [ModeRegInit_LP4] CH0 RK1
4015 00:56:34.281234 [ModeRegInit_LP4] CH1 RK0
4016 00:56:34.281518 [ModeRegInit_LP4] CH1 RK1
4017 00:56:34.281798 match AC timing 17
4018 00:56:34.282081 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4019 00:56:34.282421 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4020 00:56:34.282707 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4021 00:56:34.282989 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4022 00:56:34.283268 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4023 00:56:34.283545 ==
4024 00:56:34.283826 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 00:56:34.284111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 00:56:34.284409 ==
4027 00:56:34.284918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4028 00:56:34.285238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4029 00:56:34.285528 [CA 0] Center 36 (6~66) winsize 61
4030 00:56:34.285886 [CA 1] Center 36 (6~66) winsize 61
4031 00:56:34.286222 [CA 2] Center 34 (4~65) winsize 62
4032 00:56:34.286521 [CA 3] Center 34 (4~65) winsize 62
4033 00:56:34.288632 [CA 4] Center 33 (3~64) winsize 62
4034 00:56:34.291951 [CA 5] Center 33 (3~64) winsize 62
4035 00:56:34.292509
4036 00:56:34.295491 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4037 00:56:34.296066
4038 00:56:34.298975 [CATrainingPosCal] consider 1 rank data
4039 00:56:34.302070 u2DelayCellTimex100 = 270/100 ps
4040 00:56:34.305631 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4041 00:56:34.308612 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4042 00:56:34.311975 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4043 00:56:34.315157 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4044 00:56:34.322063 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4045 00:56:34.324897 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4046 00:56:34.325203
4047 00:56:34.328439 CA PerBit enable=1, Macro0, CA PI delay=33
4048 00:56:34.328745
4049 00:56:34.331671 [CBTSetCACLKResult] CA Dly = 33
4050 00:56:34.332027 CS Dly: 4 (0~35)
4051 00:56:34.332298 ==
4052 00:56:34.334855 Dram Type= 6, Freq= 0, CH_0, rank 1
4053 00:56:34.341564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 00:56:34.341876 ==
4055 00:56:34.344686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4056 00:56:34.351682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4057 00:56:34.354716 [CA 0] Center 36 (6~66) winsize 61
4058 00:56:34.358128 [CA 1] Center 36 (6~66) winsize 61
4059 00:56:34.361202 [CA 2] Center 33 (3~64) winsize 62
4060 00:56:34.365222 [CA 3] Center 33 (3~64) winsize 62
4061 00:56:34.367807 [CA 4] Center 33 (2~64) winsize 63
4062 00:56:34.371381 [CA 5] Center 33 (2~64) winsize 63
4063 00:56:34.371796
4064 00:56:34.374709 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4065 00:56:34.375200
4066 00:56:34.378048 [CATrainingPosCal] consider 2 rank data
4067 00:56:34.381012 u2DelayCellTimex100 = 270/100 ps
4068 00:56:34.384628 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4069 00:56:34.391044 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4070 00:56:34.394332 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4071 00:56:34.397782 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4072 00:56:34.400935 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4073 00:56:34.404181 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4074 00:56:34.404647
4075 00:56:34.407690 CA PerBit enable=1, Macro0, CA PI delay=33
4076 00:56:34.408277
4077 00:56:34.410998 [CBTSetCACLKResult] CA Dly = 33
4078 00:56:34.414288 CS Dly: 4 (0~36)
4079 00:56:34.414858
4080 00:56:34.417695 ----->DramcWriteLeveling(PI) begin...
4081 00:56:34.418306 ==
4082 00:56:34.421466 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 00:56:34.424139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 00:56:34.424730 ==
4085 00:56:34.427643 Write leveling (Byte 0): 36 => 36
4086 00:56:34.431327 Write leveling (Byte 1): 30 => 30
4087 00:56:34.434027 DramcWriteLeveling(PI) end<-----
4088 00:56:34.434649
4089 00:56:34.435030 ==
4090 00:56:34.437500 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 00:56:34.440436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 00:56:34.440936 ==
4093 00:56:34.443707 [Gating] SW mode calibration
4094 00:56:34.450723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4095 00:56:34.456844 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4096 00:56:34.460147 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4097 00:56:34.463843 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4098 00:56:34.470296 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4099 00:56:34.473694 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4100 00:56:34.476762 0 9 16 | B1->B0 | 3030 2525 | 0 0 | (1 1) (0 0)
4101 00:56:34.483518 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4102 00:56:34.486811 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4103 00:56:34.489929 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4104 00:56:34.496358 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4105 00:56:34.499655 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4106 00:56:34.503250 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4107 00:56:34.509566 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
4108 00:56:34.513152 0 10 16 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
4109 00:56:34.516540 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4110 00:56:34.522731 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4111 00:56:34.526155 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4112 00:56:34.529835 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4113 00:56:34.536251 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4114 00:56:34.539228 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4115 00:56:34.542562 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4116 00:56:34.549693 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 00:56:34.552258 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 00:56:34.555920 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 00:56:34.562312 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 00:56:34.565823 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 00:56:34.569451 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 00:56:34.575951 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 00:56:34.578898 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 00:56:34.582852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 00:56:34.589070 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 00:56:34.592594 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4127 00:56:34.595680 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4128 00:56:34.602147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4129 00:56:34.605638 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4130 00:56:34.608918 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4131 00:56:34.615294 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4132 00:56:34.619222 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4133 00:56:34.621810 Total UI for P1: 0, mck2ui 16
4134 00:56:34.624987 best dqsien dly found for B0: ( 0, 13, 14)
4135 00:56:34.628930 Total UI for P1: 0, mck2ui 16
4136 00:56:34.631583 best dqsien dly found for B1: ( 0, 13, 14)
4137 00:56:34.634800 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4138 00:56:34.638393 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4139 00:56:34.638969
4140 00:56:34.641612 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4141 00:56:34.648543 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4142 00:56:34.649238 [Gating] SW calibration Done
4143 00:56:34.649621 ==
4144 00:56:34.651768 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 00:56:34.658252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 00:56:34.658719 ==
4147 00:56:34.659090 RX Vref Scan: 0
4148 00:56:34.659437
4149 00:56:34.661033 RX Vref 0 -> 0, step: 1
4150 00:56:34.661497
4151 00:56:34.664745 RX Delay -230 -> 252, step: 16
4152 00:56:34.667804 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4153 00:56:34.671360 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4154 00:56:34.678341 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4155 00:56:34.681212 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4156 00:56:34.684940 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4157 00:56:34.687610 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4158 00:56:34.691411 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4159 00:56:34.697900 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4160 00:56:34.701052 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4161 00:56:34.704212 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4162 00:56:34.707601 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4163 00:56:34.714355 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4164 00:56:34.717667 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4165 00:56:34.720515 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4166 00:56:34.723753 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4167 00:56:34.730558 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4168 00:56:34.730987 ==
4169 00:56:34.734088 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 00:56:34.737070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 00:56:34.737297 ==
4172 00:56:34.737478 DQS Delay:
4173 00:56:34.740263 DQS0 = 0, DQS1 = 0
4174 00:56:34.740490 DQM Delay:
4175 00:56:34.743868 DQM0 = 45, DQM1 = 30
4176 00:56:34.744082 DQ Delay:
4177 00:56:34.746829 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =41
4178 00:56:34.749939 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4179 00:56:34.753308 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4180 00:56:34.756576 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4181 00:56:34.756694
4182 00:56:34.756786
4183 00:56:34.756870 ==
4184 00:56:34.759792 Dram Type= 6, Freq= 0, CH_0, rank 0
4185 00:56:34.763213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 00:56:34.766308 ==
4187 00:56:34.766410
4188 00:56:34.766492
4189 00:56:34.766567 TX Vref Scan disable
4190 00:56:34.769633 == TX Byte 0 ==
4191 00:56:34.772986 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4192 00:56:34.779680 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4193 00:56:34.779792 == TX Byte 1 ==
4194 00:56:34.782836 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4195 00:56:34.789387 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4196 00:56:34.789551 ==
4197 00:56:34.792580 Dram Type= 6, Freq= 0, CH_0, rank 0
4198 00:56:34.796017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 00:56:34.796124 ==
4200 00:56:34.796218
4201 00:56:34.796318
4202 00:56:34.799480 TX Vref Scan disable
4203 00:56:34.803074 == TX Byte 0 ==
4204 00:56:34.806166 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4205 00:56:34.809234 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4206 00:56:34.812396 == TX Byte 1 ==
4207 00:56:34.816015 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4208 00:56:34.819409 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4209 00:56:34.819571
4210 00:56:34.819720 [DATLAT]
4211 00:56:34.822540 Freq=600, CH0 RK0
4212 00:56:34.822691
4213 00:56:34.825759 DATLAT Default: 0x9
4214 00:56:34.825881 0, 0xFFFF, sum = 0
4215 00:56:34.829236 1, 0xFFFF, sum = 0
4216 00:56:34.829352 2, 0xFFFF, sum = 0
4217 00:56:34.832680 3, 0xFFFF, sum = 0
4218 00:56:34.833198 4, 0xFFFF, sum = 0
4219 00:56:34.836293 5, 0xFFFF, sum = 0
4220 00:56:34.836838 6, 0xFFFF, sum = 0
4221 00:56:34.839452 7, 0xFFFF, sum = 0
4222 00:56:34.840024 8, 0x0, sum = 1
4223 00:56:34.842656 9, 0x0, sum = 2
4224 00:56:34.843119 10, 0x0, sum = 3
4225 00:56:34.846018 11, 0x0, sum = 4
4226 00:56:34.846493 best_step = 9
4227 00:56:34.846832
4228 00:56:34.847149 ==
4229 00:56:34.849591 Dram Type= 6, Freq= 0, CH_0, rank 0
4230 00:56:34.852663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 00:56:34.853088 ==
4232 00:56:34.855803 RX Vref Scan: 1
4233 00:56:34.856262
4234 00:56:34.859221 RX Vref 0 -> 0, step: 1
4235 00:56:34.859643
4236 00:56:34.859982 RX Delay -195 -> 252, step: 8
4237 00:56:34.860295
4238 00:56:34.862641 Set Vref, RX VrefLevel [Byte0]: 59
4239 00:56:34.865741 [Byte1]: 58
4240 00:56:34.870541
4241 00:56:34.870967 Final RX Vref Byte 0 = 59 to rank0
4242 00:56:34.873834 Final RX Vref Byte 1 = 58 to rank0
4243 00:56:34.877505 Final RX Vref Byte 0 = 59 to rank1
4244 00:56:34.880702 Final RX Vref Byte 1 = 58 to rank1==
4245 00:56:34.884237 Dram Type= 6, Freq= 0, CH_0, rank 0
4246 00:56:34.890324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 00:56:34.890764 ==
4248 00:56:34.891103 DQS Delay:
4249 00:56:34.893766 DQS0 = 0, DQS1 = 0
4250 00:56:34.894259 DQM Delay:
4251 00:56:34.894611 DQM0 = 43, DQM1 = 32
4252 00:56:34.896934 DQ Delay:
4253 00:56:34.900097 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4254 00:56:34.903745 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4255 00:56:34.907015 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4256 00:56:34.910213 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4257 00:56:34.910645
4258 00:56:34.910981
4259 00:56:34.916969 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4260 00:56:34.920234 CH0 RK0: MR19=808, MR18=6C43
4261 00:56:34.927166 CH0_RK0: MR19=0x808, MR18=0x6C43, DQSOSC=389, MR23=63, INC=173, DEC=115
4262 00:56:34.927739
4263 00:56:34.929952 ----->DramcWriteLeveling(PI) begin...
4264 00:56:34.930471 ==
4265 00:56:34.933461 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 00:56:34.937155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 00:56:34.937798 ==
4268 00:56:34.939812 Write leveling (Byte 0): 33 => 33
4269 00:56:34.943560 Write leveling (Byte 1): 32 => 32
4270 00:56:34.946595 DramcWriteLeveling(PI) end<-----
4271 00:56:34.947164
4272 00:56:34.947533 ==
4273 00:56:34.950360 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 00:56:34.953152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 00:56:34.956214 ==
4276 00:56:34.956781 [Gating] SW mode calibration
4277 00:56:34.966614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4278 00:56:34.969472 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4279 00:56:34.973413 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4280 00:56:34.979734 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4281 00:56:34.982978 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4282 00:56:34.986395 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4283 00:56:34.992811 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4284 00:56:34.996484 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 00:56:34.999303 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 00:56:35.006239 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 00:56:35.009474 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4288 00:56:35.012547 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4289 00:56:35.019344 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 00:56:35.022385 0 10 12 | B1->B0 | 2929 2c2c | 0 0 | (0 0) (0 0)
4291 00:56:35.025717 0 10 16 | B1->B0 | 3736 3d3d | 1 0 | (0 0) (0 0)
4292 00:56:35.032846 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 00:56:35.035928 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 00:56:35.038878 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 00:56:35.045314 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4296 00:56:35.048811 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 00:56:35.052404 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 00:56:35.059232 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4299 00:56:35.062156 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 00:56:35.065293 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 00:56:35.072239 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 00:56:35.075463 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 00:56:35.078534 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 00:56:35.085412 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 00:56:35.088623 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 00:56:35.092259 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 00:56:35.098361 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 00:56:35.101655 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 00:56:35.105146 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 00:56:35.111588 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 00:56:35.115122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 00:56:35.118281 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 00:56:35.124971 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 00:56:35.128212 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4315 00:56:35.131147 Total UI for P1: 0, mck2ui 16
4316 00:56:35.134336 best dqsien dly found for B0: ( 0, 13, 10)
4317 00:56:35.138000 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4318 00:56:35.141590 Total UI for P1: 0, mck2ui 16
4319 00:56:35.144490 best dqsien dly found for B1: ( 0, 13, 12)
4320 00:56:35.147769 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4321 00:56:35.151089 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4322 00:56:35.154909
4323 00:56:35.157952 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4324 00:56:35.161600 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4325 00:56:35.164263 [Gating] SW calibration Done
4326 00:56:35.164739 ==
4327 00:56:35.167698 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 00:56:35.171113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 00:56:35.171705 ==
4330 00:56:35.172083 RX Vref Scan: 0
4331 00:56:35.174138
4332 00:56:35.174654 RX Vref 0 -> 0, step: 1
4333 00:56:35.175030
4334 00:56:35.177719 RX Delay -230 -> 252, step: 16
4335 00:56:35.181197 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4336 00:56:35.187480 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4337 00:56:35.191249 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4338 00:56:35.194318 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4339 00:56:35.197500 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4340 00:56:35.200594 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4341 00:56:35.207814 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4342 00:56:35.210257 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4343 00:56:35.213914 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4344 00:56:35.217377 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4345 00:56:35.223942 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4346 00:56:35.226980 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4347 00:56:35.230323 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4348 00:56:35.233512 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4349 00:56:35.240739 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4350 00:56:35.243492 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4351 00:56:35.244018 ==
4352 00:56:35.246963 Dram Type= 6, Freq= 0, CH_0, rank 1
4353 00:56:35.250150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 00:56:35.250762 ==
4355 00:56:35.253440 DQS Delay:
4356 00:56:35.253913 DQS0 = 0, DQS1 = 0
4357 00:56:35.254338 DQM Delay:
4358 00:56:35.256824 DQM0 = 42, DQM1 = 35
4359 00:56:35.257296 DQ Delay:
4360 00:56:35.259886 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4361 00:56:35.263158 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4362 00:56:35.266700 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4363 00:56:35.269839 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4364 00:56:35.270312
4365 00:56:35.270658
4366 00:56:35.270972 ==
4367 00:56:35.273113 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 00:56:35.279989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 00:56:35.280419 ==
4370 00:56:35.280761
4371 00:56:35.281073
4372 00:56:35.281374 TX Vref Scan disable
4373 00:56:35.284016 == TX Byte 0 ==
4374 00:56:35.286963 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4375 00:56:35.293525 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4376 00:56:35.294217 == TX Byte 1 ==
4377 00:56:35.296806 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4378 00:56:35.303604 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4379 00:56:35.304031 ==
4380 00:56:35.306453 Dram Type= 6, Freq= 0, CH_0, rank 1
4381 00:56:35.310030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 00:56:35.310510 ==
4383 00:56:35.310852
4384 00:56:35.311164
4385 00:56:35.313254 TX Vref Scan disable
4386 00:56:35.316745 == TX Byte 0 ==
4387 00:56:35.319707 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4388 00:56:35.323063 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4389 00:56:35.326491 == TX Byte 1 ==
4390 00:56:35.329783 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4391 00:56:35.333188 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4392 00:56:35.333717
4393 00:56:35.336140 [DATLAT]
4394 00:56:35.336566 Freq=600, CH0 RK1
4395 00:56:35.336903
4396 00:56:35.339535 DATLAT Default: 0x9
4397 00:56:35.339961 0, 0xFFFF, sum = 0
4398 00:56:35.342618 1, 0xFFFF, sum = 0
4399 00:56:35.343049 2, 0xFFFF, sum = 0
4400 00:56:35.345967 3, 0xFFFF, sum = 0
4401 00:56:35.346487 4, 0xFFFF, sum = 0
4402 00:56:35.349187 5, 0xFFFF, sum = 0
4403 00:56:35.349730 6, 0xFFFF, sum = 0
4404 00:56:35.352490 7, 0xFFFF, sum = 0
4405 00:56:35.353143 8, 0x0, sum = 1
4406 00:56:35.355992 9, 0x0, sum = 2
4407 00:56:35.356475 10, 0x0, sum = 3
4408 00:56:35.359118 11, 0x0, sum = 4
4409 00:56:35.359654 best_step = 9
4410 00:56:35.359994
4411 00:56:35.360307 ==
4412 00:56:35.362826 Dram Type= 6, Freq= 0, CH_0, rank 1
4413 00:56:35.365603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 00:56:35.369565 ==
4415 00:56:35.369989 RX Vref Scan: 0
4416 00:56:35.370377
4417 00:56:35.372370 RX Vref 0 -> 0, step: 1
4418 00:56:35.372903
4419 00:56:35.375754 RX Delay -195 -> 252, step: 8
4420 00:56:35.378621 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4421 00:56:35.385386 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4422 00:56:35.388935 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4423 00:56:35.392423 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4424 00:56:35.395238 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4425 00:56:35.398742 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4426 00:56:35.405127 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4427 00:56:35.408500 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4428 00:56:35.411729 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4429 00:56:35.414868 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4430 00:56:35.421317 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4431 00:56:35.424765 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4432 00:56:35.428673 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4433 00:56:35.431588 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4434 00:56:35.437881 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4435 00:56:35.442038 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4436 00:56:35.442658 ==
4437 00:56:35.444758 Dram Type= 6, Freq= 0, CH_0, rank 1
4438 00:56:35.448251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 00:56:35.448678 ==
4440 00:56:35.451268 DQS Delay:
4441 00:56:35.451690 DQS0 = 0, DQS1 = 0
4442 00:56:35.452025 DQM Delay:
4443 00:56:35.454629 DQM0 = 41, DQM1 = 36
4444 00:56:35.455086 DQ Delay:
4445 00:56:35.457987 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =40
4446 00:56:35.461524 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4447 00:56:35.464850 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4448 00:56:35.467578 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4449 00:56:35.468010
4450 00:56:35.468350
4451 00:56:35.477574 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4452 00:56:35.481221 CH0 RK1: MR19=808, MR18=5E12
4453 00:56:35.484147 CH0_RK1: MR19=0x808, MR18=0x5E12, DQSOSC=392, MR23=63, INC=170, DEC=113
4454 00:56:35.487832 [RxdqsGatingPostProcess] freq 600
4455 00:56:35.494333 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4456 00:56:35.497651 Pre-setting of DQS Precalculation
4457 00:56:35.500631 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4458 00:56:35.503973 ==
4459 00:56:35.504444 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 00:56:35.510401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 00:56:35.510970 ==
4462 00:56:35.513742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4463 00:56:35.520736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4464 00:56:35.524423 [CA 0] Center 35 (5~66) winsize 62
4465 00:56:35.527709 [CA 1] Center 35 (5~66) winsize 62
4466 00:56:35.531258 [CA 2] Center 34 (4~65) winsize 62
4467 00:56:35.534088 [CA 3] Center 33 (3~64) winsize 62
4468 00:56:35.537665 [CA 4] Center 34 (4~65) winsize 62
4469 00:56:35.540775 [CA 5] Center 33 (3~64) winsize 62
4470 00:56:35.541203
4471 00:56:35.544168 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4472 00:56:35.544651
4473 00:56:35.547548 [CATrainingPosCal] consider 1 rank data
4474 00:56:35.550876 u2DelayCellTimex100 = 270/100 ps
4475 00:56:35.554244 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4476 00:56:35.560518 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4477 00:56:35.564144 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4478 00:56:35.567149 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4479 00:56:35.570732 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4480 00:56:35.573448 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4481 00:56:35.573879
4482 00:56:35.576836 CA PerBit enable=1, Macro0, CA PI delay=33
4483 00:56:35.577264
4484 00:56:35.580308 [CBTSetCACLKResult] CA Dly = 33
4485 00:56:35.583657 CS Dly: 4 (0~35)
4486 00:56:35.584188 ==
4487 00:56:35.586805 Dram Type= 6, Freq= 0, CH_1, rank 1
4488 00:56:35.590275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 00:56:35.590836 ==
4490 00:56:35.596740 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4491 00:56:35.600419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4492 00:56:35.604594 [CA 0] Center 35 (5~66) winsize 62
4493 00:56:35.607888 [CA 1] Center 36 (6~66) winsize 61
4494 00:56:35.610754 [CA 2] Center 34 (4~65) winsize 62
4495 00:56:35.614878 [CA 3] Center 34 (3~65) winsize 63
4496 00:56:35.617582 [CA 4] Center 34 (3~65) winsize 63
4497 00:56:35.620862 [CA 5] Center 34 (3~65) winsize 63
4498 00:56:35.621440
4499 00:56:35.624804 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4500 00:56:35.625610
4501 00:56:35.627410 [CATrainingPosCal] consider 2 rank data
4502 00:56:35.630781 u2DelayCellTimex100 = 270/100 ps
4503 00:56:35.634362 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4504 00:56:35.641318 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4505 00:56:35.644153 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4506 00:56:35.648065 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4507 00:56:35.651072 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4508 00:56:35.654147 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4509 00:56:35.654762
4510 00:56:35.657047 CA PerBit enable=1, Macro0, CA PI delay=33
4511 00:56:35.657522
4512 00:56:35.660509 [CBTSetCACLKResult] CA Dly = 33
4513 00:56:35.664289 CS Dly: 5 (0~37)
4514 00:56:35.664862
4515 00:56:35.666937 ----->DramcWriteLeveling(PI) begin...
4516 00:56:35.667559 ==
4517 00:56:35.670934 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 00:56:35.673762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 00:56:35.674413 ==
4520 00:56:35.677827 Write leveling (Byte 0): 31 => 31
4521 00:56:35.680267 Write leveling (Byte 1): 29 => 29
4522 00:56:35.683873 DramcWriteLeveling(PI) end<-----
4523 00:56:35.684506
4524 00:56:35.685090 ==
4525 00:56:35.686914 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 00:56:35.690388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 00:56:35.690868 ==
4528 00:56:35.693476 [Gating] SW mode calibration
4529 00:56:35.700180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4530 00:56:35.707150 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4531 00:56:35.710284 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4532 00:56:35.713659 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4533 00:56:35.720382 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4534 00:56:35.723726 0 9 12 | B1->B0 | 3030 3030 | 1 1 | (1 0) (1 0)
4535 00:56:35.726793 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4536 00:56:35.733662 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4537 00:56:35.737022 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4538 00:56:35.739941 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4539 00:56:35.746500 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4540 00:56:35.749582 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4541 00:56:35.752960 0 10 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
4542 00:56:35.759788 0 10 12 | B1->B0 | 2d2d 3939 | 1 0 | (0 0) (0 0)
4543 00:56:35.762765 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4544 00:56:35.766112 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4545 00:56:35.772763 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4546 00:56:35.776390 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4547 00:56:35.779269 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4548 00:56:35.785738 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4549 00:56:35.789510 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4550 00:56:35.792600 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4551 00:56:35.799057 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 00:56:35.802130 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 00:56:35.805352 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 00:56:35.812128 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 00:56:35.815565 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 00:56:35.818830 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 00:56:35.825744 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 00:56:35.828586 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 00:56:35.831549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 00:56:35.839061 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 00:56:35.841522 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 00:56:35.844949 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4563 00:56:35.851657 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4564 00:56:35.855146 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4565 00:56:35.858126 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4566 00:56:35.865092 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4567 00:56:35.868112 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4568 00:56:35.871576 Total UI for P1: 0, mck2ui 16
4569 00:56:35.874544 best dqsien dly found for B0: ( 0, 13, 10)
4570 00:56:35.877955 Total UI for P1: 0, mck2ui 16
4571 00:56:35.881686 best dqsien dly found for B1: ( 0, 13, 12)
4572 00:56:35.884710 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4573 00:56:35.888108 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4574 00:56:35.888897
4575 00:56:35.891069 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4576 00:56:35.897901 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4577 00:56:35.898415 [Gating] SW calibration Done
4578 00:56:35.898797 ==
4579 00:56:35.901410 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 00:56:35.908129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 00:56:35.908706 ==
4582 00:56:35.909093 RX Vref Scan: 0
4583 00:56:35.909445
4584 00:56:35.911382 RX Vref 0 -> 0, step: 1
4585 00:56:35.911852
4586 00:56:35.914508 RX Delay -230 -> 252, step: 16
4587 00:56:35.917702 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4588 00:56:35.921325 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4589 00:56:35.924325 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4590 00:56:35.930937 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4591 00:56:35.934609 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4592 00:56:35.938127 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4593 00:56:35.940556 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4594 00:56:35.947472 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4595 00:56:35.950644 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4596 00:56:35.953883 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4597 00:56:35.957067 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4598 00:56:35.964094 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4599 00:56:35.966920 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4600 00:56:35.970339 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4601 00:56:35.973532 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4602 00:56:35.980112 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4603 00:56:35.980670 ==
4604 00:56:35.983419 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 00:56:35.986708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 00:56:35.987184 ==
4607 00:56:35.987558 DQS Delay:
4608 00:56:35.990157 DQS0 = 0, DQS1 = 0
4609 00:56:35.990666 DQM Delay:
4610 00:56:35.993097 DQM0 = 45, DQM1 = 35
4611 00:56:35.993566 DQ Delay:
4612 00:56:35.996970 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4613 00:56:35.999943 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4614 00:56:36.003598 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4615 00:56:36.006352 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4616 00:56:36.006829
4617 00:56:36.007202
4618 00:56:36.007549 ==
4619 00:56:36.009883 Dram Type= 6, Freq= 0, CH_1, rank 0
4620 00:56:36.012999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 00:56:36.016500 ==
4622 00:56:36.016982
4623 00:56:36.017357
4624 00:56:36.017705 TX Vref Scan disable
4625 00:56:36.019766 == TX Byte 0 ==
4626 00:56:36.023119 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4627 00:56:36.029641 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4628 00:56:36.030268 == TX Byte 1 ==
4629 00:56:36.033248 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4630 00:56:36.039268 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4631 00:56:36.039834 ==
4632 00:56:36.042646 Dram Type= 6, Freq= 0, CH_1, rank 0
4633 00:56:36.045950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 00:56:36.046486 ==
4635 00:56:36.046867
4636 00:56:36.047215
4637 00:56:36.049196 TX Vref Scan disable
4638 00:56:36.052671 == TX Byte 0 ==
4639 00:56:36.055538 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4640 00:56:36.059025 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4641 00:56:36.062855 == TX Byte 1 ==
4642 00:56:36.065862 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4643 00:56:36.069192 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4644 00:56:36.069757
4645 00:56:36.072263 [DATLAT]
4646 00:56:36.072751 Freq=600, CH1 RK0
4647 00:56:36.073117
4648 00:56:36.075448 DATLAT Default: 0x9
4649 00:56:36.075913 0, 0xFFFF, sum = 0
4650 00:56:36.078662 1, 0xFFFF, sum = 0
4651 00:56:36.079133 2, 0xFFFF, sum = 0
4652 00:56:36.082326 3, 0xFFFF, sum = 0
4653 00:56:36.082851 4, 0xFFFF, sum = 0
4654 00:56:36.085642 5, 0xFFFF, sum = 0
4655 00:56:36.086247 6, 0xFFFF, sum = 0
4656 00:56:36.089027 7, 0xFFFF, sum = 0
4657 00:56:36.089598 8, 0x0, sum = 1
4658 00:56:36.092188 9, 0x0, sum = 2
4659 00:56:36.092658 10, 0x0, sum = 3
4660 00:56:36.095758 11, 0x0, sum = 4
4661 00:56:36.096330 best_step = 9
4662 00:56:36.096702
4663 00:56:36.097077 ==
4664 00:56:36.098542 Dram Type= 6, Freq= 0, CH_1, rank 0
4665 00:56:36.102446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 00:56:36.102926 ==
4667 00:56:36.105592 RX Vref Scan: 1
4668 00:56:36.106061
4669 00:56:36.109106 RX Vref 0 -> 0, step: 1
4670 00:56:36.109698
4671 00:56:36.110074 RX Delay -195 -> 252, step: 8
4672 00:56:36.112193
4673 00:56:36.112661 Set Vref, RX VrefLevel [Byte0]: 52
4674 00:56:36.115273 [Byte1]: 54
4675 00:56:36.120230
4676 00:56:36.120802 Final RX Vref Byte 0 = 52 to rank0
4677 00:56:36.123896 Final RX Vref Byte 1 = 54 to rank0
4678 00:56:36.126922 Final RX Vref Byte 0 = 52 to rank1
4679 00:56:36.130225 Final RX Vref Byte 1 = 54 to rank1==
4680 00:56:36.133794 Dram Type= 6, Freq= 0, CH_1, rank 0
4681 00:56:36.140055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 00:56:36.140641 ==
4683 00:56:36.141026 DQS Delay:
4684 00:56:36.143333 DQS0 = 0, DQS1 = 0
4685 00:56:36.143821 DQM Delay:
4686 00:56:36.144197 DQM0 = 47, DQM1 = 37
4687 00:56:36.146675 DQ Delay:
4688 00:56:36.149837 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4689 00:56:36.153458 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4690 00:56:36.156517 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4691 00:56:36.160470 DQ12 =48, DQ13 =40, DQ14 =48, DQ15 =48
4692 00:56:36.161048
4693 00:56:36.161419
4694 00:56:36.166862 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d32, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4695 00:56:36.169784 CH1 RK0: MR19=808, MR18=4D32
4696 00:56:36.176522 CH1_RK0: MR19=0x808, MR18=0x4D32, DQSOSC=395, MR23=63, INC=168, DEC=112
4697 00:56:36.177100
4698 00:56:36.179969 ----->DramcWriteLeveling(PI) begin...
4699 00:56:36.180545 ==
4700 00:56:36.183118 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 00:56:36.186388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 00:56:36.186956 ==
4703 00:56:36.189500 Write leveling (Byte 0): 28 => 28
4704 00:56:36.192926 Write leveling (Byte 1): 28 => 28
4705 00:56:36.196456 DramcWriteLeveling(PI) end<-----
4706 00:56:36.197039
4707 00:56:36.197417 ==
4708 00:56:36.199665 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 00:56:36.202991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 00:56:36.206157 ==
4711 00:56:36.206672 [Gating] SW mode calibration
4712 00:56:36.213125 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4713 00:56:36.219613 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4714 00:56:36.222583 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4715 00:56:36.229316 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4716 00:56:36.233026 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4717 00:56:36.235578 0 9 12 | B1->B0 | 3131 3333 | 0 0 | (1 1) (0 0)
4718 00:56:36.242433 0 9 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
4719 00:56:36.245529 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4720 00:56:36.248991 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4721 00:56:36.255546 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4722 00:56:36.258859 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4723 00:56:36.262762 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4724 00:56:36.268768 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4725 00:56:36.272220 0 10 12 | B1->B0 | 3838 2b2b | 0 0 | (0 0) (1 1)
4726 00:56:36.275392 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
4727 00:56:36.282145 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4728 00:56:36.285385 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4729 00:56:36.289189 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4730 00:56:36.294891 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4731 00:56:36.298490 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4732 00:56:36.301641 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4733 00:56:36.308753 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4734 00:56:36.311527 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 00:56:36.315067 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 00:56:36.321464 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 00:56:36.324815 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 00:56:36.328203 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 00:56:36.334562 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 00:56:36.338246 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 00:56:36.341941 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 00:56:36.348276 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 00:56:36.350862 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 00:56:36.354407 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 00:56:36.361165 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 00:56:36.364478 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 00:56:36.368055 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4748 00:56:36.374541 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4749 00:56:36.377624 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4750 00:56:36.380542 Total UI for P1: 0, mck2ui 16
4751 00:56:36.384585 best dqsien dly found for B0: ( 0, 13, 10)
4752 00:56:36.387348 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4753 00:56:36.391055 Total UI for P1: 0, mck2ui 16
4754 00:56:36.394473 best dqsien dly found for B1: ( 0, 13, 12)
4755 00:56:36.397347 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4756 00:56:36.400586 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4757 00:56:36.403976
4758 00:56:36.407222 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4759 00:56:36.410422 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4760 00:56:36.413963 [Gating] SW calibration Done
4761 00:56:36.414576 ==
4762 00:56:36.417572 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 00:56:36.422809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 00:56:36.423428 ==
4765 00:56:36.424039 RX Vref Scan: 0
4766 00:56:36.425020
4767 00:56:36.425419 RX Vref 0 -> 0, step: 1
4768 00:56:36.425773
4769 00:56:36.427073 RX Delay -230 -> 252, step: 16
4770 00:56:36.430510 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4771 00:56:36.436844 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4772 00:56:36.440399 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4773 00:56:36.443598 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4774 00:56:36.447084 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4775 00:56:36.450020 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4776 00:56:36.456642 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4777 00:56:36.459823 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4778 00:56:36.463417 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4779 00:56:36.466624 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4780 00:56:36.473052 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4781 00:56:36.476409 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4782 00:56:36.479975 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4783 00:56:36.483210 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4784 00:56:36.489344 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4785 00:56:36.493020 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4786 00:56:36.493590 ==
4787 00:56:36.496362 Dram Type= 6, Freq= 0, CH_1, rank 1
4788 00:56:36.499659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4789 00:56:36.500138 ==
4790 00:56:36.502923 DQS Delay:
4791 00:56:36.503483 DQS0 = 0, DQS1 = 0
4792 00:56:36.506138 DQM Delay:
4793 00:56:36.506644 DQM0 = 46, DQM1 = 41
4794 00:56:36.507020 DQ Delay:
4795 00:56:36.509307 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4796 00:56:36.512957 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4797 00:56:36.515846 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4798 00:56:36.519369 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4799 00:56:36.520122
4800 00:56:36.520571
4801 00:56:36.522233 ==
4802 00:56:36.526020 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 00:56:36.528939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 00:56:36.529419 ==
4805 00:56:36.529798
4806 00:56:36.530310
4807 00:56:36.532483 TX Vref Scan disable
4808 00:56:36.533127 == TX Byte 0 ==
4809 00:56:36.539094 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4810 00:56:36.542106 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4811 00:56:36.542707 == TX Byte 1 ==
4812 00:56:36.548669 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4813 00:56:36.551994 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4814 00:56:36.552472 ==
4815 00:56:36.555500 Dram Type= 6, Freq= 0, CH_1, rank 1
4816 00:56:36.558501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4817 00:56:36.558993 ==
4818 00:56:36.559376
4819 00:56:36.559724
4820 00:56:36.561862 TX Vref Scan disable
4821 00:56:36.565602 == TX Byte 0 ==
4822 00:56:36.568593 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4823 00:56:36.571831 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4824 00:56:36.575386 == TX Byte 1 ==
4825 00:56:36.578601 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4826 00:56:36.581728 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4827 00:56:36.582360
4828 00:56:36.585363 [DATLAT]
4829 00:56:36.585943 Freq=600, CH1 RK1
4830 00:56:36.586390
4831 00:56:36.588684 DATLAT Default: 0x9
4832 00:56:36.589158 0, 0xFFFF, sum = 0
4833 00:56:36.591648 1, 0xFFFF, sum = 0
4834 00:56:36.592249 2, 0xFFFF, sum = 0
4835 00:56:36.595012 3, 0xFFFF, sum = 0
4836 00:56:36.595509 4, 0xFFFF, sum = 0
4837 00:56:36.598252 5, 0xFFFF, sum = 0
4838 00:56:36.598739 6, 0xFFFF, sum = 0
4839 00:56:36.601726 7, 0xFFFF, sum = 0
4840 00:56:36.602246 8, 0x0, sum = 1
4841 00:56:36.605197 9, 0x0, sum = 2
4842 00:56:36.605677 10, 0x0, sum = 3
4843 00:56:36.608298 11, 0x0, sum = 4
4844 00:56:36.608776 best_step = 9
4845 00:56:36.609150
4846 00:56:36.609497 ==
4847 00:56:36.611811 Dram Type= 6, Freq= 0, CH_1, rank 1
4848 00:56:36.618224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4849 00:56:36.618663 ==
4850 00:56:36.619010 RX Vref Scan: 0
4851 00:56:36.619334
4852 00:56:36.621334 RX Vref 0 -> 0, step: 1
4853 00:56:36.621760
4854 00:56:36.624796 RX Delay -179 -> 252, step: 8
4855 00:56:36.628438 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4856 00:56:36.635435 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4857 00:56:36.638071 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4858 00:56:36.641130 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4859 00:56:36.644694 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4860 00:56:36.647780 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4861 00:56:36.654269 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4862 00:56:36.657727 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4863 00:56:36.661136 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4864 00:56:36.664711 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4865 00:56:36.670866 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4866 00:56:36.674551 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4867 00:56:36.677597 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4868 00:56:36.680841 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4869 00:56:36.687788 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4870 00:56:36.690700 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4871 00:56:36.691152 ==
4872 00:56:36.694221 Dram Type= 6, Freq= 0, CH_1, rank 1
4873 00:56:36.697555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4874 00:56:36.698133 ==
4875 00:56:36.701263 DQS Delay:
4876 00:56:36.701735 DQS0 = 0, DQS1 = 0
4877 00:56:36.702111 DQM Delay:
4878 00:56:36.703741 DQM0 = 45, DQM1 = 37
4879 00:56:36.704186 DQ Delay:
4880 00:56:36.707338 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4881 00:56:36.710839 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4882 00:56:36.713934 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4883 00:56:36.717386 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4884 00:56:36.717811
4885 00:56:36.718147
4886 00:56:36.727289 [DQSOSCAuto] RK1, (LSB)MR18= 0x3127, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4887 00:56:36.730307 CH1 RK1: MR19=808, MR18=3127
4888 00:56:36.733455 CH1_RK1: MR19=0x808, MR18=0x3127, DQSOSC=400, MR23=63, INC=163, DEC=109
4889 00:56:36.737053 [RxdqsGatingPostProcess] freq 600
4890 00:56:36.743446 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4891 00:56:36.747265 Pre-setting of DQS Precalculation
4892 00:56:36.750221 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4893 00:56:36.759967 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4894 00:56:36.766677 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4895 00:56:36.767226
4896 00:56:36.767567
4897 00:56:36.769760 [Calibration Summary] 1200 Mbps
4898 00:56:36.770240 CH 0, Rank 0
4899 00:56:36.773344 SW Impedance : PASS
4900 00:56:36.773865 DUTY Scan : NO K
4901 00:56:36.776580 ZQ Calibration : PASS
4902 00:56:36.780559 Jitter Meter : NO K
4903 00:56:36.781083 CBT Training : PASS
4904 00:56:36.783380 Write leveling : PASS
4905 00:56:36.786881 RX DQS gating : PASS
4906 00:56:36.787406 RX DQ/DQS(RDDQC) : PASS
4907 00:56:36.790073 TX DQ/DQS : PASS
4908 00:56:36.793084 RX DATLAT : PASS
4909 00:56:36.793575 RX DQ/DQS(Engine): PASS
4910 00:56:36.796293 TX OE : NO K
4911 00:56:36.796828 All Pass.
4912 00:56:36.797170
4913 00:56:36.799907 CH 0, Rank 1
4914 00:56:36.800332 SW Impedance : PASS
4915 00:56:36.802644 DUTY Scan : NO K
4916 00:56:36.806115 ZQ Calibration : PASS
4917 00:56:36.806690 Jitter Meter : NO K
4918 00:56:36.809729 CBT Training : PASS
4919 00:56:36.813152 Write leveling : PASS
4920 00:56:36.813677 RX DQS gating : PASS
4921 00:56:36.816598 RX DQ/DQS(RDDQC) : PASS
4922 00:56:36.817155 TX DQ/DQS : PASS
4923 00:56:36.819775 RX DATLAT : PASS
4924 00:56:36.822698 RX DQ/DQS(Engine): PASS
4925 00:56:36.823123 TX OE : NO K
4926 00:56:36.825877 All Pass.
4927 00:56:36.826328
4928 00:56:36.826669 CH 1, Rank 0
4929 00:56:36.829481 SW Impedance : PASS
4930 00:56:36.829905 DUTY Scan : NO K
4931 00:56:36.833171 ZQ Calibration : PASS
4932 00:56:36.835867 Jitter Meter : NO K
4933 00:56:36.836294 CBT Training : PASS
4934 00:56:36.839118 Write leveling : PASS
4935 00:56:36.843124 RX DQS gating : PASS
4936 00:56:36.843688 RX DQ/DQS(RDDQC) : PASS
4937 00:56:36.846243 TX DQ/DQS : PASS
4938 00:56:36.849391 RX DATLAT : PASS
4939 00:56:36.849814 RX DQ/DQS(Engine): PASS
4940 00:56:36.852238 TX OE : NO K
4941 00:56:36.852666 All Pass.
4942 00:56:36.853012
4943 00:56:36.856200 CH 1, Rank 1
4944 00:56:36.856638 SW Impedance : PASS
4945 00:56:36.859549 DUTY Scan : NO K
4946 00:56:36.862481 ZQ Calibration : PASS
4947 00:56:36.862906 Jitter Meter : NO K
4948 00:56:36.865731 CBT Training : PASS
4949 00:56:36.869408 Write leveling : PASS
4950 00:56:36.870087 RX DQS gating : PASS
4951 00:56:36.872630 RX DQ/DQS(RDDQC) : PASS
4952 00:56:36.875646 TX DQ/DQS : PASS
4953 00:56:36.876177 RX DATLAT : PASS
4954 00:56:36.878732 RX DQ/DQS(Engine): PASS
4955 00:56:36.879159 TX OE : NO K
4956 00:56:36.882903 All Pass.
4957 00:56:36.883426
4958 00:56:36.883774 DramC Write-DBI off
4959 00:56:36.885560 PER_BANK_REFRESH: Hybrid Mode
4960 00:56:36.888885 TX_TRACKING: ON
4961 00:56:36.895275 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4962 00:56:36.898487 [FAST_K] Save calibration result to emmc
4963 00:56:36.905205 dramc_set_vcore_voltage set vcore to 662500
4964 00:56:36.905738 Read voltage for 933, 3
4965 00:56:36.906121 Vio18 = 0
4966 00:56:36.908662 Vcore = 662500
4967 00:56:36.909130 Vdram = 0
4968 00:56:36.909502 Vddq = 0
4969 00:56:36.912069 Vmddr = 0
4970 00:56:36.915056 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4971 00:56:36.921810 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4972 00:56:36.925368 MEM_TYPE=3, freq_sel=17
4973 00:56:36.925973 sv_algorithm_assistance_LP4_1600
4974 00:56:36.931575 ============ PULL DRAM RESETB DOWN ============
4975 00:56:36.935146 ========== PULL DRAM RESETB DOWN end =========
4976 00:56:36.938200 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4977 00:56:36.941614 ===================================
4978 00:56:36.944749 LPDDR4 DRAM CONFIGURATION
4979 00:56:36.947940 ===================================
4980 00:56:36.951651 EX_ROW_EN[0] = 0x0
4981 00:56:36.952206 EX_ROW_EN[1] = 0x0
4982 00:56:36.955068 LP4Y_EN = 0x0
4983 00:56:36.955627 WORK_FSP = 0x0
4984 00:56:36.958027 WL = 0x3
4985 00:56:36.958631 RL = 0x3
4986 00:56:36.961557 BL = 0x2
4987 00:56:36.962117 RPST = 0x0
4988 00:56:36.964738 RD_PRE = 0x0
4989 00:56:36.967987 WR_PRE = 0x1
4990 00:56:36.968459 WR_PST = 0x0
4991 00:56:36.971452 DBI_WR = 0x0
4992 00:56:36.971922 DBI_RD = 0x0
4993 00:56:36.974809 OTF = 0x1
4994 00:56:36.978046 ===================================
4995 00:56:36.981379 ===================================
4996 00:56:36.981943 ANA top config
4997 00:56:36.984533 ===================================
4998 00:56:36.987446 DLL_ASYNC_EN = 0
4999 00:56:36.990844 ALL_SLAVE_EN = 1
5000 00:56:36.991517 NEW_RANK_MODE = 1
5001 00:56:36.994066 DLL_IDLE_MODE = 1
5002 00:56:36.997528 LP45_APHY_COMB_EN = 1
5003 00:56:37.000976 TX_ODT_DIS = 1
5004 00:56:37.004078 NEW_8X_MODE = 1
5005 00:56:37.007610 ===================================
5006 00:56:37.010821 ===================================
5007 00:56:37.011290 data_rate = 1866
5008 00:56:37.014157 CKR = 1
5009 00:56:37.017487 DQ_P2S_RATIO = 8
5010 00:56:37.020578 ===================================
5011 00:56:37.024091 CA_P2S_RATIO = 8
5012 00:56:37.027256 DQ_CA_OPEN = 0
5013 00:56:37.030318 DQ_SEMI_OPEN = 0
5014 00:56:37.030795 CA_SEMI_OPEN = 0
5015 00:56:37.033806 CA_FULL_RATE = 0
5016 00:56:37.036915 DQ_CKDIV4_EN = 1
5017 00:56:37.040642 CA_CKDIV4_EN = 1
5018 00:56:37.043506 CA_PREDIV_EN = 0
5019 00:56:37.047122 PH8_DLY = 0
5020 00:56:37.047700 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5021 00:56:37.050250 DQ_AAMCK_DIV = 4
5022 00:56:37.053542 CA_AAMCK_DIV = 4
5023 00:56:37.056790 CA_ADMCK_DIV = 4
5024 00:56:37.059994 DQ_TRACK_CA_EN = 0
5025 00:56:37.063611 CA_PICK = 933
5026 00:56:37.066541 CA_MCKIO = 933
5027 00:56:37.067017 MCKIO_SEMI = 0
5028 00:56:37.070339 PLL_FREQ = 3732
5029 00:56:37.073441 DQ_UI_PI_RATIO = 32
5030 00:56:37.076658 CA_UI_PI_RATIO = 0
5031 00:56:37.079911 ===================================
5032 00:56:37.083084 ===================================
5033 00:56:37.086430 memory_type:LPDDR4
5034 00:56:37.087002 GP_NUM : 10
5035 00:56:37.089908 SRAM_EN : 1
5036 00:56:37.093290 MD32_EN : 0
5037 00:56:37.096442 ===================================
5038 00:56:37.096915 [ANA_INIT] >>>>>>>>>>>>>>
5039 00:56:37.100135 <<<<<< [CONFIGURE PHASE]: ANA_TX
5040 00:56:37.103052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5041 00:56:37.106091 ===================================
5042 00:56:37.109703 data_rate = 1866,PCW = 0X8f00
5043 00:56:37.112959 ===================================
5044 00:56:37.116257 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5045 00:56:37.122413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5046 00:56:37.129026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5047 00:56:37.132930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5048 00:56:37.135669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5049 00:56:37.139360 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5050 00:56:37.142126 [ANA_INIT] flow start
5051 00:56:37.142643 [ANA_INIT] PLL >>>>>>>>
5052 00:56:37.145522 [ANA_INIT] PLL <<<<<<<<
5053 00:56:37.149220 [ANA_INIT] MIDPI >>>>>>>>
5054 00:56:37.149805 [ANA_INIT] MIDPI <<<<<<<<
5055 00:56:37.152369 [ANA_INIT] DLL >>>>>>>>
5056 00:56:37.155752 [ANA_INIT] flow end
5057 00:56:37.159279 ============ LP4 DIFF to SE enter ============
5058 00:56:37.162200 ============ LP4 DIFF to SE exit ============
5059 00:56:37.165866 [ANA_INIT] <<<<<<<<<<<<<
5060 00:56:37.168931 [Flow] Enable top DCM control >>>>>
5061 00:56:37.172433 [Flow] Enable top DCM control <<<<<
5062 00:56:37.175513 Enable DLL master slave shuffle
5063 00:56:37.178692 ==============================================================
5064 00:56:37.182126 Gating Mode config
5065 00:56:37.188709 ==============================================================
5066 00:56:37.189188 Config description:
5067 00:56:37.198838 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5068 00:56:37.205331 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5069 00:56:37.211686 SELPH_MODE 0: By rank 1: By Phase
5070 00:56:37.214787 ==============================================================
5071 00:56:37.218204 GAT_TRACK_EN = 1
5072 00:56:37.221588 RX_GATING_MODE = 2
5073 00:56:37.224954 RX_GATING_TRACK_MODE = 2
5074 00:56:37.228154 SELPH_MODE = 1
5075 00:56:37.231805 PICG_EARLY_EN = 1
5076 00:56:37.234924 VALID_LAT_VALUE = 1
5077 00:56:37.238362 ==============================================================
5078 00:56:37.242048 Enter into Gating configuration >>>>
5079 00:56:37.244926 Exit from Gating configuration <<<<
5080 00:56:37.248273 Enter into DVFS_PRE_config >>>>>
5081 00:56:37.261024 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5082 00:56:37.264450 Exit from DVFS_PRE_config <<<<<
5083 00:56:37.267722 Enter into PICG configuration >>>>
5084 00:56:37.270852 Exit from PICG configuration <<<<
5085 00:56:37.271339 [RX_INPUT] configuration >>>>>
5086 00:56:37.274122 [RX_INPUT] configuration <<<<<
5087 00:56:37.281030 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5088 00:56:37.284231 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5089 00:56:37.290916 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5090 00:56:37.297563 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5091 00:56:37.304095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5092 00:56:37.310528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5093 00:56:37.314306 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5094 00:56:37.317474 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5095 00:56:37.323561 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5096 00:56:37.327174 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5097 00:56:37.330157 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5098 00:56:37.337103 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5099 00:56:37.340092 ===================================
5100 00:56:37.340581 LPDDR4 DRAM CONFIGURATION
5101 00:56:37.343505 ===================================
5102 00:56:37.347142 EX_ROW_EN[0] = 0x0
5103 00:56:37.347609 EX_ROW_EN[1] = 0x0
5104 00:56:37.350505 LP4Y_EN = 0x0
5105 00:56:37.353620 WORK_FSP = 0x0
5106 00:56:37.354156 WL = 0x3
5107 00:56:37.356745 RL = 0x3
5108 00:56:37.357210 BL = 0x2
5109 00:56:37.360370 RPST = 0x0
5110 00:56:37.360834 RD_PRE = 0x0
5111 00:56:37.363515 WR_PRE = 0x1
5112 00:56:37.364009 WR_PST = 0x0
5113 00:56:37.366875 DBI_WR = 0x0
5114 00:56:37.367332 DBI_RD = 0x0
5115 00:56:37.370116 OTF = 0x1
5116 00:56:37.373444 ===================================
5117 00:56:37.376791 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5118 00:56:37.380332 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5119 00:56:37.386722 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5120 00:56:37.390444 ===================================
5121 00:56:37.390865 LPDDR4 DRAM CONFIGURATION
5122 00:56:37.393115 ===================================
5123 00:56:37.396313 EX_ROW_EN[0] = 0x10
5124 00:56:37.396732 EX_ROW_EN[1] = 0x0
5125 00:56:37.400034 LP4Y_EN = 0x0
5126 00:56:37.400488 WORK_FSP = 0x0
5127 00:56:37.403566 WL = 0x3
5128 00:56:37.406517 RL = 0x3
5129 00:56:37.406977 BL = 0x2
5130 00:56:37.410248 RPST = 0x0
5131 00:56:37.410772 RD_PRE = 0x0
5132 00:56:37.413263 WR_PRE = 0x1
5133 00:56:37.413790 WR_PST = 0x0
5134 00:56:37.416508 DBI_WR = 0x0
5135 00:56:37.416932 DBI_RD = 0x0
5136 00:56:37.419739 OTF = 0x1
5137 00:56:37.422935 ===================================
5138 00:56:37.430221 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5139 00:56:37.432987 nWR fixed to 30
5140 00:56:37.433552 [ModeRegInit_LP4] CH0 RK0
5141 00:56:37.436314 [ModeRegInit_LP4] CH0 RK1
5142 00:56:37.439922 [ModeRegInit_LP4] CH1 RK0
5143 00:56:37.440488 [ModeRegInit_LP4] CH1 RK1
5144 00:56:37.442818 match AC timing 9
5145 00:56:37.446223 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5146 00:56:37.452723 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5147 00:56:37.456082 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5148 00:56:37.462498 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5149 00:56:37.465841 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5150 00:56:37.466482 ==
5151 00:56:37.468711 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 00:56:37.472328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 00:56:37.472796 ==
5154 00:56:37.478909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5155 00:56:37.485408 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5156 00:56:37.488985 [CA 0] Center 37 (7~68) winsize 62
5157 00:56:37.491917 [CA 1] Center 37 (7~68) winsize 62
5158 00:56:37.495742 [CA 2] Center 34 (4~65) winsize 62
5159 00:56:37.498758 [CA 3] Center 34 (4~65) winsize 62
5160 00:56:37.501714 [CA 4] Center 33 (3~64) winsize 62
5161 00:56:37.505311 [CA 5] Center 33 (3~63) winsize 61
5162 00:56:37.505799
5163 00:56:37.508386 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5164 00:56:37.508855
5165 00:56:37.512055 [CATrainingPosCal] consider 1 rank data
5166 00:56:37.515263 u2DelayCellTimex100 = 270/100 ps
5167 00:56:37.518464 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5168 00:56:37.521958 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5169 00:56:37.525258 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5170 00:56:37.528614 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5171 00:56:37.531920 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5172 00:56:37.535341 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5173 00:56:37.538242
5174 00:56:37.541302 CA PerBit enable=1, Macro0, CA PI delay=33
5175 00:56:37.541770
5176 00:56:37.544949 [CBTSetCACLKResult] CA Dly = 33
5177 00:56:37.545506 CS Dly: 7 (0~38)
5178 00:56:37.545881 ==
5179 00:56:37.548453 Dram Type= 6, Freq= 0, CH_0, rank 1
5180 00:56:37.551456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 00:56:37.554833 ==
5182 00:56:37.558080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5183 00:56:37.564519 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5184 00:56:37.567983 [CA 0] Center 37 (7~68) winsize 62
5185 00:56:37.571233 [CA 1] Center 37 (7~68) winsize 62
5186 00:56:37.574526 [CA 2] Center 34 (4~65) winsize 62
5187 00:56:37.577599 [CA 3] Center 34 (4~65) winsize 62
5188 00:56:37.580861 [CA 4] Center 33 (3~64) winsize 62
5189 00:56:37.584594 [CA 5] Center 33 (3~63) winsize 61
5190 00:56:37.585203
5191 00:56:37.587591 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5192 00:56:37.588063
5193 00:56:37.590866 [CATrainingPosCal] consider 2 rank data
5194 00:56:37.594509 u2DelayCellTimex100 = 270/100 ps
5195 00:56:37.597815 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5196 00:56:37.600536 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5197 00:56:37.604197 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5198 00:56:37.610629 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5199 00:56:37.614249 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5200 00:56:37.617623 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5201 00:56:37.618226
5202 00:56:37.621183 CA PerBit enable=1, Macro0, CA PI delay=33
5203 00:56:37.621746
5204 00:56:37.624916 [CBTSetCACLKResult] CA Dly = 33
5205 00:56:37.625478 CS Dly: 7 (0~39)
5206 00:56:37.625852
5207 00:56:37.627457 ----->DramcWriteLeveling(PI) begin...
5208 00:56:37.628029 ==
5209 00:56:37.630613 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 00:56:37.637335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 00:56:37.637807 ==
5212 00:56:37.640663 Write leveling (Byte 0): 33 => 33
5213 00:56:37.644257 Write leveling (Byte 1): 31 => 31
5214 00:56:37.644823 DramcWriteLeveling(PI) end<-----
5215 00:56:37.645200
5216 00:56:37.647149 ==
5217 00:56:37.650673 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 00:56:37.654286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 00:56:37.654854 ==
5220 00:56:37.657161 [Gating] SW mode calibration
5221 00:56:37.663651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5222 00:56:37.667106 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5223 00:56:37.673850 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5224 00:56:37.676501 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5225 00:56:37.683206 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5226 00:56:37.686804 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5227 00:56:37.689768 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5228 00:56:37.696617 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5229 00:56:37.700104 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5230 00:56:37.703009 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5231 00:56:37.709460 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (1 0) (1 0)
5232 00:56:37.713253 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5233 00:56:37.716524 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5234 00:56:37.722881 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5235 00:56:37.726274 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5236 00:56:37.729950 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5237 00:56:37.733732 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5238 00:56:37.739519 0 15 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5239 00:56:37.742774 1 0 0 | B1->B0 | 3030 4545 | 0 0 | (1 1) (0 0)
5240 00:56:37.746227 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5241 00:56:37.752651 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5242 00:56:37.755826 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5243 00:56:37.758889 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5244 00:56:37.765930 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5245 00:56:37.769548 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5246 00:56:37.772336 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5247 00:56:37.779180 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5248 00:56:37.782615 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 00:56:37.785533 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 00:56:37.792458 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 00:56:37.795337 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 00:56:37.798912 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 00:56:37.805076 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 00:56:37.808266 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 00:56:37.811801 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 00:56:37.818534 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 00:56:37.821636 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 00:56:37.825265 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 00:56:37.831540 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5260 00:56:37.834688 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5261 00:56:37.838141 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5262 00:56:37.844857 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5263 00:56:37.848481 Total UI for P1: 0, mck2ui 16
5264 00:56:37.851357 best dqsien dly found for B0: ( 1, 2, 26)
5265 00:56:37.854456 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5266 00:56:37.858123 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5267 00:56:37.861480 Total UI for P1: 0, mck2ui 16
5268 00:56:37.864577 best dqsien dly found for B1: ( 1, 3, 2)
5269 00:56:37.867939 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5270 00:56:37.871179 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5271 00:56:37.874571
5272 00:56:37.877854 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5273 00:56:37.881541 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5274 00:56:37.884939 [Gating] SW calibration Done
5275 00:56:37.885477 ==
5276 00:56:37.888479 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 00:56:37.890914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 00:56:37.891388 ==
5279 00:56:37.894033 RX Vref Scan: 0
5280 00:56:37.894558
5281 00:56:37.894931 RX Vref 0 -> 0, step: 1
5282 00:56:37.895281
5283 00:56:37.897596 RX Delay -80 -> 252, step: 8
5284 00:56:37.900781 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5285 00:56:37.903966 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5286 00:56:37.910839 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5287 00:56:37.914220 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5288 00:56:37.917605 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5289 00:56:37.920483 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5290 00:56:37.923723 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5291 00:56:37.927670 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5292 00:56:37.933654 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5293 00:56:37.937013 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5294 00:56:37.940833 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5295 00:56:37.943861 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5296 00:56:37.946884 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5297 00:56:37.953707 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5298 00:56:37.956876 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5299 00:56:37.959953 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5300 00:56:37.960379 ==
5301 00:56:37.963370 Dram Type= 6, Freq= 0, CH_0, rank 0
5302 00:56:37.966916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 00:56:37.967342 ==
5304 00:56:37.970294 DQS Delay:
5305 00:56:37.970819 DQS0 = 0, DQS1 = 0
5306 00:56:37.973491 DQM Delay:
5307 00:56:37.974018 DQM0 = 98, DQM1 = 86
5308 00:56:37.977165 DQ Delay:
5309 00:56:37.977703 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5310 00:56:37.979981 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5311 00:56:37.983550 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5312 00:56:37.990294 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5313 00:56:37.990825
5314 00:56:37.991167
5315 00:56:37.991483 ==
5316 00:56:37.993269 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 00:56:37.996538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 00:56:37.997066 ==
5319 00:56:37.997405
5320 00:56:37.997712
5321 00:56:37.999787 TX Vref Scan disable
5322 00:56:38.000311 == TX Byte 0 ==
5323 00:56:38.006412 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5324 00:56:38.009385 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5325 00:56:38.009813 == TX Byte 1 ==
5326 00:56:38.016156 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5327 00:56:38.019347 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5328 00:56:38.019771 ==
5329 00:56:38.022902 Dram Type= 6, Freq= 0, CH_0, rank 0
5330 00:56:38.026097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 00:56:38.026683 ==
5332 00:56:38.027027
5333 00:56:38.029632
5334 00:56:38.030156 TX Vref Scan disable
5335 00:56:38.032692 == TX Byte 0 ==
5336 00:56:38.035886 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5337 00:56:38.042540 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5338 00:56:38.042975 == TX Byte 1 ==
5339 00:56:38.045865 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5340 00:56:38.052261 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5341 00:56:38.052687
5342 00:56:38.053027 [DATLAT]
5343 00:56:38.053339 Freq=933, CH0 RK0
5344 00:56:38.053645
5345 00:56:38.055529 DATLAT Default: 0xd
5346 00:56:38.055951 0, 0xFFFF, sum = 0
5347 00:56:38.058787 1, 0xFFFF, sum = 0
5348 00:56:38.062361 2, 0xFFFF, sum = 0
5349 00:56:38.062835 3, 0xFFFF, sum = 0
5350 00:56:38.065793 4, 0xFFFF, sum = 0
5351 00:56:38.066412 5, 0xFFFF, sum = 0
5352 00:56:38.069097 6, 0xFFFF, sum = 0
5353 00:56:38.069669 7, 0xFFFF, sum = 0
5354 00:56:38.072041 8, 0xFFFF, sum = 0
5355 00:56:38.072616 9, 0xFFFF, sum = 0
5356 00:56:38.075940 10, 0x0, sum = 1
5357 00:56:38.076519 11, 0x0, sum = 2
5358 00:56:38.079022 12, 0x0, sum = 3
5359 00:56:38.079601 13, 0x0, sum = 4
5360 00:56:38.079984 best_step = 11
5361 00:56:38.080326
5362 00:56:38.082130 ==
5363 00:56:38.085457 Dram Type= 6, Freq= 0, CH_0, rank 0
5364 00:56:38.088622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 00:56:38.089088 ==
5366 00:56:38.089450 RX Vref Scan: 1
5367 00:56:38.089793
5368 00:56:38.091636 RX Vref 0 -> 0, step: 1
5369 00:56:38.092096
5370 00:56:38.095083 RX Delay -61 -> 252, step: 4
5371 00:56:38.095543
5372 00:56:38.098705 Set Vref, RX VrefLevel [Byte0]: 59
5373 00:56:38.101442 [Byte1]: 58
5374 00:56:38.104772
5375 00:56:38.105190 Final RX Vref Byte 0 = 59 to rank0
5376 00:56:38.108554 Final RX Vref Byte 1 = 58 to rank0
5377 00:56:38.111803 Final RX Vref Byte 0 = 59 to rank1
5378 00:56:38.114773 Final RX Vref Byte 1 = 58 to rank1==
5379 00:56:38.118152 Dram Type= 6, Freq= 0, CH_0, rank 0
5380 00:56:38.124544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 00:56:38.125256 ==
5382 00:56:38.125803 DQS Delay:
5383 00:56:38.127629 DQS0 = 0, DQS1 = 0
5384 00:56:38.128269 DQM Delay:
5385 00:56:38.128758 DQM0 = 96, DQM1 = 86
5386 00:56:38.130994 DQ Delay:
5387 00:56:38.134626 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5388 00:56:38.137450 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =104
5389 00:56:38.140979 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =82
5390 00:56:38.144203 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =92
5391 00:56:38.144619
5392 00:56:38.144947
5393 00:56:38.150647 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5394 00:56:38.154299 CH0 RK0: MR19=505, MR18=2F15
5395 00:56:38.160529 CH0_RK0: MR19=0x505, MR18=0x2F15, DQSOSC=407, MR23=63, INC=65, DEC=43
5396 00:56:38.161040
5397 00:56:38.164083 ----->DramcWriteLeveling(PI) begin...
5398 00:56:38.164509 ==
5399 00:56:38.167471 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 00:56:38.170609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 00:56:38.171133 ==
5402 00:56:38.173709 Write leveling (Byte 0): 32 => 32
5403 00:56:38.177164 Write leveling (Byte 1): 31 => 31
5404 00:56:38.180567 DramcWriteLeveling(PI) end<-----
5405 00:56:38.181311
5406 00:56:38.181719 ==
5407 00:56:38.183692 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 00:56:38.190310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 00:56:38.190884 ==
5410 00:56:38.191316 [Gating] SW mode calibration
5411 00:56:38.200655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5412 00:56:38.203618 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5413 00:56:38.210125 0 14 0 | B1->B0 | 2b2b 3030 | 1 1 | (0 0) (1 1)
5414 00:56:38.213730 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5415 00:56:38.216579 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5416 00:56:38.223060 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5417 00:56:38.226454 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5418 00:56:38.230032 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5419 00:56:38.237139 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5420 00:56:38.240220 0 14 28 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 0)
5421 00:56:38.243007 0 15 0 | B1->B0 | 3030 2525 | 0 0 | (1 1) (0 0)
5422 00:56:38.250265 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5423 00:56:38.253072 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 00:56:38.256065 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 00:56:38.262720 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 00:56:38.265994 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5427 00:56:38.269193 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5428 00:56:38.276322 0 15 28 | B1->B0 | 2727 3736 | 0 1 | (0 0) (0 0)
5429 00:56:38.279067 1 0 0 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
5430 00:56:38.282812 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 00:56:38.289676 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 00:56:38.293028 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 00:56:38.295906 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 00:56:38.299442 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 00:56:38.305747 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 00:56:38.308808 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5437 00:56:38.315898 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 00:56:38.318711 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 00:56:38.322416 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 00:56:38.328872 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 00:56:38.332119 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 00:56:38.335406 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 00:56:38.342528 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 00:56:38.345625 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 00:56:38.348546 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 00:56:38.355127 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 00:56:38.358602 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 00:56:38.361793 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 00:56:38.368362 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 00:56:38.371726 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 00:56:38.374698 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 00:56:38.381453 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5453 00:56:38.385083 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5454 00:56:38.388412 Total UI for P1: 0, mck2ui 16
5455 00:56:38.391387 best dqsien dly found for B0: ( 1, 2, 28)
5456 00:56:38.394531 Total UI for P1: 0, mck2ui 16
5457 00:56:38.397529 best dqsien dly found for B1: ( 1, 2, 30)
5458 00:56:38.400880 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5459 00:56:38.404176 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5460 00:56:38.404683
5461 00:56:38.407486 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5462 00:56:38.410585 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5463 00:56:38.413757 [Gating] SW calibration Done
5464 00:56:38.414263 ==
5465 00:56:38.417751 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 00:56:38.423960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 00:56:38.424525 ==
5468 00:56:38.424904 RX Vref Scan: 0
5469 00:56:38.425259
5470 00:56:38.427479 RX Vref 0 -> 0, step: 1
5471 00:56:38.428048
5472 00:56:38.430712 RX Delay -80 -> 252, step: 8
5473 00:56:38.433720 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5474 00:56:38.437294 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5475 00:56:38.440775 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5476 00:56:38.443847 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5477 00:56:38.446648 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5478 00:56:38.453442 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5479 00:56:38.457171 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5480 00:56:38.460180 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5481 00:56:38.463475 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5482 00:56:38.466821 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5483 00:56:38.473556 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5484 00:56:38.476725 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5485 00:56:38.479791 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5486 00:56:38.483414 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5487 00:56:38.486496 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5488 00:56:38.493226 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5489 00:56:38.493834 ==
5490 00:56:38.496570 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 00:56:38.499792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 00:56:38.500369 ==
5493 00:56:38.500756 DQS Delay:
5494 00:56:38.502991 DQS0 = 0, DQS1 = 0
5495 00:56:38.503474 DQM Delay:
5496 00:56:38.506343 DQM0 = 97, DQM1 = 90
5497 00:56:38.506808 DQ Delay:
5498 00:56:38.509488 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5499 00:56:38.512827 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5500 00:56:38.516430 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5501 00:56:38.519251 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5502 00:56:38.519719
5503 00:56:38.520085
5504 00:56:38.520427 ==
5505 00:56:38.522782 Dram Type= 6, Freq= 0, CH_0, rank 1
5506 00:56:38.526288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 00:56:38.529987 ==
5508 00:56:38.530617
5509 00:56:38.530995
5510 00:56:38.531337 TX Vref Scan disable
5511 00:56:38.533061 == TX Byte 0 ==
5512 00:56:38.535967 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5513 00:56:38.538889 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5514 00:56:38.543135 == TX Byte 1 ==
5515 00:56:38.546268 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5516 00:56:38.549223 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5517 00:56:38.552638 ==
5518 00:56:38.553112 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 00:56:38.559003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 00:56:38.559566 ==
5521 00:56:38.559942
5522 00:56:38.560288
5523 00:56:38.562047 TX Vref Scan disable
5524 00:56:38.562612 == TX Byte 0 ==
5525 00:56:38.568760 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5526 00:56:38.572593 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5527 00:56:38.573125 == TX Byte 1 ==
5528 00:56:38.578757 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5529 00:56:38.581975 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5530 00:56:38.582660
5531 00:56:38.583029 [DATLAT]
5532 00:56:38.585121 Freq=933, CH0 RK1
5533 00:56:38.585549
5534 00:56:38.585964 DATLAT Default: 0xb
5535 00:56:38.588304 0, 0xFFFF, sum = 0
5536 00:56:38.588739 1, 0xFFFF, sum = 0
5537 00:56:38.592020 2, 0xFFFF, sum = 0
5538 00:56:38.592619 3, 0xFFFF, sum = 0
5539 00:56:38.594824 4, 0xFFFF, sum = 0
5540 00:56:38.595259 5, 0xFFFF, sum = 0
5541 00:56:38.599078 6, 0xFFFF, sum = 0
5542 00:56:38.602248 7, 0xFFFF, sum = 0
5543 00:56:38.602785 8, 0xFFFF, sum = 0
5544 00:56:38.605221 9, 0xFFFF, sum = 0
5545 00:56:38.605761 10, 0x0, sum = 1
5546 00:56:38.608220 11, 0x0, sum = 2
5547 00:56:38.608654 12, 0x0, sum = 3
5548 00:56:38.609164 13, 0x0, sum = 4
5549 00:56:38.611658 best_step = 11
5550 00:56:38.612085
5551 00:56:38.612424 ==
5552 00:56:38.614891 Dram Type= 6, Freq= 0, CH_0, rank 1
5553 00:56:38.618588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 00:56:38.619047 ==
5555 00:56:38.621811 RX Vref Scan: 0
5556 00:56:38.622294
5557 00:56:38.622746 RX Vref 0 -> 0, step: 1
5558 00:56:38.624774
5559 00:56:38.625214 RX Delay -53 -> 252, step: 4
5560 00:56:38.632583 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5561 00:56:38.635766 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5562 00:56:38.638724 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5563 00:56:38.642804 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5564 00:56:38.645696 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5565 00:56:38.649375 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5566 00:56:38.655693 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5567 00:56:38.658851 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5568 00:56:38.661855 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5569 00:56:38.665545 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5570 00:56:38.671873 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5571 00:56:38.675587 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5572 00:56:38.678444 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5573 00:56:38.682151 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5574 00:56:38.685454 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5575 00:56:38.691531 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5576 00:56:38.692131 ==
5577 00:56:38.695050 Dram Type= 6, Freq= 0, CH_0, rank 1
5578 00:56:38.698271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 00:56:38.698703 ==
5580 00:56:38.699047 DQS Delay:
5581 00:56:38.701523 DQS0 = 0, DQS1 = 0
5582 00:56:38.701952 DQM Delay:
5583 00:56:38.704709 DQM0 = 95, DQM1 = 88
5584 00:56:38.705198 DQ Delay:
5585 00:56:38.707822 DQ0 =94, DQ1 =96, DQ2 =88, DQ3 =92
5586 00:56:38.710946 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5587 00:56:38.714233 DQ8 =82, DQ9 =78, DQ10 =92, DQ11 =82
5588 00:56:38.717698 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5589 00:56:38.718124
5590 00:56:38.718728
5591 00:56:38.727515 [DQSOSCAuto] RK1, (LSB)MR18= 0x29f9, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 408 ps
5592 00:56:38.727980 CH0 RK1: MR19=504, MR18=29F9
5593 00:56:38.734197 CH0_RK1: MR19=0x504, MR18=0x29F9, DQSOSC=408, MR23=63, INC=65, DEC=43
5594 00:56:38.737645 [RxdqsGatingPostProcess] freq 933
5595 00:56:38.744348 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5596 00:56:38.747425 best DQS0 dly(2T, 0.5T) = (0, 10)
5597 00:56:38.751087 best DQS1 dly(2T, 0.5T) = (0, 11)
5598 00:56:38.754089 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5599 00:56:38.757715 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5600 00:56:38.760264 best DQS0 dly(2T, 0.5T) = (0, 10)
5601 00:56:38.760690 best DQS1 dly(2T, 0.5T) = (0, 10)
5602 00:56:38.763817 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5603 00:56:38.767309 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5604 00:56:38.770715 Pre-setting of DQS Precalculation
5605 00:56:38.777645 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5606 00:56:38.778221 ==
5607 00:56:38.780659 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 00:56:38.783982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 00:56:38.784513 ==
5610 00:56:38.790125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5611 00:56:38.796763 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5612 00:56:38.800519 [CA 0] Center 36 (6~67) winsize 62
5613 00:56:38.803547 [CA 1] Center 37 (6~68) winsize 63
5614 00:56:38.806880 [CA 2] Center 34 (4~65) winsize 62
5615 00:56:38.810062 [CA 3] Center 33 (3~64) winsize 62
5616 00:56:38.813295 [CA 4] Center 34 (4~64) winsize 61
5617 00:56:38.816538 [CA 5] Center 33 (3~64) winsize 62
5618 00:56:38.817113
5619 00:56:38.820477 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5620 00:56:38.821047
5621 00:56:38.823106 [CATrainingPosCal] consider 1 rank data
5622 00:56:38.826904 u2DelayCellTimex100 = 270/100 ps
5623 00:56:38.830452 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5624 00:56:38.833442 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5625 00:56:38.836493 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5626 00:56:38.839634 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5627 00:56:38.843155 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5628 00:56:38.846450 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5629 00:56:38.849679
5630 00:56:38.853342 CA PerBit enable=1, Macro0, CA PI delay=33
5631 00:56:38.853927
5632 00:56:38.856223 [CBTSetCACLKResult] CA Dly = 33
5633 00:56:38.856711 CS Dly: 5 (0~36)
5634 00:56:38.857089 ==
5635 00:56:38.859437 Dram Type= 6, Freq= 0, CH_1, rank 1
5636 00:56:38.862797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 00:56:38.863272 ==
5638 00:56:38.869537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5639 00:56:38.876271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5640 00:56:38.879495 [CA 0] Center 36 (6~67) winsize 62
5641 00:56:38.882866 [CA 1] Center 37 (7~67) winsize 61
5642 00:56:38.886280 [CA 2] Center 34 (4~65) winsize 62
5643 00:56:38.889663 [CA 3] Center 33 (3~64) winsize 62
5644 00:56:38.892599 [CA 4] Center 34 (3~65) winsize 63
5645 00:56:38.895794 [CA 5] Center 33 (3~64) winsize 62
5646 00:56:38.896266
5647 00:56:38.899469 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5648 00:56:38.899942
5649 00:56:38.902611 [CATrainingPosCal] consider 2 rank data
5650 00:56:38.905939 u2DelayCellTimex100 = 270/100 ps
5651 00:56:38.908866 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5652 00:56:38.912626 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5653 00:56:38.915341 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5654 00:56:38.922374 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5655 00:56:38.925472 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5656 00:56:38.929411 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5657 00:56:38.929988
5658 00:56:38.932271 CA PerBit enable=1, Macro0, CA PI delay=33
5659 00:56:38.932846
5660 00:56:38.935340 [CBTSetCACLKResult] CA Dly = 33
5661 00:56:38.935814 CS Dly: 6 (0~39)
5662 00:56:38.936189
5663 00:56:38.938924 ----->DramcWriteLeveling(PI) begin...
5664 00:56:38.941668 ==
5665 00:56:38.945189 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 00:56:38.948507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 00:56:38.948981 ==
5668 00:56:38.951598 Write leveling (Byte 0): 26 => 26
5669 00:56:38.955016 Write leveling (Byte 1): 32 => 32
5670 00:56:38.958098 DramcWriteLeveling(PI) end<-----
5671 00:56:38.958601
5672 00:56:38.958973 ==
5673 00:56:38.961413 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 00:56:38.964667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 00:56:38.965100 ==
5676 00:56:38.967736 [Gating] SW mode calibration
5677 00:56:38.974894 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5678 00:56:38.981655 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5679 00:56:38.984415 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5680 00:56:38.987710 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5681 00:56:38.994210 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5682 00:56:38.997860 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5683 00:56:39.000785 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5684 00:56:39.007262 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5685 00:56:39.010469 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5686 00:56:39.014147 0 14 28 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (1 1)
5687 00:56:39.020405 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5688 00:56:39.024345 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5689 00:56:39.027851 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5690 00:56:39.033820 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5691 00:56:39.037352 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5692 00:56:39.040212 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5693 00:56:39.046902 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5694 00:56:39.050340 0 15 28 | B1->B0 | 3636 3a3a | 0 0 | (0 0) (0 0)
5695 00:56:39.053405 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5696 00:56:39.060313 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5697 00:56:39.063172 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5698 00:56:39.066988 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5699 00:56:39.073641 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5700 00:56:39.077164 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5701 00:56:39.079836 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5702 00:56:39.086548 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 00:56:39.089700 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 00:56:39.093475 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 00:56:39.099716 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 00:56:39.103096 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 00:56:39.106450 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 00:56:39.113297 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 00:56:39.116332 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 00:56:39.119884 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5711 00:56:39.126558 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 00:56:39.129584 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 00:56:39.132808 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5714 00:56:39.139543 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5715 00:56:39.142877 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5716 00:56:39.146019 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5717 00:56:39.153095 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5718 00:56:39.153651 Total UI for P1: 0, mck2ui 16
5719 00:56:39.159080 best dqsien dly found for B0: ( 1, 2, 22)
5720 00:56:39.162955 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5721 00:56:39.165766 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5722 00:56:39.168882 Total UI for P1: 0, mck2ui 16
5723 00:56:39.172380 best dqsien dly found for B1: ( 1, 2, 26)
5724 00:56:39.175760 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5725 00:56:39.179111 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5726 00:56:39.179606
5727 00:56:39.185359 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5728 00:56:39.188940 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5729 00:56:39.191891 [Gating] SW calibration Done
5730 00:56:39.192587 ==
5731 00:56:39.195236 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 00:56:39.198547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 00:56:39.198976 ==
5734 00:56:39.199481 RX Vref Scan: 0
5735 00:56:39.200112
5736 00:56:39.201973 RX Vref 0 -> 0, step: 1
5737 00:56:39.202438
5738 00:56:39.205612 RX Delay -80 -> 252, step: 8
5739 00:56:39.208490 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5740 00:56:39.211556 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5741 00:56:39.218326 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5742 00:56:39.221504 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5743 00:56:39.225507 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5744 00:56:39.228326 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5745 00:56:39.231519 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5746 00:56:39.234993 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5747 00:56:39.241323 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5748 00:56:39.244928 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5749 00:56:39.247978 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5750 00:56:39.251416 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5751 00:56:39.254656 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5752 00:56:39.261398 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5753 00:56:39.264667 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5754 00:56:39.267861 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5755 00:56:39.268289 ==
5756 00:56:39.271150 Dram Type= 6, Freq= 0, CH_1, rank 0
5757 00:56:39.274396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 00:56:39.274819 ==
5759 00:56:39.277777 DQS Delay:
5760 00:56:39.278514 DQS0 = 0, DQS1 = 0
5761 00:56:39.280884 DQM Delay:
5762 00:56:39.281521 DQM0 = 101, DQM1 = 91
5763 00:56:39.282085 DQ Delay:
5764 00:56:39.284275 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5765 00:56:39.287647 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5766 00:56:39.291158 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5767 00:56:39.294303 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =99
5768 00:56:39.297925
5769 00:56:39.298380
5770 00:56:39.298714 ==
5771 00:56:39.301231 Dram Type= 6, Freq= 0, CH_1, rank 0
5772 00:56:39.304988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 00:56:39.305513 ==
5774 00:56:39.305856
5775 00:56:39.306207
5776 00:56:39.307836 TX Vref Scan disable
5777 00:56:39.308252 == TX Byte 0 ==
5778 00:56:39.314121 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5779 00:56:39.317600 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5780 00:56:39.318023 == TX Byte 1 ==
5781 00:56:39.324108 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5782 00:56:39.327748 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5783 00:56:39.328275 ==
5784 00:56:39.330850 Dram Type= 6, Freq= 0, CH_1, rank 0
5785 00:56:39.334248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5786 00:56:39.334789 ==
5787 00:56:39.335134
5788 00:56:39.335444
5789 00:56:39.337307 TX Vref Scan disable
5790 00:56:39.340753 == TX Byte 0 ==
5791 00:56:39.343933 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5792 00:56:39.347173 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5793 00:56:39.351051 == TX Byte 1 ==
5794 00:56:39.353892 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5795 00:56:39.357268 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5796 00:56:39.357689
5797 00:56:39.360603 [DATLAT]
5798 00:56:39.361024 Freq=933, CH1 RK0
5799 00:56:39.361357
5800 00:56:39.363941 DATLAT Default: 0xd
5801 00:56:39.364360 0, 0xFFFF, sum = 0
5802 00:56:39.367015 1, 0xFFFF, sum = 0
5803 00:56:39.367440 2, 0xFFFF, sum = 0
5804 00:56:39.370699 3, 0xFFFF, sum = 0
5805 00:56:39.371224 4, 0xFFFF, sum = 0
5806 00:56:39.373604 5, 0xFFFF, sum = 0
5807 00:56:39.376941 6, 0xFFFF, sum = 0
5808 00:56:39.377368 7, 0xFFFF, sum = 0
5809 00:56:39.380430 8, 0xFFFF, sum = 0
5810 00:56:39.380959 9, 0xFFFF, sum = 0
5811 00:56:39.383930 10, 0x0, sum = 1
5812 00:56:39.384355 11, 0x0, sum = 2
5813 00:56:39.384697 12, 0x0, sum = 3
5814 00:56:39.387203 13, 0x0, sum = 4
5815 00:56:39.387735 best_step = 11
5816 00:56:39.388073
5817 00:56:39.390340 ==
5818 00:56:39.390867 Dram Type= 6, Freq= 0, CH_1, rank 0
5819 00:56:39.397003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 00:56:39.397534 ==
5821 00:56:39.397874 RX Vref Scan: 1
5822 00:56:39.398203
5823 00:56:39.400058 RX Vref 0 -> 0, step: 1
5824 00:56:39.400574
5825 00:56:39.403563 RX Delay -69 -> 252, step: 4
5826 00:56:39.404087
5827 00:56:39.406404 Set Vref, RX VrefLevel [Byte0]: 52
5828 00:56:39.410117 [Byte1]: 54
5829 00:56:39.410564
5830 00:56:39.413357 Final RX Vref Byte 0 = 52 to rank0
5831 00:56:39.416344 Final RX Vref Byte 1 = 54 to rank0
5832 00:56:39.420259 Final RX Vref Byte 0 = 52 to rank1
5833 00:56:39.422986 Final RX Vref Byte 1 = 54 to rank1==
5834 00:56:39.426229 Dram Type= 6, Freq= 0, CH_1, rank 0
5835 00:56:39.430361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 00:56:39.433269 ==
5837 00:56:39.433999 DQS Delay:
5838 00:56:39.434514 DQS0 = 0, DQS1 = 0
5839 00:56:39.436475 DQM Delay:
5840 00:56:39.437035 DQM0 = 100, DQM1 = 93
5841 00:56:39.439535 DQ Delay:
5842 00:56:39.442605 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =96
5843 00:56:39.446216 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =96
5844 00:56:39.449258 DQ8 =80, DQ9 =84, DQ10 =96, DQ11 =84
5845 00:56:39.453144 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =104
5846 00:56:39.453614
5847 00:56:39.454030
5848 00:56:39.459577 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5849 00:56:39.462904 CH1 RK0: MR19=505, MR18=1B0A
5850 00:56:39.469247 CH1_RK0: MR19=0x505, MR18=0x1B0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5851 00:56:39.469717
5852 00:56:39.472973 ----->DramcWriteLeveling(PI) begin...
5853 00:56:39.473542 ==
5854 00:56:39.475663 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 00:56:39.479374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 00:56:39.479942 ==
5857 00:56:39.482483 Write leveling (Byte 0): 24 => 24
5858 00:56:39.485660 Write leveling (Byte 1): 26 => 26
5859 00:56:39.489721 DramcWriteLeveling(PI) end<-----
5860 00:56:39.490324
5861 00:56:39.490708 ==
5862 00:56:39.492654 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 00:56:39.496119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 00:56:39.498807 ==
5865 00:56:39.499279 [Gating] SW mode calibration
5866 00:56:39.508567 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5867 00:56:39.511844 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5868 00:56:39.515197 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5869 00:56:39.522075 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5870 00:56:39.525302 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5871 00:56:39.529092 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5872 00:56:39.535638 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5873 00:56:39.538256 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5874 00:56:39.541852 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5875 00:56:39.548441 0 14 28 | B1->B0 | 2b2b 2f2f | 0 1 | (0 1) (0 1)
5876 00:56:39.552148 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5877 00:56:39.555099 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5878 00:56:39.561507 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5879 00:56:39.564534 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5880 00:56:39.568501 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5881 00:56:39.575049 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5882 00:56:39.578359 0 15 24 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5883 00:56:39.581196 0 15 28 | B1->B0 | 3d3c 3333 | 1 0 | (0 0) (0 0)
5884 00:56:39.588142 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5885 00:56:39.591392 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5886 00:56:39.594939 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5887 00:56:39.601869 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5888 00:56:39.604617 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5889 00:56:39.608191 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5890 00:56:39.614396 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5891 00:56:39.617848 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5892 00:56:39.621140 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 00:56:39.628328 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 00:56:39.630738 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 00:56:39.634358 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 00:56:39.640455 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 00:56:39.644259 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 00:56:39.647627 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 00:56:39.654116 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 00:56:39.657572 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 00:56:39.660360 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 00:56:39.666883 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 00:56:39.670400 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 00:56:39.674034 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 00:56:39.680939 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5906 00:56:39.683816 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5907 00:56:39.686974 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5908 00:56:39.690197 Total UI for P1: 0, mck2ui 16
5909 00:56:39.693211 best dqsien dly found for B0: ( 1, 2, 26)
5910 00:56:39.696517 Total UI for P1: 0, mck2ui 16
5911 00:56:39.700478 best dqsien dly found for B1: ( 1, 2, 24)
5912 00:56:39.703001 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5913 00:56:39.709607 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5914 00:56:39.710152
5915 00:56:39.712912 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5916 00:56:39.716614 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5917 00:56:39.719785 [Gating] SW calibration Done
5918 00:56:39.720255 ==
5919 00:56:39.723080 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 00:56:39.726207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 00:56:39.726682 ==
5922 00:56:39.729814 RX Vref Scan: 0
5923 00:56:39.730442
5924 00:56:39.730827 RX Vref 0 -> 0, step: 1
5925 00:56:39.731180
5926 00:56:39.732702 RX Delay -80 -> 252, step: 8
5927 00:56:39.735865 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5928 00:56:39.742954 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5929 00:56:39.746311 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5930 00:56:39.749450 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5931 00:56:39.753306 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5932 00:56:39.756156 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5933 00:56:39.759099 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5934 00:56:39.766129 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5935 00:56:39.769135 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5936 00:56:39.772796 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5937 00:56:39.775445 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5938 00:56:39.778899 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5939 00:56:39.785353 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5940 00:56:39.788992 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5941 00:56:39.792102 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5942 00:56:39.795453 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5943 00:56:39.795973 ==
5944 00:56:39.798936 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 00:56:39.802298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 00:56:39.805677 ==
5947 00:56:39.806230 DQS Delay:
5948 00:56:39.806613 DQS0 = 0, DQS1 = 0
5949 00:56:39.808642 DQM Delay:
5950 00:56:39.809063 DQM0 = 101, DQM1 = 90
5951 00:56:39.812119 DQ Delay:
5952 00:56:39.815257 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5953 00:56:39.818783 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5954 00:56:39.822072 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =83
5955 00:56:39.825075 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5956 00:56:39.825496
5957 00:56:39.825829
5958 00:56:39.826141 ==
5959 00:56:39.828188 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 00:56:39.831703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 00:56:39.832141 ==
5962 00:56:39.832477
5963 00:56:39.832792
5964 00:56:39.835376 TX Vref Scan disable
5965 00:56:39.835799 == TX Byte 0 ==
5966 00:56:39.841628 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5967 00:56:39.845422 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5968 00:56:39.845936 == TX Byte 1 ==
5969 00:56:39.851701 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5970 00:56:39.854657 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5971 00:56:39.855083 ==
5972 00:56:39.858242 Dram Type= 6, Freq= 0, CH_1, rank 1
5973 00:56:39.861910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5974 00:56:39.862538 ==
5975 00:56:39.862974
5976 00:56:39.863312
5977 00:56:39.864650 TX Vref Scan disable
5978 00:56:39.868479 == TX Byte 0 ==
5979 00:56:39.871595 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5980 00:56:39.875078 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5981 00:56:39.878083 == TX Byte 1 ==
5982 00:56:39.881675 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5983 00:56:39.884791 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5984 00:56:39.888078
5985 00:56:39.888596 [DATLAT]
5986 00:56:39.888937 Freq=933, CH1 RK1
5987 00:56:39.889253
5988 00:56:39.891314 DATLAT Default: 0xb
5989 00:56:39.891840 0, 0xFFFF, sum = 0
5990 00:56:39.894386 1, 0xFFFF, sum = 0
5991 00:56:39.894816 2, 0xFFFF, sum = 0
5992 00:56:39.897885 3, 0xFFFF, sum = 0
5993 00:56:39.898496 4, 0xFFFF, sum = 0
5994 00:56:39.901081 5, 0xFFFF, sum = 0
5995 00:56:39.904690 6, 0xFFFF, sum = 0
5996 00:56:39.905220 7, 0xFFFF, sum = 0
5997 00:56:39.907611 8, 0xFFFF, sum = 0
5998 00:56:39.908037 9, 0xFFFF, sum = 0
5999 00:56:39.911084 10, 0x0, sum = 1
6000 00:56:39.911618 11, 0x0, sum = 2
6001 00:56:39.914519 12, 0x0, sum = 3
6002 00:56:39.915044 13, 0x0, sum = 4
6003 00:56:39.915386 best_step = 11
6004 00:56:39.915695
6005 00:56:39.917963 ==
6006 00:56:39.921220 Dram Type= 6, Freq= 0, CH_1, rank 1
6007 00:56:39.924432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6008 00:56:39.924999 ==
6009 00:56:39.925418 RX Vref Scan: 0
6010 00:56:39.925771
6011 00:56:39.927879 RX Vref 0 -> 0, step: 1
6012 00:56:39.928341
6013 00:56:39.930594 RX Delay -69 -> 252, step: 4
6014 00:56:39.937685 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6015 00:56:39.940702 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6016 00:56:39.944195 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6017 00:56:39.947377 iDelay=207, Bit 3, Center 96 (11 ~ 182) 172
6018 00:56:39.950846 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6019 00:56:39.953501 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
6020 00:56:39.960627 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6021 00:56:39.963898 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6022 00:56:39.967263 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
6023 00:56:39.970480 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6024 00:56:39.974044 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6025 00:56:39.977428 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
6026 00:56:39.983997 iDelay=207, Bit 12, Center 100 (7 ~ 194) 188
6027 00:56:39.986752 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
6028 00:56:39.990764 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6029 00:56:39.993345 iDelay=207, Bit 15, Center 100 (7 ~ 194) 188
6030 00:56:39.993811 ==
6031 00:56:39.997267 Dram Type= 6, Freq= 0, CH_1, rank 1
6032 00:56:40.003656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6033 00:56:40.004210 ==
6034 00:56:40.004580 DQS Delay:
6035 00:56:40.004922 DQS0 = 0, DQS1 = 0
6036 00:56:40.006725 DQM Delay:
6037 00:56:40.007171 DQM0 = 101, DQM1 = 91
6038 00:56:40.010445 DQ Delay:
6039 00:56:40.013393 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =96
6040 00:56:40.016583 DQ4 =98, DQ5 =112, DQ6 =116, DQ7 =98
6041 00:56:40.020299 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =82
6042 00:56:40.023251 DQ12 =100, DQ13 =98, DQ14 =98, DQ15 =100
6043 00:56:40.023718
6044 00:56:40.024174
6045 00:56:40.029879 [DQSOSCAuto] RK1, (LSB)MR18= 0xb04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
6046 00:56:40.033299 CH1 RK1: MR19=505, MR18=B04
6047 00:56:40.039930 CH1_RK1: MR19=0x505, MR18=0xB04, DQSOSC=418, MR23=63, INC=62, DEC=41
6048 00:56:40.043012 [RxdqsGatingPostProcess] freq 933
6049 00:56:40.046276 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6050 00:56:40.049432 best DQS0 dly(2T, 0.5T) = (0, 10)
6051 00:56:40.053208 best DQS1 dly(2T, 0.5T) = (0, 10)
6052 00:56:40.056036 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6053 00:56:40.059378 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6054 00:56:40.062602 best DQS0 dly(2T, 0.5T) = (0, 10)
6055 00:56:40.065661 best DQS1 dly(2T, 0.5T) = (0, 10)
6056 00:56:40.069059 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6057 00:56:40.072632 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6058 00:56:40.075665 Pre-setting of DQS Precalculation
6059 00:56:40.081992 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6060 00:56:40.089008 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6061 00:56:40.095236 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6062 00:56:40.095762
6063 00:56:40.096146
6064 00:56:40.098841 [Calibration Summary] 1866 Mbps
6065 00:56:40.099304 CH 0, Rank 0
6066 00:56:40.102137 SW Impedance : PASS
6067 00:56:40.105918 DUTY Scan : NO K
6068 00:56:40.106490 ZQ Calibration : PASS
6069 00:56:40.108636 Jitter Meter : NO K
6070 00:56:40.112041 CBT Training : PASS
6071 00:56:40.112460 Write leveling : PASS
6072 00:56:40.115238 RX DQS gating : PASS
6073 00:56:40.118461 RX DQ/DQS(RDDQC) : PASS
6074 00:56:40.118880 TX DQ/DQS : PASS
6075 00:56:40.122108 RX DATLAT : PASS
6076 00:56:40.122671 RX DQ/DQS(Engine): PASS
6077 00:56:40.125391 TX OE : NO K
6078 00:56:40.125936 All Pass.
6079 00:56:40.126334
6080 00:56:40.128555 CH 0, Rank 1
6081 00:56:40.129077 SW Impedance : PASS
6082 00:56:40.131959 DUTY Scan : NO K
6083 00:56:40.135254 ZQ Calibration : PASS
6084 00:56:40.135882 Jitter Meter : NO K
6085 00:56:40.138202 CBT Training : PASS
6086 00:56:40.141602 Write leveling : PASS
6087 00:56:40.142022 RX DQS gating : PASS
6088 00:56:40.145123 RX DQ/DQS(RDDQC) : PASS
6089 00:56:40.148362 TX DQ/DQS : PASS
6090 00:56:40.148787 RX DATLAT : PASS
6091 00:56:40.151272 RX DQ/DQS(Engine): PASS
6092 00:56:40.154773 TX OE : NO K
6093 00:56:40.155214 All Pass.
6094 00:56:40.155567
6095 00:56:40.155941 CH 1, Rank 0
6096 00:56:40.158574 SW Impedance : PASS
6097 00:56:40.161216 DUTY Scan : NO K
6098 00:56:40.161638 ZQ Calibration : PASS
6099 00:56:40.164755 Jitter Meter : NO K
6100 00:56:40.168130 CBT Training : PASS
6101 00:56:40.168551 Write leveling : PASS
6102 00:56:40.171655 RX DQS gating : PASS
6103 00:56:40.174526 RX DQ/DQS(RDDQC) : PASS
6104 00:56:40.175121 TX DQ/DQS : PASS
6105 00:56:40.177744 RX DATLAT : PASS
6106 00:56:40.181154 RX DQ/DQS(Engine): PASS
6107 00:56:40.181675 TX OE : NO K
6108 00:56:40.184879 All Pass.
6109 00:56:40.185401
6110 00:56:40.185813 CH 1, Rank 1
6111 00:56:40.187427 SW Impedance : PASS
6112 00:56:40.187849 DUTY Scan : NO K
6113 00:56:40.191165 ZQ Calibration : PASS
6114 00:56:40.194403 Jitter Meter : NO K
6115 00:56:40.194948 CBT Training : PASS
6116 00:56:40.197490 Write leveling : PASS
6117 00:56:40.200939 RX DQS gating : PASS
6118 00:56:40.201460 RX DQ/DQS(RDDQC) : PASS
6119 00:56:40.204182 TX DQ/DQS : PASS
6120 00:56:40.204768 RX DATLAT : PASS
6121 00:56:40.207337 RX DQ/DQS(Engine): PASS
6122 00:56:40.210774 TX OE : NO K
6123 00:56:40.211346 All Pass.
6124 00:56:40.211728
6125 00:56:40.213908 DramC Write-DBI off
6126 00:56:40.217697 PER_BANK_REFRESH: Hybrid Mode
6127 00:56:40.218119 TX_TRACKING: ON
6128 00:56:40.227106 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6129 00:56:40.230510 [FAST_K] Save calibration result to emmc
6130 00:56:40.233620 dramc_set_vcore_voltage set vcore to 650000
6131 00:56:40.237200 Read voltage for 400, 6
6132 00:56:40.237724 Vio18 = 0
6133 00:56:40.238060 Vcore = 650000
6134 00:56:40.240790 Vdram = 0
6135 00:56:40.241355 Vddq = 0
6136 00:56:40.241704 Vmddr = 0
6137 00:56:40.246773 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6138 00:56:40.250475 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6139 00:56:40.253376 MEM_TYPE=3, freq_sel=20
6140 00:56:40.256928 sv_algorithm_assistance_LP4_800
6141 00:56:40.260447 ============ PULL DRAM RESETB DOWN ============
6142 00:56:40.263390 ========== PULL DRAM RESETB DOWN end =========
6143 00:56:40.269969 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6144 00:56:40.273445 ===================================
6145 00:56:40.273962 LPDDR4 DRAM CONFIGURATION
6146 00:56:40.276613 ===================================
6147 00:56:40.280553 EX_ROW_EN[0] = 0x0
6148 00:56:40.283665 EX_ROW_EN[1] = 0x0
6149 00:56:40.284188 LP4Y_EN = 0x0
6150 00:56:40.286540 WORK_FSP = 0x0
6151 00:56:40.287060 WL = 0x2
6152 00:56:40.290206 RL = 0x2
6153 00:56:40.290741 BL = 0x2
6154 00:56:40.292964 RPST = 0x0
6155 00:56:40.293384 RD_PRE = 0x0
6156 00:56:40.296449 WR_PRE = 0x1
6157 00:56:40.296870 WR_PST = 0x0
6158 00:56:40.299733 DBI_WR = 0x0
6159 00:56:40.300152 DBI_RD = 0x0
6160 00:56:40.302965 OTF = 0x1
6161 00:56:40.306898 ===================================
6162 00:56:40.310147 ===================================
6163 00:56:40.310700 ANA top config
6164 00:56:40.312733 ===================================
6165 00:56:40.316405 DLL_ASYNC_EN = 0
6166 00:56:40.319065 ALL_SLAVE_EN = 1
6167 00:56:40.322878 NEW_RANK_MODE = 1
6168 00:56:40.323319 DLL_IDLE_MODE = 1
6169 00:56:40.326262 LP45_APHY_COMB_EN = 1
6170 00:56:40.329598 TX_ODT_DIS = 1
6171 00:56:40.332788 NEW_8X_MODE = 1
6172 00:56:40.335812 ===================================
6173 00:56:40.339180 ===================================
6174 00:56:40.342366 data_rate = 800
6175 00:56:40.345528 CKR = 1
6176 00:56:40.345947 DQ_P2S_RATIO = 4
6177 00:56:40.349138 ===================================
6178 00:56:40.352157 CA_P2S_RATIO = 4
6179 00:56:40.355422 DQ_CA_OPEN = 0
6180 00:56:40.358559 DQ_SEMI_OPEN = 1
6181 00:56:40.362093 CA_SEMI_OPEN = 1
6182 00:56:40.365369 CA_FULL_RATE = 0
6183 00:56:40.365790 DQ_CKDIV4_EN = 0
6184 00:56:40.368410 CA_CKDIV4_EN = 1
6185 00:56:40.372058 CA_PREDIV_EN = 0
6186 00:56:40.375588 PH8_DLY = 0
6187 00:56:40.378933 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6188 00:56:40.381809 DQ_AAMCK_DIV = 0
6189 00:56:40.382424 CA_AAMCK_DIV = 0
6190 00:56:40.385104 CA_ADMCK_DIV = 4
6191 00:56:40.388784 DQ_TRACK_CA_EN = 0
6192 00:56:40.392097 CA_PICK = 800
6193 00:56:40.394985 CA_MCKIO = 400
6194 00:56:40.398228 MCKIO_SEMI = 400
6195 00:56:40.401797 PLL_FREQ = 3016
6196 00:56:40.405353 DQ_UI_PI_RATIO = 32
6197 00:56:40.405772 CA_UI_PI_RATIO = 32
6198 00:56:40.408703 ===================================
6199 00:56:40.411728 ===================================
6200 00:56:40.414903 memory_type:LPDDR4
6201 00:56:40.418369 GP_NUM : 10
6202 00:56:40.418788 SRAM_EN : 1
6203 00:56:40.421464 MD32_EN : 0
6204 00:56:40.424778 ===================================
6205 00:56:40.428156 [ANA_INIT] >>>>>>>>>>>>>>
6206 00:56:40.431447 <<<<<< [CONFIGURE PHASE]: ANA_TX
6207 00:56:40.434702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6208 00:56:40.437875 ===================================
6209 00:56:40.438332 data_rate = 800,PCW = 0X7400
6210 00:56:40.441529 ===================================
6211 00:56:40.444537 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6212 00:56:40.451178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6213 00:56:40.464270 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6214 00:56:40.467366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6215 00:56:40.470857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6216 00:56:40.474023 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6217 00:56:40.477628 [ANA_INIT] flow start
6218 00:56:40.478048 [ANA_INIT] PLL >>>>>>>>
6219 00:56:40.480676 [ANA_INIT] PLL <<<<<<<<
6220 00:56:40.484056 [ANA_INIT] MIDPI >>>>>>>>
6221 00:56:40.488149 [ANA_INIT] MIDPI <<<<<<<<
6222 00:56:40.488669 [ANA_INIT] DLL >>>>>>>>
6223 00:56:40.491228 [ANA_INIT] flow end
6224 00:56:40.494046 ============ LP4 DIFF to SE enter ============
6225 00:56:40.497684 ============ LP4 DIFF to SE exit ============
6226 00:56:40.500630 [ANA_INIT] <<<<<<<<<<<<<
6227 00:56:40.504120 [Flow] Enable top DCM control >>>>>
6228 00:56:40.507248 [Flow] Enable top DCM control <<<<<
6229 00:56:40.510501 Enable DLL master slave shuffle
6230 00:56:40.517434 ==============================================================
6231 00:56:40.518024 Gating Mode config
6232 00:56:40.523995 ==============================================================
6233 00:56:40.524509 Config description:
6234 00:56:40.534224 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6235 00:56:40.540599 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6236 00:56:40.546652 SELPH_MODE 0: By rank 1: By Phase
6237 00:56:40.550313 ==============================================================
6238 00:56:40.553338 GAT_TRACK_EN = 0
6239 00:56:40.557317 RX_GATING_MODE = 2
6240 00:56:40.559850 RX_GATING_TRACK_MODE = 2
6241 00:56:40.563150 SELPH_MODE = 1
6242 00:56:40.566797 PICG_EARLY_EN = 1
6243 00:56:40.570023 VALID_LAT_VALUE = 1
6244 00:56:40.576860 ==============================================================
6245 00:56:40.579836 Enter into Gating configuration >>>>
6246 00:56:40.583281 Exit from Gating configuration <<<<
6247 00:56:40.586849 Enter into DVFS_PRE_config >>>>>
6248 00:56:40.596389 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6249 00:56:40.599258 Exit from DVFS_PRE_config <<<<<
6250 00:56:40.603166 Enter into PICG configuration >>>>
6251 00:56:40.606304 Exit from PICG configuration <<<<
6252 00:56:40.609231 [RX_INPUT] configuration >>>>>
6253 00:56:40.609698 [RX_INPUT] configuration <<<<<
6254 00:56:40.616042 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6255 00:56:40.622325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6256 00:56:40.629596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6257 00:56:40.632734 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6258 00:56:40.638865 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6259 00:56:40.645673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6260 00:56:40.648784 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6261 00:56:40.655831 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6262 00:56:40.658712 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6263 00:56:40.662440 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6264 00:56:40.665451 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6265 00:56:40.672262 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6266 00:56:40.675558 ===================================
6267 00:56:40.676163 LPDDR4 DRAM CONFIGURATION
6268 00:56:40.679004 ===================================
6269 00:56:40.681772 EX_ROW_EN[0] = 0x0
6270 00:56:40.685093 EX_ROW_EN[1] = 0x0
6271 00:56:40.685605 LP4Y_EN = 0x0
6272 00:56:40.688430 WORK_FSP = 0x0
6273 00:56:40.688997 WL = 0x2
6274 00:56:40.691944 RL = 0x2
6275 00:56:40.692413 BL = 0x2
6276 00:56:40.695215 RPST = 0x0
6277 00:56:40.695636 RD_PRE = 0x0
6278 00:56:40.698561 WR_PRE = 0x1
6279 00:56:40.699090 WR_PST = 0x0
6280 00:56:40.701922 DBI_WR = 0x0
6281 00:56:40.702398 DBI_RD = 0x0
6282 00:56:40.704948 OTF = 0x1
6283 00:56:40.708236 ===================================
6284 00:56:40.711477 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6285 00:56:40.714731 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6286 00:56:40.721261 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6287 00:56:40.724591 ===================================
6288 00:56:40.725015 LPDDR4 DRAM CONFIGURATION
6289 00:56:40.727841 ===================================
6290 00:56:40.731339 EX_ROW_EN[0] = 0x10
6291 00:56:40.734614 EX_ROW_EN[1] = 0x0
6292 00:56:40.735039 LP4Y_EN = 0x0
6293 00:56:40.737797 WORK_FSP = 0x0
6294 00:56:40.738240 WL = 0x2
6295 00:56:40.741251 RL = 0x2
6296 00:56:40.741674 BL = 0x2
6297 00:56:40.744421 RPST = 0x0
6298 00:56:40.744845 RD_PRE = 0x0
6299 00:56:40.748062 WR_PRE = 0x1
6300 00:56:40.748613 WR_PST = 0x0
6301 00:56:40.751660 DBI_WR = 0x0
6302 00:56:40.752083 DBI_RD = 0x0
6303 00:56:40.754597 OTF = 0x1
6304 00:56:40.757994 ===================================
6305 00:56:40.764495 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6306 00:56:40.767927 nWR fixed to 30
6307 00:56:40.770843 [ModeRegInit_LP4] CH0 RK0
6308 00:56:40.771266 [ModeRegInit_LP4] CH0 RK1
6309 00:56:40.774504 [ModeRegInit_LP4] CH1 RK0
6310 00:56:40.777610 [ModeRegInit_LP4] CH1 RK1
6311 00:56:40.778228 match AC timing 19
6312 00:56:40.784515 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6313 00:56:40.787771 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6314 00:56:40.791247 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6315 00:56:40.797803 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6316 00:56:40.800864 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6317 00:56:40.801536 ==
6318 00:56:40.804367 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 00:56:40.807423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 00:56:40.807910 ==
6321 00:56:40.814317 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6322 00:56:40.820493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6323 00:56:40.824066 [CA 0] Center 36 (8~64) winsize 57
6324 00:56:40.827056 [CA 1] Center 36 (8~64) winsize 57
6325 00:56:40.830483 [CA 2] Center 36 (8~64) winsize 57
6326 00:56:40.833628 [CA 3] Center 36 (8~64) winsize 57
6327 00:56:40.837124 [CA 4] Center 36 (8~64) winsize 57
6328 00:56:40.837650 [CA 5] Center 36 (8~64) winsize 57
6329 00:56:40.840271
6330 00:56:40.843461 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6331 00:56:40.844111
6332 00:56:40.846833 [CATrainingPosCal] consider 1 rank data
6333 00:56:40.850035 u2DelayCellTimex100 = 270/100 ps
6334 00:56:40.853493 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 00:56:40.856708 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 00:56:40.860728 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 00:56:40.863524 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 00:56:40.866892 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 00:56:40.869782 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 00:56:40.870286
6341 00:56:40.873459 CA PerBit enable=1, Macro0, CA PI delay=36
6342 00:56:40.874032
6343 00:56:40.876755 [CBTSetCACLKResult] CA Dly = 36
6344 00:56:40.880611 CS Dly: 1 (0~32)
6345 00:56:40.881178 ==
6346 00:56:40.883539 Dram Type= 6, Freq= 0, CH_0, rank 1
6347 00:56:40.886601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 00:56:40.887421 ==
6349 00:56:40.893323 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6350 00:56:40.899876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6351 00:56:40.902999 [CA 0] Center 36 (8~64) winsize 57
6352 00:56:40.906284 [CA 1] Center 36 (8~64) winsize 57
6353 00:56:40.909375 [CA 2] Center 36 (8~64) winsize 57
6354 00:56:40.909923 [CA 3] Center 36 (8~64) winsize 57
6355 00:56:40.912875 [CA 4] Center 36 (8~64) winsize 57
6356 00:56:40.916181 [CA 5] Center 36 (8~64) winsize 57
6357 00:56:40.916651
6358 00:56:40.922807 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6359 00:56:40.923278
6360 00:56:40.925897 [CATrainingPosCal] consider 2 rank data
6361 00:56:40.929473 u2DelayCellTimex100 = 270/100 ps
6362 00:56:40.932625 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6363 00:56:40.935599 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6364 00:56:40.938966 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6365 00:56:40.942246 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6366 00:56:40.945497 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 00:56:40.949101 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 00:56:40.949627
6369 00:56:40.952335 CA PerBit enable=1, Macro0, CA PI delay=36
6370 00:56:40.952757
6371 00:56:40.955449 [CBTSetCACLKResult] CA Dly = 36
6372 00:56:40.958576 CS Dly: 1 (0~32)
6373 00:56:40.959017
6374 00:56:40.962074 ----->DramcWriteLeveling(PI) begin...
6375 00:56:40.962559 ==
6376 00:56:40.965639 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 00:56:40.969137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 00:56:40.969664 ==
6379 00:56:40.971960 Write leveling (Byte 0): 40 => 8
6380 00:56:40.975921 Write leveling (Byte 1): 32 => 0
6381 00:56:40.978764 DramcWriteLeveling(PI) end<-----
6382 00:56:40.979328
6383 00:56:40.979696 ==
6384 00:56:40.982158 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 00:56:40.984840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 00:56:40.985331 ==
6387 00:56:40.988684 [Gating] SW mode calibration
6388 00:56:40.994996 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6389 00:56:41.002122 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6390 00:56:41.005199 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6391 00:56:41.011145 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6392 00:56:41.014542 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6393 00:56:41.018292 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6394 00:56:41.024788 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6395 00:56:41.028064 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6396 00:56:41.030874 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6397 00:56:41.037685 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6398 00:56:41.041572 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6399 00:56:41.044330 Total UI for P1: 0, mck2ui 16
6400 00:56:41.048058 best dqsien dly found for B0: ( 0, 14, 24)
6401 00:56:41.051728 Total UI for P1: 0, mck2ui 16
6402 00:56:41.054535 best dqsien dly found for B1: ( 0, 14, 24)
6403 00:56:41.057732 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6404 00:56:41.060938 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6405 00:56:41.061400
6406 00:56:41.064436 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6407 00:56:41.067844 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6408 00:56:41.070796 [Gating] SW calibration Done
6409 00:56:41.071256 ==
6410 00:56:41.074840 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 00:56:41.077644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 00:56:41.081305 ==
6413 00:56:41.081865 RX Vref Scan: 0
6414 00:56:41.082282
6415 00:56:41.084185 RX Vref 0 -> 0, step: 1
6416 00:56:41.084744
6417 00:56:41.087647 RX Delay -410 -> 252, step: 16
6418 00:56:41.090829 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6419 00:56:41.094314 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6420 00:56:41.097464 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6421 00:56:41.104622 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6422 00:56:41.107219 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6423 00:56:41.110458 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6424 00:56:41.114074 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6425 00:56:41.120896 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6426 00:56:41.123471 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6427 00:56:41.126776 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6428 00:56:41.134025 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6429 00:56:41.136864 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6430 00:56:41.140142 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6431 00:56:41.143322 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6432 00:56:41.150331 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6433 00:56:41.153821 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6434 00:56:41.154332 ==
6435 00:56:41.157046 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 00:56:41.159983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 00:56:41.160457 ==
6438 00:56:41.163352 DQS Delay:
6439 00:56:41.163814 DQS0 = 43, DQS1 = 59
6440 00:56:41.166393 DQM Delay:
6441 00:56:41.166857 DQM0 = 10, DQM1 = 11
6442 00:56:41.167227 DQ Delay:
6443 00:56:41.170460 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6444 00:56:41.173062 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6445 00:56:41.176741 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6446 00:56:41.179869 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6447 00:56:41.180431
6448 00:56:41.180803
6449 00:56:41.181141 ==
6450 00:56:41.183435 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 00:56:41.189708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 00:56:41.190325 ==
6453 00:56:41.190702
6454 00:56:41.191043
6455 00:56:41.191437 TX Vref Scan disable
6456 00:56:41.193568 == TX Byte 0 ==
6457 00:56:41.196518 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6458 00:56:41.199797 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6459 00:56:41.203263 == TX Byte 1 ==
6460 00:56:41.206319 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6461 00:56:41.210112 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6462 00:56:41.210738 ==
6463 00:56:41.213078 Dram Type= 6, Freq= 0, CH_0, rank 0
6464 00:56:41.219969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 00:56:41.220550 ==
6466 00:56:41.220929
6467 00:56:41.221273
6468 00:56:41.221598 TX Vref Scan disable
6469 00:56:41.223112 == TX Byte 0 ==
6470 00:56:41.226353 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6471 00:56:41.229454 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6472 00:56:41.232623 == TX Byte 1 ==
6473 00:56:41.236472 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6474 00:56:41.242897 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6475 00:56:41.243471
6476 00:56:41.243840 [DATLAT]
6477 00:56:41.244195 Freq=400, CH0 RK0
6478 00:56:41.244582
6479 00:56:41.245747 DATLAT Default: 0xf
6480 00:56:41.246256 0, 0xFFFF, sum = 0
6481 00:56:41.249112 1, 0xFFFF, sum = 0
6482 00:56:41.253031 2, 0xFFFF, sum = 0
6483 00:56:41.253597 3, 0xFFFF, sum = 0
6484 00:56:41.255802 4, 0xFFFF, sum = 0
6485 00:56:41.256274 5, 0xFFFF, sum = 0
6486 00:56:41.259281 6, 0xFFFF, sum = 0
6487 00:56:41.259766 7, 0xFFFF, sum = 0
6488 00:56:41.262895 8, 0xFFFF, sum = 0
6489 00:56:41.263493 9, 0xFFFF, sum = 0
6490 00:56:41.265774 10, 0xFFFF, sum = 0
6491 00:56:41.266392 11, 0xFFFF, sum = 0
6492 00:56:41.269158 12, 0xFFFF, sum = 0
6493 00:56:41.269628 13, 0x0, sum = 1
6494 00:56:41.272425 14, 0x0, sum = 2
6495 00:56:41.272931 15, 0x0, sum = 3
6496 00:56:41.276033 16, 0x0, sum = 4
6497 00:56:41.276607 best_step = 14
6498 00:56:41.276976
6499 00:56:41.277311 ==
6500 00:56:41.278914 Dram Type= 6, Freq= 0, CH_0, rank 0
6501 00:56:41.282606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 00:56:41.285780 ==
6503 00:56:41.286389 RX Vref Scan: 1
6504 00:56:41.286765
6505 00:56:41.288825 RX Vref 0 -> 0, step: 1
6506 00:56:41.289287
6507 00:56:41.292463 RX Delay -359 -> 252, step: 8
6508 00:56:41.292927
6509 00:56:41.295325 Set Vref, RX VrefLevel [Byte0]: 59
6510 00:56:41.299098 [Byte1]: 58
6511 00:56:41.299664
6512 00:56:41.302205 Final RX Vref Byte 0 = 59 to rank0
6513 00:56:41.305301 Final RX Vref Byte 1 = 58 to rank0
6514 00:56:41.308763 Final RX Vref Byte 0 = 59 to rank1
6515 00:56:41.311889 Final RX Vref Byte 1 = 58 to rank1==
6516 00:56:41.315271 Dram Type= 6, Freq= 0, CH_0, rank 0
6517 00:56:41.318345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 00:56:41.321915 ==
6519 00:56:41.322498 DQS Delay:
6520 00:56:41.322868 DQS0 = 48, DQS1 = 60
6521 00:56:41.325017 DQM Delay:
6522 00:56:41.325476 DQM0 = 11, DQM1 = 10
6523 00:56:41.328424 DQ Delay:
6524 00:56:41.328887 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6525 00:56:41.331877 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6526 00:56:41.334981 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6527 00:56:41.338481 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =20
6528 00:56:41.338944
6529 00:56:41.339304
6530 00:56:41.348176 [DQSOSCAuto] RK0, (LSB)MR18= 0xc487, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6531 00:56:41.351734 CH0 RK0: MR19=C0C, MR18=C487
6532 00:56:41.358220 CH0_RK0: MR19=0xC0C, MR18=0xC487, DQSOSC=385, MR23=63, INC=398, DEC=265
6533 00:56:41.358648 ==
6534 00:56:41.361704 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 00:56:41.364757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 00:56:41.365279 ==
6537 00:56:41.368011 [Gating] SW mode calibration
6538 00:56:41.374645 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6539 00:56:41.381129 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6540 00:56:41.384622 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6541 00:56:41.388017 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6542 00:56:41.394920 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6543 00:56:41.397955 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6544 00:56:41.400898 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6545 00:56:41.407597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6546 00:56:41.410985 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6547 00:56:41.414270 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6548 00:56:41.421084 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6549 00:56:41.421508 Total UI for P1: 0, mck2ui 16
6550 00:56:41.424233 best dqsien dly found for B0: ( 0, 14, 24)
6551 00:56:41.427349 Total UI for P1: 0, mck2ui 16
6552 00:56:41.431034 best dqsien dly found for B1: ( 0, 14, 24)
6553 00:56:41.437462 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6554 00:56:41.441036 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6555 00:56:41.441562
6556 00:56:41.443923 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6557 00:56:41.447578 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6558 00:56:41.450574 [Gating] SW calibration Done
6559 00:56:41.451041 ==
6560 00:56:41.453725 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 00:56:41.457266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 00:56:41.457741 ==
6563 00:56:41.460659 RX Vref Scan: 0
6564 00:56:41.461221
6565 00:56:41.461591 RX Vref 0 -> 0, step: 1
6566 00:56:41.461937
6567 00:56:41.463541 RX Delay -410 -> 252, step: 16
6568 00:56:41.470379 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6569 00:56:41.473785 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6570 00:56:41.476966 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6571 00:56:41.479892 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6572 00:56:41.486448 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6573 00:56:41.489728 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6574 00:56:41.493105 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6575 00:56:41.496138 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6576 00:56:41.502853 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6577 00:56:41.506062 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6578 00:56:41.509488 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6579 00:56:41.516140 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6580 00:56:41.519689 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6581 00:56:41.522778 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6582 00:56:41.525685 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6583 00:56:41.532227 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6584 00:56:41.532672 ==
6585 00:56:41.535722 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 00:56:41.538828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 00:56:41.539259 ==
6588 00:56:41.539595 DQS Delay:
6589 00:56:41.542033 DQS0 = 43, DQS1 = 59
6590 00:56:41.542486 DQM Delay:
6591 00:56:41.545728 DQM0 = 9, DQM1 = 12
6592 00:56:41.546144 DQ Delay:
6593 00:56:41.549223 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6594 00:56:41.552384 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6595 00:56:41.555691 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6596 00:56:41.558674 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6597 00:56:41.559100
6598 00:56:41.559440
6599 00:56:41.559750 ==
6600 00:56:41.561765 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 00:56:41.565115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 00:56:41.565550 ==
6603 00:56:41.568340
6604 00:56:41.568841
6605 00:56:41.569186 TX Vref Scan disable
6606 00:56:41.572029 == TX Byte 0 ==
6607 00:56:41.575529 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6608 00:56:41.578250 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6609 00:56:41.581866 == TX Byte 1 ==
6610 00:56:41.585247 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6611 00:56:41.588169 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6612 00:56:41.588593 ==
6613 00:56:41.592205 Dram Type= 6, Freq= 0, CH_0, rank 1
6614 00:56:41.595116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 00:56:41.598250 ==
6616 00:56:41.598672
6617 00:56:41.599008
6618 00:56:41.599320 TX Vref Scan disable
6619 00:56:41.601594 == TX Byte 0 ==
6620 00:56:41.605449 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6621 00:56:41.608410 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6622 00:56:41.611720 == TX Byte 1 ==
6623 00:56:41.614813 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6624 00:56:41.618491 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6625 00:56:41.618914
6626 00:56:41.619246 [DATLAT]
6627 00:56:41.622054 Freq=400, CH0 RK1
6628 00:56:41.622502
6629 00:56:41.624838 DATLAT Default: 0xe
6630 00:56:41.625257 0, 0xFFFF, sum = 0
6631 00:56:41.628202 1, 0xFFFF, sum = 0
6632 00:56:41.628630 2, 0xFFFF, sum = 0
6633 00:56:41.631471 3, 0xFFFF, sum = 0
6634 00:56:41.631935 4, 0xFFFF, sum = 0
6635 00:56:41.634800 5, 0xFFFF, sum = 0
6636 00:56:41.635228 6, 0xFFFF, sum = 0
6637 00:56:41.637975 7, 0xFFFF, sum = 0
6638 00:56:41.638437 8, 0xFFFF, sum = 0
6639 00:56:41.641201 9, 0xFFFF, sum = 0
6640 00:56:41.641625 10, 0xFFFF, sum = 0
6641 00:56:41.644512 11, 0xFFFF, sum = 0
6642 00:56:41.644941 12, 0xFFFF, sum = 0
6643 00:56:41.648298 13, 0x0, sum = 1
6644 00:56:41.648821 14, 0x0, sum = 2
6645 00:56:41.651449 15, 0x0, sum = 3
6646 00:56:41.651913 16, 0x0, sum = 4
6647 00:56:41.654574 best_step = 14
6648 00:56:41.654992
6649 00:56:41.655324 ==
6650 00:56:41.657733 Dram Type= 6, Freq= 0, CH_0, rank 1
6651 00:56:41.661522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 00:56:41.662068 ==
6653 00:56:41.664288 RX Vref Scan: 0
6654 00:56:41.664703
6655 00:56:41.665035 RX Vref 0 -> 0, step: 1
6656 00:56:41.665363
6657 00:56:41.667534 RX Delay -359 -> 252, step: 8
6658 00:56:41.676178 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6659 00:56:41.678988 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6660 00:56:41.682782 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6661 00:56:41.688833 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6662 00:56:41.692223 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6663 00:56:41.695308 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6664 00:56:41.699127 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6665 00:56:41.706054 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6666 00:56:41.708991 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6667 00:56:41.712118 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6668 00:56:41.715363 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6669 00:56:41.722108 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6670 00:56:41.725117 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6671 00:56:41.728679 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6672 00:56:41.732271 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6673 00:56:41.738508 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6674 00:56:41.738978 ==
6675 00:56:41.741870 Dram Type= 6, Freq= 0, CH_0, rank 1
6676 00:56:41.745117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 00:56:41.745698 ==
6678 00:56:41.748084 DQS Delay:
6679 00:56:41.748543 DQS0 = 44, DQS1 = 60
6680 00:56:41.748908 DQM Delay:
6681 00:56:41.751449 DQM0 = 7, DQM1 = 14
6682 00:56:41.751911 DQ Delay:
6683 00:56:41.754834 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =4
6684 00:56:41.758078 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6685 00:56:41.761542 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6686 00:56:41.765094 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6687 00:56:41.765665
6688 00:56:41.766036
6689 00:56:41.771390 [DQSOSCAuto] RK1, (LSB)MR18= 0xb743, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6690 00:56:41.775013 CH0 RK1: MR19=C0C, MR18=B743
6691 00:56:41.781584 CH0_RK1: MR19=0xC0C, MR18=0xB743, DQSOSC=387, MR23=63, INC=394, DEC=262
6692 00:56:41.784969 [RxdqsGatingPostProcess] freq 400
6693 00:56:41.791284 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6694 00:56:41.794232 best DQS0 dly(2T, 0.5T) = (0, 10)
6695 00:56:41.797833 best DQS1 dly(2T, 0.5T) = (0, 10)
6696 00:56:41.800826 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6697 00:56:41.804697 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6698 00:56:41.807810 best DQS0 dly(2T, 0.5T) = (0, 10)
6699 00:56:41.808408 best DQS1 dly(2T, 0.5T) = (0, 10)
6700 00:56:41.810668 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6701 00:56:41.814263 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6702 00:56:41.817236 Pre-setting of DQS Precalculation
6703 00:56:41.823983 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6704 00:56:41.824469 ==
6705 00:56:41.827280 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 00:56:41.830426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 00:56:41.830902 ==
6708 00:56:41.837230 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6709 00:56:41.843554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6710 00:56:41.846768 [CA 0] Center 36 (8~64) winsize 57
6711 00:56:41.850245 [CA 1] Center 36 (8~64) winsize 57
6712 00:56:41.853643 [CA 2] Center 36 (8~64) winsize 57
6713 00:56:41.856916 [CA 3] Center 36 (8~64) winsize 57
6714 00:56:41.857499 [CA 4] Center 36 (8~64) winsize 57
6715 00:56:41.860207 [CA 5] Center 36 (8~64) winsize 57
6716 00:56:41.860676
6717 00:56:41.866787 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6718 00:56:41.867361
6719 00:56:41.869905 [CATrainingPosCal] consider 1 rank data
6720 00:56:41.873791 u2DelayCellTimex100 = 270/100 ps
6721 00:56:41.876841 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 00:56:41.880362 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 00:56:41.883171 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 00:56:41.886545 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 00:56:41.889813 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 00:56:41.893065 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 00:56:41.893640
6728 00:56:41.896343 CA PerBit enable=1, Macro0, CA PI delay=36
6729 00:56:41.896922
6730 00:56:41.899798 [CBTSetCACLKResult] CA Dly = 36
6731 00:56:41.903426 CS Dly: 1 (0~32)
6732 00:56:41.903996 ==
6733 00:56:41.906623 Dram Type= 6, Freq= 0, CH_1, rank 1
6734 00:56:41.909789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 00:56:41.910399 ==
6736 00:56:41.916092 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6737 00:56:41.922615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6738 00:56:41.926132 [CA 0] Center 36 (8~64) winsize 57
6739 00:56:41.929106 [CA 1] Center 36 (8~64) winsize 57
6740 00:56:41.929800 [CA 2] Center 36 (8~64) winsize 57
6741 00:56:41.932717 [CA 3] Center 36 (8~64) winsize 57
6742 00:56:41.935776 [CA 4] Center 36 (8~64) winsize 57
6743 00:56:41.938915 [CA 5] Center 36 (8~64) winsize 57
6744 00:56:41.939388
6745 00:56:41.942286 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6746 00:56:41.945923
6747 00:56:41.949142 [CATrainingPosCal] consider 2 rank data
6748 00:56:41.949821 u2DelayCellTimex100 = 270/100 ps
6749 00:56:41.955816 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6750 00:56:41.958960 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6751 00:56:41.962295 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6752 00:56:41.966077 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6753 00:56:41.969258 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6754 00:56:41.972444 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6755 00:56:41.973049
6756 00:56:41.975782 CA PerBit enable=1, Macro0, CA PI delay=36
6757 00:56:41.976253
6758 00:56:41.978911 [CBTSetCACLKResult] CA Dly = 36
6759 00:56:41.982400 CS Dly: 1 (0~32)
6760 00:56:41.982964
6761 00:56:41.985650 ----->DramcWriteLeveling(PI) begin...
6762 00:56:41.986257 ==
6763 00:56:41.988885 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 00:56:41.992662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 00:56:41.993228 ==
6766 00:56:41.995460 Write leveling (Byte 0): 40 => 8
6767 00:56:41.999494 Write leveling (Byte 1): 40 => 8
6768 00:56:42.002328 DramcWriteLeveling(PI) end<-----
6769 00:56:42.002931
6770 00:56:42.003362 ==
6771 00:56:42.005594 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 00:56:42.008910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 00:56:42.009478 ==
6774 00:56:42.011795 [Gating] SW mode calibration
6775 00:56:42.018883 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6776 00:56:42.025726 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6777 00:56:42.028175 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6778 00:56:42.031595 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6779 00:56:42.038880 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6780 00:56:42.041449 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6781 00:56:42.044731 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6782 00:56:42.051540 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6783 00:56:42.054860 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6784 00:56:42.057997 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6785 00:56:42.065043 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6786 00:56:42.068103 Total UI for P1: 0, mck2ui 16
6787 00:56:42.071151 best dqsien dly found for B0: ( 0, 14, 24)
6788 00:56:42.074578 Total UI for P1: 0, mck2ui 16
6789 00:56:42.077579 best dqsien dly found for B1: ( 0, 14, 24)
6790 00:56:42.080931 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6791 00:56:42.084957 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6792 00:56:42.085520
6793 00:56:42.087599 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6794 00:56:42.091756 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6795 00:56:42.094823 [Gating] SW calibration Done
6796 00:56:42.095383 ==
6797 00:56:42.097434 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 00:56:42.100586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 00:56:42.101054 ==
6800 00:56:42.104738 RX Vref Scan: 0
6801 00:56:42.105300
6802 00:56:42.107860 RX Vref 0 -> 0, step: 1
6803 00:56:42.108463
6804 00:56:42.108841 RX Delay -410 -> 252, step: 16
6805 00:56:42.114141 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6806 00:56:42.117579 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6807 00:56:42.120949 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6808 00:56:42.127262 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6809 00:56:42.130526 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6810 00:56:42.134480 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6811 00:56:42.137732 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6812 00:56:42.144005 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6813 00:56:42.146889 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6814 00:56:42.150432 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6815 00:56:42.154197 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6816 00:56:42.160793 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6817 00:56:42.163805 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6818 00:56:42.167311 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6819 00:56:42.170537 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6820 00:56:42.177140 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6821 00:56:42.177662 ==
6822 00:56:42.180435 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 00:56:42.183858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 00:56:42.184434 ==
6825 00:56:42.184791 DQS Delay:
6826 00:56:42.186892 DQS0 = 43, DQS1 = 51
6827 00:56:42.187372 DQM Delay:
6828 00:56:42.190427 DQM0 = 12, DQM1 = 14
6829 00:56:42.190853 DQ Delay:
6830 00:56:42.193733 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6831 00:56:42.196757 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6832 00:56:42.200130 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6833 00:56:42.203471 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6834 00:56:42.204102
6835 00:56:42.204487
6836 00:56:42.204836 ==
6837 00:56:42.206648 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 00:56:42.210631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 00:56:42.211209 ==
6840 00:56:42.211591
6841 00:56:42.213101
6842 00:56:42.213570 TX Vref Scan disable
6843 00:56:42.216489 == TX Byte 0 ==
6844 00:56:42.220034 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6845 00:56:42.223147 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6846 00:56:42.226416 == TX Byte 1 ==
6847 00:56:42.229977 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6848 00:56:42.233353 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6849 00:56:42.233826 ==
6850 00:56:42.236287 Dram Type= 6, Freq= 0, CH_1, rank 0
6851 00:56:42.239281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 00:56:42.242884 ==
6853 00:56:42.243354
6854 00:56:42.243727
6855 00:56:42.244085 TX Vref Scan disable
6856 00:56:42.246235 == TX Byte 0 ==
6857 00:56:42.249386 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6858 00:56:42.253124 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6859 00:56:42.256174 == TX Byte 1 ==
6860 00:56:42.259044 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6861 00:56:42.262878 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6862 00:56:42.263413
6863 00:56:42.266075 [DATLAT]
6864 00:56:42.266643 Freq=400, CH1 RK0
6865 00:56:42.266992
6866 00:56:42.269423 DATLAT Default: 0xf
6867 00:56:42.269929 0, 0xFFFF, sum = 0
6868 00:56:42.273025 1, 0xFFFF, sum = 0
6869 00:56:42.273567 2, 0xFFFF, sum = 0
6870 00:56:42.275674 3, 0xFFFF, sum = 0
6871 00:56:42.276110 4, 0xFFFF, sum = 0
6872 00:56:42.279471 5, 0xFFFF, sum = 0
6873 00:56:42.280089 6, 0xFFFF, sum = 0
6874 00:56:42.282640 7, 0xFFFF, sum = 0
6875 00:56:42.283099 8, 0xFFFF, sum = 0
6876 00:56:42.286003 9, 0xFFFF, sum = 0
6877 00:56:42.286595 10, 0xFFFF, sum = 0
6878 00:56:42.288914 11, 0xFFFF, sum = 0
6879 00:56:42.292217 12, 0xFFFF, sum = 0
6880 00:56:42.292655 13, 0x0, sum = 1
6881 00:56:42.293001 14, 0x0, sum = 2
6882 00:56:42.295651 15, 0x0, sum = 3
6883 00:56:42.296190 16, 0x0, sum = 4
6884 00:56:42.299235 best_step = 14
6885 00:56:42.299661
6886 00:56:42.299997 ==
6887 00:56:42.301986 Dram Type= 6, Freq= 0, CH_1, rank 0
6888 00:56:42.305804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 00:56:42.306376 ==
6890 00:56:42.308858 RX Vref Scan: 1
6891 00:56:42.309288
6892 00:56:42.309727 RX Vref 0 -> 0, step: 1
6893 00:56:42.312245
6894 00:56:42.312668 RX Delay -343 -> 252, step: 8
6895 00:56:42.313009
6896 00:56:42.315384 Set Vref, RX VrefLevel [Byte0]: 52
6897 00:56:42.318590 [Byte1]: 54
6898 00:56:42.324077
6899 00:56:42.324598 Final RX Vref Byte 0 = 52 to rank0
6900 00:56:42.327178 Final RX Vref Byte 1 = 54 to rank0
6901 00:56:42.330636 Final RX Vref Byte 0 = 52 to rank1
6902 00:56:42.333725 Final RX Vref Byte 1 = 54 to rank1==
6903 00:56:42.337070 Dram Type= 6, Freq= 0, CH_1, rank 0
6904 00:56:42.344022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 00:56:42.344559 ==
6906 00:56:42.344905 DQS Delay:
6907 00:56:42.346960 DQS0 = 44, DQS1 = 52
6908 00:56:42.347388 DQM Delay:
6909 00:56:42.347725 DQM0 = 8, DQM1 = 9
6910 00:56:42.350459 DQ Delay:
6911 00:56:42.353449 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6912 00:56:42.353876 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =0
6913 00:56:42.356894 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6914 00:56:42.360223 DQ12 =16, DQ13 =12, DQ14 =16, DQ15 =16
6915 00:56:42.360758
6916 00:56:42.363187
6917 00:56:42.370019 [DQSOSCAuto] RK0, (LSB)MR18= 0x9a70, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6918 00:56:42.373309 CH1 RK0: MR19=C0C, MR18=9A70
6919 00:56:42.379788 CH1_RK0: MR19=0xC0C, MR18=0x9A70, DQSOSC=390, MR23=63, INC=388, DEC=258
6920 00:56:42.380324 ==
6921 00:56:42.382987 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 00:56:42.386217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 00:56:42.386652 ==
6924 00:56:42.389768 [Gating] SW mode calibration
6925 00:56:42.396546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6926 00:56:42.402907 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6927 00:56:42.406013 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6928 00:56:42.409486 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6929 00:56:42.416060 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6930 00:56:42.419488 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6931 00:56:42.422508 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6932 00:56:42.429804 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6933 00:56:42.432814 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6934 00:56:42.435992 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6935 00:56:42.442759 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6936 00:56:42.443231 Total UI for P1: 0, mck2ui 16
6937 00:56:42.449149 best dqsien dly found for B0: ( 0, 14, 24)
6938 00:56:42.449727 Total UI for P1: 0, mck2ui 16
6939 00:56:42.455401 best dqsien dly found for B1: ( 0, 14, 24)
6940 00:56:42.459493 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6941 00:56:42.462627 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6942 00:56:42.463211
6943 00:56:42.465377 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6944 00:56:42.468998 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6945 00:56:42.472229 [Gating] SW calibration Done
6946 00:56:42.472697 ==
6947 00:56:42.475646 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 00:56:42.479061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 00:56:42.479602 ==
6950 00:56:42.482618 RX Vref Scan: 0
6951 00:56:42.483198
6952 00:56:42.483568 RX Vref 0 -> 0, step: 1
6953 00:56:42.483916
6954 00:56:42.485543 RX Delay -410 -> 252, step: 16
6955 00:56:42.492373 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6956 00:56:42.495535 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6957 00:56:42.498701 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6958 00:56:42.502030 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6959 00:56:42.509100 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6960 00:56:42.511926 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6961 00:56:42.515086 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6962 00:56:42.518257 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6963 00:56:42.524942 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6964 00:56:42.528260 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6965 00:56:42.531656 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6966 00:56:42.538261 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6967 00:56:42.541671 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6968 00:56:42.545058 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6969 00:56:42.548314 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6970 00:56:42.554399 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6971 00:56:42.554969 ==
6972 00:56:42.557963 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 00:56:42.561339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 00:56:42.561811 ==
6975 00:56:42.562225 DQS Delay:
6976 00:56:42.564558 DQS0 = 43, DQS1 = 59
6977 00:56:42.565142 DQM Delay:
6978 00:56:42.567709 DQM0 = 12, DQM1 = 21
6979 00:56:42.568175 DQ Delay:
6980 00:56:42.571167 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6981 00:56:42.574342 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6982 00:56:42.577810 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =8
6983 00:56:42.581228 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6984 00:56:42.581808
6985 00:56:42.582228
6986 00:56:42.582592 ==
6987 00:56:42.584543 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 00:56:42.587912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 00:56:42.588495 ==
6990 00:56:42.588871
6991 00:56:42.590786
6992 00:56:42.591251 TX Vref Scan disable
6993 00:56:42.594756 == TX Byte 0 ==
6994 00:56:42.597338 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6995 00:56:42.600989 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6996 00:56:42.604472 == TX Byte 1 ==
6997 00:56:42.607464 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6998 00:56:42.611215 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6999 00:56:42.611785 ==
7000 00:56:42.613611 Dram Type= 6, Freq= 0, CH_1, rank 1
7001 00:56:42.617324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7002 00:56:42.620969 ==
7003 00:56:42.621549
7004 00:56:42.621923
7005 00:56:42.622322 TX Vref Scan disable
7006 00:56:42.624395 == TX Byte 0 ==
7007 00:56:42.627398 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7008 00:56:42.630350 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7009 00:56:42.633738 == TX Byte 1 ==
7010 00:56:42.637083 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7011 00:56:42.640792 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7012 00:56:42.641416
7013 00:56:42.643511 [DATLAT]
7014 00:56:42.643974 Freq=400, CH1 RK1
7015 00:56:42.644348
7016 00:56:42.646748 DATLAT Default: 0xe
7017 00:56:42.647309 0, 0xFFFF, sum = 0
7018 00:56:42.650198 1, 0xFFFF, sum = 0
7019 00:56:42.650835 2, 0xFFFF, sum = 0
7020 00:56:42.653264 3, 0xFFFF, sum = 0
7021 00:56:42.653763 4, 0xFFFF, sum = 0
7022 00:56:42.656630 5, 0xFFFF, sum = 0
7023 00:56:42.657106 6, 0xFFFF, sum = 0
7024 00:56:42.659960 7, 0xFFFF, sum = 0
7025 00:56:42.660588 8, 0xFFFF, sum = 0
7026 00:56:42.662943 9, 0xFFFF, sum = 0
7027 00:56:42.663607 10, 0xFFFF, sum = 0
7028 00:56:42.666248 11, 0xFFFF, sum = 0
7029 00:56:42.669860 12, 0xFFFF, sum = 0
7030 00:56:42.670495 13, 0x0, sum = 1
7031 00:56:42.671120 14, 0x0, sum = 2
7032 00:56:42.672800 15, 0x0, sum = 3
7033 00:56:42.673273 16, 0x0, sum = 4
7034 00:56:42.676414 best_step = 14
7035 00:56:42.677086
7036 00:56:42.677745 ==
7037 00:56:42.679225 Dram Type= 6, Freq= 0, CH_1, rank 1
7038 00:56:42.682667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7039 00:56:42.683138 ==
7040 00:56:42.686133 RX Vref Scan: 0
7041 00:56:42.686609
7042 00:56:42.686944 RX Vref 0 -> 0, step: 1
7043 00:56:42.689250
7044 00:56:42.689951 RX Delay -359 -> 252, step: 8
7045 00:56:42.697971 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7046 00:56:42.701077 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7047 00:56:42.704916 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7048 00:56:42.710831 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7049 00:56:42.714820 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7050 00:56:42.717392 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7051 00:56:42.720817 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7052 00:56:42.727635 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7053 00:56:42.730781 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7054 00:56:42.734134 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7055 00:56:42.737553 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7056 00:56:42.743760 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7057 00:56:42.747214 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7058 00:56:42.750260 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7059 00:56:42.756912 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7060 00:56:42.760307 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7061 00:56:42.760886 ==
7062 00:56:42.763689 Dram Type= 6, Freq= 0, CH_1, rank 1
7063 00:56:42.767210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7064 00:56:42.767918 ==
7065 00:56:42.769989 DQS Delay:
7066 00:56:42.770526 DQS0 = 44, DQS1 = 56
7067 00:56:42.770872 DQM Delay:
7068 00:56:42.773506 DQM0 = 8, DQM1 = 11
7069 00:56:42.774263 DQ Delay:
7070 00:56:42.776895 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
7071 00:56:42.780553 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
7072 00:56:42.783523 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7073 00:56:42.786613 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7074 00:56:42.787080
7075 00:56:42.787438
7076 00:56:42.793566 [DQSOSCAuto] RK1, (LSB)MR18= 0x6757, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7077 00:56:42.797165 CH1 RK1: MR19=C0C, MR18=6757
7078 00:56:42.803365 CH1_RK1: MR19=0xC0C, MR18=0x6757, DQSOSC=396, MR23=63, INC=376, DEC=251
7079 00:56:42.806603 [RxdqsGatingPostProcess] freq 400
7080 00:56:42.812940 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7081 00:56:42.816778 best DQS0 dly(2T, 0.5T) = (0, 10)
7082 00:56:42.819745 best DQS1 dly(2T, 0.5T) = (0, 10)
7083 00:56:42.823255 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7084 00:56:42.826893 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7085 00:56:42.830233 best DQS0 dly(2T, 0.5T) = (0, 10)
7086 00:56:42.830749 best DQS1 dly(2T, 0.5T) = (0, 10)
7087 00:56:42.833059 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7088 00:56:42.837042 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7089 00:56:42.839690 Pre-setting of DQS Precalculation
7090 00:56:42.846553 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7091 00:56:42.853062 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7092 00:56:42.859379 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7093 00:56:42.859889
7094 00:56:42.860229
7095 00:56:42.862971 [Calibration Summary] 800 Mbps
7096 00:56:42.866020 CH 0, Rank 0
7097 00:56:42.866485 SW Impedance : PASS
7098 00:56:42.869659 DUTY Scan : NO K
7099 00:56:42.870228 ZQ Calibration : PASS
7100 00:56:42.872795 Jitter Meter : NO K
7101 00:56:42.876221 CBT Training : PASS
7102 00:56:42.876642 Write leveling : PASS
7103 00:56:42.879285 RX DQS gating : PASS
7104 00:56:42.882580 RX DQ/DQS(RDDQC) : PASS
7105 00:56:42.883102 TX DQ/DQS : PASS
7106 00:56:42.885655 RX DATLAT : PASS
7107 00:56:42.889256 RX DQ/DQS(Engine): PASS
7108 00:56:42.889778 TX OE : NO K
7109 00:56:42.892140 All Pass.
7110 00:56:42.892563
7111 00:56:42.892900 CH 0, Rank 1
7112 00:56:42.896128 SW Impedance : PASS
7113 00:56:42.896658 DUTY Scan : NO K
7114 00:56:42.899138 ZQ Calibration : PASS
7115 00:56:42.902255 Jitter Meter : NO K
7116 00:56:42.902784 CBT Training : PASS
7117 00:56:42.906237 Write leveling : NO K
7118 00:56:42.909150 RX DQS gating : PASS
7119 00:56:42.909573 RX DQ/DQS(RDDQC) : PASS
7120 00:56:42.912099 TX DQ/DQS : PASS
7121 00:56:42.915433 RX DATLAT : PASS
7122 00:56:42.915955 RX DQ/DQS(Engine): PASS
7123 00:56:42.918542 TX OE : NO K
7124 00:56:42.918970 All Pass.
7125 00:56:42.919308
7126 00:56:42.921876 CH 1, Rank 0
7127 00:56:42.922334 SW Impedance : PASS
7128 00:56:42.925022 DUTY Scan : NO K
7129 00:56:42.929202 ZQ Calibration : PASS
7130 00:56:42.929726 Jitter Meter : NO K
7131 00:56:42.931905 CBT Training : PASS
7132 00:56:42.934967 Write leveling : PASS
7133 00:56:42.935394 RX DQS gating : PASS
7134 00:56:42.938633 RX DQ/DQS(RDDQC) : PASS
7135 00:56:42.941858 TX DQ/DQS : PASS
7136 00:56:42.942446 RX DATLAT : PASS
7137 00:56:42.945748 RX DQ/DQS(Engine): PASS
7138 00:56:42.946317 TX OE : NO K
7139 00:56:42.948745 All Pass.
7140 00:56:42.949260
7141 00:56:42.949598 CH 1, Rank 1
7142 00:56:42.952432 SW Impedance : PASS
7143 00:56:42.952950 DUTY Scan : NO K
7144 00:56:42.955317 ZQ Calibration : PASS
7145 00:56:42.958676 Jitter Meter : NO K
7146 00:56:42.959317 CBT Training : PASS
7147 00:56:42.961816 Write leveling : NO K
7148 00:56:42.965249 RX DQS gating : PASS
7149 00:56:42.965927 RX DQ/DQS(RDDQC) : PASS
7150 00:56:42.968271 TX DQ/DQS : PASS
7151 00:56:42.971368 RX DATLAT : PASS
7152 00:56:42.971792 RX DQ/DQS(Engine): PASS
7153 00:56:42.974974 TX OE : NO K
7154 00:56:42.975499 All Pass.
7155 00:56:42.975840
7156 00:56:42.978058 DramC Write-DBI off
7157 00:56:42.981938 PER_BANK_REFRESH: Hybrid Mode
7158 00:56:42.982518 TX_TRACKING: ON
7159 00:56:42.991383 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7160 00:56:42.994659 [FAST_K] Save calibration result to emmc
7161 00:56:42.998227 dramc_set_vcore_voltage set vcore to 725000
7162 00:56:43.001168 Read voltage for 1600, 0
7163 00:56:43.001592 Vio18 = 0
7164 00:56:43.001933 Vcore = 725000
7165 00:56:43.004587 Vdram = 0
7166 00:56:43.005007 Vddq = 0
7167 00:56:43.005339 Vmddr = 0
7168 00:56:43.011487 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7169 00:56:43.014504 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7170 00:56:43.017511 MEM_TYPE=3, freq_sel=13
7171 00:56:43.021398 sv_algorithm_assistance_LP4_3733
7172 00:56:43.024586 ============ PULL DRAM RESETB DOWN ============
7173 00:56:43.030847 ========== PULL DRAM RESETB DOWN end =========
7174 00:56:43.034004 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 00:56:43.037362 ===================================
7176 00:56:43.040447 LPDDR4 DRAM CONFIGURATION
7177 00:56:43.043895 ===================================
7178 00:56:43.044365 EX_ROW_EN[0] = 0x0
7179 00:56:43.047168 EX_ROW_EN[1] = 0x0
7180 00:56:43.047654 LP4Y_EN = 0x0
7181 00:56:43.050708 WORK_FSP = 0x1
7182 00:56:43.051177 WL = 0x5
7183 00:56:43.053813 RL = 0x5
7184 00:56:43.057436 BL = 0x2
7185 00:56:43.057995 RPST = 0x0
7186 00:56:43.060775 RD_PRE = 0x0
7187 00:56:43.061360 WR_PRE = 0x1
7188 00:56:43.063935 WR_PST = 0x1
7189 00:56:43.064405 DBI_WR = 0x0
7190 00:56:43.066916 DBI_RD = 0x0
7191 00:56:43.067383 OTF = 0x1
7192 00:56:43.070397 ===================================
7193 00:56:43.073381 ===================================
7194 00:56:43.077166 ANA top config
7195 00:56:43.080441 ===================================
7196 00:56:43.080910 DLL_ASYNC_EN = 0
7197 00:56:43.083526 ALL_SLAVE_EN = 0
7198 00:56:43.086697 NEW_RANK_MODE = 1
7199 00:56:43.090136 DLL_IDLE_MODE = 1
7200 00:56:43.093850 LP45_APHY_COMB_EN = 1
7201 00:56:43.094447 TX_ODT_DIS = 0
7202 00:56:43.096986 NEW_8X_MODE = 1
7203 00:56:43.100151 ===================================
7204 00:56:43.102994 ===================================
7205 00:56:43.106276 data_rate = 3200
7206 00:56:43.109732 CKR = 1
7207 00:56:43.113504 DQ_P2S_RATIO = 8
7208 00:56:43.116627 ===================================
7209 00:56:43.119733 CA_P2S_RATIO = 8
7210 00:56:43.120157 DQ_CA_OPEN = 0
7211 00:56:43.123110 DQ_SEMI_OPEN = 0
7212 00:56:43.126346 CA_SEMI_OPEN = 0
7213 00:56:43.129542 CA_FULL_RATE = 0
7214 00:56:43.133275 DQ_CKDIV4_EN = 0
7215 00:56:43.136065 CA_CKDIV4_EN = 0
7216 00:56:43.136490 CA_PREDIV_EN = 0
7217 00:56:43.140131 PH8_DLY = 12
7218 00:56:43.142841 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7219 00:56:43.146394 DQ_AAMCK_DIV = 4
7220 00:56:43.149564 CA_AAMCK_DIV = 4
7221 00:56:43.152901 CA_ADMCK_DIV = 4
7222 00:56:43.153453 DQ_TRACK_CA_EN = 0
7223 00:56:43.156455 CA_PICK = 1600
7224 00:56:43.159652 CA_MCKIO = 1600
7225 00:56:43.163296 MCKIO_SEMI = 0
7226 00:56:43.165935 PLL_FREQ = 3068
7227 00:56:43.169586 DQ_UI_PI_RATIO = 32
7228 00:56:43.172956 CA_UI_PI_RATIO = 0
7229 00:56:43.175907 ===================================
7230 00:56:43.179116 ===================================
7231 00:56:43.179540 memory_type:LPDDR4
7232 00:56:43.182837 GP_NUM : 10
7233 00:56:43.185773 SRAM_EN : 1
7234 00:56:43.186221 MD32_EN : 0
7235 00:56:43.189270 ===================================
7236 00:56:43.192729 [ANA_INIT] >>>>>>>>>>>>>>
7237 00:56:43.195634 <<<<<< [CONFIGURE PHASE]: ANA_TX
7238 00:56:43.198911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7239 00:56:43.202225 ===================================
7240 00:56:43.205517 data_rate = 3200,PCW = 0X7600
7241 00:56:43.208808 ===================================
7242 00:56:43.212084 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7243 00:56:43.215706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7244 00:56:43.221736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7245 00:56:43.225357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7246 00:56:43.231853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7247 00:56:43.234922 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7248 00:56:43.235358 [ANA_INIT] flow start
7249 00:56:43.238063 [ANA_INIT] PLL >>>>>>>>
7250 00:56:43.241949 [ANA_INIT] PLL <<<<<<<<
7251 00:56:43.242592 [ANA_INIT] MIDPI >>>>>>>>
7252 00:56:43.244964 [ANA_INIT] MIDPI <<<<<<<<
7253 00:56:43.248281 [ANA_INIT] DLL >>>>>>>>
7254 00:56:43.248886 [ANA_INIT] DLL <<<<<<<<
7255 00:56:43.251739 [ANA_INIT] flow end
7256 00:56:43.254706 ============ LP4 DIFF to SE enter ============
7257 00:56:43.261156 ============ LP4 DIFF to SE exit ============
7258 00:56:43.261795 [ANA_INIT] <<<<<<<<<<<<<
7259 00:56:43.264807 [Flow] Enable top DCM control >>>>>
7260 00:56:43.267896 [Flow] Enable top DCM control <<<<<
7261 00:56:43.271068 Enable DLL master slave shuffle
7262 00:56:43.277886 ==============================================================
7263 00:56:43.278501 Gating Mode config
7264 00:56:43.284386 ==============================================================
7265 00:56:43.287486 Config description:
7266 00:56:43.297079 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7267 00:56:43.303789 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7268 00:56:43.307108 SELPH_MODE 0: By rank 1: By Phase
7269 00:56:43.313639 ==============================================================
7270 00:56:43.317162 GAT_TRACK_EN = 1
7271 00:56:43.320250 RX_GATING_MODE = 2
7272 00:56:43.323716 RX_GATING_TRACK_MODE = 2
7273 00:56:43.324276 SELPH_MODE = 1
7274 00:56:43.327048 PICG_EARLY_EN = 1
7275 00:56:43.330222 VALID_LAT_VALUE = 1
7276 00:56:43.336807 ==============================================================
7277 00:56:43.340330 Enter into Gating configuration >>>>
7278 00:56:43.343592 Exit from Gating configuration <<<<
7279 00:56:43.346709 Enter into DVFS_PRE_config >>>>>
7280 00:56:43.356999 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7281 00:56:43.359848 Exit from DVFS_PRE_config <<<<<
7282 00:56:43.363126 Enter into PICG configuration >>>>
7283 00:56:43.366564 Exit from PICG configuration <<<<
7284 00:56:43.369729 [RX_INPUT] configuration >>>>>
7285 00:56:43.373433 [RX_INPUT] configuration <<<<<
7286 00:56:43.376295 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7287 00:56:43.382790 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7288 00:56:43.389703 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7289 00:56:43.396286 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7290 00:56:43.402789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7291 00:56:43.409177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7292 00:56:43.412923 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7293 00:56:43.415944 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7294 00:56:43.419095 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7295 00:56:43.426115 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7296 00:56:43.429174 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7297 00:56:43.432448 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7298 00:56:43.435721 ===================================
7299 00:56:43.439279 LPDDR4 DRAM CONFIGURATION
7300 00:56:43.442588 ===================================
7301 00:56:43.443208 EX_ROW_EN[0] = 0x0
7302 00:56:43.445538 EX_ROW_EN[1] = 0x0
7303 00:56:43.446004 LP4Y_EN = 0x0
7304 00:56:43.448920 WORK_FSP = 0x1
7305 00:56:43.452515 WL = 0x5
7306 00:56:43.453122 RL = 0x5
7307 00:56:43.455510 BL = 0x2
7308 00:56:43.455978 RPST = 0x0
7309 00:56:43.458616 RD_PRE = 0x0
7310 00:56:43.459084 WR_PRE = 0x1
7311 00:56:43.461764 WR_PST = 0x1
7312 00:56:43.462270 DBI_WR = 0x0
7313 00:56:43.465416 DBI_RD = 0x0
7314 00:56:43.465975 OTF = 0x1
7315 00:56:43.468360 ===================================
7316 00:56:43.471710 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7317 00:56:43.478883 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7318 00:56:43.481835 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7319 00:56:43.485141 ===================================
7320 00:56:43.488561 LPDDR4 DRAM CONFIGURATION
7321 00:56:43.491493 ===================================
7322 00:56:43.491966 EX_ROW_EN[0] = 0x10
7323 00:56:43.495079 EX_ROW_EN[1] = 0x0
7324 00:56:43.498308 LP4Y_EN = 0x0
7325 00:56:43.498872 WORK_FSP = 0x1
7326 00:56:43.501802 WL = 0x5
7327 00:56:43.502393 RL = 0x5
7328 00:56:43.504791 BL = 0x2
7329 00:56:43.505257 RPST = 0x0
7330 00:56:43.508293 RD_PRE = 0x0
7331 00:56:43.508857 WR_PRE = 0x1
7332 00:56:43.511078 WR_PST = 0x1
7333 00:56:43.511611 DBI_WR = 0x0
7334 00:56:43.514840 DBI_RD = 0x0
7335 00:56:43.515404 OTF = 0x1
7336 00:56:43.517808 ===================================
7337 00:56:43.524258 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7338 00:56:43.524842 ==
7339 00:56:43.527444 Dram Type= 6, Freq= 0, CH_0, rank 0
7340 00:56:43.534341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7341 00:56:43.535042 ==
7342 00:56:43.535441 [Duty_Offset_Calibration]
7343 00:56:43.537749 B0:1 B1:-1 CA:0
7344 00:56:43.538249
7345 00:56:43.540999 [DutyScan_Calibration_Flow] k_type=0
7346 00:56:43.549946
7347 00:56:43.550458 ==CLK 0==
7348 00:56:43.553458 Final CLK duty delay cell = 0
7349 00:56:43.556879 [0] MAX Duty = 5124%(X100), DQS PI = 22
7350 00:56:43.560287 [0] MIN Duty = 4907%(X100), DQS PI = 4
7351 00:56:43.560855 [0] AVG Duty = 5015%(X100)
7352 00:56:43.563332
7353 00:56:43.566478 CH0 CLK Duty spec in!! Max-Min= 217%
7354 00:56:43.569906 [DutyScan_Calibration_Flow] ====Done====
7355 00:56:43.570412
7356 00:56:43.573082 [DutyScan_Calibration_Flow] k_type=1
7357 00:56:43.589447
7358 00:56:43.590231 ==DQS 0 ==
7359 00:56:43.592768 Final DQS duty delay cell = -4
7360 00:56:43.595970 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7361 00:56:43.599541 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7362 00:56:43.602281 [-4] AVG Duty = 4906%(X100)
7363 00:56:43.602747
7364 00:56:43.603114 ==DQS 1 ==
7365 00:56:43.605739 Final DQS duty delay cell = 0
7366 00:56:43.608850 [0] MAX Duty = 5156%(X100), DQS PI = 2
7367 00:56:43.612443 [0] MIN Duty = 5000%(X100), DQS PI = 18
7368 00:56:43.615891 [0] AVG Duty = 5078%(X100)
7369 00:56:43.616309
7370 00:56:43.618794 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7371 00:56:43.619239
7372 00:56:43.622269 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7373 00:56:43.625812 [DutyScan_Calibration_Flow] ====Done====
7374 00:56:43.626260
7375 00:56:43.628730 [DutyScan_Calibration_Flow] k_type=3
7376 00:56:43.646723
7377 00:56:43.647234 ==DQM 0 ==
7378 00:56:43.650030 Final DQM duty delay cell = 0
7379 00:56:43.653363 [0] MAX Duty = 5124%(X100), DQS PI = 20
7380 00:56:43.656337 [0] MIN Duty = 4907%(X100), DQS PI = 8
7381 00:56:43.660157 [0] AVG Duty = 5015%(X100)
7382 00:56:43.660580
7383 00:56:43.660908 ==DQM 1 ==
7384 00:56:43.663032 Final DQM duty delay cell = 0
7385 00:56:43.666976 [0] MAX Duty = 5000%(X100), DQS PI = 10
7386 00:56:43.669441 [0] MIN Duty = 4782%(X100), DQS PI = 20
7387 00:56:43.672782 [0] AVG Duty = 4891%(X100)
7388 00:56:43.673202
7389 00:56:43.676491 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7390 00:56:43.676912
7391 00:56:43.679623 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7392 00:56:43.682801 [DutyScan_Calibration_Flow] ====Done====
7393 00:56:43.683221
7394 00:56:43.685918 [DutyScan_Calibration_Flow] k_type=2
7395 00:56:43.702877
7396 00:56:43.703537 ==DQ 0 ==
7397 00:56:43.706755 Final DQ duty delay cell = -4
7398 00:56:43.709992 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7399 00:56:43.713155 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7400 00:56:43.716521 [-4] AVG Duty = 4953%(X100)
7401 00:56:43.717081
7402 00:56:43.717446 ==DQ 1 ==
7403 00:56:43.719590 Final DQ duty delay cell = 0
7404 00:56:43.723376 [0] MAX Duty = 5125%(X100), DQS PI = 2
7405 00:56:43.726185 [0] MIN Duty = 5000%(X100), DQS PI = 34
7406 00:56:43.729468 [0] AVG Duty = 5062%(X100)
7407 00:56:43.729931
7408 00:56:43.732692 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7409 00:56:43.733157
7410 00:56:43.735806 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7411 00:56:43.738878 [DutyScan_Calibration_Flow] ====Done====
7412 00:56:43.739343 ==
7413 00:56:43.742782 Dram Type= 6, Freq= 0, CH_1, rank 0
7414 00:56:43.745823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7415 00:56:43.746582 ==
7416 00:56:43.748908 [Duty_Offset_Calibration]
7417 00:56:43.749433 B0:-1 B1:1 CA:2
7418 00:56:43.752396
7419 00:56:43.755214 [DutyScan_Calibration_Flow] k_type=0
7420 00:56:43.763671
7421 00:56:43.764156 ==CLK 0==
7422 00:56:43.766753 Final CLK duty delay cell = 0
7423 00:56:43.770402 [0] MAX Duty = 5187%(X100), DQS PI = 22
7424 00:56:43.773241 [0] MIN Duty = 4969%(X100), DQS PI = 0
7425 00:56:43.773707 [0] AVG Duty = 5078%(X100)
7426 00:56:43.776592
7427 00:56:43.780356 CH1 CLK Duty spec in!! Max-Min= 218%
7428 00:56:43.783550 [DutyScan_Calibration_Flow] ====Done====
7429 00:56:43.784017
7430 00:56:43.786518 [DutyScan_Calibration_Flow] k_type=1
7431 00:56:43.803173
7432 00:56:43.803733 ==DQS 0 ==
7433 00:56:43.807021 Final DQS duty delay cell = 0
7434 00:56:43.810088 [0] MAX Duty = 5124%(X100), DQS PI = 18
7435 00:56:43.813436 [0] MIN Duty = 4907%(X100), DQS PI = 8
7436 00:56:43.816584 [0] AVG Duty = 5015%(X100)
7437 00:56:43.817144
7438 00:56:43.817576 ==DQS 1 ==
7439 00:56:43.820007 Final DQS duty delay cell = 0
7440 00:56:43.822764 [0] MAX Duty = 5093%(X100), DQS PI = 28
7441 00:56:43.826219 [0] MIN Duty = 4969%(X100), DQS PI = 54
7442 00:56:43.829253 [0] AVG Duty = 5031%(X100)
7443 00:56:43.829723
7444 00:56:43.832828 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7445 00:56:43.833299
7446 00:56:43.836015 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7447 00:56:43.839440 [DutyScan_Calibration_Flow] ====Done====
7448 00:56:43.839908
7449 00:56:43.842463 [DutyScan_Calibration_Flow] k_type=3
7450 00:56:43.860072
7451 00:56:43.860776 ==DQM 0 ==
7452 00:56:43.863482 Final DQM duty delay cell = 0
7453 00:56:43.866734 [0] MAX Duty = 5218%(X100), DQS PI = 18
7454 00:56:43.870251 [0] MIN Duty = 5031%(X100), DQS PI = 6
7455 00:56:43.873285 [0] AVG Duty = 5124%(X100)
7456 00:56:43.873754
7457 00:56:43.874122 ==DQM 1 ==
7458 00:56:43.876449 Final DQM duty delay cell = 0
7459 00:56:43.879672 [0] MAX Duty = 5125%(X100), DQS PI = 2
7460 00:56:43.882960 [0] MIN Duty = 4938%(X100), DQS PI = 36
7461 00:56:43.886617 [0] AVG Duty = 5031%(X100)
7462 00:56:43.887099
7463 00:56:43.889723 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7464 00:56:43.890152
7465 00:56:43.893275 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7466 00:56:43.896100 [DutyScan_Calibration_Flow] ====Done====
7467 00:56:43.896529
7468 00:56:43.899526 [DutyScan_Calibration_Flow] k_type=2
7469 00:56:43.916781
7470 00:56:43.917351 ==DQ 0 ==
7471 00:56:43.920328 Final DQ duty delay cell = 0
7472 00:56:43.923095 [0] MAX Duty = 5156%(X100), DQS PI = 30
7473 00:56:43.927045 [0] MIN Duty = 4906%(X100), DQS PI = 8
7474 00:56:43.927472 [0] AVG Duty = 5031%(X100)
7475 00:56:43.929959
7476 00:56:43.930423 ==DQ 1 ==
7477 00:56:43.933194 Final DQ duty delay cell = 0
7478 00:56:43.936436 [0] MAX Duty = 5156%(X100), DQS PI = 8
7479 00:56:43.939915 [0] MIN Duty = 4938%(X100), DQS PI = 58
7480 00:56:43.940502 [0] AVG Duty = 5047%(X100)
7481 00:56:43.940905
7482 00:56:43.943389 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7483 00:56:43.946812
7484 00:56:43.949852 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7485 00:56:43.953548 [DutyScan_Calibration_Flow] ====Done====
7486 00:56:43.956644 nWR fixed to 30
7487 00:56:43.957076 [ModeRegInit_LP4] CH0 RK0
7488 00:56:43.959955 [ModeRegInit_LP4] CH0 RK1
7489 00:56:43.962976 [ModeRegInit_LP4] CH1 RK0
7490 00:56:43.966718 [ModeRegInit_LP4] CH1 RK1
7491 00:56:43.967145 match AC timing 5
7492 00:56:43.969644 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7493 00:56:43.976588 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7494 00:56:43.979466 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7495 00:56:43.986138 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7496 00:56:43.989434 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7497 00:56:43.989863 [MiockJmeterHQA]
7498 00:56:43.990241
7499 00:56:43.993248 [DramcMiockJmeter] u1RxGatingPI = 0
7500 00:56:43.996053 0 : 4257, 4029
7501 00:56:43.996490 4 : 4252, 4027
7502 00:56:43.999518 8 : 4253, 4027
7503 00:56:44.000085 12 : 4255, 4030
7504 00:56:44.000445 16 : 4252, 4027
7505 00:56:44.002572 20 : 4363, 4138
7506 00:56:44.003009 24 : 4250, 4027
7507 00:56:44.005975 28 : 4252, 4027
7508 00:56:44.006457 32 : 4253, 4027
7509 00:56:44.009630 36 : 4257, 4029
7510 00:56:44.010152 40 : 4252, 4027
7511 00:56:44.012724 44 : 4254, 4029
7512 00:56:44.013154 48 : 4250, 4026
7513 00:56:44.013500 52 : 4258, 4030
7514 00:56:44.015859 56 : 4363, 4140
7515 00:56:44.016294 60 : 4250, 4027
7516 00:56:44.019415 64 : 4252, 4029
7517 00:56:44.019864 68 : 4250, 4027
7518 00:56:44.022477 72 : 4363, 4138
7519 00:56:44.022911 76 : 4249, 4027
7520 00:56:44.026238 80 : 4250, 4026
7521 00:56:44.026764 84 : 4252, 4029
7522 00:56:44.027109 88 : 4250, 4026
7523 00:56:44.029414 92 : 4250, 405
7524 00:56:44.029848 96 : 4362, 0
7525 00:56:44.032309 100 : 4363, 0
7526 00:56:44.032758 104 : 4249, 0
7527 00:56:44.033099 108 : 4250, 0
7528 00:56:44.036071 112 : 4250, 0
7529 00:56:44.036628 116 : 4252, 0
7530 00:56:44.038678 120 : 4250, 0
7531 00:56:44.039108 124 : 4250, 0
7532 00:56:44.039449 128 : 4250, 0
7533 00:56:44.041957 132 : 4363, 0
7534 00:56:44.042427 136 : 4250, 0
7535 00:56:44.045895 140 : 4360, 0
7536 00:56:44.046566 144 : 4255, 0
7537 00:56:44.046955 148 : 4250, 0
7538 00:56:44.048653 152 : 4250, 0
7539 00:56:44.049154 156 : 4254, 0
7540 00:56:44.052645 160 : 4250, 0
7541 00:56:44.053391 164 : 4250, 0
7542 00:56:44.053789 168 : 4252, 0
7543 00:56:44.055180 172 : 4250, 0
7544 00:56:44.055660 176 : 4250, 0
7545 00:56:44.056043 180 : 4250, 0
7546 00:56:44.059007 184 : 4250, 0
7547 00:56:44.059499 188 : 4361, 0
7548 00:56:44.062325 192 : 4363, 0
7549 00:56:44.062762 196 : 4250, 0
7550 00:56:44.063132 200 : 4250, 0
7551 00:56:44.065463 204 : 4255, 0
7552 00:56:44.066041 208 : 4250, 0
7553 00:56:44.068673 212 : 4250, 0
7554 00:56:44.069247 216 : 4255, 0
7555 00:56:44.069628 220 : 4255, 0
7556 00:56:44.071920 224 : 4250, 286
7557 00:56:44.072423 228 : 4250, 3324
7558 00:56:44.075029 232 : 4249, 4027
7559 00:56:44.075506 236 : 4255, 4029
7560 00:56:44.078291 240 : 4361, 4138
7561 00:56:44.078771 244 : 4250, 4027
7562 00:56:44.082095 248 : 4250, 4027
7563 00:56:44.082710 252 : 4250, 4027
7564 00:56:44.085285 256 : 4250, 4027
7565 00:56:44.085886 260 : 4363, 4138
7566 00:56:44.088409 264 : 4250, 4027
7567 00:56:44.088979 268 : 4363, 4137
7568 00:56:44.091352 272 : 4250, 4026
7569 00:56:44.091835 276 : 4250, 4027
7570 00:56:44.092216 280 : 4249, 4027
7571 00:56:44.094864 284 : 4250, 4027
7572 00:56:44.095343 288 : 4250, 4026
7573 00:56:44.098027 292 : 4361, 4138
7574 00:56:44.098669 296 : 4250, 4027
7575 00:56:44.101527 300 : 4250, 4027
7576 00:56:44.102206 304 : 4250, 4027
7577 00:56:44.104466 308 : 4250, 4026
7578 00:56:44.104946 312 : 4360, 4138
7579 00:56:44.108304 316 : 4360, 4138
7580 00:56:44.108781 320 : 4363, 4140
7581 00:56:44.111707 324 : 4250, 4027
7582 00:56:44.112279 328 : 4250, 4027
7583 00:56:44.114887 332 : 4250, 4027
7584 00:56:44.115454 336 : 4249, 3728
7585 00:56:44.117846 340 : 4250, 2219
7586 00:56:44.118351 344 : 4361, 8
7587 00:56:44.118736
7588 00:56:44.121373 MIOCK jitter meter ch=0
7589 00:56:44.121845
7590 00:56:44.124623 1T = (344-92) = 252 dly cells
7591 00:56:44.128058 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7592 00:56:44.128840 ==
7593 00:56:44.131087 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 00:56:44.137999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 00:56:44.138624 ==
7596 00:56:44.140846 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7597 00:56:44.147790 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7598 00:56:44.151189 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7599 00:56:44.157357 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7600 00:56:44.164947 [CA 0] Center 43 (13~74) winsize 62
7601 00:56:44.168294 [CA 1] Center 42 (12~73) winsize 62
7602 00:56:44.171941 [CA 2] Center 38 (9~68) winsize 60
7603 00:56:44.175453 [CA 3] Center 38 (9~68) winsize 60
7604 00:56:44.178874 [CA 4] Center 36 (7~66) winsize 60
7605 00:56:44.181757 [CA 5] Center 35 (6~65) winsize 60
7606 00:56:44.182364
7607 00:56:44.185329 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7608 00:56:44.185909
7609 00:56:44.191233 [CATrainingPosCal] consider 1 rank data
7610 00:56:44.191783 u2DelayCellTimex100 = 258/100 ps
7611 00:56:44.198199 CA0 delay=43 (13~74),Diff = 8 PI (30 cell)
7612 00:56:44.201653 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7613 00:56:44.204714 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7614 00:56:44.207706 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7615 00:56:44.211369 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7616 00:56:44.214843 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7617 00:56:44.215313
7618 00:56:44.217900 CA PerBit enable=1, Macro0, CA PI delay=35
7619 00:56:44.218496
7620 00:56:44.220858 [CBTSetCACLKResult] CA Dly = 35
7621 00:56:44.223879 CS Dly: 11 (0~42)
7622 00:56:44.227453 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7623 00:56:44.230796 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7624 00:56:44.233973 ==
7625 00:56:44.234476 Dram Type= 6, Freq= 0, CH_0, rank 1
7626 00:56:44.240900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 00:56:44.241631 ==
7628 00:56:44.243890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7629 00:56:44.250370 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7630 00:56:44.254105 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7631 00:56:44.260489 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7632 00:56:44.268468 [CA 0] Center 43 (13~73) winsize 61
7633 00:56:44.271706 [CA 1] Center 43 (13~73) winsize 61
7634 00:56:44.275159 [CA 2] Center 38 (9~67) winsize 59
7635 00:56:44.278594 [CA 3] Center 38 (9~67) winsize 59
7636 00:56:44.281607 [CA 4] Center 36 (7~66) winsize 60
7637 00:56:44.285044 [CA 5] Center 36 (6~66) winsize 61
7638 00:56:44.285740
7639 00:56:44.288235 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7640 00:56:44.288702
7641 00:56:44.295101 [CATrainingPosCal] consider 2 rank data
7642 00:56:44.295666 u2DelayCellTimex100 = 258/100 ps
7643 00:56:44.301902 CA0 delay=43 (13~73),Diff = 8 PI (30 cell)
7644 00:56:44.305114 CA1 delay=43 (13~73),Diff = 8 PI (30 cell)
7645 00:56:44.308427 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7646 00:56:44.311475 CA3 delay=38 (9~67),Diff = 3 PI (11 cell)
7647 00:56:44.314871 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7648 00:56:44.318241 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7649 00:56:44.318807
7650 00:56:44.321053 CA PerBit enable=1, Macro0, CA PI delay=35
7651 00:56:44.321522
7652 00:56:44.324257 [CBTSetCACLKResult] CA Dly = 35
7653 00:56:44.328126 CS Dly: 11 (0~43)
7654 00:56:44.330922 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7655 00:56:44.334512 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7656 00:56:44.334979
7657 00:56:44.338225 ----->DramcWriteLeveling(PI) begin...
7658 00:56:44.340794 ==
7659 00:56:44.341264 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 00:56:44.348262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 00:56:44.348934 ==
7662 00:56:44.350767 Write leveling (Byte 0): 36 => 36
7663 00:56:44.354284 Write leveling (Byte 1): 27 => 27
7664 00:56:44.357331 DramcWriteLeveling(PI) end<-----
7665 00:56:44.357805
7666 00:56:44.358211 ==
7667 00:56:44.361061 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 00:56:44.364099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 00:56:44.364571 ==
7670 00:56:44.367212 [Gating] SW mode calibration
7671 00:56:44.373706 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7672 00:56:44.380539 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7673 00:56:44.384289 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 00:56:44.387613 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7675 00:56:44.393963 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7676 00:56:44.397025 1 4 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
7677 00:56:44.400681 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7678 00:56:44.406839 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7679 00:56:44.410312 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7680 00:56:44.414212 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7681 00:56:44.420690 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7682 00:56:44.423880 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7683 00:56:44.426986 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7684 00:56:44.433466 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
7685 00:56:44.437212 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7686 00:56:44.439868 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7687 00:56:44.446867 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7688 00:56:44.449657 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7689 00:56:44.453066 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7690 00:56:44.459758 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7691 00:56:44.462833 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7692 00:56:44.466051 1 6 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7693 00:56:44.472976 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7694 00:56:44.476009 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7695 00:56:44.479770 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7696 00:56:44.486355 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7697 00:56:44.489488 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7698 00:56:44.492827 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7699 00:56:44.498996 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7700 00:56:44.502465 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7701 00:56:44.505725 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7702 00:56:44.512510 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7703 00:56:44.515663 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7704 00:56:44.519526 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 00:56:44.526077 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 00:56:44.528631 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 00:56:44.532571 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 00:56:44.538919 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 00:56:44.542230 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 00:56:44.545656 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 00:56:44.551704 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7712 00:56:44.555105 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7713 00:56:44.558490 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7714 00:56:44.565438 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7715 00:56:44.568430 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7716 00:56:44.571634 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7717 00:56:44.578236 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7718 00:56:44.578705 Total UI for P1: 0, mck2ui 16
7719 00:56:44.584942 best dqsien dly found for B0: ( 1, 9, 12)
7720 00:56:44.588419 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7721 00:56:44.591779 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7722 00:56:44.598447 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7723 00:56:44.599013 Total UI for P1: 0, mck2ui 16
7724 00:56:44.601630 best dqsien dly found for B1: ( 1, 9, 22)
7725 00:56:44.608113 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7726 00:56:44.611309 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7727 00:56:44.611873
7728 00:56:44.614640 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7729 00:56:44.617708 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7730 00:56:44.621134 [Gating] SW calibration Done
7731 00:56:44.621600 ==
7732 00:56:44.624514 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 00:56:44.627776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 00:56:44.628336 ==
7735 00:56:44.630872 RX Vref Scan: 0
7736 00:56:44.631337
7737 00:56:44.631705 RX Vref 0 -> 0, step: 1
7738 00:56:44.632135
7739 00:56:44.634573 RX Delay 0 -> 252, step: 8
7740 00:56:44.637489 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7741 00:56:44.644297 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7742 00:56:44.647350 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7743 00:56:44.650894 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7744 00:56:44.653870 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7745 00:56:44.657429 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7746 00:56:44.664183 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7747 00:56:44.667209 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7748 00:56:44.670832 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7749 00:56:44.673698 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7750 00:56:44.677074 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7751 00:56:44.683743 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7752 00:56:44.687020 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7753 00:56:44.690131 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7754 00:56:44.694093 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7755 00:56:44.700676 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7756 00:56:44.701239 ==
7757 00:56:44.703736 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 00:56:44.707088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 00:56:44.707656 ==
7760 00:56:44.708032 DQS Delay:
7761 00:56:44.710507 DQS0 = 0, DQS1 = 0
7762 00:56:44.710977 DQM Delay:
7763 00:56:44.713952 DQM0 = 133, DQM1 = 126
7764 00:56:44.714586 DQ Delay:
7765 00:56:44.716744 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =131
7766 00:56:44.720022 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7767 00:56:44.723216 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7768 00:56:44.726754 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7769 00:56:44.730271
7770 00:56:44.730895
7771 00:56:44.731274 ==
7772 00:56:44.732989 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 00:56:44.736333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 00:56:44.736814 ==
7775 00:56:44.737189
7776 00:56:44.737531
7777 00:56:44.739974 TX Vref Scan disable
7778 00:56:44.740576 == TX Byte 0 ==
7779 00:56:44.746360 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7780 00:56:44.749032 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7781 00:56:44.749505 == TX Byte 1 ==
7782 00:56:44.755973 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7783 00:56:44.759350 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7784 00:56:44.759829 ==
7785 00:56:44.762468 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 00:56:44.765858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 00:56:44.766375 ==
7788 00:56:44.780530
7789 00:56:44.783837 TX Vref early break, caculate TX vref
7790 00:56:44.787129 TX Vref=16, minBit 4, minWin=22, winSum=371
7791 00:56:44.790498 TX Vref=18, minBit 4, minWin=22, winSum=381
7792 00:56:44.793702 TX Vref=20, minBit 1, minWin=23, winSum=392
7793 00:56:44.797019 TX Vref=22, minBit 3, minWin=24, winSum=402
7794 00:56:44.799980 TX Vref=24, minBit 3, minWin=24, winSum=403
7795 00:56:44.806711 TX Vref=26, minBit 0, minWin=24, winSum=414
7796 00:56:44.810777 TX Vref=28, minBit 0, minWin=25, winSum=416
7797 00:56:44.813127 TX Vref=30, minBit 0, minWin=24, winSum=408
7798 00:56:44.817201 TX Vref=32, minBit 7, minWin=23, winSum=398
7799 00:56:44.820191 TX Vref=34, minBit 7, minWin=23, winSum=387
7800 00:56:44.826633 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 28
7801 00:56:44.827070
7802 00:56:44.830105 Final TX Range 0 Vref 28
7803 00:56:44.830722
7804 00:56:44.831184 ==
7805 00:56:44.833429 Dram Type= 6, Freq= 0, CH_0, rank 0
7806 00:56:44.836605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7807 00:56:44.837084 ==
7808 00:56:44.837459
7809 00:56:44.837800
7810 00:56:44.839866 TX Vref Scan disable
7811 00:56:44.846330 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7812 00:56:44.846807 == TX Byte 0 ==
7813 00:56:44.849851 u2DelayCellOfst[0]=15 cells (4 PI)
7814 00:56:44.853440 u2DelayCellOfst[1]=18 cells (5 PI)
7815 00:56:44.856421 u2DelayCellOfst[2]=15 cells (4 PI)
7816 00:56:44.859915 u2DelayCellOfst[3]=15 cells (4 PI)
7817 00:56:44.862995 u2DelayCellOfst[4]=15 cells (4 PI)
7818 00:56:44.866042 u2DelayCellOfst[5]=0 cells (0 PI)
7819 00:56:44.869688 u2DelayCellOfst[6]=18 cells (5 PI)
7820 00:56:44.872819 u2DelayCellOfst[7]=22 cells (6 PI)
7821 00:56:44.875925 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7822 00:56:44.879390 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7823 00:56:44.882823 == TX Byte 1 ==
7824 00:56:44.886348 u2DelayCellOfst[8]=0 cells (0 PI)
7825 00:56:44.889786 u2DelayCellOfst[9]=0 cells (0 PI)
7826 00:56:44.892528 u2DelayCellOfst[10]=3 cells (1 PI)
7827 00:56:44.895541 u2DelayCellOfst[11]=0 cells (0 PI)
7828 00:56:44.895964 u2DelayCellOfst[12]=11 cells (3 PI)
7829 00:56:44.899124 u2DelayCellOfst[13]=11 cells (3 PI)
7830 00:56:44.902734 u2DelayCellOfst[14]=15 cells (4 PI)
7831 00:56:44.905599 u2DelayCellOfst[15]=11 cells (3 PI)
7832 00:56:44.912335 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7833 00:56:44.916053 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7834 00:56:44.916724 DramC Write-DBI on
7835 00:56:44.918521 ==
7836 00:56:44.922332 Dram Type= 6, Freq= 0, CH_0, rank 0
7837 00:56:44.925375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7838 00:56:44.925939 ==
7839 00:56:44.926352
7840 00:56:44.926696
7841 00:56:44.929066 TX Vref Scan disable
7842 00:56:44.929628 == TX Byte 0 ==
7843 00:56:44.935216 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7844 00:56:44.935643 == TX Byte 1 ==
7845 00:56:44.938301 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7846 00:56:44.941774 DramC Write-DBI off
7847 00:56:44.942278
7848 00:56:44.942649 [DATLAT]
7849 00:56:44.944968 Freq=1600, CH0 RK0
7850 00:56:44.945445
7851 00:56:44.945811 DATLAT Default: 0xf
7852 00:56:44.948515 0, 0xFFFF, sum = 0
7853 00:56:44.949104 1, 0xFFFF, sum = 0
7854 00:56:44.951348 2, 0xFFFF, sum = 0
7855 00:56:44.954765 3, 0xFFFF, sum = 0
7856 00:56:44.955191 4, 0xFFFF, sum = 0
7857 00:56:44.958873 5, 0xFFFF, sum = 0
7858 00:56:44.959405 6, 0xFFFF, sum = 0
7859 00:56:44.961651 7, 0xFFFF, sum = 0
7860 00:56:44.962323 8, 0xFFFF, sum = 0
7861 00:56:44.964651 9, 0xFFFF, sum = 0
7862 00:56:44.965087 10, 0xFFFF, sum = 0
7863 00:56:44.968138 11, 0xFFFF, sum = 0
7864 00:56:44.968679 12, 0xFFFF, sum = 0
7865 00:56:44.971279 13, 0xFFFF, sum = 0
7866 00:56:44.971722 14, 0x0, sum = 1
7867 00:56:44.974541 15, 0x0, sum = 2
7868 00:56:44.974982 16, 0x0, sum = 3
7869 00:56:44.978102 17, 0x0, sum = 4
7870 00:56:44.978591 best_step = 15
7871 00:56:44.978928
7872 00:56:44.979238 ==
7873 00:56:44.981221 Dram Type= 6, Freq= 0, CH_0, rank 0
7874 00:56:44.987737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7875 00:56:44.988271 ==
7876 00:56:44.988609 RX Vref Scan: 1
7877 00:56:44.988920
7878 00:56:44.990979 Set Vref Range= 24 -> 127
7879 00:56:44.991481
7880 00:56:44.994513 RX Vref 24 -> 127, step: 1
7881 00:56:44.995124
7882 00:56:44.995469 RX Delay 11 -> 252, step: 4
7883 00:56:44.995887
7884 00:56:44.997739 Set Vref, RX VrefLevel [Byte0]: 24
7885 00:56:45.000965 [Byte1]: 24
7886 00:56:45.005060
7887 00:56:45.005575 Set Vref, RX VrefLevel [Byte0]: 25
7888 00:56:45.008364 [Byte1]: 25
7889 00:56:45.012588
7890 00:56:45.013226 Set Vref, RX VrefLevel [Byte0]: 26
7891 00:56:45.016137 [Byte1]: 26
7892 00:56:45.020666
7893 00:56:45.021209 Set Vref, RX VrefLevel [Byte0]: 27
7894 00:56:45.023755 [Byte1]: 27
7895 00:56:45.027787
7896 00:56:45.028226 Set Vref, RX VrefLevel [Byte0]: 28
7897 00:56:45.031214 [Byte1]: 28
7898 00:56:45.035782
7899 00:56:45.036372 Set Vref, RX VrefLevel [Byte0]: 29
7900 00:56:45.038908 [Byte1]: 29
7901 00:56:45.043393
7902 00:56:45.043834 Set Vref, RX VrefLevel [Byte0]: 30
7903 00:56:45.046379 [Byte1]: 30
7904 00:56:45.051127
7905 00:56:45.051692 Set Vref, RX VrefLevel [Byte0]: 31
7906 00:56:45.053909 [Byte1]: 31
7907 00:56:45.058625
7908 00:56:45.059067 Set Vref, RX VrefLevel [Byte0]: 32
7909 00:56:45.061515 [Byte1]: 32
7910 00:56:45.065697
7911 00:56:45.066358 Set Vref, RX VrefLevel [Byte0]: 33
7912 00:56:45.069262 [Byte1]: 33
7913 00:56:45.073720
7914 00:56:45.074199 Set Vref, RX VrefLevel [Byte0]: 34
7915 00:56:45.076857 [Byte1]: 34
7916 00:56:45.081526
7917 00:56:45.082058 Set Vref, RX VrefLevel [Byte0]: 35
7918 00:56:45.085011 [Byte1]: 35
7919 00:56:45.089251
7920 00:56:45.089776 Set Vref, RX VrefLevel [Byte0]: 36
7921 00:56:45.092670 [Byte1]: 36
7922 00:56:45.096713
7923 00:56:45.097199 Set Vref, RX VrefLevel [Byte0]: 37
7924 00:56:45.099786 [Byte1]: 37
7925 00:56:45.104287
7926 00:56:45.104959 Set Vref, RX VrefLevel [Byte0]: 38
7927 00:56:45.107167 [Byte1]: 38
7928 00:56:45.111477
7929 00:56:45.111914 Set Vref, RX VrefLevel [Byte0]: 39
7930 00:56:45.114975 [Byte1]: 39
7931 00:56:45.119186
7932 00:56:45.119608 Set Vref, RX VrefLevel [Byte0]: 40
7933 00:56:45.122503 [Byte1]: 40
7934 00:56:45.126759
7935 00:56:45.127200 Set Vref, RX VrefLevel [Byte0]: 41
7936 00:56:45.130344 [Byte1]: 41
7937 00:56:45.134605
7938 00:56:45.135046 Set Vref, RX VrefLevel [Byte0]: 42
7939 00:56:45.137943 [Byte1]: 42
7940 00:56:45.142079
7941 00:56:45.142661 Set Vref, RX VrefLevel [Byte0]: 43
7942 00:56:45.148335 [Byte1]: 43
7943 00:56:45.148967
7944 00:56:45.151704 Set Vref, RX VrefLevel [Byte0]: 44
7945 00:56:45.155004 [Byte1]: 44
7946 00:56:45.155492
7947 00:56:45.158195 Set Vref, RX VrefLevel [Byte0]: 45
7948 00:56:45.161442 [Byte1]: 45
7949 00:56:45.165090
7950 00:56:45.165516 Set Vref, RX VrefLevel [Byte0]: 46
7951 00:56:45.168131 [Byte1]: 46
7952 00:56:45.172666
7953 00:56:45.173265 Set Vref, RX VrefLevel [Byte0]: 47
7954 00:56:45.175776 [Byte1]: 47
7955 00:56:45.180141
7956 00:56:45.180567 Set Vref, RX VrefLevel [Byte0]: 48
7957 00:56:45.183957 [Byte1]: 48
7958 00:56:45.188125
7959 00:56:45.188553 Set Vref, RX VrefLevel [Byte0]: 49
7960 00:56:45.191156 [Byte1]: 49
7961 00:56:45.195190
7962 00:56:45.195631 Set Vref, RX VrefLevel [Byte0]: 50
7963 00:56:45.198833 [Byte1]: 50
7964 00:56:45.203481
7965 00:56:45.204006 Set Vref, RX VrefLevel [Byte0]: 51
7966 00:56:45.206480 [Byte1]: 51
7967 00:56:45.210820
7968 00:56:45.211401 Set Vref, RX VrefLevel [Byte0]: 52
7969 00:56:45.213716 [Byte1]: 52
7970 00:56:45.218300
7971 00:56:45.218741 Set Vref, RX VrefLevel [Byte0]: 53
7972 00:56:45.221672 [Byte1]: 53
7973 00:56:45.225793
7974 00:56:45.226278 Set Vref, RX VrefLevel [Byte0]: 54
7975 00:56:45.228846 [Byte1]: 54
7976 00:56:45.233403
7977 00:56:45.233829 Set Vref, RX VrefLevel [Byte0]: 55
7978 00:56:45.236562 [Byte1]: 55
7979 00:56:45.240816
7980 00:56:45.241338 Set Vref, RX VrefLevel [Byte0]: 56
7981 00:56:45.247941 [Byte1]: 56
7982 00:56:45.248384
7983 00:56:45.251108 Set Vref, RX VrefLevel [Byte0]: 57
7984 00:56:45.254002 [Byte1]: 57
7985 00:56:45.254462
7986 00:56:45.257447 Set Vref, RX VrefLevel [Byte0]: 58
7987 00:56:45.260704 [Byte1]: 58
7988 00:56:45.263831
7989 00:56:45.264254 Set Vref, RX VrefLevel [Byte0]: 59
7990 00:56:45.267531 [Byte1]: 59
7991 00:56:45.271848
7992 00:56:45.272285 Set Vref, RX VrefLevel [Byte0]: 60
7993 00:56:45.274586 [Byte1]: 60
7994 00:56:45.278890
7995 00:56:45.279308 Set Vref, RX VrefLevel [Byte0]: 61
7996 00:56:45.282397 [Byte1]: 61
7997 00:56:45.286769
7998 00:56:45.287195 Set Vref, RX VrefLevel [Byte0]: 62
7999 00:56:45.290283 [Byte1]: 62
8000 00:56:45.294615
8001 00:56:45.295031 Set Vref, RX VrefLevel [Byte0]: 63
8002 00:56:45.297489 [Byte1]: 63
8003 00:56:45.301956
8004 00:56:45.302513 Set Vref, RX VrefLevel [Byte0]: 64
8005 00:56:45.304924 [Byte1]: 64
8006 00:56:45.309436
8007 00:56:45.309853 Set Vref, RX VrefLevel [Byte0]: 65
8008 00:56:45.312987 [Byte1]: 65
8009 00:56:45.317296
8010 00:56:45.317809 Set Vref, RX VrefLevel [Byte0]: 66
8011 00:56:45.320723 [Byte1]: 66
8012 00:56:45.325114
8013 00:56:45.325556 Set Vref, RX VrefLevel [Byte0]: 67
8014 00:56:45.327994 [Byte1]: 67
8015 00:56:45.332808
8016 00:56:45.333233 Set Vref, RX VrefLevel [Byte0]: 68
8017 00:56:45.335591 [Byte1]: 68
8018 00:56:45.339833
8019 00:56:45.340261 Set Vref, RX VrefLevel [Byte0]: 69
8020 00:56:45.343399 [Byte1]: 69
8021 00:56:45.347686
8022 00:56:45.348114 Set Vref, RX VrefLevel [Byte0]: 70
8023 00:56:45.350601 [Byte1]: 70
8024 00:56:45.355485
8025 00:56:45.356002 Set Vref, RX VrefLevel [Byte0]: 71
8026 00:56:45.358416 [Byte1]: 71
8027 00:56:45.362609
8028 00:56:45.363027 Set Vref, RX VrefLevel [Byte0]: 72
8029 00:56:45.366318 [Byte1]: 72
8030 00:56:45.370427
8031 00:56:45.370847 Set Vref, RX VrefLevel [Byte0]: 73
8032 00:56:45.373645 [Byte1]: 73
8033 00:56:45.378505
8034 00:56:45.379018 Set Vref, RX VrefLevel [Byte0]: 74
8035 00:56:45.381612 [Byte1]: 74
8036 00:56:45.385726
8037 00:56:45.386268 Set Vref, RX VrefLevel [Byte0]: 75
8038 00:56:45.389440 [Byte1]: 75
8039 00:56:45.393151
8040 00:56:45.393568 Set Vref, RX VrefLevel [Byte0]: 76
8041 00:56:45.396956 [Byte1]: 76
8042 00:56:45.400758
8043 00:56:45.401175 Set Vref, RX VrefLevel [Byte0]: 77
8044 00:56:45.404712 [Byte1]: 77
8045 00:56:45.408745
8046 00:56:45.409163 Set Vref, RX VrefLevel [Byte0]: 78
8047 00:56:45.412052 [Byte1]: 78
8048 00:56:45.416496
8049 00:56:45.417017 Set Vref, RX VrefLevel [Byte0]: 79
8050 00:56:45.419682 [Byte1]: 79
8051 00:56:45.424061
8052 00:56:45.424481 Set Vref, RX VrefLevel [Byte0]: 80
8053 00:56:45.427342 [Byte1]: 80
8054 00:56:45.432063
8055 00:56:45.432677 Final RX Vref Byte 0 = 65 to rank0
8056 00:56:45.434724 Final RX Vref Byte 1 = 57 to rank0
8057 00:56:45.437850 Final RX Vref Byte 0 = 65 to rank1
8058 00:56:45.441109 Final RX Vref Byte 1 = 57 to rank1==
8059 00:56:45.444373 Dram Type= 6, Freq= 0, CH_0, rank 0
8060 00:56:45.451223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 00:56:45.451702 ==
8062 00:56:45.452043 DQS Delay:
8063 00:56:45.454187 DQS0 = 0, DQS1 = 0
8064 00:56:45.454611 DQM Delay:
8065 00:56:45.454943 DQM0 = 132, DQM1 = 123
8066 00:56:45.457793 DQ Delay:
8067 00:56:45.460736 DQ0 =130, DQ1 =134, DQ2 =130, DQ3 =132
8068 00:56:45.465004 DQ4 =132, DQ5 =122, DQ6 =138, DQ7 =140
8069 00:56:45.467772 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =118
8070 00:56:45.470829 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
8071 00:56:45.471249
8072 00:56:45.471580
8073 00:56:45.471883
8074 00:56:45.474145 [DramC_TX_OE_Calibration] TA2
8075 00:56:45.477467 Original DQ_B0 (3 6) =30, OEN = 27
8076 00:56:45.480796 Original DQ_B1 (3 6) =30, OEN = 27
8077 00:56:45.484048 24, 0x0, End_B0=24 End_B1=24
8078 00:56:45.484488 25, 0x0, End_B0=25 End_B1=25
8079 00:56:45.487271 26, 0x0, End_B0=26 End_B1=26
8080 00:56:45.490816 27, 0x0, End_B0=27 End_B1=27
8081 00:56:45.494424 28, 0x0, End_B0=28 End_B1=28
8082 00:56:45.497752 29, 0x0, End_B0=29 End_B1=29
8083 00:56:45.498336 30, 0x0, End_B0=30 End_B1=30
8084 00:56:45.501017 31, 0x4141, End_B0=30 End_B1=30
8085 00:56:45.504379 Byte0 end_step=30 best_step=27
8086 00:56:45.507175 Byte1 end_step=30 best_step=27
8087 00:56:45.510718 Byte0 TX OE(2T, 0.5T) = (3, 3)
8088 00:56:45.513975 Byte1 TX OE(2T, 0.5T) = (3, 3)
8089 00:56:45.514583
8090 00:56:45.514920
8091 00:56:45.520733 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8092 00:56:45.523753 CH0 RK0: MR19=303, MR18=2011
8093 00:56:45.531151 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8094 00:56:45.531719
8095 00:56:45.533604 ----->DramcWriteLeveling(PI) begin...
8096 00:56:45.534055 ==
8097 00:56:45.537415 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 00:56:45.540317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 00:56:45.540742 ==
8100 00:56:45.543954 Write leveling (Byte 0): 35 => 35
8101 00:56:45.547319 Write leveling (Byte 1): 29 => 29
8102 00:56:45.550252 DramcWriteLeveling(PI) end<-----
8103 00:56:45.550677
8104 00:56:45.551012 ==
8105 00:56:45.553743 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 00:56:45.557248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 00:56:45.560534 ==
8108 00:56:45.561071 [Gating] SW mode calibration
8109 00:56:45.570202 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8110 00:56:45.573768 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8111 00:56:45.576475 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 00:56:45.583540 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 00:56:45.586350 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 00:56:45.589639 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8115 00:56:45.595967 1 4 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8116 00:56:45.599458 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8117 00:56:45.602909 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8118 00:56:45.609817 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8119 00:56:45.612658 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8120 00:56:45.615955 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8121 00:56:45.622572 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8122 00:56:45.626132 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8123 00:56:45.629738 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8124 00:56:45.635640 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8125 00:56:45.639478 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 00:56:45.642205 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8127 00:56:45.648596 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8128 00:56:45.652326 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8129 00:56:45.658524 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8130 00:56:45.661625 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8131 00:56:45.665743 1 6 16 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
8132 00:56:45.668836 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8133 00:56:45.675282 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 00:56:45.678525 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8135 00:56:45.682216 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8136 00:56:45.688857 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8137 00:56:45.691945 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8138 00:56:45.695519 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8139 00:56:45.702035 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8140 00:56:45.705015 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 00:56:45.708461 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 00:56:45.714822 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 00:56:45.718464 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 00:56:45.721134 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 00:56:45.728106 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 00:56:45.731452 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 00:56:45.734688 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 00:56:45.741257 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 00:56:45.744765 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 00:56:45.747949 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 00:56:45.754208 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 00:56:45.757803 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8153 00:56:45.760755 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8154 00:56:45.767521 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8155 00:56:45.770801 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8156 00:56:45.774399 Total UI for P1: 0, mck2ui 16
8157 00:56:45.777431 best dqsien dly found for B0: ( 1, 9, 8)
8158 00:56:45.781407 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8159 00:56:45.787530 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8160 00:56:45.790545 Total UI for P1: 0, mck2ui 16
8161 00:56:45.794365 best dqsien dly found for B1: ( 1, 9, 18)
8162 00:56:45.797387 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8163 00:56:45.800820 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8164 00:56:45.801394
8165 00:56:45.804095 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8166 00:56:45.807513 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8167 00:56:45.810509 [Gating] SW calibration Done
8168 00:56:45.810984 ==
8169 00:56:45.814354 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 00:56:45.817429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 00:56:45.818017 ==
8172 00:56:45.820679 RX Vref Scan: 0
8173 00:56:45.821394
8174 00:56:45.823481 RX Vref 0 -> 0, step: 1
8175 00:56:45.823951
8176 00:56:45.824323 RX Delay 0 -> 252, step: 8
8177 00:56:45.830210 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8178 00:56:45.833761 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8179 00:56:45.837096 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8180 00:56:45.840570 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8181 00:56:45.843525 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8182 00:56:45.849957 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8183 00:56:45.853853 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8184 00:56:45.856397 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8185 00:56:45.860424 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8186 00:56:45.863397 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8187 00:56:45.870290 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8188 00:56:45.873362 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8189 00:56:45.876230 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8190 00:56:45.879539 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8191 00:56:45.886614 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8192 00:56:45.889576 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8193 00:56:45.890149 ==
8194 00:56:45.893535 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 00:56:45.896144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 00:56:45.896618 ==
8197 00:56:45.896988 DQS Delay:
8198 00:56:45.899697 DQS0 = 0, DQS1 = 0
8199 00:56:45.900397 DQM Delay:
8200 00:56:45.903459 DQM0 = 132, DQM1 = 128
8201 00:56:45.904031 DQ Delay:
8202 00:56:45.906208 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8203 00:56:45.909467 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8204 00:56:45.913054 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8205 00:56:45.919357 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8206 00:56:45.919917
8207 00:56:45.920289
8208 00:56:45.920635 ==
8209 00:56:45.922442 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 00:56:45.925663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 00:56:45.926135 ==
8212 00:56:45.926545
8213 00:56:45.926890
8214 00:56:45.929599 TX Vref Scan disable
8215 00:56:45.930204 == TX Byte 0 ==
8216 00:56:45.935972 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8217 00:56:45.939099 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8218 00:56:45.939527 == TX Byte 1 ==
8219 00:56:45.945844 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8220 00:56:45.948907 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8221 00:56:45.949335 ==
8222 00:56:45.952377 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 00:56:45.955605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 00:56:45.956033 ==
8225 00:56:45.970071
8226 00:56:45.974046 TX Vref early break, caculate TX vref
8227 00:56:45.976564 TX Vref=16, minBit 1, minWin=22, winSum=377
8228 00:56:45.980087 TX Vref=18, minBit 1, minWin=23, winSum=390
8229 00:56:45.983921 TX Vref=20, minBit 0, minWin=23, winSum=398
8230 00:56:45.987159 TX Vref=22, minBit 1, minWin=22, winSum=407
8231 00:56:45.989960 TX Vref=24, minBit 3, minWin=24, winSum=407
8232 00:56:45.996653 TX Vref=26, minBit 0, minWin=25, winSum=419
8233 00:56:45.999567 TX Vref=28, minBit 1, minWin=24, winSum=415
8234 00:56:46.003389 TX Vref=30, minBit 1, minWin=23, winSum=403
8235 00:56:46.007035 TX Vref=32, minBit 0, minWin=24, winSum=400
8236 00:56:46.009880 TX Vref=34, minBit 1, minWin=23, winSum=387
8237 00:56:46.016682 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 26
8238 00:56:46.017255
8239 00:56:46.019798 Final TX Range 0 Vref 26
8240 00:56:46.020265
8241 00:56:46.020633 ==
8242 00:56:46.023125 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 00:56:46.026373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 00:56:46.026850 ==
8245 00:56:46.027225
8246 00:56:46.027571
8247 00:56:46.029444 TX Vref Scan disable
8248 00:56:46.035900 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8249 00:56:46.036365 == TX Byte 0 ==
8250 00:56:46.039413 u2DelayCellOfst[0]=11 cells (3 PI)
8251 00:56:46.042946 u2DelayCellOfst[1]=15 cells (4 PI)
8252 00:56:46.045925 u2DelayCellOfst[2]=11 cells (3 PI)
8253 00:56:46.049070 u2DelayCellOfst[3]=11 cells (3 PI)
8254 00:56:46.052658 u2DelayCellOfst[4]=7 cells (2 PI)
8255 00:56:46.056306 u2DelayCellOfst[5]=0 cells (0 PI)
8256 00:56:46.059525 u2DelayCellOfst[6]=15 cells (4 PI)
8257 00:56:46.062950 u2DelayCellOfst[7]=15 cells (4 PI)
8258 00:56:46.066003 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8259 00:56:46.069239 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8260 00:56:46.072306 == TX Byte 1 ==
8261 00:56:46.075856 u2DelayCellOfst[8]=0 cells (0 PI)
8262 00:56:46.076291 u2DelayCellOfst[9]=3 cells (1 PI)
8263 00:56:46.079114 u2DelayCellOfst[10]=7 cells (2 PI)
8264 00:56:46.082485 u2DelayCellOfst[11]=3 cells (1 PI)
8265 00:56:46.085955 u2DelayCellOfst[12]=15 cells (4 PI)
8266 00:56:46.089406 u2DelayCellOfst[13]=11 cells (3 PI)
8267 00:56:46.092590 u2DelayCellOfst[14]=18 cells (5 PI)
8268 00:56:46.096171 u2DelayCellOfst[15]=11 cells (3 PI)
8269 00:56:46.102239 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8270 00:56:46.105447 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8271 00:56:46.105866 DramC Write-DBI on
8272 00:56:46.106238 ==
8273 00:56:46.109075 Dram Type= 6, Freq= 0, CH_0, rank 1
8274 00:56:46.115879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 00:56:46.116404 ==
8276 00:56:46.116795
8277 00:56:46.117280
8278 00:56:46.117803 TX Vref Scan disable
8279 00:56:46.119852 == TX Byte 0 ==
8280 00:56:46.123076 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8281 00:56:46.126517 == TX Byte 1 ==
8282 00:56:46.129744 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8283 00:56:46.132693 DramC Write-DBI off
8284 00:56:46.133110
8285 00:56:46.133441 [DATLAT]
8286 00:56:46.133778 Freq=1600, CH0 RK1
8287 00:56:46.134127
8288 00:56:46.136043 DATLAT Default: 0xf
8289 00:56:46.139772 0, 0xFFFF, sum = 0
8290 00:56:46.140355 1, 0xFFFF, sum = 0
8291 00:56:46.143048 2, 0xFFFF, sum = 0
8292 00:56:46.143478 3, 0xFFFF, sum = 0
8293 00:56:46.145909 4, 0xFFFF, sum = 0
8294 00:56:46.146367 5, 0xFFFF, sum = 0
8295 00:56:46.149283 6, 0xFFFF, sum = 0
8296 00:56:46.149787 7, 0xFFFF, sum = 0
8297 00:56:46.152770 8, 0xFFFF, sum = 0
8298 00:56:46.153232 9, 0xFFFF, sum = 0
8299 00:56:46.155944 10, 0xFFFF, sum = 0
8300 00:56:46.156469 11, 0xFFFF, sum = 0
8301 00:56:46.159562 12, 0xFFFF, sum = 0
8302 00:56:46.160086 13, 0xFFFF, sum = 0
8303 00:56:46.162489 14, 0x0, sum = 1
8304 00:56:46.162914 15, 0x0, sum = 2
8305 00:56:46.165622 16, 0x0, sum = 3
8306 00:56:46.166047 17, 0x0, sum = 4
8307 00:56:46.169376 best_step = 15
8308 00:56:46.169893
8309 00:56:46.170271 ==
8310 00:56:46.172642 Dram Type= 6, Freq= 0, CH_0, rank 1
8311 00:56:46.175554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 00:56:46.175980 ==
8313 00:56:46.178740 RX Vref Scan: 0
8314 00:56:46.179154
8315 00:56:46.179489 RX Vref 0 -> 0, step: 1
8316 00:56:46.179797
8317 00:56:46.182289 RX Delay 11 -> 252, step: 4
8318 00:56:46.189115 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8319 00:56:46.191964 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8320 00:56:46.195846 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8321 00:56:46.198820 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8322 00:56:46.202181 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8323 00:56:46.208463 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8324 00:56:46.211629 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8325 00:56:46.215105 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8326 00:56:46.218575 iDelay=191, Bit 8, Center 116 (63 ~ 170) 108
8327 00:56:46.221803 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8328 00:56:46.228955 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8329 00:56:46.231438 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8330 00:56:46.235112 iDelay=191, Bit 12, Center 132 (79 ~ 186) 108
8331 00:56:46.238070 iDelay=191, Bit 13, Center 132 (79 ~ 186) 108
8332 00:56:46.244875 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8333 00:56:46.248109 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8334 00:56:46.248533 ==
8335 00:56:46.251448 Dram Type= 6, Freq= 0, CH_0, rank 1
8336 00:56:46.254914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8337 00:56:46.255338 ==
8338 00:56:46.255668 DQS Delay:
8339 00:56:46.258132 DQS0 = 0, DQS1 = 0
8340 00:56:46.258582 DQM Delay:
8341 00:56:46.261653 DQM0 = 129, DQM1 = 125
8342 00:56:46.262070 DQ Delay:
8343 00:56:46.264693 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8344 00:56:46.268095 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
8345 00:56:46.271444 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8346 00:56:46.278102 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8347 00:56:46.278545
8348 00:56:46.278878
8349 00:56:46.279182
8350 00:56:46.281235 [DramC_TX_OE_Calibration] TA2
8351 00:56:46.284740 Original DQ_B0 (3 6) =30, OEN = 27
8352 00:56:46.285385 Original DQ_B1 (3 6) =30, OEN = 27
8353 00:56:46.287832 24, 0x0, End_B0=24 End_B1=24
8354 00:56:46.291031 25, 0x0, End_B0=25 End_B1=25
8355 00:56:46.294548 26, 0x0, End_B0=26 End_B1=26
8356 00:56:46.297914 27, 0x0, End_B0=27 End_B1=27
8357 00:56:46.298416 28, 0x0, End_B0=28 End_B1=28
8358 00:56:46.300778 29, 0x0, End_B0=29 End_B1=29
8359 00:56:46.303911 30, 0x0, End_B0=30 End_B1=30
8360 00:56:46.307433 31, 0x4545, End_B0=30 End_B1=30
8361 00:56:46.310881 Byte0 end_step=30 best_step=27
8362 00:56:46.314206 Byte1 end_step=30 best_step=27
8363 00:56:46.314640 Byte0 TX OE(2T, 0.5T) = (3, 3)
8364 00:56:46.317014 Byte1 TX OE(2T, 0.5T) = (3, 3)
8365 00:56:46.317433
8366 00:56:46.317762
8367 00:56:46.327066 [DQSOSCAuto] RK1, (LSB)MR18= 0x2206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
8368 00:56:46.330815 CH0 RK1: MR19=303, MR18=2206
8369 00:56:46.333805 CH0_RK1: MR19=0x303, MR18=0x2206, DQSOSC=392, MR23=63, INC=24, DEC=16
8370 00:56:46.337148 [RxdqsGatingPostProcess] freq 1600
8371 00:56:46.344012 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8372 00:56:46.347280 best DQS0 dly(2T, 0.5T) = (1, 1)
8373 00:56:46.350219 best DQS1 dly(2T, 0.5T) = (1, 1)
8374 00:56:46.353550 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8375 00:56:46.357175 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8376 00:56:46.360603 best DQS0 dly(2T, 0.5T) = (1, 1)
8377 00:56:46.363282 best DQS1 dly(2T, 0.5T) = (1, 1)
8378 00:56:46.363714 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8379 00:56:46.366735 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8380 00:56:46.370221 Pre-setting of DQS Precalculation
8381 00:56:46.376782 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8382 00:56:46.377201 ==
8383 00:56:46.379956 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 00:56:46.383258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 00:56:46.383681 ==
8386 00:56:46.390312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8387 00:56:46.393271 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8388 00:56:46.396526 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8389 00:56:46.402863 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8390 00:56:46.412749 [CA 0] Center 42 (12~72) winsize 61
8391 00:56:46.415859 [CA 1] Center 42 (13~72) winsize 60
8392 00:56:46.419182 [CA 2] Center 38 (9~67) winsize 59
8393 00:56:46.423090 [CA 3] Center 37 (8~66) winsize 59
8394 00:56:46.425812 [CA 4] Center 37 (8~67) winsize 60
8395 00:56:46.429164 [CA 5] Center 37 (8~67) winsize 60
8396 00:56:46.429581
8397 00:56:46.432160 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8398 00:56:46.432577
8399 00:56:46.435632 [CATrainingPosCal] consider 1 rank data
8400 00:56:46.438890 u2DelayCellTimex100 = 258/100 ps
8401 00:56:46.445428 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8402 00:56:46.448728 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8403 00:56:46.452330 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8404 00:56:46.455757 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8405 00:56:46.458706 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8406 00:56:46.462279 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8407 00:56:46.462806
8408 00:56:46.465687 CA PerBit enable=1, Macro0, CA PI delay=37
8409 00:56:46.466123
8410 00:56:46.468556 [CBTSetCACLKResult] CA Dly = 37
8411 00:56:46.471908 CS Dly: 9 (0~40)
8412 00:56:46.475531 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8413 00:56:46.478803 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8414 00:56:46.479232 ==
8415 00:56:46.481846 Dram Type= 6, Freq= 0, CH_1, rank 1
8416 00:56:46.488395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 00:56:46.488911 ==
8418 00:56:46.491871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8419 00:56:46.498370 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8420 00:56:46.501566 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8421 00:56:46.508496 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8422 00:56:46.516249 [CA 0] Center 42 (13~72) winsize 60
8423 00:56:46.519450 [CA 1] Center 42 (12~72) winsize 61
8424 00:56:46.522627 [CA 2] Center 37 (8~67) winsize 60
8425 00:56:46.525419 [CA 3] Center 37 (8~66) winsize 59
8426 00:56:46.528819 [CA 4] Center 37 (8~67) winsize 60
8427 00:56:46.532712 [CA 5] Center 37 (7~67) winsize 61
8428 00:56:46.533302
8429 00:56:46.535410 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8430 00:56:46.535835
8431 00:56:46.542093 [CATrainingPosCal] consider 2 rank data
8432 00:56:46.542539 u2DelayCellTimex100 = 258/100 ps
8433 00:56:46.549478 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8434 00:56:46.552235 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8435 00:56:46.555148 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8436 00:56:46.558655 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8437 00:56:46.562390 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8438 00:56:46.565270 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8439 00:56:46.565698
8440 00:56:46.568765 CA PerBit enable=1, Macro0, CA PI delay=37
8441 00:56:46.569349
8442 00:56:46.571932 [CBTSetCACLKResult] CA Dly = 37
8443 00:56:46.575174 CS Dly: 10 (0~43)
8444 00:56:46.578136 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8445 00:56:46.581470 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8446 00:56:46.581974
8447 00:56:46.585609 ----->DramcWriteLeveling(PI) begin...
8448 00:56:46.586146 ==
8449 00:56:46.588634 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 00:56:46.595124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 00:56:46.595886 ==
8452 00:56:46.598125 Write leveling (Byte 0): 23 => 23
8453 00:56:46.601507 Write leveling (Byte 1): 25 => 25
8454 00:56:46.602021 DramcWriteLeveling(PI) end<-----
8455 00:56:46.604693
8456 00:56:46.605139 ==
8457 00:56:46.608076 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 00:56:46.611743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 00:56:46.612174 ==
8460 00:56:46.615482 [Gating] SW mode calibration
8461 00:56:46.621525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8462 00:56:46.625335 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8463 00:56:46.631767 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 00:56:46.635000 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 00:56:46.638106 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 00:56:46.644824 1 4 12 | B1->B0 | 302f 3434 | 1 1 | (0 0) (1 1)
8467 00:56:46.647717 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8468 00:56:46.651285 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8469 00:56:46.657778 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8470 00:56:46.660997 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8471 00:56:46.664647 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8472 00:56:46.671284 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8473 00:56:46.674126 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8474 00:56:46.678013 1 5 12 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
8475 00:56:46.684743 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8476 00:56:46.687398 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8477 00:56:46.690914 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8478 00:56:46.697668 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8479 00:56:46.700848 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8480 00:56:46.703964 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8481 00:56:46.710909 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8482 00:56:46.714276 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
8483 00:56:46.717457 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 00:56:46.724250 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 00:56:46.727388 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 00:56:46.730576 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 00:56:46.737552 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 00:56:46.740411 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8489 00:56:46.743942 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 00:56:46.750639 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8491 00:56:46.753894 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8492 00:56:46.757010 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 00:56:46.763591 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 00:56:46.766817 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 00:56:46.770501 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 00:56:46.777076 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 00:56:46.780446 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 00:56:46.783831 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 00:56:46.790441 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 00:56:46.793621 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 00:56:46.796948 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 00:56:46.803100 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 00:56:46.806402 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 00:56:46.809906 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 00:56:46.816443 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8506 00:56:46.819724 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8507 00:56:46.822940 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8508 00:56:46.826430 Total UI for P1: 0, mck2ui 16
8509 00:56:46.829756 best dqsien dly found for B0: ( 1, 9, 10)
8510 00:56:46.833186 Total UI for P1: 0, mck2ui 16
8511 00:56:46.836524 best dqsien dly found for B1: ( 1, 9, 10)
8512 00:56:46.839525 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8513 00:56:46.842740 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8514 00:56:46.843221
8515 00:56:46.850077 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8516 00:56:46.852998 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8517 00:56:46.855933 [Gating] SW calibration Done
8518 00:56:46.856444 ==
8519 00:56:46.859747 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 00:56:46.862551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 00:56:46.863036 ==
8522 00:56:46.863524 RX Vref Scan: 0
8523 00:56:46.863973
8524 00:56:46.865758 RX Vref 0 -> 0, step: 1
8525 00:56:46.866286
8526 00:56:46.869425 RX Delay 0 -> 252, step: 8
8527 00:56:46.872239 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8528 00:56:46.875685 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8529 00:56:46.882234 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8530 00:56:46.885607 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8531 00:56:46.889070 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8532 00:56:46.892691 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8533 00:56:46.895611 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8534 00:56:46.902745 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8535 00:56:46.905497 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8536 00:56:46.908896 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8537 00:56:46.912266 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8538 00:56:46.915831 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8539 00:56:46.922081 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8540 00:56:46.925125 iDelay=208, Bit 13, Center 135 (72 ~ 199) 128
8541 00:56:46.928562 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8542 00:56:46.932083 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8543 00:56:46.932662 ==
8544 00:56:46.934993 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 00:56:46.941572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 00:56:46.942062 ==
8547 00:56:46.942520 DQS Delay:
8548 00:56:46.945108 DQS0 = 0, DQS1 = 0
8549 00:56:46.945670 DQM Delay:
8550 00:56:46.948090 DQM0 = 137, DQM1 = 128
8551 00:56:46.948555 DQ Delay:
8552 00:56:46.951461 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8553 00:56:46.955160 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8554 00:56:46.957983 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8555 00:56:46.961644 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8556 00:56:46.962273
8557 00:56:46.962831
8558 00:56:46.963311 ==
8559 00:56:46.964823 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 00:56:46.971454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 00:56:46.971902 ==
8562 00:56:46.972295
8563 00:56:46.972766
8564 00:56:46.973366 TX Vref Scan disable
8565 00:56:46.974889 == TX Byte 0 ==
8566 00:56:46.978007 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8567 00:56:46.985229 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8568 00:56:46.985650 == TX Byte 1 ==
8569 00:56:46.988162 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8570 00:56:46.994496 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8571 00:56:46.995098 ==
8572 00:56:46.997650 Dram Type= 6, Freq= 0, CH_1, rank 0
8573 00:56:47.001429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8574 00:56:47.001954 ==
8575 00:56:47.013477
8576 00:56:47.017242 TX Vref early break, caculate TX vref
8577 00:56:47.020434 TX Vref=16, minBit 0, minWin=21, winSum=373
8578 00:56:47.023307 TX Vref=18, minBit 5, minWin=21, winSum=383
8579 00:56:47.026726 TX Vref=20, minBit 5, minWin=23, winSum=394
8580 00:56:47.029787 TX Vref=22, minBit 5, minWin=23, winSum=407
8581 00:56:47.033574 TX Vref=24, minBit 0, minWin=24, winSum=411
8582 00:56:47.040006 TX Vref=26, minBit 5, minWin=24, winSum=418
8583 00:56:47.043613 TX Vref=28, minBit 0, minWin=25, winSum=421
8584 00:56:47.046764 TX Vref=30, minBit 0, minWin=24, winSum=411
8585 00:56:47.049939 TX Vref=32, minBit 0, minWin=24, winSum=403
8586 00:56:47.052991 TX Vref=34, minBit 0, minWin=23, winSum=394
8587 00:56:47.059712 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8588 00:56:47.060132
8589 00:56:47.063245 Final TX Range 0 Vref 28
8590 00:56:47.063668
8591 00:56:47.063998 ==
8592 00:56:47.066267 Dram Type= 6, Freq= 0, CH_1, rank 0
8593 00:56:47.069962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8594 00:56:47.070552 ==
8595 00:56:47.070896
8596 00:56:47.071203
8597 00:56:47.073137 TX Vref Scan disable
8598 00:56:47.079431 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8599 00:56:47.079850 == TX Byte 0 ==
8600 00:56:47.082710 u2DelayCellOfst[0]=18 cells (5 PI)
8601 00:56:47.086028 u2DelayCellOfst[1]=11 cells (3 PI)
8602 00:56:47.089439 u2DelayCellOfst[2]=0 cells (0 PI)
8603 00:56:47.092727 u2DelayCellOfst[3]=3 cells (1 PI)
8604 00:56:47.095967 u2DelayCellOfst[4]=7 cells (2 PI)
8605 00:56:47.098917 u2DelayCellOfst[5]=22 cells (6 PI)
8606 00:56:47.102677 u2DelayCellOfst[6]=18 cells (5 PI)
8607 00:56:47.105923 u2DelayCellOfst[7]=3 cells (1 PI)
8608 00:56:47.109551 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8609 00:56:47.112846 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8610 00:56:47.116364 == TX Byte 1 ==
8611 00:56:47.119113 u2DelayCellOfst[8]=0 cells (0 PI)
8612 00:56:47.122544 u2DelayCellOfst[9]=3 cells (1 PI)
8613 00:56:47.123064 u2DelayCellOfst[10]=11 cells (3 PI)
8614 00:56:47.125600 u2DelayCellOfst[11]=3 cells (1 PI)
8615 00:56:47.128657 u2DelayCellOfst[12]=15 cells (4 PI)
8616 00:56:47.132241 u2DelayCellOfst[13]=18 cells (5 PI)
8617 00:56:47.135478 u2DelayCellOfst[14]=18 cells (5 PI)
8618 00:56:47.138906 u2DelayCellOfst[15]=18 cells (5 PI)
8619 00:56:47.145420 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8620 00:56:47.149000 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8621 00:56:47.149467 DramC Write-DBI on
8622 00:56:47.150058 ==
8623 00:56:47.151732 Dram Type= 6, Freq= 0, CH_1, rank 0
8624 00:56:47.159148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8625 00:56:47.159653 ==
8626 00:56:47.160125
8627 00:56:47.160624
8628 00:56:47.161172 TX Vref Scan disable
8629 00:56:47.162601 == TX Byte 0 ==
8630 00:56:47.165802 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8631 00:56:47.169177 == TX Byte 1 ==
8632 00:56:47.173035 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8633 00:56:47.176389 DramC Write-DBI off
8634 00:56:47.176824
8635 00:56:47.177291 [DATLAT]
8636 00:56:47.177704 Freq=1600, CH1 RK0
8637 00:56:47.178247
8638 00:56:47.179034 DATLAT Default: 0xf
8639 00:56:47.182557 0, 0xFFFF, sum = 0
8640 00:56:47.182999 1, 0xFFFF, sum = 0
8641 00:56:47.185912 2, 0xFFFF, sum = 0
8642 00:56:47.186390 3, 0xFFFF, sum = 0
8643 00:56:47.189075 4, 0xFFFF, sum = 0
8644 00:56:47.189643 5, 0xFFFF, sum = 0
8645 00:56:47.192218 6, 0xFFFF, sum = 0
8646 00:56:47.192791 7, 0xFFFF, sum = 0
8647 00:56:47.195762 8, 0xFFFF, sum = 0
8648 00:56:47.196494 9, 0xFFFF, sum = 0
8649 00:56:47.199008 10, 0xFFFF, sum = 0
8650 00:56:47.199583 11, 0xFFFF, sum = 0
8651 00:56:47.202375 12, 0xFFFF, sum = 0
8652 00:56:47.202931 13, 0xFFFF, sum = 0
8653 00:56:47.205333 14, 0x0, sum = 1
8654 00:56:47.205850 15, 0x0, sum = 2
8655 00:56:47.208978 16, 0x0, sum = 3
8656 00:56:47.209548 17, 0x0, sum = 4
8657 00:56:47.212025 best_step = 15
8658 00:56:47.212613
8659 00:56:47.213106 ==
8660 00:56:47.215101 Dram Type= 6, Freq= 0, CH_1, rank 0
8661 00:56:47.218467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8662 00:56:47.219003 ==
8663 00:56:47.222517 RX Vref Scan: 1
8664 00:56:47.223132
8665 00:56:47.223617 Set Vref Range= 24 -> 127
8666 00:56:47.224047
8667 00:56:47.225398 RX Vref 24 -> 127, step: 1
8668 00:56:47.225779
8669 00:56:47.228573 RX Delay 11 -> 252, step: 4
8670 00:56:47.229153
8671 00:56:47.231795 Set Vref, RX VrefLevel [Byte0]: 24
8672 00:56:47.234996 [Byte1]: 24
8673 00:56:47.235574
8674 00:56:47.238260 Set Vref, RX VrefLevel [Byte0]: 25
8675 00:56:47.241781 [Byte1]: 25
8676 00:56:47.245317
8677 00:56:47.245887 Set Vref, RX VrefLevel [Byte0]: 26
8678 00:56:47.248573 [Byte1]: 26
8679 00:56:47.253193
8680 00:56:47.253607 Set Vref, RX VrefLevel [Byte0]: 27
8681 00:56:47.256785 [Byte1]: 27
8682 00:56:47.260662
8683 00:56:47.261271 Set Vref, RX VrefLevel [Byte0]: 28
8684 00:56:47.264010 [Byte1]: 28
8685 00:56:47.268226
8686 00:56:47.268644 Set Vref, RX VrefLevel [Byte0]: 29
8687 00:56:47.271367 [Byte1]: 29
8688 00:56:47.275641
8689 00:56:47.276230 Set Vref, RX VrefLevel [Byte0]: 30
8690 00:56:47.279374 [Byte1]: 30
8691 00:56:47.283450
8692 00:56:47.283867 Set Vref, RX VrefLevel [Byte0]: 31
8693 00:56:47.286798 [Byte1]: 31
8694 00:56:47.291152
8695 00:56:47.291782 Set Vref, RX VrefLevel [Byte0]: 32
8696 00:56:47.294243 [Byte1]: 32
8697 00:56:47.298602
8698 00:56:47.299057 Set Vref, RX VrefLevel [Byte0]: 33
8699 00:56:47.302264 [Byte1]: 33
8700 00:56:47.306403
8701 00:56:47.306922 Set Vref, RX VrefLevel [Byte0]: 34
8702 00:56:47.309844 [Byte1]: 34
8703 00:56:47.313991
8704 00:56:47.314573 Set Vref, RX VrefLevel [Byte0]: 35
8705 00:56:47.317468 [Byte1]: 35
8706 00:56:47.321713
8707 00:56:47.322137 Set Vref, RX VrefLevel [Byte0]: 36
8708 00:56:47.325217 [Byte1]: 36
8709 00:56:47.329172
8710 00:56:47.329806 Set Vref, RX VrefLevel [Byte0]: 37
8711 00:56:47.332339 [Byte1]: 37
8712 00:56:47.336735
8713 00:56:47.337488 Set Vref, RX VrefLevel [Byte0]: 38
8714 00:56:47.340264 [Byte1]: 38
8715 00:56:47.344883
8716 00:56:47.345401 Set Vref, RX VrefLevel [Byte0]: 39
8717 00:56:47.347621 [Byte1]: 39
8718 00:56:47.351971
8719 00:56:47.352393 Set Vref, RX VrefLevel [Byte0]: 40
8720 00:56:47.355457 [Byte1]: 40
8721 00:56:47.359721
8722 00:56:47.360140 Set Vref, RX VrefLevel [Byte0]: 41
8723 00:56:47.362920 [Byte1]: 41
8724 00:56:47.367189
8725 00:56:47.367612 Set Vref, RX VrefLevel [Byte0]: 42
8726 00:56:47.370653 [Byte1]: 42
8727 00:56:47.374815
8728 00:56:47.375238 Set Vref, RX VrefLevel [Byte0]: 43
8729 00:56:47.378285 [Byte1]: 43
8730 00:56:47.382596
8731 00:56:47.383019 Set Vref, RX VrefLevel [Byte0]: 44
8732 00:56:47.385588 [Byte1]: 44
8733 00:56:47.390244
8734 00:56:47.390666 Set Vref, RX VrefLevel [Byte0]: 45
8735 00:56:47.393323 [Byte1]: 45
8736 00:56:47.397547
8737 00:56:47.397969 Set Vref, RX VrefLevel [Byte0]: 46
8738 00:56:47.401121 [Byte1]: 46
8739 00:56:47.405459
8740 00:56:47.406194 Set Vref, RX VrefLevel [Byte0]: 47
8741 00:56:47.408598 [Byte1]: 47
8742 00:56:47.413051
8743 00:56:47.413566 Set Vref, RX VrefLevel [Byte0]: 48
8744 00:56:47.416722 [Byte1]: 48
8745 00:56:47.420703
8746 00:56:47.421126 Set Vref, RX VrefLevel [Byte0]: 49
8747 00:56:47.423705 [Byte1]: 49
8748 00:56:47.428322
8749 00:56:47.428944 Set Vref, RX VrefLevel [Byte0]: 50
8750 00:56:47.431309 [Byte1]: 50
8751 00:56:47.435917
8752 00:56:47.436336 Set Vref, RX VrefLevel [Byte0]: 51
8753 00:56:47.439277 [Byte1]: 51
8754 00:56:47.443712
8755 00:56:47.444240 Set Vref, RX VrefLevel [Byte0]: 52
8756 00:56:47.447050 [Byte1]: 52
8757 00:56:47.451185
8758 00:56:47.451641 Set Vref, RX VrefLevel [Byte0]: 53
8759 00:56:47.454237 [Byte1]: 53
8760 00:56:47.458852
8761 00:56:47.459272 Set Vref, RX VrefLevel [Byte0]: 54
8762 00:56:47.462296 [Byte1]: 54
8763 00:56:47.466119
8764 00:56:47.466589 Set Vref, RX VrefLevel [Byte0]: 55
8765 00:56:47.469525 [Byte1]: 55
8766 00:56:47.473801
8767 00:56:47.474286 Set Vref, RX VrefLevel [Byte0]: 56
8768 00:56:47.477296 [Byte1]: 56
8769 00:56:47.481578
8770 00:56:47.481995 Set Vref, RX VrefLevel [Byte0]: 57
8771 00:56:47.484963 [Byte1]: 57
8772 00:56:47.488911
8773 00:56:47.489408 Set Vref, RX VrefLevel [Byte0]: 58
8774 00:56:47.492057 [Byte1]: 58
8775 00:56:47.496844
8776 00:56:47.497271 Set Vref, RX VrefLevel [Byte0]: 59
8777 00:56:47.500511 [Byte1]: 59
8778 00:56:47.504347
8779 00:56:47.504869 Set Vref, RX VrefLevel [Byte0]: 60
8780 00:56:47.507830 [Byte1]: 60
8781 00:56:47.511916
8782 00:56:47.512343 Set Vref, RX VrefLevel [Byte0]: 61
8783 00:56:47.515417 [Byte1]: 61
8784 00:56:47.519474
8785 00:56:47.520066 Set Vref, RX VrefLevel [Byte0]: 62
8786 00:56:47.522836 [Byte1]: 62
8787 00:56:47.527116
8788 00:56:47.527539 Set Vref, RX VrefLevel [Byte0]: 63
8789 00:56:47.530404 [Byte1]: 63
8790 00:56:47.534622
8791 00:56:47.535045 Set Vref, RX VrefLevel [Byte0]: 64
8792 00:56:47.538114 [Byte1]: 64
8793 00:56:47.542838
8794 00:56:47.543353 Set Vref, RX VrefLevel [Byte0]: 65
8795 00:56:47.545533 [Byte1]: 65
8796 00:56:47.549777
8797 00:56:47.550232 Set Vref, RX VrefLevel [Byte0]: 66
8798 00:56:47.553143 [Byte1]: 66
8799 00:56:47.557713
8800 00:56:47.558131 Set Vref, RX VrefLevel [Byte0]: 67
8801 00:56:47.561003 [Byte1]: 67
8802 00:56:47.565271
8803 00:56:47.565692 Set Vref, RX VrefLevel [Byte0]: 68
8804 00:56:47.568298 [Byte1]: 68
8805 00:56:47.572651
8806 00:56:47.573072 Set Vref, RX VrefLevel [Byte0]: 69
8807 00:56:47.576001 [Byte1]: 69
8808 00:56:47.580683
8809 00:56:47.581130 Set Vref, RX VrefLevel [Byte0]: 70
8810 00:56:47.583405 [Byte1]: 70
8811 00:56:47.587824
8812 00:56:47.588246 Final RX Vref Byte 0 = 53 to rank0
8813 00:56:47.591452 Final RX Vref Byte 1 = 60 to rank0
8814 00:56:47.594335 Final RX Vref Byte 0 = 53 to rank1
8815 00:56:47.597944 Final RX Vref Byte 1 = 60 to rank1==
8816 00:56:47.601099 Dram Type= 6, Freq= 0, CH_1, rank 0
8817 00:56:47.607895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 00:56:47.608350 ==
8819 00:56:47.608683 DQS Delay:
8820 00:56:47.610876 DQS0 = 0, DQS1 = 0
8821 00:56:47.611312 DQM Delay:
8822 00:56:47.611651 DQM0 = 133, DQM1 = 127
8823 00:56:47.614073 DQ Delay:
8824 00:56:47.617586 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8825 00:56:47.621322 DQ4 =132, DQ5 =146, DQ6 =142, DQ7 =128
8826 00:56:47.624204 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8827 00:56:47.627348 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =136
8828 00:56:47.627769
8829 00:56:47.628099
8830 00:56:47.628566
8831 00:56:47.630694 [DramC_TX_OE_Calibration] TA2
8832 00:56:47.634275 Original DQ_B0 (3 6) =30, OEN = 27
8833 00:56:47.637610 Original DQ_B1 (3 6) =30, OEN = 27
8834 00:56:47.640647 24, 0x0, End_B0=24 End_B1=24
8835 00:56:47.643943 25, 0x0, End_B0=25 End_B1=25
8836 00:56:47.644412 26, 0x0, End_B0=26 End_B1=26
8837 00:56:47.647064 27, 0x0, End_B0=27 End_B1=27
8838 00:56:47.650545 28, 0x0, End_B0=28 End_B1=28
8839 00:56:47.653854 29, 0x0, End_B0=29 End_B1=29
8840 00:56:47.654366 30, 0x0, End_B0=30 End_B1=30
8841 00:56:47.657083 31, 0x4545, End_B0=30 End_B1=30
8842 00:56:47.660650 Byte0 end_step=30 best_step=27
8843 00:56:47.664014 Byte1 end_step=30 best_step=27
8844 00:56:47.666986 Byte0 TX OE(2T, 0.5T) = (3, 3)
8845 00:56:47.670027 Byte1 TX OE(2T, 0.5T) = (3, 3)
8846 00:56:47.670501
8847 00:56:47.670839
8848 00:56:47.676899 [DQSOSCAuto] RK0, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8849 00:56:47.680399 CH1 RK0: MR19=303, MR18=190F
8850 00:56:47.686681 CH1_RK0: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8851 00:56:47.687103
8852 00:56:47.690095 ----->DramcWriteLeveling(PI) begin...
8853 00:56:47.690652 ==
8854 00:56:47.693608 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 00:56:47.696656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 00:56:47.697083 ==
8857 00:56:47.700554 Write leveling (Byte 0): 22 => 22
8858 00:56:47.703444 Write leveling (Byte 1): 28 => 28
8859 00:56:47.706972 DramcWriteLeveling(PI) end<-----
8860 00:56:47.707388
8861 00:56:47.707718 ==
8862 00:56:47.709988 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 00:56:47.713468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 00:56:47.716721 ==
8865 00:56:47.717252 [Gating] SW mode calibration
8866 00:56:47.726703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8867 00:56:47.729873 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8868 00:56:47.733996 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8869 00:56:47.739864 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8870 00:56:47.743109 1 4 8 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
8871 00:56:47.746267 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8872 00:56:47.753145 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8873 00:56:47.756275 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8874 00:56:47.759450 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8875 00:56:47.766271 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8876 00:56:47.769449 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8877 00:56:47.772620 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8878 00:56:47.779400 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8879 00:56:47.782818 1 5 12 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8880 00:56:47.785856 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8881 00:56:47.792829 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8882 00:56:47.796127 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8883 00:56:47.799578 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8884 00:56:47.806437 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8885 00:56:47.809426 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8886 00:56:47.813056 1 6 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8887 00:56:47.819136 1 6 12 | B1->B0 | 4444 2424 | 0 0 | (0 0) (0 0)
8888 00:56:47.822582 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 00:56:47.826122 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 00:56:47.832242 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 00:56:47.835775 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8892 00:56:47.838966 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8893 00:56:47.845626 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8894 00:56:47.848881 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8895 00:56:47.852435 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8896 00:56:47.858785 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8897 00:56:47.862217 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 00:56:47.865569 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 00:56:47.872184 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 00:56:47.874758 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 00:56:47.878260 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 00:56:47.884916 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 00:56:47.888437 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 00:56:47.891794 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 00:56:47.897978 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 00:56:47.901277 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 00:56:47.904836 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 00:56:47.911450 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 00:56:47.914451 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 00:56:47.918026 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8911 00:56:47.924749 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8912 00:56:47.927552 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8913 00:56:47.931217 Total UI for P1: 0, mck2ui 16
8914 00:56:47.934156 best dqsien dly found for B0: ( 1, 9, 10)
8915 00:56:47.937581 Total UI for P1: 0, mck2ui 16
8916 00:56:47.940751 best dqsien dly found for B1: ( 1, 9, 10)
8917 00:56:47.944114 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8918 00:56:47.947699 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8919 00:56:47.948163
8920 00:56:47.950721 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8921 00:56:47.957272 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8922 00:56:47.957717 [Gating] SW calibration Done
8923 00:56:47.958061 ==
8924 00:56:47.960754 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 00:56:47.967034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 00:56:47.967468 ==
8927 00:56:47.967810 RX Vref Scan: 0
8928 00:56:47.968126
8929 00:56:47.970237 RX Vref 0 -> 0, step: 1
8930 00:56:47.970666
8931 00:56:47.973834 RX Delay 0 -> 252, step: 8
8932 00:56:47.977413 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8933 00:56:47.980574 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8934 00:56:47.983816 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8935 00:56:47.990064 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8936 00:56:47.993919 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8937 00:56:47.996762 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8938 00:56:48.000036 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8939 00:56:48.003746 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8940 00:56:48.009992 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8941 00:56:48.013380 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8942 00:56:48.016747 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8943 00:56:48.019637 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8944 00:56:48.023704 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8945 00:56:48.029924 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8946 00:56:48.033122 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8947 00:56:48.036536 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8948 00:56:48.037103 ==
8949 00:56:48.040068 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 00:56:48.042957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 00:56:48.046528 ==
8952 00:56:48.047090 DQS Delay:
8953 00:56:48.047468 DQS0 = 0, DQS1 = 0
8954 00:56:48.049603 DQM Delay:
8955 00:56:48.050072 DQM0 = 137, DQM1 = 129
8956 00:56:48.053026 DQ Delay:
8957 00:56:48.056052 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8958 00:56:48.059598 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8959 00:56:48.062789 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8960 00:56:48.066456 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8961 00:56:48.067259
8962 00:56:48.067657
8963 00:56:48.068005 ==
8964 00:56:48.069332 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 00:56:48.072799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 00:56:48.075997 ==
8967 00:56:48.076420
8968 00:56:48.076809
8969 00:56:48.077281 TX Vref Scan disable
8970 00:56:48.078997 == TX Byte 0 ==
8971 00:56:48.082495 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8972 00:56:48.085803 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8973 00:56:48.089361 == TX Byte 1 ==
8974 00:56:48.092575 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8975 00:56:48.096246 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8976 00:56:48.099009 ==
8977 00:56:48.099438 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 00:56:48.105408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 00:56:48.105840 ==
8980 00:56:48.118295
8981 00:56:48.121617 TX Vref early break, caculate TX vref
8982 00:56:48.124980 TX Vref=16, minBit 0, minWin=22, winSum=380
8983 00:56:48.128098 TX Vref=18, minBit 0, minWin=23, winSum=391
8984 00:56:48.131717 TX Vref=20, minBit 5, minWin=23, winSum=395
8985 00:56:48.135044 TX Vref=22, minBit 5, minWin=23, winSum=403
8986 00:56:48.138056 TX Vref=24, minBit 0, minWin=24, winSum=413
8987 00:56:48.144557 TX Vref=26, minBit 0, minWin=24, winSum=417
8988 00:56:48.147981 TX Vref=28, minBit 0, minWin=23, winSum=411
8989 00:56:48.151350 TX Vref=30, minBit 0, minWin=24, winSum=407
8990 00:56:48.154268 TX Vref=32, minBit 0, minWin=23, winSum=404
8991 00:56:48.157356 TX Vref=34, minBit 0, minWin=22, winSum=388
8992 00:56:48.164058 [TxChooseVref] Worse bit 0, Min win 24, Win sum 417, Final Vref 26
8993 00:56:48.164585
8994 00:56:48.167708 Final TX Range 0 Vref 26
8995 00:56:48.168189
8996 00:56:48.168563 ==
8997 00:56:48.170837 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 00:56:48.174045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 00:56:48.174568 ==
9000 00:56:48.174943
9001 00:56:48.175290
9002 00:56:48.177861 TX Vref Scan disable
9003 00:56:48.184088 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
9004 00:56:48.184515 == TX Byte 0 ==
9005 00:56:48.187579 u2DelayCellOfst[0]=22 cells (6 PI)
9006 00:56:48.190686 u2DelayCellOfst[1]=15 cells (4 PI)
9007 00:56:48.194182 u2DelayCellOfst[2]=0 cells (0 PI)
9008 00:56:48.197600 u2DelayCellOfst[3]=7 cells (2 PI)
9009 00:56:48.201104 u2DelayCellOfst[4]=11 cells (3 PI)
9010 00:56:48.204025 u2DelayCellOfst[5]=22 cells (6 PI)
9011 00:56:48.207478 u2DelayCellOfst[6]=18 cells (5 PI)
9012 00:56:48.210789 u2DelayCellOfst[7]=7 cells (2 PI)
9013 00:56:48.214088 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
9014 00:56:48.217581 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
9015 00:56:48.220554 == TX Byte 1 ==
9016 00:56:48.223415 u2DelayCellOfst[8]=0 cells (0 PI)
9017 00:56:48.226835 u2DelayCellOfst[9]=3 cells (1 PI)
9018 00:56:48.227306 u2DelayCellOfst[10]=11 cells (3 PI)
9019 00:56:48.230249 u2DelayCellOfst[11]=3 cells (1 PI)
9020 00:56:48.233659 u2DelayCellOfst[12]=15 cells (4 PI)
9021 00:56:48.237044 u2DelayCellOfst[13]=15 cells (4 PI)
9022 00:56:48.240408 u2DelayCellOfst[14]=15 cells (4 PI)
9023 00:56:48.243444 u2DelayCellOfst[15]=15 cells (4 PI)
9024 00:56:48.249990 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
9025 00:56:48.253087 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9026 00:56:48.253564 DramC Write-DBI on
9027 00:56:48.256350 ==
9028 00:56:48.256819 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 00:56:48.262976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 00:56:48.263449 ==
9031 00:56:48.263819
9032 00:56:48.264164
9033 00:56:48.266249 TX Vref Scan disable
9034 00:56:48.266677 == TX Byte 0 ==
9035 00:56:48.273055 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
9036 00:56:48.273676 == TX Byte 1 ==
9037 00:56:48.276295 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9038 00:56:48.279373 DramC Write-DBI off
9039 00:56:48.279799
9040 00:56:48.280139 [DATLAT]
9041 00:56:48.282640 Freq=1600, CH1 RK1
9042 00:56:48.283065
9043 00:56:48.283402 DATLAT Default: 0xf
9044 00:56:48.285886 0, 0xFFFF, sum = 0
9045 00:56:48.286359 1, 0xFFFF, sum = 0
9046 00:56:48.289642 2, 0xFFFF, sum = 0
9047 00:56:48.290225 3, 0xFFFF, sum = 0
9048 00:56:48.292932 4, 0xFFFF, sum = 0
9049 00:56:48.293468 5, 0xFFFF, sum = 0
9050 00:56:48.295943 6, 0xFFFF, sum = 0
9051 00:56:48.299064 7, 0xFFFF, sum = 0
9052 00:56:48.299499 8, 0xFFFF, sum = 0
9053 00:56:48.302966 9, 0xFFFF, sum = 0
9054 00:56:48.303401 10, 0xFFFF, sum = 0
9055 00:56:48.306207 11, 0xFFFF, sum = 0
9056 00:56:48.306756 12, 0xFFFF, sum = 0
9057 00:56:48.308900 13, 0xFFFF, sum = 0
9058 00:56:48.309288 14, 0x0, sum = 1
9059 00:56:48.312432 15, 0x0, sum = 2
9060 00:56:48.312969 16, 0x0, sum = 3
9061 00:56:48.315864 17, 0x0, sum = 4
9062 00:56:48.316299 best_step = 15
9063 00:56:48.316637
9064 00:56:48.316956 ==
9065 00:56:48.319226 Dram Type= 6, Freq= 0, CH_1, rank 1
9066 00:56:48.322334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9067 00:56:48.325783 ==
9068 00:56:48.326240 RX Vref Scan: 0
9069 00:56:48.326659
9070 00:56:48.329019 RX Vref 0 -> 0, step: 1
9071 00:56:48.329549
9072 00:56:48.332558 RX Delay 11 -> 252, step: 4
9073 00:56:48.335128 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9074 00:56:48.338628 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9075 00:56:48.341985 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9076 00:56:48.348471 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9077 00:56:48.352173 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9078 00:56:48.354941 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9079 00:56:48.358341 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9080 00:56:48.364971 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9081 00:56:48.368121 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9082 00:56:48.371275 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9083 00:56:48.374553 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9084 00:56:48.377670 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9085 00:56:48.384422 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9086 00:56:48.387765 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9087 00:56:48.391100 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9088 00:56:48.394815 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9089 00:56:48.395355 ==
9090 00:56:48.398088 Dram Type= 6, Freq= 0, CH_1, rank 1
9091 00:56:48.404145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9092 00:56:48.404702 ==
9093 00:56:48.405071 DQS Delay:
9094 00:56:48.407752 DQS0 = 0, DQS1 = 0
9095 00:56:48.408320 DQM Delay:
9096 00:56:48.411108 DQM0 = 133, DQM1 = 126
9097 00:56:48.411667 DQ Delay:
9098 00:56:48.414442 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9099 00:56:48.417292 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9100 00:56:48.420790 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9101 00:56:48.424596 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9102 00:56:48.425159
9103 00:56:48.425557
9104 00:56:48.425898
9105 00:56:48.427812 [DramC_TX_OE_Calibration] TA2
9106 00:56:48.430848 Original DQ_B0 (3 6) =30, OEN = 27
9107 00:56:48.434038 Original DQ_B1 (3 6) =30, OEN = 27
9108 00:56:48.437669 24, 0x0, End_B0=24 End_B1=24
9109 00:56:48.440700 25, 0x0, End_B0=25 End_B1=25
9110 00:56:48.441170 26, 0x0, End_B0=26 End_B1=26
9111 00:56:48.443744 27, 0x0, End_B0=27 End_B1=27
9112 00:56:48.447531 28, 0x0, End_B0=28 End_B1=28
9113 00:56:48.451109 29, 0x0, End_B0=29 End_B1=29
9114 00:56:48.451680 30, 0x0, End_B0=30 End_B1=30
9115 00:56:48.454156 31, 0x4141, End_B0=30 End_B1=30
9116 00:56:48.457227 Byte0 end_step=30 best_step=27
9117 00:56:48.460857 Byte1 end_step=30 best_step=27
9118 00:56:48.464096 Byte0 TX OE(2T, 0.5T) = (3, 3)
9119 00:56:48.467380 Byte1 TX OE(2T, 0.5T) = (3, 3)
9120 00:56:48.467849
9121 00:56:48.468224
9122 00:56:48.473489 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
9123 00:56:48.477040 CH1 RK1: MR19=303, MR18=D0B
9124 00:56:48.483541 CH1_RK1: MR19=0x303, MR18=0xD0B, DQSOSC=403, MR23=63, INC=22, DEC=15
9125 00:56:48.487453 [RxdqsGatingPostProcess] freq 1600
9126 00:56:48.490390 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9127 00:56:48.493743 best DQS0 dly(2T, 0.5T) = (1, 1)
9128 00:56:48.496920 best DQS1 dly(2T, 0.5T) = (1, 1)
9129 00:56:48.500103 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9130 00:56:48.503372 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9131 00:56:48.506909 best DQS0 dly(2T, 0.5T) = (1, 1)
9132 00:56:48.510294 best DQS1 dly(2T, 0.5T) = (1, 1)
9133 00:56:48.513602 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9134 00:56:48.516424 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9135 00:56:48.520329 Pre-setting of DQS Precalculation
9136 00:56:48.523410 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9137 00:56:48.533335 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9138 00:56:48.539936 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9139 00:56:48.540509
9140 00:56:48.540879
9141 00:56:48.543140 [Calibration Summary] 3200 Mbps
9142 00:56:48.543607 CH 0, Rank 0
9143 00:56:48.546488 SW Impedance : PASS
9144 00:56:48.547054 DUTY Scan : NO K
9145 00:56:48.550067 ZQ Calibration : PASS
9146 00:56:48.553518 Jitter Meter : NO K
9147 00:56:48.553986 CBT Training : PASS
9148 00:56:48.556004 Write leveling : PASS
9149 00:56:48.559051 RX DQS gating : PASS
9150 00:56:48.559533 RX DQ/DQS(RDDQC) : PASS
9151 00:56:48.562857 TX DQ/DQS : PASS
9152 00:56:48.565949 RX DATLAT : PASS
9153 00:56:48.566414 RX DQ/DQS(Engine): PASS
9154 00:56:48.569233 TX OE : PASS
9155 00:56:48.569656 All Pass.
9156 00:56:48.569987
9157 00:56:48.572824 CH 0, Rank 1
9158 00:56:48.573360 SW Impedance : PASS
9159 00:56:48.576365 DUTY Scan : NO K
9160 00:56:48.579161 ZQ Calibration : PASS
9161 00:56:48.579657 Jitter Meter : NO K
9162 00:56:48.582519 CBT Training : PASS
9163 00:56:48.582937 Write leveling : PASS
9164 00:56:48.585711 RX DQS gating : PASS
9165 00:56:48.589237 RX DQ/DQS(RDDQC) : PASS
9166 00:56:48.589757 TX DQ/DQS : PASS
9167 00:56:48.592920 RX DATLAT : PASS
9168 00:56:48.595897 RX DQ/DQS(Engine): PASS
9169 00:56:48.596576 TX OE : PASS
9170 00:56:48.599275 All Pass.
9171 00:56:48.599691
9172 00:56:48.600020 CH 1, Rank 0
9173 00:56:48.602268 SW Impedance : PASS
9174 00:56:48.602687 DUTY Scan : NO K
9175 00:56:48.605911 ZQ Calibration : PASS
9176 00:56:48.608924 Jitter Meter : NO K
9177 00:56:48.609345 CBT Training : PASS
9178 00:56:48.612547 Write leveling : PASS
9179 00:56:48.616454 RX DQS gating : PASS
9180 00:56:48.616877 RX DQ/DQS(RDDQC) : PASS
9181 00:56:48.618792 TX DQ/DQS : PASS
9182 00:56:48.622402 RX DATLAT : PASS
9183 00:56:48.623044 RX DQ/DQS(Engine): PASS
9184 00:56:48.625533 TX OE : PASS
9185 00:56:48.626231 All Pass.
9186 00:56:48.626853
9187 00:56:48.628560 CH 1, Rank 1
9188 00:56:48.629026 SW Impedance : PASS
9189 00:56:48.632127 DUTY Scan : NO K
9190 00:56:48.635491 ZQ Calibration : PASS
9191 00:56:48.636099 Jitter Meter : NO K
9192 00:56:48.638864 CBT Training : PASS
9193 00:56:48.641934 Write leveling : PASS
9194 00:56:48.642439 RX DQS gating : PASS
9195 00:56:48.645383 RX DQ/DQS(RDDQC) : PASS
9196 00:56:48.645985 TX DQ/DQS : PASS
9197 00:56:48.648529 RX DATLAT : PASS
9198 00:56:48.651778 RX DQ/DQS(Engine): PASS
9199 00:56:48.652244 TX OE : PASS
9200 00:56:48.655006 All Pass.
9201 00:56:48.655468
9202 00:56:48.655833 DramC Write-DBI on
9203 00:56:48.658551 PER_BANK_REFRESH: Hybrid Mode
9204 00:56:48.661695 TX_TRACKING: ON
9205 00:56:48.668514 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9206 00:56:48.678297 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9207 00:56:48.685306 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9208 00:56:48.688333 [FAST_K] Save calibration result to emmc
9209 00:56:48.691465 sync common calibartion params.
9210 00:56:48.691890 sync cbt_mode0:1, 1:1
9211 00:56:48.694772 dram_init: ddr_geometry: 2
9212 00:56:48.698022 dram_init: ddr_geometry: 2
9213 00:56:48.701532 dram_init: ddr_geometry: 2
9214 00:56:48.702110 0:dram_rank_size:100000000
9215 00:56:48.704903 1:dram_rank_size:100000000
9216 00:56:48.711275 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9217 00:56:48.711698 DFS_SHUFFLE_HW_MODE: ON
9218 00:56:48.717690 dramc_set_vcore_voltage set vcore to 725000
9219 00:56:48.718234 Read voltage for 1600, 0
9220 00:56:48.721239 Vio18 = 0
9221 00:56:48.721767 Vcore = 725000
9222 00:56:48.722108 Vdram = 0
9223 00:56:48.724480 Vddq = 0
9224 00:56:48.725062 Vmddr = 0
9225 00:56:48.727918 switch to 3200 Mbps bootup
9226 00:56:48.728387 [DramcRunTimeConfig]
9227 00:56:48.728757 PHYPLL
9228 00:56:48.731032 DPM_CONTROL_AFTERK: ON
9229 00:56:48.734314 PER_BANK_REFRESH: ON
9230 00:56:48.734784 REFRESH_OVERHEAD_REDUCTION: ON
9231 00:56:48.737594 CMD_PICG_NEW_MODE: OFF
9232 00:56:48.741229 XRTWTW_NEW_MODE: ON
9233 00:56:48.741774 XRTRTR_NEW_MODE: ON
9234 00:56:48.744061 TX_TRACKING: ON
9235 00:56:48.744497 RDSEL_TRACKING: OFF
9236 00:56:48.747507 DQS Precalculation for DVFS: ON
9237 00:56:48.747933 RX_TRACKING: OFF
9238 00:56:48.750699 HW_GATING DBG: ON
9239 00:56:48.753802 ZQCS_ENABLE_LP4: ON
9240 00:56:48.754299 RX_PICG_NEW_MODE: ON
9241 00:56:48.757033 TX_PICG_NEW_MODE: ON
9242 00:56:48.757468 ENABLE_RX_DCM_DPHY: ON
9243 00:56:48.760608 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9244 00:56:48.763801 DUMMY_READ_FOR_TRACKING: OFF
9245 00:56:48.767153 !!! SPM_CONTROL_AFTERK: OFF
9246 00:56:48.770272 !!! SPM could not control APHY
9247 00:56:48.770703 IMPEDANCE_TRACKING: ON
9248 00:56:48.773551 TEMP_SENSOR: ON
9249 00:56:48.773976 HW_SAVE_FOR_SR: OFF
9250 00:56:48.777070 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9251 00:56:48.780349 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9252 00:56:48.783944 Read ODT Tracking: ON
9253 00:56:48.787126 Refresh Rate DeBounce: ON
9254 00:56:48.787569 DFS_NO_QUEUE_FLUSH: ON
9255 00:56:48.790242 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9256 00:56:48.793862 ENABLE_DFS_RUNTIME_MRW: OFF
9257 00:56:48.797091 DDR_RESERVE_NEW_MODE: ON
9258 00:56:48.797629 MR_CBT_SWITCH_FREQ: ON
9259 00:56:48.800615 =========================
9260 00:56:48.819134 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9261 00:56:48.822370 dram_init: ddr_geometry: 2
9262 00:56:48.840459 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9263 00:56:48.843477 dram_init: dram init end (result: 0)
9264 00:56:48.849843 DRAM-K: Full calibration passed in 24621 msecs
9265 00:56:48.853538 MRC: failed to locate region type 0.
9266 00:56:48.856671 DRAM rank0 size:0x100000000,
9267 00:56:48.857094 DRAM rank1 size=0x100000000
9268 00:56:48.866362 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9269 00:56:48.873317 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9270 00:56:48.883035 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9271 00:56:48.889839 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9272 00:56:48.890457 DRAM rank0 size:0x100000000,
9273 00:56:48.893172 DRAM rank1 size=0x100000000
9274 00:56:48.893754 CBMEM:
9275 00:56:48.896451 IMD: root @ 0xfffff000 254 entries.
9276 00:56:48.899875 IMD: root @ 0xffffec00 62 entries.
9277 00:56:48.906611 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9278 00:56:48.909583 WARNING: RO_VPD is uninitialized or empty.
9279 00:56:48.912763 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9280 00:56:48.920462 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9281 00:56:48.933831 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9282 00:56:48.944662 BS: romstage times (exec / console): total (unknown) / 24109 ms
9283 00:56:48.945223
9284 00:56:48.945594
9285 00:56:48.954958 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9286 00:56:48.957764 ARM64: Exception handlers installed.
9287 00:56:48.961166 ARM64: Testing exception
9288 00:56:48.964149 ARM64: Done test exception
9289 00:56:48.964590 Enumerating buses...
9290 00:56:48.967679 Show all devs... Before device enumeration.
9291 00:56:48.970551 Root Device: enabled 1
9292 00:56:48.973876 CPU_CLUSTER: 0: enabled 1
9293 00:56:48.974374 CPU: 00: enabled 1
9294 00:56:48.977604 Compare with tree...
9295 00:56:48.978346 Root Device: enabled 1
9296 00:56:48.980844 CPU_CLUSTER: 0: enabled 1
9297 00:56:48.984034 CPU: 00: enabled 1
9298 00:56:48.984504 Root Device scanning...
9299 00:56:48.987358 scan_static_bus for Root Device
9300 00:56:48.990755 CPU_CLUSTER: 0 enabled
9301 00:56:48.994005 scan_static_bus for Root Device done
9302 00:56:48.997077 scan_bus: bus Root Device finished in 8 msecs
9303 00:56:48.997500 done
9304 00:56:49.003882 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9305 00:56:49.007302 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9306 00:56:49.013950 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9307 00:56:49.021221 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9308 00:56:49.021794 Allocating resources...
9309 00:56:49.024050 Reading resources...
9310 00:56:49.027031 Root Device read_resources bus 0 link: 0
9311 00:56:49.030609 DRAM rank0 size:0x100000000,
9312 00:56:49.031169 DRAM rank1 size=0x100000000
9313 00:56:49.037000 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9314 00:56:49.037562 CPU: 00 missing read_resources
9315 00:56:49.043988 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9316 00:56:49.046832 Root Device read_resources bus 0 link: 0 done
9317 00:56:49.050309 Done reading resources.
9318 00:56:49.053473 Show resources in subtree (Root Device)...After reading.
9319 00:56:49.056601 Root Device child on link 0 CPU_CLUSTER: 0
9320 00:56:49.059865 CPU_CLUSTER: 0 child on link 0 CPU: 00
9321 00:56:49.070047 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9322 00:56:49.070689 CPU: 00
9323 00:56:49.076766 Root Device assign_resources, bus 0 link: 0
9324 00:56:49.079698 CPU_CLUSTER: 0 missing set_resources
9325 00:56:49.082918 Root Device assign_resources, bus 0 link: 0 done
9326 00:56:49.083393 Done setting resources.
9327 00:56:49.089924 Show resources in subtree (Root Device)...After assigning values.
9328 00:56:49.092966 Root Device child on link 0 CPU_CLUSTER: 0
9329 00:56:49.096439 CPU_CLUSTER: 0 child on link 0 CPU: 00
9330 00:56:49.105899 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9331 00:56:49.106411 CPU: 00
9332 00:56:49.109154 Done allocating resources.
9333 00:56:49.116231 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9334 00:56:49.116803 Enabling resources...
9335 00:56:49.119349 done.
9336 00:56:49.122494 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9337 00:56:49.125927 Initializing devices...
9338 00:56:49.126551 Root Device init
9339 00:56:49.129209 init hardware done!
9340 00:56:49.129778 0x00000018: ctrlr->caps
9341 00:56:49.132856 52.000 MHz: ctrlr->f_max
9342 00:56:49.135916 0.400 MHz: ctrlr->f_min
9343 00:56:49.136397 0x40ff8080: ctrlr->voltages
9344 00:56:49.139354 sclk: 390625
9345 00:56:49.139957 Bus Width = 1
9346 00:56:49.142631 sclk: 390625
9347 00:56:49.143202 Bus Width = 1
9348 00:56:49.145846 Early init status = 3
9349 00:56:49.149043 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9350 00:56:49.152688 in-header: 03 fc 00 00 01 00 00 00
9351 00:56:49.155572 in-data: 00
9352 00:56:49.158731 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9353 00:56:49.163479 in-header: 03 fd 00 00 00 00 00 00
9354 00:56:49.166973 in-data:
9355 00:56:49.169933 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9356 00:56:49.173566 in-header: 03 fc 00 00 01 00 00 00
9357 00:56:49.176827 in-data: 00
9358 00:56:49.179773 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9359 00:56:49.184555 in-header: 03 fd 00 00 00 00 00 00
9360 00:56:49.187701 in-data:
9361 00:56:49.191509 [SSUSB] Setting up USB HOST controller...
9362 00:56:49.194348 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9363 00:56:49.197948 [SSUSB] phy power-on done.
9364 00:56:49.201189 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9365 00:56:49.207677 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9366 00:56:49.211265 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9367 00:56:49.217734 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9368 00:56:49.224413 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9369 00:56:49.230822 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9370 00:56:49.237806 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9371 00:56:49.243853 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9372 00:56:49.247582 SPM: binary array size = 0x9dc
9373 00:56:49.250870 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9374 00:56:49.257401 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9375 00:56:49.263993 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9376 00:56:49.270669 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9377 00:56:49.273516 configure_display: Starting display init
9378 00:56:49.308101 anx7625_power_on_init: Init interface.
9379 00:56:49.311405 anx7625_disable_pd_protocol: Disabled PD feature.
9380 00:56:49.314900 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9381 00:56:49.342574 anx7625_start_dp_work: Secure OCM version=00
9382 00:56:49.345652 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9383 00:56:49.360569 sp_tx_get_edid_block: EDID Block = 1
9384 00:56:49.463275 Extracted contents:
9385 00:56:49.466454 header: 00 ff ff ff ff ff ff 00
9386 00:56:49.470042 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9387 00:56:49.473300 version: 01 04
9388 00:56:49.475982 basic params: 95 1f 11 78 0a
9389 00:56:49.479206 chroma info: 76 90 94 55 54 90 27 21 50 54
9390 00:56:49.483139 established: 00 00 00
9391 00:56:49.490066 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9392 00:56:49.496584 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9393 00:56:49.499477 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9394 00:56:49.505736 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9395 00:56:49.512445 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9396 00:56:49.515812 extensions: 00
9397 00:56:49.516381 checksum: fb
9398 00:56:49.516760
9399 00:56:49.522458 Manufacturer: IVO Model 57d Serial Number 0
9400 00:56:49.523033 Made week 0 of 2020
9401 00:56:49.525784 EDID version: 1.4
9402 00:56:49.526394 Digital display
9403 00:56:49.528881 6 bits per primary color channel
9404 00:56:49.529463 DisplayPort interface
9405 00:56:49.531926 Maximum image size: 31 cm x 17 cm
9406 00:56:49.535441 Gamma: 220%
9407 00:56:49.536015 Check DPMS levels
9408 00:56:49.542322 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9409 00:56:49.545151 First detailed timing is preferred timing
9410 00:56:49.548769 Established timings supported:
9411 00:56:49.549346 Standard timings supported:
9412 00:56:49.552234 Detailed timings
9413 00:56:49.555211 Hex of detail: 383680a07038204018303c0035ae10000019
9414 00:56:49.561794 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9415 00:56:49.564817 0780 0798 07c8 0820 hborder 0
9416 00:56:49.568462 0438 043b 0447 0458 vborder 0
9417 00:56:49.571622 -hsync -vsync
9418 00:56:49.572099 Did detailed timing
9419 00:56:49.578112 Hex of detail: 000000000000000000000000000000000000
9420 00:56:49.581317 Manufacturer-specified data, tag 0
9421 00:56:49.584825 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9422 00:56:49.587923 ASCII string: InfoVision
9423 00:56:49.591342 Hex of detail: 000000fe00523134304e574635205248200a
9424 00:56:49.594361 ASCII string: R140NWF5 RH
9425 00:56:49.594790 Checksum
9426 00:56:49.598556 Checksum: 0xfb (valid)
9427 00:56:49.601988 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9428 00:56:49.604776 DSI data_rate: 832800000 bps
9429 00:56:49.611427 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9430 00:56:49.614523 anx7625_parse_edid: pixelclock(138800).
9431 00:56:49.617451 hactive(1920), hsync(48), hfp(24), hbp(88)
9432 00:56:49.621410 vactive(1080), vsync(12), vfp(3), vbp(17)
9433 00:56:49.624449 anx7625_dsi_config: config dsi.
9434 00:56:49.631172 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9435 00:56:49.645231 anx7625_dsi_config: success to config DSI
9436 00:56:49.648625 anx7625_dp_start: MIPI phy setup OK.
9437 00:56:49.652209 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9438 00:56:49.655183 mtk_ddp_mode_set invalid vrefresh 60
9439 00:56:49.658368 main_disp_path_setup
9440 00:56:49.658961 ovl_layer_smi_id_en
9441 00:56:49.661732 ovl_layer_smi_id_en
9442 00:56:49.662158 ccorr_config
9443 00:56:49.662580 aal_config
9444 00:56:49.664860 gamma_config
9445 00:56:49.665282 postmask_config
9446 00:56:49.668843 dither_config
9447 00:56:49.671315 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9448 00:56:49.677960 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9449 00:56:49.681953 Root Device init finished in 551 msecs
9450 00:56:49.684889 CPU_CLUSTER: 0 init
9451 00:56:49.691520 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9452 00:56:49.697666 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9453 00:56:49.698130 APU_MBOX 0x190000b0 = 0x10001
9454 00:56:49.701383 APU_MBOX 0x190001b0 = 0x10001
9455 00:56:49.704502 APU_MBOX 0x190005b0 = 0x10001
9456 00:56:49.708178 APU_MBOX 0x190006b0 = 0x10001
9457 00:56:49.714804 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9458 00:56:49.724215 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9459 00:56:49.736418 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9460 00:56:49.742987 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9461 00:56:49.754810 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9462 00:56:49.763908 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9463 00:56:49.767661 CPU_CLUSTER: 0 init finished in 81 msecs
9464 00:56:49.770545 Devices initialized
9465 00:56:49.773832 Show all devs... After init.
9466 00:56:49.774337 Root Device: enabled 1
9467 00:56:49.777147 CPU_CLUSTER: 0: enabled 1
9468 00:56:49.780330 CPU: 00: enabled 1
9469 00:56:49.783730 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9470 00:56:49.786997 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9471 00:56:49.790672 ELOG: NV offset 0x57f000 size 0x1000
9472 00:56:49.797059 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9473 00:56:49.803603 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9474 00:56:49.806782 ELOG: Event(17) added with size 13 at 2024-06-16 00:56:49 UTC
9475 00:56:49.813444 out: cmd=0x121: 03 db 21 01 00 00 00 00
9476 00:56:49.817231 in-header: 03 42 00 00 2c 00 00 00
9477 00:56:49.830051 in-data: fb 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9478 00:56:49.832851 ELOG: Event(A1) added with size 10 at 2024-06-16 00:56:49 UTC
9479 00:56:49.839857 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9480 00:56:49.846541 ELOG: Event(A0) added with size 9 at 2024-06-16 00:56:49 UTC
9481 00:56:49.849891 elog_add_boot_reason: Logged dev mode boot
9482 00:56:49.856504 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9483 00:56:49.856935 Finalize devices...
9484 00:56:49.859694 Devices finalized
9485 00:56:49.862881 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9486 00:56:49.866041 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9487 00:56:49.869575 in-header: 03 07 00 00 08 00 00 00
9488 00:56:49.872842 in-data: aa e4 47 04 13 02 00 00
9489 00:56:49.876637 Chrome EC: UHEPI supported
9490 00:56:49.882888 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9491 00:56:49.886001 in-header: 03 a9 00 00 08 00 00 00
9492 00:56:49.889485 in-data: 84 60 60 08 00 00 00 00
9493 00:56:49.895846 ELOG: Event(91) added with size 10 at 2024-06-16 00:56:49 UTC
9494 00:56:49.899116 Chrome EC: clear events_b mask to 0x0000000020004000
9495 00:56:49.905701 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9496 00:56:49.910065 in-header: 03 fd 00 00 00 00 00 00
9497 00:56:49.913259 in-data:
9498 00:56:49.916396 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9499 00:56:49.919583 Writing coreboot table at 0xffe64000
9500 00:56:49.926394 0. 000000000010a000-0000000000113fff: RAMSTAGE
9501 00:56:49.929753 1. 0000000040000000-00000000400fffff: RAM
9502 00:56:49.932658 2. 0000000040100000-000000004032afff: RAMSTAGE
9503 00:56:49.936912 3. 000000004032b000-00000000545fffff: RAM
9504 00:56:49.939359 4. 0000000054600000-000000005465ffff: BL31
9505 00:56:49.946252 5. 0000000054660000-00000000ffe63fff: RAM
9506 00:56:49.949101 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9507 00:56:49.952687 7. 0000000100000000-000000023fffffff: RAM
9508 00:56:49.955990 Passing 5 GPIOs to payload:
9509 00:56:49.959571 NAME | PORT | POLARITY | VALUE
9510 00:56:49.966056 EC in RW | 0x000000aa | low | undefined
9511 00:56:49.969391 EC interrupt | 0x00000005 | low | undefined
9512 00:56:49.976119 TPM interrupt | 0x000000ab | high | undefined
9513 00:56:49.979134 SD card detect | 0x00000011 | high | undefined
9514 00:56:49.985682 speaker enable | 0x00000093 | high | undefined
9515 00:56:49.988855 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9516 00:56:49.992552 in-header: 03 f9 00 00 02 00 00 00
9517 00:56:49.992980 in-data: 02 00
9518 00:56:49.995808 ADC[4]: Raw value=900813 ID=7
9519 00:56:49.998664 ADC[3]: Raw value=214021 ID=1
9520 00:56:49.999089 RAM Code: 0x71
9521 00:56:50.001991 ADC[6]: Raw value=75036 ID=0
9522 00:56:50.005698 ADC[5]: Raw value=213282 ID=1
9523 00:56:50.006090 SKU Code: 0x1
9524 00:56:50.012305 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9c1f
9525 00:56:50.015730 coreboot table: 964 bytes.
9526 00:56:50.018670 IMD ROOT 0. 0xfffff000 0x00001000
9527 00:56:50.021767 IMD SMALL 1. 0xffffe000 0x00001000
9528 00:56:50.025101 RO MCACHE 2. 0xffffc000 0x00001104
9529 00:56:50.028683 CONSOLE 3. 0xfff7c000 0x00080000
9530 00:56:50.031708 FMAP 4. 0xfff7b000 0x00000452
9531 00:56:50.035024 TIME STAMP 5. 0xfff7a000 0x00000910
9532 00:56:50.038423 VBOOT WORK 6. 0xfff66000 0x00014000
9533 00:56:50.041553 RAMOOPS 7. 0xffe66000 0x00100000
9534 00:56:50.045484 COREBOOT 8. 0xffe64000 0x00002000
9535 00:56:50.045912 IMD small region:
9536 00:56:50.048560 IMD ROOT 0. 0xffffec00 0x00000400
9537 00:56:50.051674 VPD 1. 0xffffeb80 0x0000006c
9538 00:56:50.054884 MMC STATUS 2. 0xffffeb60 0x00000004
9539 00:56:50.061666 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9540 00:56:50.068194 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9541 00:56:50.107402 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9542 00:56:50.110070 Checking segment from ROM address 0x40100000
9543 00:56:50.113418 Checking segment from ROM address 0x4010001c
9544 00:56:50.120408 Loading segment from ROM address 0x40100000
9545 00:56:50.120839 code (compression=0)
9546 00:56:50.130557 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9547 00:56:50.136763 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9548 00:56:50.137195 it's not compressed!
9549 00:56:50.143580 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9550 00:56:50.149948 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9551 00:56:50.167564 Loading segment from ROM address 0x4010001c
9552 00:56:50.168032 Entry Point 0x80000000
9553 00:56:50.170715 Loaded segments
9554 00:56:50.173913 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9555 00:56:50.180827 Jumping to boot code at 0x80000000(0xffe64000)
9556 00:56:50.187357 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9557 00:56:50.193463 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9558 00:56:50.201860 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9559 00:56:50.205048 Checking segment from ROM address 0x40100000
9560 00:56:50.208145 Checking segment from ROM address 0x4010001c
9561 00:56:50.215123 Loading segment from ROM address 0x40100000
9562 00:56:50.215264 code (compression=1)
9563 00:56:50.221442 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9564 00:56:50.231243 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9565 00:56:50.231406 using LZMA
9566 00:56:50.240405 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9567 00:56:50.246524 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9568 00:56:50.250034 Loading segment from ROM address 0x4010001c
9569 00:56:50.250144 Entry Point 0x54601000
9570 00:56:50.253154 Loaded segments
9571 00:56:50.256757 NOTICE: MT8192 bl31_setup
9572 00:56:50.263468 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9573 00:56:50.267168 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9574 00:56:50.270110 WARNING: region 0:
9575 00:56:50.273877 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9576 00:56:50.274042 WARNING: region 1:
9577 00:56:50.280351 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9578 00:56:50.283434 WARNING: region 2:
9579 00:56:50.286955 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9580 00:56:50.290339 WARNING: region 3:
9581 00:56:50.296996 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9582 00:56:50.297436 WARNING: region 4:
9583 00:56:50.303670 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9584 00:56:50.304102 WARNING: region 5:
9585 00:56:50.307163 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9586 00:56:50.309863 WARNING: region 6:
9587 00:56:50.313789 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9588 00:56:50.316482 WARNING: region 7:
9589 00:56:50.320198 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9590 00:56:50.326697 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9591 00:56:50.330119 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9592 00:56:50.336402 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9593 00:56:50.339756 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9594 00:56:50.343106 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9595 00:56:50.349237 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9596 00:56:50.352647 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9597 00:56:50.359093 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9598 00:56:50.362332 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9599 00:56:50.365644 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9600 00:56:50.371873 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9601 00:56:50.375582 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9602 00:56:50.382677 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9603 00:56:50.385858 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9604 00:56:50.389145 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9605 00:56:50.395609 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9606 00:56:50.398809 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9607 00:56:50.402263 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9608 00:56:50.408916 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9609 00:56:50.412506 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9610 00:56:50.418767 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9611 00:56:50.421925 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9612 00:56:50.425215 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9613 00:56:50.431723 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9614 00:56:50.435158 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9615 00:56:50.442042 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9616 00:56:50.445241 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9617 00:56:50.448264 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9618 00:56:50.455284 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9619 00:56:50.458631 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9620 00:56:50.465027 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9621 00:56:50.468026 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9622 00:56:50.471160 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9623 00:56:50.478089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9624 00:56:50.481266 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9625 00:56:50.484518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9626 00:56:50.488165 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9627 00:56:50.494585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9628 00:56:50.498332 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9629 00:56:50.501213 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9630 00:56:50.504562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9631 00:56:50.511842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9632 00:56:50.514308 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9633 00:56:50.517719 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9634 00:56:50.520859 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9635 00:56:50.527639 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9636 00:56:50.531088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9637 00:56:50.534224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9638 00:56:50.540771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9639 00:56:50.544223 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9640 00:56:50.550789 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9641 00:56:50.553959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9642 00:56:50.557336 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9643 00:56:50.563750 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9644 00:56:50.567065 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9645 00:56:50.573775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9646 00:56:50.577170 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9647 00:56:50.584000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9648 00:56:50.586822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9649 00:56:50.593652 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9650 00:56:50.596934 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9651 00:56:50.600421 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9652 00:56:50.606675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9653 00:56:50.610005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9654 00:56:50.617205 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9655 00:56:50.619900 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9656 00:56:50.626683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9657 00:56:50.630275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9658 00:56:50.636377 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9659 00:56:50.639706 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9660 00:56:50.643266 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9661 00:56:50.649791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9662 00:56:50.653705 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9663 00:56:50.659775 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9664 00:56:50.663024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9665 00:56:50.669561 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9666 00:56:50.672987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9667 00:56:50.679367 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9668 00:56:50.682790 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9669 00:56:50.686108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9670 00:56:50.693317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9671 00:56:50.695906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9672 00:56:50.702961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9673 00:56:50.706205 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9674 00:56:50.712480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9675 00:56:50.715978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9676 00:56:50.722815 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9677 00:56:50.725951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9678 00:56:50.729034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9679 00:56:50.736033 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9680 00:56:50.738814 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9681 00:56:50.745632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9682 00:56:50.748916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9683 00:56:50.755447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9684 00:56:50.758663 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9685 00:56:50.765119 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9686 00:56:50.768397 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9687 00:56:50.771908 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9688 00:56:50.775045 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9689 00:56:50.781519 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9690 00:56:50.785428 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9691 00:56:50.788269 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9692 00:56:50.794929 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9693 00:56:50.798233 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9694 00:56:50.805210 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9695 00:56:50.808504 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9696 00:56:50.811579 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9697 00:56:50.818222 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9698 00:56:50.821027 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9699 00:56:50.828325 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9700 00:56:50.831613 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9701 00:56:50.834763 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9702 00:56:50.841128 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9703 00:56:50.844738 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9704 00:56:50.851235 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9705 00:56:50.854231 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9706 00:56:50.857536 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9707 00:56:50.863923 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9708 00:56:50.867366 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9709 00:56:50.870972 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9710 00:56:50.877402 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9711 00:56:50.880732 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9712 00:56:50.883924 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9713 00:56:50.887080 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9714 00:56:50.893959 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9715 00:56:50.897315 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9716 00:56:50.903508 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9717 00:56:50.906787 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9718 00:56:50.910579 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9719 00:56:50.916930 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9720 00:56:50.920345 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9721 00:56:50.926938 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9722 00:56:50.930721 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9723 00:56:50.933351 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9724 00:56:50.939956 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9725 00:56:50.943336 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9726 00:56:50.949729 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9727 00:56:50.953241 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9728 00:56:50.956408 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9729 00:56:50.963338 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9730 00:56:50.966483 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9731 00:56:50.972789 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9732 00:56:50.976176 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9733 00:56:50.979498 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9734 00:56:50.986052 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9735 00:56:50.989975 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9736 00:56:50.992937 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9737 00:56:50.999587 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9738 00:56:51.002672 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9739 00:56:51.009292 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9740 00:56:51.012490 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9741 00:56:51.015842 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9742 00:56:51.022663 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9743 00:56:51.025965 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9744 00:56:51.033097 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9745 00:56:51.036007 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9746 00:56:51.039114 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9747 00:56:51.046218 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9748 00:56:51.049468 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9749 00:56:51.056311 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9750 00:56:51.059111 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9751 00:56:51.062589 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9752 00:56:51.069312 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9753 00:56:51.072391 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9754 00:56:51.079286 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9755 00:56:51.082357 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9756 00:56:51.085613 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9757 00:56:51.091932 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9758 00:56:51.095573 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9759 00:56:51.102379 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9760 00:56:51.105448 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9761 00:56:51.108951 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9762 00:56:51.115293 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9763 00:56:51.118946 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9764 00:56:51.125151 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9765 00:56:51.128513 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9766 00:56:51.131914 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9767 00:56:51.138586 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9768 00:56:51.141886 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9769 00:56:51.148373 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9770 00:56:51.151314 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9771 00:56:51.154898 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9772 00:56:51.161889 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9773 00:56:51.164893 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9774 00:56:51.171087 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9775 00:56:51.174390 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9776 00:56:51.177770 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9777 00:56:51.184398 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9778 00:56:51.187588 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9779 00:56:51.194330 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9780 00:56:51.197496 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9781 00:56:51.204227 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9782 00:56:51.207536 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9783 00:56:51.210805 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9784 00:56:51.217142 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9785 00:56:51.220453 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9786 00:56:51.227122 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9787 00:56:51.230750 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9788 00:56:51.237171 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9789 00:56:51.240876 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9790 00:56:51.243563 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9791 00:56:51.250319 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9792 00:56:51.253452 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9793 00:56:51.259955 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9794 00:56:51.263426 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9795 00:56:51.269877 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9796 00:56:51.273189 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9797 00:56:51.276457 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9798 00:56:51.282954 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9799 00:56:51.286833 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9800 00:56:51.293031 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9801 00:56:51.296740 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9802 00:56:51.303050 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9803 00:56:51.306076 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9804 00:56:51.309544 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9805 00:56:51.316018 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9806 00:56:51.319352 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9807 00:56:51.326361 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9808 00:56:51.329439 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9809 00:56:51.335688 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9810 00:56:51.339335 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9811 00:56:51.342357 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9812 00:56:51.349077 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9813 00:56:51.352738 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9814 00:56:51.359009 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9815 00:56:51.362543 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9816 00:56:51.365672 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9817 00:56:51.372378 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9818 00:56:51.375936 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9819 00:56:51.378682 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9820 00:56:51.385450 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9821 00:56:51.388646 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9822 00:56:51.392562 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9823 00:56:51.395490 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9824 00:56:51.402300 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9825 00:56:51.405890 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9826 00:56:51.412121 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9827 00:56:51.415262 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9828 00:56:51.418857 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9829 00:56:51.425298 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9830 00:56:51.428769 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9831 00:56:51.432139 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9832 00:56:51.438869 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9833 00:56:51.441711 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9834 00:56:51.448463 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9835 00:56:51.451912 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9836 00:56:51.455380 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9837 00:56:51.461977 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9838 00:56:51.464847 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9839 00:56:51.467881 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9840 00:56:51.474844 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9841 00:56:51.477869 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9842 00:56:51.484680 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9843 00:56:51.487709 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9844 00:56:51.491463 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9845 00:56:51.498009 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9846 00:56:51.501170 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9847 00:56:51.507671 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9848 00:56:51.511387 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9849 00:56:51.514057 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9850 00:56:51.520685 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9851 00:56:51.524303 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9852 00:56:51.527687 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9853 00:56:51.534444 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9854 00:56:51.537399 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9855 00:56:51.540545 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9856 00:56:51.547269 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9857 00:56:51.550967 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9858 00:56:51.554243 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9859 00:56:51.561075 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9860 00:56:51.563764 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9861 00:56:51.567473 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9862 00:56:51.570512 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9863 00:56:51.573727 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9864 00:56:51.580746 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9865 00:56:51.583650 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9866 00:56:51.586731 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9867 00:56:51.593687 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9868 00:56:51.597311 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9869 00:56:51.599887 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9870 00:56:51.606870 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9871 00:56:51.609954 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9872 00:56:51.613437 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9873 00:56:51.620547 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9874 00:56:51.623481 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9875 00:56:51.626653 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9876 00:56:51.633235 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9877 00:56:51.636241 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9878 00:56:51.643001 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9879 00:56:51.646626 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9880 00:56:51.653441 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9881 00:56:51.656873 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9882 00:56:51.659708 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9883 00:56:51.666578 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9884 00:56:51.669560 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9885 00:56:51.676251 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9886 00:56:51.679860 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9887 00:56:51.682837 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9888 00:56:51.689485 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9889 00:56:51.692854 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9890 00:56:51.699846 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9891 00:56:51.702677 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9892 00:56:51.709485 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9893 00:56:51.712689 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9894 00:56:51.715705 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9895 00:56:51.722294 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9896 00:56:51.726134 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9897 00:56:51.732288 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9898 00:56:51.735646 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9899 00:56:51.738640 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9900 00:56:51.745339 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9901 00:56:51.748979 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9902 00:56:51.755931 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9903 00:56:51.759305 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9904 00:56:51.762055 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9905 00:56:51.768449 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9906 00:56:51.772435 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9907 00:56:51.778915 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9908 00:56:51.782109 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9909 00:56:51.788610 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9910 00:56:51.791972 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9911 00:56:51.795444 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9912 00:56:51.802320 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9913 00:56:51.805540 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9914 00:56:51.811735 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9915 00:56:51.815417 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9916 00:56:51.821546 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9917 00:56:51.824808 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9918 00:56:51.828375 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9919 00:56:51.835089 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9920 00:56:51.838303 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9921 00:56:51.844664 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9922 00:56:51.848143 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9923 00:56:51.851431 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9924 00:56:51.857885 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9925 00:56:51.861298 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9926 00:56:51.867970 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9927 00:56:51.871343 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9928 00:56:51.874404 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9929 00:56:51.880824 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9930 00:56:51.884391 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9931 00:56:51.891391 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9932 00:56:51.894380 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9933 00:56:51.901094 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9934 00:56:51.904327 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9935 00:56:51.907733 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9936 00:56:51.914145 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9937 00:56:51.917291 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9938 00:56:51.923855 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9939 00:56:51.927956 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9940 00:56:51.930631 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9941 00:56:51.937254 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9942 00:56:51.940791 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9943 00:56:51.947098 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9944 00:56:51.950883 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9945 00:56:51.957553 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9946 00:56:51.960461 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9947 00:56:51.963943 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9948 00:56:51.969949 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9949 00:56:51.973595 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9950 00:56:51.980561 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9951 00:56:51.983446 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9952 00:56:51.990496 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9953 00:56:51.993419 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9954 00:56:52.000301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9955 00:56:52.003749 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9956 00:56:52.006858 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9957 00:56:52.013018 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9958 00:56:52.016398 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9959 00:56:52.023127 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9960 00:56:52.026728 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9961 00:56:52.033368 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9962 00:56:52.036257 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9963 00:56:52.039496 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9964 00:56:52.046446 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9965 00:56:52.049856 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9966 00:56:52.056139 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9967 00:56:52.059764 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9968 00:56:52.066260 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9969 00:56:52.069474 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9970 00:56:52.076412 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9971 00:56:52.079525 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9972 00:56:52.082975 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9973 00:56:52.089314 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9974 00:56:52.093110 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9975 00:56:52.099765 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9976 00:56:52.102350 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9977 00:56:52.109413 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9978 00:56:52.112218 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9979 00:56:52.119059 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9980 00:56:52.122105 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9981 00:56:52.125877 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9982 00:56:52.132071 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9983 00:56:52.135351 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9984 00:56:52.142345 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9985 00:56:52.145276 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9986 00:56:52.151908 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9987 00:56:52.155197 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9988 00:56:52.162143 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9989 00:56:52.164914 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9990 00:56:52.168591 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9991 00:56:52.175171 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9992 00:56:52.178271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9993 00:56:52.184819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9994 00:56:52.188344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9995 00:56:52.194862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9996 00:56:52.198381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9997 00:56:52.201863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9998 00:56:52.208573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9999 00:56:52.211280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10000 00:56:52.218058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10001 00:56:52.221565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10002 00:56:52.227959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10003 00:56:52.231556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10004 00:56:52.237863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10005 00:56:52.240793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10006 00:56:52.247510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10007 00:56:52.251089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10008 00:56:52.257851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10009 00:56:52.260727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10010 00:56:52.267295 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10011 00:56:52.270539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10012 00:56:52.277476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10013 00:56:52.280442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10014 00:56:52.287017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10015 00:56:52.290661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10016 00:56:52.297014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10017 00:56:52.300086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10018 00:56:52.306609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10019 00:56:52.309928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10020 00:56:52.316648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10021 00:56:52.319695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10022 00:56:52.326660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10023 00:56:52.330248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10024 00:56:52.336543 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10025 00:56:52.336816 INFO: [APUAPC] vio 0
10026 00:56:52.343630 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10027 00:56:52.346951 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10028 00:56:52.350186 INFO: [APUAPC] D0_APC_0: 0x400510
10029 00:56:52.353698 INFO: [APUAPC] D0_APC_1: 0x0
10030 00:56:52.357081 INFO: [APUAPC] D0_APC_2: 0x1540
10031 00:56:52.360606 INFO: [APUAPC] D0_APC_3: 0x0
10032 00:56:52.363972 INFO: [APUAPC] D1_APC_0: 0xffffffff
10033 00:56:52.367326 INFO: [APUAPC] D1_APC_1: 0xffffffff
10034 00:56:52.370279 INFO: [APUAPC] D1_APC_2: 0x3fffff
10035 00:56:52.373479 INFO: [APUAPC] D1_APC_3: 0x0
10036 00:56:52.377011 INFO: [APUAPC] D2_APC_0: 0xffffffff
10037 00:56:52.380017 INFO: [APUAPC] D2_APC_1: 0xffffffff
10038 00:56:52.383750 INFO: [APUAPC] D2_APC_2: 0x3fffff
10039 00:56:52.386960 INFO: [APUAPC] D2_APC_3: 0x0
10040 00:56:52.390737 INFO: [APUAPC] D3_APC_0: 0xffffffff
10041 00:56:52.393902 INFO: [APUAPC] D3_APC_1: 0xffffffff
10042 00:56:52.396910 INFO: [APUAPC] D3_APC_2: 0x3fffff
10043 00:56:52.399946 INFO: [APUAPC] D3_APC_3: 0x0
10044 00:56:52.403634 INFO: [APUAPC] D4_APC_0: 0xffffffff
10045 00:56:52.406843 INFO: [APUAPC] D4_APC_1: 0xffffffff
10046 00:56:52.410151 INFO: [APUAPC] D4_APC_2: 0x3fffff
10047 00:56:52.413532 INFO: [APUAPC] D4_APC_3: 0x0
10048 00:56:52.416808 INFO: [APUAPC] D5_APC_0: 0xffffffff
10049 00:56:52.420148 INFO: [APUAPC] D5_APC_1: 0xffffffff
10050 00:56:52.423320 INFO: [APUAPC] D5_APC_2: 0x3fffff
10051 00:56:52.423806 INFO: [APUAPC] D5_APC_3: 0x0
10052 00:56:52.429812 INFO: [APUAPC] D6_APC_0: 0xffffffff
10053 00:56:52.433110 INFO: [APUAPC] D6_APC_1: 0xffffffff
10054 00:56:52.436103 INFO: [APUAPC] D6_APC_2: 0x3fffff
10055 00:56:52.436324 INFO: [APUAPC] D6_APC_3: 0x0
10056 00:56:52.439631 INFO: [APUAPC] D7_APC_0: 0xffffffff
10057 00:56:52.442813 INFO: [APUAPC] D7_APC_1: 0xffffffff
10058 00:56:52.446073 INFO: [APUAPC] D7_APC_2: 0x3fffff
10059 00:56:52.449675 INFO: [APUAPC] D7_APC_3: 0x0
10060 00:56:52.452675 INFO: [APUAPC] D8_APC_0: 0xffffffff
10061 00:56:52.456122 INFO: [APUAPC] D8_APC_1: 0xffffffff
10062 00:56:52.459455 INFO: [APUAPC] D8_APC_2: 0x3fffff
10063 00:56:52.462967 INFO: [APUAPC] D8_APC_3: 0x0
10064 00:56:52.466145 INFO: [APUAPC] D9_APC_0: 0xffffffff
10065 00:56:52.469359 INFO: [APUAPC] D9_APC_1: 0xffffffff
10066 00:56:52.472689 INFO: [APUAPC] D9_APC_2: 0x3fffff
10067 00:56:52.475793 INFO: [APUAPC] D9_APC_3: 0x0
10068 00:56:52.479254 INFO: [APUAPC] D10_APC_0: 0xffffffff
10069 00:56:52.482628 INFO: [APUAPC] D10_APC_1: 0xffffffff
10070 00:56:52.486050 INFO: [APUAPC] D10_APC_2: 0x3fffff
10071 00:56:52.489150 INFO: [APUAPC] D10_APC_3: 0x0
10072 00:56:52.492376 INFO: [APUAPC] D11_APC_0: 0xffffffff
10073 00:56:52.495702 INFO: [APUAPC] D11_APC_1: 0xffffffff
10074 00:56:52.499028 INFO: [APUAPC] D11_APC_2: 0x3fffff
10075 00:56:52.502772 INFO: [APUAPC] D11_APC_3: 0x0
10076 00:56:52.506035 INFO: [APUAPC] D12_APC_0: 0xffffffff
10077 00:56:52.509220 INFO: [APUAPC] D12_APC_1: 0xffffffff
10078 00:56:52.512499 INFO: [APUAPC] D12_APC_2: 0x3fffff
10079 00:56:52.516167 INFO: [APUAPC] D12_APC_3: 0x0
10080 00:56:52.519227 INFO: [APUAPC] D13_APC_0: 0xffffffff
10081 00:56:52.522627 INFO: [APUAPC] D13_APC_1: 0xffffffff
10082 00:56:52.525967 INFO: [APUAPC] D13_APC_2: 0x3fffff
10083 00:56:52.529148 INFO: [APUAPC] D13_APC_3: 0x0
10084 00:56:52.532464 INFO: [APUAPC] D14_APC_0: 0xffffffff
10085 00:56:52.538689 INFO: [APUAPC] D14_APC_1: 0xffffffff
10086 00:56:52.541835 INFO: [APUAPC] D14_APC_2: 0x3fffff
10087 00:56:52.542325 INFO: [APUAPC] D14_APC_3: 0x0
10088 00:56:52.549274 INFO: [APUAPC] D15_APC_0: 0xffffffff
10089 00:56:52.551984 INFO: [APUAPC] D15_APC_1: 0xffffffff
10090 00:56:52.555183 INFO: [APUAPC] D15_APC_2: 0x3fffff
10091 00:56:52.558393 INFO: [APUAPC] D15_APC_3: 0x0
10092 00:56:52.558828 INFO: [APUAPC] APC_CON: 0x4
10093 00:56:52.561569 INFO: [NOCDAPC] D0_APC_0: 0x0
10094 00:56:52.565135 INFO: [NOCDAPC] D0_APC_1: 0x0
10095 00:56:52.568699 INFO: [NOCDAPC] D1_APC_0: 0x0
10096 00:56:52.571790 INFO: [NOCDAPC] D1_APC_1: 0xfff
10097 00:56:52.575439 INFO: [NOCDAPC] D2_APC_0: 0x0
10098 00:56:52.578239 INFO: [NOCDAPC] D2_APC_1: 0xfff
10099 00:56:52.581500 INFO: [NOCDAPC] D3_APC_0: 0x0
10100 00:56:52.585157 INFO: [NOCDAPC] D3_APC_1: 0xfff
10101 00:56:52.585596 INFO: [NOCDAPC] D4_APC_0: 0x0
10102 00:56:52.588448 INFO: [NOCDAPC] D4_APC_1: 0xfff
10103 00:56:52.592073 INFO: [NOCDAPC] D5_APC_0: 0x0
10104 00:56:52.595155 INFO: [NOCDAPC] D5_APC_1: 0xfff
10105 00:56:52.598428 INFO: [NOCDAPC] D6_APC_0: 0x0
10106 00:56:52.601704 INFO: [NOCDAPC] D6_APC_1: 0xfff
10107 00:56:52.604993 INFO: [NOCDAPC] D7_APC_0: 0x0
10108 00:56:52.609038 INFO: [NOCDAPC] D7_APC_1: 0xfff
10109 00:56:52.611620 INFO: [NOCDAPC] D8_APC_0: 0x0
10110 00:56:52.614746 INFO: [NOCDAPC] D8_APC_1: 0xfff
10111 00:56:52.618291 INFO: [NOCDAPC] D9_APC_0: 0x0
10112 00:56:52.621225 INFO: [NOCDAPC] D9_APC_1: 0xfff
10113 00:56:52.621662 INFO: [NOCDAPC] D10_APC_0: 0x0
10114 00:56:52.624663 INFO: [NOCDAPC] D10_APC_1: 0xfff
10115 00:56:52.628143 INFO: [NOCDAPC] D11_APC_0: 0x0
10116 00:56:52.631149 INFO: [NOCDAPC] D11_APC_1: 0xfff
10117 00:56:52.634560 INFO: [NOCDAPC] D12_APC_0: 0x0
10118 00:56:52.637710 INFO: [NOCDAPC] D12_APC_1: 0xfff
10119 00:56:52.641421 INFO: [NOCDAPC] D13_APC_0: 0x0
10120 00:56:52.644652 INFO: [NOCDAPC] D13_APC_1: 0xfff
10121 00:56:52.647692 INFO: [NOCDAPC] D14_APC_0: 0x0
10122 00:56:52.651038 INFO: [NOCDAPC] D14_APC_1: 0xfff
10123 00:56:52.654282 INFO: [NOCDAPC] D15_APC_0: 0x0
10124 00:56:52.658133 INFO: [NOCDAPC] D15_APC_1: 0xfff
10125 00:56:52.661160 INFO: [NOCDAPC] APC_CON: 0x4
10126 00:56:52.664444 INFO: [APUAPC] set_apusys_apc done
10127 00:56:52.667958 INFO: [DEVAPC] devapc_init done
10128 00:56:52.670967 INFO: GICv3 without legacy support detected.
10129 00:56:52.674232 INFO: ARM GICv3 driver initialized in EL3
10130 00:56:52.677954 INFO: Maximum SPI INTID supported: 639
10131 00:56:52.680766 INFO: BL31: Initializing runtime services
10132 00:56:52.687917 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10133 00:56:52.690719 INFO: SPM: enable CPC mode
10134 00:56:52.698052 INFO: mcdi ready for mcusys-off-idle and system suspend
10135 00:56:52.700794 INFO: BL31: Preparing for EL3 exit to normal world
10136 00:56:52.704471 INFO: Entry point address = 0x80000000
10137 00:56:52.707748 INFO: SPSR = 0x8
10138 00:56:52.712211
10139 00:56:52.712734
10140 00:56:52.713070
10141 00:56:52.715534 Starting depthcharge on Spherion...
10142 00:56:52.715956
10143 00:56:52.716287 Wipe memory regions:
10144 00:56:52.716595
10145 00:56:52.718844 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10146 00:56:52.719363 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10147 00:56:52.719771 Setting prompt string to ['asurada:']
10148 00:56:52.720183 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10149 00:56:52.720833 [0x00000040000000, 0x00000054600000)
10150 00:56:52.841085
10151 00:56:52.841646 [0x00000054660000, 0x00000080000000)
10152 00:56:53.101845
10153 00:56:53.102462 [0x000000821a7280, 0x000000ffe64000)
10154 00:56:53.846832
10155 00:56:53.847394 [0x00000100000000, 0x00000240000000)
10156 00:56:55.737246
10157 00:56:55.740148 Initializing XHCI USB controller at 0x11200000.
10158 00:56:56.778422
10159 00:56:56.781926 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10160 00:56:56.782582
10161 00:56:56.782967
10162 00:56:56.783819 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10164 00:56:56.885215 asurada: tftpboot 192.168.201.1 14368594/tftp-deploy-t_vao4_5/kernel/image.itb 14368594/tftp-deploy-t_vao4_5/kernel/cmdline
10165 00:56:56.885920 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10166 00:56:56.886419 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10167 00:56:56.890946 tftpboot 192.168.201.1 14368594/tftp-deploy-t_vao4_5/kernel/image.itp-deploy-t_vao4_5/kernel/cmdline
10168 00:56:56.891418
10169 00:56:56.891781 Waiting for link
10170 00:56:57.049333
10171 00:56:57.049898 R8152: Initializing
10172 00:56:57.050321
10173 00:56:57.052618 Version 6 (ocp_data = 5c30)
10174 00:56:57.053089
10175 00:56:57.055768 R8152: Done initializing
10176 00:56:57.056235
10177 00:56:57.056600 Adding net device
10178 00:56:58.957751
10179 00:56:58.958379 done.
10180 00:56:58.958870
10181 00:56:58.959321 MAC: 00:e0:4c:68:02:81
10182 00:56:58.959807
10183 00:56:58.960911 Sending DHCP discover... done.
10184 00:56:58.961383
10185 00:57:11.007761 Waiting for reply... R8152: Bulk read error 0xffffffbf
10186 00:57:11.008339
10187 00:57:11.011065 Receive failed.
10188 00:57:11.011537
10189 00:57:11.011908 done.
10190 00:57:11.012285
10191 00:57:11.014367 Sending DHCP request... done.
10192 00:57:11.014836
10193 00:57:11.017523 Waiting for reply... done.
10194 00:57:11.018004
10195 00:57:11.021228 My ip is 192.168.201.14
10196 00:57:11.021650
10197 00:57:11.024237 The DHCP server ip is 192.168.201.1
10198 00:57:11.024815
10199 00:57:11.027459 TFTP server IP predefined by user: 192.168.201.1
10200 00:57:11.027889
10201 00:57:11.034284 Bootfile predefined by user: 14368594/tftp-deploy-t_vao4_5/kernel/image.itb
10202 00:57:11.034821
10203 00:57:11.037761 Sending tftp read request... done.
10204 00:57:11.038402
10205 00:57:11.045260 Waiting for the transfer...
10206 00:57:11.045687
10207 00:57:11.746999 00000000 ################################################################
10208 00:57:11.747567
10209 00:57:12.432563 00080000 ################################################################
10210 00:57:12.433103
10211 00:57:13.140109 00100000 ################################################################
10212 00:57:13.140656
10213 00:57:13.845131 00180000 ################################################################
10214 00:57:13.845708
10215 00:57:14.550885 00200000 ################################################################
10216 00:57:14.551460
10217 00:57:15.262963 00280000 ################################################################
10218 00:57:15.263521
10219 00:57:15.978128 00300000 ################################################################
10220 00:57:15.978705
10221 00:57:16.685739 00380000 ################################################################
10222 00:57:16.686322
10223 00:57:17.374034 00400000 ################################################################
10224 00:57:17.374676
10225 00:57:18.066975 00480000 ################################################################
10226 00:57:18.067523
10227 00:57:18.770022 00500000 ################################################################
10228 00:57:18.770720
10229 00:57:19.464531 00580000 ################################################################
10230 00:57:19.465138
10231 00:57:20.177090 00600000 ################################################################
10232 00:57:20.177634
10233 00:57:20.863273 00680000 ################################################################
10234 00:57:20.863893
10235 00:57:21.540485 00700000 ################################################################
10236 00:57:21.541012
10237 00:57:22.246189 00780000 ################################################################
10238 00:57:22.246737
10239 00:57:22.927599 00800000 ################################################################
10240 00:57:22.928135
10241 00:57:23.631650 00880000 ################################################################
10242 00:57:23.632216
10243 00:57:24.330144 00900000 ################################################################
10244 00:57:24.330705
10245 00:57:25.048491 00980000 ################################################################
10246 00:57:25.049009
10247 00:57:25.759521 00a00000 ################################################################
10248 00:57:25.760041
10249 00:57:26.472361 00a80000 ################################################################
10250 00:57:26.472898
10251 00:57:27.168294 00b00000 ################################################################
10252 00:57:27.168820
10253 00:57:27.874512 00b80000 ################################################################
10254 00:57:27.875058
10255 00:57:28.576856 00c00000 ################################################################
10256 00:57:28.577379
10257 00:57:29.285067 00c80000 ################################################################
10258 00:57:29.285643
10259 00:57:29.991609 00d00000 ################################################################
10260 00:57:29.992154
10261 00:57:30.693425 00d80000 ################################################################
10262 00:57:30.694121
10263 00:57:31.402109 00e00000 ################################################################
10264 00:57:31.402810
10265 00:57:32.100439 00e80000 ################################################################
10266 00:57:32.101050
10267 00:57:32.811008 00f00000 ################################################################
10268 00:57:32.811593
10269 00:57:33.497127 00f80000 ################################################################
10270 00:57:33.497702
10271 00:57:34.178797 01000000 ################################################################
10272 00:57:34.179328
10273 00:57:34.860968 01080000 ################################################################
10274 00:57:34.861493
10275 00:57:35.571201 01100000 ################################################################
10276 00:57:35.571785
10277 00:57:36.286778 01180000 ################################################################
10278 00:57:36.287302
10279 00:57:36.953921 01200000 ################################################################
10280 00:57:36.954535
10281 00:57:37.660539 01280000 ################################################################
10282 00:57:37.661051
10283 00:57:38.261612 01300000 ################################################################
10284 00:57:38.261754
10285 00:57:38.820795 01380000 ################################################################
10286 00:57:38.820944
10287 00:57:39.377722 01400000 ################################################################
10288 00:57:39.377863
10289 00:57:39.930302 01480000 ################################################################
10290 00:57:39.930450
10291 00:57:40.485789 01500000 ################################################################
10292 00:57:40.485946
10293 00:57:41.052597 01580000 ################################################################
10294 00:57:41.052747
10295 00:57:41.618266 01600000 ################################################################
10296 00:57:41.618419
10297 00:57:42.185895 01680000 ################################################################
10298 00:57:42.186048
10299 00:57:42.750969 01700000 ################################################################
10300 00:57:42.751118
10301 00:57:43.313708 01780000 ################################################################
10302 00:57:43.313893
10303 00:57:43.872557 01800000 ################################################################
10304 00:57:43.872705
10305 00:57:44.436201 01880000 ################################################################
10306 00:57:44.436352
10307 00:57:44.999260 01900000 ################################################################
10308 00:57:44.999403
10309 00:57:45.579397 01980000 ################################################################
10310 00:57:45.579551
10311 00:57:46.151282 01a00000 ################################################################
10312 00:57:46.151448
10313 00:57:46.719209 01a80000 ################################################################
10314 00:57:46.719359
10315 00:57:47.271492 01b00000 ################################################################
10316 00:57:47.271657
10317 00:57:47.846307 01b80000 ################################################################
10318 00:57:47.846460
10319 00:57:48.433595 01c00000 ################################################################
10320 00:57:48.433754
10321 00:57:49.019624 01c80000 ################################################################
10322 00:57:49.020053
10323 00:57:49.629720 01d00000 ################################################################
10324 00:57:49.629968
10325 00:57:50.182173 01d80000 ################################################################
10326 00:57:50.182344
10327 00:57:50.663405 01e00000 ######################################################### done.
10328 00:57:50.663556
10329 00:57:50.666787 The bootfile was 31916366 bytes long.
10330 00:57:50.666879
10331 00:57:50.669810 Sending tftp read request... done.
10332 00:57:50.669905
10333 00:57:50.669980 Waiting for the transfer...
10334 00:57:50.670050
10335 00:57:50.673347 00000000 # done.
10336 00:57:50.673443
10337 00:57:50.680001 Command line loaded dynamically from TFTP file: 14368594/tftp-deploy-t_vao4_5/kernel/cmdline
10338 00:57:50.680114
10339 00:57:50.702776 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368594/extract-nfsrootfs-bv0vk0cp,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10340 00:57:50.702869
10341 00:57:50.702935 Loading FIT.
10342 00:57:50.706358
10343 00:57:50.706434 Image ramdisk-1 has 18742027 bytes.
10344 00:57:50.706497
10345 00:57:50.709217 Image fdt-1 has 47258 bytes.
10346 00:57:50.709292
10347 00:57:50.712887 Image kernel-1 has 13125045 bytes.
10348 00:57:50.712966
10349 00:57:50.722308 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10350 00:57:50.722402
10351 00:57:50.738951 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10352 00:57:50.739066
10353 00:57:50.745573 Choosing best match conf-1 for compat google,spherion-rev2.
10354 00:57:50.749092
10355 00:57:50.753451 Connected to device vid:did:rid of 1ae0:0028:00
10356 00:57:50.760738
10357 00:57:50.764168 tpm_get_response: command 0x17b, return code 0x0
10358 00:57:50.764252
10359 00:57:50.767336 ec_init: CrosEC protocol v3 supported (256, 248)
10360 00:57:50.771393
10361 00:57:50.774689 tpm_cleanup: add release locality here.
10362 00:57:50.774792
10363 00:57:50.774873 Shutting down all USB controllers.
10364 00:57:50.777881
10365 00:57:50.778018 Removing current net device
10366 00:57:50.778133
10367 00:57:50.784568 Exiting depthcharge with code 4 at timestamp: 87509479
10368 00:57:50.784764
10369 00:57:50.788123 LZMA decompressing kernel-1 to 0x821a6718
10370 00:57:50.788283
10371 00:57:50.791321 LZMA decompressing kernel-1 to 0x40000000
10372 00:57:52.407423
10373 00:57:52.407574 jumping to kernel
10374 00:57:52.408121 end: 2.2.4 bootloader-commands (duration 00:01:00) [common]
10375 00:57:52.408224 start: 2.2.5 auto-login-action (timeout 00:03:27) [common]
10376 00:57:52.408302 Setting prompt string to ['Linux version [0-9]']
10377 00:57:52.408370 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10378 00:57:52.408438 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10379 00:57:52.490139
10380 00:57:52.493530 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10381 00:57:52.497385 start: 2.2.5.1 login-action (timeout 00:03:27) [common]
10382 00:57:52.497488 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10383 00:57:52.497561 Setting prompt string to []
10384 00:57:52.497636 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10385 00:57:52.497708 Using line separator: #'\n'#
10386 00:57:52.497767 No login prompt set.
10387 00:57:52.497829 Parsing kernel messages
10388 00:57:52.497885 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10389 00:57:52.497988 [login-action] Waiting for messages, (timeout 00:03:27)
10390 00:57:52.498054 Waiting using forced prompt support (timeout 00:01:43)
10391 00:57:52.516717 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
10392 00:57:52.519910 [ 0.000000] random: crng init done
10393 00:57:52.526645 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10394 00:57:52.529908 [ 0.000000] efi: UEFI not found.
10395 00:57:52.536435 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10396 00:57:52.546821 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10397 00:57:52.553022 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10398 00:57:52.562883 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10399 00:57:52.569214 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10400 00:57:52.575950 [ 0.000000] printk: bootconsole [mtk8250] enabled
10401 00:57:52.582591 [ 0.000000] NUMA: No NUMA configuration found
10402 00:57:52.589103 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10403 00:57:52.595948 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10404 00:57:52.596031 [ 0.000000] Zone ranges:
10405 00:57:52.602331 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10406 00:57:52.605936 [ 0.000000] DMA32 empty
10407 00:57:52.612475 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10408 00:57:52.615349 [ 0.000000] Movable zone start for each node
10409 00:57:52.618787 [ 0.000000] Early memory node ranges
10410 00:57:52.625098 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10411 00:57:52.631846 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10412 00:57:52.638303 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10413 00:57:52.645065 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10414 00:57:52.651945 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10415 00:57:52.658321 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10416 00:57:52.714854 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10417 00:57:52.721446 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10418 00:57:52.728293 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10419 00:57:52.731366 [ 0.000000] psci: probing for conduit method from DT.
10420 00:57:52.738036 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10421 00:57:52.741424 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10422 00:57:52.748008 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10423 00:57:52.751113 [ 0.000000] psci: SMC Calling Convention v1.2
10424 00:57:52.757730 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10425 00:57:52.761008 [ 0.000000] Detected VIPT I-cache on CPU0
10426 00:57:52.767632 [ 0.000000] CPU features: detected: GIC system register CPU interface
10427 00:57:52.774093 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10428 00:57:52.780676 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10429 00:57:52.787157 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10430 00:57:52.797277 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10431 00:57:52.803720 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10432 00:57:52.807038 [ 0.000000] alternatives: applying boot alternatives
10433 00:57:52.813870 [ 0.000000] Fallback order for Node 0: 0
10434 00:57:52.820476 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10435 00:57:52.823839 [ 0.000000] Policy zone: Normal
10436 00:57:52.846635 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368594/extract-nfsrootfs-bv0vk0cp,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10437 00:57:52.856336 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10438 00:57:52.868301 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10439 00:57:52.877682 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10440 00:57:52.884369 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10441 00:57:52.887705 <6>[ 0.000000] software IO TLB: area num 8.
10442 00:57:52.945446 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10443 00:57:53.094762 <6>[ 0.000000] Memory: 7945760K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407008K reserved, 32768K cma-reserved)
10444 00:57:53.101553 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10445 00:57:53.107948 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10446 00:57:53.111578 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10447 00:57:53.118079 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10448 00:57:53.124482 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10449 00:57:53.127902 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10450 00:57:53.137467 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10451 00:57:53.144156 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10452 00:57:53.150812 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10453 00:57:53.157458 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10454 00:57:53.160706 <6>[ 0.000000] GICv3: 608 SPIs implemented
10455 00:57:53.164242 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10456 00:57:53.170477 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10457 00:57:53.173937 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10458 00:57:53.180443 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10459 00:57:53.193752 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10460 00:57:53.206680 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10461 00:57:53.213736 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10462 00:57:53.221396 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10463 00:57:53.234610 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10464 00:57:53.240822 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10465 00:57:53.247607 <6>[ 0.009181] Console: colour dummy device 80x25
10466 00:57:53.257866 <6>[ 0.013929] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10467 00:57:53.264278 <6>[ 0.024371] pid_max: default: 32768 minimum: 301
10468 00:57:53.267401 <6>[ 0.029273] LSM: Security Framework initializing
10469 00:57:53.274189 <6>[ 0.034240] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10470 00:57:53.284118 <6>[ 0.042101] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10471 00:57:53.294043 <6>[ 0.051569] cblist_init_generic: Setting adjustable number of callback queues.
10472 00:57:53.300732 <6>[ 0.059060] cblist_init_generic: Setting shift to 3 and lim to 1.
10473 00:57:53.307019 <6>[ 0.065398] cblist_init_generic: Setting adjustable number of callback queues.
10474 00:57:53.313951 <6>[ 0.072825] cblist_init_generic: Setting shift to 3 and lim to 1.
10475 00:57:53.316836 <6>[ 0.079264] rcu: Hierarchical SRCU implementation.
10476 00:57:53.323421 <6>[ 0.084279] rcu: Max phase no-delay instances is 1000.
10477 00:57:53.329976 <6>[ 0.091312] EFI services will not be available.
10478 00:57:53.333343 <6>[ 0.096271] smp: Bringing up secondary CPUs ...
10479 00:57:53.342447 <6>[ 0.101350] Detected VIPT I-cache on CPU1
10480 00:57:53.349092 <6>[ 0.101423] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10481 00:57:53.355615 <6>[ 0.101454] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10482 00:57:53.358862 <6>[ 0.101787] Detected VIPT I-cache on CPU2
10483 00:57:53.368670 <6>[ 0.101837] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10484 00:57:53.375392 <6>[ 0.101853] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10485 00:57:53.378542 <6>[ 0.102111] Detected VIPT I-cache on CPU3
10486 00:57:53.385057 <6>[ 0.102157] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10487 00:57:53.392098 <6>[ 0.102171] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10488 00:57:53.398501 <6>[ 0.102474] CPU features: detected: Spectre-v4
10489 00:57:53.401405 <6>[ 0.102480] CPU features: detected: Spectre-BHB
10490 00:57:53.404862 <6>[ 0.102485] Detected PIPT I-cache on CPU4
10491 00:57:53.414801 <6>[ 0.102544] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10492 00:57:53.421377 <6>[ 0.102560] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10493 00:57:53.425089 <6>[ 0.102853] Detected PIPT I-cache on CPU5
10494 00:57:53.431408 <6>[ 0.102915] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10495 00:57:53.437850 <6>[ 0.102931] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10496 00:57:53.441501 <6>[ 0.103211] Detected PIPT I-cache on CPU6
10497 00:57:53.451409 <6>[ 0.103275] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10498 00:57:53.457776 <6>[ 0.103291] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10499 00:57:53.460834 <6>[ 0.103589] Detected PIPT I-cache on CPU7
10500 00:57:53.467448 <6>[ 0.103653] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10501 00:57:53.474076 <6>[ 0.103669] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10502 00:57:53.477502 <6>[ 0.103716] smp: Brought up 1 node, 8 CPUs
10503 00:57:53.483871 <6>[ 0.245236] SMP: Total of 8 processors activated.
10504 00:57:53.490693 <6>[ 0.250157] CPU features: detected: 32-bit EL0 Support
10505 00:57:53.497148 <6>[ 0.255521] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10506 00:57:53.503617 <6>[ 0.264321] CPU features: detected: Common not Private translations
10507 00:57:53.510146 <6>[ 0.270837] CPU features: detected: CRC32 instructions
10508 00:57:53.516888 <6>[ 0.276188] CPU features: detected: RCpc load-acquire (LDAPR)
10509 00:57:53.520540 <6>[ 0.282148] CPU features: detected: LSE atomic instructions
10510 00:57:53.527323 <6>[ 0.287930] CPU features: detected: Privileged Access Never
10511 00:57:53.533802 <6>[ 0.293709] CPU features: detected: RAS Extension Support
10512 00:57:53.540135 <6>[ 0.299318] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10513 00:57:53.543030 <6>[ 0.306537] CPU: All CPU(s) started at EL2
10514 00:57:53.549573 <6>[ 0.310854] alternatives: applying system-wide alternatives
10515 00:57:53.560280 <6>[ 0.321694] devtmpfs: initialized
10516 00:57:53.575569 <6>[ 0.330475] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10517 00:57:53.582067 <6>[ 0.340437] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10518 00:57:53.588827 <6>[ 0.348453] pinctrl core: initialized pinctrl subsystem
10519 00:57:53.591833 <6>[ 0.355126] DMI not present or invalid.
10520 00:57:53.598955 <6>[ 0.359537] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10521 00:57:53.608809 <6>[ 0.366335] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10522 00:57:53.615288 <6>[ 0.373923] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10523 00:57:53.624809 <6>[ 0.382144] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10524 00:57:53.628321 <6>[ 0.390386] audit: initializing netlink subsys (disabled)
10525 00:57:53.637816 <5>[ 0.396080] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10526 00:57:53.644658 <6>[ 0.396791] thermal_sys: Registered thermal governor 'step_wise'
10527 00:57:53.651071 <6>[ 0.404047] thermal_sys: Registered thermal governor 'power_allocator'
10528 00:57:53.654421 <6>[ 0.410301] cpuidle: using governor menu
10529 00:57:53.661010 <6>[ 0.421260] NET: Registered PF_QIPCRTR protocol family
10530 00:57:53.667613 <6>[ 0.426746] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10531 00:57:53.674298 <6>[ 0.433850] ASID allocator initialised with 32768 entries
10532 00:57:53.677201 <6>[ 0.440426] Serial: AMBA PL011 UART driver
10533 00:57:53.687584 <4>[ 0.449264] Trying to register duplicate clock ID: 134
10534 00:57:53.746012 <6>[ 0.510737] KASLR enabled
10535 00:57:53.760216 <6>[ 0.518409] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10536 00:57:53.767197 <6>[ 0.525423] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10537 00:57:53.773240 <6>[ 0.531912] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10538 00:57:53.779838 <6>[ 0.538916] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10539 00:57:53.786446 <6>[ 0.545401] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10540 00:57:53.793228 <6>[ 0.552405] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10541 00:57:53.799832 <6>[ 0.558892] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10542 00:57:53.806104 <6>[ 0.565898] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10543 00:57:53.809355 <6>[ 0.573403] ACPI: Interpreter disabled.
10544 00:57:53.818278 <6>[ 0.579822] iommu: Default domain type: Translated
10545 00:57:53.825068 <6>[ 0.584934] iommu: DMA domain TLB invalidation policy: strict mode
10546 00:57:53.828493 <5>[ 0.591597] SCSI subsystem initialized
10547 00:57:53.834630 <6>[ 0.595761] usbcore: registered new interface driver usbfs
10548 00:57:53.841341 <6>[ 0.601493] usbcore: registered new interface driver hub
10549 00:57:53.844996 <6>[ 0.607046] usbcore: registered new device driver usb
10550 00:57:53.851909 <6>[ 0.613147] pps_core: LinuxPPS API ver. 1 registered
10551 00:57:53.861380 <6>[ 0.618339] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10552 00:57:53.865281 <6>[ 0.627684] PTP clock support registered
10553 00:57:53.868007 <6>[ 0.631927] EDAC MC: Ver: 3.0.0
10554 00:57:53.875933 <6>[ 0.637064] FPGA manager framework
10555 00:57:53.882119 <6>[ 0.640747] Advanced Linux Sound Architecture Driver Initialized.
10556 00:57:53.885462 <6>[ 0.647516] vgaarb: loaded
10557 00:57:53.892012 <6>[ 0.650665] clocksource: Switched to clocksource arch_sys_counter
10558 00:57:53.895545 <5>[ 0.657106] VFS: Disk quotas dquot_6.6.0
10559 00:57:53.902016 <6>[ 0.661295] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10560 00:57:53.904937 <6>[ 0.668484] pnp: PnP ACPI: disabled
10561 00:57:53.913797 <6>[ 0.675146] NET: Registered PF_INET protocol family
10562 00:57:53.923441 <6>[ 0.680738] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10563 00:57:53.934887 <6>[ 0.693074] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10564 00:57:53.944630 <6>[ 0.701892] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10565 00:57:53.951827 <6>[ 0.709861] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10566 00:57:53.961346 <6>[ 0.718563] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10567 00:57:53.967647 <6>[ 0.728318] TCP: Hash tables configured (established 65536 bind 65536)
10568 00:57:53.974284 <6>[ 0.735184] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10569 00:57:53.984373 <6>[ 0.742385] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10570 00:57:53.990822 <6>[ 0.750088] NET: Registered PF_UNIX/PF_LOCAL protocol family
10571 00:57:53.997192 <6>[ 0.756241] RPC: Registered named UNIX socket transport module.
10572 00:57:54.000881 <6>[ 0.762396] RPC: Registered udp transport module.
10573 00:57:54.007098 <6>[ 0.767331] RPC: Registered tcp transport module.
10574 00:57:54.013853 <6>[ 0.772264] RPC: Registered tcp NFSv4.1 backchannel transport module.
10575 00:57:54.017144 <6>[ 0.778932] PCI: CLS 0 bytes, default 64
10576 00:57:54.020338 <6>[ 0.783326] Unpacking initramfs...
10577 00:57:54.030457 <6>[ 0.787051] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10578 00:57:54.036667 <6>[ 0.795680] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10579 00:57:54.042956 <6>[ 0.804478] kvm [1]: IPA Size Limit: 40 bits
10580 00:57:54.046724 <6>[ 0.809004] kvm [1]: GICv3: no GICV resource entry
10581 00:57:54.053007 <6>[ 0.814024] kvm [1]: disabling GICv2 emulation
10582 00:57:54.059427 <6>[ 0.818708] kvm [1]: GIC system register CPU interface enabled
10583 00:57:54.063079 <6>[ 0.824872] kvm [1]: vgic interrupt IRQ18
10584 00:57:54.069817 <6>[ 0.830709] kvm [1]: VHE mode initialized successfully
10585 00:57:54.076201 <5>[ 0.837084] Initialise system trusted keyrings
10586 00:57:54.082797 <6>[ 0.841891] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10587 00:57:54.090337 <6>[ 0.851861] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10588 00:57:54.096983 <5>[ 0.858291] NFS: Registering the id_resolver key type
10589 00:57:54.100277 <5>[ 0.863596] Key type id_resolver registered
10590 00:57:54.106883 <5>[ 0.868010] Key type id_legacy registered
10591 00:57:54.113406 <6>[ 0.872283] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10592 00:57:54.120135 <6>[ 0.879207] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10593 00:57:54.126563 <6>[ 0.886933] 9p: Installing v9fs 9p2000 file system support
10594 00:57:54.162957 <5>[ 0.924323] Key type asymmetric registered
10595 00:57:54.166111 <5>[ 0.928655] Asymmetric key parser 'x509' registered
10596 00:57:54.176056 <6>[ 0.933792] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10597 00:57:54.179198 <6>[ 0.941410] io scheduler mq-deadline registered
10598 00:57:54.182614 <6>[ 0.946174] io scheduler kyber registered
10599 00:57:54.201735 <6>[ 0.963018] EINJ: ACPI disabled.
10600 00:57:54.234680 <4>[ 0.989341] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 00:57:54.244337 <4>[ 0.999972] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10602 00:57:54.259079 <6>[ 1.020705] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10603 00:57:54.267216 <6>[ 1.028676] printk: console [ttyS0] disabled
10604 00:57:54.294917 <6>[ 1.053309] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10605 00:57:54.301605 <6>[ 1.062790] printk: console [ttyS0] enabled
10606 00:57:54.305176 <6>[ 1.062790] printk: console [ttyS0] enabled
10607 00:57:54.311591 <6>[ 1.071694] printk: bootconsole [mtk8250] disabled
10608 00:57:54.314800 <6>[ 1.071694] printk: bootconsole [mtk8250] disabled
10609 00:57:54.321568 <6>[ 1.082772] SuperH (H)SCI(F) driver initialized
10610 00:57:54.324598 <6>[ 1.088047] msm_serial: driver initialized
10611 00:57:54.338734 <6>[ 1.096963] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10612 00:57:54.348585 <6>[ 1.105510] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10613 00:57:54.355199 <6>[ 1.114054] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10614 00:57:54.365492 <6>[ 1.122683] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10615 00:57:54.375164 <6>[ 1.131390] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10616 00:57:54.381661 <6>[ 1.140108] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10617 00:57:54.391666 <6>[ 1.148648] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10618 00:57:54.398134 <6>[ 1.157441] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10619 00:57:54.407977 <6>[ 1.165984] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10620 00:57:54.419819 <6>[ 1.181429] loop: module loaded
10621 00:57:54.426340 <6>[ 1.187335] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10622 00:57:54.448888 <4>[ 1.210516] mtk-pmic-keys: Failed to locate of_node [id: -1]
10623 00:57:54.455811 <6>[ 1.217271] megasas: 07.719.03.00-rc1
10624 00:57:54.465546 <6>[ 1.226945] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10625 00:57:54.472979 <6>[ 1.234069] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10626 00:57:54.489548 <6>[ 1.250619] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10627 00:57:54.549320 <6>[ 1.304338] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10628 00:57:54.816386 <6>[ 1.577898] Freeing initrd memory: 18296K
10629 00:57:54.828068 <6>[ 1.589544] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10630 00:57:54.838816 <6>[ 1.600415] tun: Universal TUN/TAP device driver, 1.6
10631 00:57:54.842282 <6>[ 1.606462] thunder_xcv, ver 1.0
10632 00:57:54.845619 <6>[ 1.609964] thunder_bgx, ver 1.0
10633 00:57:54.848937 <6>[ 1.613461] nicpf, ver 1.0
10634 00:57:54.859272 <6>[ 1.617479] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10635 00:57:54.862655 <6>[ 1.624955] hns3: Copyright (c) 2017 Huawei Corporation.
10636 00:57:54.869340 <6>[ 1.630546] hclge is initializing
10637 00:57:54.872567 <6>[ 1.634122] e1000: Intel(R) PRO/1000 Network Driver
10638 00:57:54.879131 <6>[ 1.639251] e1000: Copyright (c) 1999-2006 Intel Corporation.
10639 00:57:54.882662 <6>[ 1.645265] e1000e: Intel(R) PRO/1000 Network Driver
10640 00:57:54.889144 <6>[ 1.650481] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10641 00:57:54.896121 <6>[ 1.656667] igb: Intel(R) Gigabit Ethernet Network Driver
10642 00:57:54.902713 <6>[ 1.662318] igb: Copyright (c) 2007-2014 Intel Corporation.
10643 00:57:54.908932 <6>[ 1.668156] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10644 00:57:54.915554 <6>[ 1.674676] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10645 00:57:54.918737 <6>[ 1.681149] sky2: driver version 1.30
10646 00:57:54.925360 <6>[ 1.686084] usbcore: registered new device driver r8152-cfgselector
10647 00:57:54.932217 <6>[ 1.692621] usbcore: registered new interface driver r8152
10648 00:57:54.938556 <6>[ 1.698436] VFIO - User Level meta-driver version: 0.3
10649 00:57:54.945171 <6>[ 1.706647] usbcore: registered new interface driver usb-storage
10650 00:57:54.951560 <6>[ 1.713091] usbcore: registered new device driver onboard-usb-hub
10651 00:57:54.960688 <6>[ 1.722278] mt6397-rtc mt6359-rtc: registered as rtc0
10652 00:57:54.970546 <6>[ 1.727745] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:57:54 UTC (1718499474)
10653 00:57:54.973845 <6>[ 1.737306] i2c_dev: i2c /dev entries driver
10654 00:57:54.987892 <4>[ 1.749334] cpu cpu0: supply cpu not found, using dummy regulator
10655 00:57:54.994507 <4>[ 1.755764] cpu cpu1: supply cpu not found, using dummy regulator
10656 00:57:55.000987 <4>[ 1.762177] cpu cpu2: supply cpu not found, using dummy regulator
10657 00:57:55.007616 <4>[ 1.768578] cpu cpu3: supply cpu not found, using dummy regulator
10658 00:57:55.014106 <4>[ 1.774976] cpu cpu4: supply cpu not found, using dummy regulator
10659 00:57:55.020771 <4>[ 1.781389] cpu cpu5: supply cpu not found, using dummy regulator
10660 00:57:55.027643 <4>[ 1.787790] cpu cpu6: supply cpu not found, using dummy regulator
10661 00:57:55.033819 <4>[ 1.794185] cpu cpu7: supply cpu not found, using dummy regulator
10662 00:57:55.054379 <6>[ 1.815822] cpu cpu0: EM: created perf domain
10663 00:57:55.057369 <6>[ 1.820782] cpu cpu4: EM: created perf domain
10664 00:57:55.065045 <6>[ 1.826382] sdhci: Secure Digital Host Controller Interface driver
10665 00:57:55.071653 <6>[ 1.832815] sdhci: Copyright(c) Pierre Ossman
10666 00:57:55.078352 <6>[ 1.837775] Synopsys Designware Multimedia Card Interface Driver
10667 00:57:55.085101 <6>[ 1.844411] sdhci-pltfm: SDHCI platform and OF driver helper
10668 00:57:55.087885 <6>[ 1.844566] mmc0: CQHCI version 5.10
10669 00:57:55.094776 <6>[ 1.854430] ledtrig-cpu: registered to indicate activity on CPUs
10670 00:57:55.101539 <6>[ 1.861434] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10671 00:57:55.108201 <6>[ 1.868482] usbcore: registered new interface driver usbhid
10672 00:57:55.111351 <6>[ 1.874303] usbhid: USB HID core driver
10673 00:57:55.117803 <6>[ 1.878507] spi_master spi0: will run message pump with realtime priority
10674 00:57:55.165151 <6>[ 1.919672] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10675 00:57:55.184373 <6>[ 1.936154] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10676 00:57:55.187994 <6>[ 1.943484] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17c14
10677 00:57:55.196224 <6>[ 1.957538] cros-ec-spi spi0.0: Chrome EC device registered
10678 00:57:55.202675 <6>[ 1.963612] mmc0: Command Queue Engine enabled
10679 00:57:55.209333 <6>[ 1.968360] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10680 00:57:55.212654 <6>[ 1.976113] mmcblk0: mmc0:0001 DA4128 116 GiB
10681 00:57:55.223676 <6>[ 1.985529] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10682 00:57:55.231520 <6>[ 1.992970] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10683 00:57:55.238198 <6>[ 1.999111] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10684 00:57:55.247896 <6>[ 2.004359] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10685 00:57:55.254400 <6>[ 2.005172] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10686 00:57:55.258158 <6>[ 2.014668] NET: Registered PF_PACKET protocol family
10687 00:57:55.264363 <6>[ 2.025635] 9pnet: Installing 9P2000 support
10688 00:57:55.267914 <5>[ 2.030223] Key type dns_resolver registered
10689 00:57:55.274515 <6>[ 2.035314] registered taskstats version 1
10690 00:57:55.277670 <5>[ 2.039719] Loading compiled-in X.509 certificates
10691 00:57:55.307428 <4>[ 2.062486] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10692 00:57:55.317425 <4>[ 2.073214] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10693 00:57:55.332529 <6>[ 2.094275] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10694 00:57:55.339792 <6>[ 2.101179] xhci-mtk 11200000.usb: xHCI Host Controller
10695 00:57:55.346370 <6>[ 2.106680] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10696 00:57:55.356362 <6>[ 2.114519] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10697 00:57:55.362870 <6>[ 2.123952] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10698 00:57:55.369227 <6>[ 2.130032] xhci-mtk 11200000.usb: xHCI Host Controller
10699 00:57:55.376010 <6>[ 2.135511] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10700 00:57:55.383066 <6>[ 2.143165] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10701 00:57:55.389619 <6>[ 2.150956] hub 1-0:1.0: USB hub found
10702 00:57:55.392842 <6>[ 2.154993] hub 1-0:1.0: 1 port detected
10703 00:57:55.399379 <6>[ 2.159262] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10704 00:57:55.406284 <6>[ 2.167807] hub 2-0:1.0: USB hub found
10705 00:57:55.409579 <6>[ 2.171825] hub 2-0:1.0: 1 port detected
10706 00:57:55.417232 <6>[ 2.178885] mtk-msdc 11f70000.mmc: Got CD GPIO
10707 00:57:55.437996 <6>[ 2.196132] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10708 00:57:55.447715 <6>[ 2.204594] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10709 00:57:55.454510 <6>[ 2.212946] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10710 00:57:55.464359 <6>[ 2.221306] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10711 00:57:55.471159 <6>[ 2.229648] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10712 00:57:55.481127 <6>[ 2.237998] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10713 00:57:55.487467 <6>[ 2.246337] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10714 00:57:55.497118 <6>[ 2.254689] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10715 00:57:55.503768 <6>[ 2.263028] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10716 00:57:55.513792 <6>[ 2.271376] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10717 00:57:55.520487 <6>[ 2.279718] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10718 00:57:55.530417 <6>[ 2.288067] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10719 00:57:55.537278 <6>[ 2.296406] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10720 00:57:55.546806 <6>[ 2.304758] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10721 00:57:55.553260 <6>[ 2.313096] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10722 00:57:55.560066 <6>[ 2.321799] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10723 00:57:55.567324 <6>[ 2.328953] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10724 00:57:55.574538 <6>[ 2.335767] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10725 00:57:55.584288 <6>[ 2.342532] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10726 00:57:55.590637 <6>[ 2.349460] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10727 00:57:55.597319 <6>[ 2.356308] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10728 00:57:55.607130 <6>[ 2.365438] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10729 00:57:55.617165 <6>[ 2.374559] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10730 00:57:55.626873 <6>[ 2.383854] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10731 00:57:55.637055 <6>[ 2.393321] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10732 00:57:55.646922 <6>[ 2.402787] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10733 00:57:55.653672 <6>[ 2.411906] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10734 00:57:55.663410 <6>[ 2.421372] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10735 00:57:55.673348 <6>[ 2.430492] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10736 00:57:55.683268 <6>[ 2.439790] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10737 00:57:55.693007 <6>[ 2.449985] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10738 00:57:55.703238 <6>[ 2.461477] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10739 00:57:55.710924 <6>[ 2.472604] Trying to probe devices needed for running init ...
10740 00:57:55.721572 <3>[ 2.479879] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10741 00:57:55.828580 <6>[ 2.586960] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10742 00:57:55.982148 <6>[ 2.743946] hub 1-1:1.0: USB hub found
10743 00:57:55.985490 <6>[ 2.748448] hub 1-1:1.0: 4 ports detected
10744 00:57:55.997646 <6>[ 2.759178] hub 1-1:1.0: USB hub found
10745 00:57:56.001020 <6>[ 2.763632] hub 1-1:1.0: 4 ports detected
10746 00:57:56.108651 <6>[ 2.867113] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10747 00:57:56.134478 <6>[ 2.895964] hub 2-1:1.0: USB hub found
10748 00:57:56.137455 <6>[ 2.900423] hub 2-1:1.0: 3 ports detected
10749 00:57:56.149058 <6>[ 2.910591] hub 2-1:1.0: USB hub found
10750 00:57:56.152216 <6>[ 2.915148] hub 2-1:1.0: 3 ports detected
10751 00:57:56.324482 <6>[ 3.082990] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10752 00:57:56.457173 <6>[ 3.218836] hub 1-1.4:1.0: USB hub found
10753 00:57:56.460224 <6>[ 3.223457] hub 1-1.4:1.0: 2 ports detected
10754 00:57:56.472838 <6>[ 3.234388] hub 1-1.4:1.0: USB hub found
10755 00:57:56.475886 <6>[ 3.238971] hub 1-1.4:1.0: 2 ports detected
10756 00:57:56.536537 <6>[ 3.295183] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10757 00:57:56.645104 <6>[ 3.403615] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10758 00:57:56.681600 <4>[ 3.439975] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10759 00:57:56.691163 <4>[ 3.449157] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10760 00:57:56.727309 <6>[ 3.488562] r8152 2-1.3:1.0 eth0: v1.12.13
10761 00:57:56.772327 <6>[ 3.530818] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10762 00:57:56.964437 <6>[ 3.722794] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10763 00:57:58.399155 <6>[ 5.161079] r8152 2-1.3:1.0 eth0: carrier on
10764 00:58:00.752609 <5>[ 5.186781] Sending DHCP requests .., OK
10765 00:58:00.759271 <6>[ 7.519117] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10766 00:58:00.762438 <6>[ 7.527421] IP-Config: Complete:
10767 00:58:00.775940 <6>[ 7.530918] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10768 00:58:00.782142 <6>[ 7.541627] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10769 00:58:00.789019 <6>[ 7.550245] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10770 00:58:00.795705 <6>[ 7.550254] nameserver0=192.168.201.1
10771 00:58:00.798652 <6>[ 7.562412] clk: Disabling unused clocks
10772 00:58:00.802504 <6>[ 7.567950] ALSA device list:
10773 00:58:00.808761 <6>[ 7.571203] No soundcards found.
10774 00:58:00.816383 <6>[ 7.578604] Freeing unused kernel memory: 8512K
10775 00:58:00.819699 <6>[ 7.583495] Run /init as init process
10776 00:58:00.829071 Loading, please wait...
10777 00:58:00.857776 Starting systemd-udevd version 252.22-1~deb12u1
10778 00:58:01.115912 <6>[ 7.874830] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10779 00:58:01.130418 <6>[ 7.889447] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10780 00:58:01.146560 <6>[ 7.905549] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10781 00:58:01.153278 <6>[ 7.913711] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10782 00:58:01.160087 <6>[ 7.914900] remoteproc remoteproc0: scp is available
10783 00:58:01.166705 <6>[ 7.916275] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10784 00:58:01.176770 <6>[ 7.916300] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10785 00:58:01.182810 <6>[ 7.916307] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10786 00:58:01.192664 <4>[ 7.921943] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10787 00:58:01.199497 <6>[ 7.927448] remoteproc remoteproc0: powering up scp
10788 00:58:01.206068 <6>[ 7.935072] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10789 00:58:01.215955 <6>[ 7.943037] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10790 00:58:01.222723 <4>[ 7.945382] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10791 00:58:01.229355 <4>[ 7.945485] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10792 00:58:01.239094 <3>[ 7.948336] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10793 00:58:01.245712 <3>[ 7.948344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10794 00:58:01.255725 <3>[ 7.948348] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 00:58:01.262142 <6>[ 7.951753] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10796 00:58:01.268733 <6>[ 7.961073] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10797 00:58:01.275463 <3>[ 7.966208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10798 00:58:01.285492 <6>[ 7.966998] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10799 00:58:01.291885 <6>[ 7.967016] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10800 00:58:01.298924 <6>[ 7.967021] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10801 00:58:01.308520 <6>[ 7.967032] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10802 00:58:01.311555 <6>[ 7.979047] mc: Linux media interface: v0.10
10803 00:58:01.322086 <3>[ 7.982821] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10804 00:58:01.328775 <6>[ 7.993595] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10805 00:58:01.338683 <3>[ 7.997180] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10806 00:58:01.345474 <6>[ 8.036381] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10807 00:58:01.351670 <3>[ 8.043165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 00:58:01.361670 <4>[ 8.051084] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10809 00:58:01.365324 <4>[ 8.051084] Fallback method does not support PEC.
10810 00:58:01.374667 <6>[ 8.051103] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10811 00:58:01.381355 <6>[ 8.051127] pci_bus 0000:00: root bus resource [bus 00-ff]
10812 00:58:01.387965 <6>[ 8.051136] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10813 00:58:01.397816 <6>[ 8.051140] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10814 00:58:01.404476 <6>[ 8.051195] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10815 00:58:01.414483 <6>[ 8.051498] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10816 00:58:01.424916 <6>[ 8.056988] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10817 00:58:01.431287 <3>[ 8.059872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10818 00:58:01.437957 <6>[ 8.066850] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10819 00:58:01.444454 <6>[ 8.067383] videodev: Linux video capture interface: v2.00
10820 00:58:01.454360 <3>[ 8.076035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10821 00:58:01.457921 <6>[ 8.081034] pci 0000:00:00.0: supports D1 D2
10822 00:58:01.464538 <3>[ 8.089061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 00:58:01.471337 <6>[ 8.096895] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10824 00:58:01.474561 <6>[ 8.097657] Bluetooth: Core ver 2.22
10825 00:58:01.481243 <6>[ 8.097727] NET: Registered PF_BLUETOOTH protocol family
10826 00:58:01.487749 <6>[ 8.097729] Bluetooth: HCI device and connection manager initialized
10827 00:58:01.494866 <6>[ 8.097765] Bluetooth: HCI socket layer initialized
10828 00:58:01.497914 <6>[ 8.097776] Bluetooth: L2CAP socket layer initialized
10829 00:58:01.504220 <6>[ 8.097791] Bluetooth: SCO socket layer initialized
10830 00:58:01.510829 <6>[ 8.099508] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10831 00:58:01.517452 <3>[ 8.105126] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10832 00:58:01.527367 <6>[ 8.106297] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10833 00:58:01.533978 <6>[ 8.108536] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10834 00:58:01.544109 <6>[ 8.111692] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10835 00:58:01.553587 <6>[ 8.113939] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10836 00:58:01.557619 <6>[ 8.114062] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10837 00:58:01.567208 <6>[ 8.114093] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10838 00:58:01.573615 <6>[ 8.114114] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10839 00:58:01.580059 <6>[ 8.114133] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10840 00:58:01.586888 <6>[ 8.114251] pci 0000:01:00.0: supports D1 D2
10841 00:58:01.593192 <6>[ 8.114254] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10842 00:58:01.599982 <3>[ 8.119743] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10843 00:58:01.607014 <6>[ 8.133391] remoteproc remoteproc0: remote processor scp is now up
10844 00:58:01.613170 <6>[ 8.134742] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10845 00:58:01.623105 <6>[ 8.134775] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10846 00:58:01.629675 <6>[ 8.134782] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10847 00:58:01.636078 <6>[ 8.134795] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10848 00:58:01.646093 <6>[ 8.134812] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10849 00:58:01.652719 <6>[ 8.134828] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10850 00:58:01.659230 <6>[ 8.134848] pci 0000:00:00.0: PCI bridge to [bus 01]
10851 00:58:01.665968 <6>[ 8.134856] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10852 00:58:01.672710 <6>[ 8.135013] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10853 00:58:01.679235 <6>[ 8.135982] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10854 00:58:01.685601 <6>[ 8.136297] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10855 00:58:01.692152 <3>[ 8.143541] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10856 00:58:01.699274 <6>[ 8.144243] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10857 00:58:01.712201 <6>[ 8.145261] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10858 00:58:01.718743 <6>[ 8.145357] usbcore: registered new interface driver uvcvideo
10859 00:58:01.725581 <5>[ 8.152670] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10860 00:58:01.735054 <3>[ 8.156325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10861 00:58:01.741854 <3>[ 8.156333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 00:58:01.751810 <3>[ 8.156343] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10863 00:58:01.758316 <6>[ 8.156922] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10864 00:58:01.761968 <6>[ 8.167028] usbcore: registered new interface driver btusb
10865 00:58:01.774703 <4>[ 8.167931] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10866 00:58:01.778054 <3>[ 8.167945] Bluetooth: hci0: Failed to load firmware file (-2)
10867 00:58:01.784914 <3>[ 8.167951] Bluetooth: hci0: Failed to set up firmware (-2)
10868 00:58:01.794644 <4>[ 8.167957] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10869 00:58:01.804727 <3>[ 8.172500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10870 00:58:01.811148 <5>[ 8.179804] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10871 00:58:01.818151 <5>[ 8.180249] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10872 00:58:01.827528 <4>[ 8.180324] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10873 00:58:01.834528 <6>[ 8.180332] cfg80211: failed to load regulatory.db
10874 00:58:01.840665 <3>[ 8.186244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 00:58:01.850983 <3>[ 8.190856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 00:58:01.857265 <3>[ 8.244331] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 00:58:01.867186 <6>[ 8.277915] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10878 00:58:01.873970 <6>[ 8.633555] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10879 00:58:01.896493 <6>[ 8.658983] mt7921e 0000:01:00.0: ASIC revision: 79610010
10880 00:58:01.999143 <6>[ 8.758175] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10881 00:58:02.002428 <6>[ 8.758175]
10882 00:58:02.006117 Begin: Loading essential drivers ... done.
10883 00:58:02.009451 Begin: Running /scripts/init-premount ... done.
10884 00:58:02.015755 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10885 00:58:02.025822 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10886 00:58:02.028690 Device /sys/class/net/eth0 found
10887 00:58:02.028784 done.
10888 00:58:02.035770 Begin: Waiting up to 180 secs for any network device to become available ... done.
10889 00:58:02.072541 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10890 00:58:02.079623 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10891 00:58:02.086282 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10892 00:58:02.092525 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10893 00:58:02.099642 host : mt8192-asurada-spherion-r0-cbg-9
10894 00:58:02.106099 domain : lava-rack
10895 00:58:02.109320 rootserver: 192.168.201.1 rootpath:
10896 00:58:02.112294 filename :
10897 00:58:02.211696 done.
10898 00:58:02.219935 Begin: Running /scripts/nfs-bottom ... done.
10899 00:58:02.237294 Begin: Running /scripts/init-bottom ... done.
10900 00:58:02.265652 <6>[ 9.024898] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10901 00:58:03.598856 <6>[ 10.361143] NET: Registered PF_INET6 protocol family
10902 00:58:03.606671 <6>[ 10.368741] Segment Routing with IPv6
10903 00:58:03.609960 <6>[ 10.372763] In-situ OAM (IOAM) with IPv6
10904 00:58:03.788311 <30>[ 10.523846] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10905 00:58:03.794498 <30>[ 10.556962] systemd[1]: Detected architecture arm64.
10906 00:58:03.804461
10907 00:58:03.807190 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10908 00:58:03.807316
10909 00:58:03.829852 <30>[ 10.592458] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10910 00:58:04.960431 <30>[ 11.719724] systemd[1]: Queued start job for default target graphical.target.
10911 00:58:05.001186 <30>[ 11.760254] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10912 00:58:05.007520 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10913 00:58:05.029536 <30>[ 11.788800] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10914 00:58:05.039367 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10915 00:58:05.057234 <30>[ 11.816708] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10916 00:58:05.066909 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10917 00:58:05.084975 <30>[ 11.844286] systemd[1]: Created slice user.slice - User and Session Slice.
10918 00:58:05.091356 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10919 00:58:05.115974 <30>[ 11.871817] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10920 00:58:05.125610 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10921 00:58:05.143423 <30>[ 11.899204] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10922 00:58:05.149597 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10923 00:58:05.178092 <30>[ 11.927611] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10924 00:58:05.187934 <30>[ 11.947501] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10925 00:58:05.194578 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10926 00:58:05.212011 <30>[ 11.971344] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10927 00:58:05.221890 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10928 00:58:05.239953 <30>[ 11.999476] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10929 00:58:05.250025 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10930 00:58:05.264782 <30>[ 12.027495] systemd[1]: Reached target paths.target - Path Units.
10931 00:58:05.274673 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10932 00:58:05.292419 <30>[ 12.051430] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10933 00:58:05.298483 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10934 00:58:05.312757 <30>[ 12.074945] systemd[1]: Reached target slices.target - Slice Units.
10935 00:58:05.322387 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10936 00:58:05.336726 <30>[ 12.099438] systemd[1]: Reached target swap.target - Swaps.
10937 00:58:05.343418 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10938 00:58:05.363441 <30>[ 12.123004] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10939 00:58:05.373357 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10940 00:58:05.392314 <30>[ 12.151852] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10941 00:58:05.402149 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10942 00:58:05.422107 <30>[ 12.181576] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10943 00:58:05.431980 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10944 00:58:05.448722 <30>[ 12.208304] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10945 00:58:05.458630 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10946 00:58:05.476128 <30>[ 12.235487] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10947 00:58:05.482819 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10948 00:58:05.500960 <30>[ 12.260408] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10949 00:58:05.510821 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10950 00:58:05.530322 <30>[ 12.289756] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10951 00:58:05.540360 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10952 00:58:05.556837 <30>[ 12.315998] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10953 00:58:05.566536 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10954 00:58:05.607836 <30>[ 12.366984] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10955 00:58:05.613954 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10956 00:58:05.635882 <30>[ 12.395118] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10957 00:58:05.642334 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10958 00:58:05.668222 <30>[ 12.427881] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10959 00:58:05.674727 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10960 00:58:05.702962 <30>[ 12.455629] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10961 00:58:05.752380 <30>[ 12.511859] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10962 00:58:05.762632 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10963 00:58:05.782994 <30>[ 12.542381] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10964 00:58:05.790136 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10965 00:58:05.813499 <30>[ 12.572508] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10966 00:58:05.822779 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10967 00:58:05.845106 <30>[ 12.604628] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10968 00:58:05.858219 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 12.617061] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10969 00:58:05.861911 l Module drm...
10970 00:58:05.884920 <30>[ 12.644595] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10971 00:58:05.894716 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10972 00:58:05.917813 <30>[ 12.677125] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10973 00:58:05.924452 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10974 00:58:05.948900 <30>[ 12.708558] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10975 00:58:05.955677 Starting [0;1;39mmodpr<6>[ 12.719037] fuse: init (API version 7.37)
10976 00:58:05.962101 obe@loop.ser…e[0m - Load Kernel Module loop...
10977 00:58:05.989337 <30>[ 12.748663] systemd[1]: Starting systemd-journald.service - Journal Service...
10978 00:58:05.995956 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10979 00:58:06.049062 <30>[ 12.808132] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10980 00:58:06.055299 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10981 00:58:06.082916 <30>[ 12.839013] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10982 00:58:06.089304 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10983 00:58:06.112111 <30>[ 12.871752] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10984 00:58:06.122030 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10985 00:58:06.147879 <30>[ 12.906322] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10986 00:58:06.157502 <3>[ 12.913307] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 00:58:06.164224 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10988 00:58:06.185518 <3>[ 12.944888] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 00:58:06.192079 <30>[ 12.948869] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10990 00:58:06.202217 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10991 00:58:06.220356 <30>[ 12.979682] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10992 00:58:06.230266 <3>[ 12.985097] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10993 00:58:06.237182 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10994 00:58:06.255966 <30>[ 13.015363] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10995 00:58:06.262591 <3>[ 13.019168] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 00:58:06.272897 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10997 00:58:06.292709 <30>[ 13.051853] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10998 00:58:06.302462 <3>[ 13.055431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 00:58:06.308963 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11000 00:58:06.329264 <30>[ 13.088010] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11001 00:58:06.335707 <3>[ 13.091177] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 00:58:06.345434 <30>[ 13.096030] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11003 00:58:06.352208 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11004 00:58:06.365119 <3>[ 13.124608] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11005 00:58:06.376131 <30>[ 13.135543] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11006 00:58:06.382921 <30>[ 13.143552] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11007 00:58:06.396444 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 13.155432] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11008 00:58:06.399749 m_mod.s…e[0m - Load Kernel Module dm_mod.
11009 00:58:06.418458 <30>[ 13.180621] systemd[1]: modprobe@drm.service: Deactivated successfully.
11010 00:58:06.428371 <3>[ 13.187935] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 00:58:06.434852 <30>[ 13.188490] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11012 00:58:06.445394 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11013 00:58:06.460533 <3>[ 13.220282] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11014 00:58:06.472062 <30>[ 13.231417] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11015 00:58:06.481980 <30>[ 13.240086] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11016 00:58:06.492008 [[0;32m OK [<3>[ 13.250509] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11017 00:58:06.498515 0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11018 00:58:06.517248 <30>[ 13.276715] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11019 00:58:06.523882 <3>[ 13.282422] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11020 00:58:06.533804 <30>[ 13.284661] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11021 00:58:06.540435 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11022 00:58:06.557882 <3>[ 13.317338] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11023 00:58:06.569174 <30>[ 13.328809] systemd[1]: modprobe@loop.service: Deactivated successfully.
11024 00:58:06.576311 <30>[ 13.336807] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11025 00:58:06.586320 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11026 00:58:06.599978 <3>[ 13.359179] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11027 00:58:06.609498 <3>[ 13.360169] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
11028 00:58:06.623053 <4>[ 13.367985] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11029 00:58:06.630003 <3>[ 13.367990] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11030 00:58:06.639882 <30>[ 13.369437] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11031 00:58:06.649923 <3>[ 13.400118] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11032 00:58:06.656423 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11033 00:58:06.681466 <30>[ 13.437322] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
11034 00:58:06.688328 <3>[ 13.446714] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11035 00:58:06.698247 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11036 00:58:06.717151 <30>[ 13.476391] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
11037 00:58:06.727402 <3>[ 13.482887] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11038 00:58:06.734045 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11039 00:58:06.753736 <30>[ 13.512389] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
11040 00:58:06.760099 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11041 00:58:06.781667 <30>[ 13.540613] systemd[1]: Reached target network-pre.target - Preparation for Network.
11042 00:58:06.788480 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11043 00:58:06.847757 <30>[ 13.607361] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
11044 00:58:06.857743 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11045 00:58:06.878141 <30>[ 13.637694] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
11046 00:58:06.888064 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11047 00:58:06.906835 <30>[ 13.663120] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
11048 00:58:06.923763 <30>[ 13.676744] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
11049 00:58:06.938041 <30>[ 13.697780] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
11050 00:58:06.944828 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11051 00:58:06.970743 <30>[ 13.726764] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
11052 00:58:06.984971 <30>[ 13.744733] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
11053 00:58:06.991672 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11054 00:58:07.060315 <30>[ 13.819920] systemd[1]: Starting systemd-sysusers.service - Create System Users...
11055 00:58:07.066748 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11056 00:58:07.095816 <30>[ 13.855452] systemd[1]: Started systemd-journald.service - Journal Service.
11057 00:58:07.102584 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11058 00:58:07.122795 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11059 00:58:07.140139 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11060 00:58:07.156701 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11061 00:58:07.177239 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11062 00:58:07.197046 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11063 00:58:07.268739 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11064 00:58:07.295457 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11065 00:58:07.355646 <46>[ 14.115149] systemd-journald[312]: Received client request to flush runtime journal.
11066 00:58:08.030727 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11067 00:58:08.047686 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11068 00:58:08.063274 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11069 00:58:08.156306 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11070 00:58:08.776915 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11071 00:58:08.824021 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11072 00:58:08.893198 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11073 00:58:08.957420 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11074 00:58:09.020345 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11075 00:58:09.325233 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11076 00:58:09.360288 <6>[ 16.123496] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11077 00:58:09.389172 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11078 00:58:09.444294 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11079 00:58:09.509668 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11080 00:58:09.528036 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11081 00:58:09.599992 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11082 00:58:09.625618 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11083 00:58:09.644835 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11084 00:58:09.687962 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11085 00:58:09.776083 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11086 00:58:09.803169 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11087 00:58:09.819390 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11088 00:58:09.853692 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11089 00:58:09.972258 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11090 00:58:09.995463 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11091 00:58:10.015498 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11092 00:58:10.031134 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11093 00:58:10.056248 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11094 00:58:10.078600 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11095 00:58:10.095384 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11096 00:58:10.114489 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11097 00:58:10.134476 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11098 00:58:10.151158 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11099 00:58:10.169746 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11100 00:58:10.186895 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11101 00:58:10.193381 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11102 00:58:10.232609 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11103 00:58:10.340705 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11104 00:58:10.429002 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11105 00:58:10.454066 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11106 00:58:10.631941 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11107 00:58:10.680315 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11108 00:58:10.701866 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11109 00:58:10.723354 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11110 00:58:10.744130 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11111 00:58:10.778641 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11112 00:58:10.798106 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11113 00:58:10.817806 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11114 00:58:10.836335 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11115 00:58:10.881569 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11116 00:58:10.952814 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11117 00:58:11.041452
11118 00:58:11.044614 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11119 00:58:11.044712
11120 00:58:11.047577 debian-bookworm-arm64 login: root (automatic login)
11121 00:58:11.047664
11122 00:58:11.343258 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
11123 00:58:11.343458
11124 00:58:11.349713 The programs included with the Debian GNU/Linux system are free software;
11125 00:58:11.356674 the exact distribution terms for each program are described in the
11126 00:58:11.359562 individual files in /usr/share/doc/*/copyright.
11127 00:58:11.359654
11128 00:58:11.366362 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11129 00:58:11.369589 permitted by applicable law.
11130 00:58:12.518941 Matched prompt #10: / #
11132 00:58:12.519232 Setting prompt string to ['/ #']
11133 00:58:12.519328 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11135 00:58:12.519522 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11136 00:58:12.519611 start: 2.2.6 expect-shell-connection (timeout 00:03:07) [common]
11137 00:58:12.519688 Setting prompt string to ['/ #']
11138 00:58:12.519751 Forcing a shell prompt, looking for ['/ #']
11140 00:58:12.569989 / #
11141 00:58:12.570205 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11142 00:58:12.570330 Waiting using forced prompt support (timeout 00:02:30)
11143 00:58:12.575014
11144 00:58:12.575297 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11145 00:58:12.575394 start: 2.2.7 export-device-env (timeout 00:03:07) [common]
11147 00:58:12.675790 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368594/extract-nfsrootfs-bv0vk0cp'
11148 00:58:12.681214 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368594/extract-nfsrootfs-bv0vk0cp'
11150 00:58:12.781837 / # export NFS_SERVER_IP='192.168.201.1'
11151 00:58:12.787094 export NFS_SERVER_IP='192.168.201.1'
11152 00:58:12.787419 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11153 00:58:12.787524 end: 2.2 depthcharge-retry (duration 00:01:54) [common]
11154 00:58:12.787619 end: 2 depthcharge-action (duration 00:01:54) [common]
11155 00:58:12.787711 start: 3 lava-test-retry (timeout 00:07:25) [common]
11156 00:58:12.787800 start: 3.1 lava-test-shell (timeout 00:07:25) [common]
11157 00:58:12.787877 Using namespace: common
11159 00:58:12.888265 / # #
11160 00:58:12.888458 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11161 00:58:12.893444 #
11162 00:58:12.893726 Using /lava-14368594
11164 00:58:12.994073 / # export SHELL=/bin/bash
11165 00:58:12.999379 export SHELL=/bin/bash
11167 00:58:13.099979 / # . /lava-14368594/environment
11168 00:58:13.105267 . /lava-14368594/environment
11170 00:58:13.212225 / # /lava-14368594/bin/lava-test-runner /lava-14368594/0
11171 00:58:13.212416 Test shell timeout: 10s (minimum of the action and connection timeout)
11172 00:58:13.217592 /lava-14368594/bin/lava-test-runner /lava-14368594/0
11173 00:58:13.510379 + export TESTRUN_ID=0_timesync-off
11174 00:58:13.513736 + TESTRUN_ID=0_timesync-off
11175 00:58:13.517427 + cd /lava-14368594/0/tests/0_timesync-off
11176 00:58:13.520193 ++ cat uuid
11177 00:58:13.525852 + UUID=14368594_1.6.2.3.1
11178 00:58:13.525938 + set +x
11179 00:58:13.532350 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368594_1.6.2.3.1>
11180 00:58:13.532617 Received signal: <STARTRUN> 0_timesync-off 14368594_1.6.2.3.1
11181 00:58:13.532698 Starting test lava.0_timesync-off (14368594_1.6.2.3.1)
11182 00:58:13.532826 Skipping test definition patterns.
11183 00:58:13.535790 + systemctl stop systemd-timesyncd
11184 00:58:13.609871 + set +x
11185 00:58:13.613123 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368594_1.6.2.3.1>
11186 00:58:13.613394 Received signal: <ENDRUN> 0_timesync-off 14368594_1.6.2.3.1
11187 00:58:13.613484 Ending use of test pattern.
11188 00:58:13.613548 Ending test lava.0_timesync-off (14368594_1.6.2.3.1), duration 0.08
11190 00:58:13.691452 + export TESTRUN_ID=1_kselftest-arm64
11191 00:58:13.691606 + TESTRUN_ID=1_kselftest-arm64
11192 00:58:13.697534 + cd /lava-14368594/0/tests/1_kselftest-arm64
11193 00:58:13.697621 ++ cat uuid
11194 00:58:13.703428 + UUID=14368594_1.6.2.3.5
11195 00:58:13.703514 + set +x
11196 00:58:13.709843 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14368594_1.6.2.3.5>
11197 00:58:13.710106 Received signal: <STARTRUN> 1_kselftest-arm64 14368594_1.6.2.3.5
11198 00:58:13.710219 Starting test lava.1_kselftest-arm64 (14368594_1.6.2.3.5)
11199 00:58:13.710335 Skipping test definition patterns.
11200 00:58:13.713559 + cd ./automated/linux/kselftest/
11201 00:58:13.742713 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11202 00:58:13.786726 INFO: install_deps skipped
11203 00:58:14.296732 --2024-06-16 00:58:13-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11204 00:58:14.314852 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11205 00:58:14.440660 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11206 00:58:14.572746 HTTP request sent, awaiting response... 200 OK
11207 00:58:14.575962 Length: 1647948 (1.6M) [application/octet-stream]
11208 00:58:14.579184 Saving to: 'kselftest_armhf.tar.gz'
11209 00:58:14.579272
11210 00:58:14.579338
11211 00:58:14.818505 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11212 00:58:15.069026 kselftest_armhf.tar 3%[ ] 50.15K 205KB/s
11213 00:58:15.366901 kselftest_armhf.tar 13%[=> ] 219.84K 444KB/s
11214 00:58:15.493528 kselftest_armhf.tar 51%[=========> ] 826.96K 1.02MB/s
11215 00:58:15.499759 kselftest_armhf.tar 100%[===================>] 1.57M 1.71MB/s in 0.9s
11216 00:58:15.499863
11217 00:58:15.644798 2024-06-16 00:58:15 (1.71 MB/s) - 'kselftest_armhf.tar.gz' saved [1647948/1647948]
11218 00:58:15.644976
11219 00:58:21.022962 skiplist:
11220 00:58:21.026585 ========================================
11221 00:58:21.029750 ========================================
11222 00:58:21.093404 arm64:tags_test
11223 00:58:21.096681 arm64:run_tags_test.sh
11224 00:58:21.097325 arm64:fake_sigreturn_bad_magic
11225 00:58:21.099847 arm64:fake_sigreturn_bad_size
11226 00:58:21.103257 arm64:fake_sigreturn_bad_size_for_magic0
11227 00:58:21.106667 arm64:fake_sigreturn_duplicated_fpsimd
11228 00:58:21.109718 arm64:fake_sigreturn_misaligned_sp
11229 00:58:21.112914 arm64:fake_sigreturn_missing_fpsimd
11230 00:58:21.116360 arm64:fake_sigreturn_sme_change_vl
11231 00:58:21.119882 arm64:fake_sigreturn_sve_change_vl
11232 00:58:21.123049 arm64:mangle_pstate_invalid_compat_toggle
11233 00:58:21.126280 arm64:mangle_pstate_invalid_daif_bits
11234 00:58:21.129799 arm64:mangle_pstate_invalid_mode_el1h
11235 00:58:21.132765 arm64:mangle_pstate_invalid_mode_el1t
11236 00:58:21.136015 arm64:mangle_pstate_invalid_mode_el2h
11237 00:58:21.139465 arm64:mangle_pstate_invalid_mode_el2t
11238 00:58:21.142805 arm64:mangle_pstate_invalid_mode_el3h
11239 00:58:21.149347 arm64:mangle_pstate_invalid_mode_el3t
11240 00:58:21.149772 arm64:sme_trap_no_sm
11241 00:58:21.152774 arm64:sme_trap_non_streaming
11242 00:58:21.153330 arm64:sme_trap_za
11243 00:58:21.156262 arm64:sme_vl
11244 00:58:21.156840 arm64:ssve_regs
11245 00:58:21.159335 arm64:sve_regs
11246 00:58:21.159898 arm64:sve_vl
11247 00:58:21.160404 arm64:za_no_regs
11248 00:58:21.162735 arm64:za_regs
11249 00:58:21.163159 arm64:pac
11250 00:58:21.165931 arm64:fp-stress
11251 00:58:21.166390 arm64:sve-ptrace
11252 00:58:21.168922 arm64:sve-probe-vls
11253 00:58:21.169340 arm64:vec-syscfg
11254 00:58:21.169672 arm64:za-fork
11255 00:58:21.172225 arm64:za-ptrace
11256 00:58:21.175952 arm64:check_buffer_fill
11257 00:58:21.176399 arm64:check_child_memory
11258 00:58:21.178985 arm64:check_gcr_el1_cswitch
11259 00:58:21.182145 arm64:check_ksm_options
11260 00:58:21.182631 arm64:check_mmap_options
11261 00:58:21.185556 arm64:check_prctl
11262 00:58:21.188746 arm64:check_tags_inclusion
11263 00:58:21.189342 arm64:check_user_mem
11264 00:58:21.192266 arm64:btitest
11265 00:58:21.192804 arm64:nobtitest
11266 00:58:21.193269 arm64:hwcap
11267 00:58:21.195546 arm64:ptrace
11268 00:58:21.195995 arm64:syscall-abi
11269 00:58:21.198747 arm64:tpidr2
11270 00:58:21.202573 ============== Tests to run ===============
11271 00:58:21.202995 arm64:tags_test
11272 00:58:21.205380 arm64:run_tags_test.sh
11273 00:58:21.208854 arm64:fake_sigreturn_bad_magic
11274 00:58:21.211930 arm64:fake_sigreturn_bad_size
11275 00:58:21.215439 arm64:fake_sigreturn_bad_size_for_magic0
11276 00:58:21.218543 arm64:fake_sigreturn_duplicated_fpsimd
11277 00:58:21.221924 arm64:fake_sigreturn_misaligned_sp
11278 00:58:21.225634 arm64:fake_sigreturn_missing_fpsimd
11279 00:58:21.228468 arm64:fake_sigreturn_sme_change_vl
11280 00:58:21.232169 arm64:fake_sigreturn_sve_change_vl
11281 00:58:21.234718 arm64:mangle_pstate_invalid_compat_toggle
11282 00:58:21.238298 arm64:mangle_pstate_invalid_daif_bits
11283 00:58:21.241872 arm64:mangle_pstate_invalid_mode_el1h
11284 00:58:21.244906 arm64:mangle_pstate_invalid_mode_el1t
11285 00:58:21.248251 arm64:mangle_pstate_invalid_mode_el2h
11286 00:58:21.251367 arm64:mangle_pstate_invalid_mode_el2t
11287 00:58:21.254777 arm64:mangle_pstate_invalid_mode_el3h
11288 00:58:21.257985 arm64:mangle_pstate_invalid_mode_el3t
11289 00:58:21.258493 arm64:sme_trap_no_sm
11290 00:58:21.261591 arm64:sme_trap_non_streaming
11291 00:58:21.264743 arm64:sme_trap_za
11292 00:58:21.265231 arm64:sme_vl
11293 00:58:21.268115 arm64:ssve_regs
11294 00:58:21.268533 arm64:sve_regs
11295 00:58:21.268862 arm64:sve_vl
11296 00:58:21.271307 arm64:za_no_regs
11297 00:58:21.271781 arm64:za_regs
11298 00:58:21.272112 arm64:pac
11299 00:58:21.274678 arm64:fp-stress
11300 00:58:21.275097 arm64:sve-ptrace
11301 00:58:21.277943 arm64:sve-probe-vls
11302 00:58:21.278409 arm64:vec-syscfg
11303 00:58:21.281328 arm64:za-fork
11304 00:58:21.282048 arm64:za-ptrace
11305 00:58:21.284482 arm64:check_buffer_fill
11306 00:58:21.287543 arm64:check_child_memory
11307 00:58:21.288009 arm64:check_gcr_el1_cswitch
11308 00:58:21.290848 arm64:check_ksm_options
11309 00:58:21.294648 arm64:check_mmap_options
11310 00:58:21.295144 arm64:check_prctl
11311 00:58:21.297513 arm64:check_tags_inclusion
11312 00:58:21.301105 arm64:check_user_mem
11313 00:58:21.301521 arm64:btitest
11314 00:58:21.301850 arm64:nobtitest
11315 00:58:21.304052 arm64:hwcap
11316 00:58:21.304468 arm64:ptrace
11317 00:58:21.307611 arm64:syscall-abi
11318 00:58:21.308305 arm64:tpidr2
11319 00:58:21.310773 ===========End Tests to run ===============
11320 00:58:21.314050 shardfile-arm64 pass
11321 00:58:21.610848 <12>[ 28.375241] kselftest: Running tests in arm64
11322 00:58:21.622533 TAP version 13
11323 00:58:21.640809 1..48
11324 00:58:21.662962 # selftests: arm64: tags_test
11325 00:58:22.158252 ok 1 selftests: arm64: tags_test
11326 00:58:22.177412 # selftests: arm64: run_tags_test.sh
11327 00:58:22.244065 # --------------------
11328 00:58:22.246846 # running tags test
11329 00:58:22.247366 # --------------------
11330 00:58:22.250439 # [PASS]
11331 00:58:22.253756 ok 2 selftests: arm64: run_tags_test.sh
11332 00:58:22.271220 # selftests: arm64: fake_sigreturn_bad_magic
11333 00:58:22.336959 # Registered handlers for all signals.
11334 00:58:22.337511 # Detected MINSTKSIGSZ:4720
11335 00:58:22.340215 # Testcase initialized.
11336 00:58:22.343222 # uc context validated.
11337 00:58:22.346377 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11338 00:58:22.350189 # Handled SIG_COPYCTX
11339 00:58:22.350626 # Available space:3568
11340 00:58:22.356396 # Using badly built context - ERR: BAD MAGIC !
11341 00:58:22.363365 # SIG_OK -- SP:0xFFFFC97E4D50 si_addr@:0xffffc97e4d50 si_code:2 token@:0xffffc97e3af0 offset:-4704
11342 00:58:22.366000 # ==>> completed. PASS(1)
11343 00:58:22.373075 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11344 00:58:22.379634 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC97E3AF0
11345 00:58:22.385945 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11346 00:58:22.389483 # selftests: arm64: fake_sigreturn_bad_size
11347 00:58:22.417875 # Registered handlers for all signals.
11348 00:58:22.418446 # Detected MINSTKSIGSZ:4720
11349 00:58:22.420976 # Testcase initialized.
11350 00:58:22.424088 # uc context validated.
11351 00:58:22.427835 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11352 00:58:22.430893 # Handled SIG_COPYCTX
11353 00:58:22.431312 # Available space:3568
11354 00:58:22.434235 # uc context validated.
11355 00:58:22.440957 # Using badly built context - ERR: Bad size for esr_context
11356 00:58:22.447522 # SIG_OK -- SP:0xFFFFD968F960 si_addr@:0xffffd968f960 si_code:2 token@:0xffffd968e700 offset:-4704
11357 00:58:22.450785 # ==>> completed. PASS(1)
11358 00:58:22.457263 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11359 00:58:22.464271 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD968E700
11360 00:58:22.467509 ok 4 selftests: arm64: fake_sigreturn_bad_size
11361 00:58:22.473561 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11362 00:58:22.516008 # Registered handlers for all signals.
11363 00:58:22.516525 # Detected MINSTKSIGSZ:4720
11364 00:58:22.519137 # Testcase initialized.
11365 00:58:22.522610 # uc context validated.
11366 00:58:22.525702 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11367 00:58:22.529018 # Handled SIG_COPYCTX
11368 00:58:22.529468 # Available space:3568
11369 00:58:22.535736 # Using badly built context - ERR: Bad size for terminator
11370 00:58:22.545811 # SIG_OK -- SP:0xFFFFE7A9A230 si_addr@:0xffffe7a9a230 si_code:2 token@:0xffffe7a98fd0 offset:-4704
11371 00:58:22.546293 # ==>> completed. PASS(1)
11372 00:58:22.555866 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11373 00:58:22.562439 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE7A98FD0
11374 00:58:22.565386 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11375 00:58:22.571917 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11376 00:58:22.617387 # Registered handlers for all signals.
11377 00:58:22.617992 # Detected MINSTKSIGSZ:4720
11378 00:58:22.620498 # Testcase initialized.
11379 00:58:22.623883 # uc context validated.
11380 00:58:22.627135 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11381 00:58:22.630449 # Handled SIG_COPYCTX
11382 00:58:22.630912 # Available space:3568
11383 00:58:22.637118 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11384 00:58:22.646853 # SIG_OK -- SP:0xFFFFFF039760 si_addr@:0xffffff039760 si_code:2 token@:0xffffff038500 offset:-4704
11385 00:58:22.647294 # ==>> completed. PASS(1)
11386 00:58:22.656850 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11387 00:58:22.663715 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFF038500
11388 00:58:22.666810 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11389 00:58:22.670078 # selftests: arm64: fake_sigreturn_misaligned_sp
11390 00:58:22.705465 # Registered handlers for all signals.
11391 00:58:22.706042 # Detected MINSTKSIGSZ:4720
11392 00:58:22.708877 # Testcase initialized.
11393 00:58:22.711961 # uc context validated.
11394 00:58:22.715063 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11395 00:58:22.718256 # Handled SIG_COPYCTX
11396 00:58:22.725321 # SIG_OK -- SP:0xFFFFD7256843 si_addr@:0xffffd7256843 si_code:2 token@:0xffffd7256843 offset:0
11397 00:58:22.728427 # ==>> completed. PASS(1)
11398 00:58:22.735049 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11399 00:58:22.741248 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD7256843
11400 00:58:22.748025 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11401 00:58:22.751157 # selftests: arm64: fake_sigreturn_missing_fpsimd
11402 00:58:22.789120 # Registered handlers for all signals.
11403 00:58:22.789682 # Detected MINSTKSIGSZ:4720
11404 00:58:22.792543 # Testcase initialized.
11405 00:58:22.796068 # uc context validated.
11406 00:58:22.799695 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11407 00:58:22.802271 # Handled SIG_COPYCTX
11408 00:58:22.805986 # Mangling template header. Spare space:4096
11409 00:58:22.809031 # Using badly built context - ERR: Missing FPSIMD
11410 00:58:22.818743 # SIG_OK -- SP:0xFFFFC8813160 si_addr@:0xffffc8813160 si_code:2 token@:0xffffc8811f00 offset:-4704
11411 00:58:22.822127 # ==>> completed. PASS(1)
11412 00:58:22.828933 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11413 00:58:22.835131 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC8811F00
11414 00:58:22.838523 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11415 00:58:22.845221 # selftests: arm64: fake_sigreturn_sme_change_vl
11416 00:58:22.869360 # Registered handlers for all signals.
11417 00:58:22.869934 # Detected MINSTKSIGSZ:4720
11418 00:58:22.872673 # ==>> completed. SKIP.
11419 00:58:22.879858 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11420 00:58:22.882566 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11421 00:58:22.893704 # selftests: arm64: fake_sigreturn_sve_change_vl
11422 00:58:22.964466 # Registered handlers for all signals.
11423 00:58:22.965024 # Detected MINSTKSIGSZ:4720
11424 00:58:22.968260 # ==>> completed. SKIP.
11425 00:58:22.974540 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11426 00:58:22.977759 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11427 00:58:22.987556 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11428 00:58:23.057164 # Registered handlers for all signals.
11429 00:58:23.057352 # Detected MINSTKSIGSZ:4720
11430 00:58:23.060789 # Testcase initialized.
11431 00:58:23.063866 # uc context validated.
11432 00:58:23.063949 # Handled SIG_TRIG
11433 00:58:23.073742 # SIG_OK -- SP:0xFFFFF4B3A4A0 si_addr@:0xfffff4b3a4a0 si_code:2 token@:(nil) offset:-281474787157152
11434 00:58:23.077301 # ==>> completed. PASS(1)
11435 00:58:23.083833 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11436 00:58:23.090524 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11437 00:58:23.093572 # selftests: arm64: mangle_pstate_invalid_daif_bits
11438 00:58:23.128867 # Registered handlers for all signals.
11439 00:58:23.129016 # Detected MINSTKSIGSZ:4720
11440 00:58:23.131656 # Testcase initialized.
11441 00:58:23.134981 # uc context validated.
11442 00:58:23.135064 # Handled SIG_TRIG
11443 00:58:23.144920 # SIG_OK -- SP:0xFFFFECA8CDA0 si_addr@:0xffffeca8cda0 si_code:2 token@:(nil) offset:-281474652229024
11444 00:58:23.148380 # ==>> completed. PASS(1)
11445 00:58:23.154801 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11446 00:58:23.158028 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11447 00:58:23.164708 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11448 00:58:23.230894 # Registered handlers for all signals.
11449 00:58:23.231417 # Detected MINSTKSIGSZ:4720
11450 00:58:23.234458 # Testcase initialized.
11451 00:58:23.237694 # uc context validated.
11452 00:58:23.238212 # Handled SIG_TRIG
11453 00:58:23.247263 # SIG_OK -- SP:0xFFFFE471A600 si_addr@:0xffffe471a600 si_code:2 token@:(nil) offset:-281474514396672
11454 00:58:23.250958 # ==>> completed. PASS(1)
11455 00:58:23.256981 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11456 00:58:23.260646 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11457 00:58:23.267019 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11458 00:58:23.320424 # Registered handlers for all signals.
11459 00:58:23.320625 # Detected MINSTKSIGSZ:4720
11460 00:58:23.323449 # Testcase initialized.
11461 00:58:23.326825 # uc context validated.
11462 00:58:23.326924 # Handled SIG_TRIG
11463 00:58:23.336609 # SIG_OK -- SP:0xFFFFDCF22A10 si_addr@:0xffffdcf22a10 si_code:2 token@:(nil) offset:-281474388601360
11464 00:58:23.340183 # ==>> completed. PASS(1)
11465 00:58:23.346536 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11466 00:58:23.350028 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11467 00:58:23.356687 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11468 00:58:23.405907 # Registered handlers for all signals.
11469 00:58:23.406438 # Detected MINSTKSIGSZ:4720
11470 00:58:23.409044 # Testcase initialized.
11471 00:58:23.412379 # uc context validated.
11472 00:58:23.412813 # Handled SIG_TRIG
11473 00:58:23.422306 # SIG_OK -- SP:0xFFFFCE058620 si_addr@:0xffffce058620 si_code:2 token@:(nil) offset:-281474138211872
11474 00:58:23.425800 # ==>> completed. PASS(1)
11475 00:58:23.432595 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11476 00:58:23.435648 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11477 00:58:23.442484 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11478 00:58:23.489658 # Registered handlers for all signals.
11479 00:58:23.490450 # Detected MINSTKSIGSZ:4720
11480 00:58:23.493240 # Testcase initialized.
11481 00:58:23.496212 # uc context validated.
11482 00:58:23.496827 # Handled SIG_TRIG
11483 00:58:23.505932 # SIG_OK -- SP:0xFFFFC90BD9E0 si_addr@:0xffffc90bd9e0 si_code:2 token@:(nil) offset:-281474054740448
11484 00:58:23.509278 # ==>> completed. PASS(1)
11485 00:58:23.515944 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11486 00:58:23.519243 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11487 00:58:23.525580 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11488 00:58:23.597241 # Registered handlers for all signals.
11489 00:58:23.597834 # Detected MINSTKSIGSZ:4720
11490 00:58:23.600488 # Testcase initialized.
11491 00:58:23.603684 # uc context validated.
11492 00:58:23.604425 # Handled SIG_TRIG
11493 00:58:23.613539 # SIG_OK -- SP:0xFFFFD2DD6B70 si_addr@:0xffffd2dd6b70 si_code:2 token@:(nil) offset:-281474219469680
11494 00:58:23.616814 # ==>> completed. PASS(1)
11495 00:58:23.623489 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11496 00:58:23.627178 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11497 00:58:23.633520 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11498 00:58:23.697127 # Registered handlers for all signals.
11499 00:58:23.697695 # Detected MINSTKSIGSZ:4720
11500 00:58:23.699842 # Testcase initialized.
11501 00:58:23.703565 # uc context validated.
11502 00:58:23.704061 # Handled SIG_TRIG
11503 00:58:23.713041 # SIG_OK -- SP:0xFFFFEF631340 si_addr@:0xffffef631340 si_code:2 token@:(nil) offset:-281474697990976
11504 00:58:23.716496 # ==>> completed. PASS(1)
11505 00:58:23.723174 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11506 00:58:23.726364 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11507 00:58:23.729869 # selftests: arm64: sme_trap_no_sm
11508 00:58:23.796606 # Registered handlers for all signals.
11509 00:58:23.797181 # Detected MINSTKSIGSZ:4720
11510 00:58:23.799989 # ==>> completed. SKIP.
11511 00:58:23.809606 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11512 00:58:23.813091 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11513 00:58:23.820712 # selftests: arm64: sme_trap_non_streaming
11514 00:58:23.895378 # Registered handlers for all signals.
11515 00:58:23.895930 # Detected MINSTKSIGSZ:4720
11516 00:58:23.898943 # ==>> completed. SKIP.
11517 00:58:23.908545 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11518 00:58:23.915076 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11519 00:58:23.922293 # selftests: arm64: sme_trap_za
11520 00:58:23.998916 # Registered handlers for all signals.
11521 00:58:23.999484 # Detected MINSTKSIGSZ:4720
11522 00:58:24.002083 # Testcase initialized.
11523 00:58:24.012247 # SIG_OK -- SP:0xFFFFF0C7B2F0 si_addr@:0xaaaacb5a2510 si_code:1 token@:(nil) offset:-187650532844816
11524 00:58:24.012720 # ==>> completed. PASS(1)
11525 00:58:24.021917 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11526 00:58:24.025288 ok 21 selftests: arm64: sme_trap_za
11527 00:58:24.025758 # selftests: arm64: sme_vl
11528 00:58:24.083602 # Registered handlers for all signals.
11529 00:58:24.084196 # Detected MINSTKSIGSZ:4720
11530 00:58:24.086691 # ==>> completed. SKIP.
11531 00:58:24.093145 # # SME VL :: Check that we get the right SME VL reported
11532 00:58:24.096539 ok 22 selftests: arm64: sme_vl # SKIP
11533 00:58:24.103248 # selftests: arm64: ssve_regs
11534 00:58:24.186856 # Registered handlers for all signals.
11535 00:58:24.187451 # Detected MINSTKSIGSZ:4720
11536 00:58:24.189955 # ==>> completed. SKIP.
11537 00:58:24.196826 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11538 00:58:24.202987 ok 23 selftests: arm64: ssve_regs # SKIP
11539 00:58:24.207466 # selftests: arm64: sve_regs
11540 00:58:24.293711 # Registered handlers for all signals.
11541 00:58:24.294316 # Detected MINSTKSIGSZ:4720
11542 00:58:24.297212 # ==>> completed. SKIP.
11543 00:58:24.303529 # # SVE registers :: Check that we get the right SVE registers reported
11544 00:58:24.306641 ok 24 selftests: arm64: sve_regs # SKIP
11545 00:58:24.313442 # selftests: arm64: sve_vl
11546 00:58:24.392227 # Registered handlers for all signals.
11547 00:58:24.392922 # Detected MINSTKSIGSZ:4720
11548 00:58:24.395594 # ==>> completed. SKIP.
11549 00:58:24.402091 # # SVE VL :: Check that we get the right SVE VL reported
11550 00:58:24.405346 ok 25 selftests: arm64: sve_vl # SKIP
11551 00:58:24.411731 # selftests: arm64: za_no_regs
11552 00:58:24.473857 # Registered handlers for all signals.
11553 00:58:24.474567 # Detected MINSTKSIGSZ:4720
11554 00:58:24.477598 # ==>> completed. SKIP.
11555 00:58:24.483944 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11556 00:58:24.486964 ok 26 selftests: arm64: za_no_regs # SKIP
11557 00:58:24.493686 # selftests: arm64: za_regs
11558 00:58:24.571850 # Registered handlers for all signals.
11559 00:58:24.572426 # Detected MINSTKSIGSZ:4720
11560 00:58:24.574599 # ==>> completed. SKIP.
11561 00:58:24.581207 # # ZA register :: Check that we get the right ZA registers reported
11562 00:58:24.584368 ok 27 selftests: arm64: za_regs # SKIP
11563 00:58:24.592615 # selftests: arm64: pac
11564 00:58:24.665743 # TAP version 13
11565 00:58:24.666466 # 1..7
11566 00:58:24.668907 # # Starting 7 tests from 1 test cases.
11567 00:58:24.672122 # # RUN global.corrupt_pac ...
11568 00:58:24.675617 # # SKIP PAUTH not enabled
11569 00:58:24.678835 # # OK global.corrupt_pac
11570 00:58:24.682567 # ok 1 # SKIP PAUTH not enabled
11571 00:58:24.688479 # # RUN global.pac_instructions_not_nop ...
11572 00:58:24.691895 # # SKIP PAUTH not enabled
11573 00:58:24.694957 # # OK global.pac_instructions_not_nop
11574 00:58:24.698313 # ok 2 # SKIP PAUTH not enabled
11575 00:58:24.704964 # # RUN global.pac_instructions_not_nop_generic ...
11576 00:58:24.708355 # # SKIP Generic PAUTH not enabled
11577 00:58:24.711793 # # OK global.pac_instructions_not_nop_generic
11578 00:58:24.718010 # ok 3 # SKIP Generic PAUTH not enabled
11579 00:58:24.721568 # # RUN global.single_thread_different_keys ...
11580 00:58:24.724700 # # SKIP PAUTH not enabled
11581 00:58:24.731667 # # OK global.single_thread_different_keys
11582 00:58:24.732172 # ok 4 # SKIP PAUTH not enabled
11583 00:58:24.737926 # # RUN global.exec_changed_keys ...
11584 00:58:24.741342 # # SKIP PAUTH not enabled
11585 00:58:24.744899 # # OK global.exec_changed_keys
11586 00:58:24.748273 # ok 5 # SKIP PAUTH not enabled
11587 00:58:24.751006 # # RUN global.context_switch_keep_keys ...
11588 00:58:24.754490 # # SKIP PAUTH not enabled
11589 00:58:24.761282 # # OK global.context_switch_keep_keys
11590 00:58:24.764451 # ok 6 # SKIP PAUTH not enabled
11591 00:58:24.767728 # # RUN global.context_switch_keep_keys_generic ...
11592 00:58:24.770769 # # SKIP Generic PAUTH not enabled
11593 00:58:24.777344 # # OK global.context_switch_keep_keys_generic
11594 00:58:24.780560 # ok 7 # SKIP Generic PAUTH not enabled
11595 00:58:24.784087 # # PASSED: 7 / 7 tests passed.
11596 00:58:24.790510 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11597 00:58:24.790978 ok 28 selftests: arm64: pac
11598 00:58:24.794082 # selftests: arm64: fp-stress
11599 00:58:31.198602 <6>[ 37.966769] vpu: disabling
11600 00:58:31.201766 <6>[ 37.969819] vproc2: disabling
11601 00:58:31.204900 <6>[ 37.973308] vproc1: disabling
11602 00:58:31.208262 <6>[ 37.976595] vaud18: disabling
11603 00:58:31.214768 <6>[ 37.980028] vsram_others: disabling
11604 00:58:31.218099 <6>[ 37.983924] va09: disabling
11605 00:58:31.221822 <6>[ 37.987041] vsram_md: disabling
11606 00:58:31.224827 <6>[ 37.990541] Vgpu: disabling
11607 00:58:34.764971 # TAP version 13
11608 00:58:34.768363 # 1..16
11609 00:58:34.771805 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11610 00:58:34.771917 # # Will run for 10s
11611 00:58:34.774957 # # Started FPSIMD-0-0
11612 00:58:34.775058 # # Started FPSIMD-0-1
11613 00:58:34.778067 # # Started FPSIMD-1-0
11614 00:58:34.781585 # # Started FPSIMD-1-1
11615 00:58:34.781689 # # Started FPSIMD-2-0
11616 00:58:34.784903 # # Started FPSIMD-2-1
11617 00:58:34.787990 # # Started FPSIMD-3-0
11618 00:58:34.788100 # # Started FPSIMD-3-1
11619 00:58:34.791525 # # Started FPSIMD-4-0
11620 00:58:34.794491 # # Started FPSIMD-4-1
11621 00:58:34.794568 # # Started FPSIMD-5-0
11622 00:58:34.797956 # # Started FPSIMD-5-1
11623 00:58:34.798058 # # Started FPSIMD-6-0
11624 00:58:34.801271 # # Started FPSIMD-6-1
11625 00:58:34.804472 # # Started FPSIMD-7-0
11626 00:58:34.804582 # # Started FPSIMD-7-1
11627 00:58:34.807905 # # FPSIMD-1-0: Vector length: 128 bits
11628 00:58:34.810976 # # FPSIMD-1-0: PID: 1175
11629 00:58:34.814660 # # FPSIMD-2-0: Vector length: 128 bits
11630 00:58:34.817732 # # FPSIMD-2-0: PID: 1177
11631 00:58:34.821408 # # FPSIMD-0-1: Vector length: 128 bits
11632 00:58:34.824389 # # FPSIMD-0-1: PID: 1174
11633 00:58:34.827542 # # FPSIMD-1-1: Vector length: 128 bits
11634 00:58:34.831266 # # FPSIMD-2-1: Vector length: 128 bits
11635 00:58:34.834356 # # FPSIMD-2-1: PID: 1178
11636 00:58:34.834432 # # FPSIMD-1-1: PID: 1176
11637 00:58:34.837484 # # FPSIMD-3-1: Vector length: 128 bits
11638 00:58:34.840959 # # FPSIMD-3-1: PID: 1180
11639 00:58:34.844169 # # FPSIMD-4-0: Vector length: 128 bits
11640 00:58:34.847475 # # FPSIMD-4-0: PID: 1181
11641 00:58:34.850608 # # FPSIMD-6-0: Vector length: 128 bits
11642 00:58:34.854158 # # FPSIMD-6-0: PID: 1185
11643 00:58:34.857309 # # FPSIMD-5-1: Vector length: 128 bits
11644 00:58:34.857392 # # FPSIMD-5-1: PID: 1184
11645 00:58:34.860749 # # FPSIMD-4-1: Vector length: 128 bits
11646 00:58:34.864019 # # FPSIMD-4-1: PID: 1182
11647 00:58:34.867105 # # FPSIMD-5-0: Vector length: 128 bits
11648 00:58:34.870813 # # FPSIMD-5-0: PID: 1183
11649 00:58:34.873878 # # FPSIMD-3-0: Vector length: 128 bits
11650 00:58:34.877043 # # FPSIMD-7-0: Vector length: 128 bits
11651 00:58:34.880193 # # FPSIMD-7-0: PID: 1187
11652 00:58:34.883510 # # FPSIMD-3-0: PID: 1179
11653 00:58:34.886810 # # FPSIMD-7-1: Vector length: 128 bits
11654 00:58:34.886920 # # FPSIMD-7-1: PID: 1188
11655 00:58:34.890107 # # FPSIMD-0-0: Vector length: 128 bits
11656 00:58:34.893717 # # FPSIMD-0-0: PID: 1173
11657 00:58:34.897031 # # FPSIMD-6-1: Vector length: 128 bits
11658 00:58:34.900213 # # FPSIMD-6-1: PID: 1186
11659 00:58:34.900320 # # Finishing up...
11660 00:58:34.910439 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=940554, signals=10
11661 00:58:34.916641 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1688170, signals=10
11662 00:58:34.923135 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1121224, signals=10
11663 00:58:34.929691 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1437085, signals=10
11664 00:58:34.936586 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1417853, signals=10
11665 00:58:34.946381 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1336455, signals=10
11666 00:58:34.952944 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1572613, signals=10
11667 00:58:34.953053 # ok 1 FPSIMD-0-0
11668 00:58:34.956095 # ok 2 FPSIMD-0-1
11669 00:58:34.956200 # ok 3 FPSIMD-1-0
11670 00:58:34.959317 # ok 4 FPSIMD-1-1
11671 00:58:34.959469 # ok 5 FPSIMD-2-0
11672 00:58:34.962794 # ok 6 FPSIMD-2-1
11673 00:58:34.962899 # ok 7 FPSIMD-3-0
11674 00:58:34.966539 # ok 8 FPSIMD-3-1
11675 00:58:34.966654 # ok 9 FPSIMD-4-0
11676 00:58:34.969327 # ok 10 FPSIMD-4-1
11677 00:58:34.969430 # ok 11 FPSIMD-5-0
11678 00:58:34.972514 # ok 12 FPSIMD-5-1
11679 00:58:34.972614 # ok 13 FPSIMD-6-0
11680 00:58:34.975805 # ok 14 FPSIMD-6-1
11681 00:58:34.975904 # ok 15 FPSIMD-7-0
11682 00:58:34.979490 # ok 16 FPSIMD-7-1
11683 00:58:34.985790 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1035887, signals=9
11684 00:58:34.992574 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1016194, signals=10
11685 00:58:34.999418 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1100010, signals=10
11686 00:58:35.009320 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=903024, signals=10
11687 00:58:35.015567 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1022876, signals=10
11688 00:58:35.022213 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=976678, signals=9
11689 00:58:35.028726 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=951934, signals=10
11690 00:58:35.035308 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1364709, signals=10
11691 00:58:35.042081 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1459111, signals=10
11692 00:58:35.048629 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11693 00:58:35.051814 ok 29 selftests: arm64: fp-stress
11694 00:58:35.055127 # selftests: arm64: sve-ptrace
11695 00:58:35.055212 # TAP version 13
11696 00:58:35.058334 # 1..4104
11697 00:58:35.058445 # ok 2 # SKIP SVE not available
11698 00:58:35.065046 # # Planned tests != run tests (4104 != 1)
11699 00:58:35.068616 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11700 00:58:35.071803 ok 30 selftests: arm64: sve-ptrace # SKIP
11701 00:58:35.074935 # selftests: arm64: sve-probe-vls
11702 00:58:35.078371 # TAP version 13
11703 00:58:35.078453 # 1..2
11704 00:58:35.081326 # ok 2 # SKIP SVE not available
11705 00:58:35.084900 # # Planned tests != run tests (2 != 1)
11706 00:58:35.088387 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11707 00:58:35.094932 ok 31 selftests: arm64: sve-probe-vls # SKIP
11708 00:58:35.095015 # selftests: arm64: vec-syscfg
11709 00:58:35.098525 # TAP version 13
11710 00:58:35.098607 # 1..20
11711 00:58:35.101415 # ok 1 # SKIP SVE not supported
11712 00:58:35.105106 # ok 2 # SKIP SVE not supported
11713 00:58:35.107976 # ok 3 # SKIP SVE not supported
11714 00:58:35.111212 # ok 4 # SKIP SVE not supported
11715 00:58:35.111336 # ok 5 # SKIP SVE not supported
11716 00:58:35.114645 # ok 6 # SKIP SVE not supported
11717 00:58:35.117642 # ok 7 # SKIP SVE not supported
11718 00:58:35.121507 # ok 8 # SKIP SVE not supported
11719 00:58:35.124603 # ok 9 # SKIP SVE not supported
11720 00:58:35.127640 # ok 10 # SKIP SVE not supported
11721 00:58:35.131084 # ok 11 # SKIP SME not supported
11722 00:58:35.134085 # ok 12 # SKIP SME not supported
11723 00:58:35.134192 # ok 13 # SKIP SME not supported
11724 00:58:35.137607 # ok 14 # SKIP SME not supported
11725 00:58:35.140946 # ok 15 # SKIP SME not supported
11726 00:58:35.143956 # ok 16 # SKIP SME not supported
11727 00:58:35.147646 # ok 17 # SKIP SME not supported
11728 00:58:35.150802 # ok 18 # SKIP SME not supported
11729 00:58:35.154410 # ok 19 # SKIP SME not supported
11730 00:58:35.157234 # ok 20 # SKIP SME not supported
11731 00:58:35.160676 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11732 00:58:35.164089 ok 32 selftests: arm64: vec-syscfg
11733 00:58:35.167266 # selftests: arm64: za-fork
11734 00:58:35.167350 # TAP version 13
11735 00:58:35.170394 # 1..1
11736 00:58:35.170478 # # PID: 1265
11737 00:58:35.173784 # # SME support not present
11738 00:58:35.173884 # ok 0 skipped
11739 00:58:35.180550 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11740 00:58:35.183939 ok 33 selftests: arm64: za-fork
11741 00:58:35.184024 # selftests: arm64: za-ptrace
11742 00:58:35.187020 # TAP version 13
11743 00:58:35.187104 # 1..1
11744 00:58:35.190153 # ok 2 # SKIP SME not available
11745 00:58:35.197426 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11746 00:58:35.200177 ok 34 selftests: arm64: za-ptrace # SKIP
11747 00:58:35.203550 # selftests: arm64: check_buffer_fill
11748 00:58:35.251594 # # SKIP: MTE features unavailable
11749 00:58:35.259920 ok 35 selftests: arm64: check_buffer_fill # SKIP
11750 00:58:35.276895 # selftests: arm64: check_child_memory
11751 00:58:35.342086 # # SKIP: MTE features unavailable
11752 00:58:35.349164 ok 36 selftests: arm64: check_child_memory # SKIP
11753 00:58:35.365502 # selftests: arm64: check_gcr_el1_cswitch
11754 00:58:35.415971 # # SKIP: MTE features unavailable
11755 00:58:35.423374 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11756 00:58:35.441862 # selftests: arm64: check_ksm_options
11757 00:58:35.480926 # # SKIP: MTE features unavailable
11758 00:58:35.488158 ok 38 selftests: arm64: check_ksm_options # SKIP
11759 00:58:35.507269 # selftests: arm64: check_mmap_options
11760 00:58:35.580429 # # SKIP: MTE features unavailable
11761 00:58:35.587521 ok 39 selftests: arm64: check_mmap_options # SKIP
11762 00:58:35.602477 # selftests: arm64: check_prctl
11763 00:58:35.644783 # TAP version 13
11764 00:58:35.644901 # 1..5
11765 00:58:35.648088 # ok 1 check_basic_read
11766 00:58:35.648191 # ok 2 NONE
11767 00:58:35.651507 # ok 3 # SKIP SYNC
11768 00:58:35.651611 # ok 4 # SKIP ASYNC
11769 00:58:35.655052 # ok 5 # SKIP SYNC+ASYNC
11770 00:58:35.658468 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11771 00:58:35.661420 ok 40 selftests: arm64: check_prctl
11772 00:58:35.671484 # selftests: arm64: check_tags_inclusion
11773 00:58:35.747891 # # SKIP: MTE features unavailable
11774 00:58:35.755643 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11775 00:58:35.768660 # selftests: arm64: check_user_mem
11776 00:58:35.828733 # # SKIP: MTE features unavailable
11777 00:58:35.836288 ok 42 selftests: arm64: check_user_mem # SKIP
11778 00:58:35.850487 # selftests: arm64: btitest
11779 00:58:35.919333 # TAP version 13
11780 00:58:35.919434 # 1..18
11781 00:58:35.923059 # # HWCAP_PACA not present
11782 00:58:35.925868 # # HWCAP2_BTI not present
11783 00:58:35.925949 # # Test binary built for BTI
11784 00:58:35.932902 # ok 1 nohint_func/call_using_br_x0 # SKIP
11785 00:58:35.936082 # ok 1 nohint_func/call_using_br_x16 # SKIP
11786 00:58:35.939133 # ok 1 nohint_func/call_using_blr # SKIP
11787 00:58:35.942801 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11788 00:58:35.945679 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11789 00:58:35.952337 # ok 1 bti_none_func/call_using_blr # SKIP
11790 00:58:35.955695 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11791 00:58:35.958894 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11792 00:58:35.962317 # ok 1 bti_c_func/call_using_blr # SKIP
11793 00:58:35.965325 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11794 00:58:35.969096 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11795 00:58:35.972727 # ok 1 bti_j_func/call_using_blr # SKIP
11796 00:58:35.975574 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11797 00:58:35.982143 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11798 00:58:35.985219 # ok 1 bti_jc_func/call_using_blr # SKIP
11799 00:58:35.989019 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11800 00:58:35.991831 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11801 00:58:35.995148 # ok 1 paciasp_func/call_using_blr # SKIP
11802 00:58:36.001935 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11803 00:58:36.005674 # # WARNING - EXPECTED TEST COUNT WRONG
11804 00:58:36.008356 ok 43 selftests: arm64: btitest
11805 00:58:36.011594 # selftests: arm64: nobtitest
11806 00:58:36.011675 # TAP version 13
11807 00:58:36.011740 # 1..18
11808 00:58:36.014861 # # HWCAP_PACA not present
11809 00:58:36.018482 # # HWCAP2_BTI not present
11810 00:58:36.021578 # # Test binary not built for BTI
11811 00:58:36.024967 # ok 1 nohint_func/call_using_br_x0 # SKIP
11812 00:58:36.028224 # ok 1 nohint_func/call_using_br_x16 # SKIP
11813 00:58:36.031304 # ok 1 nohint_func/call_using_blr # SKIP
11814 00:58:36.034860 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11815 00:58:36.041622 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11816 00:58:36.044765 # ok 1 bti_none_func/call_using_blr # SKIP
11817 00:58:36.048663 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11818 00:58:36.051374 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11819 00:58:36.054593 # ok 1 bti_c_func/call_using_blr # SKIP
11820 00:58:36.058005 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11821 00:58:36.061395 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11822 00:58:36.064306 # ok 1 bti_j_func/call_using_blr # SKIP
11823 00:58:36.071045 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11824 00:58:36.074537 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11825 00:58:36.077774 # ok 1 bti_jc_func/call_using_blr # SKIP
11826 00:58:36.080932 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11827 00:58:36.084763 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11828 00:58:36.087812 # ok 1 paciasp_func/call_using_blr # SKIP
11829 00:58:36.094052 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11830 00:58:36.097770 # # WARNING - EXPECTED TEST COUNT WRONG
11831 00:58:36.100697 ok 44 selftests: arm64: nobtitest
11832 00:58:36.103883 # selftests: arm64: hwcap
11833 00:58:36.103964 # TAP version 13
11834 00:58:36.104029 # 1..28
11835 00:58:36.107596 # ok 1 cpuinfo_match_RNG
11836 00:58:36.110809 # # SIGILL reported for RNG
11837 00:58:36.113938 # ok 2 # SKIP sigill_RNG
11838 00:58:36.114020 # ok 3 cpuinfo_match_SME
11839 00:58:36.117068 # ok 4 sigill_SME
11840 00:58:36.117152 # ok 5 cpuinfo_match_SVE
11841 00:58:36.120662 # ok 6 sigill_SVE
11842 00:58:36.123680 # ok 7 cpuinfo_match_SVE 2
11843 00:58:36.123762 # # SIGILL reported for SVE 2
11844 00:58:36.127675 # ok 8 # SKIP sigill_SVE 2
11845 00:58:36.130443 # ok 9 cpuinfo_match_SVE AES
11846 00:58:36.133654 # # SIGILL reported for SVE AES
11847 00:58:36.137263 # ok 10 # SKIP sigill_SVE AES
11848 00:58:36.140169 # ok 11 cpuinfo_match_SVE2 PMULL
11849 00:58:36.143717 # # SIGILL reported for SVE2 PMULL
11850 00:58:36.143798 # ok 12 # SKIP sigill_SVE2 PMULL
11851 00:58:36.146770 # ok 13 cpuinfo_match_SVE2 BITPERM
11852 00:58:36.150465 # # SIGILL reported for SVE2 BITPERM
11853 00:58:36.153368 # ok 14 # SKIP sigill_SVE2 BITPERM
11854 00:58:36.157059 # ok 15 cpuinfo_match_SVE2 SHA3
11855 00:58:36.159957 # # SIGILL reported for SVE2 SHA3
11856 00:58:36.163668 # ok 16 # SKIP sigill_SVE2 SHA3
11857 00:58:36.166928 # ok 17 cpuinfo_match_SVE2 SM4
11858 00:58:36.170232 # # SIGILL reported for SVE2 SM4
11859 00:58:36.173455 # ok 18 # SKIP sigill_SVE2 SM4
11860 00:58:36.173540 # ok 19 cpuinfo_match_SVE2 I8MM
11861 00:58:36.176475 # # SIGILL reported for SVE2 I8MM
11862 00:58:36.179949 # ok 20 # SKIP sigill_SVE2 I8MM
11863 00:58:36.183142 # ok 21 cpuinfo_match_SVE2 F32MM
11864 00:58:36.186437 # # SIGILL reported for SVE2 F32MM
11865 00:58:36.189721 # ok 22 # SKIP sigill_SVE2 F32MM
11866 00:58:36.193096 # ok 23 cpuinfo_match_SVE2 F64MM
11867 00:58:36.196682 # # SIGILL reported for SVE2 F64MM
11868 00:58:36.199959 # ok 24 # SKIP sigill_SVE2 F64MM
11869 00:58:36.202915 # ok 25 cpuinfo_match_SVE2 BF16
11870 00:58:36.202999 # # SIGILL reported for SVE2 BF16
11871 00:58:36.206552 # ok 26 # SKIP sigill_SVE2 BF16
11872 00:58:36.209653 # ok 27 cpuinfo_match_SVE2 EBF16
11873 00:58:36.212949 # ok 28 # SKIP sigill_SVE2 EBF16
11874 00:58:36.219662 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11875 00:58:36.222684 ok 45 selftests: arm64: hwcap
11876 00:58:36.222766 # selftests: arm64: ptrace
11877 00:58:36.225986 # TAP version 13
11878 00:58:36.226068 # 1..7
11879 00:58:36.229841 # # Parent is 1507, child is 1508
11880 00:58:36.229923 # ok 1 read_tpidr_one
11881 00:58:36.232787 # ok 2 write_tpidr_one
11882 00:58:36.236424 # ok 3 verify_tpidr_one
11883 00:58:36.236507 # ok 4 count_tpidrs
11884 00:58:36.239430 # ok 5 tpidr2_write
11885 00:58:36.239522 # ok 6 tpidr2_read
11886 00:58:36.242795 # ok 7 write_tpidr_only
11887 00:58:36.249253 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11888 00:58:36.249360 ok 46 selftests: arm64: ptrace
11889 00:58:36.252551 # selftests: arm64: syscall-abi
11890 00:58:36.274076 # TAP version 13
11891 00:58:36.274220 # 1..2
11892 00:58:36.277933 # ok 1 getpid() FPSIMD
11893 00:58:36.280612 # ok 2 sched_yield() FPSIMD
11894 00:58:36.283837 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11895 00:58:36.287136 ok 47 selftests: arm64: syscall-abi
11896 00:58:36.295156 # selftests: arm64: tpidr2
11897 00:58:36.357376 # TAP version 13
11898 00:58:36.357510 # 1..5
11899 00:58:36.360931 # # PID: 1544
11900 00:58:36.361017 # # SME support not present
11901 00:58:36.364007 # ok 0 skipped, TPIDR2 not supported
11902 00:58:36.367144 # ok 1 skipped, TPIDR2 not supported
11903 00:58:36.370640 # ok 2 skipped, TPIDR2 not supported
11904 00:58:36.374223 # ok 3 skipped, TPIDR2 not supported
11905 00:58:36.377478 # ok 4 skipped, TPIDR2 not supported
11906 00:58:36.383804 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11907 00:58:36.386979 ok 48 selftests: arm64: tpidr2
11908 00:58:37.891111 arm64_tags_test pass
11909 00:58:37.894800 arm64_run_tags_test_sh pass
11910 00:58:37.897846 arm64_fake_sigreturn_bad_magic pass
11911 00:58:37.900973 arm64_fake_sigreturn_bad_size pass
11912 00:58:37.904592 arm64_fake_sigreturn_bad_size_for_magic0 pass
11913 00:58:37.907843 arm64_fake_sigreturn_duplicated_fpsimd pass
11914 00:58:37.910899 arm64_fake_sigreturn_misaligned_sp pass
11915 00:58:37.914151 arm64_fake_sigreturn_missing_fpsimd pass
11916 00:58:37.917938 arm64_fake_sigreturn_sme_change_vl skip
11917 00:58:37.924547 arm64_fake_sigreturn_sve_change_vl skip
11918 00:58:37.927298 arm64_mangle_pstate_invalid_compat_toggle pass
11919 00:58:37.930699 arm64_mangle_pstate_invalid_daif_bits pass
11920 00:58:37.934362 arm64_mangle_pstate_invalid_mode_el1h pass
11921 00:58:37.937588 arm64_mangle_pstate_invalid_mode_el1t pass
11922 00:58:37.943987 arm64_mangle_pstate_invalid_mode_el2h pass
11923 00:58:37.946918 arm64_mangle_pstate_invalid_mode_el2t pass
11924 00:58:37.950598 arm64_mangle_pstate_invalid_mode_el3h pass
11925 00:58:37.953946 arm64_mangle_pstate_invalid_mode_el3t pass
11926 00:58:37.957107 arm64_sme_trap_no_sm skip
11927 00:58:37.960548 arm64_sme_trap_non_streaming skip
11928 00:58:37.960630 arm64_sme_trap_za pass
11929 00:58:37.963722 arm64_sme_vl skip
11930 00:58:37.963804 arm64_ssve_regs skip
11931 00:58:37.967242 arm64_sve_regs skip
11932 00:58:37.967323 arm64_sve_vl skip
11933 00:58:37.970247 arm64_za_no_regs skip
11934 00:58:37.973824 arm64_za_regs skip
11935 00:58:37.973906 arm64_pac_PAUTH_not_enabled skip
11936 00:58:37.976876 arm64_pac_PAUTH_not_enabled_dup2 skip
11937 00:58:37.983395 arm64_pac_Generic_PAUTH_not_enabled skip
11938 00:58:37.986783 arm64_pac_PAUTH_not_enabled_dup3 skip
11939 00:58:37.990084 arm64_pac_PAUTH_not_enabled_dup4 skip
11940 00:58:37.993626 arm64_pac_PAUTH_not_enabled_dup5 skip
11941 00:58:37.996627 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11942 00:58:37.996709 arm64_pac pass
11943 00:58:37.999987 arm64_fp-stress_FPSIMD-0-0 pass
11944 00:58:38.003291 arm64_fp-stress_FPSIMD-0-1 pass
11945 00:58:38.006349 arm64_fp-stress_FPSIMD-1-0 pass
11946 00:58:38.009659 arm64_fp-stress_FPSIMD-1-1 pass
11947 00:58:38.012910 arm64_fp-stress_FPSIMD-2-0 pass
11948 00:58:38.016601 arm64_fp-stress_FPSIMD-2-1 pass
11949 00:58:38.016708 arm64_fp-stress_FPSIMD-3-0 pass
11950 00:58:38.019571 arm64_fp-stress_FPSIMD-3-1 pass
11951 00:58:38.022865 arm64_fp-stress_FPSIMD-4-0 pass
11952 00:58:38.026217 arm64_fp-stress_FPSIMD-4-1 pass
11953 00:58:38.029872 arm64_fp-stress_FPSIMD-5-0 pass
11954 00:58:38.032970 arm64_fp-stress_FPSIMD-5-1 pass
11955 00:58:38.036258 arm64_fp-stress_FPSIMD-6-0 pass
11956 00:58:38.039228 arm64_fp-stress_FPSIMD-6-1 pass
11957 00:58:38.039336 arm64_fp-stress_FPSIMD-7-0 pass
11958 00:58:38.042836 arm64_fp-stress_FPSIMD-7-1 pass
11959 00:58:38.045949 arm64_fp-stress pass
11960 00:58:38.049567 arm64_sve-ptrace_SVE_not_available skip
11961 00:58:38.052706 arm64_sve-ptrace skip
11962 00:58:38.055848 arm64_sve-probe-vls_SVE_not_available skip
11963 00:58:38.055952 arm64_sve-probe-vls skip
11964 00:58:38.059052 arm64_vec-syscfg_SVE_not_supported skip
11965 00:58:38.065611 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11966 00:58:38.069085 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11967 00:58:38.072252 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11968 00:58:38.075638 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11969 00:58:38.082221 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11970 00:58:38.085686 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11971 00:58:38.089080 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11972 00:58:38.092120 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11973 00:58:38.095519 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11974 00:58:38.098573 arm64_vec-syscfg_SME_not_supported skip
11975 00:58:38.105559 arm64_vec-syscfg_SME_not_supported_dup2 skip
11976 00:58:38.108594 arm64_vec-syscfg_SME_not_supported_dup3 skip
11977 00:58:38.112328 arm64_vec-syscfg_SME_not_supported_dup4 skip
11978 00:58:38.115430 arm64_vec-syscfg_SME_not_supported_dup5 skip
11979 00:58:38.121882 arm64_vec-syscfg_SME_not_supported_dup6 skip
11980 00:58:38.125047 arm64_vec-syscfg_SME_not_supported_dup7 skip
11981 00:58:38.128704 arm64_vec-syscfg_SME_not_supported_dup8 skip
11982 00:58:38.131759 arm64_vec-syscfg_SME_not_supported_dup9 skip
11983 00:58:38.135125 arm64_vec-syscfg_SME_not_supported_dup10 skip
11984 00:58:38.138275 arm64_vec-syscfg pass
11985 00:58:38.141522 arm64_za-fork_skipped pass
11986 00:58:38.141607 arm64_za-fork pass
11987 00:58:38.144795 arm64_za-ptrace_SME_not_available skip
11988 00:58:38.148092 arm64_za-ptrace skip
11989 00:58:38.151290 arm64_check_buffer_fill skip
11990 00:58:38.151408 arm64_check_child_memory skip
11991 00:58:38.154781 arm64_check_gcr_el1_cswitch skip
11992 00:58:38.158105 arm64_check_ksm_options skip
11993 00:58:38.161459 arm64_check_mmap_options skip
11994 00:58:38.164824 arm64_check_prctl_check_basic_read pass
11995 00:58:38.167866 arm64_check_prctl_NONE pass
11996 00:58:38.171454 arm64_check_prctl_SYNC skip
11997 00:58:38.171538 arm64_check_prctl_ASYNC skip
11998 00:58:38.174535 arm64_check_prctl_SYNC_ASYNC skip
11999 00:58:38.177937 arm64_check_prctl pass
12000 00:58:38.181400 arm64_check_tags_inclusion skip
12001 00:58:38.184378 arm64_check_user_mem skip
12002 00:58:38.188096 arm64_btitest_nohint_func_call_using_br_x0 skip
12003 00:58:38.190970 arm64_btitest_nohint_func_call_using_br_x16 skip
12004 00:58:38.194429 arm64_btitest_nohint_func_call_using_blr skip
12005 00:58:38.201078 arm64_btitest_bti_none_func_call_using_br_x0 skip
12006 00:58:38.204335 arm64_btitest_bti_none_func_call_using_br_x16 skip
12007 00:58:38.207709 arm64_btitest_bti_none_func_call_using_blr skip
12008 00:58:38.214361 arm64_btitest_bti_c_func_call_using_br_x0 skip
12009 00:58:38.217806 arm64_btitest_bti_c_func_call_using_br_x16 skip
12010 00:58:38.221183 arm64_btitest_bti_c_func_call_using_blr skip
12011 00:58:38.224291 arm64_btitest_bti_j_func_call_using_br_x0 skip
12012 00:58:38.230837 arm64_btitest_bti_j_func_call_using_br_x16 skip
12013 00:58:38.233987 arm64_btitest_bti_j_func_call_using_blr skip
12014 00:58:38.237259 arm64_btitest_bti_jc_func_call_using_br_x0 skip
12015 00:58:38.240361 arm64_btitest_bti_jc_func_call_using_br_x16 skip
12016 00:58:38.247099 arm64_btitest_bti_jc_func_call_using_blr skip
12017 00:58:38.250386 arm64_btitest_paciasp_func_call_using_br_x0 skip
12018 00:58:38.253847 arm64_btitest_paciasp_func_call_using_br_x16 skip
12019 00:58:38.260235 arm64_btitest_paciasp_func_call_using_blr skip
12020 00:58:38.260321 arm64_btitest pass
12021 00:58:38.266910 arm64_nobtitest_nohint_func_call_using_br_x0 skip
12022 00:58:38.270388 arm64_nobtitest_nohint_func_call_using_br_x16 skip
12023 00:58:38.273314 arm64_nobtitest_nohint_func_call_using_blr skip
12024 00:58:38.280512 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
12025 00:58:38.283526 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
12026 00:58:38.287010 arm64_nobtitest_bti_none_func_call_using_blr skip
12027 00:58:38.293256 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
12028 00:58:38.296591 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
12029 00:58:38.299946 arm64_nobtitest_bti_c_func_call_using_blr skip
12030 00:58:38.306463 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
12031 00:58:38.309649 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
12032 00:58:38.312862 arm64_nobtitest_bti_j_func_call_using_blr skip
12033 00:58:38.319742 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
12034 00:58:38.322987 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
12035 00:58:38.326402 arm64_nobtitest_bti_jc_func_call_using_blr skip
12036 00:58:38.332923 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
12037 00:58:38.336437 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
12038 00:58:38.339590 arm64_nobtitest_paciasp_func_call_using_blr skip
12039 00:58:38.342818 arm64_nobtitest pass
12040 00:58:38.346039 arm64_hwcap_cpuinfo_match_RNG pass
12041 00:58:38.349750 arm64_hwcap_sigill_RNG skip
12042 00:58:38.349854 arm64_hwcap_cpuinfo_match_SME pass
12043 00:58:38.352844 arm64_hwcap_sigill_SME pass
12044 00:58:38.355893 arm64_hwcap_cpuinfo_match_SVE pass
12045 00:58:38.359672 arm64_hwcap_sigill_SVE pass
12046 00:58:38.362501 arm64_hwcap_cpuinfo_match_SVE_2 pass
12047 00:58:38.365834 arm64_hwcap_sigill_SVE_2 skip
12048 00:58:38.368975 arm64_hwcap_cpuinfo_match_SVE_AES pass
12049 00:58:38.372311 arm64_hwcap_sigill_SVE_AES skip
12050 00:58:38.375663 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
12051 00:58:38.379285 arm64_hwcap_sigill_SVE2_PMULL skip
12052 00:58:38.382104 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
12053 00:58:38.385888 arm64_hwcap_sigill_SVE2_BITPERM skip
12054 00:58:38.389122 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
12055 00:58:38.392414 arm64_hwcap_sigill_SVE2_SHA3 skip
12056 00:58:38.395703 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
12057 00:58:38.398949 arm64_hwcap_sigill_SVE2_SM4 skip
12058 00:58:38.401982 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
12059 00:58:38.405403 arm64_hwcap_sigill_SVE2_I8MM skip
12060 00:58:38.408847 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
12061 00:58:38.412006 arm64_hwcap_sigill_SVE2_F32MM skip
12062 00:58:38.415323 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
12063 00:58:38.418797 arm64_hwcap_sigill_SVE2_F64MM skip
12064 00:58:38.422099 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
12065 00:58:38.425438 arm64_hwcap_sigill_SVE2_BF16 skip
12066 00:58:38.428837 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
12067 00:58:38.431865 arm64_hwcap_sigill_SVE2_EBF16 skip
12068 00:58:38.435177 arm64_hwcap pass
12069 00:58:38.438062 arm64_ptrace_read_tpidr_one pass
12070 00:58:38.441849 arm64_ptrace_write_tpidr_one pass
12071 00:58:38.441944 arm64_ptrace_verify_tpidr_one pass
12072 00:58:38.444946 arm64_ptrace_count_tpidrs pass
12073 00:58:38.448559 arm64_ptrace_tpidr2_write pass
12074 00:58:38.451508 arm64_ptrace_tpidr2_read pass
12075 00:58:38.455021 arm64_ptrace_write_tpidr_only pass
12076 00:58:38.455103 arm64_ptrace pass
12077 00:58:38.458132 arm64_syscall-abi_getpid_FPSIMD pass
12078 00:58:38.464904 arm64_syscall-abi_sched_yield_FPSIMD pass
12079 00:58:38.464986 arm64_syscall-abi pass
12080 00:58:38.468205 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12081 00:58:38.474725 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
12082 00:58:38.478139 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
12083 00:58:38.484805 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
12084 00:58:38.487946 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
12085 00:58:38.490999 arm64_tpidr2 pass
12086 00:58:38.494565 + ../../utils/send-to-lava.sh ./output/result.txt
12087 00:58:38.501401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
12088 00:58:38.501679 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
12090 00:58:38.504350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12091 00:58:38.504601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12093 00:58:38.510748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12094 00:58:38.511003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12096 00:58:38.517382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12097 00:58:38.517622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12099 00:58:38.524352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12100 00:58:38.524603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12102 00:58:38.568982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12103 00:58:38.569252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12105 00:58:38.621443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12106 00:58:38.621739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12108 00:58:38.674681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12109 00:58:38.674954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12111 00:58:38.726051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12112 00:58:38.726365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12114 00:58:38.778688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12115 00:58:38.778963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12117 00:58:38.832993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12118 00:58:38.833257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12120 00:58:38.888385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12121 00:58:38.888660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12123 00:58:38.941121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12124 00:58:38.941393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12126 00:58:38.994442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12127 00:58:38.994716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12129 00:58:39.048059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12130 00:58:39.048362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12132 00:58:39.099706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12133 00:58:39.099975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12135 00:58:39.151874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12136 00:58:39.152150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12138 00:58:39.205106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12139 00:58:39.205371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12141 00:58:39.258360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12142 00:58:39.258630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12144 00:58:39.306461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12145 00:58:39.306753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12147 00:58:39.361661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12149 00:58:39.364643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12150 00:58:39.412420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12151 00:58:39.412711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12153 00:58:39.465462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12154 00:58:39.465781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12156 00:58:39.517584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12157 00:58:39.517871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12159 00:58:39.570929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12160 00:58:39.571201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12162 00:58:39.620539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12163 00:58:39.620804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12165 00:58:39.673485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12166 00:58:39.673756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12168 00:58:39.725850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12169 00:58:39.726114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12171 00:58:39.780773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12173 00:58:39.783551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12174 00:58:39.838058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12175 00:58:39.838335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12177 00:58:39.890670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12178 00:58:39.890954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12180 00:58:39.944687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12181 00:58:39.944957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12183 00:58:39.996337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12184 00:58:39.996614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12186 00:58:40.046819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12187 00:58:40.047082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12189 00:58:40.102571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12190 00:58:40.102848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12192 00:58:40.150732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12193 00:58:40.150996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12195 00:58:40.204775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12197 00:58:40.207560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12198 00:58:40.255813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12199 00:58:40.256085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12201 00:58:40.307972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12202 00:58:40.308281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12204 00:58:40.359664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12205 00:58:40.359930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12207 00:58:40.411857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12208 00:58:40.412157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12210 00:58:40.463185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12211 00:58:40.463475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12213 00:58:40.511825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12215 00:58:40.514852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12216 00:58:40.560741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12217 00:58:40.561022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12219 00:58:40.611441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12220 00:58:40.611804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12222 00:58:40.661197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12223 00:58:40.661501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12225 00:58:40.710621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12226 00:58:40.710892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12228 00:58:40.763221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12229 00:58:40.763526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12231 00:58:40.817414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12232 00:58:40.817704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12234 00:58:40.871196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12235 00:58:40.871470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12237 00:58:40.921704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12238 00:58:40.921997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12240 00:58:40.975286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12241 00:58:40.975566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12243 00:58:41.026977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12244 00:58:41.027241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12246 00:58:41.081228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12247 00:58:41.081529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12249 00:58:41.131811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12250 00:58:41.132078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12252 00:58:41.188357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12253 00:58:41.188643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12255 00:58:41.235404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12256 00:58:41.235668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12258 00:58:41.288396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12259 00:58:41.288670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12261 00:58:41.338993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12262 00:58:41.339261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12264 00:58:41.393677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12265 00:58:41.393990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12267 00:58:41.444342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12268 00:58:41.444621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12270 00:58:41.493538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12271 00:58:41.493810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12273 00:58:41.539818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12274 00:58:41.540079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12276 00:58:41.590349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12277 00:58:41.590627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12279 00:58:41.638662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12280 00:58:41.638920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12282 00:58:41.689258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12283 00:58:41.689544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12285 00:58:41.740845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12286 00:58:41.741160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12288 00:58:41.792657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12289 00:58:41.792948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12291 00:58:41.844679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12292 00:58:41.844956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12294 00:58:41.894721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12295 00:58:41.895004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12297 00:58:41.944820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12298 00:58:41.945089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12300 00:58:41.996262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12301 00:58:41.996545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12303 00:58:42.049143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12304 00:58:42.049420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12306 00:58:42.102284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12307 00:58:42.102569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12309 00:58:42.156857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12310 00:58:42.157129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12312 00:58:42.208827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12313 00:58:42.209105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12315 00:58:42.262133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12316 00:58:42.262451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12318 00:58:42.308480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12319 00:58:42.308782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12321 00:58:42.357162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12322 00:58:42.357456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12324 00:58:42.407774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12325 00:58:42.408034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12327 00:58:42.460082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12328 00:58:42.460378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12330 00:58:42.510792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12331 00:58:42.511067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12333 00:58:42.561416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12334 00:58:42.561706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12336 00:58:42.609763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12337 00:58:42.610063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12339 00:58:42.660514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12341 00:58:42.664046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12342 00:58:42.709266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12343 00:58:42.709540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12345 00:58:42.758740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12346 00:58:42.759006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12348 00:58:42.811494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12349 00:58:42.811770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12351 00:58:42.856305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12352 00:58:42.856573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12354 00:58:42.907326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12355 00:58:42.907605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12357 00:58:42.958149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12358 00:58:42.958481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12360 00:58:43.009712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12362 00:58:43.012645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12363 00:58:43.062828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12364 00:58:43.063113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12366 00:58:43.114655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12367 00:58:43.114953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12369 00:58:43.164800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12370 00:58:43.165136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12372 00:58:43.218350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12373 00:58:43.218667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12375 00:58:43.270847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12376 00:58:43.271133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12378 00:58:43.323239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12379 00:58:43.323511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12381 00:58:43.376377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12382 00:58:43.376660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12384 00:58:43.428611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12385 00:58:43.428878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12387 00:58:43.479983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12388 00:58:43.480261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12390 00:58:43.530925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12391 00:58:43.531192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12393 00:58:43.583531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12394 00:58:43.583813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12396 00:58:43.636931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12397 00:58:43.637200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12399 00:58:43.686412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12400 00:58:43.686686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12402 00:58:43.736508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12403 00:58:43.736780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12405 00:58:43.786665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12406 00:58:43.786935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12408 00:58:43.837773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12409 00:58:43.838045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12411 00:58:43.888874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12412 00:58:43.889150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12414 00:58:43.941717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12415 00:58:43.941987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12417 00:58:43.992287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12418 00:58:43.992587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12420 00:58:44.040186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12421 00:58:44.040475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12423 00:58:44.088229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12424 00:58:44.088523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12426 00:58:44.135595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12427 00:58:44.135878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12429 00:58:44.186910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12430 00:58:44.187180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12432 00:58:44.236743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12433 00:58:44.237043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12435 00:58:44.288092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12436 00:58:44.288372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12438 00:58:44.339821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12439 00:58:44.340100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12441 00:58:44.390075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12442 00:58:44.390423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12444 00:58:44.437976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12445 00:58:44.438254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12447 00:58:44.492041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12448 00:58:44.492315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12450 00:58:44.545353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12451 00:58:44.545625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12453 00:58:44.599269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12454 00:58:44.599546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12456 00:58:44.651406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12457 00:58:44.651676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12459 00:58:44.705523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12460 00:58:44.705825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12462 00:58:44.758344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12463 00:58:44.758617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12465 00:58:44.811537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12466 00:58:44.811844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12468 00:58:44.865742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12469 00:58:44.866014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12471 00:58:44.920061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12472 00:58:44.920339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12474 00:58:44.974075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12475 00:58:44.974397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12477 00:58:45.027626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12478 00:58:45.027893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12480 00:58:45.079253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12481 00:58:45.079537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12483 00:58:45.124115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12484 00:58:45.124377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12486 00:58:45.178048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12487 00:58:45.178383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12489 00:58:45.225544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12490 00:58:45.225808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12492 00:58:45.278422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12493 00:58:45.278698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12495 00:58:45.324394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12496 00:58:45.324694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12498 00:58:45.376199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12499 00:58:45.376502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12501 00:58:45.422300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12502 00:58:45.422570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12504 00:58:45.476066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12505 00:58:45.476414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12507 00:58:45.522817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12508 00:58:45.523102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12510 00:58:45.575981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12511 00:58:45.576258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12513 00:58:45.626595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12514 00:58:45.626928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12516 00:58:45.688952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12517 00:58:45.689895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12519 00:58:45.746562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12520 00:58:45.747258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12522 00:58:45.803231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12523 00:58:45.803931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12525 00:58:45.859663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12526 00:58:45.860553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12528 00:58:45.915949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12529 00:58:45.916828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12531 00:58:45.974074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12533 00:58:45.977355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12534 00:58:46.037267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12535 00:58:46.038032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12537 00:58:46.095591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12539 00:58:46.098470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12540 00:58:46.162959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12541 00:58:46.163856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12543 00:58:46.223223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12544 00:58:46.223975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12546 00:58:46.285584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12547 00:58:46.286390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12549 00:58:46.346719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12550 00:58:46.346997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12552 00:58:46.397968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12553 00:58:46.398246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12555 00:58:46.449509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12556 00:58:46.449780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12558 00:58:46.501013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12559 00:58:46.501291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12561 00:58:46.550964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12563 00:58:46.553668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12564 00:58:46.606687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12565 00:58:46.606982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12567 00:58:46.656434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12569 00:58:46.659153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12570 00:58:46.709076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12571 00:58:46.709361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12573 00:58:46.765140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12575 00:58:46.768086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12576 00:58:46.816423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12578 00:58:46.819068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12579 00:58:46.869449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12580 00:58:46.869721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12582 00:58:46.915653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12583 00:58:46.915925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12585 00:58:46.970063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12586 00:58:46.970401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12588 00:58:47.023153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12589 00:58:47.023463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12591 00:58:47.077641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12592 00:58:47.077945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12594 00:58:47.124406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12595 00:58:47.124678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12597 00:58:47.178117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12598 00:58:47.178441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12600 00:58:47.231203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12601 00:58:47.231480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12603 00:58:47.278965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12604 00:58:47.279236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12606 00:58:47.330118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12607 00:58:47.330421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12609 00:58:47.380980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12610 00:58:47.381259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12612 00:58:47.432799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12613 00:58:47.433064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12615 00:58:47.486786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12616 00:58:47.487071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12618 00:58:47.540117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12619 00:58:47.540404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12621 00:58:47.588932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12622 00:58:47.589040 + set +x
12623 00:58:47.589301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12625 00:58:47.596029 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14368594_1.6.2.3.5>
12626 00:58:47.596286 Received signal: <ENDRUN> 1_kselftest-arm64 14368594_1.6.2.3.5
12627 00:58:47.596368 Ending use of test pattern.
12628 00:58:47.596445 Ending test lava.1_kselftest-arm64 (14368594_1.6.2.3.5), duration 33.89
12630 00:58:47.599128 <LAVA_TEST_RUNNER EXIT>
12631 00:58:47.599385 ok: lava_test_shell seems to have completed
12632 00:58:47.600481 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12633 00:58:47.600649 end: 3.1 lava-test-shell (duration 00:00:35) [common]
12634 00:58:47.600754 end: 3 lava-test-retry (duration 00:00:35) [common]
12635 00:58:47.600859 start: 4 finalize (timeout 00:06:50) [common]
12636 00:58:47.600962 start: 4.1 power-off (timeout 00:00:30) [common]
12637 00:58:47.601123 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
12638 00:58:47.796894 >> Command sent successfully.
12639 00:58:47.799439 Returned 0 in 0 seconds
12640 00:58:47.899866 end: 4.1 power-off (duration 00:00:00) [common]
12642 00:58:47.900200 start: 4.2 read-feedback (timeout 00:06:50) [common]
12643 00:58:47.900467 Listened to connection for namespace 'common' for up to 1s
12644 00:58:48.901543 Finalising connection for namespace 'common'
12645 00:58:48.902142 Disconnecting from shell: Finalise
12646 00:58:48.902577 / #
12647 00:58:49.003542 end: 4.2 read-feedback (duration 00:00:01) [common]
12648 00:58:49.004195 end: 4 finalize (duration 00:00:01) [common]
12649 00:58:49.004737 Cleaning after the job
12650 00:58:49.005251 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/ramdisk
12651 00:58:49.015185 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/kernel
12652 00:58:49.047036 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/dtb
12653 00:58:49.047562 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/nfsrootfs
12654 00:58:49.115942 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368594/tftp-deploy-t_vao4_5/modules
12655 00:58:49.121435 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368594
12656 00:58:49.671906 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368594
12657 00:58:49.672087 Job finished correctly