Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 01:00:07.227022 lava-dispatcher, installed at version: 2024.03
2 01:00:07.227239 start: 0 validate
3 01:00:07.227353 Start time: 2024-06-16 01:00:07.227345+00:00 (UTC)
4 01:00:07.227482 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:00:07.227616 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:00:07.483393 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:00:07.484164 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:00:07.738561 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:00:07.739426 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:00:07.994179 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:00:07.994865 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:00:08.247733 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:00:08.248385 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:00:08.514911 validate duration: 1.29
16 01:00:08.516204 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:00:08.516786 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:00:08.517325 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:00:08.518135 Not decompressing ramdisk as can be used compressed.
20 01:00:08.518727 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:00:08.519135 saving as /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/ramdisk/initrd.cpio.gz
22 01:00:08.519534 total size: 5628169 (5 MB)
23 01:00:08.524405 progress 0 % (0 MB)
24 01:00:08.533662 progress 5 % (0 MB)
25 01:00:08.542281 progress 10 % (0 MB)
26 01:00:08.547452 progress 15 % (0 MB)
27 01:00:08.551827 progress 20 % (1 MB)
28 01:00:08.555050 progress 25 % (1 MB)
29 01:00:08.558325 progress 30 % (1 MB)
30 01:00:08.561241 progress 35 % (1 MB)
31 01:00:08.563516 progress 40 % (2 MB)
32 01:00:08.566036 progress 45 % (2 MB)
33 01:00:08.568061 progress 50 % (2 MB)
34 01:00:08.570229 progress 55 % (2 MB)
35 01:00:08.572294 progress 60 % (3 MB)
36 01:00:08.573994 progress 65 % (3 MB)
37 01:00:08.575906 progress 70 % (3 MB)
38 01:00:08.577512 progress 75 % (4 MB)
39 01:00:08.579223 progress 80 % (4 MB)
40 01:00:08.580750 progress 85 % (4 MB)
41 01:00:08.582399 progress 90 % (4 MB)
42 01:00:08.583956 progress 95 % (5 MB)
43 01:00:08.585365 progress 100 % (5 MB)
44 01:00:08.585577 5 MB downloaded in 0.07 s (81.27 MB/s)
45 01:00:08.585725 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:00:08.585961 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:00:08.586046 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:00:08.586126 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:00:08.586263 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:00:08.586329 saving as /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/kernel/Image
52 01:00:08.586387 total size: 54813184 (52 MB)
53 01:00:08.586445 No compression specified
54 01:00:08.587449 progress 0 % (0 MB)
55 01:00:08.600776 progress 5 % (2 MB)
56 01:00:08.614117 progress 10 % (5 MB)
57 01:00:08.627708 progress 15 % (7 MB)
58 01:00:08.641166 progress 20 % (10 MB)
59 01:00:08.654765 progress 25 % (13 MB)
60 01:00:08.668294 progress 30 % (15 MB)
61 01:00:08.681789 progress 35 % (18 MB)
62 01:00:08.695380 progress 40 % (20 MB)
63 01:00:08.708571 progress 45 % (23 MB)
64 01:00:08.722041 progress 50 % (26 MB)
65 01:00:08.735744 progress 55 % (28 MB)
66 01:00:08.749136 progress 60 % (31 MB)
67 01:00:08.762677 progress 65 % (34 MB)
68 01:00:08.776120 progress 70 % (36 MB)
69 01:00:08.789874 progress 75 % (39 MB)
70 01:00:08.803440 progress 80 % (41 MB)
71 01:00:08.816660 progress 85 % (44 MB)
72 01:00:08.830264 progress 90 % (47 MB)
73 01:00:08.843801 progress 95 % (49 MB)
74 01:00:08.857065 progress 100 % (52 MB)
75 01:00:08.857274 52 MB downloaded in 0.27 s (192.98 MB/s)
76 01:00:08.857418 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:00:08.857628 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:00:08.857710 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:00:08.857787 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:00:08.857917 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 01:00:08.857979 saving as /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/dtb/mt8192-asurada-spherion-r0.dtb
83 01:00:08.858033 total size: 47258 (0 MB)
84 01:00:08.858087 No compression specified
85 01:00:08.859232 progress 69 % (0 MB)
86 01:00:08.859493 progress 100 % (0 MB)
87 01:00:08.859639 0 MB downloaded in 0.00 s (28.10 MB/s)
88 01:00:08.859750 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:00:08.859952 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:00:08.860029 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:00:08.860105 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:00:08.860207 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:00:08.860267 saving as /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/nfsrootfs/full.rootfs.tar
95 01:00:08.860319 total size: 120894716 (115 MB)
96 01:00:08.860372 Using unxz to decompress xz
97 01:00:08.861506 progress 0 % (0 MB)
98 01:00:09.188708 progress 5 % (5 MB)
99 01:00:09.520950 progress 10 % (11 MB)
100 01:00:09.853829 progress 15 % (17 MB)
101 01:00:10.169542 progress 20 % (23 MB)
102 01:00:10.468422 progress 25 % (28 MB)
103 01:00:10.811228 progress 30 % (34 MB)
104 01:00:11.127230 progress 35 % (40 MB)
105 01:00:11.295321 progress 40 % (46 MB)
106 01:00:11.474462 progress 45 % (51 MB)
107 01:00:11.770564 progress 50 % (57 MB)
108 01:00:12.120343 progress 55 % (63 MB)
109 01:00:12.449473 progress 60 % (69 MB)
110 01:00:12.781269 progress 65 % (74 MB)
111 01:00:13.117252 progress 70 % (80 MB)
112 01:00:13.458482 progress 75 % (86 MB)
113 01:00:13.782268 progress 80 % (92 MB)
114 01:00:14.111089 progress 85 % (98 MB)
115 01:00:14.443178 progress 90 % (103 MB)
116 01:00:14.757539 progress 95 % (109 MB)
117 01:00:15.105025 progress 100 % (115 MB)
118 01:00:15.110353 115 MB downloaded in 6.25 s (18.45 MB/s)
119 01:00:15.110506 end: 1.4.1 http-download (duration 00:00:06) [common]
121 01:00:15.110721 end: 1.4 download-retry (duration 00:00:06) [common]
122 01:00:15.110800 start: 1.5 download-retry (timeout 00:09:53) [common]
123 01:00:15.110877 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 01:00:15.111006 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:00:15.111082 saving as /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/modules/modules.tar
126 01:00:15.111138 total size: 8617404 (8 MB)
127 01:00:15.111195 Using unxz to decompress xz
128 01:00:15.112539 progress 0 % (0 MB)
129 01:00:15.130966 progress 5 % (0 MB)
130 01:00:15.156487 progress 10 % (0 MB)
131 01:00:15.183111 progress 15 % (1 MB)
132 01:00:15.205987 progress 20 % (1 MB)
133 01:00:15.228669 progress 25 % (2 MB)
134 01:00:15.251475 progress 30 % (2 MB)
135 01:00:15.276882 progress 35 % (2 MB)
136 01:00:15.300339 progress 40 % (3 MB)
137 01:00:15.322302 progress 45 % (3 MB)
138 01:00:15.345754 progress 50 % (4 MB)
139 01:00:15.369764 progress 55 % (4 MB)
140 01:00:15.394372 progress 60 % (4 MB)
141 01:00:15.418605 progress 65 % (5 MB)
142 01:00:15.445109 progress 70 % (5 MB)
143 01:00:15.468559 progress 75 % (6 MB)
144 01:00:15.494881 progress 80 % (6 MB)
145 01:00:15.518840 progress 85 % (7 MB)
146 01:00:15.543267 progress 90 % (7 MB)
147 01:00:15.567877 progress 95 % (7 MB)
148 01:00:15.591657 progress 100 % (8 MB)
149 01:00:15.597257 8 MB downloaded in 0.49 s (16.91 MB/s)
150 01:00:15.597415 end: 1.5.1 http-download (duration 00:00:00) [common]
152 01:00:15.597632 end: 1.5 download-retry (duration 00:00:00) [common]
153 01:00:15.597712 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 01:00:15.597790 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 01:00:19.120002 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368632/extract-nfsrootfs-n8p_9uxc
156 01:00:19.120163 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 01:00:19.120254 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 01:00:19.120412 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp
159 01:00:19.120531 makedir: /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin
160 01:00:19.120624 makedir: /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/tests
161 01:00:19.120712 makedir: /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/results
162 01:00:19.120794 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-add-keys
163 01:00:19.120923 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-add-sources
164 01:00:19.121042 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-background-process-start
165 01:00:19.121160 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-background-process-stop
166 01:00:19.121286 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-common-functions
167 01:00:19.121433 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-echo-ipv4
168 01:00:19.121550 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-install-packages
169 01:00:19.121664 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-installed-packages
170 01:00:19.121776 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-os-build
171 01:00:19.121890 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-probe-channel
172 01:00:19.122003 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-probe-ip
173 01:00:19.122129 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-target-ip
174 01:00:19.122519 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-target-mac
175 01:00:19.122639 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-target-storage
176 01:00:19.122759 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-test-case
177 01:00:19.122873 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-test-event
178 01:00:19.122986 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-test-feedback
179 01:00:19.123100 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-test-raise
180 01:00:19.123214 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-test-reference
181 01:00:19.123327 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-test-runner
182 01:00:19.123440 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-test-set
183 01:00:19.123551 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-test-shell
184 01:00:19.123665 Updating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-add-keys (debian)
185 01:00:19.123804 Updating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-add-sources (debian)
186 01:00:19.123929 Updating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-install-packages (debian)
187 01:00:19.124053 Updating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-installed-packages (debian)
188 01:00:19.124176 Updating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/bin/lava-os-build (debian)
189 01:00:19.124285 Creating /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/environment
190 01:00:19.124378 LAVA metadata
191 01:00:19.124455 - LAVA_JOB_ID=14368632
192 01:00:19.124512 - LAVA_DISPATCHER_IP=192.168.201.1
193 01:00:19.124605 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 01:00:19.124662 skipped lava-vland-overlay
195 01:00:19.124729 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 01:00:19.124800 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 01:00:19.124864 skipped lava-multinode-overlay
198 01:00:19.124931 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 01:00:19.125001 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 01:00:19.125064 Loading test definitions
201 01:00:19.125139 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 01:00:19.125198 Using /lava-14368632 at stage 0
203 01:00:19.125467 uuid=14368632_1.6.2.3.1 testdef=None
204 01:00:19.125547 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 01:00:19.125623 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 01:00:19.126016 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 01:00:19.126223 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 01:00:19.126733 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 01:00:19.126965 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 01:00:19.127474 runner path: /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/0/tests/0_timesync-off test_uuid 14368632_1.6.2.3.1
213 01:00:19.127634 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 01:00:19.127841 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 01:00:19.127905 Using /lava-14368632 at stage 0
217 01:00:19.127991 Fetching tests from https://github.com/kernelci/test-definitions.git
218 01:00:19.128067 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/0/tests/1_kselftest-dt'
219 01:00:21.262141 Running '/usr/bin/git checkout kernelci.org
220 01:00:21.407807 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 01:00:21.408168 uuid=14368632_1.6.2.3.5 testdef=None
222 01:00:21.408271 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 01:00:21.408469 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 01:00:21.409119 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 01:00:21.409326 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 01:00:21.410337 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 01:00:21.410556 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 01:00:21.411459 runner path: /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/0/tests/1_kselftest-dt test_uuid 14368632_1.6.2.3.5
232 01:00:21.411543 BOARD='mt8192-asurada-spherion-r0'
233 01:00:21.411603 BRANCH='cip-gitlab'
234 01:00:21.411658 SKIPFILE='/dev/null'
235 01:00:21.411709 SKIP_INSTALL='True'
236 01:00:21.411760 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 01:00:21.411811 TST_CASENAME=''
238 01:00:21.411860 TST_CMDFILES='dt'
239 01:00:21.411991 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 01:00:21.412176 Creating lava-test-runner.conf files
242 01:00:21.412232 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368632/lava-overlay-zw_4rbqp/lava-14368632/0 for stage 0
243 01:00:21.412315 - 0_timesync-off
244 01:00:21.412374 - 1_kselftest-dt
245 01:00:21.412462 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 01:00:21.412539 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 01:00:28.482640 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 01:00:28.482774 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 01:00:28.482857 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 01:00:28.482939 end: 1.6.2 lava-overlay (duration 00:00:09) [common]
251 01:00:28.483018 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 01:00:28.639752 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 01:00:28.639903 start: 1.6.4 extract-modules (timeout 00:09:40) [common]
254 01:00:28.639978 extracting modules file /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368632/extract-nfsrootfs-n8p_9uxc
255 01:00:28.853781 extracting modules file /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368632/extract-overlay-ramdisk-jqs04d0s/ramdisk
256 01:00:29.074625 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 01:00:29.074771 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 01:00:29.074855 [common] Applying overlay to NFS
259 01:00:29.074915 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368632/compress-overlay-fo4wy4t_/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368632/extract-nfsrootfs-n8p_9uxc
260 01:00:29.888718 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 01:00:29.888854 start: 1.6.6 configure-preseed-file (timeout 00:09:39) [common]
262 01:00:29.888936 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 01:00:29.889014 start: 1.6.7 compress-ramdisk (timeout 00:09:39) [common]
264 01:00:29.889081 Building ramdisk /var/lib/lava/dispatcher/tmp/14368632/extract-overlay-ramdisk-jqs04d0s/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368632/extract-overlay-ramdisk-jqs04d0s/ramdisk
265 01:00:30.227121 >> 130405 blocks
266 01:00:32.278301 rename /var/lib/lava/dispatcher/tmp/14368632/extract-overlay-ramdisk-jqs04d0s/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/ramdisk/ramdisk.cpio.gz
267 01:00:32.278475 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 01:00:32.278594 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 01:00:32.278671 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 01:00:32.278745 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/kernel/Image']
271 01:00:45.297107 Returned 0 in 13 seconds
272 01:00:45.397963 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/kernel/image.itb
273 01:00:45.879172 output: FIT description: Kernel Image image with one or more FDT blobs
274 01:00:45.879309 output: Created: Sun Jun 16 02:00:45 2024
275 01:00:45.879373 output: Image 0 (kernel-1)
276 01:00:45.879429 output: Description:
277 01:00:45.879480 output: Created: Sun Jun 16 02:00:45 2024
278 01:00:45.879532 output: Type: Kernel Image
279 01:00:45.879584 output: Compression: lzma compressed
280 01:00:45.879639 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
281 01:00:45.879689 output: Architecture: AArch64
282 01:00:45.879737 output: OS: Linux
283 01:00:45.879787 output: Load Address: 0x00000000
284 01:00:45.879837 output: Entry Point: 0x00000000
285 01:00:45.879949 output: Hash algo: crc32
286 01:00:45.880011 output: Hash value: f6f06660
287 01:00:45.880066 output: Image 1 (fdt-1)
288 01:00:45.880123 output: Description: mt8192-asurada-spherion-r0
289 01:00:45.880179 output: Created: Sun Jun 16 02:00:45 2024
290 01:00:45.880235 output: Type: Flat Device Tree
291 01:00:45.880293 output: Compression: uncompressed
292 01:00:45.880349 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 01:00:45.880405 output: Architecture: AArch64
294 01:00:45.880461 output: Hash algo: crc32
295 01:00:45.880514 output: Hash value: 0f8e4d2e
296 01:00:45.880568 output: Image 2 (ramdisk-1)
297 01:00:45.880620 output: Description: unavailable
298 01:00:45.880671 output: Created: Sun Jun 16 02:00:45 2024
299 01:00:45.880719 output: Type: RAMDisk Image
300 01:00:45.880768 output: Compression: uncompressed
301 01:00:45.880816 output: Data Size: 18732614 Bytes = 18293.57 KiB = 17.86 MiB
302 01:00:45.880865 output: Architecture: AArch64
303 01:00:45.880914 output: OS: Linux
304 01:00:45.880962 output: Load Address: unavailable
305 01:00:45.881010 output: Entry Point: unavailable
306 01:00:45.881058 output: Hash algo: crc32
307 01:00:45.881106 output: Hash value: 646e6450
308 01:00:45.881154 output: Default Configuration: 'conf-1'
309 01:00:45.881202 output: Configuration 0 (conf-1)
310 01:00:45.881250 output: Description: mt8192-asurada-spherion-r0
311 01:00:45.881298 output: Kernel: kernel-1
312 01:00:45.881346 output: Init Ramdisk: ramdisk-1
313 01:00:45.881394 output: FDT: fdt-1
314 01:00:45.881442 output: Loadables: kernel-1
315 01:00:45.881489 output:
316 01:00:45.881625 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 01:00:45.881714 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 01:00:45.881804 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 01:00:45.881884 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:23) [common]
320 01:00:45.881953 No LXC device requested
321 01:00:45.882021 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 01:00:45.882099 start: 1.8 deploy-device-env (timeout 00:09:23) [common]
323 01:00:45.882169 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 01:00:45.882271 Checking files for TFTP limit of 4294967296 bytes.
325 01:00:45.882713 end: 1 tftp-deploy (duration 00:00:37) [common]
326 01:00:45.882810 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 01:00:45.882893 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 01:00:45.883004 substitutions:
329 01:00:45.883066 - {DTB}: 14368632/tftp-deploy-gyxsuv4h/dtb/mt8192-asurada-spherion-r0.dtb
330 01:00:45.883125 - {INITRD}: 14368632/tftp-deploy-gyxsuv4h/ramdisk/ramdisk.cpio.gz
331 01:00:45.883178 - {KERNEL}: 14368632/tftp-deploy-gyxsuv4h/kernel/Image
332 01:00:45.883231 - {LAVA_MAC}: None
333 01:00:45.883283 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368632/extract-nfsrootfs-n8p_9uxc
334 01:00:45.883333 - {NFS_SERVER_IP}: 192.168.201.1
335 01:00:45.883383 - {PRESEED_CONFIG}: None
336 01:00:45.883438 - {PRESEED_LOCAL}: None
337 01:00:45.883489 - {RAMDISK}: 14368632/tftp-deploy-gyxsuv4h/ramdisk/ramdisk.cpio.gz
338 01:00:45.883539 - {ROOT_PART}: None
339 01:00:45.883588 - {ROOT}: None
340 01:00:45.883637 - {SERVER_IP}: 192.168.201.1
341 01:00:45.883685 - {TEE}: None
342 01:00:45.883733 Parsed boot commands:
343 01:00:45.883780 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 01:00:45.883928 Parsed boot commands: tftpboot 192.168.201.1 14368632/tftp-deploy-gyxsuv4h/kernel/image.itb 14368632/tftp-deploy-gyxsuv4h/kernel/cmdline
345 01:00:45.884010 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 01:00:45.884088 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 01:00:45.884168 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 01:00:45.884248 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 01:00:45.884309 Not connected, no need to disconnect.
350 01:00:45.884376 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 01:00:45.884447 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 01:00:45.884508 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 01:00:45.887879 Setting prompt string to ['lava-test: # ']
354 01:00:45.888203 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 01:00:45.888299 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 01:00:45.888389 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 01:00:45.888474 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 01:00:45.888636 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-4']
359 01:00:59.625239 Returned 0 in 13 seconds
360 01:00:59.726332 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 01:00:59.727765 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 01:00:59.728285 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 01:00:59.728759 Setting prompt string to 'Starting depthcharge on Spherion...'
365 01:00:59.729121 Changing prompt to 'Starting depthcharge on Spherion...'
366 01:00:59.729483 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 01:00:59.731480 [Enter `^Ec?' for help]
368 01:00:59.731902
369 01:00:59.732242
370 01:00:59.732639 F0: 102B 0000
371 01:00:59.732976
372 01:00:59.733299 F3: 1001 0000 [0200]
373 01:00:59.733599
374 01:00:59.733906 F3: 1001 0000
375 01:00:59.734233
376 01:00:59.734583 F7: 102D 0000
377 01:00:59.734913
378 01:00:59.735242 F1: 0000 0000
379 01:00:59.735574
380 01:00:59.735902 V0: 0000 0000 [0001]
381 01:00:59.736231
382 01:00:59.736540 00: 0007 8000
383 01:00:59.736866
384 01:00:59.737183 01: 0000 0000
385 01:00:59.737480
386 01:00:59.737764 BP: 0C00 0209 [0000]
387 01:00:59.738048
388 01:00:59.738368 G0: 1182 0000
389 01:00:59.738655
390 01:00:59.738934 EC: 0000 0021 [4000]
391 01:00:59.739216
392 01:00:59.739499 S7: 0000 0000 [0000]
393 01:00:59.739778
394 01:00:59.740055 CC: 0000 0000 [0001]
395 01:00:59.740345
396 01:00:59.740596 T0: 0000 0040 [010F]
397 01:00:59.740850
398 01:00:59.741101 Jump to BL
399 01:00:59.741370
400 01:00:59.741657
401 01:00:59.741941
402 01:00:59.742240 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 01:00:59.742536 ARM64: Exception handlers installed.
404 01:00:59.742818 ARM64: Testing exception
405 01:00:59.743097 ARM64: Done test exception
406 01:00:59.743376 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 01:00:59.743663 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 01:00:59.743958 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 01:00:59.744246 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 01:00:59.744532 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 01:00:59.744817 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 01:00:59.745097 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 01:00:59.745398 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 01:00:59.745655 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 01:00:59.745918 WDT: Last reset was cold boot
416 01:00:59.746176 SPI1(PAD0) initialized at 2873684 Hz
417 01:00:59.746454 SPI5(PAD0) initialized at 992727 Hz
418 01:00:59.746712 VBOOT: Loading verstage.
419 01:00:59.746963 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 01:00:59.747222 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 01:00:59.747512 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 01:00:59.747836 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 01:00:59.748370 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 01:00:59.748739 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 01:00:59.749033 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 01:00:59.749320
427 01:00:59.749597
428 01:00:59.749854 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 01:00:59.750122 ARM64: Exception handlers installed.
430 01:00:59.750426 ARM64: Testing exception
431 01:00:59.750687 ARM64: Done test exception
432 01:00:59.750979 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 01:00:59.751243 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 01:00:59.751502 Probing TPM: . done!
435 01:00:59.751756 TPM ready after 0 ms
436 01:00:59.752013 Connected to device vid:did:rid of 1ae0:0028:00
437 01:00:59.752363 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
438 01:00:59.752637 Initialized TPM device CR50 revision 0
439 01:00:59.752897 tlcl_send_startup: Startup return code is 0
440 01:00:59.753169 TPM: setup succeeded
441 01:00:59.753439 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 01:00:59.753697 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 01:00:59.753957 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 01:00:59.754282 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 01:00:59.754560 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 01:00:59.754822 in-header: 03 07 00 00 08 00 00 00
447 01:00:59.755080 in-data: aa e4 47 04 13 02 00 00
448 01:00:59.755338 Chrome EC: UHEPI supported
449 01:00:59.755674 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 01:00:59.755944 in-header: 03 a9 00 00 08 00 00 00
451 01:00:59.756206 in-data: 84 60 60 08 00 00 00 00
452 01:00:59.756464 Phase 1
453 01:00:59.756722 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 01:00:59.756983 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 01:00:59.757243 VB2:vb2_check_recovery() Recovery was requested manually
456 01:00:59.757547 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 01:00:59.757821 Recovery requested (1009000e)
458 01:00:59.758078 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 01:00:59.758415 tlcl_extend: response is 0
460 01:00:59.758609 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 01:00:59.758794 tlcl_extend: response is 0
462 01:00:59.758978 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 01:00:59.759164 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 01:00:59.759348 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 01:00:59.759541
466 01:00:59.759724
467 01:00:59.759907 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 01:00:59.760098 ARM64: Exception handlers installed.
469 01:00:59.760282 ARM64: Testing exception
470 01:00:59.760465 ARM64: Done test exception
471 01:00:59.760651 pmic_efuse_setting: Set efuses in 11 msecs
472 01:00:59.760834 pmwrap_interface_init: Select PMIF_VLD_RDY
473 01:00:59.761016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 01:00:59.761220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 01:00:59.761711 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 01:00:59.761939 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 01:00:59.762129 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 01:00:59.762355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 01:00:59.762543 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 01:00:59.762726 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 01:00:59.762910 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 01:00:59.763094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 01:00:59.763279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 01:00:59.763453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 01:00:59.763593 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 01:00:59.763730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 01:00:59.763868 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 01:00:59.764006 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 01:00:59.764147 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 01:00:59.764296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 01:00:59.764435 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 01:00:59.764572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 01:00:59.764710 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 01:00:59.764848 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 01:00:59.764986 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 01:00:59.765123 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 01:00:59.765261 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 01:00:59.765399 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 01:00:59.765541 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 01:00:59.765682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 01:00:59.765821 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 01:00:59.765961 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 01:00:59.766098 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 01:00:59.766298 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 01:00:59.766445 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 01:00:59.766583 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 01:00:59.766722 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 01:00:59.766860 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 01:00:59.766999 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 01:00:59.767141 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 01:00:59.767286 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 01:00:59.767426 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 01:00:59.767576 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 01:00:59.767781 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 01:00:59.767927 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 01:00:59.768066 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 01:00:59.768205 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 01:00:59.768348 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 01:00:59.768458 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 01:00:59.768570 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 01:00:59.768681 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 01:00:59.768791 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 01:00:59.768902 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 01:00:59.769013 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 01:00:59.769126 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 01:00:59.769237 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 01:00:59.769350 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 01:00:59.769462 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 01:00:59.769577 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 01:00:59.769699 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 01:00:59.769811 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 01:00:59.769922 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x4
533 01:00:59.770034 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 01:00:59.770144 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 01:00:59.770272 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 01:00:59.770387 [RTC]rtc_get_frequency_meter,154: input=15, output=764
537 01:00:59.770503 [RTC]rtc_get_frequency_meter,154: input=23, output=948
538 01:00:59.770614 [RTC]rtc_get_frequency_meter,154: input=19, output=858
539 01:00:59.770725 [RTC]rtc_get_frequency_meter,154: input=17, output=811
540 01:00:59.770846 [RTC]rtc_get_frequency_meter,154: input=16, output=787
541 01:00:59.770960 [RTC]rtc_get_frequency_meter,154: input=16, output=788
542 01:00:59.771071 [RTC]rtc_get_frequency_meter,154: input=17, output=811
543 01:00:59.771182 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 01:00:59.771294 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 01:00:59.771648 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 01:00:59.771890 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 01:00:59.772125 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 01:00:59.772359 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 01:00:59.772585 ADC[4]: Raw value=671168 ID=5
550 01:00:59.772817 ADC[3]: Raw value=212917 ID=1
551 01:00:59.773048 RAM Code: 0x51
552 01:00:59.773277 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 01:00:59.773458 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 01:00:59.773606 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
555 01:00:59.773762 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
556 01:00:59.773907 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 01:00:59.774053 in-header: 03 07 00 00 08 00 00 00
558 01:00:59.774196 in-data: aa e4 47 04 13 02 00 00
559 01:00:59.774358 Chrome EC: UHEPI supported
560 01:00:59.774458 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 01:00:59.774553 in-header: 03 a9 00 00 08 00 00 00
562 01:00:59.774647 in-data: 84 60 60 08 00 00 00 00
563 01:00:59.774740 MRC: failed to locate region type 0.
564 01:00:59.774832 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 01:00:59.774925 DRAM-K: Running full calibration
566 01:00:59.775016 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
567 01:00:59.775108 header.status = 0x0
568 01:00:59.775199 header.version = 0x6 (expected: 0x6)
569 01:00:59.775292 header.size = 0xd00 (expected: 0xd00)
570 01:00:59.775384 header.flags = 0x0
571 01:00:59.775476 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 01:00:59.775569 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
573 01:00:59.775679 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 01:00:59.775835 dram_init: ddr_geometry: 0
575 01:00:59.775938 [EMI] MDL number = 0
576 01:00:59.776041 [EMI] Get MDL freq = 0
577 01:00:59.776136 dram_init: ddr_type: 0
578 01:00:59.776228 is_discrete_lpddr4: 1
579 01:00:59.776330 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 01:00:59.776425
581 01:00:59.776536
582 01:00:59.776630 [Bian_co] ETT version 0.0.0.1
583 01:00:59.776725 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
584 01:00:59.776818
585 01:00:59.776923 dramc_set_vcore_voltage set vcore to 650000
586 01:00:59.777017 Read voltage for 800, 4
587 01:00:59.777123 Vio18 = 0
588 01:00:59.777215 Vcore = 650000
589 01:00:59.777307 Vdram = 0
590 01:00:59.777404 Vddq = 0
591 01:00:59.777497 Vmddr = 0
592 01:00:59.777588 dram_init: config_dvfs: 1
593 01:00:59.777680 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 01:00:59.777772 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 01:00:59.777865 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 01:00:59.777957 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 01:00:59.778051 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 01:00:59.778144 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 01:00:59.778283 MEM_TYPE=3, freq_sel=18
600 01:00:59.778385 sv_algorithm_assistance_LP4_1600
601 01:00:59.778478 ============ PULL DRAM RESETB DOWN ============
602 01:00:59.778565 ========== PULL DRAM RESETB DOWN end =========
603 01:00:59.778646 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 01:00:59.778726 ===================================
605 01:00:59.778806 LPDDR4 DRAM CONFIGURATION
606 01:00:59.778886 ===================================
607 01:00:59.778966 EX_ROW_EN[0] = 0x0
608 01:00:59.779045 EX_ROW_EN[1] = 0x0
609 01:00:59.779124 LP4Y_EN = 0x0
610 01:00:59.779202 WORK_FSP = 0x0
611 01:00:59.779282 WL = 0x2
612 01:00:59.779362 RL = 0x2
613 01:00:59.779440 BL = 0x2
614 01:00:59.779519 RPST = 0x0
615 01:00:59.779597 RD_PRE = 0x0
616 01:00:59.779676 WR_PRE = 0x1
617 01:00:59.779754 WR_PST = 0x0
618 01:00:59.779831 DBI_WR = 0x0
619 01:00:59.779910 DBI_RD = 0x0
620 01:00:59.779987 OTF = 0x1
621 01:00:59.780067 ===================================
622 01:00:59.780147 ===================================
623 01:00:59.780226 ANA top config
624 01:00:59.780305 ===================================
625 01:00:59.780385 DLL_ASYNC_EN = 0
626 01:00:59.780464 ALL_SLAVE_EN = 1
627 01:00:59.780542 NEW_RANK_MODE = 1
628 01:00:59.780621 DLL_IDLE_MODE = 1
629 01:00:59.780700 LP45_APHY_COMB_EN = 1
630 01:00:59.780779 TX_ODT_DIS = 1
631 01:00:59.780868 NEW_8X_MODE = 1
632 01:00:59.780949 ===================================
633 01:00:59.781029 ===================================
634 01:00:59.781109 data_rate = 1600
635 01:00:59.781188 CKR = 1
636 01:00:59.781267 DQ_P2S_RATIO = 8
637 01:00:59.781346 ===================================
638 01:00:59.781426 CA_P2S_RATIO = 8
639 01:00:59.781506 DQ_CA_OPEN = 0
640 01:00:59.781584 DQ_SEMI_OPEN = 0
641 01:00:59.781663 CA_SEMI_OPEN = 0
642 01:00:59.781742 CA_FULL_RATE = 0
643 01:00:59.781822 DQ_CKDIV4_EN = 1
644 01:00:59.781900 CA_CKDIV4_EN = 1
645 01:00:59.781978 CA_PREDIV_EN = 0
646 01:00:59.782056 PH8_DLY = 0
647 01:00:59.782135 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 01:00:59.782221 DQ_AAMCK_DIV = 4
649 01:00:59.782302 CA_AAMCK_DIV = 4
650 01:00:59.782381 CA_ADMCK_DIV = 4
651 01:00:59.782459 DQ_TRACK_CA_EN = 0
652 01:00:59.782537 CA_PICK = 800
653 01:00:59.782617 CA_MCKIO = 800
654 01:00:59.782695 MCKIO_SEMI = 0
655 01:00:59.782773 PLL_FREQ = 3068
656 01:00:59.782851 DQ_UI_PI_RATIO = 32
657 01:00:59.782929 CA_UI_PI_RATIO = 0
658 01:00:59.783007 ===================================
659 01:00:59.783086 ===================================
660 01:00:59.783165 memory_type:LPDDR4
661 01:00:59.783243 GP_NUM : 10
662 01:00:59.783329 SRAM_EN : 1
663 01:00:59.783398 MD32_EN : 0
664 01:00:59.783465 ===================================
665 01:00:59.783772 [ANA_INIT] >>>>>>>>>>>>>>
666 01:00:59.783898 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 01:00:59.784043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 01:00:59.784183 ===================================
669 01:00:59.784323 data_rate = 1600,PCW = 0X7600
670 01:00:59.784460 ===================================
671 01:00:59.784572 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 01:00:59.784682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 01:00:59.784792 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 01:00:59.784902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 01:00:59.785011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 01:00:59.785120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 01:00:59.785228 [ANA_INIT] flow start
678 01:00:59.785335 [ANA_INIT] PLL >>>>>>>>
679 01:00:59.785442 [ANA_INIT] PLL <<<<<<<<
680 01:00:59.785549 [ANA_INIT] MIDPI >>>>>>>>
681 01:00:59.785657 [ANA_INIT] MIDPI <<<<<<<<
682 01:00:59.785764 [ANA_INIT] DLL >>>>>>>>
683 01:00:59.785871 [ANA_INIT] flow end
684 01:00:59.785980 ============ LP4 DIFF to SE enter ============
685 01:00:59.786089 ============ LP4 DIFF to SE exit ============
686 01:00:59.786197 [ANA_INIT] <<<<<<<<<<<<<
687 01:00:59.786317 [Flow] Enable top DCM control >>>>>
688 01:00:59.786426 [Flow] Enable top DCM control <<<<<
689 01:00:59.786533 Enable DLL master slave shuffle
690 01:00:59.786642 ==============================================================
691 01:00:59.786751 Gating Mode config
692 01:00:59.786860 ==============================================================
693 01:00:59.786968 Config description:
694 01:00:59.787078 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 01:00:59.787190 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 01:00:59.787301 SELPH_MODE 0: By rank 1: By Phase
697 01:00:59.787413 ==============================================================
698 01:00:59.787521 GAT_TRACK_EN = 1
699 01:00:59.787630 RX_GATING_MODE = 2
700 01:00:59.787737 RX_GATING_TRACK_MODE = 2
701 01:00:59.787846 SELPH_MODE = 1
702 01:00:59.787954 PICG_EARLY_EN = 1
703 01:00:59.788066 VALID_LAT_VALUE = 1
704 01:00:59.788143 ==============================================================
705 01:00:59.788214 Enter into Gating configuration >>>>
706 01:00:59.788285 Exit from Gating configuration <<<<
707 01:00:59.788363 Enter into DVFS_PRE_config >>>>>
708 01:00:59.788424 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 01:00:59.788491 Exit from DVFS_PRE_config <<<<<
710 01:00:59.788556 Enter into PICG configuration >>>>
711 01:00:59.788620 Exit from PICG configuration <<<<
712 01:00:59.788682 [RX_INPUT] configuration >>>>>
713 01:00:59.788743 [RX_INPUT] configuration <<<<<
714 01:00:59.788813 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 01:00:59.788875 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 01:00:59.788938 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 01:00:59.788999 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 01:00:59.789060 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 01:00:59.789122 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 01:00:59.789184 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 01:00:59.789246 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 01:00:59.789307 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 01:00:59.789369 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 01:00:59.789430 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 01:00:59.789491 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 01:00:59.789553 ===================================
727 01:00:59.789615 LPDDR4 DRAM CONFIGURATION
728 01:00:59.789676 ===================================
729 01:00:59.789738 EX_ROW_EN[0] = 0x0
730 01:00:59.789799 EX_ROW_EN[1] = 0x0
731 01:00:59.789860 LP4Y_EN = 0x0
732 01:00:59.789921 WORK_FSP = 0x0
733 01:00:59.789982 WL = 0x2
734 01:00:59.790042 RL = 0x2
735 01:00:59.790102 BL = 0x2
736 01:00:59.790162 RPST = 0x0
737 01:00:59.790231 RD_PRE = 0x0
738 01:00:59.790294 WR_PRE = 0x1
739 01:00:59.790355 WR_PST = 0x0
740 01:00:59.790416 DBI_WR = 0x0
741 01:00:59.790477 DBI_RD = 0x0
742 01:00:59.790537 OTF = 0x1
743 01:00:59.790599 ===================================
744 01:00:59.790661 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 01:00:59.790723 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 01:00:59.790784 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 01:00:59.790845 ===================================
748 01:00:59.790907 LPDDR4 DRAM CONFIGURATION
749 01:00:59.790968 ===================================
750 01:00:59.791029 EX_ROW_EN[0] = 0x10
751 01:00:59.791091 EX_ROW_EN[1] = 0x0
752 01:00:59.791152 LP4Y_EN = 0x0
753 01:00:59.791220 WORK_FSP = 0x0
754 01:00:59.791282 WL = 0x2
755 01:00:59.791342 RL = 0x2
756 01:00:59.791402 BL = 0x2
757 01:00:59.791463 RPST = 0x0
758 01:00:59.791525 RD_PRE = 0x0
759 01:00:59.791587 WR_PRE = 0x1
760 01:00:59.791648 WR_PST = 0x0
761 01:00:59.791709 DBI_WR = 0x0
762 01:00:59.791770 DBI_RD = 0x0
763 01:00:59.791830 OTF = 0x1
764 01:00:59.791892 ===================================
765 01:00:59.791954 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 01:00:59.792015 nWR fixed to 40
767 01:00:59.792077 [ModeRegInit_LP4] CH0 RK0
768 01:00:59.792139 [ModeRegInit_LP4] CH0 RK1
769 01:00:59.792201 [ModeRegInit_LP4] CH1 RK0
770 01:00:59.792262 [ModeRegInit_LP4] CH1 RK1
771 01:00:59.792323 match AC timing 12
772 01:00:59.792384 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
773 01:00:59.792446 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 01:00:59.792711 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 01:00:59.792813 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 01:00:59.792937 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 01:00:59.793059 [EMI DOE] emi_dcm 0
778 01:00:59.793181 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 01:00:59.793313 ==
780 01:00:59.793402 Dram Type= 6, Freq= 0, CH_0, rank 0
781 01:00:59.793489 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 01:00:59.793576 ==
783 01:00:59.793663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 01:00:59.793751 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 01:00:59.793839 [CA 0] Center 37 (7~68) winsize 62
786 01:00:59.793927 [CA 1] Center 37 (7~68) winsize 62
787 01:00:59.793998 [CA 2] Center 35 (5~66) winsize 62
788 01:00:59.794055 [CA 3] Center 35 (5~66) winsize 62
789 01:00:59.794114 [CA 4] Center 34 (3~65) winsize 63
790 01:00:59.794206 [CA 5] Center 33 (3~64) winsize 62
791 01:00:59.794276
792 01:00:59.794333 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 01:00:59.794390
794 01:00:59.794445 [CATrainingPosCal] consider 1 rank data
795 01:00:59.794501 u2DelayCellTimex100 = 270/100 ps
796 01:00:59.794558 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 01:00:59.794613 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
798 01:00:59.794669 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
799 01:00:59.794724 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
800 01:00:59.794780 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
801 01:00:59.794836 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 01:00:59.794891
803 01:00:59.794947 CA PerBit enable=1, Macro0, CA PI delay=33
804 01:00:59.795003
805 01:00:59.795057 [CBTSetCACLKResult] CA Dly = 33
806 01:00:59.795113 CS Dly: 6 (0~37)
807 01:00:59.795168 ==
808 01:00:59.795223 Dram Type= 6, Freq= 0, CH_0, rank 1
809 01:00:59.795278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
810 01:00:59.795333 ==
811 01:00:59.795389 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 01:00:59.795445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 01:00:59.795502 [CA 0] Center 37 (7~68) winsize 62
814 01:00:59.795557 [CA 1] Center 37 (6~68) winsize 63
815 01:00:59.795613 [CA 2] Center 35 (4~66) winsize 63
816 01:00:59.795667 [CA 3] Center 34 (4~65) winsize 62
817 01:00:59.795722 [CA 4] Center 33 (3~64) winsize 62
818 01:00:59.795777 [CA 5] Center 33 (3~64) winsize 62
819 01:00:59.795832
820 01:00:59.795887 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 01:00:59.795942
822 01:00:59.795997 [CATrainingPosCal] consider 2 rank data
823 01:00:59.796052 u2DelayCellTimex100 = 270/100 ps
824 01:00:59.796107 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 01:00:59.796162 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 01:00:59.796217 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
827 01:00:59.796272 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
828 01:00:59.796327 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 01:00:59.796381 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 01:00:59.796436
831 01:00:59.796491 CA PerBit enable=1, Macro0, CA PI delay=33
832 01:00:59.796546
833 01:00:59.796600 [CBTSetCACLKResult] CA Dly = 33
834 01:00:59.796654 CS Dly: 6 (0~38)
835 01:00:59.796710
836 01:00:59.796764 ----->DramcWriteLeveling(PI) begin...
837 01:00:59.796821 ==
838 01:00:59.796876 Dram Type= 6, Freq= 0, CH_0, rank 0
839 01:00:59.796931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
840 01:00:59.796987 ==
841 01:00:59.797042 Write leveling (Byte 0): 28 => 28
842 01:00:59.797098 Write leveling (Byte 1): 28 => 28
843 01:00:59.797152 DramcWriteLeveling(PI) end<-----
844 01:00:59.797208
845 01:00:59.797261 ==
846 01:00:59.797320 Dram Type= 6, Freq= 0, CH_0, rank 0
847 01:00:59.797377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
848 01:00:59.797433 ==
849 01:00:59.797489 [Gating] SW mode calibration
850 01:00:59.797545 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 01:00:59.797602 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 01:00:59.797658 0 6 0 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 1)
853 01:00:59.797714 0 6 4 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
854 01:00:59.797769 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 01:00:59.797824 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 01:00:59.797879 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 01:00:59.797935 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 01:00:59.797991 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:00:59.798046 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 01:00:59.798101 0 7 0 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
861 01:00:59.798156 0 7 4 | B1->B0 | 3737 4444 | 0 0 | (1 1) (0 0)
862 01:00:59.798218 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 01:00:59.798277 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 01:00:59.798333 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 01:00:59.798388 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 01:00:59.798452 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 01:00:59.798503 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 01:00:59.798553 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
869 01:00:59.798603 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 01:00:59.798654 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 01:00:59.798704 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 01:00:59.798754 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 01:00:59.798804 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 01:00:59.798855 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 01:00:59.798905 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 01:00:59.798956 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 01:00:59.799013 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 01:00:59.799065 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 01:00:59.799116 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 01:00:59.799167 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 01:00:59.799430 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 01:00:59.799521 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 01:00:59.799622 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 01:00:59.799722 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
885 01:00:59.799823 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 01:00:59.799919 Total UI for P1: 0, mck2ui 16
887 01:00:59.800006 best dqsien dly found for B0: ( 0, 10, 0)
888 01:00:59.800089 Total UI for P1: 0, mck2ui 16
889 01:00:59.800168 best dqsien dly found for B1: ( 0, 10, 0)
890 01:00:59.800247 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
891 01:00:59.800327 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
892 01:00:59.800405
893 01:00:59.800484 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
894 01:00:59.800540 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 01:00:59.800592 [Gating] SW calibration Done
896 01:00:59.800642 ==
897 01:00:59.800693 Dram Type= 6, Freq= 0, CH_0, rank 0
898 01:00:59.800744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 01:00:59.800795 ==
900 01:00:59.800845 RX Vref Scan: 0
901 01:00:59.800895
902 01:00:59.800944 RX Vref 0 -> 0, step: 1
903 01:00:59.800994
904 01:00:59.801043 RX Delay -130 -> 252, step: 16
905 01:00:59.801094 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
906 01:00:59.801144 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
907 01:00:59.801195 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
908 01:00:59.801244 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
909 01:00:59.801294 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
910 01:00:59.801344 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
911 01:00:59.801394 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
912 01:00:59.801444 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
913 01:00:59.801493 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
914 01:00:59.801544 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
915 01:00:59.801594 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
916 01:00:59.801645 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
917 01:00:59.801695 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
918 01:00:59.801745 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
919 01:00:59.801796 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
920 01:00:59.801846 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
921 01:00:59.801896 ==
922 01:00:59.801946 Dram Type= 6, Freq= 0, CH_0, rank 0
923 01:00:59.801997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
924 01:00:59.802047 ==
925 01:00:59.802097 DQS Delay:
926 01:00:59.802147 DQS0 = 0, DQS1 = 0
927 01:00:59.802197 DQM Delay:
928 01:00:59.802257 DQM0 = 82, DQM1 = 73
929 01:00:59.802308 DQ Delay:
930 01:00:59.802358 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
931 01:00:59.802407 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
932 01:00:59.802457 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
933 01:00:59.802508 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
934 01:00:59.802558
935 01:00:59.802607
936 01:00:59.802656 ==
937 01:00:59.802706 Dram Type= 6, Freq= 0, CH_0, rank 0
938 01:00:59.802756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
939 01:00:59.802807 ==
940 01:00:59.802856
941 01:00:59.802904
942 01:00:59.802954 TX Vref Scan disable
943 01:00:59.803003 == TX Byte 0 ==
944 01:00:59.803053 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
945 01:00:59.803103 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
946 01:00:59.803153 == TX Byte 1 ==
947 01:00:59.803203 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
948 01:00:59.803253 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
949 01:00:59.803303 ==
950 01:00:59.803353 Dram Type= 6, Freq= 0, CH_0, rank 0
951 01:00:59.803414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
952 01:00:59.803463 ==
953 01:00:59.803512 TX Vref=22, minBit 0, minWin=27, winSum=442
954 01:00:59.803563 TX Vref=24, minBit 0, minWin=27, winSum=445
955 01:00:59.803612 TX Vref=26, minBit 4, minWin=27, winSum=450
956 01:00:59.803662 TX Vref=28, minBit 4, minWin=28, winSum=455
957 01:00:59.803712 TX Vref=30, minBit 0, minWin=27, winSum=452
958 01:00:59.803761 TX Vref=32, minBit 0, minWin=28, winSum=453
959 01:00:59.803815 [TxChooseVref] Worse bit 4, Min win 28, Win sum 455, Final Vref 28
960 01:00:59.803865
961 01:00:59.803915 Final TX Range 1 Vref 28
962 01:00:59.803964
963 01:00:59.804013 ==
964 01:00:59.804062 Dram Type= 6, Freq= 0, CH_0, rank 0
965 01:00:59.804110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
966 01:00:59.804160 ==
967 01:00:59.804209
968 01:00:59.804257
969 01:00:59.804335 TX Vref Scan disable
970 01:00:59.804411 == TX Byte 0 ==
971 01:00:59.804493 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
972 01:00:59.804571 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
973 01:00:59.804639 == TX Byte 1 ==
974 01:00:59.804690 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
975 01:00:59.804741 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
976 01:00:59.804790
977 01:00:59.804839 [DATLAT]
978 01:00:59.804888 Freq=800, CH0 RK0
979 01:00:59.804938
980 01:00:59.804987 DATLAT Default: 0xa
981 01:00:59.805036 0, 0xFFFF, sum = 0
982 01:00:59.805086 1, 0xFFFF, sum = 0
983 01:00:59.805136 2, 0xFFFF, sum = 0
984 01:00:59.805186 3, 0xFFFF, sum = 0
985 01:00:59.805238 4, 0xFFFF, sum = 0
986 01:00:59.805288 5, 0xFFFF, sum = 0
987 01:00:59.805337 6, 0xFFFF, sum = 0
988 01:00:59.805386 7, 0xFFFF, sum = 0
989 01:00:59.805437 8, 0x0, sum = 1
990 01:00:59.805487 9, 0x0, sum = 2
991 01:00:59.805536 10, 0x0, sum = 3
992 01:00:59.805587 11, 0x0, sum = 4
993 01:00:59.805636 best_step = 9
994 01:00:59.805685
995 01:00:59.805733 ==
996 01:00:59.805783 Dram Type= 6, Freq= 0, CH_0, rank 0
997 01:00:59.805833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
998 01:00:59.805883 ==
999 01:00:59.805932 RX Vref Scan: 1
1000 01:00:59.805980
1001 01:00:59.806029 Set Vref Range= 32 -> 127
1002 01:00:59.806077
1003 01:00:59.806126 RX Vref 32 -> 127, step: 1
1004 01:00:59.806175
1005 01:00:59.806231 RX Delay -111 -> 252, step: 8
1006 01:00:59.806282
1007 01:00:59.806331 Set Vref, RX VrefLevel [Byte0]: 32
1008 01:00:59.806381 [Byte1]: 32
1009 01:00:59.806431
1010 01:00:59.806479 Set Vref, RX VrefLevel [Byte0]: 33
1011 01:00:59.806529 [Byte1]: 33
1012 01:00:59.806577
1013 01:00:59.806625 Set Vref, RX VrefLevel [Byte0]: 34
1014 01:00:59.806673 [Byte1]: 34
1015 01:00:59.806721
1016 01:00:59.806769 Set Vref, RX VrefLevel [Byte0]: 35
1017 01:00:59.806819 [Byte1]: 35
1018 01:00:59.806869
1019 01:00:59.806917 Set Vref, RX VrefLevel [Byte0]: 36
1020 01:00:59.806966 [Byte1]: 36
1021 01:00:59.807016
1022 01:00:59.807067 Set Vref, RX VrefLevel [Byte0]: 37
1023 01:00:59.807120 [Byte1]: 37
1024 01:00:59.807183
1025 01:00:59.807233 Set Vref, RX VrefLevel [Byte0]: 38
1026 01:00:59.807285 [Byte1]: 38
1027 01:00:59.807336
1028 01:00:59.807386 Set Vref, RX VrefLevel [Byte0]: 39
1029 01:00:59.807435 [Byte1]: 39
1030 01:00:59.807484
1031 01:00:59.807727 Set Vref, RX VrefLevel [Byte0]: 40
1032 01:00:59.807805 [Byte1]: 40
1033 01:00:59.807902
1034 01:00:59.807998 Set Vref, RX VrefLevel [Byte0]: 41
1035 01:00:59.808095 [Byte1]: 41
1036 01:00:59.808188
1037 01:00:59.808272 Set Vref, RX VrefLevel [Byte0]: 42
1038 01:00:59.808352 [Byte1]: 42
1039 01:00:59.808429
1040 01:00:59.808506 Set Vref, RX VrefLevel [Byte0]: 43
1041 01:00:59.808583 [Byte1]: 43
1042 01:00:59.808659
1043 01:00:59.808736 Set Vref, RX VrefLevel [Byte0]: 44
1044 01:00:59.808813 [Byte1]: 44
1045 01:00:59.808890
1046 01:00:59.808967 Set Vref, RX VrefLevel [Byte0]: 45
1047 01:00:59.809044 [Byte1]: 45
1048 01:00:59.809120
1049 01:00:59.809172 Set Vref, RX VrefLevel [Byte0]: 46
1050 01:00:59.809223 [Byte1]: 46
1051 01:00:59.809272
1052 01:00:59.809321 Set Vref, RX VrefLevel [Byte0]: 47
1053 01:00:59.809370 [Byte1]: 47
1054 01:00:59.809419
1055 01:00:59.809469 Set Vref, RX VrefLevel [Byte0]: 48
1056 01:00:59.809518 [Byte1]: 48
1057 01:00:59.809566
1058 01:00:59.809615 Set Vref, RX VrefLevel [Byte0]: 49
1059 01:00:59.809671 [Byte1]: 49
1060 01:00:59.809721
1061 01:00:59.809769 Set Vref, RX VrefLevel [Byte0]: 50
1062 01:00:59.809825 [Byte1]: 50
1063 01:00:59.809875
1064 01:00:59.809924 Set Vref, RX VrefLevel [Byte0]: 51
1065 01:00:59.809973 [Byte1]: 51
1066 01:00:59.810022
1067 01:00:59.810070 Set Vref, RX VrefLevel [Byte0]: 52
1068 01:00:59.810118 [Byte1]: 52
1069 01:00:59.810167
1070 01:00:59.810221 Set Vref, RX VrefLevel [Byte0]: 53
1071 01:00:59.810272 [Byte1]: 53
1072 01:00:59.810320
1073 01:00:59.810368 Set Vref, RX VrefLevel [Byte0]: 54
1074 01:00:59.810417 [Byte1]: 54
1075 01:00:59.810466
1076 01:00:59.810521 Set Vref, RX VrefLevel [Byte0]: 55
1077 01:00:59.810571 [Byte1]: 55
1078 01:00:59.810619
1079 01:00:59.810668 Set Vref, RX VrefLevel [Byte0]: 56
1080 01:00:59.810717 [Byte1]: 56
1081 01:00:59.810767
1082 01:00:59.810815 Set Vref, RX VrefLevel [Byte0]: 57
1083 01:00:59.810865 [Byte1]: 57
1084 01:00:59.810913
1085 01:00:59.810962 Set Vref, RX VrefLevel [Byte0]: 58
1086 01:00:59.811011 [Byte1]: 58
1087 01:00:59.811061
1088 01:00:59.811109 Set Vref, RX VrefLevel [Byte0]: 59
1089 01:00:59.811158 [Byte1]: 59
1090 01:00:59.811207
1091 01:00:59.811257 Set Vref, RX VrefLevel [Byte0]: 60
1092 01:00:59.811306 [Byte1]: 60
1093 01:00:59.811354
1094 01:00:59.811403 Set Vref, RX VrefLevel [Byte0]: 61
1095 01:00:59.811452 [Byte1]: 61
1096 01:00:59.811501
1097 01:00:59.811549 Set Vref, RX VrefLevel [Byte0]: 62
1098 01:00:59.811598 [Byte1]: 62
1099 01:00:59.811646
1100 01:00:59.811695 Set Vref, RX VrefLevel [Byte0]: 63
1101 01:00:59.811745 [Byte1]: 63
1102 01:00:59.811794
1103 01:00:59.811843 Set Vref, RX VrefLevel [Byte0]: 64
1104 01:00:59.811892 [Byte1]: 64
1105 01:00:59.811941
1106 01:00:59.811990 Set Vref, RX VrefLevel [Byte0]: 65
1107 01:00:59.812039 [Byte1]: 65
1108 01:00:59.812087
1109 01:00:59.812135 Set Vref, RX VrefLevel [Byte0]: 66
1110 01:00:59.812184 [Byte1]: 66
1111 01:00:59.812233
1112 01:00:59.812282 Set Vref, RX VrefLevel [Byte0]: 67
1113 01:00:59.812331 [Byte1]: 67
1114 01:00:59.812380
1115 01:00:59.812429 Set Vref, RX VrefLevel [Byte0]: 68
1116 01:00:59.812479 [Byte1]: 68
1117 01:00:59.812527
1118 01:00:59.812575 Set Vref, RX VrefLevel [Byte0]: 69
1119 01:00:59.812624 [Byte1]: 69
1120 01:00:59.812673
1121 01:00:59.812722 Set Vref, RX VrefLevel [Byte0]: 70
1122 01:00:59.812771 [Byte1]: 70
1123 01:00:59.812820
1124 01:00:59.812869 Set Vref, RX VrefLevel [Byte0]: 71
1125 01:00:59.812918 [Byte1]: 71
1126 01:00:59.812967
1127 01:00:59.813015 Set Vref, RX VrefLevel [Byte0]: 72
1128 01:00:59.813064 [Byte1]: 72
1129 01:00:59.813117
1130 01:00:59.813167 Set Vref, RX VrefLevel [Byte0]: 73
1131 01:00:59.813216 [Byte1]: 73
1132 01:00:59.813265
1133 01:00:59.813314 Set Vref, RX VrefLevel [Byte0]: 74
1134 01:00:59.813363 [Byte1]: 74
1135 01:00:59.813412
1136 01:00:59.813461 Final RX Vref Byte 0 = 49 to rank0
1137 01:00:59.813510 Final RX Vref Byte 1 = 55 to rank0
1138 01:00:59.813560 Final RX Vref Byte 0 = 49 to rank1
1139 01:00:59.813609 Final RX Vref Byte 1 = 55 to rank1==
1140 01:00:59.813659 Dram Type= 6, Freq= 0, CH_0, rank 0
1141 01:00:59.813708 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1142 01:00:59.813757 ==
1143 01:00:59.813807 DQS Delay:
1144 01:00:59.813860 DQS0 = 0, DQS1 = 0
1145 01:00:59.813909 DQM Delay:
1146 01:00:59.813957 DQM0 = 84, DQM1 = 73
1147 01:00:59.814006 DQ Delay:
1148 01:00:59.814055 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1149 01:00:59.814104 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1150 01:00:59.814153 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1151 01:00:59.814202 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1152 01:00:59.814296
1153 01:00:59.814345
1154 01:00:59.814394 [DQSOSCAuto] RK0, (LSB)MR18= 0x3535, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1155 01:00:59.814445 CH0 RK0: MR19=606, MR18=3535
1156 01:00:59.814494 CH0_RK0: MR19=0x606, MR18=0x3535, DQSOSC=396, MR23=63, INC=94, DEC=62
1157 01:00:59.814544
1158 01:00:59.814593 ----->DramcWriteLeveling(PI) begin...
1159 01:00:59.814643 ==
1160 01:00:59.814693 Dram Type= 6, Freq= 0, CH_0, rank 1
1161 01:00:59.814742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1162 01:00:59.814797 ==
1163 01:00:59.814847 Write leveling (Byte 0): 28 => 28
1164 01:00:59.814897 Write leveling (Byte 1): 32 => 32
1165 01:00:59.814951 DramcWriteLeveling(PI) end<-----
1166 01:00:59.815001
1167 01:00:59.815050 ==
1168 01:00:59.815101 Dram Type= 6, Freq= 0, CH_0, rank 1
1169 01:00:59.815167 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1170 01:00:59.815217 ==
1171 01:00:59.815267 [Gating] SW mode calibration
1172 01:00:59.815317 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1173 01:00:59.815368 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1174 01:00:59.815417 0 6 0 | B1->B0 | 3030 3030 | 0 0 | (0 1) (1 0)
1175 01:00:59.815467 0 6 4 | B1->B0 | 2828 2323 | 0 0 | (1 1) (1 0)
1176 01:00:59.815516 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 01:00:59.815565 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 01:00:59.815615 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 01:00:59.815857 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 01:00:59.815939 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 01:00:59.816037 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 01:00:59.816134 0 7 0 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (0 0)
1183 01:00:59.816230 0 7 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1184 01:00:59.816324 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 01:00:59.816410 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 01:00:59.816491 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 01:00:59.816569 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 01:00:59.816647 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 01:00:59.816724 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 01:00:59.816802 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1191 01:00:59.816879 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1192 01:00:59.816957 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 01:00:59.817034 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 01:00:59.817112 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 01:00:59.817207 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 01:00:59.817257 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 01:00:59.817306 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 01:00:59.817356 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 01:00:59.817406 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 01:00:59.817455 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 01:00:59.817505 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 01:00:59.817554 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 01:00:59.817604 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 01:00:59.817653 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 01:00:59.817703 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 01:00:59.817753 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1207 01:00:59.817802 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 01:00:59.817852 Total UI for P1: 0, mck2ui 16
1209 01:00:59.817901 best dqsien dly found for B0: ( 0, 10, 0)
1210 01:00:59.817951 Total UI for P1: 0, mck2ui 16
1211 01:00:59.818000 best dqsien dly found for B1: ( 0, 10, 0)
1212 01:00:59.818048 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1213 01:00:59.818098 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1214 01:00:59.818147
1215 01:00:59.818197 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1216 01:00:59.818289 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1217 01:00:59.818339 [Gating] SW calibration Done
1218 01:00:59.818388 ==
1219 01:00:59.818437 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 01:00:59.818486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1221 01:00:59.818536 ==
1222 01:00:59.818585 RX Vref Scan: 0
1223 01:00:59.818635
1224 01:00:59.818684 RX Vref 0 -> 0, step: 1
1225 01:00:59.818733
1226 01:00:59.818782 RX Delay -130 -> 252, step: 16
1227 01:00:59.818831 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1228 01:00:59.818880 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1229 01:00:59.818929 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1230 01:00:59.818978 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1231 01:00:59.819027 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1232 01:00:59.819076 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1233 01:00:59.819168 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1234 01:00:59.819219 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1235 01:00:59.819268 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1236 01:00:59.819317 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1237 01:00:59.819366 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1238 01:00:59.819416 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1239 01:00:59.819465 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1240 01:00:59.819514 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1241 01:00:59.819564 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1242 01:00:59.819613 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1243 01:00:59.819662 ==
1244 01:00:59.819711 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 01:00:59.819761 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1246 01:00:59.819810 ==
1247 01:00:59.819859 DQS Delay:
1248 01:00:59.819907 DQS0 = 0, DQS1 = 0
1249 01:00:59.819956 DQM Delay:
1250 01:00:59.820008 DQM0 = 81, DQM1 = 73
1251 01:00:59.820059 DQ Delay:
1252 01:00:59.820108 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =69
1253 01:00:59.820157 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1254 01:00:59.820215 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1255 01:00:59.820265 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1256 01:00:59.820314
1257 01:00:59.820362
1258 01:00:59.820410 ==
1259 01:00:59.820459 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 01:00:59.820508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1261 01:00:59.820557 ==
1262 01:00:59.820610
1263 01:00:59.820660
1264 01:00:59.820709 TX Vref Scan disable
1265 01:00:59.820758 == TX Byte 0 ==
1266 01:00:59.820807 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1267 01:00:59.820857 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1268 01:00:59.820906 == TX Byte 1 ==
1269 01:00:59.820955 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1270 01:00:59.821005 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1271 01:00:59.821054 ==
1272 01:00:59.821107 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 01:00:59.821159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1274 01:00:59.821209 ==
1275 01:00:59.821259 TX Vref=22, minBit 2, minWin=27, winSum=446
1276 01:00:59.821309 TX Vref=24, minBit 0, minWin=28, winSum=451
1277 01:00:59.821358 TX Vref=26, minBit 0, minWin=28, winSum=454
1278 01:00:59.821408 TX Vref=28, minBit 4, minWin=28, winSum=459
1279 01:00:59.821458 TX Vref=30, minBit 2, minWin=28, winSum=460
1280 01:00:59.821508 TX Vref=32, minBit 4, minWin=28, winSum=461
1281 01:00:59.821557 [TxChooseVref] Worse bit 4, Min win 28, Win sum 461, Final Vref 32
1282 01:00:59.821607
1283 01:00:59.821657 Final TX Range 1 Vref 32
1284 01:00:59.821705
1285 01:00:59.821753 ==
1286 01:00:59.821802 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 01:00:59.821852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1288 01:00:59.821902 ==
1289 01:00:59.821951
1290 01:00:59.821999
1291 01:00:59.822048 TX Vref Scan disable
1292 01:00:59.822097 == TX Byte 0 ==
1293 01:00:59.822147 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1294 01:00:59.822197 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1295 01:00:59.822492 == TX Byte 1 ==
1296 01:00:59.822575 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1297 01:00:59.822674 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1298 01:00:59.822770
1299 01:00:59.822866 [DATLAT]
1300 01:00:59.822962 Freq=800, CH0 RK1
1301 01:00:59.823049
1302 01:00:59.823137 DATLAT Default: 0x9
1303 01:00:59.823279 0, 0xFFFF, sum = 0
1304 01:00:59.823378 1, 0xFFFF, sum = 0
1305 01:00:59.823458 2, 0xFFFF, sum = 0
1306 01:00:59.823537 3, 0xFFFF, sum = 0
1307 01:00:59.823616 4, 0xFFFF, sum = 0
1308 01:00:59.823695 5, 0xFFFF, sum = 0
1309 01:00:59.823774 6, 0xFFFF, sum = 0
1310 01:00:59.823852 7, 0xFFFF, sum = 0
1311 01:00:59.823920 8, 0x0, sum = 1
1312 01:00:59.823972 9, 0x0, sum = 2
1313 01:00:59.824023 10, 0x0, sum = 3
1314 01:00:59.824074 11, 0x0, sum = 4
1315 01:00:59.824124 best_step = 9
1316 01:00:59.824173
1317 01:00:59.824222 ==
1318 01:00:59.824271 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 01:00:59.824321 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1320 01:00:59.824371 ==
1321 01:00:59.824420 RX Vref Scan: 0
1322 01:00:59.824469
1323 01:00:59.824518 RX Vref 0 -> 0, step: 1
1324 01:00:59.824567
1325 01:00:59.824616 RX Delay -111 -> 252, step: 8
1326 01:00:59.824666 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1327 01:00:59.824715 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1328 01:00:59.824764 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1329 01:00:59.824814 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1330 01:00:59.824863 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1331 01:00:59.824912 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1332 01:00:59.824960 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1333 01:00:59.825010 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1334 01:00:59.825061 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1335 01:00:59.825114 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1336 01:00:59.825165 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1337 01:00:59.825214 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1338 01:00:59.825263 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1339 01:00:59.825321 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1340 01:00:59.825372 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1341 01:00:59.825421 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1342 01:00:59.825471 ==
1343 01:00:59.825520 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 01:00:59.825569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1345 01:00:59.825619 ==
1346 01:00:59.825668 DQS Delay:
1347 01:00:59.825717 DQS0 = 0, DQS1 = 0
1348 01:00:59.825766 DQM Delay:
1349 01:00:59.825814 DQM0 = 86, DQM1 = 74
1350 01:00:59.825863 DQ Delay:
1351 01:00:59.825912 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1352 01:00:59.825962 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1353 01:00:59.826011 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1354 01:00:59.826060 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1355 01:00:59.826109
1356 01:00:59.826158
1357 01:00:59.826206 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f4f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1358 01:00:59.826266 CH0 RK1: MR19=606, MR18=4F4F
1359 01:00:59.826316 CH0_RK1: MR19=0x606, MR18=0x4F4F, DQSOSC=390, MR23=63, INC=97, DEC=64
1360 01:00:59.826366 [RxdqsGatingPostProcess] freq 800
1361 01:00:59.826416 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1362 01:00:59.826466 Pre-setting of DQS Precalculation
1363 01:00:59.826516 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1364 01:00:59.826565 ==
1365 01:00:59.826614 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 01:00:59.826662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1367 01:00:59.826711 ==
1368 01:00:59.826759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1369 01:00:59.826808 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1370 01:00:59.826858 [CA 0] Center 37 (6~68) winsize 63
1371 01:00:59.826920 [CA 1] Center 37 (6~68) winsize 63
1372 01:00:59.826971 [CA 2] Center 34 (4~65) winsize 62
1373 01:00:59.827020 [CA 3] Center 34 (4~65) winsize 62
1374 01:00:59.827069 [CA 4] Center 33 (3~64) winsize 62
1375 01:00:59.827118 [CA 5] Center 33 (3~64) winsize 62
1376 01:00:59.827166
1377 01:00:59.827215 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1378 01:00:59.827264
1379 01:00:59.827318 [CATrainingPosCal] consider 1 rank data
1380 01:00:59.827367 u2DelayCellTimex100 = 270/100 ps
1381 01:00:59.827417 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1382 01:00:59.827466 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1383 01:00:59.827515 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1384 01:00:59.827564 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1385 01:00:59.827613 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1386 01:00:59.827662 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1387 01:00:59.827711
1388 01:00:59.827760 CA PerBit enable=1, Macro0, CA PI delay=33
1389 01:00:59.827809
1390 01:00:59.827858 [CBTSetCACLKResult] CA Dly = 33
1391 01:00:59.827907 CS Dly: 5 (0~36)
1392 01:00:59.827956 ==
1393 01:00:59.828004 Dram Type= 6, Freq= 0, CH_1, rank 1
1394 01:00:59.828053 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1395 01:00:59.828103 ==
1396 01:00:59.828152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1397 01:00:59.828202 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1398 01:00:59.828252 [CA 0] Center 37 (6~68) winsize 63
1399 01:00:59.828301 [CA 1] Center 37 (6~68) winsize 63
1400 01:00:59.828351 [CA 2] Center 34 (4~65) winsize 62
1401 01:00:59.828401 [CA 3] Center 34 (4~65) winsize 62
1402 01:00:59.828450 [CA 4] Center 33 (3~64) winsize 62
1403 01:00:59.828498 [CA 5] Center 33 (3~64) winsize 62
1404 01:00:59.828546
1405 01:00:59.828594 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1406 01:00:59.828643
1407 01:00:59.828691 [CATrainingPosCal] consider 2 rank data
1408 01:00:59.828740 u2DelayCellTimex100 = 270/100 ps
1409 01:00:59.828789 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1410 01:00:59.828838 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1411 01:00:59.828887 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1412 01:00:59.828935 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 01:00:59.828983 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1414 01:00:59.829031 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1415 01:00:59.829079
1416 01:00:59.829127 CA PerBit enable=1, Macro0, CA PI delay=33
1417 01:00:59.829175
1418 01:00:59.829223 [CBTSetCACLKResult] CA Dly = 33
1419 01:00:59.829272 CS Dly: 5 (0~36)
1420 01:00:59.829320
1421 01:00:59.829369 ----->DramcWriteLeveling(PI) begin...
1422 01:00:59.829418 ==
1423 01:00:59.829467 Dram Type= 6, Freq= 0, CH_1, rank 0
1424 01:00:59.829516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1425 01:00:59.829566 ==
1426 01:00:59.829615 Write leveling (Byte 0): 26 => 26
1427 01:00:59.829665 Write leveling (Byte 1): 24 => 24
1428 01:00:59.829906 DramcWriteLeveling(PI) end<-----
1429 01:00:59.829986
1430 01:00:59.830082 ==
1431 01:00:59.830179 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 01:00:59.830283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1433 01:00:59.830400 ==
1434 01:00:59.830496 [Gating] SW mode calibration
1435 01:00:59.830576 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1436 01:00:59.830655 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1437 01:00:59.830733 0 6 0 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
1438 01:00:59.830810 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1439 01:00:59.830888 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 01:00:59.830966 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 01:00:59.831044 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 01:00:59.831121 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 01:00:59.831199 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 01:00:59.831276 0 6 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1445 01:00:59.831353 0 7 0 | B1->B0 | 3131 3e3e | 1 0 | (0 0) (0 0)
1446 01:00:59.831430 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1447 01:00:59.831507 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 01:00:59.831584 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 01:00:59.831661 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 01:00:59.831737 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 01:00:59.831815 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 01:00:59.831894 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1453 01:00:59.831981 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 01:00:59.832062 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 01:00:59.832140 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 01:00:59.832218 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 01:00:59.832297 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 01:00:59.832374 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 01:00:59.832453 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 01:00:59.832530 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 01:00:59.832608 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 01:00:59.832690 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 01:00:59.832744 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 01:00:59.832794 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 01:00:59.832844 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 01:00:59.832893 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 01:00:59.832942 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 01:00:59.832991 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 01:00:59.833039 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1470 01:00:59.833088 Total UI for P1: 0, mck2ui 16
1471 01:00:59.833137 best dqsien dly found for B0: ( 0, 9, 30)
1472 01:00:59.833186 Total UI for P1: 0, mck2ui 16
1473 01:00:59.833235 best dqsien dly found for B1: ( 0, 9, 30)
1474 01:00:59.833285 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1475 01:00:59.833334 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1476 01:00:59.833383
1477 01:00:59.833431 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1478 01:00:59.833479 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1479 01:00:59.833528 [Gating] SW calibration Done
1480 01:00:59.833576 ==
1481 01:00:59.833625 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 01:00:59.833675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1483 01:00:59.833723 ==
1484 01:00:59.833772 RX Vref Scan: 0
1485 01:00:59.833823
1486 01:00:59.833871 RX Vref 0 -> 0, step: 1
1487 01:00:59.833919
1488 01:00:59.833967 RX Delay -130 -> 252, step: 16
1489 01:00:59.834015 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1490 01:00:59.834064 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1491 01:00:59.834112 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1492 01:00:59.834161 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1493 01:00:59.834215 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1494 01:00:59.834289 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1495 01:00:59.834351 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1496 01:00:59.834399 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1497 01:00:59.834447 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1498 01:00:59.834495 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1499 01:00:59.834544 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1500 01:00:59.834593 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1501 01:00:59.834642 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1502 01:00:59.834690 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1503 01:00:59.834738 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1504 01:00:59.834787 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1505 01:00:59.834834 ==
1506 01:00:59.834882 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 01:00:59.834932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1508 01:00:59.834982 ==
1509 01:00:59.835030 DQS Delay:
1510 01:00:59.835079 DQS0 = 0, DQS1 = 0
1511 01:00:59.835127 DQM Delay:
1512 01:00:59.835176 DQM0 = 85, DQM1 = 75
1513 01:00:59.835225 DQ Delay:
1514 01:00:59.835274 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1515 01:00:59.835323 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1516 01:00:59.835371 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1517 01:00:59.835420 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1518 01:00:59.835467
1519 01:00:59.835516
1520 01:00:59.835564 ==
1521 01:00:59.835613 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 01:00:59.835662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1523 01:00:59.835711 ==
1524 01:00:59.835759
1525 01:00:59.835806
1526 01:00:59.835853 TX Vref Scan disable
1527 01:00:59.835902 == TX Byte 0 ==
1528 01:00:59.835950 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1529 01:00:59.835999 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1530 01:00:59.836047 == TX Byte 1 ==
1531 01:00:59.836095 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1532 01:00:59.836143 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1533 01:00:59.836192 ==
1534 01:00:59.836240 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 01:00:59.836289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1536 01:00:59.836337 ==
1537 01:00:59.836385 TX Vref=22, minBit 2, minWin=27, winSum=446
1538 01:00:59.836435 TX Vref=24, minBit 0, minWin=28, winSum=450
1539 01:00:59.836673 TX Vref=26, minBit 3, minWin=27, winSum=453
1540 01:00:59.836739 TX Vref=28, minBit 0, minWin=28, winSum=454
1541 01:00:59.836838 TX Vref=30, minBit 5, minWin=28, winSum=459
1542 01:00:59.836936 TX Vref=32, minBit 0, minWin=28, winSum=459
1543 01:00:59.837034 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
1544 01:00:59.837130
1545 01:00:59.837216 Final TX Range 1 Vref 30
1546 01:00:59.837299
1547 01:00:59.837376 ==
1548 01:00:59.837453 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 01:00:59.837530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1550 01:00:59.837606 ==
1551 01:00:59.837682
1552 01:00:59.837757
1553 01:00:59.837833 TX Vref Scan disable
1554 01:00:59.837909 == TX Byte 0 ==
1555 01:00:59.837987 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1556 01:00:59.838064 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1557 01:00:59.838141 == TX Byte 1 ==
1558 01:00:59.838223 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1559 01:00:59.838313 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1560 01:00:59.838363
1561 01:00:59.838411 [DATLAT]
1562 01:00:59.838460 Freq=800, CH1 RK0
1563 01:00:59.838509
1564 01:00:59.838558 DATLAT Default: 0xa
1565 01:00:59.838607 0, 0xFFFF, sum = 0
1566 01:00:59.838656 1, 0xFFFF, sum = 0
1567 01:00:59.838705 2, 0xFFFF, sum = 0
1568 01:00:59.838754 3, 0xFFFF, sum = 0
1569 01:00:59.838804 4, 0xFFFF, sum = 0
1570 01:00:59.838853 5, 0xFFFF, sum = 0
1571 01:00:59.838902 6, 0xFFFF, sum = 0
1572 01:00:59.838950 7, 0xFFFF, sum = 0
1573 01:00:59.838999 8, 0x0, sum = 1
1574 01:00:59.839048 9, 0x0, sum = 2
1575 01:00:59.839097 10, 0x0, sum = 3
1576 01:00:59.839145 11, 0x0, sum = 4
1577 01:00:59.839195 best_step = 9
1578 01:00:59.839243
1579 01:00:59.839291 ==
1580 01:00:59.839339 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 01:00:59.839388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1582 01:00:59.839437 ==
1583 01:00:59.839485 RX Vref Scan: 1
1584 01:00:59.839533
1585 01:00:59.839581 Set Vref Range= 32 -> 127
1586 01:00:59.839629
1587 01:00:59.839677 RX Vref 32 -> 127, step: 1
1588 01:00:59.839725
1589 01:00:59.839772 RX Delay -111 -> 252, step: 8
1590 01:00:59.839820
1591 01:00:59.839868 Set Vref, RX VrefLevel [Byte0]: 32
1592 01:00:59.839917 [Byte1]: 32
1593 01:00:59.839966
1594 01:00:59.840014 Set Vref, RX VrefLevel [Byte0]: 33
1595 01:00:59.840062 [Byte1]: 33
1596 01:00:59.840114
1597 01:00:59.840164 Set Vref, RX VrefLevel [Byte0]: 34
1598 01:00:59.840214 [Byte1]: 34
1599 01:00:59.840263
1600 01:00:59.840312 Set Vref, RX VrefLevel [Byte0]: 35
1601 01:00:59.840360 [Byte1]: 35
1602 01:00:59.840408
1603 01:00:59.840456 Set Vref, RX VrefLevel [Byte0]: 36
1604 01:00:59.840504 [Byte1]: 36
1605 01:00:59.840552
1606 01:00:59.840600 Set Vref, RX VrefLevel [Byte0]: 37
1607 01:00:59.840649 [Byte1]: 37
1608 01:00:59.840696
1609 01:00:59.840743 Set Vref, RX VrefLevel [Byte0]: 38
1610 01:00:59.840791 [Byte1]: 38
1611 01:00:59.840839
1612 01:00:59.840893 Set Vref, RX VrefLevel [Byte0]: 39
1613 01:00:59.840942 [Byte1]: 39
1614 01:00:59.840991
1615 01:00:59.841041 Set Vref, RX VrefLevel [Byte0]: 40
1616 01:00:59.841093 [Byte1]: 40
1617 01:00:59.841142
1618 01:00:59.841191 Set Vref, RX VrefLevel [Byte0]: 41
1619 01:00:59.841239 [Byte1]: 41
1620 01:00:59.841288
1621 01:00:59.841336 Set Vref, RX VrefLevel [Byte0]: 42
1622 01:00:59.841384 [Byte1]: 42
1623 01:00:59.841432
1624 01:00:59.841479 Set Vref, RX VrefLevel [Byte0]: 43
1625 01:00:59.841527 [Byte1]: 43
1626 01:00:59.841576
1627 01:00:59.841625 Set Vref, RX VrefLevel [Byte0]: 44
1628 01:00:59.841673 [Byte1]: 44
1629 01:00:59.841722
1630 01:00:59.841770 Set Vref, RX VrefLevel [Byte0]: 45
1631 01:00:59.841818 [Byte1]: 45
1632 01:00:59.841867
1633 01:00:59.841915 Set Vref, RX VrefLevel [Byte0]: 46
1634 01:00:59.841964 [Byte1]: 46
1635 01:00:59.842012
1636 01:00:59.842060 Set Vref, RX VrefLevel [Byte0]: 47
1637 01:00:59.842109 [Byte1]: 47
1638 01:00:59.842157
1639 01:00:59.842205 Set Vref, RX VrefLevel [Byte0]: 48
1640 01:00:59.842263 [Byte1]: 48
1641 01:00:59.842313
1642 01:00:59.842362 Set Vref, RX VrefLevel [Byte0]: 49
1643 01:00:59.842410 [Byte1]: 49
1644 01:00:59.842458
1645 01:00:59.842506 Set Vref, RX VrefLevel [Byte0]: 50
1646 01:00:59.842555 [Byte1]: 50
1647 01:00:59.842604
1648 01:00:59.842651 Set Vref, RX VrefLevel [Byte0]: 51
1649 01:00:59.842700 [Byte1]: 51
1650 01:00:59.842748
1651 01:00:59.842797 Set Vref, RX VrefLevel [Byte0]: 52
1652 01:00:59.842845 [Byte1]: 52
1653 01:00:59.842892
1654 01:00:59.842944 Set Vref, RX VrefLevel [Byte0]: 53
1655 01:00:59.843013 [Byte1]: 53
1656 01:00:59.843064
1657 01:00:59.843112 Set Vref, RX VrefLevel [Byte0]: 54
1658 01:00:59.843179 [Byte1]: 54
1659 01:00:59.843230
1660 01:00:59.843279 Set Vref, RX VrefLevel [Byte0]: 55
1661 01:00:59.843337 [Byte1]: 55
1662 01:00:59.843398
1663 01:00:59.843448 Set Vref, RX VrefLevel [Byte0]: 56
1664 01:00:59.843497 [Byte1]: 56
1665 01:00:59.843557
1666 01:00:59.843610 Set Vref, RX VrefLevel [Byte0]: 57
1667 01:00:59.843659 [Byte1]: 57
1668 01:00:59.843708
1669 01:00:59.843761 Set Vref, RX VrefLevel [Byte0]: 58
1670 01:00:59.843810 [Byte1]: 58
1671 01:00:59.843858
1672 01:00:59.843906 Set Vref, RX VrefLevel [Byte0]: 59
1673 01:00:59.843958 [Byte1]: 59
1674 01:00:59.844008
1675 01:00:59.844058 Set Vref, RX VrefLevel [Byte0]: 60
1676 01:00:59.844109 [Byte1]: 60
1677 01:00:59.844158
1678 01:00:59.844207 Set Vref, RX VrefLevel [Byte0]: 61
1679 01:00:59.844256 [Byte1]: 61
1680 01:00:59.844303
1681 01:00:59.844351 Set Vref, RX VrefLevel [Byte0]: 62
1682 01:00:59.844400 [Byte1]: 62
1683 01:00:59.844449
1684 01:00:59.844498 Set Vref, RX VrefLevel [Byte0]: 63
1685 01:00:59.844547 [Byte1]: 63
1686 01:00:59.844594
1687 01:00:59.844642 Set Vref, RX VrefLevel [Byte0]: 64
1688 01:00:59.844691 [Byte1]: 64
1689 01:00:59.844740
1690 01:00:59.844788 Set Vref, RX VrefLevel [Byte0]: 65
1691 01:00:59.844836 [Byte1]: 65
1692 01:00:59.844884
1693 01:00:59.844932 Set Vref, RX VrefLevel [Byte0]: 66
1694 01:00:59.844981 [Byte1]: 66
1695 01:00:59.845029
1696 01:00:59.845078 Set Vref, RX VrefLevel [Byte0]: 67
1697 01:00:59.845126 [Byte1]: 67
1698 01:00:59.845175
1699 01:00:59.845222 Set Vref, RX VrefLevel [Byte0]: 68
1700 01:00:59.845271 [Byte1]: 68
1701 01:00:59.845319
1702 01:00:59.845367 Set Vref, RX VrefLevel [Byte0]: 69
1703 01:00:59.845416 [Byte1]: 69
1704 01:00:59.845464
1705 01:00:59.845513 Set Vref, RX VrefLevel [Byte0]: 70
1706 01:00:59.845561 [Byte1]: 70
1707 01:00:59.845609
1708 01:00:59.845850 Set Vref, RX VrefLevel [Byte0]: 71
1709 01:00:59.845923 [Byte1]: 71
1710 01:00:59.846054
1711 01:00:59.846149 Set Vref, RX VrefLevel [Byte0]: 72
1712 01:00:59.846268 [Byte1]: 72
1713 01:00:59.846362
1714 01:00:59.846439 Set Vref, RX VrefLevel [Byte0]: 73
1715 01:00:59.846516 [Byte1]: 73
1716 01:00:59.846591
1717 01:00:59.846668 Set Vref, RX VrefLevel [Byte0]: 74
1718 01:00:59.846745 [Byte1]: 74
1719 01:00:59.846821
1720 01:00:59.846898 Set Vref, RX VrefLevel [Byte0]: 75
1721 01:00:59.846974 [Byte1]: 75
1722 01:00:59.847049
1723 01:00:59.847125 Set Vref, RX VrefLevel [Byte0]: 76
1724 01:00:59.847202 [Byte1]: 76
1725 01:00:59.847278
1726 01:00:59.847355 Final RX Vref Byte 0 = 59 to rank0
1727 01:00:59.847432 Final RX Vref Byte 1 = 57 to rank0
1728 01:00:59.847509 Final RX Vref Byte 0 = 59 to rank1
1729 01:00:59.847585 Final RX Vref Byte 1 = 57 to rank1==
1730 01:00:59.847662 Dram Type= 6, Freq= 0, CH_1, rank 0
1731 01:00:59.847739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1732 01:00:59.847815 ==
1733 01:00:59.847892 DQS Delay:
1734 01:00:59.847967 DQS0 = 0, DQS1 = 0
1735 01:00:59.848043 DQM Delay:
1736 01:00:59.848119 DQM0 = 81, DQM1 = 74
1737 01:00:59.848194 DQ Delay:
1738 01:00:59.848271 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1739 01:00:59.848352 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1740 01:00:59.848429 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1741 01:00:59.848510 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
1742 01:00:59.848597
1743 01:00:59.848651
1744 01:00:59.848700 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e4e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1745 01:00:59.848751 CH1 RK0: MR19=606, MR18=4E4E
1746 01:00:59.848800 CH1_RK0: MR19=0x606, MR18=0x4E4E, DQSOSC=390, MR23=63, INC=97, DEC=64
1747 01:00:59.848849
1748 01:00:59.848897 ----->DramcWriteLeveling(PI) begin...
1749 01:00:59.848947 ==
1750 01:00:59.848996 Dram Type= 6, Freq= 0, CH_1, rank 1
1751 01:00:59.849045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1752 01:00:59.849093 ==
1753 01:00:59.849142 Write leveling (Byte 0): 24 => 24
1754 01:00:59.849190 Write leveling (Byte 1): 23 => 23
1755 01:00:59.849239 DramcWriteLeveling(PI) end<-----
1756 01:00:59.849286
1757 01:00:59.849337 ==
1758 01:00:59.849395 Dram Type= 6, Freq= 0, CH_1, rank 1
1759 01:00:59.849446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1760 01:00:59.849495 ==
1761 01:00:59.849545 [Gating] SW mode calibration
1762 01:00:59.849594 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1763 01:00:59.849643 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1764 01:00:59.849692 0 6 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
1765 01:00:59.849742 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1766 01:00:59.849791 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1767 01:00:59.849840 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1768 01:00:59.849888 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1769 01:00:59.849937 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1770 01:00:59.849986 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1771 01:00:59.850034 0 6 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
1772 01:00:59.850082 0 7 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
1773 01:00:59.850131 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1774 01:00:59.850180 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1775 01:00:59.850236 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1776 01:00:59.850322 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1777 01:00:59.850371 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1778 01:00:59.850419 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1779 01:00:59.850468 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1780 01:00:59.850517 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 01:00:59.850565 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 01:00:59.850614 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 01:00:59.850662 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 01:00:59.850711 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 01:00:59.850760 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 01:00:59.850809 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 01:00:59.850858 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 01:00:59.850907 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 01:00:59.850956 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 01:00:59.851004 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 01:00:59.851053 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 01:00:59.851101 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 01:00:59.851150 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 01:00:59.851199 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 01:00:59.851247 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1796 01:00:59.851296 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1797 01:00:59.851344 Total UI for P1: 0, mck2ui 16
1798 01:00:59.851393 best dqsien dly found for B0: ( 0, 9, 28)
1799 01:00:59.851442 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1800 01:00:59.851491 Total UI for P1: 0, mck2ui 16
1801 01:00:59.851540 best dqsien dly found for B1: ( 0, 9, 30)
1802 01:00:59.851589 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1803 01:00:59.851638 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1804 01:00:59.851686
1805 01:00:59.851734 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1806 01:00:59.851783 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1807 01:00:59.851831 [Gating] SW calibration Done
1808 01:00:59.851880 ==
1809 01:00:59.851929 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 01:00:59.851978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1811 01:00:59.852027 ==
1812 01:00:59.852075 RX Vref Scan: 0
1813 01:00:59.852123
1814 01:00:59.852171 RX Vref 0 -> 0, step: 1
1815 01:00:59.852220
1816 01:00:59.852267 RX Delay -130 -> 252, step: 16
1817 01:00:59.852316 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1818 01:00:59.852364 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1819 01:00:59.852413 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1820 01:00:59.852462 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1821 01:00:59.852702 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1822 01:00:59.852758 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1823 01:00:59.852807 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1824 01:00:59.852857 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1825 01:00:59.852905 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1826 01:00:59.852954 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1827 01:00:59.853003 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1828 01:00:59.853051 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1829 01:00:59.853100 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1830 01:00:59.853148 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1831 01:00:59.853196 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1832 01:00:59.853244 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1833 01:00:59.853291 ==
1834 01:00:59.853339 Dram Type= 6, Freq= 0, CH_1, rank 1
1835 01:00:59.853388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1836 01:00:59.853437 ==
1837 01:00:59.853486 DQS Delay:
1838 01:00:59.853534 DQS0 = 0, DQS1 = 0
1839 01:00:59.853583 DQM Delay:
1840 01:00:59.853632 DQM0 = 85, DQM1 = 74
1841 01:00:59.853680 DQ Delay:
1842 01:00:59.853727 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1843 01:00:59.853781 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1844 01:00:59.853867 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1845 01:00:59.853946 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1846 01:00:59.854029
1847 01:00:59.854105
1848 01:00:59.854190 ==
1849 01:00:59.854297 Dram Type= 6, Freq= 0, CH_1, rank 1
1850 01:00:59.854348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1851 01:00:59.854417 ==
1852 01:00:59.854471
1853 01:00:59.854519
1854 01:00:59.854571 TX Vref Scan disable
1855 01:00:59.854630 == TX Byte 0 ==
1856 01:00:59.854680 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1857 01:00:59.854730 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1858 01:00:59.854778 == TX Byte 1 ==
1859 01:00:59.854837 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1860 01:00:59.854888 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1861 01:00:59.854938 ==
1862 01:00:59.854996 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 01:00:59.855075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1864 01:00:59.855152 ==
1865 01:00:59.855234 TX Vref=22, minBit 0, minWin=27, winSum=450
1866 01:00:59.855312 TX Vref=24, minBit 2, minWin=28, winSum=456
1867 01:00:59.855392 TX Vref=26, minBit 0, minWin=28, winSum=457
1868 01:00:59.855471 TX Vref=28, minBit 0, minWin=28, winSum=458
1869 01:00:59.855549 TX Vref=30, minBit 9, minWin=27, winSum=459
1870 01:00:59.855619 TX Vref=32, minBit 9, minWin=27, winSum=456
1871 01:00:59.855671 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1872 01:00:59.855720
1873 01:00:59.855769 Final TX Range 1 Vref 28
1874 01:00:59.855818
1875 01:00:59.855866 ==
1876 01:00:59.855915 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 01:00:59.855963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1878 01:00:59.856012 ==
1879 01:00:59.856061
1880 01:00:59.856110
1881 01:00:59.856157 TX Vref Scan disable
1882 01:00:59.856206 == TX Byte 0 ==
1883 01:00:59.856255 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1884 01:00:59.856304 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1885 01:00:59.856353 == TX Byte 1 ==
1886 01:00:59.856401 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1887 01:00:59.856450 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1888 01:00:59.856499
1889 01:00:59.856547 [DATLAT]
1890 01:00:59.856595 Freq=800, CH1 RK1
1891 01:00:59.856643
1892 01:00:59.856692 DATLAT Default: 0x9
1893 01:00:59.856741 0, 0xFFFF, sum = 0
1894 01:00:59.856791 1, 0xFFFF, sum = 0
1895 01:00:59.856840 2, 0xFFFF, sum = 0
1896 01:00:59.856889 3, 0xFFFF, sum = 0
1897 01:00:59.856938 4, 0xFFFF, sum = 0
1898 01:00:59.856987 5, 0xFFFF, sum = 0
1899 01:00:59.857036 6, 0xFFFF, sum = 0
1900 01:00:59.857085 7, 0xFFFF, sum = 0
1901 01:00:59.857134 8, 0x0, sum = 1
1902 01:00:59.857183 9, 0x0, sum = 2
1903 01:00:59.857232 10, 0x0, sum = 3
1904 01:00:59.857282 11, 0x0, sum = 4
1905 01:00:59.857331 best_step = 9
1906 01:00:59.857379
1907 01:00:59.857428 ==
1908 01:00:59.857476 Dram Type= 6, Freq= 0, CH_1, rank 1
1909 01:00:59.857526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1910 01:00:59.857575 ==
1911 01:00:59.857623 RX Vref Scan: 0
1912 01:00:59.857671
1913 01:00:59.857720 RX Vref 0 -> 0, step: 1
1914 01:00:59.857768
1915 01:00:59.857816 RX Delay -111 -> 252, step: 8
1916 01:00:59.857863 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1917 01:00:59.857912 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1918 01:00:59.857960 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1919 01:00:59.858009 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1920 01:00:59.858057 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1921 01:00:59.858106 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1922 01:00:59.858154 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1923 01:00:59.858204 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1924 01:00:59.858288 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1925 01:00:59.858350 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1926 01:00:59.858399 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1927 01:00:59.858448 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1928 01:00:59.858497 iDelay=217, Bit 12, Center 88 (-31 ~ 208) 240
1929 01:00:59.858545 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1930 01:00:59.858594 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1931 01:00:59.858642 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1932 01:00:59.858690 ==
1933 01:00:59.858738 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 01:00:59.858786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1935 01:00:59.858835 ==
1936 01:00:59.858884 DQS Delay:
1937 01:00:59.858932 DQS0 = 0, DQS1 = 0
1938 01:00:59.858980 DQM Delay:
1939 01:00:59.859028 DQM0 = 85, DQM1 = 75
1940 01:00:59.859077 DQ Delay:
1941 01:00:59.859126 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1942 01:00:59.859175 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1943 01:00:59.859223 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1944 01:00:59.859271 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1945 01:00:59.859319
1946 01:00:59.859368
1947 01:00:59.859416 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1948 01:00:59.859466 CH1 RK1: MR19=606, MR18=3E3E
1949 01:00:59.859515 CH1_RK1: MR19=0x606, MR18=0x3E3E, DQSOSC=394, MR23=63, INC=95, DEC=63
1950 01:00:59.859564 [RxdqsGatingPostProcess] freq 800
1951 01:00:59.859612 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1952 01:00:59.859661 Pre-setting of DQS Precalculation
1953 01:00:59.859708 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1954 01:00:59.859757 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1955 01:00:59.859997 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1956 01:00:59.860055
1957 01:00:59.860131
1958 01:00:59.860214 [Calibration Summary] 1600 Mbps
1959 01:00:59.860291 CH 0, Rank 0
1960 01:00:59.860368 SW Impedance : PASS
1961 01:00:59.860446 DUTY Scan : NO K
1962 01:00:59.860523 ZQ Calibration : PASS
1963 01:00:59.860599 Jitter Meter : NO K
1964 01:00:59.860675 CBT Training : PASS
1965 01:00:59.860752 Write leveling : PASS
1966 01:00:59.860828 RX DQS gating : PASS
1967 01:00:59.860904 RX DQ/DQS(RDDQC) : PASS
1968 01:00:59.860980 TX DQ/DQS : PASS
1969 01:00:59.861057 RX DATLAT : PASS
1970 01:00:59.861133 RX DQ/DQS(Engine): PASS
1971 01:00:59.861209 TX OE : NO K
1972 01:00:59.861285 All Pass.
1973 01:00:59.861361
1974 01:00:59.861437 CH 0, Rank 1
1975 01:00:59.861513 SW Impedance : PASS
1976 01:00:59.861589 DUTY Scan : NO K
1977 01:00:59.861666 ZQ Calibration : PASS
1978 01:00:59.861742 Jitter Meter : NO K
1979 01:00:59.861818 CBT Training : PASS
1980 01:00:59.861894 Write leveling : PASS
1981 01:00:59.861969 RX DQS gating : PASS
1982 01:00:59.862045 RX DQ/DQS(RDDQC) : PASS
1983 01:00:59.862121 TX DQ/DQS : PASS
1984 01:00:59.862198 RX DATLAT : PASS
1985 01:00:59.862288 RX DQ/DQS(Engine): PASS
1986 01:00:59.862337 TX OE : NO K
1987 01:00:59.862387 All Pass.
1988 01:00:59.862436
1989 01:00:59.862485 CH 1, Rank 0
1990 01:00:59.862533 SW Impedance : PASS
1991 01:00:59.862582 DUTY Scan : NO K
1992 01:00:59.862630 ZQ Calibration : PASS
1993 01:00:59.862679 Jitter Meter : NO K
1994 01:00:59.862727 CBT Training : PASS
1995 01:00:59.862774 Write leveling : PASS
1996 01:00:59.862822 RX DQS gating : PASS
1997 01:00:59.862871 RX DQ/DQS(RDDQC) : PASS
1998 01:00:59.862920 TX DQ/DQS : PASS
1999 01:00:59.862968 RX DATLAT : PASS
2000 01:00:59.863017 RX DQ/DQS(Engine): PASS
2001 01:00:59.863065 TX OE : NO K
2002 01:00:59.863113 All Pass.
2003 01:00:59.863161
2004 01:00:59.863209 CH 1, Rank 1
2005 01:00:59.989723 SW Impedance : PASS
2006 01:00:59.990203 DUTY Scan : NO K
2007 01:00:59.990597 ZQ Calibration : PASS
2008 01:00:59.990910 Jitter Meter : NO K
2009 01:00:59.991207 CBT Training : PASS
2010 01:00:59.991498 Write leveling : PASS
2011 01:00:59.991788 RX DQS gating : PASS
2012 01:00:59.992071 RX DQ/DQS(RDDQC) : PASS
2013 01:00:59.992350 TX DQ/DQS : PASS
2014 01:00:59.992630 RX DATLAT : PASS
2015 01:00:59.992927 RX DQ/DQS(Engine): PASS
2016 01:00:59.993220 TX OE : NO K
2017 01:00:59.993498 All Pass.
2018 01:00:59.993775
2019 01:00:59.994051 DramC Write-DBI off
2020 01:00:59.994377 PER_BANK_REFRESH: Hybrid Mode
2021 01:00:59.994723 TX_TRACKING: ON
2022 01:00:59.995011 [GetDramInforAfterCalByMRR] Vendor 6.
2023 01:00:59.995287 [GetDramInforAfterCalByMRR] Revision 606.
2024 01:00:59.995565 [GetDramInforAfterCalByMRR] Revision 2 0.
2025 01:00:59.995849 MR0 0x3939
2026 01:00:59.996131 MR8 0x1111
2027 01:00:59.996437 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2028 01:00:59.996719
2029 01:00:59.996998 MR0 0x3939
2030 01:00:59.997276 MR8 0x1111
2031 01:00:59.997552 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2032 01:00:59.997834
2033 01:00:59.998113 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2034 01:00:59.998453 [FAST_K] Save calibration result to emmc
2035 01:00:59.998741 [FAST_K] Save calibration result to emmc
2036 01:00:59.999020 dram_init: config_dvfs: 1
2037 01:00:59.999296 dramc_set_vcore_voltage set vcore to 662500
2038 01:00:59.999614 Read voltage for 1200, 2
2039 01:00:59.999898 Vio18 = 0
2040 01:01:00.000174 Vcore = 662500
2041 01:01:00.000446 Vdram = 0
2042 01:01:00.000740 Vddq = 0
2043 01:01:00.001023 Vmddr = 0
2044 01:01:00.001305 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2045 01:01:00.001640 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2046 01:01:00.001927 MEM_TYPE=3, freq_sel=15
2047 01:01:00.002248 sv_algorithm_assistance_LP4_1600
2048 01:01:00.002567 ============ PULL DRAM RESETB DOWN ============
2049 01:01:00.003042 ========== PULL DRAM RESETB DOWN end =========
2050 01:01:00.003395 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2051 01:01:00.003684 ===================================
2052 01:01:00.003964 LPDDR4 DRAM CONFIGURATION
2053 01:01:00.004245 ===================================
2054 01:01:00.004520 EX_ROW_EN[0] = 0x0
2055 01:01:00.004793 EX_ROW_EN[1] = 0x0
2056 01:01:00.005171 LP4Y_EN = 0x0
2057 01:01:00.005460 WORK_FSP = 0x0
2058 01:01:00.005738 WL = 0x4
2059 01:01:00.006015 RL = 0x4
2060 01:01:00.006315 BL = 0x2
2061 01:01:00.006594 RPST = 0x0
2062 01:01:00.006843 RD_PRE = 0x0
2063 01:01:00.007091 WR_PRE = 0x1
2064 01:01:00.007340 WR_PST = 0x0
2065 01:01:00.007589 DBI_WR = 0x0
2066 01:01:00.007838 DBI_RD = 0x0
2067 01:01:00.008090 OTF = 0x1
2068 01:01:00.008342 ===================================
2069 01:01:00.008597 ===================================
2070 01:01:00.008848 ANA top config
2071 01:01:00.009099 ===================================
2072 01:01:00.009353 DLL_ASYNC_EN = 0
2073 01:01:00.009603 ALL_SLAVE_EN = 0
2074 01:01:00.009851 NEW_RANK_MODE = 1
2075 01:01:00.010103 DLL_IDLE_MODE = 1
2076 01:01:00.010377 LP45_APHY_COMB_EN = 1
2077 01:01:00.010632 TX_ODT_DIS = 1
2078 01:01:00.010884 NEW_8X_MODE = 1
2079 01:01:00.011138 ===================================
2080 01:01:00.011387 ===================================
2081 01:01:00.011643 data_rate = 2400
2082 01:01:00.011891 CKR = 1
2083 01:01:00.012141 DQ_P2S_RATIO = 8
2084 01:01:00.012392 ===================================
2085 01:01:00.012643 CA_P2S_RATIO = 8
2086 01:01:00.012892 DQ_CA_OPEN = 0
2087 01:01:00.013140 DQ_SEMI_OPEN = 0
2088 01:01:00.013389 CA_SEMI_OPEN = 0
2089 01:01:00.013636 CA_FULL_RATE = 0
2090 01:01:00.013884 DQ_CKDIV4_EN = 0
2091 01:01:00.014132 CA_CKDIV4_EN = 0
2092 01:01:00.014411 CA_PREDIV_EN = 0
2093 01:01:00.014662 PH8_DLY = 17
2094 01:01:00.014909 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2095 01:01:00.015163 DQ_AAMCK_DIV = 4
2096 01:01:00.015414 CA_AAMCK_DIV = 4
2097 01:01:00.015663 CA_ADMCK_DIV = 4
2098 01:01:00.015913 DQ_TRACK_CA_EN = 0
2099 01:01:00.016165 CA_PICK = 1200
2100 01:01:00.016416 CA_MCKIO = 1200
2101 01:01:00.016665 MCKIO_SEMI = 0
2102 01:01:00.016917 PLL_FREQ = 2366
2103 01:01:00.017173 DQ_UI_PI_RATIO = 32
2104 01:01:00.017429 CA_UI_PI_RATIO = 0
2105 01:01:00.017682 ===================================
2106 01:01:00.017936 ===================================
2107 01:01:00.018189 memory_type:LPDDR4
2108 01:01:00.018747 GP_NUM : 10
2109 01:01:00.018957 SRAM_EN : 1
2110 01:01:00.019144 MD32_EN : 0
2111 01:01:00.019327 ===================================
2112 01:01:00.019511 [ANA_INIT] >>>>>>>>>>>>>>
2113 01:01:00.019693 <<<<<< [CONFIGURE PHASE]: ANA_TX
2114 01:01:00.019878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2115 01:01:00.020060 ===================================
2116 01:01:00.020244 data_rate = 2400,PCW = 0X5b00
2117 01:01:00.020424 ===================================
2118 01:01:00.020604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2119 01:01:00.020786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2120 01:01:00.020968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2121 01:01:00.021151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2122 01:01:00.021334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2123 01:01:00.021517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2124 01:01:00.021699 [ANA_INIT] flow start
2125 01:01:00.021876 [ANA_INIT] PLL >>>>>>>>
2126 01:01:00.022055 [ANA_INIT] PLL <<<<<<<<
2127 01:01:00.022258 [ANA_INIT] MIDPI >>>>>>>>
2128 01:01:00.022443 [ANA_INIT] MIDPI <<<<<<<<
2129 01:01:00.022628 [ANA_INIT] DLL >>>>>>>>
2130 01:01:00.022809 [ANA_INIT] DLL <<<<<<<<
2131 01:01:00.022989 [ANA_INIT] flow end
2132 01:01:00.023171 ============ LP4 DIFF to SE enter ============
2133 01:01:00.023354 ============ LP4 DIFF to SE exit ============
2134 01:01:00.023489 [ANA_INIT] <<<<<<<<<<<<<
2135 01:01:00.023625 [Flow] Enable top DCM control >>>>>
2136 01:01:00.023762 [Flow] Enable top DCM control <<<<<
2137 01:01:00.023900 Enable DLL master slave shuffle
2138 01:01:00.024037 ==============================================================
2139 01:01:00.024174 Gating Mode config
2140 01:01:00.024310 ==============================================================
2141 01:01:00.024447 Config description:
2142 01:01:00.024583 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2143 01:01:00.024725 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2144 01:01:00.024866 SELPH_MODE 0: By rank 1: By Phase
2145 01:01:00.025005 ==============================================================
2146 01:01:00.025145 GAT_TRACK_EN = 1
2147 01:01:00.025282 RX_GATING_MODE = 2
2148 01:01:00.025419 RX_GATING_TRACK_MODE = 2
2149 01:01:00.025556 SELPH_MODE = 1
2150 01:01:00.025691 PICG_EARLY_EN = 1
2151 01:01:00.025827 VALID_LAT_VALUE = 1
2152 01:01:00.025963 ==============================================================
2153 01:01:00.026102 Enter into Gating configuration >>>>
2154 01:01:00.026248 Exit from Gating configuration <<<<
2155 01:01:00.026386 Enter into DVFS_PRE_config >>>>>
2156 01:01:00.026524 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2157 01:01:00.026665 Exit from DVFS_PRE_config <<<<<
2158 01:01:00.026801 Enter into PICG configuration >>>>
2159 01:01:00.026936 Exit from PICG configuration <<<<
2160 01:01:00.027070 [RX_INPUT] configuration >>>>>
2161 01:01:00.027211 [RX_INPUT] configuration <<<<<
2162 01:01:00.027373 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2163 01:01:00.027514 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2164 01:01:00.027652 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2165 01:01:00.027792 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2166 01:01:00.027929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2167 01:01:00.028066 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2168 01:01:00.028202 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2169 01:01:00.028347 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2170 01:01:00.028455 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2171 01:01:00.028565 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2172 01:01:00.028674 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2173 01:01:00.028784 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2174 01:01:00.028894 ===================================
2175 01:01:00.029003 LPDDR4 DRAM CONFIGURATION
2176 01:01:00.029111 ===================================
2177 01:01:00.029220 EX_ROW_EN[0] = 0x0
2178 01:01:00.029327 EX_ROW_EN[1] = 0x0
2179 01:01:00.029438 LP4Y_EN = 0x0
2180 01:01:00.029547 WORK_FSP = 0x0
2181 01:01:00.029656 WL = 0x4
2182 01:01:00.029765 RL = 0x4
2183 01:01:00.029875 BL = 0x2
2184 01:01:00.029983 RPST = 0x0
2185 01:01:00.030090 RD_PRE = 0x0
2186 01:01:00.030198 WR_PRE = 0x1
2187 01:01:00.030331 WR_PST = 0x0
2188 01:01:00.030442 DBI_WR = 0x0
2189 01:01:00.030551 DBI_RD = 0x0
2190 01:01:00.030660 OTF = 0x1
2191 01:01:00.030804 ===================================
2192 01:01:00.030922 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2193 01:01:00.031034 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2194 01:01:00.031144 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2195 01:01:00.031255 ===================================
2196 01:01:00.031365 LPDDR4 DRAM CONFIGURATION
2197 01:01:00.031475 ===================================
2198 01:01:00.031585 EX_ROW_EN[0] = 0x10
2199 01:01:00.031695 EX_ROW_EN[1] = 0x0
2200 01:01:00.031805 LP4Y_EN = 0x0
2201 01:01:00.031916 WORK_FSP = 0x0
2202 01:01:00.032024 WL = 0x4
2203 01:01:00.032131 RL = 0x4
2204 01:01:00.032240 BL = 0x2
2205 01:01:00.032349 RPST = 0x0
2206 01:01:00.032457 RD_PRE = 0x0
2207 01:01:00.032567 WR_PRE = 0x1
2208 01:01:00.032676 WR_PST = 0x0
2209 01:01:00.032784 DBI_WR = 0x0
2210 01:01:00.032893 DBI_RD = 0x0
2211 01:01:00.033011 OTF = 0x1
2212 01:01:00.033142 ===================================
2213 01:01:00.033255 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2214 01:01:00.033365 ==
2215 01:01:00.033458 Dram Type= 6, Freq= 0, CH_0, rank 0
2216 01:01:00.033552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2217 01:01:00.033644 ==
2218 01:01:00.033960 [Duty_Offset_Calibration]
2219 01:01:00.034065 B0:0 B1:2 CA:1
2220 01:01:00.034263
2221 01:01:00.034415 [DutyScan_Calibration_Flow] k_type=0
2222 01:01:00.034558
2223 01:01:00.034726 ==CLK 0==
2224 01:01:00.034913 Final CLK duty delay cell = 0
2225 01:01:00.035096 [0] MAX Duty = 5093%(X100), DQS PI = 12
2226 01:01:00.035285 [0] MIN Duty = 4938%(X100), DQS PI = 54
2227 01:01:00.035472 [0] AVG Duty = 5015%(X100)
2228 01:01:00.035659
2229 01:01:00.035844 CH0 CLK Duty spec in!! Max-Min= 155%
2230 01:01:00.036009 [DutyScan_Calibration_Flow] ====Done====
2231 01:01:00.036152
2232 01:01:00.036295 [DutyScan_Calibration_Flow] k_type=1
2233 01:01:00.036436
2234 01:01:00.036578 ==DQS 0 ==
2235 01:01:00.036722 Final DQS duty delay cell = 0
2236 01:01:00.036866 [0] MAX Duty = 5124%(X100), DQS PI = 50
2237 01:01:00.037009 [0] MIN Duty = 5031%(X100), DQS PI = 6
2238 01:01:00.037152 [0] AVG Duty = 5077%(X100)
2239 01:01:00.037292
2240 01:01:00.037434 ==DQS 1 ==
2241 01:01:00.037577 Final DQS duty delay cell = 0
2242 01:01:00.037721 [0] MAX Duty = 5062%(X100), DQS PI = 58
2243 01:01:00.037864 [0] MIN Duty = 4875%(X100), DQS PI = 20
2244 01:01:00.038021 [0] AVG Duty = 4968%(X100)
2245 01:01:00.038163
2246 01:01:00.038329 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2247 01:01:00.038452
2248 01:01:00.038575 CH0 DQS 1 Duty spec in!! Max-Min= 187%
2249 01:01:00.038699 [DutyScan_Calibration_Flow] ====Done====
2250 01:01:00.038821
2251 01:01:00.038944 [DutyScan_Calibration_Flow] k_type=3
2252 01:01:00.039065
2253 01:01:00.039190 ==DQM 0 ==
2254 01:01:00.039275 Final DQM duty delay cell = 0
2255 01:01:00.039355 [0] MAX Duty = 5156%(X100), DQS PI = 22
2256 01:01:00.039434 [0] MIN Duty = 4969%(X100), DQS PI = 40
2257 01:01:00.039512 [0] AVG Duty = 5062%(X100)
2258 01:01:00.039590
2259 01:01:00.039674 ==DQM 1 ==
2260 01:01:00.039755 Final DQM duty delay cell = 4
2261 01:01:00.039833 [4] MAX Duty = 5187%(X100), DQS PI = 54
2262 01:01:00.039918 [4] MIN Duty = 5000%(X100), DQS PI = 16
2263 01:01:00.040002 [4] AVG Duty = 5093%(X100)
2264 01:01:00.040081
2265 01:01:00.040160 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2266 01:01:00.040239
2267 01:01:00.040317 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2268 01:01:00.040395 [DutyScan_Calibration_Flow] ====Done====
2269 01:01:00.040474
2270 01:01:00.040552 [DutyScan_Calibration_Flow] k_type=2
2271 01:01:00.040630
2272 01:01:00.040708 ==DQ 0 ==
2273 01:01:00.040787 Final DQ duty delay cell = 0
2274 01:01:00.040865 [0] MAX Duty = 5218%(X100), DQS PI = 16
2275 01:01:00.040945 [0] MIN Duty = 4969%(X100), DQS PI = 8
2276 01:01:00.041025 [0] AVG Duty = 5093%(X100)
2277 01:01:00.041104
2278 01:01:00.041183 ==DQ 1 ==
2279 01:01:00.041262 Final DQ duty delay cell = -4
2280 01:01:00.041342 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2281 01:01:00.041420 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2282 01:01:00.041498 [-4] AVG Duty = 4969%(X100)
2283 01:01:00.041577
2284 01:01:00.041668 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2285 01:01:00.041751
2286 01:01:00.041829 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2287 01:01:00.041937 [DutyScan_Calibration_Flow] ====Done====
2288 01:01:00.042019 ==
2289 01:01:00.042097 Dram Type= 6, Freq= 0, CH_1, rank 0
2290 01:01:00.042176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2291 01:01:00.042283 ==
2292 01:01:00.042365 [Duty_Offset_Calibration]
2293 01:01:00.042444 B0:0 B1:5 CA:-5
2294 01:01:00.042522
2295 01:01:00.042600 [DutyScan_Calibration_Flow] k_type=0
2296 01:01:00.042678
2297 01:01:00.042781 ==CLK 0==
2298 01:01:00.042862 Final CLK duty delay cell = 0
2299 01:01:00.042941 [0] MAX Duty = 5094%(X100), DQS PI = 24
2300 01:01:00.043020 [0] MIN Duty = 4907%(X100), DQS PI = 2
2301 01:01:00.043099 [0] AVG Duty = 5000%(X100)
2302 01:01:00.043178
2303 01:01:00.043256 CH1 CLK Duty spec in!! Max-Min= 187%
2304 01:01:00.043343 [DutyScan_Calibration_Flow] ====Done====
2305 01:01:00.043412
2306 01:01:00.043480 [DutyScan_Calibration_Flow] k_type=1
2307 01:01:00.043550
2308 01:01:00.043617 ==DQS 0 ==
2309 01:01:00.043686 Final DQS duty delay cell = 0
2310 01:01:00.043754 [0] MAX Duty = 5125%(X100), DQS PI = 16
2311 01:01:00.043823 [0] MIN Duty = 4875%(X100), DQS PI = 42
2312 01:01:00.043901 [0] AVG Duty = 5000%(X100)
2313 01:01:00.043971
2314 01:01:00.044040 ==DQS 1 ==
2315 01:01:00.044109 Final DQS duty delay cell = -4
2316 01:01:00.044178 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2317 01:01:00.044247 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2318 01:01:00.044315 [-4] AVG Duty = 4953%(X100)
2319 01:01:00.044384
2320 01:01:00.044452 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2321 01:01:00.044520
2322 01:01:00.044589 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2323 01:01:00.044663 [DutyScan_Calibration_Flow] ====Done====
2324 01:01:00.044735
2325 01:01:00.044803 [DutyScan_Calibration_Flow] k_type=3
2326 01:01:00.044872
2327 01:01:00.044951 ==DQM 0 ==
2328 01:01:00.045020 Final DQM duty delay cell = -4
2329 01:01:00.045090 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2330 01:01:00.045158 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2331 01:01:00.045226 [-4] AVG Duty = 4968%(X100)
2332 01:01:00.045294
2333 01:01:00.045363 ==DQM 1 ==
2334 01:01:00.045432 Final DQM duty delay cell = -4
2335 01:01:00.045502 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2336 01:01:00.045580 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2337 01:01:00.045651 [-4] AVG Duty = 4968%(X100)
2338 01:01:00.045719
2339 01:01:00.045787 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2340 01:01:00.045857
2341 01:01:00.045926 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2342 01:01:00.045995 [DutyScan_Calibration_Flow] ====Done====
2343 01:01:00.046063
2344 01:01:00.046132 [DutyScan_Calibration_Flow] k_type=2
2345 01:01:00.046201
2346 01:01:00.046282 ==DQ 0 ==
2347 01:01:00.046354 Final DQ duty delay cell = 0
2348 01:01:00.046423 [0] MAX Duty = 5062%(X100), DQS PI = 0
2349 01:01:00.046492 [0] MIN Duty = 4969%(X100), DQS PI = 44
2350 01:01:00.046560 [0] AVG Duty = 5015%(X100)
2351 01:01:00.046629
2352 01:01:00.046697 ==DQ 1 ==
2353 01:01:00.046766 Final DQ duty delay cell = 0
2354 01:01:00.046835 [0] MAX Duty = 5000%(X100), DQS PI = 6
2355 01:01:00.046903 [0] MIN Duty = 4907%(X100), DQS PI = 0
2356 01:01:00.046973 [0] AVG Duty = 4953%(X100)
2357 01:01:00.047040
2358 01:01:00.047108 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2359 01:01:00.047176
2360 01:01:00.047244 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2361 01:01:00.047314 [DutyScan_Calibration_Flow] ====Done====
2362 01:01:00.047383 nWR fixed to 30
2363 01:01:00.047452 [ModeRegInit_LP4] CH0 RK0
2364 01:01:00.047520 [ModeRegInit_LP4] CH0 RK1
2365 01:01:00.047588 [ModeRegInit_LP4] CH1 RK0
2366 01:01:00.047656 [ModeRegInit_LP4] CH1 RK1
2367 01:01:00.047723 match AC timing 6
2368 01:01:00.047790 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2369 01:01:00.047863 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2370 01:01:00.047933 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2371 01:01:00.048001 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2372 01:01:00.048070 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2373 01:01:00.048138 ==
2374 01:01:00.048206 Dram Type= 6, Freq= 0, CH_0, rank 0
2375 01:01:00.048275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2376 01:01:00.048343 ==
2377 01:01:00.048625 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2378 01:01:00.048741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2379 01:01:00.048863 [CA 0] Center 39 (9~70) winsize 62
2380 01:01:00.048985 [CA 1] Center 39 (8~70) winsize 63
2381 01:01:00.049108 [CA 2] Center 36 (5~67) winsize 63
2382 01:01:00.049221 [CA 3] Center 35 (4~66) winsize 63
2383 01:01:00.049325 [CA 4] Center 34 (3~65) winsize 63
2384 01:01:00.049421 [CA 5] Center 34 (3~65) winsize 63
2385 01:01:00.049516
2386 01:01:00.049612 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2387 01:01:00.049707
2388 01:01:00.049802 [CATrainingPosCal] consider 1 rank data
2389 01:01:00.049906 u2DelayCellTimex100 = 270/100 ps
2390 01:01:00.050018 CA0 delay=39 (9~70),Diff = 5 PI (24 cell)
2391 01:01:00.050117 CA1 delay=39 (8~70),Diff = 5 PI (24 cell)
2392 01:01:00.050223 CA2 delay=36 (5~67),Diff = 2 PI (9 cell)
2393 01:01:00.050291 CA3 delay=35 (4~66),Diff = 1 PI (4 cell)
2394 01:01:00.050353 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
2395 01:01:00.050420 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
2396 01:01:00.050483
2397 01:01:00.050545 CA PerBit enable=1, Macro0, CA PI delay=34
2398 01:01:00.050606
2399 01:01:00.050667 [CBTSetCACLKResult] CA Dly = 34
2400 01:01:00.050730 CS Dly: 7 (0~38)
2401 01:01:00.050790 ==
2402 01:01:00.050852 Dram Type= 6, Freq= 0, CH_0, rank 1
2403 01:01:00.050914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2404 01:01:00.050976 ==
2405 01:01:00.051036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2406 01:01:00.051096 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2407 01:01:00.051157 [CA 0] Center 39 (8~70) winsize 63
2408 01:01:00.051218 [CA 1] Center 39 (8~70) winsize 63
2409 01:01:00.051278 [CA 2] Center 36 (5~67) winsize 63
2410 01:01:00.051338 [CA 3] Center 35 (4~66) winsize 63
2411 01:01:00.051398 [CA 4] Center 33 (3~64) winsize 62
2412 01:01:00.051459 [CA 5] Center 33 (3~64) winsize 62
2413 01:01:00.051519
2414 01:01:00.051578 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2415 01:01:00.051638
2416 01:01:00.051698 [CATrainingPosCal] consider 2 rank data
2417 01:01:00.051759 u2DelayCellTimex100 = 270/100 ps
2418 01:01:00.051820 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2419 01:01:00.051881 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2420 01:01:00.051942 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2421 01:01:00.052002 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2422 01:01:00.052063 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2423 01:01:00.052127 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2424 01:01:00.052189
2425 01:01:00.052249 CA PerBit enable=1, Macro0, CA PI delay=33
2426 01:01:00.052310
2427 01:01:00.052371 [CBTSetCACLKResult] CA Dly = 33
2428 01:01:00.052431 CS Dly: 7 (0~39)
2429 01:01:00.052491
2430 01:01:00.052551 ----->DramcWriteLeveling(PI) begin...
2431 01:01:00.052614 ==
2432 01:01:00.052676 Dram Type= 6, Freq= 0, CH_0, rank 0
2433 01:01:00.052736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2434 01:01:00.052796 ==
2435 01:01:00.052856 Write leveling (Byte 0): 29 => 29
2436 01:01:00.052917 Write leveling (Byte 1): 25 => 25
2437 01:01:00.052977 DramcWriteLeveling(PI) end<-----
2438 01:01:00.053040
2439 01:01:00.053106 ==
2440 01:01:00.053177 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 01:01:00.053250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2442 01:01:00.053354 ==
2443 01:01:00.053445 [Gating] SW mode calibration
2444 01:01:00.053535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2445 01:01:00.053628 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2446 01:01:00.053716 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2447 01:01:00.053805 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2448 01:01:00.053892 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2449 01:01:00.053982 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2450 01:01:00.054071 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2451 01:01:00.054159 0 11 20 | B1->B0 | 2c2c 2727 | 0 0 | (1 0) (0 0)
2452 01:01:00.054251 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2453 01:01:00.054311 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2454 01:01:00.054374 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2455 01:01:00.054432 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2456 01:01:00.054487 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2457 01:01:00.054545 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2458 01:01:00.054601 0 12 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2459 01:01:00.054655 0 12 20 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
2460 01:01:00.054711 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2461 01:01:00.054768 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2462 01:01:00.054823 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2463 01:01:00.054878 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2464 01:01:00.054956 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2465 01:01:00.055043 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2466 01:01:00.055131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2467 01:01:00.055218 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2468 01:01:00.055307 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 01:01:00.055394 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 01:01:00.055486 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 01:01:00.055577 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 01:01:00.055664 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 01:01:00.055751 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 01:01:00.055837 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 01:01:00.055925 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 01:01:00.056012 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 01:01:00.056093 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 01:01:00.056150 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 01:01:00.056206 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 01:01:00.056260 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 01:01:00.056315 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 01:01:00.056571 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2483 01:01:00.056660 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2484 01:01:00.056769 Total UI for P1: 0, mck2ui 16
2485 01:01:00.056880 best dqsien dly found for B1: ( 0, 15, 16)
2486 01:01:00.056989 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2487 01:01:00.057094 Total UI for P1: 0, mck2ui 16
2488 01:01:00.057184 best dqsien dly found for B0: ( 0, 15, 18)
2489 01:01:00.057270 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2490 01:01:00.057357 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
2491 01:01:00.057441
2492 01:01:00.057527 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2493 01:01:00.057613 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
2494 01:01:00.057699 [Gating] SW calibration Done
2495 01:01:00.057783 ==
2496 01:01:00.057869 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 01:01:00.057955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2498 01:01:00.058040 ==
2499 01:01:00.058125 RX Vref Scan: 0
2500 01:01:00.058215
2501 01:01:00.058304 RX Vref 0 -> 0, step: 1
2502 01:01:00.058400
2503 01:01:00.058477 RX Delay -40 -> 252, step: 8
2504 01:01:00.058556 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2505 01:01:00.058635 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2506 01:01:00.058689 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2507 01:01:00.058739 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2508 01:01:00.058790 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2509 01:01:00.058839 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2510 01:01:00.058889 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2511 01:01:00.058938 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2512 01:01:00.058989 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2513 01:01:00.059039 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2514 01:01:00.059089 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2515 01:01:00.059140 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2516 01:01:00.059190 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2517 01:01:00.059240 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2518 01:01:00.059289 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2519 01:01:00.059339 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2520 01:01:00.059389 ==
2521 01:01:00.059438 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 01:01:00.059488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2523 01:01:00.059538 ==
2524 01:01:00.059588 DQS Delay:
2525 01:01:00.059638 DQS0 = 0, DQS1 = 0
2526 01:01:00.059688 DQM Delay:
2527 01:01:00.059736 DQM0 = 115, DQM1 = 105
2528 01:01:00.059786 DQ Delay:
2529 01:01:00.059835 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2530 01:01:00.059885 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2531 01:01:00.059935 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2532 01:01:00.059985 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2533 01:01:00.060034
2534 01:01:00.060083
2535 01:01:00.060132 ==
2536 01:01:00.060181 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 01:01:00.060231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2538 01:01:00.060280 ==
2539 01:01:00.060329
2540 01:01:00.060378
2541 01:01:00.060431 TX Vref Scan disable
2542 01:01:00.060482 == TX Byte 0 ==
2543 01:01:00.060532 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2544 01:01:00.060582 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2545 01:01:00.060641 == TX Byte 1 ==
2546 01:01:00.060691 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2547 01:01:00.060741 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2548 01:01:00.060790 ==
2549 01:01:00.060840 Dram Type= 6, Freq= 0, CH_0, rank 0
2550 01:01:00.060891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2551 01:01:00.060941 ==
2552 01:01:00.060991 TX Vref=22, minBit 10, minWin=24, winSum=411
2553 01:01:00.061042 TX Vref=24, minBit 8, minWin=25, winSum=417
2554 01:01:00.061093 TX Vref=26, minBit 9, minWin=25, winSum=418
2555 01:01:00.061142 TX Vref=28, minBit 10, minWin=25, winSum=424
2556 01:01:00.061192 TX Vref=30, minBit 8, minWin=26, winSum=429
2557 01:01:00.061242 TX Vref=32, minBit 6, minWin=26, winSum=429
2558 01:01:00.061292 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
2559 01:01:00.061343
2560 01:01:00.061392 Final TX Range 1 Vref 30
2561 01:01:00.061442
2562 01:01:00.061491 ==
2563 01:01:00.061541 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 01:01:00.061590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2565 01:01:00.061640 ==
2566 01:01:00.061689
2567 01:01:00.061738
2568 01:01:00.061788 TX Vref Scan disable
2569 01:01:00.061837 == TX Byte 0 ==
2570 01:01:00.061887 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2571 01:01:00.061938 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2572 01:01:00.061994 == TX Byte 1 ==
2573 01:01:00.062045 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2574 01:01:00.062095 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2575 01:01:00.062144
2576 01:01:00.062193 [DATLAT]
2577 01:01:00.062252 Freq=1200, CH0 RK0
2578 01:01:00.062303
2579 01:01:00.062352 DATLAT Default: 0xd
2580 01:01:00.062402 0, 0xFFFF, sum = 0
2581 01:01:00.062452 1, 0xFFFF, sum = 0
2582 01:01:00.062502 2, 0xFFFF, sum = 0
2583 01:01:00.062553 3, 0xFFFF, sum = 0
2584 01:01:00.062602 4, 0xFFFF, sum = 0
2585 01:01:00.062652 5, 0xFFFF, sum = 0
2586 01:01:00.062702 6, 0xFFFF, sum = 0
2587 01:01:00.062753 7, 0xFFFF, sum = 0
2588 01:01:00.062803 8, 0xFFFF, sum = 0
2589 01:01:00.062854 9, 0xFFFF, sum = 0
2590 01:01:00.062904 10, 0xFFFF, sum = 0
2591 01:01:00.062954 11, 0x0, sum = 1
2592 01:01:00.063004 12, 0x0, sum = 2
2593 01:01:00.063054 13, 0x0, sum = 3
2594 01:01:00.063105 14, 0x0, sum = 4
2595 01:01:00.063154 best_step = 12
2596 01:01:00.063204
2597 01:01:00.063253 ==
2598 01:01:00.063302 Dram Type= 6, Freq= 0, CH_0, rank 0
2599 01:01:00.063353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2600 01:01:00.063414 ==
2601 01:01:00.063462 RX Vref Scan: 1
2602 01:01:00.063511
2603 01:01:00.063559 Set Vref Range= 32 -> 127
2604 01:01:00.063608
2605 01:01:00.063656 RX Vref 32 -> 127, step: 1
2606 01:01:00.063703
2607 01:01:00.063752 RX Delay -21 -> 252, step: 4
2608 01:01:00.063800
2609 01:01:00.063848 Set Vref, RX VrefLevel [Byte0]: 32
2610 01:01:00.063896 [Byte1]: 32
2611 01:01:00.063944
2612 01:01:00.064000 Set Vref, RX VrefLevel [Byte0]: 33
2613 01:01:00.064053 [Byte1]: 33
2614 01:01:00.064115
2615 01:01:00.064172 Set Vref, RX VrefLevel [Byte0]: 34
2616 01:01:00.064231 [Byte1]: 34
2617 01:01:00.064283
2618 01:01:00.064332 Set Vref, RX VrefLevel [Byte0]: 35
2619 01:01:00.064384 [Byte1]: 35
2620 01:01:00.064434
2621 01:01:00.064484 Set Vref, RX VrefLevel [Byte0]: 36
2622 01:01:00.064533 [Byte1]: 36
2623 01:01:00.064582
2624 01:01:00.064630 Set Vref, RX VrefLevel [Byte0]: 37
2625 01:01:00.064679 [Byte1]: 37
2626 01:01:00.064727
2627 01:01:00.064776 Set Vref, RX VrefLevel [Byte0]: 38
2628 01:01:00.064824 [Byte1]: 38
2629 01:01:00.064872
2630 01:01:00.064920 Set Vref, RX VrefLevel [Byte0]: 39
2631 01:01:00.064969 [Byte1]: 39
2632 01:01:00.065017
2633 01:01:00.065065 Set Vref, RX VrefLevel [Byte0]: 40
2634 01:01:00.065306 [Byte1]: 40
2635 01:01:00.065403
2636 01:01:00.065500 Set Vref, RX VrefLevel [Byte0]: 41
2637 01:01:00.065597 [Byte1]: 41
2638 01:01:00.065693
2639 01:01:00.065777 Set Vref, RX VrefLevel [Byte0]: 42
2640 01:01:00.065862 [Byte1]: 42
2641 01:01:00.065928
2642 01:01:00.066013 Set Vref, RX VrefLevel [Byte0]: 43
2643 01:01:00.066094 [Byte1]: 43
2644 01:01:00.066176
2645 01:01:00.066304 Set Vref, RX VrefLevel [Byte0]: 44
2646 01:01:00.066387 [Byte1]: 44
2647 01:01:00.066470
2648 01:01:00.066552 Set Vref, RX VrefLevel [Byte0]: 45
2649 01:01:00.066633 [Byte1]: 45
2650 01:01:00.066710
2651 01:01:00.066786 Set Vref, RX VrefLevel [Byte0]: 46
2652 01:01:00.066863 [Byte1]: 46
2653 01:01:00.066938
2654 01:01:00.067014 Set Vref, RX VrefLevel [Byte0]: 47
2655 01:01:00.067091 [Byte1]: 47
2656 01:01:00.067167
2657 01:01:00.067243 Set Vref, RX VrefLevel [Byte0]: 48
2658 01:01:00.067320 [Byte1]: 48
2659 01:01:00.067396
2660 01:01:00.067477 Set Vref, RX VrefLevel [Byte0]: 49
2661 01:01:00.067561 [Byte1]: 49
2662 01:01:00.067643
2663 01:01:00.067726 Set Vref, RX VrefLevel [Byte0]: 50
2664 01:01:00.067808 [Byte1]: 50
2665 01:01:00.067887
2666 01:01:00.067963 Set Vref, RX VrefLevel [Byte0]: 51
2667 01:01:00.068040 [Byte1]: 51
2668 01:01:00.068115
2669 01:01:00.068191 Set Vref, RX VrefLevel [Byte0]: 52
2670 01:01:00.068272 [Byte1]: 52
2671 01:01:00.068350
2672 01:01:00.068426 Set Vref, RX VrefLevel [Byte0]: 53
2673 01:01:00.068503 [Byte1]: 53
2674 01:01:00.068579
2675 01:01:00.068655 Set Vref, RX VrefLevel [Byte0]: 54
2676 01:01:00.068732 [Byte1]: 54
2677 01:01:00.068807
2678 01:01:00.068883 Set Vref, RX VrefLevel [Byte0]: 55
2679 01:01:00.068960 [Byte1]: 55
2680 01:01:00.069035
2681 01:01:00.069111 Set Vref, RX VrefLevel [Byte0]: 56
2682 01:01:00.069188 [Byte1]: 56
2683 01:01:00.069265
2684 01:01:00.069341 Set Vref, RX VrefLevel [Byte0]: 57
2685 01:01:00.069418 [Byte1]: 57
2686 01:01:00.069493
2687 01:01:00.069569 Set Vref, RX VrefLevel [Byte0]: 58
2688 01:01:00.069645 [Byte1]: 58
2689 01:01:00.069721
2690 01:01:00.069797 Set Vref, RX VrefLevel [Byte0]: 59
2691 01:01:00.069873 [Byte1]: 59
2692 01:01:00.069949
2693 01:01:00.070028 Set Vref, RX VrefLevel [Byte0]: 60
2694 01:01:00.070108 [Byte1]: 60
2695 01:01:00.070189
2696 01:01:00.070304 Set Vref, RX VrefLevel [Byte0]: 61
2697 01:01:00.070360 [Byte1]: 61
2698 01:01:00.070422
2699 01:01:00.070479 Set Vref, RX VrefLevel [Byte0]: 62
2700 01:01:00.070537 [Byte1]: 62
2701 01:01:00.070595
2702 01:01:00.070651 Set Vref, RX VrefLevel [Byte0]: 63
2703 01:01:00.070706 [Byte1]: 63
2704 01:01:00.070759
2705 01:01:00.070818 Set Vref, RX VrefLevel [Byte0]: 64
2706 01:01:00.070874 [Byte1]: 64
2707 01:01:00.070931
2708 01:01:00.070987 Set Vref, RX VrefLevel [Byte0]: 65
2709 01:01:00.071038 [Byte1]: 65
2710 01:01:00.071086
2711 01:01:00.071135 Set Vref, RX VrefLevel [Byte0]: 66
2712 01:01:00.071183 [Byte1]: 66
2713 01:01:00.071233
2714 01:01:00.071280 Final RX Vref Byte 0 = 50 to rank0
2715 01:01:00.071329 Final RX Vref Byte 1 = 51 to rank0
2716 01:01:00.071378 Final RX Vref Byte 0 = 50 to rank1
2717 01:01:00.071427 Final RX Vref Byte 1 = 51 to rank1==
2718 01:01:00.071476 Dram Type= 6, Freq= 0, CH_0, rank 0
2719 01:01:00.071525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2720 01:01:00.071574 ==
2721 01:01:00.071622 DQS Delay:
2722 01:01:00.071670 DQS0 = 0, DQS1 = 0
2723 01:01:00.071718 DQM Delay:
2724 01:01:00.071766 DQM0 = 114, DQM1 = 106
2725 01:01:00.071815 DQ Delay:
2726 01:01:00.071863 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =110
2727 01:01:00.071913 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2728 01:01:00.071962 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =100
2729 01:01:00.072011 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =118
2730 01:01:00.072060
2731 01:01:00.072109
2732 01:01:00.072157 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2733 01:01:00.072207 CH0 RK0: MR19=404, MR18=D0D
2734 01:01:00.072255 CH0_RK0: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
2735 01:01:00.072304
2736 01:01:00.072352 ----->DramcWriteLeveling(PI) begin...
2737 01:01:00.072401 ==
2738 01:01:00.072449 Dram Type= 6, Freq= 0, CH_0, rank 1
2739 01:01:00.072498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2740 01:01:00.072547 ==
2741 01:01:00.072595 Write leveling (Byte 0): 28 => 28
2742 01:01:00.072643 Write leveling (Byte 1): 24 => 24
2743 01:01:00.072691 DramcWriteLeveling(PI) end<-----
2744 01:01:00.072739
2745 01:01:00.072787 ==
2746 01:01:00.072836 Dram Type= 6, Freq= 0, CH_0, rank 1
2747 01:01:00.072884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2748 01:01:00.072933 ==
2749 01:01:00.072981 [Gating] SW mode calibration
2750 01:01:00.073029 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2751 01:01:00.073079 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2752 01:01:00.073127 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2753 01:01:00.073177 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2754 01:01:00.073226 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2755 01:01:00.073274 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2756 01:01:00.073322 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2757 01:01:00.073371 0 11 20 | B1->B0 | 2d2d 2525 | 0 0 | (1 0) (0 0)
2758 01:01:00.073420 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2759 01:01:00.073467 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2760 01:01:00.073516 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2761 01:01:00.073564 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2762 01:01:00.073614 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2763 01:01:00.073663 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2764 01:01:00.073711 0 12 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2765 01:01:00.073760 0 12 20 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
2766 01:01:00.073809 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2767 01:01:00.073858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 01:01:00.073906 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2769 01:01:00.074146 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2770 01:01:00.074225 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2771 01:01:00.074325 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2772 01:01:00.074421 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2773 01:01:00.074518 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2774 01:01:00.074613 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 01:01:00.074698 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 01:01:00.074778 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 01:01:00.074830 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 01:01:00.074880 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 01:01:00.074929 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 01:01:00.074978 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 01:01:00.075027 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 01:01:00.075075 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 01:01:00.075124 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 01:01:00.075172 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 01:01:00.075220 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 01:01:00.075269 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 01:01:00.075318 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 01:01:00.075367 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2789 01:01:00.075423 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2790 01:01:00.075473 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2791 01:01:00.075521 Total UI for P1: 0, mck2ui 16
2792 01:01:00.075570 best dqsien dly found for B0: ( 0, 15, 20)
2793 01:01:00.075619 Total UI for P1: 0, mck2ui 16
2794 01:01:00.075668 best dqsien dly found for B1: ( 0, 15, 20)
2795 01:01:00.075718 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2796 01:01:00.075768 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2797 01:01:00.075817
2798 01:01:00.075865 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2799 01:01:00.075914 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2800 01:01:00.075963 [Gating] SW calibration Done
2801 01:01:00.076011 ==
2802 01:01:00.076060 Dram Type= 6, Freq= 0, CH_0, rank 1
2803 01:01:00.076112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2804 01:01:00.076163 ==
2805 01:01:00.076212 RX Vref Scan: 0
2806 01:01:00.076261
2807 01:01:00.076318 RX Vref 0 -> 0, step: 1
2808 01:01:00.076368
2809 01:01:00.076417 RX Delay -40 -> 252, step: 8
2810 01:01:00.076466 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2811 01:01:00.076515 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2812 01:01:00.076563 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2813 01:01:00.076612 iDelay=200, Bit 3, Center 103 (32 ~ 175) 144
2814 01:01:00.076661 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2815 01:01:00.076710 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2816 01:01:00.076758 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2817 01:01:00.076807 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2818 01:01:00.076856 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2819 01:01:00.076904 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2820 01:01:00.076952 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2821 01:01:00.077001 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2822 01:01:00.077049 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2823 01:01:00.077098 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2824 01:01:00.077146 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2825 01:01:00.077195 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2826 01:01:00.077244 ==
2827 01:01:00.077292 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 01:01:00.077341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2829 01:01:00.077390 ==
2830 01:01:00.077439 DQS Delay:
2831 01:01:00.077487 DQS0 = 0, DQS1 = 0
2832 01:01:00.077536 DQM Delay:
2833 01:01:00.077583 DQM0 = 113, DQM1 = 106
2834 01:01:00.077632 DQ Delay:
2835 01:01:00.077680 DQ0 =107, DQ1 =119, DQ2 =115, DQ3 =103
2836 01:01:00.077730 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2837 01:01:00.077778 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
2838 01:01:00.077826 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2839 01:01:00.077874
2840 01:01:00.077922
2841 01:01:00.077970 ==
2842 01:01:00.078019 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 01:01:00.078068 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2844 01:01:00.078116 ==
2845 01:01:00.078164
2846 01:01:00.078216
2847 01:01:00.078304 TX Vref Scan disable
2848 01:01:00.078353 == TX Byte 0 ==
2849 01:01:00.078401 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2850 01:01:00.078449 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2851 01:01:00.078499 == TX Byte 1 ==
2852 01:01:00.078555 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2853 01:01:00.078605 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2854 01:01:00.078654 ==
2855 01:01:00.078703 Dram Type= 6, Freq= 0, CH_0, rank 1
2856 01:01:00.078751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2857 01:01:00.078800 ==
2858 01:01:00.078848 TX Vref=22, minBit 8, minWin=24, winSum=413
2859 01:01:00.078898 TX Vref=24, minBit 8, minWin=25, winSum=420
2860 01:01:00.078948 TX Vref=26, minBit 8, minWin=25, winSum=420
2861 01:01:00.078997 TX Vref=28, minBit 7, minWin=26, winSum=426
2862 01:01:00.079046 TX Vref=30, minBit 4, minWin=26, winSum=425
2863 01:01:00.079095 TX Vref=32, minBit 8, minWin=25, winSum=423
2864 01:01:00.079145 [TxChooseVref] Worse bit 7, Min win 26, Win sum 426, Final Vref 28
2865 01:01:00.079194
2866 01:01:00.079242 Final TX Range 1 Vref 28
2867 01:01:00.079291
2868 01:01:00.079340 ==
2869 01:01:00.079389 Dram Type= 6, Freq= 0, CH_0, rank 1
2870 01:01:00.079438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2871 01:01:00.079487 ==
2872 01:01:00.079535
2873 01:01:00.079582
2874 01:01:00.079630 TX Vref Scan disable
2875 01:01:00.079678 == TX Byte 0 ==
2876 01:01:00.079726 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2877 01:01:00.079776 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2878 01:01:00.079825 == TX Byte 1 ==
2879 01:01:00.079874 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2880 01:01:00.079923 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2881 01:01:00.079971
2882 01:01:00.080020 [DATLAT]
2883 01:01:00.080068 Freq=1200, CH0 RK1
2884 01:01:00.080117
2885 01:01:00.080165 DATLAT Default: 0xc
2886 01:01:00.080213 0, 0xFFFF, sum = 0
2887 01:01:00.080263 1, 0xFFFF, sum = 0
2888 01:01:00.080312 2, 0xFFFF, sum = 0
2889 01:01:00.080361 3, 0xFFFF, sum = 0
2890 01:01:00.080410 4, 0xFFFF, sum = 0
2891 01:01:00.080459 5, 0xFFFF, sum = 0
2892 01:01:00.080508 6, 0xFFFF, sum = 0
2893 01:01:00.080557 7, 0xFFFF, sum = 0
2894 01:01:00.080607 8, 0xFFFF, sum = 0
2895 01:01:00.080847 9, 0xFFFF, sum = 0
2896 01:01:00.080929 10, 0xFFFF, sum = 0
2897 01:01:00.081028 11, 0x0, sum = 1
2898 01:01:00.081127 12, 0x0, sum = 2
2899 01:01:00.081225 13, 0x0, sum = 3
2900 01:01:00.081321 14, 0x0, sum = 4
2901 01:01:00.081407 best_step = 12
2902 01:01:00.081486
2903 01:01:00.081562 ==
2904 01:01:00.081639 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 01:01:00.081716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2906 01:01:00.081793 ==
2907 01:01:00.081870 RX Vref Scan: 0
2908 01:01:00.081945
2909 01:01:00.082021 RX Vref 0 -> 0, step: 1
2910 01:01:00.082097
2911 01:01:00.082173 RX Delay -21 -> 252, step: 4
2912 01:01:00.082297 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2913 01:01:00.082364 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2914 01:01:00.082414 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2915 01:01:00.082463 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2916 01:01:00.082512 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2917 01:01:00.082562 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2918 01:01:00.082611 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2919 01:01:00.082660 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2920 01:01:00.082711 iDelay=195, Bit 8, Center 92 (31 ~ 154) 124
2921 01:01:00.082761 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2922 01:01:00.082810 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
2923 01:01:00.082858 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2924 01:01:00.082907 iDelay=195, Bit 12, Center 112 (51 ~ 174) 124
2925 01:01:00.082957 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
2926 01:01:00.083006 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2927 01:01:00.083054 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2928 01:01:00.083103 ==
2929 01:01:00.083153 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 01:01:00.083202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2931 01:01:00.083250 ==
2932 01:01:00.083299 DQS Delay:
2933 01:01:00.083348 DQS0 = 0, DQS1 = 0
2934 01:01:00.083396 DQM Delay:
2935 01:01:00.083446 DQM0 = 114, DQM1 = 105
2936 01:01:00.083495 DQ Delay:
2937 01:01:00.083544 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2938 01:01:00.083593 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2939 01:01:00.083642 DQ8 =92, DQ9 =90, DQ10 =108, DQ11 =96
2940 01:01:00.083691 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =114
2941 01:01:00.083739
2942 01:01:00.083788
2943 01:01:00.083836 [DQSOSCAuto] RK1, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
2944 01:01:00.083886 CH0 RK1: MR19=404, MR18=1515
2945 01:01:00.083935 CH0_RK1: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27
2946 01:01:00.083984 [RxdqsGatingPostProcess] freq 1200
2947 01:01:00.084033 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2948 01:01:00.084082 Pre-setting of DQS Precalculation
2949 01:01:00.084132 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2950 01:01:00.084181 ==
2951 01:01:00.084230 Dram Type= 6, Freq= 0, CH_1, rank 0
2952 01:01:00.084278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2953 01:01:00.084328 ==
2954 01:01:00.084378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2955 01:01:00.084428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2956 01:01:00.084477 [CA 0] Center 37 (7~68) winsize 62
2957 01:01:00.084526 [CA 1] Center 37 (6~68) winsize 63
2958 01:01:00.084576 [CA 2] Center 34 (4~65) winsize 62
2959 01:01:00.084624 [CA 3] Center 33 (3~64) winsize 62
2960 01:01:00.084673 [CA 4] Center 32 (2~63) winsize 62
2961 01:01:00.084722 [CA 5] Center 32 (2~63) winsize 62
2962 01:01:00.084771
2963 01:01:00.084820 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2964 01:01:00.084868
2965 01:01:00.084917 [CATrainingPosCal] consider 1 rank data
2966 01:01:00.084966 u2DelayCellTimex100 = 270/100 ps
2967 01:01:00.085014 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2968 01:01:00.085063 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2969 01:01:00.085111 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2970 01:01:00.085160 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2971 01:01:00.085209 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2972 01:01:00.085258 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2973 01:01:00.085306
2974 01:01:00.085354 CA PerBit enable=1, Macro0, CA PI delay=32
2975 01:01:00.085402
2976 01:01:00.085450 [CBTSetCACLKResult] CA Dly = 32
2977 01:01:00.085499 CS Dly: 6 (0~37)
2978 01:01:00.085547 ==
2979 01:01:00.085596 Dram Type= 6, Freq= 0, CH_1, rank 1
2980 01:01:00.085645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2981 01:01:00.085694 ==
2982 01:01:00.085743 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2983 01:01:00.085792 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2984 01:01:00.085842 [CA 0] Center 37 (7~68) winsize 62
2985 01:01:00.085890 [CA 1] Center 37 (7~68) winsize 62
2986 01:01:00.085938 [CA 2] Center 33 (3~64) winsize 62
2987 01:01:00.085986 [CA 3] Center 33 (3~64) winsize 62
2988 01:01:00.086034 [CA 4] Center 32 (1~63) winsize 63
2989 01:01:00.086083 [CA 5] Center 32 (1~63) winsize 63
2990 01:01:00.086131
2991 01:01:00.086179 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2992 01:01:00.086233
2993 01:01:00.086323 [CATrainingPosCal] consider 2 rank data
2994 01:01:00.086372 u2DelayCellTimex100 = 270/100 ps
2995 01:01:00.086420 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2996 01:01:00.086469 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2997 01:01:00.256887 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2998 01:01:00.257374 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2999 01:01:00.257735 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3000 01:01:00.258055 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3001 01:01:00.258407
3002 01:01:00.258707 CA PerBit enable=1, Macro0, CA PI delay=32
3003 01:01:00.258999
3004 01:01:00.259309 [CBTSetCACLKResult] CA Dly = 32
3005 01:01:00.259608 CS Dly: 6 (0~38)
3006 01:01:00.259897
3007 01:01:00.260229 ----->DramcWriteLeveling(PI) begin...
3008 01:01:00.260613 ==
3009 01:01:00.260922 Dram Type= 6, Freq= 0, CH_1, rank 0
3010 01:01:00.261215 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3011 01:01:00.261499 ==
3012 01:01:00.261778 Write leveling (Byte 0): 22 => 22
3013 01:01:00.262057 Write leveling (Byte 1): 22 => 22
3014 01:01:00.262523 DramcWriteLeveling(PI) end<-----
3015 01:01:00.262828
3016 01:01:00.263112 ==
3017 01:01:00.263394 Dram Type= 6, Freq= 0, CH_1, rank 0
3018 01:01:00.263675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3019 01:01:00.263962 ==
3020 01:01:00.264267 [Gating] SW mode calibration
3021 01:01:00.264612 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3022 01:01:00.265499 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3023 01:01:00.266119 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3024 01:01:00.266763 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3025 01:01:00.267377 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3026 01:01:00.267982 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3027 01:01:00.268439 0 11 16 | B1->B0 | 2e2e 2727 | 1 0 | (1 1) (1 0)
3028 01:01:00.268909 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3029 01:01:00.269356 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3030 01:01:00.269806 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3031 01:01:00.270275 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3032 01:01:00.270585 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3033 01:01:00.270920 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3034 01:01:00.271205 0 12 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3035 01:01:00.271489 0 12 16 | B1->B0 | 2e2e 4343 | 0 0 | (0 0) (0 0)
3036 01:01:00.271800 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 01:01:00.272081 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 01:01:00.272362 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3039 01:01:00.272642 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3040 01:01:00.272924 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3041 01:01:00.273199 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3042 01:01:00.273475 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3043 01:01:00.273751 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3044 01:01:00.274029 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3045 01:01:00.274335 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3046 01:01:00.274616 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 01:01:00.274928 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 01:01:00.275235 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 01:01:00.275513 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 01:01:00.275791 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 01:01:00.276112 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 01:01:00.276394 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 01:01:00.276675 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 01:01:00.276952 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 01:01:00.277228 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 01:01:00.277504 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 01:01:00.277782 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 01:01:00.278059 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3059 01:01:00.278462 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3060 01:01:00.278750 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3061 01:01:00.279032 Total UI for P1: 0, mck2ui 16
3062 01:01:00.279314 best dqsien dly found for B0: ( 0, 15, 14)
3063 01:01:00.279592 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3064 01:01:00.279869 Total UI for P1: 0, mck2ui 16
3065 01:01:00.280148 best dqsien dly found for B1: ( 0, 15, 18)
3066 01:01:00.280448 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3067 01:01:00.280726 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3068 01:01:00.281002
3069 01:01:00.281324 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3070 01:01:00.281641 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3071 01:01:00.281931 [Gating] SW calibration Done
3072 01:01:00.282234 ==
3073 01:01:00.282528 Dram Type= 6, Freq= 0, CH_1, rank 0
3074 01:01:00.282790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3075 01:01:00.283050 ==
3076 01:01:00.283319 RX Vref Scan: 0
3077 01:01:00.283501
3078 01:01:00.283683 RX Vref 0 -> 0, step: 1
3079 01:01:00.283865
3080 01:01:00.284045 RX Delay -40 -> 252, step: 8
3081 01:01:00.284226 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3082 01:01:00.284409 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3083 01:01:00.284592 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3084 01:01:00.284774 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3085 01:01:00.284968 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3086 01:01:00.285156 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3087 01:01:00.285344 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3088 01:01:00.285540 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3089 01:01:00.285725 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3090 01:01:00.285908 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3091 01:01:00.286113 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3092 01:01:00.286329 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3093 01:01:00.286516 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3094 01:01:00.286697 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3095 01:01:00.286880 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3096 01:01:00.287061 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3097 01:01:00.287244 ==
3098 01:01:00.287427 Dram Type= 6, Freq= 0, CH_1, rank 0
3099 01:01:00.287609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3100 01:01:00.287791 ==
3101 01:01:00.287972 DQS Delay:
3102 01:01:00.288228 DQS0 = 0, DQS1 = 0
3103 01:01:00.288478 DQM Delay:
3104 01:01:00.288685 DQM0 = 116, DQM1 = 107
3105 01:01:00.288830 DQ Delay:
3106 01:01:00.288968 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3107 01:01:00.289107 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3108 01:01:00.289244 DQ8 =87, DQ9 =95, DQ10 =107, DQ11 =99
3109 01:01:00.289381 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3110 01:01:00.289519
3111 01:01:00.289654
3112 01:01:00.289789 ==
3113 01:01:00.289925 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 01:01:00.290062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3115 01:01:00.290200 ==
3116 01:01:00.290353
3117 01:01:00.290511
3118 01:01:00.290652 TX Vref Scan disable
3119 01:01:00.290789 == TX Byte 0 ==
3120 01:01:00.290939 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3121 01:01:00.291084 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3122 01:01:00.291222 == TX Byte 1 ==
3123 01:01:00.291370 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3124 01:01:00.291512 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3125 01:01:00.291650 ==
3126 01:01:00.291788 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 01:01:00.291925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3128 01:01:00.292063 ==
3129 01:01:00.292199 TX Vref=22, minBit 8, minWin=25, winSum=419
3130 01:01:00.292603 TX Vref=24, minBit 0, minWin=26, winSum=422
3131 01:01:00.292880 TX Vref=26, minBit 1, minWin=26, winSum=427
3132 01:01:00.293173 TX Vref=28, minBit 0, minWin=26, winSum=430
3133 01:01:00.293444 TX Vref=30, minBit 10, minWin=26, winSum=431
3134 01:01:00.293679 TX Vref=32, minBit 8, minWin=26, winSum=430
3135 01:01:00.293865 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 30
3136 01:01:00.294038
3137 01:01:00.294221 Final TX Range 1 Vref 30
3138 01:01:00.294355
3139 01:01:00.294466 ==
3140 01:01:00.294579 Dram Type= 6, Freq= 0, CH_1, rank 0
3141 01:01:00.294705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3142 01:01:00.294820 ==
3143 01:01:00.294932
3144 01:01:00.295040
3145 01:01:00.295150 TX Vref Scan disable
3146 01:01:00.295260 == TX Byte 0 ==
3147 01:01:00.295372 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3148 01:01:00.295483 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3149 01:01:00.295593 == TX Byte 1 ==
3150 01:01:00.295708 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3151 01:01:00.295824 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3152 01:01:00.295937
3153 01:01:00.296053 [DATLAT]
3154 01:01:00.296170 Freq=1200, CH1 RK0
3155 01:01:00.296281
3156 01:01:00.296392 DATLAT Default: 0xd
3157 01:01:00.296503 0, 0xFFFF, sum = 0
3158 01:01:00.296616 1, 0xFFFF, sum = 0
3159 01:01:00.296730 2, 0xFFFF, sum = 0
3160 01:01:00.296842 3, 0xFFFF, sum = 0
3161 01:01:00.296953 4, 0xFFFF, sum = 0
3162 01:01:00.297064 5, 0xFFFF, sum = 0
3163 01:01:00.297175 6, 0xFFFF, sum = 0
3164 01:01:00.297287 7, 0xFFFF, sum = 0
3165 01:01:00.297398 8, 0xFFFF, sum = 0
3166 01:01:00.297509 9, 0xFFFF, sum = 0
3167 01:01:00.297621 10, 0xFFFF, sum = 0
3168 01:01:00.297734 11, 0x0, sum = 1
3169 01:01:00.297846 12, 0x0, sum = 2
3170 01:01:00.297971 13, 0x0, sum = 3
3171 01:01:00.298085 14, 0x0, sum = 4
3172 01:01:00.298196 best_step = 12
3173 01:01:00.298328
3174 01:01:00.298443 ==
3175 01:01:00.298535 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 01:01:00.298628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3177 01:01:00.298721 ==
3178 01:01:00.298812 RX Vref Scan: 1
3179 01:01:00.298902
3180 01:01:00.298993 Set Vref Range= 32 -> 127
3181 01:01:00.299084
3182 01:01:00.299175 RX Vref 32 -> 127, step: 1
3183 01:01:00.299265
3184 01:01:00.299355 RX Delay -29 -> 252, step: 4
3185 01:01:00.299445
3186 01:01:00.299536 Set Vref, RX VrefLevel [Byte0]: 32
3187 01:01:00.299630 [Byte1]: 32
3188 01:01:00.299723
3189 01:01:00.299815 Set Vref, RX VrefLevel [Byte0]: 33
3190 01:01:00.299906 [Byte1]: 33
3191 01:01:00.299997
3192 01:01:00.300088 Set Vref, RX VrefLevel [Byte0]: 34
3193 01:01:00.300179 [Byte1]: 34
3194 01:01:00.300269
3195 01:01:00.300360 Set Vref, RX VrefLevel [Byte0]: 35
3196 01:01:00.300452 [Byte1]: 35
3197 01:01:00.300544
3198 01:01:00.300635 Set Vref, RX VrefLevel [Byte0]: 36
3199 01:01:00.300726 [Byte1]: 36
3200 01:01:00.300817
3201 01:01:00.300915 Set Vref, RX VrefLevel [Byte0]: 37
3202 01:01:00.301010 [Byte1]: 37
3203 01:01:00.301102
3204 01:01:00.301200 Set Vref, RX VrefLevel [Byte0]: 38
3205 01:01:00.301296 [Byte1]: 38
3206 01:01:00.301389
3207 01:01:00.301486 Set Vref, RX VrefLevel [Byte0]: 39
3208 01:01:00.301581 [Byte1]: 39
3209 01:01:00.301673
3210 01:01:00.301764 Set Vref, RX VrefLevel [Byte0]: 40
3211 01:01:00.301857 [Byte1]: 40
3212 01:01:00.301949
3213 01:01:00.302039 Set Vref, RX VrefLevel [Byte0]: 41
3214 01:01:00.302130 [Byte1]: 41
3215 01:01:00.302234
3216 01:01:00.302330 Set Vref, RX VrefLevel [Byte0]: 42
3217 01:01:00.302424 [Byte1]: 42
3218 01:01:00.302516
3219 01:01:00.302607 Set Vref, RX VrefLevel [Byte0]: 43
3220 01:01:00.302697 [Byte1]: 43
3221 01:01:00.302788
3222 01:01:00.302879 Set Vref, RX VrefLevel [Byte0]: 44
3223 01:01:00.302970 [Byte1]: 44
3224 01:01:00.303061
3225 01:01:00.303153 Set Vref, RX VrefLevel [Byte0]: 45
3226 01:01:00.303245 [Byte1]: 45
3227 01:01:00.303344
3228 01:01:00.303422 Set Vref, RX VrefLevel [Byte0]: 46
3229 01:01:00.303502 [Byte1]: 46
3230 01:01:00.303581
3231 01:01:00.303661 Set Vref, RX VrefLevel [Byte0]: 47
3232 01:01:00.303740 [Byte1]: 47
3233 01:01:00.303818
3234 01:01:00.303895 Set Vref, RX VrefLevel [Byte0]: 48
3235 01:01:00.303974 [Byte1]: 48
3236 01:01:00.304053
3237 01:01:00.304131 Set Vref, RX VrefLevel [Byte0]: 49
3238 01:01:00.304211 [Byte1]: 49
3239 01:01:00.304290
3240 01:01:00.304367 Set Vref, RX VrefLevel [Byte0]: 50
3241 01:01:00.304446 [Byte1]: 50
3242 01:01:00.304523
3243 01:01:00.304611 Set Vref, RX VrefLevel [Byte0]: 51
3244 01:01:00.304691 [Byte1]: 51
3245 01:01:00.304770
3246 01:01:00.304849 Set Vref, RX VrefLevel [Byte0]: 52
3247 01:01:00.304928 [Byte1]: 52
3248 01:01:00.305007
3249 01:01:00.305086 Set Vref, RX VrefLevel [Byte0]: 53
3250 01:01:00.305165 [Byte1]: 53
3251 01:01:00.305244
3252 01:01:00.305321 Set Vref, RX VrefLevel [Byte0]: 54
3253 01:01:00.305399 [Byte1]: 54
3254 01:01:00.305477
3255 01:01:00.305555 Set Vref, RX VrefLevel [Byte0]: 55
3256 01:01:00.305648 [Byte1]: 55
3257 01:01:00.305739
3258 01:01:00.305818 Set Vref, RX VrefLevel [Byte0]: 56
3259 01:01:00.305897 [Byte1]: 56
3260 01:01:00.305976
3261 01:01:00.306054 Set Vref, RX VrefLevel [Byte0]: 57
3262 01:01:00.306138 [Byte1]: 57
3263 01:01:00.306246
3264 01:01:00.306330 Set Vref, RX VrefLevel [Byte0]: 58
3265 01:01:00.306426 [Byte1]: 58
3266 01:01:00.306507
3267 01:01:00.306585 Set Vref, RX VrefLevel [Byte0]: 59
3268 01:01:00.306665 [Byte1]: 59
3269 01:01:00.306743
3270 01:01:00.306823 Set Vref, RX VrefLevel [Byte0]: 60
3271 01:01:00.306902 [Byte1]: 60
3272 01:01:00.306981
3273 01:01:00.307059 Set Vref, RX VrefLevel [Byte0]: 61
3274 01:01:00.307138 [Byte1]: 61
3275 01:01:00.307217
3276 01:01:00.307295 Set Vref, RX VrefLevel [Byte0]: 62
3277 01:01:00.307374 [Byte1]: 62
3278 01:01:00.307453
3279 01:01:00.307532 Set Vref, RX VrefLevel [Byte0]: 63
3280 01:01:00.307613 [Byte1]: 63
3281 01:01:00.307691
3282 01:01:00.307769 Set Vref, RX VrefLevel [Byte0]: 64
3283 01:01:00.307852 [Byte1]: 64
3284 01:01:00.307934
3285 01:01:00.308014 Set Vref, RX VrefLevel [Byte0]: 65
3286 01:01:00.308094 [Byte1]: 65
3287 01:01:00.308172
3288 01:01:00.308250 Final RX Vref Byte 0 = 51 to rank0
3289 01:01:00.308340 Final RX Vref Byte 1 = 50 to rank0
3290 01:01:00.308411 Final RX Vref Byte 0 = 51 to rank1
3291 01:01:00.308479 Final RX Vref Byte 1 = 50 to rank1==
3292 01:01:00.308549 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 01:01:00.308619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3294 01:01:00.308689 ==
3295 01:01:00.308758 DQS Delay:
3296 01:01:00.308826 DQS0 = 0, DQS1 = 0
3297 01:01:00.309102 DQM Delay:
3298 01:01:00.309221 DQM0 = 115, DQM1 = 105
3299 01:01:00.309358 DQ Delay:
3300 01:01:00.309489 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3301 01:01:00.309600 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3302 01:01:00.309709 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3303 01:01:00.309818 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =116
3304 01:01:00.309925
3305 01:01:00.310033
3306 01:01:00.310143 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3307 01:01:00.310264 CH1 RK0: MR19=404, MR18=1B1B
3308 01:01:00.310376 CH1_RK0: MR19=0x404, MR18=0x1B1B, DQSOSC=399, MR23=63, INC=41, DEC=27
3309 01:01:00.310483
3310 01:01:00.310592 ----->DramcWriteLeveling(PI) begin...
3311 01:01:00.310701 ==
3312 01:01:00.310810 Dram Type= 6, Freq= 0, CH_1, rank 1
3313 01:01:00.310919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3314 01:01:00.311027 ==
3315 01:01:00.311136 Write leveling (Byte 0): 21 => 21
3316 01:01:00.311244 Write leveling (Byte 1): 21 => 21
3317 01:01:00.311355 DramcWriteLeveling(PI) end<-----
3318 01:01:00.311455
3319 01:01:00.311533 ==
3320 01:01:00.311602 Dram Type= 6, Freq= 0, CH_1, rank 1
3321 01:01:00.311673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3322 01:01:00.311751 ==
3323 01:01:00.311820 [Gating] SW mode calibration
3324 01:01:00.311888 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3325 01:01:00.311959 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3326 01:01:00.312029 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3327 01:01:00.312099 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3328 01:01:00.312168 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3329 01:01:00.312237 0 11 12 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
3330 01:01:00.312305 0 11 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
3331 01:01:00.312374 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3332 01:01:00.312443 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3333 01:01:00.312512 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3334 01:01:00.312580 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3335 01:01:00.312650 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3336 01:01:00.312719 0 12 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3337 01:01:00.312787 0 12 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (1 1)
3338 01:01:00.312855 0 12 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3339 01:01:00.312924 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3340 01:01:00.312993 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3341 01:01:00.313062 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3342 01:01:00.313130 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3343 01:01:00.313199 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3344 01:01:00.313268 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3345 01:01:00.313347 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3346 01:01:00.313408 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3347 01:01:00.313469 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3348 01:01:00.313530 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 01:01:00.313591 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 01:01:00.313652 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 01:01:00.313714 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 01:01:00.313776 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 01:01:00.313836 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 01:01:00.313898 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 01:01:00.313960 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 01:01:00.314023 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 01:01:00.314085 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 01:01:00.314146 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 01:01:00.314207 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 01:01:00.314283 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 01:01:00.314345 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3362 01:01:00.314406 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3363 01:01:00.314466 Total UI for P1: 0, mck2ui 16
3364 01:01:00.314528 best dqsien dly found for B0: ( 0, 15, 12)
3365 01:01:00.314589 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3366 01:01:00.314648 Total UI for P1: 0, mck2ui 16
3367 01:01:00.314708 best dqsien dly found for B1: ( 0, 15, 16)
3368 01:01:00.314769 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3369 01:01:00.314836 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3370 01:01:00.314901
3371 01:01:00.314963 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3372 01:01:00.315024 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3373 01:01:00.315084 [Gating] SW calibration Done
3374 01:01:00.315144 ==
3375 01:01:00.315204 Dram Type= 6, Freq= 0, CH_1, rank 1
3376 01:01:00.315264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3377 01:01:00.315325 ==
3378 01:01:00.315386 RX Vref Scan: 0
3379 01:01:00.315445
3380 01:01:00.315506 RX Vref 0 -> 0, step: 1
3381 01:01:00.315566
3382 01:01:00.315626 RX Delay -40 -> 252, step: 8
3383 01:01:00.315686 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3384 01:01:00.315747 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3385 01:01:00.315808 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3386 01:01:00.315868 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3387 01:01:00.315929 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3388 01:01:00.315989 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3389 01:01:00.316051 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3390 01:01:00.316111 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3391 01:01:00.316172 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3392 01:01:00.316233 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3393 01:01:00.316294 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3394 01:01:00.316354 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3395 01:01:00.316414 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3396 01:01:00.316474 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3397 01:01:00.316536 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3398 01:01:00.316799 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3399 01:01:00.316875 ==
3400 01:01:00.316945 Dram Type= 6, Freq= 0, CH_1, rank 1
3401 01:01:00.317009 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3402 01:01:00.317071 ==
3403 01:01:00.317132 DQS Delay:
3404 01:01:00.317194 DQS0 = 0, DQS1 = 0
3405 01:01:00.317255 DQM Delay:
3406 01:01:00.317316 DQM0 = 115, DQM1 = 105
3407 01:01:00.317377 DQ Delay:
3408 01:01:00.317438 DQ0 =115, DQ1 =111, DQ2 =107, DQ3 =115
3409 01:01:00.317499 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3410 01:01:00.317560 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3411 01:01:00.317621 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3412 01:01:00.317681
3413 01:01:00.317741
3414 01:01:00.317801 ==
3415 01:01:00.317863 Dram Type= 6, Freq= 0, CH_1, rank 1
3416 01:01:00.317928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3417 01:01:00.317992 ==
3418 01:01:00.318059
3419 01:01:00.318153
3420 01:01:00.318249 TX Vref Scan disable
3421 01:01:00.318325 == TX Byte 0 ==
3422 01:01:00.318381 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3423 01:01:00.318437 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3424 01:01:00.318492 == TX Byte 1 ==
3425 01:01:00.318547 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3426 01:01:00.318601 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3427 01:01:00.318656 ==
3428 01:01:00.318711 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 01:01:00.318765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3430 01:01:00.318821 ==
3431 01:01:00.318875 TX Vref=22, minBit 8, minWin=25, winSum=421
3432 01:01:00.318931 TX Vref=24, minBit 8, minWin=25, winSum=423
3433 01:01:00.318986 TX Vref=26, minBit 9, minWin=25, winSum=431
3434 01:01:00.319041 TX Vref=28, minBit 9, minWin=26, winSum=431
3435 01:01:00.319096 TX Vref=30, minBit 9, minWin=25, winSum=431
3436 01:01:00.319150 TX Vref=32, minBit 3, minWin=26, winSum=430
3437 01:01:00.319205 [TxChooseVref] Worse bit 9, Min win 26, Win sum 431, Final Vref 28
3438 01:01:00.319260
3439 01:01:00.319314 Final TX Range 1 Vref 28
3440 01:01:00.319370
3441 01:01:00.319425 ==
3442 01:01:00.319480 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 01:01:00.319534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3444 01:01:00.319589 ==
3445 01:01:00.319644
3446 01:01:00.319697
3447 01:01:00.319752 TX Vref Scan disable
3448 01:01:00.319807 == TX Byte 0 ==
3449 01:01:00.319870 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3450 01:01:00.319933 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3451 01:01:00.319994 == TX Byte 1 ==
3452 01:01:00.320053 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3453 01:01:00.320110 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3454 01:01:00.320164
3455 01:01:00.320224 [DATLAT]
3456 01:01:00.320281 Freq=1200, CH1 RK1
3457 01:01:00.320336
3458 01:01:00.320391 DATLAT Default: 0xc
3459 01:01:00.320446 0, 0xFFFF, sum = 0
3460 01:01:00.320502 1, 0xFFFF, sum = 0
3461 01:01:00.320558 2, 0xFFFF, sum = 0
3462 01:01:00.320625 3, 0xFFFF, sum = 0
3463 01:01:00.320681 4, 0xFFFF, sum = 0
3464 01:01:00.320737 5, 0xFFFF, sum = 0
3465 01:01:00.320795 6, 0xFFFF, sum = 0
3466 01:01:00.320851 7, 0xFFFF, sum = 0
3467 01:01:00.320906 8, 0xFFFF, sum = 0
3468 01:01:00.320968 9, 0xFFFF, sum = 0
3469 01:01:00.321023 10, 0xFFFF, sum = 0
3470 01:01:00.321080 11, 0x0, sum = 1
3471 01:01:00.321139 12, 0x0, sum = 2
3472 01:01:00.321196 13, 0x0, sum = 3
3473 01:01:00.321251 14, 0x0, sum = 4
3474 01:01:00.321310 best_step = 12
3475 01:01:00.321369
3476 01:01:00.321429 ==
3477 01:01:00.321484 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 01:01:00.321539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3479 01:01:00.321594 ==
3480 01:01:00.321649 RX Vref Scan: 0
3481 01:01:00.321704
3482 01:01:00.321758 RX Vref 0 -> 0, step: 1
3483 01:01:00.321812
3484 01:01:00.321867 RX Delay -29 -> 252, step: 4
3485 01:01:00.321923 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3486 01:01:00.321979 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3487 01:01:00.322033 iDelay=199, Bit 2, Center 106 (35 ~ 178) 144
3488 01:01:00.322088 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3489 01:01:00.322143 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3490 01:01:00.322198 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3491 01:01:00.322264 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3492 01:01:00.322319 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3493 01:01:00.322373 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3494 01:01:00.322428 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3495 01:01:00.322483 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3496 01:01:00.322538 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3497 01:01:00.322592 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3498 01:01:00.322647 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3499 01:01:00.322701 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3500 01:01:00.322756 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3501 01:01:00.322810 ==
3502 01:01:00.322865 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 01:01:00.322919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3504 01:01:00.322974 ==
3505 01:01:00.323029 DQS Delay:
3506 01:01:00.323083 DQS0 = 0, DQS1 = 0
3507 01:01:00.323136 DQM Delay:
3508 01:01:00.323191 DQM0 = 114, DQM1 = 104
3509 01:01:00.323246 DQ Delay:
3510 01:01:00.323300 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =112
3511 01:01:00.323363 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3512 01:01:00.323413 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3513 01:01:00.323462 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =110
3514 01:01:00.323512
3515 01:01:00.323560
3516 01:01:00.323610 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3517 01:01:00.323661 CH1 RK1: MR19=404, MR18=B0B
3518 01:01:00.323711 CH1_RK1: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3519 01:01:00.323761 [RxdqsGatingPostProcess] freq 1200
3520 01:01:00.323810 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3521 01:01:00.323860 Pre-setting of DQS Precalculation
3522 01:01:00.323910 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3523 01:01:00.323963 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3524 01:01:00.324015 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3525 01:01:00.324065
3526 01:01:00.324115
3527 01:01:00.324164 [Calibration Summary] 2400 Mbps
3528 01:01:00.324213 CH 0, Rank 0
3529 01:01:00.324262 SW Impedance : PASS
3530 01:01:00.324312 DUTY Scan : NO K
3531 01:01:00.324362 ZQ Calibration : PASS
3532 01:01:00.324411 Jitter Meter : NO K
3533 01:01:00.324460 CBT Training : PASS
3534 01:01:00.324514 Write leveling : PASS
3535 01:01:00.324565 RX DQS gating : PASS
3536 01:01:00.324618 RX DQ/DQS(RDDQC) : PASS
3537 01:01:00.324670 TX DQ/DQS : PASS
3538 01:01:00.324720 RX DATLAT : PASS
3539 01:01:00.324769 RX DQ/DQS(Engine): PASS
3540 01:01:00.324819 TX OE : NO K
3541 01:01:00.324869 All Pass.
3542 01:01:00.324918
3543 01:01:00.324967 CH 0, Rank 1
3544 01:01:00.325212 SW Impedance : PASS
3545 01:01:00.325269 DUTY Scan : NO K
3546 01:01:00.325319 ZQ Calibration : PASS
3547 01:01:00.325369 Jitter Meter : NO K
3548 01:01:00.325419 CBT Training : PASS
3549 01:01:00.325471 Write leveling : PASS
3550 01:01:00.325521 RX DQS gating : PASS
3551 01:01:00.325571 RX DQ/DQS(RDDQC) : PASS
3552 01:01:00.325622 TX DQ/DQS : PASS
3553 01:01:00.325672 RX DATLAT : PASS
3554 01:01:00.325722 RX DQ/DQS(Engine): PASS
3555 01:01:00.325772 TX OE : NO K
3556 01:01:00.325822 All Pass.
3557 01:01:00.325872
3558 01:01:00.325921 CH 1, Rank 0
3559 01:01:00.325971 SW Impedance : PASS
3560 01:01:00.326021 DUTY Scan : NO K
3561 01:01:00.326070 ZQ Calibration : PASS
3562 01:01:00.326120 Jitter Meter : NO K
3563 01:01:00.326169 CBT Training : PASS
3564 01:01:00.326227 Write leveling : PASS
3565 01:01:00.326279 RX DQS gating : PASS
3566 01:01:00.326329 RX DQ/DQS(RDDQC) : PASS
3567 01:01:00.326379 TX DQ/DQS : PASS
3568 01:01:00.326430 RX DATLAT : PASS
3569 01:01:00.326480 RX DQ/DQS(Engine): PASS
3570 01:01:00.326530 TX OE : NO K
3571 01:01:00.326580 All Pass.
3572 01:01:00.326629
3573 01:01:00.326679 CH 1, Rank 1
3574 01:01:00.326728 SW Impedance : PASS
3575 01:01:00.326778 DUTY Scan : NO K
3576 01:01:00.326827 ZQ Calibration : PASS
3577 01:01:00.326875 Jitter Meter : NO K
3578 01:01:00.326924 CBT Training : PASS
3579 01:01:00.326975 Write leveling : PASS
3580 01:01:00.327024 RX DQS gating : PASS
3581 01:01:00.327074 RX DQ/DQS(RDDQC) : PASS
3582 01:01:00.327123 TX DQ/DQS : PASS
3583 01:01:00.327173 RX DATLAT : PASS
3584 01:01:00.327222 RX DQ/DQS(Engine): PASS
3585 01:01:00.327271 TX OE : NO K
3586 01:01:00.327320 All Pass.
3587 01:01:00.327369
3588 01:01:00.327417 DramC Write-DBI off
3589 01:01:00.327467 PER_BANK_REFRESH: Hybrid Mode
3590 01:01:00.327517 TX_TRACKING: ON
3591 01:01:00.327567 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3592 01:01:00.327618 [FAST_K] Save calibration result to emmc
3593 01:01:00.327668 dramc_set_vcore_voltage set vcore to 650000
3594 01:01:00.327718 Read voltage for 600, 5
3595 01:01:00.327774 Vio18 = 0
3596 01:01:00.327827 Vcore = 650000
3597 01:01:00.327876 Vdram = 0
3598 01:01:00.327932 Vddq = 0
3599 01:01:00.327982 Vmddr = 0
3600 01:01:00.328036 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3601 01:01:00.328088 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3602 01:01:00.328138 MEM_TYPE=3, freq_sel=19
3603 01:01:00.328188 sv_algorithm_assistance_LP4_1600
3604 01:01:00.328237 ============ PULL DRAM RESETB DOWN ============
3605 01:01:00.328287 ========== PULL DRAM RESETB DOWN end =========
3606 01:01:00.328349 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3607 01:01:00.328401 ===================================
3608 01:01:00.328451 LPDDR4 DRAM CONFIGURATION
3609 01:01:00.328499 ===================================
3610 01:01:00.328548 EX_ROW_EN[0] = 0x0
3611 01:01:00.328596 EX_ROW_EN[1] = 0x0
3612 01:01:00.328644 LP4Y_EN = 0x0
3613 01:01:00.328692 WORK_FSP = 0x0
3614 01:01:00.328740 WL = 0x2
3615 01:01:00.328788 RL = 0x2
3616 01:01:00.328836 BL = 0x2
3617 01:01:00.328885 RPST = 0x0
3618 01:01:00.328933 RD_PRE = 0x0
3619 01:01:00.328981 WR_PRE = 0x1
3620 01:01:00.329029 WR_PST = 0x0
3621 01:01:00.329078 DBI_WR = 0x0
3622 01:01:00.329126 DBI_RD = 0x0
3623 01:01:00.329175 OTF = 0x1
3624 01:01:00.329222 ===================================
3625 01:01:00.329271 ===================================
3626 01:01:00.329319 ANA top config
3627 01:01:00.329367 ===================================
3628 01:01:00.329416 DLL_ASYNC_EN = 0
3629 01:01:00.329465 ALL_SLAVE_EN = 1
3630 01:01:00.329513 NEW_RANK_MODE = 1
3631 01:01:00.329562 DLL_IDLE_MODE = 1
3632 01:01:00.329610 LP45_APHY_COMB_EN = 1
3633 01:01:00.329658 TX_ODT_DIS = 1
3634 01:01:00.329706 NEW_8X_MODE = 1
3635 01:01:00.329755 ===================================
3636 01:01:00.329835 ===================================
3637 01:01:00.329912 data_rate = 1200
3638 01:01:00.329996 CKR = 1
3639 01:01:00.330049 DQ_P2S_RATIO = 8
3640 01:01:00.330098 ===================================
3641 01:01:00.330147 CA_P2S_RATIO = 8
3642 01:01:00.330196 DQ_CA_OPEN = 0
3643 01:01:00.330283 DQ_SEMI_OPEN = 0
3644 01:01:00.330333 CA_SEMI_OPEN = 0
3645 01:01:00.330381 CA_FULL_RATE = 0
3646 01:01:00.330430 DQ_CKDIV4_EN = 1
3647 01:01:00.330479 CA_CKDIV4_EN = 1
3648 01:01:00.330528 CA_PREDIV_EN = 0
3649 01:01:00.330578 PH8_DLY = 0
3650 01:01:00.330627 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3651 01:01:00.330675 DQ_AAMCK_DIV = 4
3652 01:01:00.330723 CA_AAMCK_DIV = 4
3653 01:01:00.330772 CA_ADMCK_DIV = 4
3654 01:01:00.330821 DQ_TRACK_CA_EN = 0
3655 01:01:00.330875 CA_PICK = 600
3656 01:01:00.330956 CA_MCKIO = 600
3657 01:01:00.331033 MCKIO_SEMI = 0
3658 01:01:00.331113 PLL_FREQ = 2288
3659 01:01:00.331190 DQ_UI_PI_RATIO = 32
3660 01:01:00.331268 CA_UI_PI_RATIO = 0
3661 01:01:00.331345 ===================================
3662 01:01:00.331411 ===================================
3663 01:01:00.331462 memory_type:LPDDR4
3664 01:01:00.331512 GP_NUM : 10
3665 01:01:00.331560 SRAM_EN : 1
3666 01:01:00.331625 MD32_EN : 0
3667 01:01:00.331701 ===================================
3668 01:01:00.331764 [ANA_INIT] >>>>>>>>>>>>>>
3669 01:01:00.331825 <<<<<< [CONFIGURE PHASE]: ANA_TX
3670 01:01:00.331887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3671 01:01:00.331942 ===================================
3672 01:01:00.331993 data_rate = 1200,PCW = 0X5800
3673 01:01:00.332054 ===================================
3674 01:01:00.332107 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3675 01:01:00.332167 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3676 01:01:00.332250 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3677 01:01:00.332333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3678 01:01:00.332415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3679 01:01:00.332497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3680 01:01:00.332575 [ANA_INIT] flow start
3681 01:01:00.332651 [ANA_INIT] PLL >>>>>>>>
3682 01:01:00.332728 [ANA_INIT] PLL <<<<<<<<
3683 01:01:00.332804 [ANA_INIT] MIDPI >>>>>>>>
3684 01:01:00.332880 [ANA_INIT] MIDPI <<<<<<<<
3685 01:01:00.332956 [ANA_INIT] DLL >>>>>>>>
3686 01:01:00.333229 [ANA_INIT] flow end
3687 01:01:00.333315 ============ LP4 DIFF to SE enter ============
3688 01:01:00.333395 ============ LP4 DIFF to SE exit ============
3689 01:01:00.333472 [ANA_INIT] <<<<<<<<<<<<<
3690 01:01:00.333549 [Flow] Enable top DCM control >>>>>
3691 01:01:00.333628 [Flow] Enable top DCM control <<<<<
3692 01:01:00.333712 Enable DLL master slave shuffle
3693 01:01:00.333790 ==============================================================
3694 01:01:00.333868 Gating Mode config
3695 01:01:00.333946 ==============================================================
3696 01:01:00.334023 Config description:
3697 01:01:00.334101 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3698 01:01:00.334180 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3699 01:01:00.334288 SELPH_MODE 0: By rank 1: By Phase
3700 01:01:00.334340 ==============================================================
3701 01:01:00.334390 GAT_TRACK_EN = 1
3702 01:01:00.334439 RX_GATING_MODE = 2
3703 01:01:00.334488 RX_GATING_TRACK_MODE = 2
3704 01:01:00.334536 SELPH_MODE = 1
3705 01:01:00.334585 PICG_EARLY_EN = 1
3706 01:01:00.334634 VALID_LAT_VALUE = 1
3707 01:01:00.334683 ==============================================================
3708 01:01:00.334732 Enter into Gating configuration >>>>
3709 01:01:00.334781 Exit from Gating configuration <<<<
3710 01:01:00.334829 Enter into DVFS_PRE_config >>>>>
3711 01:01:00.334879 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3712 01:01:00.334929 Exit from DVFS_PRE_config <<<<<
3713 01:01:00.334978 Enter into PICG configuration >>>>
3714 01:01:00.335026 Exit from PICG configuration <<<<
3715 01:01:00.335075 [RX_INPUT] configuration >>>>>
3716 01:01:00.335123 [RX_INPUT] configuration <<<<<
3717 01:01:00.335171 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3718 01:01:00.335226 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3719 01:01:00.335288 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3720 01:01:00.335351 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3721 01:01:00.335408 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3722 01:01:00.335465 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3723 01:01:00.335519 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3724 01:01:00.335580 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3725 01:01:00.335665 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3726 01:01:00.335748 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3727 01:01:00.335830 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3728 01:01:00.335925 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3729 01:01:00.336007 ===================================
3730 01:01:00.336091 LPDDR4 DRAM CONFIGURATION
3731 01:01:00.336173 ===================================
3732 01:01:00.336254 EX_ROW_EN[0] = 0x0
3733 01:01:00.336335 EX_ROW_EN[1] = 0x0
3734 01:01:00.336413 LP4Y_EN = 0x0
3735 01:01:00.336490 WORK_FSP = 0x0
3736 01:01:00.336566 WL = 0x2
3737 01:01:00.336642 RL = 0x2
3738 01:01:00.336718 BL = 0x2
3739 01:01:00.336794 RPST = 0x0
3740 01:01:00.336870 RD_PRE = 0x0
3741 01:01:00.336947 WR_PRE = 0x1
3742 01:01:00.337023 WR_PST = 0x0
3743 01:01:00.337099 DBI_WR = 0x0
3744 01:01:00.337174 DBI_RD = 0x0
3745 01:01:00.337250 OTF = 0x1
3746 01:01:00.337326 ===================================
3747 01:01:00.337404 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3748 01:01:00.337481 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3749 01:01:00.337558 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3750 01:01:00.337635 ===================================
3751 01:01:00.337711 LPDDR4 DRAM CONFIGURATION
3752 01:01:00.337788 ===================================
3753 01:01:00.337865 EX_ROW_EN[0] = 0x10
3754 01:01:00.337941 EX_ROW_EN[1] = 0x0
3755 01:01:00.338017 LP4Y_EN = 0x0
3756 01:01:00.338092 WORK_FSP = 0x0
3757 01:01:00.338168 WL = 0x2
3758 01:01:00.338277 RL = 0x2
3759 01:01:00.338367 BL = 0x2
3760 01:01:00.338443 RPST = 0x0
3761 01:01:00.338520 RD_PRE = 0x0
3762 01:01:00.338596 WR_PRE = 0x1
3763 01:01:00.338671 WR_PST = 0x0
3764 01:01:00.338747 DBI_WR = 0x0
3765 01:01:00.338823 DBI_RD = 0x0
3766 01:01:00.338899 OTF = 0x1
3767 01:01:00.338976 ===================================
3768 01:01:00.339054 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3769 01:01:00.339130 nWR fixed to 30
3770 01:01:00.339208 [ModeRegInit_LP4] CH0 RK0
3771 01:01:00.339284 [ModeRegInit_LP4] CH0 RK1
3772 01:01:00.339360 [ModeRegInit_LP4] CH1 RK0
3773 01:01:00.339436 [ModeRegInit_LP4] CH1 RK1
3774 01:01:00.339512 match AC timing 16
3775 01:01:00.339590 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3776 01:01:00.339667 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3777 01:01:00.339745 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3778 01:01:00.339823 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3779 01:01:00.339900 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3780 01:01:00.339976 ==
3781 01:01:00.340054 Dram Type= 6, Freq= 0, CH_0, rank 0
3782 01:01:00.340132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3783 01:01:00.340208 ==
3784 01:01:00.340286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3785 01:01:00.340364 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3786 01:01:00.340441 [CA 0] Center 36 (6~66) winsize 61
3787 01:01:00.340518 [CA 1] Center 36 (6~66) winsize 61
3788 01:01:00.340595 [CA 2] Center 34 (4~65) winsize 62
3789 01:01:00.340672 [CA 3] Center 34 (3~65) winsize 63
3790 01:01:00.340749 [CA 4] Center 33 (3~64) winsize 62
3791 01:01:00.340826 [CA 5] Center 33 (3~64) winsize 62
3792 01:01:00.340902
3793 01:01:00.340978 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3794 01:01:00.341054
3795 01:01:00.341321 [CATrainingPosCal] consider 1 rank data
3796 01:01:00.341403 u2DelayCellTimex100 = 270/100 ps
3797 01:01:00.341481 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3798 01:01:00.341558 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3799 01:01:00.341636 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3800 01:01:00.341713 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3801 01:01:00.341790 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3802 01:01:00.341870 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3803 01:01:00.341986
3804 01:01:00.342078 CA PerBit enable=1, Macro0, CA PI delay=33
3805 01:01:00.342156
3806 01:01:00.342269 [CBTSetCACLKResult] CA Dly = 33
3807 01:01:00.342323 CS Dly: 4 (0~35)
3808 01:01:00.342372 ==
3809 01:01:00.342420 Dram Type= 6, Freq= 0, CH_0, rank 1
3810 01:01:00.342470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3811 01:01:00.342520 ==
3812 01:01:00.342569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3813 01:01:00.342618 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3814 01:01:00.342667 [CA 0] Center 35 (5~66) winsize 62
3815 01:01:00.342716 [CA 1] Center 35 (5~66) winsize 62
3816 01:01:00.342764 [CA 2] Center 34 (4~65) winsize 62
3817 01:01:00.342812 [CA 3] Center 34 (3~65) winsize 63
3818 01:01:00.342860 [CA 4] Center 33 (3~64) winsize 62
3819 01:01:00.342909 [CA 5] Center 33 (3~64) winsize 62
3820 01:01:00.342958
3821 01:01:00.343006 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3822 01:01:00.343055
3823 01:01:00.343104 [CATrainingPosCal] consider 2 rank data
3824 01:01:00.343153 u2DelayCellTimex100 = 270/100 ps
3825 01:01:00.343202 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3826 01:01:00.343251 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3827 01:01:00.343300 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3828 01:01:00.343348 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3829 01:01:00.343397 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3830 01:01:00.343445 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3831 01:01:00.343494
3832 01:01:00.343542 CA PerBit enable=1, Macro0, CA PI delay=33
3833 01:01:00.343591
3834 01:01:00.343639 [CBTSetCACLKResult] CA Dly = 33
3835 01:01:00.343687 CS Dly: 4 (0~36)
3836 01:01:00.343735
3837 01:01:00.343783 ----->DramcWriteLeveling(PI) begin...
3838 01:01:00.343832 ==
3839 01:01:00.343887 Dram Type= 6, Freq= 0, CH_0, rank 0
3840 01:01:00.343937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3841 01:01:00.343985 ==
3842 01:01:00.344034 Write leveling (Byte 0): 32 => 32
3843 01:01:00.344083 Write leveling (Byte 1): 30 => 30
3844 01:01:00.344132 DramcWriteLeveling(PI) end<-----
3845 01:01:00.344181
3846 01:01:00.344228 ==
3847 01:01:00.344276 Dram Type= 6, Freq= 0, CH_0, rank 0
3848 01:01:00.344324 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3849 01:01:00.344373 ==
3850 01:01:00.344422 [Gating] SW mode calibration
3851 01:01:00.344471 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3852 01:01:00.344521 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3853 01:01:00.344570 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3854 01:01:00.344619 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3855 01:01:00.344667 0 5 8 | B1->B0 | 3232 3030 | 1 1 | (1 0) (1 0)
3856 01:01:00.344715 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3857 01:01:00.344764 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3858 01:01:00.344813 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3859 01:01:00.344862 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3860 01:01:00.344911 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3861 01:01:00.344960 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3862 01:01:00.345009 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3863 01:01:00.345057 0 6 8 | B1->B0 | 2b2b 3030 | 0 0 | (0 0) (0 0)
3864 01:01:00.345105 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3865 01:01:00.345154 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3866 01:01:00.345202 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3867 01:01:00.345252 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3868 01:01:00.345301 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3869 01:01:00.345350 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3870 01:01:00.345399 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3871 01:01:00.345447 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3872 01:01:00.345495 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 01:01:00.345543 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 01:01:00.345592 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 01:01:00.345642 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 01:01:00.345691 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 01:01:00.345740 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 01:01:00.345788 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 01:01:00.345836 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 01:01:00.345885 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 01:01:00.345933 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 01:01:00.345982 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 01:01:00.346030 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 01:01:00.346078 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 01:01:00.346126 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 01:01:00.346175 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 01:01:00.346233 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3888 01:01:00.346323 Total UI for P1: 0, mck2ui 16
3889 01:01:00.346372 best dqsien dly found for B0: ( 0, 9, 6)
3890 01:01:00.346421 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3891 01:01:00.346470 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3892 01:01:00.346519 Total UI for P1: 0, mck2ui 16
3893 01:01:00.346569 best dqsien dly found for B1: ( 0, 9, 10)
3894 01:01:00.346618 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3895 01:01:00.346667 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3896 01:01:00.346716
3897 01:01:00.346764 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3898 01:01:00.346812 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3899 01:01:00.346861 [Gating] SW calibration Done
3900 01:01:00.346909 ==
3901 01:01:00.347146 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 01:01:00.347206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3903 01:01:00.347257 ==
3904 01:01:00.347307 RX Vref Scan: 0
3905 01:01:00.347356
3906 01:01:00.347404 RX Vref 0 -> 0, step: 1
3907 01:01:00.347453
3908 01:01:00.347501 RX Delay -230 -> 252, step: 16
3909 01:01:00.347551 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
3910 01:01:00.347602 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3911 01:01:00.347651 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3912 01:01:00.347701 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3913 01:01:00.347750 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3914 01:01:00.347800 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3915 01:01:00.347849 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3916 01:01:00.347898 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3917 01:01:00.347947 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3918 01:01:00.347996 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3919 01:01:00.348045 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3920 01:01:00.348094 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3921 01:01:00.348143 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3922 01:01:00.348192 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3923 01:01:00.348241 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3924 01:01:00.348289 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3925 01:01:00.348338 ==
3926 01:01:00.348387 Dram Type= 6, Freq= 0, CH_0, rank 0
3927 01:01:00.348436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3928 01:01:00.348485 ==
3929 01:01:00.348533 DQS Delay:
3930 01:01:00.348581 DQS0 = 0, DQS1 = 0
3931 01:01:00.348630 DQM Delay:
3932 01:01:00.348678 DQM0 = 41, DQM1 = 33
3933 01:01:00.348727 DQ Delay:
3934 01:01:00.348774 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
3935 01:01:00.348823 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3936 01:01:00.348872 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3937 01:01:00.348921 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3938 01:01:00.348970
3939 01:01:00.349018
3940 01:01:00.349066 ==
3941 01:01:00.349114 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 01:01:00.349163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3943 01:01:00.349213 ==
3944 01:01:00.349261
3945 01:01:00.349309
3946 01:01:00.349357 TX Vref Scan disable
3947 01:01:00.349406 == TX Byte 0 ==
3948 01:01:00.349455 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3949 01:01:00.349504 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3950 01:01:00.349553 == TX Byte 1 ==
3951 01:01:00.349601 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3952 01:01:00.349651 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3953 01:01:00.349700 ==
3954 01:01:00.349748 Dram Type= 6, Freq= 0, CH_0, rank 0
3955 01:01:00.349797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3956 01:01:00.349846 ==
3957 01:01:00.349896
3958 01:01:00.349944
3959 01:01:00.349992 TX Vref Scan disable
3960 01:01:00.350041 == TX Byte 0 ==
3961 01:01:00.350089 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3962 01:01:00.350138 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3963 01:01:00.350187 == TX Byte 1 ==
3964 01:01:00.350269 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3965 01:01:00.350333 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3966 01:01:00.350383
3967 01:01:00.350430 [DATLAT]
3968 01:01:00.350479 Freq=600, CH0 RK0
3969 01:01:00.350527
3970 01:01:00.350575 DATLAT Default: 0x9
3971 01:01:00.350624 0, 0xFFFF, sum = 0
3972 01:01:00.350674 1, 0xFFFF, sum = 0
3973 01:01:00.350722 2, 0xFFFF, sum = 0
3974 01:01:00.350772 3, 0xFFFF, sum = 0
3975 01:01:00.350821 4, 0xFFFF, sum = 0
3976 01:01:00.350870 5, 0xFFFF, sum = 0
3977 01:01:00.350919 6, 0xFFFF, sum = 0
3978 01:01:00.350968 7, 0x0, sum = 1
3979 01:01:00.351018 8, 0x0, sum = 2
3980 01:01:00.351067 9, 0x0, sum = 3
3981 01:01:00.351116 10, 0x0, sum = 4
3982 01:01:00.351165 best_step = 8
3983 01:01:00.351214
3984 01:01:00.351262 ==
3985 01:01:00.351323 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 01:01:00.355054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3987 01:01:00.355133 ==
3988 01:01:00.355193 RX Vref Scan: 1
3989 01:01:00.355248
3990 01:01:00.358223 RX Vref 0 -> 0, step: 1
3991 01:01:00.358318
3992 01:01:00.361619 RX Delay -195 -> 252, step: 8
3993 01:01:00.361695
3994 01:01:00.364670 Set Vref, RX VrefLevel [Byte0]: 50
3995 01:01:00.368194 [Byte1]: 51
3996 01:01:00.654948
3997 01:01:00.655739 Final RX Vref Byte 0 = 50 to rank0
3998 01:01:00.656079 Final RX Vref Byte 1 = 51 to rank0
3999 01:01:00.656378 Final RX Vref Byte 0 = 50 to rank1
4000 01:01:00.656714 Final RX Vref Byte 1 = 51 to rank1==
4001 01:01:00.656997 Dram Type= 6, Freq= 0, CH_0, rank 0
4002 01:01:00.657263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4003 01:01:00.657579 ==
4004 01:01:00.658003 DQS Delay:
4005 01:01:00.658621 DQS0 = 0, DQS1 = 0
4006 01:01:00.659109 DQM Delay:
4007 01:01:00.659521 DQM0 = 39, DQM1 = 30
4008 01:01:00.659918 DQ Delay:
4009 01:01:00.660316 DQ0 =32, DQ1 =40, DQ2 =40, DQ3 =36
4010 01:01:00.660716 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4011 01:01:00.661140 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
4012 01:01:00.661707 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4013 01:01:00.662287
4014 01:01:00.662797
4015 01:01:00.663218 [DQSOSCAuto] RK0, (LSB)MR18= 0x5959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4016 01:01:00.663630 CH0 RK0: MR19=808, MR18=5959
4017 01:01:00.664037 CH0_RK0: MR19=0x808, MR18=0x5959, DQSOSC=393, MR23=63, INC=169, DEC=113
4018 01:01:00.664433
4019 01:01:00.664847 ----->DramcWriteLeveling(PI) begin...
4020 01:01:00.665356 ==
4021 01:01:00.665860 Dram Type= 6, Freq= 0, CH_0, rank 1
4022 01:01:00.666332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4023 01:01:00.666623 ==
4024 01:01:00.666932 Write leveling (Byte 0): 32 => 32
4025 01:01:00.667200 Write leveling (Byte 1): 31 => 31
4026 01:01:00.667454 DramcWriteLeveling(PI) end<-----
4027 01:01:00.667712
4028 01:01:00.667962 ==
4029 01:01:00.668213 Dram Type= 6, Freq= 0, CH_0, rank 1
4030 01:01:00.668463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4031 01:01:00.668719 ==
4032 01:01:00.669222 [Gating] SW mode calibration
4033 01:01:00.669713 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4034 01:01:00.670005 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4035 01:01:00.670304 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 01:01:00.670718 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4037 01:01:00.671229 0 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 1)
4038 01:01:00.671575 0 5 12 | B1->B0 | 2525 2323 | 1 0 | (1 1) (0 0)
4039 01:01:00.671841 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 01:01:00.672146 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 01:01:00.672413 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 01:01:00.672672 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 01:01:00.672926 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 01:01:00.673418 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 01:01:00.673913 0 6 8 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
4046 01:01:00.674350 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 01:01:00.674626 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 01:01:00.674886 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 01:01:00.675143 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 01:01:00.675397 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 01:01:00.675646 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 01:01:00.675896 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 01:01:00.676144 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4054 01:01:00.676395 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 01:01:00.676650 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 01:01:00.676920 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 01:01:00.677183 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 01:01:00.677462 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 01:01:00.677727 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 01:01:00.677980 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 01:01:00.678255 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 01:01:00.678517 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 01:01:00.678770 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 01:01:00.679079 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 01:01:00.679375 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 01:01:00.679560 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 01:01:00.679739 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 01:01:00.679919 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 01:01:00.680099 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4070 01:01:00.680283 Total UI for P1: 0, mck2ui 16
4071 01:01:00.680465 best dqsien dly found for B0: ( 0, 9, 6)
4072 01:01:00.680645 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 01:01:00.680822 Total UI for P1: 0, mck2ui 16
4074 01:01:00.681003 best dqsien dly found for B1: ( 0, 9, 8)
4075 01:01:00.681198 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4076 01:01:00.681384 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4077 01:01:00.681567
4078 01:01:00.681747 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4079 01:01:00.681935 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4080 01:01:00.682184 [Gating] SW calibration Done
4081 01:01:00.682410 ==
4082 01:01:00.682626 Dram Type= 6, Freq= 0, CH_0, rank 1
4083 01:01:00.682815 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4084 01:01:00.682998 ==
4085 01:01:00.683180 RX Vref Scan: 0
4086 01:01:00.683359
4087 01:01:00.683541 RX Vref 0 -> 0, step: 1
4088 01:01:00.683723
4089 01:01:00.683902 RX Delay -230 -> 252, step: 16
4090 01:01:00.684084 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4091 01:01:00.684269 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4092 01:01:00.685433 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4093 01:01:00.688933 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4094 01:01:00.692258 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4095 01:01:00.698533 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4096 01:01:00.701996 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4097 01:01:00.705246 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4098 01:01:00.708499 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4099 01:01:00.714944 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4100 01:01:00.718159 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4101 01:01:00.721640 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4102 01:01:00.724883 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4103 01:01:00.731874 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4104 01:01:00.734988 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4105 01:01:00.738819 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4106 01:01:00.739296 ==
4107 01:01:00.741716 Dram Type= 6, Freq= 0, CH_0, rank 1
4108 01:01:00.744870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4109 01:01:00.745269 ==
4110 01:01:00.748344 DQS Delay:
4111 01:01:00.748741 DQS0 = 0, DQS1 = 0
4112 01:01:00.751465 DQM Delay:
4113 01:01:00.751863 DQM0 = 40, DQM1 = 33
4114 01:01:00.752172 DQ Delay:
4115 01:01:00.754944 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4116 01:01:00.758165 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4117 01:01:00.761486 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4118 01:01:00.764819 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4119 01:01:00.765296
4120 01:01:00.765607
4121 01:01:00.767876 ==
4122 01:01:00.771381 Dram Type= 6, Freq= 0, CH_0, rank 1
4123 01:01:00.774520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4124 01:01:00.774923 ==
4125 01:01:00.775304
4126 01:01:00.775597
4127 01:01:00.777698 TX Vref Scan disable
4128 01:01:00.778094 == TX Byte 0 ==
4129 01:01:00.784947 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4130 01:01:00.787862 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4131 01:01:00.788265 == TX Byte 1 ==
4132 01:01:00.794444 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4133 01:01:00.797956 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4134 01:01:00.798388 ==
4135 01:01:00.801841 Dram Type= 6, Freq= 0, CH_0, rank 1
4136 01:01:00.804428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4137 01:01:00.804829 ==
4138 01:01:00.805139
4139 01:01:00.805425
4140 01:01:00.807668 TX Vref Scan disable
4141 01:01:00.811216 == TX Byte 0 ==
4142 01:01:00.814548 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4143 01:01:00.817940 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4144 01:01:00.820997 == TX Byte 1 ==
4145 01:01:00.824370 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4146 01:01:00.827727 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4147 01:01:00.828123
4148 01:01:00.830975 [DATLAT]
4149 01:01:00.831369 Freq=600, CH0 RK1
4150 01:01:00.831676
4151 01:01:00.834333 DATLAT Default: 0x8
4152 01:01:00.834835 0, 0xFFFF, sum = 0
4153 01:01:00.838058 1, 0xFFFF, sum = 0
4154 01:01:00.838608 2, 0xFFFF, sum = 0
4155 01:01:00.841028 3, 0xFFFF, sum = 0
4156 01:01:00.841431 4, 0xFFFF, sum = 0
4157 01:01:00.844387 5, 0xFFFF, sum = 0
4158 01:01:00.844829 6, 0xFFFF, sum = 0
4159 01:01:00.847884 7, 0x0, sum = 1
4160 01:01:00.848287 8, 0x0, sum = 2
4161 01:01:00.850839 9, 0x0, sum = 3
4162 01:01:00.851254 10, 0x0, sum = 4
4163 01:01:00.854265 best_step = 8
4164 01:01:00.854798
4165 01:01:00.855159 ==
4166 01:01:00.857717 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 01:01:00.861041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4168 01:01:00.861436 ==
4169 01:01:00.861745 RX Vref Scan: 0
4170 01:01:00.864584
4171 01:01:00.865076 RX Vref 0 -> 0, step: 1
4172 01:01:00.865406
4173 01:01:00.867320 RX Delay -195 -> 252, step: 8
4174 01:01:00.874167 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4175 01:01:00.877710 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4176 01:01:00.880740 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4177 01:01:00.884246 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4178 01:01:00.890553 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4179 01:01:00.894021 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4180 01:01:00.897030 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4181 01:01:00.900839 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4182 01:01:00.907118 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4183 01:01:00.910638 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4184 01:01:00.913985 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4185 01:01:00.917344 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4186 01:01:00.923763 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4187 01:01:00.926934 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4188 01:01:00.930208 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4189 01:01:00.933486 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4190 01:01:00.933884 ==
4191 01:01:00.936871 Dram Type= 6, Freq= 0, CH_0, rank 1
4192 01:01:00.943540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4193 01:01:00.944043 ==
4194 01:01:00.944397 DQS Delay:
4195 01:01:00.946645 DQS0 = 0, DQS1 = 0
4196 01:01:00.947043 DQM Delay:
4197 01:01:00.947352 DQM0 = 42, DQM1 = 32
4198 01:01:00.950042 DQ Delay:
4199 01:01:00.953435 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4200 01:01:00.957032 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =48
4201 01:01:00.960067 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4202 01:01:00.963628 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4203 01:01:00.964104
4204 01:01:00.964416
4205 01:01:00.969940 [DQSOSCAuto] RK1, (LSB)MR18= 0x6767, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4206 01:01:00.973513 CH0 RK1: MR19=808, MR18=6767
4207 01:01:00.980150 CH0_RK1: MR19=0x808, MR18=0x6767, DQSOSC=390, MR23=63, INC=172, DEC=114
4208 01:01:00.983409 [RxdqsGatingPostProcess] freq 600
4209 01:01:00.986924 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4210 01:01:00.990025 Pre-setting of DQS Precalculation
4211 01:01:00.996794 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4212 01:01:00.997316 ==
4213 01:01:01.000082 Dram Type= 6, Freq= 0, CH_1, rank 0
4214 01:01:01.002931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4215 01:01:01.003456 ==
4216 01:01:01.010015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4217 01:01:01.016718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4218 01:01:01.019687 [CA 0] Center 35 (5~66) winsize 62
4219 01:01:01.023101 [CA 1] Center 35 (5~66) winsize 62
4220 01:01:01.026465 [CA 2] Center 33 (3~64) winsize 62
4221 01:01:01.029336 [CA 3] Center 33 (3~64) winsize 62
4222 01:01:01.032681 [CA 4] Center 33 (2~64) winsize 63
4223 01:01:01.036124 [CA 5] Center 33 (2~64) winsize 63
4224 01:01:01.036570
4225 01:01:01.039795 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4226 01:01:01.040304
4227 01:01:01.042695 [CATrainingPosCal] consider 1 rank data
4228 01:01:01.045861 u2DelayCellTimex100 = 270/100 ps
4229 01:01:01.049207 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4230 01:01:01.052568 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4231 01:01:01.055808 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4232 01:01:01.059567 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4233 01:01:01.062534 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4234 01:01:01.065794 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4235 01:01:01.066358
4236 01:01:01.072393 CA PerBit enable=1, Macro0, CA PI delay=33
4237 01:01:01.072792
4238 01:01:01.073102 [CBTSetCACLKResult] CA Dly = 33
4239 01:01:01.075571 CS Dly: 4 (0~35)
4240 01:01:01.075980 ==
4241 01:01:01.079095 Dram Type= 6, Freq= 0, CH_1, rank 1
4242 01:01:01.082483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4243 01:01:01.082883 ==
4244 01:01:01.089076 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4245 01:01:01.095549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4246 01:01:01.099147 [CA 0] Center 34 (4~65) winsize 62
4247 01:01:01.102580 [CA 1] Center 34 (4~65) winsize 62
4248 01:01:01.105922 [CA 2] Center 33 (3~64) winsize 62
4249 01:01:01.108873 [CA 3] Center 33 (3~64) winsize 62
4250 01:01:01.112543 [CA 4] Center 32 (2~63) winsize 62
4251 01:01:01.115448 [CA 5] Center 32 (2~63) winsize 62
4252 01:01:01.115849
4253 01:01:01.118783 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4254 01:01:01.119176
4255 01:01:01.121900 [CATrainingPosCal] consider 2 rank data
4256 01:01:01.125855 u2DelayCellTimex100 = 270/100 ps
4257 01:01:01.128591 CA0 delay=35 (5~65),Diff = 3 PI (28 cell)
4258 01:01:01.132277 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4259 01:01:01.135212 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4260 01:01:01.138568 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4261 01:01:01.142090 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4262 01:01:01.148660 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4263 01:01:01.149058
4264 01:01:01.151847 CA PerBit enable=1, Macro0, CA PI delay=32
4265 01:01:01.152243
4266 01:01:01.155077 [CBTSetCACLKResult] CA Dly = 32
4267 01:01:01.155593 CS Dly: 4 (0~36)
4268 01:01:01.155978
4269 01:01:01.158573 ----->DramcWriteLeveling(PI) begin...
4270 01:01:01.158979 ==
4271 01:01:01.161867 Dram Type= 6, Freq= 0, CH_1, rank 0
4272 01:01:01.168459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4273 01:01:01.168863 ==
4274 01:01:01.171674 Write leveling (Byte 0): 25 => 25
4275 01:01:01.172073 Write leveling (Byte 1): 25 => 25
4276 01:01:01.175005 DramcWriteLeveling(PI) end<-----
4277 01:01:01.175400
4278 01:01:01.175704 ==
4279 01:01:01.178424 Dram Type= 6, Freq= 0, CH_1, rank 0
4280 01:01:01.185073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4281 01:01:01.185564 ==
4282 01:01:01.188272 [Gating] SW mode calibration
4283 01:01:01.195043 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4284 01:01:01.198642 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4285 01:01:01.205165 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4286 01:01:01.208119 0 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4287 01:01:01.211846 0 5 8 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
4288 01:01:01.218373 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4289 01:01:01.221937 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 01:01:01.225036 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 01:01:01.231399 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 01:01:01.234798 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4293 01:01:01.237860 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 01:01:01.244788 0 6 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
4295 01:01:01.248095 0 6 8 | B1->B0 | 3333 4141 | 1 0 | (0 0) (0 0)
4296 01:01:01.251848 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 01:01:01.254608 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 01:01:01.261742 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 01:01:01.264809 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 01:01:01.268022 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 01:01:01.274695 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 01:01:01.277955 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 01:01:01.281444 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4304 01:01:01.288002 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4305 01:01:01.291127 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 01:01:01.294812 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 01:01:01.301208 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 01:01:01.304718 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 01:01:01.307846 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 01:01:01.314351 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 01:01:01.317485 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 01:01:01.321204 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 01:01:01.327288 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 01:01:01.330844 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 01:01:01.334002 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 01:01:01.340594 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 01:01:01.343863 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 01:01:01.347100 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 01:01:01.353859 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4320 01:01:01.357215 Total UI for P1: 0, mck2ui 16
4321 01:01:01.360629 best dqsien dly found for B0: ( 0, 9, 6)
4322 01:01:01.363640 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4323 01:01:01.367223 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4324 01:01:01.370503 Total UI for P1: 0, mck2ui 16
4325 01:01:01.373816 best dqsien dly found for B1: ( 0, 9, 10)
4326 01:01:01.377039 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4327 01:01:01.380714 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4328 01:01:01.381197
4329 01:01:01.387029 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4330 01:01:01.390381 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4331 01:01:01.393582 [Gating] SW calibration Done
4332 01:01:01.394078 ==
4333 01:01:01.396919 Dram Type= 6, Freq= 0, CH_1, rank 0
4334 01:01:01.400325 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4335 01:01:01.400804 ==
4336 01:01:01.401117 RX Vref Scan: 0
4337 01:01:01.401406
4338 01:01:01.403873 RX Vref 0 -> 0, step: 1
4339 01:01:01.404268
4340 01:01:01.407186 RX Delay -230 -> 252, step: 16
4341 01:01:01.410550 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4342 01:01:01.413876 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4343 01:01:01.420363 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4344 01:01:01.423604 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4345 01:01:01.426760 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4346 01:01:01.430110 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4347 01:01:01.436546 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4348 01:01:01.440325 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4349 01:01:01.443714 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4350 01:01:01.446668 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4351 01:01:01.453489 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4352 01:01:01.456729 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4353 01:01:01.459741 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4354 01:01:01.463023 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4355 01:01:01.469626 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4356 01:01:01.472999 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4357 01:01:01.473391 ==
4358 01:01:01.476362 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 01:01:01.479737 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4360 01:01:01.480218 ==
4361 01:01:01.482775 DQS Delay:
4362 01:01:01.483164 DQS0 = 0, DQS1 = 0
4363 01:01:01.483471 DQM Delay:
4364 01:01:01.486256 DQM0 = 42, DQM1 = 33
4365 01:01:01.486647 DQ Delay:
4366 01:01:01.489420 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4367 01:01:01.492830 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4368 01:01:01.496189 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4369 01:01:01.499332 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4370 01:01:01.499726
4371 01:01:01.500028
4372 01:01:01.500311 ==
4373 01:01:01.502963 Dram Type= 6, Freq= 0, CH_1, rank 0
4374 01:01:01.509355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4375 01:01:01.509754 ==
4376 01:01:01.510067
4377 01:01:01.510408
4378 01:01:01.510691 TX Vref Scan disable
4379 01:01:01.513178 == TX Byte 0 ==
4380 01:01:01.516297 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4381 01:01:01.522762 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4382 01:01:01.523279 == TX Byte 1 ==
4383 01:01:01.526135 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4384 01:01:01.532730 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4385 01:01:01.533196 ==
4386 01:01:01.535975 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 01:01:01.539255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4388 01:01:01.539654 ==
4389 01:01:01.539960
4390 01:01:01.540416
4391 01:01:01.542932 TX Vref Scan disable
4392 01:01:01.545942 == TX Byte 0 ==
4393 01:01:01.549396 Update DQ dly =569 (2 ,1, 25) DQ OEN =(1 ,6)
4394 01:01:01.552482 Update DQM dly =569 (2 ,1, 25) DQM OEN =(1 ,6)
4395 01:01:01.555635 == TX Byte 1 ==
4396 01:01:01.558974 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4397 01:01:01.562526 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4398 01:01:01.562922
4399 01:01:01.563230 [DATLAT]
4400 01:01:01.565809 Freq=600, CH1 RK0
4401 01:01:01.566495
4402 01:01:01.568877 DATLAT Default: 0x9
4403 01:01:01.569386 0, 0xFFFF, sum = 0
4404 01:01:01.572255 1, 0xFFFF, sum = 0
4405 01:01:01.572664 2, 0xFFFF, sum = 0
4406 01:01:01.575924 3, 0xFFFF, sum = 0
4407 01:01:01.576408 4, 0xFFFF, sum = 0
4408 01:01:01.579146 5, 0xFFFF, sum = 0
4409 01:01:01.579548 6, 0xFFFF, sum = 0
4410 01:01:01.582295 7, 0x0, sum = 1
4411 01:01:01.582781 8, 0x0, sum = 2
4412 01:01:01.583100 9, 0x0, sum = 3
4413 01:01:01.585912 10, 0x0, sum = 4
4414 01:01:01.586497 best_step = 8
4415 01:01:01.586815
4416 01:01:01.587240 ==
4417 01:01:01.588870 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 01:01:01.595787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4419 01:01:01.596248 ==
4420 01:01:01.596553 RX Vref Scan: 1
4421 01:01:01.596835
4422 01:01:01.598912 RX Vref 0 -> 0, step: 1
4423 01:01:01.599311
4424 01:01:01.602687 RX Delay -195 -> 252, step: 8
4425 01:01:01.603250
4426 01:01:01.605513 Set Vref, RX VrefLevel [Byte0]: 51
4427 01:01:01.608828 [Byte1]: 50
4428 01:01:01.609225
4429 01:01:01.612139 Final RX Vref Byte 0 = 51 to rank0
4430 01:01:01.615813 Final RX Vref Byte 1 = 50 to rank0
4431 01:01:01.619031 Final RX Vref Byte 0 = 51 to rank1
4432 01:01:01.622640 Final RX Vref Byte 1 = 50 to rank1==
4433 01:01:01.625548 Dram Type= 6, Freq= 0, CH_1, rank 0
4434 01:01:01.629025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4435 01:01:01.629540 ==
4436 01:01:01.632501 DQS Delay:
4437 01:01:01.632968 DQS0 = 0, DQS1 = 0
4438 01:01:01.635369 DQM Delay:
4439 01:01:01.635760 DQM0 = 37, DQM1 = 31
4440 01:01:01.636064 DQ Delay:
4441 01:01:01.638968 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4442 01:01:01.642289 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4443 01:01:01.645484 DQ8 =12, DQ9 =20, DQ10 =36, DQ11 =24
4444 01:01:01.648815 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4445 01:01:01.649233
4446 01:01:01.649544
4447 01:01:01.658703 [DQSOSCAuto] RK0, (LSB)MR18= 0x8383, (MSB)MR19= 0x808, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
4448 01:01:01.662010 CH1 RK0: MR19=808, MR18=8383
4449 01:01:01.668751 CH1_RK0: MR19=0x808, MR18=0x8383, DQSOSC=385, MR23=63, INC=176, DEC=117
4450 01:01:01.669227
4451 01:01:01.671838 ----->DramcWriteLeveling(PI) begin...
4452 01:01:01.672243 ==
4453 01:01:01.675400 Dram Type= 6, Freq= 0, CH_1, rank 1
4454 01:01:01.678712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4455 01:01:01.679185 ==
4456 01:01:01.681665 Write leveling (Byte 0): 29 => 29
4457 01:01:01.685205 Write leveling (Byte 1): 26 => 26
4458 01:01:01.688464 DramcWriteLeveling(PI) end<-----
4459 01:01:01.688857
4460 01:01:01.689164 ==
4461 01:01:01.691783 Dram Type= 6, Freq= 0, CH_1, rank 1
4462 01:01:01.695069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4463 01:01:01.695466 ==
4464 01:01:01.698401 [Gating] SW mode calibration
4465 01:01:01.705332 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4466 01:01:01.711782 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4467 01:01:01.715239 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 01:01:01.718670 0 5 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
4469 01:01:01.724913 0 5 8 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
4470 01:01:01.728242 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 01:01:01.731567 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 01:01:01.738198 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 01:01:01.741503 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 01:01:01.744696 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 01:01:01.751485 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 01:01:01.754790 0 6 4 | B1->B0 | 2626 3131 | 0 1 | (0 0) (0 0)
4477 01:01:01.757916 0 6 8 | B1->B0 | 3232 4444 | 0 0 | (0 0) (0 0)
4478 01:01:01.764920 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 01:01:01.768027 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 01:01:01.771371 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 01:01:01.778252 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 01:01:01.781235 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 01:01:01.784708 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 01:01:01.788011 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4485 01:01:01.794669 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 01:01:01.797853 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 01:01:01.801335 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 01:01:01.807907 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 01:01:01.811352 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 01:01:01.814368 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 01:01:01.821230 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 01:01:01.824854 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 01:01:01.827652 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 01:01:01.834514 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 01:01:01.837781 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 01:01:01.841205 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 01:01:01.847708 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 01:01:01.851491 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 01:01:01.854295 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4500 01:01:01.861230 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4501 01:01:01.864445 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 01:01:01.867607 Total UI for P1: 0, mck2ui 16
4503 01:01:01.870852 best dqsien dly found for B0: ( 0, 9, 2)
4504 01:01:01.874071 Total UI for P1: 0, mck2ui 16
4505 01:01:01.877606 best dqsien dly found for B1: ( 0, 9, 4)
4506 01:01:01.880758 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4507 01:01:01.884359 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4508 01:01:01.884914
4509 01:01:01.887651 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4510 01:01:01.890745 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4511 01:01:01.894300 [Gating] SW calibration Done
4512 01:01:01.894775 ==
4513 01:01:01.897440 Dram Type= 6, Freq= 0, CH_1, rank 1
4514 01:01:01.900635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4515 01:01:01.903936 ==
4516 01:01:01.904332 RX Vref Scan: 0
4517 01:01:01.904643
4518 01:01:01.907330 RX Vref 0 -> 0, step: 1
4519 01:01:01.907731
4520 01:01:01.910591 RX Delay -230 -> 252, step: 16
4521 01:01:01.914105 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4522 01:01:01.917344 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4523 01:01:01.920643 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4524 01:01:01.927184 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4525 01:01:01.930678 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4526 01:01:01.933771 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4527 01:01:01.937118 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4528 01:01:01.940380 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4529 01:01:01.947140 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4530 01:01:01.950954 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4531 01:01:01.954048 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4532 01:01:01.957158 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4533 01:01:01.964210 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4534 01:01:01.966980 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4535 01:01:01.970526 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4536 01:01:01.973742 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4537 01:01:01.974193 ==
4538 01:01:01.977005 Dram Type= 6, Freq= 0, CH_1, rank 1
4539 01:01:01.983690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4540 01:01:01.984260 ==
4541 01:01:01.984589 DQS Delay:
4542 01:01:01.987129 DQS0 = 0, DQS1 = 0
4543 01:01:01.987530 DQM Delay:
4544 01:01:01.987839 DQM0 = 41, DQM1 = 34
4545 01:01:01.990206 DQ Delay:
4546 01:01:01.993571 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4547 01:01:01.997109 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4548 01:01:02.000562 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4549 01:01:02.003624 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4550 01:01:02.004025
4551 01:01:02.004332
4552 01:01:02.004621 ==
4553 01:01:02.007086 Dram Type= 6, Freq= 0, CH_1, rank 1
4554 01:01:02.010405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4555 01:01:02.010802 ==
4556 01:01:02.011197
4557 01:01:02.011690
4558 01:01:02.013533 TX Vref Scan disable
4559 01:01:02.013929 == TX Byte 0 ==
4560 01:01:02.019940 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4561 01:01:02.023500 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4562 01:01:02.026568 == TX Byte 1 ==
4563 01:01:02.030187 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4564 01:01:02.033224 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4565 01:01:02.033620 ==
4566 01:01:02.036606 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 01:01:02.039763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4568 01:01:02.043087 ==
4569 01:01:02.043478
4570 01:01:02.043782
4571 01:01:02.044067 TX Vref Scan disable
4572 01:01:02.046973 == TX Byte 0 ==
4573 01:01:02.050338 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4574 01:01:02.056947 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4575 01:01:02.057449 == TX Byte 1 ==
4576 01:01:02.060246 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4577 01:01:02.066974 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4578 01:01:02.067374
4579 01:01:02.067682 [DATLAT]
4580 01:01:02.068004 Freq=600, CH1 RK1
4581 01:01:02.068352
4582 01:01:02.070110 DATLAT Default: 0x8
4583 01:01:02.070536 0, 0xFFFF, sum = 0
4584 01:01:02.073398 1, 0xFFFF, sum = 0
4585 01:01:02.077021 2, 0xFFFF, sum = 0
4586 01:01:02.077505 3, 0xFFFF, sum = 0
4587 01:01:02.080147 4, 0xFFFF, sum = 0
4588 01:01:02.080547 5, 0xFFFF, sum = 0
4589 01:01:02.083293 6, 0xFFFF, sum = 0
4590 01:01:02.083694 7, 0x0, sum = 1
4591 01:01:02.084031 8, 0x0, sum = 2
4592 01:01:02.086770 9, 0x0, sum = 3
4593 01:01:02.087170 10, 0x0, sum = 4
4594 01:01:02.089827 best_step = 8
4595 01:01:02.090236
4596 01:01:02.090553 ==
4597 01:01:02.093977 Dram Type= 6, Freq= 0, CH_1, rank 1
4598 01:01:02.096885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4599 01:01:02.097358 ==
4600 01:01:02.100025 RX Vref Scan: 0
4601 01:01:02.100671
4602 01:01:02.101044 RX Vref 0 -> 0, step: 1
4603 01:01:02.101341
4604 01:01:02.103379 RX Delay -195 -> 252, step: 8
4605 01:01:02.110567 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4606 01:01:02.114179 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4607 01:01:02.117104 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4608 01:01:02.120699 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4609 01:01:02.127332 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4610 01:01:02.130754 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4611 01:01:02.133692 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4612 01:01:02.136864 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4613 01:01:02.144064 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4614 01:01:02.146867 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4615 01:01:02.150508 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4616 01:01:02.153750 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4617 01:01:02.157050 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4618 01:01:02.163580 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4619 01:01:02.166898 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4620 01:01:02.170402 iDelay=205, Bit 15, Center 36 (-115 ~ 188) 304
4621 01:01:02.170839 ==
4622 01:01:02.173399 Dram Type= 6, Freq= 0, CH_1, rank 1
4623 01:01:02.180212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4624 01:01:02.180679 ==
4625 01:01:02.180990 DQS Delay:
4626 01:01:02.181278 DQS0 = 0, DQS1 = 0
4627 01:01:02.183331 DQM Delay:
4628 01:01:02.183902 DQM0 = 37, DQM1 = 29
4629 01:01:02.186719 DQ Delay:
4630 01:01:02.190147 DQ0 =36, DQ1 =32, DQ2 =28, DQ3 =32
4631 01:01:02.193558 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4632 01:01:02.194087 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4633 01:01:02.200256 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =36
4634 01:01:02.200650
4635 01:01:02.200956
4636 01:01:02.206830 [DQSOSCAuto] RK1, (LSB)MR18= 0x6363, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4637 01:01:02.210039 CH1 RK1: MR19=808, MR18=6363
4638 01:01:02.217146 CH1_RK1: MR19=0x808, MR18=0x6363, DQSOSC=391, MR23=63, INC=171, DEC=114
4639 01:01:02.220064 [RxdqsGatingPostProcess] freq 600
4640 01:01:02.223379 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4641 01:01:02.226541 Pre-setting of DQS Precalculation
4642 01:01:02.233480 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4643 01:01:02.239943 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4644 01:01:02.246749 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4645 01:01:02.247389
4646 01:01:02.247837
4647 01:01:02.249916 [Calibration Summary] 1200 Mbps
4648 01:01:02.250437 CH 0, Rank 0
4649 01:01:02.253317 SW Impedance : PASS
4650 01:01:02.256563 DUTY Scan : NO K
4651 01:01:02.257112 ZQ Calibration : PASS
4652 01:01:02.259502 Jitter Meter : NO K
4653 01:01:02.262880 CBT Training : PASS
4654 01:01:02.263287 Write leveling : PASS
4655 01:01:02.266484 RX DQS gating : PASS
4656 01:01:02.269527 RX DQ/DQS(RDDQC) : PASS
4657 01:01:02.269922 TX DQ/DQS : PASS
4658 01:01:02.273206 RX DATLAT : PASS
4659 01:01:02.276800 RX DQ/DQS(Engine): PASS
4660 01:01:02.277286 TX OE : NO K
4661 01:01:02.277691 All Pass.
4662 01:01:02.278082
4663 01:01:02.279411 CH 0, Rank 1
4664 01:01:02.282630 SW Impedance : PASS
4665 01:01:02.283187 DUTY Scan : NO K
4666 01:01:02.286090 ZQ Calibration : PASS
4667 01:01:02.286492 Jitter Meter : NO K
4668 01:01:02.289572 CBT Training : PASS
4669 01:01:02.292902 Write leveling : PASS
4670 01:01:02.293448 RX DQS gating : PASS
4671 01:01:02.296109 RX DQ/DQS(RDDQC) : PASS
4672 01:01:02.299348 TX DQ/DQS : PASS
4673 01:01:02.299744 RX DATLAT : PASS
4674 01:01:02.302606 RX DQ/DQS(Engine): PASS
4675 01:01:02.306125 TX OE : NO K
4676 01:01:02.306632 All Pass.
4677 01:01:02.306943
4678 01:01:02.307227 CH 1, Rank 0
4679 01:01:02.309238 SW Impedance : PASS
4680 01:01:02.312892 DUTY Scan : NO K
4681 01:01:02.313372 ZQ Calibration : PASS
4682 01:01:02.316182 Jitter Meter : NO K
4683 01:01:02.319415 CBT Training : PASS
4684 01:01:02.319965 Write leveling : PASS
4685 01:01:02.322771 RX DQS gating : PASS
4686 01:01:02.325912 RX DQ/DQS(RDDQC) : PASS
4687 01:01:02.326421 TX DQ/DQS : PASS
4688 01:01:02.329422 RX DATLAT : PASS
4689 01:01:02.332459 RX DQ/DQS(Engine): PASS
4690 01:01:02.332854 TX OE : NO K
4691 01:01:02.333164 All Pass.
4692 01:01:02.335709
4693 01:01:02.336099 CH 1, Rank 1
4694 01:01:02.339198 SW Impedance : PASS
4695 01:01:02.339591 DUTY Scan : NO K
4696 01:01:02.342559 ZQ Calibration : PASS
4697 01:01:02.342951 Jitter Meter : NO K
4698 01:01:02.345655 CBT Training : PASS
4699 01:01:02.349024 Write leveling : PASS
4700 01:01:02.349419 RX DQS gating : PASS
4701 01:01:02.352350 RX DQ/DQS(RDDQC) : PASS
4702 01:01:02.355740 TX DQ/DQS : PASS
4703 01:01:02.356314 RX DATLAT : PASS
4704 01:01:02.359102 RX DQ/DQS(Engine): PASS
4705 01:01:02.362365 TX OE : NO K
4706 01:01:02.362760 All Pass.
4707 01:01:02.363061
4708 01:01:02.365867 DramC Write-DBI off
4709 01:01:02.366293 PER_BANK_REFRESH: Hybrid Mode
4710 01:01:02.369152 TX_TRACKING: ON
4711 01:01:02.375845 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4712 01:01:02.382639 [FAST_K] Save calibration result to emmc
4713 01:01:02.385622 dramc_set_vcore_voltage set vcore to 662500
4714 01:01:02.386016 Read voltage for 933, 3
4715 01:01:02.389018 Vio18 = 0
4716 01:01:02.389495 Vcore = 662500
4717 01:01:02.389804 Vdram = 0
4718 01:01:02.392283 Vddq = 0
4719 01:01:02.392692 Vmddr = 0
4720 01:01:02.395403 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4721 01:01:02.401996 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4722 01:01:02.405459 MEM_TYPE=3, freq_sel=17
4723 01:01:02.408709 sv_algorithm_assistance_LP4_1600
4724 01:01:02.412076 ============ PULL DRAM RESETB DOWN ============
4725 01:01:02.415286 ========== PULL DRAM RESETB DOWN end =========
4726 01:01:02.422232 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4727 01:01:02.425404 ===================================
4728 01:01:02.425799 LPDDR4 DRAM CONFIGURATION
4729 01:01:02.428586 ===================================
4730 01:01:02.432017 EX_ROW_EN[0] = 0x0
4731 01:01:02.432413 EX_ROW_EN[1] = 0x0
4732 01:01:02.435211 LP4Y_EN = 0x0
4733 01:01:02.435606 WORK_FSP = 0x0
4734 01:01:02.438584 WL = 0x3
4735 01:01:02.438978 RL = 0x3
4736 01:01:02.441816 BL = 0x2
4737 01:01:02.445564 RPST = 0x0
4738 01:01:02.446034 RD_PRE = 0x0
4739 01:01:02.448966 WR_PRE = 0x1
4740 01:01:02.449526 WR_PST = 0x0
4741 01:01:02.451926 DBI_WR = 0x0
4742 01:01:02.452363 DBI_RD = 0x0
4743 01:01:02.455183 OTF = 0x1
4744 01:01:02.458872 ===================================
4745 01:01:02.461798 ===================================
4746 01:01:02.462263 ANA top config
4747 01:01:02.465063 ===================================
4748 01:01:02.468339 DLL_ASYNC_EN = 0
4749 01:01:02.471723 ALL_SLAVE_EN = 1
4750 01:01:02.472157 NEW_RANK_MODE = 1
4751 01:01:02.475205 DLL_IDLE_MODE = 1
4752 01:01:02.478405 LP45_APHY_COMB_EN = 1
4753 01:01:02.481978 TX_ODT_DIS = 1
4754 01:01:02.482492 NEW_8X_MODE = 1
4755 01:01:02.485303 ===================================
4756 01:01:02.488698 ===================================
4757 01:01:02.491988 data_rate = 1866
4758 01:01:02.495379 CKR = 1
4759 01:01:02.498581 DQ_P2S_RATIO = 8
4760 01:01:02.501935 ===================================
4761 01:01:02.505122 CA_P2S_RATIO = 8
4762 01:01:02.508321 DQ_CA_OPEN = 0
4763 01:01:02.508717 DQ_SEMI_OPEN = 0
4764 01:01:02.511716 CA_SEMI_OPEN = 0
4765 01:01:02.514967 CA_FULL_RATE = 0
4766 01:01:02.518379 DQ_CKDIV4_EN = 1
4767 01:01:02.521288 CA_CKDIV4_EN = 1
4768 01:01:02.524996 CA_PREDIV_EN = 0
4769 01:01:02.525509 PH8_DLY = 0
4770 01:01:02.528098 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4771 01:01:02.531593 DQ_AAMCK_DIV = 4
4772 01:01:02.534798 CA_AAMCK_DIV = 4
4773 01:01:02.537987 CA_ADMCK_DIV = 4
4774 01:01:02.541306 DQ_TRACK_CA_EN = 0
4775 01:01:02.544508 CA_PICK = 933
4776 01:01:02.544987 CA_MCKIO = 933
4777 01:01:02.547885 MCKIO_SEMI = 0
4778 01:01:02.551345 PLL_FREQ = 3732
4779 01:01:02.554756 DQ_UI_PI_RATIO = 32
4780 01:01:02.558193 CA_UI_PI_RATIO = 0
4781 01:01:02.561172 ===================================
4782 01:01:02.564373 ===================================
4783 01:01:02.567836 memory_type:LPDDR4
4784 01:01:02.568230 GP_NUM : 10
4785 01:01:02.571392 SRAM_EN : 1
4786 01:01:02.571922 MD32_EN : 0
4787 01:01:02.574483 ===================================
4788 01:01:02.578370 [ANA_INIT] >>>>>>>>>>>>>>
4789 01:01:02.581135 <<<<<< [CONFIGURE PHASE]: ANA_TX
4790 01:01:02.584666 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4791 01:01:02.588072 ===================================
4792 01:01:02.590955 data_rate = 1866,PCW = 0X8f00
4793 01:01:02.594709 ===================================
4794 01:01:02.597815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4795 01:01:02.604581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4796 01:01:02.607692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4797 01:01:02.614324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4798 01:01:02.617763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4799 01:01:02.621039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4800 01:01:02.621482 [ANA_INIT] flow start
4801 01:01:02.624736 [ANA_INIT] PLL >>>>>>>>
4802 01:01:02.627861 [ANA_INIT] PLL <<<<<<<<
4803 01:01:02.628378 [ANA_INIT] MIDPI >>>>>>>>
4804 01:01:02.630925 [ANA_INIT] MIDPI <<<<<<<<
4805 01:01:02.634646 [ANA_INIT] DLL >>>>>>>>
4806 01:01:02.635133 [ANA_INIT] flow end
4807 01:01:02.640785 ============ LP4 DIFF to SE enter ============
4808 01:01:02.644281 ============ LP4 DIFF to SE exit ============
4809 01:01:02.644722 [ANA_INIT] <<<<<<<<<<<<<
4810 01:01:02.647518 [Flow] Enable top DCM control >>>>>
4811 01:01:02.650906 [Flow] Enable top DCM control <<<<<
4812 01:01:02.654286 Enable DLL master slave shuffle
4813 01:01:02.660782 ==============================================================
4814 01:01:02.664083 Gating Mode config
4815 01:01:02.667502 ==============================================================
4816 01:01:02.670700 Config description:
4817 01:01:02.680763 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4818 01:01:02.687404 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4819 01:01:02.690569 SELPH_MODE 0: By rank 1: By Phase
4820 01:01:02.697378 ==============================================================
4821 01:01:02.700765 GAT_TRACK_EN = 1
4822 01:01:02.704357 RX_GATING_MODE = 2
4823 01:01:02.707332 RX_GATING_TRACK_MODE = 2
4824 01:01:02.707848 SELPH_MODE = 1
4825 01:01:02.710524 PICG_EARLY_EN = 1
4826 01:01:02.713842 VALID_LAT_VALUE = 1
4827 01:01:02.720816 ==============================================================
4828 01:01:02.723982 Enter into Gating configuration >>>>
4829 01:01:02.726969 Exit from Gating configuration <<<<
4830 01:01:02.730525 Enter into DVFS_PRE_config >>>>>
4831 01:01:02.740162 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4832 01:01:02.743481 Exit from DVFS_PRE_config <<<<<
4833 01:01:02.747165 Enter into PICG configuration >>>>
4834 01:01:02.750412 Exit from PICG configuration <<<<
4835 01:01:02.753702 [RX_INPUT] configuration >>>>>
4836 01:01:02.757116 [RX_INPUT] configuration <<<<<
4837 01:01:02.760116 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4838 01:01:02.766716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4839 01:01:02.773384 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4840 01:01:02.780055 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4841 01:01:02.786657 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4842 01:01:02.790090 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4843 01:01:02.796563 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4844 01:01:02.799741 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4845 01:01:02.803269 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4846 01:01:02.806689 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4847 01:01:02.813248 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4848 01:01:02.816249 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4849 01:01:02.819830 ===================================
4850 01:01:02.822924 LPDDR4 DRAM CONFIGURATION
4851 01:01:02.826578 ===================================
4852 01:01:02.827106 EX_ROW_EN[0] = 0x0
4853 01:01:02.829696 EX_ROW_EN[1] = 0x0
4854 01:01:02.830128 LP4Y_EN = 0x0
4855 01:01:02.832947 WORK_FSP = 0x0
4856 01:01:02.833383 WL = 0x3
4857 01:01:02.836234 RL = 0x3
4858 01:01:02.836672 BL = 0x2
4859 01:01:02.839547 RPST = 0x0
4860 01:01:02.842657 RD_PRE = 0x0
4861 01:01:02.843094 WR_PRE = 0x1
4862 01:01:02.845965 WR_PST = 0x0
4863 01:01:02.846389 DBI_WR = 0x0
4864 01:01:02.849419 DBI_RD = 0x0
4865 01:01:02.849853 OTF = 0x1
4866 01:01:02.852883 ===================================
4867 01:01:02.856281 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4868 01:01:02.862744 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4869 01:01:02.865884 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4870 01:01:02.869388 ===================================
4871 01:01:02.872756 LPDDR4 DRAM CONFIGURATION
4872 01:01:02.875747 ===================================
4873 01:01:02.876187 EX_ROW_EN[0] = 0x10
4874 01:01:02.879449 EX_ROW_EN[1] = 0x0
4875 01:01:02.879900 LP4Y_EN = 0x0
4876 01:01:02.882510 WORK_FSP = 0x0
4877 01:01:02.882947 WL = 0x3
4878 01:01:02.885793 RL = 0x3
4879 01:01:02.886266 BL = 0x2
4880 01:01:02.889345 RPST = 0x0
4881 01:01:02.892543 RD_PRE = 0x0
4882 01:01:02.893063 WR_PRE = 0x1
4883 01:01:02.895599 WR_PST = 0x0
4884 01:01:02.896089 DBI_WR = 0x0
4885 01:01:02.899158 DBI_RD = 0x0
4886 01:01:02.899597 OTF = 0x1
4887 01:01:02.902516 ===================================
4888 01:01:02.909007 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4889 01:01:02.912686 nWR fixed to 30
4890 01:01:02.916308 [ModeRegInit_LP4] CH0 RK0
4891 01:01:02.916776 [ModeRegInit_LP4] CH0 RK1
4892 01:01:02.919240 [ModeRegInit_LP4] CH1 RK0
4893 01:01:02.922595 [ModeRegInit_LP4] CH1 RK1
4894 01:01:02.922991 match AC timing 8
4895 01:01:02.929405 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4896 01:01:02.932511 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4897 01:01:02.936026 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4898 01:01:02.942493 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4899 01:01:02.945599 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4900 01:01:02.946014 ==
4901 01:01:02.948957 Dram Type= 6, Freq= 0, CH_0, rank 0
4902 01:01:02.952572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4903 01:01:02.953015 ==
4904 01:01:02.959089 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4905 01:01:02.965651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4906 01:01:02.969090 [CA 0] Center 38 (8~69) winsize 62
4907 01:01:02.972382 [CA 1] Center 38 (8~69) winsize 62
4908 01:01:02.975319 [CA 2] Center 36 (6~67) winsize 62
4909 01:01:02.978838 [CA 3] Center 36 (6~67) winsize 62
4910 01:01:02.982045 [CA 4] Center 34 (4~65) winsize 62
4911 01:01:02.985493 [CA 5] Center 34 (4~65) winsize 62
4912 01:01:02.986006
4913 01:01:02.988659 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4914 01:01:02.989110
4915 01:01:02.991955 [CATrainingPosCal] consider 1 rank data
4916 01:01:02.995582 u2DelayCellTimex100 = 270/100 ps
4917 01:01:02.998643 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4918 01:01:03.002043 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4919 01:01:03.005412 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4920 01:01:03.008623 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4921 01:01:03.012069 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4922 01:01:03.018697 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4923 01:01:03.019126
4924 01:01:03.021769 CA PerBit enable=1, Macro0, CA PI delay=34
4925 01:01:03.022167
4926 01:01:03.025299 [CBTSetCACLKResult] CA Dly = 34
4927 01:01:03.025695 CS Dly: 7 (0~38)
4928 01:01:03.026004 ==
4929 01:01:03.028563 Dram Type= 6, Freq= 0, CH_0, rank 1
4930 01:01:03.031620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4931 01:01:03.035045 ==
4932 01:01:03.038251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4933 01:01:03.045276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4934 01:01:03.048740 [CA 0] Center 38 (8~69) winsize 62
4935 01:01:03.051638 [CA 1] Center 38 (8~69) winsize 62
4936 01:01:03.054975 [CA 2] Center 36 (5~67) winsize 63
4937 01:01:03.058443 [CA 3] Center 35 (5~66) winsize 62
4938 01:01:03.061912 [CA 4] Center 34 (4~65) winsize 62
4939 01:01:03.065125 [CA 5] Center 34 (4~65) winsize 62
4940 01:01:03.065529
4941 01:01:03.068233 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4942 01:01:03.068631
4943 01:01:03.071551 [CATrainingPosCal] consider 2 rank data
4944 01:01:03.075093 u2DelayCellTimex100 = 270/100 ps
4945 01:01:03.078297 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4946 01:01:03.081563 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4947 01:01:03.084982 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4948 01:01:03.091488 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4949 01:01:03.094716 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4950 01:01:03.098177 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4951 01:01:03.098607
4952 01:01:03.101449 CA PerBit enable=1, Macro0, CA PI delay=34
4953 01:01:03.101847
4954 01:01:03.105001 [CBTSetCACLKResult] CA Dly = 34
4955 01:01:03.105400 CS Dly: 7 (0~39)
4956 01:01:03.105709
4957 01:01:03.108192 ----->DramcWriteLeveling(PI) begin...
4958 01:01:03.108695 ==
4959 01:01:03.111397 Dram Type= 6, Freq= 0, CH_0, rank 0
4960 01:01:03.117899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4961 01:01:03.118342 ==
4962 01:01:03.121295 Write leveling (Byte 0): 31 => 31
4963 01:01:03.124596 Write leveling (Byte 1): 30 => 30
4964 01:01:03.124995 DramcWriteLeveling(PI) end<-----
4965 01:01:03.127833
4966 01:01:03.128347 ==
4967 01:01:03.131285 Dram Type= 6, Freq= 0, CH_0, rank 0
4968 01:01:03.134569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4969 01:01:03.134970 ==
4970 01:01:03.138118 [Gating] SW mode calibration
4971 01:01:03.144431 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4972 01:01:03.147955 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4973 01:01:03.154658 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4974 01:01:03.157902 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4975 01:01:03.161210 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4976 01:01:03.167811 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4977 01:01:03.171321 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4978 01:01:03.174178 0 10 20 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
4979 01:01:03.180880 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
4980 01:01:03.184213 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4981 01:01:03.187774 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4982 01:01:03.194373 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4983 01:01:03.197509 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4984 01:01:03.201176 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4985 01:01:03.207589 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4986 01:01:03.210720 0 11 20 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (1 1)
4987 01:01:03.214019 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
4988 01:01:03.220747 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4989 01:01:03.224157 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4990 01:01:03.227462 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4991 01:01:03.234160 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4992 01:01:03.237466 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4993 01:01:03.240543 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4994 01:01:03.247237 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4995 01:01:03.250627 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4996 01:01:03.254003 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 01:01:03.260470 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 01:01:03.263722 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 01:01:03.267081 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 01:01:03.273878 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 01:01:03.277123 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 01:01:03.280818 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 01:01:03.287168 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 01:01:03.290874 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 01:01:03.293756 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 01:01:03.300160 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 01:01:03.303571 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 01:01:03.306938 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 01:01:03.313482 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 01:01:03.317268 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5011 01:01:03.320249 Total UI for P1: 0, mck2ui 16
5012 01:01:03.323429 best dqsien dly found for B0: ( 0, 14, 18)
5013 01:01:03.327136 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5014 01:01:03.330466 Total UI for P1: 0, mck2ui 16
5015 01:01:03.333668 best dqsien dly found for B1: ( 0, 14, 20)
5016 01:01:03.336686 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5017 01:01:03.339969 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5018 01:01:03.340404
5019 01:01:03.343463 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5020 01:01:03.350357 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5021 01:01:03.350797 [Gating] SW calibration Done
5022 01:01:03.351138 ==
5023 01:01:03.353647 Dram Type= 6, Freq= 0, CH_0, rank 0
5024 01:01:03.359927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5025 01:01:03.360371 ==
5026 01:01:03.360715 RX Vref Scan: 0
5027 01:01:03.361029
5028 01:01:03.363148 RX Vref 0 -> 0, step: 1
5029 01:01:03.363658
5030 01:01:03.366287 RX Delay -80 -> 252, step: 8
5031 01:01:03.369981 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5032 01:01:03.373376 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5033 01:01:03.376455 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5034 01:01:03.383182 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5035 01:01:03.386399 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5036 01:01:03.389630 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5037 01:01:03.393023 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5038 01:01:03.396527 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5039 01:01:03.399842 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5040 01:01:03.406528 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5041 01:01:03.410175 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5042 01:01:03.412927 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5043 01:01:03.416632 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5044 01:01:03.419511 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5045 01:01:03.426163 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5046 01:01:03.429329 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5047 01:01:03.429765 ==
5048 01:01:03.433138 Dram Type= 6, Freq= 0, CH_0, rank 0
5049 01:01:03.436021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5050 01:01:03.436465 ==
5051 01:01:03.439467 DQS Delay:
5052 01:01:03.439902 DQS0 = 0, DQS1 = 0
5053 01:01:03.440241 DQM Delay:
5054 01:01:03.442834 DQM0 = 95, DQM1 = 84
5055 01:01:03.443270 DQ Delay:
5056 01:01:03.446362 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5057 01:01:03.449839 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5058 01:01:03.453148 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5059 01:01:03.455956 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5060 01:01:03.456394
5061 01:01:03.456730
5062 01:01:03.457038 ==
5063 01:01:03.459373 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 01:01:03.465894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5065 01:01:03.466371 ==
5066 01:01:03.466717
5067 01:01:03.467032
5068 01:01:03.467331 TX Vref Scan disable
5069 01:01:03.469433 == TX Byte 0 ==
5070 01:01:03.473086 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5071 01:01:03.479401 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5072 01:01:03.479844 == TX Byte 1 ==
5073 01:01:03.482657 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5074 01:01:03.489537 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5075 01:01:03.489976 ==
5076 01:01:03.493048 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 01:01:03.496066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5078 01:01:03.496584 ==
5079 01:01:03.496928
5080 01:01:03.497242
5081 01:01:03.499266 TX Vref Scan disable
5082 01:01:03.499701 == TX Byte 0 ==
5083 01:01:03.506208 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5084 01:01:03.509108 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5085 01:01:03.509548 == TX Byte 1 ==
5086 01:01:03.516069 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5087 01:01:03.519308 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5088 01:01:03.519822
5089 01:01:03.520163 [DATLAT]
5090 01:01:03.522207 Freq=933, CH0 RK0
5091 01:01:03.522688
5092 01:01:03.523027 DATLAT Default: 0xd
5093 01:01:03.525801 0, 0xFFFF, sum = 0
5094 01:01:03.526373 1, 0xFFFF, sum = 0
5095 01:01:03.529266 2, 0xFFFF, sum = 0
5096 01:01:03.532298 3, 0xFFFF, sum = 0
5097 01:01:03.532764 4, 0xFFFF, sum = 0
5098 01:01:03.535938 5, 0xFFFF, sum = 0
5099 01:01:03.536500 6, 0xFFFF, sum = 0
5100 01:01:03.538968 7, 0xFFFF, sum = 0
5101 01:01:03.539402 8, 0xFFFF, sum = 0
5102 01:01:03.542036 9, 0xFFFF, sum = 0
5103 01:01:03.542722 10, 0x0, sum = 1
5104 01:01:03.545322 11, 0x0, sum = 2
5105 01:01:03.545967 12, 0x0, sum = 3
5106 01:01:03.548606 13, 0x0, sum = 4
5107 01:01:03.549100 best_step = 11
5108 01:01:03.549437
5109 01:01:03.549748 ==
5110 01:01:03.552028 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 01:01:03.555615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5112 01:01:03.556135 ==
5113 01:01:03.558648 RX Vref Scan: 1
5114 01:01:03.559258
5115 01:01:03.561948 RX Vref 0 -> 0, step: 1
5116 01:01:03.562457
5117 01:01:03.562797 RX Delay -69 -> 252, step: 4
5118 01:01:03.563145
5119 01:01:03.565411 Set Vref, RX VrefLevel [Byte0]: 50
5120 01:01:03.568841 [Byte1]: 51
5121 01:01:03.573289
5122 01:01:03.573757 Final RX Vref Byte 0 = 50 to rank0
5123 01:01:03.576924 Final RX Vref Byte 1 = 51 to rank0
5124 01:01:03.579962 Final RX Vref Byte 0 = 50 to rank1
5125 01:01:03.583450 Final RX Vref Byte 1 = 51 to rank1==
5126 01:01:03.586710 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 01:01:03.593473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5128 01:01:03.593952 ==
5129 01:01:03.594363 DQS Delay:
5130 01:01:03.596557 DQS0 = 0, DQS1 = 0
5131 01:01:03.596947 DQM Delay:
5132 01:01:03.597254 DQM0 = 96, DQM1 = 86
5133 01:01:03.599731 DQ Delay:
5134 01:01:03.603358 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =94
5135 01:01:03.606484 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =102
5136 01:01:03.610042 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5137 01:01:03.613063 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5138 01:01:03.613452
5139 01:01:03.613893
5140 01:01:03.620199 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5141 01:01:03.623179 CH0 RK0: MR19=505, MR18=1F1F
5142 01:01:03.629821 CH0_RK0: MR19=0x505, MR18=0x1F1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5143 01:01:03.630328
5144 01:01:03.633118 ----->DramcWriteLeveling(PI) begin...
5145 01:01:03.633515 ==
5146 01:01:03.636639 Dram Type= 6, Freq= 0, CH_0, rank 1
5147 01:01:03.639994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5148 01:01:03.640394 ==
5149 01:01:03.642885 Write leveling (Byte 0): 28 => 28
5150 01:01:03.646764 Write leveling (Byte 1): 25 => 25
5151 01:01:03.649808 DramcWriteLeveling(PI) end<-----
5152 01:01:03.650305
5153 01:01:03.650612 ==
5154 01:01:03.653371 Dram Type= 6, Freq= 0, CH_0, rank 1
5155 01:01:03.656430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5156 01:01:03.656908 ==
5157 01:01:03.659574 [Gating] SW mode calibration
5158 01:01:03.666004 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5159 01:01:03.672752 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5160 01:01:03.676282 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 01:01:03.683082 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 01:01:03.686278 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 01:01:03.689450 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 01:01:03.696340 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5165 01:01:03.699455 0 10 20 | B1->B0 | 3232 3030 | 1 0 | (1 0) (0 0)
5166 01:01:03.702660 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5167 01:01:03.709826 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 01:01:03.712613 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 01:01:03.715926 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 01:01:03.722885 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 01:01:03.726011 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 01:01:03.729679 0 11 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5173 01:01:03.732568 0 11 20 | B1->B0 | 2f2f 3737 | 1 0 | (0 0) (1 1)
5174 01:01:03.739373 0 11 24 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5175 01:01:03.742600 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 01:01:03.746005 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 01:01:03.752521 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 01:01:03.755892 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 01:01:03.759223 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 01:01:03.765900 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 01:01:03.769340 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5182 01:01:03.772396 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5183 01:01:03.779315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 01:01:03.782533 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 01:01:03.786075 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 01:01:03.792342 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 01:01:03.795438 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 01:01:03.798759 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 01:01:03.805492 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 01:01:03.809388 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 01:01:03.812165 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 01:01:03.818914 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 01:01:03.822448 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 01:01:03.825490 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 01:01:03.832116 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 01:01:03.835378 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 01:01:03.838613 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5198 01:01:03.845381 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 01:01:03.845833 Total UI for P1: 0, mck2ui 16
5200 01:01:03.852059 best dqsien dly found for B0: ( 0, 14, 20)
5201 01:01:03.852570 Total UI for P1: 0, mck2ui 16
5202 01:01:03.858434 best dqsien dly found for B1: ( 0, 14, 20)
5203 01:01:03.862037 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5204 01:01:03.865164 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5205 01:01:03.865613
5206 01:01:03.868474 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5207 01:01:03.871860 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5208 01:01:03.875175 [Gating] SW calibration Done
5209 01:01:03.875611 ==
5210 01:01:03.878468 Dram Type= 6, Freq= 0, CH_0, rank 1
5211 01:01:03.881855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5212 01:01:03.882291 ==
5213 01:01:03.885367 RX Vref Scan: 0
5214 01:01:03.885834
5215 01:01:03.886141 RX Vref 0 -> 0, step: 1
5216 01:01:03.886498
5217 01:01:03.888475 RX Delay -80 -> 252, step: 8
5218 01:01:03.891939 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5219 01:01:03.898339 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5220 01:01:03.901546 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5221 01:01:03.905422 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5222 01:01:03.908530 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5223 01:01:03.911525 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5224 01:01:03.914815 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5225 01:01:03.921378 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5226 01:01:03.925029 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5227 01:01:03.928483 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5228 01:01:03.931463 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5229 01:01:03.938087 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5230 01:01:03.941133 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5231 01:01:03.944538 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5232 01:01:03.947881 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5233 01:01:03.951341 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5234 01:01:03.951815 ==
5235 01:01:03.954418 Dram Type= 6, Freq= 0, CH_0, rank 1
5236 01:01:03.958205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5237 01:01:03.961188 ==
5238 01:01:03.961585 DQS Delay:
5239 01:01:03.961893 DQS0 = 0, DQS1 = 0
5240 01:01:03.964617 DQM Delay:
5241 01:01:03.965024 DQM0 = 96, DQM1 = 87
5242 01:01:03.967667 DQ Delay:
5243 01:01:03.971084 DQ0 =91, DQ1 =103, DQ2 =95, DQ3 =87
5244 01:01:03.974670 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5245 01:01:03.977972 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5246 01:01:03.981041 DQ12 =99, DQ13 =91, DQ14 =99, DQ15 =99
5247 01:01:03.981512
5248 01:01:03.981886
5249 01:01:03.982177 ==
5250 01:01:03.984827 Dram Type= 6, Freq= 0, CH_0, rank 1
5251 01:01:03.987658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5252 01:01:03.988064 ==
5253 01:01:03.988376
5254 01:01:03.988658
5255 01:01:03.991007 TX Vref Scan disable
5256 01:01:03.991400 == TX Byte 0 ==
5257 01:01:03.997772 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5258 01:01:04.001098 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5259 01:01:04.001496 == TX Byte 1 ==
5260 01:01:04.008027 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5261 01:01:04.011225 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5262 01:01:04.011623 ==
5263 01:01:04.014678 Dram Type= 6, Freq= 0, CH_0, rank 1
5264 01:01:04.017779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5265 01:01:04.018291 ==
5266 01:01:04.018607
5267 01:01:04.018892
5268 01:01:04.021336 TX Vref Scan disable
5269 01:01:04.024476 == TX Byte 0 ==
5270 01:01:04.027587 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5271 01:01:04.031241 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5272 01:01:04.034339 == TX Byte 1 ==
5273 01:01:04.037663 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5274 01:01:04.040904 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5275 01:01:04.041338
5276 01:01:04.044147 [DATLAT]
5277 01:01:04.044554 Freq=933, CH0 RK1
5278 01:01:04.044866
5279 01:01:04.047435 DATLAT Default: 0xb
5280 01:01:04.047996 0, 0xFFFF, sum = 0
5281 01:01:04.050859 1, 0xFFFF, sum = 0
5282 01:01:04.051285 2, 0xFFFF, sum = 0
5283 01:01:04.054082 3, 0xFFFF, sum = 0
5284 01:01:04.054508 4, 0xFFFF, sum = 0
5285 01:01:04.057548 5, 0xFFFF, sum = 0
5286 01:01:04.058027 6, 0xFFFF, sum = 0
5287 01:01:04.060702 7, 0xFFFF, sum = 0
5288 01:01:04.063892 8, 0xFFFF, sum = 0
5289 01:01:04.064290 9, 0xFFFF, sum = 0
5290 01:01:04.067265 10, 0x0, sum = 1
5291 01:01:04.067665 11, 0x0, sum = 2
5292 01:01:04.067977 12, 0x0, sum = 3
5293 01:01:04.070444 13, 0x0, sum = 4
5294 01:01:04.070843 best_step = 11
5295 01:01:04.071152
5296 01:01:04.071439 ==
5297 01:01:04.073946 Dram Type= 6, Freq= 0, CH_0, rank 1
5298 01:01:04.080373 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5299 01:01:04.080888 ==
5300 01:01:04.081222 RX Vref Scan: 0
5301 01:01:04.081516
5302 01:01:04.084087 RX Vref 0 -> 0, step: 1
5303 01:01:04.084563
5304 01:01:04.087227 RX Delay -69 -> 252, step: 4
5305 01:01:04.090447 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5306 01:01:04.097247 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5307 01:01:04.100502 iDelay=199, Bit 2, Center 96 (3 ~ 190) 188
5308 01:01:04.103727 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5309 01:01:04.106783 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5310 01:01:04.110484 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5311 01:01:04.113992 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5312 01:01:04.120622 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5313 01:01:04.123636 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5314 01:01:04.127117 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5315 01:01:04.130466 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5316 01:01:04.133666 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5317 01:01:04.140111 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5318 01:01:04.143374 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5319 01:01:04.146890 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5320 01:01:04.150446 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5321 01:01:04.150968 ==
5322 01:01:04.153322 Dram Type= 6, Freq= 0, CH_0, rank 1
5323 01:01:04.156950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5324 01:01:04.160175 ==
5325 01:01:04.160686 DQS Delay:
5326 01:01:04.161029 DQS0 = 0, DQS1 = 0
5327 01:01:04.163436 DQM Delay:
5328 01:01:04.163918 DQM0 = 97, DQM1 = 86
5329 01:01:04.164276 DQ Delay:
5330 01:01:04.166704 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5331 01:01:04.170036 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =108
5332 01:01:04.173410 DQ8 =74, DQ9 =72, DQ10 =88, DQ11 =78
5333 01:01:04.177078 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =96
5334 01:01:04.177519
5335 01:01:04.180014
5336 01:01:04.187122 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d2d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5337 01:01:04.190130 CH0 RK1: MR19=505, MR18=2D2D
5338 01:01:04.196563 CH0_RK1: MR19=0x505, MR18=0x2D2D, DQSOSC=407, MR23=63, INC=65, DEC=43
5339 01:01:04.200137 [RxdqsGatingPostProcess] freq 933
5340 01:01:04.203284 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5341 01:01:04.206805 Pre-setting of DQS Precalculation
5342 01:01:04.213182 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5343 01:01:04.213683 ==
5344 01:01:04.216948 Dram Type= 6, Freq= 0, CH_1, rank 0
5345 01:01:04.219987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5346 01:01:04.220427 ==
5347 01:01:04.226726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5348 01:01:04.229628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5349 01:01:04.233741 [CA 0] Center 37 (7~68) winsize 62
5350 01:01:04.236903 [CA 1] Center 37 (6~68) winsize 63
5351 01:01:04.240293 [CA 2] Center 34 (4~65) winsize 62
5352 01:01:04.243473 [CA 3] Center 34 (4~65) winsize 62
5353 01:01:04.246866 [CA 4] Center 33 (3~64) winsize 62
5354 01:01:04.250060 [CA 5] Center 33 (3~64) winsize 62
5355 01:01:04.250371
5356 01:01:04.253529 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5357 01:01:04.253744
5358 01:01:04.256626 [CATrainingPosCal] consider 1 rank data
5359 01:01:04.259866 u2DelayCellTimex100 = 270/100 ps
5360 01:01:04.263314 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5361 01:01:04.269797 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5362 01:01:04.273525 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5363 01:01:04.277106 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5364 01:01:04.279644 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5365 01:01:04.283131 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5366 01:01:04.283251
5367 01:01:04.286648 CA PerBit enable=1, Macro0, CA PI delay=33
5368 01:01:04.286769
5369 01:01:04.290023 [CBTSetCACLKResult] CA Dly = 33
5370 01:01:04.290144 CS Dly: 5 (0~36)
5371 01:01:04.293037 ==
5372 01:01:04.296433 Dram Type= 6, Freq= 0, CH_1, rank 1
5373 01:01:04.299752 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5374 01:01:04.299876 ==
5375 01:01:04.303069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5376 01:01:04.309671 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5377 01:01:04.313237 [CA 0] Center 37 (6~68) winsize 63
5378 01:01:04.316608 [CA 1] Center 37 (6~68) winsize 63
5379 01:01:04.320165 [CA 2] Center 34 (4~65) winsize 62
5380 01:01:04.323289 [CA 3] Center 34 (4~65) winsize 62
5381 01:01:04.326428 [CA 4] Center 33 (2~64) winsize 63
5382 01:01:04.330296 [CA 5] Center 32 (2~63) winsize 62
5383 01:01:04.330658
5384 01:01:04.333240 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5385 01:01:04.333428
5386 01:01:04.336987 [CATrainingPosCal] consider 2 rank data
5387 01:01:04.339893 u2DelayCellTimex100 = 270/100 ps
5388 01:01:04.343299 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5389 01:01:04.349994 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5390 01:01:04.353424 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5391 01:01:04.356571 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5392 01:01:04.360398 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5393 01:01:04.363370 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5394 01:01:04.363800
5395 01:01:04.366544 CA PerBit enable=1, Macro0, CA PI delay=33
5396 01:01:04.367060
5397 01:01:04.369910 [CBTSetCACLKResult] CA Dly = 33
5398 01:01:04.370340 CS Dly: 5 (0~37)
5399 01:01:04.370652
5400 01:01:04.376594 ----->DramcWriteLeveling(PI) begin...
5401 01:01:04.376990 ==
5402 01:01:04.380071 Dram Type= 6, Freq= 0, CH_1, rank 0
5403 01:01:04.383436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5404 01:01:04.383859 ==
5405 01:01:04.386598 Write leveling (Byte 0): 24 => 24
5406 01:01:04.389789 Write leveling (Byte 1): 24 => 24
5407 01:01:04.393126 DramcWriteLeveling(PI) end<-----
5408 01:01:04.393515
5409 01:01:04.393815 ==
5410 01:01:04.396376 Dram Type= 6, Freq= 0, CH_1, rank 0
5411 01:01:04.399621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5412 01:01:04.400018 ==
5413 01:01:04.402863 [Gating] SW mode calibration
5414 01:01:04.409731 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5415 01:01:04.416247 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5416 01:01:04.419649 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5417 01:01:04.422909 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5418 01:01:04.429785 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5419 01:01:04.433227 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5420 01:01:04.436200 0 10 16 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 1)
5421 01:01:04.442734 0 10 20 | B1->B0 | 3333 2424 | 0 0 | (0 0) (0 0)
5422 01:01:04.446346 0 10 24 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
5423 01:01:04.449326 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 01:01:04.455889 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 01:01:04.459557 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 01:01:04.462640 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5427 01:01:04.468992 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5428 01:01:04.472465 0 11 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5429 01:01:04.475626 0 11 20 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
5430 01:01:04.482183 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5431 01:01:04.485866 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 01:01:04.489400 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 01:01:04.495531 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 01:01:04.499202 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 01:01:04.502253 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 01:01:04.509157 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5437 01:01:04.512325 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5438 01:01:04.515561 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 01:01:04.522426 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 01:01:04.525622 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 01:01:04.528912 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 01:01:04.535665 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 01:01:04.538914 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 01:01:04.541998 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 01:01:04.548476 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 01:01:04.552020 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 01:01:04.555225 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 01:01:04.562014 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 01:01:04.565128 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 01:01:04.568332 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 01:01:04.571675 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 01:01:04.578239 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5453 01:01:04.581937 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5454 01:01:04.585375 Total UI for P1: 0, mck2ui 16
5455 01:01:04.588445 best dqsien dly found for B0: ( 0, 14, 16)
5456 01:01:04.591613 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5457 01:01:04.594926 Total UI for P1: 0, mck2ui 16
5458 01:01:04.598178 best dqsien dly found for B1: ( 0, 14, 20)
5459 01:01:04.602018 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5460 01:01:04.608543 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5461 01:01:04.609069
5462 01:01:04.611741 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5463 01:01:04.614930 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5464 01:01:04.618283 [Gating] SW calibration Done
5465 01:01:04.618804 ==
5466 01:01:04.621558 Dram Type= 6, Freq= 0, CH_1, rank 0
5467 01:01:04.625071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5468 01:01:04.625608 ==
5469 01:01:04.628308 RX Vref Scan: 0
5470 01:01:04.628823
5471 01:01:04.629166 RX Vref 0 -> 0, step: 1
5472 01:01:04.629483
5473 01:01:04.631367 RX Delay -80 -> 252, step: 8
5474 01:01:04.634774 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5475 01:01:04.638175 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5476 01:01:04.644750 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5477 01:01:04.647870 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5478 01:01:04.651398 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5479 01:01:04.654993 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5480 01:01:04.658032 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5481 01:01:04.664644 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5482 01:01:04.667783 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5483 01:01:04.671421 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5484 01:01:04.674688 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5485 01:01:04.677992 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5486 01:01:04.681162 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5487 01:01:04.687881 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5488 01:01:04.690990 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5489 01:01:04.694482 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5490 01:01:04.695014 ==
5491 01:01:04.697735 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 01:01:04.701150 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5493 01:01:04.701667 ==
5494 01:01:04.704301 DQS Delay:
5495 01:01:04.704827 DQS0 = 0, DQS1 = 0
5496 01:01:04.707934 DQM Delay:
5497 01:01:04.708621 DQM0 = 95, DQM1 = 87
5498 01:01:04.708983 DQ Delay:
5499 01:01:04.711085 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5500 01:01:04.714716 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =95
5501 01:01:04.717796 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5502 01:01:04.721186 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5503 01:01:04.721706
5504 01:01:04.722044
5505 01:01:04.724078 ==
5506 01:01:04.727863 Dram Type= 6, Freq= 0, CH_1, rank 0
5507 01:01:04.730671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5508 01:01:04.731109 ==
5509 01:01:04.731448
5510 01:01:04.731762
5511 01:01:04.734374 TX Vref Scan disable
5512 01:01:04.734989 == TX Byte 0 ==
5513 01:01:04.740750 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5514 01:01:04.743999 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5515 01:01:04.744438 == TX Byte 1 ==
5516 01:01:04.751029 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5517 01:01:04.754185 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5518 01:01:04.754743 ==
5519 01:01:04.757790 Dram Type= 6, Freq= 0, CH_1, rank 0
5520 01:01:04.761002 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5521 01:01:04.761530 ==
5522 01:01:04.761880
5523 01:01:04.762194
5524 01:01:04.764146 TX Vref Scan disable
5525 01:01:04.767486 == TX Byte 0 ==
5526 01:01:04.770810 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5527 01:01:04.774285 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5528 01:01:04.777744 == TX Byte 1 ==
5529 01:01:04.780541 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5530 01:01:04.784118 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5531 01:01:04.784708
5532 01:01:04.787227 [DATLAT]
5533 01:01:04.787656 Freq=933, CH1 RK0
5534 01:01:04.787995
5535 01:01:04.790816 DATLAT Default: 0xd
5536 01:01:04.791249 0, 0xFFFF, sum = 0
5537 01:01:04.794456 1, 0xFFFF, sum = 0
5538 01:01:04.795063 2, 0xFFFF, sum = 0
5539 01:01:04.797669 3, 0xFFFF, sum = 0
5540 01:01:04.798196 4, 0xFFFF, sum = 0
5541 01:01:04.800930 5, 0xFFFF, sum = 0
5542 01:01:04.801477 6, 0xFFFF, sum = 0
5543 01:01:04.804032 7, 0xFFFF, sum = 0
5544 01:01:04.804514 8, 0xFFFF, sum = 0
5545 01:01:04.807398 9, 0xFFFF, sum = 0
5546 01:01:04.807841 10, 0x0, sum = 1
5547 01:01:04.810503 11, 0x0, sum = 2
5548 01:01:04.811056 12, 0x0, sum = 3
5549 01:01:04.814008 13, 0x0, sum = 4
5550 01:01:04.814498 best_step = 11
5551 01:01:04.814839
5552 01:01:04.815154 ==
5553 01:01:04.816998 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 01:01:04.820442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5555 01:01:04.823632 ==
5556 01:01:04.824066 RX Vref Scan: 1
5557 01:01:04.824403
5558 01:01:04.826839 RX Vref 0 -> 0, step: 1
5559 01:01:04.827231
5560 01:01:04.830478 RX Delay -69 -> 252, step: 4
5561 01:01:04.830871
5562 01:01:04.833832 Set Vref, RX VrefLevel [Byte0]: 51
5563 01:01:04.836888 [Byte1]: 50
5564 01:01:04.837290
5565 01:01:04.840132 Final RX Vref Byte 0 = 51 to rank0
5566 01:01:04.843656 Final RX Vref Byte 1 = 50 to rank0
5567 01:01:04.846777 Final RX Vref Byte 0 = 51 to rank1
5568 01:01:04.850179 Final RX Vref Byte 1 = 50 to rank1==
5569 01:01:04.853536 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 01:01:04.856940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5571 01:01:04.857334 ==
5572 01:01:04.860094 DQS Delay:
5573 01:01:04.860488 DQS0 = 0, DQS1 = 0
5574 01:01:04.860795 DQM Delay:
5575 01:01:04.863827 DQM0 = 93, DQM1 = 87
5576 01:01:04.864300 DQ Delay:
5577 01:01:04.866841 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =90
5578 01:01:04.870644 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5579 01:01:04.873381 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
5580 01:01:04.876641 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5581 01:01:04.877035
5582 01:01:04.877337
5583 01:01:04.886690 [DQSOSCAuto] RK0, (LSB)MR18= 0x3333, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5584 01:01:04.889903 CH1 RK0: MR19=505, MR18=3333
5585 01:01:04.893300 CH1_RK0: MR19=0x505, MR18=0x3333, DQSOSC=405, MR23=63, INC=66, DEC=44
5586 01:01:04.893694
5587 01:01:04.896792 ----->DramcWriteLeveling(PI) begin...
5588 01:01:04.899944 ==
5589 01:01:04.902974 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 01:01:04.906591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5591 01:01:04.906990 ==
5592 01:01:04.910120 Write leveling (Byte 0): 23 => 23
5593 01:01:04.913440 Write leveling (Byte 1): 24 => 24
5594 01:01:04.917045 DramcWriteLeveling(PI) end<-----
5595 01:01:04.917539
5596 01:01:04.917851 ==
5597 01:01:04.920120 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 01:01:04.922984 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5599 01:01:04.923382 ==
5600 01:01:04.926672 [Gating] SW mode calibration
5601 01:01:04.933280 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 01:01:04.939605 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5603 01:01:04.942756 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 01:01:04.946174 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 01:01:04.952905 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 01:01:04.955837 0 10 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5607 01:01:04.959778 0 10 16 | B1->B0 | 3434 2626 | 1 0 | (0 0) (0 0)
5608 01:01:04.965946 0 10 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5609 01:01:04.969571 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 01:01:04.972554 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 01:01:04.979733 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 01:01:04.982657 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 01:01:04.986040 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 01:01:04.992405 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5615 01:01:04.995675 0 11 16 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
5616 01:01:04.999034 0 11 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
5617 01:01:05.005784 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 01:01:05.009175 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 01:01:05.012551 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 01:01:05.018961 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 01:01:05.022365 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 01:01:05.025772 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 01:01:05.031994 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5624 01:01:05.035673 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5625 01:01:05.038765 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 01:01:05.042174 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 01:01:05.048976 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 01:01:05.052012 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 01:01:05.055247 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 01:01:05.062036 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 01:01:05.065264 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 01:01:05.068447 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 01:01:05.075008 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 01:01:05.078522 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 01:01:05.081607 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 01:01:05.088577 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 01:01:05.091653 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 01:01:05.095140 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 01:01:05.101524 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5640 01:01:05.105170 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5641 01:01:05.107940 Total UI for P1: 0, mck2ui 16
5642 01:01:05.111404 best dqsien dly found for B0: ( 0, 14, 16)
5643 01:01:05.114527 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 01:01:05.118193 Total UI for P1: 0, mck2ui 16
5645 01:01:05.121358 best dqsien dly found for B1: ( 0, 14, 18)
5646 01:01:05.124864 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5647 01:01:05.131198 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5648 01:01:05.131723
5649 01:01:05.134458 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5650 01:01:05.137601 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5651 01:01:05.140912 [Gating] SW calibration Done
5652 01:01:05.141348 ==
5653 01:01:05.144362 Dram Type= 6, Freq= 0, CH_1, rank 1
5654 01:01:05.147774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5655 01:01:05.148403 ==
5656 01:01:05.151258 RX Vref Scan: 0
5657 01:01:05.151719
5658 01:01:05.152031 RX Vref 0 -> 0, step: 1
5659 01:01:05.152321
5660 01:01:05.154161 RX Delay -80 -> 252, step: 8
5661 01:01:05.157589 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5662 01:01:05.161226 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5663 01:01:05.167518 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5664 01:01:05.170780 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5665 01:01:05.174188 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5666 01:01:05.177483 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5667 01:01:05.181250 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5668 01:01:05.184169 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5669 01:01:05.191036 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5670 01:01:05.194030 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5671 01:01:05.197066 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5672 01:01:05.200825 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5673 01:01:05.203742 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5674 01:01:05.210487 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5675 01:01:05.213719 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5676 01:01:05.216997 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5677 01:01:05.217394 ==
5678 01:01:05.220683 Dram Type= 6, Freq= 0, CH_1, rank 1
5679 01:01:05.224067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5680 01:01:05.224549 ==
5681 01:01:05.226874 DQS Delay:
5682 01:01:05.227304 DQS0 = 0, DQS1 = 0
5683 01:01:05.230891 DQM Delay:
5684 01:01:05.231418 DQM0 = 95, DQM1 = 85
5685 01:01:05.231917 DQ Delay:
5686 01:01:05.233734 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =91
5687 01:01:05.237082 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5688 01:01:05.240314 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =75
5689 01:01:05.243658 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5690 01:01:05.244067
5691 01:01:05.244395
5692 01:01:05.247073 ==
5693 01:01:05.247482 Dram Type= 6, Freq= 0, CH_1, rank 1
5694 01:01:05.253637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5695 01:01:05.254032 ==
5696 01:01:05.254383
5697 01:01:05.254669
5698 01:01:05.256802 TX Vref Scan disable
5699 01:01:05.257195 == TX Byte 0 ==
5700 01:01:05.260092 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5701 01:01:05.266871 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5702 01:01:05.267269 == TX Byte 1 ==
5703 01:01:05.270065 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5704 01:01:05.276965 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5705 01:01:05.277643 ==
5706 01:01:05.280548 Dram Type= 6, Freq= 0, CH_1, rank 1
5707 01:01:05.283357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5708 01:01:05.283760 ==
5709 01:01:05.284068
5710 01:01:05.284392
5711 01:01:05.286576 TX Vref Scan disable
5712 01:01:05.290196 == TX Byte 0 ==
5713 01:01:05.293639 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5714 01:01:05.297133 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5715 01:01:05.299994 == TX Byte 1 ==
5716 01:01:05.303456 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5717 01:01:05.306795 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5718 01:01:05.307189
5719 01:01:05.307494 [DATLAT]
5720 01:01:05.309886 Freq=933, CH1 RK1
5721 01:01:05.310301
5722 01:01:05.313391 DATLAT Default: 0xb
5723 01:01:05.313868 0, 0xFFFF, sum = 0
5724 01:01:05.316831 1, 0xFFFF, sum = 0
5725 01:01:05.317229 2, 0xFFFF, sum = 0
5726 01:01:05.319859 3, 0xFFFF, sum = 0
5727 01:01:05.320261 4, 0xFFFF, sum = 0
5728 01:01:05.323405 5, 0xFFFF, sum = 0
5729 01:01:05.323887 6, 0xFFFF, sum = 0
5730 01:01:05.326554 7, 0xFFFF, sum = 0
5731 01:01:05.326951 8, 0xFFFF, sum = 0
5732 01:01:05.329766 9, 0xFFFF, sum = 0
5733 01:01:05.330162 10, 0x0, sum = 1
5734 01:01:05.333119 11, 0x0, sum = 2
5735 01:01:05.333601 12, 0x0, sum = 3
5736 01:01:05.336707 13, 0x0, sum = 4
5737 01:01:05.337184 best_step = 11
5738 01:01:05.337593
5739 01:01:05.337978 ==
5740 01:01:05.340037 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 01:01:05.343032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5742 01:01:05.346273 ==
5743 01:01:05.346672 RX Vref Scan: 0
5744 01:01:05.346982
5745 01:01:05.349708 RX Vref 0 -> 0, step: 1
5746 01:01:05.350097
5747 01:01:05.352873 RX Delay -77 -> 252, step: 4
5748 01:01:05.356522 iDelay=203, Bit 0, Center 98 (11 ~ 186) 176
5749 01:01:05.359531 iDelay=203, Bit 1, Center 92 (3 ~ 182) 180
5750 01:01:05.366398 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5751 01:01:05.369549 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5752 01:01:05.372807 iDelay=203, Bit 4, Center 98 (7 ~ 190) 184
5753 01:01:05.376336 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5754 01:01:05.379468 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5755 01:01:05.382799 iDelay=203, Bit 7, Center 96 (7 ~ 186) 180
5756 01:01:05.389699 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5757 01:01:05.393207 iDelay=203, Bit 9, Center 76 (-13 ~ 166) 180
5758 01:01:05.396119 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5759 01:01:05.399341 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5760 01:01:05.402774 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5761 01:01:05.406341 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5762 01:01:05.412936 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5763 01:01:05.416396 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5764 01:01:05.416908 ==
5765 01:01:05.419426 Dram Type= 6, Freq= 0, CH_1, rank 1
5766 01:01:05.422806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5767 01:01:05.423240 ==
5768 01:01:05.423607 DQS Delay:
5769 01:01:05.425997 DQS0 = 0, DQS1 = 0
5770 01:01:05.426528 DQM Delay:
5771 01:01:05.429607 DQM0 = 96, DQM1 = 87
5772 01:01:05.430123 DQ Delay:
5773 01:01:05.432761 DQ0 =98, DQ1 =92, DQ2 =86, DQ3 =92
5774 01:01:05.435827 DQ4 =98, DQ5 =108, DQ6 =104, DQ7 =96
5775 01:01:05.439359 DQ8 =74, DQ9 =76, DQ10 =86, DQ11 =82
5776 01:01:05.442738 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5777 01:01:05.443289
5778 01:01:05.443761
5779 01:01:05.452766 [DQSOSCAuto] RK1, (LSB)MR18= 0x2626, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5780 01:01:05.453167 CH1 RK1: MR19=505, MR18=2626
5781 01:01:05.459116 CH1_RK1: MR19=0x505, MR18=0x2626, DQSOSC=409, MR23=63, INC=64, DEC=43
5782 01:01:05.462355 [RxdqsGatingPostProcess] freq 933
5783 01:01:05.469012 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5784 01:01:05.472161 Pre-setting of DQS Precalculation
5785 01:01:05.475646 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5786 01:01:05.482325 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5787 01:01:05.492567 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5788 01:01:05.493197
5789 01:01:05.493699
5790 01:01:05.495678 [Calibration Summary] 1866 Mbps
5791 01:01:05.496075 CH 0, Rank 0
5792 01:01:05.499081 SW Impedance : PASS
5793 01:01:05.499476 DUTY Scan : NO K
5794 01:01:05.502250 ZQ Calibration : PASS
5795 01:01:05.505518 Jitter Meter : NO K
5796 01:01:05.505912 CBT Training : PASS
5797 01:01:05.508704 Write leveling : PASS
5798 01:01:05.511992 RX DQS gating : PASS
5799 01:01:05.512392 RX DQ/DQS(RDDQC) : PASS
5800 01:01:05.515497 TX DQ/DQS : PASS
5801 01:01:05.515890 RX DATLAT : PASS
5802 01:01:05.518754 RX DQ/DQS(Engine): PASS
5803 01:01:05.522315 TX OE : NO K
5804 01:01:05.522709 All Pass.
5805 01:01:05.523016
5806 01:01:05.523299 CH 0, Rank 1
5807 01:01:05.525551 SW Impedance : PASS
5808 01:01:05.528952 DUTY Scan : NO K
5809 01:01:05.529461 ZQ Calibration : PASS
5810 01:01:05.532283 Jitter Meter : NO K
5811 01:01:05.535392 CBT Training : PASS
5812 01:01:05.535787 Write leveling : PASS
5813 01:01:05.538809 RX DQS gating : PASS
5814 01:01:05.541947 RX DQ/DQS(RDDQC) : PASS
5815 01:01:05.542370 TX DQ/DQS : PASS
5816 01:01:05.545324 RX DATLAT : PASS
5817 01:01:05.548870 RX DQ/DQS(Engine): PASS
5818 01:01:05.549267 TX OE : NO K
5819 01:01:05.552115 All Pass.
5820 01:01:05.552509
5821 01:01:05.552815 CH 1, Rank 0
5822 01:01:05.555194 SW Impedance : PASS
5823 01:01:05.555611 DUTY Scan : NO K
5824 01:01:05.558573 ZQ Calibration : PASS
5825 01:01:05.561841 Jitter Meter : NO K
5826 01:01:05.562269 CBT Training : PASS
5827 01:01:05.565118 Write leveling : PASS
5828 01:01:05.568634 RX DQS gating : PASS
5829 01:01:05.569028 RX DQ/DQS(RDDQC) : PASS
5830 01:01:05.571790 TX DQ/DQS : PASS
5831 01:01:05.572184 RX DATLAT : PASS
5832 01:01:05.575152 RX DQ/DQS(Engine): PASS
5833 01:01:05.578592 TX OE : NO K
5834 01:01:05.578986 All Pass.
5835 01:01:05.579292
5836 01:01:05.579577 CH 1, Rank 1
5837 01:01:05.581694 SW Impedance : PASS
5838 01:01:05.585138 DUTY Scan : NO K
5839 01:01:05.585528 ZQ Calibration : PASS
5840 01:01:05.588564 Jitter Meter : NO K
5841 01:01:05.591856 CBT Training : PASS
5842 01:01:05.592247 Write leveling : PASS
5843 01:01:05.595415 RX DQS gating : PASS
5844 01:01:05.598508 RX DQ/DQS(RDDQC) : PASS
5845 01:01:05.598900 TX DQ/DQS : PASS
5846 01:01:05.601920 RX DATLAT : PASS
5847 01:01:05.605012 RX DQ/DQS(Engine): PASS
5848 01:01:05.605442 TX OE : NO K
5849 01:01:05.608203 All Pass.
5850 01:01:05.608695
5851 01:01:05.609195 DramC Write-DBI off
5852 01:01:05.611537 PER_BANK_REFRESH: Hybrid Mode
5853 01:01:05.612003 TX_TRACKING: ON
5854 01:01:05.621994 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5855 01:01:05.625191 [FAST_K] Save calibration result to emmc
5856 01:01:05.628405 dramc_set_vcore_voltage set vcore to 650000
5857 01:01:05.631550 Read voltage for 400, 6
5858 01:01:05.631980 Vio18 = 0
5859 01:01:05.634961 Vcore = 650000
5860 01:01:05.635453 Vdram = 0
5861 01:01:05.635835 Vddq = 0
5862 01:01:05.636130 Vmddr = 0
5863 01:01:05.641434 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5864 01:01:05.648360 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5865 01:01:05.648752 MEM_TYPE=3, freq_sel=20
5866 01:01:05.651416 sv_algorithm_assistance_LP4_800
5867 01:01:05.655070 ============ PULL DRAM RESETB DOWN ============
5868 01:01:05.661724 ========== PULL DRAM RESETB DOWN end =========
5869 01:01:05.665274 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5870 01:01:05.668221 ===================================
5871 01:01:05.671537 LPDDR4 DRAM CONFIGURATION
5872 01:01:05.675123 ===================================
5873 01:01:05.675697 EX_ROW_EN[0] = 0x0
5874 01:01:05.678059 EX_ROW_EN[1] = 0x0
5875 01:01:05.678538 LP4Y_EN = 0x0
5876 01:01:05.681629 WORK_FSP = 0x0
5877 01:01:05.682062 WL = 0x2
5878 01:01:05.685103 RL = 0x2
5879 01:01:05.685650 BL = 0x2
5880 01:01:05.688449 RPST = 0x0
5881 01:01:05.691614 RD_PRE = 0x0
5882 01:01:05.692156 WR_PRE = 0x1
5883 01:01:05.695019 WR_PST = 0x0
5884 01:01:05.695552 DBI_WR = 0x0
5885 01:01:05.698155 DBI_RD = 0x0
5886 01:01:05.698644 OTF = 0x1
5887 01:01:05.701553 ===================================
5888 01:01:05.704759 ===================================
5889 01:01:05.708192 ANA top config
5890 01:01:05.711632 ===================================
5891 01:01:05.712149 DLL_ASYNC_EN = 0
5892 01:01:05.714562 ALL_SLAVE_EN = 1
5893 01:01:05.718379 NEW_RANK_MODE = 1
5894 01:01:05.721411 DLL_IDLE_MODE = 1
5895 01:01:05.721940 LP45_APHY_COMB_EN = 1
5896 01:01:05.724783 TX_ODT_DIS = 1
5897 01:01:05.727913 NEW_8X_MODE = 1
5898 01:01:05.731687 ===================================
5899 01:01:05.734493 ===================================
5900 01:01:05.737993 data_rate = 800
5901 01:01:05.741187 CKR = 1
5902 01:01:05.744486 DQ_P2S_RATIO = 4
5903 01:01:05.747851 ===================================
5904 01:01:05.748331 CA_P2S_RATIO = 4
5905 01:01:05.751237 DQ_CA_OPEN = 0
5906 01:01:05.754353 DQ_SEMI_OPEN = 1
5907 01:01:05.758086 CA_SEMI_OPEN = 1
5908 01:01:05.761402 CA_FULL_RATE = 0
5909 01:01:05.764242 DQ_CKDIV4_EN = 0
5910 01:01:05.764677 CA_CKDIV4_EN = 1
5911 01:01:05.767545 CA_PREDIV_EN = 0
5912 01:01:05.770889 PH8_DLY = 0
5913 01:01:05.774279 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5914 01:01:05.777669 DQ_AAMCK_DIV = 0
5915 01:01:05.780673 CA_AAMCK_DIV = 0
5916 01:01:05.781063 CA_ADMCK_DIV = 4
5917 01:01:05.784048 DQ_TRACK_CA_EN = 0
5918 01:01:05.787777 CA_PICK = 800
5919 01:01:05.790806 CA_MCKIO = 400
5920 01:01:05.794001 MCKIO_SEMI = 400
5921 01:01:05.797263 PLL_FREQ = 3016
5922 01:01:05.800910 DQ_UI_PI_RATIO = 32
5923 01:01:05.804351 CA_UI_PI_RATIO = 32
5924 01:01:05.804834 ===================================
5925 01:01:05.807184 ===================================
5926 01:01:05.811003 memory_type:LPDDR4
5927 01:01:05.814272 GP_NUM : 10
5928 01:01:05.814744 SRAM_EN : 1
5929 01:01:05.817237 MD32_EN : 0
5930 01:01:05.820829 ===================================
5931 01:01:05.824005 [ANA_INIT] >>>>>>>>>>>>>>
5932 01:01:05.827442 <<<<<< [CONFIGURE PHASE]: ANA_TX
5933 01:01:05.830821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5934 01:01:05.833918 ===================================
5935 01:01:05.834340 data_rate = 800,PCW = 0X7400
5936 01:01:05.837220 ===================================
5937 01:01:05.840523 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5938 01:01:05.847234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5939 01:01:05.860632 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5940 01:01:05.863650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5941 01:01:05.867291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5942 01:01:05.870610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5943 01:01:05.873694 [ANA_INIT] flow start
5944 01:01:05.874130 [ANA_INIT] PLL >>>>>>>>
5945 01:01:05.877133 [ANA_INIT] PLL <<<<<<<<
5946 01:01:05.880411 [ANA_INIT] MIDPI >>>>>>>>
5947 01:01:05.880848 [ANA_INIT] MIDPI <<<<<<<<
5948 01:01:05.883676 [ANA_INIT] DLL >>>>>>>>
5949 01:01:05.886878 [ANA_INIT] flow end
5950 01:01:05.890150 ============ LP4 DIFF to SE enter ============
5951 01:01:05.893687 ============ LP4 DIFF to SE exit ============
5952 01:01:05.897003 [ANA_INIT] <<<<<<<<<<<<<
5953 01:01:05.900110 [Flow] Enable top DCM control >>>>>
5954 01:01:05.903951 [Flow] Enable top DCM control <<<<<
5955 01:01:05.906947 Enable DLL master slave shuffle
5956 01:01:05.910040 ==============================================================
5957 01:01:05.913419 Gating Mode config
5958 01:01:05.919954 ==============================================================
5959 01:01:05.920463 Config description:
5960 01:01:05.930003 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5961 01:01:05.936815 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5962 01:01:05.943307 SELPH_MODE 0: By rank 1: By Phase
5963 01:01:05.946496 ==============================================================
5964 01:01:05.950019 GAT_TRACK_EN = 0
5965 01:01:05.953149 RX_GATING_MODE = 2
5966 01:01:05.956442 RX_GATING_TRACK_MODE = 2
5967 01:01:05.959896 SELPH_MODE = 1
5968 01:01:05.963180 PICG_EARLY_EN = 1
5969 01:01:05.966534 VALID_LAT_VALUE = 1
5970 01:01:05.969865 ==============================================================
5971 01:01:05.973225 Enter into Gating configuration >>>>
5972 01:01:05.976400 Exit from Gating configuration <<<<
5973 01:01:05.979614 Enter into DVFS_PRE_config >>>>>
5974 01:01:05.992989 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5975 01:01:05.996468 Exit from DVFS_PRE_config <<<<<
5976 01:01:05.999781 Enter into PICG configuration >>>>
5977 01:01:06.000304 Exit from PICG configuration <<<<
5978 01:01:06.002785 [RX_INPUT] configuration >>>>>
5979 01:01:06.006352 [RX_INPUT] configuration <<<<<
5980 01:01:06.012641 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5981 01:01:06.016065 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5982 01:01:06.022830 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5983 01:01:06.029566 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5984 01:01:06.036141 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5985 01:01:06.042701 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5986 01:01:06.046039 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5987 01:01:06.049782 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5988 01:01:06.052882 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5989 01:01:06.059377 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5990 01:01:06.062884 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5991 01:01:06.066021 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5992 01:01:06.069278 ===================================
5993 01:01:06.072978 LPDDR4 DRAM CONFIGURATION
5994 01:01:06.076038 ===================================
5995 01:01:06.079154 EX_ROW_EN[0] = 0x0
5996 01:01:06.079597 EX_ROW_EN[1] = 0x0
5997 01:01:06.082586 LP4Y_EN = 0x0
5998 01:01:06.083027 WORK_FSP = 0x0
5999 01:01:06.085701 WL = 0x2
6000 01:01:06.086140 RL = 0x2
6001 01:01:06.089250 BL = 0x2
6002 01:01:06.089774 RPST = 0x0
6003 01:01:06.092738 RD_PRE = 0x0
6004 01:01:06.093252 WR_PRE = 0x1
6005 01:01:06.095711 WR_PST = 0x0
6006 01:01:06.096147 DBI_WR = 0x0
6007 01:01:06.099066 DBI_RD = 0x0
6008 01:01:06.099503 OTF = 0x1
6009 01:01:06.102405 ===================================
6010 01:01:06.109319 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6011 01:01:06.112239 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6012 01:01:06.115818 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6013 01:01:06.119384 ===================================
6014 01:01:06.122350 LPDDR4 DRAM CONFIGURATION
6015 01:01:06.125738 ===================================
6016 01:01:06.129181 EX_ROW_EN[0] = 0x10
6017 01:01:06.129699 EX_ROW_EN[1] = 0x0
6018 01:01:06.132422 LP4Y_EN = 0x0
6019 01:01:06.132956 WORK_FSP = 0x0
6020 01:01:06.135692 WL = 0x2
6021 01:01:06.136131 RL = 0x2
6022 01:01:06.138997 BL = 0x2
6023 01:01:06.139436 RPST = 0x0
6024 01:01:06.142075 RD_PRE = 0x0
6025 01:01:06.142559 WR_PRE = 0x1
6026 01:01:06.145450 WR_PST = 0x0
6027 01:01:06.145904 DBI_WR = 0x0
6028 01:01:06.148945 DBI_RD = 0x0
6029 01:01:06.149508 OTF = 0x1
6030 01:01:06.152209 ===================================
6031 01:01:06.158732 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6032 01:01:06.163664 nWR fixed to 30
6033 01:01:06.166724 [ModeRegInit_LP4] CH0 RK0
6034 01:01:06.167165 [ModeRegInit_LP4] CH0 RK1
6035 01:01:06.169983 [ModeRegInit_LP4] CH1 RK0
6036 01:01:06.173513 [ModeRegInit_LP4] CH1 RK1
6037 01:01:06.174025 match AC timing 18
6038 01:01:06.180157 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6039 01:01:06.183410 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6040 01:01:06.186947 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6041 01:01:06.193332 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6042 01:01:06.197470 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6043 01:01:06.197951 ==
6044 01:01:06.200614 Dram Type= 6, Freq= 0, CH_0, rank 0
6045 01:01:06.203659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6046 01:01:06.204161 ==
6047 01:01:06.210300 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6048 01:01:06.216874 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6049 01:01:06.219801 [CA 0] Center 36 (8~64) winsize 57
6050 01:01:06.223284 [CA 1] Center 36 (8~64) winsize 57
6051 01:01:06.226620 [CA 2] Center 36 (8~64) winsize 57
6052 01:01:06.227020 [CA 3] Center 36 (8~64) winsize 57
6053 01:01:06.230208 [CA 4] Center 36 (8~64) winsize 57
6054 01:01:06.233399 [CA 5] Center 36 (8~64) winsize 57
6055 01:01:06.233875
6056 01:01:06.239723 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6057 01:01:06.240124
6058 01:01:06.243256 [CATrainingPosCal] consider 1 rank data
6059 01:01:06.246241 u2DelayCellTimex100 = 270/100 ps
6060 01:01:06.249902 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6061 01:01:06.253330 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6062 01:01:06.256274 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6063 01:01:06.259892 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6064 01:01:06.263323 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6065 01:01:06.266457 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6066 01:01:06.266970
6067 01:01:06.269630 CA PerBit enable=1, Macro0, CA PI delay=36
6068 01:01:06.270032
6069 01:01:06.272857 [CBTSetCACLKResult] CA Dly = 36
6070 01:01:06.276036 CS Dly: 1 (0~32)
6071 01:01:06.276433 ==
6072 01:01:06.279408 Dram Type= 6, Freq= 0, CH_0, rank 1
6073 01:01:06.282691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6074 01:01:06.283176 ==
6075 01:01:06.289403 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6076 01:01:06.292866 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6077 01:01:06.296153 [CA 0] Center 36 (8~64) winsize 57
6078 01:01:06.299347 [CA 1] Center 36 (8~64) winsize 57
6079 01:01:06.302648 [CA 2] Center 36 (8~64) winsize 57
6080 01:01:06.305892 [CA 3] Center 36 (8~64) winsize 57
6081 01:01:06.309316 [CA 4] Center 36 (8~64) winsize 57
6082 01:01:06.312854 [CA 5] Center 36 (8~64) winsize 57
6083 01:01:06.313337
6084 01:01:06.315922 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6085 01:01:06.316322
6086 01:01:06.319065 [CATrainingPosCal] consider 2 rank data
6087 01:01:06.323069 u2DelayCellTimex100 = 270/100 ps
6088 01:01:06.325878 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6089 01:01:06.329591 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6090 01:01:06.336044 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6091 01:01:06.339336 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6092 01:01:06.342449 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6093 01:01:06.345822 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6094 01:01:06.346249
6095 01:01:06.349131 CA PerBit enable=1, Macro0, CA PI delay=36
6096 01:01:06.349528
6097 01:01:06.352753 [CBTSetCACLKResult] CA Dly = 36
6098 01:01:06.353230 CS Dly: 1 (0~32)
6099 01:01:06.353545
6100 01:01:06.355699 ----->DramcWriteLeveling(PI) begin...
6101 01:01:06.359044 ==
6102 01:01:06.362666 Dram Type= 6, Freq= 0, CH_0, rank 0
6103 01:01:06.365905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6104 01:01:06.366448 ==
6105 01:01:06.368984 Write leveling (Byte 0): 32 => 0
6106 01:01:06.372406 Write leveling (Byte 1): 32 => 0
6107 01:01:06.375866 DramcWriteLeveling(PI) end<-----
6108 01:01:06.376261
6109 01:01:06.376567 ==
6110 01:01:06.378983 Dram Type= 6, Freq= 0, CH_0, rank 0
6111 01:01:06.382206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6112 01:01:06.382641 ==
6113 01:01:06.385983 [Gating] SW mode calibration
6114 01:01:06.392646 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6115 01:01:06.395887 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6116 01:01:06.402312 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6117 01:01:06.405549 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6118 01:01:06.408623 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6119 01:01:06.415805 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6120 01:01:06.418580 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6121 01:01:06.422316 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6122 01:01:06.428995 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6123 01:01:06.432165 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6124 01:01:06.435780 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6125 01:01:06.439022 Total UI for P1: 0, mck2ui 16
6126 01:01:06.442054 best dqsien dly found for B0: ( 0, 10, 16)
6127 01:01:06.445384 Total UI for P1: 0, mck2ui 16
6128 01:01:06.448500 best dqsien dly found for B1: ( 0, 10, 24)
6129 01:01:06.451936 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6130 01:01:06.455387 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6131 01:01:06.458518
6132 01:01:06.461998 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6133 01:01:06.465399 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6134 01:01:06.468479 [Gating] SW calibration Done
6135 01:01:06.468915 ==
6136 01:01:06.471640 Dram Type= 6, Freq= 0, CH_0, rank 0
6137 01:01:06.474852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6138 01:01:06.475293 ==
6139 01:01:06.478516 RX Vref Scan: 0
6140 01:01:06.478954
6141 01:01:06.479296 RX Vref 0 -> 0, step: 1
6142 01:01:06.479624
6143 01:01:06.481485 RX Delay -410 -> 252, step: 16
6144 01:01:06.484969 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6145 01:01:06.491620 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6146 01:01:06.494820 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6147 01:01:06.498368 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6148 01:01:06.501573 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6149 01:01:06.508097 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6150 01:01:06.511619 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6151 01:01:06.514892 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6152 01:01:06.518163 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6153 01:01:06.525014 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6154 01:01:06.528239 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6155 01:01:06.531450 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6156 01:01:06.538344 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6157 01:01:06.541483 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6158 01:01:06.544453 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6159 01:01:06.547823 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6160 01:01:06.548260 ==
6161 01:01:06.551199 Dram Type= 6, Freq= 0, CH_0, rank 0
6162 01:01:06.557937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6163 01:01:06.558495 ==
6164 01:01:06.558845 DQS Delay:
6165 01:01:06.561148 DQS0 = 51, DQS1 = 59
6166 01:01:06.561583 DQM Delay:
6167 01:01:06.564343 DQM0 = 12, DQM1 = 16
6168 01:01:06.564779 DQ Delay:
6169 01:01:06.568015 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6170 01:01:06.571193 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6171 01:01:06.571629 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6172 01:01:06.577467 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6173 01:01:06.577908
6174 01:01:06.578291
6175 01:01:06.578618 ==
6176 01:01:06.580955 Dram Type= 6, Freq= 0, CH_0, rank 0
6177 01:01:06.584458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6178 01:01:06.584900 ==
6179 01:01:06.585242
6180 01:01:06.585557
6181 01:01:06.587881 TX Vref Scan disable
6182 01:01:06.588316 == TX Byte 0 ==
6183 01:01:06.590964 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6184 01:01:06.597517 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6185 01:01:06.598036 == TX Byte 1 ==
6186 01:01:06.604256 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6187 01:01:06.607981 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6188 01:01:06.608422 ==
6189 01:01:06.610855 Dram Type= 6, Freq= 0, CH_0, rank 0
6190 01:01:06.614129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6191 01:01:06.614590 ==
6192 01:01:06.614917
6193 01:01:06.615229
6194 01:01:06.617608 TX Vref Scan disable
6195 01:01:06.618126 == TX Byte 0 ==
6196 01:01:06.624227 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6197 01:01:06.627254 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6198 01:01:06.627650 == TX Byte 1 ==
6199 01:01:06.634189 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6200 01:01:06.637306 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6201 01:01:06.637701
6202 01:01:06.638008 [DATLAT]
6203 01:01:06.640757 Freq=400, CH0 RK0
6204 01:01:06.641154
6205 01:01:06.641524 DATLAT Default: 0xf
6206 01:01:06.644078 0, 0xFFFF, sum = 0
6207 01:01:06.644484 1, 0xFFFF, sum = 0
6208 01:01:06.647614 2, 0xFFFF, sum = 0
6209 01:01:06.648018 3, 0xFFFF, sum = 0
6210 01:01:06.650675 4, 0xFFFF, sum = 0
6211 01:01:06.651269 5, 0xFFFF, sum = 0
6212 01:01:06.653896 6, 0xFFFF, sum = 0
6213 01:01:06.657302 7, 0xFFFF, sum = 0
6214 01:01:06.657704 8, 0xFFFF, sum = 0
6215 01:01:06.660414 9, 0xFFFF, sum = 0
6216 01:01:06.660845 10, 0xFFFF, sum = 0
6217 01:01:06.664196 11, 0xFFFF, sum = 0
6218 01:01:06.664705 12, 0x0, sum = 1
6219 01:01:06.667502 13, 0x0, sum = 2
6220 01:01:06.667908 14, 0x0, sum = 3
6221 01:01:06.668224 15, 0x0, sum = 4
6222 01:01:06.670691 best_step = 13
6223 01:01:06.671086
6224 01:01:06.671397 ==
6225 01:01:06.673920 Dram Type= 6, Freq= 0, CH_0, rank 0
6226 01:01:06.677110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6227 01:01:06.677644 ==
6228 01:01:06.680465 RX Vref Scan: 1
6229 01:01:06.680866
6230 01:01:06.683811 RX Vref 0 -> 0, step: 1
6231 01:01:06.684205
6232 01:01:06.684513 RX Delay -359 -> 252, step: 8
6233 01:01:06.684805
6234 01:01:06.687062 Set Vref, RX VrefLevel [Byte0]: 50
6235 01:01:06.690389 [Byte1]: 51
6236 01:01:06.695806
6237 01:01:06.696195 Final RX Vref Byte 0 = 50 to rank0
6238 01:01:06.699280 Final RX Vref Byte 1 = 51 to rank0
6239 01:01:06.702597 Final RX Vref Byte 0 = 50 to rank1
6240 01:01:06.705641 Final RX Vref Byte 1 = 51 to rank1==
6241 01:01:06.709415 Dram Type= 6, Freq= 0, CH_0, rank 0
6242 01:01:06.715886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6243 01:01:06.716289 ==
6244 01:01:06.716599 DQS Delay:
6245 01:01:06.719153 DQS0 = 52, DQS1 = 64
6246 01:01:06.719546 DQM Delay:
6247 01:01:06.719932 DQM0 = 8, DQM1 = 14
6248 01:01:06.722348 DQ Delay:
6249 01:01:06.725759 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6250 01:01:06.726310 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6251 01:01:06.728984 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6252 01:01:06.732264 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6253 01:01:06.732667
6254 01:01:06.735532
6255 01:01:06.742102 [DQSOSCAuto] RK0, (LSB)MR18= 0xaeae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6256 01:01:06.745296 CH0 RK0: MR19=C0C, MR18=AEAE
6257 01:01:06.752399 CH0_RK0: MR19=0xC0C, MR18=0xAEAE, DQSOSC=388, MR23=63, INC=392, DEC=261
6258 01:01:06.752805 ==
6259 01:01:06.755598 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 01:01:06.758836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6261 01:01:06.759448 ==
6262 01:01:06.762136 [Gating] SW mode calibration
6263 01:01:06.768782 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6264 01:01:06.775072 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6265 01:01:06.778580 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6266 01:01:06.781699 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 01:01:06.788850 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 01:01:06.792079 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6269 01:01:06.795035 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 01:01:06.798535 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 01:01:06.805173 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 01:01:06.808279 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6273 01:01:06.811720 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 01:01:06.814978 Total UI for P1: 0, mck2ui 16
6275 01:01:06.818326 best dqsien dly found for B0: ( 0, 10, 16)
6276 01:01:06.821788 Total UI for P1: 0, mck2ui 16
6277 01:01:06.824888 best dqsien dly found for B1: ( 0, 10, 16)
6278 01:01:06.828367 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6279 01:01:06.835137 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6280 01:01:06.835598
6281 01:01:06.838428 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6282 01:01:06.841869 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6283 01:01:06.845103 [Gating] SW calibration Done
6284 01:01:06.845542 ==
6285 01:01:06.848087 Dram Type= 6, Freq= 0, CH_0, rank 1
6286 01:01:06.851556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6287 01:01:06.852079 ==
6288 01:01:06.854854 RX Vref Scan: 0
6289 01:01:06.855292
6290 01:01:06.855632 RX Vref 0 -> 0, step: 1
6291 01:01:06.855952
6292 01:01:06.858239 RX Delay -410 -> 252, step: 16
6293 01:01:06.861433 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6294 01:01:06.868311 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6295 01:01:06.871617 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6296 01:01:06.874891 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6297 01:01:06.878098 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6298 01:01:06.884837 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6299 01:01:06.888007 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6300 01:01:06.891292 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6301 01:01:06.894854 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6302 01:01:06.901366 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6303 01:01:06.904704 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6304 01:01:06.907766 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6305 01:01:06.914482 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6306 01:01:06.917664 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6307 01:01:06.920748 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6308 01:01:06.924287 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6309 01:01:06.924459 ==
6310 01:01:06.927783 Dram Type= 6, Freq= 0, CH_0, rank 1
6311 01:01:06.933995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6312 01:01:06.934168 ==
6313 01:01:06.934301 DQS Delay:
6314 01:01:06.937839 DQS0 = 43, DQS1 = 59
6315 01:01:06.937947 DQM Delay:
6316 01:01:06.938031 DQM0 = 6, DQM1 = 14
6317 01:01:06.940800 DQ Delay:
6318 01:01:06.944181 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6319 01:01:06.944279 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6320 01:01:06.947628 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6321 01:01:06.950835 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6322 01:01:06.950917
6323 01:01:06.953975
6324 01:01:06.954053 ==
6325 01:01:06.957230 Dram Type= 6, Freq= 0, CH_0, rank 1
6326 01:01:06.960820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6327 01:01:06.960900 ==
6328 01:01:06.960962
6329 01:01:06.961018
6330 01:01:06.964009 TX Vref Scan disable
6331 01:01:06.964088 == TX Byte 0 ==
6332 01:01:06.967285 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6333 01:01:06.974028 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6334 01:01:06.974130 == TX Byte 1 ==
6335 01:01:06.977260 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6336 01:01:06.983754 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6337 01:01:06.983845 ==
6338 01:01:06.987364 Dram Type= 6, Freq= 0, CH_0, rank 1
6339 01:01:06.990527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6340 01:01:06.990608 ==
6341 01:01:06.990668
6342 01:01:06.990724
6343 01:01:06.993719 TX Vref Scan disable
6344 01:01:06.993802 == TX Byte 0 ==
6345 01:01:06.997026 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6346 01:01:07.003639 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6347 01:01:07.003724 == TX Byte 1 ==
6348 01:01:07.007015 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6349 01:01:07.013487 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6350 01:01:07.013574
6351 01:01:07.013643 [DATLAT]
6352 01:01:07.013698 Freq=400, CH0 RK1
6353 01:01:07.016735
6354 01:01:07.016819 DATLAT Default: 0xd
6355 01:01:07.020118 0, 0xFFFF, sum = 0
6356 01:01:07.020199 1, 0xFFFF, sum = 0
6357 01:01:07.023460 2, 0xFFFF, sum = 0
6358 01:01:07.023540 3, 0xFFFF, sum = 0
6359 01:01:07.026725 4, 0xFFFF, sum = 0
6360 01:01:07.026811 5, 0xFFFF, sum = 0
6361 01:01:07.030101 6, 0xFFFF, sum = 0
6362 01:01:07.030181 7, 0xFFFF, sum = 0
6363 01:01:07.033310 8, 0xFFFF, sum = 0
6364 01:01:07.033390 9, 0xFFFF, sum = 0
6365 01:01:07.036744 10, 0xFFFF, sum = 0
6366 01:01:07.036824 11, 0xFFFF, sum = 0
6367 01:01:07.039943 12, 0x0, sum = 1
6368 01:01:07.040022 13, 0x0, sum = 2
6369 01:01:07.043453 14, 0x0, sum = 3
6370 01:01:07.043532 15, 0x0, sum = 4
6371 01:01:07.047013 best_step = 13
6372 01:01:07.047092
6373 01:01:07.047154 ==
6374 01:01:07.049930 Dram Type= 6, Freq= 0, CH_0, rank 1
6375 01:01:07.053522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6376 01:01:07.053604 ==
6377 01:01:07.056642 RX Vref Scan: 0
6378 01:01:07.056724
6379 01:01:07.056785 RX Vref 0 -> 0, step: 1
6380 01:01:07.056843
6381 01:01:07.059879 RX Delay -359 -> 252, step: 8
6382 01:01:07.067817 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6383 01:01:07.070942 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6384 01:01:07.074397 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6385 01:01:07.077641 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6386 01:01:07.084248 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6387 01:01:07.087791 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6388 01:01:07.090985 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6389 01:01:07.094121 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6390 01:01:07.100845 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6391 01:01:07.104202 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6392 01:01:07.107509 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6393 01:01:07.114168 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6394 01:01:07.117542 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6395 01:01:07.120725 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6396 01:01:07.123918 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6397 01:01:07.130901 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6398 01:01:07.131215 ==
6399 01:01:07.134380 Dram Type= 6, Freq= 0, CH_0, rank 1
6400 01:01:07.137704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6401 01:01:07.138009 ==
6402 01:01:07.138193 DQS Delay:
6403 01:01:07.140933 DQS0 = 52, DQS1 = 64
6404 01:01:07.141231 DQM Delay:
6405 01:01:07.144080 DQM0 = 10, DQM1 = 14
6406 01:01:07.144329 DQ Delay:
6407 01:01:07.147306 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6408 01:01:07.150537 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6409 01:01:07.153790 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6410 01:01:07.157399 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6411 01:01:07.157708
6412 01:01:07.157892
6413 01:01:07.164202 [DQSOSCAuto] RK1, (LSB)MR18= 0xc9c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6414 01:01:07.167475 CH0 RK1: MR19=C0C, MR18=C9C9
6415 01:01:07.174250 CH0_RK1: MR19=0xC0C, MR18=0xC9C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6416 01:01:07.177476 [RxdqsGatingPostProcess] freq 400
6417 01:01:07.184383 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6418 01:01:07.184885 Pre-setting of DQS Precalculation
6419 01:01:07.190997 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6420 01:01:07.191427 ==
6421 01:01:07.194101 Dram Type= 6, Freq= 0, CH_1, rank 0
6422 01:01:07.197618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6423 01:01:07.198143 ==
6424 01:01:07.204212 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6425 01:01:07.210762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6426 01:01:07.214012 [CA 0] Center 36 (8~64) winsize 57
6427 01:01:07.217618 [CA 1] Center 36 (8~64) winsize 57
6428 01:01:07.220875 [CA 2] Center 36 (8~64) winsize 57
6429 01:01:07.224113 [CA 3] Center 36 (8~64) winsize 57
6430 01:01:07.224664 [CA 4] Center 36 (8~64) winsize 57
6431 01:01:07.227279 [CA 5] Center 36 (8~64) winsize 57
6432 01:01:07.227708
6433 01:01:07.233888 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6434 01:01:07.234482
6435 01:01:07.237376 [CATrainingPosCal] consider 1 rank data
6436 01:01:07.240786 u2DelayCellTimex100 = 270/100 ps
6437 01:01:07.244102 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6438 01:01:07.247185 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6439 01:01:07.250674 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6440 01:01:07.254000 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6441 01:01:07.257325 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6442 01:01:07.260605 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6443 01:01:07.261034
6444 01:01:07.264097 CA PerBit enable=1, Macro0, CA PI delay=36
6445 01:01:07.264607
6446 01:01:07.267123 [CBTSetCACLKResult] CA Dly = 36
6447 01:01:07.270503 CS Dly: 1 (0~32)
6448 01:01:07.270929 ==
6449 01:01:07.273564 Dram Type= 6, Freq= 0, CH_1, rank 1
6450 01:01:07.277099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6451 01:01:07.277606 ==
6452 01:01:07.283722 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6453 01:01:07.290642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6454 01:01:07.291159 [CA 0] Center 36 (8~64) winsize 57
6455 01:01:07.293716 [CA 1] Center 36 (8~64) winsize 57
6456 01:01:07.296969 [CA 2] Center 36 (8~64) winsize 57
6457 01:01:07.300374 [CA 3] Center 36 (8~64) winsize 57
6458 01:01:07.303506 [CA 4] Center 36 (8~64) winsize 57
6459 01:01:07.307092 [CA 5] Center 36 (8~64) winsize 57
6460 01:01:07.307739
6461 01:01:07.310503 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6462 01:01:07.310938
6463 01:01:07.313530 [CATrainingPosCal] consider 2 rank data
6464 01:01:07.316979 u2DelayCellTimex100 = 270/100 ps
6465 01:01:07.320093 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6466 01:01:07.323515 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6467 01:01:07.330319 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6468 01:01:07.333811 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6469 01:01:07.336837 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6470 01:01:07.339998 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6471 01:01:07.340434
6472 01:01:07.343367 CA PerBit enable=1, Macro0, CA PI delay=36
6473 01:01:07.343803
6474 01:01:07.346593 [CBTSetCACLKResult] CA Dly = 36
6475 01:01:07.347029 CS Dly: 1 (0~32)
6476 01:01:07.347366
6477 01:01:07.353688 ----->DramcWriteLeveling(PI) begin...
6478 01:01:07.354270 ==
6479 01:01:07.356954 Dram Type= 6, Freq= 0, CH_1, rank 0
6480 01:01:07.359941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6481 01:01:07.360479 ==
6482 01:01:07.363407 Write leveling (Byte 0): 32 => 0
6483 01:01:07.366516 Write leveling (Byte 1): 32 => 0
6484 01:01:07.370072 DramcWriteLeveling(PI) end<-----
6485 01:01:07.370656
6486 01:01:07.371100 ==
6487 01:01:07.373315 Dram Type= 6, Freq= 0, CH_1, rank 0
6488 01:01:07.376831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6489 01:01:07.377438 ==
6490 01:01:07.379946 [Gating] SW mode calibration
6491 01:01:07.386625 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6492 01:01:07.389979 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6493 01:01:07.396574 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6494 01:01:07.400282 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 01:01:07.402974 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 01:01:07.409757 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
6497 01:01:07.413195 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 01:01:07.416249 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 01:01:07.422916 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 01:01:07.426780 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6501 01:01:07.429783 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 01:01:07.433498 Total UI for P1: 0, mck2ui 16
6503 01:01:07.436241 best dqsien dly found for B0: ( 0, 10, 16)
6504 01:01:07.440137 Total UI for P1: 0, mck2ui 16
6505 01:01:07.442918 best dqsien dly found for B1: ( 0, 10, 16)
6506 01:01:07.446430 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6507 01:01:07.449481 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6508 01:01:07.452649
6509 01:01:07.456305 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6510 01:01:07.459439 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6511 01:01:07.463039 [Gating] SW calibration Done
6512 01:01:07.463556 ==
6513 01:01:07.466599 Dram Type= 6, Freq= 0, CH_1, rank 0
6514 01:01:07.469489 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6515 01:01:07.470022 ==
6516 01:01:07.472843 RX Vref Scan: 0
6517 01:01:07.473277
6518 01:01:07.473682 RX Vref 0 -> 0, step: 1
6519 01:01:07.474017
6520 01:01:07.476022 RX Delay -410 -> 252, step: 16
6521 01:01:07.479310 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6522 01:01:07.486066 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6523 01:01:07.489253 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6524 01:01:07.492645 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6525 01:01:07.495981 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6526 01:01:07.502721 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6527 01:01:07.506007 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6528 01:01:07.509103 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6529 01:01:07.512531 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6530 01:01:07.518987 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6531 01:01:07.522730 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6532 01:01:07.526035 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6533 01:01:07.529328 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6534 01:01:07.535755 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6535 01:01:07.538895 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6536 01:01:07.542517 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6537 01:01:07.542957 ==
6538 01:01:07.545697 Dram Type= 6, Freq= 0, CH_1, rank 0
6539 01:01:07.552438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6540 01:01:07.552880 ==
6541 01:01:07.553224 DQS Delay:
6542 01:01:07.555689 DQS0 = 43, DQS1 = 59
6543 01:01:07.556130 DQM Delay:
6544 01:01:07.556477 DQM0 = 6, DQM1 = 14
6545 01:01:07.558765 DQ Delay:
6546 01:01:07.562170 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6547 01:01:07.565613 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6548 01:01:07.566129 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6549 01:01:07.569220 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6550 01:01:07.572029
6551 01:01:07.572563
6552 01:01:07.572935 ==
6553 01:01:07.575190 Dram Type= 6, Freq= 0, CH_1, rank 0
6554 01:01:07.578558 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6555 01:01:07.579003 ==
6556 01:01:07.579347
6557 01:01:07.579663
6558 01:01:07.581981 TX Vref Scan disable
6559 01:01:07.582507 == TX Byte 0 ==
6560 01:01:07.585246 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6561 01:01:07.591923 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6562 01:01:07.592441 == TX Byte 1 ==
6563 01:01:07.598557 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6564 01:01:07.601594 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6565 01:01:07.602035 ==
6566 01:01:07.605236 Dram Type= 6, Freq= 0, CH_1, rank 0
6567 01:01:07.608281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6568 01:01:07.608729 ==
6569 01:01:07.609088
6570 01:01:07.609407
6571 01:01:07.611840 TX Vref Scan disable
6572 01:01:07.612285 == TX Byte 0 ==
6573 01:01:07.618302 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6574 01:01:07.621468 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6575 01:01:07.621909 == TX Byte 1 ==
6576 01:01:07.628416 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6577 01:01:07.631744 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6578 01:01:07.632255
6579 01:01:07.632601 [DATLAT]
6580 01:01:07.634877 Freq=400, CH1 RK0
6581 01:01:07.635317
6582 01:01:07.635659 DATLAT Default: 0xf
6583 01:01:07.638252 0, 0xFFFF, sum = 0
6584 01:01:07.638715 1, 0xFFFF, sum = 0
6585 01:01:07.641479 2, 0xFFFF, sum = 0
6586 01:01:07.641923 3, 0xFFFF, sum = 0
6587 01:01:07.644965 4, 0xFFFF, sum = 0
6588 01:01:07.645413 5, 0xFFFF, sum = 0
6589 01:01:07.648386 6, 0xFFFF, sum = 0
6590 01:01:07.651634 7, 0xFFFF, sum = 0
6591 01:01:07.652078 8, 0xFFFF, sum = 0
6592 01:01:07.655131 9, 0xFFFF, sum = 0
6593 01:01:07.655575 10, 0xFFFF, sum = 0
6594 01:01:07.658336 11, 0xFFFF, sum = 0
6595 01:01:07.658855 12, 0x0, sum = 1
6596 01:01:07.661424 13, 0x0, sum = 2
6597 01:01:07.661867 14, 0x0, sum = 3
6598 01:01:07.662250 15, 0x0, sum = 4
6599 01:01:07.665048 best_step = 13
6600 01:01:07.665559
6601 01:01:07.665899 ==
6602 01:01:07.668133 Dram Type= 6, Freq= 0, CH_1, rank 0
6603 01:01:07.671452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6604 01:01:07.671906 ==
6605 01:01:07.674940 RX Vref Scan: 1
6606 01:01:07.675450
6607 01:01:07.678132 RX Vref 0 -> 0, step: 1
6608 01:01:07.678616
6609 01:01:07.678961 RX Delay -359 -> 252, step: 8
6610 01:01:07.679282
6611 01:01:07.681340 Set Vref, RX VrefLevel [Byte0]: 51
6612 01:01:07.684612 [Byte1]: 50
6613 01:01:07.690267
6614 01:01:07.690706 Final RX Vref Byte 0 = 51 to rank0
6615 01:01:07.693721 Final RX Vref Byte 1 = 50 to rank0
6616 01:01:07.696600 Final RX Vref Byte 0 = 51 to rank1
6617 01:01:07.699812 Final RX Vref Byte 1 = 50 to rank1==
6618 01:01:07.703280 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 01:01:07.709980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6620 01:01:07.710459 ==
6621 01:01:07.710800 DQS Delay:
6622 01:01:07.713481 DQS0 = 48, DQS1 = 64
6623 01:01:07.713906 DQM Delay:
6624 01:01:07.714289 DQM0 = 9, DQM1 = 15
6625 01:01:07.716879 DQ Delay:
6626 01:01:07.717447 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =8
6627 01:01:07.719908 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6628 01:01:07.723245 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6629 01:01:07.726962 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6630 01:01:07.727468
6631 01:01:07.727809
6632 01:01:07.736480 [DQSOSCAuto] RK0, (LSB)MR18= 0xe6e6, (MSB)MR19= 0xc0c, tDQSOscB0 = 381 ps tDQSOscB1 = 381 ps
6633 01:01:07.740104 CH1 RK0: MR19=C0C, MR18=E6E6
6634 01:01:07.746487 CH1_RK0: MR19=0xC0C, MR18=0xE6E6, DQSOSC=381, MR23=63, INC=406, DEC=271
6635 01:01:07.746928 ==
6636 01:01:07.749684 Dram Type= 6, Freq= 0, CH_1, rank 1
6637 01:01:07.753172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6638 01:01:07.753608 ==
6639 01:01:07.756148 [Gating] SW mode calibration
6640 01:01:07.762987 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6641 01:01:07.766452 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6642 01:01:07.772797 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6643 01:01:07.776631 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6644 01:01:07.779543 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6645 01:01:07.786060 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6646 01:01:07.789393 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6647 01:01:07.792790 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6648 01:01:07.799262 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 01:01:07.802477 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6650 01:01:07.805678 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 01:01:07.809066 Total UI for P1: 0, mck2ui 16
6652 01:01:07.812838 best dqsien dly found for B0: ( 0, 10, 16)
6653 01:01:07.815827 Total UI for P1: 0, mck2ui 16
6654 01:01:07.819374 best dqsien dly found for B1: ( 0, 10, 16)
6655 01:01:07.822516 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6656 01:01:07.829016 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6657 01:01:07.829645
6658 01:01:07.832436 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6659 01:01:07.835819 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6660 01:01:07.838806 [Gating] SW calibration Done
6661 01:01:07.839257 ==
6662 01:01:07.842295 Dram Type= 6, Freq= 0, CH_1, rank 1
6663 01:01:07.845540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6664 01:01:07.846023 ==
6665 01:01:07.848751 RX Vref Scan: 0
6666 01:01:07.849253
6667 01:01:07.849601 RX Vref 0 -> 0, step: 1
6668 01:01:07.849924
6669 01:01:07.852149 RX Delay -410 -> 252, step: 16
6670 01:01:07.858779 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6671 01:01:07.862081 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6672 01:01:07.865567 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6673 01:01:07.868749 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6674 01:01:07.875282 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6675 01:01:07.878583 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6676 01:01:07.881779 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6677 01:01:07.885130 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6678 01:01:07.891860 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6679 01:01:07.895398 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6680 01:01:07.898303 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6681 01:01:07.901847 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6682 01:01:07.908562 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6683 01:01:07.911870 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6684 01:01:07.914794 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6685 01:01:07.918198 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6686 01:01:07.921524 ==
6687 01:01:07.925167 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 01:01:07.928593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6689 01:01:07.929029 ==
6690 01:01:07.929391 DQS Delay:
6691 01:01:07.931576 DQS0 = 35, DQS1 = 59
6692 01:01:07.932033 DQM Delay:
6693 01:01:07.934817 DQM0 = 5, DQM1 = 17
6694 01:01:07.935252 DQ Delay:
6695 01:01:07.938023 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6696 01:01:07.941650 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6697 01:01:07.945068 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6698 01:01:07.947902 DQ12 =32, DQ13 =24, DQ14 =32, DQ15 =24
6699 01:01:07.948449
6700 01:01:07.948928
6701 01:01:07.949401 ==
6702 01:01:07.951389 Dram Type= 6, Freq= 0, CH_1, rank 1
6703 01:01:07.954890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6704 01:01:07.955381 ==
6705 01:01:07.955752
6706 01:01:07.956046
6707 01:01:07.958077 TX Vref Scan disable
6708 01:01:07.958497 == TX Byte 0 ==
6709 01:01:07.964859 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6710 01:01:07.967914 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6711 01:01:07.968307 == TX Byte 1 ==
6712 01:01:07.971332 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6713 01:01:07.978003 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6714 01:01:07.978664 ==
6715 01:01:07.981497 Dram Type= 6, Freq= 0, CH_1, rank 1
6716 01:01:07.984428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6717 01:01:07.984870 ==
6718 01:01:07.985231
6719 01:01:07.985794
6720 01:01:07.987811 TX Vref Scan disable
6721 01:01:07.988272 == TX Byte 0 ==
6722 01:01:07.994307 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6723 01:01:07.997788 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6724 01:01:07.998379 == TX Byte 1 ==
6725 01:01:08.004380 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6726 01:01:08.007687 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6727 01:01:08.008233
6728 01:01:08.008611 [DATLAT]
6729 01:01:08.011169 Freq=400, CH1 RK1
6730 01:01:08.011635
6731 01:01:08.011978 DATLAT Default: 0xd
6732 01:01:08.014124 0, 0xFFFF, sum = 0
6733 01:01:08.014600 1, 0xFFFF, sum = 0
6734 01:01:08.018001 2, 0xFFFF, sum = 0
6735 01:01:08.018636 3, 0xFFFF, sum = 0
6736 01:01:08.020872 4, 0xFFFF, sum = 0
6737 01:01:08.021395 5, 0xFFFF, sum = 0
6738 01:01:08.024203 6, 0xFFFF, sum = 0
6739 01:01:08.024646 7, 0xFFFF, sum = 0
6740 01:01:08.027704 8, 0xFFFF, sum = 0
6741 01:01:08.028237 9, 0xFFFF, sum = 0
6742 01:01:08.030853 10, 0xFFFF, sum = 0
6743 01:01:08.031297 11, 0xFFFF, sum = 0
6744 01:01:08.034572 12, 0x0, sum = 1
6745 01:01:08.035095 13, 0x0, sum = 2
6746 01:01:08.037789 14, 0x0, sum = 3
6747 01:01:08.038365 15, 0x0, sum = 4
6748 01:01:08.041218 best_step = 13
6749 01:01:08.041739
6750 01:01:08.042080 ==
6751 01:01:08.044195 Dram Type= 6, Freq= 0, CH_1, rank 1
6752 01:01:08.047384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6753 01:01:08.047821 ==
6754 01:01:08.050765 RX Vref Scan: 0
6755 01:01:08.051199
6756 01:01:08.051537 RX Vref 0 -> 0, step: 1
6757 01:01:08.051857
6758 01:01:08.054134 RX Delay -359 -> 252, step: 8
6759 01:01:08.062370 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6760 01:01:08.065941 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6761 01:01:08.069142 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6762 01:01:08.072471 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6763 01:01:08.078617 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6764 01:01:08.082305 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6765 01:01:08.085301 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6766 01:01:08.088993 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6767 01:01:08.095514 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6768 01:01:08.098680 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6769 01:01:08.101822 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6770 01:01:08.108461 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6771 01:01:08.111838 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6772 01:01:08.115497 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6773 01:01:08.118665 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6774 01:01:08.124899 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6775 01:01:08.125335 ==
6776 01:01:08.128551 Dram Type= 6, Freq= 0, CH_1, rank 1
6777 01:01:08.132089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6778 01:01:08.132606 ==
6779 01:01:08.132958 DQS Delay:
6780 01:01:08.135213 DQS0 = 44, DQS1 = 64
6781 01:01:08.135652 DQM Delay:
6782 01:01:08.138844 DQM0 = 5, DQM1 = 15
6783 01:01:08.139367 DQ Delay:
6784 01:01:08.142288 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6785 01:01:08.145123 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =0
6786 01:01:08.148347 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6787 01:01:08.151625 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6788 01:01:08.152059
6789 01:01:08.152399
6790 01:01:08.158462 [DQSOSCAuto] RK1, (LSB)MR18= 0xb7b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6791 01:01:08.161632 CH1 RK1: MR19=C0C, MR18=B7B7
6792 01:01:08.168417 CH1_RK1: MR19=0xC0C, MR18=0xB7B7, DQSOSC=387, MR23=63, INC=394, DEC=262
6793 01:01:08.171529 [RxdqsGatingPostProcess] freq 400
6794 01:01:08.178356 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6795 01:01:08.178669 Pre-setting of DQS Precalculation
6796 01:01:08.184775 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6797 01:01:08.191199 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6798 01:01:08.197974 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6799 01:01:08.198107
6800 01:01:08.198217
6801 01:01:08.200950 [Calibration Summary] 800 Mbps
6802 01:01:08.204368 CH 0, Rank 0
6803 01:01:08.204481 SW Impedance : PASS
6804 01:01:08.207779 DUTY Scan : NO K
6805 01:01:08.210922 ZQ Calibration : PASS
6806 01:01:08.211012 Jitter Meter : NO K
6807 01:01:08.214232 CBT Training : PASS
6808 01:01:08.214324 Write leveling : PASS
6809 01:01:08.217586 RX DQS gating : PASS
6810 01:01:08.221141 RX DQ/DQS(RDDQC) : PASS
6811 01:01:08.221222 TX DQ/DQS : PASS
6812 01:01:08.224266 RX DATLAT : PASS
6813 01:01:08.227548 RX DQ/DQS(Engine): PASS
6814 01:01:08.227626 TX OE : NO K
6815 01:01:08.230785 All Pass.
6816 01:01:08.230863
6817 01:01:08.230924 CH 0, Rank 1
6818 01:01:08.234181 SW Impedance : PASS
6819 01:01:08.234298 DUTY Scan : NO K
6820 01:01:08.237373 ZQ Calibration : PASS
6821 01:01:08.240764 Jitter Meter : NO K
6822 01:01:08.240843 CBT Training : PASS
6823 01:01:08.244100 Write leveling : NO K
6824 01:01:08.247362 RX DQS gating : PASS
6825 01:01:08.247440 RX DQ/DQS(RDDQC) : PASS
6826 01:01:08.250781 TX DQ/DQS : PASS
6827 01:01:08.253970 RX DATLAT : PASS
6828 01:01:08.254048 RX DQ/DQS(Engine): PASS
6829 01:01:08.257377 TX OE : NO K
6830 01:01:08.257456 All Pass.
6831 01:01:08.257516
6832 01:01:08.260721 CH 1, Rank 0
6833 01:01:08.260799 SW Impedance : PASS
6834 01:01:08.263826 DUTY Scan : NO K
6835 01:01:08.267225 ZQ Calibration : PASS
6836 01:01:08.267303 Jitter Meter : NO K
6837 01:01:08.270589 CBT Training : PASS
6838 01:01:08.270667 Write leveling : PASS
6839 01:01:08.273964 RX DQS gating : PASS
6840 01:01:08.277244 RX DQ/DQS(RDDQC) : PASS
6841 01:01:08.277322 TX DQ/DQS : PASS
6842 01:01:08.280743 RX DATLAT : PASS
6843 01:01:08.283679 RX DQ/DQS(Engine): PASS
6844 01:01:08.283757 TX OE : NO K
6845 01:01:08.287048 All Pass.
6846 01:01:08.287127
6847 01:01:08.287187 CH 1, Rank 1
6848 01:01:08.290414 SW Impedance : PASS
6849 01:01:08.290493 DUTY Scan : NO K
6850 01:01:08.293683 ZQ Calibration : PASS
6851 01:01:08.296941 Jitter Meter : NO K
6852 01:01:08.297019 CBT Training : PASS
6853 01:01:08.300338 Write leveling : NO K
6854 01:01:08.303661 RX DQS gating : PASS
6855 01:01:08.303739 RX DQ/DQS(RDDQC) : PASS
6856 01:01:08.307139 TX DQ/DQS : PASS
6857 01:01:08.310386 RX DATLAT : PASS
6858 01:01:08.310464 RX DQ/DQS(Engine): PASS
6859 01:01:08.313479 TX OE : NO K
6860 01:01:08.313558 All Pass.
6861 01:01:08.313619
6862 01:01:08.316885 DramC Write-DBI off
6863 01:01:08.320175 PER_BANK_REFRESH: Hybrid Mode
6864 01:01:08.320253 TX_TRACKING: ON
6865 01:01:08.330055 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6866 01:01:08.333367 [FAST_K] Save calibration result to emmc
6867 01:01:08.336715 dramc_set_vcore_voltage set vcore to 725000
6868 01:01:08.339937 Read voltage for 1600, 0
6869 01:01:08.340017 Vio18 = 0
6870 01:01:08.340077 Vcore = 725000
6871 01:01:08.343282 Vdram = 0
6872 01:01:08.343359 Vddq = 0
6873 01:01:08.343419 Vmddr = 0
6874 01:01:08.349969 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6875 01:01:08.353245 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6876 01:01:08.356575 MEM_TYPE=3, freq_sel=13
6877 01:01:08.359934 sv_algorithm_assistance_LP4_3733
6878 01:01:08.363137 ============ PULL DRAM RESETB DOWN ============
6879 01:01:08.366365 ========== PULL DRAM RESETB DOWN end =========
6880 01:01:08.373449 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6881 01:01:08.376731 ===================================
6882 01:01:08.379659 LPDDR4 DRAM CONFIGURATION
6883 01:01:08.383136 ===================================
6884 01:01:08.383214 EX_ROW_EN[0] = 0x0
6885 01:01:08.386369 EX_ROW_EN[1] = 0x0
6886 01:01:08.386446 LP4Y_EN = 0x0
6887 01:01:08.389683 WORK_FSP = 0x1
6888 01:01:08.389762 WL = 0x5
6889 01:01:08.393202 RL = 0x5
6890 01:01:08.393279 BL = 0x2
6891 01:01:08.396310 RPST = 0x0
6892 01:01:08.396386 RD_PRE = 0x0
6893 01:01:08.399752 WR_PRE = 0x1
6894 01:01:08.399830 WR_PST = 0x1
6895 01:01:08.403213 DBI_WR = 0x0
6896 01:01:08.403290 DBI_RD = 0x0
6897 01:01:08.406162 OTF = 0x1
6898 01:01:08.409709 ===================================
6899 01:01:08.412944 ===================================
6900 01:01:08.413022 ANA top config
6901 01:01:08.416201 ===================================
6902 01:01:08.419431 DLL_ASYNC_EN = 0
6903 01:01:08.422699 ALL_SLAVE_EN = 0
6904 01:01:08.426020 NEW_RANK_MODE = 1
6905 01:01:08.426099 DLL_IDLE_MODE = 1
6906 01:01:08.429389 LP45_APHY_COMB_EN = 1
6907 01:01:08.432649 TX_ODT_DIS = 0
6908 01:01:08.435827 NEW_8X_MODE = 1
6909 01:01:08.439250 ===================================
6910 01:01:08.442810 ===================================
6911 01:01:08.446004 data_rate = 3200
6912 01:01:08.449182 CKR = 1
6913 01:01:08.449261 DQ_P2S_RATIO = 8
6914 01:01:08.452511 ===================================
6915 01:01:08.456065 CA_P2S_RATIO = 8
6916 01:01:08.459085 DQ_CA_OPEN = 0
6917 01:01:08.462347 DQ_SEMI_OPEN = 0
6918 01:01:08.466171 CA_SEMI_OPEN = 0
6919 01:01:08.469038 CA_FULL_RATE = 0
6920 01:01:08.469122 DQ_CKDIV4_EN = 0
6921 01:01:08.472448 CA_CKDIV4_EN = 0
6922 01:01:08.475833 CA_PREDIV_EN = 0
6923 01:01:08.479164 PH8_DLY = 12
6924 01:01:08.482196 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6925 01:01:08.485665 DQ_AAMCK_DIV = 4
6926 01:01:08.485744 CA_AAMCK_DIV = 4
6927 01:01:08.488978 CA_ADMCK_DIV = 4
6928 01:01:08.492139 DQ_TRACK_CA_EN = 0
6929 01:01:08.495540 CA_PICK = 1600
6930 01:01:08.498924 CA_MCKIO = 1600
6931 01:01:08.502562 MCKIO_SEMI = 0
6932 01:01:08.505530 PLL_FREQ = 3068
6933 01:01:08.505629 DQ_UI_PI_RATIO = 32
6934 01:01:08.508794 CA_UI_PI_RATIO = 0
6935 01:01:08.512139 ===================================
6936 01:01:08.515496 ===================================
6937 01:01:08.519015 memory_type:LPDDR4
6938 01:01:08.522101 GP_NUM : 10
6939 01:01:08.522179 SRAM_EN : 1
6940 01:01:08.525333 MD32_EN : 0
6941 01:01:08.528582 ===================================
6942 01:01:08.532169 [ANA_INIT] >>>>>>>>>>>>>>
6943 01:01:08.532247 <<<<<< [CONFIGURE PHASE]: ANA_TX
6944 01:01:08.538641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6945 01:01:08.541998 ===================================
6946 01:01:08.542077 data_rate = 3200,PCW = 0X7600
6947 01:01:08.545127 ===================================
6948 01:01:08.548525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6949 01:01:08.555493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6950 01:01:08.561887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6951 01:01:08.565139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6952 01:01:08.568414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6953 01:01:08.571773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6954 01:01:08.575121 [ANA_INIT] flow start
6955 01:01:08.575198 [ANA_INIT] PLL >>>>>>>>
6956 01:01:08.578589 [ANA_INIT] PLL <<<<<<<<
6957 01:01:08.581965 [ANA_INIT] MIDPI >>>>>>>>
6958 01:01:08.584962 [ANA_INIT] MIDPI <<<<<<<<
6959 01:01:08.585041 [ANA_INIT] DLL >>>>>>>>
6960 01:01:08.588542 [ANA_INIT] DLL <<<<<<<<
6961 01:01:08.588621 [ANA_INIT] flow end
6962 01:01:08.595102 ============ LP4 DIFF to SE enter ============
6963 01:01:08.598219 ============ LP4 DIFF to SE exit ============
6964 01:01:08.601628 [ANA_INIT] <<<<<<<<<<<<<
6965 01:01:08.604819 [Flow] Enable top DCM control >>>>>
6966 01:01:08.608286 [Flow] Enable top DCM control <<<<<
6967 01:01:08.611448 Enable DLL master slave shuffle
6968 01:01:08.614813 ==============================================================
6969 01:01:08.618129 Gating Mode config
6970 01:01:08.621446 ==============================================================
6971 01:01:08.624669 Config description:
6972 01:01:08.634546 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6973 01:01:08.641259 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6974 01:01:08.644564 SELPH_MODE 0: By rank 1: By Phase
6975 01:01:08.651229 ==============================================================
6976 01:01:08.654553 GAT_TRACK_EN = 1
6977 01:01:08.657908 RX_GATING_MODE = 2
6978 01:01:08.661338 RX_GATING_TRACK_MODE = 2
6979 01:01:08.664629 SELPH_MODE = 1
6980 01:01:08.667672 PICG_EARLY_EN = 1
6981 01:01:08.667751 VALID_LAT_VALUE = 1
6982 01:01:08.674465 ==============================================================
6983 01:01:08.677875 Enter into Gating configuration >>>>
6984 01:01:08.681014 Exit from Gating configuration <<<<
6985 01:01:08.684321 Enter into DVFS_PRE_config >>>>>
6986 01:01:08.694452 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6987 01:01:08.697737 Exit from DVFS_PRE_config <<<<<
6988 01:01:08.701040 Enter into PICG configuration >>>>
6989 01:01:08.704544 Exit from PICG configuration <<<<
6990 01:01:08.707657 [RX_INPUT] configuration >>>>>
6991 01:01:08.710908 [RX_INPUT] configuration <<<<<
6992 01:01:08.717524 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6993 01:01:08.720937 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6994 01:01:08.727548 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6995 01:01:08.734167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6996 01:01:08.740947 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6997 01:01:08.747419 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6998 01:01:08.750924 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6999 01:01:08.753940 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7000 01:01:08.757340 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7001 01:01:08.763733 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7002 01:01:08.767259 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7003 01:01:08.770467 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7004 01:01:08.773832 ===================================
7005 01:01:08.777321 LPDDR4 DRAM CONFIGURATION
7006 01:01:08.780492 ===================================
7007 01:01:08.780570 EX_ROW_EN[0] = 0x0
7008 01:01:08.783882 EX_ROW_EN[1] = 0x0
7009 01:01:08.786952 LP4Y_EN = 0x0
7010 01:01:08.787030 WORK_FSP = 0x1
7011 01:01:08.790513 WL = 0x5
7012 01:01:08.790591 RL = 0x5
7013 01:01:08.793504 BL = 0x2
7014 01:01:08.793583 RPST = 0x0
7015 01:01:08.796835 RD_PRE = 0x0
7016 01:01:08.796914 WR_PRE = 0x1
7017 01:01:08.800466 WR_PST = 0x1
7018 01:01:08.800544 DBI_WR = 0x0
7019 01:01:08.803473 DBI_RD = 0x0
7020 01:01:08.803552 OTF = 0x1
7021 01:01:08.806744 ===================================
7022 01:01:08.810426 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7023 01:01:08.816805 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7024 01:01:08.819996 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7025 01:01:08.823406 ===================================
7026 01:01:08.826905 LPDDR4 DRAM CONFIGURATION
7027 01:01:08.830080 ===================================
7028 01:01:08.830159 EX_ROW_EN[0] = 0x10
7029 01:01:08.833237 EX_ROW_EN[1] = 0x0
7030 01:01:08.836742 LP4Y_EN = 0x0
7031 01:01:08.836820 WORK_FSP = 0x1
7032 01:01:08.839993 WL = 0x5
7033 01:01:08.840070 RL = 0x5
7034 01:01:08.843135 BL = 0x2
7035 01:01:08.843212 RPST = 0x0
7036 01:01:08.846469 RD_PRE = 0x0
7037 01:01:08.846548 WR_PRE = 0x1
7038 01:01:08.849824 WR_PST = 0x1
7039 01:01:08.849901 DBI_WR = 0x0
7040 01:01:08.853080 DBI_RD = 0x0
7041 01:01:08.853158 OTF = 0x1
7042 01:01:08.856140 ===================================
7043 01:01:08.862885 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7044 01:01:08.862964 ==
7045 01:01:08.866424 Dram Type= 6, Freq= 0, CH_0, rank 0
7046 01:01:08.869605 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7047 01:01:08.872894 ==
7048 01:01:08.872972 [Duty_Offset_Calibration]
7049 01:01:08.876361 B0:0 B1:2 CA:1
7050 01:01:08.876438
7051 01:01:08.879506 [DutyScan_Calibration_Flow] k_type=0
7052 01:01:08.888666
7053 01:01:08.888752 ==CLK 0==
7054 01:01:08.891564 Final CLK duty delay cell = 0
7055 01:01:08.894952 [0] MAX Duty = 5156%(X100), DQS PI = 22
7056 01:01:08.898365 [0] MIN Duty = 4938%(X100), DQS PI = 54
7057 01:01:08.901568 [0] AVG Duty = 5047%(X100)
7058 01:01:08.901646
7059 01:01:08.904987 CH0 CLK Duty spec in!! Max-Min= 218%
7060 01:01:08.908247 [DutyScan_Calibration_Flow] ====Done====
7061 01:01:08.908325
7062 01:01:08.911518 [DutyScan_Calibration_Flow] k_type=1
7063 01:01:08.928409
7064 01:01:08.928496 ==DQS 0 ==
7065 01:01:08.931598 Final DQS duty delay cell = 0
7066 01:01:08.934948 [0] MAX Duty = 5125%(X100), DQS PI = 2
7067 01:01:08.938459 [0] MIN Duty = 5031%(X100), DQS PI = 8
7068 01:01:08.938538 [0] AVG Duty = 5078%(X100)
7069 01:01:08.941621
7070 01:01:08.941698 ==DQS 1 ==
7071 01:01:08.944993 Final DQS duty delay cell = 0
7072 01:01:08.948316 [0] MAX Duty = 5031%(X100), DQS PI = 46
7073 01:01:08.951678 [0] MIN Duty = 4876%(X100), DQS PI = 16
7074 01:01:08.954929 [0] AVG Duty = 4953%(X100)
7075 01:01:08.955007
7076 01:01:08.958505 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7077 01:01:08.958583
7078 01:01:08.961615 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7079 01:01:08.964900 [DutyScan_Calibration_Flow] ====Done====
7080 01:01:08.964979
7081 01:01:08.968076 [DutyScan_Calibration_Flow] k_type=3
7082 01:01:08.985603
7083 01:01:08.985697 ==DQM 0 ==
7084 01:01:08.988671 Final DQM duty delay cell = 0
7085 01:01:08.992044 [0] MAX Duty = 5187%(X100), DQS PI = 22
7086 01:01:08.995356 [0] MIN Duty = 4876%(X100), DQS PI = 56
7087 01:01:08.998745 [0] AVG Duty = 5031%(X100)
7088 01:01:08.998824
7089 01:01:08.998884 ==DQM 1 ==
7090 01:01:09.001972 Final DQM duty delay cell = 0
7091 01:01:09.005239 [0] MAX Duty = 5031%(X100), DQS PI = 52
7092 01:01:09.008466 [0] MIN Duty = 4782%(X100), DQS PI = 12
7093 01:01:09.012108 [0] AVG Duty = 4906%(X100)
7094 01:01:09.012187
7095 01:01:09.015333 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7096 01:01:09.015411
7097 01:01:09.018254 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7098 01:01:09.021684 [DutyScan_Calibration_Flow] ====Done====
7099 01:01:09.021766
7100 01:01:09.025005 [DutyScan_Calibration_Flow] k_type=2
7101 01:01:09.042091
7102 01:01:09.042186 ==DQ 0 ==
7103 01:01:09.045079 Final DQ duty delay cell = 0
7104 01:01:09.048496 [0] MAX Duty = 5218%(X100), DQS PI = 20
7105 01:01:09.051631 [0] MIN Duty = 4938%(X100), DQS PI = 56
7106 01:01:09.051708 [0] AVG Duty = 5078%(X100)
7107 01:01:09.055052
7108 01:01:09.055129 ==DQ 1 ==
7109 01:01:09.058413 Final DQ duty delay cell = -4
7110 01:01:09.061773 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7111 01:01:09.065176 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7112 01:01:09.068324 [-4] AVG Duty = 4953%(X100)
7113 01:01:09.068402
7114 01:01:09.071699 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7115 01:01:09.071777
7116 01:01:09.075125 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7117 01:01:09.078341 [DutyScan_Calibration_Flow] ====Done====
7118 01:01:09.078419 ==
7119 01:01:09.081881 Dram Type= 6, Freq= 0, CH_1, rank 0
7120 01:01:09.085139 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7121 01:01:09.085218 ==
7122 01:01:09.088235 [Duty_Offset_Calibration]
7123 01:01:09.088312 B0:0 B1:5 CA:-5
7124 01:01:09.088372
7125 01:01:09.091360 [DutyScan_Calibration_Flow] k_type=0
7126 01:01:09.102372
7127 01:01:09.102457 ==CLK 0==
7128 01:01:09.105732 Final CLK duty delay cell = 0
7129 01:01:09.109166 [0] MAX Duty = 5156%(X100), DQS PI = 22
7130 01:01:09.112402 [0] MIN Duty = 4906%(X100), DQS PI = 50
7131 01:01:09.112481 [0] AVG Duty = 5031%(X100)
7132 01:01:09.115793
7133 01:01:09.119160 CH1 CLK Duty spec in!! Max-Min= 250%
7134 01:01:09.122560 [DutyScan_Calibration_Flow] ====Done====
7135 01:01:09.122643
7136 01:01:09.125802 [DutyScan_Calibration_Flow] k_type=1
7137 01:01:09.141393
7138 01:01:09.141487 ==DQS 0 ==
7139 01:01:09.144703 Final DQS duty delay cell = 0
7140 01:01:09.147952 [0] MAX Duty = 5187%(X100), DQS PI = 20
7141 01:01:09.151299 [0] MIN Duty = 4876%(X100), DQS PI = 42
7142 01:01:09.154620 [0] AVG Duty = 5031%(X100)
7143 01:01:09.154698
7144 01:01:09.154760 ==DQS 1 ==
7145 01:01:09.157790 Final DQS duty delay cell = -4
7146 01:01:09.161180 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7147 01:01:09.164464 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7148 01:01:09.167946 [-4] AVG Duty = 4922%(X100)
7149 01:01:09.168025
7150 01:01:09.171150 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7151 01:01:09.171227
7152 01:01:09.174441 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7153 01:01:09.177733 [DutyScan_Calibration_Flow] ====Done====
7154 01:01:09.177810
7155 01:01:09.181344 [DutyScan_Calibration_Flow] k_type=3
7156 01:01:09.197110
7157 01:01:09.197205 ==DQM 0 ==
7158 01:01:09.200555 Final DQM duty delay cell = -4
7159 01:01:09.203573 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7160 01:01:09.207102 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7161 01:01:09.210189 [-4] AVG Duty = 4937%(X100)
7162 01:01:09.210307
7163 01:01:09.210369 ==DQM 1 ==
7164 01:01:09.213462 Final DQM duty delay cell = -4
7165 01:01:09.216779 [-4] MAX Duty = 5031%(X100), DQS PI = 0
7166 01:01:09.220045 [-4] MIN Duty = 4876%(X100), DQS PI = 40
7167 01:01:09.223550 [-4] AVG Duty = 4953%(X100)
7168 01:01:09.223668
7169 01:01:09.226684 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7170 01:01:09.226763
7171 01:01:09.230044 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7172 01:01:09.233421 [DutyScan_Calibration_Flow] ====Done====
7173 01:01:09.233500
7174 01:01:09.236711 [DutyScan_Calibration_Flow] k_type=2
7175 01:01:09.254757
7176 01:01:09.254838 ==DQ 0 ==
7177 01:01:09.257837 Final DQ duty delay cell = 0
7178 01:01:09.261141 [0] MAX Duty = 5093%(X100), DQS PI = 34
7179 01:01:09.264344 [0] MIN Duty = 4938%(X100), DQS PI = 46
7180 01:01:09.267694 [0] AVG Duty = 5015%(X100)
7181 01:01:09.267771
7182 01:01:09.267832 ==DQ 1 ==
7183 01:01:09.270931 Final DQ duty delay cell = 0
7184 01:01:09.274563 [0] MAX Duty = 5062%(X100), DQS PI = 6
7185 01:01:09.277591 [0] MIN Duty = 4876%(X100), DQS PI = 26
7186 01:01:09.277670 [0] AVG Duty = 4969%(X100)
7187 01:01:09.280949
7188 01:01:09.284227 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7189 01:01:09.284305
7190 01:01:09.287565 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7191 01:01:09.290907 [DutyScan_Calibration_Flow] ====Done====
7192 01:01:09.294459 nWR fixed to 30
7193 01:01:09.294538 [ModeRegInit_LP4] CH0 RK0
7194 01:01:09.297554 [ModeRegInit_LP4] CH0 RK1
7195 01:01:09.300812 [ModeRegInit_LP4] CH1 RK0
7196 01:01:09.304075 [ModeRegInit_LP4] CH1 RK1
7197 01:01:09.304153 match AC timing 4
7198 01:01:09.310674 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7199 01:01:09.313900 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7200 01:01:09.317185 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7201 01:01:09.323783 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7202 01:01:09.327105 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7203 01:01:09.327183 [MiockJmeterHQA]
7204 01:01:09.327244
7205 01:01:09.330680 [DramcMiockJmeter] u1RxGatingPI = 0
7206 01:01:09.333742 0 : 4257, 4029
7207 01:01:09.333820 4 : 4252, 4027
7208 01:01:09.337092 8 : 4371, 4140
7209 01:01:09.337170 12 : 4368, 4140
7210 01:01:09.340431 16 : 4367, 4139
7211 01:01:09.340509 20 : 4255, 4029
7212 01:01:09.340570 24 : 4252, 4027
7213 01:01:09.343708 28 : 4253, 4026
7214 01:01:09.343786 32 : 4257, 4029
7215 01:01:09.347052 36 : 4259, 4031
7216 01:01:09.347131 40 : 4365, 4137
7217 01:01:09.350522 44 : 4255, 4030
7218 01:01:09.350600 48 : 4253, 4027
7219 01:01:09.350663 52 : 4252, 4027
7220 01:01:09.353666 56 : 4254, 4029
7221 01:01:09.353743 60 : 4250, 4027
7222 01:01:09.357407 64 : 4250, 4027
7223 01:01:09.357484 68 : 4363, 4140
7224 01:01:09.360304 72 : 4250, 4027
7225 01:01:09.360382 76 : 4252, 4029
7226 01:01:09.363773 80 : 4250, 4027
7227 01:01:09.363852 84 : 4360, 4138
7228 01:01:09.363915 88 : 4250, 4027
7229 01:01:09.367017 92 : 4361, 4137
7230 01:01:09.367095 96 : 4249, 4027
7231 01:01:09.370468 100 : 4250, 1668
7232 01:01:09.370585 104 : 4361, 0
7233 01:01:09.373725 108 : 4363, 0
7234 01:01:09.373803 112 : 4249, 0
7235 01:01:09.373864 116 : 4250, 0
7236 01:01:09.377081 120 : 4250, 0
7237 01:01:09.377159 124 : 4252, 0
7238 01:01:09.380250 128 : 4250, 0
7239 01:01:09.380328 132 : 4250, 0
7240 01:01:09.380389 136 : 4252, 0
7241 01:01:09.383577 140 : 4360, 0
7242 01:01:09.383655 144 : 4250, 0
7243 01:01:09.383716 148 : 4250, 0
7244 01:01:09.386966 152 : 4249, 0
7245 01:01:09.387045 156 : 4361, 0
7246 01:01:09.390508 160 : 4360, 0
7247 01:01:09.390587 164 : 4250, 0
7248 01:01:09.390650 168 : 4250, 0
7249 01:01:09.393644 172 : 4250, 0
7250 01:01:09.393723 176 : 4252, 0
7251 01:01:09.397088 180 : 4250, 0
7252 01:01:09.397166 184 : 4250, 0
7253 01:01:09.397227 188 : 4252, 0
7254 01:01:09.400302 192 : 4250, 0
7255 01:01:09.400380 196 : 4250, 0
7256 01:01:09.403297 200 : 4252, 0
7257 01:01:09.403375 204 : 4360, 0
7258 01:01:09.403436 208 : 4361, 0
7259 01:01:09.406749 212 : 4250, 0
7260 01:01:09.406827 216 : 4250, 0
7261 01:01:09.409943 220 : 4360, 519
7262 01:01:09.410021 224 : 4250, 3969
7263 01:01:09.413190 228 : 4360, 4137
7264 01:01:09.413267 232 : 4252, 4030
7265 01:01:09.413327 236 : 4250, 4027
7266 01:01:09.416807 240 : 4249, 4027
7267 01:01:09.416885 244 : 4361, 4137
7268 01:01:09.419877 248 : 4250, 4027
7269 01:01:09.419955 252 : 4250, 4027
7270 01:01:09.423418 256 : 4250, 4027
7271 01:01:09.423495 260 : 4252, 4029
7272 01:01:09.426455 264 : 4250, 4027
7273 01:01:09.426537 268 : 4361, 4137
7274 01:01:09.429780 272 : 4360, 4138
7275 01:01:09.429859 276 : 4250, 4027
7276 01:01:09.433145 280 : 4363, 4140
7277 01:01:09.433224 284 : 4250, 4027
7278 01:01:09.436481 288 : 4250, 4027
7279 01:01:09.436559 292 : 4250, 4027
7280 01:01:09.436620 296 : 4252, 4029
7281 01:01:09.439666 300 : 4250, 4027
7282 01:01:09.439758 304 : 4250, 4027
7283 01:01:09.443090 308 : 4249, 4027
7284 01:01:09.443169 312 : 4252, 4029
7285 01:01:09.446272 316 : 4250, 4027
7286 01:01:09.446350 320 : 4361, 4137
7287 01:01:09.449869 324 : 4360, 4138
7288 01:01:09.449950 328 : 4250, 4027
7289 01:01:09.453219 332 : 4363, 4140
7290 01:01:09.453298 336 : 4250, 3752
7291 01:01:09.456255 340 : 4250, 1747
7292 01:01:09.456335
7293 01:01:09.456396 MIOCK jitter meter ch=0
7294 01:01:09.456452
7295 01:01:09.459550 1T = (340-100) = 240 dly cells
7296 01:01:09.466257 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7297 01:01:09.466336 ==
7298 01:01:09.469514 Dram Type= 6, Freq= 0, CH_0, rank 0
7299 01:01:09.472892 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7300 01:01:09.472970 ==
7301 01:01:09.479433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7302 01:01:09.483037 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7303 01:01:09.486122 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7304 01:01:09.492622 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7305 01:01:09.501673 [CA 0] Center 41 (11~72) winsize 62
7306 01:01:09.504991 [CA 1] Center 41 (11~72) winsize 62
7307 01:01:09.508500 [CA 2] Center 37 (7~67) winsize 61
7308 01:01:09.511753 [CA 3] Center 37 (7~67) winsize 61
7309 01:01:09.514991 [CA 4] Center 35 (5~66) winsize 62
7310 01:01:09.518643 [CA 5] Center 35 (5~65) winsize 61
7311 01:01:09.518746
7312 01:01:09.521506 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7313 01:01:09.521583
7314 01:01:09.524991 [CATrainingPosCal] consider 1 rank data
7315 01:01:09.528391 u2DelayCellTimex100 = 271/100 ps
7316 01:01:09.531778 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7317 01:01:09.538275 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7318 01:01:09.541504 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7319 01:01:09.544877 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7320 01:01:09.548225 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7321 01:01:09.551570 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7322 01:01:09.551648
7323 01:01:09.554749 CA PerBit enable=1, Macro0, CA PI delay=35
7324 01:01:09.554827
7325 01:01:09.558113 [CBTSetCACLKResult] CA Dly = 35
7326 01:01:09.561528 CS Dly: 11 (0~42)
7327 01:01:09.564696 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7328 01:01:09.567963 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7329 01:01:09.568041 ==
7330 01:01:09.571329 Dram Type= 6, Freq= 0, CH_0, rank 1
7331 01:01:09.574548 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7332 01:01:09.578246 ==
7333 01:01:09.581435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7334 01:01:09.584577 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7335 01:01:09.591130 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7336 01:01:09.597793 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7337 01:01:09.604420 [CA 0] Center 42 (12~73) winsize 62
7338 01:01:09.607711 [CA 1] Center 42 (12~73) winsize 62
7339 01:01:09.610960 [CA 2] Center 38 (9~68) winsize 60
7340 01:01:09.614282 [CA 3] Center 38 (8~68) winsize 61
7341 01:01:09.617729 [CA 4] Center 36 (6~66) winsize 61
7342 01:01:09.620971 [CA 5] Center 36 (6~66) winsize 61
7343 01:01:09.621049
7344 01:01:09.624487 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7345 01:01:09.624566
7346 01:01:09.627556 [CATrainingPosCal] consider 2 rank data
7347 01:01:09.630808 u2DelayCellTimex100 = 271/100 ps
7348 01:01:09.634169 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7349 01:01:09.640725 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7350 01:01:09.644061 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7351 01:01:09.647527 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7352 01:01:09.650717 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7353 01:01:09.653908 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7354 01:01:09.653986
7355 01:01:09.657487 CA PerBit enable=1, Macro0, CA PI delay=35
7356 01:01:09.657567
7357 01:01:09.660583 [CBTSetCACLKResult] CA Dly = 35
7358 01:01:09.663918 CS Dly: 11 (0~42)
7359 01:01:09.667284 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7360 01:01:09.670563 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7361 01:01:09.670642
7362 01:01:09.673950 ----->DramcWriteLeveling(PI) begin...
7363 01:01:09.674029 ==
7364 01:01:09.677236 Dram Type= 6, Freq= 0, CH_0, rank 0
7365 01:01:09.683854 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7366 01:01:09.683959 ==
7367 01:01:09.687081 Write leveling (Byte 0): 29 => 29
7368 01:01:09.690474 Write leveling (Byte 1): 23 => 23
7369 01:01:09.690551 DramcWriteLeveling(PI) end<-----
7370 01:01:09.690611
7371 01:01:09.693762 ==
7372 01:01:09.697067 Dram Type= 6, Freq= 0, CH_0, rank 0
7373 01:01:09.700586 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7374 01:01:09.700658 ==
7375 01:01:09.703850 [Gating] SW mode calibration
7376 01:01:09.710346 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7377 01:01:09.713843 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7378 01:01:09.720096 0 12 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7379 01:01:09.723392 0 12 4 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
7380 01:01:09.726807 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7381 01:01:09.733435 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7382 01:01:09.736875 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7383 01:01:09.740098 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7384 01:01:09.746632 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7385 01:01:09.750017 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7386 01:01:09.753320 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
7387 01:01:09.760024 0 13 4 | B1->B0 | 3232 2424 | 0 0 | (1 0) (1 0)
7388 01:01:09.763407 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7389 01:01:09.766734 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7390 01:01:09.773389 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7391 01:01:09.776562 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7392 01:01:09.780126 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7393 01:01:09.786447 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7394 01:01:09.790026 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
7395 01:01:09.793232 0 14 4 | B1->B0 | 3a39 4646 | 1 0 | (0 0) (0 0)
7396 01:01:09.799810 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7397 01:01:09.803032 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7398 01:01:09.806332 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7399 01:01:09.813117 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7400 01:01:09.816227 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7401 01:01:09.819671 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7402 01:01:09.826382 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7403 01:01:09.829710 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7404 01:01:09.832815 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7405 01:01:09.839462 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 01:01:09.843033 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 01:01:09.846014 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 01:01:09.852788 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 01:01:09.855948 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 01:01:09.859362 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 01:01:09.862592 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 01:01:09.869249 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 01:01:09.872631 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 01:01:09.876165 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 01:01:09.882901 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 01:01:09.886031 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 01:01:09.889216 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 01:01:09.895753 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7419 01:01:09.899097 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7420 01:01:09.902570 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7421 01:01:09.905818 Total UI for P1: 0, mck2ui 16
7422 01:01:09.909267 best dqsien dly found for B0: ( 1, 1, 2)
7423 01:01:09.912791 Total UI for P1: 0, mck2ui 16
7424 01:01:09.915737 best dqsien dly found for B1: ( 1, 1, 4)
7425 01:01:09.918920 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7426 01:01:09.922568 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7427 01:01:09.922646
7428 01:01:09.929156 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7429 01:01:09.932326 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7430 01:01:09.932406 [Gating] SW calibration Done
7431 01:01:09.935631 ==
7432 01:01:09.939089 Dram Type= 6, Freq= 0, CH_0, rank 0
7433 01:01:09.942139 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7434 01:01:09.942223 ==
7435 01:01:09.942318 RX Vref Scan: 0
7436 01:01:09.942374
7437 01:01:09.945660 RX Vref 0 -> 0, step: 1
7438 01:01:09.945737
7439 01:01:09.948948 RX Delay 0 -> 252, step: 8
7440 01:01:09.951935 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7441 01:01:09.955386 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7442 01:01:09.958611 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7443 01:01:09.965250 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7444 01:01:09.968920 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7445 01:01:09.971990 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7446 01:01:09.975417 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7447 01:01:09.978346 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7448 01:01:09.985107 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7449 01:01:09.988609 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7450 01:01:09.991681 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7451 01:01:09.995035 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7452 01:01:09.998481 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7453 01:01:10.005209 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7454 01:01:10.008586 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7455 01:01:10.011505 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7456 01:01:10.011594 ==
7457 01:01:10.014961 Dram Type= 6, Freq= 0, CH_0, rank 0
7458 01:01:10.018208 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7459 01:01:10.021562 ==
7460 01:01:10.021638 DQS Delay:
7461 01:01:10.021698 DQS0 = 0, DQS1 = 0
7462 01:01:10.024934 DQM Delay:
7463 01:01:10.025011 DQM0 = 130, DQM1 = 123
7464 01:01:10.028127 DQ Delay:
7465 01:01:10.031474 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7466 01:01:10.035092 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7467 01:01:10.038374 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7468 01:01:10.041525 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7469 01:01:10.041602
7470 01:01:10.041662
7471 01:01:10.041718 ==
7472 01:01:10.044842 Dram Type= 6, Freq= 0, CH_0, rank 0
7473 01:01:10.048298 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7474 01:01:10.048377 ==
7475 01:01:10.048437
7476 01:01:10.051592
7477 01:01:10.051669 TX Vref Scan disable
7478 01:01:10.054754 == TX Byte 0 ==
7479 01:01:10.058076 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7480 01:01:10.061646 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7481 01:01:10.064669 == TX Byte 1 ==
7482 01:01:10.067945 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7483 01:01:10.071411 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
7484 01:01:10.071489 ==
7485 01:01:10.074601 Dram Type= 6, Freq= 0, CH_0, rank 0
7486 01:01:10.081333 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7487 01:01:10.081411 ==
7488 01:01:10.093444
7489 01:01:10.096626 TX Vref early break, caculate TX vref
7490 01:01:10.100306 TX Vref=16, minBit 8, minWin=22, winSum=376
7491 01:01:10.103306 TX Vref=18, minBit 8, minWin=22, winSum=384
7492 01:01:10.106618 TX Vref=20, minBit 0, minWin=24, winSum=391
7493 01:01:10.109912 TX Vref=22, minBit 8, minWin=24, winSum=402
7494 01:01:10.113288 TX Vref=24, minBit 8, minWin=24, winSum=409
7495 01:01:10.120133 TX Vref=26, minBit 9, minWin=25, winSum=420
7496 01:01:10.123192 TX Vref=28, minBit 4, minWin=25, winSum=420
7497 01:01:10.126732 TX Vref=30, minBit 0, minWin=25, winSum=415
7498 01:01:10.129827 TX Vref=32, minBit 1, minWin=24, winSum=403
7499 01:01:10.133165 TX Vref=34, minBit 1, minWin=24, winSum=397
7500 01:01:10.140017 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 26
7501 01:01:10.140103
7502 01:01:10.143096 Final TX Range 0 Vref 26
7503 01:01:10.143175
7504 01:01:10.143235 ==
7505 01:01:10.146486 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 01:01:10.149845 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7507 01:01:10.149932 ==
7508 01:01:10.149994
7509 01:01:10.150050
7510 01:01:10.153023 TX Vref Scan disable
7511 01:01:10.159938 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7512 01:01:10.160034 == TX Byte 0 ==
7513 01:01:10.163057 u2DelayCellOfst[0]=14 cells (4 PI)
7514 01:01:10.166483 u2DelayCellOfst[1]=21 cells (6 PI)
7515 01:01:10.169763 u2DelayCellOfst[2]=18 cells (5 PI)
7516 01:01:10.173479 u2DelayCellOfst[3]=14 cells (4 PI)
7517 01:01:10.176468 u2DelayCellOfst[4]=10 cells (3 PI)
7518 01:01:10.179747 u2DelayCellOfst[5]=0 cells (0 PI)
7519 01:01:10.183134 u2DelayCellOfst[6]=21 cells (6 PI)
7520 01:01:10.186288 u2DelayCellOfst[7]=18 cells (5 PI)
7521 01:01:10.189541 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7522 01:01:10.193184 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7523 01:01:10.196397 == TX Byte 1 ==
7524 01:01:10.196479 u2DelayCellOfst[8]=3 cells (1 PI)
7525 01:01:10.199677 u2DelayCellOfst[9]=0 cells (0 PI)
7526 01:01:10.203084 u2DelayCellOfst[10]=7 cells (2 PI)
7527 01:01:10.206420 u2DelayCellOfst[11]=3 cells (1 PI)
7528 01:01:10.209683 u2DelayCellOfst[12]=14 cells (4 PI)
7529 01:01:10.212991 u2DelayCellOfst[13]=14 cells (4 PI)
7530 01:01:10.216342 u2DelayCellOfst[14]=18 cells (5 PI)
7531 01:01:10.219720 u2DelayCellOfst[15]=14 cells (4 PI)
7532 01:01:10.222927 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
7533 01:01:10.229371 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
7534 01:01:10.229451 DramC Write-DBI on
7535 01:01:10.229511 ==
7536 01:01:10.232720 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 01:01:10.235934 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7538 01:01:10.239357 ==
7539 01:01:10.239436
7540 01:01:10.239496
7541 01:01:10.239552 TX Vref Scan disable
7542 01:01:10.242906 == TX Byte 0 ==
7543 01:01:10.246220 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7544 01:01:10.249621 == TX Byte 1 ==
7545 01:01:10.252983 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
7546 01:01:10.256453 DramC Write-DBI off
7547 01:01:10.256531
7548 01:01:10.256592 [DATLAT]
7549 01:01:10.256647 Freq=1600, CH0 RK0
7550 01:01:10.256701
7551 01:01:10.259742 DATLAT Default: 0xf
7552 01:01:10.259821 0, 0xFFFF, sum = 0
7553 01:01:10.262904 1, 0xFFFF, sum = 0
7554 01:01:10.266049 2, 0xFFFF, sum = 0
7555 01:01:10.266152 3, 0xFFFF, sum = 0
7556 01:01:10.269424 4, 0xFFFF, sum = 0
7557 01:01:10.269503 5, 0xFFFF, sum = 0
7558 01:01:10.272724 6, 0xFFFF, sum = 0
7559 01:01:10.272803 7, 0xFFFF, sum = 0
7560 01:01:10.276219 8, 0xFFFF, sum = 0
7561 01:01:10.276326 9, 0xFFFF, sum = 0
7562 01:01:10.279331 10, 0xFFFF, sum = 0
7563 01:01:10.279411 11, 0xFFFF, sum = 0
7564 01:01:10.282701 12, 0x8FFF, sum = 0
7565 01:01:10.282780 13, 0x0, sum = 1
7566 01:01:10.286120 14, 0x0, sum = 2
7567 01:01:10.286199 15, 0x0, sum = 3
7568 01:01:10.289477 16, 0x0, sum = 4
7569 01:01:10.289592 best_step = 14
7570 01:01:10.289679
7571 01:01:10.289737 ==
7572 01:01:10.292773 Dram Type= 6, Freq= 0, CH_0, rank 0
7573 01:01:10.296065 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7574 01:01:10.299439 ==
7575 01:01:10.299559 RX Vref Scan: 1
7576 01:01:10.299618
7577 01:01:10.302648 Set Vref Range= 24 -> 127
7578 01:01:10.302728
7579 01:01:10.306098 RX Vref 24 -> 127, step: 1
7580 01:01:10.306179
7581 01:01:10.306286 RX Delay 11 -> 252, step: 4
7582 01:01:10.306344
7583 01:01:10.309320 Set Vref, RX VrefLevel [Byte0]: 24
7584 01:01:10.312470 [Byte1]: 24
7585 01:01:10.316552
7586 01:01:10.316630 Set Vref, RX VrefLevel [Byte0]: 25
7587 01:01:10.319744 [Byte1]: 25
7588 01:01:10.323979
7589 01:01:10.324056 Set Vref, RX VrefLevel [Byte0]: 26
7590 01:01:10.327219 [Byte1]: 26
7591 01:01:10.331624
7592 01:01:10.331703 Set Vref, RX VrefLevel [Byte0]: 27
7593 01:01:10.334894 [Byte1]: 27
7594 01:01:10.339278
7595 01:01:10.339355 Set Vref, RX VrefLevel [Byte0]: 28
7596 01:01:10.342450 [Byte1]: 28
7597 01:01:10.346901
7598 01:01:10.346978 Set Vref, RX VrefLevel [Byte0]: 29
7599 01:01:10.349983 [Byte1]: 29
7600 01:01:10.354584
7601 01:01:10.354660 Set Vref, RX VrefLevel [Byte0]: 30
7602 01:01:10.358004 [Byte1]: 30
7603 01:01:10.361936
7604 01:01:10.362014 Set Vref, RX VrefLevel [Byte0]: 31
7605 01:01:10.365264 [Byte1]: 31
7606 01:01:10.369628
7607 01:01:10.369707 Set Vref, RX VrefLevel [Byte0]: 32
7608 01:01:10.375990 [Byte1]: 32
7609 01:01:10.376069
7610 01:01:10.379426 Set Vref, RX VrefLevel [Byte0]: 33
7611 01:01:10.382626 [Byte1]: 33
7612 01:01:10.382709
7613 01:01:10.386009 Set Vref, RX VrefLevel [Byte0]: 34
7614 01:01:10.389415 [Byte1]: 34
7615 01:01:10.389493
7616 01:01:10.392952 Set Vref, RX VrefLevel [Byte0]: 35
7617 01:01:10.395890 [Byte1]: 35
7618 01:01:10.400146
7619 01:01:10.400224 Set Vref, RX VrefLevel [Byte0]: 36
7620 01:01:10.403363 [Byte1]: 36
7621 01:01:10.407844
7622 01:01:10.407923 Set Vref, RX VrefLevel [Byte0]: 37
7623 01:01:10.411051 [Byte1]: 37
7624 01:01:10.415468
7625 01:01:10.415537 Set Vref, RX VrefLevel [Byte0]: 38
7626 01:01:10.418525 [Byte1]: 38
7627 01:01:10.423191
7628 01:01:10.423271 Set Vref, RX VrefLevel [Byte0]: 39
7629 01:01:10.426399 [Byte1]: 39
7630 01:01:10.430409
7631 01:01:10.430488 Set Vref, RX VrefLevel [Byte0]: 40
7632 01:01:10.433803 [Byte1]: 40
7633 01:01:10.438329
7634 01:01:10.438407 Set Vref, RX VrefLevel [Byte0]: 41
7635 01:01:10.441537 [Byte1]: 41
7636 01:01:10.445673
7637 01:01:10.445751 Set Vref, RX VrefLevel [Byte0]: 42
7638 01:01:10.449067 [Byte1]: 42
7639 01:01:10.453473
7640 01:01:10.453552 Set Vref, RX VrefLevel [Byte0]: 43
7641 01:01:10.456794 [Byte1]: 43
7642 01:01:10.460998
7643 01:01:10.461076 Set Vref, RX VrefLevel [Byte0]: 44
7644 01:01:10.464394 [Byte1]: 44
7645 01:01:10.468601
7646 01:01:10.468679 Set Vref, RX VrefLevel [Byte0]: 45
7647 01:01:10.471844 [Byte1]: 45
7648 01:01:10.476237
7649 01:01:10.476314 Set Vref, RX VrefLevel [Byte0]: 46
7650 01:01:10.479474 [Byte1]: 46
7651 01:01:10.483823
7652 01:01:10.483902 Set Vref, RX VrefLevel [Byte0]: 47
7653 01:01:10.487039 [Byte1]: 47
7654 01:01:10.491457
7655 01:01:10.491536 Set Vref, RX VrefLevel [Byte0]: 48
7656 01:01:10.494725 [Byte1]: 48
7657 01:01:10.499294
7658 01:01:10.499372 Set Vref, RX VrefLevel [Byte0]: 49
7659 01:01:10.502502 [Byte1]: 49
7660 01:01:10.506594
7661 01:01:10.506731 Set Vref, RX VrefLevel [Byte0]: 50
7662 01:01:10.509847 [Byte1]: 50
7663 01:01:10.514109
7664 01:01:10.514284 Set Vref, RX VrefLevel [Byte0]: 51
7665 01:01:10.517484 [Byte1]: 51
7666 01:01:10.521810
7667 01:01:10.521939 Set Vref, RX VrefLevel [Byte0]: 52
7668 01:01:10.525099 [Byte1]: 52
7669 01:01:10.529379
7670 01:01:10.529520 Set Vref, RX VrefLevel [Byte0]: 53
7671 01:01:10.532913 [Byte1]: 53
7672 01:01:10.537090
7673 01:01:10.537222 Set Vref, RX VrefLevel [Byte0]: 54
7674 01:01:10.540607 [Byte1]: 54
7675 01:01:10.544663
7676 01:01:10.544803 Set Vref, RX VrefLevel [Byte0]: 55
7677 01:01:10.547947 [Byte1]: 55
7678 01:01:10.552386
7679 01:01:10.552525 Set Vref, RX VrefLevel [Byte0]: 56
7680 01:01:10.555517 [Byte1]: 56
7681 01:01:10.559796
7682 01:01:10.559936 Set Vref, RX VrefLevel [Byte0]: 57
7683 01:01:10.563133 [Byte1]: 57
7684 01:01:10.567681
7685 01:01:10.567811 Set Vref, RX VrefLevel [Byte0]: 58
7686 01:01:10.570748 [Byte1]: 58
7687 01:01:10.575035
7688 01:01:10.575167 Set Vref, RX VrefLevel [Byte0]: 59
7689 01:01:10.578498 [Byte1]: 59
7690 01:01:10.582636
7691 01:01:10.582777 Set Vref, RX VrefLevel [Byte0]: 60
7692 01:01:10.586049 [Byte1]: 60
7693 01:01:10.590340
7694 01:01:10.590478 Set Vref, RX VrefLevel [Byte0]: 61
7695 01:01:10.593913 [Byte1]: 61
7696 01:01:10.597931
7697 01:01:10.598067 Set Vref, RX VrefLevel [Byte0]: 62
7698 01:01:10.601289 [Byte1]: 62
7699 01:01:10.605610
7700 01:01:10.605748 Set Vref, RX VrefLevel [Byte0]: 63
7701 01:01:10.609048 [Byte1]: 63
7702 01:01:10.613285
7703 01:01:10.613365 Set Vref, RX VrefLevel [Byte0]: 64
7704 01:01:10.616536 [Byte1]: 64
7705 01:01:10.620991
7706 01:01:10.621070 Set Vref, RX VrefLevel [Byte0]: 65
7707 01:01:10.624317 [Byte1]: 65
7708 01:01:10.628405
7709 01:01:10.628485 Set Vref, RX VrefLevel [Byte0]: 66
7710 01:01:10.631729 [Byte1]: 66
7711 01:01:10.636139
7712 01:01:10.636219 Set Vref, RX VrefLevel [Byte0]: 67
7713 01:01:10.639331 [Byte1]: 67
7714 01:01:10.643895
7715 01:01:10.643974 Set Vref, RX VrefLevel [Byte0]: 68
7716 01:01:10.647023 [Byte1]: 68
7717 01:01:10.651568
7718 01:01:10.651646 Set Vref, RX VrefLevel [Byte0]: 69
7719 01:01:10.654546 [Byte1]: 69
7720 01:01:10.659243
7721 01:01:10.659321 Set Vref, RX VrefLevel [Byte0]: 70
7722 01:01:10.662366 [Byte1]: 70
7723 01:01:10.666658
7724 01:01:10.666737 Set Vref, RX VrefLevel [Byte0]: 71
7725 01:01:10.669721 [Byte1]: 71
7726 01:01:10.674252
7727 01:01:10.674398 Set Vref, RX VrefLevel [Byte0]: 72
7728 01:01:10.677507 [Byte1]: 72
7729 01:01:10.681694
7730 01:01:10.681823 Final RX Vref Byte 0 = 53 to rank0
7731 01:01:10.684927 Final RX Vref Byte 1 = 57 to rank0
7732 01:01:10.688198 Final RX Vref Byte 0 = 53 to rank1
7733 01:01:10.691705 Final RX Vref Byte 1 = 57 to rank1==
7734 01:01:10.694872 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 01:01:10.701521 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7736 01:01:10.701666 ==
7737 01:01:10.701797 DQS Delay:
7738 01:01:10.701921 DQS0 = 0, DQS1 = 0
7739 01:01:10.704884 DQM Delay:
7740 01:01:10.705020 DQM0 = 126, DQM1 = 120
7741 01:01:10.708298 DQ Delay:
7742 01:01:10.711803 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7743 01:01:10.714988 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7744 01:01:10.718365 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7745 01:01:10.721663 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7746 01:01:10.721799
7747 01:01:10.721926
7748 01:01:10.722051
7749 01:01:10.725019 [DramC_TX_OE_Calibration] TA2
7750 01:01:10.728175 Original DQ_B0 (3 6) =30, OEN = 27
7751 01:01:10.731734 Original DQ_B1 (3 6) =30, OEN = 27
7752 01:01:10.735135 24, 0x0, End_B0=24 End_B1=24
7753 01:01:10.735213 25, 0x0, End_B0=25 End_B1=25
7754 01:01:10.738121 26, 0x0, End_B0=26 End_B1=26
7755 01:01:10.741571 27, 0x0, End_B0=27 End_B1=27
7756 01:01:10.744697 28, 0x0, End_B0=28 End_B1=28
7757 01:01:10.748185 29, 0x0, End_B0=29 End_B1=29
7758 01:01:10.748328 30, 0x0, End_B0=30 End_B1=30
7759 01:01:10.751243 31, 0x4141, End_B0=30 End_B1=30
7760 01:01:10.754670 Byte0 end_step=30 best_step=27
7761 01:01:10.758059 Byte1 end_step=30 best_step=27
7762 01:01:10.761602 Byte0 TX OE(2T, 0.5T) = (3, 3)
7763 01:01:10.764579 Byte1 TX OE(2T, 0.5T) = (3, 3)
7764 01:01:10.764715
7765 01:01:10.764841
7766 01:01:10.771200 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7767 01:01:10.774485 CH0 RK0: MR19=303, MR18=1D1D
7768 01:01:10.781051 CH0_RK0: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
7769 01:01:10.781193
7770 01:01:10.784371 ----->DramcWriteLeveling(PI) begin...
7771 01:01:10.784510 ==
7772 01:01:10.787716 Dram Type= 6, Freq= 0, CH_0, rank 1
7773 01:01:10.791046 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7774 01:01:10.791186 ==
7775 01:01:10.794490 Write leveling (Byte 0): 30 => 30
7776 01:01:10.797691 Write leveling (Byte 1): 25 => 25
7777 01:01:10.801022 DramcWriteLeveling(PI) end<-----
7778 01:01:10.801161
7779 01:01:10.801290 ==
7780 01:01:10.804236 Dram Type= 6, Freq= 0, CH_0, rank 1
7781 01:01:10.807479 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7782 01:01:10.807616 ==
7783 01:01:10.810882 [Gating] SW mode calibration
7784 01:01:10.817500 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7785 01:01:10.824064 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7786 01:01:10.827449 0 12 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7787 01:01:10.834177 0 12 4 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
7788 01:01:10.837869 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7789 01:01:10.841118 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7790 01:01:10.847581 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7791 01:01:10.850706 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7792 01:01:10.854003 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7793 01:01:10.860726 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
7794 01:01:10.863979 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
7795 01:01:10.867338 0 13 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
7796 01:01:10.871080 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7797 01:01:10.877525 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7798 01:01:10.880998 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7799 01:01:10.884073 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7800 01:01:10.890704 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7801 01:01:10.893965 0 13 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7802 01:01:10.897329 0 14 0 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7803 01:01:10.903918 0 14 4 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
7804 01:01:10.907471 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7805 01:01:10.910653 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7806 01:01:10.917394 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7807 01:01:10.920765 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7808 01:01:10.923996 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7809 01:01:10.930726 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7810 01:01:10.933722 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7811 01:01:10.937074 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7812 01:01:10.943588 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7813 01:01:10.946934 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 01:01:10.950177 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 01:01:10.957015 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 01:01:10.960198 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 01:01:10.963713 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 01:01:10.970185 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 01:01:10.973212 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 01:01:10.976823 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 01:01:10.983186 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 01:01:10.986537 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 01:01:10.989824 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 01:01:10.996455 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 01:01:10.999666 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7826 01:01:11.002977 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7827 01:01:11.009733 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7828 01:01:11.009811 Total UI for P1: 0, mck2ui 16
7829 01:01:11.016240 best dqsien dly found for B0: ( 1, 0, 30)
7830 01:01:11.019661 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7831 01:01:11.023089 Total UI for P1: 0, mck2ui 16
7832 01:01:11.026329 best dqsien dly found for B1: ( 1, 1, 4)
7833 01:01:11.029542 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7834 01:01:11.033042 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7835 01:01:11.033120
7836 01:01:11.035977 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7837 01:01:11.039375 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7838 01:01:11.042537 [Gating] SW calibration Done
7839 01:01:11.042614 ==
7840 01:01:11.045865 Dram Type= 6, Freq= 0, CH_0, rank 1
7841 01:01:11.049439 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7842 01:01:11.049518 ==
7843 01:01:11.052677 RX Vref Scan: 0
7844 01:01:11.052754
7845 01:01:11.055930 RX Vref 0 -> 0, step: 1
7846 01:01:11.056008
7847 01:01:11.056068 RX Delay 0 -> 252, step: 8
7848 01:01:11.062478 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7849 01:01:11.065754 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7850 01:01:11.069042 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7851 01:01:11.072503 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7852 01:01:11.075753 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7853 01:01:11.082385 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7854 01:01:11.085742 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7855 01:01:11.088913 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7856 01:01:11.092362 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7857 01:01:11.095791 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7858 01:01:11.102439 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7859 01:01:11.105656 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7860 01:01:11.108879 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7861 01:01:11.112337 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7862 01:01:11.118928 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7863 01:01:11.122101 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7864 01:01:11.122179 ==
7865 01:01:11.125668 Dram Type= 6, Freq= 0, CH_0, rank 1
7866 01:01:11.128778 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7867 01:01:11.128857 ==
7868 01:01:11.128917 DQS Delay:
7869 01:01:11.132057 DQS0 = 0, DQS1 = 0
7870 01:01:11.132134 DQM Delay:
7871 01:01:11.135229 DQM0 = 130, DQM1 = 124
7872 01:01:11.135306 DQ Delay:
7873 01:01:11.138667 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7874 01:01:11.141966 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7875 01:01:11.145237 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7876 01:01:11.151879 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7877 01:01:11.151957
7878 01:01:11.152017
7879 01:01:11.152072 ==
7880 01:01:11.155050 Dram Type= 6, Freq= 0, CH_0, rank 1
7881 01:01:11.158465 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7882 01:01:11.158541 ==
7883 01:01:11.158601
7884 01:01:11.158656
7885 01:01:11.161666 TX Vref Scan disable
7886 01:01:11.161744 == TX Byte 0 ==
7887 01:01:11.168322 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7888 01:01:11.171767 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7889 01:01:11.171845 == TX Byte 1 ==
7890 01:01:11.178161 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7891 01:01:11.181614 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7892 01:01:11.181692 ==
7893 01:01:11.184963 Dram Type= 6, Freq= 0, CH_0, rank 1
7894 01:01:11.188312 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7895 01:01:11.188391 ==
7896 01:01:11.202573
7897 01:01:11.205918 TX Vref early break, caculate TX vref
7898 01:01:11.209148 TX Vref=16, minBit 8, minWin=22, winSum=373
7899 01:01:11.212652 TX Vref=18, minBit 8, minWin=22, winSum=377
7900 01:01:11.216149 TX Vref=20, minBit 1, minWin=23, winSum=386
7901 01:01:11.219089 TX Vref=22, minBit 10, minWin=23, winSum=394
7902 01:01:11.222801 TX Vref=24, minBit 7, minWin=24, winSum=403
7903 01:01:11.229052 TX Vref=26, minBit 3, minWin=25, winSum=411
7904 01:01:11.232207 TX Vref=28, minBit 8, minWin=24, winSum=408
7905 01:01:11.235780 TX Vref=30, minBit 8, minWin=24, winSum=412
7906 01:01:11.238990 TX Vref=32, minBit 7, minWin=24, winSum=403
7907 01:01:11.242328 TX Vref=34, minBit 8, minWin=23, winSum=390
7908 01:01:11.249208 [TxChooseVref] Worse bit 3, Min win 25, Win sum 411, Final Vref 26
7909 01:01:11.249285
7910 01:01:11.252370 Final TX Range 0 Vref 26
7911 01:01:11.252447
7912 01:01:11.252509 ==
7913 01:01:11.255722 Dram Type= 6, Freq= 0, CH_0, rank 1
7914 01:01:11.258850 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7915 01:01:11.258929 ==
7916 01:01:11.259024
7917 01:01:11.259078
7918 01:01:11.262311 TX Vref Scan disable
7919 01:01:11.268771 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7920 01:01:11.268849 == TX Byte 0 ==
7921 01:01:11.272145 u2DelayCellOfst[0]=10 cells (3 PI)
7922 01:01:11.275699 u2DelayCellOfst[1]=18 cells (5 PI)
7923 01:01:11.278787 u2DelayCellOfst[2]=10 cells (3 PI)
7924 01:01:11.282132 u2DelayCellOfst[3]=14 cells (4 PI)
7925 01:01:11.285531 u2DelayCellOfst[4]=7 cells (2 PI)
7926 01:01:11.288813 u2DelayCellOfst[5]=0 cells (0 PI)
7927 01:01:11.292241 u2DelayCellOfst[6]=18 cells (5 PI)
7928 01:01:11.295356 u2DelayCellOfst[7]=18 cells (5 PI)
7929 01:01:11.298587 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7930 01:01:11.302052 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7931 01:01:11.305352 == TX Byte 1 ==
7932 01:01:11.308507 u2DelayCellOfst[8]=3 cells (1 PI)
7933 01:01:11.308584 u2DelayCellOfst[9]=0 cells (0 PI)
7934 01:01:11.311877 u2DelayCellOfst[10]=10 cells (3 PI)
7935 01:01:11.315204 u2DelayCellOfst[11]=7 cells (2 PI)
7936 01:01:11.318577 u2DelayCellOfst[12]=18 cells (5 PI)
7937 01:01:11.321940 u2DelayCellOfst[13]=18 cells (5 PI)
7938 01:01:11.325179 u2DelayCellOfst[14]=21 cells (6 PI)
7939 01:01:11.328420 u2DelayCellOfst[15]=18 cells (5 PI)
7940 01:01:11.331796 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7941 01:01:11.338304 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7942 01:01:11.338381 DramC Write-DBI on
7943 01:01:11.338440 ==
7944 01:01:11.341812 Dram Type= 6, Freq= 0, CH_0, rank 1
7945 01:01:11.348185 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7946 01:01:11.348263 ==
7947 01:01:11.348331
7948 01:01:11.348392
7949 01:01:11.348445 TX Vref Scan disable
7950 01:01:11.352100 == TX Byte 0 ==
7951 01:01:11.355479 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7952 01:01:11.358646 == TX Byte 1 ==
7953 01:01:11.362007 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7954 01:01:11.365271 DramC Write-DBI off
7955 01:01:11.365346
7956 01:01:11.365405 [DATLAT]
7957 01:01:11.365460 Freq=1600, CH0 RK1
7958 01:01:11.365513
7959 01:01:11.368712 DATLAT Default: 0xe
7960 01:01:11.368788 0, 0xFFFF, sum = 0
7961 01:01:11.372157 1, 0xFFFF, sum = 0
7962 01:01:11.375275 2, 0xFFFF, sum = 0
7963 01:01:11.375352 3, 0xFFFF, sum = 0
7964 01:01:11.378677 4, 0xFFFF, sum = 0
7965 01:01:11.378754 5, 0xFFFF, sum = 0
7966 01:01:11.381811 6, 0xFFFF, sum = 0
7967 01:01:11.381887 7, 0xFFFF, sum = 0
7968 01:01:11.385311 8, 0xFFFF, sum = 0
7969 01:01:11.385388 9, 0xFFFF, sum = 0
7970 01:01:11.388825 10, 0xFFFF, sum = 0
7971 01:01:11.388903 11, 0xFFFF, sum = 0
7972 01:01:11.391762 12, 0x8FFF, sum = 0
7973 01:01:11.391842 13, 0x0, sum = 1
7974 01:01:11.394965 14, 0x0, sum = 2
7975 01:01:11.395071 15, 0x0, sum = 3
7976 01:01:11.398613 16, 0x0, sum = 4
7977 01:01:11.398693 best_step = 14
7978 01:01:11.398770
7979 01:01:11.398843 ==
7980 01:01:11.401750 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 01:01:11.404958 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7982 01:01:11.408276 ==
7983 01:01:11.408353 RX Vref Scan: 0
7984 01:01:11.408431
7985 01:01:11.411510 RX Vref 0 -> 0, step: 1
7986 01:01:11.411588
7987 01:01:11.414831 RX Delay 11 -> 252, step: 4
7988 01:01:11.418066 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7989 01:01:11.421548 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7990 01:01:11.424712 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7991 01:01:11.431390 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7992 01:01:11.434631 iDelay=195, Bit 4, Center 132 (75 ~ 190) 116
7993 01:01:11.438126 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7994 01:01:11.441497 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7995 01:01:11.444641 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7996 01:01:11.451628 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
7997 01:01:11.454792 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7998 01:01:11.457920 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7999 01:01:11.461280 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8000 01:01:11.464518 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8001 01:01:11.471384 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8002 01:01:11.474604 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8003 01:01:11.478041 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8004 01:01:11.478118 ==
8005 01:01:11.481396 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 01:01:11.484502 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8007 01:01:11.484600 ==
8008 01:01:11.487619 DQS Delay:
8009 01:01:11.487696 DQS0 = 0, DQS1 = 0
8010 01:01:11.491055 DQM Delay:
8011 01:01:11.491133 DQM0 = 128, DQM1 = 120
8012 01:01:11.494459 DQ Delay:
8013 01:01:11.497814 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
8014 01:01:11.501074 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8015 01:01:11.504476 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8016 01:01:11.507585 DQ12 =126, DQ13 =126, DQ14 =130, DQ15 =130
8017 01:01:11.507663
8018 01:01:11.507723
8019 01:01:11.507779
8020 01:01:11.510961 [DramC_TX_OE_Calibration] TA2
8021 01:01:11.514553 Original DQ_B0 (3 6) =30, OEN = 27
8022 01:01:11.517505 Original DQ_B1 (3 6) =30, OEN = 27
8023 01:01:11.517598 24, 0x0, End_B0=24 End_B1=24
8024 01:01:11.521040 25, 0x0, End_B0=25 End_B1=25
8025 01:01:11.524218 26, 0x0, End_B0=26 End_B1=26
8026 01:01:11.527404 27, 0x0, End_B0=27 End_B1=27
8027 01:01:11.531198 28, 0x0, End_B0=28 End_B1=28
8028 01:01:11.531277 29, 0x0, End_B0=29 End_B1=29
8029 01:01:11.534434 30, 0x0, End_B0=30 End_B1=30
8030 01:01:11.537681 31, 0x5151, End_B0=30 End_B1=30
8031 01:01:11.540842 Byte0 end_step=30 best_step=27
8032 01:01:11.544250 Byte1 end_step=30 best_step=27
8033 01:01:11.547503 Byte0 TX OE(2T, 0.5T) = (3, 3)
8034 01:01:11.547598 Byte1 TX OE(2T, 0.5T) = (3, 3)
8035 01:01:11.547681
8036 01:01:11.547762
8037 01:01:11.557497 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8038 01:01:11.561008 CH0 RK1: MR19=303, MR18=2323
8039 01:01:11.567609 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
8040 01:01:11.567710 [RxdqsGatingPostProcess] freq 1600
8041 01:01:11.573991 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8042 01:01:11.577402 Pre-setting of DQS Precalculation
8043 01:01:11.584249 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8044 01:01:11.584327 ==
8045 01:01:11.587466 Dram Type= 6, Freq= 0, CH_1, rank 0
8046 01:01:11.590672 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8047 01:01:11.590750 ==
8048 01:01:11.597448 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8049 01:01:11.600747 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8050 01:01:11.604031 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8051 01:01:11.610531 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8052 01:01:11.618168 [CA 0] Center 41 (11~71) winsize 61
8053 01:01:11.621384 [CA 1] Center 41 (11~71) winsize 61
8054 01:01:11.624677 [CA 2] Center 37 (8~67) winsize 60
8055 01:01:11.627931 [CA 3] Center 36 (6~66) winsize 61
8056 01:01:11.631323 [CA 4] Center 34 (4~64) winsize 61
8057 01:01:11.634577 [CA 5] Center 34 (5~64) winsize 60
8058 01:01:11.634656
8059 01:01:11.638189 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8060 01:01:11.638305
8061 01:01:11.641248 [CATrainingPosCal] consider 1 rank data
8062 01:01:11.644623 u2DelayCellTimex100 = 271/100 ps
8063 01:01:11.651247 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8064 01:01:11.654598 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8065 01:01:11.657736 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8066 01:01:11.661219 CA3 delay=36 (6~66),Diff = 2 PI (7 cell)
8067 01:01:11.664587 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8068 01:01:11.667792 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8069 01:01:11.667870
8070 01:01:11.671210 CA PerBit enable=1, Macro0, CA PI delay=34
8071 01:01:11.671287
8072 01:01:11.674470 [CBTSetCACLKResult] CA Dly = 34
8073 01:01:11.677733 CS Dly: 8 (0~39)
8074 01:01:11.681234 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8075 01:01:11.684635 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8076 01:01:11.684711 ==
8077 01:01:11.687753 Dram Type= 6, Freq= 0, CH_1, rank 1
8078 01:01:11.691195 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8079 01:01:11.694605 ==
8080 01:01:11.698040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8081 01:01:11.701119 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8082 01:01:11.707800 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8083 01:01:11.710908 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8084 01:01:11.720433 [CA 0] Center 40 (10~70) winsize 61
8085 01:01:11.723733 [CA 1] Center 39 (9~70) winsize 62
8086 01:01:11.727333 [CA 2] Center 35 (6~65) winsize 60
8087 01:01:11.730772 [CA 3] Center 34 (5~64) winsize 60
8088 01:01:11.733763 [CA 4] Center 33 (3~63) winsize 61
8089 01:01:11.737239 [CA 5] Center 33 (3~63) winsize 61
8090 01:01:11.737316
8091 01:01:11.740477 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8092 01:01:11.740554
8093 01:01:11.743607 [CATrainingPosCal] consider 2 rank data
8094 01:01:11.746932 u2DelayCellTimex100 = 271/100 ps
8095 01:01:11.750250 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8096 01:01:11.757118 CA1 delay=40 (11~70),Diff = 7 PI (25 cell)
8097 01:01:11.760297 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8098 01:01:11.763415 CA3 delay=35 (6~64),Diff = 2 PI (7 cell)
8099 01:01:11.766995 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8100 01:01:11.770348 CA5 delay=34 (5~63),Diff = 1 PI (3 cell)
8101 01:01:11.770426
8102 01:01:11.773494 CA PerBit enable=1, Macro0, CA PI delay=33
8103 01:01:11.773572
8104 01:01:11.776735 [CBTSetCACLKResult] CA Dly = 33
8105 01:01:11.780403 CS Dly: 9 (0~41)
8106 01:01:11.783301 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8107 01:01:11.786724 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8108 01:01:11.786802
8109 01:01:11.790013 ----->DramcWriteLeveling(PI) begin...
8110 01:01:11.790091 ==
8111 01:01:11.793434 Dram Type= 6, Freq= 0, CH_1, rank 0
8112 01:01:11.799872 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8113 01:01:11.799950 ==
8114 01:01:11.803416 Write leveling (Byte 0): 22 => 22
8115 01:01:11.803494 Write leveling (Byte 1): 22 => 22
8116 01:01:11.806496 DramcWriteLeveling(PI) end<-----
8117 01:01:11.806574
8118 01:01:11.806634 ==
8119 01:01:11.809918 Dram Type= 6, Freq= 0, CH_1, rank 0
8120 01:01:11.816643 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8121 01:01:11.816721 ==
8122 01:01:11.820087 [Gating] SW mode calibration
8123 01:01:11.826772 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8124 01:01:11.829905 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8125 01:01:11.836268 0 12 0 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
8126 01:01:11.839662 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8127 01:01:11.843052 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8128 01:01:11.849633 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8129 01:01:11.852849 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8130 01:01:11.856221 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8131 01:01:11.862671 0 12 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
8132 01:01:11.865821 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8133 01:01:11.869136 0 13 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8134 01:01:11.875791 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8135 01:01:11.879321 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8136 01:01:11.882791 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8137 01:01:11.889432 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8138 01:01:11.892507 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8139 01:01:11.895962 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8140 01:01:11.902614 0 13 28 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8141 01:01:11.905616 0 14 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8142 01:01:11.909099 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8143 01:01:11.915968 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8144 01:01:11.919088 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8145 01:01:11.922319 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 01:01:11.925819 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8147 01:01:11.932322 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8148 01:01:11.935880 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8149 01:01:11.939118 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8150 01:01:11.945567 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8151 01:01:11.949144 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 01:01:11.952308 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 01:01:11.958984 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 01:01:11.962354 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 01:01:11.965607 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 01:01:11.972182 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 01:01:11.975501 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 01:01:11.979059 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 01:01:11.985418 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 01:01:11.988821 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 01:01:11.992418 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 01:01:11.998661 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 01:01:12.002251 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8164 01:01:12.005805 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8165 01:01:12.012150 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8166 01:01:12.012228 Total UI for P1: 0, mck2ui 16
8167 01:01:12.018375 best dqsien dly found for B0: ( 1, 0, 26)
8168 01:01:12.022205 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8169 01:01:12.025276 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8170 01:01:12.028707 Total UI for P1: 0, mck2ui 16
8171 01:01:12.032023 best dqsien dly found for B1: ( 1, 1, 2)
8172 01:01:12.035305 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8173 01:01:12.038432 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8174 01:01:12.038510
8175 01:01:12.045153 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8176 01:01:12.048436 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8177 01:01:12.048513 [Gating] SW calibration Done
8178 01:01:12.051630 ==
8179 01:01:12.055030 Dram Type= 6, Freq= 0, CH_1, rank 0
8180 01:01:12.058236 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8181 01:01:12.058331 ==
8182 01:01:12.058392 RX Vref Scan: 0
8183 01:01:12.058448
8184 01:01:12.061576 RX Vref 0 -> 0, step: 1
8185 01:01:12.061653
8186 01:01:12.064854 RX Delay 0 -> 252, step: 8
8187 01:01:12.068191 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8188 01:01:12.071489 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8189 01:01:12.074871 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8190 01:01:12.081467 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8191 01:01:12.084909 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8192 01:01:12.088137 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8193 01:01:12.091699 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8194 01:01:12.094619 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8195 01:01:12.101307 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8196 01:01:12.104746 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8197 01:01:12.107976 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8198 01:01:12.111210 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8199 01:01:12.114434 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8200 01:01:12.121295 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8201 01:01:12.124546 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8202 01:01:12.128049 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8203 01:01:12.128127 ==
8204 01:01:12.131244 Dram Type= 6, Freq= 0, CH_1, rank 0
8205 01:01:12.134308 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8206 01:01:12.137684 ==
8207 01:01:12.137762 DQS Delay:
8208 01:01:12.137822 DQS0 = 0, DQS1 = 0
8209 01:01:12.141020 DQM Delay:
8210 01:01:12.141098 DQM0 = 130, DQM1 = 125
8211 01:01:12.144382 DQ Delay:
8212 01:01:12.147892 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8213 01:01:12.151019 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8214 01:01:12.154340 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =115
8215 01:01:12.157793 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8216 01:01:12.157870
8217 01:01:12.157931
8218 01:01:12.157986 ==
8219 01:01:12.161030 Dram Type= 6, Freq= 0, CH_1, rank 0
8220 01:01:12.164226 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8221 01:01:12.164305 ==
8222 01:01:12.164365
8223 01:01:12.167618
8224 01:01:12.167695 TX Vref Scan disable
8225 01:01:12.170920 == TX Byte 0 ==
8226 01:01:12.174155 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8227 01:01:12.177572 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8228 01:01:12.180994 == TX Byte 1 ==
8229 01:01:12.184222 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8230 01:01:12.187642 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8231 01:01:12.187719 ==
8232 01:01:12.190710 Dram Type= 6, Freq= 0, CH_1, rank 0
8233 01:01:12.197397 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8234 01:01:12.197476 ==
8235 01:01:12.208628
8236 01:01:12.211838 TX Vref early break, caculate TX vref
8237 01:01:12.214996 TX Vref=16, minBit 3, minWin=21, winSum=367
8238 01:01:12.218535 TX Vref=18, minBit 1, minWin=22, winSum=375
8239 01:01:12.221711 TX Vref=20, minBit 3, minWin=22, winSum=381
8240 01:01:12.225065 TX Vref=22, minBit 3, minWin=23, winSum=395
8241 01:01:12.228552 TX Vref=24, minBit 1, minWin=24, winSum=402
8242 01:01:12.235198 TX Vref=26, minBit 3, minWin=24, winSum=412
8243 01:01:12.238254 TX Vref=28, minBit 0, minWin=25, winSum=411
8244 01:01:12.241851 TX Vref=30, minBit 3, minWin=23, winSum=409
8245 01:01:12.244762 TX Vref=32, minBit 3, minWin=23, winSum=395
8246 01:01:12.248158 TX Vref=34, minBit 1, minWin=23, winSum=386
8247 01:01:12.254774 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 28
8248 01:01:12.254853
8249 01:01:12.257955 Final TX Range 0 Vref 28
8250 01:01:12.258070
8251 01:01:12.258131 ==
8252 01:01:12.261576 Dram Type= 6, Freq= 0, CH_1, rank 0
8253 01:01:12.264802 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8254 01:01:12.264880 ==
8255 01:01:12.264941
8256 01:01:12.264996
8257 01:01:12.267963 TX Vref Scan disable
8258 01:01:12.274669 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8259 01:01:12.274747 == TX Byte 0 ==
8260 01:01:12.278167 u2DelayCellOfst[0]=14 cells (4 PI)
8261 01:01:12.281371 u2DelayCellOfst[1]=10 cells (3 PI)
8262 01:01:12.284816 u2DelayCellOfst[2]=0 cells (0 PI)
8263 01:01:12.287893 u2DelayCellOfst[3]=3 cells (1 PI)
8264 01:01:12.291237 u2DelayCellOfst[4]=7 cells (2 PI)
8265 01:01:12.294574 u2DelayCellOfst[5]=14 cells (4 PI)
8266 01:01:12.298146 u2DelayCellOfst[6]=14 cells (4 PI)
8267 01:01:12.298284 u2DelayCellOfst[7]=7 cells (2 PI)
8268 01:01:12.304588 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8269 01:01:12.307765 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8270 01:01:12.311078 == TX Byte 1 ==
8271 01:01:12.311156 u2DelayCellOfst[8]=0 cells (0 PI)
8272 01:01:12.314660 u2DelayCellOfst[9]=3 cells (1 PI)
8273 01:01:12.318141 u2DelayCellOfst[10]=10 cells (3 PI)
8274 01:01:12.321324 u2DelayCellOfst[11]=3 cells (1 PI)
8275 01:01:12.324636 u2DelayCellOfst[12]=18 cells (5 PI)
8276 01:01:12.327688 u2DelayCellOfst[13]=21 cells (6 PI)
8277 01:01:12.330976 u2DelayCellOfst[14]=21 cells (6 PI)
8278 01:01:12.334323 u2DelayCellOfst[15]=21 cells (6 PI)
8279 01:01:12.337568 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8280 01:01:12.344293 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8281 01:01:12.344370 DramC Write-DBI on
8282 01:01:12.344429 ==
8283 01:01:12.347421 Dram Type= 6, Freq= 0, CH_1, rank 0
8284 01:01:12.350700 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8285 01:01:12.353880 ==
8286 01:01:12.353957
8287 01:01:12.354020
8288 01:01:12.354103 TX Vref Scan disable
8289 01:01:12.357537 == TX Byte 0 ==
8290 01:01:12.361267 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8291 01:01:12.364306 == TX Byte 1 ==
8292 01:01:12.367487 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8293 01:01:12.370918 DramC Write-DBI off
8294 01:01:12.370995
8295 01:01:12.371054 [DATLAT]
8296 01:01:12.371109 Freq=1600, CH1 RK0
8297 01:01:12.371164
8298 01:01:12.374109 DATLAT Default: 0xf
8299 01:01:12.374184 0, 0xFFFF, sum = 0
8300 01:01:12.377521 1, 0xFFFF, sum = 0
8301 01:01:12.380802 2, 0xFFFF, sum = 0
8302 01:01:12.380879 3, 0xFFFF, sum = 0
8303 01:01:12.384121 4, 0xFFFF, sum = 0
8304 01:01:12.384198 5, 0xFFFF, sum = 0
8305 01:01:12.387416 6, 0xFFFF, sum = 0
8306 01:01:12.387493 7, 0xFFFF, sum = 0
8307 01:01:12.390970 8, 0xFFFF, sum = 0
8308 01:01:12.391047 9, 0xFFFF, sum = 0
8309 01:01:12.394055 10, 0xFFFF, sum = 0
8310 01:01:12.394156 11, 0xFFFF, sum = 0
8311 01:01:12.397485 12, 0xF7F, sum = 0
8312 01:01:12.397563 13, 0x0, sum = 1
8313 01:01:12.400868 14, 0x0, sum = 2
8314 01:01:12.400945 15, 0x0, sum = 3
8315 01:01:12.403923 16, 0x0, sum = 4
8316 01:01:12.404001 best_step = 14
8317 01:01:12.404070
8318 01:01:12.404130 ==
8319 01:01:12.407315 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 01:01:12.410590 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8321 01:01:12.413921 ==
8322 01:01:12.413997 RX Vref Scan: 1
8323 01:01:12.414056
8324 01:01:12.417156 Set Vref Range= 24 -> 127
8325 01:01:12.417233
8326 01:01:12.417292 RX Vref 24 -> 127, step: 1
8327 01:01:12.420610
8328 01:01:12.420686 RX Delay 11 -> 252, step: 4
8329 01:01:12.420745
8330 01:01:12.424001 Set Vref, RX VrefLevel [Byte0]: 24
8331 01:01:12.427158 [Byte1]: 24
8332 01:01:12.430720
8333 01:01:12.430795 Set Vref, RX VrefLevel [Byte0]: 25
8334 01:01:12.434128 [Byte1]: 25
8335 01:01:12.438646
8336 01:01:12.438723 Set Vref, RX VrefLevel [Byte0]: 26
8337 01:01:12.441681 [Byte1]: 26
8338 01:01:12.446045
8339 01:01:12.446145 Set Vref, RX VrefLevel [Byte0]: 27
8340 01:01:12.449398 [Byte1]: 27
8341 01:01:12.453627
8342 01:01:12.453704 Set Vref, RX VrefLevel [Byte0]: 28
8343 01:01:12.457110 [Byte1]: 28
8344 01:01:12.461293
8345 01:01:12.461370 Set Vref, RX VrefLevel [Byte0]: 29
8346 01:01:12.464464 [Byte1]: 29
8347 01:01:12.468965
8348 01:01:12.469041 Set Vref, RX VrefLevel [Byte0]: 30
8349 01:01:12.472245 [Byte1]: 30
8350 01:01:12.476418
8351 01:01:12.476494 Set Vref, RX VrefLevel [Byte0]: 31
8352 01:01:12.479753 [Byte1]: 31
8353 01:01:12.484093
8354 01:01:12.484192 Set Vref, RX VrefLevel [Byte0]: 32
8355 01:01:12.487403 [Byte1]: 32
8356 01:01:12.491568
8357 01:01:12.491645 Set Vref, RX VrefLevel [Byte0]: 33
8358 01:01:12.495018 [Byte1]: 33
8359 01:01:12.499370
8360 01:01:12.499447 Set Vref, RX VrefLevel [Byte0]: 34
8361 01:01:12.502558 [Byte1]: 34
8362 01:01:12.506941
8363 01:01:12.507017 Set Vref, RX VrefLevel [Byte0]: 35
8364 01:01:12.510539 [Byte1]: 35
8365 01:01:12.514547
8366 01:01:12.514623 Set Vref, RX VrefLevel [Byte0]: 36
8367 01:01:12.517908 [Byte1]: 36
8368 01:01:12.522308
8369 01:01:12.522384 Set Vref, RX VrefLevel [Byte0]: 37
8370 01:01:12.525541 [Byte1]: 37
8371 01:01:12.529685
8372 01:01:12.529763 Set Vref, RX VrefLevel [Byte0]: 38
8373 01:01:12.533101 [Byte1]: 38
8374 01:01:12.537306
8375 01:01:12.537398 Set Vref, RX VrefLevel [Byte0]: 39
8376 01:01:12.540621 [Byte1]: 39
8377 01:01:12.545067
8378 01:01:12.545143 Set Vref, RX VrefLevel [Byte0]: 40
8379 01:01:12.548478 [Byte1]: 40
8380 01:01:12.552506
8381 01:01:12.552607 Set Vref, RX VrefLevel [Byte0]: 41
8382 01:01:12.555839 [Byte1]: 41
8383 01:01:12.560219
8384 01:01:12.560295 Set Vref, RX VrefLevel [Byte0]: 42
8385 01:01:12.563458 [Byte1]: 42
8386 01:01:12.567982
8387 01:01:12.568059 Set Vref, RX VrefLevel [Byte0]: 43
8388 01:01:12.571428 [Byte1]: 43
8389 01:01:12.575374
8390 01:01:12.575450 Set Vref, RX VrefLevel [Byte0]: 44
8391 01:01:12.578726 [Byte1]: 44
8392 01:01:12.583049
8393 01:01:12.583124 Set Vref, RX VrefLevel [Byte0]: 45
8394 01:01:12.586346 [Byte1]: 45
8395 01:01:12.590742
8396 01:01:12.590823 Set Vref, RX VrefLevel [Byte0]: 46
8397 01:01:12.594180 [Byte1]: 46
8398 01:01:12.598460
8399 01:01:12.598536 Set Vref, RX VrefLevel [Byte0]: 47
8400 01:01:12.601804 [Byte1]: 47
8401 01:01:12.605992
8402 01:01:12.606069 Set Vref, RX VrefLevel [Byte0]: 48
8403 01:01:12.609243 [Byte1]: 48
8404 01:01:12.613589
8405 01:01:12.613667 Set Vref, RX VrefLevel [Byte0]: 49
8406 01:01:12.616733 [Byte1]: 49
8407 01:01:12.621111
8408 01:01:12.621187 Set Vref, RX VrefLevel [Byte0]: 50
8409 01:01:12.624550 [Byte1]: 50
8410 01:01:12.628739
8411 01:01:12.628816 Set Vref, RX VrefLevel [Byte0]: 51
8412 01:01:12.632061 [Byte1]: 51
8413 01:01:12.636473
8414 01:01:12.636612 Set Vref, RX VrefLevel [Byte0]: 52
8415 01:01:12.639485 [Byte1]: 52
8416 01:01:12.644084
8417 01:01:12.644160 Set Vref, RX VrefLevel [Byte0]: 53
8418 01:01:12.647137 [Byte1]: 53
8419 01:01:12.651486
8420 01:01:12.651564 Set Vref, RX VrefLevel [Byte0]: 54
8421 01:01:12.654792 [Byte1]: 54
8422 01:01:12.659521
8423 01:01:12.659599 Set Vref, RX VrefLevel [Byte0]: 55
8424 01:01:12.662733 [Byte1]: 55
8425 01:01:12.666738
8426 01:01:12.666816 Set Vref, RX VrefLevel [Byte0]: 56
8427 01:01:12.670366 [Byte1]: 56
8428 01:01:12.674545
8429 01:01:12.674622 Set Vref, RX VrefLevel [Byte0]: 57
8430 01:01:12.677931 [Byte1]: 57
8431 01:01:12.682045
8432 01:01:12.682123 Set Vref, RX VrefLevel [Byte0]: 58
8433 01:01:12.685358 [Byte1]: 58
8434 01:01:12.689926
8435 01:01:12.690003 Set Vref, RX VrefLevel [Byte0]: 59
8436 01:01:12.693013 [Byte1]: 59
8437 01:01:12.697231
8438 01:01:12.697317 Set Vref, RX VrefLevel [Byte0]: 60
8439 01:01:12.700523 [Byte1]: 60
8440 01:01:12.705122
8441 01:01:12.705200 Set Vref, RX VrefLevel [Byte0]: 61
8442 01:01:12.708230 [Byte1]: 61
8443 01:01:12.712425
8444 01:01:12.712503 Set Vref, RX VrefLevel [Byte0]: 62
8445 01:01:12.715823 [Byte1]: 62
8446 01:01:12.720029
8447 01:01:12.720107 Set Vref, RX VrefLevel [Byte0]: 63
8448 01:01:12.723472 [Byte1]: 63
8449 01:01:12.727967
8450 01:01:12.728045 Set Vref, RX VrefLevel [Byte0]: 64
8451 01:01:12.730910 [Byte1]: 64
8452 01:01:12.735239
8453 01:01:12.735316 Set Vref, RX VrefLevel [Byte0]: 65
8454 01:01:12.738845 [Byte1]: 65
8455 01:01:12.743064
8456 01:01:12.743142 Set Vref, RX VrefLevel [Byte0]: 66
8457 01:01:12.746143 [Byte1]: 66
8458 01:01:12.750651
8459 01:01:12.750729 Set Vref, RX VrefLevel [Byte0]: 67
8460 01:01:12.753720 [Byte1]: 67
8461 01:01:12.758086
8462 01:01:12.758187 Set Vref, RX VrefLevel [Byte0]: 68
8463 01:01:12.761899 [Byte1]: 68
8464 01:01:12.765847
8465 01:01:12.765949 Set Vref, RX VrefLevel [Byte0]: 69
8466 01:01:12.769066 [Byte1]: 69
8467 01:01:12.773303
8468 01:01:12.773380 Set Vref, RX VrefLevel [Byte0]: 70
8469 01:01:12.776765 [Byte1]: 70
8470 01:01:12.780868
8471 01:01:12.780969 Set Vref, RX VrefLevel [Byte0]: 71
8472 01:01:12.784180 [Byte1]: 71
8473 01:01:12.788486
8474 01:01:12.788563 Set Vref, RX VrefLevel [Byte0]: 72
8475 01:01:12.792041 [Byte1]: 72
8476 01:01:12.796119
8477 01:01:12.796196 Set Vref, RX VrefLevel [Byte0]: 73
8478 01:01:12.799499 [Byte1]: 73
8479 01:01:12.803866
8480 01:01:12.803942 Set Vref, RX VrefLevel [Byte0]: 74
8481 01:01:12.807128 [Byte1]: 74
8482 01:01:12.811887
8483 01:01:12.811967 Set Vref, RX VrefLevel [Byte0]: 75
8484 01:01:12.814939 [Byte1]: 75
8485 01:01:12.819276
8486 01:01:12.819352 Set Vref, RX VrefLevel [Byte0]: 76
8487 01:01:12.822433 [Byte1]: 76
8488 01:01:12.826890
8489 01:01:12.827005 Final RX Vref Byte 0 = 58 to rank0
8490 01:01:12.829975 Final RX Vref Byte 1 = 54 to rank0
8491 01:01:12.833543 Final RX Vref Byte 0 = 58 to rank1
8492 01:01:12.836578 Final RX Vref Byte 1 = 54 to rank1==
8493 01:01:12.839929 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 01:01:12.846671 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8495 01:01:12.846748 ==
8496 01:01:12.846808 DQS Delay:
8497 01:01:12.849834 DQS0 = 0, DQS1 = 0
8498 01:01:12.849911 DQM Delay:
8499 01:01:12.849970 DQM0 = 128, DQM1 = 123
8500 01:01:12.853278 DQ Delay:
8501 01:01:12.856509 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8502 01:01:12.859806 DQ4 =126, DQ5 =138, DQ6 =138, DQ7 =126
8503 01:01:12.862893 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114
8504 01:01:12.866330 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8505 01:01:12.866406
8506 01:01:12.866466
8507 01:01:12.866522
8508 01:01:12.869582 [DramC_TX_OE_Calibration] TA2
8509 01:01:12.873023 Original DQ_B0 (3 6) =30, OEN = 27
8510 01:01:12.876344 Original DQ_B1 (3 6) =30, OEN = 27
8511 01:01:12.879568 24, 0x0, End_B0=24 End_B1=24
8512 01:01:12.879646 25, 0x0, End_B0=25 End_B1=25
8513 01:01:12.882914 26, 0x0, End_B0=26 End_B1=26
8514 01:01:12.886333 27, 0x0, End_B0=27 End_B1=27
8515 01:01:12.889592 28, 0x0, End_B0=28 End_B1=28
8516 01:01:12.892792 29, 0x0, End_B0=29 End_B1=29
8517 01:01:12.892869 30, 0x0, End_B0=30 End_B1=30
8518 01:01:12.896187 31, 0x4141, End_B0=30 End_B1=30
8519 01:01:12.899415 Byte0 end_step=30 best_step=27
8520 01:01:12.902732 Byte1 end_step=30 best_step=27
8521 01:01:12.906120 Byte0 TX OE(2T, 0.5T) = (3, 3)
8522 01:01:12.909390 Byte1 TX OE(2T, 0.5T) = (3, 3)
8523 01:01:12.909467
8524 01:01:12.909527
8525 01:01:12.916120 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8526 01:01:12.919613 CH1 RK0: MR19=303, MR18=2626
8527 01:01:12.925871 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8528 01:01:12.925949
8529 01:01:12.929278 ----->DramcWriteLeveling(PI) begin...
8530 01:01:12.929357 ==
8531 01:01:12.932566 Dram Type= 6, Freq= 0, CH_1, rank 1
8532 01:01:12.935783 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8533 01:01:12.935862 ==
8534 01:01:12.939490 Write leveling (Byte 0): 21 => 21
8535 01:01:12.942397 Write leveling (Byte 1): 20 => 20
8536 01:01:12.946047 DramcWriteLeveling(PI) end<-----
8537 01:01:12.946123
8538 01:01:12.946183 ==
8539 01:01:12.949210 Dram Type= 6, Freq= 0, CH_1, rank 1
8540 01:01:12.952539 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8541 01:01:12.952617 ==
8542 01:01:12.956032 [Gating] SW mode calibration
8543 01:01:12.962224 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8544 01:01:12.969126 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8545 01:01:12.972547 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8546 01:01:12.978737 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8547 01:01:12.982092 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8548 01:01:12.985500 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8549 01:01:12.992056 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8550 01:01:12.995555 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8551 01:01:12.998789 0 12 24 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
8552 01:01:13.005533 0 12 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8553 01:01:13.008752 0 13 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8554 01:01:13.011913 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8555 01:01:13.018862 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8556 01:01:13.022037 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8557 01:01:13.025327 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8558 01:01:13.032017 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
8559 01:01:13.035321 0 13 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8560 01:01:13.038630 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8561 01:01:13.042019 0 14 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8562 01:01:13.048639 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8563 01:01:13.052078 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8564 01:01:13.055300 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8565 01:01:13.061833 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8566 01:01:13.065111 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8567 01:01:13.068454 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8568 01:01:13.075042 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8569 01:01:13.078450 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8570 01:01:13.081765 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8571 01:01:13.088263 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 01:01:13.091822 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 01:01:13.094914 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 01:01:13.101492 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 01:01:13.105113 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 01:01:13.108198 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 01:01:13.114810 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 01:01:13.118149 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8579 01:01:13.121470 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8580 01:01:13.128220 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 01:01:13.131563 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 01:01:13.134744 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 01:01:13.141473 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8584 01:01:13.144971 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8585 01:01:13.148437 Total UI for P1: 0, mck2ui 16
8586 01:01:13.151502 best dqsien dly found for B0: ( 1, 0, 24)
8587 01:01:13.154866 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8588 01:01:13.158198 Total UI for P1: 0, mck2ui 16
8589 01:01:13.161605 best dqsien dly found for B1: ( 1, 0, 28)
8590 01:01:13.164888 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8591 01:01:13.168273 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8592 01:01:13.168349
8593 01:01:13.171540 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8594 01:01:13.178200 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8595 01:01:13.178316 [Gating] SW calibration Done
8596 01:01:13.178376 ==
8597 01:01:13.181632 Dram Type= 6, Freq= 0, CH_1, rank 1
8598 01:01:13.188166 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8599 01:01:13.188243 ==
8600 01:01:13.188302 RX Vref Scan: 0
8601 01:01:13.188358
8602 01:01:13.191318 RX Vref 0 -> 0, step: 1
8603 01:01:13.191396
8604 01:01:13.194673 RX Delay 0 -> 252, step: 8
8605 01:01:13.198103 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8606 01:01:13.201631 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8607 01:01:13.204811 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8608 01:01:13.207927 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8609 01:01:13.214609 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8610 01:01:13.218000 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8611 01:01:13.221337 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8612 01:01:13.224593 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8613 01:01:13.227821 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8614 01:01:13.234614 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8615 01:01:13.237837 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8616 01:01:13.241084 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8617 01:01:13.244581 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8618 01:01:13.251004 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8619 01:01:13.254208 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8620 01:01:13.257681 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8621 01:01:13.257759 ==
8622 01:01:13.261128 Dram Type= 6, Freq= 0, CH_1, rank 1
8623 01:01:13.264429 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8624 01:01:13.264508 ==
8625 01:01:13.267744 DQS Delay:
8626 01:01:13.267822 DQS0 = 0, DQS1 = 0
8627 01:01:13.270896 DQM Delay:
8628 01:01:13.270973 DQM0 = 130, DQM1 = 124
8629 01:01:13.271034 DQ Delay:
8630 01:01:13.277744 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =131
8631 01:01:13.280956 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =127
8632 01:01:13.284158 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
8633 01:01:13.287493 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8634 01:01:13.287570
8635 01:01:13.287636
8636 01:01:13.287693 ==
8637 01:01:13.290833 Dram Type= 6, Freq= 0, CH_1, rank 1
8638 01:01:13.294256 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8639 01:01:13.294335 ==
8640 01:01:13.294395
8641 01:01:13.294451
8642 01:01:13.297357 TX Vref Scan disable
8643 01:01:13.300743 == TX Byte 0 ==
8644 01:01:13.304134 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8645 01:01:13.307507 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8646 01:01:13.310910 == TX Byte 1 ==
8647 01:01:13.314340 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8648 01:01:13.317707 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8649 01:01:13.317786 ==
8650 01:01:13.321330 Dram Type= 6, Freq= 0, CH_1, rank 1
8651 01:01:13.324521 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8652 01:01:13.327432 ==
8653 01:01:13.339272
8654 01:01:13.342535 TX Vref early break, caculate TX vref
8655 01:01:13.345833 TX Vref=16, minBit 3, minWin=22, winSum=382
8656 01:01:13.349108 TX Vref=18, minBit 3, minWin=23, winSum=390
8657 01:01:13.352409 TX Vref=20, minBit 2, minWin=23, winSum=399
8658 01:01:13.355784 TX Vref=22, minBit 0, minWin=24, winSum=406
8659 01:01:13.358958 TX Vref=24, minBit 3, minWin=24, winSum=410
8660 01:01:13.365882 TX Vref=26, minBit 2, minWin=25, winSum=422
8661 01:01:13.368923 TX Vref=28, minBit 1, minWin=25, winSum=422
8662 01:01:13.372426 TX Vref=30, minBit 0, minWin=25, winSum=420
8663 01:01:13.375639 TX Vref=32, minBit 0, minWin=24, winSum=415
8664 01:01:13.378947 TX Vref=34, minBit 0, minWin=23, winSum=402
8665 01:01:13.382204 TX Vref=36, minBit 0, minWin=23, winSum=396
8666 01:01:13.388736 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 26
8667 01:01:13.388814
8668 01:01:13.392192 Final TX Range 0 Vref 26
8669 01:01:13.392269
8670 01:01:13.392329 ==
8671 01:01:13.395645 Dram Type= 6, Freq= 0, CH_1, rank 1
8672 01:01:13.398893 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8673 01:01:13.398970 ==
8674 01:01:13.399031
8675 01:01:13.399087
8676 01:01:13.402051 TX Vref Scan disable
8677 01:01:13.409056 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8678 01:01:13.409134 == TX Byte 0 ==
8679 01:01:13.412155 u2DelayCellOfst[0]=18 cells (5 PI)
8680 01:01:13.415549 u2DelayCellOfst[1]=10 cells (3 PI)
8681 01:01:13.418818 u2DelayCellOfst[2]=0 cells (0 PI)
8682 01:01:13.422137 u2DelayCellOfst[3]=7 cells (2 PI)
8683 01:01:13.425625 u2DelayCellOfst[4]=7 cells (2 PI)
8684 01:01:13.428670 u2DelayCellOfst[5]=18 cells (5 PI)
8685 01:01:13.431948 u2DelayCellOfst[6]=14 cells (4 PI)
8686 01:01:13.435306 u2DelayCellOfst[7]=7 cells (2 PI)
8687 01:01:13.439001 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8688 01:01:13.442116 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8689 01:01:13.445278 == TX Byte 1 ==
8690 01:01:13.448488 u2DelayCellOfst[8]=0 cells (0 PI)
8691 01:01:13.448567 u2DelayCellOfst[9]=3 cells (1 PI)
8692 01:01:13.451961 u2DelayCellOfst[10]=10 cells (3 PI)
8693 01:01:13.455078 u2DelayCellOfst[11]=3 cells (1 PI)
8694 01:01:13.458539 u2DelayCellOfst[12]=14 cells (4 PI)
8695 01:01:13.461853 u2DelayCellOfst[13]=18 cells (5 PI)
8696 01:01:13.465053 u2DelayCellOfst[14]=18 cells (5 PI)
8697 01:01:13.468598 u2DelayCellOfst[15]=18 cells (5 PI)
8698 01:01:13.474963 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8699 01:01:13.478411 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8700 01:01:13.478489 DramC Write-DBI on
8701 01:01:13.478550 ==
8702 01:01:13.481506 Dram Type= 6, Freq= 0, CH_1, rank 1
8703 01:01:13.488118 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8704 01:01:13.488197 ==
8705 01:01:13.488258
8706 01:01:13.488313
8707 01:01:13.488365 TX Vref Scan disable
8708 01:01:13.492197 == TX Byte 0 ==
8709 01:01:13.495511 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8710 01:01:13.499000 == TX Byte 1 ==
8711 01:01:13.502174 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8712 01:01:13.505579 DramC Write-DBI off
8713 01:01:13.505654
8714 01:01:13.505713 [DATLAT]
8715 01:01:13.505768 Freq=1600, CH1 RK1
8716 01:01:13.505821
8717 01:01:13.509028 DATLAT Default: 0xe
8718 01:01:13.509105 0, 0xFFFF, sum = 0
8719 01:01:13.512088 1, 0xFFFF, sum = 0
8720 01:01:13.515465 2, 0xFFFF, sum = 0
8721 01:01:13.515542 3, 0xFFFF, sum = 0
8722 01:01:13.518885 4, 0xFFFF, sum = 0
8723 01:01:13.518964 5, 0xFFFF, sum = 0
8724 01:01:13.522175 6, 0xFFFF, sum = 0
8725 01:01:13.522293 7, 0xFFFF, sum = 0
8726 01:01:13.525443 8, 0xFFFF, sum = 0
8727 01:01:13.525521 9, 0xFFFF, sum = 0
8728 01:01:13.528573 10, 0xFFFF, sum = 0
8729 01:01:13.528652 11, 0xFFFF, sum = 0
8730 01:01:13.532328 12, 0xF7F, sum = 0
8731 01:01:13.532407 13, 0x0, sum = 1
8732 01:01:13.535477 14, 0x0, sum = 2
8733 01:01:13.535556 15, 0x0, sum = 3
8734 01:01:13.538693 16, 0x0, sum = 4
8735 01:01:13.538772 best_step = 14
8736 01:01:13.538833
8737 01:01:13.538888 ==
8738 01:01:13.542333 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 01:01:13.545428 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8740 01:01:13.545506 ==
8741 01:01:13.548658 RX Vref Scan: 0
8742 01:01:13.548735
8743 01:01:13.551966 RX Vref 0 -> 0, step: 1
8744 01:01:13.552043
8745 01:01:13.552103 RX Delay 3 -> 252, step: 4
8746 01:01:13.559277 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8747 01:01:13.562589 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8748 01:01:13.566322 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8749 01:01:13.569414 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8750 01:01:13.572505 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8751 01:01:13.578991 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8752 01:01:13.582537 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8753 01:01:13.585922 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8754 01:01:13.589037 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8755 01:01:13.592459 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8756 01:01:13.598766 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8757 01:01:13.602096 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8758 01:01:13.605362 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8759 01:01:13.608746 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8760 01:01:13.615408 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8761 01:01:13.618673 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8762 01:01:13.618750 ==
8763 01:01:13.621986 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 01:01:13.625248 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8765 01:01:13.625329 ==
8766 01:01:13.628635 DQS Delay:
8767 01:01:13.628713 DQS0 = 0, DQS1 = 0
8768 01:01:13.628773 DQM Delay:
8769 01:01:13.631971 DQM0 = 127, DQM1 = 122
8770 01:01:13.632048 DQ Delay:
8771 01:01:13.635240 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8772 01:01:13.638771 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8773 01:01:13.641868 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8774 01:01:13.648402 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8775 01:01:13.648480
8776 01:01:13.648539
8777 01:01:13.648594
8778 01:01:13.651836 [DramC_TX_OE_Calibration] TA2
8779 01:01:13.654927 Original DQ_B0 (3 6) =30, OEN = 27
8780 01:01:13.655006 Original DQ_B1 (3 6) =30, OEN = 27
8781 01:01:13.658243 24, 0x0, End_B0=24 End_B1=24
8782 01:01:13.661938 25, 0x0, End_B0=25 End_B1=25
8783 01:01:13.664907 26, 0x0, End_B0=26 End_B1=26
8784 01:01:13.668418 27, 0x0, End_B0=27 End_B1=27
8785 01:01:13.668497 28, 0x0, End_B0=28 End_B1=28
8786 01:01:13.671603 29, 0x0, End_B0=29 End_B1=29
8787 01:01:13.674922 30, 0x0, End_B0=30 End_B1=30
8788 01:01:13.678135 31, 0x5151, End_B0=30 End_B1=30
8789 01:01:13.681610 Byte0 end_step=30 best_step=27
8790 01:01:13.681688 Byte1 end_step=30 best_step=27
8791 01:01:13.684829 Byte0 TX OE(2T, 0.5T) = (3, 3)
8792 01:01:13.688233 Byte1 TX OE(2T, 0.5T) = (3, 3)
8793 01:01:13.688310
8794 01:01:13.688370
8795 01:01:13.698247 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8796 01:01:13.701451 CH1 RK1: MR19=303, MR18=1C1C
8797 01:01:13.705090 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8798 01:01:13.708442 [RxdqsGatingPostProcess] freq 1600
8799 01:01:13.714663 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8800 01:01:13.717800 Pre-setting of DQS Precalculation
8801 01:01:13.721472 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8802 01:01:13.731122 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8803 01:01:13.737814 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8804 01:01:13.737892
8805 01:01:13.737952
8806 01:01:13.741311 [Calibration Summary] 3200 Mbps
8807 01:01:13.741388 CH 0, Rank 0
8808 01:01:13.744498 SW Impedance : PASS
8809 01:01:13.744575 DUTY Scan : NO K
8810 01:01:13.747856 ZQ Calibration : PASS
8811 01:01:13.751077 Jitter Meter : NO K
8812 01:01:13.751160 CBT Training : PASS
8813 01:01:13.754480 Write leveling : PASS
8814 01:01:13.757774 RX DQS gating : PASS
8815 01:01:13.757852 RX DQ/DQS(RDDQC) : PASS
8816 01:01:13.760997 TX DQ/DQS : PASS
8817 01:01:13.764384 RX DATLAT : PASS
8818 01:01:13.764462 RX DQ/DQS(Engine): PASS
8819 01:01:13.767666 TX OE : PASS
8820 01:01:13.767744 All Pass.
8821 01:01:13.767804
8822 01:01:13.771138 CH 0, Rank 1
8823 01:01:13.771214 SW Impedance : PASS
8824 01:01:13.774501 DUTY Scan : NO K
8825 01:01:13.774579 ZQ Calibration : PASS
8826 01:01:13.777647 Jitter Meter : NO K
8827 01:01:13.781040 CBT Training : PASS
8828 01:01:13.781119 Write leveling : PASS
8829 01:01:13.784379 RX DQS gating : PASS
8830 01:01:13.787620 RX DQ/DQS(RDDQC) : PASS
8831 01:01:13.787697 TX DQ/DQS : PASS
8832 01:01:13.791323 RX DATLAT : PASS
8833 01:01:13.794193 RX DQ/DQS(Engine): PASS
8834 01:01:13.794307 TX OE : PASS
8835 01:01:13.797529 All Pass.
8836 01:01:13.797607
8837 01:01:13.797667 CH 1, Rank 0
8838 01:01:13.800876 SW Impedance : PASS
8839 01:01:13.800953 DUTY Scan : NO K
8840 01:01:13.804336 ZQ Calibration : PASS
8841 01:01:13.807608 Jitter Meter : NO K
8842 01:01:13.807686 CBT Training : PASS
8843 01:01:13.810672 Write leveling : PASS
8844 01:01:13.814140 RX DQS gating : PASS
8845 01:01:13.814269 RX DQ/DQS(RDDQC) : PASS
8846 01:01:13.817487 TX DQ/DQS : PASS
8847 01:01:13.820663 RX DATLAT : PASS
8848 01:01:13.820741 RX DQ/DQS(Engine): PASS
8849 01:01:13.824043 TX OE : PASS
8850 01:01:13.824122 All Pass.
8851 01:01:13.824182
8852 01:01:13.827516 CH 1, Rank 1
8853 01:01:13.827593 SW Impedance : PASS
8854 01:01:13.830722 DUTY Scan : NO K
8855 01:01:13.830800 ZQ Calibration : PASS
8856 01:01:13.834023 Jitter Meter : NO K
8857 01:01:13.837456 CBT Training : PASS
8858 01:01:13.837534 Write leveling : PASS
8859 01:01:13.840824 RX DQS gating : PASS
8860 01:01:13.844180 RX DQ/DQS(RDDQC) : PASS
8861 01:01:13.844258 TX DQ/DQS : PASS
8862 01:01:13.847293 RX DATLAT : PASS
8863 01:01:13.850561 RX DQ/DQS(Engine): PASS
8864 01:01:13.850661 TX OE : PASS
8865 01:01:13.853935 All Pass.
8866 01:01:13.854037
8867 01:01:13.854125 DramC Write-DBI on
8868 01:01:13.857263 PER_BANK_REFRESH: Hybrid Mode
8869 01:01:13.857353 TX_TRACKING: ON
8870 01:01:13.867182 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8871 01:01:13.877227 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8872 01:01:13.883765 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8873 01:01:13.887004 [FAST_K] Save calibration result to emmc
8874 01:01:13.890336 sync common calibartion params.
8875 01:01:13.890414 sync cbt_mode0:0, 1:0
8876 01:01:13.893885 dram_init: ddr_geometry: 0
8877 01:01:13.896991 dram_init: ddr_geometry: 0
8878 01:01:13.897069 dram_init: ddr_geometry: 0
8879 01:01:13.900305 0:dram_rank_size:80000000
8880 01:01:13.903949 1:dram_rank_size:80000000
8881 01:01:13.907206 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8882 01:01:13.910480 DFS_SHUFFLE_HW_MODE: ON
8883 01:01:13.913718 dramc_set_vcore_voltage set vcore to 725000
8884 01:01:13.917200 Read voltage for 1600, 0
8885 01:01:13.917278 Vio18 = 0
8886 01:01:13.920368 Vcore = 725000
8887 01:01:13.920446 Vdram = 0
8888 01:01:13.920507 Vddq = 0
8889 01:01:13.920562 Vmddr = 0
8890 01:01:13.924045 switch to 3200 Mbps bootup
8891 01:01:13.926966 [DramcRunTimeConfig]
8892 01:01:13.927044 PHYPLL
8893 01:01:13.930308 DPM_CONTROL_AFTERK: ON
8894 01:01:13.930386 PER_BANK_REFRESH: ON
8895 01:01:13.933537 REFRESH_OVERHEAD_REDUCTION: ON
8896 01:01:13.936916 CMD_PICG_NEW_MODE: OFF
8897 01:01:13.936993 XRTWTW_NEW_MODE: ON
8898 01:01:13.940317 XRTRTR_NEW_MODE: ON
8899 01:01:13.940417 TX_TRACKING: ON
8900 01:01:13.943544 RDSEL_TRACKING: OFF
8901 01:01:13.947087 DQS Precalculation for DVFS: ON
8902 01:01:13.947166 RX_TRACKING: OFF
8903 01:01:13.950316 HW_GATING DBG: ON
8904 01:01:13.950393 ZQCS_ENABLE_LP4: ON
8905 01:01:13.953840 RX_PICG_NEW_MODE: ON
8906 01:01:13.953916 TX_PICG_NEW_MODE: ON
8907 01:01:13.956883 ENABLE_RX_DCM_DPHY: ON
8908 01:01:13.960274 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8909 01:01:13.963545 DUMMY_READ_FOR_TRACKING: OFF
8910 01:01:13.963623 !!! SPM_CONTROL_AFTERK: OFF
8911 01:01:13.966724 !!! SPM could not control APHY
8912 01:01:13.970131 IMPEDANCE_TRACKING: ON
8913 01:01:13.970208 TEMP_SENSOR: ON
8914 01:01:13.973523 HW_SAVE_FOR_SR: OFF
8915 01:01:13.976785 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8916 01:01:13.980140 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8917 01:01:13.980216 Read ODT Tracking: ON
8918 01:01:13.983339 Refresh Rate DeBounce: ON
8919 01:01:13.986606 DFS_NO_QUEUE_FLUSH: ON
8920 01:01:13.990053 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8921 01:01:13.990129 ENABLE_DFS_RUNTIME_MRW: OFF
8922 01:01:13.993220 DDR_RESERVE_NEW_MODE: ON
8923 01:01:13.996580 MR_CBT_SWITCH_FREQ: ON
8924 01:01:13.996679 =========================
8925 01:01:14.016790 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8926 01:01:14.020003 dram_init: ddr_geometry: 0
8927 01:01:14.037920 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8928 01:01:14.041288 dram_init: dram init end (result: 0)
8929 01:01:14.048080 DRAM-K: Full calibration passed in 23418 msecs
8930 01:01:14.051148 MRC: failed to locate region type 0.
8931 01:01:14.051224 DRAM rank0 size:0x80000000,
8932 01:01:14.054664 DRAM rank1 size=0x80000000
8933 01:01:14.064437 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8934 01:01:14.071117 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8935 01:01:14.077652 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8936 01:01:14.084519 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8937 01:01:14.087729 DRAM rank0 size:0x80000000,
8938 01:01:14.091156 DRAM rank1 size=0x80000000
8939 01:01:14.091233 CBMEM:
8940 01:01:14.094331 IMD: root @ 0xfffff000 254 entries.
8941 01:01:14.097710 IMD: root @ 0xffffec00 62 entries.
8942 01:01:14.100887 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8943 01:01:14.104158 WARNING: RO_VPD is uninitialized or empty.
8944 01:01:14.110490 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8945 01:01:14.117648 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8946 01:01:14.130403 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8947 01:01:14.141957 BS: romstage times (exec / console): total (unknown) / 22956 ms
8948 01:01:14.142035
8949 01:01:14.142095
8950 01:01:14.151745 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8951 01:01:14.155036 ARM64: Exception handlers installed.
8952 01:01:14.158205 ARM64: Testing exception
8953 01:01:14.161560 ARM64: Done test exception
8954 01:01:14.161635 Enumerating buses...
8955 01:01:14.164918 Show all devs... Before device enumeration.
8956 01:01:14.168477 Root Device: enabled 1
8957 01:01:14.171557 CPU_CLUSTER: 0: enabled 1
8958 01:01:14.171636 CPU: 00: enabled 1
8959 01:01:14.174811 Compare with tree...
8960 01:01:14.174887 Root Device: enabled 1
8961 01:01:14.178382 CPU_CLUSTER: 0: enabled 1
8962 01:01:14.181491 CPU: 00: enabled 1
8963 01:01:14.181567 Root Device scanning...
8964 01:01:14.184709 scan_static_bus for Root Device
8965 01:01:14.188160 CPU_CLUSTER: 0 enabled
8966 01:01:14.191348 scan_static_bus for Root Device done
8967 01:01:14.194655 scan_bus: bus Root Device finished in 8 msecs
8968 01:01:14.194731 done
8969 01:01:14.201322 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8970 01:01:14.204617 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8971 01:01:14.211305 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8972 01:01:14.214867 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8973 01:01:14.218181 Allocating resources...
8974 01:01:14.221321 Reading resources...
8975 01:01:14.224471 Root Device read_resources bus 0 link: 0
8976 01:01:14.224547 DRAM rank0 size:0x80000000,
8977 01:01:14.228004 DRAM rank1 size=0x80000000
8978 01:01:14.231171 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8979 01:01:14.234555 CPU: 00 missing read_resources
8980 01:01:14.237538 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8981 01:01:14.244250 Root Device read_resources bus 0 link: 0 done
8982 01:01:14.244327 Done reading resources.
8983 01:01:14.250989 Show resources in subtree (Root Device)...After reading.
8984 01:01:14.254205 Root Device child on link 0 CPU_CLUSTER: 0
8985 01:01:14.257669 CPU_CLUSTER: 0 child on link 0 CPU: 00
8986 01:01:14.267402 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8987 01:01:14.267479 CPU: 00
8988 01:01:14.270720 Root Device assign_resources, bus 0 link: 0
8989 01:01:14.274080 CPU_CLUSTER: 0 missing set_resources
8990 01:01:14.280671 Root Device assign_resources, bus 0 link: 0 done
8991 01:01:14.280747 Done setting resources.
8992 01:01:14.287463 Show resources in subtree (Root Device)...After assigning values.
8993 01:01:14.290593 Root Device child on link 0 CPU_CLUSTER: 0
8994 01:01:14.294062 CPU_CLUSTER: 0 child on link 0 CPU: 00
8995 01:01:14.303832 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8996 01:01:14.303911 CPU: 00
8997 01:01:14.307070 Done allocating resources.
8998 01:01:14.310458 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8999 01:01:14.313931 Enabling resources...
9000 01:01:14.314008 done.
9001 01:01:14.320547 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9002 01:01:14.320625 Initializing devices...
9003 01:01:14.323787 Root Device init
9004 01:01:14.323864 init hardware done!
9005 01:01:14.327302 0x00000018: ctrlr->caps
9006 01:01:14.330377 52.000 MHz: ctrlr->f_max
9007 01:01:14.330457 0.400 MHz: ctrlr->f_min
9008 01:01:14.333711 0x40ff8080: ctrlr->voltages
9009 01:01:14.337217 sclk: 390625
9010 01:01:14.337295 Bus Width = 1
9011 01:01:14.337356 sclk: 390625
9012 01:01:14.340424 Bus Width = 1
9013 01:01:14.340502 Early init status = 3
9014 01:01:14.346953 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9015 01:01:14.350199 in-header: 03 fc 00 00 01 00 00 00
9016 01:01:14.353657 in-data: 00
9017 01:01:14.356881 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9018 01:01:14.361180 in-header: 03 fd 00 00 00 00 00 00
9019 01:01:14.364376 in-data:
9020 01:01:14.367794 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9021 01:01:14.371407 in-header: 03 fc 00 00 01 00 00 00
9022 01:01:14.374593 in-data: 00
9023 01:01:14.377887 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9024 01:01:14.382907 in-header: 03 fd 00 00 00 00 00 00
9025 01:01:14.386364 in-data:
9026 01:01:14.389613 [SSUSB] Setting up USB HOST controller...
9027 01:01:14.392931 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9028 01:01:14.396059 [SSUSB] phy power-on done.
9029 01:01:14.399429 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9030 01:01:14.406069 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9031 01:01:14.409862 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9032 01:01:14.416042 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9033 01:01:14.422610 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9034 01:01:14.429488 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9035 01:01:14.435908 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9036 01:01:14.442560 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9037 01:01:14.445975 SPM: binary array size = 0x9dc
9038 01:01:14.449294 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9039 01:01:14.455796 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9040 01:01:14.462554 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9041 01:01:14.468870 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9042 01:01:14.472153 configure_display: Starting display init
9043 01:01:14.506321 anx7625_power_on_init: Init interface.
9044 01:01:14.509403 anx7625_disable_pd_protocol: Disabled PD feature.
9045 01:01:14.513159 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9046 01:01:14.540504 anx7625_start_dp_work: Secure OCM version=00
9047 01:01:14.543673 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9048 01:01:14.558606 sp_tx_get_edid_block: EDID Block = 1
9049 01:01:14.661423 Extracted contents:
9050 01:01:14.664762 header: 00 ff ff ff ff ff ff 00
9051 01:01:14.667997 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9052 01:01:14.671189 version: 01 04
9053 01:01:14.674583 basic params: 95 1f 11 78 0a
9054 01:01:14.677989 chroma info: 76 90 94 55 54 90 27 21 50 54
9055 01:01:14.681122 established: 00 00 00
9056 01:01:14.687818 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9057 01:01:14.691232 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9058 01:01:14.697908 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9059 01:01:14.704648 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9060 01:01:14.711352 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9061 01:01:14.714382 extensions: 00
9062 01:01:14.714458 checksum: fb
9063 01:01:14.714518
9064 01:01:14.717730 Manufacturer: IVO Model 57d Serial Number 0
9065 01:01:14.721235 Made week 0 of 2020
9066 01:01:14.721354 EDID version: 1.4
9067 01:01:14.724587 Digital display
9068 01:01:14.727792 6 bits per primary color channel
9069 01:01:14.727896 DisplayPort interface
9070 01:01:14.731181 Maximum image size: 31 cm x 17 cm
9071 01:01:14.734519 Gamma: 220%
9072 01:01:14.734621 Check DPMS levels
9073 01:01:14.737698 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9074 01:01:14.741281 First detailed timing is preferred timing
9075 01:01:14.744642 Established timings supported:
9076 01:01:14.747798 Standard timings supported:
9077 01:01:14.747874 Detailed timings
9078 01:01:14.754419 Hex of detail: 383680a07038204018303c0035ae10000019
9079 01:01:14.757708 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9080 01:01:14.764374 0780 0798 07c8 0820 hborder 0
9081 01:01:14.768087 0438 043b 0447 0458 vborder 0
9082 01:01:14.771323 -hsync -vsync
9083 01:01:14.771400 Did detailed timing
9084 01:01:14.774462 Hex of detail: 000000000000000000000000000000000000
9085 01:01:14.777618 Manufacturer-specified data, tag 0
9086 01:01:14.784365 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9087 01:01:14.784443 ASCII string: InfoVision
9088 01:01:14.790787 Hex of detail: 000000fe00523134304e574635205248200a
9089 01:01:14.794108 ASCII string: R140NWF5 RH
9090 01:01:14.794185 Checksum
9091 01:01:14.794283 Checksum: 0xfb (valid)
9092 01:01:14.800679 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9093 01:01:14.803980 DSI data_rate: 832800000 bps
9094 01:01:14.807477 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9095 01:01:14.813901 anx7625_parse_edid: pixelclock(138800).
9096 01:01:14.817276 hactive(1920), hsync(48), hfp(24), hbp(88)
9097 01:01:14.820687 vactive(1080), vsync(12), vfp(3), vbp(17)
9098 01:01:14.823813 anx7625_dsi_config: config dsi.
9099 01:01:14.830274 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9100 01:01:14.843380 anx7625_dsi_config: success to config DSI
9101 01:01:14.846552 anx7625_dp_start: MIPI phy setup OK.
9102 01:01:14.849922 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9103 01:01:14.853303 mtk_ddp_mode_set invalid vrefresh 60
9104 01:01:14.856530 main_disp_path_setup
9105 01:01:14.856632 ovl_layer_smi_id_en
9106 01:01:14.859920 ovl_layer_smi_id_en
9107 01:01:14.860020 ccorr_config
9108 01:01:14.860105 aal_config
9109 01:01:14.863228 gamma_config
9110 01:01:14.863366 postmask_config
9111 01:01:14.866610 dither_config
9112 01:01:14.870130 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9113 01:01:14.876479 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9114 01:01:14.879895 Root Device init finished in 552 msecs
9115 01:01:14.879994 CPU_CLUSTER: 0 init
9116 01:01:14.889686 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9117 01:01:14.893393 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9118 01:01:14.896274 APU_MBOX 0x190000b0 = 0x10001
9119 01:01:14.899724 APU_MBOX 0x190001b0 = 0x10001
9120 01:01:14.903107 APU_MBOX 0x190005b0 = 0x10001
9121 01:01:14.906300 APU_MBOX 0x190006b0 = 0x10001
9122 01:01:14.909659 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9123 01:01:14.922189 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9124 01:01:14.934697 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9125 01:01:14.941357 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9126 01:01:14.952956 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9127 01:01:14.961859 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9128 01:01:14.965280 CPU_CLUSTER: 0 init finished in 81 msecs
9129 01:01:14.968456 Devices initialized
9130 01:01:14.972014 Show all devs... After init.
9131 01:01:14.972115 Root Device: enabled 1
9132 01:01:14.975330 CPU_CLUSTER: 0: enabled 1
9133 01:01:14.978630 CPU: 00: enabled 1
9134 01:01:14.982064 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9135 01:01:14.985317 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9136 01:01:14.988731 ELOG: NV offset 0x57f000 size 0x1000
9137 01:01:14.995528 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9138 01:01:15.002132 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9139 01:01:15.005266 ELOG: Event(17) added with size 13 at 2024-06-16 01:01:15 UTC
9140 01:01:15.008679 out: cmd=0x121: 03 db 21 01 00 00 00 00
9141 01:01:15.012370 in-header: 03 2e 00 00 2c 00 00 00
9142 01:01:15.025460 in-data: 14 6d 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9143 01:01:15.032024 ELOG: Event(A1) added with size 10 at 2024-06-16 01:01:15 UTC
9144 01:01:15.038560 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9145 01:01:15.045116 ELOG: Event(A0) added with size 9 at 2024-06-16 01:01:15 UTC
9146 01:01:15.048664 elog_add_boot_reason: Logged dev mode boot
9147 01:01:15.051931 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9148 01:01:15.055171 Finalize devices...
9149 01:01:15.055249 Devices finalized
9150 01:01:15.062170 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9151 01:01:15.065134 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9152 01:01:15.068597 in-header: 03 07 00 00 08 00 00 00
9153 01:01:15.071936 in-data: aa e4 47 04 13 02 00 00
9154 01:01:15.075075 Chrome EC: UHEPI supported
9155 01:01:15.081939 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9156 01:01:15.085019 in-header: 03 a9 00 00 08 00 00 00
9157 01:01:15.088549 in-data: 84 60 60 08 00 00 00 00
9158 01:01:15.091819 ELOG: Event(91) added with size 10 at 2024-06-16 01:01:15 UTC
9159 01:01:15.098134 Chrome EC: clear events_b mask to 0x0000000020004000
9160 01:01:15.105140 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9161 01:01:15.108442 in-header: 03 fd 00 00 00 00 00 00
9162 01:01:15.108520 in-data:
9163 01:01:15.115430 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9164 01:01:15.118434 Writing coreboot table at 0xffe64000
9165 01:01:15.121704 0. 000000000010a000-0000000000113fff: RAMSTAGE
9166 01:01:15.125031 1. 0000000040000000-00000000400fffff: RAM
9167 01:01:15.128351 2. 0000000040100000-000000004032afff: RAMSTAGE
9168 01:01:15.135111 3. 000000004032b000-00000000545fffff: RAM
9169 01:01:15.138422 4. 0000000054600000-000000005465ffff: BL31
9170 01:01:15.141570 5. 0000000054660000-00000000ffe63fff: RAM
9171 01:01:15.148559 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9172 01:01:15.151553 7. 0000000100000000-000000013fffffff: RAM
9173 01:01:15.151655 Passing 5 GPIOs to payload:
9174 01:01:15.158250 NAME | PORT | POLARITY | VALUE
9175 01:01:15.161454 EC in RW | 0x000000aa | low | undefined
9176 01:01:15.168416 EC interrupt | 0x00000005 | low | undefined
9177 01:01:15.171530 TPM interrupt | 0x000000ab | high | undefined
9178 01:01:15.174818 SD card detect | 0x00000011 | high | undefined
9179 01:01:15.181327 speaker enable | 0x00000093 | high | undefined
9180 01:01:15.184541 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9181 01:01:15.188008 in-header: 03 f8 00 00 02 00 00 00
9182 01:01:15.191209 in-data: 03 00
9183 01:01:15.191290 ADC[4]: Raw value=668958 ID=5
9184 01:01:15.194836 ADC[3]: Raw value=212549 ID=1
9185 01:01:15.197906 RAM Code: 0x51
9186 01:01:15.197986 ADC[6]: Raw value=74410 ID=0
9187 01:01:15.201169 ADC[5]: Raw value=211812 ID=1
9188 01:01:15.204562 SKU Code: 0x1
9189 01:01:15.207898 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 20e
9190 01:01:15.211098 coreboot table: 964 bytes.
9191 01:01:15.214544 IMD ROOT 0. 0xfffff000 0x00001000
9192 01:01:15.218014 IMD SMALL 1. 0xffffe000 0x00001000
9193 01:01:15.221351 RO MCACHE 2. 0xffffc000 0x00001104
9194 01:01:15.224358 CONSOLE 3. 0xfff7c000 0x00080000
9195 01:01:15.227765 FMAP 4. 0xfff7b000 0x00000452
9196 01:01:15.231053 TIME STAMP 5. 0xfff7a000 0x00000910
9197 01:01:15.234500 VBOOT WORK 6. 0xfff66000 0x00014000
9198 01:01:15.237610 RAMOOPS 7. 0xffe66000 0x00100000
9199 01:01:15.241021 COREBOOT 8. 0xffe64000 0x00002000
9200 01:01:15.241133 IMD small region:
9201 01:01:15.244462 IMD ROOT 0. 0xffffec00 0x00000400
9202 01:01:15.247654 VPD 1. 0xffffeb80 0x0000006c
9203 01:01:15.251020 MMC STATUS 2. 0xffffeb60 0x00000004
9204 01:01:15.257812 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9205 01:01:15.264051 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9206 01:01:15.304228 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9207 01:01:15.307762 Checking segment from ROM address 0x40100000
9208 01:01:15.310948 Checking segment from ROM address 0x4010001c
9209 01:01:15.317695 Loading segment from ROM address 0x40100000
9210 01:01:15.317779 code (compression=0)
9211 01:01:15.327309 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9212 01:01:15.334061 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9213 01:01:15.334154 it's not compressed!
9214 01:01:15.340596 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9215 01:01:15.347021 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9216 01:01:15.364565 Loading segment from ROM address 0x4010001c
9217 01:01:15.364684 Entry Point 0x80000000
9218 01:01:15.367982 Loaded segments
9219 01:01:15.371223 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9220 01:01:15.377845 Jumping to boot code at 0x80000000(0xffe64000)
9221 01:01:15.384602 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9222 01:01:15.391273 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9223 01:01:15.399068 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9224 01:01:15.402348 Checking segment from ROM address 0x40100000
9225 01:01:15.405815 Checking segment from ROM address 0x4010001c
9226 01:01:15.412404 Loading segment from ROM address 0x40100000
9227 01:01:15.412496 code (compression=1)
9228 01:01:15.419072 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9229 01:01:15.428706 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9230 01:01:15.428821 using LZMA
9231 01:01:15.437335 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9232 01:01:15.443839 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9233 01:01:15.447269 Loading segment from ROM address 0x4010001c
9234 01:01:15.450609 Entry Point 0x54601000
9235 01:01:15.450691 Loaded segments
9236 01:01:15.453809 NOTICE: MT8192 bl31_setup
9237 01:01:15.460917 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9238 01:01:15.464363 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9239 01:01:15.467823 WARNING: region 0:
9240 01:01:15.471048 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9241 01:01:15.471128 WARNING: region 1:
9242 01:01:15.477574 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9243 01:01:15.481084 WARNING: region 2:
9244 01:01:15.484173 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9245 01:01:15.487793 WARNING: region 3:
9246 01:01:15.490832 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9247 01:01:15.494171 WARNING: region 4:
9248 01:01:15.500816 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9249 01:01:15.500920 WARNING: region 5:
9250 01:01:15.504289 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9251 01:01:15.507355 WARNING: region 6:
9252 01:01:15.510802 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9253 01:01:15.514009 WARNING: region 7:
9254 01:01:15.517427 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9255 01:01:15.524070 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9256 01:01:15.527257 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9257 01:01:15.530685 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9258 01:01:15.537256 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9259 01:01:15.540579 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9260 01:01:15.543907 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9261 01:01:15.550515 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9262 01:01:15.553980 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9263 01:01:15.560442 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9264 01:01:15.563827 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9265 01:01:15.567409 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9266 01:01:15.573757 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9267 01:01:15.577174 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9268 01:01:15.580489 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9269 01:01:15.587193 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9270 01:01:15.590481 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9271 01:01:15.597062 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9272 01:01:15.600543 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9273 01:01:15.603768 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9274 01:01:15.610526 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9275 01:01:15.613859 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9276 01:01:15.620422 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9277 01:01:15.623905 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9278 01:01:15.627235 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9279 01:01:15.633799 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9280 01:01:15.637155 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9281 01:01:15.643699 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9282 01:01:15.646996 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9283 01:01:15.650276 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9284 01:01:15.656982 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9285 01:01:15.660491 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9286 01:01:15.666955 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9287 01:01:15.670343 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9288 01:01:15.673590 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9289 01:01:15.677023 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9290 01:01:15.680293 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9291 01:01:15.687001 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9292 01:01:15.690024 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9293 01:01:15.693562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9294 01:01:15.700185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9295 01:01:15.703403 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9296 01:01:15.706588 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9297 01:01:15.709930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9298 01:01:15.716576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9299 01:01:15.720076 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9300 01:01:15.723314 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9301 01:01:15.726490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9302 01:01:15.733171 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9303 01:01:15.736622 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9304 01:01:15.742978 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9305 01:01:15.746273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9306 01:01:15.749720 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9307 01:01:15.756559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9308 01:01:15.759544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9309 01:01:15.766217 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9310 01:01:15.769507 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9311 01:01:15.776165 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9312 01:01:15.780002 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9313 01:01:15.783062 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9314 01:01:15.789392 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9315 01:01:15.792747 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9316 01:01:15.799422 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9317 01:01:15.802941 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9318 01:01:15.809404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9319 01:01:15.812966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9320 01:01:15.819397 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9321 01:01:15.822707 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9322 01:01:15.825950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9323 01:01:15.832606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9324 01:01:15.835850 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9325 01:01:15.842358 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9326 01:01:15.845760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9327 01:01:15.852583 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9328 01:01:15.855703 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9329 01:01:15.859055 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9330 01:01:15.865609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9331 01:01:15.869013 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9332 01:01:15.875627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9333 01:01:15.878999 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9334 01:01:15.885594 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9335 01:01:15.888979 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9336 01:01:15.895543 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9337 01:01:15.898970 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9338 01:01:15.902334 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9339 01:01:15.909262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9340 01:01:15.912150 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9341 01:01:15.918883 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9342 01:01:15.921848 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9343 01:01:15.928546 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9344 01:01:15.932034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9345 01:01:15.935297 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9346 01:01:15.942160 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9347 01:01:15.945179 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9348 01:01:15.951891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9349 01:01:15.954929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9350 01:01:15.961654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9351 01:01:15.965103 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9352 01:01:15.968338 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9353 01:01:15.974868 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9354 01:01:15.978324 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9355 01:01:15.981634 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9356 01:01:15.985032 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9357 01:01:15.991597 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9358 01:01:15.994855 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9359 01:01:16.001450 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9360 01:01:16.004828 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9361 01:01:16.008163 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9362 01:01:16.014820 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9363 01:01:16.018151 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9364 01:01:16.024524 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9365 01:01:16.027951 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9366 01:01:16.031303 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9367 01:01:16.038029 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9368 01:01:16.041336 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9369 01:01:16.047891 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9370 01:01:16.051232 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9371 01:01:16.054538 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9372 01:01:16.061156 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9373 01:01:16.064751 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9374 01:01:16.068029 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9375 01:01:16.071521 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9376 01:01:16.077830 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9377 01:01:16.081316 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9378 01:01:16.084751 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9379 01:01:16.091303 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9380 01:01:16.094506 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9381 01:01:16.097926 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9382 01:01:16.104592 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9383 01:01:16.107639 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9384 01:01:16.114478 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9385 01:01:16.117887 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9386 01:01:16.120890 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9387 01:01:16.127623 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9388 01:01:16.130917 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9389 01:01:16.137469 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9390 01:01:16.140804 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9391 01:01:16.144097 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9392 01:01:16.150651 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9393 01:01:16.154027 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9394 01:01:16.157425 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9395 01:01:16.164033 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9396 01:01:16.167289 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9397 01:01:16.174087 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9398 01:01:16.177371 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9399 01:01:16.180681 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9400 01:01:16.187372 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9401 01:01:16.190841 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9402 01:01:16.197465 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9403 01:01:16.200658 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9404 01:01:16.204064 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9405 01:01:16.210622 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9406 01:01:16.213931 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9407 01:01:16.220631 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9408 01:01:16.224045 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9409 01:01:16.227269 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9410 01:01:16.233905 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9411 01:01:16.237186 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9412 01:01:16.243804 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9413 01:01:16.247203 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9414 01:01:16.250531 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9415 01:01:16.257243 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9416 01:01:16.260651 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9417 01:01:16.263786 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9418 01:01:16.270440 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9419 01:01:16.273737 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9420 01:01:16.280488 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9421 01:01:16.283944 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9422 01:01:16.287085 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9423 01:01:16.293864 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9424 01:01:16.296990 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9425 01:01:16.303678 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9426 01:01:16.307356 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9427 01:01:16.310321 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9428 01:01:16.316889 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9429 01:01:16.320234 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9430 01:01:16.326915 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9431 01:01:16.330380 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9432 01:01:16.333722 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9433 01:01:16.340275 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9434 01:01:16.343646 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9435 01:01:16.347214 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9436 01:01:16.353784 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9437 01:01:16.357161 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9438 01:01:16.363568 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9439 01:01:16.366982 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9440 01:01:16.370127 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9441 01:01:16.376746 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9442 01:01:16.380152 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9443 01:01:16.386989 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9444 01:01:16.390093 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9445 01:01:16.393552 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9446 01:01:16.400050 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9447 01:01:16.403643 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9448 01:01:16.410009 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9449 01:01:16.413550 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9450 01:01:16.419821 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9451 01:01:16.423219 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9452 01:01:16.426516 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9453 01:01:16.433353 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9454 01:01:16.436628 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9455 01:01:16.443332 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9456 01:01:16.446719 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9457 01:01:16.449862 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9458 01:01:16.456551 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9459 01:01:16.459941 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9460 01:01:16.466674 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9461 01:01:16.470099 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9462 01:01:16.473365 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9463 01:01:16.480039 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9464 01:01:16.483180 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9465 01:01:16.489763 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9466 01:01:16.493268 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9467 01:01:16.499940 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9468 01:01:16.503199 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9469 01:01:16.506610 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9470 01:01:16.513077 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9471 01:01:16.516606 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9472 01:01:16.523141 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9473 01:01:16.526194 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9474 01:01:16.532886 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9475 01:01:16.536331 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9476 01:01:16.539544 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9477 01:01:16.546474 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9478 01:01:16.549931 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9479 01:01:16.556264 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9480 01:01:16.559498 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9481 01:01:16.563067 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9482 01:01:16.569701 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9483 01:01:16.572969 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9484 01:01:16.576148 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9485 01:01:16.582817 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9486 01:01:16.586071 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9487 01:01:16.589565 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9488 01:01:16.593033 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9489 01:01:16.599885 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9490 01:01:16.602724 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9491 01:01:16.606033 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9492 01:01:16.612857 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9493 01:01:16.616125 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9494 01:01:16.622619 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9495 01:01:16.626145 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9496 01:01:16.629410 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9497 01:01:16.636057 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9498 01:01:16.639218 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9499 01:01:16.642574 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9500 01:01:16.649532 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9501 01:01:16.652700 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9502 01:01:16.659285 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9503 01:01:16.662775 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9504 01:01:16.665809 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9505 01:01:16.672685 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9506 01:01:16.676043 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9507 01:01:16.679205 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9508 01:01:16.686664 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9509 01:01:16.689136 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9510 01:01:16.692876 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9511 01:01:16.699082 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9512 01:01:16.702292 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9513 01:01:16.705739 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9514 01:01:16.712280 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9515 01:01:16.715634 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9516 01:01:16.722126 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9517 01:01:16.725625 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9518 01:01:16.728907 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9519 01:01:16.735607 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9520 01:01:16.738772 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9521 01:01:16.742063 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9522 01:01:16.748580 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9523 01:01:16.752027 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9524 01:01:16.755206 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9525 01:01:16.761911 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9526 01:01:16.765699 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9527 01:01:16.768528 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9528 01:01:16.771931 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9529 01:01:16.775315 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9530 01:01:16.782007 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9531 01:01:16.785139 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9532 01:01:16.788483 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9533 01:01:16.791624 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9534 01:01:16.798515 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9535 01:01:16.801572 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9536 01:01:16.805352 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9537 01:01:16.811597 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9538 01:01:16.815233 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9539 01:01:16.821943 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9540 01:01:16.824931 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9541 01:01:16.828392 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9542 01:01:16.834872 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9543 01:01:16.838147 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9544 01:01:16.844874 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9545 01:01:16.848008 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9546 01:01:16.851406 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9547 01:01:16.858199 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9548 01:01:16.861239 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9549 01:01:16.867858 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9550 01:01:16.871404 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9551 01:01:16.877926 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9552 01:01:16.881176 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9553 01:01:16.884294 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9554 01:01:16.891076 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9555 01:01:16.894195 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9556 01:01:16.900822 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9557 01:01:16.904250 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9558 01:01:16.908289 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9559 01:01:16.914382 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9560 01:01:16.917556 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9561 01:01:16.924155 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9562 01:01:16.927835 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9563 01:01:16.934144 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9564 01:01:16.937781 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9565 01:01:16.940795 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9566 01:01:16.947534 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9567 01:01:16.950954 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9568 01:01:16.957207 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9569 01:01:16.960706 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9570 01:01:16.963943 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9571 01:01:16.970884 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9572 01:01:16.973892 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9573 01:01:16.980346 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9574 01:01:16.983654 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9575 01:01:16.990431 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9576 01:01:16.993866 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9577 01:01:16.997103 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9578 01:01:17.003714 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9579 01:01:17.007162 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9580 01:01:17.013636 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9581 01:01:17.016953 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9582 01:01:17.020183 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9583 01:01:17.026769 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9584 01:01:17.030416 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9585 01:01:17.037177 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9586 01:01:17.040093 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9587 01:01:17.043590 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9588 01:01:17.049975 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9589 01:01:17.053283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9590 01:01:17.060077 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9591 01:01:17.063317 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9592 01:01:17.067063 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9593 01:01:17.073081 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9594 01:01:17.076734 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9595 01:01:17.083183 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9596 01:01:17.086692 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9597 01:01:17.093196 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9598 01:01:17.096494 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9599 01:01:17.100078 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9600 01:01:17.106423 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9601 01:01:17.109727 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9602 01:01:17.112978 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9603 01:01:17.119881 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9604 01:01:17.123132 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9605 01:01:17.129839 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9606 01:01:17.133081 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9607 01:01:17.139818 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9608 01:01:17.142956 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9609 01:01:17.146202 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9610 01:01:17.153134 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9611 01:01:17.156164 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9612 01:01:17.162802 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9613 01:01:17.166243 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9614 01:01:17.172789 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9615 01:01:17.176050 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9616 01:01:17.179783 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9617 01:01:17.186100 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9618 01:01:17.189350 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9619 01:01:17.195946 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9620 01:01:17.199532 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9621 01:01:17.206077 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9622 01:01:17.209200 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9623 01:01:17.215705 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9624 01:01:17.219043 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9625 01:01:17.222633 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9626 01:01:17.228977 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9627 01:01:17.232345 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9628 01:01:17.238929 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9629 01:01:17.242157 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9630 01:01:17.248969 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9631 01:01:17.252076 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9632 01:01:17.255292 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9633 01:01:17.262055 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9634 01:01:17.265582 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9635 01:01:17.271918 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9636 01:01:17.275292 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9637 01:01:17.281809 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9638 01:01:17.285139 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9639 01:01:17.291775 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9640 01:01:17.295236 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9641 01:01:17.298503 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9642 01:01:17.304891 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9643 01:01:17.308474 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9644 01:01:17.314949 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9645 01:01:17.318310 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9646 01:01:17.325074 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9647 01:01:17.328434 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9648 01:01:17.331826 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9649 01:01:17.338342 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9650 01:01:17.341632 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9651 01:01:17.348156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9652 01:01:17.351646 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9653 01:01:17.358359 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9654 01:01:17.361754 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9655 01:01:17.368508 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9656 01:01:17.371575 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9657 01:01:17.375106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9658 01:01:17.381570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9659 01:01:17.384937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9660 01:01:17.391607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9661 01:01:17.394802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9662 01:01:17.401672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9663 01:01:17.404977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9664 01:01:17.408163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9665 01:01:17.414893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9666 01:01:17.418095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9667 01:01:17.424935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9668 01:01:17.428165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9669 01:01:17.434863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9670 01:01:17.437978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9671 01:01:17.444840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9672 01:01:17.448120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9673 01:01:17.454816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9674 01:01:17.458176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9675 01:01:17.464659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9676 01:01:17.468212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9677 01:01:17.474856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9678 01:01:17.478344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9679 01:01:17.484777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9680 01:01:17.488065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9681 01:01:17.494646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9682 01:01:17.498121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9683 01:01:17.504658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9684 01:01:17.507937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9685 01:01:17.514639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9686 01:01:17.518062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9687 01:01:17.524771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9688 01:01:17.528067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9689 01:01:17.531439 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9690 01:01:17.534585 INFO: [APUAPC] vio 0
9691 01:01:17.541298 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9692 01:01:17.544438 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9693 01:01:17.548176 INFO: [APUAPC] D0_APC_0: 0x400510
9694 01:01:17.551015 INFO: [APUAPC] D0_APC_1: 0x0
9695 01:01:17.554450 INFO: [APUAPC] D0_APC_2: 0x1540
9696 01:01:17.557578 INFO: [APUAPC] D0_APC_3: 0x0
9697 01:01:17.561258 INFO: [APUAPC] D1_APC_0: 0xffffffff
9698 01:01:17.564390 INFO: [APUAPC] D1_APC_1: 0xffffffff
9699 01:01:17.567603 INFO: [APUAPC] D1_APC_2: 0x3fffff
9700 01:01:17.570910 INFO: [APUAPC] D1_APC_3: 0x0
9701 01:01:17.574193 INFO: [APUAPC] D2_APC_0: 0xffffffff
9702 01:01:17.577824 INFO: [APUAPC] D2_APC_1: 0xffffffff
9703 01:01:17.580921 INFO: [APUAPC] D2_APC_2: 0x3fffff
9704 01:01:17.584316 INFO: [APUAPC] D2_APC_3: 0x0
9705 01:01:17.587734 INFO: [APUAPC] D3_APC_0: 0xffffffff
9706 01:01:17.590841 INFO: [APUAPC] D3_APC_1: 0xffffffff
9707 01:01:17.594112 INFO: [APUAPC] D3_APC_2: 0x3fffff
9708 01:01:17.594195 INFO: [APUAPC] D3_APC_3: 0x0
9709 01:01:17.597583 INFO: [APUAPC] D4_APC_0: 0xffffffff
9710 01:01:17.604051 INFO: [APUAPC] D4_APC_1: 0xffffffff
9711 01:01:17.607415 INFO: [APUAPC] D4_APC_2: 0x3fffff
9712 01:01:17.607502 INFO: [APUAPC] D4_APC_3: 0x0
9713 01:01:17.610733 INFO: [APUAPC] D5_APC_0: 0xffffffff
9714 01:01:17.614002 INFO: [APUAPC] D5_APC_1: 0xffffffff
9715 01:01:17.617458 INFO: [APUAPC] D5_APC_2: 0x3fffff
9716 01:01:17.620597 INFO: [APUAPC] D5_APC_3: 0x0
9717 01:01:17.624118 INFO: [APUAPC] D6_APC_0: 0xffffffff
9718 01:01:17.627432 INFO: [APUAPC] D6_APC_1: 0xffffffff
9719 01:01:17.630660 INFO: [APUAPC] D6_APC_2: 0x3fffff
9720 01:01:17.633881 INFO: [APUAPC] D6_APC_3: 0x0
9721 01:01:17.637579 INFO: [APUAPC] D7_APC_0: 0xffffffff
9722 01:01:17.640787 INFO: [APUAPC] D7_APC_1: 0xffffffff
9723 01:01:17.643909 INFO: [APUAPC] D7_APC_2: 0x3fffff
9724 01:01:17.647158 INFO: [APUAPC] D7_APC_3: 0x0
9725 01:01:17.650538 INFO: [APUAPC] D8_APC_0: 0xffffffff
9726 01:01:17.653565 INFO: [APUAPC] D8_APC_1: 0xffffffff
9727 01:01:17.656925 INFO: [APUAPC] D8_APC_2: 0x3fffff
9728 01:01:17.660208 INFO: [APUAPC] D8_APC_3: 0x0
9729 01:01:17.663652 INFO: [APUAPC] D9_APC_0: 0xffffffff
9730 01:01:17.667006 INFO: [APUAPC] D9_APC_1: 0xffffffff
9731 01:01:17.670397 INFO: [APUAPC] D9_APC_2: 0x3fffff
9732 01:01:17.673616 INFO: [APUAPC] D9_APC_3: 0x0
9733 01:01:17.676916 INFO: [APUAPC] D10_APC_0: 0xffffffff
9734 01:01:17.680285 INFO: [APUAPC] D10_APC_1: 0xffffffff
9735 01:01:17.683468 INFO: [APUAPC] D10_APC_2: 0x3fffff
9736 01:01:17.686918 INFO: [APUAPC] D10_APC_3: 0x0
9737 01:01:17.690149 INFO: [APUAPC] D11_APC_0: 0xffffffff
9738 01:01:17.693608 INFO: [APUAPC] D11_APC_1: 0xffffffff
9739 01:01:17.697007 INFO: [APUAPC] D11_APC_2: 0x3fffff
9740 01:01:17.700075 INFO: [APUAPC] D11_APC_3: 0x0
9741 01:01:17.703801 INFO: [APUAPC] D12_APC_0: 0xffffffff
9742 01:01:17.706870 INFO: [APUAPC] D12_APC_1: 0xffffffff
9743 01:01:17.710058 INFO: [APUAPC] D12_APC_2: 0x3fffff
9744 01:01:17.713585 INFO: [APUAPC] D12_APC_3: 0x0
9745 01:01:17.717036 INFO: [APUAPC] D13_APC_0: 0xffffffff
9746 01:01:17.720439 INFO: [APUAPC] D13_APC_1: 0xffffffff
9747 01:01:17.723486 INFO: [APUAPC] D13_APC_2: 0x3fffff
9748 01:01:17.726684 INFO: [APUAPC] D13_APC_3: 0x0
9749 01:01:17.730200 INFO: [APUAPC] D14_APC_0: 0xffffffff
9750 01:01:17.733576 INFO: [APUAPC] D14_APC_1: 0xffffffff
9751 01:01:17.736905 INFO: [APUAPC] D14_APC_2: 0x3fffff
9752 01:01:17.740172 INFO: [APUAPC] D14_APC_3: 0x0
9753 01:01:17.743715 INFO: [APUAPC] D15_APC_0: 0xffffffff
9754 01:01:17.747124 INFO: [APUAPC] D15_APC_1: 0xffffffff
9755 01:01:17.750129 INFO: [APUAPC] D15_APC_2: 0x3fffff
9756 01:01:17.753472 INFO: [APUAPC] D15_APC_3: 0x0
9757 01:01:17.756928 INFO: [APUAPC] APC_CON: 0x4
9758 01:01:17.760043 INFO: [NOCDAPC] D0_APC_0: 0x0
9759 01:01:17.763488 INFO: [NOCDAPC] D0_APC_1: 0x0
9760 01:01:17.766692 INFO: [NOCDAPC] D1_APC_0: 0x0
9761 01:01:17.770110 INFO: [NOCDAPC] D1_APC_1: 0xfff
9762 01:01:17.770196 INFO: [NOCDAPC] D2_APC_0: 0x0
9763 01:01:17.773639 INFO: [NOCDAPC] D2_APC_1: 0xfff
9764 01:01:17.776889 INFO: [NOCDAPC] D3_APC_0: 0x0
9765 01:01:17.780315 INFO: [NOCDAPC] D3_APC_1: 0xfff
9766 01:01:17.783499 INFO: [NOCDAPC] D4_APC_0: 0x0
9767 01:01:17.786669 INFO: [NOCDAPC] D4_APC_1: 0xfff
9768 01:01:17.789973 INFO: [NOCDAPC] D5_APC_0: 0x0
9769 01:01:17.793394 INFO: [NOCDAPC] D5_APC_1: 0xfff
9770 01:01:17.796626 INFO: [NOCDAPC] D6_APC_0: 0x0
9771 01:01:17.800091 INFO: [NOCDAPC] D6_APC_1: 0xfff
9772 01:01:17.800175 INFO: [NOCDAPC] D7_APC_0: 0x0
9773 01:01:17.803369 INFO: [NOCDAPC] D7_APC_1: 0xfff
9774 01:01:17.806589 INFO: [NOCDAPC] D8_APC_0: 0x0
9775 01:01:17.809938 INFO: [NOCDAPC] D8_APC_1: 0xfff
9776 01:01:17.813213 INFO: [NOCDAPC] D9_APC_0: 0x0
9777 01:01:17.816629 INFO: [NOCDAPC] D9_APC_1: 0xfff
9778 01:01:17.819830 INFO: [NOCDAPC] D10_APC_0: 0x0
9779 01:01:17.823211 INFO: [NOCDAPC] D10_APC_1: 0xfff
9780 01:01:17.826503 INFO: [NOCDAPC] D11_APC_0: 0x0
9781 01:01:17.829918 INFO: [NOCDAPC] D11_APC_1: 0xfff
9782 01:01:17.833174 INFO: [NOCDAPC] D12_APC_0: 0x0
9783 01:01:17.836467 INFO: [NOCDAPC] D12_APC_1: 0xfff
9784 01:01:17.839840 INFO: [NOCDAPC] D13_APC_0: 0x0
9785 01:01:17.843282 INFO: [NOCDAPC] D13_APC_1: 0xfff
9786 01:01:17.843368 INFO: [NOCDAPC] D14_APC_0: 0x0
9787 01:01:17.846474 INFO: [NOCDAPC] D14_APC_1: 0xfff
9788 01:01:17.849843 INFO: [NOCDAPC] D15_APC_0: 0x0
9789 01:01:17.853073 INFO: [NOCDAPC] D15_APC_1: 0xfff
9790 01:01:17.856346 INFO: [NOCDAPC] APC_CON: 0x4
9791 01:01:17.859713 INFO: [APUAPC] set_apusys_apc done
9792 01:01:17.862896 INFO: [DEVAPC] devapc_init done
9793 01:01:17.866154 INFO: GICv3 without legacy support detected.
9794 01:01:17.873125 INFO: ARM GICv3 driver initialized in EL3
9795 01:01:17.876201 INFO: Maximum SPI INTID supported: 639
9796 01:01:17.879527 INFO: BL31: Initializing runtime services
9797 01:01:17.886409 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9798 01:01:17.886513 INFO: SPM: enable CPC mode
9799 01:01:17.892773 INFO: mcdi ready for mcusys-off-idle and system suspend
9800 01:01:17.896411 INFO: BL31: Preparing for EL3 exit to normal world
9801 01:01:17.902840 INFO: Entry point address = 0x80000000
9802 01:01:17.902946 INFO: SPSR = 0x8
9803 01:01:17.909022
9804 01:01:17.909132
9805 01:01:17.909193
9806 01:01:17.912067 Starting depthcharge on Spherion...
9807 01:01:17.912146
9808 01:01:17.912207 Wipe memory regions:
9809 01:01:17.912264
9810 01:01:17.912855 end: 2.2.3 depthcharge-start (duration 00:00:18) [common]
9811 01:01:17.912953 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
9812 01:01:17.913032 Setting prompt string to ['asurada:']
9813 01:01:17.913106 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:28)
9814 01:01:17.915213 [0x00000040000000, 0x00000054600000)
9815 01:01:18.037561
9816 01:01:18.037708 [0x00000054660000, 0x00000080000000)
9817 01:01:18.297887
9818 01:01:18.298022 [0x000000821a7280, 0x000000ffe64000)
9819 01:01:19.041666
9820 01:01:19.041804 [0x00000100000000, 0x00000140000000)
9821 01:01:19.421199
9822 01:01:19.424334 Initializing XHCI USB controller at 0x11200000.
9823 01:01:20.462460
9824 01:01:20.465583 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9825 01:01:20.465668
9826 01:01:20.465730
9827 01:01:20.466001 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9829 01:01:20.566360 asurada: tftpboot 192.168.201.1 14368632/tftp-deploy-gyxsuv4h/kernel/image.itb 14368632/tftp-deploy-gyxsuv4h/kernel/cmdline
9830 01:01:20.566580 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9831 01:01:20.566658 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:25)
9832 01:01:20.570979 tftpboot 192.168.201.1 14368632/tftp-deploy-gyxsuv4h/kernel/image.itp-deploy-gyxsuv4h/kernel/cmdline
9833 01:01:20.571065
9834 01:01:20.571126 Waiting for link
9835 01:01:20.728998
9836 01:01:20.729137 R8152: Initializing
9837 01:01:20.729204
9838 01:01:20.732328 Version 9 (ocp_data = 6010)
9839 01:01:20.732409
9840 01:01:20.735560 R8152: Done initializing
9841 01:01:20.735645
9842 01:01:20.735706 Adding net device
9843 01:01:22.749874
9844 01:01:22.750011 done.
9845 01:01:22.750072
9846 01:01:22.750127 MAC: 00:e0:4c:68:03:bd
9847 01:01:22.750179
9848 01:01:22.753077 Sending DHCP discover... done.
9849 01:01:22.753156
9850 01:01:22.756373 Waiting for reply... done.
9851 01:01:22.756481
9852 01:01:22.759720 Sending DHCP request... done.
9853 01:01:22.759797
9854 01:01:22.759857 Waiting for reply... done.
9855 01:01:22.759912
9856 01:01:22.763207 My ip is 192.168.201.16
9857 01:01:22.763282
9858 01:01:22.766314 The DHCP server ip is 192.168.201.1
9859 01:01:22.766390
9860 01:01:22.769726 TFTP server IP predefined by user: 192.168.201.1
9861 01:01:22.769802
9862 01:01:22.776228 Bootfile predefined by user: 14368632/tftp-deploy-gyxsuv4h/kernel/image.itb
9863 01:01:22.776307
9864 01:01:22.779474 Sending tftp read request... done.
9865 01:01:22.779551
9866 01:01:22.782814 Waiting for the transfer...
9867 01:01:22.782907
9868 01:01:23.072894 00000000 ################################################################
9869 01:01:23.073025
9870 01:01:23.351017 00080000 ################################################################
9871 01:01:23.351149
9872 01:01:23.617144 00100000 ################################################################
9873 01:01:23.617297
9874 01:01:23.899561 00180000 ################################################################
9875 01:01:23.899696
9876 01:01:24.173768 00200000 ################################################################
9877 01:01:24.173921
9878 01:01:24.440032 00280000 ################################################################
9879 01:01:24.440175
9880 01:01:24.696609 00300000 ################################################################
9881 01:01:24.696744
9882 01:01:24.968865 00380000 ################################################################
9883 01:01:24.968997
9884 01:01:25.244537 00400000 ################################################################
9885 01:01:25.244672
9886 01:01:25.533613 00480000 ################################################################
9887 01:01:25.533748
9888 01:01:25.800544 00500000 ################################################################
9889 01:01:25.800685
9890 01:01:26.073856 00580000 ################################################################
9891 01:01:26.073987
9892 01:01:26.334643 00600000 ################################################################
9893 01:01:26.334777
9894 01:01:26.612705 00680000 ################################################################
9895 01:01:26.612840
9896 01:01:26.868927 00700000 ################################################################
9897 01:01:26.869061
9898 01:01:27.148300 00780000 ################################################################
9899 01:01:27.148433
9900 01:01:27.408792 00800000 ################################################################
9901 01:01:27.408928
9902 01:01:27.707030 00880000 ################################################################
9903 01:01:27.707167
9904 01:01:27.996992 00900000 ################################################################
9905 01:01:27.997126
9906 01:01:28.293271 00980000 ################################################################
9907 01:01:28.293406
9908 01:01:28.582362 00a00000 ################################################################
9909 01:01:28.582481
9910 01:01:28.860867 00a80000 ################################################################
9911 01:01:28.860999
9912 01:01:29.158837 00b00000 ################################################################
9913 01:01:29.158977
9914 01:01:29.440811 00b80000 ################################################################
9915 01:01:29.440949
9916 01:01:29.735233 00c00000 ################################################################
9917 01:01:29.735364
9918 01:01:30.002749 00c80000 ################################################################
9919 01:01:30.002888
9920 01:01:30.289397 00d00000 ################################################################
9921 01:01:30.289528
9922 01:01:30.557892 00d80000 ################################################################
9923 01:01:30.558018
9924 01:01:30.823494 00e00000 ################################################################
9925 01:01:30.823620
9926 01:01:31.087560 00e80000 ################################################################
9927 01:01:31.087692
9928 01:01:31.356171 00f00000 ################################################################
9929 01:01:31.356301
9930 01:01:31.643853 00f80000 ################################################################
9931 01:01:31.643987
9932 01:01:31.924580 01000000 ################################################################
9933 01:01:31.924710
9934 01:01:32.206369 01080000 ################################################################
9935 01:01:32.206497
9936 01:01:32.467160 01100000 ################################################################
9937 01:01:32.467290
9938 01:01:32.726687 01180000 ################################################################
9939 01:01:32.726842
9940 01:01:32.985057 01200000 ################################################################
9941 01:01:32.985204
9942 01:01:33.247555 01280000 ################################################################
9943 01:01:33.247681
9944 01:01:33.522177 01300000 ################################################################
9945 01:01:33.522329
9946 01:01:33.810572 01380000 ################################################################
9947 01:01:33.810701
9948 01:01:34.070372 01400000 ################################################################
9949 01:01:34.070500
9950 01:01:34.330023 01480000 ################################################################
9951 01:01:34.330191
9952 01:01:34.608572 01500000 ################################################################
9953 01:01:34.608705
9954 01:01:34.871078 01580000 ################################################################
9955 01:01:34.871211
9956 01:01:35.142526 01600000 ################################################################
9957 01:01:35.142657
9958 01:01:35.405039 01680000 ################################################################
9959 01:01:35.405167
9960 01:01:35.676645 01700000 ################################################################
9961 01:01:35.676773
9962 01:01:35.938640 01780000 ################################################################
9963 01:01:35.938770
9964 01:01:36.192560 01800000 ################################################################
9965 01:01:36.192715
9966 01:01:36.450828 01880000 ################################################################
9967 01:01:36.450956
9968 01:01:36.720897 01900000 ################################################################
9969 01:01:36.721026
9970 01:01:36.974254 01980000 ################################################################
9971 01:01:36.974398
9972 01:01:37.244270 01a00000 ################################################################
9973 01:01:37.244401
9974 01:01:37.505834 01a80000 ################################################################
9975 01:01:37.505961
9976 01:01:37.786685 01b00000 ################################################################
9977 01:01:37.786814
9978 01:01:38.067909 01b80000 ################################################################
9979 01:01:38.068038
9980 01:01:38.320745 01c00000 ################################################################
9981 01:01:38.320875
9982 01:01:38.577463 01c80000 ################################################################
9983 01:01:38.577589
9984 01:01:38.834826 01d00000 ################################################################
9985 01:01:38.834954
9986 01:01:39.099829 01d80000 ################################################################
9987 01:01:39.099958
9988 01:01:39.352280 01e00000 ####################################################### done.
9989 01:01:39.352751
9990 01:01:39.355734 The bootfile was 31906946 bytes long.
9991 01:01:39.356187
9992 01:01:39.358932 Sending tftp read request... done.
9993 01:01:39.359332
9994 01:01:39.363036 Waiting for the transfer...
9995 01:01:39.363439
9996 01:01:39.363749 00000000 # done.
9997 01:01:39.364045
9998 01:01:39.369867 Command line loaded dynamically from TFTP file: 14368632/tftp-deploy-gyxsuv4h/kernel/cmdline
9999 01:01:39.373093
10000 01:01:39.392842 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368632/extract-nfsrootfs-n8p_9uxc,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10001 01:01:39.393395
10002 01:01:39.396057 Loading FIT.
10003 01:01:39.396493
10004 01:01:39.396834 Image ramdisk-1 has 18732614 bytes.
10005 01:01:39.400277
10006 01:01:39.400803 Image fdt-1 has 47258 bytes.
10007 01:01:39.401152
10008 01:01:39.402612 Image kernel-1 has 13125045 bytes.
10009 01:01:39.402982
10010 01:01:39.413343 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10011 01:01:39.413932
10012 01:01:39.429362 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10013 01:01:39.429900
10014 01:01:39.436166 Choosing best match conf-1 for compat google,spherion-rev3.
10015 01:01:39.439414
10016 01:01:39.444163 Connected to device vid:did:rid of 1ae0:0028:00
10017 01:01:39.452285
10018 01:01:39.455760 tpm_get_response: command 0x17b, return code 0x0
10019 01:01:39.456319
10020 01:01:39.458799 ec_init: CrosEC protocol v3 supported (256, 248)
10021 01:01:39.463086
10022 01:01:39.466477 tpm_cleanup: add release locality here.
10023 01:01:39.467064
10024 01:01:39.467422 Shutting down all USB controllers.
10025 01:01:39.469832
10026 01:01:39.470316 Removing current net device
10027 01:01:39.470670
10028 01:01:39.476661 Exiting depthcharge with code 4 at timestamp: 49795558
10029 01:01:39.477203
10030 01:01:39.480140 LZMA decompressing kernel-1 to 0x821a6718
10031 01:01:39.480786
10032 01:01:39.482765 LZMA decompressing kernel-1 to 0x40000000
10033 01:01:41.098484
10034 01:01:41.098786 jumping to kernel
10035 01:01:41.099756 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10036 01:01:41.100031 start: 2.2.5 auto-login-action (timeout 00:04:05) [common]
10037 01:01:41.100248 Setting prompt string to ['Linux version [0-9]']
10038 01:01:41.100397 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10039 01:01:41.100548 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10040 01:01:41.148541
10041 01:01:41.152055 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10042 01:01:41.156218 start: 2.2.5.1 login-action (timeout 00:04:05) [common]
10043 01:01:41.156748 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10044 01:01:41.157132 Setting prompt string to []
10045 01:01:41.157551 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10046 01:01:41.157996 Using line separator: #'\n'#
10047 01:01:41.158375 No login prompt set.
10048 01:01:41.158707 Parsing kernel messages
10049 01:01:41.158998 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10050 01:01:41.159527 [login-action] Waiting for messages, (timeout 00:04:05)
10051 01:01:41.159878 Waiting using forced prompt support (timeout 00:02:02)
10052 01:01:41.175860 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
10053 01:01:41.178420 [ 0.000000] random: crng init done
10054 01:01:41.185088 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10055 01:01:41.188369 [ 0.000000] efi: UEFI not found.
10056 01:01:41.195030 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10057 01:01:41.201563 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10058 01:01:41.211383 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10059 01:01:41.221314 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10060 01:01:41.227526 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10061 01:01:41.234119 [ 0.000000] printk: bootconsole [mtk8250] enabled
10062 01:01:41.241202 [ 0.000000] NUMA: No NUMA configuration found
10063 01:01:41.247422 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10064 01:01:41.250861 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10065 01:01:41.254234 [ 0.000000] Zone ranges:
10066 01:01:41.260855 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10067 01:01:41.263936 [ 0.000000] DMA32 empty
10068 01:01:41.270489 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10069 01:01:41.273745 [ 0.000000] Movable zone start for each node
10070 01:01:41.277031 [ 0.000000] Early memory node ranges
10071 01:01:41.284085 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10072 01:01:41.290483 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10073 01:01:41.296997 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10074 01:01:41.303499 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10075 01:01:41.310194 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10076 01:01:41.316676 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10077 01:01:41.347277 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10078 01:01:41.354283 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10079 01:01:41.360762 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10080 01:01:41.363877 [ 0.000000] psci: probing for conduit method from DT.
10081 01:01:41.370282 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10082 01:01:41.373541 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10083 01:01:41.380283 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10084 01:01:41.383517 [ 0.000000] psci: SMC Calling Convention v1.2
10085 01:01:41.390251 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10086 01:01:41.393624 [ 0.000000] Detected VIPT I-cache on CPU0
10087 01:01:41.400168 [ 0.000000] CPU features: detected: GIC system register CPU interface
10088 01:01:41.406348 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10089 01:01:41.413267 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10090 01:01:41.419525 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10091 01:01:41.429805 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10092 01:01:41.436366 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10093 01:01:41.440120 [ 0.000000] alternatives: applying boot alternatives
10094 01:01:41.446505 [ 0.000000] Fallback order for Node 0: 0
10095 01:01:41.453260 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10096 01:01:41.456580 [ 0.000000] Policy zone: Normal
10097 01:01:41.479545 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368632/extract-nfsrootfs-n8p_9uxc,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10098 01:01:41.489746 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10099 01:01:41.499393 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10100 01:01:41.506252 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10101 01:01:41.512723 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10102 01:01:41.519379 <6>[ 0.000000] software IO TLB: area num 8.
10103 01:01:41.574506 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10104 01:01:41.654939 <6>[ 0.000000] Memory: 3831356K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 327108K reserved, 32768K cma-reserved)
10105 01:01:41.661389 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10106 01:01:41.667901 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10107 01:01:41.671024 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10108 01:01:41.678096 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10109 01:01:41.684251 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10110 01:01:41.687789 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10111 01:01:41.697752 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10112 01:01:41.704623 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10113 01:01:41.710667 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10114 01:01:41.717835 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10115 01:01:41.720545 <6>[ 0.000000] GICv3: 608 SPIs implemented
10116 01:01:41.726881 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10117 01:01:41.730673 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10118 01:01:41.733787 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10119 01:01:41.740970 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10120 01:01:41.753443 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10121 01:01:41.766917 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10122 01:01:41.773368 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10123 01:01:41.781693 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10124 01:01:41.794277 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10125 01:01:41.801360 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10126 01:01:41.808293 <6>[ 0.009227] Console: colour dummy device 80x25
10127 01:01:41.818187 <6>[ 0.013953] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10128 01:01:41.824613 <6>[ 0.024394] pid_max: default: 32768 minimum: 301
10129 01:01:41.828010 <6>[ 0.029295] LSM: Security Framework initializing
10130 01:01:41.834401 <6>[ 0.034208] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10131 01:01:41.844102 <6>[ 0.041815] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10132 01:01:41.850579 <6>[ 0.051095] cblist_init_generic: Setting adjustable number of callback queues.
10133 01:01:41.857282 <6>[ 0.058538] cblist_init_generic: Setting shift to 3 and lim to 1.
10134 01:01:41.867253 <6>[ 0.064912] cblist_init_generic: Setting adjustable number of callback queues.
10135 01:01:41.873714 <6>[ 0.072339] cblist_init_generic: Setting shift to 3 and lim to 1.
10136 01:01:41.877019 <6>[ 0.078737] rcu: Hierarchical SRCU implementation.
10137 01:01:41.883821 <6>[ 0.083752] rcu: Max phase no-delay instances is 1000.
10138 01:01:41.890462 <6>[ 0.090783] EFI services will not be available.
10139 01:01:41.893526 <6>[ 0.095734] smp: Bringing up secondary CPUs ...
10140 01:01:41.901654 <6>[ 0.100781] Detected VIPT I-cache on CPU1
10141 01:01:41.908279 <6>[ 0.100850] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10142 01:01:41.915166 <6>[ 0.100880] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10143 01:01:41.918366 <6>[ 0.101212] Detected VIPT I-cache on CPU2
10144 01:01:41.924900 <6>[ 0.101263] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10145 01:01:41.934915 <6>[ 0.101282] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10146 01:01:41.938162 <6>[ 0.101541] Detected VIPT I-cache on CPU3
10147 01:01:41.944535 <6>[ 0.101589] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10148 01:01:41.951174 <6>[ 0.101604] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10149 01:01:41.954723 <6>[ 0.101905] CPU features: detected: Spectre-v4
10150 01:01:41.961420 <6>[ 0.101911] CPU features: detected: Spectre-BHB
10151 01:01:41.964520 <6>[ 0.101915] Detected PIPT I-cache on CPU4
10152 01:01:41.971156 <6>[ 0.101973] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10153 01:01:41.977589 <6>[ 0.101989] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10154 01:01:41.984398 <6>[ 0.102283] Detected PIPT I-cache on CPU5
10155 01:01:41.990874 <6>[ 0.102344] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10156 01:01:41.997892 <6>[ 0.102360] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10157 01:01:42.001366 <6>[ 0.102640] Detected PIPT I-cache on CPU6
10158 01:01:42.007440 <6>[ 0.102702] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10159 01:01:42.013887 <6>[ 0.102718] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10160 01:01:42.020729 <6>[ 0.103016] Detected PIPT I-cache on CPU7
10161 01:01:42.027462 <6>[ 0.103081] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10162 01:01:42.033888 <6>[ 0.103097] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10163 01:01:42.037155 <6>[ 0.103143] smp: Brought up 1 node, 8 CPUs
10164 01:01:42.043797 <6>[ 0.244421] SMP: Total of 8 processors activated.
10165 01:01:42.047160 <6>[ 0.249342] CPU features: detected: 32-bit EL0 Support
10166 01:01:42.056887 <6>[ 0.254705] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10167 01:01:42.063841 <6>[ 0.263560] CPU features: detected: Common not Private translations
10168 01:01:42.070099 <6>[ 0.270036] CPU features: detected: CRC32 instructions
10169 01:01:42.073406 <6>[ 0.275388] CPU features: detected: RCpc load-acquire (LDAPR)
10170 01:01:42.080101 <6>[ 0.281347] CPU features: detected: LSE atomic instructions
10171 01:01:42.086480 <6>[ 0.287164] CPU features: detected: Privileged Access Never
10172 01:01:42.093365 <6>[ 0.292944] CPU features: detected: RAS Extension Support
10173 01:01:42.100448 <6>[ 0.298553] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10174 01:01:42.103231 <6>[ 0.305819] CPU: All CPU(s) started at EL2
10175 01:01:42.109802 <6>[ 0.310136] alternatives: applying system-wide alternatives
10176 01:01:42.118591 <6>[ 0.320125] devtmpfs: initialized
10177 01:01:42.130467 <6>[ 0.328278] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10178 01:01:42.140413 <6>[ 0.338234] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10179 01:01:42.146497 <6>[ 0.346259] pinctrl core: initialized pinctrl subsystem
10180 01:01:42.150099 <6>[ 0.352949] DMI not present or invalid.
10181 01:01:42.156475 <6>[ 0.357351] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10182 01:01:42.166392 <6>[ 0.364190] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10183 01:01:42.172914 <6>[ 0.371640] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10184 01:01:42.182933 <6>[ 0.379734] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10185 01:01:42.186332 <6>[ 0.387891] audit: initializing netlink subsys (disabled)
10186 01:01:42.195765 <5>[ 0.393587] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10187 01:01:42.202715 <6>[ 0.394302] thermal_sys: Registered thermal governor 'step_wise'
10188 01:01:42.209155 <6>[ 0.401553] thermal_sys: Registered thermal governor 'power_allocator'
10189 01:01:42.212990 <6>[ 0.407808] cpuidle: using governor menu
10190 01:01:42.219132 <6>[ 0.418767] NET: Registered PF_QIPCRTR protocol family
10191 01:01:42.225954 <6>[ 0.424251] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10192 01:01:42.228823 <6>[ 0.431352] ASID allocator initialised with 32768 entries
10193 01:01:42.236399 <6>[ 0.437914] Serial: AMBA PL011 UART driver
10194 01:01:42.245502 <4>[ 0.446739] Trying to register duplicate clock ID: 134
10195 01:01:42.303734 <6>[ 0.508400] KASLR enabled
10196 01:01:42.318296 <6>[ 0.516131] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10197 01:01:42.324650 <6>[ 0.523146] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10198 01:01:42.331260 <6>[ 0.529633] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10199 01:01:42.338316 <6>[ 0.536639] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10200 01:01:42.344888 <6>[ 0.543126] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10201 01:01:42.351317 <6>[ 0.550132] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10202 01:01:42.357692 <6>[ 0.556618] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10203 01:01:42.364444 <6>[ 0.563621] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10204 01:01:42.367338 <6>[ 0.571134] ACPI: Interpreter disabled.
10205 01:01:42.376125 <6>[ 0.577556] iommu: Default domain type: Translated
10206 01:01:42.382833 <6>[ 0.582667] iommu: DMA domain TLB invalidation policy: strict mode
10207 01:01:42.386414 <5>[ 0.589325] SCSI subsystem initialized
10208 01:01:42.392890 <6>[ 0.593489] usbcore: registered new interface driver usbfs
10209 01:01:42.399188 <6>[ 0.599222] usbcore: registered new interface driver hub
10210 01:01:42.402545 <6>[ 0.604775] usbcore: registered new device driver usb
10211 01:01:42.409500 <6>[ 0.610869] pps_core: LinuxPPS API ver. 1 registered
10212 01:01:42.419375 <6>[ 0.616062] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10213 01:01:42.422691 <6>[ 0.625410] PTP clock support registered
10214 01:01:42.426350 <6>[ 0.629653] EDAC MC: Ver: 3.0.0
10215 01:01:42.433544 <6>[ 0.634804] FPGA manager framework
10216 01:01:42.440139 <6>[ 0.638489] Advanced Linux Sound Architecture Driver Initialized.
10217 01:01:42.443371 <6>[ 0.645258] vgaarb: loaded
10218 01:01:42.450333 <6>[ 0.648413] clocksource: Switched to clocksource arch_sys_counter
10219 01:01:42.453306 <5>[ 0.654853] VFS: Disk quotas dquot_6.6.0
10220 01:01:42.459663 <6>[ 0.659038] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10221 01:01:42.462847 <6>[ 0.666226] pnp: PnP ACPI: disabled
10222 01:01:42.471617 <6>[ 0.672925] NET: Registered PF_INET protocol family
10223 01:01:42.477871 <6>[ 0.678303] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10224 01:01:42.490377 <6>[ 0.688326] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10225 01:01:42.499822 <6>[ 0.697116] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10226 01:01:42.507014 <6>[ 0.705080] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10227 01:01:42.513465 <6>[ 0.713482] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10228 01:01:42.523987 <6>[ 0.722139] TCP: Hash tables configured (established 32768 bind 32768)
10229 01:01:42.530844 <6>[ 0.728997] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10230 01:01:42.537193 <6>[ 0.736017] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10231 01:01:42.544522 <6>[ 0.743517] NET: Registered PF_UNIX/PF_LOCAL protocol family
10232 01:01:42.550534 <6>[ 0.749642] RPC: Registered named UNIX socket transport module.
10233 01:01:42.553495 <6>[ 0.755795] RPC: Registered udp transport module.
10234 01:01:42.560239 <6>[ 0.760729] RPC: Registered tcp transport module.
10235 01:01:42.567061 <6>[ 0.765662] RPC: Registered tcp NFSv4.1 backchannel transport module.
10236 01:01:42.570266 <6>[ 0.772329] PCI: CLS 0 bytes, default 64
10237 01:01:42.573581 <6>[ 0.776628] Unpacking initramfs...
10238 01:01:42.602857 <6>[ 0.800976] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10239 01:01:42.612927 <6>[ 0.809631] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10240 01:01:42.615922 <6>[ 0.818465] kvm [1]: IPA Size Limit: 40 bits
10241 01:01:42.622847 <6>[ 0.822994] kvm [1]: GICv3: no GICV resource entry
10242 01:01:42.626016 <6>[ 0.828020] kvm [1]: disabling GICv2 emulation
10243 01:01:42.632701 <6>[ 0.832708] kvm [1]: GIC system register CPU interface enabled
10244 01:01:42.636023 <6>[ 0.838873] kvm [1]: vgic interrupt IRQ18
10245 01:01:42.642379 <6>[ 0.843224] kvm [1]: VHE mode initialized successfully
10246 01:01:42.649552 <5>[ 0.849719] Initialise system trusted keyrings
10247 01:01:42.655487 <6>[ 0.854540] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10248 01:01:42.663495 <6>[ 0.864509] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10249 01:01:42.669877 <5>[ 0.870876] NFS: Registering the id_resolver key type
10250 01:01:42.673197 <5>[ 0.876174] Key type id_resolver registered
10251 01:01:42.679778 <5>[ 0.880589] Key type id_legacy registered
10252 01:01:42.686347 <6>[ 0.884869] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10253 01:01:42.692708 <6>[ 0.891789] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10254 01:01:42.699703 <6>[ 0.899517] 9p: Installing v9fs 9p2000 file system support
10255 01:01:42.735933 <5>[ 0.937346] Key type asymmetric registered
10256 01:01:42.738975 <5>[ 0.941678] Asymmetric key parser 'x509' registered
10257 01:01:42.749389 <6>[ 0.946824] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10258 01:01:42.752268 <6>[ 0.954460] io scheduler mq-deadline registered
10259 01:01:42.755455 <6>[ 0.959242] io scheduler kyber registered
10260 01:01:42.775455 <6>[ 0.976463] EINJ: ACPI disabled.
10261 01:01:42.808049 <4>[ 1.002871] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10262 01:01:42.818193 <4>[ 1.013531] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10263 01:01:42.833358 <6>[ 1.034498] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10264 01:01:42.841269 <6>[ 1.042547] printk: console [ttyS0] disabled
10265 01:01:42.869209 <6>[ 1.067188] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10266 01:01:42.875996 <6>[ 1.076667] printk: console [ttyS0] enabled
10267 01:01:42.879209 <6>[ 1.076667] printk: console [ttyS0] enabled
10268 01:01:42.885522 <6>[ 1.085561] printk: bootconsole [mtk8250] disabled
10269 01:01:42.889073 <6>[ 1.085561] printk: bootconsole [mtk8250] disabled
10270 01:01:42.895328 <6>[ 1.096910] SuperH (H)SCI(F) driver initialized
10271 01:01:42.899040 <6>[ 1.102183] msm_serial: driver initialized
10272 01:01:42.913484 <6>[ 1.111228] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10273 01:01:42.923107 <6>[ 1.119793] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10274 01:01:42.929647 <6>[ 1.128335] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10275 01:01:42.939966 <6>[ 1.136968] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10276 01:01:42.950041 <6>[ 1.145674] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10277 01:01:42.956473 <6>[ 1.154393] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10278 01:01:42.966168 <6>[ 1.162935] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10279 01:01:42.972496 <6>[ 1.171740] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10280 01:01:42.982851 <6>[ 1.180283] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10281 01:01:42.994635 <6>[ 1.195934] loop: module loaded
10282 01:01:43.001229 <6>[ 1.201898] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10283 01:01:43.023731 <4>[ 1.225120] mtk-pmic-keys: Failed to locate of_node [id: -1]
10284 01:01:43.030578 <6>[ 1.232170] megasas: 07.719.03.00-rc1
10285 01:01:43.040566 <6>[ 1.242040] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10286 01:01:43.047366 <6>[ 1.243852] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10287 01:01:43.062804 <6>[ 1.263910] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10288 01:01:43.118866 <6>[ 1.313727] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10289 01:01:43.362092 <6>[ 1.563536] Freeing initrd memory: 18288K
10290 01:01:43.373485 <6>[ 1.575212] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10291 01:01:43.384497 <6>[ 1.586231] tun: Universal TUN/TAP device driver, 1.6
10292 01:01:43.388084 <6>[ 1.592305] thunder_xcv, ver 1.0
10293 01:01:43.391606 <6>[ 1.595812] thunder_bgx, ver 1.0
10294 01:01:43.394796 <6>[ 1.599311] nicpf, ver 1.0
10295 01:01:43.404863 <6>[ 1.603334] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10296 01:01:43.408157 <6>[ 1.610811] hns3: Copyright (c) 2017 Huawei Corporation.
10297 01:01:43.415002 <6>[ 1.616398] hclge is initializing
10298 01:01:43.418102 <6>[ 1.619982] e1000: Intel(R) PRO/1000 Network Driver
10299 01:01:43.424692 <6>[ 1.625110] e1000: Copyright (c) 1999-2006 Intel Corporation.
10300 01:01:43.428250 <6>[ 1.631126] e1000e: Intel(R) PRO/1000 Network Driver
10301 01:01:43.434769 <6>[ 1.636341] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10302 01:01:43.441430 <6>[ 1.642529] igb: Intel(R) Gigabit Ethernet Network Driver
10303 01:01:43.448166 <6>[ 1.648180] igb: Copyright (c) 2007-2014 Intel Corporation.
10304 01:01:43.454985 <6>[ 1.654015] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10305 01:01:43.461301 <6>[ 1.660532] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10306 01:01:43.464791 <6>[ 1.666996] sky2: driver version 1.30
10307 01:01:43.471569 <6>[ 1.671921] usbcore: registered new device driver r8152-cfgselector
10308 01:01:43.478381 <6>[ 1.678458] usbcore: registered new interface driver r8152
10309 01:01:43.484804 <6>[ 1.684277] VFIO - User Level meta-driver version: 0.3
10310 01:01:43.491701 <6>[ 1.692515] usbcore: registered new interface driver usb-storage
10311 01:01:43.498008 <6>[ 1.698955] usbcore: registered new device driver onboard-usb-hub
10312 01:01:43.506753 <6>[ 1.708133] mt6397-rtc mt6359-rtc: registered as rtc0
10313 01:01:43.516583 <6>[ 1.713601] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T01:01:43 UTC (1718499703)
10314 01:01:43.520346 <6>[ 1.723170] i2c_dev: i2c /dev entries driver
10315 01:01:43.533897 <4>[ 1.735187] cpu cpu0: supply cpu not found, using dummy regulator
10316 01:01:43.540683 <4>[ 1.741612] cpu cpu1: supply cpu not found, using dummy regulator
10317 01:01:43.546963 <4>[ 1.748033] cpu cpu2: supply cpu not found, using dummy regulator
10318 01:01:43.553779 <4>[ 1.754432] cpu cpu3: supply cpu not found, using dummy regulator
10319 01:01:43.560574 <4>[ 1.760827] cpu cpu4: supply cpu not found, using dummy regulator
10320 01:01:43.567112 <4>[ 1.767231] cpu cpu5: supply cpu not found, using dummy regulator
10321 01:01:43.573588 <4>[ 1.773626] cpu cpu6: supply cpu not found, using dummy regulator
10322 01:01:43.580134 <4>[ 1.780037] cpu cpu7: supply cpu not found, using dummy regulator
10323 01:01:43.599955 <6>[ 1.801660] cpu cpu0: EM: created perf domain
10324 01:01:43.603446 <6>[ 1.806585] cpu cpu4: EM: created perf domain
10325 01:01:43.610977 <6>[ 1.812146] sdhci: Secure Digital Host Controller Interface driver
10326 01:01:43.617784 <6>[ 1.818579] sdhci: Copyright(c) Pierre Ossman
10327 01:01:43.624004 <6>[ 1.823490] Synopsys Designware Multimedia Card Interface Driver
10328 01:01:43.631171 <6>[ 1.830085] sdhci-pltfm: SDHCI platform and OF driver helper
10329 01:01:43.634272 <6>[ 1.830253] mmc0: CQHCI version 5.10
10330 01:01:43.640882 <6>[ 1.840141] ledtrig-cpu: registered to indicate activity on CPUs
10331 01:01:43.647078 <6>[ 1.847221] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10332 01:01:43.654170 <6>[ 1.854254] usbcore: registered new interface driver usbhid
10333 01:01:43.657225 <6>[ 1.860075] usbhid: USB HID core driver
10334 01:01:43.663802 <6>[ 1.864265] spi_master spi0: will run message pump with realtime priority
10335 01:01:43.926154 <6>[ 2.121324] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10336 01:01:43.945119 <6>[ 2.136566] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10337 01:01:43.948067 <6>[ 2.149061] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16414
10338 01:01:43.955540 <6>[ 2.157141] cros-ec-spi spi0.0: Chrome EC device registered
10339 01:01:43.962096 <6>[ 2.163280] mmc0: Command Queue Engine enabled
10340 01:01:43.968804 <6>[ 2.168074] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10341 01:01:43.972411 <6>[ 2.175628] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10342 01:01:43.983058 <6>[ 2.184673] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10343 01:01:43.990699 <6>[ 2.192080] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10344 01:01:43.997099 <6>[ 2.198229] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10345 01:01:44.007087 <6>[ 2.198538] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10346 01:01:44.013964 <6>[ 2.204174] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10347 01:01:44.016777 <6>[ 2.214560] NET: Registered PF_PACKET protocol family
10348 01:01:44.023672 <6>[ 2.224710] 9pnet: Installing 9P2000 support
10349 01:01:44.026886 <5>[ 2.229284] Key type dns_resolver registered
10350 01:01:44.033774 <6>[ 2.234325] registered taskstats version 1
10351 01:01:44.036991 <5>[ 2.238715] Loading compiled-in X.509 certificates
10352 01:01:44.074909 <4>[ 2.269692] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10353 01:01:44.084709 <4>[ 2.280640] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10354 01:01:44.101555 <6>[ 2.302583] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10355 01:01:44.108393 <6>[ 2.309506] xhci-mtk 11200000.usb: xHCI Host Controller
10356 01:01:44.114815 <6>[ 2.315009] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10357 01:01:44.124618 <6>[ 2.322846] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10358 01:01:44.131404 <6>[ 2.332276] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10359 01:01:44.138510 <6>[ 2.338364] xhci-mtk 11200000.usb: xHCI Host Controller
10360 01:01:44.144691 <6>[ 2.343851] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10361 01:01:44.151051 <6>[ 2.351503] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10362 01:01:44.158044 <6>[ 2.359159] hub 1-0:1.0: USB hub found
10363 01:01:44.160982 <6>[ 2.363170] hub 1-0:1.0: 1 port detected
10364 01:01:44.167824 <6>[ 2.367437] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10365 01:01:44.174169 <6>[ 2.375936] hub 2-0:1.0: USB hub found
10366 01:01:44.177418 <6>[ 2.379940] hub 2-0:1.0: 1 port detected
10367 01:01:44.185260 <6>[ 2.386971] mtk-msdc 11f70000.mmc: Got CD GPIO
10368 01:01:44.203322 <6>[ 2.400988] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10369 01:01:44.212714 <6>[ 2.409389] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10370 01:01:44.219594 <6>[ 2.417734] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10371 01:01:44.229135 <6>[ 2.426073] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10372 01:01:44.236020 <6>[ 2.434411] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10373 01:01:44.245937 <6>[ 2.442749] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10374 01:01:44.252587 <6>[ 2.451086] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10375 01:01:44.262177 <6>[ 2.459424] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10376 01:01:44.269015 <6>[ 2.467761] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10377 01:01:44.278834 <6>[ 2.476099] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10378 01:01:44.285451 <6>[ 2.484451] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10379 01:01:44.295547 <6>[ 2.492789] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10380 01:01:44.302065 <6>[ 2.501126] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10381 01:01:44.311885 <6>[ 2.509463] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10382 01:01:44.318868 <6>[ 2.517800] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10383 01:01:44.325219 <6>[ 2.526499] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10384 01:01:44.332134 <6>[ 2.533668] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10385 01:01:44.338723 <6>[ 2.540433] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10386 01:01:44.349050 <6>[ 2.547174] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10387 01:01:44.355530 <6>[ 2.554126] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10388 01:01:44.361917 <6>[ 2.560980] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10389 01:01:44.372428 <6>[ 2.570110] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10390 01:01:44.381877 <6>[ 2.579229] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10391 01:01:44.391755 <6>[ 2.588524] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10392 01:01:44.401978 <6>[ 2.597991] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10393 01:01:44.408211 <6>[ 2.607458] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10394 01:01:44.418252 <6>[ 2.616577] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10395 01:01:44.427950 <6>[ 2.626043] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10396 01:01:44.438442 <6>[ 2.635162] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10397 01:01:44.448284 <6>[ 2.644459] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10398 01:01:44.457673 <6>[ 2.654619] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10399 01:01:44.468519 <6>[ 2.666526] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10400 01:01:44.475946 <6>[ 2.677676] Trying to probe devices needed for running init ...
10401 01:01:44.486585 <3>[ 2.684939] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10402 01:01:44.566773 <6>[ 2.764984] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10403 01:01:44.595515 <6>[ 2.796657] hub 2-1:1.0: USB hub found
10404 01:01:44.598295 <6>[ 2.801158] hub 2-1:1.0: 3 ports detected
10405 01:01:44.608948 <6>[ 2.810602] hub 2-1:1.0: USB hub found
10406 01:01:44.612342 <6>[ 2.814979] hub 2-1:1.0: 3 ports detected
10407 01:01:44.718365 <6>[ 2.916701] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10408 01:01:44.872764 <6>[ 3.074354] hub 1-1:1.0: USB hub found
10409 01:01:44.875874 <6>[ 3.078830] hub 1-1:1.0: 4 ports detected
10410 01:01:44.888708 <6>[ 3.090403] hub 1-1:1.0: USB hub found
10411 01:01:44.892002 <6>[ 3.094801] hub 1-1:1.0: 4 ports detected
10412 01:01:44.950602 <6>[ 3.148941] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10413 01:01:45.059442 <6>[ 3.257351] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10414 01:01:45.094666 <4>[ 3.292978] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10415 01:01:45.104700 <4>[ 3.302126] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10416 01:01:45.143808 <6>[ 3.345331] r8152 2-1.3:1.0 eth0: v1.12.13
10417 01:01:45.218613 <6>[ 3.416668] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10418 01:01:45.351275 <6>[ 3.552622] hub 1-1.4:1.0: USB hub found
10419 01:01:45.354750 <6>[ 3.557289] hub 1-1.4:1.0: 2 ports detected
10420 01:01:45.368491 <6>[ 3.570157] hub 1-1.4:1.0: USB hub found
10421 01:01:45.371883 <6>[ 3.574777] hub 1-1.4:1.0: 2 ports detected
10422 01:01:45.670388 <6>[ 3.868721] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10423 01:01:45.866064 <6>[ 4.064769] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10424 01:01:46.769626 <6>[ 4.971583] r8152 2-1.3:1.0 eth0: carrier on
10425 01:01:48.914615 <5>[ 4.996460] Sending DHCP requests .., OK
10426 01:01:48.921265 <6>[ 7.120876] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10427 01:01:48.924623 <6>[ 7.129170] IP-Config: Complete:
10428 01:01:48.937757 <6>[ 7.132671] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10429 01:01:48.944790 <6>[ 7.143392] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10430 01:01:48.950768 <6>[ 7.152010] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10431 01:01:48.958102 <6>[ 7.152019] nameserver0=192.168.201.1
10432 01:01:48.960725 <6>[ 7.164148] clk: Disabling unused clocks
10433 01:01:48.964248 <6>[ 7.169644] ALSA device list:
10434 01:01:48.971113 <6>[ 7.172912] No soundcards found.
10435 01:01:48.977930 <6>[ 7.180092] Freeing unused kernel memory: 8512K
10436 01:01:48.981813 <6>[ 7.185109] Run /init as init process
10437 01:01:48.991337 Loading, please wait...
10438 01:01:49.016837 Starting systemd-udevd version 252.22-1~deb12u1
10439 01:01:49.217560 <6>[ 7.415910] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10440 01:01:49.238014 <6>[ 7.439945] remoteproc remoteproc0: scp is available
10441 01:01:49.244699 <6>[ 7.445302] remoteproc remoteproc0: powering up scp
10442 01:01:49.251014 <6>[ 7.449369] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10443 01:01:49.261550 <6>[ 7.450445] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10444 01:01:49.267361 <6>[ 7.459782] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10445 01:01:49.274093 <6>[ 7.466525] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10446 01:01:49.280733 <6>[ 7.476377] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10447 01:01:49.291918 <4>[ 7.490654] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10448 01:01:49.298258 <4>[ 7.498801] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10449 01:01:49.310163 <3>[ 7.508732] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10450 01:01:49.316834 <3>[ 7.516900] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10451 01:01:49.326574 <6>[ 7.517248] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10452 01:01:49.333612 <3>[ 7.525000] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10453 01:01:49.343239 <6>[ 7.525643] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10454 01:01:49.350288 <3>[ 7.526929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10455 01:01:49.359739 <3>[ 7.526975] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10456 01:01:49.366478 <3>[ 7.526990] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10457 01:01:49.372975 <3>[ 7.527019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10458 01:01:49.382977 <3>[ 7.527032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10459 01:01:49.389653 <3>[ 7.530813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10460 01:01:49.399778 <6>[ 7.540121] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10461 01:01:49.406374 <3>[ 7.542302] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10462 01:01:49.413158 <6>[ 7.548953] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10463 01:01:49.423717 <4>[ 7.549122] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10464 01:01:49.430051 <3>[ 7.557080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10465 01:01:49.439938 <6>[ 7.565633] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10466 01:01:49.443554 <6>[ 7.566406] mc: Linux media interface: v0.10
10467 01:01:49.453800 <3>[ 7.573226] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10468 01:01:49.459961 <4>[ 7.577122] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10469 01:01:49.466461 <4>[ 7.577122] Fallback method does not support PEC.
10470 01:01:49.473104 <6>[ 7.581293] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10471 01:01:49.482926 <6>[ 7.581576] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10472 01:01:49.489503 <3>[ 7.589459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10473 01:01:49.499448 <3>[ 7.594360] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10474 01:01:49.505900 <6>[ 7.597619] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10475 01:01:49.515802 <3>[ 7.605541] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10476 01:01:49.522516 <6>[ 7.605987] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10477 01:01:49.528964 <6>[ 7.606029] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10478 01:01:49.535788 <6>[ 7.606036] remoteproc remoteproc0: remote processor scp is now up
10479 01:01:49.542272 <6>[ 7.610830] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10480 01:01:49.548895 <6>[ 7.610834] pci_bus 0000:00: root bus resource [bus 00-ff]
10481 01:01:49.556164 <6>[ 7.610838] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10482 01:01:49.565041 <6>[ 7.610841] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10483 01:01:49.572331 <6>[ 7.610867] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10484 01:01:49.578594 <6>[ 7.610879] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10485 01:01:49.585377 <6>[ 7.610951] pci 0000:00:00.0: supports D1 D2
10486 01:01:49.591754 <6>[ 7.610954] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10487 01:01:49.598374 <6>[ 7.611745] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10488 01:01:49.605063 <6>[ 7.611805] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10489 01:01:49.614986 <6>[ 7.611830] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10490 01:01:49.621923 <6>[ 7.611845] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10491 01:01:49.628074 <6>[ 7.611860] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10492 01:01:49.631461 <6>[ 7.611960] pci 0000:01:00.0: supports D1 D2
10493 01:01:49.638084 <6>[ 7.611961] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10494 01:01:49.648310 <6>[ 7.613661] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10495 01:01:49.654801 <3>[ 7.621501] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10496 01:01:49.664728 <6>[ 7.622830] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10497 01:01:49.671154 <6>[ 7.624705] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10498 01:01:49.677570 <6>[ 7.624778] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10499 01:01:49.688208 <6>[ 7.624788] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10500 01:01:49.694051 <6>[ 7.624810] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10501 01:01:49.704047 <6>[ 7.624827] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10502 01:01:49.710691 <6>[ 7.624845] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10503 01:01:49.717086 <6>[ 7.624868] pci 0000:00:00.0: PCI bridge to [bus 01]
10504 01:01:49.723833 <6>[ 7.624879] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10505 01:01:49.730702 <6>[ 7.625161] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10506 01:01:49.736919 <6>[ 7.626195] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10507 01:01:49.743845 <6>[ 7.626279] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10508 01:01:49.750512 <6>[ 7.626822] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10509 01:01:49.760458 <3>[ 7.627047] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10510 01:01:49.770527 <6>[ 7.628679] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10511 01:01:49.776913 <6>[ 7.630454] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10512 01:01:49.786672 <6>[ 7.630494] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10513 01:01:49.796795 <3>[ 7.638883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10514 01:01:49.806542 <6>[ 7.647053] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10515 01:01:49.813001 <3>[ 7.651158] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10516 01:01:49.819564 <3>[ 7.651188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10517 01:01:49.826110 <6>[ 7.681264] videodev: Linux video capture interface: v2.00
10518 01:01:49.829924 <6>[ 7.690046] Bluetooth: Core ver 2.22
10519 01:01:49.839301 <5>[ 7.691970] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10520 01:01:49.846059 <5>[ 7.707545] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10521 01:01:49.849503 <6>[ 7.713624] NET: Registered PF_BLUETOOTH protocol family
10522 01:01:49.859569 <5>[ 7.722241] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10523 01:01:49.865997 <6>[ 7.728736] Bluetooth: HCI device and connection manager initialized
10524 01:01:49.875801 <4>[ 7.737307] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10525 01:01:49.879488 <6>[ 7.743642] Bluetooth: HCI socket layer initialized
10526 01:01:49.885926 <6>[ 7.750560] cfg80211: failed to load regulatory.db
10527 01:01:49.889149 <6>[ 7.756209] Bluetooth: L2CAP socket layer initialized
10528 01:01:49.895694 <6>[ 7.756240] Bluetooth: SCO socket layer initialized
10529 01:01:49.902462 <6>[ 7.756362] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10530 01:01:49.908805 <6>[ 7.774776] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10531 01:01:49.922035 <6>[ 7.782611] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10532 01:01:49.925646 <6>[ 7.814196] usbcore: registered new interface driver btusb
10533 01:01:49.938547 <4>[ 7.815305] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10534 01:01:49.944994 <3>[ 7.815322] Bluetooth: hci0: Failed to load firmware file (-2)
10535 01:01:49.948187 <3>[ 7.815326] Bluetooth: hci0: Failed to set up firmware (-2)
10536 01:01:49.958896 <4>[ 7.815330] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10537 01:01:49.965316 <6>[ 7.820867] usbcore: registered new interface driver uvcvideo
10538 01:01:49.971654 <6>[ 7.826082] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10539 01:01:49.978512 <6>[ 7.826172] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10540 01:01:49.984980 <6>[ 7.844609] mt7921e 0000:01:00.0: ASIC revision: 79610010
10541 01:01:50.085074 <6>[ 8.283984] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10542 01:01:50.088468 <6>[ 8.283984]
10543 01:01:50.091409 Begin: Loading essential drivers ... done.
10544 01:01:50.094897 Begin: Running /scripts/init-premount ... done.
10545 01:01:50.101628 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10546 01:01:50.111410 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10547 01:01:50.114744 Device /sys/class/net/eth0 found
10548 01:01:50.115180 done.
10549 01:01:50.121584 Begin: Waiting up to 180 secs for any network device to become available ... done.
10550 01:01:50.178578 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10551 01:01:50.185221 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10552 01:01:50.191647 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10553 01:01:50.198149 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10554 01:01:50.204681 host : mt8192-asurada-spherion-r0-cbg-4
10555 01:01:50.211556 domain : lava-rack
10556 01:01:50.215151 rootserver: 192.168.201.1 rootpath:
10557 01:01:50.215589 filename :
10558 01:01:50.224761 done.
10559 01:01:50.232815 Begin: Running /scripts/nfs-bottom ... done.
10560 01:01:50.244595 Begin: Running /scripts/init-bottom ... done.
10561 01:01:50.356139 <6>[ 8.555028] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10562 01:01:51.588077 <6>[ 9.790915] NET: Registered PF_INET6 protocol family
10563 01:01:51.595744 <6>[ 9.798572] Segment Routing with IPv6
10564 01:01:51.599177 <6>[ 9.802577] In-situ OAM (IOAM) with IPv6
10565 01:01:51.767869 <30>[ 9.943601] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10566 01:01:51.774196 <30>[ 9.976757] systemd[1]: Detected architecture arm64.
10567 01:01:51.783495
10568 01:01:51.786662 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10569 01:01:51.787057
10570 01:01:51.811380 <30>[ 10.014362] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10571 01:01:52.882651 <30>[ 11.082275] systemd[1]: Queued start job for default target graphical.target.
10572 01:01:52.930940 <30>[ 11.129880] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10573 01:01:52.937165 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10574 01:01:52.959295 <30>[ 11.158554] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10575 01:01:52.969563 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10576 01:01:52.987267 <30>[ 11.186549] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10577 01:01:52.996946 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10578 01:01:53.014785 <30>[ 11.214102] systemd[1]: Created slice user.slice - User and Session Slice.
10579 01:01:53.021295 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10580 01:01:53.045409 <30>[ 11.241471] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10581 01:01:53.055123 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10582 01:01:53.073027 <30>[ 11.268984] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10583 01:01:53.079418 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10584 01:01:53.107825 <30>[ 11.297333] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10585 01:01:53.117701 <30>[ 11.317221] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10586 01:01:53.124449 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10587 01:01:53.141690 <30>[ 11.341087] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10588 01:01:53.151351 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10589 01:01:53.169997 <30>[ 11.369105] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10590 01:01:53.180103 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10591 01:01:53.194087 <30>[ 11.396797] systemd[1]: Reached target paths.target - Path Units.
10592 01:01:53.203671 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10593 01:01:53.221762 <30>[ 11.421163] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10594 01:01:53.228410 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10595 01:01:53.241902 <30>[ 11.444690] systemd[1]: Reached target slices.target - Slice Units.
10596 01:01:53.252126 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10597 01:01:53.266180 <30>[ 11.469189] systemd[1]: Reached target swap.target - Swaps.
10598 01:01:53.272968 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10599 01:01:53.293776 <30>[ 11.493236] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10600 01:01:53.303469 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10601 01:01:53.322338 <30>[ 11.521677] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10602 01:01:53.332100 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10603 01:01:53.352725 <30>[ 11.551994] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10604 01:01:53.362316 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10605 01:01:53.379065 <30>[ 11.578205] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10606 01:01:53.388898 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10607 01:01:53.405679 <30>[ 11.605331] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10608 01:01:53.412519 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10609 01:01:53.430592 <30>[ 11.630091] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10610 01:01:53.440226 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10611 01:01:53.460321 <30>[ 11.659460] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10612 01:01:53.469899 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10613 01:01:53.486841 <30>[ 11.685858] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10614 01:01:53.496626 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10615 01:01:53.545883 <30>[ 11.745210] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10616 01:01:53.552223 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10617 01:01:53.574952 <30>[ 11.774547] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10618 01:01:53.581635 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10619 01:01:53.604719 <30>[ 11.804076] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10620 01:01:53.610866 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10621 01:01:53.636377 <30>[ 11.829324] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10622 01:01:53.670020 <30>[ 11.869515] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10623 01:01:53.679659 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10624 01:01:53.703277 <30>[ 11.902534] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10625 01:01:53.712966 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10626 01:01:53.734537 <30>[ 11.934032] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10627 01:01:53.741147 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10628 01:01:53.767040 <30>[ 11.966478] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10629 01:01:53.776828 Startin<6>[ 11.975466] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10630 01:01:53.783675 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10631 01:01:53.807767 <30>[ 12.006776] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10632 01:01:53.817364 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10633 01:01:53.838849 <30>[ 12.038136] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10634 01:01:53.845312 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10635 01:01:53.870619 <30>[ 12.070234] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10636 01:01:53.877133 Startin<6>[ 12.079012] fuse: init (API version 7.37)
10637 01:01:53.883725 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10638 01:01:53.907907 <30>[ 12.107654] systemd[1]: Starting systemd-journald.service - Journal Service...
10639 01:01:53.914656 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10640 01:01:53.946426 <30>[ 12.145731] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10641 01:01:53.952929 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10642 01:01:53.983850 <30>[ 12.179998] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10643 01:01:53.990265 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10644 01:01:54.046266 <30>[ 12.245915] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10645 01:01:54.055966 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10646 01:01:54.079477 <30>[ 12.278999] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10647 01:01:54.086026 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10648 01:01:54.110819 <3>[ 12.310192] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10649 01:01:54.117523 <30>[ 12.315254] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10650 01:01:54.127263 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10651 01:01:54.146034 <30>[ 12.345578] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10652 01:01:54.155968 <3>[ 12.346475] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10653 01:01:54.162520 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10654 01:01:54.186069 <30>[ 12.385322] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10655 01:01:54.193016 <3>[ 12.389569] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 01:01:54.202649 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10657 01:01:54.222018 <30>[ 12.421502] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10658 01:01:54.232252 <3>[ 12.422010] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10659 01:01:54.248976 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10660 01:01:54.260237 <3>[ 12.459525] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10661 01:01:54.270399 <30>[ 12.469676] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10662 01:01:54.277081 <30>[ 12.477443] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10663 01:01:54.287556 [[0;32m OK [<3>[ 12.487006] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10664 01:01:54.293949 0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10665 01:01:54.314389 <30>[ 12.513633] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10666 01:01:54.320879 <3>[ 12.516936] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10667 01:01:54.330825 <30>[ 12.521559] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10668 01:01:54.352181 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m <3>[ 12.549977] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10669 01:01:54.352646 - Load Kernel Module dm_mod.
10670 01:01:54.371592 <30>[ 12.573773] systemd[1]: modprobe@drm.service: Deactivated successfully.
10671 01:01:54.382543 <30>[ 12.581938] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10672 01:01:54.389477 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10673 01:01:54.396972 <4>[ 12.599608] power_supply_show_property: 1 callbacks suppressed
10674 01:01:54.406764 <3>[ 12.599618] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10675 01:01:54.416998 <30>[ 12.616592] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10676 01:01:54.424140 <30>[ 12.624788] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10677 01:01:54.434408 <3>[ 12.633550] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10678 01:01:54.444139 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10679 01:01:54.463159 <3>[ 12.662677] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10680 01:01:54.469627 <30>[ 12.663054] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10681 01:01:54.479864 <30>[ 12.679350] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10682 01:01:54.493571 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Mo<3>[ 12.693249] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10683 01:01:54.497129 dule fuse.
10684 01:01:54.510940 <4>[ 12.703192] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10685 01:01:54.521200 <3>[ 12.709274] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10686 01:01:54.527399 <3>[ 12.719959] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10687 01:01:54.534307 <30>[ 12.730047] systemd[1]: modprobe@loop.service: Deactivated successfully.
10688 01:01:54.546072 <30>[ 12.744841] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10689 01:01:54.555531 [[0;32m OK [<3>[ 12.753825] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10690 01:01:54.562201 0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10691 01:01:54.582846 <30>[ 12.781784] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10692 01:01:54.589600 <3>[ 12.785195] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10693 01:01:54.599279 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10694 01:01:54.621562 <30>[ 12.817617] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10695 01:01:54.628441 <3>[ 12.821036] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10696 01:01:54.638078 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10697 01:01:54.658249 <30>[ 12.857490] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10698 01:01:54.668351 <3>[ 12.858928] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10699 01:01:54.678048 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10700 01:01:54.694410 <30>[ 12.893500] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10701 01:01:54.704068 <3>[ 12.898562] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10702 01:01:54.710782 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10703 01:01:54.730919 <30>[ 12.930065] systemd[1]: Reached target network-pre.target - Preparation for Network.
10704 01:01:54.737739 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10705 01:01:54.785386 <30>[ 12.985041] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10706 01:01:54.795107 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10707 01:01:54.817965 <30>[ 13.017838] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10708 01:01:54.827761 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10709 01:01:54.848606 <30>[ 13.045053] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10710 01:01:54.865930 <30>[ 13.058766] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10711 01:01:54.897661 <30>[ 13.097454] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10712 01:01:54.904616 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10713 01:01:54.931374 <30>[ 13.127768] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10714 01:01:54.945957 <30>[ 13.145460] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10715 01:01:54.952408 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10716 01:01:54.980635 <30>[ 13.180088] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10717 01:01:54.986653 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10718 01:01:55.016941 <30>[ 13.216879] systemd[1]: Started systemd-journald.service - Journal Service.
10719 01:01:55.023512 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10720 01:01:55.050441 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10721 01:01:55.069542 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10722 01:01:55.090871 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10723 01:01:55.110750 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10724 01:01:55.130888 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10725 01:01:55.174522 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10726 01:01:55.204066 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10727 01:01:55.238124 <46>[ 13.437842] systemd-journald[308]: Received client request to flush runtime journal.
10728 01:01:56.342728 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10729 01:01:56.362037 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10730 01:01:56.380885 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10731 01:01:56.649782 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10732 01:01:56.671157 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10733 01:01:56.697866 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10734 01:01:56.798388 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10735 01:01:56.874969 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10736 01:01:56.939113 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10737 01:01:57.211032 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10738 01:01:57.249879 <6>[ 15.453124] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10739 01:01:57.266300 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10740 01:01:57.310453 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10741 01:01:57.371301 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10742 01:01:57.409555 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10743 01:01:57.434100 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10744 01:01:57.467233 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10745 01:01:57.482057 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10746 01:01:57.522204 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10747 01:01:57.550048 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10748 01:01:57.614124 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10749 01:01:57.639594 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10750 01:01:57.699989 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10751 01:01:57.843132 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10752 01:01:57.865357 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10753 01:01:57.884990 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10754 01:01:57.905085 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10755 01:01:57.934368 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10756 01:01:57.956282 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10757 01:01:57.973196 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10758 01:01:57.991976 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10759 01:01:58.012093 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10760 01:01:58.029155 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10761 01:01:58.046996 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10762 01:01:58.064783 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10763 01:01:58.080995 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10764 01:01:58.126697 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10765 01:01:58.185107 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10766 01:01:58.240959 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10767 01:01:58.264580 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10768 01:01:58.444432 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10769 01:01:58.509898 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10770 01:01:58.530872 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10771 01:01:58.550373 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10772 01:01:58.568530 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10773 01:01:58.586670 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10774 01:01:58.622062 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10775 01:01:58.643169 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10776 01:01:58.661711 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10777 01:01:58.721642 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10778 01:01:58.804666 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10779 01:01:58.885277
10780 01:01:58.888469 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10781 01:01:58.889001
10782 01:01:58.891927 debian-bookworm-arm64 login: root (automatic login)
10783 01:01:58.892319
10784 01:01:59.196974 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
10785 01:01:59.197411
10786 01:01:59.203349 The programs included with the Debian GNU/Linux system are free software;
10787 01:01:59.209814 the exact distribution terms for each program are described in the
10788 01:01:59.213105 individual files in /usr/share/doc/*/copyright.
10789 01:01:59.213496
10790 01:01:59.220047 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10791 01:01:59.223034 permitted by applicable law.
10792 01:02:00.261230 Matched prompt #10: / #
10794 01:02:00.262339 Setting prompt string to ['/ #']
10795 01:02:00.262767 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10797 01:02:00.263728 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10798 01:02:00.264136 start: 2.2.6 expect-shell-connection (timeout 00:03:46) [common]
10799 01:02:00.264477 Setting prompt string to ['/ #']
10800 01:02:00.264766 Forcing a shell prompt, looking for ['/ #']
10802 01:02:00.315569 / #
10803 01:02:00.316245 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10804 01:02:00.316669 Waiting using forced prompt support (timeout 00:02:30)
10805 01:02:00.321828
10806 01:02:00.322829 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10807 01:02:00.323343 start: 2.2.7 export-device-env (timeout 00:03:46) [common]
10809 01:02:00.424591 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368632/extract-nfsrootfs-n8p_9uxc'
10810 01:02:00.431226 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368632/extract-nfsrootfs-n8p_9uxc'
10812 01:02:00.533036 / # export NFS_SERVER_IP='192.168.201.1'
10813 01:02:00.539354 export NFS_SERVER_IP='192.168.201.1'
10814 01:02:00.540195 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10815 01:02:00.540684 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
10816 01:02:00.541163 end: 2 depthcharge-action (duration 00:01:15) [common]
10817 01:02:00.541646 start: 3 lava-test-retry (timeout 00:08:08) [common]
10818 01:02:00.542120 start: 3.1 lava-test-shell (timeout 00:08:08) [common]
10819 01:02:00.542571 Using namespace: common
10821 01:02:00.643745 / # #
10822 01:02:00.644400 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10823 01:02:00.649746 #
10824 01:02:00.650546 Using /lava-14368632
10826 01:02:00.751612 / # export SHELL=/bin/bash
10827 01:02:00.757570 export SHELL=/bin/bash
10829 01:02:00.858983 / # . /lava-14368632/environment
10830 01:02:00.864876 . /lava-14368632/environment
10832 01:02:00.972062 / # /lava-14368632/bin/lava-test-runner /lava-14368632/0
10833 01:02:00.972739 Test shell timeout: 10s (minimum of the action and connection timeout)
10834 01:02:00.978181 /lava-14368632/bin/lava-test-runner /lava-14368632/0
10835 01:02:01.240902 + export TESTRUN_ID=0_timesync-off
10836 01:02:01.243896 + TESTRUN_ID=0_timesync-off
10837 01:02:01.247386 + cd /lava-14368632/0/tests/0_timesync-off
10838 01:02:01.250656 ++ cat uuid
10839 01:02:01.256674 + UUID=14368632_1.6.2.3.1
10840 01:02:01.257069 + set +x
10841 01:02:01.263540 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368632_1.6.2.3.1>
10842 01:02:01.264210 Received signal: <STARTRUN> 0_timesync-off 14368632_1.6.2.3.1
10843 01:02:01.264564 Starting test lava.0_timesync-off (14368632_1.6.2.3.1)
10844 01:02:01.264964 Skipping test definition patterns.
10845 01:02:01.266369 + systemctl stop systemd-timesyncd
10846 01:02:01.336634 + set +x
10847 01:02:01.339802 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368632_1.6.2.3.1>
10848 01:02:01.340435 Received signal: <ENDRUN> 0_timesync-off 14368632_1.6.2.3.1
10849 01:02:01.340825 Ending use of test pattern.
10850 01:02:01.341122 Ending test lava.0_timesync-off (14368632_1.6.2.3.1), duration 0.08
10852 01:02:01.424220 + export TESTRUN_ID=1_kselftest-dt
10853 01:02:01.427361 + TESTRUN_ID=1_kselftest-dt
10854 01:02:01.430780 + cd /lava-14368632/0/tests/1_kselftest-dt
10855 01:02:01.433892 ++ cat uuid
10856 01:02:01.437875 + UUID=14368632_1.6.2.3.5
10857 01:02:01.438318 + set +x
10858 01:02:01.444634 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14368632_1.6.2.3.5>
10859 01:02:01.445299 Received signal: <STARTRUN> 1_kselftest-dt 14368632_1.6.2.3.5
10860 01:02:01.445665 Starting test lava.1_kselftest-dt (14368632_1.6.2.3.5)
10861 01:02:01.446081 Skipping test definition patterns.
10862 01:02:01.447822 + cd ./automated/linux/kselftest/
10863 01:02:01.474290 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10864 01:02:01.512554 INFO: install_deps skipped
10865 01:02:02.014612 --2024-06-16 01:02:01-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10866 01:02:02.021370 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10867 01:02:02.142022 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10868 01:02:02.267557 HTTP request sent, awaiting response... 200 OK
10869 01:02:02.270889 Length: 1647948 (1.6M) [application/octet-stream]
10870 01:02:02.274061 Saving to: 'kselftest_armhf.tar.gz'
10871 01:02:02.274625
10872 01:02:02.274980
10873 01:02:02.520087 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
10874 01:02:02.770811 kselftest_armhf.tar 2%[ ] 47.81K 190KB/s
10875 01:02:03.194369 kselftest_armhf.tar 13%[=> ] 217.50K 432KB/s
10876 01:02:03.271342 kselftest_armhf.tar 50%[=========> ] 808.57K 873KB/s
10877 01:02:03.277793 kselftest_armhf.tar 100%[===================>] 1.57M 1.57MB/s in 1.0s
10878 01:02:03.278397
10879 01:02:03.421996 2024-06-16 01:02:03 (1.57 MB/s) - 'kselftest_armhf.tar.gz' saved [1647948/1647948]
10880 01:02:03.422135
10881 01:02:07.363953 skiplist:
10882 01:02:07.366583 ========================================
10883 01:02:07.369911 ========================================
10884 01:02:07.430975 ============== Tests to run ===============
10885 01:02:07.434270 ===========End Tests to run ===============
10886 01:02:07.439418 shardfile-dt fail
10887 01:02:07.460758 ./kselftest.sh: 131: cannot open /lava-14368632/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
10888 01:02:07.464073 + ../../utils/send-to-lava.sh ./output/result.txt
10889 01:02:07.513457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
10890 01:02:07.513563 + set +x
10891 01:02:07.513844 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
10893 01:02:07.519664 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14368632_1.6.2.3.5>
10894 01:02:07.519903 Received signal: <ENDRUN> 1_kselftest-dt 14368632_1.6.2.3.5
10895 01:02:07.519972 Ending use of test pattern.
10896 01:02:07.520029 Ending test lava.1_kselftest-dt (14368632_1.6.2.3.5), duration 6.07
10898 01:02:07.520248 ok: lava_test_shell seems to have completed
10899 01:02:07.520333 shardfile-dt: fail
10900 01:02:07.520443 end: 3.1 lava-test-shell (duration 00:00:07) [common]
10901 01:02:07.520521 end: 3 lava-test-retry (duration 00:00:07) [common]
10902 01:02:07.520599 start: 4 finalize (timeout 00:08:01) [common]
10903 01:02:07.520722 start: 4.1 power-off (timeout 00:00:30) [common]
10904 01:02:07.520978 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
10905 01:02:07.735034 >> Command sent successfully.
10906 01:02:07.748860 Returned 0 in 0 seconds
10907 01:02:07.850107 end: 4.1 power-off (duration 00:00:00) [common]
10909 01:02:07.851525 start: 4.2 read-feedback (timeout 00:08:01) [common]
10911 01:02:07.853683 Listened to connection for namespace 'common' for up to 1s
10912 01:02:08.853309 Finalising connection for namespace 'common'
10913 01:02:08.853984 Disconnecting from shell: Finalise
10914 01:02:08.854419 / #
10915 01:02:08.955350 end: 4.2 read-feedback (duration 00:00:01) [common]
10916 01:02:08.956011 end: 4 finalize (duration 00:00:01) [common]
10917 01:02:08.956567 Cleaning after the job
10918 01:02:08.957034 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/ramdisk
10919 01:02:08.961520 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/kernel
10920 01:02:08.972377 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/dtb
10921 01:02:08.972550 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/nfsrootfs
10922 01:02:09.036511 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368632/tftp-deploy-gyxsuv4h/modules
10923 01:02:09.042095 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368632
10924 01:02:09.573484 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368632
10925 01:02:09.573661 Job finished correctly