Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:54:44.917924 lava-dispatcher, installed at version: 2024.03
2 00:54:44.918210 start: 0 validate
3 00:54:44.918328 Start time: 2024-06-16 00:54:44.918322+00:00 (UTC)
4 00:54:44.918467 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:54:44.918606 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:54:45.169807 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:54:45.169975 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:54:45.421623 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:54:45.422442 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:55:18.734397 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:55:18.734537 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:55:19.230596 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:55:19.230739 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:55:19.480538 validate duration: 34.56
16 00:55:19.480781 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:55:19.480879 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:55:19.480965 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:55:19.481106 Not decompressing ramdisk as can be used compressed.
20 00:55:19.481195 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:55:19.481258 saving as /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/ramdisk/initrd.cpio.gz
22 00:55:19.481318 total size: 5628169 (5 MB)
23 00:55:22.957704 progress 0 % (0 MB)
24 00:55:22.959413 progress 5 % (0 MB)
25 00:55:22.960948 progress 10 % (0 MB)
26 00:55:22.962376 progress 15 % (0 MB)
27 00:55:22.963896 progress 20 % (1 MB)
28 00:55:22.965282 progress 25 % (1 MB)
29 00:55:22.966853 progress 30 % (1 MB)
30 00:55:22.968356 progress 35 % (1 MB)
31 00:55:22.969690 progress 40 % (2 MB)
32 00:55:22.971218 progress 45 % (2 MB)
33 00:55:22.972570 progress 50 % (2 MB)
34 00:55:22.974105 progress 55 % (2 MB)
35 00:55:22.975602 progress 60 % (3 MB)
36 00:55:22.976937 progress 65 % (3 MB)
37 00:55:22.978488 progress 70 % (3 MB)
38 00:55:22.979822 progress 75 % (4 MB)
39 00:55:22.981306 progress 80 % (4 MB)
40 00:55:22.982691 progress 85 % (4 MB)
41 00:55:22.984218 progress 90 % (4 MB)
42 00:55:22.985710 progress 95 % (5 MB)
43 00:55:22.987110 progress 100 % (5 MB)
44 00:55:22.987317 5 MB downloaded in 3.51 s (1.53 MB/s)
45 00:55:22.987461 end: 1.1.1 http-download (duration 00:00:04) [common]
47 00:55:22.987679 end: 1.1 download-retry (duration 00:00:04) [common]
48 00:55:22.987760 start: 1.2 download-retry (timeout 00:09:56) [common]
49 00:55:22.987836 start: 1.2.1 http-download (timeout 00:09:56) [common]
50 00:55:22.987964 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:55:22.988028 saving as /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/kernel/Image
52 00:55:22.988082 total size: 54813184 (52 MB)
53 00:55:22.988136 No compression specified
54 00:55:22.989143 progress 0 % (0 MB)
55 00:55:23.002799 progress 5 % (2 MB)
56 00:55:23.016571 progress 10 % (5 MB)
57 00:55:23.030162 progress 15 % (7 MB)
58 00:55:23.043969 progress 20 % (10 MB)
59 00:55:23.057585 progress 25 % (13 MB)
60 00:55:23.071231 progress 30 % (15 MB)
61 00:55:23.085245 progress 35 % (18 MB)
62 00:55:23.099118 progress 40 % (20 MB)
63 00:55:23.112748 progress 45 % (23 MB)
64 00:55:23.126665 progress 50 % (26 MB)
65 00:55:23.140427 progress 55 % (28 MB)
66 00:55:23.154045 progress 60 % (31 MB)
67 00:55:23.167700 progress 65 % (34 MB)
68 00:55:23.181208 progress 70 % (36 MB)
69 00:55:23.195046 progress 75 % (39 MB)
70 00:55:23.208810 progress 80 % (41 MB)
71 00:55:23.222588 progress 85 % (44 MB)
72 00:55:23.236366 progress 90 % (47 MB)
73 00:55:23.249957 progress 95 % (49 MB)
74 00:55:23.263448 progress 100 % (52 MB)
75 00:55:23.263666 52 MB downloaded in 0.28 s (189.69 MB/s)
76 00:55:23.263811 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:55:23.264017 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:55:23.264097 start: 1.3 download-retry (timeout 00:09:56) [common]
80 00:55:23.264173 start: 1.3.1 http-download (timeout 00:09:56) [common]
81 00:55:23.264300 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:55:23.264365 saving as /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/dtb/mt8192-asurada-spherion-r0.dtb
83 00:55:23.264418 total size: 47258 (0 MB)
84 00:55:23.264470 No compression specified
85 00:55:23.265703 progress 69 % (0 MB)
86 00:55:23.265961 progress 100 % (0 MB)
87 00:55:23.266152 0 MB downloaded in 0.00 s (26.04 MB/s)
88 00:55:23.266264 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:55:23.266462 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:55:23.266537 start: 1.4 download-retry (timeout 00:09:56) [common]
92 00:55:23.266612 start: 1.4.1 http-download (timeout 00:09:56) [common]
93 00:55:23.266714 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:55:23.266773 saving as /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/nfsrootfs/full.rootfs.tar
95 00:55:23.266825 total size: 120894716 (115 MB)
96 00:55:23.266879 Using unxz to decompress xz
97 00:55:23.268034 progress 0 % (0 MB)
98 00:55:23.616092 progress 5 % (5 MB)
99 00:55:23.980093 progress 10 % (11 MB)
100 00:55:24.352091 progress 15 % (17 MB)
101 00:55:24.695148 progress 20 % (23 MB)
102 00:55:25.012040 progress 25 % (28 MB)
103 00:55:25.388429 progress 30 % (34 MB)
104 00:55:25.720126 progress 35 % (40 MB)
105 00:55:25.893485 progress 40 % (46 MB)
106 00:55:26.081974 progress 45 % (51 MB)
107 00:55:26.406976 progress 50 % (57 MB)
108 00:55:26.774115 progress 55 % (63 MB)
109 00:55:27.119526 progress 60 % (69 MB)
110 00:55:27.467008 progress 65 % (74 MB)
111 00:55:27.813849 progress 70 % (80 MB)
112 00:55:28.175812 progress 75 % (86 MB)
113 00:55:28.531809 progress 80 % (92 MB)
114 00:55:28.877261 progress 85 % (98 MB)
115 00:55:29.222400 progress 90 % (103 MB)
116 00:55:29.554098 progress 95 % (109 MB)
117 00:55:29.918479 progress 100 % (115 MB)
118 00:55:29.923918 115 MB downloaded in 6.66 s (17.32 MB/s)
119 00:55:29.924075 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:55:29.924290 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:55:29.924372 start: 1.5 download-retry (timeout 00:09:50) [common]
123 00:55:29.924449 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 00:55:29.924577 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:55:29.924639 saving as /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/modules/modules.tar
126 00:55:29.924693 total size: 8617404 (8 MB)
127 00:55:29.924749 Using unxz to decompress xz
128 00:55:29.926095 progress 0 % (0 MB)
129 00:55:29.944737 progress 5 % (0 MB)
130 00:55:29.971092 progress 10 % (0 MB)
131 00:55:29.998623 progress 15 % (1 MB)
132 00:55:30.022317 progress 20 % (1 MB)
133 00:55:30.045946 progress 25 % (2 MB)
134 00:55:30.069473 progress 30 % (2 MB)
135 00:55:30.095559 progress 35 % (2 MB)
136 00:55:30.119774 progress 40 % (3 MB)
137 00:55:30.142276 progress 45 % (3 MB)
138 00:55:30.166166 progress 50 % (4 MB)
139 00:55:30.191129 progress 55 % (4 MB)
140 00:55:30.215409 progress 60 % (4 MB)
141 00:55:30.239433 progress 65 % (5 MB)
142 00:55:30.265863 progress 70 % (5 MB)
143 00:55:30.289416 progress 75 % (6 MB)
144 00:55:30.314819 progress 80 % (6 MB)
145 00:55:30.338776 progress 85 % (7 MB)
146 00:55:30.363405 progress 90 % (7 MB)
147 00:55:30.387953 progress 95 % (7 MB)
148 00:55:30.412385 progress 100 % (8 MB)
149 00:55:30.418288 8 MB downloaded in 0.49 s (16.65 MB/s)
150 00:55:30.418461 end: 1.5.1 http-download (duration 00:00:00) [common]
152 00:55:30.418675 end: 1.5 download-retry (duration 00:00:00) [common]
153 00:55:30.418754 start: 1.6 prepare-tftp-overlay (timeout 00:09:49) [common]
154 00:55:30.418831 start: 1.6.1 extract-nfsrootfs (timeout 00:09:49) [common]
155 00:55:34.007473 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368562/extract-nfsrootfs-azas7lbe
156 00:55:34.007651 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:55:34.007741 start: 1.6.2 lava-overlay (timeout 00:09:45) [common]
158 00:55:34.007909 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c
159 00:55:34.008029 makedir: /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin
160 00:55:34.008126 makedir: /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/tests
161 00:55:34.008215 makedir: /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/results
162 00:55:34.008300 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-add-keys
163 00:55:34.008427 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-add-sources
164 00:55:34.008552 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-background-process-start
165 00:55:34.008673 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-background-process-stop
166 00:55:34.008801 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-common-functions
167 00:55:34.008921 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-echo-ipv4
168 00:55:34.009040 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-install-packages
169 00:55:34.009158 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-installed-packages
170 00:55:34.009275 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-os-build
171 00:55:34.009389 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-probe-channel
172 00:55:34.009504 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-probe-ip
173 00:55:34.009619 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-target-ip
174 00:55:34.009732 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-target-mac
175 00:55:34.009847 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-target-storage
176 00:55:34.009964 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-test-case
177 00:55:34.010092 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-test-event
178 00:55:34.010205 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-test-feedback
179 00:55:34.010322 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-test-raise
180 00:55:34.010434 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-test-reference
181 00:55:34.010550 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-test-runner
182 00:55:34.010665 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-test-set
183 00:55:34.010777 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-test-shell
184 00:55:34.010893 Updating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-add-keys (debian)
185 00:55:34.011032 Updating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-add-sources (debian)
186 00:55:34.011159 Updating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-install-packages (debian)
187 00:55:34.011285 Updating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-installed-packages (debian)
188 00:55:34.011413 Updating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/bin/lava-os-build (debian)
189 00:55:34.011522 Creating /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/environment
190 00:55:34.011614 LAVA metadata
191 00:55:34.011679 - LAVA_JOB_ID=14368562
192 00:55:34.011737 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:55:34.011830 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:45) [common]
194 00:55:34.011888 skipped lava-vland-overlay
195 00:55:34.011957 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:55:34.012029 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:45) [common]
197 00:55:34.012082 skipped lava-multinode-overlay
198 00:55:34.012147 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:55:34.012217 start: 1.6.2.3 test-definition (timeout 00:09:45) [common]
200 00:55:34.012292 Loading test definitions
201 00:55:34.012369 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:45) [common]
202 00:55:34.012428 Using /lava-14368562 at stage 0
203 00:55:34.012706 uuid=14368562_1.6.2.3.1 testdef=None
204 00:55:34.012788 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:55:34.012867 start: 1.6.2.3.2 test-overlay (timeout 00:09:45) [common]
206 00:55:34.013271 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:55:34.013471 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:45) [common]
209 00:55:34.014104 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:55:34.014323 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:45) [common]
212 00:55:34.014827 runner path: /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/0/tests/0_timesync-off test_uuid 14368562_1.6.2.3.1
213 00:55:34.014977 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:55:34.015188 start: 1.6.2.3.5 git-repo-action (timeout 00:09:45) [common]
216 00:55:34.015253 Using /lava-14368562 at stage 0
217 00:55:34.015347 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:55:34.015423 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/0/tests/1_kselftest-rtc'
219 00:55:36.329116 Running '/usr/bin/git checkout kernelci.org
220 00:55:36.484274 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 00:55:36.484738 uuid=14368562_1.6.2.3.5 testdef=None
222 00:55:36.484880 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 00:55:36.485174 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 00:55:36.485842 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:55:36.486092 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 00:55:36.486996 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:55:36.487206 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 00:55:36.488035 runner path: /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/0/tests/1_kselftest-rtc test_uuid 14368562_1.6.2.3.5
232 00:55:36.488113 BOARD='mt8192-asurada-spherion-r0'
233 00:55:36.488170 BRANCH='cip-gitlab'
234 00:55:36.488221 SKIPFILE='/dev/null'
235 00:55:36.488271 SKIP_INSTALL='True'
236 00:55:36.488319 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:55:36.488370 TST_CASENAME=''
238 00:55:36.488418 TST_CMDFILES='rtc'
239 00:55:36.488548 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:55:36.488725 Creating lava-test-runner.conf files
242 00:55:36.488778 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368562/lava-overlay-fcrtmd6c/lava-14368562/0 for stage 0
243 00:55:36.488858 - 0_timesync-off
244 00:55:36.488917 - 1_kselftest-rtc
245 00:55:36.489003 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 00:55:36.489078 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 00:55:43.787227 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:55:43.787371 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 00:55:43.787455 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:55:43.787536 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 00:55:43.787616 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 00:55:43.949276 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:55:43.949425 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 00:55:43.949503 extracting modules file /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368562/extract-nfsrootfs-azas7lbe
255 00:55:44.170858 extracting modules file /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368562/extract-overlay-ramdisk-ez7dd2pn/ramdisk
256 00:55:44.395887 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:55:44.396039 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 00:55:44.396120 [common] Applying overlay to NFS
259 00:55:44.396178 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368562/compress-overlay-2g0p4cq7/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368562/extract-nfsrootfs-azas7lbe
260 00:55:45.234825 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:55:45.234963 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 00:55:45.235046 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:55:45.235126 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 00:55:45.235194 Building ramdisk /var/lib/lava/dispatcher/tmp/14368562/extract-overlay-ramdisk-ez7dd2pn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368562/extract-overlay-ramdisk-ez7dd2pn/ramdisk
265 00:55:45.561065 >> 130405 blocks
266 00:55:47.704870 rename /var/lib/lava/dispatcher/tmp/14368562/extract-overlay-ramdisk-ez7dd2pn/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/ramdisk/ramdisk.cpio.gz
267 00:55:47.705092 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:55:47.705224 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 00:55:47.705341 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 00:55:47.705457 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/kernel/Image']
271 00:56:02.660396 Returned 0 in 14 seconds
272 00:56:02.760904 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/kernel/image.itb
273 00:56:03.134335 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:56:03.134472 output: Created: Sun Jun 16 01:56:03 2024
275 00:56:03.134541 output: Image 0 (kernel-1)
276 00:56:03.134612 output: Description:
277 00:56:03.134672 output: Created: Sun Jun 16 01:56:03 2024
278 00:56:03.134725 output: Type: Kernel Image
279 00:56:03.134777 output: Compression: lzma compressed
280 00:56:03.134830 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
281 00:56:03.134880 output: Architecture: AArch64
282 00:56:03.134929 output: OS: Linux
283 00:56:03.134978 output: Load Address: 0x00000000
284 00:56:03.135026 output: Entry Point: 0x00000000
285 00:56:03.135075 output: Hash algo: crc32
286 00:56:03.135124 output: Hash value: f6f06660
287 00:56:03.135171 output: Image 1 (fdt-1)
288 00:56:03.135217 output: Description: mt8192-asurada-spherion-r0
289 00:56:03.135264 output: Created: Sun Jun 16 01:56:03 2024
290 00:56:03.135311 output: Type: Flat Device Tree
291 00:56:03.135358 output: Compression: uncompressed
292 00:56:03.135407 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:56:03.135455 output: Architecture: AArch64
294 00:56:03.135504 output: Hash algo: crc32
295 00:56:03.135550 output: Hash value: 0f8e4d2e
296 00:56:03.135601 output: Image 2 (ramdisk-1)
297 00:56:03.135651 output: Description: unavailable
298 00:56:03.135701 output: Created: Sun Jun 16 01:56:03 2024
299 00:56:03.135749 output: Type: RAMDisk Image
300 00:56:03.135797 output: Compression: uncompressed
301 00:56:03.135843 output: Data Size: 18738002 Bytes = 18298.83 KiB = 17.87 MiB
302 00:56:03.135890 output: Architecture: AArch64
303 00:56:03.135936 output: OS: Linux
304 00:56:03.135982 output: Load Address: unavailable
305 00:56:03.136028 output: Entry Point: unavailable
306 00:56:03.136075 output: Hash algo: crc32
307 00:56:03.136121 output: Hash value: ba460849
308 00:56:03.136167 output: Default Configuration: 'conf-1'
309 00:56:03.136213 output: Configuration 0 (conf-1)
310 00:56:03.136259 output: Description: mt8192-asurada-spherion-r0
311 00:56:03.136307 output: Kernel: kernel-1
312 00:56:03.136354 output: Init Ramdisk: ramdisk-1
313 00:56:03.136401 output: FDT: fdt-1
314 00:56:03.136447 output: Loadables: kernel-1
315 00:56:03.136493 output:
316 00:56:03.136625 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 00:56:03.136711 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 00:56:03.136798 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 00:56:03.136882 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 00:56:03.136948 No LXC device requested
321 00:56:03.137015 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:56:03.137090 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 00:56:03.137159 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:56:03.137217 Checking files for TFTP limit of 4294967296 bytes.
325 00:56:03.137659 end: 1 tftp-deploy (duration 00:00:44) [common]
326 00:56:03.137757 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:56:03.137839 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:56:03.137944 substitutions:
329 00:56:03.138034 - {DTB}: 14368562/tftp-deploy-hnw5p4e_/dtb/mt8192-asurada-spherion-r0.dtb
330 00:56:03.138105 - {INITRD}: 14368562/tftp-deploy-hnw5p4e_/ramdisk/ramdisk.cpio.gz
331 00:56:03.138157 - {KERNEL}: 14368562/tftp-deploy-hnw5p4e_/kernel/Image
332 00:56:03.138209 - {LAVA_MAC}: None
333 00:56:03.138259 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368562/extract-nfsrootfs-azas7lbe
334 00:56:03.138308 - {NFS_SERVER_IP}: 192.168.201.1
335 00:56:03.138355 - {PRESEED_CONFIG}: None
336 00:56:03.138410 - {PRESEED_LOCAL}: None
337 00:56:03.138458 - {RAMDISK}: 14368562/tftp-deploy-hnw5p4e_/ramdisk/ramdisk.cpio.gz
338 00:56:03.138505 - {ROOT_PART}: None
339 00:56:03.138552 - {ROOT}: None
340 00:56:03.138598 - {SERVER_IP}: 192.168.201.1
341 00:56:03.138645 - {TEE}: None
342 00:56:03.138698 Parsed boot commands:
343 00:56:03.138749 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:56:03.138897 Parsed boot commands: tftpboot 192.168.201.1 14368562/tftp-deploy-hnw5p4e_/kernel/image.itb 14368562/tftp-deploy-hnw5p4e_/kernel/cmdline
345 00:56:03.138977 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:56:03.139051 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:56:03.139131 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:56:03.139205 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:56:03.139264 Not connected, no need to disconnect.
350 00:56:03.139329 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:56:03.139401 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:56:03.139458 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 00:56:03.142782 Setting prompt string to ['lava-test: # ']
354 00:56:03.143167 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:56:03.143266 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:56:03.143360 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:56:03.143444 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:56:03.143617 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
359 00:56:09.789687 >> Command sent successfully.
360 00:56:09.803444 Returned 0 in 6 seconds
361 00:56:09.904157 end: 2.2.2.1 pdu-reboot (duration 00:00:07) [common]
363 00:56:09.904513 end: 2.2.2 reset-device (duration 00:00:07) [common]
364 00:56:09.904642 start: 2.2.3 depthcharge-start (timeout 00:04:53) [common]
365 00:56:09.904751 Setting prompt string to 'Starting depthcharge on Spherion...'
366 00:56:09.904836 Changing prompt to 'Starting depthcharge on Spherion...'
367 00:56:09.904933 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 00:56:09.905309 [Enter `^Ec?' for help]
369 00:56:09.905392
370 00:56:09.905462
371 00:56:09.905536 F0: 102B 0000
372 00:56:09.905592
373 00:56:09.905643 F3: 1001 0000 [0200]
374 00:56:09.905697
375 00:56:09.905753 F3: 1001 0000
376 00:56:09.905839
377 00:56:09.905917 F7: 102D 0000
378 00:56:09.906021
379 00:56:09.906149 F1: 0000 0000
380 00:56:09.906222
381 00:56:09.906277 V0: 0000 0000 [0001]
382 00:56:09.906332
383 00:56:09.906401 00: 0007 8000
384 00:56:09.906469
385 00:56:09.906521 01: 0000 0000
386 00:56:09.906570
387 00:56:09.906619 BP: 0C00 0209 [0000]
388 00:56:09.906695
389 00:56:09.906773 G0: 1182 0000
390 00:56:09.906825
391 00:56:09.906873 EC: 0000 0021 [4000]
392 00:56:09.906920
393 00:56:09.906967 S7: 0000 0000 [0000]
394 00:56:09.907014
395 00:56:09.907061 CC: 0000 0000 [0001]
396 00:56:09.907108
397 00:56:09.907155 T0: 0000 0040 [010F]
398 00:56:09.907202
399 00:56:09.907248 Jump to BL
400 00:56:09.907295
401 00:56:09.907343
402 00:56:09.907390
403 00:56:09.907437 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 00:56:09.908562 ARM64: Exception handlers installed.
405 00:56:09.911563 ARM64: Testing exception
406 00:56:09.914678 ARM64: Done test exception
407 00:56:09.921610 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 00:56:09.931191 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 00:56:09.938081 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 00:56:09.947927 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 00:56:09.954898 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 00:56:09.961204 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 00:56:09.973020 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 00:56:09.979786 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 00:56:09.999758 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 00:56:10.002679 WDT: Last reset was cold boot
417 00:56:10.006276 SPI1(PAD0) initialized at 2873684 Hz
418 00:56:10.009791 SPI5(PAD0) initialized at 992727 Hz
419 00:56:10.013230 VBOOT: Loading verstage.
420 00:56:10.019765 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 00:56:10.023197 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 00:56:10.026363 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 00:56:10.030049 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 00:56:10.037692 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 00:56:10.044062 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 00:56:10.054486 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
427 00:56:10.054988
428 00:56:10.055302
429 00:56:10.064914 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 00:56:10.068296 ARM64: Exception handlers installed.
431 00:56:10.072184 ARM64: Testing exception
432 00:56:10.072709 ARM64: Done test exception
433 00:56:10.077842 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 00:56:10.081393 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 00:56:10.095824 Probing TPM: . done!
436 00:56:10.096199 TPM ready after 0 ms
437 00:56:10.102507 Connected to device vid:did:rid of 1ae0:0028:00
438 00:56:10.108862 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 00:56:10.149389 Initialized TPM device CR50 revision 0
440 00:56:10.161183 tlcl_send_startup: Startup return code is 0
441 00:56:10.161275 TPM: setup succeeded
442 00:56:10.172708 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 00:56:10.181001 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 00:56:10.191548 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 00:56:10.200437 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 00:56:10.203831 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 00:56:10.207170 in-header: 03 07 00 00 08 00 00 00
448 00:56:10.210559 in-data: aa e4 47 04 13 02 00 00
449 00:56:10.213732 Chrome EC: UHEPI supported
450 00:56:10.220647 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 00:56:10.223717 in-header: 03 c9 00 00 08 00 00 00
452 00:56:10.227038 in-data: 04 00 20 08 00 00 00 00
453 00:56:10.227114 Phase 1
454 00:56:10.230456 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 00:56:10.237401 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 00:56:10.243892 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 00:56:10.247200 Recovery requested (1009000e)
458 00:56:10.251306 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 00:56:10.259476 tlcl_extend: response is 0
460 00:56:10.267808 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 00:56:10.273346 tlcl_extend: response is 0
462 00:56:10.280296 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 00:56:10.300710 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
464 00:56:10.307654 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 00:56:10.308060
466 00:56:10.308369
467 00:56:10.317665 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 00:56:10.320604 ARM64: Exception handlers installed.
469 00:56:10.324111 ARM64: Testing exception
470 00:56:10.324534 ARM64: Done test exception
471 00:56:10.346248 pmic_efuse_setting: Set efuses in 11 msecs
472 00:56:10.349704 pmwrap_interface_init: Select PMIF_VLD_RDY
473 00:56:10.356113 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 00:56:10.359632 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 00:56:10.366240 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 00:56:10.369731 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 00:56:10.375889 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 00:56:10.379048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 00:56:10.382950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 00:56:10.389652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 00:56:10.392790 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 00:56:10.399757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 00:56:10.403146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 00:56:10.406496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 00:56:10.412821 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 00:56:10.419556 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 00:56:10.422899 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 00:56:10.429629 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 00:56:10.436711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 00:56:10.439760 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 00:56:10.446159 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 00:56:10.453044 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 00:56:10.456444 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 00:56:10.463312 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 00:56:10.470167 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 00:56:10.473065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 00:56:10.479937 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 00:56:10.486797 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 00:56:10.490061 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 00:56:10.496587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 00:56:10.499896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 00:56:10.503481 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 00:56:10.510485 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 00:56:10.513650 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 00:56:10.520006 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 00:56:10.523479 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 00:56:10.530309 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 00:56:10.533866 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 00:56:10.540199 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 00:56:10.543543 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 00:56:10.550661 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 00:56:10.554002 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 00:56:10.557362 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 00:56:10.561442 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 00:56:10.568007 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 00:56:10.571229 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 00:56:10.574493 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 00:56:10.581318 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 00:56:10.584575 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 00:56:10.587427 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 00:56:10.591128 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 00:56:10.597663 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 00:56:10.600896 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 00:56:10.607841 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 00:56:10.618080 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 00:56:10.620970 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 00:56:10.631003 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 00:56:10.638270 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 00:56:10.640983 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 00:56:10.648040 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:56:10.651266 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:56:10.658285 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x30
533 00:56:10.664933 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 00:56:10.668435 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
535 00:56:10.671641 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 00:56:10.682952 [RTC]rtc_get_frequency_meter,154: input=15, output=791
537 00:56:10.692340 [RTC]rtc_get_frequency_meter,154: input=23, output=979
538 00:56:10.702004 [RTC]rtc_get_frequency_meter,154: input=19, output=886
539 00:56:10.711327 [RTC]rtc_get_frequency_meter,154: input=17, output=838
540 00:56:10.720986 [RTC]rtc_get_frequency_meter,154: input=16, output=813
541 00:56:10.730308 [RTC]rtc_get_frequency_meter,154: input=15, output=792
542 00:56:10.740329 [RTC]rtc_get_frequency_meter,154: input=16, output=814
543 00:56:10.743177 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
544 00:56:10.750480 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
545 00:56:10.754187 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 00:56:10.757534 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
547 00:56:10.763973 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 00:56:10.767271 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
549 00:56:10.770788 ADC[4]: Raw value=901697 ID=7
550 00:56:10.770862 ADC[3]: Raw value=213336 ID=1
551 00:56:10.773845 RAM Code: 0x71
552 00:56:10.777340 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 00:56:10.784113 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 00:56:10.790565 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 00:56:10.797491 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 00:56:10.801164 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 00:56:10.804188 in-header: 03 07 00 00 08 00 00 00
558 00:56:10.807438 in-data: aa e4 47 04 13 02 00 00
559 00:56:10.810668 Chrome EC: UHEPI supported
560 00:56:10.817873 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 00:56:10.820848 in-header: 03 c9 00 00 08 00 00 00
562 00:56:10.824105 in-data: 04 00 20 08 00 00 00 00
563 00:56:10.827389 MRC: failed to locate region type 0.
564 00:56:10.834479 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 00:56:10.837816 DRAM-K: Running full calibration
566 00:56:10.844156 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 00:56:10.844233 header.status = 0x0
568 00:56:10.847571 header.version = 0x6 (expected: 0x6)
569 00:56:10.851384 header.size = 0xd00 (expected: 0xd00)
570 00:56:10.854346 header.flags = 0x0
571 00:56:10.858149 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 00:56:10.877059 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
573 00:56:10.883607 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 00:56:10.886833 dram_init: ddr_geometry: 2
575 00:56:10.890181 [EMI] MDL number = 2
576 00:56:10.890252 [EMI] Get MDL freq = 0
577 00:56:10.893384 dram_init: ddr_type: 0
578 00:56:10.893454 is_discrete_lpddr4: 1
579 00:56:10.897361 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 00:56:10.897427
581 00:56:10.897482
582 00:56:10.900248 [Bian_co] ETT version 0.0.0.1
583 00:56:10.907167 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 00:56:10.907241
585 00:56:10.910132 dramc_set_vcore_voltage set vcore to 650000
586 00:56:10.910223 Read voltage for 800, 4
587 00:56:10.913565 Vio18 = 0
588 00:56:10.913672 Vcore = 650000
589 00:56:10.913762 Vdram = 0
590 00:56:10.917165 Vddq = 0
591 00:56:10.917241 Vmddr = 0
592 00:56:10.920507 dram_init: config_dvfs: 1
593 00:56:10.923558 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 00:56:10.930414 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 00:56:10.933874 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
596 00:56:10.937085 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
597 00:56:10.940744 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
598 00:56:10.944031 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
599 00:56:10.947136 MEM_TYPE=3, freq_sel=18
600 00:56:10.950493 sv_algorithm_assistance_LP4_1600
601 00:56:10.953797 ============ PULL DRAM RESETB DOWN ============
602 00:56:10.957366 ========== PULL DRAM RESETB DOWN end =========
603 00:56:10.963960 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 00:56:10.967708 ===================================
605 00:56:10.967785 LPDDR4 DRAM CONFIGURATION
606 00:56:10.970989 ===================================
607 00:56:10.974476 EX_ROW_EN[0] = 0x0
608 00:56:10.977440 EX_ROW_EN[1] = 0x0
609 00:56:10.977509 LP4Y_EN = 0x0
610 00:56:10.980698 WORK_FSP = 0x0
611 00:56:10.980769 WL = 0x2
612 00:56:10.984185 RL = 0x2
613 00:56:10.984260 BL = 0x2
614 00:56:10.987555 RPST = 0x0
615 00:56:10.987660 RD_PRE = 0x0
616 00:56:10.990789 WR_PRE = 0x1
617 00:56:10.990865 WR_PST = 0x0
618 00:56:10.994232 DBI_WR = 0x0
619 00:56:10.994308 DBI_RD = 0x0
620 00:56:10.997746 OTF = 0x1
621 00:56:11.000920 ===================================
622 00:56:11.004203 ===================================
623 00:56:11.004280 ANA top config
624 00:56:11.007676 ===================================
625 00:56:11.010957 DLL_ASYNC_EN = 0
626 00:56:11.014435 ALL_SLAVE_EN = 1
627 00:56:11.014517 NEW_RANK_MODE = 1
628 00:56:11.018046 DLL_IDLE_MODE = 1
629 00:56:11.021117 LP45_APHY_COMB_EN = 1
630 00:56:11.024550 TX_ODT_DIS = 1
631 00:56:11.024645 NEW_8X_MODE = 1
632 00:56:11.028173 ===================================
633 00:56:11.031426 ===================================
634 00:56:11.034632 data_rate = 1600
635 00:56:11.037720 CKR = 1
636 00:56:11.041300 DQ_P2S_RATIO = 8
637 00:56:11.044572 ===================================
638 00:56:11.048190 CA_P2S_RATIO = 8
639 00:56:11.051228 DQ_CA_OPEN = 0
640 00:56:11.051304 DQ_SEMI_OPEN = 0
641 00:56:11.055015 CA_SEMI_OPEN = 0
642 00:56:11.057921 CA_FULL_RATE = 0
643 00:56:11.061399 DQ_CKDIV4_EN = 1
644 00:56:11.064936 CA_CKDIV4_EN = 1
645 00:56:11.065011 CA_PREDIV_EN = 0
646 00:56:11.068330 PH8_DLY = 0
647 00:56:11.071867 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 00:56:11.075145 DQ_AAMCK_DIV = 4
649 00:56:11.078430 CA_AAMCK_DIV = 4
650 00:56:11.081342 CA_ADMCK_DIV = 4
651 00:56:11.081417 DQ_TRACK_CA_EN = 0
652 00:56:11.084720 CA_PICK = 800
653 00:56:11.088269 CA_MCKIO = 800
654 00:56:11.091688 MCKIO_SEMI = 0
655 00:56:11.095576 PLL_FREQ = 3068
656 00:56:11.098534 DQ_UI_PI_RATIO = 32
657 00:56:11.098610 CA_UI_PI_RATIO = 0
658 00:56:11.101895 ===================================
659 00:56:11.106350 ===================================
660 00:56:11.108594 memory_type:LPDDR4
661 00:56:11.112100 GP_NUM : 10
662 00:56:11.112176 SRAM_EN : 1
663 00:56:11.115318 MD32_EN : 0
664 00:56:11.118418 ===================================
665 00:56:11.121777 [ANA_INIT] >>>>>>>>>>>>>>
666 00:56:11.125250 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 00:56:11.128717 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 00:56:11.132166 ===================================
669 00:56:11.132242 data_rate = 1600,PCW = 0X7600
670 00:56:11.135888 ===================================
671 00:56:11.138616 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 00:56:11.145935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 00:56:11.151973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 00:56:11.155960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 00:56:11.158940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 00:56:11.162150 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 00:56:11.165702 [ANA_INIT] flow start
678 00:56:11.165838 [ANA_INIT] PLL >>>>>>>>
679 00:56:11.168691 [ANA_INIT] PLL <<<<<<<<
680 00:56:11.172206 [ANA_INIT] MIDPI >>>>>>>>
681 00:56:11.172322 [ANA_INIT] MIDPI <<<<<<<<
682 00:56:11.175796 [ANA_INIT] DLL >>>>>>>>
683 00:56:11.179251 [ANA_INIT] flow end
684 00:56:11.182658 ============ LP4 DIFF to SE enter ============
685 00:56:11.185560 ============ LP4 DIFF to SE exit ============
686 00:56:11.189053 [ANA_INIT] <<<<<<<<<<<<<
687 00:56:11.192625 [Flow] Enable top DCM control >>>>>
688 00:56:11.195493 [Flow] Enable top DCM control <<<<<
689 00:56:11.198982 Enable DLL master slave shuffle
690 00:56:11.202653 ==============================================================
691 00:56:11.206008 Gating Mode config
692 00:56:11.212540 ==============================================================
693 00:56:11.212815 Config description:
694 00:56:11.222932 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 00:56:11.229909 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 00:56:11.232849 SELPH_MODE 0: By rank 1: By Phase
697 00:56:11.239816 ==============================================================
698 00:56:11.243109 GAT_TRACK_EN = 1
699 00:56:11.246074 RX_GATING_MODE = 2
700 00:56:11.250012 RX_GATING_TRACK_MODE = 2
701 00:56:11.253182 SELPH_MODE = 1
702 00:56:11.256495 PICG_EARLY_EN = 1
703 00:56:11.256886 VALID_LAT_VALUE = 1
704 00:56:11.263083 ==============================================================
705 00:56:11.266159 Enter into Gating configuration >>>>
706 00:56:11.270125 Exit from Gating configuration <<<<
707 00:56:11.272871 Enter into DVFS_PRE_config >>>>>
708 00:56:11.282950 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 00:56:11.286535 Exit from DVFS_PRE_config <<<<<
710 00:56:11.289593 Enter into PICG configuration >>>>
711 00:56:11.292894 Exit from PICG configuration <<<<
712 00:56:11.296895 [RX_INPUT] configuration >>>>>
713 00:56:11.299691 [RX_INPUT] configuration <<<<<
714 00:56:11.303610 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 00:56:11.309901 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 00:56:11.316822 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 00:56:11.323594 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 00:56:11.326814 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 00:56:11.333523 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 00:56:11.336943 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 00:56:11.343632 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 00:56:11.346343 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 00:56:11.350108 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 00:56:11.352976 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 00:56:11.360169 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 00:56:11.362892 ===================================
727 00:56:11.363104 LPDDR4 DRAM CONFIGURATION
728 00:56:11.366627 ===================================
729 00:56:11.369538 EX_ROW_EN[0] = 0x0
730 00:56:11.373073 EX_ROW_EN[1] = 0x0
731 00:56:11.373282 LP4Y_EN = 0x0
732 00:56:11.376438 WORK_FSP = 0x0
733 00:56:11.376647 WL = 0x2
734 00:56:11.379977 RL = 0x2
735 00:56:11.380401 BL = 0x2
736 00:56:11.383754 RPST = 0x0
737 00:56:11.384240 RD_PRE = 0x0
738 00:56:11.386603 WR_PRE = 0x1
739 00:56:11.386996 WR_PST = 0x0
740 00:56:11.390411 DBI_WR = 0x0
741 00:56:11.390800 DBI_RD = 0x0
742 00:56:11.393355 OTF = 0x1
743 00:56:11.396486 ===================================
744 00:56:11.399818 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 00:56:11.403251 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 00:56:11.409855 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 00:56:11.413288 ===================================
748 00:56:11.413499 LPDDR4 DRAM CONFIGURATION
749 00:56:11.416558 ===================================
750 00:56:11.420176 EX_ROW_EN[0] = 0x10
751 00:56:11.420389 EX_ROW_EN[1] = 0x0
752 00:56:11.423519 LP4Y_EN = 0x0
753 00:56:11.426367 WORK_FSP = 0x0
754 00:56:11.426577 WL = 0x2
755 00:56:11.430312 RL = 0x2
756 00:56:11.430522 BL = 0x2
757 00:56:11.433043 RPST = 0x0
758 00:56:11.433252 RD_PRE = 0x0
759 00:56:11.436619 WR_PRE = 0x1
760 00:56:11.436830 WR_PST = 0x0
761 00:56:11.439769 DBI_WR = 0x0
762 00:56:11.439980 DBI_RD = 0x0
763 00:56:11.443153 OTF = 0x1
764 00:56:11.446467 ===================================
765 00:56:11.449874 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 00:56:11.455672 nWR fixed to 40
767 00:56:11.458578 [ModeRegInit_LP4] CH0 RK0
768 00:56:11.458789 [ModeRegInit_LP4] CH0 RK1
769 00:56:11.462362 [ModeRegInit_LP4] CH1 RK0
770 00:56:11.466004 [ModeRegInit_LP4] CH1 RK1
771 00:56:11.466264 match AC timing 13
772 00:56:11.471957 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 00:56:11.475394 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 00:56:11.479115 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 00:56:11.485513 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 00:56:11.489245 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 00:56:11.489640 [EMI DOE] emi_dcm 0
778 00:56:11.495866 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 00:56:11.496374 ==
780 00:56:11.499231 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:56:11.502750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 00:56:11.503148 ==
783 00:56:11.509257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 00:56:11.512806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 00:56:11.523116 [CA 0] Center 37 (7~68) winsize 62
786 00:56:11.526353 [CA 1] Center 37 (6~68) winsize 63
787 00:56:11.530037 [CA 2] Center 35 (5~66) winsize 62
788 00:56:11.533255 [CA 3] Center 35 (4~66) winsize 63
789 00:56:11.536990 [CA 4] Center 34 (3~65) winsize 63
790 00:56:11.540185 [CA 5] Center 33 (3~64) winsize 62
791 00:56:11.540575
792 00:56:11.542972 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 00:56:11.543365
794 00:56:11.546933 [CATrainingPosCal] consider 1 rank data
795 00:56:11.550047 u2DelayCellTimex100 = 270/100 ps
796 00:56:11.553444 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 00:56:11.556880 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 00:56:11.560241 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
799 00:56:11.563635 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
800 00:56:11.570528 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
801 00:56:11.573792 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 00:56:11.574022
803 00:56:11.576891 CA PerBit enable=1, Macro0, CA PI delay=33
804 00:56:11.577102
805 00:56:11.580643 [CBTSetCACLKResult] CA Dly = 33
806 00:56:11.580894 CS Dly: 5 (0~36)
807 00:56:11.581066 ==
808 00:56:11.584062 Dram Type= 6, Freq= 0, CH_0, rank 1
809 00:56:11.590292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 00:56:11.590545 ==
811 00:56:11.593455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 00:56:11.600297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 00:56:11.609204 [CA 0] Center 37 (6~68) winsize 63
814 00:56:11.612439 [CA 1] Center 37 (7~68) winsize 62
815 00:56:11.615883 [CA 2] Center 35 (5~66) winsize 62
816 00:56:11.619149 [CA 3] Center 35 (4~66) winsize 63
817 00:56:11.622548 [CA 4] Center 34 (4~65) winsize 62
818 00:56:11.625876 [CA 5] Center 33 (3~64) winsize 62
819 00:56:11.626135
820 00:56:11.629382 [CmdBusTrainingLP45] Vref(ca) range 1: 32
821 00:56:11.629593
822 00:56:11.632916 [CATrainingPosCal] consider 2 rank data
823 00:56:11.636264 u2DelayCellTimex100 = 270/100 ps
824 00:56:11.639709 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 00:56:11.642495 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 00:56:11.649450 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
827 00:56:11.653158 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
828 00:56:11.656423 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
829 00:56:11.659449 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 00:56:11.659732
831 00:56:11.662801 CA PerBit enable=1, Macro0, CA PI delay=33
832 00:56:11.663072
833 00:56:11.666247 [CBTSetCACLKResult] CA Dly = 33
834 00:56:11.666492 CS Dly: 5 (0~37)
835 00:56:11.666715
836 00:56:11.669924 ----->DramcWriteLeveling(PI) begin...
837 00:56:11.673034 ==
838 00:56:11.673310 Dram Type= 6, Freq= 0, CH_0, rank 0
839 00:56:11.679392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 00:56:11.679617 ==
841 00:56:11.683125 Write leveling (Byte 0): 31 => 31
842 00:56:11.686322 Write leveling (Byte 1): 28 => 28
843 00:56:11.689632 DramcWriteLeveling(PI) end<-----
844 00:56:11.689842
845 00:56:11.690029 ==
846 00:56:11.692614 Dram Type= 6, Freq= 0, CH_0, rank 0
847 00:56:11.696277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 00:56:11.696489 ==
849 00:56:11.699690 [Gating] SW mode calibration
850 00:56:11.705803 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 00:56:11.709750 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 00:56:11.716094 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 00:56:11.719711 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 00:56:11.723448 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
855 00:56:11.729537 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:56:11.733323 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:56:11.736457 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:56:11.742617 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:56:11.746126 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:56:11.749630 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:56:11.756234 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:56:11.759687 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:56:11.763016 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:56:11.769820 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:56:11.773340 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:56:11.776045 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:56:11.783054 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:56:11.786514 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 00:56:11.789689 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 00:56:11.796220 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 00:56:11.799623 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:56:11.802943 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 00:56:11.809417 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:56:11.812539 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 00:56:11.816131 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 00:56:11.819400 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 00:56:11.826102 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 00:56:11.829397 0 9 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
879 00:56:11.832701 0 9 12 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
880 00:56:11.839387 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 00:56:11.843033 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:56:11.846264 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 00:56:11.852769 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 00:56:11.856212 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 00:56:11.859822 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
886 00:56:11.866368 0 10 8 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
887 00:56:11.869946 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
888 00:56:11.873315 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 00:56:11.879788 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:56:11.882961 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 00:56:11.886433 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 00:56:11.892988 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 00:56:11.896757 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 00:56:11.899544 0 11 8 | B1->B0 | 2424 3030 | 0 1 | (0 0) (0 0)
895 00:56:11.903244 0 11 12 | B1->B0 | 3737 3f3f | 1 0 | (0 0) (0 0)
896 00:56:11.909886 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 00:56:11.913240 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 00:56:11.916335 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 00:56:11.923395 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 00:56:11.926293 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 00:56:11.929648 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 00:56:11.936387 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
903 00:56:11.939794 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:56:11.942895 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:56:11.949823 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:56:11.952803 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:56:11.955996 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:56:11.963106 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:56:11.965930 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:56:11.969450 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:56:11.976680 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:56:11.979728 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:56:11.983271 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:56:11.989755 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 00:56:11.993237 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 00:56:11.996685 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 00:56:11.999919 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 00:56:12.006461 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 00:56:12.010144 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 00:56:12.012949 Total UI for P1: 0, mck2ui 16
921 00:56:12.016579 best dqsien dly found for B0: ( 0, 14, 8)
922 00:56:12.019797 Total UI for P1: 0, mck2ui 16
923 00:56:12.023506 best dqsien dly found for B1: ( 0, 14, 10)
924 00:56:12.026251 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
925 00:56:12.029801 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
926 00:56:12.030261
927 00:56:12.033295 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
928 00:56:12.036688 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
929 00:56:12.039920 [Gating] SW calibration Done
930 00:56:12.040424 ==
931 00:56:12.043663 Dram Type= 6, Freq= 0, CH_0, rank 0
932 00:56:12.046516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 00:56:12.050203 ==
934 00:56:12.050716 RX Vref Scan: 0
935 00:56:12.051053
936 00:56:12.053607 RX Vref 0 -> 0, step: 1
937 00:56:12.054147
938 00:56:12.056630 RX Delay -130 -> 252, step: 16
939 00:56:12.060076 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
940 00:56:12.063194 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
941 00:56:12.066377 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
942 00:56:12.069954 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
943 00:56:12.076523 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
944 00:56:12.079681 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
945 00:56:12.082973 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
946 00:56:12.086311 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
947 00:56:12.090084 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
948 00:56:12.096696 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
949 00:56:12.099594 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
950 00:56:12.103069 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 00:56:12.106550 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
952 00:56:12.109676 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
953 00:56:12.116557 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
954 00:56:12.120052 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
955 00:56:12.120442 ==
956 00:56:12.123447 Dram Type= 6, Freq= 0, CH_0, rank 0
957 00:56:12.126915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 00:56:12.127311 ==
959 00:56:12.129530 DQS Delay:
960 00:56:12.129963 DQS0 = 0, DQS1 = 0
961 00:56:12.130313 DQM Delay:
962 00:56:12.133044 DQM0 = 84, DQM1 = 73
963 00:56:12.133443 DQ Delay:
964 00:56:12.136788 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
965 00:56:12.140237 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
966 00:56:12.142973 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
967 00:56:12.146303 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =85
968 00:56:12.146697
969 00:56:12.147002
970 00:56:12.147281 ==
971 00:56:12.150198 Dram Type= 6, Freq= 0, CH_0, rank 0
972 00:56:12.153310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 00:56:12.156825 ==
974 00:56:12.157289
975 00:56:12.157595
976 00:56:12.157877 TX Vref Scan disable
977 00:56:12.160228 == TX Byte 0 ==
978 00:56:12.163318 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
979 00:56:12.166637 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
980 00:56:12.170128 == TX Byte 1 ==
981 00:56:12.173073 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
982 00:56:12.177044 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
983 00:56:12.179626 ==
984 00:56:12.183360 Dram Type= 6, Freq= 0, CH_0, rank 0
985 00:56:12.186240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 00:56:12.186743 ==
987 00:56:12.199240 TX Vref=22, minBit 5, minWin=27, winSum=443
988 00:56:12.202815 TX Vref=24, minBit 5, minWin=27, winSum=446
989 00:56:12.206386 TX Vref=26, minBit 12, minWin=27, winSum=451
990 00:56:12.209671 TX Vref=28, minBit 12, minWin=27, winSum=455
991 00:56:12.212478 TX Vref=30, minBit 12, minWin=27, winSum=455
992 00:56:12.216413 TX Vref=32, minBit 8, minWin=28, winSum=458
993 00:56:12.223070 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
994 00:56:12.223573
995 00:56:12.226411 Final TX Range 1 Vref 32
996 00:56:12.226854
997 00:56:12.227188 ==
998 00:56:12.229819 Dram Type= 6, Freq= 0, CH_0, rank 0
999 00:56:12.233537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 00:56:12.234110 ==
1001 00:56:12.234458
1002 00:56:12.235853
1003 00:56:12.236287 TX Vref Scan disable
1004 00:56:12.239598 == TX Byte 0 ==
1005 00:56:12.242632 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1006 00:56:12.246270 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1007 00:56:12.249945 == TX Byte 1 ==
1008 00:56:12.252807 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1009 00:56:12.256319 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1010 00:56:12.259470
1011 00:56:12.259901 [DATLAT]
1012 00:56:12.260242 Freq=800, CH0 RK0
1013 00:56:12.260558
1014 00:56:12.262880 DATLAT Default: 0xa
1015 00:56:12.263309 0, 0xFFFF, sum = 0
1016 00:56:12.266099 1, 0xFFFF, sum = 0
1017 00:56:12.266541 2, 0xFFFF, sum = 0
1018 00:56:12.269500 3, 0xFFFF, sum = 0
1019 00:56:12.269934 4, 0xFFFF, sum = 0
1020 00:56:12.273143 5, 0xFFFF, sum = 0
1021 00:56:12.273683 6, 0xFFFF, sum = 0
1022 00:56:12.276256 7, 0xFFFF, sum = 0
1023 00:56:12.279506 8, 0xFFFF, sum = 0
1024 00:56:12.279952 9, 0x0, sum = 1
1025 00:56:12.280296 10, 0x0, sum = 2
1026 00:56:12.282825 11, 0x0, sum = 3
1027 00:56:12.283222 12, 0x0, sum = 4
1028 00:56:12.286363 best_step = 10
1029 00:56:12.286792
1030 00:56:12.287100 ==
1031 00:56:12.289955 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 00:56:12.292816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 00:56:12.293227 ==
1034 00:56:12.295994 RX Vref Scan: 1
1035 00:56:12.296383
1036 00:56:12.296685 Set Vref Range= 32 -> 127
1037 00:56:12.296967
1038 00:56:12.299724 RX Vref 32 -> 127, step: 1
1039 00:56:12.300114
1040 00:56:12.302715 RX Delay -111 -> 252, step: 8
1041 00:56:12.303102
1042 00:56:12.306360 Set Vref, RX VrefLevel [Byte0]: 32
1043 00:56:12.309517 [Byte1]: 32
1044 00:56:12.310114
1045 00:56:12.312564 Set Vref, RX VrefLevel [Byte0]: 33
1046 00:56:12.316253 [Byte1]: 33
1047 00:56:12.319858
1048 00:56:12.320404 Set Vref, RX VrefLevel [Byte0]: 34
1049 00:56:12.323134 [Byte1]: 34
1050 00:56:12.327612
1051 00:56:12.328095 Set Vref, RX VrefLevel [Byte0]: 35
1052 00:56:12.330817 [Byte1]: 35
1053 00:56:12.335141
1054 00:56:12.335530 Set Vref, RX VrefLevel [Byte0]: 36
1055 00:56:12.338691 [Byte1]: 36
1056 00:56:12.343150
1057 00:56:12.343616 Set Vref, RX VrefLevel [Byte0]: 37
1058 00:56:12.345978 [Byte1]: 37
1059 00:56:12.351117
1060 00:56:12.351635 Set Vref, RX VrefLevel [Byte0]: 38
1061 00:56:12.353776 [Byte1]: 38
1062 00:56:12.358379
1063 00:56:12.358805 Set Vref, RX VrefLevel [Byte0]: 39
1064 00:56:12.361330 [Byte1]: 39
1065 00:56:12.366128
1066 00:56:12.366634 Set Vref, RX VrefLevel [Byte0]: 40
1067 00:56:12.369282 [Byte1]: 40
1068 00:56:12.373802
1069 00:56:12.374342 Set Vref, RX VrefLevel [Byte0]: 41
1070 00:56:12.376887 [Byte1]: 41
1071 00:56:12.381545
1072 00:56:12.382106 Set Vref, RX VrefLevel [Byte0]: 42
1073 00:56:12.384609 [Byte1]: 42
1074 00:56:12.388463
1075 00:56:12.388895 Set Vref, RX VrefLevel [Byte0]: 43
1076 00:56:12.392262 [Byte1]: 43
1077 00:56:12.396367
1078 00:56:12.396796 Set Vref, RX VrefLevel [Byte0]: 44
1079 00:56:12.400139 [Byte1]: 44
1080 00:56:12.404346
1081 00:56:12.404856 Set Vref, RX VrefLevel [Byte0]: 45
1082 00:56:12.407561 [Byte1]: 45
1083 00:56:12.411389
1084 00:56:12.411871 Set Vref, RX VrefLevel [Byte0]: 46
1085 00:56:12.414798 [Byte1]: 46
1086 00:56:12.419432
1087 00:56:12.419938 Set Vref, RX VrefLevel [Byte0]: 47
1088 00:56:12.422687 [Byte1]: 47
1089 00:56:12.426871
1090 00:56:12.427300 Set Vref, RX VrefLevel [Byte0]: 48
1091 00:56:12.430560 [Byte1]: 48
1092 00:56:12.434346
1093 00:56:12.437926 Set Vref, RX VrefLevel [Byte0]: 49
1094 00:56:12.438478 [Byte1]: 49
1095 00:56:12.442461
1096 00:56:12.442893 Set Vref, RX VrefLevel [Byte0]: 50
1097 00:56:12.445808 [Byte1]: 50
1098 00:56:12.450059
1099 00:56:12.450679 Set Vref, RX VrefLevel [Byte0]: 51
1100 00:56:12.453368 [Byte1]: 51
1101 00:56:12.457707
1102 00:56:12.458174 Set Vref, RX VrefLevel [Byte0]: 52
1103 00:56:12.460853 [Byte1]: 52
1104 00:56:12.465543
1105 00:56:12.466009 Set Vref, RX VrefLevel [Byte0]: 53
1106 00:56:12.468280 [Byte1]: 53
1107 00:56:12.472839
1108 00:56:12.473231 Set Vref, RX VrefLevel [Byte0]: 54
1109 00:56:12.475956 [Byte1]: 54
1110 00:56:12.480569
1111 00:56:12.480968 Set Vref, RX VrefLevel [Byte0]: 55
1112 00:56:12.483592 [Byte1]: 55
1113 00:56:12.487908
1114 00:56:12.488295 Set Vref, RX VrefLevel [Byte0]: 56
1115 00:56:12.491585 [Byte1]: 56
1116 00:56:12.495842
1117 00:56:12.496308 Set Vref, RX VrefLevel [Byte0]: 57
1118 00:56:12.499417 [Byte1]: 57
1119 00:56:12.503933
1120 00:56:12.504440 Set Vref, RX VrefLevel [Byte0]: 58
1121 00:56:12.506871 [Byte1]: 58
1122 00:56:12.511202
1123 00:56:12.511677 Set Vref, RX VrefLevel [Byte0]: 59
1124 00:56:12.514295 [Byte1]: 59
1125 00:56:12.518928
1126 00:56:12.519435 Set Vref, RX VrefLevel [Byte0]: 60
1127 00:56:12.521737 [Byte1]: 60
1128 00:56:12.526406
1129 00:56:12.526892 Set Vref, RX VrefLevel [Byte0]: 61
1130 00:56:12.529497 [Byte1]: 61
1131 00:56:12.533857
1132 00:56:12.537444 Set Vref, RX VrefLevel [Byte0]: 62
1133 00:56:12.540529 [Byte1]: 62
1134 00:56:12.540958
1135 00:56:12.543609 Set Vref, RX VrefLevel [Byte0]: 63
1136 00:56:12.547055 [Byte1]: 63
1137 00:56:12.547488
1138 00:56:12.550052 Set Vref, RX VrefLevel [Byte0]: 64
1139 00:56:12.553850 [Byte1]: 64
1140 00:56:12.554282
1141 00:56:12.556855 Set Vref, RX VrefLevel [Byte0]: 65
1142 00:56:12.560280 [Byte1]: 65
1143 00:56:12.564635
1144 00:56:12.565114 Set Vref, RX VrefLevel [Byte0]: 66
1145 00:56:12.567817 [Byte1]: 66
1146 00:56:12.572116
1147 00:56:12.572655 Set Vref, RX VrefLevel [Byte0]: 67
1148 00:56:12.575632 [Byte1]: 67
1149 00:56:12.579483
1150 00:56:12.579879 Set Vref, RX VrefLevel [Byte0]: 68
1151 00:56:12.583207 [Byte1]: 68
1152 00:56:12.587232
1153 00:56:12.587726 Set Vref, RX VrefLevel [Byte0]: 69
1154 00:56:12.590646 [Byte1]: 69
1155 00:56:12.595278
1156 00:56:12.595748 Set Vref, RX VrefLevel [Byte0]: 70
1157 00:56:12.598454 [Byte1]: 70
1158 00:56:12.602837
1159 00:56:12.603226 Set Vref, RX VrefLevel [Byte0]: 71
1160 00:56:12.605795 [Byte1]: 71
1161 00:56:12.610428
1162 00:56:12.610941 Set Vref, RX VrefLevel [Byte0]: 72
1163 00:56:12.613310 [Byte1]: 72
1164 00:56:12.617723
1165 00:56:12.618223 Set Vref, RX VrefLevel [Byte0]: 73
1166 00:56:12.621458 [Byte1]: 73
1167 00:56:12.625703
1168 00:56:12.626213 Set Vref, RX VrefLevel [Byte0]: 74
1169 00:56:12.628794 [Byte1]: 74
1170 00:56:12.633295
1171 00:56:12.633961 Set Vref, RX VrefLevel [Byte0]: 75
1172 00:56:12.636761 [Byte1]: 75
1173 00:56:12.640750
1174 00:56:12.641143 Set Vref, RX VrefLevel [Byte0]: 76
1175 00:56:12.644314 [Byte1]: 76
1176 00:56:12.648446
1177 00:56:12.648847 Final RX Vref Byte 0 = 60 to rank0
1178 00:56:12.651868 Final RX Vref Byte 1 = 56 to rank0
1179 00:56:12.654918 Final RX Vref Byte 0 = 60 to rank1
1180 00:56:12.658458 Final RX Vref Byte 1 = 56 to rank1==
1181 00:56:12.662247 Dram Type= 6, Freq= 0, CH_0, rank 0
1182 00:56:12.668479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1183 00:56:12.668872 ==
1184 00:56:12.669181 DQS Delay:
1185 00:56:12.669463 DQS0 = 0, DQS1 = 0
1186 00:56:12.672052 DQM Delay:
1187 00:56:12.672442 DQM0 = 88, DQM1 = 78
1188 00:56:12.675400 DQ Delay:
1189 00:56:12.678411 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1190 00:56:12.678813 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1191 00:56:12.681949 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1192 00:56:12.685160 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1193 00:56:12.688594
1194 00:56:12.688994
1195 00:56:12.694979 [DQSOSCAuto] RK0, (LSB)MR18= 0x3017, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
1196 00:56:12.698534 CH0 RK0: MR19=606, MR18=3017
1197 00:56:12.705350 CH0_RK0: MR19=0x606, MR18=0x3017, DQSOSC=397, MR23=63, INC=93, DEC=62
1198 00:56:12.705602
1199 00:56:12.708148 ----->DramcWriteLeveling(PI) begin...
1200 00:56:12.708326 ==
1201 00:56:12.711587 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 00:56:12.715087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1203 00:56:12.715259 ==
1204 00:56:12.718221 Write leveling (Byte 0): 29 => 29
1205 00:56:12.721721 Write leveling (Byte 1): 29 => 29
1206 00:56:12.725315 DramcWriteLeveling(PI) end<-----
1207 00:56:12.725445
1208 00:56:12.725531 ==
1209 00:56:12.728011 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 00:56:12.731452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 00:56:12.731564 ==
1212 00:56:12.734688 [Gating] SW mode calibration
1213 00:56:12.741890 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1214 00:56:12.748585 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1215 00:56:12.751825 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1216 00:56:12.755198 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 00:56:12.762117 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1218 00:56:12.765091 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 00:56:12.768377 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 00:56:12.775051 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 00:56:12.778958 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 00:56:12.823194 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 00:56:12.823747 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 00:56:12.824123 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:56:12.824483 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:56:12.825142 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:56:12.825470 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:56:12.825770 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:56:12.826119 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 00:56:12.826421 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 00:56:12.826744 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:56:12.827815 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1233 00:56:12.830856 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1234 00:56:12.834236 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:56:12.840823 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:56:12.844398 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:56:12.847957 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:56:12.854570 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 00:56:12.857977 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 00:56:12.861081 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1241 00:56:12.867481 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1242 00:56:12.871070 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1243 00:56:12.874031 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 00:56:12.877560 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 00:56:12.884483 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 00:56:12.887531 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 00:56:12.890731 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1248 00:56:12.897611 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
1249 00:56:12.900756 0 10 8 | B1->B0 | 3232 2929 | 1 0 | (1 0) (1 1)
1250 00:56:12.903936 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1251 00:56:12.910405 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 00:56:12.913732 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 00:56:12.917179 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 00:56:12.923703 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 00:56:12.927660 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 00:56:12.930387 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1257 00:56:12.937362 0 11 8 | B1->B0 | 2c2c 4040 | 0 0 | (0 0) (0 0)
1258 00:56:12.940656 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1259 00:56:12.944673 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 00:56:12.950778 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 00:56:12.954243 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 00:56:12.957764 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 00:56:12.961224 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 00:56:12.967572 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1265 00:56:12.971283 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1266 00:56:12.974212 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1267 00:56:12.980724 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 00:56:12.987196 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 00:56:12.987985 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 00:56:12.994816 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 00:56:12.998342 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 00:56:13.000933 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 00:56:13.007622 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 00:56:13.011390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 00:56:13.014726 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 00:56:13.021188 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 00:56:13.024472 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 00:56:13.027973 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 00:56:13.034379 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 00:56:13.037859 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 00:56:13.041361 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1282 00:56:13.044828 Total UI for P1: 0, mck2ui 16
1283 00:56:13.048181 best dqsien dly found for B0: ( 0, 14, 6)
1284 00:56:13.051634 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1285 00:56:13.058075 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 00:56:13.061577 Total UI for P1: 0, mck2ui 16
1287 00:56:13.064648 best dqsien dly found for B1: ( 0, 14, 10)
1288 00:56:13.067941 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1289 00:56:13.071379 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1290 00:56:13.071449
1291 00:56:13.074082 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1292 00:56:13.077923 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1293 00:56:13.080815 [Gating] SW calibration Done
1294 00:56:13.080883 ==
1295 00:56:13.084227 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 00:56:13.087567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 00:56:13.087632 ==
1298 00:56:13.090932 RX Vref Scan: 0
1299 00:56:13.091020
1300 00:56:13.091100 RX Vref 0 -> 0, step: 1
1301 00:56:13.091186
1302 00:56:13.094304 RX Delay -130 -> 252, step: 16
1303 00:56:13.101154 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1304 00:56:13.104585 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1305 00:56:13.107470 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1306 00:56:13.111032 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1307 00:56:13.114417 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1308 00:56:13.117886 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1309 00:56:13.124474 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1310 00:56:13.127816 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1311 00:56:13.131180 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1312 00:56:13.134430 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1313 00:56:13.141084 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1314 00:56:13.143995 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1315 00:56:13.147461 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1316 00:56:13.151055 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1317 00:56:13.154520 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1318 00:56:13.161113 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1319 00:56:13.161205 ==
1320 00:56:13.164622 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 00:56:13.167934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 00:56:13.168009 ==
1323 00:56:13.168067 DQS Delay:
1324 00:56:13.170865 DQS0 = 0, DQS1 = 0
1325 00:56:13.170940 DQM Delay:
1326 00:56:13.174326 DQM0 = 88, DQM1 = 78
1327 00:56:13.174423 DQ Delay:
1328 00:56:13.177561 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1329 00:56:13.181061 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
1330 00:56:13.184370 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1331 00:56:13.187651 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1332 00:56:13.187725
1333 00:56:13.187782
1334 00:56:13.187834 ==
1335 00:56:13.191416 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 00:56:13.194348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 00:56:13.194423 ==
1338 00:56:13.194481
1339 00:56:13.194535
1340 00:56:13.197585 TX Vref Scan disable
1341 00:56:13.200831 == TX Byte 0 ==
1342 00:56:13.204641 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1343 00:56:13.207690 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1344 00:56:13.211058 == TX Byte 1 ==
1345 00:56:13.214158 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1346 00:56:13.217977 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1347 00:56:13.218086 ==
1348 00:56:13.220819 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 00:56:13.227610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 00:56:13.227687 ==
1351 00:56:13.239013 TX Vref=22, minBit 2, minWin=27, winSum=442
1352 00:56:13.242266 TX Vref=24, minBit 3, minWin=27, winSum=447
1353 00:56:13.245916 TX Vref=26, minBit 3, minWin=27, winSum=449
1354 00:56:13.249211 TX Vref=28, minBit 7, minWin=27, winSum=450
1355 00:56:13.252810 TX Vref=30, minBit 0, minWin=28, winSum=454
1356 00:56:13.255680 TX Vref=32, minBit 0, minWin=28, winSum=454
1357 00:56:13.262805 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1358 00:56:13.262882
1359 00:56:13.266020 Final TX Range 1 Vref 30
1360 00:56:13.266133
1361 00:56:13.266191 ==
1362 00:56:13.269442 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 00:56:13.272361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 00:56:13.272439 ==
1365 00:56:13.272497
1366 00:56:13.272550
1367 00:56:13.275726 TX Vref Scan disable
1368 00:56:13.278993 == TX Byte 0 ==
1369 00:56:13.282732 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1370 00:56:13.286430 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1371 00:56:13.289305 == TX Byte 1 ==
1372 00:56:13.292723 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1373 00:56:13.295962 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1374 00:56:13.296037
1375 00:56:13.299107 [DATLAT]
1376 00:56:13.299181 Freq=800, CH0 RK1
1377 00:56:13.299239
1378 00:56:13.302771 DATLAT Default: 0xa
1379 00:56:13.302846 0, 0xFFFF, sum = 0
1380 00:56:13.306020 1, 0xFFFF, sum = 0
1381 00:56:13.306110 2, 0xFFFF, sum = 0
1382 00:56:13.309528 3, 0xFFFF, sum = 0
1383 00:56:13.309603 4, 0xFFFF, sum = 0
1384 00:56:13.312771 5, 0xFFFF, sum = 0
1385 00:56:13.312847 6, 0xFFFF, sum = 0
1386 00:56:13.315952 7, 0xFFFF, sum = 0
1387 00:56:13.316045 8, 0xFFFF, sum = 0
1388 00:56:13.319720 9, 0x0, sum = 1
1389 00:56:13.319796 10, 0x0, sum = 2
1390 00:56:13.322605 11, 0x0, sum = 3
1391 00:56:13.322680 12, 0x0, sum = 4
1392 00:56:13.326379 best_step = 10
1393 00:56:13.326452
1394 00:56:13.326509 ==
1395 00:56:13.329382 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 00:56:13.332522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 00:56:13.332621 ==
1398 00:56:13.335923 RX Vref Scan: 0
1399 00:56:13.335998
1400 00:56:13.336057 RX Vref 0 -> 0, step: 1
1401 00:56:13.336111
1402 00:56:13.339257 RX Delay -95 -> 252, step: 8
1403 00:56:13.346028 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1404 00:56:13.349558 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1405 00:56:13.352577 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1406 00:56:13.355849 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1407 00:56:13.359269 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1408 00:56:13.366204 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1409 00:56:13.369232 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1410 00:56:13.372498 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1411 00:56:13.375917 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1412 00:56:13.379397 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1413 00:56:13.386066 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1414 00:56:13.389363 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1415 00:56:13.392387 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1416 00:56:13.395895 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1417 00:56:13.399310 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1418 00:56:13.406087 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1419 00:56:13.406179 ==
1420 00:56:13.409292 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 00:56:13.413002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 00:56:13.413098 ==
1423 00:56:13.413183 DQS Delay:
1424 00:56:13.415769 DQS0 = 0, DQS1 = 0
1425 00:56:13.415840 DQM Delay:
1426 00:56:13.419420 DQM0 = 87, DQM1 = 77
1427 00:56:13.419488 DQ Delay:
1428 00:56:13.422955 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1429 00:56:13.425750 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1430 00:56:13.429694 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1431 00:56:13.432438 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1432 00:56:13.432536
1433 00:56:13.432620
1434 00:56:13.440434 [DQSOSCAuto] RK1, (LSB)MR18= 0x341e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1435 00:56:13.443012 CH0 RK1: MR19=606, MR18=341E
1436 00:56:13.449191 CH0_RK1: MR19=0x606, MR18=0x341E, DQSOSC=396, MR23=63, INC=94, DEC=62
1437 00:56:13.452706 [RxdqsGatingPostProcess] freq 800
1438 00:56:13.459778 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 00:56:13.459854 Pre-setting of DQS Precalculation
1440 00:56:13.465857 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 00:56:13.465932 ==
1442 00:56:13.469258 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 00:56:13.472699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 00:56:13.472776 ==
1445 00:56:13.479546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 00:56:13.486509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 00:56:13.493892 [CA 0] Center 36 (6~66) winsize 61
1448 00:56:13.497360 [CA 1] Center 36 (6~66) winsize 61
1449 00:56:13.500687 [CA 2] Center 35 (5~65) winsize 61
1450 00:56:13.504054 [CA 3] Center 34 (3~65) winsize 63
1451 00:56:13.507405 [CA 4] Center 34 (4~65) winsize 62
1452 00:56:13.510728 [CA 5] Center 33 (3~64) winsize 62
1453 00:56:13.510803
1454 00:56:13.514178 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1455 00:56:13.514254
1456 00:56:13.517557 [CATrainingPosCal] consider 1 rank data
1457 00:56:13.520677 u2DelayCellTimex100 = 270/100 ps
1458 00:56:13.524247 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1459 00:56:13.527468 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1460 00:56:13.533799 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1461 00:56:13.537139 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1462 00:56:13.540644 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1463 00:56:13.544119 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 00:56:13.544208
1465 00:56:13.547438 CA PerBit enable=1, Macro0, CA PI delay=33
1466 00:56:13.547540
1467 00:56:13.550553 [CBTSetCACLKResult] CA Dly = 33
1468 00:56:13.550628 CS Dly: 4 (0~35)
1469 00:56:13.550686 ==
1470 00:56:13.554162 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 00:56:13.560552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 00:56:13.560628 ==
1473 00:56:13.563917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 00:56:13.570939 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 00:56:13.580096 [CA 0] Center 36 (6~66) winsize 61
1476 00:56:13.583542 [CA 1] Center 36 (6~66) winsize 61
1477 00:56:13.587011 [CA 2] Center 34 (4~64) winsize 61
1478 00:56:13.589933 [CA 3] Center 33 (3~64) winsize 62
1479 00:56:13.593357 [CA 4] Center 34 (4~65) winsize 62
1480 00:56:13.596778 [CA 5] Center 33 (3~64) winsize 62
1481 00:56:13.596853
1482 00:56:13.600022 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1483 00:56:13.600097
1484 00:56:13.603422 [CATrainingPosCal] consider 2 rank data
1485 00:56:13.606420 u2DelayCellTimex100 = 270/100 ps
1486 00:56:13.609737 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1487 00:56:13.613639 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1488 00:56:13.619953 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1489 00:56:13.623420 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1490 00:56:13.627095 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1491 00:56:13.630388 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1492 00:56:13.630464
1493 00:56:13.633580 CA PerBit enable=1, Macro0, CA PI delay=33
1494 00:56:13.633655
1495 00:56:13.636983 [CBTSetCACLKResult] CA Dly = 33
1496 00:56:13.637059 CS Dly: 4 (0~36)
1497 00:56:13.637118
1498 00:56:13.640243 ----->DramcWriteLeveling(PI) begin...
1499 00:56:13.640319 ==
1500 00:56:13.643657 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 00:56:13.650261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 00:56:13.650337 ==
1503 00:56:13.653529 Write leveling (Byte 0): 26 => 26
1504 00:56:13.656868 Write leveling (Byte 1): 29 => 29
1505 00:56:13.656943 DramcWriteLeveling(PI) end<-----
1506 00:56:13.660411
1507 00:56:13.660486 ==
1508 00:56:13.663730 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 00:56:13.667087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 00:56:13.667163 ==
1511 00:56:13.670273 [Gating] SW mode calibration
1512 00:56:13.677026 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 00:56:13.680355 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 00:56:13.686961 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 00:56:13.690051 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1516 00:56:13.693604 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 00:56:13.700312 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 00:56:13.703562 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 00:56:13.707077 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 00:56:13.713629 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 00:56:13.716516 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:56:13.719764 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:56:13.726846 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:56:13.730144 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:56:13.733534 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 00:56:13.740351 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:56:13.743266 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1528 00:56:13.746909 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 00:56:13.753139 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1530 00:56:13.756756 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:56:13.760180 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1532 00:56:13.763693 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1533 00:56:13.770166 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:56:13.773606 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:56:13.777002 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:56:13.783633 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 00:56:13.786628 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 00:56:13.790338 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 00:56:13.796955 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 00:56:13.800141 0 9 8 | B1->B0 | 2626 2424 | 0 1 | (1 1) (1 1)
1541 00:56:13.803233 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 00:56:13.809945 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 00:56:13.813642 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 00:56:13.816643 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 00:56:13.823439 0 9 28 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1546 00:56:13.826724 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 00:56:13.830194 0 10 4 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
1548 00:56:13.837002 0 10 8 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
1549 00:56:13.840066 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 00:56:13.843702 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 00:56:13.846647 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 00:56:13.853727 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 00:56:13.857182 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 00:56:13.860320 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 00:56:13.866732 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1556 00:56:13.870263 0 11 8 | B1->B0 | 3131 2f2f | 1 0 | (1 1) (1 1)
1557 00:56:13.873567 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 00:56:13.880300 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 00:56:13.883736 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 00:56:13.886992 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 00:56:13.893651 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 00:56:13.897552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 00:56:13.900513 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 00:56:13.906918 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1565 00:56:13.910279 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 00:56:13.913688 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 00:56:13.920451 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 00:56:13.923457 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 00:56:13.926789 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 00:56:13.930702 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 00:56:13.936993 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 00:56:13.940474 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 00:56:13.943876 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 00:56:13.950657 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 00:56:13.953555 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 00:56:13.957037 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 00:56:13.963496 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 00:56:13.966833 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 00:56:13.970607 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 00:56:13.977157 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1581 00:56:13.977233 Total UI for P1: 0, mck2ui 16
1582 00:56:13.983560 best dqsien dly found for B0: ( 0, 14, 6)
1583 00:56:13.987143 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 00:56:13.990321 Total UI for P1: 0, mck2ui 16
1585 00:56:13.993691 best dqsien dly found for B1: ( 0, 14, 8)
1586 00:56:13.996937 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1587 00:56:14.000586 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1588 00:56:14.000661
1589 00:56:14.003895 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1590 00:56:14.007211 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1591 00:56:14.010423 [Gating] SW calibration Done
1592 00:56:14.010507 ==
1593 00:56:14.013725 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 00:56:14.017215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 00:56:14.017306 ==
1596 00:56:14.020728 RX Vref Scan: 0
1597 00:56:14.020803
1598 00:56:14.020861 RX Vref 0 -> 0, step: 1
1599 00:56:14.024394
1600 00:56:14.024470 RX Delay -130 -> 252, step: 16
1601 00:56:14.030256 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1602 00:56:14.033858 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1603 00:56:14.037276 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1604 00:56:14.040895 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1605 00:56:14.044318 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1606 00:56:14.050585 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1607 00:56:14.053964 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1608 00:56:14.057499 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1609 00:56:14.060521 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1610 00:56:14.063912 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1611 00:56:14.067137 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1612 00:56:14.073724 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1613 00:56:14.077346 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1614 00:56:14.080389 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1615 00:56:14.083806 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1616 00:56:14.090882 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1617 00:56:14.090958 ==
1618 00:56:14.093894 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 00:56:14.097164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 00:56:14.097240 ==
1621 00:56:14.097299 DQS Delay:
1622 00:56:14.100465 DQS0 = 0, DQS1 = 0
1623 00:56:14.100540 DQM Delay:
1624 00:56:14.104083 DQM0 = 83, DQM1 = 76
1625 00:56:14.104158 DQ Delay:
1626 00:56:14.107513 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1627 00:56:14.111008 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =69
1628 00:56:14.113767 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1629 00:56:14.117310 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1630 00:56:14.117385
1631 00:56:14.117443
1632 00:56:14.117496 ==
1633 00:56:14.120522 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 00:56:14.123806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 00:56:14.123882 ==
1636 00:56:14.123941
1637 00:56:14.123995
1638 00:56:14.127235 TX Vref Scan disable
1639 00:56:14.130301 == TX Byte 0 ==
1640 00:56:14.133604 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1641 00:56:14.137673 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1642 00:56:14.140388 == TX Byte 1 ==
1643 00:56:14.143730 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1644 00:56:14.147065 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1645 00:56:14.147144 ==
1646 00:56:14.150555 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 00:56:14.156825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 00:56:14.156901 ==
1649 00:56:14.168934 TX Vref=22, minBit 0, minWin=27, winSum=441
1650 00:56:14.172288 TX Vref=24, minBit 0, minWin=27, winSum=444
1651 00:56:14.175691 TX Vref=26, minBit 0, minWin=27, winSum=448
1652 00:56:14.178926 TX Vref=28, minBit 11, minWin=27, winSum=451
1653 00:56:14.181883 TX Vref=30, minBit 11, minWin=27, winSum=452
1654 00:56:14.189086 TX Vref=32, minBit 1, minWin=28, winSum=454
1655 00:56:14.192007 [TxChooseVref] Worse bit 1, Min win 28, Win sum 454, Final Vref 32
1656 00:56:14.192082
1657 00:56:14.195535 Final TX Range 1 Vref 32
1658 00:56:14.195610
1659 00:56:14.195668 ==
1660 00:56:14.198964 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 00:56:14.201945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 00:56:14.202065 ==
1663 00:56:14.206069
1664 00:56:14.206144
1665 00:56:14.206202 TX Vref Scan disable
1666 00:56:14.208926 == TX Byte 0 ==
1667 00:56:14.212470 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1668 00:56:14.215291 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1669 00:56:14.218785 == TX Byte 1 ==
1670 00:56:14.222077 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1671 00:56:14.225403 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1672 00:56:14.228780
1673 00:56:14.228854 [DATLAT]
1674 00:56:14.228912 Freq=800, CH1 RK0
1675 00:56:14.228968
1676 00:56:14.232556 DATLAT Default: 0xa
1677 00:56:14.232631 0, 0xFFFF, sum = 0
1678 00:56:14.235300 1, 0xFFFF, sum = 0
1679 00:56:14.235377 2, 0xFFFF, sum = 0
1680 00:56:14.238840 3, 0xFFFF, sum = 0
1681 00:56:14.238916 4, 0xFFFF, sum = 0
1682 00:56:14.242421 5, 0xFFFF, sum = 0
1683 00:56:14.245782 6, 0xFFFF, sum = 0
1684 00:56:14.245858 7, 0xFFFF, sum = 0
1685 00:56:14.248950 8, 0xFFFF, sum = 0
1686 00:56:14.249056 9, 0x0, sum = 1
1687 00:56:14.249116 10, 0x0, sum = 2
1688 00:56:14.252235 11, 0x0, sum = 3
1689 00:56:14.252312 12, 0x0, sum = 4
1690 00:56:14.255571 best_step = 10
1691 00:56:14.255646
1692 00:56:14.255705 ==
1693 00:56:14.258620 Dram Type= 6, Freq= 0, CH_1, rank 0
1694 00:56:14.262119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1695 00:56:14.262194 ==
1696 00:56:14.265474 RX Vref Scan: 1
1697 00:56:14.265549
1698 00:56:14.265608 Set Vref Range= 32 -> 127
1699 00:56:14.265662
1700 00:56:14.269098 RX Vref 32 -> 127, step: 1
1701 00:56:14.269173
1702 00:56:14.272503 RX Delay -95 -> 252, step: 8
1703 00:56:14.272578
1704 00:56:14.275413 Set Vref, RX VrefLevel [Byte0]: 32
1705 00:56:14.278973 [Byte1]: 32
1706 00:56:14.279057
1707 00:56:14.282407 Set Vref, RX VrefLevel [Byte0]: 33
1708 00:56:14.285858 [Byte1]: 33
1709 00:56:14.289298
1710 00:56:14.289373 Set Vref, RX VrefLevel [Byte0]: 34
1711 00:56:14.292541 [Byte1]: 34
1712 00:56:14.296730
1713 00:56:14.296805 Set Vref, RX VrefLevel [Byte0]: 35
1714 00:56:14.300133 [Byte1]: 35
1715 00:56:14.304515
1716 00:56:14.304590 Set Vref, RX VrefLevel [Byte0]: 36
1717 00:56:14.307750 [Byte1]: 36
1718 00:56:14.312428
1719 00:56:14.315685 Set Vref, RX VrefLevel [Byte0]: 37
1720 00:56:14.315762 [Byte1]: 37
1721 00:56:14.319982
1722 00:56:14.320057 Set Vref, RX VrefLevel [Byte0]: 38
1723 00:56:14.322716 [Byte1]: 38
1724 00:56:14.327403
1725 00:56:14.327478 Set Vref, RX VrefLevel [Byte0]: 39
1726 00:56:14.330773 [Byte1]: 39
1727 00:56:14.334699
1728 00:56:14.334774 Set Vref, RX VrefLevel [Byte0]: 40
1729 00:56:14.337941 [Byte1]: 40
1730 00:56:14.342644
1731 00:56:14.342719 Set Vref, RX VrefLevel [Byte0]: 41
1732 00:56:14.345939 [Byte1]: 41
1733 00:56:14.349831
1734 00:56:14.349905 Set Vref, RX VrefLevel [Byte0]: 42
1735 00:56:14.353437 [Byte1]: 42
1736 00:56:14.357868
1737 00:56:14.357942 Set Vref, RX VrefLevel [Byte0]: 43
1738 00:56:14.360948 [Byte1]: 43
1739 00:56:14.365143
1740 00:56:14.365218 Set Vref, RX VrefLevel [Byte0]: 44
1741 00:56:14.368365 [Byte1]: 44
1742 00:56:14.372993
1743 00:56:14.373068 Set Vref, RX VrefLevel [Byte0]: 45
1744 00:56:14.376393 [Byte1]: 45
1745 00:56:14.380580
1746 00:56:14.380655 Set Vref, RX VrefLevel [Byte0]: 46
1747 00:56:14.383930 [Byte1]: 46
1748 00:56:14.387848
1749 00:56:14.387923 Set Vref, RX VrefLevel [Byte0]: 47
1750 00:56:14.391457 [Byte1]: 47
1751 00:56:14.395877
1752 00:56:14.395952 Set Vref, RX VrefLevel [Byte0]: 48
1753 00:56:14.398711 [Byte1]: 48
1754 00:56:14.403475
1755 00:56:14.403550 Set Vref, RX VrefLevel [Byte0]: 49
1756 00:56:14.406477 [Byte1]: 49
1757 00:56:14.410566
1758 00:56:14.410640 Set Vref, RX VrefLevel [Byte0]: 50
1759 00:56:14.413910 [Byte1]: 50
1760 00:56:14.418356
1761 00:56:14.418431 Set Vref, RX VrefLevel [Byte0]: 51
1762 00:56:14.421682 [Byte1]: 51
1763 00:56:14.425784
1764 00:56:14.425859 Set Vref, RX VrefLevel [Byte0]: 52
1765 00:56:14.429512 [Byte1]: 52
1766 00:56:14.433237
1767 00:56:14.433312 Set Vref, RX VrefLevel [Byte0]: 53
1768 00:56:14.436694 [Byte1]: 53
1769 00:56:14.441076
1770 00:56:14.441151 Set Vref, RX VrefLevel [Byte0]: 54
1771 00:56:14.444704 [Byte1]: 54
1772 00:56:14.448628
1773 00:56:14.448703 Set Vref, RX VrefLevel [Byte0]: 55
1774 00:56:14.452242 [Byte1]: 55
1775 00:56:14.456250
1776 00:56:14.456325 Set Vref, RX VrefLevel [Byte0]: 56
1777 00:56:14.459457 [Byte1]: 56
1778 00:56:14.464111
1779 00:56:14.464186 Set Vref, RX VrefLevel [Byte0]: 57
1780 00:56:14.467542 [Byte1]: 57
1781 00:56:14.471531
1782 00:56:14.471608 Set Vref, RX VrefLevel [Byte0]: 58
1783 00:56:14.474951 [Byte1]: 58
1784 00:56:14.479362
1785 00:56:14.479458 Set Vref, RX VrefLevel [Byte0]: 59
1786 00:56:14.482414 [Byte1]: 59
1787 00:56:14.486435
1788 00:56:14.486509 Set Vref, RX VrefLevel [Byte0]: 60
1789 00:56:14.490097 [Byte1]: 60
1790 00:56:14.494350
1791 00:56:14.494424 Set Vref, RX VrefLevel [Byte0]: 61
1792 00:56:14.497886 [Byte1]: 61
1793 00:56:14.501951
1794 00:56:14.502070 Set Vref, RX VrefLevel [Byte0]: 62
1795 00:56:14.505255 [Byte1]: 62
1796 00:56:14.509266
1797 00:56:14.509340 Set Vref, RX VrefLevel [Byte0]: 63
1798 00:56:14.512621 [Byte1]: 63
1799 00:56:14.516809
1800 00:56:14.516884 Set Vref, RX VrefLevel [Byte0]: 64
1801 00:56:14.520524 [Byte1]: 64
1802 00:56:14.524849
1803 00:56:14.524924 Set Vref, RX VrefLevel [Byte0]: 65
1804 00:56:14.527924 [Byte1]: 65
1805 00:56:14.532209
1806 00:56:14.532284 Set Vref, RX VrefLevel [Byte0]: 66
1807 00:56:14.535347 [Byte1]: 66
1808 00:56:14.540446
1809 00:56:14.540521 Set Vref, RX VrefLevel [Byte0]: 67
1810 00:56:14.543287 [Byte1]: 67
1811 00:56:14.547907
1812 00:56:14.547981 Set Vref, RX VrefLevel [Byte0]: 68
1813 00:56:14.550828 [Byte1]: 68
1814 00:56:14.555438
1815 00:56:14.555513 Set Vref, RX VrefLevel [Byte0]: 69
1816 00:56:14.558731 [Byte1]: 69
1817 00:56:14.562878
1818 00:56:14.562953 Set Vref, RX VrefLevel [Byte0]: 70
1819 00:56:14.566265 [Byte1]: 70
1820 00:56:14.570476
1821 00:56:14.570550 Set Vref, RX VrefLevel [Byte0]: 71
1822 00:56:14.573713 [Byte1]: 71
1823 00:56:14.577763
1824 00:56:14.577838 Set Vref, RX VrefLevel [Byte0]: 72
1825 00:56:14.581189 [Byte1]: 72
1826 00:56:14.585474
1827 00:56:14.585554 Set Vref, RX VrefLevel [Byte0]: 73
1828 00:56:14.589027 [Byte1]: 73
1829 00:56:14.593020
1830 00:56:14.593101 Set Vref, RX VrefLevel [Byte0]: 74
1831 00:56:14.596475 [Byte1]: 74
1832 00:56:14.600451
1833 00:56:14.600543 Set Vref, RX VrefLevel [Byte0]: 75
1834 00:56:14.603891 [Byte1]: 75
1835 00:56:14.608444
1836 00:56:14.608522 Set Vref, RX VrefLevel [Byte0]: 76
1837 00:56:14.611783 [Byte1]: 76
1838 00:56:14.615833
1839 00:56:14.615910 Set Vref, RX VrefLevel [Byte0]: 77
1840 00:56:14.619136 [Byte1]: 77
1841 00:56:14.623274
1842 00:56:14.623366 Set Vref, RX VrefLevel [Byte0]: 78
1843 00:56:14.626812 [Byte1]: 78
1844 00:56:14.631078
1845 00:56:14.631173 Final RX Vref Byte 0 = 65 to rank0
1846 00:56:14.634229 Final RX Vref Byte 1 = 57 to rank0
1847 00:56:14.637581 Final RX Vref Byte 0 = 65 to rank1
1848 00:56:14.641101 Final RX Vref Byte 1 = 57 to rank1==
1849 00:56:14.644330 Dram Type= 6, Freq= 0, CH_1, rank 0
1850 00:56:14.651190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 00:56:14.651267 ==
1852 00:56:14.651326 DQS Delay:
1853 00:56:14.651380 DQS0 = 0, DQS1 = 0
1854 00:56:14.654634 DQM Delay:
1855 00:56:14.654747 DQM0 = 82, DQM1 = 74
1856 00:56:14.658135 DQ Delay:
1857 00:56:14.661122 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1858 00:56:14.661198 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1859 00:56:14.664352 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1860 00:56:14.667761 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1861 00:56:14.667836
1862 00:56:14.671394
1863 00:56:14.677609 [DQSOSCAuto] RK0, (LSB)MR18= 0x2bff, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
1864 00:56:14.681221 CH1 RK0: MR19=605, MR18=2BFF
1865 00:56:14.687816 CH1_RK0: MR19=0x605, MR18=0x2BFF, DQSOSC=398, MR23=63, INC=93, DEC=62
1866 00:56:14.687892
1867 00:56:14.691232 ----->DramcWriteLeveling(PI) begin...
1868 00:56:14.691309 ==
1869 00:56:14.694569 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 00:56:14.698073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1871 00:56:14.698149 ==
1872 00:56:14.701175 Write leveling (Byte 0): 29 => 29
1873 00:56:14.704487 Write leveling (Byte 1): 31 => 31
1874 00:56:14.707679 DramcWriteLeveling(PI) end<-----
1875 00:56:14.707754
1876 00:56:14.707813 ==
1877 00:56:14.711298 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 00:56:14.714687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 00:56:14.714763 ==
1880 00:56:14.718246 [Gating] SW mode calibration
1881 00:56:14.724586 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1882 00:56:14.731418 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1883 00:56:14.734611 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1884 00:56:14.737746 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1885 00:56:14.744742 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:56:14.747542 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:56:14.750981 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:56:14.758119 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:56:14.761006 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:56:14.764498 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 00:56:14.768137 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 00:56:14.774635 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 00:56:14.777759 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 00:56:14.781368 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1895 00:56:14.788283 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1896 00:56:14.791121 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1897 00:56:14.794558 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1898 00:56:14.801167 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 00:56:14.804687 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:56:14.808364 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1901 00:56:14.814398 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:56:14.817940 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:56:14.821305 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:56:14.827758 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 00:56:14.831096 0 8 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1906 00:56:14.834310 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 00:56:14.841528 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 00:56:14.844786 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
1909 00:56:14.847946 0 9 8 | B1->B0 | 2928 3434 | 1 1 | (0 0) (1 1)
1910 00:56:14.854242 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 00:56:14.857749 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 00:56:14.861028 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 00:56:14.864511 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 00:56:14.871263 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 00:56:14.874236 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 00:56:14.877627 0 10 4 | B1->B0 | 3030 2f2f | 0 0 | (1 0) (1 0)
1917 00:56:14.884391 0 10 8 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
1918 00:56:14.887476 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 00:56:14.890935 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 00:56:14.897965 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 00:56:14.900846 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 00:56:14.904210 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 00:56:14.911158 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 00:56:14.914598 0 11 4 | B1->B0 | 2525 3939 | 0 0 | (0 0) (0 0)
1925 00:56:14.917642 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
1926 00:56:14.924049 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 00:56:14.927952 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 00:56:14.930777 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 00:56:14.937718 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 00:56:14.941166 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 00:56:14.944356 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1932 00:56:14.950972 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1933 00:56:14.954094 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1934 00:56:14.957504 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 00:56:14.964123 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 00:56:14.967588 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 00:56:14.970676 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 00:56:14.977555 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 00:56:14.980997 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 00:56:14.984280 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 00:56:14.990871 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 00:56:14.994216 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 00:56:14.997184 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 00:56:15.003820 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 00:56:15.007160 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 00:56:15.010569 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 00:56:15.017504 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 00:56:15.020948 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1949 00:56:15.024240 Total UI for P1: 0, mck2ui 16
1950 00:56:15.027406 best dqsien dly found for B0: ( 0, 14, 2)
1951 00:56:15.030826 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1952 00:56:15.033911 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1953 00:56:15.037306 Total UI for P1: 0, mck2ui 16
1954 00:56:15.040746 best dqsien dly found for B1: ( 0, 14, 6)
1955 00:56:15.044148 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1956 00:56:15.047559 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1957 00:56:15.047634
1958 00:56:15.053916 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1959 00:56:15.057609 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1960 00:56:15.057684 [Gating] SW calibration Done
1961 00:56:15.060613 ==
1962 00:56:15.060689 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 00:56:15.067577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 00:56:15.067654 ==
1965 00:56:15.067713 RX Vref Scan: 0
1966 00:56:15.067768
1967 00:56:15.070946 RX Vref 0 -> 0, step: 1
1968 00:56:15.071034
1969 00:56:15.073896 RX Delay -130 -> 252, step: 16
1970 00:56:15.077232 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1971 00:56:15.080589 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1972 00:56:15.084374 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1973 00:56:15.090715 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1974 00:56:15.094284 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1975 00:56:15.097971 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1976 00:56:15.100745 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1977 00:56:15.104196 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1978 00:56:15.111122 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1979 00:56:15.113963 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1980 00:56:15.117713 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1981 00:56:15.120624 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1982 00:56:15.124126 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1983 00:56:15.131145 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1984 00:56:15.134279 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1985 00:56:15.137850 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1986 00:56:15.137949 ==
1987 00:56:15.141301 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 00:56:15.144703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 00:56:15.144778 ==
1990 00:56:15.147527 DQS Delay:
1991 00:56:15.147632 DQS0 = 0, DQS1 = 0
1992 00:56:15.150898 DQM Delay:
1993 00:56:15.150989 DQM0 = 79, DQM1 = 78
1994 00:56:15.151071 DQ Delay:
1995 00:56:15.154109 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1996 00:56:15.157457 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =69
1997 00:56:15.161371 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1998 00:56:15.164552 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1999 00:56:15.164627
2000 00:56:15.164685
2001 00:56:15.164738 ==
2002 00:56:15.167801 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 00:56:15.174311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 00:56:15.174388 ==
2005 00:56:15.174447
2006 00:56:15.174501
2007 00:56:15.174552 TX Vref Scan disable
2008 00:56:15.178154 == TX Byte 0 ==
2009 00:56:15.181677 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2010 00:56:15.188167 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2011 00:56:15.188243 == TX Byte 1 ==
2012 00:56:15.191653 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2013 00:56:15.198237 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2014 00:56:15.198316 ==
2015 00:56:15.201451 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 00:56:15.204800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 00:56:15.204876 ==
2018 00:56:15.217262 TX Vref=22, minBit 1, minWin=27, winSum=445
2019 00:56:15.220546 TX Vref=24, minBit 1, minWin=27, winSum=445
2020 00:56:15.223835 TX Vref=26, minBit 1, minWin=27, winSum=448
2021 00:56:15.227486 TX Vref=28, minBit 1, minWin=27, winSum=450
2022 00:56:15.230850 TX Vref=30, minBit 0, minWin=28, winSum=451
2023 00:56:15.233766 TX Vref=32, minBit 0, minWin=28, winSum=452
2024 00:56:15.240710 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 32
2025 00:56:15.240786
2026 00:56:15.243571 Final TX Range 1 Vref 32
2027 00:56:15.243647
2028 00:56:15.243705 ==
2029 00:56:15.247586 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 00:56:15.250702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 00:56:15.250778 ==
2032 00:56:15.250837
2033 00:56:15.253635
2034 00:56:15.253710 TX Vref Scan disable
2035 00:56:15.257175 == TX Byte 0 ==
2036 00:56:15.260592 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2037 00:56:15.263690 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2038 00:56:15.267448 == TX Byte 1 ==
2039 00:56:15.270865 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2040 00:56:15.273689 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2041 00:56:15.273781
2042 00:56:15.277080 [DATLAT]
2043 00:56:15.277155 Freq=800, CH1 RK1
2044 00:56:15.277215
2045 00:56:15.280595 DATLAT Default: 0xa
2046 00:56:15.280674 0, 0xFFFF, sum = 0
2047 00:56:15.283649 1, 0xFFFF, sum = 0
2048 00:56:15.283726 2, 0xFFFF, sum = 0
2049 00:56:15.287845 3, 0xFFFF, sum = 0
2050 00:56:15.287921 4, 0xFFFF, sum = 0
2051 00:56:15.290541 5, 0xFFFF, sum = 0
2052 00:56:15.290617 6, 0xFFFF, sum = 0
2053 00:56:15.293820 7, 0xFFFF, sum = 0
2054 00:56:15.293924 8, 0xFFFF, sum = 0
2055 00:56:15.297276 9, 0x0, sum = 1
2056 00:56:15.297353 10, 0x0, sum = 2
2057 00:56:15.300793 11, 0x0, sum = 3
2058 00:56:15.300869 12, 0x0, sum = 4
2059 00:56:15.304267 best_step = 10
2060 00:56:15.304342
2061 00:56:15.304401 ==
2062 00:56:15.307343 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 00:56:15.310762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 00:56:15.310838 ==
2065 00:56:15.314065 RX Vref Scan: 0
2066 00:56:15.314140
2067 00:56:15.314199 RX Vref 0 -> 0, step: 1
2068 00:56:15.314254
2069 00:56:15.317661 RX Delay -95 -> 252, step: 8
2070 00:56:15.324124 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2071 00:56:15.327323 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2072 00:56:15.331230 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2073 00:56:15.334181 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2074 00:56:15.337642 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2075 00:56:15.341098 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2076 00:56:15.347346 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2077 00:56:15.350765 iDelay=201, Bit 7, Center 72 (-39 ~ 184) 224
2078 00:56:15.353951 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2079 00:56:15.357752 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2080 00:56:15.360791 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2081 00:56:15.367394 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2082 00:56:15.370707 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2083 00:56:15.373966 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2084 00:56:15.377415 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2085 00:56:15.384258 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2086 00:56:15.384334 ==
2087 00:56:15.387653 Dram Type= 6, Freq= 0, CH_1, rank 1
2088 00:56:15.390907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2089 00:56:15.390984 ==
2090 00:56:15.391043 DQS Delay:
2091 00:56:15.394310 DQS0 = 0, DQS1 = 0
2092 00:56:15.394385 DQM Delay:
2093 00:56:15.397620 DQM0 = 79, DQM1 = 75
2094 00:56:15.397695 DQ Delay:
2095 00:56:15.400979 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =76
2096 00:56:15.404072 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =72
2097 00:56:15.407580 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2098 00:56:15.410822 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2099 00:56:15.410897
2100 00:56:15.410955
2101 00:56:15.418425 [DQSOSCAuto] RK1, (LSB)MR18= 0x212c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2102 00:56:15.421089 CH1 RK1: MR19=606, MR18=212C
2103 00:56:15.427386 CH1_RK1: MR19=0x606, MR18=0x212C, DQSOSC=398, MR23=63, INC=93, DEC=62
2104 00:56:15.430979 [RxdqsGatingPostProcess] freq 800
2105 00:56:15.437674 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2106 00:56:15.437749 Pre-setting of DQS Precalculation
2107 00:56:15.444052 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2108 00:56:15.450746 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2109 00:56:15.457532 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2110 00:56:15.457608
2111 00:56:15.457667
2112 00:56:15.460687 [Calibration Summary] 1600 Mbps
2113 00:56:15.463968 CH 0, Rank 0
2114 00:56:15.464043 SW Impedance : PASS
2115 00:56:15.467424 DUTY Scan : NO K
2116 00:56:15.470508 ZQ Calibration : PASS
2117 00:56:15.470584 Jitter Meter : NO K
2118 00:56:15.474095 CBT Training : PASS
2119 00:56:15.474170 Write leveling : PASS
2120 00:56:15.477275 RX DQS gating : PASS
2121 00:56:15.480688 RX DQ/DQS(RDDQC) : PASS
2122 00:56:15.480763 TX DQ/DQS : PASS
2123 00:56:15.484168 RX DATLAT : PASS
2124 00:56:15.487654 RX DQ/DQS(Engine): PASS
2125 00:56:15.487736 TX OE : NO K
2126 00:56:15.490556 All Pass.
2127 00:56:15.490631
2128 00:56:15.490689 CH 0, Rank 1
2129 00:56:15.493846 SW Impedance : PASS
2130 00:56:15.493922 DUTY Scan : NO K
2131 00:56:15.497393 ZQ Calibration : PASS
2132 00:56:15.500912 Jitter Meter : NO K
2133 00:56:15.500987 CBT Training : PASS
2134 00:56:15.503881 Write leveling : PASS
2135 00:56:15.507118 RX DQS gating : PASS
2136 00:56:15.507193 RX DQ/DQS(RDDQC) : PASS
2137 00:56:15.510481 TX DQ/DQS : PASS
2138 00:56:15.514025 RX DATLAT : PASS
2139 00:56:15.514113 RX DQ/DQS(Engine): PASS
2140 00:56:15.517134 TX OE : NO K
2141 00:56:15.517245 All Pass.
2142 00:56:15.517304
2143 00:56:15.520384 CH 1, Rank 0
2144 00:56:15.520459 SW Impedance : PASS
2145 00:56:15.523993 DUTY Scan : NO K
2146 00:56:15.524068 ZQ Calibration : PASS
2147 00:56:15.527134 Jitter Meter : NO K
2148 00:56:15.530436 CBT Training : PASS
2149 00:56:15.530511 Write leveling : PASS
2150 00:56:15.533863 RX DQS gating : PASS
2151 00:56:15.536732 RX DQ/DQS(RDDQC) : PASS
2152 00:56:15.536807 TX DQ/DQS : PASS
2153 00:56:15.540205 RX DATLAT : PASS
2154 00:56:15.543639 RX DQ/DQS(Engine): PASS
2155 00:56:15.543714 TX OE : NO K
2156 00:56:15.546934 All Pass.
2157 00:56:15.547009
2158 00:56:15.547068 CH 1, Rank 1
2159 00:56:15.550685 SW Impedance : PASS
2160 00:56:15.550760 DUTY Scan : NO K
2161 00:56:15.553463 ZQ Calibration : PASS
2162 00:56:15.556972 Jitter Meter : NO K
2163 00:56:15.557046 CBT Training : PASS
2164 00:56:15.560227 Write leveling : PASS
2165 00:56:15.563530 RX DQS gating : PASS
2166 00:56:15.563605 RX DQ/DQS(RDDQC) : PASS
2167 00:56:15.566943 TX DQ/DQS : PASS
2168 00:56:15.570365 RX DATLAT : PASS
2169 00:56:15.570440 RX DQ/DQS(Engine): PASS
2170 00:56:15.573852 TX OE : NO K
2171 00:56:15.573927 All Pass.
2172 00:56:15.573992
2173 00:56:15.576988 DramC Write-DBI off
2174 00:56:15.580694 PER_BANK_REFRESH: Hybrid Mode
2175 00:56:15.580800 TX_TRACKING: ON
2176 00:56:15.583871 [GetDramInforAfterCalByMRR] Vendor 6.
2177 00:56:15.587149 [GetDramInforAfterCalByMRR] Revision 606.
2178 00:56:15.590565 [GetDramInforAfterCalByMRR] Revision 2 0.
2179 00:56:15.590657 MR0 0x3b3b
2180 00:56:15.593589 MR8 0x5151
2181 00:56:15.596841 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 00:56:15.596906
2183 00:56:15.596961 MR0 0x3b3b
2184 00:56:15.600238 MR8 0x5151
2185 00:56:15.603715 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 00:56:15.603808
2187 00:56:15.610089 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2188 00:56:15.613509 [FAST_K] Save calibration result to emmc
2189 00:56:15.620408 [FAST_K] Save calibration result to emmc
2190 00:56:15.620503 dram_init: config_dvfs: 1
2191 00:56:15.623403 dramc_set_vcore_voltage set vcore to 662500
2192 00:56:15.627092 Read voltage for 1200, 2
2193 00:56:15.627170 Vio18 = 0
2194 00:56:15.630367 Vcore = 662500
2195 00:56:15.630441 Vdram = 0
2196 00:56:15.630499 Vddq = 0
2197 00:56:15.633471 Vmddr = 0
2198 00:56:15.636962 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2199 00:56:15.643518 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2200 00:56:15.643595 MEM_TYPE=3, freq_sel=15
2201 00:56:15.646787 sv_algorithm_assistance_LP4_1600
2202 00:56:15.653679 ============ PULL DRAM RESETB DOWN ============
2203 00:56:15.656982 ========== PULL DRAM RESETB DOWN end =========
2204 00:56:15.660073 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2205 00:56:15.663657 ===================================
2206 00:56:15.666877 LPDDR4 DRAM CONFIGURATION
2207 00:56:15.670414 ===================================
2208 00:56:15.670482 EX_ROW_EN[0] = 0x0
2209 00:56:15.673788 EX_ROW_EN[1] = 0x0
2210 00:56:15.677061 LP4Y_EN = 0x0
2211 00:56:15.677127 WORK_FSP = 0x0
2212 00:56:15.680596 WL = 0x4
2213 00:56:15.680659 RL = 0x4
2214 00:56:15.683406 BL = 0x2
2215 00:56:15.683470 RPST = 0x0
2216 00:56:15.687205 RD_PRE = 0x0
2217 00:56:15.687269 WR_PRE = 0x1
2218 00:56:15.690539 WR_PST = 0x0
2219 00:56:15.690627 DBI_WR = 0x0
2220 00:56:15.693633 DBI_RD = 0x0
2221 00:56:15.693719 OTF = 0x1
2222 00:56:15.697057 ===================================
2223 00:56:15.700048 ===================================
2224 00:56:15.703449 ANA top config
2225 00:56:15.707011 ===================================
2226 00:56:15.707108 DLL_ASYNC_EN = 0
2227 00:56:15.710423 ALL_SLAVE_EN = 0
2228 00:56:15.713395 NEW_RANK_MODE = 1
2229 00:56:15.716735 DLL_IDLE_MODE = 1
2230 00:56:15.720608 LP45_APHY_COMB_EN = 1
2231 00:56:15.720697 TX_ODT_DIS = 1
2232 00:56:15.723682 NEW_8X_MODE = 1
2233 00:56:15.727127 ===================================
2234 00:56:15.730517 ===================================
2235 00:56:15.733593 data_rate = 2400
2236 00:56:15.737051 CKR = 1
2237 00:56:15.740090 DQ_P2S_RATIO = 8
2238 00:56:15.743684 ===================================
2239 00:56:15.743776 CA_P2S_RATIO = 8
2240 00:56:15.746924 DQ_CA_OPEN = 0
2241 00:56:15.750054 DQ_SEMI_OPEN = 0
2242 00:56:15.753481 CA_SEMI_OPEN = 0
2243 00:56:15.756606 CA_FULL_RATE = 0
2244 00:56:15.760071 DQ_CKDIV4_EN = 0
2245 00:56:15.760158 CA_CKDIV4_EN = 0
2246 00:56:15.763588 CA_PREDIV_EN = 0
2247 00:56:15.766881 PH8_DLY = 17
2248 00:56:15.770151 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2249 00:56:15.773577 DQ_AAMCK_DIV = 4
2250 00:56:15.776822 CA_AAMCK_DIV = 4
2251 00:56:15.776912 CA_ADMCK_DIV = 4
2252 00:56:15.780273 DQ_TRACK_CA_EN = 0
2253 00:56:15.783556 CA_PICK = 1200
2254 00:56:15.787119 CA_MCKIO = 1200
2255 00:56:15.790386 MCKIO_SEMI = 0
2256 00:56:15.793664 PLL_FREQ = 2366
2257 00:56:15.796796 DQ_UI_PI_RATIO = 32
2258 00:56:15.796885 CA_UI_PI_RATIO = 0
2259 00:56:15.800488 ===================================
2260 00:56:15.803365 ===================================
2261 00:56:15.806772 memory_type:LPDDR4
2262 00:56:15.810199 GP_NUM : 10
2263 00:56:15.810275 SRAM_EN : 1
2264 00:56:15.813784 MD32_EN : 0
2265 00:56:15.817113 ===================================
2266 00:56:15.820219 [ANA_INIT] >>>>>>>>>>>>>>
2267 00:56:15.820294 <<<<<< [CONFIGURE PHASE]: ANA_TX
2268 00:56:15.826998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2269 00:56:15.827073 ===================================
2270 00:56:15.830425 data_rate = 2400,PCW = 0X5b00
2271 00:56:15.833629 ===================================
2272 00:56:15.837099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2273 00:56:15.843843 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2274 00:56:15.850589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2275 00:56:15.853643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2276 00:56:15.857046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2277 00:56:15.860626 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2278 00:56:15.863537 [ANA_INIT] flow start
2279 00:56:15.863612 [ANA_INIT] PLL >>>>>>>>
2280 00:56:15.867406 [ANA_INIT] PLL <<<<<<<<
2281 00:56:15.870806 [ANA_INIT] MIDPI >>>>>>>>
2282 00:56:15.870881 [ANA_INIT] MIDPI <<<<<<<<
2283 00:56:15.874105 [ANA_INIT] DLL >>>>>>>>
2284 00:56:15.877407 [ANA_INIT] DLL <<<<<<<<
2285 00:56:15.877483 [ANA_INIT] flow end
2286 00:56:15.883733 ============ LP4 DIFF to SE enter ============
2287 00:56:15.887090 ============ LP4 DIFF to SE exit ============
2288 00:56:15.887166 [ANA_INIT] <<<<<<<<<<<<<
2289 00:56:15.890541 [Flow] Enable top DCM control >>>>>
2290 00:56:15.893804 [Flow] Enable top DCM control <<<<<
2291 00:56:15.897128 Enable DLL master slave shuffle
2292 00:56:15.904474 ==============================================================
2293 00:56:15.904550 Gating Mode config
2294 00:56:15.910387 ==============================================================
2295 00:56:15.913899 Config description:
2296 00:56:15.923771 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2297 00:56:15.930632 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2298 00:56:15.933791 SELPH_MODE 0: By rank 1: By Phase
2299 00:56:15.940524 ==============================================================
2300 00:56:15.944179 GAT_TRACK_EN = 1
2301 00:56:15.944255 RX_GATING_MODE = 2
2302 00:56:15.947454 RX_GATING_TRACK_MODE = 2
2303 00:56:15.950679 SELPH_MODE = 1
2304 00:56:15.954188 PICG_EARLY_EN = 1
2305 00:56:15.957603 VALID_LAT_VALUE = 1
2306 00:56:15.963998 ==============================================================
2307 00:56:15.967463 Enter into Gating configuration >>>>
2308 00:56:15.970692 Exit from Gating configuration <<<<
2309 00:56:15.974179 Enter into DVFS_PRE_config >>>>>
2310 00:56:15.984099 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2311 00:56:15.987650 Exit from DVFS_PRE_config <<<<<
2312 00:56:15.990773 Enter into PICG configuration >>>>
2313 00:56:15.994105 Exit from PICG configuration <<<<
2314 00:56:15.997603 [RX_INPUT] configuration >>>>>
2315 00:56:15.997678 [RX_INPUT] configuration <<<<<
2316 00:56:16.003941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2317 00:56:16.010994 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2318 00:56:16.014115 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 00:56:16.020801 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 00:56:16.027707 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 00:56:16.034215 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 00:56:16.037447 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2323 00:56:16.040985 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2324 00:56:16.047528 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2325 00:56:16.050981 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2326 00:56:16.054622 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2327 00:56:16.057992 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 00:56:16.061614 ===================================
2329 00:56:16.064344 LPDDR4 DRAM CONFIGURATION
2330 00:56:16.067854 ===================================
2331 00:56:16.071224 EX_ROW_EN[0] = 0x0
2332 00:56:16.071298 EX_ROW_EN[1] = 0x0
2333 00:56:16.074645 LP4Y_EN = 0x0
2334 00:56:16.074720 WORK_FSP = 0x0
2335 00:56:16.077508 WL = 0x4
2336 00:56:16.077582 RL = 0x4
2337 00:56:16.080958 BL = 0x2
2338 00:56:16.081033 RPST = 0x0
2339 00:56:16.084151 RD_PRE = 0x0
2340 00:56:16.084225 WR_PRE = 0x1
2341 00:56:16.087837 WR_PST = 0x0
2342 00:56:16.087912 DBI_WR = 0x0
2343 00:56:16.091003 DBI_RD = 0x0
2344 00:56:16.091077 OTF = 0x1
2345 00:56:16.094491 ===================================
2346 00:56:16.101422 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2347 00:56:16.104414 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2348 00:56:16.108134 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2349 00:56:16.110875 ===================================
2350 00:56:16.114381 LPDDR4 DRAM CONFIGURATION
2351 00:56:16.118150 ===================================
2352 00:56:16.121379 EX_ROW_EN[0] = 0x10
2353 00:56:16.121468 EX_ROW_EN[1] = 0x0
2354 00:56:16.124706 LP4Y_EN = 0x0
2355 00:56:16.124800 WORK_FSP = 0x0
2356 00:56:16.127705 WL = 0x4
2357 00:56:16.127779 RL = 0x4
2358 00:56:16.131115 BL = 0x2
2359 00:56:16.131190 RPST = 0x0
2360 00:56:16.134600 RD_PRE = 0x0
2361 00:56:16.134675 WR_PRE = 0x1
2362 00:56:16.137996 WR_PST = 0x0
2363 00:56:16.138133 DBI_WR = 0x0
2364 00:56:16.140951 DBI_RD = 0x0
2365 00:56:16.141025 OTF = 0x1
2366 00:56:16.144392 ===================================
2367 00:56:16.150842 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2368 00:56:16.150918 ==
2369 00:56:16.154239 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 00:56:16.160838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 00:56:16.160913 ==
2372 00:56:16.160970 [Duty_Offset_Calibration]
2373 00:56:16.164296 B0:2 B1:-1 CA:1
2374 00:56:16.164370
2375 00:56:16.167800 [DutyScan_Calibration_Flow] k_type=0
2376 00:56:16.175698
2377 00:56:16.175774 ==CLK 0==
2378 00:56:16.179472 Final CLK duty delay cell = -4
2379 00:56:16.182597 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2380 00:56:16.185478 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2381 00:56:16.188845 [-4] AVG Duty = 4953%(X100)
2382 00:56:16.188936
2383 00:56:16.192242 CH0 CLK Duty spec in!! Max-Min= 156%
2384 00:56:16.195774 [DutyScan_Calibration_Flow] ====Done====
2385 00:56:16.195849
2386 00:56:16.199190 [DutyScan_Calibration_Flow] k_type=1
2387 00:56:16.213529
2388 00:56:16.213609 ==DQS 0 ==
2389 00:56:16.217188 Final DQS duty delay cell = -4
2390 00:56:16.220474 [-4] MAX Duty = 5000%(X100), DQS PI = 42
2391 00:56:16.224023 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2392 00:56:16.227217 [-4] AVG Duty = 4938%(X100)
2393 00:56:16.227295
2394 00:56:16.227354 ==DQS 1 ==
2395 00:56:16.230324 Final DQS duty delay cell = -4
2396 00:56:16.233895 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2397 00:56:16.237041 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2398 00:56:16.240458 [-4] AVG Duty = 5062%(X100)
2399 00:56:16.240533
2400 00:56:16.243886 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2401 00:56:16.243961
2402 00:56:16.247382 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2403 00:56:16.250342 [DutyScan_Calibration_Flow] ====Done====
2404 00:56:16.250417
2405 00:56:16.253687 [DutyScan_Calibration_Flow] k_type=3
2406 00:56:16.270900
2407 00:56:16.270978 ==DQM 0 ==
2408 00:56:16.274028 Final DQM duty delay cell = 0
2409 00:56:16.277217 [0] MAX Duty = 5000%(X100), DQS PI = 54
2410 00:56:16.281172 [0] MIN Duty = 4907%(X100), DQS PI = 0
2411 00:56:16.281248 [0] AVG Duty = 4953%(X100)
2412 00:56:16.283993
2413 00:56:16.284067 ==DQM 1 ==
2414 00:56:16.287353 Final DQM duty delay cell = 0
2415 00:56:16.290962 [0] MAX Duty = 5124%(X100), DQS PI = 32
2416 00:56:16.294396 [0] MIN Duty = 4969%(X100), DQS PI = 8
2417 00:56:16.294471 [0] AVG Duty = 5046%(X100)
2418 00:56:16.294529
2419 00:56:16.300864 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2420 00:56:16.300940
2421 00:56:16.304249 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2422 00:56:16.307675 [DutyScan_Calibration_Flow] ====Done====
2423 00:56:16.307750
2424 00:56:16.310759 [DutyScan_Calibration_Flow] k_type=2
2425 00:56:16.326211
2426 00:56:16.326293 ==DQ 0 ==
2427 00:56:16.330115 Final DQ duty delay cell = -4
2428 00:56:16.333200 [-4] MAX Duty = 5031%(X100), DQS PI = 44
2429 00:56:16.336442 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2430 00:56:16.339473 [-4] AVG Duty = 4953%(X100)
2431 00:56:16.339557
2432 00:56:16.339621 ==DQ 1 ==
2433 00:56:16.343214 Final DQ duty delay cell = 0
2434 00:56:16.346603 [0] MAX Duty = 5031%(X100), DQS PI = 18
2435 00:56:16.349995 [0] MIN Duty = 4907%(X100), DQS PI = 46
2436 00:56:16.352953 [0] AVG Duty = 4969%(X100)
2437 00:56:16.353029
2438 00:56:16.356427 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2439 00:56:16.356503
2440 00:56:16.359715 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2441 00:56:16.363289 [DutyScan_Calibration_Flow] ====Done====
2442 00:56:16.363364 ==
2443 00:56:16.366437 Dram Type= 6, Freq= 0, CH_1, rank 0
2444 00:56:16.369810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 00:56:16.369887 ==
2446 00:56:16.373372 [Duty_Offset_Calibration]
2447 00:56:16.373447 B0:1 B1:1 CA:2
2448 00:56:16.373507
2449 00:56:16.376106 [DutyScan_Calibration_Flow] k_type=0
2450 00:56:16.386708
2451 00:56:16.386784 ==CLK 0==
2452 00:56:16.390309 Final CLK duty delay cell = 0
2453 00:56:16.393657 [0] MAX Duty = 5125%(X100), DQS PI = 24
2454 00:56:16.396561 [0] MIN Duty = 4938%(X100), DQS PI = 42
2455 00:56:16.396637 [0] AVG Duty = 5031%(X100)
2456 00:56:16.399943
2457 00:56:16.403283 CH1 CLK Duty spec in!! Max-Min= 187%
2458 00:56:16.406631 [DutyScan_Calibration_Flow] ====Done====
2459 00:56:16.406707
2460 00:56:16.410167 [DutyScan_Calibration_Flow] k_type=1
2461 00:56:16.426169
2462 00:56:16.426247 ==DQS 0 ==
2463 00:56:16.429336 Final DQS duty delay cell = 0
2464 00:56:16.432795 [0] MAX Duty = 5031%(X100), DQS PI = 18
2465 00:56:16.436152 [0] MIN Duty = 4813%(X100), DQS PI = 50
2466 00:56:16.436230 [0] AVG Duty = 4922%(X100)
2467 00:56:16.439236
2468 00:56:16.439317 ==DQS 1 ==
2469 00:56:16.442828 Final DQS duty delay cell = 0
2470 00:56:16.446399 [0] MAX Duty = 5031%(X100), DQS PI = 20
2471 00:56:16.449369 [0] MIN Duty = 4875%(X100), DQS PI = 16
2472 00:56:16.452714 [0] AVG Duty = 4953%(X100)
2473 00:56:16.452791
2474 00:56:16.456262 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2475 00:56:16.456340
2476 00:56:16.459435 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2477 00:56:16.463077 [DutyScan_Calibration_Flow] ====Done====
2478 00:56:16.463154
2479 00:56:16.466289 [DutyScan_Calibration_Flow] k_type=3
2480 00:56:16.482663
2481 00:56:16.482739 ==DQM 0 ==
2482 00:56:16.485999 Final DQM duty delay cell = 0
2483 00:56:16.489381 [0] MAX Duty = 5093%(X100), DQS PI = 16
2484 00:56:16.492675 [0] MIN Duty = 4875%(X100), DQS PI = 50
2485 00:56:16.492751 [0] AVG Duty = 4984%(X100)
2486 00:56:16.496290
2487 00:56:16.496366 ==DQM 1 ==
2488 00:56:16.499287 Final DQM duty delay cell = 0
2489 00:56:16.502939 [0] MAX Duty = 5156%(X100), DQS PI = 62
2490 00:56:16.505753 [0] MIN Duty = 4938%(X100), DQS PI = 22
2491 00:56:16.509649 [0] AVG Duty = 5047%(X100)
2492 00:56:16.509726
2493 00:56:16.512396 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2494 00:56:16.512472
2495 00:56:16.516013 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2496 00:56:16.519583 [DutyScan_Calibration_Flow] ====Done====
2497 00:56:16.519659
2498 00:56:16.522881 [DutyScan_Calibration_Flow] k_type=2
2499 00:56:16.539206
2500 00:56:16.539282 ==DQ 0 ==
2501 00:56:16.542599 Final DQ duty delay cell = 0
2502 00:56:16.546262 [0] MAX Duty = 5124%(X100), DQS PI = 18
2503 00:56:16.549432 [0] MIN Duty = 4938%(X100), DQS PI = 50
2504 00:56:16.549528 [0] AVG Duty = 5031%(X100)
2505 00:56:16.552724
2506 00:56:16.552825 ==DQ 1 ==
2507 00:56:16.555984 Final DQ duty delay cell = 0
2508 00:56:16.559221 [0] MAX Duty = 5093%(X100), DQS PI = 10
2509 00:56:16.562735 [0] MIN Duty = 5031%(X100), DQS PI = 2
2510 00:56:16.562809 [0] AVG Duty = 5062%(X100)
2511 00:56:16.562867
2512 00:56:16.565815 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2513 00:56:16.565890
2514 00:56:16.569454 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2515 00:56:16.575893 [DutyScan_Calibration_Flow] ====Done====
2516 00:56:16.579369 nWR fixed to 30
2517 00:56:16.579455 [ModeRegInit_LP4] CH0 RK0
2518 00:56:16.582632 [ModeRegInit_LP4] CH0 RK1
2519 00:56:16.586084 [ModeRegInit_LP4] CH1 RK0
2520 00:56:16.586161 [ModeRegInit_LP4] CH1 RK1
2521 00:56:16.589526 match AC timing 7
2522 00:56:16.592733 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2523 00:56:16.595692 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2524 00:56:16.602564 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2525 00:56:16.606191 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2526 00:56:16.612531 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2527 00:56:16.612607 ==
2528 00:56:16.615827 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 00:56:16.619511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 00:56:16.619588 ==
2531 00:56:16.625919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2532 00:56:16.629513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2533 00:56:16.639287 [CA 0] Center 40 (10~71) winsize 62
2534 00:56:16.642694 [CA 1] Center 39 (9~70) winsize 62
2535 00:56:16.645943 [CA 2] Center 36 (6~67) winsize 62
2536 00:56:16.649252 [CA 3] Center 36 (5~67) winsize 63
2537 00:56:16.652605 [CA 4] Center 35 (5~65) winsize 61
2538 00:56:16.656025 [CA 5] Center 35 (5~65) winsize 61
2539 00:56:16.656113
2540 00:56:16.659082 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2541 00:56:16.659149
2542 00:56:16.662682 [CATrainingPosCal] consider 1 rank data
2543 00:56:16.666001 u2DelayCellTimex100 = 270/100 ps
2544 00:56:16.669759 CA0 delay=40 (10~71),Diff = 5 PI (24 cell)
2545 00:56:16.672675 CA1 delay=39 (9~70),Diff = 4 PI (19 cell)
2546 00:56:16.679470 CA2 delay=36 (6~67),Diff = 1 PI (4 cell)
2547 00:56:16.682734 CA3 delay=36 (5~67),Diff = 1 PI (4 cell)
2548 00:56:16.685845 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
2549 00:56:16.689357 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
2550 00:56:16.689432
2551 00:56:16.692443 CA PerBit enable=1, Macro0, CA PI delay=35
2552 00:56:16.692519
2553 00:56:16.695969 [CBTSetCACLKResult] CA Dly = 35
2554 00:56:16.696044 CS Dly: 7 (0~38)
2555 00:56:16.696123 ==
2556 00:56:16.699460 Dram Type= 6, Freq= 0, CH_0, rank 1
2557 00:56:16.705831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 00:56:16.705908 ==
2559 00:56:16.709206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2560 00:56:16.716194 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2561 00:56:16.725090 [CA 0] Center 39 (9~70) winsize 62
2562 00:56:16.728471 [CA 1] Center 39 (9~70) winsize 62
2563 00:56:16.731895 [CA 2] Center 36 (6~67) winsize 62
2564 00:56:16.734744 [CA 3] Center 36 (5~67) winsize 63
2565 00:56:16.738238 [CA 4] Center 34 (4~65) winsize 62
2566 00:56:16.741465 [CA 5] Center 34 (4~64) winsize 61
2567 00:56:16.741540
2568 00:56:16.745112 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2569 00:56:16.745187
2570 00:56:16.748279 [CATrainingPosCal] consider 2 rank data
2571 00:56:16.751350 u2DelayCellTimex100 = 270/100 ps
2572 00:56:16.755227 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2573 00:56:16.761556 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2574 00:56:16.765165 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2575 00:56:16.767951 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2576 00:56:16.771627 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2577 00:56:16.775008 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
2578 00:56:16.775105
2579 00:56:16.778415 CA PerBit enable=1, Macro0, CA PI delay=34
2580 00:56:16.778482
2581 00:56:16.781892 [CBTSetCACLKResult] CA Dly = 34
2582 00:56:16.781985 CS Dly: 8 (0~41)
2583 00:56:16.782080
2584 00:56:16.784675 ----->DramcWriteLeveling(PI) begin...
2585 00:56:16.788385 ==
2586 00:56:16.791802 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 00:56:16.795029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 00:56:16.795107 ==
2589 00:56:16.798388 Write leveling (Byte 0): 32 => 32
2590 00:56:16.801704 Write leveling (Byte 1): 30 => 30
2591 00:56:16.804830 DramcWriteLeveling(PI) end<-----
2592 00:56:16.804898
2593 00:56:16.804954 ==
2594 00:56:16.808175 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 00:56:16.811459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 00:56:16.811525 ==
2597 00:56:16.814772 [Gating] SW mode calibration
2598 00:56:16.821697 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2599 00:56:16.824960 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2600 00:56:16.831951 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 00:56:16.834838 0 15 4 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
2602 00:56:16.838319 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
2603 00:56:16.845001 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 00:56:16.848512 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 00:56:16.851359 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 00:56:16.858346 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 00:56:16.861688 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 00:56:16.865010 1 0 0 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 0)
2609 00:56:16.871752 1 0 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
2610 00:56:16.875169 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 00:56:16.878315 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 00:56:16.884841 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 00:56:16.888309 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 00:56:16.891654 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 00:56:16.898157 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 00:56:16.901453 1 1 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2617 00:56:16.905275 1 1 4 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2618 00:56:16.911689 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 00:56:16.914876 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 00:56:16.918530 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 00:56:16.921949 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 00:56:16.928697 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 00:56:16.931580 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 00:56:16.935134 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2625 00:56:16.941791 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 00:56:16.945358 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 00:56:16.948664 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 00:56:16.955006 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 00:56:16.958458 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 00:56:16.961979 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 00:56:16.968355 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 00:56:16.972053 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 00:56:16.975355 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 00:56:16.981848 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 00:56:16.985308 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 00:56:16.988501 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 00:56:16.995431 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 00:56:16.998311 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 00:56:17.001922 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 00:56:17.005366 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2641 00:56:17.011971 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2642 00:56:17.015321 Total UI for P1: 0, mck2ui 16
2643 00:56:17.018476 best dqsien dly found for B0: ( 1, 4, 0)
2644 00:56:17.022112 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2645 00:56:17.025149 Total UI for P1: 0, mck2ui 16
2646 00:56:17.028546 best dqsien dly found for B1: ( 1, 4, 4)
2647 00:56:17.031880 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2648 00:56:17.035174 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2649 00:56:17.035249
2650 00:56:17.038627 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2651 00:56:17.041976 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2652 00:56:17.045471 [Gating] SW calibration Done
2653 00:56:17.045546 ==
2654 00:56:17.048952 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 00:56:17.051750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 00:56:17.055320 ==
2657 00:56:17.055420 RX Vref Scan: 0
2658 00:56:17.055513
2659 00:56:17.058672 RX Vref 0 -> 0, step: 1
2660 00:56:17.058771
2661 00:56:17.058857 RX Delay -40 -> 252, step: 8
2662 00:56:17.064988 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2663 00:56:17.068817 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2664 00:56:17.071816 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2665 00:56:17.075345 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2666 00:56:17.078497 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2667 00:56:17.085375 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2668 00:56:17.088819 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2669 00:56:17.091781 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2670 00:56:17.095475 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2671 00:56:17.099151 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2672 00:56:17.105225 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2673 00:56:17.108580 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2674 00:56:17.111920 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2675 00:56:17.115180 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2676 00:56:17.118693 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2677 00:56:17.124890 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2678 00:56:17.125000 ==
2679 00:56:17.128651 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 00:56:17.131672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 00:56:17.131749 ==
2682 00:56:17.131825 DQS Delay:
2683 00:56:17.135106 DQS0 = 0, DQS1 = 0
2684 00:56:17.135184 DQM Delay:
2685 00:56:17.138593 DQM0 = 115, DQM1 = 107
2686 00:56:17.138670 DQ Delay:
2687 00:56:17.142148 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2688 00:56:17.144899 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2689 00:56:17.148489 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2690 00:56:17.151715 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2691 00:56:17.151792
2692 00:56:17.151869
2693 00:56:17.155060 ==
2694 00:56:17.155137 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 00:56:17.161956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 00:56:17.162072 ==
2697 00:56:17.162149
2698 00:56:17.162220
2699 00:56:17.164781 TX Vref Scan disable
2700 00:56:17.164859 == TX Byte 0 ==
2701 00:56:17.168531 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2702 00:56:17.175144 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2703 00:56:17.175224 == TX Byte 1 ==
2704 00:56:17.178699 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2705 00:56:17.185592 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2706 00:56:17.185666 ==
2707 00:56:17.188931 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 00:56:17.191804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 00:56:17.191876 ==
2710 00:56:17.203434 TX Vref=22, minBit 0, minWin=25, winSum=415
2711 00:56:17.206847 TX Vref=24, minBit 1, minWin=25, winSum=420
2712 00:56:17.210438 TX Vref=26, minBit 0, minWin=26, winSum=425
2713 00:56:17.213607 TX Vref=28, minBit 0, minWin=26, winSum=427
2714 00:56:17.216863 TX Vref=30, minBit 0, minWin=26, winSum=428
2715 00:56:17.220365 TX Vref=32, minBit 0, minWin=26, winSum=428
2716 00:56:17.227240 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
2717 00:56:17.227328
2718 00:56:17.230157 Final TX Range 1 Vref 30
2719 00:56:17.230252
2720 00:56:17.230332 ==
2721 00:56:17.233608 Dram Type= 6, Freq= 0, CH_0, rank 0
2722 00:56:17.236767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2723 00:56:17.236864 ==
2724 00:56:17.236946
2725 00:56:17.239945
2726 00:56:17.240032 TX Vref Scan disable
2727 00:56:17.243374 == TX Byte 0 ==
2728 00:56:17.246895 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2729 00:56:17.250383 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2730 00:56:17.253133 == TX Byte 1 ==
2731 00:56:17.256545 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2732 00:56:17.260176 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2733 00:56:17.263480
2734 00:56:17.263552 [DATLAT]
2735 00:56:17.263608 Freq=1200, CH0 RK0
2736 00:56:17.263661
2737 00:56:17.266612 DATLAT Default: 0xd
2738 00:56:17.266674 0, 0xFFFF, sum = 0
2739 00:56:17.269817 1, 0xFFFF, sum = 0
2740 00:56:17.269912 2, 0xFFFF, sum = 0
2741 00:56:17.273595 3, 0xFFFF, sum = 0
2742 00:56:17.273690 4, 0xFFFF, sum = 0
2743 00:56:17.276536 5, 0xFFFF, sum = 0
2744 00:56:17.276601 6, 0xFFFF, sum = 0
2745 00:56:17.280523 7, 0xFFFF, sum = 0
2746 00:56:17.280617 8, 0xFFFF, sum = 0
2747 00:56:17.283315 9, 0xFFFF, sum = 0
2748 00:56:17.287047 10, 0xFFFF, sum = 0
2749 00:56:17.287117 11, 0xFFFF, sum = 0
2750 00:56:17.290597 12, 0x0, sum = 1
2751 00:56:17.290663 13, 0x0, sum = 2
2752 00:56:17.290723 14, 0x0, sum = 3
2753 00:56:17.294008 15, 0x0, sum = 4
2754 00:56:17.294114 best_step = 13
2755 00:56:17.294200
2756 00:56:17.294279 ==
2757 00:56:17.297493 Dram Type= 6, Freq= 0, CH_0, rank 0
2758 00:56:17.303742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2759 00:56:17.303809 ==
2760 00:56:17.303864 RX Vref Scan: 1
2761 00:56:17.303921
2762 00:56:17.306831 Set Vref Range= 32 -> 127
2763 00:56:17.306920
2764 00:56:17.310202 RX Vref 32 -> 127, step: 1
2765 00:56:17.310288
2766 00:56:17.313930 RX Delay -21 -> 252, step: 4
2767 00:56:17.314077
2768 00:56:17.316953 Set Vref, RX VrefLevel [Byte0]: 32
2769 00:56:17.320486 [Byte1]: 32
2770 00:56:17.320580
2771 00:56:17.323371 Set Vref, RX VrefLevel [Byte0]: 33
2772 00:56:17.326764 [Byte1]: 33
2773 00:56:17.326861
2774 00:56:17.330238 Set Vref, RX VrefLevel [Byte0]: 34
2775 00:56:17.333604 [Byte1]: 34
2776 00:56:17.337685
2777 00:56:17.337830 Set Vref, RX VrefLevel [Byte0]: 35
2778 00:56:17.340779 [Byte1]: 35
2779 00:56:17.345363
2780 00:56:17.345432 Set Vref, RX VrefLevel [Byte0]: 36
2781 00:56:17.348721 [Byte1]: 36
2782 00:56:17.353526
2783 00:56:17.353603 Set Vref, RX VrefLevel [Byte0]: 37
2784 00:56:17.360022 [Byte1]: 37
2785 00:56:17.360099
2786 00:56:17.363607 Set Vref, RX VrefLevel [Byte0]: 38
2787 00:56:17.366587 [Byte1]: 38
2788 00:56:17.366665
2789 00:56:17.369776 Set Vref, RX VrefLevel [Byte0]: 39
2790 00:56:17.373365 [Byte1]: 39
2791 00:56:17.377569
2792 00:56:17.377646 Set Vref, RX VrefLevel [Byte0]: 40
2793 00:56:17.380432 [Byte1]: 40
2794 00:56:17.385460
2795 00:56:17.385568 Set Vref, RX VrefLevel [Byte0]: 41
2796 00:56:17.388392 [Byte1]: 41
2797 00:56:17.393332
2798 00:56:17.393410 Set Vref, RX VrefLevel [Byte0]: 42
2799 00:56:17.396573 [Byte1]: 42
2800 00:56:17.401270
2801 00:56:17.401372 Set Vref, RX VrefLevel [Byte0]: 43
2802 00:56:17.404730 [Byte1]: 43
2803 00:56:17.409200
2804 00:56:17.409267 Set Vref, RX VrefLevel [Byte0]: 44
2805 00:56:17.412670 [Byte1]: 44
2806 00:56:17.417051
2807 00:56:17.417129 Set Vref, RX VrefLevel [Byte0]: 45
2808 00:56:17.420550 [Byte1]: 45
2809 00:56:17.424923
2810 00:56:17.425001 Set Vref, RX VrefLevel [Byte0]: 46
2811 00:56:17.428500 [Byte1]: 46
2812 00:56:17.433069
2813 00:56:17.433146 Set Vref, RX VrefLevel [Byte0]: 47
2814 00:56:17.435888 [Byte1]: 47
2815 00:56:17.440892
2816 00:56:17.441007 Set Vref, RX VrefLevel [Byte0]: 48
2817 00:56:17.443854 [Byte1]: 48
2818 00:56:17.448814
2819 00:56:17.448905 Set Vref, RX VrefLevel [Byte0]: 49
2820 00:56:17.452033 [Byte1]: 49
2821 00:56:17.456415
2822 00:56:17.456483 Set Vref, RX VrefLevel [Byte0]: 50
2823 00:56:17.459920 [Byte1]: 50
2824 00:56:17.464810
2825 00:56:17.464881 Set Vref, RX VrefLevel [Byte0]: 51
2826 00:56:17.468117 [Byte1]: 51
2827 00:56:17.472541
2828 00:56:17.472633 Set Vref, RX VrefLevel [Byte0]: 52
2829 00:56:17.475804 [Byte1]: 52
2830 00:56:17.480292
2831 00:56:17.480392 Set Vref, RX VrefLevel [Byte0]: 53
2832 00:56:17.483817 [Byte1]: 53
2833 00:56:17.488422
2834 00:56:17.488492 Set Vref, RX VrefLevel [Byte0]: 54
2835 00:56:17.491329 [Byte1]: 54
2836 00:56:17.496621
2837 00:56:17.496721 Set Vref, RX VrefLevel [Byte0]: 55
2838 00:56:17.499226 [Byte1]: 55
2839 00:56:17.504018
2840 00:56:17.504094 Set Vref, RX VrefLevel [Byte0]: 56
2841 00:56:17.507954 [Byte1]: 56
2842 00:56:17.511984
2843 00:56:17.512058 Set Vref, RX VrefLevel [Byte0]: 57
2844 00:56:17.515553 [Byte1]: 57
2845 00:56:17.519898
2846 00:56:17.520009 Set Vref, RX VrefLevel [Byte0]: 58
2847 00:56:17.523207 [Byte1]: 58
2848 00:56:17.528032
2849 00:56:17.528103 Set Vref, RX VrefLevel [Byte0]: 59
2850 00:56:17.531471 [Byte1]: 59
2851 00:56:17.536043
2852 00:56:17.536114 Set Vref, RX VrefLevel [Byte0]: 60
2853 00:56:17.539015 [Byte1]: 60
2854 00:56:17.543429
2855 00:56:17.543496 Set Vref, RX VrefLevel [Byte0]: 61
2856 00:56:17.546981 [Byte1]: 61
2857 00:56:17.551849
2858 00:56:17.551927 Set Vref, RX VrefLevel [Byte0]: 62
2859 00:56:17.555228 [Byte1]: 62
2860 00:56:17.559535
2861 00:56:17.559648 Set Vref, RX VrefLevel [Byte0]: 63
2862 00:56:17.562675 [Byte1]: 63
2863 00:56:17.567480
2864 00:56:17.567558 Set Vref, RX VrefLevel [Byte0]: 64
2865 00:56:17.570904 [Byte1]: 64
2866 00:56:17.575451
2867 00:56:17.575529 Set Vref, RX VrefLevel [Byte0]: 65
2868 00:56:17.578651 [Byte1]: 65
2869 00:56:17.583206
2870 00:56:17.583281 Set Vref, RX VrefLevel [Byte0]: 66
2871 00:56:17.586740 [Byte1]: 66
2872 00:56:17.591459
2873 00:56:17.591531 Set Vref, RX VrefLevel [Byte0]: 67
2874 00:56:17.594817 [Byte1]: 67
2875 00:56:17.599399
2876 00:56:17.599491 Set Vref, RX VrefLevel [Byte0]: 68
2877 00:56:17.602529 [Byte1]: 68
2878 00:56:17.606982
2879 00:56:17.607051 Set Vref, RX VrefLevel [Byte0]: 69
2880 00:56:17.610335 [Byte1]: 69
2881 00:56:17.615222
2882 00:56:17.615290 Final RX Vref Byte 0 = 52 to rank0
2883 00:56:17.618358 Final RX Vref Byte 1 = 57 to rank0
2884 00:56:17.622014 Final RX Vref Byte 0 = 52 to rank1
2885 00:56:17.625278 Final RX Vref Byte 1 = 57 to rank1==
2886 00:56:17.628567 Dram Type= 6, Freq= 0, CH_0, rank 0
2887 00:56:17.635280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 00:56:17.635361 ==
2889 00:56:17.635439 DQS Delay:
2890 00:56:17.635511 DQS0 = 0, DQS1 = 0
2891 00:56:17.638835 DQM Delay:
2892 00:56:17.638912 DQM0 = 115, DQM1 = 106
2893 00:56:17.641655 DQ Delay:
2894 00:56:17.645051 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2895 00:56:17.648675 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =120
2896 00:56:17.652012 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =96
2897 00:56:17.655369 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =114
2898 00:56:17.655446
2899 00:56:17.655523
2900 00:56:17.661856 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 409 ps
2901 00:56:17.665320 CH0 RK0: MR19=403, MR18=2F1
2902 00:56:17.672189 CH0_RK0: MR19=0x403, MR18=0x2F1, DQSOSC=409, MR23=63, INC=39, DEC=26
2903 00:56:17.672297
2904 00:56:17.675342 ----->DramcWriteLeveling(PI) begin...
2905 00:56:17.675435 ==
2906 00:56:17.678700 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 00:56:17.682117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 00:56:17.682192 ==
2909 00:56:17.685483 Write leveling (Byte 0): 34 => 34
2910 00:56:17.688561 Write leveling (Byte 1): 30 => 30
2911 00:56:17.692026 DramcWriteLeveling(PI) end<-----
2912 00:56:17.692104
2913 00:56:17.692180 ==
2914 00:56:17.695408 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 00:56:17.698508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 00:56:17.698586 ==
2917 00:56:17.702632 [Gating] SW mode calibration
2918 00:56:17.709063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2919 00:56:17.715377 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2920 00:56:17.718782 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2921 00:56:17.725462 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2922 00:56:17.729179 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 00:56:17.732278 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 00:56:17.735722 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 00:56:17.742207 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 00:56:17.745667 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2927 00:56:17.748967 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
2928 00:56:17.755841 1 0 0 | B1->B0 | 2c2c 2929 | 0 0 | (1 0) (0 0)
2929 00:56:17.758919 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2930 00:56:17.762479 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 00:56:17.769187 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 00:56:17.772544 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 00:56:17.775913 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 00:56:17.782258 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
2935 00:56:17.785847 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2936 00:56:17.789245 1 1 0 | B1->B0 | 3636 3d3d | 0 1 | (1 1) (0 0)
2937 00:56:17.795468 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 00:56:17.799233 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 00:56:17.802918 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 00:56:17.805602 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 00:56:17.812851 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 00:56:17.816024 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 00:56:17.818976 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2944 00:56:17.825821 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2945 00:56:17.829173 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 00:56:17.832781 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 00:56:17.839453 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 00:56:17.842425 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 00:56:17.845857 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 00:56:17.852640 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 00:56:17.856040 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 00:56:17.859169 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 00:56:17.865821 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 00:56:17.869259 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 00:56:17.872729 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 00:56:17.879111 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 00:56:17.882501 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 00:56:17.885872 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2959 00:56:17.889383 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2960 00:56:17.896352 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2961 00:56:17.899278 Total UI for P1: 0, mck2ui 16
2962 00:56:17.902939 best dqsien dly found for B0: ( 1, 3, 26)
2963 00:56:17.905931 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 00:56:17.909484 Total UI for P1: 0, mck2ui 16
2965 00:56:17.912441 best dqsien dly found for B1: ( 1, 4, 0)
2966 00:56:17.916057 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2967 00:56:17.919625 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2968 00:56:17.919727
2969 00:56:17.922535 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2970 00:56:17.926150 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2971 00:56:17.929301 [Gating] SW calibration Done
2972 00:56:17.929379 ==
2973 00:56:17.932537 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 00:56:17.936388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 00:56:17.939351 ==
2976 00:56:17.939431 RX Vref Scan: 0
2977 00:56:17.939508
2978 00:56:17.942879 RX Vref 0 -> 0, step: 1
2979 00:56:17.942957
2980 00:56:17.946209 RX Delay -40 -> 252, step: 8
2981 00:56:17.949061 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2982 00:56:17.952537 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2983 00:56:17.955899 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2984 00:56:17.959422 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2985 00:56:17.966195 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2986 00:56:17.969380 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2987 00:56:17.972743 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2988 00:56:17.975968 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2989 00:56:17.979440 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2990 00:56:17.982763 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2991 00:56:17.989591 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2992 00:56:17.992891 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2993 00:56:17.995879 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2994 00:56:17.999286 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2995 00:56:18.002613 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2996 00:56:18.009433 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2997 00:56:18.009527 ==
2998 00:56:18.012878 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 00:56:18.015999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 00:56:18.016108 ==
3001 00:56:18.016227 DQS Delay:
3002 00:56:18.019337 DQS0 = 0, DQS1 = 0
3003 00:56:18.019496 DQM Delay:
3004 00:56:18.022830 DQM0 = 115, DQM1 = 108
3005 00:56:18.022908 DQ Delay:
3006 00:56:18.026128 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3007 00:56:18.029387 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
3008 00:56:18.032711 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3009 00:56:18.035944 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
3010 00:56:18.036026
3011 00:56:18.036096
3012 00:56:18.039313 ==
3013 00:56:18.039379 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 00:56:18.046286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 00:56:18.046371 ==
3016 00:56:18.046443
3017 00:56:18.046511
3018 00:56:18.049190 TX Vref Scan disable
3019 00:56:18.049252 == TX Byte 0 ==
3020 00:56:18.052624 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3021 00:56:18.059197 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3022 00:56:18.059284 == TX Byte 1 ==
3023 00:56:18.062600 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3024 00:56:18.069494 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3025 00:56:18.069594 ==
3026 00:56:18.072882 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 00:56:18.076282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 00:56:18.076359 ==
3029 00:56:18.088350 TX Vref=22, minBit 1, minWin=25, winSum=420
3030 00:56:18.091656 TX Vref=24, minBit 3, minWin=25, winSum=426
3031 00:56:18.094897 TX Vref=26, minBit 1, minWin=25, winSum=429
3032 00:56:18.098169 TX Vref=28, minBit 2, minWin=26, winSum=434
3033 00:56:18.101765 TX Vref=30, minBit 3, minWin=26, winSum=437
3034 00:56:18.108430 TX Vref=32, minBit 13, minWin=26, winSum=438
3035 00:56:18.111409 [TxChooseVref] Worse bit 13, Min win 26, Win sum 438, Final Vref 32
3036 00:56:18.111479
3037 00:56:18.114682 Final TX Range 1 Vref 32
3038 00:56:18.114749
3039 00:56:18.114807 ==
3040 00:56:18.118215 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 00:56:18.121653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 00:56:18.125012 ==
3043 00:56:18.125083
3044 00:56:18.125140
3045 00:56:18.125192 TX Vref Scan disable
3046 00:56:18.128330 == TX Byte 0 ==
3047 00:56:18.131847 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3048 00:56:18.134925 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3049 00:56:18.138354 == TX Byte 1 ==
3050 00:56:18.141590 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3051 00:56:18.145049 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3052 00:56:18.148325
3053 00:56:18.148402 [DATLAT]
3054 00:56:18.148466 Freq=1200, CH0 RK1
3055 00:56:18.148523
3056 00:56:18.151843 DATLAT Default: 0xd
3057 00:56:18.151921 0, 0xFFFF, sum = 0
3058 00:56:18.154792 1, 0xFFFF, sum = 0
3059 00:56:18.154865 2, 0xFFFF, sum = 0
3060 00:56:18.158279 3, 0xFFFF, sum = 0
3061 00:56:18.158350 4, 0xFFFF, sum = 0
3062 00:56:18.161821 5, 0xFFFF, sum = 0
3063 00:56:18.161892 6, 0xFFFF, sum = 0
3064 00:56:18.165224 7, 0xFFFF, sum = 0
3065 00:56:18.168530 8, 0xFFFF, sum = 0
3066 00:56:18.168598 9, 0xFFFF, sum = 0
3067 00:56:18.172152 10, 0xFFFF, sum = 0
3068 00:56:18.172218 11, 0xFFFF, sum = 0
3069 00:56:18.175429 12, 0x0, sum = 1
3070 00:56:18.175496 13, 0x0, sum = 2
3071 00:56:18.175552 14, 0x0, sum = 3
3072 00:56:18.178542 15, 0x0, sum = 4
3073 00:56:18.178612 best_step = 13
3074 00:56:18.178669
3075 00:56:18.182104 ==
3076 00:56:18.182167 Dram Type= 6, Freq= 0, CH_0, rank 1
3077 00:56:18.188673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 00:56:18.188749 ==
3079 00:56:18.188807 RX Vref Scan: 0
3080 00:56:18.188864
3081 00:56:18.191658 RX Vref 0 -> 0, step: 1
3082 00:56:18.191723
3083 00:56:18.194849 RX Delay -21 -> 252, step: 4
3084 00:56:18.198276 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3085 00:56:18.205433 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3086 00:56:18.208472 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3087 00:56:18.211854 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3088 00:56:18.215417 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3089 00:56:18.218697 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3090 00:56:18.221870 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3091 00:56:18.228548 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3092 00:56:18.232010 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3093 00:56:18.235026 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3094 00:56:18.238968 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3095 00:56:18.241940 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3096 00:56:18.248506 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3097 00:56:18.251848 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3098 00:56:18.255470 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3099 00:56:18.258502 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3100 00:56:18.258578 ==
3101 00:56:18.262064 Dram Type= 6, Freq= 0, CH_0, rank 1
3102 00:56:18.265266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 00:56:18.268606 ==
3104 00:56:18.268683 DQS Delay:
3105 00:56:18.268742 DQS0 = 0, DQS1 = 0
3106 00:56:18.272059 DQM Delay:
3107 00:56:18.272134 DQM0 = 114, DQM1 = 105
3108 00:56:18.275535 DQ Delay:
3109 00:56:18.279016 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3110 00:56:18.282282 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =120
3111 00:56:18.285808 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3112 00:56:18.288573 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =114
3113 00:56:18.288682
3114 00:56:18.288756
3115 00:56:18.295287 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3116 00:56:18.298713 CH0 RK1: MR19=403, MR18=3F4
3117 00:56:18.305333 CH0_RK1: MR19=0x403, MR18=0x3F4, DQSOSC=408, MR23=63, INC=39, DEC=26
3118 00:56:18.308896 [RxdqsGatingPostProcess] freq 1200
3119 00:56:18.312160 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3120 00:56:18.315640 best DQS0 dly(2T, 0.5T) = (0, 12)
3121 00:56:18.319022 best DQS1 dly(2T, 0.5T) = (0, 12)
3122 00:56:18.322368 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3123 00:56:18.325220 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3124 00:56:18.329252 best DQS0 dly(2T, 0.5T) = (0, 11)
3125 00:56:18.332152 best DQS1 dly(2T, 0.5T) = (0, 12)
3126 00:56:18.335514 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3127 00:56:18.339089 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3128 00:56:18.342295 Pre-setting of DQS Precalculation
3129 00:56:18.345661 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3130 00:56:18.345738 ==
3131 00:56:18.348834 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 00:56:18.356001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 00:56:18.356079 ==
3134 00:56:18.358801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3135 00:56:18.365719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3136 00:56:18.374019 [CA 0] Center 38 (9~68) winsize 60
3137 00:56:18.377192 [CA 1] Center 38 (8~68) winsize 61
3138 00:56:18.380885 [CA 2] Center 35 (5~65) winsize 61
3139 00:56:18.383815 [CA 3] Center 34 (4~65) winsize 62
3140 00:56:18.387495 [CA 4] Center 34 (4~65) winsize 62
3141 00:56:18.390724 [CA 5] Center 34 (4~64) winsize 61
3142 00:56:18.390833
3143 00:56:18.394119 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3144 00:56:18.394195
3145 00:56:18.398092 [CATrainingPosCal] consider 1 rank data
3146 00:56:18.400686 u2DelayCellTimex100 = 270/100 ps
3147 00:56:18.404136 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3148 00:56:18.407444 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3149 00:56:18.410782 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3150 00:56:18.417564 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3151 00:56:18.421017 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3152 00:56:18.423931 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3153 00:56:18.424008
3154 00:56:18.427347 CA PerBit enable=1, Macro0, CA PI delay=34
3155 00:56:18.427422
3156 00:56:18.430771 [CBTSetCACLKResult] CA Dly = 34
3157 00:56:18.430846 CS Dly: 6 (0~37)
3158 00:56:18.430932 ==
3159 00:56:18.434203 Dram Type= 6, Freq= 0, CH_1, rank 1
3160 00:56:18.441286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3161 00:56:18.441363 ==
3162 00:56:18.444185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3163 00:56:18.450721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3164 00:56:18.459341 [CA 0] Center 38 (8~68) winsize 61
3165 00:56:18.462750 [CA 1] Center 38 (8~68) winsize 61
3166 00:56:18.466252 [CA 2] Center 34 (4~65) winsize 62
3167 00:56:18.469757 [CA 3] Center 34 (4~65) winsize 62
3168 00:56:18.472792 [CA 4] Center 34 (4~65) winsize 62
3169 00:56:18.476145 [CA 5] Center 33 (3~63) winsize 61
3170 00:56:18.476221
3171 00:56:18.479584 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3172 00:56:18.479659
3173 00:56:18.483136 [CATrainingPosCal] consider 2 rank data
3174 00:56:18.486454 u2DelayCellTimex100 = 270/100 ps
3175 00:56:18.489632 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3176 00:56:18.492894 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3177 00:56:18.499734 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3178 00:56:18.502992 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3179 00:56:18.506152 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3180 00:56:18.509633 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3181 00:56:18.509709
3182 00:56:18.512736 CA PerBit enable=1, Macro0, CA PI delay=33
3183 00:56:18.512811
3184 00:56:18.516408 [CBTSetCACLKResult] CA Dly = 33
3185 00:56:18.516484 CS Dly: 7 (0~40)
3186 00:56:18.516542
3187 00:56:18.519254 ----->DramcWriteLeveling(PI) begin...
3188 00:56:18.522616 ==
3189 00:56:18.525932 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 00:56:18.529421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 00:56:18.529497 ==
3192 00:56:18.532744 Write leveling (Byte 0): 27 => 27
3193 00:56:18.536168 Write leveling (Byte 1): 30 => 30
3194 00:56:18.539787 DramcWriteLeveling(PI) end<-----
3195 00:56:18.539853
3196 00:56:18.539908 ==
3197 00:56:18.542588 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 00:56:18.546071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 00:56:18.546130 ==
3200 00:56:18.549542 [Gating] SW mode calibration
3201 00:56:18.556316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3202 00:56:18.559505 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3203 00:56:18.565889 0 15 0 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
3204 00:56:18.569166 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 00:56:18.573118 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 00:56:18.579443 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 00:56:18.582874 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 00:56:18.586327 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 00:56:18.593168 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 00:56:18.596688 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3211 00:56:18.600041 1 0 0 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)
3212 00:56:18.606209 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 00:56:18.609621 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 00:56:18.612763 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 00:56:18.619533 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 00:56:18.623311 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 00:56:18.626325 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 00:56:18.633061 1 0 28 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
3219 00:56:18.636366 1 1 0 | B1->B0 | 4141 3636 | 0 1 | (1 1) (0 0)
3220 00:56:18.639395 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 00:56:18.642704 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 00:56:18.649437 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 00:56:18.652980 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 00:56:18.656261 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 00:56:18.663106 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 00:56:18.666497 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3227 00:56:18.669800 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3228 00:56:18.676688 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 00:56:18.679576 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 00:56:18.683007 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 00:56:18.689783 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 00:56:18.693205 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 00:56:18.696109 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 00:56:18.703167 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 00:56:18.706400 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 00:56:18.709873 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 00:56:18.716387 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 00:56:18.719878 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 00:56:18.723332 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 00:56:18.726604 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 00:56:18.732856 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 00:56:18.736719 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3243 00:56:18.739901 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3244 00:56:18.743229 Total UI for P1: 0, mck2ui 16
3245 00:56:18.746421 best dqsien dly found for B0: ( 1, 3, 28)
3246 00:56:18.753349 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 00:56:18.753431 Total UI for P1: 0, mck2ui 16
3248 00:56:18.759603 best dqsien dly found for B1: ( 1, 3, 30)
3249 00:56:18.763300 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3250 00:56:18.766882 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3251 00:56:18.766960
3252 00:56:18.769713 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3253 00:56:18.773637 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3254 00:56:18.776766 [Gating] SW calibration Done
3255 00:56:18.776846 ==
3256 00:56:18.779789 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 00:56:18.783255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 00:56:18.783324 ==
3259 00:56:18.786711 RX Vref Scan: 0
3260 00:56:18.786772
3261 00:56:18.786825 RX Vref 0 -> 0, step: 1
3262 00:56:18.786877
3263 00:56:18.790087 RX Delay -40 -> 252, step: 8
3264 00:56:18.793504 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3265 00:56:18.800154 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3266 00:56:18.803333 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3267 00:56:18.806716 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3268 00:56:18.810081 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3269 00:56:18.813475 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3270 00:56:18.820201 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3271 00:56:18.823290 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3272 00:56:18.826780 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3273 00:56:18.829581 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3274 00:56:18.833061 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3275 00:56:18.840050 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3276 00:56:18.842950 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3277 00:56:18.846524 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3278 00:56:18.850175 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3279 00:56:18.852843 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3280 00:56:18.856187 ==
3281 00:56:18.856279 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 00:56:18.863169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 00:56:18.863237 ==
3284 00:56:18.863293 DQS Delay:
3285 00:56:18.866454 DQS0 = 0, DQS1 = 0
3286 00:56:18.866520 DQM Delay:
3287 00:56:18.869865 DQM0 = 115, DQM1 = 108
3288 00:56:18.869929 DQ Delay:
3289 00:56:18.872946 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3290 00:56:18.876113 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3291 00:56:18.879720 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3292 00:56:18.883228 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3293 00:56:18.883306
3294 00:56:18.883383
3295 00:56:18.883454 ==
3296 00:56:18.886340 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 00:56:18.892913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 00:56:18.892991 ==
3299 00:56:18.893068
3300 00:56:18.893140
3301 00:56:18.893209 TX Vref Scan disable
3302 00:56:18.896464 == TX Byte 0 ==
3303 00:56:18.899826 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3304 00:56:18.903362 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3305 00:56:18.906107 == TX Byte 1 ==
3306 00:56:18.910166 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3307 00:56:18.912933 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3308 00:56:18.916662 ==
3309 00:56:18.916736 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 00:56:18.922833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 00:56:18.922907 ==
3312 00:56:18.933919 TX Vref=22, minBit 15, minWin=24, winSum=413
3313 00:56:18.937269 TX Vref=24, minBit 1, minWin=25, winSum=419
3314 00:56:18.940946 TX Vref=26, minBit 1, minWin=25, winSum=420
3315 00:56:18.944416 TX Vref=28, minBit 1, minWin=26, winSum=424
3316 00:56:18.947388 TX Vref=30, minBit 1, minWin=26, winSum=429
3317 00:56:18.950847 TX Vref=32, minBit 15, minWin=25, winSum=428
3318 00:56:18.957724 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3319 00:56:18.957793
3320 00:56:18.961035 Final TX Range 1 Vref 30
3321 00:56:18.961100
3322 00:56:18.961155 ==
3323 00:56:18.964633 Dram Type= 6, Freq= 0, CH_1, rank 0
3324 00:56:18.967955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3325 00:56:18.968021 ==
3326 00:56:18.968076
3327 00:56:18.971318
3328 00:56:18.971379 TX Vref Scan disable
3329 00:56:18.974116 == TX Byte 0 ==
3330 00:56:18.977566 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3331 00:56:18.980951 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3332 00:56:18.984023 == TX Byte 1 ==
3333 00:56:18.987721 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3334 00:56:18.990684 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3335 00:56:18.990749
3336 00:56:18.994201 [DATLAT]
3337 00:56:18.994263 Freq=1200, CH1 RK0
3338 00:56:18.994320
3339 00:56:18.997836 DATLAT Default: 0xd
3340 00:56:18.997901 0, 0xFFFF, sum = 0
3341 00:56:19.000852 1, 0xFFFF, sum = 0
3342 00:56:19.000920 2, 0xFFFF, sum = 0
3343 00:56:19.004442 3, 0xFFFF, sum = 0
3344 00:56:19.004512 4, 0xFFFF, sum = 0
3345 00:56:19.007868 5, 0xFFFF, sum = 0
3346 00:56:19.007934 6, 0xFFFF, sum = 0
3347 00:56:19.011249 7, 0xFFFF, sum = 0
3348 00:56:19.011318 8, 0xFFFF, sum = 0
3349 00:56:19.014655 9, 0xFFFF, sum = 0
3350 00:56:19.014721 10, 0xFFFF, sum = 0
3351 00:56:19.017820 11, 0xFFFF, sum = 0
3352 00:56:19.017886 12, 0x0, sum = 1
3353 00:56:19.020900 13, 0x0, sum = 2
3354 00:56:19.020977 14, 0x0, sum = 3
3355 00:56:19.024422 15, 0x0, sum = 4
3356 00:56:19.024499 best_step = 13
3357 00:56:19.024558
3358 00:56:19.024611 ==
3359 00:56:19.027648 Dram Type= 6, Freq= 0, CH_1, rank 0
3360 00:56:19.034425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3361 00:56:19.034502 ==
3362 00:56:19.034560 RX Vref Scan: 1
3363 00:56:19.034614
3364 00:56:19.037894 Set Vref Range= 32 -> 127
3365 00:56:19.037968
3366 00:56:19.041258 RX Vref 32 -> 127, step: 1
3367 00:56:19.041332
3368 00:56:19.044288 RX Delay -21 -> 252, step: 4
3369 00:56:19.044364
3370 00:56:19.047753 Set Vref, RX VrefLevel [Byte0]: 32
3371 00:56:19.051191 [Byte1]: 32
3372 00:56:19.051289
3373 00:56:19.054647 Set Vref, RX VrefLevel [Byte0]: 33
3374 00:56:19.058008 [Byte1]: 33
3375 00:56:19.058097
3376 00:56:19.061369 Set Vref, RX VrefLevel [Byte0]: 34
3377 00:56:19.064640 [Byte1]: 34
3378 00:56:19.068596
3379 00:56:19.068671 Set Vref, RX VrefLevel [Byte0]: 35
3380 00:56:19.071772 [Byte1]: 35
3381 00:56:19.076603
3382 00:56:19.076678 Set Vref, RX VrefLevel [Byte0]: 36
3383 00:56:19.079425 [Byte1]: 36
3384 00:56:19.084208
3385 00:56:19.084286 Set Vref, RX VrefLevel [Byte0]: 37
3386 00:56:19.087627 [Byte1]: 37
3387 00:56:19.092204
3388 00:56:19.092278 Set Vref, RX VrefLevel [Byte0]: 38
3389 00:56:19.095625 [Byte1]: 38
3390 00:56:19.100118
3391 00:56:19.100194 Set Vref, RX VrefLevel [Byte0]: 39
3392 00:56:19.103236 [Byte1]: 39
3393 00:56:19.108302
3394 00:56:19.108378 Set Vref, RX VrefLevel [Byte0]: 40
3395 00:56:19.111502 [Byte1]: 40
3396 00:56:19.115941
3397 00:56:19.116017 Set Vref, RX VrefLevel [Byte0]: 41
3398 00:56:19.119174 [Byte1]: 41
3399 00:56:19.123879
3400 00:56:19.123957 Set Vref, RX VrefLevel [Byte0]: 42
3401 00:56:19.127107 [Byte1]: 42
3402 00:56:19.131456
3403 00:56:19.131524 Set Vref, RX VrefLevel [Byte0]: 43
3404 00:56:19.134852 [Byte1]: 43
3405 00:56:19.139561
3406 00:56:19.139629 Set Vref, RX VrefLevel [Byte0]: 44
3407 00:56:19.142628 [Byte1]: 44
3408 00:56:19.147833
3409 00:56:19.147904 Set Vref, RX VrefLevel [Byte0]: 45
3410 00:56:19.151201 [Byte1]: 45
3411 00:56:19.155821
3412 00:56:19.155888 Set Vref, RX VrefLevel [Byte0]: 46
3413 00:56:19.158555 [Byte1]: 46
3414 00:56:19.163199
3415 00:56:19.163268 Set Vref, RX VrefLevel [Byte0]: 47
3416 00:56:19.166608 [Byte1]: 47
3417 00:56:19.171357
3418 00:56:19.171433 Set Vref, RX VrefLevel [Byte0]: 48
3419 00:56:19.174483 [Byte1]: 48
3420 00:56:19.179470
3421 00:56:19.179547 Set Vref, RX VrefLevel [Byte0]: 49
3422 00:56:19.182464 [Byte1]: 49
3423 00:56:19.187172
3424 00:56:19.187248 Set Vref, RX VrefLevel [Byte0]: 50
3425 00:56:19.190430 [Byte1]: 50
3426 00:56:19.194951
3427 00:56:19.195042 Set Vref, RX VrefLevel [Byte0]: 51
3428 00:56:19.198480 [Byte1]: 51
3429 00:56:19.202950
3430 00:56:19.203025 Set Vref, RX VrefLevel [Byte0]: 52
3431 00:56:19.206160 [Byte1]: 52
3432 00:56:19.211069
3433 00:56:19.211145 Set Vref, RX VrefLevel [Byte0]: 53
3434 00:56:19.214545 [Byte1]: 53
3435 00:56:19.218840
3436 00:56:19.218915 Set Vref, RX VrefLevel [Byte0]: 54
3437 00:56:19.222460 [Byte1]: 54
3438 00:56:19.227106
3439 00:56:19.227182 Set Vref, RX VrefLevel [Byte0]: 55
3440 00:56:19.230129 [Byte1]: 55
3441 00:56:19.234810
3442 00:56:19.234886 Set Vref, RX VrefLevel [Byte0]: 56
3443 00:56:19.237680 [Byte1]: 56
3444 00:56:19.242750
3445 00:56:19.242826 Set Vref, RX VrefLevel [Byte0]: 57
3446 00:56:19.245903 [Byte1]: 57
3447 00:56:19.250433
3448 00:56:19.250509 Set Vref, RX VrefLevel [Byte0]: 58
3449 00:56:19.253854 [Byte1]: 58
3450 00:56:19.258343
3451 00:56:19.258412 Set Vref, RX VrefLevel [Byte0]: 59
3452 00:56:19.261747 [Byte1]: 59
3453 00:56:19.266591
3454 00:56:19.266662 Set Vref, RX VrefLevel [Byte0]: 60
3455 00:56:19.269680 [Byte1]: 60
3456 00:56:19.274409
3457 00:56:19.274480 Set Vref, RX VrefLevel [Byte0]: 61
3458 00:56:19.277654 [Byte1]: 61
3459 00:56:19.282162
3460 00:56:19.282240 Set Vref, RX VrefLevel [Byte0]: 62
3461 00:56:19.285604 [Byte1]: 62
3462 00:56:19.290137
3463 00:56:19.290212 Set Vref, RX VrefLevel [Byte0]: 63
3464 00:56:19.293624 [Byte1]: 63
3465 00:56:19.297874
3466 00:56:19.297950 Set Vref, RX VrefLevel [Byte0]: 64
3467 00:56:19.301126 [Byte1]: 64
3468 00:56:19.305735
3469 00:56:19.305811 Set Vref, RX VrefLevel [Byte0]: 65
3470 00:56:19.309259 [Byte1]: 65
3471 00:56:19.314219
3472 00:56:19.314296 Set Vref, RX VrefLevel [Byte0]: 66
3473 00:56:19.317002 [Byte1]: 66
3474 00:56:19.321486
3475 00:56:19.321564 Set Vref, RX VrefLevel [Byte0]: 67
3476 00:56:19.324809 [Byte1]: 67
3477 00:56:19.329951
3478 00:56:19.330066 Set Vref, RX VrefLevel [Byte0]: 68
3479 00:56:19.333167 [Byte1]: 68
3480 00:56:19.337483
3481 00:56:19.337559 Set Vref, RX VrefLevel [Byte0]: 69
3482 00:56:19.341044 [Byte1]: 69
3483 00:56:19.345263
3484 00:56:19.345341 Set Vref, RX VrefLevel [Byte0]: 70
3485 00:56:19.349129 [Byte1]: 70
3486 00:56:19.353542
3487 00:56:19.353618 Set Vref, RX VrefLevel [Byte0]: 71
3488 00:56:19.357103 [Byte1]: 71
3489 00:56:19.361497
3490 00:56:19.361566 Final RX Vref Byte 0 = 52 to rank0
3491 00:56:19.365018 Final RX Vref Byte 1 = 52 to rank0
3492 00:56:19.367841 Final RX Vref Byte 0 = 52 to rank1
3493 00:56:19.371422 Final RX Vref Byte 1 = 52 to rank1==
3494 00:56:19.374383 Dram Type= 6, Freq= 0, CH_1, rank 0
3495 00:56:19.381176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3496 00:56:19.381269 ==
3497 00:56:19.381328 DQS Delay:
3498 00:56:19.381383 DQS0 = 0, DQS1 = 0
3499 00:56:19.384519 DQM Delay:
3500 00:56:19.384595 DQM0 = 115, DQM1 = 109
3501 00:56:19.387778 DQ Delay:
3502 00:56:19.391224 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =112
3503 00:56:19.395053 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =112
3504 00:56:19.397735 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3505 00:56:19.401308 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3506 00:56:19.401376
3507 00:56:19.401432
3508 00:56:19.408008 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe3, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3509 00:56:19.411494 CH1 RK0: MR19=303, MR18=FFE3
3510 00:56:19.417522 CH1_RK0: MR19=0x303, MR18=0xFFE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3511 00:56:19.417594
3512 00:56:19.421123 ----->DramcWriteLeveling(PI) begin...
3513 00:56:19.421195 ==
3514 00:56:19.424420 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 00:56:19.427799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 00:56:19.430961 ==
3517 00:56:19.431030 Write leveling (Byte 0): 26 => 26
3518 00:56:19.434380 Write leveling (Byte 1): 29 => 29
3519 00:56:19.437935 DramcWriteLeveling(PI) end<-----
3520 00:56:19.438042
3521 00:56:19.438099 ==
3522 00:56:19.441007 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 00:56:19.447906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 00:56:19.447982 ==
3525 00:56:19.448039 [Gating] SW mode calibration
3526 00:56:19.458074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3527 00:56:19.461534 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3528 00:56:19.464624 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3529 00:56:19.471552 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 00:56:19.474295 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3531 00:56:19.477788 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3532 00:56:19.484493 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3533 00:56:19.487881 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3534 00:56:19.491115 0 15 24 | B1->B0 | 3333 2b2b | 1 0 | (1 1) (1 0)
3535 00:56:19.497622 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3536 00:56:19.501381 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 00:56:19.504350 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 00:56:19.511127 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3539 00:56:19.514325 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3540 00:56:19.517656 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3541 00:56:19.524626 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3542 00:56:19.528146 1 0 24 | B1->B0 | 2828 3c3c | 0 0 | (0 0) (0 0)
3543 00:56:19.531139 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3544 00:56:19.537642 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 00:56:19.541204 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 00:56:19.544562 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 00:56:19.548193 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 00:56:19.555015 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 00:56:19.558349 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3550 00:56:19.561704 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3551 00:56:19.568188 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3552 00:56:19.571564 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 00:56:19.574488 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 00:56:19.581477 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 00:56:19.584858 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 00:56:19.587750 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 00:56:19.594388 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 00:56:19.597943 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 00:56:19.601436 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 00:56:19.607805 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 00:56:19.611620 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 00:56:19.615070 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 00:56:19.621589 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 00:56:19.624899 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 00:56:19.628095 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3566 00:56:19.631496 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3567 00:56:19.638216 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3568 00:56:19.641546 Total UI for P1: 0, mck2ui 16
3569 00:56:19.644567 best dqsien dly found for B0: ( 1, 3, 22)
3570 00:56:19.648253 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3571 00:56:19.651646 Total UI for P1: 0, mck2ui 16
3572 00:56:19.655180 best dqsien dly found for B1: ( 1, 3, 26)
3573 00:56:19.658517 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3574 00:56:19.661826 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3575 00:56:19.661901
3576 00:56:19.665250 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3577 00:56:19.668206 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3578 00:56:19.671641 [Gating] SW calibration Done
3579 00:56:19.671722 ==
3580 00:56:19.674852 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 00:56:19.681742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 00:56:19.681816 ==
3583 00:56:19.681875 RX Vref Scan: 0
3584 00:56:19.681930
3585 00:56:19.684804 RX Vref 0 -> 0, step: 1
3586 00:56:19.684872
3587 00:56:19.688495 RX Delay -40 -> 252, step: 8
3588 00:56:19.691264 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3589 00:56:19.694567 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3590 00:56:19.697865 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3591 00:56:19.701390 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3592 00:56:19.708119 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3593 00:56:19.711623 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3594 00:56:19.714886 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3595 00:56:19.718102 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3596 00:56:19.721762 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3597 00:56:19.725297 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3598 00:56:19.731647 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3599 00:56:19.734940 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3600 00:56:19.738309 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3601 00:56:19.741764 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3602 00:56:19.748324 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3603 00:56:19.751568 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3604 00:56:19.751644 ==
3605 00:56:19.755152 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 00:56:19.758446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 00:56:19.758523 ==
3608 00:56:19.758582 DQS Delay:
3609 00:56:19.761492 DQS0 = 0, DQS1 = 0
3610 00:56:19.761568 DQM Delay:
3611 00:56:19.764935 DQM0 = 114, DQM1 = 111
3612 00:56:19.765011 DQ Delay:
3613 00:56:19.768107 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3614 00:56:19.771614 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =111
3615 00:56:19.775073 DQ8 =103, DQ9 =99, DQ10 =111, DQ11 =103
3616 00:56:19.778394 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3617 00:56:19.782058
3618 00:56:19.782133
3619 00:56:19.782192 ==
3620 00:56:19.784762 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 00:56:19.788586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 00:56:19.788662 ==
3623 00:56:19.788721
3624 00:56:19.788775
3625 00:56:19.791630 TX Vref Scan disable
3626 00:56:19.791705 == TX Byte 0 ==
3627 00:56:19.798341 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3628 00:56:19.801758 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3629 00:56:19.801834 == TX Byte 1 ==
3630 00:56:19.808577 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3631 00:56:19.811451 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3632 00:56:19.811527 ==
3633 00:56:19.814986 Dram Type= 6, Freq= 0, CH_1, rank 1
3634 00:56:19.818237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3635 00:56:19.818313 ==
3636 00:56:19.830718 TX Vref=22, minBit 0, minWin=25, winSum=418
3637 00:56:19.833910 TX Vref=24, minBit 3, minWin=25, winSum=425
3638 00:56:19.837520 TX Vref=26, minBit 0, minWin=26, winSum=429
3639 00:56:19.840547 TX Vref=28, minBit 9, minWin=26, winSum=432
3640 00:56:19.843879 TX Vref=30, minBit 4, minWin=26, winSum=437
3641 00:56:19.847476 TX Vref=32, minBit 4, minWin=26, winSum=436
3642 00:56:19.853847 [TxChooseVref] Worse bit 4, Min win 26, Win sum 437, Final Vref 30
3643 00:56:19.853946
3644 00:56:19.857420 Final TX Range 1 Vref 30
3645 00:56:19.857496
3646 00:56:19.857554 ==
3647 00:56:19.861009 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 00:56:19.863666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 00:56:19.863743 ==
3650 00:56:19.863805
3651 00:56:19.867339
3652 00:56:19.867415 TX Vref Scan disable
3653 00:56:19.870504 == TX Byte 0 ==
3654 00:56:19.874185 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3655 00:56:19.877418 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3656 00:56:19.881104 == TX Byte 1 ==
3657 00:56:19.884090 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3658 00:56:19.887311 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3659 00:56:19.887383
3660 00:56:19.890677 [DATLAT]
3661 00:56:19.890754 Freq=1200, CH1 RK1
3662 00:56:19.890832
3663 00:56:19.894098 DATLAT Default: 0xd
3664 00:56:19.894188 0, 0xFFFF, sum = 0
3665 00:56:19.897711 1, 0xFFFF, sum = 0
3666 00:56:19.897813 2, 0xFFFF, sum = 0
3667 00:56:19.900930 3, 0xFFFF, sum = 0
3668 00:56:19.901032 4, 0xFFFF, sum = 0
3669 00:56:19.904349 5, 0xFFFF, sum = 0
3670 00:56:19.904428 6, 0xFFFF, sum = 0
3671 00:56:19.907414 7, 0xFFFF, sum = 0
3672 00:56:19.907493 8, 0xFFFF, sum = 0
3673 00:56:19.910554 9, 0xFFFF, sum = 0
3674 00:56:19.910632 10, 0xFFFF, sum = 0
3675 00:56:19.914403 11, 0xFFFF, sum = 0
3676 00:56:19.917278 12, 0x0, sum = 1
3677 00:56:19.917352 13, 0x0, sum = 2
3678 00:56:19.917425 14, 0x0, sum = 3
3679 00:56:19.920692 15, 0x0, sum = 4
3680 00:56:19.920771 best_step = 13
3681 00:56:19.920846
3682 00:56:19.920917 ==
3683 00:56:19.924190 Dram Type= 6, Freq= 0, CH_1, rank 1
3684 00:56:19.931159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3685 00:56:19.931237 ==
3686 00:56:19.931314 RX Vref Scan: 0
3687 00:56:19.931386
3688 00:56:19.934104 RX Vref 0 -> 0, step: 1
3689 00:56:19.934173
3690 00:56:19.937461 RX Delay -13 -> 252, step: 4
3691 00:56:19.940987 iDelay=195, Bit 0, Center 112 (43 ~ 182) 140
3692 00:56:19.944357 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3693 00:56:19.950501 iDelay=195, Bit 2, Center 104 (39 ~ 170) 132
3694 00:56:19.954076 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3695 00:56:19.957299 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3696 00:56:19.960571 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3697 00:56:19.963949 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3698 00:56:19.970521 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3699 00:56:19.973960 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3700 00:56:19.977461 iDelay=195, Bit 9, Center 98 (35 ~ 162) 128
3701 00:56:19.981015 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3702 00:56:19.984137 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3703 00:56:19.987392 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3704 00:56:19.994175 iDelay=195, Bit 13, Center 120 (55 ~ 186) 132
3705 00:56:19.997600 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3706 00:56:20.000956 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3707 00:56:20.001038 ==
3708 00:56:20.004259 Dram Type= 6, Freq= 0, CH_1, rank 1
3709 00:56:20.007742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3710 00:56:20.007820 ==
3711 00:56:20.011269 DQS Delay:
3712 00:56:20.011347 DQS0 = 0, DQS1 = 0
3713 00:56:20.014512 DQM Delay:
3714 00:56:20.014589 DQM0 = 112, DQM1 = 109
3715 00:56:20.017872 DQ Delay:
3716 00:56:20.021190 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =110
3717 00:56:20.024314 DQ4 =110, DQ5 =124, DQ6 =122, DQ7 =110
3718 00:56:20.028122 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3719 00:56:20.031390 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3720 00:56:20.031467
3721 00:56:20.031543
3722 00:56:20.038429 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3723 00:56:20.041376 CH1 RK1: MR19=303, MR18=F7FE
3724 00:56:20.048131 CH1_RK1: MR19=0x303, MR18=0xF7FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3725 00:56:20.051693 [RxdqsGatingPostProcess] freq 1200
3726 00:56:20.055138 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3727 00:56:20.058041 best DQS0 dly(2T, 0.5T) = (0, 11)
3728 00:56:20.061547 best DQS1 dly(2T, 0.5T) = (0, 11)
3729 00:56:20.065387 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3730 00:56:20.068110 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3731 00:56:20.071278 best DQS0 dly(2T, 0.5T) = (0, 11)
3732 00:56:20.074756 best DQS1 dly(2T, 0.5T) = (0, 11)
3733 00:56:20.078253 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3734 00:56:20.081624 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3735 00:56:20.084712 Pre-setting of DQS Precalculation
3736 00:56:20.088187 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3737 00:56:20.098149 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3738 00:56:20.104861 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3739 00:56:20.104940
3740 00:56:20.105016
3741 00:56:20.108346 [Calibration Summary] 2400 Mbps
3742 00:56:20.108424 CH 0, Rank 0
3743 00:56:20.111424 SW Impedance : PASS
3744 00:56:20.111501 DUTY Scan : NO K
3745 00:56:20.114809 ZQ Calibration : PASS
3746 00:56:20.118001 Jitter Meter : NO K
3747 00:56:20.118096 CBT Training : PASS
3748 00:56:20.121469 Write leveling : PASS
3749 00:56:20.124858 RX DQS gating : PASS
3750 00:56:20.124935 RX DQ/DQS(RDDQC) : PASS
3751 00:56:20.128012 TX DQ/DQS : PASS
3752 00:56:20.128089 RX DATLAT : PASS
3753 00:56:20.131530 RX DQ/DQS(Engine): PASS
3754 00:56:20.135112 TX OE : NO K
3755 00:56:20.135190 All Pass.
3756 00:56:20.135266
3757 00:56:20.135356 CH 0, Rank 1
3758 00:56:20.138329 SW Impedance : PASS
3759 00:56:20.141553 DUTY Scan : NO K
3760 00:56:20.141644 ZQ Calibration : PASS
3761 00:56:20.145108 Jitter Meter : NO K
3762 00:56:20.148665 CBT Training : PASS
3763 00:56:20.148803 Write leveling : PASS
3764 00:56:20.151783 RX DQS gating : PASS
3765 00:56:20.155167 RX DQ/DQS(RDDQC) : PASS
3766 00:56:20.155244 TX DQ/DQS : PASS
3767 00:56:20.158549 RX DATLAT : PASS
3768 00:56:20.161495 RX DQ/DQS(Engine): PASS
3769 00:56:20.161564 TX OE : NO K
3770 00:56:20.161625 All Pass.
3771 00:56:20.161678
3772 00:56:20.165105 CH 1, Rank 0
3773 00:56:20.165173 SW Impedance : PASS
3774 00:56:20.168435 DUTY Scan : NO K
3775 00:56:20.171739 ZQ Calibration : PASS
3776 00:56:20.171807 Jitter Meter : NO K
3777 00:56:20.175298 CBT Training : PASS
3778 00:56:20.178450 Write leveling : PASS
3779 00:56:20.178560 RX DQS gating : PASS
3780 00:56:20.181581 RX DQ/DQS(RDDQC) : PASS
3781 00:56:20.184853 TX DQ/DQS : PASS
3782 00:56:20.184926 RX DATLAT : PASS
3783 00:56:20.188380 RX DQ/DQS(Engine): PASS
3784 00:56:20.192088 TX OE : NO K
3785 00:56:20.192159 All Pass.
3786 00:56:20.192231
3787 00:56:20.192301 CH 1, Rank 1
3788 00:56:20.195485 SW Impedance : PASS
3789 00:56:20.198254 DUTY Scan : NO K
3790 00:56:20.198333 ZQ Calibration : PASS
3791 00:56:20.201752 Jitter Meter : NO K
3792 00:56:20.205272 CBT Training : PASS
3793 00:56:20.205349 Write leveling : PASS
3794 00:56:20.208265 RX DQS gating : PASS
3795 00:56:20.208343 RX DQ/DQS(RDDQC) : PASS
3796 00:56:20.212044 TX DQ/DQS : PASS
3797 00:56:20.215444 RX DATLAT : PASS
3798 00:56:20.215522 RX DQ/DQS(Engine): PASS
3799 00:56:20.218110 TX OE : NO K
3800 00:56:20.218202 All Pass.
3801 00:56:20.218278
3802 00:56:20.221481 DramC Write-DBI off
3803 00:56:20.224779 PER_BANK_REFRESH: Hybrid Mode
3804 00:56:20.224875 TX_TRACKING: ON
3805 00:56:20.234952 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3806 00:56:20.238306 [FAST_K] Save calibration result to emmc
3807 00:56:20.241755 dramc_set_vcore_voltage set vcore to 650000
3808 00:56:20.244946 Read voltage for 600, 5
3809 00:56:20.245023 Vio18 = 0
3810 00:56:20.245116 Vcore = 650000
3811 00:56:20.248810 Vdram = 0
3812 00:56:20.248899 Vddq = 0
3813 00:56:20.248969 Vmddr = 0
3814 00:56:20.254904 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3815 00:56:20.258547 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3816 00:56:20.261569 MEM_TYPE=3, freq_sel=19
3817 00:56:20.264815 sv_algorithm_assistance_LP4_1600
3818 00:56:20.268340 ============ PULL DRAM RESETB DOWN ============
3819 00:56:20.271811 ========== PULL DRAM RESETB DOWN end =========
3820 00:56:20.278634 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3821 00:56:20.281908 ===================================
3822 00:56:20.284777 LPDDR4 DRAM CONFIGURATION
3823 00:56:20.284851 ===================================
3824 00:56:20.288468 EX_ROW_EN[0] = 0x0
3825 00:56:20.291606 EX_ROW_EN[1] = 0x0
3826 00:56:20.291677 LP4Y_EN = 0x0
3827 00:56:20.295230 WORK_FSP = 0x0
3828 00:56:20.295298 WL = 0x2
3829 00:56:20.298131 RL = 0x2
3830 00:56:20.298195 BL = 0x2
3831 00:56:20.302069 RPST = 0x0
3832 00:56:20.302138 RD_PRE = 0x0
3833 00:56:20.304937 WR_PRE = 0x1
3834 00:56:20.305004 WR_PST = 0x0
3835 00:56:20.308342 DBI_WR = 0x0
3836 00:56:20.308409 DBI_RD = 0x0
3837 00:56:20.311696 OTF = 0x1
3838 00:56:20.315047 ===================================
3839 00:56:20.318305 ===================================
3840 00:56:20.318376 ANA top config
3841 00:56:20.321661 ===================================
3842 00:56:20.325074 DLL_ASYNC_EN = 0
3843 00:56:20.328228 ALL_SLAVE_EN = 1
3844 00:56:20.331799 NEW_RANK_MODE = 1
3845 00:56:20.331875 DLL_IDLE_MODE = 1
3846 00:56:20.335288 LP45_APHY_COMB_EN = 1
3847 00:56:20.338575 TX_ODT_DIS = 1
3848 00:56:20.341618 NEW_8X_MODE = 1
3849 00:56:20.344900 ===================================
3850 00:56:20.348152 ===================================
3851 00:56:20.351529 data_rate = 1200
3852 00:56:20.351607 CKR = 1
3853 00:56:20.354981 DQ_P2S_RATIO = 8
3854 00:56:20.358569 ===================================
3855 00:56:20.361812 CA_P2S_RATIO = 8
3856 00:56:20.364949 DQ_CA_OPEN = 0
3857 00:56:20.368327 DQ_SEMI_OPEN = 0
3858 00:56:20.368401 CA_SEMI_OPEN = 0
3859 00:56:20.371978 CA_FULL_RATE = 0
3860 00:56:20.375477 DQ_CKDIV4_EN = 1
3861 00:56:20.378821 CA_CKDIV4_EN = 1
3862 00:56:20.382178 CA_PREDIV_EN = 0
3863 00:56:20.385011 PH8_DLY = 0
3864 00:56:20.385086 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3865 00:56:20.388435 DQ_AAMCK_DIV = 4
3866 00:56:20.391732 CA_AAMCK_DIV = 4
3867 00:56:20.394970 CA_ADMCK_DIV = 4
3868 00:56:20.398619 DQ_TRACK_CA_EN = 0
3869 00:56:20.401769 CA_PICK = 600
3870 00:56:20.405213 CA_MCKIO = 600
3871 00:56:20.405288 MCKIO_SEMI = 0
3872 00:56:20.408589 PLL_FREQ = 2288
3873 00:56:20.411454 DQ_UI_PI_RATIO = 32
3874 00:56:20.414843 CA_UI_PI_RATIO = 0
3875 00:56:20.418335 ===================================
3876 00:56:20.421555 ===================================
3877 00:56:20.425411 memory_type:LPDDR4
3878 00:56:20.425487 GP_NUM : 10
3879 00:56:20.428289 SRAM_EN : 1
3880 00:56:20.428364 MD32_EN : 0
3881 00:56:20.431697 ===================================
3882 00:56:20.435059 [ANA_INIT] >>>>>>>>>>>>>>
3883 00:56:20.438615 <<<<<< [CONFIGURE PHASE]: ANA_TX
3884 00:56:20.442095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3885 00:56:20.445015 ===================================
3886 00:56:20.448633 data_rate = 1200,PCW = 0X5800
3887 00:56:20.452073 ===================================
3888 00:56:20.455537 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3889 00:56:20.458559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3890 00:56:20.465330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3891 00:56:20.468769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3892 00:56:20.475296 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3893 00:56:20.478386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3894 00:56:20.478462 [ANA_INIT] flow start
3895 00:56:20.481959 [ANA_INIT] PLL >>>>>>>>
3896 00:56:20.485083 [ANA_INIT] PLL <<<<<<<<
3897 00:56:20.485157 [ANA_INIT] MIDPI >>>>>>>>
3898 00:56:20.488403 [ANA_INIT] MIDPI <<<<<<<<
3899 00:56:20.492039 [ANA_INIT] DLL >>>>>>>>
3900 00:56:20.492114 [ANA_INIT] flow end
3901 00:56:20.495403 ============ LP4 DIFF to SE enter ============
3902 00:56:20.501902 ============ LP4 DIFF to SE exit ============
3903 00:56:20.501978 [ANA_INIT] <<<<<<<<<<<<<
3904 00:56:20.505077 [Flow] Enable top DCM control >>>>>
3905 00:56:20.508748 [Flow] Enable top DCM control <<<<<
3906 00:56:20.511905 Enable DLL master slave shuffle
3907 00:56:20.518701 ==============================================================
3908 00:56:20.518777 Gating Mode config
3909 00:56:20.525467 ==============================================================
3910 00:56:20.528651 Config description:
3911 00:56:20.538265 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3912 00:56:20.545086 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3913 00:56:20.548478 SELPH_MODE 0: By rank 1: By Phase
3914 00:56:20.555379 ==============================================================
3915 00:56:20.558813 GAT_TRACK_EN = 1
3916 00:56:20.558956 RX_GATING_MODE = 2
3917 00:56:20.561928 RX_GATING_TRACK_MODE = 2
3918 00:56:20.565170 SELPH_MODE = 1
3919 00:56:20.568803 PICG_EARLY_EN = 1
3920 00:56:20.571818 VALID_LAT_VALUE = 1
3921 00:56:20.578337 ==============================================================
3922 00:56:20.582023 Enter into Gating configuration >>>>
3923 00:56:20.585422 Exit from Gating configuration <<<<
3924 00:56:20.588545 Enter into DVFS_PRE_config >>>>>
3925 00:56:20.598563 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3926 00:56:20.602210 Exit from DVFS_PRE_config <<<<<
3927 00:56:20.605494 Enter into PICG configuration >>>>
3928 00:56:20.608900 Exit from PICG configuration <<<<
3929 00:56:20.612192 [RX_INPUT] configuration >>>>>
3930 00:56:20.612267 [RX_INPUT] configuration <<<<<
3931 00:56:20.618925 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3932 00:56:20.625202 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3933 00:56:20.628693 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3934 00:56:20.635301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3935 00:56:20.641884 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3936 00:56:20.648690 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3937 00:56:20.652063 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3938 00:56:20.655502 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3939 00:56:20.662257 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3940 00:56:20.665809 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3941 00:56:20.668589 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3942 00:56:20.672074 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3943 00:56:20.675499 ===================================
3944 00:56:20.678908 LPDDR4 DRAM CONFIGURATION
3945 00:56:20.681961 ===================================
3946 00:56:20.685478 EX_ROW_EN[0] = 0x0
3947 00:56:20.685554 EX_ROW_EN[1] = 0x0
3948 00:56:20.689131 LP4Y_EN = 0x0
3949 00:56:20.689205 WORK_FSP = 0x0
3950 00:56:20.692009 WL = 0x2
3951 00:56:20.692084 RL = 0x2
3952 00:56:20.695571 BL = 0x2
3953 00:56:20.695646 RPST = 0x0
3954 00:56:20.698625 RD_PRE = 0x0
3955 00:56:20.698700 WR_PRE = 0x1
3956 00:56:20.702441 WR_PST = 0x0
3957 00:56:20.702517 DBI_WR = 0x0
3958 00:56:20.705771 DBI_RD = 0x0
3959 00:56:20.705845 OTF = 0x1
3960 00:56:20.709163 ===================================
3961 00:56:20.716089 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3962 00:56:20.718718 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3963 00:56:20.722080 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3964 00:56:20.725427 ===================================
3965 00:56:20.729249 LPDDR4 DRAM CONFIGURATION
3966 00:56:20.732597 ===================================
3967 00:56:20.732667 EX_ROW_EN[0] = 0x10
3968 00:56:20.735417 EX_ROW_EN[1] = 0x0
3969 00:56:20.738838 LP4Y_EN = 0x0
3970 00:56:20.738907 WORK_FSP = 0x0
3971 00:56:20.742483 WL = 0x2
3972 00:56:20.742556 RL = 0x2
3973 00:56:20.745262 BL = 0x2
3974 00:56:20.745325 RPST = 0x0
3975 00:56:20.748757 RD_PRE = 0x0
3976 00:56:20.748822 WR_PRE = 0x1
3977 00:56:20.752324 WR_PST = 0x0
3978 00:56:20.752392 DBI_WR = 0x0
3979 00:56:20.755711 DBI_RD = 0x0
3980 00:56:20.755779 OTF = 0x1
3981 00:56:20.759076 ===================================
3982 00:56:20.765589 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3983 00:56:20.770056 nWR fixed to 30
3984 00:56:20.773492 [ModeRegInit_LP4] CH0 RK0
3985 00:56:20.773567 [ModeRegInit_LP4] CH0 RK1
3986 00:56:20.776915 [ModeRegInit_LP4] CH1 RK0
3987 00:56:20.779726 [ModeRegInit_LP4] CH1 RK1
3988 00:56:20.779801 match AC timing 17
3989 00:56:20.786641 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3990 00:56:20.790124 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3991 00:56:20.793122 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3992 00:56:20.799894 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3993 00:56:20.803381 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3994 00:56:20.803455 ==
3995 00:56:20.806690 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 00:56:20.810294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 00:56:20.810369 ==
3998 00:56:20.816515 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3999 00:56:20.823715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4000 00:56:20.826779 [CA 0] Center 36 (6~66) winsize 61
4001 00:56:20.830523 [CA 1] Center 36 (6~66) winsize 61
4002 00:56:20.833601 [CA 2] Center 34 (4~65) winsize 62
4003 00:56:20.836888 [CA 3] Center 34 (4~64) winsize 61
4004 00:56:20.840088 [CA 4] Center 34 (4~64) winsize 61
4005 00:56:20.843488 [CA 5] Center 33 (3~64) winsize 62
4006 00:56:20.843563
4007 00:56:20.846905 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4008 00:56:20.846979
4009 00:56:20.850413 [CATrainingPosCal] consider 1 rank data
4010 00:56:20.853394 u2DelayCellTimex100 = 270/100 ps
4011 00:56:20.856910 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4012 00:56:20.860350 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4013 00:56:20.863762 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4014 00:56:20.867371 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4015 00:56:20.870671 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4016 00:56:20.873575 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4017 00:56:20.873650
4018 00:56:20.877108 CA PerBit enable=1, Macro0, CA PI delay=33
4019 00:56:20.880499
4020 00:56:20.880573 [CBTSetCACLKResult] CA Dly = 33
4021 00:56:20.883416 CS Dly: 6 (0~37)
4022 00:56:20.883490 ==
4023 00:56:20.886755 Dram Type= 6, Freq= 0, CH_0, rank 1
4024 00:56:20.890402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 00:56:20.890478 ==
4026 00:56:20.897112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4027 00:56:20.903863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4028 00:56:20.907153 [CA 0] Center 36 (6~67) winsize 62
4029 00:56:20.910642 [CA 1] Center 35 (5~66) winsize 62
4030 00:56:20.913541 [CA 2] Center 34 (4~65) winsize 62
4031 00:56:20.917182 [CA 3] Center 34 (4~65) winsize 62
4032 00:56:20.920192 [CA 4] Center 33 (3~64) winsize 62
4033 00:56:20.923768 [CA 5] Center 33 (3~64) winsize 62
4034 00:56:20.923859
4035 00:56:20.927198 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4036 00:56:20.927274
4037 00:56:20.930460 [CATrainingPosCal] consider 2 rank data
4038 00:56:20.933521 u2DelayCellTimex100 = 270/100 ps
4039 00:56:20.937165 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4040 00:56:20.940644 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4041 00:56:20.943572 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4042 00:56:20.946995 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4043 00:56:20.950231 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4044 00:56:20.953874 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4045 00:56:20.953949
4046 00:56:20.957389 CA PerBit enable=1, Macro0, CA PI delay=33
4047 00:56:20.960279
4048 00:56:20.960355 [CBTSetCACLKResult] CA Dly = 33
4049 00:56:20.963761 CS Dly: 6 (0~37)
4050 00:56:20.963938
4051 00:56:20.966884 ----->DramcWriteLeveling(PI) begin...
4052 00:56:20.966979 ==
4053 00:56:20.970410 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 00:56:20.973627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 00:56:20.973704 ==
4056 00:56:20.977090 Write leveling (Byte 0): 31 => 31
4057 00:56:20.980405 Write leveling (Byte 1): 29 => 29
4058 00:56:20.983867 DramcWriteLeveling(PI) end<-----
4059 00:56:20.983942
4060 00:56:20.984000 ==
4061 00:56:20.986823 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 00:56:20.990161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 00:56:20.990237 ==
4064 00:56:20.994036 [Gating] SW mode calibration
4065 00:56:21.000885 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4066 00:56:21.007269 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4067 00:56:21.010368 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4068 00:56:21.017317 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4069 00:56:21.020283 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4070 00:56:21.023576 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4071 00:56:21.027201 0 9 16 | B1->B0 | 2f2f 2e2e | 1 1 | (1 0) (1 0)
4072 00:56:21.033542 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 00:56:21.037260 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 00:56:21.040672 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 00:56:21.047350 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4076 00:56:21.050668 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4077 00:56:21.053582 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4078 00:56:21.060451 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4079 00:56:21.063771 0 10 16 | B1->B0 | 2e2e 4040 | 0 0 | (0 0) (1 1)
4080 00:56:21.067070 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 00:56:21.073780 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 00:56:21.077139 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 00:56:21.080407 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 00:56:21.087127 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 00:56:21.090493 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 00:56:21.094405 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 00:56:21.097612 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4088 00:56:21.103932 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 00:56:21.107351 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 00:56:21.110865 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 00:56:21.117419 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 00:56:21.121118 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 00:56:21.123950 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 00:56:21.130679 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 00:56:21.134137 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 00:56:21.137543 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 00:56:21.144294 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 00:56:21.147789 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 00:56:21.150753 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 00:56:21.157429 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 00:56:21.161181 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 00:56:21.164118 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 00:56:21.170983 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4104 00:56:21.171057 Total UI for P1: 0, mck2ui 16
4105 00:56:21.174339 best dqsien dly found for B0: ( 0, 13, 14)
4106 00:56:21.181111 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4107 00:56:21.184158 Total UI for P1: 0, mck2ui 16
4108 00:56:21.187488 best dqsien dly found for B1: ( 0, 13, 16)
4109 00:56:21.190874 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4110 00:56:21.194212 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4111 00:56:21.194290
4112 00:56:21.197770 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4113 00:56:21.200904 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4114 00:56:21.204502 [Gating] SW calibration Done
4115 00:56:21.204580 ==
4116 00:56:21.207987 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 00:56:21.210808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 00:56:21.210880 ==
4119 00:56:21.214545 RX Vref Scan: 0
4120 00:56:21.214637
4121 00:56:21.217326 RX Vref 0 -> 0, step: 1
4122 00:56:21.217404
4123 00:56:21.217484 RX Delay -230 -> 252, step: 16
4124 00:56:21.224112 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4125 00:56:21.227613 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4126 00:56:21.230817 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4127 00:56:21.234228 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4128 00:56:21.241286 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4129 00:56:21.244038 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4130 00:56:21.247318 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4131 00:56:21.251260 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4132 00:56:21.253945 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4133 00:56:21.260986 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4134 00:56:21.264355 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4135 00:56:21.267622 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4136 00:56:21.270850 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4137 00:56:21.277783 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4138 00:56:21.281003 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4139 00:56:21.284471 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4140 00:56:21.284549 ==
4141 00:56:21.287903 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 00:56:21.290684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 00:56:21.290762 ==
4144 00:56:21.294132 DQS Delay:
4145 00:56:21.294209 DQS0 = 0, DQS1 = 0
4146 00:56:21.297669 DQM Delay:
4147 00:56:21.297747 DQM0 = 43, DQM1 = 34
4148 00:56:21.297823 DQ Delay:
4149 00:56:21.301145 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4150 00:56:21.304448 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4151 00:56:21.307779 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4152 00:56:21.310779 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4153 00:56:21.310848
4154 00:56:21.310903
4155 00:56:21.314455 ==
4156 00:56:21.314523 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 00:56:21.320778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 00:56:21.320849 ==
4159 00:56:21.320906
4160 00:56:21.320958
4161 00:56:21.321007 TX Vref Scan disable
4162 00:56:21.324917 == TX Byte 0 ==
4163 00:56:21.328203 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4164 00:56:21.331937 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4165 00:56:21.335154 == TX Byte 1 ==
4166 00:56:21.338426 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4167 00:56:21.341872 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4168 00:56:21.344843 ==
4169 00:56:21.348590 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 00:56:21.351931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 00:56:21.351995 ==
4172 00:56:21.352049
4173 00:56:21.352100
4174 00:56:21.354731 TX Vref Scan disable
4175 00:56:21.354797 == TX Byte 0 ==
4176 00:56:21.361667 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4177 00:56:21.364897 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4178 00:56:21.364977 == TX Byte 1 ==
4179 00:56:21.371529 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4180 00:56:21.374837 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4181 00:56:21.374912
4182 00:56:21.374971 [DATLAT]
4183 00:56:21.378115 Freq=600, CH0 RK0
4184 00:56:21.378191
4185 00:56:21.378248 DATLAT Default: 0x9
4186 00:56:21.381716 0, 0xFFFF, sum = 0
4187 00:56:21.381792 1, 0xFFFF, sum = 0
4188 00:56:21.385000 2, 0xFFFF, sum = 0
4189 00:56:21.385076 3, 0xFFFF, sum = 0
4190 00:56:21.388603 4, 0xFFFF, sum = 0
4191 00:56:21.391806 5, 0xFFFF, sum = 0
4192 00:56:21.391883 6, 0xFFFF, sum = 0
4193 00:56:21.395248 7, 0xFFFF, sum = 0
4194 00:56:21.395324 8, 0x0, sum = 1
4195 00:56:21.395384 9, 0x0, sum = 2
4196 00:56:21.398251 10, 0x0, sum = 3
4197 00:56:21.398327 11, 0x0, sum = 4
4198 00:56:21.402117 best_step = 9
4199 00:56:21.402192
4200 00:56:21.402252 ==
4201 00:56:21.404933 Dram Type= 6, Freq= 0, CH_0, rank 0
4202 00:56:21.408332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 00:56:21.408409 ==
4204 00:56:21.411856 RX Vref Scan: 1
4205 00:56:21.411933
4206 00:56:21.412009 RX Vref 0 -> 0, step: 1
4207 00:56:21.412080
4208 00:56:21.415053 RX Delay -195 -> 252, step: 8
4209 00:56:21.415130
4210 00:56:21.418591 Set Vref, RX VrefLevel [Byte0]: 52
4211 00:56:21.421475 [Byte1]: 57
4212 00:56:21.425836
4213 00:56:21.425935 Final RX Vref Byte 0 = 52 to rank0
4214 00:56:21.428963 Final RX Vref Byte 1 = 57 to rank0
4215 00:56:21.432147 Final RX Vref Byte 0 = 52 to rank1
4216 00:56:21.435382 Final RX Vref Byte 1 = 57 to rank1==
4217 00:56:21.439042 Dram Type= 6, Freq= 0, CH_0, rank 0
4218 00:56:21.445768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 00:56:21.445846 ==
4220 00:56:21.445940 DQS Delay:
4221 00:56:21.446056 DQS0 = 0, DQS1 = 0
4222 00:56:21.448538 DQM Delay:
4223 00:56:21.448626 DQM0 = 42, DQM1 = 34
4224 00:56:21.452011 DQ Delay:
4225 00:56:21.455483 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4226 00:56:21.455560 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4227 00:56:21.458908 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4228 00:56:21.465863 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4229 00:56:21.465938
4230 00:56:21.466019
4231 00:56:21.472460 [DQSOSCAuto] RK0, (LSB)MR18= 0x4726, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4232 00:56:21.475736 CH0 RK0: MR19=808, MR18=4726
4233 00:56:21.482674 CH0_RK0: MR19=0x808, MR18=0x4726, DQSOSC=396, MR23=63, INC=167, DEC=111
4234 00:56:21.482772
4235 00:56:21.485383 ----->DramcWriteLeveling(PI) begin...
4236 00:56:21.485459 ==
4237 00:56:21.489190 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 00:56:21.492449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 00:56:21.492527 ==
4240 00:56:21.495652 Write leveling (Byte 0): 31 => 31
4241 00:56:21.499181 Write leveling (Byte 1): 30 => 30
4242 00:56:21.502690 DramcWriteLeveling(PI) end<-----
4243 00:56:21.502767
4244 00:56:21.502843 ==
4245 00:56:21.505476 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 00:56:21.508951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 00:56:21.509029 ==
4248 00:56:21.512416 [Gating] SW mode calibration
4249 00:56:21.519333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4250 00:56:21.525740 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4251 00:56:21.529123 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4252 00:56:21.532685 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4253 00:56:21.539357 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4254 00:56:21.542643 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
4255 00:56:21.545790 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4256 00:56:21.552369 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 00:56:21.555940 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 00:56:21.559138 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 00:56:21.565516 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 00:56:21.569563 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 00:56:21.572662 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4262 00:56:21.575800 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4263 00:56:21.582330 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4264 00:56:21.585845 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 00:56:21.589165 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 00:56:21.595920 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 00:56:21.599207 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 00:56:21.602323 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 00:56:21.609432 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 00:56:21.612487 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 00:56:21.615841 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4272 00:56:21.622759 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 00:56:21.625662 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 00:56:21.629224 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 00:56:21.635853 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 00:56:21.639145 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 00:56:21.642443 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 00:56:21.649397 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 00:56:21.652727 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 00:56:21.655812 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 00:56:21.662320 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 00:56:21.665746 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 00:56:21.669071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 00:56:21.672408 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 00:56:21.679173 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4286 00:56:21.682526 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4287 00:56:21.685866 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4288 00:56:21.689325 Total UI for P1: 0, mck2ui 16
4289 00:56:21.692638 best dqsien dly found for B0: ( 0, 13, 10)
4290 00:56:21.699445 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 00:56:21.699522 Total UI for P1: 0, mck2ui 16
4292 00:56:21.706191 best dqsien dly found for B1: ( 0, 13, 16)
4293 00:56:21.709670 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4294 00:56:21.712940 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4295 00:56:21.713016
4296 00:56:21.715967 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4297 00:56:21.719292 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4298 00:56:21.722724 [Gating] SW calibration Done
4299 00:56:21.722802 ==
4300 00:56:21.726193 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 00:56:21.729089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 00:56:21.729167 ==
4303 00:56:21.732459 RX Vref Scan: 0
4304 00:56:21.732536
4305 00:56:21.732614 RX Vref 0 -> 0, step: 1
4306 00:56:21.732685
4307 00:56:21.735912 RX Delay -230 -> 252, step: 16
4308 00:56:21.742480 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4309 00:56:21.745872 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4310 00:56:21.749014 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4311 00:56:21.752429 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4312 00:56:21.755895 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4313 00:56:21.763205 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4314 00:56:21.766070 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4315 00:56:21.769813 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4316 00:56:21.772859 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4317 00:56:21.776319 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4318 00:56:21.783006 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4319 00:56:21.786412 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4320 00:56:21.789852 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4321 00:56:21.792550 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4322 00:56:21.799491 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4323 00:56:21.802652 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4324 00:56:21.802727 ==
4325 00:56:21.806104 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 00:56:21.809363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 00:56:21.809438 ==
4328 00:56:21.812809 DQS Delay:
4329 00:56:21.812883 DQS0 = 0, DQS1 = 0
4330 00:56:21.812941 DQM Delay:
4331 00:56:21.816231 DQM0 = 40, DQM1 = 30
4332 00:56:21.816305 DQ Delay:
4333 00:56:21.819593 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4334 00:56:21.822683 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4335 00:56:21.826131 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4336 00:56:21.829515 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4337 00:56:21.829589
4338 00:56:21.829646
4339 00:56:21.829698 ==
4340 00:56:21.832536 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 00:56:21.839647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 00:56:21.839722 ==
4343 00:56:21.839781
4344 00:56:21.839833
4345 00:56:21.839883 TX Vref Scan disable
4346 00:56:21.843135 == TX Byte 0 ==
4347 00:56:21.846348 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4348 00:56:21.849907 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4349 00:56:21.852854 == TX Byte 1 ==
4350 00:56:21.856570 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4351 00:56:21.859811 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4352 00:56:21.863351 ==
4353 00:56:21.866551 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 00:56:21.869904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 00:56:21.870035 ==
4356 00:56:21.870094
4357 00:56:21.870147
4358 00:56:21.873263 TX Vref Scan disable
4359 00:56:21.873338 == TX Byte 0 ==
4360 00:56:21.879898 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4361 00:56:21.882957 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4362 00:56:21.883032 == TX Byte 1 ==
4363 00:56:21.889862 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4364 00:56:21.893064 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4365 00:56:21.893139
4366 00:56:21.893196 [DATLAT]
4367 00:56:21.896701 Freq=600, CH0 RK1
4368 00:56:21.896776
4369 00:56:21.896833 DATLAT Default: 0x9
4370 00:56:21.900070 0, 0xFFFF, sum = 0
4371 00:56:21.900146 1, 0xFFFF, sum = 0
4372 00:56:21.902969 2, 0xFFFF, sum = 0
4373 00:56:21.903044 3, 0xFFFF, sum = 0
4374 00:56:21.906272 4, 0xFFFF, sum = 0
4375 00:56:21.906348 5, 0xFFFF, sum = 0
4376 00:56:21.909890 6, 0xFFFF, sum = 0
4377 00:56:21.909968 7, 0xFFFF, sum = 0
4378 00:56:21.913216 8, 0x0, sum = 1
4379 00:56:21.913291 9, 0x0, sum = 2
4380 00:56:21.916496 10, 0x0, sum = 3
4381 00:56:21.916571 11, 0x0, sum = 4
4382 00:56:21.920042 best_step = 9
4383 00:56:21.920116
4384 00:56:21.920173 ==
4385 00:56:21.923309 Dram Type= 6, Freq= 0, CH_0, rank 1
4386 00:56:21.926664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 00:56:21.926739 ==
4388 00:56:21.929861 RX Vref Scan: 0
4389 00:56:21.929935
4390 00:56:21.930015 RX Vref 0 -> 0, step: 1
4391 00:56:21.930084
4392 00:56:21.933046 RX Delay -195 -> 252, step: 8
4393 00:56:21.939949 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4394 00:56:21.943445 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4395 00:56:21.946883 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4396 00:56:21.950461 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4397 00:56:21.956813 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4398 00:56:21.960158 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4399 00:56:21.963901 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4400 00:56:21.966713 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4401 00:56:21.969998 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4402 00:56:21.976835 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4403 00:56:21.979994 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4404 00:56:21.983437 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4405 00:56:21.986965 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4406 00:56:21.993465 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4407 00:56:21.996991 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4408 00:56:21.999983 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4409 00:56:22.000060 ==
4410 00:56:22.003570 Dram Type= 6, Freq= 0, CH_0, rank 1
4411 00:56:22.007010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 00:56:22.007088 ==
4413 00:56:22.010296 DQS Delay:
4414 00:56:22.010373 DQS0 = 0, DQS1 = 0
4415 00:56:22.013527 DQM Delay:
4416 00:56:22.013604 DQM0 = 39, DQM1 = 33
4417 00:56:22.013680 DQ Delay:
4418 00:56:22.017155 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4419 00:56:22.020192 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4420 00:56:22.023525 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4421 00:56:22.027110 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4422 00:56:22.027186
4423 00:56:22.027262
4424 00:56:22.036749 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
4425 00:56:22.040062 CH0 RK1: MR19=808, MR18=4B2D
4426 00:56:22.047000 CH0_RK1: MR19=0x808, MR18=0x4B2D, DQSOSC=395, MR23=63, INC=168, DEC=112
4427 00:56:22.047077 [RxdqsGatingPostProcess] freq 600
4428 00:56:22.053747 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4429 00:56:22.056573 Pre-setting of DQS Precalculation
4430 00:56:22.059962 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4431 00:56:22.060039 ==
4432 00:56:22.063302 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 00:56:22.070894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 00:56:22.070971 ==
4435 00:56:22.073497 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4436 00:56:22.080186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4437 00:56:22.083453 [CA 0] Center 35 (5~65) winsize 61
4438 00:56:22.086878 [CA 1] Center 35 (5~66) winsize 62
4439 00:56:22.090316 [CA 2] Center 33 (3~64) winsize 62
4440 00:56:22.093706 [CA 3] Center 33 (3~64) winsize 62
4441 00:56:22.097164 [CA 4] Center 34 (3~65) winsize 63
4442 00:56:22.100623 [CA 5] Center 33 (3~64) winsize 62
4443 00:56:22.100701
4444 00:56:22.103728 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4445 00:56:22.103806
4446 00:56:22.106860 [CATrainingPosCal] consider 1 rank data
4447 00:56:22.110325 u2DelayCellTimex100 = 270/100 ps
4448 00:56:22.113546 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4449 00:56:22.116789 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4450 00:56:22.123971 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4451 00:56:22.127391 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4452 00:56:22.130845 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4453 00:56:22.133656 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4454 00:56:22.133733
4455 00:56:22.137138 CA PerBit enable=1, Macro0, CA PI delay=33
4456 00:56:22.137216
4457 00:56:22.140541 [CBTSetCACLKResult] CA Dly = 33
4458 00:56:22.140619 CS Dly: 4 (0~35)
4459 00:56:22.140695 ==
4460 00:56:22.143651 Dram Type= 6, Freq= 0, CH_1, rank 1
4461 00:56:22.150391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 00:56:22.150468 ==
4463 00:56:22.153894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4464 00:56:22.160235 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4465 00:56:22.163813 [CA 0] Center 35 (5~66) winsize 62
4466 00:56:22.167120 [CA 1] Center 35 (5~66) winsize 62
4467 00:56:22.170348 [CA 2] Center 34 (4~65) winsize 62
4468 00:56:22.173572 [CA 3] Center 34 (4~64) winsize 61
4469 00:56:22.177258 [CA 4] Center 34 (4~65) winsize 62
4470 00:56:22.180785 [CA 5] Center 33 (3~64) winsize 62
4471 00:56:22.180862
4472 00:56:22.183934 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4473 00:56:22.184011
4474 00:56:22.187150 [CATrainingPosCal] consider 2 rank data
4475 00:56:22.190406 u2DelayCellTimex100 = 270/100 ps
4476 00:56:22.193907 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4477 00:56:22.197485 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4478 00:56:22.203939 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4479 00:56:22.207322 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4480 00:56:22.210788 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4481 00:56:22.214103 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4482 00:56:22.214180
4483 00:56:22.217255 CA PerBit enable=1, Macro0, CA PI delay=33
4484 00:56:22.217332
4485 00:56:22.220394 [CBTSetCACLKResult] CA Dly = 33
4486 00:56:22.220471 CS Dly: 5 (0~37)
4487 00:56:22.220548
4488 00:56:22.223785 ----->DramcWriteLeveling(PI) begin...
4489 00:56:22.223865 ==
4490 00:56:22.227213 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 00:56:22.233579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 00:56:22.233661 ==
4493 00:56:22.236976 Write leveling (Byte 0): 28 => 28
4494 00:56:22.240423 Write leveling (Byte 1): 31 => 31
4495 00:56:22.240498 DramcWriteLeveling(PI) end<-----
4496 00:56:22.243774
4497 00:56:22.243848 ==
4498 00:56:22.247227 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 00:56:22.250313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 00:56:22.250380 ==
4501 00:56:22.253511 [Gating] SW mode calibration
4502 00:56:22.260462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4503 00:56:22.263866 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4504 00:56:22.270167 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4505 00:56:22.273473 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4506 00:56:22.276920 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4507 00:56:22.283883 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4508 00:56:22.286974 0 9 16 | B1->B0 | 2929 2929 | 1 0 | (1 0) (0 0)
4509 00:56:22.290171 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 00:56:22.296990 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 00:56:22.300750 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4512 00:56:22.303667 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4513 00:56:22.310508 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4514 00:56:22.313394 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4515 00:56:22.316765 0 10 12 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
4516 00:56:22.323518 0 10 16 | B1->B0 | 3a3a 3c3c | 0 0 | (0 0) (0 0)
4517 00:56:22.327094 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 00:56:22.330236 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 00:56:22.337176 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 00:56:22.340386 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 00:56:22.343351 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 00:56:22.347181 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 00:56:22.353382 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 00:56:22.357101 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4525 00:56:22.360252 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 00:56:22.367119 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 00:56:22.370532 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 00:56:22.373313 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 00:56:22.380126 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 00:56:22.383455 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 00:56:22.386921 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 00:56:22.393869 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 00:56:22.397009 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 00:56:22.400341 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 00:56:22.407001 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 00:56:22.410375 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 00:56:22.413673 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 00:56:22.420604 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 00:56:22.424013 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4540 00:56:22.426974 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4541 00:56:22.430791 Total UI for P1: 0, mck2ui 16
4542 00:56:22.434098 best dqsien dly found for B0: ( 0, 13, 14)
4543 00:56:22.437396 Total UI for P1: 0, mck2ui 16
4544 00:56:22.440273 best dqsien dly found for B1: ( 0, 13, 12)
4545 00:56:22.443684 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4546 00:56:22.447091 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4547 00:56:22.447167
4548 00:56:22.450251 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4549 00:56:22.457142 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4550 00:56:22.457218 [Gating] SW calibration Done
4551 00:56:22.457277 ==
4552 00:56:22.460657 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 00:56:22.467005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 00:56:22.467082 ==
4555 00:56:22.467141 RX Vref Scan: 0
4556 00:56:22.467196
4557 00:56:22.470568 RX Vref 0 -> 0, step: 1
4558 00:56:22.470644
4559 00:56:22.473978 RX Delay -230 -> 252, step: 16
4560 00:56:22.477248 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4561 00:56:22.480498 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4562 00:56:22.483629 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4563 00:56:22.490520 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4564 00:56:22.494186 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4565 00:56:22.496874 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4566 00:56:22.500359 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4567 00:56:22.507161 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4568 00:56:22.510676 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4569 00:56:22.514228 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4570 00:56:22.517274 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4571 00:56:22.520673 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4572 00:56:22.527285 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4573 00:56:22.530923 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4574 00:56:22.533609 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4575 00:56:22.537582 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4576 00:56:22.537659 ==
4577 00:56:22.541316 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 00:56:22.547286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 00:56:22.547363 ==
4580 00:56:22.547422 DQS Delay:
4581 00:56:22.550813 DQS0 = 0, DQS1 = 0
4582 00:56:22.550889 DQM Delay:
4583 00:56:22.550948 DQM0 = 42, DQM1 = 35
4584 00:56:22.554020 DQ Delay:
4585 00:56:22.557407 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4586 00:56:22.560306 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4587 00:56:22.563780 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4588 00:56:22.567135 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4589 00:56:22.567211
4590 00:56:22.567270
4591 00:56:22.567323 ==
4592 00:56:22.570434 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 00:56:22.573601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 00:56:22.573677 ==
4595 00:56:22.573736
4596 00:56:22.573790
4597 00:56:22.577192 TX Vref Scan disable
4598 00:56:22.580756 == TX Byte 0 ==
4599 00:56:22.584180 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4600 00:56:22.586983 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4601 00:56:22.587059 == TX Byte 1 ==
4602 00:56:22.593638 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4603 00:56:22.597027 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4604 00:56:22.597102 ==
4605 00:56:22.600513 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 00:56:22.604079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 00:56:22.604156 ==
4608 00:56:22.604215
4609 00:56:22.604268
4610 00:56:22.607733 TX Vref Scan disable
4611 00:56:22.610879 == TX Byte 0 ==
4612 00:56:22.614374 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4613 00:56:22.620556 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4614 00:56:22.620632 == TX Byte 1 ==
4615 00:56:22.624083 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4616 00:56:22.630906 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4617 00:56:22.630982
4618 00:56:22.631040 [DATLAT]
4619 00:56:22.631094 Freq=600, CH1 RK0
4620 00:56:22.631146
4621 00:56:22.633934 DATLAT Default: 0x9
4622 00:56:22.634050 0, 0xFFFF, sum = 0
4623 00:56:22.637152 1, 0xFFFF, sum = 0
4624 00:56:22.637258 2, 0xFFFF, sum = 0
4625 00:56:22.641109 3, 0xFFFF, sum = 0
4626 00:56:22.643735 4, 0xFFFF, sum = 0
4627 00:56:22.643812 5, 0xFFFF, sum = 0
4628 00:56:22.647253 6, 0xFFFF, sum = 0
4629 00:56:22.647336 7, 0xFFFF, sum = 0
4630 00:56:22.647413 8, 0x0, sum = 1
4631 00:56:22.650582 9, 0x0, sum = 2
4632 00:56:22.650658 10, 0x0, sum = 3
4633 00:56:22.654056 11, 0x0, sum = 4
4634 00:56:22.654134 best_step = 9
4635 00:56:22.654193
4636 00:56:22.654247 ==
4637 00:56:22.657119 Dram Type= 6, Freq= 0, CH_1, rank 0
4638 00:56:22.664046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 00:56:22.664124 ==
4640 00:56:22.664183 RX Vref Scan: 1
4641 00:56:22.664238
4642 00:56:22.667450 RX Vref 0 -> 0, step: 1
4643 00:56:22.667525
4644 00:56:22.670705 RX Delay -195 -> 252, step: 8
4645 00:56:22.670780
4646 00:56:22.674110 Set Vref, RX VrefLevel [Byte0]: 52
4647 00:56:22.677142 [Byte1]: 52
4648 00:56:22.677218
4649 00:56:22.680638 Final RX Vref Byte 0 = 52 to rank0
4650 00:56:22.684034 Final RX Vref Byte 1 = 52 to rank0
4651 00:56:22.687215 Final RX Vref Byte 0 = 52 to rank1
4652 00:56:22.690359 Final RX Vref Byte 1 = 52 to rank1==
4653 00:56:22.693988 Dram Type= 6, Freq= 0, CH_1, rank 0
4654 00:56:22.697273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 00:56:22.697349 ==
4656 00:56:22.700317 DQS Delay:
4657 00:56:22.700393 DQS0 = 0, DQS1 = 0
4658 00:56:22.700452 DQM Delay:
4659 00:56:22.704004 DQM0 = 41, DQM1 = 33
4660 00:56:22.704079 DQ Delay:
4661 00:56:22.707433 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4662 00:56:22.710281 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4663 00:56:22.713750 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4664 00:56:22.717327 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4665 00:56:22.717402
4666 00:56:22.717461
4667 00:56:22.727049 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
4668 00:56:22.730514 CH1 RK0: MR19=808, MR18=4C12
4669 00:56:22.733897 CH1_RK0: MR19=0x808, MR18=0x4C12, DQSOSC=395, MR23=63, INC=168, DEC=112
4670 00:56:22.733973
4671 00:56:22.737420 ----->DramcWriteLeveling(PI) begin...
4672 00:56:22.740611 ==
4673 00:56:22.740687 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 00:56:22.747490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 00:56:22.747565 ==
4676 00:56:22.750342 Write leveling (Byte 0): 28 => 28
4677 00:56:22.754016 Write leveling (Byte 1): 33 => 33
4678 00:56:22.757335 DramcWriteLeveling(PI) end<-----
4679 00:56:22.757410
4680 00:56:22.757468 ==
4681 00:56:22.760687 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 00:56:22.763766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 00:56:22.763841 ==
4684 00:56:22.767343 [Gating] SW mode calibration
4685 00:56:22.773866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4686 00:56:22.777229 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4687 00:56:22.783980 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4688 00:56:22.787416 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4689 00:56:22.790740 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4690 00:56:22.797605 0 9 12 | B1->B0 | 3030 2929 | 1 0 | (1 1) (1 0)
4691 00:56:22.800767 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4692 00:56:22.804029 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 00:56:22.811013 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 00:56:22.814509 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4695 00:56:22.817886 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 00:56:22.824045 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4697 00:56:22.827405 0 10 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
4698 00:56:22.830828 0 10 12 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (1 1)
4699 00:56:22.834126 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4700 00:56:22.840947 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 00:56:22.844284 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 00:56:22.847226 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 00:56:22.854238 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 00:56:22.857637 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 00:56:22.861015 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 00:56:22.867730 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4707 00:56:22.871262 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 00:56:22.874199 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 00:56:22.880815 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 00:56:22.884129 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 00:56:22.887544 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 00:56:22.894118 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 00:56:22.897731 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 00:56:22.900719 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 00:56:22.907649 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 00:56:22.910890 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 00:56:22.913990 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 00:56:22.920890 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 00:56:22.924194 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 00:56:22.927515 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 00:56:22.931033 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 00:56:22.937366 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4723 00:56:22.940830 Total UI for P1: 0, mck2ui 16
4724 00:56:22.944267 best dqsien dly found for B0: ( 0, 13, 10)
4725 00:56:22.947486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4726 00:56:22.950930 Total UI for P1: 0, mck2ui 16
4727 00:56:22.954362 best dqsien dly found for B1: ( 0, 13, 14)
4728 00:56:22.957292 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4729 00:56:22.960775 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4730 00:56:22.960852
4731 00:56:22.964181 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4732 00:56:22.967344 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4733 00:56:22.971191 [Gating] SW calibration Done
4734 00:56:22.971268 ==
4735 00:56:22.974164 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 00:56:22.981119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 00:56:22.981196 ==
4738 00:56:22.981273 RX Vref Scan: 0
4739 00:56:22.981344
4740 00:56:22.983956 RX Vref 0 -> 0, step: 1
4741 00:56:22.984034
4742 00:56:22.987595 RX Delay -230 -> 252, step: 16
4743 00:56:22.991169 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4744 00:56:22.993961 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4745 00:56:22.997817 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4746 00:56:23.004163 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4747 00:56:23.007666 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4748 00:56:23.010795 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4749 00:56:23.014501 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4750 00:56:23.017588 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4751 00:56:23.024369 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4752 00:56:23.027489 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4753 00:56:23.030914 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4754 00:56:23.034426 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4755 00:56:23.041242 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4756 00:56:23.044574 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4757 00:56:23.047484 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4758 00:56:23.050961 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4759 00:56:23.051036 ==
4760 00:56:23.054590 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 00:56:23.061271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 00:56:23.061350 ==
4763 00:56:23.061415 DQS Delay:
4764 00:56:23.061488 DQS0 = 0, DQS1 = 0
4765 00:56:23.064304 DQM Delay:
4766 00:56:23.064381 DQM0 = 39, DQM1 = 37
4767 00:56:23.067604 DQ Delay:
4768 00:56:23.070995 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4769 00:56:23.071072 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4770 00:56:23.074487 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4771 00:56:23.077826 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4772 00:56:23.080859
4773 00:56:23.080935
4774 00:56:23.081011 ==
4775 00:56:23.084142 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 00:56:23.087692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 00:56:23.087768 ==
4778 00:56:23.087826
4779 00:56:23.087879
4780 00:56:23.091072 TX Vref Scan disable
4781 00:56:23.091162 == TX Byte 0 ==
4782 00:56:23.098014 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4783 00:56:23.100995 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4784 00:56:23.101072 == TX Byte 1 ==
4785 00:56:23.108135 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4786 00:56:23.111275 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4787 00:56:23.111351 ==
4788 00:56:23.114327 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 00:56:23.117902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 00:56:23.117978 ==
4791 00:56:23.118081
4792 00:56:23.118136
4793 00:56:23.120934 TX Vref Scan disable
4794 00:56:23.124052 == TX Byte 0 ==
4795 00:56:23.127682 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4796 00:56:23.130896 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4797 00:56:23.134126 == TX Byte 1 ==
4798 00:56:23.137668 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4799 00:56:23.140882 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4800 00:56:23.144401
4801 00:56:23.144476 [DATLAT]
4802 00:56:23.144535 Freq=600, CH1 RK1
4803 00:56:23.144589
4804 00:56:23.147989 DATLAT Default: 0x9
4805 00:56:23.148065 0, 0xFFFF, sum = 0
4806 00:56:23.151322 1, 0xFFFF, sum = 0
4807 00:56:23.151399 2, 0xFFFF, sum = 0
4808 00:56:23.154099 3, 0xFFFF, sum = 0
4809 00:56:23.154176 4, 0xFFFF, sum = 0
4810 00:56:23.157509 5, 0xFFFF, sum = 0
4811 00:56:23.157587 6, 0xFFFF, sum = 0
4812 00:56:23.160998 7, 0xFFFF, sum = 0
4813 00:56:23.161074 8, 0x0, sum = 1
4814 00:56:23.164304 9, 0x0, sum = 2
4815 00:56:23.164381 10, 0x0, sum = 3
4816 00:56:23.167832 11, 0x0, sum = 4
4817 00:56:23.167910 best_step = 9
4818 00:56:23.167970
4819 00:56:23.168024 ==
4820 00:56:23.171087 Dram Type= 6, Freq= 0, CH_1, rank 1
4821 00:56:23.177969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4822 00:56:23.178086 ==
4823 00:56:23.178146 RX Vref Scan: 0
4824 00:56:23.178201
4825 00:56:23.180711 RX Vref 0 -> 0, step: 1
4826 00:56:23.180787
4827 00:56:23.184211 RX Delay -179 -> 252, step: 8
4828 00:56:23.187243 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4829 00:56:23.194271 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4830 00:56:23.197768 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4831 00:56:23.201204 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4832 00:56:23.204730 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4833 00:56:23.207879 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4834 00:56:23.214386 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4835 00:56:23.217501 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4836 00:56:23.221406 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4837 00:56:23.224612 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4838 00:56:23.227426 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4839 00:56:23.234407 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4840 00:56:23.238110 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4841 00:56:23.241370 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4842 00:56:23.244685 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4843 00:56:23.251348 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4844 00:56:23.251418 ==
4845 00:56:23.254866 Dram Type= 6, Freq= 0, CH_1, rank 1
4846 00:56:23.257956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4847 00:56:23.258062 ==
4848 00:56:23.258135 DQS Delay:
4849 00:56:23.261409 DQS0 = 0, DQS1 = 0
4850 00:56:23.261486 DQM Delay:
4851 00:56:23.264986 DQM0 = 38, DQM1 = 33
4852 00:56:23.265062 DQ Delay:
4853 00:56:23.268147 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4854 00:56:23.271561 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4855 00:56:23.274994 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4856 00:56:23.277858 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4857 00:56:23.277935
4858 00:56:23.278054
4859 00:56:23.284605 [DQSOSCAuto] RK1, (LSB)MR18= 0x3946, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4860 00:56:23.287979 CH1 RK1: MR19=808, MR18=3946
4861 00:56:23.294801 CH1_RK1: MR19=0x808, MR18=0x3946, DQSOSC=396, MR23=63, INC=167, DEC=111
4862 00:56:23.297845 [RxdqsGatingPostProcess] freq 600
4863 00:56:23.304569 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4864 00:56:23.304654 Pre-setting of DQS Precalculation
4865 00:56:23.311569 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4866 00:56:23.318202 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4867 00:56:23.324901 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4868 00:56:23.324977
4869 00:56:23.325036
4870 00:56:23.328055 [Calibration Summary] 1200 Mbps
4871 00:56:23.331336 CH 0, Rank 0
4872 00:56:23.331412 SW Impedance : PASS
4873 00:56:23.334781 DUTY Scan : NO K
4874 00:56:23.334856 ZQ Calibration : PASS
4875 00:56:23.338172 Jitter Meter : NO K
4876 00:56:23.341591 CBT Training : PASS
4877 00:56:23.341667 Write leveling : PASS
4878 00:56:23.345007 RX DQS gating : PASS
4879 00:56:23.348032 RX DQ/DQS(RDDQC) : PASS
4880 00:56:23.348107 TX DQ/DQS : PASS
4881 00:56:23.351348 RX DATLAT : PASS
4882 00:56:23.354594 RX DQ/DQS(Engine): PASS
4883 00:56:23.354674 TX OE : NO K
4884 00:56:23.358232 All Pass.
4885 00:56:23.358307
4886 00:56:23.358364 CH 0, Rank 1
4887 00:56:23.361208 SW Impedance : PASS
4888 00:56:23.361282 DUTY Scan : NO K
4889 00:56:23.365098 ZQ Calibration : PASS
4890 00:56:23.368000 Jitter Meter : NO K
4891 00:56:23.368085 CBT Training : PASS
4892 00:56:23.371411 Write leveling : PASS
4893 00:56:23.374523 RX DQS gating : PASS
4894 00:56:23.374598 RX DQ/DQS(RDDQC) : PASS
4895 00:56:23.377776 TX DQ/DQS : PASS
4896 00:56:23.377851 RX DATLAT : PASS
4897 00:56:23.381220 RX DQ/DQS(Engine): PASS
4898 00:56:23.384667 TX OE : NO K
4899 00:56:23.384754 All Pass.
4900 00:56:23.384830
4901 00:56:23.384902 CH 1, Rank 0
4902 00:56:23.387952 SW Impedance : PASS
4903 00:56:23.391457 DUTY Scan : NO K
4904 00:56:23.391535 ZQ Calibration : PASS
4905 00:56:23.394801 Jitter Meter : NO K
4906 00:56:23.398344 CBT Training : PASS
4907 00:56:23.398421 Write leveling : PASS
4908 00:56:23.401224 RX DQS gating : PASS
4909 00:56:23.404899 RX DQ/DQS(RDDQC) : PASS
4910 00:56:23.404976 TX DQ/DQS : PASS
4911 00:56:23.408080 RX DATLAT : PASS
4912 00:56:23.411539 RX DQ/DQS(Engine): PASS
4913 00:56:23.411614 TX OE : NO K
4914 00:56:23.411672 All Pass.
4915 00:56:23.414849
4916 00:56:23.414925 CH 1, Rank 1
4917 00:56:23.415022 SW Impedance : PASS
4918 00:56:23.418326 DUTY Scan : NO K
4919 00:56:23.421850 ZQ Calibration : PASS
4920 00:56:23.421926 Jitter Meter : NO K
4921 00:56:23.425100 CBT Training : PASS
4922 00:56:23.428199 Write leveling : PASS
4923 00:56:23.428275 RX DQS gating : PASS
4924 00:56:23.432044 RX DQ/DQS(RDDQC) : PASS
4925 00:56:23.435175 TX DQ/DQS : PASS
4926 00:56:23.435251 RX DATLAT : PASS
4927 00:56:23.438463 RX DQ/DQS(Engine): PASS
4928 00:56:23.441602 TX OE : NO K
4929 00:56:23.441674 All Pass.
4930 00:56:23.441746
4931 00:56:23.441817 DramC Write-DBI off
4932 00:56:23.444987 PER_BANK_REFRESH: Hybrid Mode
4933 00:56:23.447968 TX_TRACKING: ON
4934 00:56:23.454894 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4935 00:56:23.458019 [FAST_K] Save calibration result to emmc
4936 00:56:23.464847 dramc_set_vcore_voltage set vcore to 662500
4937 00:56:23.464926 Read voltage for 933, 3
4938 00:56:23.467961 Vio18 = 0
4939 00:56:23.468060 Vcore = 662500
4940 00:56:23.468157 Vdram = 0
4941 00:56:23.468230 Vddq = 0
4942 00:56:23.471650 Vmddr = 0
4943 00:56:23.474961 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4944 00:56:23.481400 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4945 00:56:23.485037 MEM_TYPE=3, freq_sel=17
4946 00:56:23.485124 sv_algorithm_assistance_LP4_1600
4947 00:56:23.491498 ============ PULL DRAM RESETB DOWN ============
4948 00:56:23.494905 ========== PULL DRAM RESETB DOWN end =========
4949 00:56:23.498208 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4950 00:56:23.501724 ===================================
4951 00:56:23.504984 LPDDR4 DRAM CONFIGURATION
4952 00:56:23.508283 ===================================
4953 00:56:23.511481 EX_ROW_EN[0] = 0x0
4954 00:56:23.511571 EX_ROW_EN[1] = 0x0
4955 00:56:23.515041 LP4Y_EN = 0x0
4956 00:56:23.515132 WORK_FSP = 0x0
4957 00:56:23.518440 WL = 0x3
4958 00:56:23.518503 RL = 0x3
4959 00:56:23.521280 BL = 0x2
4960 00:56:23.521341 RPST = 0x0
4961 00:56:23.524769 RD_PRE = 0x0
4962 00:56:23.524832 WR_PRE = 0x1
4963 00:56:23.528192 WR_PST = 0x0
4964 00:56:23.528278 DBI_WR = 0x0
4965 00:56:23.531834 DBI_RD = 0x0
4966 00:56:23.531919 OTF = 0x1
4967 00:56:23.534901 ===================================
4968 00:56:23.538061 ===================================
4969 00:56:23.541356 ANA top config
4970 00:56:23.544628 ===================================
4971 00:56:23.548205 DLL_ASYNC_EN = 0
4972 00:56:23.548295 ALL_SLAVE_EN = 1
4973 00:56:23.551450 NEW_RANK_MODE = 1
4974 00:56:23.554878 DLL_IDLE_MODE = 1
4975 00:56:23.558364 LP45_APHY_COMB_EN = 1
4976 00:56:23.558453 TX_ODT_DIS = 1
4977 00:56:23.561821 NEW_8X_MODE = 1
4978 00:56:23.565030 ===================================
4979 00:56:23.568618 ===================================
4980 00:56:23.571768 data_rate = 1866
4981 00:56:23.575029 CKR = 1
4982 00:56:23.578633 DQ_P2S_RATIO = 8
4983 00:56:23.581328 ===================================
4984 00:56:23.581396 CA_P2S_RATIO = 8
4985 00:56:23.585327 DQ_CA_OPEN = 0
4986 00:56:23.588171 DQ_SEMI_OPEN = 0
4987 00:56:23.591604 CA_SEMI_OPEN = 0
4988 00:56:23.594821 CA_FULL_RATE = 0
4989 00:56:23.598405 DQ_CKDIV4_EN = 1
4990 00:56:23.598480 CA_CKDIV4_EN = 1
4991 00:56:23.601493 CA_PREDIV_EN = 0
4992 00:56:23.605348 PH8_DLY = 0
4993 00:56:23.608355 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4994 00:56:23.611725 DQ_AAMCK_DIV = 4
4995 00:56:23.614793 CA_AAMCK_DIV = 4
4996 00:56:23.614868 CA_ADMCK_DIV = 4
4997 00:56:23.618569 DQ_TRACK_CA_EN = 0
4998 00:56:23.621950 CA_PICK = 933
4999 00:56:23.625443 CA_MCKIO = 933
5000 00:56:23.628528 MCKIO_SEMI = 0
5001 00:56:23.631439 PLL_FREQ = 3732
5002 00:56:23.635098 DQ_UI_PI_RATIO = 32
5003 00:56:23.635173 CA_UI_PI_RATIO = 0
5004 00:56:23.638541 ===================================
5005 00:56:23.641752 ===================================
5006 00:56:23.644758 memory_type:LPDDR4
5007 00:56:23.648190 GP_NUM : 10
5008 00:56:23.648265 SRAM_EN : 1
5009 00:56:23.651646 MD32_EN : 0
5010 00:56:23.654948 ===================================
5011 00:56:23.658463 [ANA_INIT] >>>>>>>>>>>>>>
5012 00:56:23.661875 <<<<<< [CONFIGURE PHASE]: ANA_TX
5013 00:56:23.664886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5014 00:56:23.668139 ===================================
5015 00:56:23.668215 data_rate = 1866,PCW = 0X8f00
5016 00:56:23.671520 ===================================
5017 00:56:23.675093 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5018 00:56:23.681692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5019 00:56:23.688408 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5020 00:56:23.691332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5021 00:56:23.694626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5022 00:56:23.698386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5023 00:56:23.701561 [ANA_INIT] flow start
5024 00:56:23.701636 [ANA_INIT] PLL >>>>>>>>
5025 00:56:23.704853 [ANA_INIT] PLL <<<<<<<<
5026 00:56:23.708346 [ANA_INIT] MIDPI >>>>>>>>
5027 00:56:23.711756 [ANA_INIT] MIDPI <<<<<<<<
5028 00:56:23.711831 [ANA_INIT] DLL >>>>>>>>
5029 00:56:23.714970 [ANA_INIT] flow end
5030 00:56:23.718561 ============ LP4 DIFF to SE enter ============
5031 00:56:23.721367 ============ LP4 DIFF to SE exit ============
5032 00:56:23.724955 [ANA_INIT] <<<<<<<<<<<<<
5033 00:56:23.728048 [Flow] Enable top DCM control >>>>>
5034 00:56:23.731630 [Flow] Enable top DCM control <<<<<
5035 00:56:23.735158 Enable DLL master slave shuffle
5036 00:56:23.738239 ==============================================================
5037 00:56:23.741717 Gating Mode config
5038 00:56:23.748349 ==============================================================
5039 00:56:23.748424 Config description:
5040 00:56:23.758174 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5041 00:56:23.764627 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5042 00:56:23.771341 SELPH_MODE 0: By rank 1: By Phase
5043 00:56:23.774666 ==============================================================
5044 00:56:23.777868 GAT_TRACK_EN = 1
5045 00:56:23.781442 RX_GATING_MODE = 2
5046 00:56:23.784911 RX_GATING_TRACK_MODE = 2
5047 00:56:23.788342 SELPH_MODE = 1
5048 00:56:23.791301 PICG_EARLY_EN = 1
5049 00:56:23.794698 VALID_LAT_VALUE = 1
5050 00:56:23.798089 ==============================================================
5051 00:56:23.801453 Enter into Gating configuration >>>>
5052 00:56:23.804576 Exit from Gating configuration <<<<
5053 00:56:23.808071 Enter into DVFS_PRE_config >>>>>
5054 00:56:23.821368 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5055 00:56:23.824590 Exit from DVFS_PRE_config <<<<<
5056 00:56:23.824667 Enter into PICG configuration >>>>
5057 00:56:23.828056 Exit from PICG configuration <<<<
5058 00:56:23.831446 [RX_INPUT] configuration >>>>>
5059 00:56:23.834781 [RX_INPUT] configuration <<<<<
5060 00:56:23.841498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5061 00:56:23.844966 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5062 00:56:23.851580 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5063 00:56:23.858693 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5064 00:56:23.864831 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5065 00:56:23.871404 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5066 00:56:23.875021 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5067 00:56:23.878203 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5068 00:56:23.881409 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5069 00:56:23.887981 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5070 00:56:23.891536 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5071 00:56:23.895070 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5072 00:56:23.898399 ===================================
5073 00:56:23.901834 LPDDR4 DRAM CONFIGURATION
5074 00:56:23.905250 ===================================
5075 00:56:23.905327 EX_ROW_EN[0] = 0x0
5076 00:56:23.908570 EX_ROW_EN[1] = 0x0
5077 00:56:23.908649 LP4Y_EN = 0x0
5078 00:56:23.911841 WORK_FSP = 0x0
5079 00:56:23.914737 WL = 0x3
5080 00:56:23.914813 RL = 0x3
5081 00:56:23.918296 BL = 0x2
5082 00:56:23.918373 RPST = 0x0
5083 00:56:23.921635 RD_PRE = 0x0
5084 00:56:23.921712 WR_PRE = 0x1
5085 00:56:23.924718 WR_PST = 0x0
5086 00:56:23.924794 DBI_WR = 0x0
5087 00:56:23.928319 DBI_RD = 0x0
5088 00:56:23.928400 OTF = 0x1
5089 00:56:23.931363 ===================================
5090 00:56:23.934787 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5091 00:56:23.941584 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5092 00:56:23.945162 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5093 00:56:23.948631 ===================================
5094 00:56:23.951455 LPDDR4 DRAM CONFIGURATION
5095 00:56:23.954950 ===================================
5096 00:56:23.955026 EX_ROW_EN[0] = 0x10
5097 00:56:23.958498 EX_ROW_EN[1] = 0x0
5098 00:56:23.958573 LP4Y_EN = 0x0
5099 00:56:23.961899 WORK_FSP = 0x0
5100 00:56:23.962031 WL = 0x3
5101 00:56:23.965488 RL = 0x3
5102 00:56:23.965562 BL = 0x2
5103 00:56:23.968337 RPST = 0x0
5104 00:56:23.968435 RD_PRE = 0x0
5105 00:56:23.971831 WR_PRE = 0x1
5106 00:56:23.971905 WR_PST = 0x0
5107 00:56:23.975447 DBI_WR = 0x0
5108 00:56:23.975522 DBI_RD = 0x0
5109 00:56:23.978291 OTF = 0x1
5110 00:56:23.981733 ===================================
5111 00:56:23.988438 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5112 00:56:23.991705 nWR fixed to 30
5113 00:56:23.995007 [ModeRegInit_LP4] CH0 RK0
5114 00:56:23.995082 [ModeRegInit_LP4] CH0 RK1
5115 00:56:23.998669 [ModeRegInit_LP4] CH1 RK0
5116 00:56:24.002216 [ModeRegInit_LP4] CH1 RK1
5117 00:56:24.002291 match AC timing 9
5118 00:56:24.008952 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5119 00:56:24.011762 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5120 00:56:24.015663 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5121 00:56:24.022005 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5122 00:56:24.025330 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5123 00:56:24.025424 ==
5124 00:56:24.028737 Dram Type= 6, Freq= 0, CH_0, rank 0
5125 00:56:24.032007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 00:56:24.032098 ==
5127 00:56:24.039052 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5128 00:56:24.045324 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5129 00:56:24.048670 [CA 0] Center 38 (8~69) winsize 62
5130 00:56:24.052164 [CA 1] Center 38 (8~68) winsize 61
5131 00:56:24.055298 [CA 2] Center 35 (5~66) winsize 62
5132 00:56:24.058806 [CA 3] Center 35 (5~66) winsize 62
5133 00:56:24.061899 [CA 4] Center 34 (4~64) winsize 61
5134 00:56:24.062022 [CA 5] Center 34 (4~64) winsize 61
5135 00:56:24.065372
5136 00:56:24.069025 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5137 00:56:24.069100
5138 00:56:24.072319 [CATrainingPosCal] consider 1 rank data
5139 00:56:24.075293 u2DelayCellTimex100 = 270/100 ps
5140 00:56:24.078669 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5141 00:56:24.082329 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5142 00:56:24.085613 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5143 00:56:24.088922 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5144 00:56:24.092130 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5145 00:56:24.095716 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5146 00:56:24.095791
5147 00:56:24.099029 CA PerBit enable=1, Macro0, CA PI delay=34
5148 00:56:24.099104
5149 00:56:24.101922 [CBTSetCACLKResult] CA Dly = 34
5150 00:56:24.105578 CS Dly: 6 (0~37)
5151 00:56:24.105676 ==
5152 00:56:24.108887 Dram Type= 6, Freq= 0, CH_0, rank 1
5153 00:56:24.111916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 00:56:24.111992 ==
5155 00:56:24.118593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5156 00:56:24.125300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5157 00:56:24.128736 [CA 0] Center 38 (8~69) winsize 62
5158 00:56:24.132417 [CA 1] Center 38 (8~69) winsize 62
5159 00:56:24.135336 [CA 2] Center 35 (5~66) winsize 62
5160 00:56:24.138812 [CA 3] Center 35 (4~66) winsize 63
5161 00:56:24.138888 [CA 4] Center 34 (4~64) winsize 61
5162 00:56:24.142094 [CA 5] Center 33 (3~64) winsize 62
5163 00:56:24.142170
5164 00:56:24.149053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5165 00:56:24.149127
5166 00:56:24.152503 [CATrainingPosCal] consider 2 rank data
5167 00:56:24.155750 u2DelayCellTimex100 = 270/100 ps
5168 00:56:24.158631 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5169 00:56:24.162419 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5170 00:56:24.165695 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5171 00:56:24.169231 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5172 00:56:24.172465 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5173 00:56:24.175845 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5174 00:56:24.175920
5175 00:56:24.179267 CA PerBit enable=1, Macro0, CA PI delay=34
5176 00:56:24.179343
5177 00:56:24.182047 [CBTSetCACLKResult] CA Dly = 34
5178 00:56:24.185531 CS Dly: 7 (0~39)
5179 00:56:24.185605
5180 00:56:24.188870 ----->DramcWriteLeveling(PI) begin...
5181 00:56:24.188948 ==
5182 00:56:24.192189 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 00:56:24.195728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 00:56:24.195805 ==
5185 00:56:24.199139 Write leveling (Byte 0): 30 => 30
5186 00:56:24.202693 Write leveling (Byte 1): 29 => 29
5187 00:56:24.205832 DramcWriteLeveling(PI) end<-----
5188 00:56:24.205933
5189 00:56:24.206037 ==
5190 00:56:24.209171 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 00:56:24.212494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 00:56:24.212569 ==
5193 00:56:24.215978 [Gating] SW mode calibration
5194 00:56:24.222548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5195 00:56:24.229061 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5196 00:56:24.232764 0 14 0 | B1->B0 | 2424 3030 | 1 0 | (1 1) (0 0)
5197 00:56:24.235988 0 14 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5198 00:56:24.242613 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 00:56:24.245856 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5200 00:56:24.249191 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5201 00:56:24.255712 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5202 00:56:24.259037 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5203 00:56:24.262639 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
5204 00:56:24.269279 0 15 0 | B1->B0 | 3232 2929 | 0 0 | (0 1) (0 0)
5205 00:56:24.272639 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5206 00:56:24.276046 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 00:56:24.282244 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5208 00:56:24.285657 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 00:56:24.288988 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 00:56:24.295420 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5211 00:56:24.298820 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5212 00:56:24.302149 1 0 0 | B1->B0 | 2c2c 4040 | 0 0 | (1 1) (0 0)
5213 00:56:24.305524 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5214 00:56:24.312325 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 00:56:24.315596 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 00:56:24.318992 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 00:56:24.325427 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 00:56:24.329214 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 00:56:24.332179 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 00:56:24.338844 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5221 00:56:24.342516 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 00:56:24.345538 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 00:56:24.352466 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 00:56:24.355722 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 00:56:24.358759 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 00:56:24.365517 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 00:56:24.369057 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 00:56:24.372228 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 00:56:24.378960 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 00:56:24.382301 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 00:56:24.385510 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 00:56:24.389064 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 00:56:24.395940 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 00:56:24.399465 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 00:56:24.402113 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5236 00:56:24.409121 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5237 00:56:24.412110 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5238 00:56:24.415599 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5239 00:56:24.418852 Total UI for P1: 0, mck2ui 16
5240 00:56:24.422359 best dqsien dly found for B0: ( 1, 3, 0)
5241 00:56:24.425466 Total UI for P1: 0, mck2ui 16
5242 00:56:24.428895 best dqsien dly found for B1: ( 1, 3, 0)
5243 00:56:24.432307 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5244 00:56:24.435886 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5245 00:56:24.435977
5246 00:56:24.442130 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5247 00:56:24.445892 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5248 00:56:24.445989 [Gating] SW calibration Done
5249 00:56:24.448998 ==
5250 00:56:24.449090 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 00:56:24.455686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 00:56:24.455779 ==
5253 00:56:24.455864 RX Vref Scan: 0
5254 00:56:24.455946
5255 00:56:24.459237 RX Vref 0 -> 0, step: 1
5256 00:56:24.459321
5257 00:56:24.462652 RX Delay -80 -> 252, step: 8
5258 00:56:24.465547 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5259 00:56:24.469148 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5260 00:56:24.472515 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5261 00:56:24.476082 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5262 00:56:24.482299 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5263 00:56:24.485728 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5264 00:56:24.489235 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5265 00:56:24.492431 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5266 00:56:24.495781 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5267 00:56:24.498968 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5268 00:56:24.505702 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5269 00:56:24.508964 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5270 00:56:24.512488 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5271 00:56:24.516004 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5272 00:56:24.519414 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5273 00:56:24.522325 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5274 00:56:24.525600 ==
5275 00:56:24.529144 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 00:56:24.532481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 00:56:24.532572 ==
5278 00:56:24.532654 DQS Delay:
5279 00:56:24.535909 DQS0 = 0, DQS1 = 0
5280 00:56:24.535995 DQM Delay:
5281 00:56:24.538849 DQM0 = 99, DQM1 = 87
5282 00:56:24.538935 DQ Delay:
5283 00:56:24.542764 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5284 00:56:24.545642 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5285 00:56:24.548975 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5286 00:56:24.552224 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5287 00:56:24.552314
5288 00:56:24.552399
5289 00:56:24.552454 ==
5290 00:56:24.555637 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 00:56:24.559101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 00:56:24.559200 ==
5293 00:56:24.559286
5294 00:56:24.559365
5295 00:56:24.562690 TX Vref Scan disable
5296 00:56:24.565747 == TX Byte 0 ==
5297 00:56:24.569416 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5298 00:56:24.572912 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5299 00:56:24.575920 == TX Byte 1 ==
5300 00:56:24.579398 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5301 00:56:24.582964 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5302 00:56:24.583062 ==
5303 00:56:24.585892 Dram Type= 6, Freq= 0, CH_0, rank 0
5304 00:56:24.589396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 00:56:24.592758 ==
5306 00:56:24.592850
5307 00:56:24.592931
5308 00:56:24.593016 TX Vref Scan disable
5309 00:56:24.596192 == TX Byte 0 ==
5310 00:56:24.599607 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5311 00:56:24.603041 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5312 00:56:24.606466 == TX Byte 1 ==
5313 00:56:24.609817 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5314 00:56:24.613343 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5315 00:56:24.616245
5316 00:56:24.616313 [DATLAT]
5317 00:56:24.616399 Freq=933, CH0 RK0
5318 00:56:24.616484
5319 00:56:24.619475 DATLAT Default: 0xd
5320 00:56:24.619569 0, 0xFFFF, sum = 0
5321 00:56:24.623124 1, 0xFFFF, sum = 0
5322 00:56:24.623201 2, 0xFFFF, sum = 0
5323 00:56:24.626633 3, 0xFFFF, sum = 0
5324 00:56:24.626709 4, 0xFFFF, sum = 0
5325 00:56:24.629877 5, 0xFFFF, sum = 0
5326 00:56:24.629954 6, 0xFFFF, sum = 0
5327 00:56:24.633497 7, 0xFFFF, sum = 0
5328 00:56:24.633572 8, 0xFFFF, sum = 0
5329 00:56:24.636064 9, 0xFFFF, sum = 0
5330 00:56:24.636140 10, 0x0, sum = 1
5331 00:56:24.639877 11, 0x0, sum = 2
5332 00:56:24.639954 12, 0x0, sum = 3
5333 00:56:24.642729 13, 0x0, sum = 4
5334 00:56:24.642804 best_step = 11
5335 00:56:24.642861
5336 00:56:24.642915 ==
5337 00:56:24.646237 Dram Type= 6, Freq= 0, CH_0, rank 0
5338 00:56:24.653160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 00:56:24.653243 ==
5340 00:56:24.653301 RX Vref Scan: 1
5341 00:56:24.653355
5342 00:56:24.656021 RX Vref 0 -> 0, step: 1
5343 00:56:24.656096
5344 00:56:24.659764 RX Delay -61 -> 252, step: 4
5345 00:56:24.659838
5346 00:56:24.663157 Set Vref, RX VrefLevel [Byte0]: 52
5347 00:56:24.666458 [Byte1]: 57
5348 00:56:24.666533
5349 00:56:24.669348 Final RX Vref Byte 0 = 52 to rank0
5350 00:56:24.672697 Final RX Vref Byte 1 = 57 to rank0
5351 00:56:24.676256 Final RX Vref Byte 0 = 52 to rank1
5352 00:56:24.679359 Final RX Vref Byte 1 = 57 to rank1==
5353 00:56:24.683038 Dram Type= 6, Freq= 0, CH_0, rank 0
5354 00:56:24.685974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 00:56:24.686071 ==
5356 00:56:24.689743 DQS Delay:
5357 00:56:24.689818 DQS0 = 0, DQS1 = 0
5358 00:56:24.693106 DQM Delay:
5359 00:56:24.693181 DQM0 = 96, DQM1 = 89
5360 00:56:24.693238 DQ Delay:
5361 00:56:24.696235 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5362 00:56:24.699829 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5363 00:56:24.702808 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5364 00:56:24.706124 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5365 00:56:24.706198
5366 00:56:24.706255
5367 00:56:24.716111 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5368 00:56:24.719856 CH0 RK0: MR19=505, MR18=1601
5369 00:56:24.722667 CH0_RK0: MR19=0x505, MR18=0x1601, DQSOSC=414, MR23=63, INC=63, DEC=42
5370 00:56:24.722744
5371 00:56:24.726055 ----->DramcWriteLeveling(PI) begin...
5372 00:56:24.729551 ==
5373 00:56:24.732811 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 00:56:24.736463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 00:56:24.736539 ==
5376 00:56:24.739537 Write leveling (Byte 0): 34 => 34
5377 00:56:24.743126 Write leveling (Byte 1): 26 => 26
5378 00:56:24.746022 DramcWriteLeveling(PI) end<-----
5379 00:56:24.746111
5380 00:56:24.746169 ==
5381 00:56:24.749475 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 00:56:24.753046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 00:56:24.753122 ==
5384 00:56:24.756194 [Gating] SW mode calibration
5385 00:56:24.762679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5386 00:56:24.769715 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5387 00:56:24.773185 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
5388 00:56:24.776110 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 00:56:24.779641 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 00:56:24.786482 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 00:56:24.789711 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 00:56:24.793453 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 00:56:24.799756 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5394 00:56:24.803364 0 14 28 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
5395 00:56:24.806485 0 15 0 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
5396 00:56:24.812901 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5397 00:56:24.816732 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 00:56:24.819992 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 00:56:24.826283 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 00:56:24.830108 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 00:56:24.832894 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 00:56:24.839818 0 15 28 | B1->B0 | 2323 2e2e | 1 0 | (0 0) (0 0)
5403 00:56:24.843600 1 0 0 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5404 00:56:24.846359 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 00:56:24.849787 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 00:56:24.856655 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 00:56:24.859581 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 00:56:24.862836 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 00:56:24.869923 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5410 00:56:24.872933 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5411 00:56:24.876212 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5412 00:56:24.883190 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 00:56:24.886819 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 00:56:24.889886 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 00:56:24.896356 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 00:56:24.899695 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 00:56:24.903137 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 00:56:24.909852 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 00:56:24.913043 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 00:56:24.916823 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 00:56:24.922925 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 00:56:24.926343 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 00:56:24.929580 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 00:56:24.936295 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 00:56:24.939761 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5426 00:56:24.943067 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5427 00:56:24.946731 Total UI for P1: 0, mck2ui 16
5428 00:56:24.950142 best dqsien dly found for B0: ( 1, 2, 24)
5429 00:56:24.953510 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5430 00:56:24.959820 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 00:56:24.963192 Total UI for P1: 0, mck2ui 16
5432 00:56:24.966533 best dqsien dly found for B1: ( 1, 2, 30)
5433 00:56:24.969689 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5434 00:56:24.972856 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5435 00:56:24.972933
5436 00:56:24.976247 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5437 00:56:24.979491 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5438 00:56:24.983418 [Gating] SW calibration Done
5439 00:56:24.983494 ==
5440 00:56:24.986172 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 00:56:24.989782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 00:56:24.989884 ==
5443 00:56:24.993410 RX Vref Scan: 0
5444 00:56:24.993503
5445 00:56:24.993593 RX Vref 0 -> 0, step: 1
5446 00:56:24.993682
5447 00:56:24.996644 RX Delay -80 -> 252, step: 8
5448 00:56:24.999495 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5449 00:56:25.006435 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5450 00:56:25.009917 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5451 00:56:25.013451 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5452 00:56:25.016392 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5453 00:56:25.019688 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5454 00:56:25.023153 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5455 00:56:25.029998 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5456 00:56:25.032992 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5457 00:56:25.036494 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5458 00:56:25.040043 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5459 00:56:25.043232 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5460 00:56:25.046634 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5461 00:56:25.053621 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5462 00:56:25.056538 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5463 00:56:25.059946 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5464 00:56:25.060031 ==
5465 00:56:25.063300 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 00:56:25.067024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 00:56:25.067133 ==
5468 00:56:25.069876 DQS Delay:
5469 00:56:25.069968 DQS0 = 0, DQS1 = 0
5470 00:56:25.073163 DQM Delay:
5471 00:56:25.073253 DQM0 = 96, DQM1 = 86
5472 00:56:25.073343 DQ Delay:
5473 00:56:25.076277 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5474 00:56:25.080016 DQ4 =95, DQ5 =83, DQ6 =107, DQ7 =103
5475 00:56:25.083359 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5476 00:56:25.086541 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =95
5477 00:56:25.086634
5478 00:56:25.086717
5479 00:56:25.086797 ==
5480 00:56:25.090342 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 00:56:25.096667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 00:56:25.096767 ==
5483 00:56:25.096842
5484 00:56:25.096910
5485 00:56:25.096977 TX Vref Scan disable
5486 00:56:25.100812 == TX Byte 0 ==
5487 00:56:25.103708 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5488 00:56:25.110710 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5489 00:56:25.110783 == TX Byte 1 ==
5490 00:56:25.114132 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5491 00:56:25.117580 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5492 00:56:25.120555 ==
5493 00:56:25.123871 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 00:56:25.127256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 00:56:25.127353 ==
5496 00:56:25.127425
5497 00:56:25.127492
5498 00:56:25.130722 TX Vref Scan disable
5499 00:56:25.130810 == TX Byte 0 ==
5500 00:56:25.137228 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5501 00:56:25.140270 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5502 00:56:25.140362 == TX Byte 1 ==
5503 00:56:25.147413 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5504 00:56:25.150398 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5505 00:56:25.150468
5506 00:56:25.150544 [DATLAT]
5507 00:56:25.153676 Freq=933, CH0 RK1
5508 00:56:25.153783
5509 00:56:25.153864 DATLAT Default: 0xb
5510 00:56:25.157110 0, 0xFFFF, sum = 0
5511 00:56:25.157202 1, 0xFFFF, sum = 0
5512 00:56:25.160525 2, 0xFFFF, sum = 0
5513 00:56:25.160591 3, 0xFFFF, sum = 0
5514 00:56:25.163871 4, 0xFFFF, sum = 0
5515 00:56:25.163960 5, 0xFFFF, sum = 0
5516 00:56:25.167128 6, 0xFFFF, sum = 0
5517 00:56:25.167229 7, 0xFFFF, sum = 0
5518 00:56:25.170698 8, 0xFFFF, sum = 0
5519 00:56:25.174023 9, 0xFFFF, sum = 0
5520 00:56:25.174105 10, 0x0, sum = 1
5521 00:56:25.174180 11, 0x0, sum = 2
5522 00:56:25.177188 12, 0x0, sum = 3
5523 00:56:25.177267 13, 0x0, sum = 4
5524 00:56:25.180326 best_step = 11
5525 00:56:25.180417
5526 00:56:25.180500 ==
5527 00:56:25.184164 Dram Type= 6, Freq= 0, CH_0, rank 1
5528 00:56:25.187101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 00:56:25.187196 ==
5530 00:56:25.190923 RX Vref Scan: 0
5531 00:56:25.191014
5532 00:56:25.191107 RX Vref 0 -> 0, step: 1
5533 00:56:25.191195
5534 00:56:25.194127 RX Delay -61 -> 252, step: 4
5535 00:56:25.201306 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5536 00:56:25.204812 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5537 00:56:25.207541 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5538 00:56:25.211010 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5539 00:56:25.214506 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5540 00:56:25.217874 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5541 00:56:25.224679 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5542 00:56:25.228266 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5543 00:56:25.231040 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5544 00:56:25.234848 iDelay=199, Bit 9, Center 80 (-5 ~ 166) 172
5545 00:56:25.237687 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5546 00:56:25.241345 iDelay=199, Bit 11, Center 82 (-5 ~ 170) 176
5547 00:56:25.248043 iDelay=199, Bit 12, Center 94 (11 ~ 178) 168
5548 00:56:25.251484 iDelay=199, Bit 13, Center 96 (11 ~ 182) 172
5549 00:56:25.254563 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5550 00:56:25.258415 iDelay=199, Bit 15, Center 98 (11 ~ 186) 176
5551 00:56:25.258511 ==
5552 00:56:25.261471 Dram Type= 6, Freq= 0, CH_0, rank 1
5553 00:56:25.264847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 00:56:25.268195 ==
5555 00:56:25.268289 DQS Delay:
5556 00:56:25.268382 DQS0 = 0, DQS1 = 0
5557 00:56:25.271787 DQM Delay:
5558 00:56:25.271878 DQM0 = 96, DQM1 = 90
5559 00:56:25.271970 DQ Delay:
5560 00:56:25.274509 DQ0 =98, DQ1 =96, DQ2 =92, DQ3 =94
5561 00:56:25.278103 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =102
5562 00:56:25.281447 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =82
5563 00:56:25.284655 DQ12 =94, DQ13 =96, DQ14 =98, DQ15 =98
5564 00:56:25.284749
5565 00:56:25.287987
5566 00:56:25.294791 [DQSOSCAuto] RK1, (LSB)MR18= 0x1906, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 413 ps
5567 00:56:25.297945 CH0 RK1: MR19=505, MR18=1906
5568 00:56:25.305002 CH0_RK1: MR19=0x505, MR18=0x1906, DQSOSC=413, MR23=63, INC=63, DEC=42
5569 00:56:25.305073 [RxdqsGatingPostProcess] freq 933
5570 00:56:25.311468 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5571 00:56:25.314744 best DQS0 dly(2T, 0.5T) = (0, 11)
5572 00:56:25.318261 best DQS1 dly(2T, 0.5T) = (0, 11)
5573 00:56:25.321573 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5574 00:56:25.325166 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5575 00:56:25.327876 best DQS0 dly(2T, 0.5T) = (0, 10)
5576 00:56:25.331191 best DQS1 dly(2T, 0.5T) = (0, 10)
5577 00:56:25.334670 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5578 00:56:25.337898 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5579 00:56:25.341172 Pre-setting of DQS Precalculation
5580 00:56:25.344626 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5581 00:56:25.344722 ==
5582 00:56:25.348411 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 00:56:25.351369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 00:56:25.351460 ==
5585 00:56:25.358268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5586 00:56:25.364665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5587 00:56:25.368059 [CA 0] Center 36 (6~67) winsize 62
5588 00:56:25.371281 [CA 1] Center 36 (6~67) winsize 62
5589 00:56:25.374611 [CA 2] Center 34 (4~64) winsize 61
5590 00:56:25.378002 [CA 3] Center 33 (3~64) winsize 62
5591 00:56:25.381556 [CA 4] Center 34 (4~65) winsize 62
5592 00:56:25.384700 [CA 5] Center 33 (3~63) winsize 61
5593 00:56:25.384792
5594 00:56:25.388085 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5595 00:56:25.388191
5596 00:56:25.391189 [CATrainingPosCal] consider 1 rank data
5597 00:56:25.394677 u2DelayCellTimex100 = 270/100 ps
5598 00:56:25.398113 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5599 00:56:25.401560 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5600 00:56:25.404605 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5601 00:56:25.408380 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5602 00:56:25.411498 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5603 00:56:25.418294 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5604 00:56:25.418385
5605 00:56:25.421256 CA PerBit enable=1, Macro0, CA PI delay=33
5606 00:56:25.421372
5607 00:56:25.424904 [CBTSetCACLKResult] CA Dly = 33
5608 00:56:25.424998 CS Dly: 4 (0~35)
5609 00:56:25.425080 ==
5610 00:56:25.428406 Dram Type= 6, Freq= 0, CH_1, rank 1
5611 00:56:25.431188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 00:56:25.431297 ==
5613 00:56:25.437959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5614 00:56:25.444661 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5615 00:56:25.447886 [CA 0] Center 36 (6~67) winsize 62
5616 00:56:25.450982 [CA 1] Center 36 (6~67) winsize 62
5617 00:56:25.454387 [CA 2] Center 33 (3~64) winsize 62
5618 00:56:25.457809 [CA 3] Center 33 (3~64) winsize 62
5619 00:56:25.461212 [CA 4] Center 34 (4~65) winsize 62
5620 00:56:25.464714 [CA 5] Center 32 (2~63) winsize 62
5621 00:56:25.464803
5622 00:56:25.468192 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5623 00:56:25.468283
5624 00:56:25.471501 [CATrainingPosCal] consider 2 rank data
5625 00:56:25.474697 u2DelayCellTimex100 = 270/100 ps
5626 00:56:25.478347 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5627 00:56:25.481409 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5628 00:56:25.484694 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5629 00:56:25.488294 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5630 00:56:25.491110 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5631 00:56:25.494580 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5632 00:56:25.497930
5633 00:56:25.501058 CA PerBit enable=1, Macro0, CA PI delay=33
5634 00:56:25.501149
5635 00:56:25.504556 [CBTSetCACLKResult] CA Dly = 33
5636 00:56:25.504656 CS Dly: 5 (0~37)
5637 00:56:25.504742
5638 00:56:25.507856 ----->DramcWriteLeveling(PI) begin...
5639 00:56:25.507948 ==
5640 00:56:25.511263 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 00:56:25.514419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 00:56:25.517738 ==
5643 00:56:25.517831 Write leveling (Byte 0): 24 => 24
5644 00:56:25.521129 Write leveling (Byte 1): 30 => 30
5645 00:56:25.524525 DramcWriteLeveling(PI) end<-----
5646 00:56:25.524617
5647 00:56:25.524698 ==
5648 00:56:25.528186 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 00:56:25.534562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 00:56:25.534666 ==
5651 00:56:25.534768 [Gating] SW mode calibration
5652 00:56:25.544617 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5653 00:56:25.548170 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5654 00:56:25.551441 0 14 0 | B1->B0 | 3030 2e2e | 1 0 | (1 1) (0 0)
5655 00:56:25.558260 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5656 00:56:25.561236 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5657 00:56:25.564615 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5658 00:56:25.571567 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5659 00:56:25.575019 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5660 00:56:25.578599 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5661 00:56:25.584753 0 14 28 | B1->B0 | 3131 3333 | 1 1 | (1 0) (1 0)
5662 00:56:25.588003 0 15 0 | B1->B0 | 2727 2727 | 0 0 | (1 0) (1 0)
5663 00:56:25.591467 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5664 00:56:25.598153 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5665 00:56:25.601715 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5666 00:56:25.605026 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5667 00:56:25.611985 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5668 00:56:25.615214 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5669 00:56:25.618584 0 15 28 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (0 0)
5670 00:56:25.621724 1 0 0 | B1->B0 | 4141 3c3c | 0 0 | (0 0) (0 0)
5671 00:56:25.628450 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 00:56:25.631850 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 00:56:25.635029 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 00:56:25.641385 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 00:56:25.644783 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 00:56:25.648129 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 00:56:25.654777 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5678 00:56:25.658219 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 00:56:25.661573 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 00:56:25.668378 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 00:56:25.671342 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 00:56:25.675253 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 00:56:25.681335 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 00:56:25.684874 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 00:56:25.687909 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 00:56:25.694968 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 00:56:25.698256 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 00:56:25.701884 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 00:56:25.705129 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 00:56:25.711474 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 00:56:25.715081 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 00:56:25.718643 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5693 00:56:25.725596 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5694 00:56:25.728253 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5695 00:56:25.731641 Total UI for P1: 0, mck2ui 16
5696 00:56:25.734974 best dqsien dly found for B0: ( 1, 2, 26)
5697 00:56:25.738428 Total UI for P1: 0, mck2ui 16
5698 00:56:25.741712 best dqsien dly found for B1: ( 1, 2, 28)
5699 00:56:25.745219 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5700 00:56:25.748593 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5701 00:56:25.748718
5702 00:56:25.751973 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5703 00:56:25.755287 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5704 00:56:25.758124 [Gating] SW calibration Done
5705 00:56:25.758204 ==
5706 00:56:25.761815 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 00:56:25.765420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 00:56:25.768608 ==
5709 00:56:25.768721 RX Vref Scan: 0
5710 00:56:25.768788
5711 00:56:25.771660 RX Vref 0 -> 0, step: 1
5712 00:56:25.771724
5713 00:56:25.771778 RX Delay -80 -> 252, step: 8
5714 00:56:25.778923 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5715 00:56:25.782272 iDelay=200, Bit 1, Center 91 (0 ~ 183) 184
5716 00:56:25.785733 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5717 00:56:25.788627 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5718 00:56:25.792093 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5719 00:56:25.795536 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5720 00:56:25.801931 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5721 00:56:25.805722 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5722 00:56:25.808838 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5723 00:56:25.811923 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5724 00:56:25.815225 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5725 00:56:25.822284 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5726 00:56:25.825603 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5727 00:56:25.828431 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5728 00:56:25.831815 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5729 00:56:25.835309 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5730 00:56:25.835389 ==
5731 00:56:25.838569 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 00:56:25.845109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 00:56:25.845220 ==
5734 00:56:25.845311 DQS Delay:
5735 00:56:25.845395 DQS0 = 0, DQS1 = 0
5736 00:56:25.848529 DQM Delay:
5737 00:56:25.848631 DQM0 = 94, DQM1 = 88
5738 00:56:25.852012 DQ Delay:
5739 00:56:25.854913 DQ0 =95, DQ1 =91, DQ2 =79, DQ3 =95
5740 00:56:25.858414 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5741 00:56:25.861787 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5742 00:56:25.865178 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5743 00:56:25.865255
5744 00:56:25.865316
5745 00:56:25.865375 ==
5746 00:56:25.868490 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 00:56:25.871814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 00:56:25.871887 ==
5749 00:56:25.871953
5750 00:56:25.872008
5751 00:56:25.875008 TX Vref Scan disable
5752 00:56:25.875069 == TX Byte 0 ==
5753 00:56:25.882099 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5754 00:56:25.885343 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5755 00:56:25.885412 == TX Byte 1 ==
5756 00:56:25.891623 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5757 00:56:25.895127 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5758 00:56:25.895191 ==
5759 00:56:25.898713 Dram Type= 6, Freq= 0, CH_1, rank 0
5760 00:56:25.902076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 00:56:25.902139 ==
5762 00:56:25.902193
5763 00:56:25.902252
5764 00:56:25.905080 TX Vref Scan disable
5765 00:56:25.908301 == TX Byte 0 ==
5766 00:56:25.911763 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5767 00:56:25.915003 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5768 00:56:25.918780 == TX Byte 1 ==
5769 00:56:25.921698 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5770 00:56:25.925221 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5771 00:56:25.925284
5772 00:56:25.928710 [DATLAT]
5773 00:56:25.928773 Freq=933, CH1 RK0
5774 00:56:25.928827
5775 00:56:25.932008 DATLAT Default: 0xd
5776 00:56:25.932076 0, 0xFFFF, sum = 0
5777 00:56:25.934959 1, 0xFFFF, sum = 0
5778 00:56:25.935046 2, 0xFFFF, sum = 0
5779 00:56:25.938889 3, 0xFFFF, sum = 0
5780 00:56:25.938953 4, 0xFFFF, sum = 0
5781 00:56:25.941810 5, 0xFFFF, sum = 0
5782 00:56:25.941877 6, 0xFFFF, sum = 0
5783 00:56:25.945222 7, 0xFFFF, sum = 0
5784 00:56:25.945287 8, 0xFFFF, sum = 0
5785 00:56:25.948674 9, 0xFFFF, sum = 0
5786 00:56:25.948744 10, 0x0, sum = 1
5787 00:56:25.952056 11, 0x0, sum = 2
5788 00:56:25.952121 12, 0x0, sum = 3
5789 00:56:25.955408 13, 0x0, sum = 4
5790 00:56:25.955473 best_step = 11
5791 00:56:25.955527
5792 00:56:25.955578 ==
5793 00:56:25.958574 Dram Type= 6, Freq= 0, CH_1, rank 0
5794 00:56:25.965055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 00:56:25.965124 ==
5796 00:56:25.965185 RX Vref Scan: 1
5797 00:56:25.965239
5798 00:56:25.968440 RX Vref 0 -> 0, step: 1
5799 00:56:25.968510
5800 00:56:25.971978 RX Delay -61 -> 252, step: 4
5801 00:56:25.972046
5802 00:56:25.975365 Set Vref, RX VrefLevel [Byte0]: 52
5803 00:56:25.978284 [Byte1]: 52
5804 00:56:25.978354
5805 00:56:25.981631 Final RX Vref Byte 0 = 52 to rank0
5806 00:56:25.985239 Final RX Vref Byte 1 = 52 to rank0
5807 00:56:25.988376 Final RX Vref Byte 0 = 52 to rank1
5808 00:56:25.991607 Final RX Vref Byte 1 = 52 to rank1==
5809 00:56:25.995425 Dram Type= 6, Freq= 0, CH_1, rank 0
5810 00:56:25.998828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 00:56:25.998894 ==
5812 00:56:26.002248 DQS Delay:
5813 00:56:26.002312 DQS0 = 0, DQS1 = 0
5814 00:56:26.002367 DQM Delay:
5815 00:56:26.005098 DQM0 = 98, DQM1 = 90
5816 00:56:26.005161 DQ Delay:
5817 00:56:26.008441 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =98
5818 00:56:26.012021 DQ4 =98, DQ5 =108, DQ6 =108, DQ7 =92
5819 00:56:26.015188 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =84
5820 00:56:26.018664 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =96
5821 00:56:26.018730
5822 00:56:26.018792
5823 00:56:26.028908 [DQSOSCAuto] RK0, (LSB)MR18= 0x1bf7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 413 ps
5824 00:56:26.028990 CH1 RK0: MR19=504, MR18=1BF7
5825 00:56:26.035865 CH1_RK0: MR19=0x504, MR18=0x1BF7, DQSOSC=413, MR23=63, INC=63, DEC=42
5826 00:56:26.035949
5827 00:56:26.038608 ----->DramcWriteLeveling(PI) begin...
5828 00:56:26.038686 ==
5829 00:56:26.042107 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 00:56:26.048901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 00:56:26.049008 ==
5832 00:56:26.051701 Write leveling (Byte 0): 27 => 27
5833 00:56:26.055239 Write leveling (Byte 1): 27 => 27
5834 00:56:26.055303 DramcWriteLeveling(PI) end<-----
5835 00:56:26.058750
5836 00:56:26.058812 ==
5837 00:56:26.062079 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 00:56:26.065360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 00:56:26.065433 ==
5840 00:56:26.068661 [Gating] SW mode calibration
5841 00:56:26.075500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5842 00:56:26.078526 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5843 00:56:26.085367 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5844 00:56:26.088645 0 14 4 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5845 00:56:26.092146 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5846 00:56:26.098574 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5847 00:56:26.101934 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5848 00:56:26.105379 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5849 00:56:26.111809 0 14 24 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (1 0)
5850 00:56:26.115158 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5851 00:56:26.118712 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5852 00:56:26.125348 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5853 00:56:26.128590 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 00:56:26.132324 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5855 00:56:26.138636 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 00:56:26.142260 0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5857 00:56:26.145611 0 15 24 | B1->B0 | 2b2b 3636 | 0 0 | (1 1) (0 0)
5858 00:56:26.148498 0 15 28 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
5859 00:56:26.155153 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 00:56:26.158638 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 00:56:26.162125 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 00:56:26.168841 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 00:56:26.172205 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 00:56:26.175080 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 00:56:26.181770 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5866 00:56:26.185067 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 00:56:26.188717 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 00:56:26.195515 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 00:56:26.198995 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 00:56:26.202297 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 00:56:26.209145 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 00:56:26.212589 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 00:56:26.215580 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 00:56:26.222124 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 00:56:26.225355 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 00:56:26.228837 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 00:56:26.232073 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 00:56:26.238664 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 00:56:26.242333 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 00:56:26.245248 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 00:56:26.252274 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5882 00:56:26.255703 Total UI for P1: 0, mck2ui 16
5883 00:56:26.258527 best dqsien dly found for B0: ( 1, 2, 22)
5884 00:56:26.262329 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5885 00:56:26.265699 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5886 00:56:26.269091 Total UI for P1: 0, mck2ui 16
5887 00:56:26.272383 best dqsien dly found for B1: ( 1, 2, 26)
5888 00:56:26.276207 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5889 00:56:26.279252 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5890 00:56:26.279346
5891 00:56:26.285762 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5892 00:56:26.288719 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5893 00:56:26.288802 [Gating] SW calibration Done
5894 00:56:26.292153 ==
5895 00:56:26.295798 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 00:56:26.299198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 00:56:26.299265 ==
5898 00:56:26.299334 RX Vref Scan: 0
5899 00:56:26.299403
5900 00:56:26.302210 RX Vref 0 -> 0, step: 1
5901 00:56:26.302276
5902 00:56:26.305763 RX Delay -80 -> 252, step: 8
5903 00:56:26.308989 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5904 00:56:26.312071 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5905 00:56:26.315461 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5906 00:56:26.322456 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5907 00:56:26.325702 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5908 00:56:26.328902 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5909 00:56:26.332235 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5910 00:56:26.335805 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5911 00:56:26.339383 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5912 00:56:26.345831 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5913 00:56:26.349358 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5914 00:56:26.352210 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5915 00:56:26.355583 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5916 00:56:26.359121 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5917 00:56:26.362381 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5918 00:56:26.369458 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5919 00:56:26.369534 ==
5920 00:56:26.372268 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 00:56:26.375553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 00:56:26.375618 ==
5923 00:56:26.375678 DQS Delay:
5924 00:56:26.379326 DQS0 = 0, DQS1 = 0
5925 00:56:26.379393 DQM Delay:
5926 00:56:26.382144 DQM0 = 93, DQM1 = 89
5927 00:56:26.382203 DQ Delay:
5928 00:56:26.385588 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5929 00:56:26.388880 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5930 00:56:26.392490 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5931 00:56:26.395842 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5932 00:56:26.395902
5933 00:56:26.395955
5934 00:56:26.396009 ==
5935 00:56:26.399429 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 00:56:26.402316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 00:56:26.402380 ==
5938 00:56:26.402433
5939 00:56:26.402483
5940 00:56:26.405780 TX Vref Scan disable
5941 00:56:26.409062 == TX Byte 0 ==
5942 00:56:26.412355 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5943 00:56:26.415910 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5944 00:56:26.419279 == TX Byte 1 ==
5945 00:56:26.422563 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5946 00:56:26.425858 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5947 00:56:26.425961 ==
5948 00:56:26.428999 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 00:56:26.432618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 00:56:26.435813 ==
5951 00:56:26.435882
5952 00:56:26.435939
5953 00:56:26.435992 TX Vref Scan disable
5954 00:56:26.439333 == TX Byte 0 ==
5955 00:56:26.443130 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5956 00:56:26.446231 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5957 00:56:26.449855 == TX Byte 1 ==
5958 00:56:26.453377 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5959 00:56:26.456274 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5960 00:56:26.459516
5961 00:56:26.459583 [DATLAT]
5962 00:56:26.459640 Freq=933, CH1 RK1
5963 00:56:26.459694
5964 00:56:26.462649 DATLAT Default: 0xb
5965 00:56:26.462749 0, 0xFFFF, sum = 0
5966 00:56:26.466326 1, 0xFFFF, sum = 0
5967 00:56:26.466395 2, 0xFFFF, sum = 0
5968 00:56:26.469865 3, 0xFFFF, sum = 0
5969 00:56:26.469955 4, 0xFFFF, sum = 0
5970 00:56:26.472555 5, 0xFFFF, sum = 0
5971 00:56:26.475956 6, 0xFFFF, sum = 0
5972 00:56:26.476018 7, 0xFFFF, sum = 0
5973 00:56:26.479281 8, 0xFFFF, sum = 0
5974 00:56:26.479345 9, 0xFFFF, sum = 0
5975 00:56:26.482980 10, 0x0, sum = 1
5976 00:56:26.483052 11, 0x0, sum = 2
5977 00:56:26.483108 12, 0x0, sum = 3
5978 00:56:26.486233 13, 0x0, sum = 4
5979 00:56:26.486296 best_step = 11
5980 00:56:26.486348
5981 00:56:26.489143 ==
5982 00:56:26.489222 Dram Type= 6, Freq= 0, CH_1, rank 1
5983 00:56:26.495722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5984 00:56:26.495791 ==
5985 00:56:26.495846 RX Vref Scan: 0
5986 00:56:26.495905
5987 00:56:26.499234 RX Vref 0 -> 0, step: 1
5988 00:56:26.499295
5989 00:56:26.502664 RX Delay -61 -> 252, step: 4
5990 00:56:26.505966 iDelay=199, Bit 0, Center 98 (11 ~ 186) 176
5991 00:56:26.512645 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5992 00:56:26.515969 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5993 00:56:26.519558 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5994 00:56:26.522360 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5995 00:56:26.525822 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5996 00:56:26.529272 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5997 00:56:26.535819 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5998 00:56:26.539476 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5999 00:56:26.542628 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
6000 00:56:26.545896 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
6001 00:56:26.549062 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
6002 00:56:26.552543 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
6003 00:56:26.559347 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
6004 00:56:26.562679 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
6005 00:56:26.565654 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
6006 00:56:26.565746 ==
6007 00:56:26.569222 Dram Type= 6, Freq= 0, CH_1, rank 1
6008 00:56:26.572596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6009 00:56:26.575918 ==
6010 00:56:26.576002 DQS Delay:
6011 00:56:26.576072 DQS0 = 0, DQS1 = 0
6012 00:56:26.578995 DQM Delay:
6013 00:56:26.579060 DQM0 = 94, DQM1 = 91
6014 00:56:26.582351 DQ Delay:
6015 00:56:26.582417 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =92
6016 00:56:26.585948 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =90
6017 00:56:26.589458 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =84
6018 00:56:26.592724 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
6019 00:56:26.596019
6020 00:56:26.596085
6021 00:56:26.602490 [DQSOSCAuto] RK1, (LSB)MR18= 0x131d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
6022 00:56:26.605897 CH1 RK1: MR19=505, MR18=131D
6023 00:56:26.612938 CH1_RK1: MR19=0x505, MR18=0x131D, DQSOSC=412, MR23=63, INC=63, DEC=42
6024 00:56:26.616056 [RxdqsGatingPostProcess] freq 933
6025 00:56:26.619001 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6026 00:56:26.622464 best DQS0 dly(2T, 0.5T) = (0, 10)
6027 00:56:26.626153 best DQS1 dly(2T, 0.5T) = (0, 10)
6028 00:56:26.629468 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6029 00:56:26.632430 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6030 00:56:26.635684 best DQS0 dly(2T, 0.5T) = (0, 10)
6031 00:56:26.639124 best DQS1 dly(2T, 0.5T) = (0, 10)
6032 00:56:26.642551 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6033 00:56:26.645947 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6034 00:56:26.649378 Pre-setting of DQS Precalculation
6035 00:56:26.652626 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6036 00:56:26.659173 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6037 00:56:26.668976 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6038 00:56:26.669046
6039 00:56:26.669103
6040 00:56:26.672566 [Calibration Summary] 1866 Mbps
6041 00:56:26.672632 CH 0, Rank 0
6042 00:56:26.675516 SW Impedance : PASS
6043 00:56:26.675582 DUTY Scan : NO K
6044 00:56:26.679115 ZQ Calibration : PASS
6045 00:56:26.679206 Jitter Meter : NO K
6046 00:56:26.682151 CBT Training : PASS
6047 00:56:26.685640 Write leveling : PASS
6048 00:56:26.685739 RX DQS gating : PASS
6049 00:56:26.688893 RX DQ/DQS(RDDQC) : PASS
6050 00:56:26.692311 TX DQ/DQS : PASS
6051 00:56:26.692374 RX DATLAT : PASS
6052 00:56:26.695689 RX DQ/DQS(Engine): PASS
6053 00:56:26.699085 TX OE : NO K
6054 00:56:26.699155 All Pass.
6055 00:56:26.699208
6056 00:56:26.699259 CH 0, Rank 1
6057 00:56:26.702430 SW Impedance : PASS
6058 00:56:26.705633 DUTY Scan : NO K
6059 00:56:26.705721 ZQ Calibration : PASS
6060 00:56:26.709111 Jitter Meter : NO K
6061 00:56:26.712539 CBT Training : PASS
6062 00:56:26.712618 Write leveling : PASS
6063 00:56:26.715805 RX DQS gating : PASS
6064 00:56:26.719354 RX DQ/DQS(RDDQC) : PASS
6065 00:56:26.719417 TX DQ/DQS : PASS
6066 00:56:26.722095 RX DATLAT : PASS
6067 00:56:26.722169 RX DQ/DQS(Engine): PASS
6068 00:56:26.725527 TX OE : NO K
6069 00:56:26.725585 All Pass.
6070 00:56:26.725635
6071 00:56:26.729025 CH 1, Rank 0
6072 00:56:26.729086 SW Impedance : PASS
6073 00:56:26.732428 DUTY Scan : NO K
6074 00:56:26.735843 ZQ Calibration : PASS
6075 00:56:26.735928 Jitter Meter : NO K
6076 00:56:26.739235 CBT Training : PASS
6077 00:56:26.742095 Write leveling : PASS
6078 00:56:26.742170 RX DQS gating : PASS
6079 00:56:26.745635 RX DQ/DQS(RDDQC) : PASS
6080 00:56:26.749113 TX DQ/DQS : PASS
6081 00:56:26.749188 RX DATLAT : PASS
6082 00:56:26.752088 RX DQ/DQS(Engine): PASS
6083 00:56:26.755490 TX OE : NO K
6084 00:56:26.755568 All Pass.
6085 00:56:26.755660
6086 00:56:26.755726 CH 1, Rank 1
6087 00:56:26.758948 SW Impedance : PASS
6088 00:56:26.762208 DUTY Scan : NO K
6089 00:56:26.762289 ZQ Calibration : PASS
6090 00:56:26.765882 Jitter Meter : NO K
6091 00:56:26.765963 CBT Training : PASS
6092 00:56:26.769270 Write leveling : PASS
6093 00:56:26.772658 RX DQS gating : PASS
6094 00:56:26.772719 RX DQ/DQS(RDDQC) : PASS
6095 00:56:26.775886 TX DQ/DQS : PASS
6096 00:56:26.779217 RX DATLAT : PASS
6097 00:56:26.779278 RX DQ/DQS(Engine): PASS
6098 00:56:26.782388 TX OE : NO K
6099 00:56:26.782452 All Pass.
6100 00:56:26.782505
6101 00:56:26.786111 DramC Write-DBI off
6102 00:56:26.789152 PER_BANK_REFRESH: Hybrid Mode
6103 00:56:26.789221 TX_TRACKING: ON
6104 00:56:26.799560 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6105 00:56:26.802532 [FAST_K] Save calibration result to emmc
6106 00:56:26.805677 dramc_set_vcore_voltage set vcore to 650000
6107 00:56:26.809030 Read voltage for 400, 6
6108 00:56:26.809097 Vio18 = 0
6109 00:56:26.809153 Vcore = 650000
6110 00:56:26.812406 Vdram = 0
6111 00:56:26.812471 Vddq = 0
6112 00:56:26.812525 Vmddr = 0
6113 00:56:26.819461 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6114 00:56:26.822300 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6115 00:56:26.825772 MEM_TYPE=3, freq_sel=20
6116 00:56:26.829150 sv_algorithm_assistance_LP4_800
6117 00:56:26.833074 ============ PULL DRAM RESETB DOWN ============
6118 00:56:26.836276 ========== PULL DRAM RESETB DOWN end =========
6119 00:56:26.842539 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6120 00:56:26.846155 ===================================
6121 00:56:26.846223 LPDDR4 DRAM CONFIGURATION
6122 00:56:26.849453 ===================================
6123 00:56:26.852892 EX_ROW_EN[0] = 0x0
6124 00:56:26.852964 EX_ROW_EN[1] = 0x0
6125 00:56:26.856229 LP4Y_EN = 0x0
6126 00:56:26.859080 WORK_FSP = 0x0
6127 00:56:26.859146 WL = 0x2
6128 00:56:26.862587 RL = 0x2
6129 00:56:26.862652 BL = 0x2
6130 00:56:26.865797 RPST = 0x0
6131 00:56:26.865867 RD_PRE = 0x0
6132 00:56:26.869278 WR_PRE = 0x1
6133 00:56:26.869344 WR_PST = 0x0
6134 00:56:26.872606 DBI_WR = 0x0
6135 00:56:26.872692 DBI_RD = 0x0
6136 00:56:26.875947 OTF = 0x1
6137 00:56:26.879507 ===================================
6138 00:56:26.882688 ===================================
6139 00:56:26.882790 ANA top config
6140 00:56:26.886207 ===================================
6141 00:56:26.889511 DLL_ASYNC_EN = 0
6142 00:56:26.892666 ALL_SLAVE_EN = 1
6143 00:56:26.892742 NEW_RANK_MODE = 1
6144 00:56:26.896298 DLL_IDLE_MODE = 1
6145 00:56:26.899982 LP45_APHY_COMB_EN = 1
6146 00:56:26.902597 TX_ODT_DIS = 1
6147 00:56:26.902665 NEW_8X_MODE = 1
6148 00:56:26.906079 ===================================
6149 00:56:26.909332 ===================================
6150 00:56:26.912779 data_rate = 800
6151 00:56:26.916260 CKR = 1
6152 00:56:26.919735 DQ_P2S_RATIO = 4
6153 00:56:26.922595 ===================================
6154 00:56:26.926157 CA_P2S_RATIO = 4
6155 00:56:26.929333 DQ_CA_OPEN = 0
6156 00:56:26.929401 DQ_SEMI_OPEN = 1
6157 00:56:26.933035 CA_SEMI_OPEN = 1
6158 00:56:26.936407 CA_FULL_RATE = 0
6159 00:56:26.939720 DQ_CKDIV4_EN = 0
6160 00:56:26.942741 CA_CKDIV4_EN = 1
6161 00:56:26.945929 CA_PREDIV_EN = 0
6162 00:56:26.946072 PH8_DLY = 0
6163 00:56:26.949266 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6164 00:56:26.952799 DQ_AAMCK_DIV = 0
6165 00:56:26.956346 CA_AAMCK_DIV = 0
6166 00:56:26.959787 CA_ADMCK_DIV = 4
6167 00:56:26.962568 DQ_TRACK_CA_EN = 0
6168 00:56:26.962648 CA_PICK = 800
6169 00:56:26.965959 CA_MCKIO = 400
6170 00:56:26.969793 MCKIO_SEMI = 400
6171 00:56:26.972754 PLL_FREQ = 3016
6172 00:56:26.976209 DQ_UI_PI_RATIO = 32
6173 00:56:26.979404 CA_UI_PI_RATIO = 32
6174 00:56:26.982959 ===================================
6175 00:56:26.986495 ===================================
6176 00:56:26.986571 memory_type:LPDDR4
6177 00:56:26.989809 GP_NUM : 10
6178 00:56:26.993345 SRAM_EN : 1
6179 00:56:26.993419 MD32_EN : 0
6180 00:56:26.996292 ===================================
6181 00:56:26.999758 [ANA_INIT] >>>>>>>>>>>>>>
6182 00:56:27.003352 <<<<<< [CONFIGURE PHASE]: ANA_TX
6183 00:56:27.006739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6184 00:56:27.009777 ===================================
6185 00:56:27.013393 data_rate = 800,PCW = 0X7400
6186 00:56:27.016678 ===================================
6187 00:56:27.019649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6188 00:56:27.023198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6189 00:56:27.036465 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6190 00:56:27.039802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6191 00:56:27.043439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6192 00:56:27.046779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6193 00:56:27.049723 [ANA_INIT] flow start
6194 00:56:27.049799 [ANA_INIT] PLL >>>>>>>>
6195 00:56:27.052929 [ANA_INIT] PLL <<<<<<<<
6196 00:56:27.056624 [ANA_INIT] MIDPI >>>>>>>>
6197 00:56:27.060181 [ANA_INIT] MIDPI <<<<<<<<
6198 00:56:27.060273 [ANA_INIT] DLL >>>>>>>>
6199 00:56:27.062906 [ANA_INIT] flow end
6200 00:56:27.066357 ============ LP4 DIFF to SE enter ============
6201 00:56:27.069864 ============ LP4 DIFF to SE exit ============
6202 00:56:27.073162 [ANA_INIT] <<<<<<<<<<<<<
6203 00:56:27.076724 [Flow] Enable top DCM control >>>>>
6204 00:56:27.080110 [Flow] Enable top DCM control <<<<<
6205 00:56:27.083276 Enable DLL master slave shuffle
6206 00:56:27.089863 ==============================================================
6207 00:56:27.089942 Gating Mode config
6208 00:56:27.096263 ==============================================================
6209 00:56:27.096338 Config description:
6210 00:56:27.106270 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6211 00:56:27.112871 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6212 00:56:27.119530 SELPH_MODE 0: By rank 1: By Phase
6213 00:56:27.122982 ==============================================================
6214 00:56:27.126458 GAT_TRACK_EN = 0
6215 00:56:27.129962 RX_GATING_MODE = 2
6216 00:56:27.133323 RX_GATING_TRACK_MODE = 2
6217 00:56:27.136341 SELPH_MODE = 1
6218 00:56:27.139555 PICG_EARLY_EN = 1
6219 00:56:27.142813 VALID_LAT_VALUE = 1
6220 00:56:27.146848 ==============================================================
6221 00:56:27.149588 Enter into Gating configuration >>>>
6222 00:56:27.153053 Exit from Gating configuration <<<<
6223 00:56:27.156456 Enter into DVFS_PRE_config >>>>>
6224 00:56:27.170193 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6225 00:56:27.170290 Exit from DVFS_PRE_config <<<<<
6226 00:56:27.173176 Enter into PICG configuration >>>>
6227 00:56:27.176351 Exit from PICG configuration <<<<
6228 00:56:27.179673 [RX_INPUT] configuration >>>>>
6229 00:56:27.183120 [RX_INPUT] configuration <<<<<
6230 00:56:27.190103 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6231 00:56:27.193228 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6232 00:56:27.199939 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6233 00:56:27.206642 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6234 00:56:27.213338 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6235 00:56:27.219876 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6236 00:56:27.223405 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6237 00:56:27.226842 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6238 00:56:27.230046 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6239 00:56:27.236495 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6240 00:56:27.239716 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6241 00:56:27.243581 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6242 00:56:27.246631 ===================================
6243 00:56:27.249608 LPDDR4 DRAM CONFIGURATION
6244 00:56:27.253157 ===================================
6245 00:56:27.253265 EX_ROW_EN[0] = 0x0
6246 00:56:27.256476 EX_ROW_EN[1] = 0x0
6247 00:56:27.256553 LP4Y_EN = 0x0
6248 00:56:27.259977 WORK_FSP = 0x0
6249 00:56:27.260054 WL = 0x2
6250 00:56:27.263369 RL = 0x2
6251 00:56:27.266806 BL = 0x2
6252 00:56:27.266884 RPST = 0x0
6253 00:56:27.270037 RD_PRE = 0x0
6254 00:56:27.270115 WR_PRE = 0x1
6255 00:56:27.273390 WR_PST = 0x0
6256 00:56:27.273466 DBI_WR = 0x0
6257 00:56:27.276478 DBI_RD = 0x0
6258 00:56:27.276554 OTF = 0x1
6259 00:56:27.279919 ===================================
6260 00:56:27.283137 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6261 00:56:27.289658 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6262 00:56:27.293362 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6263 00:56:27.296604 ===================================
6264 00:56:27.300039 LPDDR4 DRAM CONFIGURATION
6265 00:56:27.303308 ===================================
6266 00:56:27.303383 EX_ROW_EN[0] = 0x10
6267 00:56:27.306871 EX_ROW_EN[1] = 0x0
6268 00:56:27.306946 LP4Y_EN = 0x0
6269 00:56:27.310153 WORK_FSP = 0x0
6270 00:56:27.310228 WL = 0x2
6271 00:56:27.313126 RL = 0x2
6272 00:56:27.313202 BL = 0x2
6273 00:56:27.316373 RPST = 0x0
6274 00:56:27.316489 RD_PRE = 0x0
6275 00:56:27.319771 WR_PRE = 0x1
6276 00:56:27.319846 WR_PST = 0x0
6277 00:56:27.322972 DBI_WR = 0x0
6278 00:56:27.323048 DBI_RD = 0x0
6279 00:56:27.326886 OTF = 0x1
6280 00:56:27.329930 ===================================
6281 00:56:27.336900 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6282 00:56:27.339741 nWR fixed to 30
6283 00:56:27.343556 [ModeRegInit_LP4] CH0 RK0
6284 00:56:27.343633 [ModeRegInit_LP4] CH0 RK1
6285 00:56:27.346592 [ModeRegInit_LP4] CH1 RK0
6286 00:56:27.349716 [ModeRegInit_LP4] CH1 RK1
6287 00:56:27.349807 match AC timing 19
6288 00:56:27.356866 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6289 00:56:27.360499 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6290 00:56:27.363527 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6291 00:56:27.369935 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6292 00:56:27.373495 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6293 00:56:27.373563 ==
6294 00:56:27.376936 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 00:56:27.379789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 00:56:27.379862 ==
6297 00:56:27.386445 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6298 00:56:27.393124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6299 00:56:27.396426 [CA 0] Center 36 (8~64) winsize 57
6300 00:56:27.400074 [CA 1] Center 36 (8~64) winsize 57
6301 00:56:27.400154 [CA 2] Center 36 (8~64) winsize 57
6302 00:56:27.403545 [CA 3] Center 36 (8~64) winsize 57
6303 00:56:27.406366 [CA 4] Center 36 (8~64) winsize 57
6304 00:56:27.410024 [CA 5] Center 36 (8~64) winsize 57
6305 00:56:27.410115
6306 00:56:27.413411 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6307 00:56:27.413473
6308 00:56:27.420199 [CATrainingPosCal] consider 1 rank data
6309 00:56:27.420268 u2DelayCellTimex100 = 270/100 ps
6310 00:56:27.423524 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 00:56:27.430292 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 00:56:27.433515 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 00:56:27.436915 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 00:56:27.440230 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 00:56:27.443557 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 00:56:27.443626
6317 00:56:27.446940 CA PerBit enable=1, Macro0, CA PI delay=36
6318 00:56:27.447012
6319 00:56:27.450351 [CBTSetCACLKResult] CA Dly = 36
6320 00:56:27.450418 CS Dly: 1 (0~32)
6321 00:56:27.453675 ==
6322 00:56:27.456780 Dram Type= 6, Freq= 0, CH_0, rank 1
6323 00:56:27.460214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 00:56:27.460284 ==
6325 00:56:27.463686 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6326 00:56:27.470015 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6327 00:56:27.473338 [CA 0] Center 36 (8~64) winsize 57
6328 00:56:27.476722 [CA 1] Center 36 (8~64) winsize 57
6329 00:56:27.480450 [CA 2] Center 36 (8~64) winsize 57
6330 00:56:27.483666 [CA 3] Center 36 (8~64) winsize 57
6331 00:56:27.487126 [CA 4] Center 36 (8~64) winsize 57
6332 00:56:27.490196 [CA 5] Center 36 (8~64) winsize 57
6333 00:56:27.490264
6334 00:56:27.493436 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6335 00:56:27.493510
6336 00:56:27.496895 [CATrainingPosCal] consider 2 rank data
6337 00:56:27.500450 u2DelayCellTimex100 = 270/100 ps
6338 00:56:27.503766 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 00:56:27.506645 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 00:56:27.510253 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 00:56:27.513580 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 00:56:27.516824 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 00:56:27.523402 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 00:56:27.523485
6345 00:56:27.526411 CA PerBit enable=1, Macro0, CA PI delay=36
6346 00:56:27.526496
6347 00:56:27.530202 [CBTSetCACLKResult] CA Dly = 36
6348 00:56:27.530272 CS Dly: 1 (0~32)
6349 00:56:27.530328
6350 00:56:27.533369 ----->DramcWriteLeveling(PI) begin...
6351 00:56:27.533450 ==
6352 00:56:27.536822 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 00:56:27.540300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 00:56:27.543505 ==
6355 00:56:27.543582 Write leveling (Byte 0): 40 => 8
6356 00:56:27.546582 Write leveling (Byte 1): 32 => 0
6357 00:56:27.550058 DramcWriteLeveling(PI) end<-----
6358 00:56:27.550134
6359 00:56:27.550192 ==
6360 00:56:27.553296 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 00:56:27.559924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 00:56:27.560005 ==
6363 00:56:27.560064 [Gating] SW mode calibration
6364 00:56:27.569809 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6365 00:56:27.573405 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6366 00:56:27.576694 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6367 00:56:27.583304 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6368 00:56:27.586905 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6369 00:56:27.589783 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6370 00:56:27.596568 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6371 00:56:27.600095 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6372 00:56:27.603569 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6373 00:56:27.609746 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6374 00:56:27.613079 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6375 00:56:27.616360 Total UI for P1: 0, mck2ui 16
6376 00:56:27.620027 best dqsien dly found for B0: ( 0, 14, 24)
6377 00:56:27.623706 Total UI for P1: 0, mck2ui 16
6378 00:56:27.626489 best dqsien dly found for B1: ( 0, 14, 24)
6379 00:56:27.629825 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6380 00:56:27.633173 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6381 00:56:27.633277
6382 00:56:27.636676 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6383 00:56:27.639997 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6384 00:56:27.643397 [Gating] SW calibration Done
6385 00:56:27.643481 ==
6386 00:56:27.646783 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 00:56:27.650451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 00:56:27.653205 ==
6389 00:56:27.653310 RX Vref Scan: 0
6390 00:56:27.653402
6391 00:56:27.656390 RX Vref 0 -> 0, step: 1
6392 00:56:27.656494
6393 00:56:27.660105 RX Delay -410 -> 252, step: 16
6394 00:56:27.663230 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6395 00:56:27.666491 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6396 00:56:27.669892 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6397 00:56:27.676983 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6398 00:56:27.680493 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6399 00:56:27.683309 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6400 00:56:27.686591 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6401 00:56:27.693341 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6402 00:56:27.696743 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6403 00:56:27.700186 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6404 00:56:27.703416 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6405 00:56:27.710349 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6406 00:56:27.713748 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6407 00:56:27.716965 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6408 00:56:27.720338 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6409 00:56:27.727360 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6410 00:56:27.727445 ==
6411 00:56:27.730005 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 00:56:27.733545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 00:56:27.733652 ==
6414 00:56:27.733726 DQS Delay:
6415 00:56:27.736767 DQS0 = 43, DQS1 = 51
6416 00:56:27.736873 DQM Delay:
6417 00:56:27.740332 DQM0 = 12, DQM1 = 10
6418 00:56:27.740435 DQ Delay:
6419 00:56:27.743521 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6420 00:56:27.747130 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6421 00:56:27.750010 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6422 00:56:27.753563 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6423 00:56:27.753655
6424 00:56:27.753729
6425 00:56:27.753798 ==
6426 00:56:27.756752 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 00:56:27.760129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 00:56:27.760221 ==
6429 00:56:27.760294
6430 00:56:27.760362
6431 00:56:27.763616 TX Vref Scan disable
6432 00:56:27.763683 == TX Byte 0 ==
6433 00:56:27.770236 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6434 00:56:27.773647 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6435 00:56:27.773745 == TX Byte 1 ==
6436 00:56:27.780251 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6437 00:56:27.783546 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6438 00:56:27.783639 ==
6439 00:56:27.786578 Dram Type= 6, Freq= 0, CH_0, rank 0
6440 00:56:27.789828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 00:56:27.789923 ==
6442 00:56:27.790048
6443 00:56:27.790121
6444 00:56:27.793320 TX Vref Scan disable
6445 00:56:27.793412 == TX Byte 0 ==
6446 00:56:27.800157 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6447 00:56:27.803401 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6448 00:56:27.803470 == TX Byte 1 ==
6449 00:56:27.810244 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6450 00:56:27.813753 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6451 00:56:27.813846
6452 00:56:27.813931 [DATLAT]
6453 00:56:27.817110 Freq=400, CH0 RK0
6454 00:56:27.817200
6455 00:56:27.817282 DATLAT Default: 0xf
6456 00:56:27.820433 0, 0xFFFF, sum = 0
6457 00:56:27.820503 1, 0xFFFF, sum = 0
6458 00:56:27.823903 2, 0xFFFF, sum = 0
6459 00:56:27.823994 3, 0xFFFF, sum = 0
6460 00:56:27.826742 4, 0xFFFF, sum = 0
6461 00:56:27.826809 5, 0xFFFF, sum = 0
6462 00:56:27.830261 6, 0xFFFF, sum = 0
6463 00:56:27.830332 7, 0xFFFF, sum = 0
6464 00:56:27.833599 8, 0xFFFF, sum = 0
6465 00:56:27.837018 9, 0xFFFF, sum = 0
6466 00:56:27.837102 10, 0xFFFF, sum = 0
6467 00:56:27.840542 11, 0xFFFF, sum = 0
6468 00:56:27.840635 12, 0xFFFF, sum = 0
6469 00:56:27.843815 13, 0x0, sum = 1
6470 00:56:27.843885 14, 0x0, sum = 2
6471 00:56:27.847112 15, 0x0, sum = 3
6472 00:56:27.847205 16, 0x0, sum = 4
6473 00:56:27.847291 best_step = 14
6474 00:56:27.847371
6475 00:56:27.850281 ==
6476 00:56:27.850346 Dram Type= 6, Freq= 0, CH_0, rank 0
6477 00:56:27.857020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 00:56:27.857090 ==
6479 00:56:27.857147 RX Vref Scan: 1
6480 00:56:27.857201
6481 00:56:27.860527 RX Vref 0 -> 0, step: 1
6482 00:56:27.860596
6483 00:56:27.863984 RX Delay -343 -> 252, step: 8
6484 00:56:27.864054
6485 00:56:27.866883 Set Vref, RX VrefLevel [Byte0]: 52
6486 00:56:27.870356 [Byte1]: 57
6487 00:56:27.873824
6488 00:56:27.873919 Final RX Vref Byte 0 = 52 to rank0
6489 00:56:27.877229 Final RX Vref Byte 1 = 57 to rank0
6490 00:56:27.880109 Final RX Vref Byte 0 = 52 to rank1
6491 00:56:27.883404 Final RX Vref Byte 1 = 57 to rank1==
6492 00:56:27.887077 Dram Type= 6, Freq= 0, CH_0, rank 0
6493 00:56:27.894009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 00:56:27.894142 ==
6495 00:56:27.894220 DQS Delay:
6496 00:56:27.896987 DQS0 = 44, DQS1 = 60
6497 00:56:27.897095 DQM Delay:
6498 00:56:27.897154 DQM0 = 11, DQM1 = 13
6499 00:56:27.900093 DQ Delay:
6500 00:56:27.903494 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6501 00:56:27.903571 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6502 00:56:27.907013 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =12
6503 00:56:27.910378 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6504 00:56:27.910454
6505 00:56:27.913979
6506 00:56:27.920541 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6507 00:56:27.923717 CH0 RK0: MR19=C0C, MR18=8D5C
6508 00:56:27.930157 CH0_RK0: MR19=0xC0C, MR18=0x8D5C, DQSOSC=392, MR23=63, INC=384, DEC=256
6509 00:56:27.930233 ==
6510 00:56:27.933768 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 00:56:27.937174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 00:56:27.937251 ==
6513 00:56:27.940027 [Gating] SW mode calibration
6514 00:56:27.946764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6515 00:56:27.953586 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6516 00:56:27.957025 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6517 00:56:27.960122 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6518 00:56:27.967070 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6519 00:56:27.970079 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6520 00:56:27.973714 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6521 00:56:27.977171 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6522 00:56:27.983131 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6523 00:56:27.986493 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6524 00:56:27.990495 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6525 00:56:27.993611 Total UI for P1: 0, mck2ui 16
6526 00:56:27.996988 best dqsien dly found for B0: ( 0, 14, 24)
6527 00:56:28.000226 Total UI for P1: 0, mck2ui 16
6528 00:56:28.003426 best dqsien dly found for B1: ( 0, 14, 24)
6529 00:56:28.007193 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6530 00:56:28.009854 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6531 00:56:28.013361
6532 00:56:28.016612 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6533 00:56:28.019957 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6534 00:56:28.023598 [Gating] SW calibration Done
6535 00:56:28.023688 ==
6536 00:56:28.026783 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 00:56:28.030331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 00:56:28.030408 ==
6539 00:56:28.030467 RX Vref Scan: 0
6540 00:56:28.030522
6541 00:56:28.033284 RX Vref 0 -> 0, step: 1
6542 00:56:28.033360
6543 00:56:28.037270 RX Delay -410 -> 252, step: 16
6544 00:56:28.040137 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6545 00:56:28.047004 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6546 00:56:28.050363 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6547 00:56:28.053686 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6548 00:56:28.057169 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6549 00:56:28.063235 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6550 00:56:28.066595 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6551 00:56:28.070162 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6552 00:56:28.073615 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6553 00:56:28.076734 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6554 00:56:28.083549 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6555 00:56:28.087023 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6556 00:56:28.090184 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6557 00:56:28.096957 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6558 00:56:28.100450 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6559 00:56:28.103676 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6560 00:56:28.103752 ==
6561 00:56:28.107027 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 00:56:28.110314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 00:56:28.113368 ==
6564 00:56:28.113451 DQS Delay:
6565 00:56:28.113508 DQS0 = 43, DQS1 = 51
6566 00:56:28.117216 DQM Delay:
6567 00:56:28.117298 DQM0 = 11, DQM1 = 10
6568 00:56:28.120239 DQ Delay:
6569 00:56:28.120321 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6570 00:56:28.123586 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6571 00:56:28.127006 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6572 00:56:28.130360 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6573 00:56:28.130436
6574 00:56:28.130494
6575 00:56:28.130548 ==
6576 00:56:28.133348 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 00:56:28.140404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 00:56:28.140530 ==
6579 00:56:28.140626
6580 00:56:28.140684
6581 00:56:28.140737 TX Vref Scan disable
6582 00:56:28.143271 == TX Byte 0 ==
6583 00:56:28.146791 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6584 00:56:28.150292 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6585 00:56:28.153547 == TX Byte 1 ==
6586 00:56:28.156912 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6587 00:56:28.159978 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6588 00:56:28.160055 ==
6589 00:56:28.163451 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 00:56:28.170074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 00:56:28.170152 ==
6592 00:56:28.170211
6593 00:56:28.170264
6594 00:56:28.170316 TX Vref Scan disable
6595 00:56:28.173426 == TX Byte 0 ==
6596 00:56:28.176928 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6597 00:56:28.180268 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6598 00:56:28.183180 == TX Byte 1 ==
6599 00:56:28.186674 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6600 00:56:28.189856 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6601 00:56:28.189957
6602 00:56:28.193671 [DATLAT]
6603 00:56:28.193746 Freq=400, CH0 RK1
6604 00:56:28.193805
6605 00:56:28.196561 DATLAT Default: 0xe
6606 00:56:28.196637 0, 0xFFFF, sum = 0
6607 00:56:28.200152 1, 0xFFFF, sum = 0
6608 00:56:28.200230 2, 0xFFFF, sum = 0
6609 00:56:28.203628 3, 0xFFFF, sum = 0
6610 00:56:28.203706 4, 0xFFFF, sum = 0
6611 00:56:28.206807 5, 0xFFFF, sum = 0
6612 00:56:28.206913 6, 0xFFFF, sum = 0
6613 00:56:28.210335 7, 0xFFFF, sum = 0
6614 00:56:28.210411 8, 0xFFFF, sum = 0
6615 00:56:28.213423 9, 0xFFFF, sum = 0
6616 00:56:28.213495 10, 0xFFFF, sum = 0
6617 00:56:28.216776 11, 0xFFFF, sum = 0
6618 00:56:28.216871 12, 0xFFFF, sum = 0
6619 00:56:28.219913 13, 0x0, sum = 1
6620 00:56:28.219981 14, 0x0, sum = 2
6621 00:56:28.223521 15, 0x0, sum = 3
6622 00:56:28.223590 16, 0x0, sum = 4
6623 00:56:28.227046 best_step = 14
6624 00:56:28.227115
6625 00:56:28.227170 ==
6626 00:56:28.230378 Dram Type= 6, Freq= 0, CH_0, rank 1
6627 00:56:28.233278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 00:56:28.233356 ==
6629 00:56:28.236893 RX Vref Scan: 0
6630 00:56:28.236968
6631 00:56:28.237028 RX Vref 0 -> 0, step: 1
6632 00:56:28.237082
6633 00:56:28.240026 RX Delay -343 -> 252, step: 8
6634 00:56:28.247855 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6635 00:56:28.251686 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6636 00:56:28.254757 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6637 00:56:28.258170 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6638 00:56:28.264997 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6639 00:56:28.267853 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6640 00:56:28.271167 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6641 00:56:28.274489 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6642 00:56:28.281528 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6643 00:56:28.285111 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6644 00:56:28.288061 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6645 00:56:28.291360 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6646 00:56:28.298330 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6647 00:56:28.301247 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6648 00:56:28.304424 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6649 00:56:28.311513 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6650 00:56:28.311590 ==
6651 00:56:28.314822 Dram Type= 6, Freq= 0, CH_0, rank 1
6652 00:56:28.317651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 00:56:28.317727 ==
6654 00:56:28.317785 DQS Delay:
6655 00:56:28.321193 DQS0 = 48, DQS1 = 56
6656 00:56:28.321269 DQM Delay:
6657 00:56:28.324710 DQM0 = 11, DQM1 = 10
6658 00:56:28.324786 DQ Delay:
6659 00:56:28.327910 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6660 00:56:28.331126 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =16
6661 00:56:28.334449 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6662 00:56:28.337542 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =20
6663 00:56:28.337618
6664 00:56:28.337676
6665 00:56:28.344562 [DQSOSCAuto] RK1, (LSB)MR18= 0x9c71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6666 00:56:28.347819 CH0 RK1: MR19=C0C, MR18=9C71
6667 00:56:28.354684 CH0_RK1: MR19=0xC0C, MR18=0x9C71, DQSOSC=390, MR23=63, INC=388, DEC=258
6668 00:56:28.357992 [RxdqsGatingPostProcess] freq 400
6669 00:56:28.364301 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6670 00:56:28.364378 best DQS0 dly(2T, 0.5T) = (0, 10)
6671 00:56:28.368055 best DQS1 dly(2T, 0.5T) = (0, 10)
6672 00:56:28.371062 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6673 00:56:28.374346 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6674 00:56:28.378015 best DQS0 dly(2T, 0.5T) = (0, 10)
6675 00:56:28.380973 best DQS1 dly(2T, 0.5T) = (0, 10)
6676 00:56:28.384544 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6677 00:56:28.387807 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6678 00:56:28.391227 Pre-setting of DQS Precalculation
6679 00:56:28.397626 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6680 00:56:28.397704 ==
6681 00:56:28.401125 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 00:56:28.404603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 00:56:28.404681 ==
6684 00:56:28.408109 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6685 00:56:28.414643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6686 00:56:28.417913 [CA 0] Center 36 (8~64) winsize 57
6687 00:56:28.421050 [CA 1] Center 36 (8~64) winsize 57
6688 00:56:28.424389 [CA 2] Center 36 (8~64) winsize 57
6689 00:56:28.427792 [CA 3] Center 36 (8~64) winsize 57
6690 00:56:28.431128 [CA 4] Center 36 (8~64) winsize 57
6691 00:56:28.434533 [CA 5] Center 36 (8~64) winsize 57
6692 00:56:28.434612
6693 00:56:28.438090 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6694 00:56:28.438168
6695 00:56:28.441137 [CATrainingPosCal] consider 1 rank data
6696 00:56:28.444679 u2DelayCellTimex100 = 270/100 ps
6697 00:56:28.448174 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 00:56:28.451054 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 00:56:28.454282 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 00:56:28.457830 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 00:56:28.461426 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 00:56:28.467866 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 00:56:28.467944
6704 00:56:28.471113 CA PerBit enable=1, Macro0, CA PI delay=36
6705 00:56:28.471190
6706 00:56:28.474345 [CBTSetCACLKResult] CA Dly = 36
6707 00:56:28.474437 CS Dly: 1 (0~32)
6708 00:56:28.474495 ==
6709 00:56:28.478021 Dram Type= 6, Freq= 0, CH_1, rank 1
6710 00:56:28.481271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 00:56:28.481342 ==
6712 00:56:28.488144 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6713 00:56:28.494715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6714 00:56:28.498208 [CA 0] Center 36 (8~64) winsize 57
6715 00:56:28.501068 [CA 1] Center 36 (8~64) winsize 57
6716 00:56:28.504648 [CA 2] Center 36 (8~64) winsize 57
6717 00:56:28.507874 [CA 3] Center 36 (8~64) winsize 57
6718 00:56:28.511319 [CA 4] Center 36 (8~64) winsize 57
6719 00:56:28.511412 [CA 5] Center 36 (8~64) winsize 57
6720 00:56:28.511494
6721 00:56:28.518029 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6722 00:56:28.518099
6723 00:56:28.521450 [CATrainingPosCal] consider 2 rank data
6724 00:56:28.524380 u2DelayCellTimex100 = 270/100 ps
6725 00:56:28.527827 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 00:56:28.531234 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 00:56:28.534741 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 00:56:28.538128 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 00:56:28.540973 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 00:56:28.544610 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 00:56:28.544700
6732 00:56:28.547935 CA PerBit enable=1, Macro0, CA PI delay=36
6733 00:56:28.548024
6734 00:56:28.551368 [CBTSetCACLKResult] CA Dly = 36
6735 00:56:28.555050 CS Dly: 1 (0~32)
6736 00:56:28.555119
6737 00:56:28.558058 ----->DramcWriteLeveling(PI) begin...
6738 00:56:28.558126 ==
6739 00:56:28.560880 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 00:56:28.564605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 00:56:28.564698 ==
6742 00:56:28.567847 Write leveling (Byte 0): 40 => 8
6743 00:56:28.571329 Write leveling (Byte 1): 40 => 8
6744 00:56:28.574723 DramcWriteLeveling(PI) end<-----
6745 00:56:28.574801
6746 00:56:28.574859 ==
6747 00:56:28.577630 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 00:56:28.581042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 00:56:28.581168 ==
6750 00:56:28.584586 [Gating] SW mode calibration
6751 00:56:28.591600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6752 00:56:28.597729 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6753 00:56:28.601206 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6754 00:56:28.604345 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6755 00:56:28.611186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6756 00:56:28.614617 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6757 00:56:28.617948 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6758 00:56:28.624648 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6759 00:56:28.628287 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6760 00:56:28.631585 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6761 00:56:28.637833 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6762 00:56:28.637926 Total UI for P1: 0, mck2ui 16
6763 00:56:28.641308 best dqsien dly found for B0: ( 0, 14, 24)
6764 00:56:28.644736 Total UI for P1: 0, mck2ui 16
6765 00:56:28.648360 best dqsien dly found for B1: ( 0, 14, 24)
6766 00:56:28.651090 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6767 00:56:28.658461 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6768 00:56:28.658531
6769 00:56:28.661198 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6770 00:56:28.664457 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6771 00:56:28.667849 [Gating] SW calibration Done
6772 00:56:28.667951 ==
6773 00:56:28.671205 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 00:56:28.674548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 00:56:28.674615 ==
6776 00:56:28.678149 RX Vref Scan: 0
6777 00:56:28.678212
6778 00:56:28.678266 RX Vref 0 -> 0, step: 1
6779 00:56:28.678318
6780 00:56:28.681600 RX Delay -410 -> 252, step: 16
6781 00:56:28.684941 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6782 00:56:28.691305 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6783 00:56:28.694655 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6784 00:56:28.698055 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6785 00:56:28.701338 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6786 00:56:28.708489 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6787 00:56:28.711338 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6788 00:56:28.714678 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6789 00:56:28.718288 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6790 00:56:28.724993 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6791 00:56:28.728040 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6792 00:56:28.731435 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6793 00:56:28.734911 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6794 00:56:28.741761 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6795 00:56:28.744784 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6796 00:56:28.748299 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6797 00:56:28.748374 ==
6798 00:56:28.751397 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 00:56:28.754749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 00:56:28.758255 ==
6801 00:56:28.758330 DQS Delay:
6802 00:56:28.758398 DQS0 = 51, DQS1 = 59
6803 00:56:28.761708 DQM Delay:
6804 00:56:28.761783 DQM0 = 19, DQM1 = 16
6805 00:56:28.765112 DQ Delay:
6806 00:56:28.768348 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6807 00:56:28.768423 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6808 00:56:28.771338 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6809 00:56:28.774859 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6810 00:56:28.774935
6811 00:56:28.777677
6812 00:56:28.777751 ==
6813 00:56:28.781040 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 00:56:28.784877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 00:56:28.784952 ==
6816 00:56:28.785010
6817 00:56:28.785064
6818 00:56:28.787929 TX Vref Scan disable
6819 00:56:28.788004 == TX Byte 0 ==
6820 00:56:28.791374 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6821 00:56:28.797724 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6822 00:56:28.797800 == TX Byte 1 ==
6823 00:56:28.801292 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6824 00:56:28.808190 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6825 00:56:28.808279 ==
6826 00:56:28.811604 Dram Type= 6, Freq= 0, CH_1, rank 0
6827 00:56:28.814668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 00:56:28.814769 ==
6829 00:56:28.814855
6830 00:56:28.814941
6831 00:56:28.818057 TX Vref Scan disable
6832 00:56:28.818156 == TX Byte 0 ==
6833 00:56:28.821483 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6834 00:56:28.828072 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6835 00:56:28.828173 == TX Byte 1 ==
6836 00:56:28.831611 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6837 00:56:28.838427 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6838 00:56:28.838570
6839 00:56:28.838713 [DATLAT]
6840 00:56:28.838792 Freq=400, CH1 RK0
6841 00:56:28.838942
6842 00:56:28.841295 DATLAT Default: 0xf
6843 00:56:28.841364 0, 0xFFFF, sum = 0
6844 00:56:28.844705 1, 0xFFFF, sum = 0
6845 00:56:28.844807 2, 0xFFFF, sum = 0
6846 00:56:28.848232 3, 0xFFFF, sum = 0
6847 00:56:28.848328 4, 0xFFFF, sum = 0
6848 00:56:28.851646 5, 0xFFFF, sum = 0
6849 00:56:28.854654 6, 0xFFFF, sum = 0
6850 00:56:28.854754 7, 0xFFFF, sum = 0
6851 00:56:28.858396 8, 0xFFFF, sum = 0
6852 00:56:28.858494 9, 0xFFFF, sum = 0
6853 00:56:28.861325 10, 0xFFFF, sum = 0
6854 00:56:28.861422 11, 0xFFFF, sum = 0
6855 00:56:28.864852 12, 0xFFFF, sum = 0
6856 00:56:28.864947 13, 0x0, sum = 1
6857 00:56:28.868191 14, 0x0, sum = 2
6858 00:56:28.868287 15, 0x0, sum = 3
6859 00:56:28.871462 16, 0x0, sum = 4
6860 00:56:28.871557 best_step = 14
6861 00:56:28.871643
6862 00:56:28.871725 ==
6863 00:56:28.874919 Dram Type= 6, Freq= 0, CH_1, rank 0
6864 00:56:28.878342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 00:56:28.878438 ==
6866 00:56:28.881819 RX Vref Scan: 1
6867 00:56:28.881917
6868 00:56:28.884705 RX Vref 0 -> 0, step: 1
6869 00:56:28.884799
6870 00:56:28.884886 RX Delay -359 -> 252, step: 8
6871 00:56:28.884972
6872 00:56:28.888265 Set Vref, RX VrefLevel [Byte0]: 52
6873 00:56:28.891513 [Byte1]: 52
6874 00:56:28.896751
6875 00:56:28.896845 Final RX Vref Byte 0 = 52 to rank0
6876 00:56:28.900751 Final RX Vref Byte 1 = 52 to rank0
6877 00:56:28.903971 Final RX Vref Byte 0 = 52 to rank1
6878 00:56:28.907182 Final RX Vref Byte 1 = 52 to rank1==
6879 00:56:28.910688 Dram Type= 6, Freq= 0, CH_1, rank 0
6880 00:56:28.913605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 00:56:28.916992 ==
6882 00:56:28.917079 DQS Delay:
6883 00:56:28.917155 DQS0 = 48, DQS1 = 60
6884 00:56:28.920482 DQM Delay:
6885 00:56:28.920567 DQM0 = 12, DQM1 = 12
6886 00:56:28.923920 DQ Delay:
6887 00:56:28.927541 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6888 00:56:28.927607 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6889 00:56:28.930602 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6890 00:56:28.934017 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6891 00:56:28.934075
6892 00:56:28.934127
6893 00:56:28.943957 [DQSOSCAuto] RK0, (LSB)MR18= 0x953c, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
6894 00:56:28.947013 CH1 RK0: MR19=C0C, MR18=953C
6895 00:56:28.954231 CH1_RK0: MR19=0xC0C, MR18=0x953C, DQSOSC=391, MR23=63, INC=386, DEC=257
6896 00:56:28.954309 ==
6897 00:56:28.957153 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 00:56:28.960413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 00:56:28.960490 ==
6900 00:56:28.964098 [Gating] SW mode calibration
6901 00:56:28.970669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6902 00:56:28.974312 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6903 00:56:28.980673 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6904 00:56:28.984180 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6905 00:56:28.987622 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6906 00:56:28.994572 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6907 00:56:28.997419 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6908 00:56:29.000935 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6909 00:56:29.007720 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6910 00:56:29.010908 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6911 00:56:29.014361 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6912 00:56:29.017409 Total UI for P1: 0, mck2ui 16
6913 00:56:29.020892 best dqsien dly found for B0: ( 0, 14, 24)
6914 00:56:29.024225 Total UI for P1: 0, mck2ui 16
6915 00:56:29.027835 best dqsien dly found for B1: ( 0, 14, 24)
6916 00:56:29.030904 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6917 00:56:29.034250 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6918 00:56:29.034326
6919 00:56:29.037414 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6920 00:56:29.044086 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6921 00:56:29.044162 [Gating] SW calibration Done
6922 00:56:29.044220 ==
6923 00:56:29.047562 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 00:56:29.054288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 00:56:29.054365 ==
6926 00:56:29.054422 RX Vref Scan: 0
6927 00:56:29.054476
6928 00:56:29.057828 RX Vref 0 -> 0, step: 1
6929 00:56:29.057902
6930 00:56:29.061176 RX Delay -410 -> 252, step: 16
6931 00:56:29.064047 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6932 00:56:29.067602 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6933 00:56:29.074370 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6934 00:56:29.077679 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6935 00:56:29.081008 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6936 00:56:29.084378 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6937 00:56:29.087719 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6938 00:56:29.094418 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6939 00:56:29.097323 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6940 00:56:29.101049 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6941 00:56:29.104224 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6942 00:56:29.110851 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6943 00:56:29.114532 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6944 00:56:29.117352 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6945 00:56:29.124388 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6946 00:56:29.127841 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6947 00:56:29.127932 ==
6948 00:56:29.130878 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 00:56:29.134293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 00:56:29.134360 ==
6951 00:56:29.137785 DQS Delay:
6952 00:56:29.137872 DQS0 = 51, DQS1 = 59
6953 00:56:29.137961 DQM Delay:
6954 00:56:29.141146 DQM0 = 16, DQM1 = 19
6955 00:56:29.141209 DQ Delay:
6956 00:56:29.144324 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6957 00:56:29.147988 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6958 00:56:29.150785 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6959 00:56:29.154102 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6960 00:56:29.154166
6961 00:56:29.154238
6962 00:56:29.154305 ==
6963 00:56:29.157412 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 00:56:29.160869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 00:56:29.160956 ==
6966 00:56:29.164385
6967 00:56:29.164471
6968 00:56:29.164558 TX Vref Scan disable
6969 00:56:29.167786 == TX Byte 0 ==
6970 00:56:29.171078 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6971 00:56:29.174679 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6972 00:56:29.177743 == TX Byte 1 ==
6973 00:56:29.181023 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6974 00:56:29.184525 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6975 00:56:29.184595 ==
6976 00:56:29.187791 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 00:56:29.191408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 00:56:29.191475 ==
6979 00:56:29.194455
6980 00:56:29.194545
6981 00:56:29.194636 TX Vref Scan disable
6982 00:56:29.197609 == TX Byte 0 ==
6983 00:56:29.201840 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6984 00:56:29.204167 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6985 00:56:29.208075 == TX Byte 1 ==
6986 00:56:29.211038 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6987 00:56:29.214414 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6988 00:56:29.214481
6989 00:56:29.214552 [DATLAT]
6990 00:56:29.217717 Freq=400, CH1 RK1
6991 00:56:29.217804
6992 00:56:29.217894 DATLAT Default: 0xe
6993 00:56:29.221110 0, 0xFFFF, sum = 0
6994 00:56:29.221176 1, 0xFFFF, sum = 0
6995 00:56:29.224791 2, 0xFFFF, sum = 0
6996 00:56:29.227531 3, 0xFFFF, sum = 0
6997 00:56:29.227600 4, 0xFFFF, sum = 0
6998 00:56:29.231095 5, 0xFFFF, sum = 0
6999 00:56:29.231166 6, 0xFFFF, sum = 0
7000 00:56:29.234364 7, 0xFFFF, sum = 0
7001 00:56:29.234429 8, 0xFFFF, sum = 0
7002 00:56:29.237854 9, 0xFFFF, sum = 0
7003 00:56:29.237946 10, 0xFFFF, sum = 0
7004 00:56:29.240668 11, 0xFFFF, sum = 0
7005 00:56:29.240735 12, 0xFFFF, sum = 0
7006 00:56:29.244647 13, 0x0, sum = 1
7007 00:56:29.244713 14, 0x0, sum = 2
7008 00:56:29.247496 15, 0x0, sum = 3
7009 00:56:29.247564 16, 0x0, sum = 4
7010 00:56:29.251145 best_step = 14
7011 00:56:29.251212
7012 00:56:29.251283 ==
7013 00:56:29.254307 Dram Type= 6, Freq= 0, CH_1, rank 1
7014 00:56:29.257619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7015 00:56:29.257691 ==
7016 00:56:29.257774 RX Vref Scan: 0
7017 00:56:29.257862
7018 00:56:29.260976 RX Vref 0 -> 0, step: 1
7019 00:56:29.261042
7020 00:56:29.264380 RX Delay -359 -> 252, step: 8
7021 00:56:29.271884 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
7022 00:56:29.274830 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7023 00:56:29.278204 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7024 00:56:29.281553 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7025 00:56:29.288592 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
7026 00:56:29.291737 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7027 00:56:29.294983 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7028 00:56:29.298568 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7029 00:56:29.304820 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7030 00:56:29.308363 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7031 00:56:29.311669 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7032 00:56:29.314919 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7033 00:56:29.321797 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
7034 00:56:29.325182 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7035 00:56:29.328164 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7036 00:56:29.335151 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7037 00:56:29.335241 ==
7038 00:56:29.338495 Dram Type= 6, Freq= 0, CH_1, rank 1
7039 00:56:29.341818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7040 00:56:29.341911 ==
7041 00:56:29.342034 DQS Delay:
7042 00:56:29.345328 DQS0 = 52, DQS1 = 56
7043 00:56:29.345420 DQM Delay:
7044 00:56:29.348141 DQM0 = 12, DQM1 = 9
7045 00:56:29.348230 DQ Delay:
7046 00:56:29.351593 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
7047 00:56:29.354886 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7048 00:56:29.358510 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7049 00:56:29.361641 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
7050 00:56:29.361728
7051 00:56:29.361818
7052 00:56:29.368680 [DQSOSCAuto] RK1, (LSB)MR18= 0x7f96, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 393 ps
7053 00:56:29.371498 CH1 RK1: MR19=C0C, MR18=7F96
7054 00:56:29.378362 CH1_RK1: MR19=0xC0C, MR18=0x7F96, DQSOSC=391, MR23=63, INC=386, DEC=257
7055 00:56:29.381729 [RxdqsGatingPostProcess] freq 400
7056 00:56:29.385042 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7057 00:56:29.388371 best DQS0 dly(2T, 0.5T) = (0, 10)
7058 00:56:29.391713 best DQS1 dly(2T, 0.5T) = (0, 10)
7059 00:56:29.395452 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7060 00:56:29.398792 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7061 00:56:29.402171 best DQS0 dly(2T, 0.5T) = (0, 10)
7062 00:56:29.404946 best DQS1 dly(2T, 0.5T) = (0, 10)
7063 00:56:29.408452 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7064 00:56:29.411830 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7065 00:56:29.415268 Pre-setting of DQS Precalculation
7066 00:56:29.418548 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7067 00:56:29.425055 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7068 00:56:29.435085 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7069 00:56:29.435162
7070 00:56:29.435238
7071 00:56:29.438622 [Calibration Summary] 800 Mbps
7072 00:56:29.438716 CH 0, Rank 0
7073 00:56:29.441896 SW Impedance : PASS
7074 00:56:29.441966 DUTY Scan : NO K
7075 00:56:29.445078 ZQ Calibration : PASS
7076 00:56:29.445174 Jitter Meter : NO K
7077 00:56:29.448514 CBT Training : PASS
7078 00:56:29.451821 Write leveling : PASS
7079 00:56:29.451916 RX DQS gating : PASS
7080 00:56:29.455236 RX DQ/DQS(RDDQC) : PASS
7081 00:56:29.458668 TX DQ/DQS : PASS
7082 00:56:29.458738 RX DATLAT : PASS
7083 00:56:29.461923 RX DQ/DQS(Engine): PASS
7084 00:56:29.465222 TX OE : NO K
7085 00:56:29.465314 All Pass.
7086 00:56:29.465404
7087 00:56:29.465494 CH 0, Rank 1
7088 00:56:29.468532 SW Impedance : PASS
7089 00:56:29.471821 DUTY Scan : NO K
7090 00:56:29.471891 ZQ Calibration : PASS
7091 00:56:29.475402 Jitter Meter : NO K
7092 00:56:29.478719 CBT Training : PASS
7093 00:56:29.478787 Write leveling : NO K
7094 00:56:29.482160 RX DQS gating : PASS
7095 00:56:29.485161 RX DQ/DQS(RDDQC) : PASS
7096 00:56:29.485238 TX DQ/DQS : PASS
7097 00:56:29.488416 RX DATLAT : PASS
7098 00:56:29.488487 RX DQ/DQS(Engine): PASS
7099 00:56:29.492243 TX OE : NO K
7100 00:56:29.492337 All Pass.
7101 00:56:29.492430
7102 00:56:29.495231 CH 1, Rank 0
7103 00:56:29.495299 SW Impedance : PASS
7104 00:56:29.498403 DUTY Scan : NO K
7105 00:56:29.501715 ZQ Calibration : PASS
7106 00:56:29.501818 Jitter Meter : NO K
7107 00:56:29.505403 CBT Training : PASS
7108 00:56:29.508700 Write leveling : PASS
7109 00:56:29.508775 RX DQS gating : PASS
7110 00:56:29.512133 RX DQ/DQS(RDDQC) : PASS
7111 00:56:29.515573 TX DQ/DQS : PASS
7112 00:56:29.515648 RX DATLAT : PASS
7113 00:56:29.518927 RX DQ/DQS(Engine): PASS
7114 00:56:29.521847 TX OE : NO K
7115 00:56:29.521961 All Pass.
7116 00:56:29.522049
7117 00:56:29.522104 CH 1, Rank 1
7118 00:56:29.525390 SW Impedance : PASS
7119 00:56:29.528439 DUTY Scan : NO K
7120 00:56:29.528514 ZQ Calibration : PASS
7121 00:56:29.531933 Jitter Meter : NO K
7122 00:56:29.532008 CBT Training : PASS
7123 00:56:29.535436 Write leveling : NO K
7124 00:56:29.539109 RX DQS gating : PASS
7125 00:56:29.539183 RX DQ/DQS(RDDQC) : PASS
7126 00:56:29.541923 TX DQ/DQS : PASS
7127 00:56:29.545301 RX DATLAT : PASS
7128 00:56:29.545376 RX DQ/DQS(Engine): PASS
7129 00:56:29.548881 TX OE : NO K
7130 00:56:29.548955 All Pass.
7131 00:56:29.549012
7132 00:56:29.552213 DramC Write-DBI off
7133 00:56:29.555398 PER_BANK_REFRESH: Hybrid Mode
7134 00:56:29.555473 TX_TRACKING: ON
7135 00:56:29.565357 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7136 00:56:29.568806 [FAST_K] Save calibration result to emmc
7137 00:56:29.572028 dramc_set_vcore_voltage set vcore to 725000
7138 00:56:29.575731 Read voltage for 1600, 0
7139 00:56:29.575805 Vio18 = 0
7140 00:56:29.575862 Vcore = 725000
7141 00:56:29.578717 Vdram = 0
7142 00:56:29.578792 Vddq = 0
7143 00:56:29.578850 Vmddr = 0
7144 00:56:29.585735 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7145 00:56:29.589082 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7146 00:56:29.592509 MEM_TYPE=3, freq_sel=13
7147 00:56:29.595737 sv_algorithm_assistance_LP4_3733
7148 00:56:29.599055 ============ PULL DRAM RESETB DOWN ============
7149 00:56:29.602410 ========== PULL DRAM RESETB DOWN end =========
7150 00:56:29.608989 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7151 00:56:29.612119 ===================================
7152 00:56:29.612194 LPDDR4 DRAM CONFIGURATION
7153 00:56:29.615413 ===================================
7154 00:56:29.618843 EX_ROW_EN[0] = 0x0
7155 00:56:29.622385 EX_ROW_EN[1] = 0x0
7156 00:56:29.622460 LP4Y_EN = 0x0
7157 00:56:29.625602 WORK_FSP = 0x1
7158 00:56:29.625676 WL = 0x5
7159 00:56:29.628979 RL = 0x5
7160 00:56:29.629054 BL = 0x2
7161 00:56:29.632694 RPST = 0x0
7162 00:56:29.632769 RD_PRE = 0x0
7163 00:56:29.635527 WR_PRE = 0x1
7164 00:56:29.635602 WR_PST = 0x1
7165 00:56:29.639025 DBI_WR = 0x0
7166 00:56:29.639099 DBI_RD = 0x0
7167 00:56:29.642411 OTF = 0x1
7168 00:56:29.645461 ===================================
7169 00:56:29.649207 ===================================
7170 00:56:29.649283 ANA top config
7171 00:56:29.652833 ===================================
7172 00:56:29.655593 DLL_ASYNC_EN = 0
7173 00:56:29.659062 ALL_SLAVE_EN = 0
7174 00:56:29.659152 NEW_RANK_MODE = 1
7175 00:56:29.662373 DLL_IDLE_MODE = 1
7176 00:56:29.665768 LP45_APHY_COMB_EN = 1
7177 00:56:29.668697 TX_ODT_DIS = 0
7178 00:56:29.672354 NEW_8X_MODE = 1
7179 00:56:29.675765 ===================================
7180 00:56:29.678589 ===================================
7181 00:56:29.678655 data_rate = 3200
7182 00:56:29.682223 CKR = 1
7183 00:56:29.685626 DQ_P2S_RATIO = 8
7184 00:56:29.689345 ===================================
7185 00:56:29.692154 CA_P2S_RATIO = 8
7186 00:56:29.696030 DQ_CA_OPEN = 0
7187 00:56:29.699185 DQ_SEMI_OPEN = 0
7188 00:56:29.699249 CA_SEMI_OPEN = 0
7189 00:56:29.702596 CA_FULL_RATE = 0
7190 00:56:29.705922 DQ_CKDIV4_EN = 0
7191 00:56:29.709284 CA_CKDIV4_EN = 0
7192 00:56:29.712015 CA_PREDIV_EN = 0
7193 00:56:29.715546 PH8_DLY = 12
7194 00:56:29.715610 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7195 00:56:29.719291 DQ_AAMCK_DIV = 4
7196 00:56:29.721952 CA_AAMCK_DIV = 4
7197 00:56:29.725366 CA_ADMCK_DIV = 4
7198 00:56:29.728792 DQ_TRACK_CA_EN = 0
7199 00:56:29.732373 CA_PICK = 1600
7200 00:56:29.732439 CA_MCKIO = 1600
7201 00:56:29.735651 MCKIO_SEMI = 0
7202 00:56:29.738819 PLL_FREQ = 3068
7203 00:56:29.742340 DQ_UI_PI_RATIO = 32
7204 00:56:29.745619 CA_UI_PI_RATIO = 0
7205 00:56:29.749005 ===================================
7206 00:56:29.752571 ===================================
7207 00:56:29.755536 memory_type:LPDDR4
7208 00:56:29.755601 GP_NUM : 10
7209 00:56:29.758822 SRAM_EN : 1
7210 00:56:29.758886 MD32_EN : 0
7211 00:56:29.762039 ===================================
7212 00:56:29.765478 [ANA_INIT] >>>>>>>>>>>>>>
7213 00:56:29.768868 <<<<<< [CONFIGURE PHASE]: ANA_TX
7214 00:56:29.772237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7215 00:56:29.775557 ===================================
7216 00:56:29.778734 data_rate = 3200,PCW = 0X7600
7217 00:56:29.782159 ===================================
7218 00:56:29.785636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7219 00:56:29.788746 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7220 00:56:29.795505 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7221 00:56:29.798824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7222 00:56:29.805737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7223 00:56:29.809225 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7224 00:56:29.809317 [ANA_INIT] flow start
7225 00:56:29.812684 [ANA_INIT] PLL >>>>>>>>
7226 00:56:29.815814 [ANA_INIT] PLL <<<<<<<<
7227 00:56:29.815881 [ANA_INIT] MIDPI >>>>>>>>
7228 00:56:29.819361 [ANA_INIT] MIDPI <<<<<<<<
7229 00:56:29.822503 [ANA_INIT] DLL >>>>>>>>
7230 00:56:29.822569 [ANA_INIT] DLL <<<<<<<<
7231 00:56:29.825606 [ANA_INIT] flow end
7232 00:56:29.829304 ============ LP4 DIFF to SE enter ============
7233 00:56:29.832548 ============ LP4 DIFF to SE exit ============
7234 00:56:29.835987 [ANA_INIT] <<<<<<<<<<<<<
7235 00:56:29.839413 [Flow] Enable top DCM control >>>>>
7236 00:56:29.842635 [Flow] Enable top DCM control <<<<<
7237 00:56:29.846121 Enable DLL master slave shuffle
7238 00:56:29.852334 ==============================================================
7239 00:56:29.852409 Gating Mode config
7240 00:56:29.859082 ==============================================================
7241 00:56:29.859157 Config description:
7242 00:56:29.869124 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7243 00:56:29.875943 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7244 00:56:29.882427 SELPH_MODE 0: By rank 1: By Phase
7245 00:56:29.885949 ==============================================================
7246 00:56:29.889551 GAT_TRACK_EN = 1
7247 00:56:29.892622 RX_GATING_MODE = 2
7248 00:56:29.895440 RX_GATING_TRACK_MODE = 2
7249 00:56:29.898883 SELPH_MODE = 1
7250 00:56:29.902347 PICG_EARLY_EN = 1
7251 00:56:29.905966 VALID_LAT_VALUE = 1
7252 00:56:29.909269 ==============================================================
7253 00:56:29.912379 Enter into Gating configuration >>>>
7254 00:56:29.915573 Exit from Gating configuration <<<<
7255 00:56:29.918772 Enter into DVFS_PRE_config >>>>>
7256 00:56:29.932425 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7257 00:56:29.935515 Exit from DVFS_PRE_config <<<<<
7258 00:56:29.938976 Enter into PICG configuration >>>>
7259 00:56:29.939050 Exit from PICG configuration <<<<
7260 00:56:29.942232 [RX_INPUT] configuration >>>>>
7261 00:56:29.945934 [RX_INPUT] configuration <<<<<
7262 00:56:29.952450 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7263 00:56:29.955839 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7264 00:56:29.962999 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7265 00:56:29.969145 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7266 00:56:29.975720 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7267 00:56:29.982688 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7268 00:56:29.986151 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7269 00:56:29.989158 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7270 00:56:29.992950 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7271 00:56:29.999501 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7272 00:56:30.003048 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7273 00:56:30.006030 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7274 00:56:30.009083 ===================================
7275 00:56:30.012576 LPDDR4 DRAM CONFIGURATION
7276 00:56:30.015952 ===================================
7277 00:56:30.016027 EX_ROW_EN[0] = 0x0
7278 00:56:30.019358 EX_ROW_EN[1] = 0x0
7279 00:56:30.019432 LP4Y_EN = 0x0
7280 00:56:30.022370 WORK_FSP = 0x1
7281 00:56:30.025858 WL = 0x5
7282 00:56:30.025932 RL = 0x5
7283 00:56:30.029232 BL = 0x2
7284 00:56:30.029306 RPST = 0x0
7285 00:56:30.032510 RD_PRE = 0x0
7286 00:56:30.032584 WR_PRE = 0x1
7287 00:56:30.035905 WR_PST = 0x1
7288 00:56:30.035980 DBI_WR = 0x0
7289 00:56:30.039735 DBI_RD = 0x0
7290 00:56:30.039810 OTF = 0x1
7291 00:56:30.042734 ===================================
7292 00:56:30.046170 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7293 00:56:30.052910 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7294 00:56:30.055725 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7295 00:56:30.059202 ===================================
7296 00:56:30.062775 LPDDR4 DRAM CONFIGURATION
7297 00:56:30.066225 ===================================
7298 00:56:30.066301 EX_ROW_EN[0] = 0x10
7299 00:56:30.069373 EX_ROW_EN[1] = 0x0
7300 00:56:30.069448 LP4Y_EN = 0x0
7301 00:56:30.072878 WORK_FSP = 0x1
7302 00:56:30.072953 WL = 0x5
7303 00:56:30.076155 RL = 0x5
7304 00:56:30.076230 BL = 0x2
7305 00:56:30.079265 RPST = 0x0
7306 00:56:30.079340 RD_PRE = 0x0
7307 00:56:30.082534 WR_PRE = 0x1
7308 00:56:30.086029 WR_PST = 0x1
7309 00:56:30.086103 DBI_WR = 0x0
7310 00:56:30.088897 DBI_RD = 0x0
7311 00:56:30.088971 OTF = 0x1
7312 00:56:30.092434 ===================================
7313 00:56:30.099309 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7314 00:56:30.099385 ==
7315 00:56:30.102875 Dram Type= 6, Freq= 0, CH_0, rank 0
7316 00:56:30.105751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7317 00:56:30.105826 ==
7318 00:56:30.109373 [Duty_Offset_Calibration]
7319 00:56:30.109447 B0:2 B1:-1 CA:1
7320 00:56:30.109504
7321 00:56:30.112729 [DutyScan_Calibration_Flow] k_type=0
7322 00:56:30.123180
7323 00:56:30.123253 ==CLK 0==
7324 00:56:30.126585 Final CLK duty delay cell = -4
7325 00:56:30.129711 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7326 00:56:30.133248 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7327 00:56:30.136451 [-4] AVG Duty = 4937%(X100)
7328 00:56:30.136526
7329 00:56:30.139758 CH0 CLK Duty spec in!! Max-Min= 187%
7330 00:56:30.142985 [DutyScan_Calibration_Flow] ====Done====
7331 00:56:30.143060
7332 00:56:30.146563 [DutyScan_Calibration_Flow] k_type=1
7333 00:56:30.162564
7334 00:56:30.162640 ==DQS 0 ==
7335 00:56:30.165850 Final DQS duty delay cell = 0
7336 00:56:30.169162 [0] MAX Duty = 5125%(X100), DQS PI = 22
7337 00:56:30.172472 [0] MIN Duty = 5000%(X100), DQS PI = 14
7338 00:56:30.172581 [0] AVG Duty = 5062%(X100)
7339 00:56:30.175759
7340 00:56:30.175826 ==DQS 1 ==
7341 00:56:30.179207 Final DQS duty delay cell = -4
7342 00:56:30.182380 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7343 00:56:30.185770 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7344 00:56:30.189171 [-4] AVG Duty = 5046%(X100)
7345 00:56:30.189245
7346 00:56:30.192605 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7347 00:56:30.192677
7348 00:56:30.196000 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7349 00:56:30.199490 [DutyScan_Calibration_Flow] ====Done====
7350 00:56:30.199565
7351 00:56:30.202244 [DutyScan_Calibration_Flow] k_type=3
7352 00:56:30.219531
7353 00:56:30.219599 ==DQM 0 ==
7354 00:56:30.223013 Final DQM duty delay cell = 0
7355 00:56:30.226274 [0] MAX Duty = 5000%(X100), DQS PI = 18
7356 00:56:30.229860 [0] MIN Duty = 4875%(X100), DQS PI = 4
7357 00:56:30.229954 [0] AVG Duty = 4937%(X100)
7358 00:56:30.232946
7359 00:56:30.233009 ==DQM 1 ==
7360 00:56:30.236364 Final DQM duty delay cell = 0
7361 00:56:30.239914 [0] MAX Duty = 5187%(X100), DQS PI = 58
7362 00:56:30.242889 [0] MIN Duty = 4969%(X100), DQS PI = 18
7363 00:56:30.242981 [0] AVG Duty = 5078%(X100)
7364 00:56:30.246347
7365 00:56:30.249653 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7366 00:56:30.249727
7367 00:56:30.253328 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7368 00:56:30.256596 [DutyScan_Calibration_Flow] ====Done====
7369 00:56:30.256681
7370 00:56:30.259718 [DutyScan_Calibration_Flow] k_type=2
7371 00:56:30.276971
7372 00:56:30.277062 ==DQ 0 ==
7373 00:56:30.280241 Final DQ duty delay cell = 0
7374 00:56:30.283738 [0] MAX Duty = 5156%(X100), DQS PI = 0
7375 00:56:30.286672 [0] MIN Duty = 5031%(X100), DQS PI = 12
7376 00:56:30.286761 [0] AVG Duty = 5093%(X100)
7377 00:56:30.286840
7378 00:56:30.290162 ==DQ 1 ==
7379 00:56:30.293435 Final DQ duty delay cell = 0
7380 00:56:30.296902 [0] MAX Duty = 5000%(X100), DQS PI = 0
7381 00:56:30.300227 [0] MIN Duty = 4907%(X100), DQS PI = 18
7382 00:56:30.300302 [0] AVG Duty = 4953%(X100)
7383 00:56:30.300359
7384 00:56:30.304006 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7385 00:56:30.304080
7386 00:56:30.306912 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7387 00:56:30.313434 [DutyScan_Calibration_Flow] ====Done====
7388 00:56:30.313509 ==
7389 00:56:30.316976 Dram Type= 6, Freq= 0, CH_1, rank 0
7390 00:56:30.320361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7391 00:56:30.320435 ==
7392 00:56:30.323746 [Duty_Offset_Calibration]
7393 00:56:30.323819 B0:1 B1:1 CA:2
7394 00:56:30.323877
7395 00:56:30.326634 [DutyScan_Calibration_Flow] k_type=0
7396 00:56:30.336756
7397 00:56:30.336829 ==CLK 0==
7398 00:56:30.340016 Final CLK duty delay cell = 0
7399 00:56:30.343269 [0] MAX Duty = 5187%(X100), DQS PI = 24
7400 00:56:30.346814 [0] MIN Duty = 4938%(X100), DQS PI = 50
7401 00:56:30.346915 [0] AVG Duty = 5062%(X100)
7402 00:56:30.350056
7403 00:56:30.353372 CH1 CLK Duty spec in!! Max-Min= 249%
7404 00:56:30.356672 [DutyScan_Calibration_Flow] ====Done====
7405 00:56:30.356746
7406 00:56:30.360186 [DutyScan_Calibration_Flow] k_type=1
7407 00:56:30.376577
7408 00:56:30.376652 ==DQS 0 ==
7409 00:56:30.379699 Final DQS duty delay cell = 0
7410 00:56:30.383144 [0] MAX Duty = 5062%(X100), DQS PI = 22
7411 00:56:30.386769 [0] MIN Duty = 4813%(X100), DQS PI = 52
7412 00:56:30.386862 [0] AVG Duty = 4937%(X100)
7413 00:56:30.389905
7414 00:56:30.389984 ==DQS 1 ==
7415 00:56:30.393109 Final DQS duty delay cell = 0
7416 00:56:30.396749 [0] MAX Duty = 5031%(X100), DQS PI = 34
7417 00:56:30.399639 [0] MIN Duty = 4938%(X100), DQS PI = 14
7418 00:56:30.403120 [0] AVG Duty = 4984%(X100)
7419 00:56:30.403201
7420 00:56:30.406175 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7421 00:56:30.406250
7422 00:56:30.409746 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7423 00:56:30.413223 [DutyScan_Calibration_Flow] ====Done====
7424 00:56:30.413298
7425 00:56:30.416625 [DutyScan_Calibration_Flow] k_type=3
7426 00:56:30.433190
7427 00:56:30.433264 ==DQM 0 ==
7428 00:56:30.436568 Final DQM duty delay cell = 0
7429 00:56:30.440048 [0] MAX Duty = 5156%(X100), DQS PI = 20
7430 00:56:30.443255 [0] MIN Duty = 4844%(X100), DQS PI = 50
7431 00:56:30.443330 [0] AVG Duty = 5000%(X100)
7432 00:56:30.446660
7433 00:56:30.446734 ==DQM 1 ==
7434 00:56:30.449906 Final DQM duty delay cell = 0
7435 00:56:30.453206 [0] MAX Duty = 5125%(X100), DQS PI = 8
7436 00:56:30.456656 [0] MIN Duty = 4875%(X100), DQS PI = 22
7437 00:56:30.456731 [0] AVG Duty = 5000%(X100)
7438 00:56:30.459946
7439 00:56:30.463141 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7440 00:56:30.463216
7441 00:56:30.466961 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7442 00:56:30.469791 [DutyScan_Calibration_Flow] ====Done====
7443 00:56:30.469866
7444 00:56:30.473163 [DutyScan_Calibration_Flow] k_type=2
7445 00:56:30.489866
7446 00:56:30.489971 ==DQ 0 ==
7447 00:56:30.493915 Final DQ duty delay cell = 0
7448 00:56:30.496692 [0] MAX Duty = 5156%(X100), DQS PI = 20
7449 00:56:30.500067 [0] MIN Duty = 4907%(X100), DQS PI = 52
7450 00:56:30.500143 [0] AVG Duty = 5031%(X100)
7451 00:56:30.500201
7452 00:56:30.503232 ==DQ 1 ==
7453 00:56:30.506982 Final DQ duty delay cell = 0
7454 00:56:30.510837 [0] MAX Duty = 5093%(X100), DQS PI = 6
7455 00:56:30.513239 [0] MIN Duty = 5031%(X100), DQS PI = 0
7456 00:56:30.513315 [0] AVG Duty = 5062%(X100)
7457 00:56:30.513373
7458 00:56:30.517096 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7459 00:56:30.517277
7460 00:56:30.519902 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7461 00:56:30.526950 [DutyScan_Calibration_Flow] ====Done====
7462 00:56:30.529797 nWR fixed to 30
7463 00:56:30.529896 [ModeRegInit_LP4] CH0 RK0
7464 00:56:30.533282 [ModeRegInit_LP4] CH0 RK1
7465 00:56:30.536709 [ModeRegInit_LP4] CH1 RK0
7466 00:56:30.536784 [ModeRegInit_LP4] CH1 RK1
7467 00:56:30.540277 match AC timing 5
7468 00:56:30.543873 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7469 00:56:30.547224 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7470 00:56:30.553409 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7471 00:56:30.557147 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7472 00:56:30.563525 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7473 00:56:30.563601 [MiockJmeterHQA]
7474 00:56:30.563659
7475 00:56:30.566712 [DramcMiockJmeter] u1RxGatingPI = 0
7476 00:56:30.566787 0 : 4255, 4029
7477 00:56:30.570052 4 : 4253, 4027
7478 00:56:30.570129 8 : 4370, 4142
7479 00:56:30.573659 12 : 4257, 4029
7480 00:56:30.573734 16 : 4255, 4029
7481 00:56:30.576991 20 : 4252, 4027
7482 00:56:30.577067 24 : 4366, 4140
7483 00:56:30.577126 28 : 4362, 4137
7484 00:56:30.580243 32 : 4255, 4029
7485 00:56:30.580320 36 : 4255, 4029
7486 00:56:30.583467 40 : 4363, 4137
7487 00:56:30.583543 44 : 4363, 4137
7488 00:56:30.586794 48 : 4370, 4143
7489 00:56:30.586896 52 : 4252, 4027
7490 00:56:30.590159 56 : 4260, 4032
7491 00:56:30.590235 60 : 4254, 4029
7492 00:56:30.590294 64 : 4252, 4027
7493 00:56:30.593590 68 : 4363, 4140
7494 00:56:30.593666 72 : 4252, 4029
7495 00:56:30.596791 76 : 4255, 4031
7496 00:56:30.596868 80 : 4366, 4140
7497 00:56:30.600168 84 : 4253, 4029
7498 00:56:30.600244 88 : 4255, 4030
7499 00:56:30.603474 92 : 4361, 4137
7500 00:56:30.603550 96 : 4361, 3204
7501 00:56:30.603610 100 : 4365, 0
7502 00:56:30.607053 104 : 4250, 0
7503 00:56:30.607228 108 : 4360, 0
7504 00:56:30.607338 112 : 4363, 0
7505 00:56:30.610522 116 : 4253, 0
7506 00:56:30.610599 120 : 4252, 0
7507 00:56:30.613818 124 : 4252, 0
7508 00:56:30.613894 128 : 4250, 0
7509 00:56:30.613952 132 : 4361, 0
7510 00:56:30.617037 136 : 4250, 0
7511 00:56:30.617113 140 : 4249, 0
7512 00:56:30.620071 144 : 4250, 0
7513 00:56:30.620147 148 : 4250, 0
7514 00:56:30.620205 152 : 4366, 0
7515 00:56:30.623977 156 : 4250, 0
7516 00:56:30.624053 160 : 4255, 0
7517 00:56:30.626948 164 : 4368, 0
7518 00:56:30.627025 168 : 4250, 0
7519 00:56:30.627086 172 : 4361, 0
7520 00:56:30.630280 176 : 4252, 0
7521 00:56:30.630356 180 : 4249, 0
7522 00:56:30.630415 184 : 4253, 0
7523 00:56:30.633703 188 : 4361, 0
7524 00:56:30.633780 192 : 4252, 0
7525 00:56:30.637335 196 : 4250, 0
7526 00:56:30.637436 200 : 4250, 0
7527 00:56:30.637498 204 : 4365, 0
7528 00:56:30.640132 208 : 4363, 0
7529 00:56:30.640307 212 : 4252, 203
7530 00:56:30.643558 216 : 4255, 3894
7531 00:56:30.643634 220 : 4361, 4137
7532 00:56:30.647083 224 : 4250, 4026
7533 00:56:30.647159 228 : 4250, 4027
7534 00:56:30.650638 232 : 4252, 4029
7535 00:56:30.650715 236 : 4361, 4137
7536 00:56:30.650775 240 : 4255, 4029
7537 00:56:30.653902 244 : 4250, 4027
7538 00:56:30.654097 248 : 4250, 4027
7539 00:56:30.657321 252 : 4253, 4029
7540 00:56:30.657398 256 : 4250, 4026
7541 00:56:30.660583 260 : 4252, 4029
7542 00:56:30.660660 264 : 4363, 4139
7543 00:56:30.664076 268 : 4254, 4030
7544 00:56:30.664153 272 : 4361, 4137
7545 00:56:30.667268 276 : 4363, 4140
7546 00:56:30.667345 280 : 4255, 4030
7547 00:56:30.670691 284 : 4253, 4029
7548 00:56:30.670768 288 : 4363, 4140
7549 00:56:30.670827 292 : 4361, 4137
7550 00:56:30.673696 296 : 4252, 4029
7551 00:56:30.673773 300 : 4366, 4140
7552 00:56:30.677166 304 : 4250, 4027
7553 00:56:30.677243 308 : 4360, 4137
7554 00:56:30.680235 312 : 4252, 4029
7555 00:56:30.680312 316 : 4250, 4026
7556 00:56:30.683907 320 : 4250, 4027
7557 00:56:30.683984 324 : 4368, 4145
7558 00:56:30.687089 328 : 4363, 4140
7559 00:56:30.687167 332 : 4362, 2800
7560 00:56:30.690535 336 : 4254, 22
7561 00:56:30.690612
7562 00:56:30.690671 MIOCK jitter meter ch=0
7563 00:56:30.690726
7564 00:56:30.694106 1T = (336-100) = 236 dly cells
7565 00:56:30.700361 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7566 00:56:30.700461 ==
7567 00:56:30.704032 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 00:56:30.707228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 00:56:30.707304 ==
7570 00:56:30.713646 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7571 00:56:30.717240 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7572 00:56:30.720752 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7573 00:56:30.726875 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7574 00:56:30.736816 [CA 0] Center 44 (14~75) winsize 62
7575 00:56:30.739832 [CA 1] Center 44 (13~75) winsize 63
7576 00:56:30.743424 [CA 2] Center 40 (11~69) winsize 59
7577 00:56:30.746513 [CA 3] Center 39 (10~69) winsize 60
7578 00:56:30.749785 [CA 4] Center 38 (8~68) winsize 61
7579 00:56:30.753109 [CA 5] Center 37 (7~67) winsize 61
7580 00:56:30.753185
7581 00:56:30.756488 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7582 00:56:30.756564
7583 00:56:30.760114 [CATrainingPosCal] consider 1 rank data
7584 00:56:30.763458 u2DelayCellTimex100 = 275/100 ps
7585 00:56:30.766736 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7586 00:56:30.773121 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7587 00:56:30.776459 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7588 00:56:30.779934 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7589 00:56:30.783197 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7590 00:56:30.786956 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7591 00:56:30.787032
7592 00:56:30.789914 CA PerBit enable=1, Macro0, CA PI delay=37
7593 00:56:30.790046
7594 00:56:30.793491 [CBTSetCACLKResult] CA Dly = 37
7595 00:56:30.796689 CS Dly: 10 (0~41)
7596 00:56:30.800201 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7597 00:56:30.803017 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7598 00:56:30.803093 ==
7599 00:56:30.806581 Dram Type= 6, Freq= 0, CH_0, rank 1
7600 00:56:30.809769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 00:56:30.813443 ==
7602 00:56:30.816756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7603 00:56:30.819695 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7604 00:56:30.826587 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7605 00:56:30.829868 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7606 00:56:30.840231 [CA 0] Center 44 (14~75) winsize 62
7607 00:56:30.843540 [CA 1] Center 44 (14~75) winsize 62
7608 00:56:30.846990 [CA 2] Center 40 (11~69) winsize 59
7609 00:56:30.850317 [CA 3] Center 39 (10~69) winsize 60
7610 00:56:30.854129 [CA 4] Center 37 (8~67) winsize 60
7611 00:56:30.857104 [CA 5] Center 37 (7~67) winsize 61
7612 00:56:30.857179
7613 00:56:30.860456 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7614 00:56:30.860531
7615 00:56:30.863767 [CATrainingPosCal] consider 2 rank data
7616 00:56:30.867016 u2DelayCellTimex100 = 275/100 ps
7617 00:56:30.870358 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7618 00:56:30.877391 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7619 00:56:30.880253 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7620 00:56:30.883687 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7621 00:56:30.887122 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7622 00:56:30.890518 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7623 00:56:30.890594
7624 00:56:30.893583 CA PerBit enable=1, Macro0, CA PI delay=37
7625 00:56:30.893659
7626 00:56:30.896809 [CBTSetCACLKResult] CA Dly = 37
7627 00:56:30.900460 CS Dly: 11 (0~44)
7628 00:56:30.903545 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7629 00:56:30.906957 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7630 00:56:30.907033
7631 00:56:30.910481 ----->DramcWriteLeveling(PI) begin...
7632 00:56:30.910577 ==
7633 00:56:30.913828 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 00:56:30.920191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 00:56:30.920267 ==
7636 00:56:30.923884 Write leveling (Byte 0): 32 => 32
7637 00:56:30.923959 Write leveling (Byte 1): 28 => 28
7638 00:56:30.927368 DramcWriteLeveling(PI) end<-----
7639 00:56:30.927444
7640 00:56:30.927501 ==
7641 00:56:30.930218 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 00:56:30.937037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 00:56:30.937114 ==
7644 00:56:30.940604 [Gating] SW mode calibration
7645 00:56:30.946846 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7646 00:56:30.950350 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7647 00:56:30.957080 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 00:56:30.960510 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 00:56:30.963525 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 00:56:30.966953 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 00:56:30.973861 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 00:56:30.977050 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7653 00:56:30.980639 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
7654 00:56:30.987064 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7655 00:56:30.990664 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7656 00:56:30.993893 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7657 00:56:31.000167 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7658 00:56:31.003570 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 00:56:31.007401 1 5 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7660 00:56:31.013867 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7661 00:56:31.017061 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
7662 00:56:31.020578 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 00:56:31.027032 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 00:56:31.030524 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 00:56:31.033942 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 00:56:31.040407 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7667 00:56:31.043712 1 6 16 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
7668 00:56:31.047040 1 6 20 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7669 00:56:31.050698 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7670 00:56:31.057690 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7671 00:56:31.060958 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 00:56:31.063794 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 00:56:31.070627 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 00:56:31.073971 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 00:56:31.077466 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7676 00:56:31.083685 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7677 00:56:31.087117 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7678 00:56:31.090313 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 00:56:31.097063 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 00:56:31.100503 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 00:56:31.103672 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 00:56:31.110485 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 00:56:31.113939 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 00:56:31.117028 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 00:56:31.123736 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 00:56:31.127300 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 00:56:31.130727 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 00:56:31.133844 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 00:56:31.140438 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 00:56:31.144247 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 00:56:31.147245 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7692 00:56:31.154171 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7693 00:56:31.157416 Total UI for P1: 0, mck2ui 16
7694 00:56:31.160386 best dqsien dly found for B0: ( 1, 9, 16)
7695 00:56:31.163871 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7696 00:56:31.167158 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7697 00:56:31.170798 Total UI for P1: 0, mck2ui 16
7698 00:56:31.173938 best dqsien dly found for B1: ( 1, 9, 22)
7699 00:56:31.177132 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7700 00:56:31.180340 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7701 00:56:31.180407
7702 00:56:31.187277 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7703 00:56:31.190434 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7704 00:56:31.194291 [Gating] SW calibration Done
7705 00:56:31.194368 ==
7706 00:56:31.197340 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 00:56:31.200734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 00:56:31.200809 ==
7709 00:56:31.200866 RX Vref Scan: 0
7710 00:56:31.200919
7711 00:56:31.204146 RX Vref 0 -> 0, step: 1
7712 00:56:31.204209
7713 00:56:31.207401 RX Delay 0 -> 252, step: 8
7714 00:56:31.210603 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7715 00:56:31.213924 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7716 00:56:31.220554 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7717 00:56:31.223995 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7718 00:56:31.227046 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7719 00:56:31.230383 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7720 00:56:31.233859 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7721 00:56:31.236965 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7722 00:56:31.243698 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7723 00:56:31.246973 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7724 00:56:31.250389 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7725 00:56:31.253577 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7726 00:56:31.260650 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7727 00:56:31.263756 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7728 00:56:31.267005 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7729 00:56:31.270268 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7730 00:56:31.270335 ==
7731 00:56:31.273766 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 00:56:31.277001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 00:56:31.280365 ==
7734 00:56:31.280432 DQS Delay:
7735 00:56:31.280486 DQS0 = 0, DQS1 = 0
7736 00:56:31.284003 DQM Delay:
7737 00:56:31.284076 DQM0 = 132, DQM1 = 124
7738 00:56:31.287408 DQ Delay:
7739 00:56:31.290722 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7740 00:56:31.293735 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7741 00:56:31.297269 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =119
7742 00:56:31.300264 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7743 00:56:31.300330
7744 00:56:31.300386
7745 00:56:31.300438 ==
7746 00:56:31.304148 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 00:56:31.306995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 00:56:31.307060 ==
7749 00:56:31.307113
7750 00:56:31.307163
7751 00:56:31.310653 TX Vref Scan disable
7752 00:56:31.313957 == TX Byte 0 ==
7753 00:56:31.317280 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7754 00:56:31.320312 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7755 00:56:31.323651 == TX Byte 1 ==
7756 00:56:31.327305 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7757 00:56:31.330645 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7758 00:56:31.330744 ==
7759 00:56:31.333787 Dram Type= 6, Freq= 0, CH_0, rank 0
7760 00:56:31.337260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7761 00:56:31.340830 ==
7762 00:56:31.353368
7763 00:56:31.356949 TX Vref early break, caculate TX vref
7764 00:56:31.360119 TX Vref=16, minBit 7, minWin=21, winSum=367
7765 00:56:31.363258 TX Vref=18, minBit 7, minWin=21, winSum=371
7766 00:56:31.366660 TX Vref=20, minBit 7, minWin=22, winSum=388
7767 00:56:31.369874 TX Vref=22, minBit 4, minWin=23, winSum=394
7768 00:56:31.373428 TX Vref=24, minBit 7, minWin=24, winSum=405
7769 00:56:31.380059 TX Vref=26, minBit 7, minWin=24, winSum=415
7770 00:56:31.383582 TX Vref=28, minBit 0, minWin=25, winSum=419
7771 00:56:31.386845 TX Vref=30, minBit 4, minWin=24, winSum=421
7772 00:56:31.389926 TX Vref=32, minBit 0, minWin=24, winSum=405
7773 00:56:31.393331 TX Vref=34, minBit 3, minWin=23, winSum=402
7774 00:56:31.396790 TX Vref=36, minBit 3, minWin=23, winSum=390
7775 00:56:31.403704 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
7776 00:56:31.403788
7777 00:56:31.406690 Final TX Range 0 Vref 28
7778 00:56:31.406760
7779 00:56:31.406818 ==
7780 00:56:31.410102 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 00:56:31.413606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 00:56:31.413722 ==
7783 00:56:31.413798
7784 00:56:31.413871
7785 00:56:31.416539 TX Vref Scan disable
7786 00:56:31.423279 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7787 00:56:31.423362 == TX Byte 0 ==
7788 00:56:31.426673 u2DelayCellOfst[0]=17 cells (5 PI)
7789 00:56:31.430473 u2DelayCellOfst[1]=21 cells (6 PI)
7790 00:56:31.433888 u2DelayCellOfst[2]=10 cells (3 PI)
7791 00:56:31.436906 u2DelayCellOfst[3]=17 cells (5 PI)
7792 00:56:31.440224 u2DelayCellOfst[4]=10 cells (3 PI)
7793 00:56:31.443593 u2DelayCellOfst[5]=0 cells (0 PI)
7794 00:56:31.446963 u2DelayCellOfst[6]=21 cells (6 PI)
7795 00:56:31.450499 u2DelayCellOfst[7]=21 cells (6 PI)
7796 00:56:31.453611 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7797 00:56:31.456664 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7798 00:56:31.460309 == TX Byte 1 ==
7799 00:56:31.460375 u2DelayCellOfst[8]=0 cells (0 PI)
7800 00:56:31.463792 u2DelayCellOfst[9]=0 cells (0 PI)
7801 00:56:31.466608 u2DelayCellOfst[10]=3 cells (1 PI)
7802 00:56:31.470579 u2DelayCellOfst[11]=0 cells (0 PI)
7803 00:56:31.473309 u2DelayCellOfst[12]=10 cells (3 PI)
7804 00:56:31.476847 u2DelayCellOfst[13]=7 cells (2 PI)
7805 00:56:31.480356 u2DelayCellOfst[14]=10 cells (3 PI)
7806 00:56:31.483475 u2DelayCellOfst[15]=7 cells (2 PI)
7807 00:56:31.486753 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7808 00:56:31.493715 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7809 00:56:31.493797 DramC Write-DBI on
7810 00:56:31.493856 ==
7811 00:56:31.496784 Dram Type= 6, Freq= 0, CH_0, rank 0
7812 00:56:31.500431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7813 00:56:31.500503 ==
7814 00:56:31.503400
7815 00:56:31.503471
7816 00:56:31.503529 TX Vref Scan disable
7817 00:56:31.506497 == TX Byte 0 ==
7818 00:56:31.509873 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7819 00:56:31.513382 == TX Byte 1 ==
7820 00:56:31.516820 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7821 00:56:31.520233 DramC Write-DBI off
7822 00:56:31.520302
7823 00:56:31.520359 [DATLAT]
7824 00:56:31.520420 Freq=1600, CH0 RK0
7825 00:56:31.520472
7826 00:56:31.523756 DATLAT Default: 0xf
7827 00:56:31.523826 0, 0xFFFF, sum = 0
7828 00:56:31.527153 1, 0xFFFF, sum = 0
7829 00:56:31.527224 2, 0xFFFF, sum = 0
7830 00:56:31.529972 3, 0xFFFF, sum = 0
7831 00:56:31.530047 4, 0xFFFF, sum = 0
7832 00:56:31.533483 5, 0xFFFF, sum = 0
7833 00:56:31.536843 6, 0xFFFF, sum = 0
7834 00:56:31.536919 7, 0xFFFF, sum = 0
7835 00:56:31.540301 8, 0xFFFF, sum = 0
7836 00:56:31.540370 9, 0xFFFF, sum = 0
7837 00:56:31.543475 10, 0xFFFF, sum = 0
7838 00:56:31.543555 11, 0xFFFF, sum = 0
7839 00:56:31.546836 12, 0xFFFF, sum = 0
7840 00:56:31.546904 13, 0xFFFF, sum = 0
7841 00:56:31.550431 14, 0x0, sum = 1
7842 00:56:31.550499 15, 0x0, sum = 2
7843 00:56:31.553288 16, 0x0, sum = 3
7844 00:56:31.553358 17, 0x0, sum = 4
7845 00:56:31.556777 best_step = 15
7846 00:56:31.556845
7847 00:56:31.556901 ==
7848 00:56:31.560071 Dram Type= 6, Freq= 0, CH_0, rank 0
7849 00:56:31.563613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7850 00:56:31.563685 ==
7851 00:56:31.563740 RX Vref Scan: 1
7852 00:56:31.563790
7853 00:56:31.566787 Set Vref Range= 24 -> 127
7854 00:56:31.566853
7855 00:56:31.570667 RX Vref 24 -> 127, step: 1
7856 00:56:31.570737
7857 00:56:31.573652 RX Delay 11 -> 252, step: 4
7858 00:56:31.573716
7859 00:56:31.577025 Set Vref, RX VrefLevel [Byte0]: 24
7860 00:56:31.580308 [Byte1]: 24
7861 00:56:31.580374
7862 00:56:31.583488 Set Vref, RX VrefLevel [Byte0]: 25
7863 00:56:31.586826 [Byte1]: 25
7864 00:56:31.586897
7865 00:56:31.590327 Set Vref, RX VrefLevel [Byte0]: 26
7866 00:56:31.593858 [Byte1]: 26
7867 00:56:31.597175
7868 00:56:31.597274 Set Vref, RX VrefLevel [Byte0]: 27
7869 00:56:31.600122 [Byte1]: 27
7870 00:56:31.604993
7871 00:56:31.605092 Set Vref, RX VrefLevel [Byte0]: 28
7872 00:56:31.607770 [Byte1]: 28
7873 00:56:31.612162
7874 00:56:31.612251 Set Vref, RX VrefLevel [Byte0]: 29
7875 00:56:31.615650 [Byte1]: 29
7876 00:56:31.619859
7877 00:56:31.619969 Set Vref, RX VrefLevel [Byte0]: 30
7878 00:56:31.623340 [Byte1]: 30
7879 00:56:31.627485
7880 00:56:31.627578 Set Vref, RX VrefLevel [Byte0]: 31
7881 00:56:31.630922 [Byte1]: 31
7882 00:56:31.634997
7883 00:56:31.635094 Set Vref, RX VrefLevel [Byte0]: 32
7884 00:56:31.638326 [Byte1]: 32
7885 00:56:31.642768
7886 00:56:31.642839 Set Vref, RX VrefLevel [Byte0]: 33
7887 00:56:31.646156 [Byte1]: 33
7888 00:56:31.650548
7889 00:56:31.650639 Set Vref, RX VrefLevel [Byte0]: 34
7890 00:56:31.653573 [Byte1]: 34
7891 00:56:31.658104
7892 00:56:31.658178 Set Vref, RX VrefLevel [Byte0]: 35
7893 00:56:31.661167 [Byte1]: 35
7894 00:56:31.665535
7895 00:56:31.665609 Set Vref, RX VrefLevel [Byte0]: 36
7896 00:56:31.668940 [Byte1]: 36
7897 00:56:31.673426
7898 00:56:31.673502 Set Vref, RX VrefLevel [Byte0]: 37
7899 00:56:31.676797 [Byte1]: 37
7900 00:56:31.680762
7901 00:56:31.680830 Set Vref, RX VrefLevel [Byte0]: 38
7902 00:56:31.684150 [Byte1]: 38
7903 00:56:31.688591
7904 00:56:31.688669 Set Vref, RX VrefLevel [Byte0]: 39
7905 00:56:31.691872 [Byte1]: 39
7906 00:56:31.695913
7907 00:56:31.695989 Set Vref, RX VrefLevel [Byte0]: 40
7908 00:56:31.699476 [Byte1]: 40
7909 00:56:31.703412
7910 00:56:31.703489 Set Vref, RX VrefLevel [Byte0]: 41
7911 00:56:31.707006 [Byte1]: 41
7912 00:56:31.711709
7913 00:56:31.711785 Set Vref, RX VrefLevel [Byte0]: 42
7914 00:56:31.714461 [Byte1]: 42
7915 00:56:31.718885
7916 00:56:31.718962 Set Vref, RX VrefLevel [Byte0]: 43
7917 00:56:31.722208 [Byte1]: 43
7918 00:56:31.726524
7919 00:56:31.726600 Set Vref, RX VrefLevel [Byte0]: 44
7920 00:56:31.729689 [Byte1]: 44
7921 00:56:31.734265
7922 00:56:31.734365 Set Vref, RX VrefLevel [Byte0]: 45
7923 00:56:31.737427 [Byte1]: 45
7924 00:56:31.741915
7925 00:56:31.742009 Set Vref, RX VrefLevel [Byte0]: 46
7926 00:56:31.745446 [Byte1]: 46
7927 00:56:31.749259
7928 00:56:31.749346 Set Vref, RX VrefLevel [Byte0]: 47
7929 00:56:31.752306 [Byte1]: 47
7930 00:56:31.756983
7931 00:56:31.757052 Set Vref, RX VrefLevel [Byte0]: 48
7932 00:56:31.760276 [Byte1]: 48
7933 00:56:31.764334
7934 00:56:31.764405 Set Vref, RX VrefLevel [Byte0]: 49
7935 00:56:31.767800 [Byte1]: 49
7936 00:56:31.771964
7937 00:56:31.772039 Set Vref, RX VrefLevel [Byte0]: 50
7938 00:56:31.775416 [Byte1]: 50
7939 00:56:31.779526
7940 00:56:31.779592 Set Vref, RX VrefLevel [Byte0]: 51
7941 00:56:31.782788 [Byte1]: 51
7942 00:56:31.787552
7943 00:56:31.787626 Set Vref, RX VrefLevel [Byte0]: 52
7944 00:56:31.790767 [Byte1]: 52
7945 00:56:31.795192
7946 00:56:31.795261 Set Vref, RX VrefLevel [Byte0]: 53
7947 00:56:31.798133 [Byte1]: 53
7948 00:56:31.802762
7949 00:56:31.802835 Set Vref, RX VrefLevel [Byte0]: 54
7950 00:56:31.806205 [Byte1]: 54
7951 00:56:31.810234
7952 00:56:31.810302 Set Vref, RX VrefLevel [Byte0]: 55
7953 00:56:31.814163 [Byte1]: 55
7954 00:56:31.817623
7955 00:56:31.817693 Set Vref, RX VrefLevel [Byte0]: 56
7956 00:56:31.820965 [Byte1]: 56
7957 00:56:31.825282
7958 00:56:31.825351 Set Vref, RX VrefLevel [Byte0]: 57
7959 00:56:31.829135 [Byte1]: 57
7960 00:56:31.832817
7961 00:56:31.832886 Set Vref, RX VrefLevel [Byte0]: 58
7962 00:56:31.836527 [Byte1]: 58
7963 00:56:31.840610
7964 00:56:31.840681 Set Vref, RX VrefLevel [Byte0]: 59
7965 00:56:31.844003 [Byte1]: 59
7966 00:56:31.848622
7967 00:56:31.848691 Set Vref, RX VrefLevel [Byte0]: 60
7968 00:56:31.851487 [Byte1]: 60
7969 00:56:31.855889
7970 00:56:31.855967 Set Vref, RX VrefLevel [Byte0]: 61
7971 00:56:31.858959 [Byte1]: 61
7972 00:56:31.863730
7973 00:56:31.863806 Set Vref, RX VrefLevel [Byte0]: 62
7974 00:56:31.866915 [Byte1]: 62
7975 00:56:31.871258
7976 00:56:31.871334 Set Vref, RX VrefLevel [Byte0]: 63
7977 00:56:31.874434 [Byte1]: 63
7978 00:56:31.878773
7979 00:56:31.878848 Set Vref, RX VrefLevel [Byte0]: 64
7980 00:56:31.882292 [Byte1]: 64
7981 00:56:31.886833
7982 00:56:31.886909 Set Vref, RX VrefLevel [Byte0]: 65
7983 00:56:31.889792 [Byte1]: 65
7984 00:56:31.894037
7985 00:56:31.894113 Set Vref, RX VrefLevel [Byte0]: 66
7986 00:56:31.897091 [Byte1]: 66
7987 00:56:31.901399
7988 00:56:31.901501 Set Vref, RX VrefLevel [Byte0]: 67
7989 00:56:31.905004 [Byte1]: 67
7990 00:56:31.909132
7991 00:56:31.909219 Set Vref, RX VrefLevel [Byte0]: 68
7992 00:56:31.912777 [Byte1]: 68
7993 00:56:31.916750
7994 00:56:31.916831 Set Vref, RX VrefLevel [Byte0]: 69
7995 00:56:31.920217 [Byte1]: 69
7996 00:56:31.924264
7997 00:56:31.924359 Set Vref, RX VrefLevel [Byte0]: 70
7998 00:56:31.927883 [Byte1]: 70
7999 00:56:31.931846
8000 00:56:31.931913 Set Vref, RX VrefLevel [Byte0]: 71
8001 00:56:31.935191 [Byte1]: 71
8002 00:56:31.939751
8003 00:56:31.939831 Set Vref, RX VrefLevel [Byte0]: 72
8004 00:56:31.943183 [Byte1]: 72
8005 00:56:31.947117
8006 00:56:31.947193 Set Vref, RX VrefLevel [Byte0]: 73
8007 00:56:31.950488 [Byte1]: 73
8008 00:56:31.954870
8009 00:56:31.954945 Set Vref, RX VrefLevel [Byte0]: 74
8010 00:56:31.958040 [Byte1]: 74
8011 00:56:31.962623
8012 00:56:31.962698 Set Vref, RX VrefLevel [Byte0]: 75
8013 00:56:31.966012 [Byte1]: 75
8014 00:56:31.969856
8015 00:56:31.969931 Set Vref, RX VrefLevel [Byte0]: 76
8016 00:56:31.973566 [Byte1]: 76
8017 00:56:31.977491
8018 00:56:31.977580 Set Vref, RX VrefLevel [Byte0]: 77
8019 00:56:31.980828 [Byte1]: 77
8020 00:56:31.985412
8021 00:56:31.985508 Final RX Vref Byte 0 = 63 to rank0
8022 00:56:31.988344 Final RX Vref Byte 1 = 59 to rank0
8023 00:56:31.991732 Final RX Vref Byte 0 = 63 to rank1
8024 00:56:31.995467 Final RX Vref Byte 1 = 59 to rank1==
8025 00:56:31.998560 Dram Type= 6, Freq= 0, CH_0, rank 0
8026 00:56:32.005688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8027 00:56:32.005757 ==
8028 00:56:32.005844 DQS Delay:
8029 00:56:32.005927 DQS0 = 0, DQS1 = 0
8030 00:56:32.008426 DQM Delay:
8031 00:56:32.008489 DQM0 = 130, DQM1 = 121
8032 00:56:32.011964 DQ Delay:
8033 00:56:32.015360 DQ0 =130, DQ1 =134, DQ2 =126, DQ3 =126
8034 00:56:32.018717 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8035 00:56:32.022186 DQ8 =108, DQ9 =110, DQ10 =122, DQ11 =116
8036 00:56:32.025065 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8037 00:56:32.025126
8038 00:56:32.025179
8039 00:56:32.025230
8040 00:56:32.028686 [DramC_TX_OE_Calibration] TA2
8041 00:56:32.031869 Original DQ_B0 (3 6) =30, OEN = 27
8042 00:56:32.035498 Original DQ_B1 (3 6) =30, OEN = 27
8043 00:56:32.038969 24, 0x0, End_B0=24 End_B1=24
8044 00:56:32.039039 25, 0x0, End_B0=25 End_B1=25
8045 00:56:32.041889 26, 0x0, End_B0=26 End_B1=26
8046 00:56:32.045227 27, 0x0, End_B0=27 End_B1=27
8047 00:56:32.048785 28, 0x0, End_B0=28 End_B1=28
8048 00:56:32.048856 29, 0x0, End_B0=29 End_B1=29
8049 00:56:32.052178 30, 0x0, End_B0=30 End_B1=30
8050 00:56:32.055773 31, 0x4545, End_B0=30 End_B1=30
8051 00:56:32.058676 Byte0 end_step=30 best_step=27
8052 00:56:32.062156 Byte1 end_step=30 best_step=27
8053 00:56:32.065860 Byte0 TX OE(2T, 0.5T) = (3, 3)
8054 00:56:32.065960 Byte1 TX OE(2T, 0.5T) = (3, 3)
8055 00:56:32.066058
8056 00:56:32.066111
8057 00:56:32.075381 [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
8058 00:56:32.078987 CH0 RK0: MR19=303, MR18=1307
8059 00:56:32.082142 CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15
8060 00:56:32.085428
8061 00:56:32.088850 ----->DramcWriteLeveling(PI) begin...
8062 00:56:32.088918 ==
8063 00:56:32.092308 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 00:56:32.095406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 00:56:32.095480 ==
8066 00:56:32.099097 Write leveling (Byte 0): 31 => 31
8067 00:56:32.102741 Write leveling (Byte 1): 25 => 25
8068 00:56:32.105572 DramcWriteLeveling(PI) end<-----
8069 00:56:32.105700
8070 00:56:32.105754 ==
8071 00:56:32.109094 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 00:56:32.112989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 00:56:32.113092 ==
8074 00:56:32.115964 [Gating] SW mode calibration
8075 00:56:32.122173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8076 00:56:32.129183 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8077 00:56:32.132452 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 00:56:32.136006 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 00:56:32.139010 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8080 00:56:32.145956 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8081 00:56:32.149332 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8082 00:56:32.152561 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8083 00:56:32.159338 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 00:56:32.162845 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8085 00:56:32.166119 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8086 00:56:32.172398 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8087 00:56:32.175912 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8088 00:56:32.179283 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8089 00:56:32.185795 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8090 00:56:32.189126 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8091 00:56:32.192467 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8092 00:56:32.199532 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 00:56:32.202466 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 00:56:32.205955 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 00:56:32.212846 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8096 00:56:32.215948 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8097 00:56:32.219056 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8098 00:56:32.222262 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8099 00:56:32.229027 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 00:56:32.232589 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 00:56:32.235835 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 00:56:32.242582 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 00:56:32.246259 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8104 00:56:32.249131 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8105 00:56:32.255656 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8106 00:56:32.259045 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8107 00:56:32.262491 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 00:56:32.269001 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 00:56:32.272456 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 00:56:32.275579 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 00:56:32.282630 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 00:56:32.285773 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 00:56:32.289328 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 00:56:32.295910 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 00:56:32.299108 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 00:56:32.302554 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 00:56:32.309442 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 00:56:32.312624 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 00:56:32.315910 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8120 00:56:32.319342 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8121 00:56:32.326215 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8122 00:56:32.329419 Total UI for P1: 0, mck2ui 16
8123 00:56:32.332976 best dqsien dly found for B0: ( 1, 9, 10)
8124 00:56:32.335848 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8125 00:56:32.339332 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8126 00:56:32.342730 Total UI for P1: 0, mck2ui 16
8127 00:56:32.346132 best dqsien dly found for B1: ( 1, 9, 20)
8128 00:56:32.349650 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8129 00:56:32.352434 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8130 00:56:32.352510
8131 00:56:32.359206 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8132 00:56:32.362551 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8133 00:56:32.366039 [Gating] SW calibration Done
8134 00:56:32.366115 ==
8135 00:56:32.369041 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 00:56:32.372508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 00:56:32.372584 ==
8138 00:56:32.372644 RX Vref Scan: 0
8139 00:56:32.372699
8140 00:56:32.376150 RX Vref 0 -> 0, step: 1
8141 00:56:32.376230
8142 00:56:32.379622 RX Delay 0 -> 252, step: 8
8143 00:56:32.382872 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8144 00:56:32.385885 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8145 00:56:32.389175 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8146 00:56:32.396158 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8147 00:56:32.399537 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8148 00:56:32.402626 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8149 00:56:32.405958 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8150 00:56:32.409478 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8151 00:56:32.416291 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8152 00:56:32.419663 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8153 00:56:32.422952 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8154 00:56:32.426031 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8155 00:56:32.429432 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8156 00:56:32.436246 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8157 00:56:32.439767 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8158 00:56:32.443112 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8159 00:56:32.443188 ==
8160 00:56:32.445960 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 00:56:32.449385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 00:56:32.449461 ==
8163 00:56:32.453171 DQS Delay:
8164 00:56:32.453246 DQS0 = 0, DQS1 = 0
8165 00:56:32.456690 DQM Delay:
8166 00:56:32.456766 DQM0 = 131, DQM1 = 123
8167 00:56:32.456825 DQ Delay:
8168 00:56:32.459803 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
8169 00:56:32.463291 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8170 00:56:32.469552 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8171 00:56:32.473079 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8172 00:56:32.473184
8173 00:56:32.473274
8174 00:56:32.473341 ==
8175 00:56:32.476101 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 00:56:32.479336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 00:56:32.479429 ==
8178 00:56:32.479512
8179 00:56:32.479590
8180 00:56:32.483228 TX Vref Scan disable
8181 00:56:32.486520 == TX Byte 0 ==
8182 00:56:32.489462 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8183 00:56:32.492794 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8184 00:56:32.496256 == TX Byte 1 ==
8185 00:56:32.499761 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8186 00:56:32.503111 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8187 00:56:32.503186 ==
8188 00:56:32.506463 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 00:56:32.509879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 00:56:32.509978 ==
8191 00:56:32.525536
8192 00:56:32.529034 TX Vref early break, caculate TX vref
8193 00:56:32.532499 TX Vref=16, minBit 0, minWin=22, winSum=370
8194 00:56:32.536067 TX Vref=18, minBit 9, minWin=22, winSum=380
8195 00:56:32.539370 TX Vref=20, minBit 7, minWin=23, winSum=392
8196 00:56:32.542464 TX Vref=22, minBit 1, minWin=24, winSum=397
8197 00:56:32.545693 TX Vref=24, minBit 9, minWin=24, winSum=407
8198 00:56:32.549123 TX Vref=26, minBit 3, minWin=25, winSum=416
8199 00:56:32.555824 TX Vref=28, minBit 8, minWin=25, winSum=419
8200 00:56:32.559000 TX Vref=30, minBit 8, minWin=25, winSum=419
8201 00:56:32.562658 TX Vref=32, minBit 7, minWin=25, winSum=414
8202 00:56:32.565821 TX Vref=34, minBit 2, minWin=24, winSum=403
8203 00:56:32.569332 TX Vref=36, minBit 1, minWin=23, winSum=392
8204 00:56:32.576353 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 28
8205 00:56:32.576454
8206 00:56:32.579377 Final TX Range 0 Vref 28
8207 00:56:32.579496
8208 00:56:32.579587 ==
8209 00:56:32.582567 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 00:56:32.585946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 00:56:32.586060 ==
8212 00:56:32.586119
8213 00:56:32.586172
8214 00:56:32.589496 TX Vref Scan disable
8215 00:56:32.596015 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8216 00:56:32.596127 == TX Byte 0 ==
8217 00:56:32.599455 u2DelayCellOfst[0]=10 cells (3 PI)
8218 00:56:32.603026 u2DelayCellOfst[1]=17 cells (5 PI)
8219 00:56:32.605897 u2DelayCellOfst[2]=7 cells (2 PI)
8220 00:56:32.609531 u2DelayCellOfst[3]=10 cells (3 PI)
8221 00:56:32.612461 u2DelayCellOfst[4]=7 cells (2 PI)
8222 00:56:32.616203 u2DelayCellOfst[5]=0 cells (0 PI)
8223 00:56:32.619738 u2DelayCellOfst[6]=17 cells (5 PI)
8224 00:56:32.619827 u2DelayCellOfst[7]=17 cells (5 PI)
8225 00:56:32.625871 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8226 00:56:32.629420 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8227 00:56:32.629521 == TX Byte 1 ==
8228 00:56:32.633293 u2DelayCellOfst[8]=3 cells (1 PI)
8229 00:56:32.636162 u2DelayCellOfst[9]=0 cells (0 PI)
8230 00:56:32.639606 u2DelayCellOfst[10]=10 cells (3 PI)
8231 00:56:32.643202 u2DelayCellOfst[11]=3 cells (1 PI)
8232 00:56:32.646431 u2DelayCellOfst[12]=14 cells (4 PI)
8233 00:56:32.649630 u2DelayCellOfst[13]=14 cells (4 PI)
8234 00:56:32.653108 u2DelayCellOfst[14]=17 cells (5 PI)
8235 00:56:32.656018 u2DelayCellOfst[15]=14 cells (4 PI)
8236 00:56:32.659819 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8237 00:56:32.663260 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8238 00:56:32.666361 DramC Write-DBI on
8239 00:56:32.666434 ==
8240 00:56:32.669593 Dram Type= 6, Freq= 0, CH_0, rank 1
8241 00:56:32.672951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 00:56:32.673051 ==
8243 00:56:32.673137
8244 00:56:32.673248
8245 00:56:32.676177 TX Vref Scan disable
8246 00:56:32.679462 == TX Byte 0 ==
8247 00:56:32.683536 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
8248 00:56:32.686484 == TX Byte 1 ==
8249 00:56:32.689932 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8250 00:56:32.690038 DramC Write-DBI off
8251 00:56:32.690096
8252 00:56:32.692593 [DATLAT]
8253 00:56:32.692659 Freq=1600, CH0 RK1
8254 00:56:32.692721
8255 00:56:32.696097 DATLAT Default: 0xf
8256 00:56:32.696157 0, 0xFFFF, sum = 0
8257 00:56:32.699501 1, 0xFFFF, sum = 0
8258 00:56:32.699565 2, 0xFFFF, sum = 0
8259 00:56:32.702748 3, 0xFFFF, sum = 0
8260 00:56:32.702811 4, 0xFFFF, sum = 0
8261 00:56:32.706157 5, 0xFFFF, sum = 0
8262 00:56:32.706265 6, 0xFFFF, sum = 0
8263 00:56:32.709653 7, 0xFFFF, sum = 0
8264 00:56:32.709722 8, 0xFFFF, sum = 0
8265 00:56:32.712982 9, 0xFFFF, sum = 0
8266 00:56:32.715956 10, 0xFFFF, sum = 0
8267 00:56:32.716055 11, 0xFFFF, sum = 0
8268 00:56:32.719307 12, 0xFFFF, sum = 0
8269 00:56:32.719391 13, 0xFFFF, sum = 0
8270 00:56:32.723515 14, 0x0, sum = 1
8271 00:56:32.723626 15, 0x0, sum = 2
8272 00:56:32.726373 16, 0x0, sum = 3
8273 00:56:32.726447 17, 0x0, sum = 4
8274 00:56:32.726506 best_step = 15
8275 00:56:32.726558
8276 00:56:32.729559 ==
8277 00:56:32.732884 Dram Type= 6, Freq= 0, CH_0, rank 1
8278 00:56:32.736370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 00:56:32.736439 ==
8280 00:56:32.736496 RX Vref Scan: 0
8281 00:56:32.736549
8282 00:56:32.739461 RX Vref 0 -> 0, step: 1
8283 00:56:32.739562
8284 00:56:32.742954 RX Delay 3 -> 252, step: 4
8285 00:56:32.745829 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8286 00:56:32.749779 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8287 00:56:32.756119 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8288 00:56:32.759626 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8289 00:56:32.763135 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8290 00:56:32.765860 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8291 00:56:32.769467 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8292 00:56:32.775882 iDelay=195, Bit 7, Center 136 (83 ~ 190) 108
8293 00:56:32.779411 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8294 00:56:32.782649 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8295 00:56:32.785931 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8296 00:56:32.789619 iDelay=195, Bit 11, Center 114 (63 ~ 166) 104
8297 00:56:32.796178 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8298 00:56:32.799385 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8299 00:56:32.802739 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8300 00:56:32.806402 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8301 00:56:32.806498 ==
8302 00:56:32.809610 Dram Type= 6, Freq= 0, CH_0, rank 1
8303 00:56:32.816079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 00:56:32.816152 ==
8305 00:56:32.816210 DQS Delay:
8306 00:56:32.816264 DQS0 = 0, DQS1 = 0
8307 00:56:32.819418 DQM Delay:
8308 00:56:32.819484 DQM0 = 128, DQM1 = 122
8309 00:56:32.822904 DQ Delay:
8310 00:56:32.826246 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8311 00:56:32.829353 DQ4 =128, DQ5 =116, DQ6 =138, DQ7 =136
8312 00:56:32.832823 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =114
8313 00:56:32.836273 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8314 00:56:32.836339
8315 00:56:32.836395
8316 00:56:32.836448
8317 00:56:32.839694 [DramC_TX_OE_Calibration] TA2
8318 00:56:32.842491 Original DQ_B0 (3 6) =30, OEN = 27
8319 00:56:32.845975 Original DQ_B1 (3 6) =30, OEN = 27
8320 00:56:32.849492 24, 0x0, End_B0=24 End_B1=24
8321 00:56:32.849555 25, 0x0, End_B0=25 End_B1=25
8322 00:56:32.852654 26, 0x0, End_B0=26 End_B1=26
8323 00:56:32.856376 27, 0x0, End_B0=27 End_B1=27
8324 00:56:32.859320 28, 0x0, End_B0=28 End_B1=28
8325 00:56:32.859384 29, 0x0, End_B0=29 End_B1=29
8326 00:56:32.862717 30, 0x0, End_B0=30 End_B1=30
8327 00:56:32.866021 31, 0x4545, End_B0=30 End_B1=30
8328 00:56:32.869521 Byte0 end_step=30 best_step=27
8329 00:56:32.873069 Byte1 end_step=30 best_step=27
8330 00:56:32.876185 Byte0 TX OE(2T, 0.5T) = (3, 3)
8331 00:56:32.876262 Byte1 TX OE(2T, 0.5T) = (3, 3)
8332 00:56:32.876319
8333 00:56:32.879693
8334 00:56:32.886362 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8335 00:56:32.889314 CH0 RK1: MR19=303, MR18=1A0F
8336 00:56:32.896076 CH0_RK1: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8337 00:56:32.896142 [RxdqsGatingPostProcess] freq 1600
8338 00:56:32.902836 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8339 00:56:32.906117 best DQS0 dly(2T, 0.5T) = (1, 1)
8340 00:56:32.909235 best DQS1 dly(2T, 0.5T) = (1, 1)
8341 00:56:32.912597 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8342 00:56:32.916306 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8343 00:56:32.919406 best DQS0 dly(2T, 0.5T) = (1, 1)
8344 00:56:32.922954 best DQS1 dly(2T, 0.5T) = (1, 1)
8345 00:56:32.926374 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8346 00:56:32.929864 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8347 00:56:32.929928 Pre-setting of DQS Precalculation
8348 00:56:32.936146 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8349 00:56:32.936222 ==
8350 00:56:32.939701 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 00:56:32.942879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 00:56:32.942947 ==
8353 00:56:32.949855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8354 00:56:32.952698 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8355 00:56:32.955948 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8356 00:56:32.962873 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8357 00:56:32.972047 [CA 0] Center 42 (13~71) winsize 59
8358 00:56:32.975593 [CA 1] Center 42 (13~71) winsize 59
8359 00:56:32.979224 [CA 2] Center 37 (8~66) winsize 59
8360 00:56:32.982246 [CA 3] Center 36 (7~65) winsize 59
8361 00:56:32.985369 [CA 4] Center 37 (8~67) winsize 60
8362 00:56:32.988681 [CA 5] Center 36 (7~66) winsize 60
8363 00:56:32.988752
8364 00:56:32.992104 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8365 00:56:32.992174
8366 00:56:32.995604 [CATrainingPosCal] consider 1 rank data
8367 00:56:32.999181 u2DelayCellTimex100 = 275/100 ps
8368 00:56:33.002367 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8369 00:56:33.008968 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8370 00:56:33.012440 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8371 00:56:33.015834 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8372 00:56:33.018884 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8373 00:56:33.022413 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8374 00:56:33.022504
8375 00:56:33.025585 CA PerBit enable=1, Macro0, CA PI delay=36
8376 00:56:33.025659
8377 00:56:33.029209 [CBTSetCACLKResult] CA Dly = 36
8378 00:56:33.029289 CS Dly: 9 (0~40)
8379 00:56:33.035968 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8380 00:56:33.039205 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8381 00:56:33.039274 ==
8382 00:56:33.042013 Dram Type= 6, Freq= 0, CH_1, rank 1
8383 00:56:33.045812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 00:56:33.045889 ==
8385 00:56:33.052135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8386 00:56:33.055584 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8387 00:56:33.059039 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8388 00:56:33.065851 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8389 00:56:33.075318 [CA 0] Center 42 (13~72) winsize 60
8390 00:56:33.078848 [CA 1] Center 42 (14~71) winsize 58
8391 00:56:33.081865 [CA 2] Center 37 (9~66) winsize 58
8392 00:56:33.085445 [CA 3] Center 37 (8~66) winsize 59
8393 00:56:33.089104 [CA 4] Center 37 (8~67) winsize 60
8394 00:56:33.092030 [CA 5] Center 36 (7~66) winsize 60
8395 00:56:33.092102
8396 00:56:33.095414 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8397 00:56:33.095480
8398 00:56:33.098694 [CATrainingPosCal] consider 2 rank data
8399 00:56:33.102101 u2DelayCellTimex100 = 275/100 ps
8400 00:56:33.105415 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8401 00:56:33.112025 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8402 00:56:33.115646 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8403 00:56:33.118594 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8404 00:56:33.122092 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8405 00:56:33.125102 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8406 00:56:33.125228
8407 00:56:33.128887 CA PerBit enable=1, Macro0, CA PI delay=36
8408 00:56:33.128997
8409 00:56:33.131978 [CBTSetCACLKResult] CA Dly = 36
8410 00:56:33.132096 CS Dly: 11 (0~45)
8411 00:56:33.138591 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8412 00:56:33.142267 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8413 00:56:33.142428
8414 00:56:33.145436 ----->DramcWriteLeveling(PI) begin...
8415 00:56:33.145537 ==
8416 00:56:33.148879 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 00:56:33.152264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 00:56:33.152372 ==
8419 00:56:33.155205 Write leveling (Byte 0): 24 => 24
8420 00:56:33.158792 Write leveling (Byte 1): 28 => 28
8421 00:56:33.162367 DramcWriteLeveling(PI) end<-----
8422 00:56:33.162454
8423 00:56:33.162527 ==
8424 00:56:33.165254 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 00:56:33.168528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 00:56:33.171863 ==
8427 00:56:33.171954 [Gating] SW mode calibration
8428 00:56:33.178675 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8429 00:56:33.185565 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8430 00:56:33.189052 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 00:56:33.195665 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 00:56:33.199041 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 00:56:33.202198 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 00:56:33.208740 1 4 16 | B1->B0 | 3232 2727 | 0 1 | (0 0) (1 1)
8435 00:56:33.212289 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8436 00:56:33.215981 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8437 00:56:33.222302 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8438 00:56:33.225084 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8439 00:56:33.228576 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 00:56:33.235199 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 00:56:33.238852 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8442 00:56:33.241798 1 5 16 | B1->B0 | 2727 2e2e | 0 0 | (1 0) (1 0)
8443 00:56:33.248251 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 00:56:33.251707 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 00:56:33.255004 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8446 00:56:33.261915 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 00:56:33.265415 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 00:56:33.268264 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 00:56:33.271691 1 6 12 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
8450 00:56:33.278521 1 6 16 | B1->B0 | 3737 2d2d | 0 0 | (0 0) (0 0)
8451 00:56:33.281442 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8452 00:56:33.288290 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 00:56:33.292016 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 00:56:33.295088 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 00:56:33.298080 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 00:56:33.305190 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 00:56:33.308196 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8458 00:56:33.311465 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8459 00:56:33.318158 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8460 00:56:33.321521 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 00:56:33.324793 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 00:56:33.331478 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 00:56:33.335017 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 00:56:33.338310 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 00:56:33.345038 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 00:56:33.348148 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 00:56:33.351554 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 00:56:33.358258 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 00:56:33.361511 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 00:56:33.365051 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 00:56:33.371514 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 00:56:33.374810 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 00:56:33.378404 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 00:56:33.384893 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8475 00:56:33.388274 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8476 00:56:33.391669 Total UI for P1: 0, mck2ui 16
8477 00:56:33.395082 best dqsien dly found for B0: ( 1, 9, 16)
8478 00:56:33.398304 Total UI for P1: 0, mck2ui 16
8479 00:56:33.401278 best dqsien dly found for B1: ( 1, 9, 16)
8480 00:56:33.404837 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8481 00:56:33.408418 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8482 00:56:33.408513
8483 00:56:33.411707 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8484 00:56:33.414632 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8485 00:56:33.417966 [Gating] SW calibration Done
8486 00:56:33.418079 ==
8487 00:56:33.421121 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 00:56:33.424721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 00:56:33.424811 ==
8490 00:56:33.428060 RX Vref Scan: 0
8491 00:56:33.428147
8492 00:56:33.431590 RX Vref 0 -> 0, step: 1
8493 00:56:33.431665
8494 00:56:33.431722 RX Delay 0 -> 252, step: 8
8495 00:56:33.438363 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8496 00:56:33.441302 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8497 00:56:33.444839 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8498 00:56:33.447885 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8499 00:56:33.451205 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8500 00:56:33.458131 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8501 00:56:33.461492 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8502 00:56:33.464766 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8503 00:56:33.468266 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8504 00:56:33.471610 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8505 00:56:33.475169 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8506 00:56:33.481813 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8507 00:56:33.484833 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8508 00:56:33.488481 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8509 00:56:33.491959 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8510 00:56:33.495297 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8511 00:56:33.498765 ==
8512 00:56:33.501512 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 00:56:33.504745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 00:56:33.504846 ==
8515 00:56:33.504934 DQS Delay:
8516 00:56:33.508487 DQS0 = 0, DQS1 = 0
8517 00:56:33.508563 DQM Delay:
8518 00:56:33.511550 DQM0 = 134, DQM1 = 127
8519 00:56:33.511626 DQ Delay:
8520 00:56:33.514910 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8521 00:56:33.518203 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8522 00:56:33.521686 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8523 00:56:33.524852 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8524 00:56:33.524933
8525 00:56:33.524993
8526 00:56:33.525048 ==
8527 00:56:33.528361 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 00:56:33.535043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 00:56:33.535117 ==
8530 00:56:33.535176
8531 00:56:33.535230
8532 00:56:33.535289 TX Vref Scan disable
8533 00:56:33.538442 == TX Byte 0 ==
8534 00:56:33.542075 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8535 00:56:33.545437 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8536 00:56:33.548354 == TX Byte 1 ==
8537 00:56:33.551714 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8538 00:56:33.558536 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8539 00:56:33.558614 ==
8540 00:56:33.561529 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 00:56:33.564695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 00:56:33.564797 ==
8543 00:56:33.578401
8544 00:56:33.582258 TX Vref early break, caculate TX vref
8545 00:56:33.585235 TX Vref=16, minBit 8, minWin=20, winSum=364
8546 00:56:33.588337 TX Vref=18, minBit 8, minWin=21, winSum=372
8547 00:56:33.592138 TX Vref=20, minBit 8, minWin=21, winSum=384
8548 00:56:33.595141 TX Vref=22, minBit 8, minWin=22, winSum=390
8549 00:56:33.598626 TX Vref=24, minBit 8, minWin=23, winSum=399
8550 00:56:33.605113 TX Vref=26, minBit 5, minWin=24, winSum=414
8551 00:56:33.608644 TX Vref=28, minBit 8, minWin=25, winSum=419
8552 00:56:33.611876 TX Vref=30, minBit 0, minWin=25, winSum=421
8553 00:56:33.615615 TX Vref=32, minBit 11, minWin=24, winSum=412
8554 00:56:33.618845 TX Vref=34, minBit 8, minWin=23, winSum=399
8555 00:56:33.621821 TX Vref=36, minBit 8, minWin=23, winSum=388
8556 00:56:33.628505 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 30
8557 00:56:33.628576
8558 00:56:33.631744 Final TX Range 0 Vref 30
8559 00:56:33.631814
8560 00:56:33.631872 ==
8561 00:56:33.635487 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 00:56:33.638882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 00:56:33.638960 ==
8564 00:56:33.639019
8565 00:56:33.639073
8566 00:56:33.642256 TX Vref Scan disable
8567 00:56:33.649327 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8568 00:56:33.649431 == TX Byte 0 ==
8569 00:56:33.652151 u2DelayCellOfst[0]=17 cells (5 PI)
8570 00:56:33.655611 u2DelayCellOfst[1]=14 cells (4 PI)
8571 00:56:33.658864 u2DelayCellOfst[2]=0 cells (0 PI)
8572 00:56:33.662558 u2DelayCellOfst[3]=7 cells (2 PI)
8573 00:56:33.665584 u2DelayCellOfst[4]=10 cells (3 PI)
8574 00:56:33.668949 u2DelayCellOfst[5]=17 cells (5 PI)
8575 00:56:33.672250 u2DelayCellOfst[6]=17 cells (5 PI)
8576 00:56:33.672344 u2DelayCellOfst[7]=7 cells (2 PI)
8577 00:56:33.678886 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8578 00:56:33.681763 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8579 00:56:33.685357 == TX Byte 1 ==
8580 00:56:33.685458 u2DelayCellOfst[8]=0 cells (0 PI)
8581 00:56:33.688918 u2DelayCellOfst[9]=3 cells (1 PI)
8582 00:56:33.691924 u2DelayCellOfst[10]=10 cells (3 PI)
8583 00:56:33.695721 u2DelayCellOfst[11]=7 cells (2 PI)
8584 00:56:33.698422 u2DelayCellOfst[12]=14 cells (4 PI)
8585 00:56:33.701959 u2DelayCellOfst[13]=17 cells (5 PI)
8586 00:56:33.705497 u2DelayCellOfst[14]=17 cells (5 PI)
8587 00:56:33.708746 u2DelayCellOfst[15]=17 cells (5 PI)
8588 00:56:33.711799 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8589 00:56:33.718244 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8590 00:56:33.718320 DramC Write-DBI on
8591 00:56:33.718379 ==
8592 00:56:33.721935 Dram Type= 6, Freq= 0, CH_1, rank 0
8593 00:56:33.725442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8594 00:56:33.728417 ==
8595 00:56:33.728517
8596 00:56:33.728602
8597 00:56:33.728684 TX Vref Scan disable
8598 00:56:33.732043 == TX Byte 0 ==
8599 00:56:33.735372 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8600 00:56:33.738354 == TX Byte 1 ==
8601 00:56:33.741842 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8602 00:56:33.745229 DramC Write-DBI off
8603 00:56:33.745328
8604 00:56:33.745413 [DATLAT]
8605 00:56:33.745495 Freq=1600, CH1 RK0
8606 00:56:33.745574
8607 00:56:33.748761 DATLAT Default: 0xf
8608 00:56:33.748837 0, 0xFFFF, sum = 0
8609 00:56:33.751979 1, 0xFFFF, sum = 0
8610 00:56:33.754981 2, 0xFFFF, sum = 0
8611 00:56:33.755057 3, 0xFFFF, sum = 0
8612 00:56:33.758409 4, 0xFFFF, sum = 0
8613 00:56:33.758485 5, 0xFFFF, sum = 0
8614 00:56:33.761904 6, 0xFFFF, sum = 0
8615 00:56:33.762012 7, 0xFFFF, sum = 0
8616 00:56:33.765479 8, 0xFFFF, sum = 0
8617 00:56:33.765555 9, 0xFFFF, sum = 0
8618 00:56:33.768314 10, 0xFFFF, sum = 0
8619 00:56:33.768391 11, 0xFFFF, sum = 0
8620 00:56:33.771566 12, 0xFFFF, sum = 0
8621 00:56:33.771643 13, 0xFFFF, sum = 0
8622 00:56:33.775251 14, 0x0, sum = 1
8623 00:56:33.775325 15, 0x0, sum = 2
8624 00:56:33.778881 16, 0x0, sum = 3
8625 00:56:33.778956 17, 0x0, sum = 4
8626 00:56:33.782222 best_step = 15
8627 00:56:33.782322
8628 00:56:33.782455 ==
8629 00:56:33.785343 Dram Type= 6, Freq= 0, CH_1, rank 0
8630 00:56:33.788590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8631 00:56:33.788665 ==
8632 00:56:33.788722 RX Vref Scan: 1
8633 00:56:33.792013
8634 00:56:33.792087 Set Vref Range= 24 -> 127
8635 00:56:33.792144
8636 00:56:33.795127 RX Vref 24 -> 127, step: 1
8637 00:56:33.795201
8638 00:56:33.798374 RX Delay 19 -> 252, step: 4
8639 00:56:33.798448
8640 00:56:33.802013 Set Vref, RX VrefLevel [Byte0]: 24
8641 00:56:33.805230 [Byte1]: 24
8642 00:56:33.805327
8643 00:56:33.808242 Set Vref, RX VrefLevel [Byte0]: 25
8644 00:56:33.811668 [Byte1]: 25
8645 00:56:33.811742
8646 00:56:33.815135 Set Vref, RX VrefLevel [Byte0]: 26
8647 00:56:33.818450 [Byte1]: 26
8648 00:56:33.822431
8649 00:56:33.822497 Set Vref, RX VrefLevel [Byte0]: 27
8650 00:56:33.825719 [Byte1]: 27
8651 00:56:33.829493
8652 00:56:33.829600 Set Vref, RX VrefLevel [Byte0]: 28
8653 00:56:33.833288 [Byte1]: 28
8654 00:56:33.837264
8655 00:56:33.837354 Set Vref, RX VrefLevel [Byte0]: 29
8656 00:56:33.840951 [Byte1]: 29
8657 00:56:33.845084
8658 00:56:33.845169 Set Vref, RX VrefLevel [Byte0]: 30
8659 00:56:33.848350 [Byte1]: 30
8660 00:56:33.852276
8661 00:56:33.852336 Set Vref, RX VrefLevel [Byte0]: 31
8662 00:56:33.855562 [Byte1]: 31
8663 00:56:33.860415
8664 00:56:33.860477 Set Vref, RX VrefLevel [Byte0]: 32
8665 00:56:33.863440 [Byte1]: 32
8666 00:56:33.867861
8667 00:56:33.867939 Set Vref, RX VrefLevel [Byte0]: 33
8668 00:56:33.870684 [Byte1]: 33
8669 00:56:33.875455
8670 00:56:33.875553 Set Vref, RX VrefLevel [Byte0]: 34
8671 00:56:33.878737 [Byte1]: 34
8672 00:56:33.882673
8673 00:56:33.882773 Set Vref, RX VrefLevel [Byte0]: 35
8674 00:56:33.885943 [Byte1]: 35
8675 00:56:33.890270
8676 00:56:33.890344 Set Vref, RX VrefLevel [Byte0]: 36
8677 00:56:33.893519 [Byte1]: 36
8678 00:56:33.898205
8679 00:56:33.898280 Set Vref, RX VrefLevel [Byte0]: 37
8680 00:56:33.901218 [Byte1]: 37
8681 00:56:33.905595
8682 00:56:33.905666 Set Vref, RX VrefLevel [Byte0]: 38
8683 00:56:33.909010 [Byte1]: 38
8684 00:56:33.913102
8685 00:56:33.913179 Set Vref, RX VrefLevel [Byte0]: 39
8686 00:56:33.916713 [Byte1]: 39
8687 00:56:33.920443
8688 00:56:33.920545 Set Vref, RX VrefLevel [Byte0]: 40
8689 00:56:33.923850 [Byte1]: 40
8690 00:56:33.928504
8691 00:56:33.928604 Set Vref, RX VrefLevel [Byte0]: 41
8692 00:56:33.931307 [Byte1]: 41
8693 00:56:33.935987
8694 00:56:33.936072 Set Vref, RX VrefLevel [Byte0]: 42
8695 00:56:33.938975 [Byte1]: 42
8696 00:56:33.943372
8697 00:56:33.943439 Set Vref, RX VrefLevel [Byte0]: 43
8698 00:56:33.946398 [Byte1]: 43
8699 00:56:33.950725
8700 00:56:33.950788 Set Vref, RX VrefLevel [Byte0]: 44
8701 00:56:33.954376 [Byte1]: 44
8702 00:56:33.958623
8703 00:56:33.958693 Set Vref, RX VrefLevel [Byte0]: 45
8704 00:56:33.961516 [Byte1]: 45
8705 00:56:33.966041
8706 00:56:33.966125 Set Vref, RX VrefLevel [Byte0]: 46
8707 00:56:33.969696 [Byte1]: 46
8708 00:56:33.973644
8709 00:56:33.973727 Set Vref, RX VrefLevel [Byte0]: 47
8710 00:56:33.977021 [Byte1]: 47
8711 00:56:33.981248
8712 00:56:33.981336 Set Vref, RX VrefLevel [Byte0]: 48
8713 00:56:33.984360 [Byte1]: 48
8714 00:56:33.989365
8715 00:56:33.989450 Set Vref, RX VrefLevel [Byte0]: 49
8716 00:56:33.992418 [Byte1]: 49
8717 00:56:33.996242
8718 00:56:33.996304 Set Vref, RX VrefLevel [Byte0]: 50
8719 00:56:33.999672 [Byte1]: 50
8720 00:56:34.003875
8721 00:56:34.003946 Set Vref, RX VrefLevel [Byte0]: 51
8722 00:56:34.007055 [Byte1]: 51
8723 00:56:34.011608
8724 00:56:34.011700 Set Vref, RX VrefLevel [Byte0]: 52
8725 00:56:34.014801 [Byte1]: 52
8726 00:56:34.019157
8727 00:56:34.019253 Set Vref, RX VrefLevel [Byte0]: 53
8728 00:56:34.022288 [Byte1]: 53
8729 00:56:34.026910
8730 00:56:34.026998 Set Vref, RX VrefLevel [Byte0]: 54
8731 00:56:34.029596 [Byte1]: 54
8732 00:56:34.034243
8733 00:56:34.034307 Set Vref, RX VrefLevel [Byte0]: 55
8734 00:56:34.037554 [Byte1]: 55
8735 00:56:34.041938
8736 00:56:34.042064 Set Vref, RX VrefLevel [Byte0]: 56
8737 00:56:34.044852 [Byte1]: 56
8738 00:56:34.049472
8739 00:56:34.049560 Set Vref, RX VrefLevel [Byte0]: 57
8740 00:56:34.052412 [Byte1]: 57
8741 00:56:34.056912
8742 00:56:34.056999 Set Vref, RX VrefLevel [Byte0]: 58
8743 00:56:34.060161 [Byte1]: 58
8744 00:56:34.064546
8745 00:56:34.064621 Set Vref, RX VrefLevel [Byte0]: 59
8746 00:56:34.068005 [Byte1]: 59
8747 00:56:34.072026
8748 00:56:34.072101 Set Vref, RX VrefLevel [Byte0]: 60
8749 00:56:34.075518 [Byte1]: 60
8750 00:56:34.079593
8751 00:56:34.079692 Set Vref, RX VrefLevel [Byte0]: 61
8752 00:56:34.082919 [Byte1]: 61
8753 00:56:34.087417
8754 00:56:34.087485 Set Vref, RX VrefLevel [Byte0]: 62
8755 00:56:34.090448 [Byte1]: 62
8756 00:56:34.094783
8757 00:56:34.094874 Set Vref, RX VrefLevel [Byte0]: 63
8758 00:56:34.098216 [Byte1]: 63
8759 00:56:34.102723
8760 00:56:34.102812 Set Vref, RX VrefLevel [Byte0]: 64
8761 00:56:34.105537 [Byte1]: 64
8762 00:56:34.109794
8763 00:56:34.109879 Set Vref, RX VrefLevel [Byte0]: 65
8764 00:56:34.113467 [Byte1]: 65
8765 00:56:34.117439
8766 00:56:34.117506 Set Vref, RX VrefLevel [Byte0]: 66
8767 00:56:34.120669 [Byte1]: 66
8768 00:56:34.124989
8769 00:56:34.125061 Set Vref, RX VrefLevel [Byte0]: 67
8770 00:56:34.128470 [Byte1]: 67
8771 00:56:34.132775
8772 00:56:34.132867 Set Vref, RX VrefLevel [Byte0]: 68
8773 00:56:34.136237 [Byte1]: 68
8774 00:56:34.140147
8775 00:56:34.140234 Set Vref, RX VrefLevel [Byte0]: 69
8776 00:56:34.143561 [Byte1]: 69
8777 00:56:34.147817
8778 00:56:34.147905 Set Vref, RX VrefLevel [Byte0]: 70
8779 00:56:34.150870 [Byte1]: 70
8780 00:56:34.155336
8781 00:56:34.155423 Set Vref, RX VrefLevel [Byte0]: 71
8782 00:56:34.158385 [Byte1]: 71
8783 00:56:34.162866
8784 00:56:34.162956 Set Vref, RX VrefLevel [Byte0]: 72
8785 00:56:34.166042 [Byte1]: 72
8786 00:56:34.170315
8787 00:56:34.170383 Set Vref, RX VrefLevel [Byte0]: 73
8788 00:56:34.173703 [Byte1]: 73
8789 00:56:34.178334
8790 00:56:34.178427 Final RX Vref Byte 0 = 58 to rank0
8791 00:56:34.181372 Final RX Vref Byte 1 = 57 to rank0
8792 00:56:34.184773 Final RX Vref Byte 0 = 58 to rank1
8793 00:56:34.188051 Final RX Vref Byte 1 = 57 to rank1==
8794 00:56:34.191412 Dram Type= 6, Freq= 0, CH_1, rank 0
8795 00:56:34.194938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 00:56:34.198356 ==
8797 00:56:34.198422 DQS Delay:
8798 00:56:34.198478 DQS0 = 0, DQS1 = 0
8799 00:56:34.201572 DQM Delay:
8800 00:56:34.201659 DQM0 = 131, DQM1 = 124
8801 00:56:34.205166 DQ Delay:
8802 00:56:34.208461 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8803 00:56:34.211321 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8804 00:56:34.215167 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =120
8805 00:56:34.218475 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8806 00:56:34.218551
8807 00:56:34.218610
8808 00:56:34.218665
8809 00:56:34.221394 [DramC_TX_OE_Calibration] TA2
8810 00:56:34.224688 Original DQ_B0 (3 6) =30, OEN = 27
8811 00:56:34.228369 Original DQ_B1 (3 6) =30, OEN = 27
8812 00:56:34.228466 24, 0x0, End_B0=24 End_B1=24
8813 00:56:34.232167 25, 0x0, End_B0=25 End_B1=25
8814 00:56:34.234828 26, 0x0, End_B0=26 End_B1=26
8815 00:56:34.238618 27, 0x0, End_B0=27 End_B1=27
8816 00:56:34.241745 28, 0x0, End_B0=28 End_B1=28
8817 00:56:34.241845 29, 0x0, End_B0=29 End_B1=29
8818 00:56:34.245237 30, 0x0, End_B0=30 End_B1=30
8819 00:56:34.248206 31, 0x4141, End_B0=30 End_B1=30
8820 00:56:34.251920 Byte0 end_step=30 best_step=27
8821 00:56:34.255090 Byte1 end_step=30 best_step=27
8822 00:56:34.255188 Byte0 TX OE(2T, 0.5T) = (3, 3)
8823 00:56:34.258467 Byte1 TX OE(2T, 0.5T) = (3, 3)
8824 00:56:34.258536
8825 00:56:34.258593
8826 00:56:34.268613 [DQSOSCAuto] RK0, (LSB)MR18= 0x14fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
8827 00:56:34.272136 CH1 RK0: MR19=302, MR18=14FE
8828 00:56:34.274882 CH1_RK0: MR19=0x302, MR18=0x14FE, DQSOSC=399, MR23=63, INC=23, DEC=15
8829 00:56:34.278196
8830 00:56:34.281496 ----->DramcWriteLeveling(PI) begin...
8831 00:56:34.281592 ==
8832 00:56:34.285349 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 00:56:34.288431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 00:56:34.288527 ==
8835 00:56:34.291908 Write leveling (Byte 0): 23 => 23
8836 00:56:34.294762 Write leveling (Byte 1): 30 => 30
8837 00:56:34.298209 DramcWriteLeveling(PI) end<-----
8838 00:56:34.298343
8839 00:56:34.298419 ==
8840 00:56:34.301532 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 00:56:34.304925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 00:56:34.305013 ==
8843 00:56:34.308625 [Gating] SW mode calibration
8844 00:56:34.315020 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8845 00:56:34.321959 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8846 00:56:34.325045 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 00:56:34.328527 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 00:56:34.332109 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8849 00:56:34.338428 1 4 12 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
8850 00:56:34.341906 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 00:56:34.344801 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 00:56:34.351788 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 00:56:34.355530 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 00:56:34.358644 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8855 00:56:34.365271 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8856 00:56:34.368903 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
8857 00:56:34.372082 1 5 12 | B1->B0 | 2d2d 2525 | 0 0 | (1 0) (0 0)
8858 00:56:34.378374 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8859 00:56:34.381911 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 00:56:34.385278 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 00:56:34.392044 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 00:56:34.395409 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 00:56:34.398459 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 00:56:34.405373 1 6 8 | B1->B0 | 2424 3838 | 0 1 | (0 0) (0 0)
8865 00:56:34.408756 1 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8866 00:56:34.412128 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 00:56:34.415404 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 00:56:34.422002 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 00:56:34.425621 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 00:56:34.428807 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 00:56:34.435789 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 00:56:34.438719 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8873 00:56:34.441950 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8874 00:56:34.448754 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8875 00:56:34.452557 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 00:56:34.455231 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 00:56:34.462299 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 00:56:34.465249 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 00:56:34.468562 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 00:56:34.475589 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 00:56:34.479058 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 00:56:34.481914 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 00:56:34.488864 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 00:56:34.492318 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 00:56:34.495594 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 00:56:34.499071 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 00:56:34.505213 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8888 00:56:34.508756 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8889 00:56:34.512054 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8890 00:56:34.519131 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 00:56:34.522428 Total UI for P1: 0, mck2ui 16
8892 00:56:34.525244 best dqsien dly found for B0: ( 1, 9, 8)
8893 00:56:34.525313 Total UI for P1: 0, mck2ui 16
8894 00:56:34.532097 best dqsien dly found for B1: ( 1, 9, 14)
8895 00:56:34.535586 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8896 00:56:34.539059 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8897 00:56:34.539127
8898 00:56:34.541971 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8899 00:56:34.545378 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8900 00:56:34.548899 [Gating] SW calibration Done
8901 00:56:34.548967 ==
8902 00:56:34.552129 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 00:56:34.555695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 00:56:34.555797 ==
8905 00:56:34.559230 RX Vref Scan: 0
8906 00:56:34.559331
8907 00:56:34.559424 RX Vref 0 -> 0, step: 1
8908 00:56:34.559512
8909 00:56:34.562265 RX Delay 0 -> 252, step: 8
8910 00:56:34.565711 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8911 00:56:34.572311 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8912 00:56:34.575892 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8913 00:56:34.579117 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8914 00:56:34.582427 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8915 00:56:34.585819 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8916 00:56:34.588754 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8917 00:56:34.595746 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8918 00:56:34.599106 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8919 00:56:34.601979 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8920 00:56:34.605371 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8921 00:56:34.608792 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8922 00:56:34.615678 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8923 00:56:34.619045 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8924 00:56:34.622503 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8925 00:56:34.625751 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8926 00:56:34.625840 ==
8927 00:56:34.629140 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 00:56:34.635604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 00:56:34.635703 ==
8930 00:56:34.635788 DQS Delay:
8931 00:56:34.639126 DQS0 = 0, DQS1 = 0
8932 00:56:34.639205 DQM Delay:
8933 00:56:34.642188 DQM0 = 132, DQM1 = 127
8934 00:56:34.642265 DQ Delay:
8935 00:56:34.645726 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8936 00:56:34.649153 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8937 00:56:34.652441 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8938 00:56:34.655444 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8939 00:56:34.655546
8940 00:56:34.655632
8941 00:56:34.655714 ==
8942 00:56:34.658985 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 00:56:34.662267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 00:56:34.665814 ==
8945 00:56:34.665916
8946 00:56:34.666004
8947 00:56:34.666061 TX Vref Scan disable
8948 00:56:34.668941 == TX Byte 0 ==
8949 00:56:34.672125 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8950 00:56:34.675738 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8951 00:56:34.679018 == TX Byte 1 ==
8952 00:56:34.682243 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8953 00:56:34.685770 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8954 00:56:34.685865 ==
8955 00:56:34.688990 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 00:56:34.695823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 00:56:34.695908 ==
8958 00:56:34.709340
8959 00:56:34.712719 TX Vref early break, caculate TX vref
8960 00:56:34.715764 TX Vref=16, minBit 8, minWin=22, winSum=378
8961 00:56:34.719080 TX Vref=18, minBit 8, minWin=22, winSum=386
8962 00:56:34.722549 TX Vref=20, minBit 8, minWin=23, winSum=394
8963 00:56:34.726026 TX Vref=22, minBit 8, minWin=24, winSum=404
8964 00:56:34.729438 TX Vref=24, minBit 0, minWin=25, winSum=416
8965 00:56:34.735847 TX Vref=26, minBit 8, minWin=25, winSum=419
8966 00:56:34.739294 TX Vref=28, minBit 9, minWin=25, winSum=425
8967 00:56:34.742825 TX Vref=30, minBit 0, minWin=25, winSum=419
8968 00:56:34.746199 TX Vref=32, minBit 5, minWin=25, winSum=418
8969 00:56:34.749049 TX Vref=34, minBit 0, minWin=24, winSum=404
8970 00:56:34.752622 TX Vref=36, minBit 0, minWin=23, winSum=392
8971 00:56:34.759397 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 28
8972 00:56:34.759470
8973 00:56:34.762910 Final TX Range 0 Vref 28
8974 00:56:34.762976
8975 00:56:34.763031 ==
8976 00:56:34.765968 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 00:56:34.769031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 00:56:34.769130 ==
8979 00:56:34.769216
8980 00:56:34.769308
8981 00:56:34.772623 TX Vref Scan disable
8982 00:56:34.779621 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8983 00:56:34.779698 == TX Byte 0 ==
8984 00:56:34.782338 u2DelayCellOfst[0]=14 cells (4 PI)
8985 00:56:34.785732 u2DelayCellOfst[1]=7 cells (2 PI)
8986 00:56:34.789414 u2DelayCellOfst[2]=0 cells (0 PI)
8987 00:56:34.792744 u2DelayCellOfst[3]=3 cells (1 PI)
8988 00:56:34.795984 u2DelayCellOfst[4]=3 cells (1 PI)
8989 00:56:34.799380 u2DelayCellOfst[5]=14 cells (4 PI)
8990 00:56:34.802500 u2DelayCellOfst[6]=10 cells (3 PI)
8991 00:56:34.805769 u2DelayCellOfst[7]=3 cells (1 PI)
8992 00:56:34.809487 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8993 00:56:34.812675 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8994 00:56:34.815903 == TX Byte 1 ==
8995 00:56:34.815979 u2DelayCellOfst[8]=0 cells (0 PI)
8996 00:56:34.819411 u2DelayCellOfst[9]=7 cells (2 PI)
8997 00:56:34.822852 u2DelayCellOfst[10]=10 cells (3 PI)
8998 00:56:34.825905 u2DelayCellOfst[11]=7 cells (2 PI)
8999 00:56:34.829421 u2DelayCellOfst[12]=14 cells (4 PI)
9000 00:56:34.832955 u2DelayCellOfst[13]=17 cells (5 PI)
9001 00:56:34.836033 u2DelayCellOfst[14]=17 cells (5 PI)
9002 00:56:34.839784 u2DelayCellOfst[15]=17 cells (5 PI)
9003 00:56:34.842776 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
9004 00:56:34.849798 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
9005 00:56:34.849874 DramC Write-DBI on
9006 00:56:34.849932 ==
9007 00:56:34.853207 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 00:56:34.855916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 00:56:34.855992 ==
9010 00:56:34.856050
9011 00:56:34.859279
9012 00:56:34.859354 TX Vref Scan disable
9013 00:56:34.862605 == TX Byte 0 ==
9014 00:56:34.866168 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9015 00:56:34.869611 == TX Byte 1 ==
9016 00:56:34.872973 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
9017 00:56:34.873049 DramC Write-DBI off
9018 00:56:34.876504
9019 00:56:34.876594 [DATLAT]
9020 00:56:34.876653 Freq=1600, CH1 RK1
9021 00:56:34.876723
9022 00:56:34.879268 DATLAT Default: 0xf
9023 00:56:34.879343 0, 0xFFFF, sum = 0
9024 00:56:34.882655 1, 0xFFFF, sum = 0
9025 00:56:34.882734 2, 0xFFFF, sum = 0
9026 00:56:34.886116 3, 0xFFFF, sum = 0
9027 00:56:34.886193 4, 0xFFFF, sum = 0
9028 00:56:34.889604 5, 0xFFFF, sum = 0
9029 00:56:34.892555 6, 0xFFFF, sum = 0
9030 00:56:34.892632 7, 0xFFFF, sum = 0
9031 00:56:34.895952 8, 0xFFFF, sum = 0
9032 00:56:34.896052 9, 0xFFFF, sum = 0
9033 00:56:34.899263 10, 0xFFFF, sum = 0
9034 00:56:34.899340 11, 0xFFFF, sum = 0
9035 00:56:34.902835 12, 0xFFFF, sum = 0
9036 00:56:34.902911 13, 0xFFFF, sum = 0
9037 00:56:34.905940 14, 0x0, sum = 1
9038 00:56:34.906028 15, 0x0, sum = 2
9039 00:56:34.909340 16, 0x0, sum = 3
9040 00:56:34.909419 17, 0x0, sum = 4
9041 00:56:34.912821 best_step = 15
9042 00:56:34.912896
9043 00:56:34.912953 ==
9044 00:56:34.916356 Dram Type= 6, Freq= 0, CH_1, rank 1
9045 00:56:34.919274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9046 00:56:34.919357 ==
9047 00:56:34.919420 RX Vref Scan: 0
9048 00:56:34.919479
9049 00:56:34.922419 RX Vref 0 -> 0, step: 1
9050 00:56:34.922483
9051 00:56:34.925879 RX Delay 11 -> 252, step: 4
9052 00:56:34.929554 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9053 00:56:34.935954 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9054 00:56:34.939472 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9055 00:56:34.942480 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9056 00:56:34.946094 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
9057 00:56:34.948929 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9058 00:56:34.955790 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9059 00:56:34.959077 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9060 00:56:34.962521 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9061 00:56:34.965709 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9062 00:56:34.969198 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
9063 00:56:34.972551 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9064 00:56:34.979381 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9065 00:56:34.982449 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9066 00:56:34.985865 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9067 00:56:34.989158 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9068 00:56:34.989227 ==
9069 00:56:34.992490 Dram Type= 6, Freq= 0, CH_1, rank 1
9070 00:56:34.999276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9071 00:56:34.999356 ==
9072 00:56:34.999414 DQS Delay:
9073 00:56:35.002932 DQS0 = 0, DQS1 = 0
9074 00:56:35.003006 DQM Delay:
9075 00:56:35.003065 DQM0 = 129, DQM1 = 126
9076 00:56:35.005900 DQ Delay:
9077 00:56:35.009499 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9078 00:56:35.012818 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9079 00:56:35.016318 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
9080 00:56:35.019171 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
9081 00:56:35.019238
9082 00:56:35.019292
9083 00:56:35.019344
9084 00:56:35.022437 [DramC_TX_OE_Calibration] TA2
9085 00:56:35.025719 Original DQ_B0 (3 6) =30, OEN = 27
9086 00:56:35.029303 Original DQ_B1 (3 6) =30, OEN = 27
9087 00:56:35.032357 24, 0x0, End_B0=24 End_B1=24
9088 00:56:35.032427 25, 0x0, End_B0=25 End_B1=25
9089 00:56:35.035789 26, 0x0, End_B0=26 End_B1=26
9090 00:56:35.038903 27, 0x0, End_B0=27 End_B1=27
9091 00:56:35.042273 28, 0x0, End_B0=28 End_B1=28
9092 00:56:35.045565 29, 0x0, End_B0=29 End_B1=29
9093 00:56:35.045635 30, 0x0, End_B0=30 End_B1=30
9094 00:56:35.049699 31, 0x4141, End_B0=30 End_B1=30
9095 00:56:35.052343 Byte0 end_step=30 best_step=27
9096 00:56:35.055892 Byte1 end_step=30 best_step=27
9097 00:56:35.059068 Byte0 TX OE(2T, 0.5T) = (3, 3)
9098 00:56:35.062366 Byte1 TX OE(2T, 0.5T) = (3, 3)
9099 00:56:35.062434
9100 00:56:35.062491
9101 00:56:35.069251 [DQSOSCAuto] RK1, (LSB)MR18= 0xd14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 403 ps
9102 00:56:35.072220 CH1 RK1: MR19=303, MR18=D14
9103 00:56:35.079694 CH1_RK1: MR19=0x303, MR18=0xD14, DQSOSC=399, MR23=63, INC=23, DEC=15
9104 00:56:35.082371 [RxdqsGatingPostProcess] freq 1600
9105 00:56:35.085975 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9106 00:56:35.089357 best DQS0 dly(2T, 0.5T) = (1, 1)
9107 00:56:35.092889 best DQS1 dly(2T, 0.5T) = (1, 1)
9108 00:56:35.095970 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9109 00:56:35.099325 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9110 00:56:35.102416 best DQS0 dly(2T, 0.5T) = (1, 1)
9111 00:56:35.105890 best DQS1 dly(2T, 0.5T) = (1, 1)
9112 00:56:35.109259 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9113 00:56:35.112790 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9114 00:56:35.112857 Pre-setting of DQS Precalculation
9115 00:56:35.119380 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9116 00:56:35.125926 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9117 00:56:35.132391 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9118 00:56:35.132486
9119 00:56:35.132541
9120 00:56:35.135565 [Calibration Summary] 3200 Mbps
9121 00:56:35.138948 CH 0, Rank 0
9122 00:56:35.139010 SW Impedance : PASS
9123 00:56:35.142493 DUTY Scan : NO K
9124 00:56:35.145576 ZQ Calibration : PASS
9125 00:56:35.145638 Jitter Meter : NO K
9126 00:56:35.149053 CBT Training : PASS
9127 00:56:35.152346 Write leveling : PASS
9128 00:56:35.152459 RX DQS gating : PASS
9129 00:56:35.155656 RX DQ/DQS(RDDQC) : PASS
9130 00:56:35.159039 TX DQ/DQS : PASS
9131 00:56:35.159103 RX DATLAT : PASS
9132 00:56:35.162087 RX DQ/DQS(Engine): PASS
9133 00:56:35.162146 TX OE : PASS
9134 00:56:35.165431 All Pass.
9135 00:56:35.165522
9136 00:56:35.165574 CH 0, Rank 1
9137 00:56:35.169146 SW Impedance : PASS
9138 00:56:35.169215 DUTY Scan : NO K
9139 00:56:35.172486 ZQ Calibration : PASS
9140 00:56:35.175958 Jitter Meter : NO K
9141 00:56:35.176026 CBT Training : PASS
9142 00:56:35.179247 Write leveling : PASS
9143 00:56:35.182540 RX DQS gating : PASS
9144 00:56:35.182630 RX DQ/DQS(RDDQC) : PASS
9145 00:56:35.186242 TX DQ/DQS : PASS
9146 00:56:35.189268 RX DATLAT : PASS
9147 00:56:35.189339 RX DQ/DQS(Engine): PASS
9148 00:56:35.192236 TX OE : PASS
9149 00:56:35.192336 All Pass.
9150 00:56:35.192397
9151 00:56:35.195717 CH 1, Rank 0
9152 00:56:35.195790 SW Impedance : PASS
9153 00:56:35.199325 DUTY Scan : NO K
9154 00:56:35.202699 ZQ Calibration : PASS
9155 00:56:35.202761 Jitter Meter : NO K
9156 00:56:35.205586 CBT Training : PASS
9157 00:56:35.205652 Write leveling : PASS
9158 00:56:35.209275 RX DQS gating : PASS
9159 00:56:35.212494 RX DQ/DQS(RDDQC) : PASS
9160 00:56:35.212559 TX DQ/DQS : PASS
9161 00:56:35.215877 RX DATLAT : PASS
9162 00:56:35.219323 RX DQ/DQS(Engine): PASS
9163 00:56:35.219393 TX OE : PASS
9164 00:56:35.222651 All Pass.
9165 00:56:35.222717
9166 00:56:35.222772 CH 1, Rank 1
9167 00:56:35.225811 SW Impedance : PASS
9168 00:56:35.225879 DUTY Scan : NO K
9169 00:56:35.229103 ZQ Calibration : PASS
9170 00:56:35.232466 Jitter Meter : NO K
9171 00:56:35.232541 CBT Training : PASS
9172 00:56:35.235897 Write leveling : PASS
9173 00:56:35.239153 RX DQS gating : PASS
9174 00:56:35.239224 RX DQ/DQS(RDDQC) : PASS
9175 00:56:35.242214 TX DQ/DQS : PASS
9176 00:56:35.242280 RX DATLAT : PASS
9177 00:56:35.246015 RX DQ/DQS(Engine): PASS
9178 00:56:35.249032 TX OE : PASS
9179 00:56:35.249102 All Pass.
9180 00:56:35.249159
9181 00:56:35.252220 DramC Write-DBI on
9182 00:56:35.252290 PER_BANK_REFRESH: Hybrid Mode
9183 00:56:35.255912 TX_TRACKING: ON
9184 00:56:35.266214 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9185 00:56:35.272616 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9186 00:56:35.279037 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9187 00:56:35.282671 [FAST_K] Save calibration result to emmc
9188 00:56:35.286187 sync common calibartion params.
9189 00:56:35.289091 sync cbt_mode0:1, 1:1
9190 00:56:35.289161 dram_init: ddr_geometry: 2
9191 00:56:35.292691 dram_init: ddr_geometry: 2
9192 00:56:35.295846 dram_init: ddr_geometry: 2
9193 00:56:35.299367 0:dram_rank_size:100000000
9194 00:56:35.299439 1:dram_rank_size:100000000
9195 00:56:35.306170 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9196 00:56:35.309033 DFS_SHUFFLE_HW_MODE: ON
9197 00:56:35.312615 dramc_set_vcore_voltage set vcore to 725000
9198 00:56:35.312697 Read voltage for 1600, 0
9199 00:56:35.316022 Vio18 = 0
9200 00:56:35.316086 Vcore = 725000
9201 00:56:35.316142 Vdram = 0
9202 00:56:35.319456 Vddq = 0
9203 00:56:35.319520 Vmddr = 0
9204 00:56:35.322741 switch to 3200 Mbps bootup
9205 00:56:35.322806 [DramcRunTimeConfig]
9206 00:56:35.322890 PHYPLL
9207 00:56:35.325934 DPM_CONTROL_AFTERK: ON
9208 00:56:35.329406 PER_BANK_REFRESH: ON
9209 00:56:35.329497 REFRESH_OVERHEAD_REDUCTION: ON
9210 00:56:35.332495 CMD_PICG_NEW_MODE: OFF
9211 00:56:35.336081 XRTWTW_NEW_MODE: ON
9212 00:56:35.336161 XRTRTR_NEW_MODE: ON
9213 00:56:35.339513 TX_TRACKING: ON
9214 00:56:35.339582 RDSEL_TRACKING: OFF
9215 00:56:35.343020 DQS Precalculation for DVFS: ON
9216 00:56:35.343099 RX_TRACKING: OFF
9217 00:56:35.345822 HW_GATING DBG: ON
9218 00:56:35.345918 ZQCS_ENABLE_LP4: ON
9219 00:56:35.349227 RX_PICG_NEW_MODE: ON
9220 00:56:35.352745 TX_PICG_NEW_MODE: ON
9221 00:56:35.352818 ENABLE_RX_DCM_DPHY: ON
9222 00:56:35.356087 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9223 00:56:35.359322 DUMMY_READ_FOR_TRACKING: OFF
9224 00:56:35.362680 !!! SPM_CONTROL_AFTERK: OFF
9225 00:56:35.362747 !!! SPM could not control APHY
9226 00:56:35.366424 IMPEDANCE_TRACKING: ON
9227 00:56:35.369639 TEMP_SENSOR: ON
9228 00:56:35.369727 HW_SAVE_FOR_SR: OFF
9229 00:56:35.372559 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9230 00:56:35.375909 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9231 00:56:35.379462 Read ODT Tracking: ON
9232 00:56:35.379535 Refresh Rate DeBounce: ON
9233 00:56:35.382726 DFS_NO_QUEUE_FLUSH: ON
9234 00:56:35.385887 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9235 00:56:35.389624 ENABLE_DFS_RUNTIME_MRW: OFF
9236 00:56:35.389730 DDR_RESERVE_NEW_MODE: ON
9237 00:56:35.392596 MR_CBT_SWITCH_FREQ: ON
9238 00:56:35.395996 =========================
9239 00:56:35.413861 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9240 00:56:35.417203 dram_init: ddr_geometry: 2
9241 00:56:35.435390 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9242 00:56:35.438623 dram_init: dram init end (result: 0)
9243 00:56:35.445501 DRAM-K: Full calibration passed in 24596 msecs
9244 00:56:35.448655 MRC: failed to locate region type 0.
9245 00:56:35.448742 DRAM rank0 size:0x100000000,
9246 00:56:35.451995 DRAM rank1 size=0x100000000
9247 00:56:35.462133 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9248 00:56:35.468364 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9249 00:56:35.475107 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9250 00:56:35.481926 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9251 00:56:35.485119 DRAM rank0 size:0x100000000,
9252 00:56:35.488576 DRAM rank1 size=0x100000000
9253 00:56:35.488675 CBMEM:
9254 00:56:35.491932 IMD: root @ 0xfffff000 254 entries.
9255 00:56:35.495634 IMD: root @ 0xffffec00 62 entries.
9256 00:56:35.498500 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9257 00:56:35.502437 WARNING: RO_VPD is uninitialized or empty.
9258 00:56:35.508602 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9259 00:56:35.515764 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9260 00:56:35.528317 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9261 00:56:35.539352 BS: romstage times (exec / console): total (unknown) / 24098 ms
9262 00:56:35.539429
9263 00:56:35.539487
9264 00:56:35.549713 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9265 00:56:35.552891 ARM64: Exception handlers installed.
9266 00:56:35.556446 ARM64: Testing exception
9267 00:56:35.559620 ARM64: Done test exception
9268 00:56:35.559685 Enumerating buses...
9269 00:56:35.563179 Show all devs... Before device enumeration.
9270 00:56:35.566223 Root Device: enabled 1
9271 00:56:35.569879 CPU_CLUSTER: 0: enabled 1
9272 00:56:35.569942 CPU: 00: enabled 1
9273 00:56:35.573182 Compare with tree...
9274 00:56:35.573298 Root Device: enabled 1
9275 00:56:35.576370 CPU_CLUSTER: 0: enabled 1
9276 00:56:35.580047 CPU: 00: enabled 1
9277 00:56:35.580112 Root Device scanning...
9278 00:56:35.583278 scan_static_bus for Root Device
9279 00:56:35.586718 CPU_CLUSTER: 0 enabled
9280 00:56:35.589653 scan_static_bus for Root Device done
9281 00:56:35.593092 scan_bus: bus Root Device finished in 8 msecs
9282 00:56:35.593153 done
9283 00:56:35.600035 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9284 00:56:35.603231 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9285 00:56:35.606514 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9286 00:56:35.613359 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9287 00:56:35.617087 Allocating resources...
9288 00:56:35.617156 Reading resources...
9289 00:56:35.620322 Root Device read_resources bus 0 link: 0
9290 00:56:35.623446 DRAM rank0 size:0x100000000,
9291 00:56:35.626573 DRAM rank1 size=0x100000000
9292 00:56:35.630103 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9293 00:56:35.633317 CPU: 00 missing read_resources
9294 00:56:35.637041 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9295 00:56:35.640385 Root Device read_resources bus 0 link: 0 done
9296 00:56:35.644020 Done reading resources.
9297 00:56:35.647516 Show resources in subtree (Root Device)...After reading.
9298 00:56:35.653790 Root Device child on link 0 CPU_CLUSTER: 0
9299 00:56:35.656913 CPU_CLUSTER: 0 child on link 0 CPU: 00
9300 00:56:35.663998 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9301 00:56:35.667269 CPU: 00
9302 00:56:35.670550 Root Device assign_resources, bus 0 link: 0
9303 00:56:35.673525 CPU_CLUSTER: 0 missing set_resources
9304 00:56:35.677129 Root Device assign_resources, bus 0 link: 0 done
9305 00:56:35.680600 Done setting resources.
9306 00:56:35.683943 Show resources in subtree (Root Device)...After assigning values.
9307 00:56:35.690524 Root Device child on link 0 CPU_CLUSTER: 0
9308 00:56:35.693909 CPU_CLUSTER: 0 child on link 0 CPU: 00
9309 00:56:35.700801 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9310 00:56:35.703754 CPU: 00
9311 00:56:35.703823 Done allocating resources.
9312 00:56:35.710453 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9313 00:56:35.713917 Enabling resources...
9314 00:56:35.714029 done.
9315 00:56:35.717122 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9316 00:56:35.720411 Initializing devices...
9317 00:56:35.720499 Root Device init
9318 00:56:35.723679 init hardware done!
9319 00:56:35.723778 0x00000018: ctrlr->caps
9320 00:56:35.726749 52.000 MHz: ctrlr->f_max
9321 00:56:35.730259 0.400 MHz: ctrlr->f_min
9322 00:56:35.733945 0x40ff8080: ctrlr->voltages
9323 00:56:35.734051 sclk: 390625
9324 00:56:35.734109 Bus Width = 1
9325 00:56:35.736768 sclk: 390625
9326 00:56:35.736834 Bus Width = 1
9327 00:56:35.740953 Early init status = 3
9328 00:56:35.743769 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9329 00:56:35.747304 in-header: 03 fc 00 00 01 00 00 00
9330 00:56:35.750647 in-data: 00
9331 00:56:35.753961 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9332 00:56:35.758173 in-header: 03 fd 00 00 00 00 00 00
9333 00:56:35.762209 in-data:
9334 00:56:35.764950 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9335 00:56:35.768625 in-header: 03 fc 00 00 01 00 00 00
9336 00:56:35.771551 in-data: 00
9337 00:56:35.775168 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9338 00:56:35.780136 in-header: 03 fd 00 00 00 00 00 00
9339 00:56:35.783651 in-data:
9340 00:56:35.786653 [SSUSB] Setting up USB HOST controller...
9341 00:56:35.789898 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9342 00:56:35.793195 [SSUSB] phy power-on done.
9343 00:56:35.796507 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9344 00:56:35.803463 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9345 00:56:35.806311 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9346 00:56:35.813695 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9347 00:56:35.819833 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9348 00:56:35.826333 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9349 00:56:35.833215 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9350 00:56:35.839686 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9351 00:56:35.842936 SPM: binary array size = 0x9dc
9352 00:56:35.846787 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9353 00:56:35.852979 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9354 00:56:35.859848 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9355 00:56:35.863282 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9356 00:56:35.866498 configure_display: Starting display init
9357 00:56:35.903077 anx7625_power_on_init: Init interface.
9358 00:56:35.906475 anx7625_disable_pd_protocol: Disabled PD feature.
9359 00:56:35.910095 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9360 00:56:35.937543 anx7625_start_dp_work: Secure OCM version=00
9361 00:56:35.940930 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9362 00:56:35.955714 sp_tx_get_edid_block: EDID Block = 1
9363 00:56:36.058721 Extracted contents:
9364 00:56:36.061691 header: 00 ff ff ff ff ff ff 00
9365 00:56:36.065123 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9366 00:56:36.068525 version: 01 04
9367 00:56:36.071778 basic params: 95 1f 11 78 0a
9368 00:56:36.075062 chroma info: 76 90 94 55 54 90 27 21 50 54
9369 00:56:36.078544 established: 00 00 00
9370 00:56:36.084831 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9371 00:56:36.088042 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9372 00:56:36.095031 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9373 00:56:36.101265 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9374 00:56:36.108223 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9375 00:56:36.111658 extensions: 00
9376 00:56:36.111724 checksum: fb
9377 00:56:36.111786
9378 00:56:36.114695 Manufacturer: IVO Model 57d Serial Number 0
9379 00:56:36.117798 Made week 0 of 2020
9380 00:56:36.117873 EDID version: 1.4
9381 00:56:36.121132 Digital display
9382 00:56:36.124432 6 bits per primary color channel
9383 00:56:36.124503 DisplayPort interface
9384 00:56:36.127879 Maximum image size: 31 cm x 17 cm
9385 00:56:36.131510 Gamma: 220%
9386 00:56:36.131578 Check DPMS levels
9387 00:56:36.134855 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9388 00:56:36.138291 First detailed timing is preferred timing
9389 00:56:36.141256 Established timings supported:
9390 00:56:36.144849 Standard timings supported:
9391 00:56:36.144920 Detailed timings
9392 00:56:36.151376 Hex of detail: 383680a07038204018303c0035ae10000019
9393 00:56:36.154822 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9394 00:56:36.158210 0780 0798 07c8 0820 hborder 0
9395 00:56:36.165050 0438 043b 0447 0458 vborder 0
9396 00:56:36.165123 -hsync -vsync
9397 00:56:36.168412 Did detailed timing
9398 00:56:36.171794 Hex of detail: 000000000000000000000000000000000000
9399 00:56:36.175262 Manufacturer-specified data, tag 0
9400 00:56:36.181565 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9401 00:56:36.181637 ASCII string: InfoVision
9402 00:56:36.188362 Hex of detail: 000000fe00523134304e574635205248200a
9403 00:56:36.188435 ASCII string: R140NWF5 RH
9404 00:56:36.191635 Checksum
9405 00:56:36.191702 Checksum: 0xfb (valid)
9406 00:56:36.198384 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9407 00:56:36.201606 DSI data_rate: 832800000 bps
9408 00:56:36.204918 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9409 00:56:36.208186 anx7625_parse_edid: pixelclock(138800).
9410 00:56:36.214586 hactive(1920), hsync(48), hfp(24), hbp(88)
9411 00:56:36.217950 vactive(1080), vsync(12), vfp(3), vbp(17)
9412 00:56:36.221441 anx7625_dsi_config: config dsi.
9413 00:56:36.227861 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9414 00:56:36.240053 anx7625_dsi_config: success to config DSI
9415 00:56:36.243406 anx7625_dp_start: MIPI phy setup OK.
9416 00:56:36.247177 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9417 00:56:36.250471 mtk_ddp_mode_set invalid vrefresh 60
9418 00:56:36.253806 main_disp_path_setup
9419 00:56:36.253900 ovl_layer_smi_id_en
9420 00:56:36.257247 ovl_layer_smi_id_en
9421 00:56:36.257342 ccorr_config
9422 00:56:36.257426 aal_config
9423 00:56:36.260736 gamma_config
9424 00:56:36.260818 postmask_config
9425 00:56:36.263851 dither_config
9426 00:56:36.267226 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9427 00:56:36.273665 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9428 00:56:36.277076 Root Device init finished in 551 msecs
9429 00:56:36.277147 CPU_CLUSTER: 0 init
9430 00:56:36.287242 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9431 00:56:36.290641 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9432 00:56:36.294037 APU_MBOX 0x190000b0 = 0x10001
9433 00:56:36.297551 APU_MBOX 0x190001b0 = 0x10001
9434 00:56:36.300455 APU_MBOX 0x190005b0 = 0x10001
9435 00:56:36.303817 APU_MBOX 0x190006b0 = 0x10001
9436 00:56:36.307154 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9437 00:56:36.319290 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9438 00:56:36.331744 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9439 00:56:36.338169 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9440 00:56:36.349806 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9441 00:56:36.359311 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9442 00:56:36.362347 CPU_CLUSTER: 0 init finished in 81 msecs
9443 00:56:36.366185 Devices initialized
9444 00:56:36.369177 Show all devs... After init.
9445 00:56:36.369252 Root Device: enabled 1
9446 00:56:36.372737 CPU_CLUSTER: 0: enabled 1
9447 00:56:36.375868 CPU: 00: enabled 1
9448 00:56:36.379484 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9449 00:56:36.382584 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9450 00:56:36.386028 ELOG: NV offset 0x57f000 size 0x1000
9451 00:56:36.392834 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9452 00:56:36.399144 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9453 00:56:36.402773 ELOG: Event(17) added with size 13 at 2024-06-16 00:56:36 UTC
9454 00:56:36.406058 out: cmd=0x121: 03 db 21 01 00 00 00 00
9455 00:56:36.410168 in-header: 03 b7 00 00 2c 00 00 00
9456 00:56:36.423549 in-data: 82 9e cc 12 41 02 00 00 0a 00 00 00 06 80 00 00 94 29 d1 11 06 80 00 00 8a f1 bd 12 06 80 00 00 86 a2 c5 12 06 80 00 00 d5 1c cc 12
9457 00:56:36.430304 ELOG: Event(A1) added with size 10 at 2024-06-16 00:56:36 UTC
9458 00:56:36.437110 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9459 00:56:36.443500 ELOG: Event(A0) added with size 9 at 2024-06-16 00:56:36 UTC
9460 00:56:36.446677 elog_add_boot_reason: Logged dev mode boot
9461 00:56:36.450213 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9462 00:56:36.453876 Finalize devices...
9463 00:56:36.453967 Devices finalized
9464 00:56:36.460203 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9465 00:56:36.463221 Writing coreboot table at 0xffe64000
9466 00:56:36.467067 0. 000000000010a000-0000000000113fff: RAMSTAGE
9467 00:56:36.470546 1. 0000000040000000-00000000400fffff: RAM
9468 00:56:36.473405 2. 0000000040100000-000000004032afff: RAMSTAGE
9469 00:56:36.480299 3. 000000004032b000-00000000545fffff: RAM
9470 00:56:36.483430 4. 0000000054600000-000000005465ffff: BL31
9471 00:56:36.487607 5. 0000000054660000-00000000ffe63fff: RAM
9472 00:56:36.490626 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9473 00:56:36.496855 7. 0000000100000000-000000023fffffff: RAM
9474 00:56:36.496925 Passing 5 GPIOs to payload:
9475 00:56:36.503352 NAME | PORT | POLARITY | VALUE
9476 00:56:36.506905 EC in RW | 0x000000aa | low | undefined
9477 00:56:36.513842 EC interrupt | 0x00000005 | low | undefined
9478 00:56:36.516853 TPM interrupt | 0x000000ab | high | undefined
9479 00:56:36.520215 SD card detect | 0x00000011 | high | undefined
9480 00:56:36.526742 speaker enable | 0x00000093 | high | undefined
9481 00:56:36.530421 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9482 00:56:36.533935 in-header: 03 f9 00 00 02 00 00 00
9483 00:56:36.534065 in-data: 02 00
9484 00:56:36.537117 ADC[4]: Raw value=900959 ID=7
9485 00:56:36.540091 ADC[3]: Raw value=213336 ID=1
9486 00:56:36.540176 RAM Code: 0x71
9487 00:56:36.543397 ADC[6]: Raw value=74557 ID=0
9488 00:56:36.547348 ADC[5]: Raw value=212229 ID=1
9489 00:56:36.547423 SKU Code: 0x1
9490 00:56:36.553484 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b267
9491 00:56:36.557091 coreboot table: 964 bytes.
9492 00:56:36.560237 IMD ROOT 0. 0xfffff000 0x00001000
9493 00:56:36.563347 IMD SMALL 1. 0xffffe000 0x00001000
9494 00:56:36.567145 RO MCACHE 2. 0xffffc000 0x00001104
9495 00:56:36.570333 CONSOLE 3. 0xfff7c000 0x00080000
9496 00:56:36.573428 FMAP 4. 0xfff7b000 0x00000452
9497 00:56:36.576742 TIME STAMP 5. 0xfff7a000 0x00000910
9498 00:56:36.580225 VBOOT WORK 6. 0xfff66000 0x00014000
9499 00:56:36.583691 RAMOOPS 7. 0xffe66000 0x00100000
9500 00:56:36.586709 COREBOOT 8. 0xffe64000 0x00002000
9501 00:56:36.586785 IMD small region:
9502 00:56:36.590055 IMD ROOT 0. 0xffffec00 0x00000400
9503 00:56:36.593219 VPD 1. 0xffffeb80 0x0000006c
9504 00:56:36.596878 MMC STATUS 2. 0xffffeb60 0x00000004
9505 00:56:36.603466 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9506 00:56:36.603536 Probing TPM: done!
9507 00:56:36.610316 Connected to device vid:did:rid of 1ae0:0028:00
9508 00:56:36.616953 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9509 00:56:36.620370 Initialized TPM device CR50 revision 0
9510 00:56:36.623782 Checking cr50 for pending updates
9511 00:56:36.629616 Reading cr50 TPM mode
9512 00:56:36.638677 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9513 00:56:36.645231 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9514 00:56:36.685893 read SPI 0x3990ec 0x4f1b0: 34858 us, 9295 KB/s, 74.360 Mbps
9515 00:56:36.688710 Checking segment from ROM address 0x40100000
9516 00:56:36.692225 Checking segment from ROM address 0x4010001c
9517 00:56:36.698811 Loading segment from ROM address 0x40100000
9518 00:56:36.698890 code (compression=0)
9519 00:56:36.705690 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9520 00:56:36.715669 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9521 00:56:36.715743 it's not compressed!
9522 00:56:36.722416 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9523 00:56:36.725660 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9524 00:56:36.745876 Loading segment from ROM address 0x4010001c
9525 00:56:36.745954 Entry Point 0x80000000
9526 00:56:36.748960 Loaded segments
9527 00:56:36.752460 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9528 00:56:36.758928 Jumping to boot code at 0x80000000(0xffe64000)
9529 00:56:36.765557 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9530 00:56:36.772612 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9531 00:56:36.780378 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9532 00:56:36.783836 Checking segment from ROM address 0x40100000
9533 00:56:36.787033 Checking segment from ROM address 0x4010001c
9534 00:56:36.793493 Loading segment from ROM address 0x40100000
9535 00:56:36.793570 code (compression=1)
9536 00:56:36.800367 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9537 00:56:36.810224 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9538 00:56:36.810302 using LZMA
9539 00:56:36.818701 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9540 00:56:36.825105 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9541 00:56:36.828492 Loading segment from ROM address 0x4010001c
9542 00:56:36.828570 Entry Point 0x54601000
9543 00:56:36.831911 Loaded segments
9544 00:56:36.835485 NOTICE: MT8192 bl31_setup
9545 00:56:36.841949 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9546 00:56:36.845292 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9547 00:56:36.848600 WARNING: region 0:
9548 00:56:36.851985 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 00:56:36.852074 WARNING: region 1:
9550 00:56:36.858885 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9551 00:56:36.862360 WARNING: region 2:
9552 00:56:36.865751 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9553 00:56:36.868751 WARNING: region 3:
9554 00:56:36.872471 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9555 00:56:36.875365 WARNING: region 4:
9556 00:56:36.879139 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9557 00:56:36.882177 WARNING: region 5:
9558 00:56:36.885576 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9559 00:56:36.889196 WARNING: region 6:
9560 00:56:36.892267 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9561 00:56:36.892342 WARNING: region 7:
9562 00:56:36.899501 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9563 00:56:36.905775 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9564 00:56:36.909236 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9565 00:56:36.912600 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9566 00:56:36.918930 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9567 00:56:36.922441 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9568 00:56:36.925828 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9569 00:56:36.932728 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9570 00:56:36.935603 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9571 00:56:36.938991 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9572 00:56:36.945718 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9573 00:56:36.949208 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9574 00:56:36.952710 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9575 00:56:36.959324 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9576 00:56:36.962758 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9577 00:56:36.969713 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9578 00:56:36.972474 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9579 00:56:36.975810 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9580 00:56:36.982737 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9581 00:56:36.986348 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9582 00:56:36.989347 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9583 00:56:36.995911 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9584 00:56:36.999206 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9585 00:56:37.006440 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9586 00:56:37.009234 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9587 00:56:37.012606 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9588 00:56:37.019507 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9589 00:56:37.022811 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9590 00:56:37.026479 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9591 00:56:37.033321 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9592 00:56:37.036269 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9593 00:56:37.043043 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9594 00:56:37.046565 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9595 00:56:37.049503 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9596 00:56:37.056362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9597 00:56:37.059402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9598 00:56:37.062931 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9599 00:56:37.066194 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9600 00:56:37.069799 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9601 00:56:37.076276 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9602 00:56:37.079824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9603 00:56:37.083139 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9604 00:56:37.086610 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9605 00:56:37.093153 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9606 00:56:37.096687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9607 00:56:37.100091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9608 00:56:37.103349 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9609 00:56:37.109904 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9610 00:56:37.113241 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9611 00:56:37.116696 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9612 00:56:37.123534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9613 00:56:37.127027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9614 00:56:37.133351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9615 00:56:37.136897 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9616 00:56:37.140246 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9617 00:56:37.146685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9618 00:56:37.150099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9619 00:56:37.156946 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9620 00:56:37.160368 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9621 00:56:37.167306 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9622 00:56:37.170211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9623 00:56:37.173722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9624 00:56:37.180597 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9625 00:56:37.183922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9626 00:56:37.190698 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9627 00:56:37.193579 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9628 00:56:37.200694 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9629 00:56:37.203572 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9630 00:56:37.206936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9631 00:56:37.213778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9632 00:56:37.217228 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9633 00:56:37.223845 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9634 00:56:37.227373 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9635 00:56:37.230622 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9636 00:56:37.237034 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9637 00:56:37.240509 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9638 00:56:37.247411 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9639 00:56:37.250384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9640 00:56:37.257310 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9641 00:56:37.260678 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9642 00:56:37.267669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9643 00:56:37.270876 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9644 00:56:37.273971 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9645 00:56:37.280868 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9646 00:56:37.284422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9647 00:56:37.291191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9648 00:56:37.294140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9649 00:56:37.297590 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9650 00:56:37.304646 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9651 00:56:37.307467 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9652 00:56:37.314582 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9653 00:56:37.317874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9654 00:56:37.324412 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9655 00:56:37.327785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9656 00:56:37.331223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9657 00:56:37.337894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9658 00:56:37.341071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9659 00:56:37.347841 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9660 00:56:37.351060 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9661 00:56:37.354700 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9662 00:56:37.357762 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9663 00:56:37.361582 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9664 00:56:37.368010 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9665 00:56:37.371535 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9666 00:56:37.377903 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9667 00:56:37.381355 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9668 00:56:37.385000 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9669 00:56:37.391807 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9670 00:56:37.394705 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9671 00:56:37.401450 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9672 00:56:37.405053 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9673 00:56:37.408474 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9674 00:56:37.415222 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9675 00:56:37.418285 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9676 00:56:37.424822 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9677 00:56:37.428574 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9678 00:56:37.432054 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9679 00:56:37.435091 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9680 00:56:37.441895 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9681 00:56:37.445223 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9682 00:56:37.448466 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9683 00:56:37.454945 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9684 00:56:37.458357 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9685 00:56:37.461882 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9686 00:56:37.465042 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9687 00:56:37.471788 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9688 00:56:37.474712 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9689 00:56:37.481640 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9690 00:56:37.485184 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9691 00:56:37.488352 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9692 00:56:37.495300 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9693 00:56:37.498824 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9694 00:56:37.501467 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9695 00:56:37.508456 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9696 00:56:37.511860 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9697 00:56:37.518466 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9698 00:56:37.521881 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9699 00:56:37.525392 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9700 00:56:37.531768 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9701 00:56:37.535304 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9702 00:56:37.538861 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9703 00:56:37.545506 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9704 00:56:37.548902 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9705 00:56:37.555540 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9706 00:56:37.558911 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9707 00:56:37.562490 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9708 00:56:37.568684 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9709 00:56:37.572626 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9710 00:56:37.575696 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9711 00:56:37.581941 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9712 00:56:37.585665 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9713 00:56:37.592285 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9714 00:56:37.595619 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9715 00:56:37.598781 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9716 00:56:37.605545 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9717 00:56:37.609062 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9718 00:56:37.615553 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9719 00:56:37.618807 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9720 00:56:37.622223 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9721 00:56:37.628916 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9722 00:56:37.632402 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9723 00:56:37.635276 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9724 00:56:37.642488 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9725 00:56:37.645194 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9726 00:56:37.652377 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9727 00:56:37.655705 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9728 00:56:37.659406 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9729 00:56:37.665587 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9730 00:56:37.668919 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9731 00:56:37.676095 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9732 00:56:37.678911 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9733 00:56:37.682166 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9734 00:56:37.688943 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9735 00:56:37.692551 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9736 00:56:37.695535 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9737 00:56:37.702331 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9738 00:56:37.705813 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9739 00:56:37.712248 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9740 00:56:37.715604 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9741 00:56:37.719106 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9742 00:56:37.725790 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9743 00:56:37.728978 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9744 00:56:37.735433 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9745 00:56:37.739062 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9746 00:56:37.742314 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9747 00:56:37.748654 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9748 00:56:37.752126 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9749 00:56:37.755518 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9750 00:56:37.762267 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9751 00:56:37.765307 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9752 00:56:37.772249 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9753 00:56:37.775594 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9754 00:56:37.781925 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9755 00:56:37.785306 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9756 00:56:37.788693 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9757 00:56:37.795369 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9758 00:56:37.798512 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9759 00:56:37.805330 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9760 00:56:37.808770 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9761 00:56:37.812204 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9762 00:56:37.819084 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9763 00:56:37.821916 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9764 00:56:37.828826 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9765 00:56:37.832173 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9766 00:56:37.838382 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9767 00:56:37.841739 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9768 00:56:37.846064 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9769 00:56:37.851872 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9770 00:56:37.855330 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9771 00:56:37.861971 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9772 00:56:37.865402 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9773 00:56:37.868415 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9774 00:56:37.875332 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9775 00:56:37.878721 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9776 00:56:37.885104 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9777 00:56:37.888684 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9778 00:56:37.892394 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9779 00:56:37.898586 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9780 00:56:37.901921 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9781 00:56:37.908451 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9782 00:56:37.912156 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9783 00:56:37.918743 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9784 00:56:37.921515 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9785 00:56:37.925617 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9786 00:56:37.931844 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9787 00:56:37.935402 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9788 00:56:37.941556 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9789 00:56:37.945170 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9790 00:56:37.948131 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9791 00:56:37.955476 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9792 00:56:37.958591 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9793 00:56:37.961716 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9794 00:56:37.964913 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9795 00:56:37.971809 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9796 00:56:37.975185 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9797 00:56:37.978234 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9798 00:56:37.985075 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9799 00:56:37.988654 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9800 00:56:37.992129 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9801 00:56:37.998367 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9802 00:56:38.001950 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9803 00:56:38.005427 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9804 00:56:38.011925 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9805 00:56:38.014755 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9806 00:56:38.021815 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9807 00:56:38.024949 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9808 00:56:38.028648 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9809 00:56:38.034978 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9810 00:56:38.038418 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9811 00:56:38.042066 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9812 00:56:38.048305 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9813 00:56:38.051961 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9814 00:56:38.054869 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9815 00:56:38.061503 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9816 00:56:38.064883 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9817 00:56:38.071507 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9818 00:56:38.075221 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9819 00:56:38.078366 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9820 00:56:38.084840 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9821 00:56:38.088283 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9822 00:56:38.091287 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9823 00:56:38.098388 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9824 00:56:38.101823 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9825 00:56:38.108266 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9826 00:56:38.111265 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9827 00:56:38.115046 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9828 00:56:38.121471 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9829 00:56:38.124541 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9830 00:56:38.128087 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9831 00:56:38.134448 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9832 00:56:38.137782 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9833 00:56:38.141203 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9834 00:56:38.144679 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9835 00:56:38.148242 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9836 00:56:38.154658 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9837 00:56:38.158116 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9838 00:56:38.161656 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9839 00:56:38.164465 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9840 00:56:38.171317 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9841 00:56:38.174463 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9842 00:56:38.178148 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9843 00:56:38.184801 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9844 00:56:38.188211 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9845 00:56:38.191029 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9846 00:56:38.198237 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9847 00:56:38.201326 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9848 00:56:38.204813 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9849 00:56:38.211457 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9850 00:56:38.214944 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9851 00:56:38.221383 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9852 00:56:38.224742 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9853 00:56:38.227663 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9854 00:56:38.234375 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9855 00:56:38.237797 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9856 00:56:38.244674 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9857 00:56:38.248007 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9858 00:56:38.254448 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9859 00:56:38.257802 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9860 00:56:38.261317 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9861 00:56:38.267928 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9862 00:56:38.271356 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9863 00:56:38.277756 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9864 00:56:38.280987 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9865 00:56:38.284606 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9866 00:56:38.291035 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9867 00:56:38.294480 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9868 00:56:38.297827 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9869 00:56:38.304467 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9870 00:56:38.307788 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9871 00:56:38.314391 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9872 00:56:38.317716 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9873 00:56:38.324489 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9874 00:56:38.328031 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9875 00:56:38.331438 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9876 00:56:38.338146 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9877 00:56:38.341062 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9878 00:56:38.347500 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9879 00:56:38.350995 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9880 00:56:38.354145 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9881 00:56:38.361155 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9882 00:56:38.364428 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9883 00:56:38.371248 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9884 00:56:38.374750 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9885 00:56:38.378153 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9886 00:56:38.384590 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9887 00:56:38.388000 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9888 00:56:38.394823 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9889 00:56:38.397813 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9890 00:56:38.401233 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9891 00:56:38.408061 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9892 00:56:38.411326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9893 00:56:38.417962 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9894 00:56:38.421274 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9895 00:56:38.424877 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9896 00:56:38.431469 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9897 00:56:38.434549 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9898 00:56:38.441258 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9899 00:56:38.444686 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9900 00:56:38.448165 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9901 00:56:38.454351 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9902 00:56:38.457838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9903 00:56:38.464515 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9904 00:56:38.467753 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9905 00:56:38.474450 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9906 00:56:38.477471 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9907 00:56:38.480868 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9908 00:56:38.487650 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9909 00:56:38.491052 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9910 00:56:38.494475 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9911 00:56:38.500750 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9912 00:56:38.504707 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9913 00:56:38.511177 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9914 00:56:38.514697 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9915 00:56:38.521249 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9916 00:56:38.524349 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9917 00:56:38.527838 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9918 00:56:38.534383 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9919 00:56:38.538119 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9920 00:56:38.544176 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9921 00:56:38.548017 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9922 00:56:38.554296 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9923 00:56:38.557666 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9924 00:56:38.561101 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9925 00:56:38.567832 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9926 00:56:38.570744 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9927 00:56:38.577497 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9928 00:56:38.580902 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9929 00:56:38.587695 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9930 00:56:38.591099 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9931 00:56:38.594594 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9932 00:56:38.600782 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9933 00:56:38.604174 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9934 00:56:38.610962 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9935 00:56:38.614562 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9936 00:56:38.620886 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9937 00:56:38.624551 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9938 00:56:38.627645 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9939 00:56:38.634320 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9940 00:56:38.637584 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9941 00:56:38.644060 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9942 00:56:38.647735 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9943 00:56:38.653957 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9944 00:56:38.657497 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9945 00:56:38.661219 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9946 00:56:38.667356 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9947 00:56:38.670647 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9948 00:56:38.677566 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9949 00:56:38.680753 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9950 00:56:38.687651 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9951 00:56:38.691040 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9952 00:56:38.694585 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9953 00:56:38.700831 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9954 00:56:38.704259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9955 00:56:38.711028 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9956 00:56:38.714392 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9957 00:56:38.720759 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9958 00:56:38.724149 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9959 00:56:38.727539 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9960 00:56:38.734442 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9961 00:56:38.737233 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9962 00:56:38.743870 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9963 00:56:38.747371 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9964 00:56:38.750571 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9965 00:56:38.757485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9966 00:56:38.761069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9967 00:56:38.767674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9968 00:56:38.770951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9969 00:56:38.777577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9970 00:56:38.781045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9971 00:56:38.787373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9972 00:56:38.790559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9973 00:56:38.797659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9974 00:56:38.800697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9975 00:56:38.804119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9976 00:56:38.811171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9977 00:56:38.813950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9978 00:56:38.820789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9979 00:56:38.824388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9980 00:56:38.830447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9981 00:56:38.833952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9982 00:56:38.840568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9983 00:56:38.843801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9984 00:56:38.850652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9985 00:56:38.853915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9986 00:56:38.860726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9987 00:56:38.864021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9988 00:56:38.870479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9989 00:56:38.874319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9990 00:56:38.881070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9991 00:56:38.884185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9992 00:56:38.890835 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9993 00:56:38.894246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9994 00:56:38.900622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9995 00:56:38.904075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9996 00:56:38.910941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9997 00:56:38.913612 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9998 00:56:38.917122 INFO: [APUAPC] vio 0
9999 00:56:38.920559 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10000 00:56:38.927382 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10001 00:56:38.930276 INFO: [APUAPC] D0_APC_0: 0x400510
10002 00:56:38.930353 INFO: [APUAPC] D0_APC_1: 0x0
10003 00:56:38.934229 INFO: [APUAPC] D0_APC_2: 0x1540
10004 00:56:38.937249 INFO: [APUAPC] D0_APC_3: 0x0
10005 00:56:38.940621 INFO: [APUAPC] D1_APC_0: 0xffffffff
10006 00:56:38.944040 INFO: [APUAPC] D1_APC_1: 0xffffffff
10007 00:56:38.947476 INFO: [APUAPC] D1_APC_2: 0x3fffff
10008 00:56:38.950814 INFO: [APUAPC] D1_APC_3: 0x0
10009 00:56:38.954291 INFO: [APUAPC] D2_APC_0: 0xffffffff
10010 00:56:38.957574 INFO: [APUAPC] D2_APC_1: 0xffffffff
10011 00:56:38.960813 INFO: [APUAPC] D2_APC_2: 0x3fffff
10012 00:56:38.964284 INFO: [APUAPC] D2_APC_3: 0x0
10013 00:56:38.967034 INFO: [APUAPC] D3_APC_0: 0xffffffff
10014 00:56:38.970442 INFO: [APUAPC] D3_APC_1: 0xffffffff
10015 00:56:38.973765 INFO: [APUAPC] D3_APC_2: 0x3fffff
10016 00:56:38.977143 INFO: [APUAPC] D3_APC_3: 0x0
10017 00:56:38.980880 INFO: [APUAPC] D4_APC_0: 0xffffffff
10018 00:56:38.984058 INFO: [APUAPC] D4_APC_1: 0xffffffff
10019 00:56:38.987154 INFO: [APUAPC] D4_APC_2: 0x3fffff
10020 00:56:38.990528 INFO: [APUAPC] D4_APC_3: 0x0
10021 00:56:38.993935 INFO: [APUAPC] D5_APC_0: 0xffffffff
10022 00:56:38.997005 INFO: [APUAPC] D5_APC_1: 0xffffffff
10023 00:56:39.000213 INFO: [APUAPC] D5_APC_2: 0x3fffff
10024 00:56:39.003554 INFO: [APUAPC] D5_APC_3: 0x0
10025 00:56:39.007070 INFO: [APUAPC] D6_APC_0: 0xffffffff
10026 00:56:39.010305 INFO: [APUAPC] D6_APC_1: 0xffffffff
10027 00:56:39.013946 INFO: [APUAPC] D6_APC_2: 0x3fffff
10028 00:56:39.017043 INFO: [APUAPC] D6_APC_3: 0x0
10029 00:56:39.020929 INFO: [APUAPC] D7_APC_0: 0xffffffff
10030 00:56:39.024146 INFO: [APUAPC] D7_APC_1: 0xffffffff
10031 00:56:39.027431 INFO: [APUAPC] D7_APC_2: 0x3fffff
10032 00:56:39.030532 INFO: [APUAPC] D7_APC_3: 0x0
10033 00:56:39.033900 INFO: [APUAPC] D8_APC_0: 0xffffffff
10034 00:56:39.037485 INFO: [APUAPC] D8_APC_1: 0xffffffff
10035 00:56:39.040356 INFO: [APUAPC] D8_APC_2: 0x3fffff
10036 00:56:39.043841 INFO: [APUAPC] D8_APC_3: 0x0
10037 00:56:39.047229 INFO: [APUAPC] D9_APC_0: 0xffffffff
10038 00:56:39.050696 INFO: [APUAPC] D9_APC_1: 0xffffffff
10039 00:56:39.053823 INFO: [APUAPC] D9_APC_2: 0x3fffff
10040 00:56:39.054277 INFO: [APUAPC] D9_APC_3: 0x0
10041 00:56:39.060533 INFO: [APUAPC] D10_APC_0: 0xffffffff
10042 00:56:39.063686 INFO: [APUAPC] D10_APC_1: 0xffffffff
10043 00:56:39.067007 INFO: [APUAPC] D10_APC_2: 0x3fffff
10044 00:56:39.070554 INFO: [APUAPC] D10_APC_3: 0x0
10045 00:56:39.073287 INFO: [APUAPC] D11_APC_0: 0xffffffff
10046 00:56:39.077090 INFO: [APUAPC] D11_APC_1: 0xffffffff
10047 00:56:39.080098 INFO: [APUAPC] D11_APC_2: 0x3fffff
10048 00:56:39.083854 INFO: [APUAPC] D11_APC_3: 0x0
10049 00:56:39.087054 INFO: [APUAPC] D12_APC_0: 0xffffffff
10050 00:56:39.090480 INFO: [APUAPC] D12_APC_1: 0xffffffff
10051 00:56:39.093586 INFO: [APUAPC] D12_APC_2: 0x3fffff
10052 00:56:39.096575 INFO: [APUAPC] D12_APC_3: 0x0
10053 00:56:39.099958 INFO: [APUAPC] D13_APC_0: 0xffffffff
10054 00:56:39.103700 INFO: [APUAPC] D13_APC_1: 0xffffffff
10055 00:56:39.106916 INFO: [APUAPC] D13_APC_2: 0x3fffff
10056 00:56:39.110055 INFO: [APUAPC] D13_APC_3: 0x0
10057 00:56:39.113518 INFO: [APUAPC] D14_APC_0: 0xffffffff
10058 00:56:39.117019 INFO: [APUAPC] D14_APC_1: 0xffffffff
10059 00:56:39.120514 INFO: [APUAPC] D14_APC_2: 0x3fffff
10060 00:56:39.123269 INFO: [APUAPC] D14_APC_3: 0x0
10061 00:56:39.126664 INFO: [APUAPC] D15_APC_0: 0xffffffff
10062 00:56:39.130340 INFO: [APUAPC] D15_APC_1: 0xffffffff
10063 00:56:39.133155 INFO: [APUAPC] D15_APC_2: 0x3fffff
10064 00:56:39.136673 INFO: [APUAPC] D15_APC_3: 0x0
10065 00:56:39.137088 INFO: [APUAPC] APC_CON: 0x4
10066 00:56:39.140049 INFO: [NOCDAPC] D0_APC_0: 0x0
10067 00:56:39.143246 INFO: [NOCDAPC] D0_APC_1: 0x0
10068 00:56:39.146598 INFO: [NOCDAPC] D1_APC_0: 0x0
10069 00:56:39.149890 INFO: [NOCDAPC] D1_APC_1: 0xfff
10070 00:56:39.153539 INFO: [NOCDAPC] D2_APC_0: 0x0
10071 00:56:39.156736 INFO: [NOCDAPC] D2_APC_1: 0xfff
10072 00:56:39.160297 INFO: [NOCDAPC] D3_APC_0: 0x0
10073 00:56:39.163112 INFO: [NOCDAPC] D3_APC_1: 0xfff
10074 00:56:39.166390 INFO: [NOCDAPC] D4_APC_0: 0x0
10075 00:56:39.166783 INFO: [NOCDAPC] D4_APC_1: 0xfff
10076 00:56:39.170219 INFO: [NOCDAPC] D5_APC_0: 0x0
10077 00:56:39.173536 INFO: [NOCDAPC] D5_APC_1: 0xfff
10078 00:56:39.176572 INFO: [NOCDAPC] D6_APC_0: 0x0
10079 00:56:39.179831 INFO: [NOCDAPC] D6_APC_1: 0xfff
10080 00:56:39.183192 INFO: [NOCDAPC] D7_APC_0: 0x0
10081 00:56:39.186481 INFO: [NOCDAPC] D7_APC_1: 0xfff
10082 00:56:39.189904 INFO: [NOCDAPC] D8_APC_0: 0x0
10083 00:56:39.193237 INFO: [NOCDAPC] D8_APC_1: 0xfff
10084 00:56:39.196851 INFO: [NOCDAPC] D9_APC_0: 0x0
10085 00:56:39.200079 INFO: [NOCDAPC] D9_APC_1: 0xfff
10086 00:56:39.200470 INFO: [NOCDAPC] D10_APC_0: 0x0
10087 00:56:39.203641 INFO: [NOCDAPC] D10_APC_1: 0xfff
10088 00:56:39.206688 INFO: [NOCDAPC] D11_APC_0: 0x0
10089 00:56:39.209858 INFO: [NOCDAPC] D11_APC_1: 0xfff
10090 00:56:39.213249 INFO: [NOCDAPC] D12_APC_0: 0x0
10091 00:56:39.216379 INFO: [NOCDAPC] D12_APC_1: 0xfff
10092 00:56:39.219987 INFO: [NOCDAPC] D13_APC_0: 0x0
10093 00:56:39.223417 INFO: [NOCDAPC] D13_APC_1: 0xfff
10094 00:56:39.226288 INFO: [NOCDAPC] D14_APC_0: 0x0
10095 00:56:39.229577 INFO: [NOCDAPC] D14_APC_1: 0xfff
10096 00:56:39.233097 INFO: [NOCDAPC] D15_APC_0: 0x0
10097 00:56:39.236406 INFO: [NOCDAPC] D15_APC_1: 0xfff
10098 00:56:39.239750 INFO: [NOCDAPC] APC_CON: 0x4
10099 00:56:39.243025 INFO: [APUAPC] set_apusys_apc done
10100 00:56:39.243420 INFO: [DEVAPC] devapc_init done
10101 00:56:39.250370 INFO: GICv3 without legacy support detected.
10102 00:56:39.253166 INFO: ARM GICv3 driver initialized in EL3
10103 00:56:39.256547 INFO: Maximum SPI INTID supported: 639
10104 00:56:39.260157 INFO: BL31: Initializing runtime services
10105 00:56:39.266135 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10106 00:56:39.269835 INFO: SPM: enable CPC mode
10107 00:56:39.272772 INFO: mcdi ready for mcusys-off-idle and system suspend
10108 00:56:39.279790 INFO: BL31: Preparing for EL3 exit to normal world
10109 00:56:39.282640 INFO: Entry point address = 0x80000000
10110 00:56:39.282716 INFO: SPSR = 0x8
10111 00:56:39.289965
10112 00:56:39.290081
10113 00:56:39.290140
10114 00:56:39.293511 Starting depthcharge on Spherion...
10115 00:56:39.293586
10116 00:56:39.293644 Wipe memory regions:
10117 00:56:39.293698
10118 00:56:39.294342 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10119 00:56:39.294437 start: 2.2.4 bootloader-commands (timeout 00:04:24) [common]
10120 00:56:39.294512 Setting prompt string to ['asurada:']
10121 00:56:39.294583 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:24)
10122 00:56:39.296801 [0x00000040000000, 0x00000054600000)
10123 00:56:39.419844
10124 00:56:39.420287 [0x00000054660000, 0x00000080000000)
10125 00:56:39.679650
10126 00:56:39.680091 [0x000000821a7280, 0x000000ffe64000)
10127 00:56:40.424748
10128 00:56:40.424915 [0x00000100000000, 0x00000240000000)
10129 00:56:42.314926
10130 00:56:42.318275 Initializing XHCI USB controller at 0x11200000.
10131 00:56:43.356975
10132 00:56:43.360364 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10133 00:56:43.360445
10134 00:56:43.360505
10135 00:56:43.360790 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10137 00:56:43.461178 asurada: tftpboot 192.168.201.1 14368562/tftp-deploy-hnw5p4e_/kernel/image.itb 14368562/tftp-deploy-hnw5p4e_/kernel/cmdline
10138 00:56:43.461394 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10139 00:56:43.461497 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10140 00:56:43.466069 tftpboot 192.168.201.1 14368562/tftp-deploy-hnw5p4e_/kernel/image.ittp-deploy-hnw5p4e_/kernel/cmdline
10141 00:56:43.466151
10142 00:56:43.466211 Waiting for link
10143 00:56:43.623893
10144 00:56:43.624004 R8152: Initializing
10145 00:56:43.624066
10146 00:56:43.627301 Version 6 (ocp_data = 5c30)
10147 00:56:43.627378
10148 00:56:43.630415 R8152: Done initializing
10149 00:56:43.630492
10150 00:56:43.630551 Adding net device
10151 00:56:45.482899
10152 00:56:45.483022 done.
10153 00:56:45.483083
10154 00:56:45.483139 MAC: 00:24:32:30:78:52
10155 00:56:45.483192
10156 00:56:45.486137 Sending DHCP discover... done.
10157 00:56:45.486215
10158 00:56:45.489605 Waiting for reply... done.
10159 00:56:45.489681
10160 00:56:45.493029 Sending DHCP request... done.
10161 00:56:45.493105
10162 00:56:45.498211 Waiting for reply... done.
10163 00:56:45.498289
10164 00:56:45.498348 My ip is 192.168.201.14
10165 00:56:45.498402
10166 00:56:45.501459 The DHCP server ip is 192.168.201.1
10167 00:56:45.501536
10168 00:56:45.507853 TFTP server IP predefined by user: 192.168.201.1
10169 00:56:45.507931
10170 00:56:45.514631 Bootfile predefined by user: 14368562/tftp-deploy-hnw5p4e_/kernel/image.itb
10171 00:56:45.514708
10172 00:56:45.514766 Sending tftp read request... done.
10173 00:56:45.517603
10174 00:56:45.521676 Waiting for the transfer...
10175 00:56:45.521768
10176 00:56:46.080945 00000000 ################################################################
10177 00:56:46.081075
10178 00:56:46.634523 00080000 ################################################################
10179 00:56:46.634638
10180 00:56:47.199083 00100000 ################################################################
10181 00:56:47.199215
10182 00:56:47.750859 00180000 ################################################################
10183 00:56:47.750974
10184 00:56:48.296605 00200000 ################################################################
10185 00:56:48.296728
10186 00:56:48.833697 00280000 ################################################################
10187 00:56:48.833860
10188 00:56:49.386250 00300000 ################################################################
10189 00:56:49.386377
10190 00:56:49.948494 00380000 ################################################################
10191 00:56:49.948621
10192 00:56:50.509393 00400000 ################################################################
10193 00:56:50.509515
10194 00:56:51.070117 00480000 ################################################################
10195 00:56:51.070239
10196 00:56:51.628959 00500000 ################################################################
10197 00:56:51.629072
10198 00:56:52.193746 00580000 ################################################################
10199 00:56:52.193876
10200 00:56:52.767352 00600000 ################################################################
10201 00:56:52.767468
10202 00:56:53.338535 00680000 ################################################################
10203 00:56:53.338649
10204 00:56:53.906649 00700000 ################################################################
10205 00:56:53.906762
10206 00:56:54.447487 00780000 ################################################################
10207 00:56:54.447603
10208 00:56:54.982532 00800000 ################################################################
10209 00:56:54.982649
10210 00:56:55.546863 00880000 ################################################################
10211 00:56:55.546979
10212 00:56:56.132746 00900000 ################################################################
10213 00:56:56.132871
10214 00:56:56.713720 00980000 ################################################################
10215 00:56:56.713849
10216 00:56:57.288567 00a00000 ################################################################
10217 00:56:57.288683
10218 00:56:57.860867 00a80000 ################################################################
10219 00:56:57.860988
10220 00:56:58.443979 00b00000 ################################################################
10221 00:56:58.444094
10222 00:56:59.013329 00b80000 ################################################################
10223 00:56:59.013444
10224 00:56:59.589240 00c00000 ################################################################
10225 00:56:59.589357
10226 00:57:00.167490 00c80000 ################################################################
10227 00:57:00.167608
10228 00:57:00.753218 00d00000 ################################################################
10229 00:57:00.753340
10230 00:57:01.326247 00d80000 ################################################################
10231 00:57:01.326372
10232 00:57:01.861824 00e00000 ################################################################
10233 00:57:01.861949
10234 00:57:02.421178 00e80000 ################################################################
10235 00:57:02.421321
10236 00:57:03.010436 00f00000 ################################################################
10237 00:57:03.010923
10238 00:57:03.728340 00f80000 ################################################################
10239 00:57:03.728914
10240 00:57:04.455728 01000000 ################################################################
10241 00:57:04.456220
10242 00:57:05.157952 01080000 ################################################################
10243 00:57:05.158440
10244 00:57:05.859004 01100000 ################################################################
10245 00:57:05.859442
10246 00:57:06.561518 01180000 ################################################################
10247 00:57:06.562057
10248 00:57:07.277206 01200000 ################################################################
10249 00:57:07.277668
10250 00:57:07.977099 01280000 ################################################################
10251 00:57:07.977587
10252 00:57:08.684923 01300000 ################################################################
10253 00:57:08.685366
10254 00:57:09.407480 01380000 ################################################################
10255 00:57:09.407925
10256 00:57:10.127804 01400000 ################################################################
10257 00:57:10.128281
10258 00:57:10.846050 01480000 ################################################################
10259 00:57:10.846532
10260 00:57:11.512936 01500000 ################################################################
10261 00:57:11.513063
10262 00:57:12.178941 01580000 ################################################################
10263 00:57:12.179380
10264 00:57:12.889771 01600000 ################################################################
10265 00:57:12.890297
10266 00:57:13.596198 01680000 ################################################################
10267 00:57:13.596667
10268 00:57:14.310093 01700000 ################################################################
10269 00:57:14.310581
10270 00:57:15.005490 01780000 ################################################################
10271 00:57:15.005924
10272 00:57:15.712474 01800000 ################################################################
10273 00:57:15.712921
10274 00:57:16.417642 01880000 ################################################################
10275 00:57:16.418135
10276 00:57:17.122752 01900000 ################################################################
10277 00:57:17.123203
10278 00:57:17.838580 01980000 ################################################################
10279 00:57:17.839069
10280 00:57:18.558113 01a00000 ################################################################
10281 00:57:18.558658
10282 00:57:19.264690 01a80000 ################################################################
10283 00:57:19.265131
10284 00:57:19.964340 01b00000 ################################################################
10285 00:57:19.964851
10286 00:57:20.676046 01b80000 ################################################################
10287 00:57:20.676504
10288 00:57:21.386461 01c00000 ################################################################
10289 00:57:21.386924
10290 00:57:22.048466 01c80000 ################################################################
10291 00:57:22.048603
10292 00:57:22.754950 01d00000 ################################################################
10293 00:57:22.755415
10294 00:57:23.463537 01d80000 ################################################################
10295 00:57:23.464010
10296 00:57:24.080880 01e00000 ######################################################## done.
10297 00:57:24.081344
10298 00:57:24.084026 The bootfile was 31912334 bytes long.
10299 00:57:24.084425
10300 00:57:24.087370 Sending tftp read request... done.
10301 00:57:24.087760
10302 00:57:24.092137 Waiting for the transfer...
10303 00:57:24.092528
10304 00:57:24.092827 00000000 # done.
10305 00:57:24.093113
10306 00:57:24.098430 Command line loaded dynamically from TFTP file: 14368562/tftp-deploy-hnw5p4e_/kernel/cmdline
10307 00:57:24.098896
10308 00:57:24.122236 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368562/extract-nfsrootfs-azas7lbe,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10309 00:57:24.122789
10310 00:57:24.123126 Loading FIT.
10311 00:57:24.123437
10312 00:57:24.125405 Image ramdisk-1 has 18738002 bytes.
10313 00:57:24.125837
10314 00:57:24.128598 Image fdt-1 has 47258 bytes.
10315 00:57:24.129025
10316 00:57:24.131947 Image kernel-1 has 13125045 bytes.
10317 00:57:24.132377
10318 00:57:24.141896 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10319 00:57:24.142422
10320 00:57:24.158766 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10321 00:57:24.159232
10322 00:57:24.165553 Choosing best match conf-1 for compat google,spherion-rev2.
10323 00:57:24.166088
10324 00:57:24.173079 Connected to device vid:did:rid of 1ae0:0028:00
10325 00:57:24.180853
10326 00:57:24.184129 tpm_get_response: command 0x17b, return code 0x0
10327 00:57:24.184525
10328 00:57:24.187662 ec_init: CrosEC protocol v3 supported (256, 248)
10329 00:57:24.191280
10330 00:57:24.195530 tpm_cleanup: add release locality here.
10331 00:57:24.196041
10332 00:57:24.196352 Shutting down all USB controllers.
10333 00:57:24.198404
10334 00:57:24.198794 Removing current net device
10335 00:57:24.199095
10336 00:57:24.204866 Exiting depthcharge with code 4 at timestamp: 74304399
10337 00:57:24.205256
10338 00:57:24.208819 LZMA decompressing kernel-1 to 0x821a6718
10339 00:57:24.209209
10340 00:57:24.211577 LZMA decompressing kernel-1 to 0x40000000
10341 00:57:25.827492
10342 00:57:25.827673 jumping to kernel
10343 00:57:25.828269 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10344 00:57:25.828443 start: 2.2.5 auto-login-action (timeout 00:03:37) [common]
10345 00:57:25.828552 Setting prompt string to ['Linux version [0-9]']
10346 00:57:25.828650 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10347 00:57:25.828747 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10348 00:57:25.909945
10349 00:57:25.913803 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10350 00:57:25.917318 start: 2.2.5.1 login-action (timeout 00:03:37) [common]
10351 00:57:25.917905 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10352 00:57:25.918402 Setting prompt string to []
10353 00:57:25.918799 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10354 00:57:25.919167 Using line separator: #'\n'#
10355 00:57:25.919476 No login prompt set.
10356 00:57:25.919793 Parsing kernel messages
10357 00:57:25.920079 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10358 00:57:25.920597 [login-action] Waiting for messages, (timeout 00:03:37)
10359 00:57:25.920928 Waiting using forced prompt support (timeout 00:01:49)
10360 00:57:25.936245 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
10361 00:57:25.940211 [ 0.000000] random: crng init done
10362 00:57:25.946452 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10363 00:57:25.946891 [ 0.000000] efi: UEFI not found.
10364 00:57:25.956677 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10365 00:57:25.963371 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10366 00:57:25.973060 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10367 00:57:25.983057 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10368 00:57:25.990043 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10369 00:57:25.992913 [ 0.000000] printk: bootconsole [mtk8250] enabled
10370 00:57:26.001794 [ 0.000000] NUMA: No NUMA configuration found
10371 00:57:26.008900 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10372 00:57:26.015365 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10373 00:57:26.015884 [ 0.000000] Zone ranges:
10374 00:57:26.022382 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10375 00:57:26.025094 [ 0.000000] DMA32 empty
10376 00:57:26.031460 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10377 00:57:26.035315 [ 0.000000] Movable zone start for each node
10378 00:57:26.038888 [ 0.000000] Early memory node ranges
10379 00:57:26.045272 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10380 00:57:26.052060 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10381 00:57:26.058046 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10382 00:57:26.064857 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10383 00:57:26.071391 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10384 00:57:26.078523 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10385 00:57:26.134509 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10386 00:57:26.141264 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10387 00:57:26.148327 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10388 00:57:26.151922 [ 0.000000] psci: probing for conduit method from DT.
10389 00:57:26.157909 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10390 00:57:26.161066 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10391 00:57:26.167876 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10392 00:57:26.170917 [ 0.000000] psci: SMC Calling Convention v1.2
10393 00:57:26.177766 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10394 00:57:26.181298 [ 0.000000] Detected VIPT I-cache on CPU0
10395 00:57:26.188324 [ 0.000000] CPU features: detected: GIC system register CPU interface
10396 00:57:26.194392 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10397 00:57:26.201551 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10398 00:57:26.207810 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10399 00:57:26.214359 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10400 00:57:26.221185 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10401 00:57:26.227781 [ 0.000000] alternatives: applying boot alternatives
10402 00:57:26.231001 [ 0.000000] Fallback order for Node 0: 0
10403 00:57:26.237675 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10404 00:57:26.241428 [ 0.000000] Policy zone: Normal
10405 00:57:26.264692 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368562/extract-nfsrootfs-azas7lbe,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10406 00:57:26.277653 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10407 00:57:26.287936 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10408 00:57:26.297448 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10409 00:57:26.304076 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10410 00:57:26.307603 <6>[ 0.000000] software IO TLB: area num 8.
10411 00:57:26.362945 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10412 00:57:26.512319 <6>[ 0.000000] Memory: 7945764K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407004K reserved, 32768K cma-reserved)
10413 00:57:26.518779 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10414 00:57:26.525858 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10415 00:57:26.529455 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10416 00:57:26.535528 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10417 00:57:26.542566 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10418 00:57:26.545773 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10419 00:57:26.555721 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10420 00:57:26.562499 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10421 00:57:26.565764 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10422 00:57:26.573666 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10423 00:57:26.576900 <6>[ 0.000000] GICv3: 608 SPIs implemented
10424 00:57:26.583246 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10425 00:57:26.586550 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10426 00:57:26.590249 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10427 00:57:26.599802 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10428 00:57:26.609948 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10429 00:57:26.623379 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10430 00:57:26.629841 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10431 00:57:26.638939 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10432 00:57:26.652294 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10433 00:57:26.658872 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10434 00:57:26.665667 <6>[ 0.009184] Console: colour dummy device 80x25
10435 00:57:26.675342 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10436 00:57:26.679064 <6>[ 0.024354] pid_max: default: 32768 minimum: 301
10437 00:57:26.685713 <6>[ 0.029256] LSM: Security Framework initializing
10438 00:57:26.692282 <6>[ 0.034194] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10439 00:57:26.702153 <6>[ 0.042008] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10440 00:57:26.709066 <6>[ 0.051431] cblist_init_generic: Setting adjustable number of callback queues.
10441 00:57:26.715723 <6>[ 0.058875] cblist_init_generic: Setting shift to 3 and lim to 1.
10442 00:57:26.722114 <6>[ 0.065253] cblist_init_generic: Setting adjustable number of callback queues.
10443 00:57:26.728966 <6>[ 0.072725] cblist_init_generic: Setting shift to 3 and lim to 1.
10444 00:57:26.735796 <6>[ 0.079125] rcu: Hierarchical SRCU implementation.
10445 00:57:26.738813 <6>[ 0.084139] rcu: Max phase no-delay instances is 1000.
10446 00:57:26.747409 <6>[ 0.091174] EFI services will not be available.
10447 00:57:26.751092 <6>[ 0.096157] smp: Bringing up secondary CPUs ...
10448 00:57:26.760011 <6>[ 0.101207] Detected VIPT I-cache on CPU1
10449 00:57:26.766493 <6>[ 0.101280] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10450 00:57:26.772763 <6>[ 0.101309] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10451 00:57:26.776329 <6>[ 0.101645] Detected VIPT I-cache on CPU2
10452 00:57:26.782942 <6>[ 0.101700] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10453 00:57:26.789598 <6>[ 0.101717] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10454 00:57:26.796468 <6>[ 0.101976] Detected VIPT I-cache on CPU3
10455 00:57:26.802968 <6>[ 0.102024] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10456 00:57:26.809508 <6>[ 0.102038] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10457 00:57:26.813213 <6>[ 0.102339] CPU features: detected: Spectre-v4
10458 00:57:26.819538 <6>[ 0.102345] CPU features: detected: Spectre-BHB
10459 00:57:26.822916 <6>[ 0.102349] Detected PIPT I-cache on CPU4
10460 00:57:26.829236 <6>[ 0.102408] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10461 00:57:26.835998 <6>[ 0.102424] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10462 00:57:26.843102 <6>[ 0.102716] Detected PIPT I-cache on CPU5
10463 00:57:26.849547 <6>[ 0.102779] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10464 00:57:26.856230 <6>[ 0.102795] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10465 00:57:26.859612 <6>[ 0.103075] Detected PIPT I-cache on CPU6
10466 00:57:26.866136 <6>[ 0.103142] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10467 00:57:26.872890 <6>[ 0.103158] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10468 00:57:26.876157 <6>[ 0.103457] Detected PIPT I-cache on CPU7
10469 00:57:26.886270 <6>[ 0.103522] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10470 00:57:26.892847 <6>[ 0.103538] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10471 00:57:26.896292 <6>[ 0.103585] smp: Brought up 1 node, 8 CPUs
10472 00:57:26.899628 <6>[ 0.244948] SMP: Total of 8 processors activated.
10473 00:57:26.906321 <6>[ 0.249900] CPU features: detected: 32-bit EL0 Support
10474 00:57:26.916254 <6>[ 0.255264] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10475 00:57:26.922920 <6>[ 0.264064] CPU features: detected: Common not Private translations
10476 00:57:26.925949 <6>[ 0.270540] CPU features: detected: CRC32 instructions
10477 00:57:26.932800 <6>[ 0.275892] CPU features: detected: RCpc load-acquire (LDAPR)
10478 00:57:26.939863 <6>[ 0.281889] CPU features: detected: LSE atomic instructions
10479 00:57:26.946539 <6>[ 0.287670] CPU features: detected: Privileged Access Never
10480 00:57:26.949252 <6>[ 0.293449] CPU features: detected: RAS Extension Support
10481 00:57:26.956198 <6>[ 0.299058] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10482 00:57:26.962897 <6>[ 0.306318] CPU: All CPU(s) started at EL2
10483 00:57:26.966078 <6>[ 0.310634] alternatives: applying system-wide alternatives
10484 00:57:26.977344 <6>[ 0.321483] devtmpfs: initialized
10485 00:57:26.989803 <6>[ 0.330323] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10486 00:57:26.999840 <6>[ 0.340285] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10487 00:57:27.006195 <6>[ 0.348300] pinctrl core: initialized pinctrl subsystem
10488 00:57:27.009734 <6>[ 0.354976] DMI not present or invalid.
10489 00:57:27.016668 <6>[ 0.359389] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10490 00:57:27.023014 <6>[ 0.366246] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10491 00:57:27.033569 <6>[ 0.373837] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10492 00:57:27.039899 <6>[ 0.382059] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10493 00:57:27.046217 <6>[ 0.390299] audit: initializing netlink subsys (disabled)
10494 00:57:27.056194 <5>[ 0.395991] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10495 00:57:27.059925 <6>[ 0.396706] thermal_sys: Registered thermal governor 'step_wise'
10496 00:57:27.066465 <6>[ 0.403961] thermal_sys: Registered thermal governor 'power_allocator'
10497 00:57:27.073216 <6>[ 0.410214] cpuidle: using governor menu
10498 00:57:27.076322 <6>[ 0.421173] NET: Registered PF_QIPCRTR protocol family
10499 00:57:27.082985 <6>[ 0.426659] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10500 00:57:27.089799 <6>[ 0.433764] ASID allocator initialised with 32768 entries
10501 00:57:27.096303 <6>[ 0.440338] Serial: AMBA PL011 UART driver
10502 00:57:27.105189 <4>[ 0.449178] Trying to register duplicate clock ID: 134
10503 00:57:27.163675 <6>[ 0.510821] KASLR enabled
10504 00:57:27.177948 <6>[ 0.518543] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10505 00:57:27.185024 <6>[ 0.525557] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10506 00:57:27.191544 <6>[ 0.532046] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10507 00:57:27.198595 <6>[ 0.539051] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10508 00:57:27.204864 <6>[ 0.545538] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10509 00:57:27.211076 <6>[ 0.552544] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10510 00:57:27.217684 <6>[ 0.559031] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10511 00:57:27.224399 <6>[ 0.566035] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10512 00:57:27.227809 <6>[ 0.573566] ACPI: Interpreter disabled.
10513 00:57:27.236118 <6>[ 0.580011] iommu: Default domain type: Translated
10514 00:57:27.242527 <6>[ 0.585124] iommu: DMA domain TLB invalidation policy: strict mode
10515 00:57:27.246207 <5>[ 0.591781] SCSI subsystem initialized
10516 00:57:27.252576 <6>[ 0.595948] usbcore: registered new interface driver usbfs
10517 00:57:27.259440 <6>[ 0.601678] usbcore: registered new interface driver hub
10518 00:57:27.262872 <6>[ 0.607231] usbcore: registered new device driver usb
10519 00:57:27.269137 <6>[ 0.613332] pps_core: LinuxPPS API ver. 1 registered
10520 00:57:27.279256 <6>[ 0.618525] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10521 00:57:27.282849 <6>[ 0.627872] PTP clock support registered
10522 00:57:27.285689 <6>[ 0.632116] EDAC MC: Ver: 3.0.0
10523 00:57:27.293361 <6>[ 0.637272] FPGA manager framework
10524 00:57:27.300098 <6>[ 0.640957] Advanced Linux Sound Architecture Driver Initialized.
10525 00:57:27.303469 <6>[ 0.647728] vgaarb: loaded
10526 00:57:27.306632 <6>[ 0.650880] clocksource: Switched to clocksource arch_sys_counter
10527 00:57:27.313355 <5>[ 0.657318] VFS: Disk quotas dquot_6.6.0
10528 00:57:27.319828 <6>[ 0.661502] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10529 00:57:27.323392 <6>[ 0.668692] pnp: PnP ACPI: disabled
10530 00:57:27.331376 <6>[ 0.675429] NET: Registered PF_INET protocol family
10531 00:57:27.341363 <6>[ 0.681025] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10532 00:57:27.352734 <6>[ 0.693349] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10533 00:57:27.362644 <6>[ 0.702165] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10534 00:57:27.369749 <6>[ 0.710137] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10535 00:57:27.376016 <6>[ 0.718840] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10536 00:57:27.388186 <6>[ 0.728594] TCP: Hash tables configured (established 65536 bind 65536)
10537 00:57:27.394622 <6>[ 0.735460] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10538 00:57:27.401335 <6>[ 0.742658] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10539 00:57:27.408291 <6>[ 0.750362] NET: Registered PF_UNIX/PF_LOCAL protocol family
10540 00:57:27.414767 <6>[ 0.756517] RPC: Registered named UNIX socket transport module.
10541 00:57:27.418021 <6>[ 0.762670] RPC: Registered udp transport module.
10542 00:57:27.424717 <6>[ 0.767602] RPC: Registered tcp transport module.
10543 00:57:27.431554 <6>[ 0.772535] RPC: Registered tcp NFSv4.1 backchannel transport module.
10544 00:57:27.434799 <6>[ 0.779201] PCI: CLS 0 bytes, default 64
10545 00:57:27.438260 <6>[ 0.783536] Unpacking initramfs...
10546 00:57:27.462768 <6>[ 0.802973] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10547 00:57:27.472079 <6>[ 0.811624] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10548 00:57:27.475576 <6>[ 0.820473] kvm [1]: IPA Size Limit: 40 bits
10549 00:57:27.482232 <6>[ 0.824999] kvm [1]: GICv3: no GICV resource entry
10550 00:57:27.485784 <6>[ 0.830021] kvm [1]: disabling GICv2 emulation
10551 00:57:27.492211 <6>[ 0.834710] kvm [1]: GIC system register CPU interface enabled
10552 00:57:27.495520 <6>[ 0.840878] kvm [1]: vgic interrupt IRQ18
10553 00:57:27.502218 <6>[ 0.845228] kvm [1]: VHE mode initialized successfully
10554 00:57:27.509230 <5>[ 0.851618] Initialise system trusted keyrings
10555 00:57:27.515119 <6>[ 0.856460] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10556 00:57:27.522326 <6>[ 0.866490] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10557 00:57:27.529213 <5>[ 0.872892] NFS: Registering the id_resolver key type
10558 00:57:27.532486 <5>[ 0.878188] Key type id_resolver registered
10559 00:57:27.539352 <5>[ 0.882605] Key type id_legacy registered
10560 00:57:27.545972 <6>[ 0.886899] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10561 00:57:27.552210 <6>[ 0.893825] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10562 00:57:27.558966 <6>[ 0.901570] 9p: Installing v9fs 9p2000 file system support
10563 00:57:27.595539 <5>[ 0.939454] Key type asymmetric registered
10564 00:57:27.598654 <5>[ 0.943787] Asymmetric key parser 'x509' registered
10565 00:57:27.609363 <6>[ 0.948958] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10566 00:57:27.612012 <6>[ 0.956572] io scheduler mq-deadline registered
10567 00:57:27.615332 <6>[ 0.961351] io scheduler kyber registered
10568 00:57:27.633978 <6>[ 0.978322] EINJ: ACPI disabled.
10569 00:57:27.667322 <4>[ 1.004423] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10570 00:57:27.677495 <4>[ 1.015062] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 00:57:27.692401 <6>[ 1.036008] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10572 00:57:27.700125 <6>[ 1.044042] printk: console [ttyS0] disabled
10573 00:57:27.728094 <6>[ 1.068673] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10574 00:57:27.734598 <6>[ 1.078147] printk: console [ttyS0] enabled
10575 00:57:27.738092 <6>[ 1.078147] printk: console [ttyS0] enabled
10576 00:57:27.744907 <6>[ 1.087041] printk: bootconsole [mtk8250] disabled
10577 00:57:27.748057 <6>[ 1.087041] printk: bootconsole [mtk8250] disabled
10578 00:57:27.754853 <6>[ 1.098320] SuperH (H)SCI(F) driver initialized
10579 00:57:27.757845 <6>[ 1.103603] msm_serial: driver initialized
10580 00:57:27.772076 <6>[ 1.112622] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10581 00:57:27.781701 <6>[ 1.121170] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10582 00:57:27.788425 <6>[ 1.129719] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10583 00:57:27.798648 <6>[ 1.138350] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10584 00:57:27.808221 <6>[ 1.147066] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10585 00:57:27.814678 <6>[ 1.155784] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10586 00:57:27.825294 <6>[ 1.164325] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10587 00:57:27.831639 <6>[ 1.173152] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10588 00:57:27.841326 <6>[ 1.181695] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10589 00:57:27.853080 <6>[ 1.197184] loop: module loaded
10590 00:57:27.859496 <6>[ 1.203208] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10591 00:57:27.882642 <4>[ 1.226677] mtk-pmic-keys: Failed to locate of_node [id: -1]
10592 00:57:27.889616 <6>[ 1.233729] megasas: 07.719.03.00-rc1
10593 00:57:27.899659 <6>[ 1.243531] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10594 00:57:27.906336 <6>[ 1.250257] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10595 00:57:27.923082 <6>[ 1.266891] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10596 00:57:27.979519 <6>[ 1.316861] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10597 00:57:28.230414 <6>[ 1.574593] Freeing initrd memory: 18292K
10598 00:57:28.242308 <6>[ 1.586147] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10599 00:57:28.253093 <6>[ 1.597185] tun: Universal TUN/TAP device driver, 1.6
10600 00:57:28.256618 <6>[ 1.603271] thunder_xcv, ver 1.0
10601 00:57:28.259537 <6>[ 1.606767] thunder_bgx, ver 1.0
10602 00:57:28.263026 <6>[ 1.610265] nicpf, ver 1.0
10603 00:57:28.273394 <6>[ 1.614308] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10604 00:57:28.276901 <6>[ 1.621785] hns3: Copyright (c) 2017 Huawei Corporation.
10605 00:57:28.280439 <6>[ 1.627378] hclge is initializing
10606 00:57:28.286828 <6>[ 1.630961] e1000: Intel(R) PRO/1000 Network Driver
10607 00:57:28.293896 <6>[ 1.636091] e1000: Copyright (c) 1999-2006 Intel Corporation.
10608 00:57:28.297067 <6>[ 1.642105] e1000e: Intel(R) PRO/1000 Network Driver
10609 00:57:28.304022 <6>[ 1.647321] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10610 00:57:28.310627 <6>[ 1.653508] igb: Intel(R) Gigabit Ethernet Network Driver
10611 00:57:28.317032 <6>[ 1.659159] igb: Copyright (c) 2007-2014 Intel Corporation.
10612 00:57:28.323619 <6>[ 1.664996] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10613 00:57:28.327260 <6>[ 1.671513] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10614 00:57:28.334077 <6>[ 1.677974] sky2: driver version 1.30
10615 00:57:28.340503 <6>[ 1.682909] usbcore: registered new device driver r8152-cfgselector
10616 00:57:28.347082 <6>[ 1.689443] usbcore: registered new interface driver r8152
10617 00:57:28.351641 <6>[ 1.695263] VFIO - User Level meta-driver version: 0.3
10618 00:57:28.359326 <6>[ 1.703554] usbcore: registered new interface driver usb-storage
10619 00:57:28.366443 <6>[ 1.709997] usbcore: registered new device driver onboard-usb-hub
10620 00:57:28.375239 <6>[ 1.719190] mt6397-rtc mt6359-rtc: registered as rtc0
10621 00:57:28.385094 <6>[ 1.724659] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:57:28 UTC (1718499448)
10622 00:57:28.388311 <6>[ 1.734240] i2c_dev: i2c /dev entries driver
10623 00:57:28.402528 <4>[ 1.746268] cpu cpu0: supply cpu not found, using dummy regulator
10624 00:57:28.408935 <4>[ 1.752708] cpu cpu1: supply cpu not found, using dummy regulator
10625 00:57:28.415405 <4>[ 1.759111] cpu cpu2: supply cpu not found, using dummy regulator
10626 00:57:28.422473 <4>[ 1.765511] cpu cpu3: supply cpu not found, using dummy regulator
10627 00:57:28.429526 <4>[ 1.771906] cpu cpu4: supply cpu not found, using dummy regulator
10628 00:57:28.435518 <4>[ 1.778304] cpu cpu5: supply cpu not found, using dummy regulator
10629 00:57:28.442493 <4>[ 1.784718] cpu cpu6: supply cpu not found, using dummy regulator
10630 00:57:28.448691 <4>[ 1.791143] cpu cpu7: supply cpu not found, using dummy regulator
10631 00:57:28.470382 <6>[ 1.812782] cpu cpu0: EM: created perf domain
10632 00:57:28.472811 <6>[ 1.817715] cpu cpu4: EM: created perf domain
10633 00:57:28.479164 <6>[ 1.823353] sdhci: Secure Digital Host Controller Interface driver
10634 00:57:28.486522 <6>[ 1.829784] sdhci: Copyright(c) Pierre Ossman
10635 00:57:28.493022 <6>[ 1.834740] Synopsys Designware Multimedia Card Interface Driver
10636 00:57:28.499496 <6>[ 1.841378] sdhci-pltfm: SDHCI platform and OF driver helper
10637 00:57:28.502717 <6>[ 1.841445] mmc0: CQHCI version 5.10
10638 00:57:28.509422 <6>[ 1.851734] ledtrig-cpu: registered to indicate activity on CPUs
10639 00:57:28.516253 <6>[ 1.858849] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10640 00:57:28.522663 <6>[ 1.865908] usbcore: registered new interface driver usbhid
10641 00:57:28.526532 <6>[ 1.871740] usbhid: USB HID core driver
10642 00:57:28.533248 <6>[ 1.875924] spi_master spi0: will run message pump with realtime priority
10643 00:57:28.577814 <6>[ 1.915207] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10644 00:57:28.593821 <6>[ 1.931190] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10645 00:57:28.600270 <6>[ 1.940950] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10646 00:57:28.609491 <6>[ 1.953014] cros-ec-spi spi0.0: Chrome EC device registered
10647 00:57:28.615841 <6>[ 1.959059] mmc0: Command Queue Engine enabled
10648 00:57:28.622295 <6>[ 1.963817] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10649 00:57:28.625844 <6>[ 1.971550] mmcblk0: mmc0:0001 DA4128 116 GiB
10650 00:57:28.638239 <6>[ 1.982272] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10651 00:57:28.648337 <6>[ 1.987546] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10652 00:57:28.654828 <6>[ 1.989520] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10653 00:57:28.657949 <6>[ 1.998762] NET: Registered PF_PACKET protocol family
10654 00:57:28.664537 <6>[ 2.003492] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10655 00:57:28.668471 <6>[ 2.008095] 9pnet: Installing 9P2000 support
10656 00:57:28.675054 <6>[ 2.013920] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10657 00:57:28.678268 <5>[ 2.017782] Key type dns_resolver registered
10658 00:57:28.685157 <6>[ 2.029233] registered taskstats version 1
10659 00:57:28.688524 <5>[ 2.033608] Loading compiled-in X.509 certificates
10660 00:57:28.718411 <4>[ 2.055610] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10661 00:57:28.728453 <4>[ 2.066367] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10662 00:57:28.741916 <6>[ 2.085909] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10663 00:57:28.748722 <6>[ 2.092790] xhci-mtk 11200000.usb: xHCI Host Controller
10664 00:57:28.755204 <6>[ 2.098291] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10665 00:57:28.765437 <6>[ 2.106134] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10666 00:57:28.772136 <6>[ 2.115558] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10667 00:57:28.778747 <6>[ 2.121668] xhci-mtk 11200000.usb: xHCI Host Controller
10668 00:57:28.785411 <6>[ 2.127154] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10669 00:57:28.791886 <6>[ 2.134809] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10670 00:57:28.798546 <6>[ 2.142437] hub 1-0:1.0: USB hub found
10671 00:57:28.802270 <6>[ 2.146472] hub 1-0:1.0: 1 port detected
10672 00:57:28.808562 <6>[ 2.150752] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10673 00:57:28.815777 <6>[ 2.159279] hub 2-0:1.0: USB hub found
10674 00:57:28.818666 <6>[ 2.163290] hub 2-0:1.0: 1 port detected
10675 00:57:28.826431 <6>[ 2.170302] mtk-msdc 11f70000.mmc: Got CD GPIO
10676 00:57:28.839523 <6>[ 2.180483] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10677 00:57:28.846617 <6>[ 2.188882] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10678 00:57:28.856379 <6>[ 2.197231] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10679 00:57:28.863463 <6>[ 2.205570] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10680 00:57:28.873319 <6>[ 2.213908] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10681 00:57:28.880143 <6>[ 2.222246] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10682 00:57:28.889925 <6>[ 2.230586] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10683 00:57:28.896320 <6>[ 2.238925] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10684 00:57:28.906499 <6>[ 2.247262] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10685 00:57:28.916383 <6>[ 2.255603] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10686 00:57:28.923141 <6>[ 2.263942] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10687 00:57:28.932860 <6>[ 2.272288] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10688 00:57:28.940141 <6>[ 2.280626] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10689 00:57:28.949991 <6>[ 2.288964] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10690 00:57:28.956592 <6>[ 2.297301] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10691 00:57:28.963450 <6>[ 2.306009] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10692 00:57:28.969646 <6>[ 2.313174] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10693 00:57:28.976271 <6>[ 2.319989] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10694 00:57:28.983020 <6>[ 2.326754] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10695 00:57:28.989354 <6>[ 2.333723] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10696 00:57:28.999833 <6>[ 2.340573] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10697 00:57:29.009404 <6>[ 2.349705] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10698 00:57:29.019650 <6>[ 2.358824] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10699 00:57:29.029426 <6>[ 2.368120] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10700 00:57:29.039455 <6>[ 2.377586] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10701 00:57:29.046776 <6>[ 2.387054] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10702 00:57:29.056082 <6>[ 2.396174] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10703 00:57:29.065929 <6>[ 2.405640] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10704 00:57:29.075866 <6>[ 2.414759] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10705 00:57:29.085717 <6>[ 2.424056] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10706 00:57:29.095741 <6>[ 2.434216] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10707 00:57:29.105837 <6>[ 2.445898] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10708 00:57:29.112586 <6>[ 2.457034] Trying to probe devices needed for running init ...
10709 00:57:29.123714 <3>[ 2.464292] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10710 00:57:29.223238 <6>[ 2.567164] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10711 00:57:29.380900 <6>[ 2.724953] hub 1-1:1.0: USB hub found
10712 00:57:29.383828 <6>[ 2.729507] hub 1-1:1.0: 4 ports detected
10713 00:57:29.396176 <6>[ 2.740394] hub 1-1:1.0: USB hub found
10714 00:57:29.399629 <6>[ 2.744821] hub 1-1:1.0: 4 ports detected
10715 00:57:29.505944 <6>[ 2.847206] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10716 00:57:29.533057 <6>[ 2.877177] hub 2-1:1.0: USB hub found
10717 00:57:29.536258 <6>[ 2.881698] hub 2-1:1.0: 3 ports detected
10718 00:57:29.548246 <6>[ 2.892423] hub 2-1:1.0: USB hub found
10719 00:57:29.551263 <6>[ 2.896855] hub 2-1:1.0: 3 ports detected
10720 00:57:29.722359 <6>[ 3.063199] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10721 00:57:29.854971 <6>[ 3.199091] hub 1-1.4:1.0: USB hub found
10722 00:57:29.858220 <6>[ 3.203679] hub 1-1.4:1.0: 2 ports detected
10723 00:57:29.870340 <6>[ 3.214503] hub 1-1.4:1.0: USB hub found
10724 00:57:29.873454 <6>[ 3.219114] hub 1-1.4:1.0: 2 ports detected
10725 00:57:29.938239 <6>[ 3.279401] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10726 00:57:30.046860 <6>[ 3.387835] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10727 00:57:30.083468 <4>[ 3.424330] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10728 00:57:30.093530 <4>[ 3.433417] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10729 00:57:30.128153 <6>[ 3.472452] r8152 2-1.3:1.0 eth0: v1.12.13
10730 00:57:30.169968 <6>[ 3.510909] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10731 00:57:30.362391 <6>[ 3.703053] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10732 00:57:31.793075 <6>[ 5.136888] r8152 2-1.3:1.0 eth0: carrier on
10733 00:57:34.246234 <5>[ 5.158951] Sending DHCP requests .., OK
10734 00:57:34.252641 <6>[ 7.595351] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10735 00:57:34.256263 <6>[ 7.603644] IP-Config: Complete:
10736 00:57:34.269957 <6>[ 7.607144] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10737 00:57:34.276107 <6>[ 7.617854] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10738 00:57:34.282687 <6>[ 7.626473] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10739 00:57:34.289214 <6>[ 7.626482] nameserver0=192.168.201.1
10740 00:57:34.292754 <6>[ 7.638639] clk: Disabling unused clocks
10741 00:57:34.296689 <6>[ 7.644185] ALSA device list:
10742 00:57:34.302607 <6>[ 7.647462] No soundcards found.
10743 00:57:34.310432 <6>[ 7.655219] Freeing unused kernel memory: 8512K
10744 00:57:34.314327 <6>[ 7.660127] Run /init as init process
10745 00:57:34.323282 Loading, please wait...
10746 00:57:34.349270 Starting systemd-udevd version 252.22-1~deb12u1
10747 00:57:34.659355 <6>[ 8.001038] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10748 00:57:34.690451 <6>[ 8.031880] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10749 00:57:34.697028 <6>[ 8.040207] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10750 00:57:34.704002 <6>[ 8.041698] mc: Linux media interface: v0.10
10751 00:57:34.710148 <4>[ 8.048293] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10752 00:57:34.721477 <6>[ 8.062725] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10753 00:57:34.727705 <6>[ 8.065918] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10754 00:57:34.737630 <6>[ 8.072361] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10755 00:57:34.744314 <6>[ 8.072420] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10756 00:57:34.754684 <6>[ 8.072467] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10757 00:57:34.761500 <6>[ 8.072480] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10758 00:57:34.771067 <3>[ 8.083351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 00:57:34.777976 <6>[ 8.086726] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10760 00:57:34.784763 <4>[ 8.087806] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10761 00:57:34.790929 <4>[ 8.087900] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10762 00:57:34.800844 <3>[ 8.094175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10763 00:57:34.807862 <6>[ 8.098110] videodev: Linux video capture interface: v2.00
10764 00:57:34.814495 <6>[ 8.102791] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10765 00:57:34.821245 <6>[ 8.102801] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10766 00:57:34.831071 <6>[ 8.102809] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10767 00:57:34.840820 <6>[ 8.168671] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10768 00:57:34.847823 <3>[ 8.171681] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10769 00:57:34.857394 <6>[ 8.181130] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10770 00:57:34.867646 <3>[ 8.191118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 00:57:34.874713 <6>[ 8.196236] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10772 00:57:34.877879 <6>[ 8.196246] pci_bus 0000:00: root bus resource [bus 00-ff]
10773 00:57:34.888107 <6>[ 8.196254] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10774 00:57:34.897510 <6>[ 8.196261] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10775 00:57:34.904202 <6>[ 8.196306] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10776 00:57:34.910976 <6>[ 8.196334] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10777 00:57:34.914407 <6>[ 8.196438] pci 0000:00:00.0: supports D1 D2
10778 00:57:34.920782 <6>[ 8.196444] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10779 00:57:34.931344 <6>[ 8.198668] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10780 00:57:34.937610 <6>[ 8.198803] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10781 00:57:34.944282 <6>[ 8.198839] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10782 00:57:34.950857 <6>[ 8.198863] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10783 00:57:34.957310 <6>[ 8.198897] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10784 00:57:34.964610 <6>[ 8.199049] pci 0000:01:00.0: supports D1 D2
10785 00:57:34.971405 <6>[ 8.199058] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10786 00:57:34.977884 <6>[ 8.199314] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10787 00:57:34.987705 <3>[ 8.208309] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10788 00:57:34.996047 <6>[ 8.214980] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10789 00:57:35.002502 <6>[ 8.215011] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10790 00:57:35.008931 <6>[ 8.215018] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10791 00:57:35.018511 <6>[ 8.215030] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10792 00:57:35.025287 <6>[ 8.215047] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10793 00:57:35.036039 <6>[ 8.215063] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10794 00:57:35.038385 <6>[ 8.215079] pci 0000:00:00.0: PCI bridge to [bus 01]
10795 00:57:35.048365 <6>[ 8.215088] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10796 00:57:35.054955 <6>[ 8.215226] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10797 00:57:35.058980 <6>[ 8.216173] pcieport 0000:00:00.0: PME: Signaling with IRQ 281
10798 00:57:35.065089 <6>[ 8.216911] pcieport 0000:00:00.0: AER: enabled with IRQ 281
10799 00:57:35.075002 <3>[ 8.223505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10800 00:57:35.081583 <6>[ 8.224902] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10801 00:57:35.084880 <6>[ 8.227348] remoteproc remoteproc0: scp is available
10802 00:57:35.091595 <6>[ 8.227424] remoteproc remoteproc0: powering up scp
10803 00:57:35.098322 <6>[ 8.227431] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10804 00:57:35.104726 <6>[ 8.227450] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10805 00:57:35.114973 <4>[ 8.246249] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10806 00:57:35.118140 <4>[ 8.246249] Fallback method does not support PEC.
10807 00:57:35.128203 <5>[ 8.248731] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10808 00:57:35.134763 <3>[ 8.252512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10809 00:57:35.138094 <6>[ 8.265142] Bluetooth: Core ver 2.22
10810 00:57:35.144813 <5>[ 8.269348] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10811 00:57:35.155123 <5>[ 8.269800] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10812 00:57:35.161163 <4>[ 8.269876] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10813 00:57:35.167908 <6>[ 8.269884] cfg80211: failed to load regulatory.db
10814 00:57:35.174398 <3>[ 8.271366] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10815 00:57:35.184840 <3>[ 8.271442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10816 00:57:35.191495 <6>[ 8.272869] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10817 00:57:35.204845 <6>[ 8.274239] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10818 00:57:35.211218 <6>[ 8.274331] usbcore: registered new interface driver uvcvideo
10819 00:57:35.214541 <6>[ 8.279728] NET: Registered PF_BLUETOOTH protocol family
10820 00:57:35.224481 <3>[ 8.285947] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10821 00:57:35.231383 <6>[ 8.293360] Bluetooth: HCI device and connection manager initialized
10822 00:57:35.238147 <3>[ 8.300831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 00:57:35.244518 <6>[ 8.308325] Bluetooth: HCI socket layer initialized
10824 00:57:35.251022 <3>[ 8.312831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10825 00:57:35.257803 <6>[ 8.319699] Bluetooth: L2CAP socket layer initialized
10826 00:57:35.264503 <6>[ 8.320419] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10827 00:57:35.271097 <3>[ 8.322428] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10828 00:57:35.281404 <3>[ 8.329054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10829 00:57:35.284838 <6>[ 8.337074] Bluetooth: SCO socket layer initialized
10830 00:57:35.294043 <3>[ 8.343939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 00:57:35.300983 <3>[ 8.345477] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10832 00:57:35.307620 <6>[ 8.348811] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10833 00:57:35.318080 <6>[ 8.349039] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10834 00:57:35.324250 <6>[ 8.349049] remoteproc remoteproc0: remote processor scp is now up
10835 00:57:35.330626 <6>[ 8.356446] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10836 00:57:35.340545 <3>[ 8.360022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10837 00:57:35.347471 <6>[ 8.361578] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10838 00:57:35.353791 <6>[ 8.364331] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10839 00:57:35.360839 <6>[ 8.368299] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10840 00:57:35.370880 <3>[ 8.376008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 00:57:35.377177 <3>[ 8.376012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 00:57:35.387183 <3>[ 8.376038] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10843 00:57:35.390596 <6>[ 8.403084] mt7921e 0000:01:00.0: ASIC revision: 79610010
10844 00:57:35.397045 <6>[ 8.404127] usbcore: registered new interface driver btusb
10845 00:57:35.410122 Begin: Loading e<4>[ 8.404996] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10846 00:57:35.413661 <3>[ 8.405005] Bluetooth: hci0: Failed to load firmware file (-2)
10847 00:57:35.420665 <3>[ 8.405008] Bluetooth: hci0: Failed to set up firmware (-2)
10848 00:57:35.430766 <4>[ 8.405011] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10849 00:57:35.440476 <6>[ 8.502429] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10850 00:57:35.440562 <6>[ 8.502429]
10851 00:57:35.444178 ssential drivers ... done.
10852 00:57:35.447275 Begin: Running /scripts/init-premount ... done.
10853 00:57:35.457066 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10854 00:57:35.463516 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10855 00:57:35.466771 Device /sys/class/net/eth0 found
10856 00:57:35.466847 done.
10857 00:57:35.489738 Begin: Waiting up to 180 secs for any network device to become available ... done.
10858 00:57:35.550523 IP-Config: eth0 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10859 00:57:35.556759 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10860 00:57:35.563420 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10861 00:57:35.570446 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10862 00:57:35.576625 host : mt8192-asurada-spherion-r0-cbg-3
10863 00:57:35.583765 domain : lava-rack
10864 00:57:35.586724 rootserver: 192.168.201.1 rootpath:
10865 00:57:35.586802 filename :
10866 00:57:35.593600 done.
10867 00:57:35.601595 Begin: Running /scripts/nfs-bottom ... done.
10868 00:57:35.614201 Begin: Running /scripts/init-bottom ... done.
10869 00:57:35.709728 <6>[ 9.051287] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10870 00:57:36.957873 <6>[ 10.302506] NET: Registered PF_INET6 protocol family
10871 00:57:36.965840 <6>[ 10.310098] Segment Routing with IPv6
10872 00:57:36.969095 <6>[ 10.314073] In-situ OAM (IOAM) with IPv6
10873 00:57:37.157881 <30>[ 10.475886] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10874 00:57:37.164253 <30>[ 10.508978] systemd[1]: Detected architecture arm64.
10875 00:57:37.174621
10876 00:57:37.177499 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10877 00:57:37.177841
10878 00:57:37.200436 <30>[ 10.545395] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10879 00:57:38.259990 <30>[ 11.602280] systemd[1]: Queued start job for default target graphical.target.
10880 00:57:38.298859 <30>[ 11.640526] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10881 00:57:38.305701 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10882 00:57:38.326929 <30>[ 11.668900] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10883 00:57:38.336780 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10884 00:57:38.354751 <30>[ 11.696920] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10885 00:57:38.364924 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10886 00:57:38.383614 <30>[ 11.725370] systemd[1]: Created slice user.slice - User and Session Slice.
10887 00:57:38.389772 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10888 00:57:38.413175 <30>[ 11.752080] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10889 00:57:38.423211 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10890 00:57:38.441156 <30>[ 11.779428] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10891 00:57:38.447669 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10892 00:57:38.475988 <30>[ 11.807860] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10893 00:57:38.485869 <30>[ 11.827767] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10894 00:57:38.492176 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10895 00:57:38.509327 <30>[ 11.851548] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10896 00:57:38.519397 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10897 00:57:38.537786 <30>[ 11.879698] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10898 00:57:38.547715 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10899 00:57:38.562445 <30>[ 11.907711] systemd[1]: Reached target paths.target - Path Units.
10900 00:57:38.572413 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10901 00:57:38.589570 <30>[ 11.931656] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10902 00:57:38.596385 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10903 00:57:38.610050 <30>[ 11.955175] systemd[1]: Reached target slices.target - Slice Units.
10904 00:57:38.620094 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10905 00:57:38.634335 <30>[ 11.979676] systemd[1]: Reached target swap.target - Swaps.
10906 00:57:38.640839 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10907 00:57:38.661747 <30>[ 12.003669] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10908 00:57:38.672059 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10909 00:57:38.690310 <30>[ 12.032226] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10910 00:57:38.700486 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10911 00:57:38.720414 <30>[ 12.062294] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10912 00:57:38.730209 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10913 00:57:38.746517 <30>[ 12.088647] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10914 00:57:38.757169 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10915 00:57:38.773017 <30>[ 12.115310] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10916 00:57:38.779743 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10917 00:57:38.798426 <30>[ 12.140737] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10918 00:57:38.808482 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10919 00:57:38.828037 <30>[ 12.169944] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10920 00:57:38.837560 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10921 00:57:38.854684 <30>[ 12.196367] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10922 00:57:38.864281 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10923 00:57:38.905257 <30>[ 12.247230] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10924 00:57:38.911725 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10925 00:57:38.933546 <30>[ 12.275398] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10926 00:57:38.940363 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10927 00:57:38.965728 <30>[ 12.307572] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10928 00:57:38.972600 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10929 00:57:39.000040 <30>[ 12.335765] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10930 00:57:39.049923 <30>[ 12.391901] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10931 00:57:39.059847 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10932 00:57:39.082797 <30>[ 12.424905] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10933 00:57:39.089673 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10934 00:57:39.114726 <30>[ 12.456343] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10935 00:57:39.120724 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10936 00:57:39.145875 <30>[ 12.488017] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10937 00:57:39.152806 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10938 00:57:39.162894 <6>[ 12.503380] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10939 00:57:39.169235 <30>[ 12.509439] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10940 00:57:39.179633 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10941 00:57:39.202784 <30>[ 12.544879] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10942 00:57:39.209148 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10943 00:57:39.234631 <30>[ 12.576342] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10944 00:57:39.244113 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 12.590183] fuse: init (API version 7.37)
10945 00:57:39.247319 el Module loop...
10946 00:57:39.297596 <30>[ 12.639627] systemd[1]: Starting systemd-journald.service - Journal Service...
10947 00:57:39.303931 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10948 00:57:39.329654 <30>[ 12.671607] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10949 00:57:39.336385 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10950 00:57:39.365648 <30>[ 12.703955] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10951 00:57:39.371774 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10952 00:57:39.396186 <30>[ 12.738192] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10953 00:57:39.406205 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10954 00:57:39.430906 <30>[ 12.772951] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10955 00:57:39.437499 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10956 00:57:39.465422 <30>[ 12.807275] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10957 00:57:39.471845 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10958 00:57:39.489696 <30>[ 12.831745] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10959 00:57:39.496816 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10960 00:57:39.517671 <30>[ 12.859844] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10961 00:57:39.524637 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10962 00:57:39.538523 <3>[ 12.880400] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 00:57:39.549493 <30>[ 12.891813] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10964 00:57:39.560578 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10965 00:57:39.567451 <3>[ 12.909202] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 00:57:39.582333 <30>[ 12.924237] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10967 00:57:39.588571 <30>[ 12.932075] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10968 00:57:39.606419 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Modu<3>[ 12.947503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 00:57:39.606541 le configfs.
10970 00:57:39.626604 <30>[ 12.968288] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10971 00:57:39.633763 <30>[ 12.975997] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10972 00:57:39.643732 <3>[ 12.979819] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 00:57:39.650452 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10974 00:57:39.667516 <30>[ 13.012163] systemd[1]: modprobe@drm.service: Deactivated successfully.
10975 00:57:39.677025 <3>[ 13.014513] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 00:57:39.683749 <30>[ 13.019634] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10977 00:57:39.693707 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10978 00:57:39.710661 <30>[ 13.051837] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10979 00:57:39.716954 <3>[ 13.053881] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 00:57:39.726754 <30>[ 13.059717] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10981 00:57:39.736933 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10982 00:57:39.750755 <3>[ 13.092583] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 00:57:39.757290 <30>[ 13.102357] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10984 00:57:39.768282 <30>[ 13.109704] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10985 00:57:39.775450 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10986 00:57:39.785341 <3>[ 13.124730] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 00:57:39.797947 <30>[ 13.140127] systemd[1]: modprobe@loop.service: Deactivated successfully.
10988 00:57:39.804824 <30>[ 13.147552] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10989 00:57:39.811666 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10990 00:57:39.834612 <30>[ 13.176123] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10991 00:57:39.854735 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Ker<4>[ 13.190666] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10992 00:57:39.864619 <3>[ 13.206986] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10993 00:57:39.864723 nel Modules.
10994 00:57:39.883982 <30>[ 13.225284] systemd[1]: Started systemd-journald.service - Journal Service.
10995 00:57:39.890498 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10996 00:57:39.911024 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10997 00:57:39.934125 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10998 00:57:39.958354 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10999 00:57:39.983809 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11000 00:57:40.025931 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11001 00:57:40.050275 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11002 00:57:40.101883 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11003 00:57:40.124456 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11004 00:57:40.149669 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11005 00:57:40.180637 Starting [0;1;39msystemd-sysusers.…rvice[0m - Creat<46>[ 13.520635] systemd-journald[311]: Received client request to flush runtime journal.
11006 00:57:40.180753 e System Users...
11007 00:57:40.215803 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11008 00:57:40.234122 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11009 00:57:40.254333 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11010 00:57:40.274147 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11011 00:57:40.979210 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11012 00:57:41.033954 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11013 00:57:41.630856 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11014 00:57:41.686474 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11015 00:57:41.705629 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11016 00:57:41.725164 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11017 00:57:41.773909 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11018 00:57:41.801006 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11019 00:57:42.076241 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11020 00:57:42.152405 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11021 00:57:42.237440 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11022 00:57:42.456998 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11023 00:57:42.504444 <6>[ 15.850205] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11024 00:57:42.510959 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11025 00:57:42.549349 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11026 00:57:42.587083 <4>[ 15.933049] power_supply_show_property: 4 callbacks suppressed
11027 00:57:42.597100 <3>[ 15.933082] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11028 00:57:42.603900 <3>[ 15.939985] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11029 00:57:42.613875 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11030 00:57:42.627655 <3>[ 15.970275] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11031 00:57:42.641889 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11032 00:57:42.660068 <3>[ 16.002599] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11033 00:57:42.698333 Startin<3>[ 16.041550] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11034 00:57:42.705562 g [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11035 00:57:42.730908 <3>[ 16.073227] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11036 00:57:42.760611 <3>[ 16.102690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11037 00:57:42.770510 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11038 00:57:42.789287 [[0;32m OK [0m] Started [0;1;39msystemd-net<3>[ 16.131787] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11039 00:57:42.793029 workd.service[0m - Network Configuration.
11040 00:57:42.820938 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutd<3>[ 16.162369] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11041 00:57:42.821027 own in UTMP.
11042 00:57:42.842848 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11043 00:57:42.862196 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11044 00:57:42.872292 <3>[ 16.213003] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11045 00:57:42.901333 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11046 00:57:42.922143 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11047 00:57:42.941004 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11048 00:57:42.955984 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11049 00:57:42.973225 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11050 00:57:42.997858 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11051 00:57:43.020338 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11052 00:57:43.037384 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11053 00:57:43.056580 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11054 00:57:43.076450 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11055 00:57:43.092801 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11056 00:57:43.110961 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11057 00:57:43.128551 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11058 00:57:43.135478 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11059 00:57:43.183132 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11060 00:57:43.215650 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11061 00:57:43.342178 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11062 00:57:43.365456 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11063 00:57:43.385944 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11064 00:57:43.418578 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11065 00:57:43.466270 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11066 00:57:43.485189 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11067 00:57:43.501056 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11068 00:57:43.533814 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11069 00:57:43.591936 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11070 00:57:43.725657 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11071 00:57:43.753910 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11072 00:57:43.777534 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11073 00:57:43.849961 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11074 00:57:43.919928 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11075 00:57:43.994278
11076 00:57:43.997859 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11077 00:57:43.997934
11078 00:57:44.001535 debian-bookworm-arm64 login: root (automatic login)
11079 00:57:44.001602
11080 00:57:44.305054 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
11081 00:57:44.305182
11082 00:57:44.311754 The programs included with the Debian GNU/Linux system are free software;
11083 00:57:44.318066 the exact distribution terms for each program are described in the
11084 00:57:44.321355 individual files in /usr/share/doc/*/copyright.
11085 00:57:44.321424
11086 00:57:44.328381 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11087 00:57:44.331671 permitted by applicable law.
11088 00:57:45.379001 Matched prompt #10: / #
11090 00:57:45.379249 Setting prompt string to ['/ #']
11091 00:57:45.379339 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11093 00:57:45.379515 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11094 00:57:45.379597 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
11095 00:57:45.379665 Setting prompt string to ['/ #']
11096 00:57:45.379720 Forcing a shell prompt, looking for ['/ #']
11098 00:57:45.429952 / #
11099 00:57:45.430140 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11100 00:57:45.430216 Waiting using forced prompt support (timeout 00:02:30)
11101 00:57:45.435316
11102 00:57:45.435579 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11103 00:57:45.435668 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
11105 00:57:45.535999 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368562/extract-nfsrootfs-azas7lbe'
11106 00:57:45.541619 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368562/extract-nfsrootfs-azas7lbe'
11108 00:57:45.642169 / # export NFS_SERVER_IP='192.168.201.1'
11109 00:57:45.647273 export NFS_SERVER_IP='192.168.201.1'
11110 00:57:45.647546 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11111 00:57:45.647638 end: 2.2 depthcharge-retry (duration 00:01:43) [common]
11112 00:57:45.647722 end: 2 depthcharge-action (duration 00:01:43) [common]
11113 00:57:45.647806 start: 3 lava-test-retry (timeout 00:07:34) [common]
11114 00:57:45.647892 start: 3.1 lava-test-shell (timeout 00:07:34) [common]
11115 00:57:45.647959 Using namespace: common
11117 00:57:45.748289 / # #
11118 00:57:45.748467 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11119 00:57:45.753936 #
11120 00:57:45.754236 Using /lava-14368562
11122 00:57:45.854529 / # export SHELL=/bin/bash
11123 00:57:45.859733 export SHELL=/bin/bash
11125 00:57:45.960208 / # . /lava-14368562/environment
11126 00:57:45.965786 . /lava-14368562/environment
11128 00:57:46.072011 / # /lava-14368562/bin/lava-test-runner /lava-14368562/0
11129 00:57:46.072198 Test shell timeout: 10s (minimum of the action and connection timeout)
11130 00:57:46.077328 /lava-14368562/bin/lava-test-runner /lava-14368562/0
11131 00:57:46.371739 + export TESTRUN_ID=0_timesync-off
11132 00:57:46.375328 + TESTRUN_ID=0_timesync-off
11133 00:57:46.378678 + cd /lava-14368562/0/tests/0_timesync-off
11134 00:57:46.381756 ++ cat uuid
11135 00:57:46.387800 + UUID=14368562_1.6.2.3.1
11136 00:57:46.387899 + set +x
11137 00:57:46.394740 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368562_1.6.2.3.1>
11138 00:57:46.395039 Received signal: <STARTRUN> 0_timesync-off 14368562_1.6.2.3.1
11139 00:57:46.395150 Starting test lava.0_timesync-off (14368562_1.6.2.3.1)
11140 00:57:46.395263 Skipping test definition patterns.
11141 00:57:46.397797 + systemctl stop systemd-timesyncd
11142 00:57:46.480008 + set +x
11143 00:57:46.483730 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368562_1.6.2.3.1>
11144 00:57:46.484025 Received signal: <ENDRUN> 0_timesync-off 14368562_1.6.2.3.1
11145 00:57:46.484129 Ending use of test pattern.
11146 00:57:46.484224 Ending test lava.0_timesync-off (14368562_1.6.2.3.1), duration 0.09
11148 00:57:46.564226 + export TESTRUN_ID=1_kselftest-rtc
11149 00:57:46.567398 + TESTRUN_ID=1_kselftest-rtc
11150 00:57:46.570537 + cd /lava-14368562/0/tests/1_kselftest-rtc
11151 00:57:46.573859 ++ cat uuid
11152 00:57:46.579961 + UUID=14368562_1.6.2.3.5
11153 00:57:46.580074 + set +x
11154 00:57:46.586800 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14368562_1.6.2.3.5>
11155 00:57:46.587074 Received signal: <STARTRUN> 1_kselftest-rtc 14368562_1.6.2.3.5
11156 00:57:46.587170 Starting test lava.1_kselftest-rtc (14368562_1.6.2.3.5)
11157 00:57:46.587279 Skipping test definition patterns.
11158 00:57:46.590052 + cd ./automated/linux/kselftest/
11159 00:57:46.616396 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11160 00:57:46.662628 INFO: install_deps skipped
11161 00:57:47.177437 --2024-06-16 00:57:47-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11162 00:57:47.184131 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11163 00:57:47.308390 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11164 00:57:47.433007 HTTP request sent, awaiting response... 200 OK
11165 00:57:47.436304 Length: 1647948 (1.6M) [application/octet-stream]
11166 00:57:47.439895 Saving to: 'kselftest_armhf.tar.gz'
11167 00:57:47.439977
11168 00:57:47.440037
11169 00:57:47.682628 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11170 00:57:47.931358 kselftest_armhf.tar 2%[ ] 47.81K 192KB/s
11171 00:57:48.228798 kselftest_armhf.tar 13%[=> ] 217.50K 437KB/s
11172 00:57:48.354852 kselftest_armhf.tar 51%[=========> ] 829.78K 1.02MB/s
11173 00:57:48.361822 kselftest_armhf.tar 100%[===================>] 1.57M 1.71MB/s in 0.9s
11174 00:57:48.361936
11175 00:57:48.513002 2024-06-16 00:57:48 (1.71 MB/s) - 'kselftest_armhf.tar.gz' saved [1647948/1647948]
11176 00:57:48.513169
11177 00:57:53.449159 skiplist:
11178 00:57:53.452089 ========================================
11179 00:57:53.455354 ========================================
11180 00:57:53.504571 rtc:rtctest
11181 00:57:53.526688 ============== Tests to run ===============
11182 00:57:53.526821 rtc:rtctest
11183 00:57:53.533277 ===========End Tests to run ===============
11184 00:57:53.536315 shardfile-rtc pass
11185 00:57:53.650064 <12>[ 26.996881] kselftest: Running tests in rtc
11186 00:57:53.661810 TAP version 13
11187 00:57:53.677325 1..1
11188 00:57:53.711613 # selftests: rtc: rtctest
11189 00:57:54.178281 # TAP version 13
11190 00:57:54.178464 # 1..8
11191 00:57:54.181570 # # Starting 8 tests from 2 test cases.
11192 00:57:54.184398 # # RUN rtc.date_read ...
11193 00:57:54.191341 # # rtctest.c:49:date_read:Current RTC date/time is 16/06/2024 00:57:53.
11194 00:57:54.194543 # # OK rtc.date_read
11195 00:57:54.197926 # ok 1 rtc.date_read
11196 00:57:54.201281 # # RUN rtc.date_read_loop ...
11197 00:57:54.211534 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11198 00:58:04.615349 <6>[ 37.967181] vpu: disabling
11199 00:58:04.618990 <6>[ 37.970288] vproc2: disabling
11200 00:58:04.622480 <6>[ 37.973630] vproc1: disabling
11201 00:58:04.625633 <6>[ 37.976942] vaud18: disabling
11202 00:58:04.632103 <6>[ 37.980454] vsram_others: disabling
11203 00:58:04.635260 <6>[ 37.984413] va09: disabling
11204 00:58:04.639064 <6>[ 37.987704] vsram_md: disabling
11205 00:58:04.641687 <6>[ 37.991274] Vgpu: disabling
11206 00:58:23.965671 # # rtctest.c:115:date_read_loop:Performed 2604 RTC time reads.
11207 00:58:23.969126 # # OK rtc.date_read_loop
11208 00:58:23.972251 # ok 2 rtc.date_read_loop
11209 00:58:23.975902 # # RUN rtc.uie_read ...
11210 00:58:26.948455 # # OK rtc.uie_read
11211 00:58:26.951973 # ok 3 rtc.uie_read
11212 00:58:26.954969 # # RUN rtc.uie_select ...
11213 00:58:29.948260 # # OK rtc.uie_select
11214 00:58:29.951436 # ok 4 rtc.uie_select
11215 00:58:29.954270 # # RUN rtc.alarm_alm_set ...
11216 00:58:29.961097 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 00:58:33.
11217 00:58:29.964516 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11218 00:58:29.971434 # # alarm_alm_set: Test terminated by assertion
11219 00:58:29.974770 # # FAIL rtc.alarm_alm_set
11220 00:58:29.974844 # not ok 5 rtc.alarm_alm_set
11221 00:58:29.981070 # # RUN rtc.alarm_wkalm_set ...
11222 00:58:29.987819 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 16/06/2024 00:58:33.
11223 00:58:32.950857 # # OK rtc.alarm_wkalm_set
11224 00:58:32.951345 # ok 6 rtc.alarm_wkalm_set
11225 00:58:32.957458 # # RUN rtc.alarm_alm_set_minute ...
11226 00:58:32.960850 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 00:59:00.
11227 00:58:32.967877 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11228 00:58:32.974593 # # alarm_alm_set_minute: Test terminated by assertion
11229 00:58:32.977650 # # FAIL rtc.alarm_alm_set_minute
11230 00:58:32.980755 # not ok 7 rtc.alarm_alm_set_minute
11231 00:58:32.984142 # # RUN rtc.alarm_wkalm_set_minute ...
11232 00:58:32.990504 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 16/06/2024 00:59:00.
11233 00:58:59.947553 # # OK rtc.alarm_wkalm_set_minute
11234 00:58:59.951169 # ok 8 rtc.alarm_wkalm_set_minute
11235 00:58:59.951248 # # FAILED: 6 / 8 tests passed.
11236 00:58:59.957534 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11237 00:58:59.960907 not ok 1 selftests: rtc: rtctest # exit=1
11238 00:59:01.474139 rtc_rtctest_rtc_date_read pass
11239 00:59:01.477313 rtc_rtctest_rtc_date_read_loop pass
11240 00:59:01.480268 rtc_rtctest_rtc_uie_read pass
11241 00:59:01.483697 rtc_rtctest_rtc_uie_select pass
11242 00:59:01.487326 rtc_rtctest_rtc_alarm_alm_set fail
11243 00:59:01.490578 rtc_rtctest_rtc_alarm_wkalm_set pass
11244 00:59:01.493578 rtc_rtctest_rtc_alarm_alm_set_minute fail
11245 00:59:01.496807 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11246 00:59:01.500264 rtc_rtctest fail
11247 00:59:01.547616 + ../../utils/send-to-lava.sh ./output/result.txt
11248 00:59:01.621418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11249 00:59:01.621692 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11251 00:59:01.678510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11252 00:59:01.678782 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11254 00:59:01.740818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11255 00:59:01.741097 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11257 00:59:01.788780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11258 00:59:01.789029 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11260 00:59:01.842056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11261 00:59:01.842394 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11263 00:59:01.901380 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11265 00:59:01.904624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11266 00:59:01.960733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11267 00:59:01.961004 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11269 00:59:02.012614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11270 00:59:02.012886 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11272 00:59:02.066729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11273 00:59:02.066999 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11275 00:59:02.119870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11276 00:59:02.119961 + set +x
11277 00:59:02.120212 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11279 00:59:02.126598 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14368562_1.6.2.3.5>
11280 00:59:02.126690 <LAVA_TEST_RUNNER EXIT>
11281 00:59:02.126931 Received signal: <ENDRUN> 1_kselftest-rtc 14368562_1.6.2.3.5
11282 00:59:02.127013 Ending use of test pattern.
11283 00:59:02.127099 Ending test lava.1_kselftest-rtc (14368562_1.6.2.3.5), duration 75.54
11285 00:59:02.127357 ok: lava_test_shell seems to have completed
11286 00:59:02.127507 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11287 00:59:02.127632 end: 3.1 lava-test-shell (duration 00:01:16) [common]
11288 00:59:02.127762 end: 3 lava-test-retry (duration 00:01:16) [common]
11289 00:59:02.127868 start: 4 finalize (timeout 00:06:17) [common]
11290 00:59:02.127951 start: 4.1 power-off (timeout 00:00:30) [common]
11291 00:59:02.128089 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11292 00:59:02.329839 >> Command sent successfully.
11293 00:59:02.332916 Returned 0 in 0 seconds
11294 00:59:02.433279 end: 4.1 power-off (duration 00:00:00) [common]
11296 00:59:02.433592 start: 4.2 read-feedback (timeout 00:06:17) [common]
11297 00:59:02.433822 Listened to connection for namespace 'common' for up to 1s
11298 00:59:02.434089 Listened to connection for namespace 'common' for up to 1s
11299 00:59:03.434058 Finalising connection for namespace 'common'
11300 00:59:03.434212 Disconnecting from shell: Finalise
11301 00:59:03.434280 / #
11302 00:59:03.534529 end: 4.2 read-feedback (duration 00:00:01) [common]
11303 00:59:03.534674 end: 4 finalize (duration 00:00:01) [common]
11304 00:59:03.534785 Cleaning after the job
11305 00:59:03.534885 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/ramdisk
11306 00:59:03.536938 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/kernel
11307 00:59:03.547522 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/dtb
11308 00:59:03.547693 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/nfsrootfs
11309 00:59:03.613154 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368562/tftp-deploy-hnw5p4e_/modules
11310 00:59:03.618914 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368562
11311 00:59:04.162189 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368562
11312 00:59:04.162362 Job finished correctly