Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 00:54:44.600015 lava-dispatcher, installed at version: 2024.03
2 00:54:44.600236 start: 0 validate
3 00:54:44.600354 Start time: 2024-06-16 00:54:44.600347+00:00 (UTC)
4 00:54:44.600484 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:54:44.600703 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:54:44.851946 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:54:44.852181 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:55:08.877208 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:55:08.878051 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:55:09.133363 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:55:09.133960 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:55:09.385883 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:55:09.386502 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:55:12.891160 validate duration: 28.29
16 00:55:12.891414 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:55:12.891512 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:55:12.891600 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:55:12.891744 Not decompressing ramdisk as can be used compressed.
20 00:55:12.891831 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 00:55:12.891894 saving as /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/ramdisk/initrd.cpio.gz
22 00:55:12.891950 total size: 5628169 (5 MB)
23 00:55:12.892965 progress 0 % (0 MB)
24 00:55:12.894532 progress 5 % (0 MB)
25 00:55:12.896054 progress 10 % (0 MB)
26 00:55:12.897450 progress 15 % (0 MB)
27 00:55:12.898974 progress 20 % (1 MB)
28 00:55:12.900338 progress 25 % (1 MB)
29 00:55:12.901895 progress 30 % (1 MB)
30 00:55:12.903388 progress 35 % (1 MB)
31 00:55:12.904753 progress 40 % (2 MB)
32 00:55:12.906289 progress 45 % (2 MB)
33 00:55:12.907640 progress 50 % (2 MB)
34 00:55:12.909165 progress 55 % (2 MB)
35 00:55:12.910653 progress 60 % (3 MB)
36 00:55:12.911980 progress 65 % (3 MB)
37 00:55:12.913482 progress 70 % (3 MB)
38 00:55:12.914816 progress 75 % (4 MB)
39 00:55:12.916305 progress 80 % (4 MB)
40 00:55:12.917674 progress 85 % (4 MB)
41 00:55:12.919162 progress 90 % (4 MB)
42 00:55:12.920819 progress 95 % (5 MB)
43 00:55:12.922166 progress 100 % (5 MB)
44 00:55:12.922377 5 MB downloaded in 0.03 s (176.45 MB/s)
45 00:55:12.922523 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:55:12.922748 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:55:12.922829 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:55:12.922906 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:55:12.923036 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:55:12.923098 saving as /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/kernel/Image
52 00:55:12.923152 total size: 54813184 (52 MB)
53 00:55:12.923206 No compression specified
54 00:55:12.924209 progress 0 % (0 MB)
55 00:55:12.937802 progress 5 % (2 MB)
56 00:55:12.951656 progress 10 % (5 MB)
57 00:55:12.965397 progress 15 % (7 MB)
58 00:55:12.979411 progress 20 % (10 MB)
59 00:55:12.993184 progress 25 % (13 MB)
60 00:55:13.007014 progress 30 % (15 MB)
61 00:55:13.020991 progress 35 % (18 MB)
62 00:55:13.034862 progress 40 % (20 MB)
63 00:55:13.048733 progress 45 % (23 MB)
64 00:55:13.062900 progress 50 % (26 MB)
65 00:55:13.077191 progress 55 % (28 MB)
66 00:55:13.091173 progress 60 % (31 MB)
67 00:55:13.105806 progress 65 % (34 MB)
68 00:55:13.120087 progress 70 % (36 MB)
69 00:55:13.135534 progress 75 % (39 MB)
70 00:55:13.150511 progress 80 % (41 MB)
71 00:55:13.164326 progress 85 % (44 MB)
72 00:55:13.178395 progress 90 % (47 MB)
73 00:55:13.192276 progress 95 % (49 MB)
74 00:55:13.205852 progress 100 % (52 MB)
75 00:55:13.206093 52 MB downloaded in 0.28 s (184.75 MB/s)
76 00:55:13.206243 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:55:13.206456 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:55:13.206540 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:55:13.206618 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:55:13.206750 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:55:13.206813 saving as /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/dtb/mt8192-asurada-spherion-r0.dtb
83 00:55:13.206868 total size: 47258 (0 MB)
84 00:55:13.206922 No compression specified
85 00:55:13.208060 progress 69 % (0 MB)
86 00:55:13.208325 progress 100 % (0 MB)
87 00:55:13.208479 0 MB downloaded in 0.00 s (28.03 MB/s)
88 00:55:13.208595 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:55:13.208814 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:55:13.208894 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:55:13.208973 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:55:13.209080 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 00:55:13.209143 saving as /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/nfsrootfs/full.rootfs.tar
95 00:55:13.209198 total size: 120894716 (115 MB)
96 00:55:13.209254 Using unxz to decompress xz
97 00:55:13.210427 progress 0 % (0 MB)
98 00:55:13.561518 progress 5 % (5 MB)
99 00:55:13.920162 progress 10 % (11 MB)
100 00:55:14.280552 progress 15 % (17 MB)
101 00:55:14.617860 progress 20 % (23 MB)
102 00:55:14.937492 progress 25 % (28 MB)
103 00:55:15.313484 progress 30 % (34 MB)
104 00:55:15.667703 progress 35 % (40 MB)
105 00:55:15.848950 progress 40 % (46 MB)
106 00:55:16.046259 progress 45 % (51 MB)
107 00:55:16.377470 progress 50 % (57 MB)
108 00:55:16.762156 progress 55 % (63 MB)
109 00:55:17.123476 progress 60 % (69 MB)
110 00:55:17.482460 progress 65 % (74 MB)
111 00:55:17.829037 progress 70 % (80 MB)
112 00:55:18.198956 progress 75 % (86 MB)
113 00:55:18.551662 progress 80 % (92 MB)
114 00:55:18.910136 progress 85 % (98 MB)
115 00:55:19.272201 progress 90 % (103 MB)
116 00:55:19.615246 progress 95 % (109 MB)
117 00:55:19.985691 progress 100 % (115 MB)
118 00:55:19.991080 115 MB downloaded in 6.78 s (17.00 MB/s)
119 00:55:19.991242 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:55:19.991489 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:55:19.991570 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:55:19.991646 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:55:19.991775 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:55:19.991837 saving as /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/modules/modules.tar
126 00:55:19.991891 total size: 8617404 (8 MB)
127 00:55:19.991946 Using unxz to decompress xz
128 00:55:19.993306 progress 0 % (0 MB)
129 00:55:20.011893 progress 5 % (0 MB)
130 00:55:20.038116 progress 10 % (0 MB)
131 00:55:20.065511 progress 15 % (1 MB)
132 00:55:20.089120 progress 20 % (1 MB)
133 00:55:20.112136 progress 25 % (2 MB)
134 00:55:20.135412 progress 30 % (2 MB)
135 00:55:20.161278 progress 35 % (2 MB)
136 00:55:20.185868 progress 40 % (3 MB)
137 00:55:20.208654 progress 45 % (3 MB)
138 00:55:20.232422 progress 50 % (4 MB)
139 00:55:20.256698 progress 55 % (4 MB)
140 00:55:20.280431 progress 60 % (4 MB)
141 00:55:20.304492 progress 65 % (5 MB)
142 00:55:20.330592 progress 70 % (5 MB)
143 00:55:20.353814 progress 75 % (6 MB)
144 00:55:20.380347 progress 80 % (6 MB)
145 00:55:20.405108 progress 85 % (7 MB)
146 00:55:20.430783 progress 90 % (7 MB)
147 00:55:20.457711 progress 95 % (7 MB)
148 00:55:20.482918 progress 100 % (8 MB)
149 00:55:20.488989 8 MB downloaded in 0.50 s (16.53 MB/s)
150 00:55:20.489216 end: 1.5.1 http-download (duration 00:00:00) [common]
152 00:55:20.489589 end: 1.5 download-retry (duration 00:00:00) [common]
153 00:55:20.489718 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 00:55:20.489845 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 00:55:24.208732 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368602/extract-nfsrootfs-0wliq_c2
156 00:55:24.208919 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:55:24.209012 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 00:55:24.209182 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo
159 00:55:24.209303 makedir: /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin
160 00:55:24.209396 makedir: /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/tests
161 00:55:24.209486 makedir: /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/results
162 00:55:24.209570 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-add-keys
163 00:55:24.209698 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-add-sources
164 00:55:24.209824 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-background-process-start
165 00:55:24.209944 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-background-process-stop
166 00:55:24.210070 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-common-functions
167 00:55:24.210187 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-echo-ipv4
168 00:55:24.210304 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-install-packages
169 00:55:24.210417 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-installed-packages
170 00:55:24.210531 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-os-build
171 00:55:24.210644 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-probe-channel
172 00:55:24.210757 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-probe-ip
173 00:55:24.210871 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-target-ip
174 00:55:24.210985 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-target-mac
175 00:55:24.211098 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-target-storage
176 00:55:24.211220 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-test-case
177 00:55:24.211335 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-test-event
178 00:55:24.211448 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-test-feedback
179 00:55:24.211562 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-test-raise
180 00:55:24.211674 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-test-reference
181 00:55:24.211787 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-test-runner
182 00:55:24.211900 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-test-set
183 00:55:24.212013 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-test-shell
184 00:55:24.212129 Updating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-add-keys (debian)
185 00:55:24.212275 Updating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-add-sources (debian)
186 00:55:24.212404 Updating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-install-packages (debian)
187 00:55:24.212530 Updating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-installed-packages (debian)
188 00:55:24.212662 Updating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/bin/lava-os-build (debian)
189 00:55:24.212773 Creating /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/environment
190 00:55:24.212859 LAVA metadata
191 00:55:24.212925 - LAVA_JOB_ID=14368602
192 00:55:24.212983 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:55:24.213077 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 00:55:24.213135 skipped lava-vland-overlay
195 00:55:24.213205 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:55:24.213279 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 00:55:24.213334 skipped lava-multinode-overlay
198 00:55:24.213399 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:55:24.213471 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 00:55:24.213547 Loading test definitions
201 00:55:24.213624 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 00:55:24.213685 Using /lava-14368602 at stage 0
203 00:55:24.214007 uuid=14368602_1.6.2.3.1 testdef=None
204 00:55:24.214092 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:55:24.214171 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 00:55:24.214576 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:55:24.214783 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 00:55:24.215301 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:55:24.215516 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 00:55:24.216017 runner path: /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/0/tests/0_timesync-off test_uuid 14368602_1.6.2.3.1
213 00:55:24.216164 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:55:24.216371 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 00:55:24.216437 Using /lava-14368602 at stage 0
217 00:55:24.216529 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:55:24.216611 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/0/tests/1_kselftest-tpm2'
219 00:55:26.874689 Running '/usr/bin/git checkout kernelci.org
220 00:55:27.019869 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 00:55:27.020246 uuid=14368602_1.6.2.3.5 testdef=None
222 00:55:27.020345 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 00:55:27.020540 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 00:55:27.021217 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:55:27.021421 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 00:55:27.022413 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:55:27.022632 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 00:55:27.023475 runner path: /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/0/tests/1_kselftest-tpm2 test_uuid 14368602_1.6.2.3.5
232 00:55:27.023559 BOARD='mt8192-asurada-spherion-r0'
233 00:55:27.023619 BRANCH='cip-gitlab'
234 00:55:27.023672 SKIPFILE='/dev/null'
235 00:55:27.023724 SKIP_INSTALL='True'
236 00:55:27.023772 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:55:27.023823 TST_CASENAME=''
238 00:55:27.023872 TST_CMDFILES='tpm2'
239 00:55:27.024003 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:55:27.024185 Creating lava-test-runner.conf files
242 00:55:27.024240 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368602/lava-overlay-8mffdmgo/lava-14368602/0 for stage 0
243 00:55:27.024323 - 0_timesync-off
244 00:55:27.024382 - 1_kselftest-tpm2
245 00:55:27.024470 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 00:55:27.024547 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 00:55:34.189276 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:55:34.189414 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 00:55:34.189498 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:55:34.189583 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 00:55:34.189665 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 00:55:34.347411 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:55:34.347548 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 00:55:34.347623 extracting modules file /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368602/extract-nfsrootfs-0wliq_c2
255 00:55:34.575561 extracting modules file /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368602/extract-overlay-ramdisk-0ai6amf0/ramdisk
256 00:55:34.809187 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:55:34.809327 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 00:55:34.809404 [common] Applying overlay to NFS
259 00:55:34.809500 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368602/compress-overlay-wb4tvl1g/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368602/extract-nfsrootfs-0wliq_c2
260 00:55:35.640274 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:55:35.640437 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 00:55:35.640523 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:55:35.640606 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 00:55:35.640684 Building ramdisk /var/lib/lava/dispatcher/tmp/14368602/extract-overlay-ramdisk-0ai6amf0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368602/extract-overlay-ramdisk-0ai6amf0/ramdisk
265 00:55:35.967985 >> 130405 blocks
266 00:55:38.099672 rename /var/lib/lava/dispatcher/tmp/14368602/extract-overlay-ramdisk-0ai6amf0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/ramdisk/ramdisk.cpio.gz
267 00:55:38.099850 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:55:38.099938 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 00:55:38.100017 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 00:55:38.100093 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/kernel/Image']
271 00:55:53.336945 Returned 0 in 15 seconds
272 00:55:53.437500 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/kernel/image.itb
273 00:55:53.831210 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:55:53.831356 output: Created: Sun Jun 16 01:55:53 2024
275 00:55:53.831422 output: Image 0 (kernel-1)
276 00:55:53.831481 output: Description:
277 00:55:53.831538 output: Created: Sun Jun 16 01:55:53 2024
278 00:55:53.831597 output: Type: Kernel Image
279 00:55:53.831654 output: Compression: lzma compressed
280 00:55:53.831713 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
281 00:55:53.831770 output: Architecture: AArch64
282 00:55:53.831824 output: OS: Linux
283 00:55:53.831875 output: Load Address: 0x00000000
284 00:55:53.831927 output: Entry Point: 0x00000000
285 00:55:53.831977 output: Hash algo: crc32
286 00:55:53.832026 output: Hash value: f6f06660
287 00:55:53.832076 output: Image 1 (fdt-1)
288 00:55:53.832123 output: Description: mt8192-asurada-spherion-r0
289 00:55:53.832171 output: Created: Sun Jun 16 01:55:53 2024
290 00:55:53.832218 output: Type: Flat Device Tree
291 00:55:53.832269 output: Compression: uncompressed
292 00:55:53.832318 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 00:55:53.832368 output: Architecture: AArch64
294 00:55:53.832415 output: Hash algo: crc32
295 00:55:53.832462 output: Hash value: 0f8e4d2e
296 00:55:53.832510 output: Image 2 (ramdisk-1)
297 00:55:53.832556 output: Description: unavailable
298 00:55:53.832603 output: Created: Sun Jun 16 01:55:53 2024
299 00:55:53.832678 output: Type: RAMDisk Image
300 00:55:53.832742 output: Compression: uncompressed
301 00:55:53.832789 output: Data Size: 18734994 Bytes = 18295.89 KiB = 17.87 MiB
302 00:55:53.832837 output: Architecture: AArch64
303 00:55:53.832884 output: OS: Linux
304 00:55:53.832932 output: Load Address: unavailable
305 00:55:53.832979 output: Entry Point: unavailable
306 00:55:53.833026 output: Hash algo: crc32
307 00:55:53.833073 output: Hash value: 4f558d2e
308 00:55:53.833120 output: Default Configuration: 'conf-1'
309 00:55:53.833167 output: Configuration 0 (conf-1)
310 00:55:53.833214 output: Description: mt8192-asurada-spherion-r0
311 00:55:53.833261 output: Kernel: kernel-1
312 00:55:53.833307 output: Init Ramdisk: ramdisk-1
313 00:55:53.833354 output: FDT: fdt-1
314 00:55:53.833400 output: Loadables: kernel-1
315 00:55:53.833447 output:
316 00:55:53.833585 end: 1.6.8.1 prepare-fit (duration 00:00:16) [common]
317 00:55:53.833672 end: 1.6.8 prepare-kernel (duration 00:00:16) [common]
318 00:55:53.833758 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 00:55:53.833839 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 00:55:53.833904 No LXC device requested
321 00:55:53.833971 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:55:53.834044 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 00:55:53.834112 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:55:53.834174 Checking files for TFTP limit of 4294967296 bytes.
325 00:55:53.834610 end: 1 tftp-deploy (duration 00:00:41) [common]
326 00:55:53.834710 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:55:53.834793 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:55:53.834900 substitutions:
329 00:55:53.834961 - {DTB}: 14368602/tftp-deploy-22_ggd8q/dtb/mt8192-asurada-spherion-r0.dtb
330 00:55:53.835016 - {INITRD}: 14368602/tftp-deploy-22_ggd8q/ramdisk/ramdisk.cpio.gz
331 00:55:53.835067 - {KERNEL}: 14368602/tftp-deploy-22_ggd8q/kernel/Image
332 00:55:53.835117 - {LAVA_MAC}: None
333 00:55:53.835166 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368602/extract-nfsrootfs-0wliq_c2
334 00:55:53.835215 - {NFS_SERVER_IP}: 192.168.201.1
335 00:55:53.835264 - {PRESEED_CONFIG}: None
336 00:55:53.835320 - {PRESEED_LOCAL}: None
337 00:55:53.835369 - {RAMDISK}: 14368602/tftp-deploy-22_ggd8q/ramdisk/ramdisk.cpio.gz
338 00:55:53.835416 - {ROOT_PART}: None
339 00:55:53.835464 - {ROOT}: None
340 00:55:53.835510 - {SERVER_IP}: 192.168.201.1
341 00:55:53.835557 - {TEE}: None
342 00:55:53.835605 Parsed boot commands:
343 00:55:53.835651 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:55:53.835797 Parsed boot commands: tftpboot 192.168.201.1 14368602/tftp-deploy-22_ggd8q/kernel/image.itb 14368602/tftp-deploy-22_ggd8q/kernel/cmdline
345 00:55:53.835878 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:55:53.835953 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:55:53.836033 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:55:53.836108 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:55:53.836171 Not connected, no need to disconnect.
350 00:55:53.836236 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:55:53.836307 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:55:53.836366 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 00:55:53.839465 Setting prompt string to ['lava-test: # ']
354 00:55:53.839785 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:55:53.839885 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:55:53.839994 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:55:53.840103 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:55:53.840279 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-8']
359 00:56:07.617521 Returned 0 in 13 seconds
360 00:56:07.718050 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 00:56:07.718325 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 00:56:07.718421 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 00:56:07.718509 Setting prompt string to 'Starting depthcharge on Spherion...'
365 00:56:07.718575 Changing prompt to 'Starting depthcharge on Spherion...'
366 00:56:07.718639 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 00:56:07.719006 [Enter `^Ec?' for help]
368 00:56:07.719082
369 00:56:07.719146
370 00:56:07.719206 F0: 102B 0000
371 00:56:07.719264
372 00:56:07.719323 F3: 1001 0000 [0200]
373 00:56:07.719383
374 00:56:07.719444 F3: 1001 0000
375 00:56:07.719507
376 00:56:07.719586 F7: 102D 0000
377 00:56:07.719662
378 00:56:07.719736 F1: 0000 0000
379 00:56:07.719810
380 00:56:07.719888 V0: 0000 0000 [0001]
381 00:56:07.719957
382 00:56:07.720047 00: 0007 8000
383 00:56:07.720136
384 00:56:07.720222 01: 0000 0000
385 00:56:07.720312
386 00:56:07.720398 BP: 0C00 0209 [0000]
387 00:56:07.720484
388 00:56:07.720570 G0: 1182 0000
389 00:56:07.720662
390 00:56:07.720749 EC: 0000 0021 [4000]
391 00:56:07.720835
392 00:56:07.720920 S7: 0000 0000 [0000]
393 00:56:07.721006
394 00:56:07.721091 CC: 0000 0000 [0001]
395 00:56:07.721177
396 00:56:07.721262 T0: 0000 0040 [010F]
397 00:56:07.721348
398 00:56:07.721434 Jump to BL
399 00:56:07.721519
400 00:56:07.721604
401 00:56:07.721689
402 00:56:07.721776 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 00:56:07.721865 ARM64: Exception handlers installed.
404 00:56:07.721952 ARM64: Testing exception
405 00:56:07.722037 ARM64: Done test exception
406 00:56:07.722123 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 00:56:07.722211 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 00:56:07.722300 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 00:56:07.722387 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 00:56:07.722473 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 00:56:07.722560 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 00:56:07.722646 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 00:56:07.722733 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 00:56:07.722819 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 00:56:07.722907 WDT: Last reset was cold boot
416 00:56:07.722994 SPI1(PAD0) initialized at 2873684 Hz
417 00:56:07.723081 SPI5(PAD0) initialized at 992727 Hz
418 00:56:07.723167 VBOOT: Loading verstage.
419 00:56:07.723254 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 00:56:07.723340 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 00:56:07.723427 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 00:56:07.723514 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 00:56:07.723601 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 00:56:07.723688 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 00:56:07.723774 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 00:56:07.723860
427 00:56:07.723945
428 00:56:07.724032 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 00:56:07.724120 ARM64: Exception handlers installed.
430 00:56:07.724206 ARM64: Testing exception
431 00:56:07.724292 ARM64: Done test exception
432 00:56:07.724378 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 00:56:07.724465 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 00:56:07.724551 Probing TPM: . done!
435 00:56:07.724638 TPM ready after 0 ms
436 00:56:07.724730 Connected to device vid:did:rid of 1ae0:0028:00
437 00:56:07.724817 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 00:56:07.724904 Initialized TPM device CR50 revision 0
439 00:56:07.724991 tlcl_send_startup: Startup return code is 0
440 00:56:07.725077 TPM: setup succeeded
441 00:56:07.725163 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 00:56:07.725250 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 00:56:07.725337 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 00:56:07.725424 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:56:07.725510 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 00:56:07.725597 in-header: 03 07 00 00 08 00 00 00
447 00:56:07.725683 in-data: aa e4 47 04 13 02 00 00
448 00:56:07.725769 Chrome EC: UHEPI supported
449 00:56:07.725856 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 00:56:07.725943 in-header: 03 a9 00 00 08 00 00 00
451 00:56:07.726030 in-data: 84 60 60 08 00 00 00 00
452 00:56:07.726116 Phase 1
453 00:56:07.726202 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 00:56:07.726289 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 00:56:07.726375 VB2:vb2_check_recovery() Recovery was requested manually
456 00:56:07.726462 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 00:56:07.726549 Recovery requested (1009000e)
458 00:56:07.726635 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 00:56:07.726722 tlcl_extend: response is 0
460 00:56:07.726809 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 00:56:07.726895 tlcl_extend: response is 0
462 00:56:07.726982 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 00:56:07.727069 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 00:56:07.727156 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 00:56:07.727242
466 00:56:07.727328
467 00:56:07.727414 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 00:56:07.727501 ARM64: Exception handlers installed.
469 00:56:07.727587 ARM64: Testing exception
470 00:56:07.727673 ARM64: Done test exception
471 00:56:07.727759 pmic_efuse_setting: Set efuses in 11 msecs
472 00:56:07.727845 pmwrap_interface_init: Select PMIF_VLD_RDY
473 00:56:07.727931 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 00:56:07.728018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 00:56:07.728301 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 00:56:07.728387 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 00:56:07.728474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 00:56:07.728561 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 00:56:07.728653 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 00:56:07.728740 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 00:56:07.728826 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 00:56:07.728912 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 00:56:07.728998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 00:56:07.729084 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 00:56:07.729171 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 00:56:07.729258 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 00:56:07.729344 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 00:56:07.729431 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 00:56:07.729517 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 00:56:07.729603 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 00:56:07.729689 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 00:56:07.729775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 00:56:07.729862 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 00:56:07.729948 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 00:56:07.730034 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 00:56:07.730119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 00:56:07.730205 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 00:56:07.730292 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 00:56:07.730379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 00:56:07.730467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 00:56:07.730553 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 00:56:07.730639 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 00:56:07.730725 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 00:56:07.730811 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 00:56:07.730897 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 00:56:07.730983 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 00:56:07.731069 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 00:56:07.731156 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 00:56:07.731241 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 00:56:07.731331 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 00:56:07.731417 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 00:56:07.731497 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 00:56:07.731577 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 00:56:07.731656 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 00:56:07.731735 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 00:56:07.731814 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 00:56:07.731893 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 00:56:07.731971 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 00:56:07.732050 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 00:56:07.732129 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 00:56:07.732208 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 00:56:07.732286 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 00:56:07.732365 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 00:56:07.732446 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 00:56:07.732528 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 00:56:07.732608 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 00:56:07.732697 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 00:56:07.732779 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 00:56:07.732858 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 00:56:07.732937 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 00:56:07.733017 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:56:07.733096 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x5
533 00:56:07.733176 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 00:56:07.733255 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
535 00:56:07.733334 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 00:56:07.733413 [RTC]rtc_get_frequency_meter,154: input=15, output=794
537 00:56:07.733492 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
538 00:56:07.733571 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
539 00:56:07.733650 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
540 00:56:07.733728 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
541 00:56:07.733809 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
542 00:56:07.733880 ADC[4]: Raw value=896300 ID=7
543 00:56:07.733948 ADC[3]: Raw value=213440 ID=1
544 00:56:07.734017 RAM Code: 0x71
545 00:56:07.734084 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
546 00:56:07.734152 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
547 00:56:07.734413 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
548 00:56:07.734503 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
549 00:56:07.734591 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
550 00:56:07.734679 in-header: 03 07 00 00 08 00 00 00
551 00:56:07.734766 in-data: aa e4 47 04 13 02 00 00
552 00:56:07.734852 Chrome EC: UHEPI supported
553 00:56:07.734938 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
554 00:56:07.735025 in-header: 03 a9 00 00 08 00 00 00
555 00:56:07.735112 in-data: 84 60 60 08 00 00 00 00
556 00:56:07.735197 MRC: failed to locate region type 0.
557 00:56:07.735283 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
558 00:56:07.735369 DRAM-K: Running full calibration
559 00:56:07.735456 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
560 00:56:07.735542 header.status = 0x0
561 00:56:07.735628 header.version = 0x6 (expected: 0x6)
562 00:56:07.735713 header.size = 0xd00 (expected: 0xd00)
563 00:56:07.735799 header.flags = 0x0
564 00:56:07.735885 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
565 00:56:07.735971 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
566 00:56:07.736057 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
567 00:56:07.736143 dram_init: ddr_geometry: 2
568 00:56:07.736228 [EMI] MDL number = 2
569 00:56:07.736314 [EMI] Get MDL freq = 0
570 00:56:07.736399 dram_init: ddr_type: 0
571 00:56:07.736485 is_discrete_lpddr4: 1
572 00:56:07.736570 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
573 00:56:07.736662
574 00:56:07.736749
575 00:56:07.736835 [Bian_co] ETT version 0.0.0.1
576 00:56:07.736921 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
577 00:56:07.737007
578 00:56:07.737092 dramc_set_vcore_voltage set vcore to 650000
579 00:56:07.737179 Read voltage for 800, 4
580 00:56:07.737264 Vio18 = 0
581 00:56:07.737349 Vcore = 650000
582 00:56:07.737435 Vdram = 0
583 00:56:07.737521 Vddq = 0
584 00:56:07.737607 Vmddr = 0
585 00:56:07.737692 dram_init: config_dvfs: 1
586 00:56:07.737778 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
587 00:56:07.737865 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
588 00:56:07.737951 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
589 00:56:07.738037 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
590 00:56:07.738129 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
591 00:56:07.738215 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
592 00:56:07.738303 MEM_TYPE=3, freq_sel=18
593 00:56:07.738388 sv_algorithm_assistance_LP4_1600
594 00:56:07.738474 ============ PULL DRAM RESETB DOWN ============
595 00:56:07.738562 ========== PULL DRAM RESETB DOWN end =========
596 00:56:07.738649 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
597 00:56:07.738736 ===================================
598 00:56:07.738823 LPDDR4 DRAM CONFIGURATION
599 00:56:07.738909 ===================================
600 00:56:07.738995 EX_ROW_EN[0] = 0x0
601 00:56:07.739081 EX_ROW_EN[1] = 0x0
602 00:56:07.739167 LP4Y_EN = 0x0
603 00:56:07.739252 WORK_FSP = 0x0
604 00:56:07.739338 WL = 0x2
605 00:56:07.739423 RL = 0x2
606 00:56:07.739509 BL = 0x2
607 00:56:07.739594 RPST = 0x0
608 00:56:07.739680 RD_PRE = 0x0
609 00:56:07.739766 WR_PRE = 0x1
610 00:56:07.739854 WR_PST = 0x0
611 00:56:07.739941 DBI_WR = 0x0
612 00:56:07.740027 DBI_RD = 0x0
613 00:56:07.740116 OTF = 0x1
614 00:56:07.740210 ===================================
615 00:56:07.740304 ===================================
616 00:56:07.740382 ANA top config
617 00:56:07.740460 ===================================
618 00:56:07.740537 DLL_ASYNC_EN = 0
619 00:56:07.740613 ALL_SLAVE_EN = 1
620 00:56:07.740731 NEW_RANK_MODE = 1
621 00:56:07.740809 DLL_IDLE_MODE = 1
622 00:56:07.740886 LP45_APHY_COMB_EN = 1
623 00:56:07.740962 TX_ODT_DIS = 1
624 00:56:07.741038 NEW_8X_MODE = 1
625 00:56:07.741116 ===================================
626 00:56:07.741193 ===================================
627 00:56:07.741270 data_rate = 1600
628 00:56:07.741349 CKR = 1
629 00:56:07.741432 DQ_P2S_RATIO = 8
630 00:56:07.741517 ===================================
631 00:56:07.741602 CA_P2S_RATIO = 8
632 00:56:07.741686 DQ_CA_OPEN = 0
633 00:56:07.741770 DQ_SEMI_OPEN = 0
634 00:56:07.741855 CA_SEMI_OPEN = 0
635 00:56:07.741939 CA_FULL_RATE = 0
636 00:56:07.742023 DQ_CKDIV4_EN = 1
637 00:56:07.742106 CA_CKDIV4_EN = 1
638 00:56:07.742190 CA_PREDIV_EN = 0
639 00:56:07.742291 PH8_DLY = 0
640 00:56:07.742378 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
641 00:56:07.742463 DQ_AAMCK_DIV = 4
642 00:56:07.742563 CA_AAMCK_DIV = 4
643 00:56:07.742646 CA_ADMCK_DIV = 4
644 00:56:07.742730 DQ_TRACK_CA_EN = 0
645 00:56:07.742814 CA_PICK = 800
646 00:56:07.742898 CA_MCKIO = 800
647 00:56:07.742982 MCKIO_SEMI = 0
648 00:56:07.743065 PLL_FREQ = 3068
649 00:56:07.743149 DQ_UI_PI_RATIO = 32
650 00:56:07.743233 CA_UI_PI_RATIO = 0
651 00:56:07.743316 ===================================
652 00:56:07.743400 ===================================
653 00:56:07.743485 memory_type:LPDDR4
654 00:56:07.743568 GP_NUM : 10
655 00:56:07.743651 SRAM_EN : 1
656 00:56:07.743735 MD32_EN : 0
657 00:56:07.743819 ===================================
658 00:56:07.743903 [ANA_INIT] >>>>>>>>>>>>>>
659 00:56:07.743987 <<<<<< [CONFIGURE PHASE]: ANA_TX
660 00:56:07.744074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
661 00:56:07.744176 ===================================
662 00:56:07.744276 data_rate = 1600,PCW = 0X7600
663 00:56:07.744360 ===================================
664 00:56:07.744444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
665 00:56:07.744528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
666 00:56:07.744612 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 00:56:07.744960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
668 00:56:07.745046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
669 00:56:07.745134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
670 00:56:07.745222 [ANA_INIT] flow start
671 00:56:07.745308 [ANA_INIT] PLL >>>>>>>>
672 00:56:07.745395 [ANA_INIT] PLL <<<<<<<<
673 00:56:07.745481 [ANA_INIT] MIDPI >>>>>>>>
674 00:56:07.745567 [ANA_INIT] MIDPI <<<<<<<<
675 00:56:07.745653 [ANA_INIT] DLL >>>>>>>>
676 00:56:07.745740 [ANA_INIT] flow end
677 00:56:07.745826 ============ LP4 DIFF to SE enter ============
678 00:56:07.745912 ============ LP4 DIFF to SE exit ============
679 00:56:07.745999 [ANA_INIT] <<<<<<<<<<<<<
680 00:56:07.746099 [Flow] Enable top DCM control >>>>>
681 00:56:07.746184 [Flow] Enable top DCM control <<<<<
682 00:56:07.746268 Enable DLL master slave shuffle
683 00:56:07.746353 ==============================================================
684 00:56:07.746438 Gating Mode config
685 00:56:07.746522 ==============================================================
686 00:56:07.746606 Config description:
687 00:56:07.746691 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
688 00:56:07.746776 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
689 00:56:07.746861 SELPH_MODE 0: By rank 1: By Phase
690 00:56:07.746946 ==============================================================
691 00:56:07.747030 GAT_TRACK_EN = 1
692 00:56:07.747115 RX_GATING_MODE = 2
693 00:56:07.747198 RX_GATING_TRACK_MODE = 2
694 00:56:07.747282 SELPH_MODE = 1
695 00:56:07.747367 PICG_EARLY_EN = 1
696 00:56:07.747451 VALID_LAT_VALUE = 1
697 00:56:07.747534 ==============================================================
698 00:56:07.747619 Enter into Gating configuration >>>>
699 00:56:07.747703 Exit from Gating configuration <<<<
700 00:56:07.747787 Enter into DVFS_PRE_config >>>>>
701 00:56:07.747872 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
702 00:56:07.747960 Exit from DVFS_PRE_config <<<<<
703 00:56:07.748062 Enter into PICG configuration >>>>
704 00:56:07.748161 Exit from PICG configuration <<<<
705 00:56:07.748245 [RX_INPUT] configuration >>>>>
706 00:56:07.748329 [RX_INPUT] configuration <<<<<
707 00:56:07.748413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
708 00:56:07.748497 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
709 00:56:07.748582 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
710 00:56:07.748706 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
711 00:56:07.748791 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
712 00:56:07.748875 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
713 00:56:07.748960 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
714 00:56:07.749044 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
715 00:56:07.749128 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
716 00:56:07.749213 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
717 00:56:07.749296 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
718 00:56:07.749380 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
719 00:56:07.749482 ===================================
720 00:56:07.749581 LPDDR4 DRAM CONFIGURATION
721 00:56:07.749665 ===================================
722 00:56:07.749749 EX_ROW_EN[0] = 0x0
723 00:56:07.749833 EX_ROW_EN[1] = 0x0
724 00:56:07.749917 LP4Y_EN = 0x0
725 00:56:07.750050 WORK_FSP = 0x0
726 00:56:07.750185 WL = 0x2
727 00:56:07.750268 RL = 0x2
728 00:56:07.750352 BL = 0x2
729 00:56:07.750436 RPST = 0x0
730 00:56:07.750519 RD_PRE = 0x0
731 00:56:07.750603 WR_PRE = 0x1
732 00:56:07.750686 WR_PST = 0x0
733 00:56:07.750769 DBI_WR = 0x0
734 00:56:07.750852 DBI_RD = 0x0
735 00:56:07.750936 OTF = 0x1
736 00:56:07.751020 ===================================
737 00:56:07.751105 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
738 00:56:07.751189 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
739 00:56:07.751273 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
740 00:56:07.751389 ===================================
741 00:56:07.751474 LPDDR4 DRAM CONFIGURATION
742 00:56:07.751558 ===================================
743 00:56:07.751642 EX_ROW_EN[0] = 0x10
744 00:56:07.751726 EX_ROW_EN[1] = 0x0
745 00:56:07.751810 LP4Y_EN = 0x0
746 00:56:07.751893 WORK_FSP = 0x0
747 00:56:07.751976 WL = 0x2
748 00:56:07.752060 RL = 0x2
749 00:56:07.752144 BL = 0x2
750 00:56:07.752227 RPST = 0x0
751 00:56:07.752311 RD_PRE = 0x0
752 00:56:07.752396 WR_PRE = 0x1
753 00:56:07.752479 WR_PST = 0x0
754 00:56:07.752564 DBI_WR = 0x0
755 00:56:07.752651 DBI_RD = 0x0
756 00:56:07.752770 OTF = 0x1
757 00:56:07.752855 ===================================
758 00:56:07.752940 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
759 00:56:07.753025 nWR fixed to 40
760 00:56:07.753110 [ModeRegInit_LP4] CH0 RK0
761 00:56:07.753194 [ModeRegInit_LP4] CH0 RK1
762 00:56:07.753278 [ModeRegInit_LP4] CH1 RK0
763 00:56:07.753362 [ModeRegInit_LP4] CH1 RK1
764 00:56:07.753446 match AC timing 13
765 00:56:07.753530 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
766 00:56:07.753615 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
767 00:56:07.753703 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
768 00:56:07.753792 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
769 00:56:07.753875 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
770 00:56:07.753952 [EMI DOE] emi_dcm 0
771 00:56:07.754047 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
772 00:56:07.754125 ==
773 00:56:07.754204 Dram Type= 6, Freq= 0, CH_0, rank 0
774 00:56:07.754297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 00:56:07.754373 ==
776 00:56:07.754666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
777 00:56:07.754764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
778 00:56:07.754842 [CA 0] Center 38 (7~69) winsize 63
779 00:56:07.754919 [CA 1] Center 37 (7~68) winsize 62
780 00:56:07.754996 [CA 2] Center 35 (5~66) winsize 62
781 00:56:07.755091 [CA 3] Center 35 (5~66) winsize 62
782 00:56:07.755185 [CA 4] Center 34 (4~65) winsize 62
783 00:56:07.755269 [CA 5] Center 33 (3~64) winsize 62
784 00:56:07.755354
785 00:56:07.755439 [CmdBusTrainingLP45] Vref(ca) range 1: 34
786 00:56:07.755523
787 00:56:07.755608 [CATrainingPosCal] consider 1 rank data
788 00:56:07.755730 u2DelayCellTimex100 = 270/100 ps
789 00:56:07.755814 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
790 00:56:07.755899 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
791 00:56:07.755983 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
792 00:56:07.756067 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
793 00:56:07.756192 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
794 00:56:07.756276 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
795 00:56:07.756360
796 00:56:07.756444 CA PerBit enable=1, Macro0, CA PI delay=33
797 00:56:07.756528
798 00:56:07.756612 [CBTSetCACLKResult] CA Dly = 33
799 00:56:07.756734 CS Dly: 6 (0~37)
800 00:56:07.756820 ==
801 00:56:07.756905 Dram Type= 6, Freq= 0, CH_0, rank 1
802 00:56:07.756989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
803 00:56:07.757074 ==
804 00:56:07.757158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
805 00:56:07.757243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
806 00:56:07.757327 [CA 0] Center 38 (7~69) winsize 63
807 00:56:07.757412 [CA 1] Center 37 (7~68) winsize 62
808 00:56:07.757496 [CA 2] Center 35 (5~66) winsize 62
809 00:56:07.757580 [CA 3] Center 35 (5~66) winsize 62
810 00:56:07.757663 [CA 4] Center 34 (4~65) winsize 62
811 00:56:07.757747 [CA 5] Center 34 (4~65) winsize 62
812 00:56:07.757831
813 00:56:07.757946 [CmdBusTrainingLP45] Vref(ca) range 1: 30
814 00:56:07.758048
815 00:56:07.758146 [CATrainingPosCal] consider 2 rank data
816 00:56:07.758230 u2DelayCellTimex100 = 270/100 ps
817 00:56:07.758314 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
818 00:56:07.758398 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
819 00:56:07.758482 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
820 00:56:07.758565 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
821 00:56:07.758649 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
822 00:56:07.758733 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
823 00:56:07.758816
824 00:56:07.758900 CA PerBit enable=1, Macro0, CA PI delay=34
825 00:56:07.758983
826 00:56:07.759067 [CBTSetCACLKResult] CA Dly = 34
827 00:56:07.759152 CS Dly: 6 (0~38)
828 00:56:07.759235
829 00:56:07.759319 ----->DramcWriteLeveling(PI) begin...
830 00:56:07.759404 ==
831 00:56:07.759488 Dram Type= 6, Freq= 0, CH_0, rank 0
832 00:56:07.759572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
833 00:56:07.759656 ==
834 00:56:07.759740 Write leveling (Byte 0): 30 => 30
835 00:56:07.759825 Write leveling (Byte 1): 29 => 29
836 00:56:07.759910 DramcWriteLeveling(PI) end<-----
837 00:56:07.759994
838 00:56:07.760078 ==
839 00:56:07.760162 Dram Type= 6, Freq= 0, CH_0, rank 0
840 00:56:07.760246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 00:56:07.760330 ==
842 00:56:07.760414 [Gating] SW mode calibration
843 00:56:07.760499 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
844 00:56:07.760584 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
845 00:56:07.760697 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
846 00:56:07.760797 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 00:56:07.760882 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
848 00:56:07.760966 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 00:56:07.761051 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 00:56:07.761135 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 00:56:07.761219 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 00:56:07.761303 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 00:56:07.761387 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 00:56:07.761471 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:56:07.761555 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:56:07.761639 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:56:07.761723 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:56:07.761840 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:56:07.761957 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:56:07.762041 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:56:07.762156 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:56:07.762291 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:56:07.762421 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
864 00:56:07.762505 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:56:07.762589 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:56:07.762704 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:56:07.762788 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:56:07.762871 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 00:56:07.762956 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 00:56:07.763041 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 00:56:07.763125 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:56:07.763209 0 9 12 | B1->B0 | 2c2c 2f2f | 0 1 | (0 0) (1 1)
873 00:56:07.763293 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
874 00:56:07.763377 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 00:56:07.763461 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 00:56:07.763545 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 00:56:07.763630 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 00:56:07.763714 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
879 00:56:07.763798 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
880 00:56:07.763882 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
881 00:56:07.763966 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
882 00:56:07.764256 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 00:56:07.764414 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 00:56:07.764517 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 00:56:07.764604 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 00:56:07.764698 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 00:56:07.764785 0 11 8 | B1->B0 | 2626 3030 | 0 0 | (0 0) (1 1)
888 00:56:07.764872 0 11 12 | B1->B0 | 3333 4343 | 1 0 | (0 0) (0 0)
889 00:56:07.764958 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 00:56:07.765044 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 00:56:07.765131 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 00:56:07.765217 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 00:56:07.765315 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 00:56:07.765400 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 00:56:07.765484 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
896 00:56:07.765569 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
897 00:56:07.765654 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 00:56:07.765738 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 00:56:07.765822 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 00:56:07.765905 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 00:56:07.766010 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 00:56:07.766142 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:56:07.766226 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:56:07.766342 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:56:07.766445 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:56:07.766531 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:56:07.766630 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:56:07.766746 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:56:07.766830 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:56:07.766914 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:56:07.766998 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
912 00:56:07.767082 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
913 00:56:07.767165 Total UI for P1: 0, mck2ui 16
914 00:56:07.767250 best dqsien dly found for B0: ( 0, 14, 8)
915 00:56:07.767334 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
916 00:56:07.767417 Total UI for P1: 0, mck2ui 16
917 00:56:07.767502 best dqsien dly found for B1: ( 0, 14, 12)
918 00:56:07.767615 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
919 00:56:07.767700 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
920 00:56:07.767784
921 00:56:07.767868 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
922 00:56:07.767953 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
923 00:56:07.768037 [Gating] SW calibration Done
924 00:56:07.768120 ==
925 00:56:07.768234 Dram Type= 6, Freq= 0, CH_0, rank 0
926 00:56:07.768319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 00:56:07.768403 ==
928 00:56:07.768488 RX Vref Scan: 0
929 00:56:07.768571
930 00:56:07.768692 RX Vref 0 -> 0, step: 1
931 00:56:07.768776
932 00:56:07.768860 RX Delay -130 -> 252, step: 16
933 00:56:07.768945 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
934 00:56:07.769030 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
935 00:56:07.769114 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
936 00:56:07.769198 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
937 00:56:07.769287 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
938 00:56:07.769368 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
939 00:56:07.769445 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
940 00:56:07.769557 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
941 00:56:07.769634 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
942 00:56:07.769710 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
943 00:56:07.769787 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
944 00:56:07.769864 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
945 00:56:07.769941 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
946 00:56:07.770037 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
947 00:56:07.770169 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
948 00:56:07.770253 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
949 00:56:07.770337 ==
950 00:56:07.770422 Dram Type= 6, Freq= 0, CH_0, rank 0
951 00:56:07.770506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
952 00:56:07.770591 ==
953 00:56:07.770675 DQS Delay:
954 00:56:07.770759 DQS0 = 0, DQS1 = 0
955 00:56:07.770843 DQM Delay:
956 00:56:07.770927 DQM0 = 81, DQM1 = 69
957 00:56:07.771011 DQ Delay:
958 00:56:07.771095 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
959 00:56:07.771179 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
960 00:56:07.771263 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
961 00:56:07.771347 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
962 00:56:07.771431
963 00:56:07.771514
964 00:56:07.771598 ==
965 00:56:07.771682 Dram Type= 6, Freq= 0, CH_0, rank 0
966 00:56:07.771766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 00:56:07.771851 ==
968 00:56:07.771935
969 00:56:07.772018
970 00:56:07.772101 TX Vref Scan disable
971 00:56:07.772186 == TX Byte 0 ==
972 00:56:07.772269 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
973 00:56:07.772353 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
974 00:56:07.772474 == TX Byte 1 ==
975 00:56:07.772559 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
976 00:56:07.772646 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
977 00:56:07.772763 ==
978 00:56:07.772848 Dram Type= 6, Freq= 0, CH_0, rank 0
979 00:56:07.772932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 00:56:07.773016 ==
981 00:56:07.773101 TX Vref=22, minBit 5, minWin=26, winSum=435
982 00:56:07.773185 TX Vref=24, minBit 11, minWin=26, winSum=437
983 00:56:07.773270 TX Vref=26, minBit 7, minWin=27, winSum=444
984 00:56:07.773354 TX Vref=28, minBit 14, minWin=26, winSum=442
985 00:56:07.773439 TX Vref=30, minBit 2, minWin=27, winSum=442
986 00:56:07.773523 TX Vref=32, minBit 2, minWin=27, winSum=441
987 00:56:07.773647 [TxChooseVref] Worse bit 7, Min win 27, Win sum 444, Final Vref 26
988 00:56:07.773730
989 00:56:07.773815 Final TX Range 1 Vref 26
990 00:56:07.773899
991 00:56:07.773982 ==
992 00:56:07.774066 Dram Type= 6, Freq= 0, CH_0, rank 0
993 00:56:07.774408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
994 00:56:07.774557 ==
995 00:56:07.774675
996 00:56:07.774761
997 00:56:07.774847 TX Vref Scan disable
998 00:56:07.774932 == TX Byte 0 ==
999 00:56:07.775019 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1000 00:56:07.775118 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1001 00:56:07.775202 == TX Byte 1 ==
1002 00:56:07.775315 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1003 00:56:07.775447 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1004 00:56:07.775565
1005 00:56:07.775651 [DATLAT]
1006 00:56:07.775736 Freq=800, CH0 RK0
1007 00:56:07.775884
1008 00:56:07.775970 DATLAT Default: 0xa
1009 00:56:07.776056 0, 0xFFFF, sum = 0
1010 00:56:07.776145 1, 0xFFFF, sum = 0
1011 00:56:07.776233 2, 0xFFFF, sum = 0
1012 00:56:07.776322 3, 0xFFFF, sum = 0
1013 00:56:07.776409 4, 0xFFFF, sum = 0
1014 00:56:07.776497 5, 0xFFFF, sum = 0
1015 00:56:07.776584 6, 0xFFFF, sum = 0
1016 00:56:07.776695 7, 0xFFFF, sum = 0
1017 00:56:07.776783 8, 0xFFFF, sum = 0
1018 00:56:07.776870 9, 0x0, sum = 1
1019 00:56:07.776956 10, 0x0, sum = 2
1020 00:56:07.777042 11, 0x0, sum = 3
1021 00:56:07.777128 12, 0x0, sum = 4
1022 00:56:07.777217 best_step = 10
1023 00:56:07.777301
1024 00:56:07.777384 ==
1025 00:56:07.777468 Dram Type= 6, Freq= 0, CH_0, rank 0
1026 00:56:07.777552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1027 00:56:07.777636 ==
1028 00:56:07.777721 RX Vref Scan: 1
1029 00:56:07.777804
1030 00:56:07.777888 Set Vref Range= 32 -> 127
1031 00:56:07.777972
1032 00:56:07.778056 RX Vref 32 -> 127, step: 1
1033 00:56:07.778140
1034 00:56:07.778224 RX Delay -111 -> 252, step: 8
1035 00:56:07.778308
1036 00:56:07.778424 Set Vref, RX VrefLevel [Byte0]: 32
1037 00:56:07.778539 [Byte1]: 32
1038 00:56:07.778624
1039 00:56:07.778708 Set Vref, RX VrefLevel [Byte0]: 33
1040 00:56:07.778793 [Byte1]: 33
1041 00:56:07.778876
1042 00:56:07.778960 Set Vref, RX VrefLevel [Byte0]: 34
1043 00:56:07.779044 [Byte1]: 34
1044 00:56:07.779127
1045 00:56:07.779210 Set Vref, RX VrefLevel [Byte0]: 35
1046 00:56:07.779295 [Byte1]: 35
1047 00:56:07.779378
1048 00:56:07.779462 Set Vref, RX VrefLevel [Byte0]: 36
1049 00:56:07.779578 [Byte1]: 36
1050 00:56:07.779662
1051 00:56:07.779745 Set Vref, RX VrefLevel [Byte0]: 37
1052 00:56:07.779829 [Byte1]: 37
1053 00:56:07.779913
1054 00:56:07.779996 Set Vref, RX VrefLevel [Byte0]: 38
1055 00:56:07.780079 [Byte1]: 38
1056 00:56:07.780162
1057 00:56:07.780245 Set Vref, RX VrefLevel [Byte0]: 39
1058 00:56:07.780328 [Byte1]: 39
1059 00:56:07.780412
1060 00:56:07.780495 Set Vref, RX VrefLevel [Byte0]: 40
1061 00:56:07.780578 [Byte1]: 40
1062 00:56:07.780685
1063 00:56:07.780783 Set Vref, RX VrefLevel [Byte0]: 41
1064 00:56:07.780868 [Byte1]: 41
1065 00:56:07.780952
1066 00:56:07.781035 Set Vref, RX VrefLevel [Byte0]: 42
1067 00:56:07.781119 [Byte1]: 42
1068 00:56:07.781202
1069 00:56:07.781290 Set Vref, RX VrefLevel [Byte0]: 43
1070 00:56:07.781375 [Byte1]: 43
1071 00:56:07.781458
1072 00:56:07.781541 Set Vref, RX VrefLevel [Byte0]: 44
1073 00:56:07.781626 [Byte1]: 44
1074 00:56:07.781709
1075 00:56:07.781793 Set Vref, RX VrefLevel [Byte0]: 45
1076 00:56:07.781877 [Byte1]: 45
1077 00:56:07.781960
1078 00:56:07.782044 Set Vref, RX VrefLevel [Byte0]: 46
1079 00:56:07.782128 [Byte1]: 46
1080 00:56:07.782211
1081 00:56:07.782359 Set Vref, RX VrefLevel [Byte0]: 47
1082 00:56:07.782443 [Byte1]: 47
1083 00:56:07.782527
1084 00:56:07.782610 Set Vref, RX VrefLevel [Byte0]: 48
1085 00:56:07.782694 [Byte1]: 48
1086 00:56:07.782777
1087 00:56:07.782862 Set Vref, RX VrefLevel [Byte0]: 49
1088 00:56:07.782946 [Byte1]: 49
1089 00:56:07.783030
1090 00:56:07.783114 Set Vref, RX VrefLevel [Byte0]: 50
1091 00:56:07.783198 [Byte1]: 50
1092 00:56:07.783281
1093 00:56:07.783365 Set Vref, RX VrefLevel [Byte0]: 51
1094 00:56:07.783449 [Byte1]: 51
1095 00:56:07.783533
1096 00:56:07.783616 Set Vref, RX VrefLevel [Byte0]: 52
1097 00:56:07.783700 [Byte1]: 52
1098 00:56:07.783831
1099 00:56:07.783929 Set Vref, RX VrefLevel [Byte0]: 53
1100 00:56:07.784013 [Byte1]: 53
1101 00:56:07.784116
1102 00:56:07.784260 Set Vref, RX VrefLevel [Byte0]: 54
1103 00:56:07.784360 [Byte1]: 54
1104 00:56:07.784444
1105 00:56:07.784528 Set Vref, RX VrefLevel [Byte0]: 55
1106 00:56:07.784613 [Byte1]: 55
1107 00:56:07.784732
1108 00:56:07.784816 Set Vref, RX VrefLevel [Byte0]: 56
1109 00:56:07.784901 [Byte1]: 56
1110 00:56:07.784985
1111 00:56:07.785068 Set Vref, RX VrefLevel [Byte0]: 57
1112 00:56:07.785152 [Byte1]: 57
1113 00:56:07.785235
1114 00:56:07.785318 Set Vref, RX VrefLevel [Byte0]: 58
1115 00:56:07.785403 [Byte1]: 58
1116 00:56:07.785487
1117 00:56:07.785605 Set Vref, RX VrefLevel [Byte0]: 59
1118 00:56:07.785690 [Byte1]: 59
1119 00:56:07.785775
1120 00:56:07.785858 Set Vref, RX VrefLevel [Byte0]: 60
1121 00:56:07.785943 [Byte1]: 60
1122 00:56:07.786026
1123 00:56:07.786110 Set Vref, RX VrefLevel [Byte0]: 61
1124 00:56:07.786194 [Byte1]: 61
1125 00:56:07.786278
1126 00:56:07.786361 Set Vref, RX VrefLevel [Byte0]: 62
1127 00:56:07.786477 [Byte1]: 62
1128 00:56:07.786592
1129 00:56:07.786676 Set Vref, RX VrefLevel [Byte0]: 63
1130 00:56:07.786760 [Byte1]: 63
1131 00:56:07.786844
1132 00:56:07.786927 Set Vref, RX VrefLevel [Byte0]: 64
1133 00:56:07.787011 [Byte1]: 64
1134 00:56:07.787095
1135 00:56:07.787179 Set Vref, RX VrefLevel [Byte0]: 65
1136 00:56:07.787299 [Byte1]: 65
1137 00:56:07.787383
1138 00:56:07.787466 Set Vref, RX VrefLevel [Byte0]: 66
1139 00:56:07.787551 [Byte1]: 66
1140 00:56:07.787634
1141 00:56:07.787718 Set Vref, RX VrefLevel [Byte0]: 67
1142 00:56:07.787802 [Byte1]: 67
1143 00:56:07.787885
1144 00:56:07.787968 Set Vref, RX VrefLevel [Byte0]: 68
1145 00:56:07.788052 [Byte1]: 68
1146 00:56:07.788135
1147 00:56:07.788218 Set Vref, RX VrefLevel [Byte0]: 69
1148 00:56:07.788302 [Byte1]: 69
1149 00:56:07.788386
1150 00:56:07.788469 Set Vref, RX VrefLevel [Byte0]: 70
1151 00:56:07.788553 [Byte1]: 70
1152 00:56:07.788636
1153 00:56:07.788756 Set Vref, RX VrefLevel [Byte0]: 71
1154 00:56:07.788840 [Byte1]: 71
1155 00:56:07.788924
1156 00:56:07.789008 Set Vref, RX VrefLevel [Byte0]: 72
1157 00:56:07.789092 [Byte1]: 72
1158 00:56:07.789176
1159 00:56:07.789260 Set Vref, RX VrefLevel [Byte0]: 73
1160 00:56:07.789344 [Byte1]: 73
1161 00:56:07.789427
1162 00:56:07.789511 Set Vref, RX VrefLevel [Byte0]: 74
1163 00:56:07.789594 [Byte1]: 74
1164 00:56:07.789678
1165 00:56:07.789958 Set Vref, RX VrefLevel [Byte0]: 75
1166 00:56:07.790098 [Byte1]: 75
1167 00:56:07.790185
1168 00:56:07.790271 Set Vref, RX VrefLevel [Byte0]: 76
1169 00:56:07.790358 [Byte1]: 76
1170 00:56:07.790444
1171 00:56:07.790545 Set Vref, RX VrefLevel [Byte0]: 77
1172 00:56:07.790630 [Byte1]: 77
1173 00:56:07.790714
1174 00:56:07.790814 Final RX Vref Byte 0 = 63 to rank0
1175 00:56:07.790930 Final RX Vref Byte 1 = 59 to rank0
1176 00:56:07.791017 Final RX Vref Byte 0 = 63 to rank1
1177 00:56:07.791103 Final RX Vref Byte 1 = 59 to rank1==
1178 00:56:07.791204 Dram Type= 6, Freq= 0, CH_0, rank 0
1179 00:56:07.791288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1180 00:56:07.791373 ==
1181 00:56:07.791457 DQS Delay:
1182 00:56:07.791571 DQS0 = 0, DQS1 = 0
1183 00:56:07.791655 DQM Delay:
1184 00:56:07.791738 DQM0 = 81, DQM1 = 67
1185 00:56:07.791823 DQ Delay:
1186 00:56:07.791907 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1187 00:56:07.791991 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1188 00:56:07.792075 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1189 00:56:07.792159 DQ12 =72, DQ13 =68, DQ14 =76, DQ15 =76
1190 00:56:07.792243
1191 00:56:07.792326
1192 00:56:07.792410 [DQSOSCAuto] RK0, (LSB)MR18= 0x302f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1193 00:56:07.792495 CH0 RK0: MR19=606, MR18=302F
1194 00:56:07.792579 CH0_RK0: MR19=0x606, MR18=0x302F, DQSOSC=397, MR23=63, INC=93, DEC=62
1195 00:56:07.792700
1196 00:56:07.792815 ----->DramcWriteLeveling(PI) begin...
1197 00:56:07.792901 ==
1198 00:56:07.792986 Dram Type= 6, Freq= 0, CH_0, rank 1
1199 00:56:07.793070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1200 00:56:07.793155 ==
1201 00:56:07.793239 Write leveling (Byte 0): 31 => 31
1202 00:56:07.793323 Write leveling (Byte 1): 30 => 30
1203 00:56:07.793408 DramcWriteLeveling(PI) end<-----
1204 00:56:07.793491
1205 00:56:07.793575 ==
1206 00:56:07.793659 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 00:56:07.793743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1208 00:56:07.793828 ==
1209 00:56:07.793912 [Gating] SW mode calibration
1210 00:56:07.793996 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1211 00:56:07.794081 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1212 00:56:07.794165 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1213 00:56:07.794251 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1214 00:56:07.794335 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1215 00:56:07.794419 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1216 00:56:07.794504 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 00:56:07.794588 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 00:56:07.794672 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 00:56:07.794798 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 00:56:07.794913 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 00:56:07.795061 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 00:56:07.795175 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 00:56:07.795260 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 00:56:07.795344 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:56:07.795427 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:56:07.795511 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:56:07.795627 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:56:07.795711 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:56:07.795795 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1230 00:56:07.795879 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1231 00:56:07.795963 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:56:07.796047 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:56:07.796132 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:56:07.796215 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:56:07.796299 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:56:07.796383 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:56:07.796467 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:56:07.796550 0 9 8 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
1239 00:56:07.796634 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
1240 00:56:07.796758 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 00:56:07.796842 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 00:56:07.796926 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 00:56:07.797010 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 00:56:07.797109 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 00:56:07.797207 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1246 00:56:07.797292 0 10 8 | B1->B0 | 2f2f 2828 | 1 0 | (1 1) (0 0)
1247 00:56:07.797376 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1248 00:56:07.797459 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 00:56:07.797543 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 00:56:07.797626 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 00:56:07.797710 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 00:56:07.797793 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 00:56:07.797877 0 11 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1254 00:56:07.797960 0 11 8 | B1->B0 | 2b2b 3a3a | 1 0 | (0 0) (0 0)
1255 00:56:07.798045 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1256 00:56:07.798129 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 00:56:07.798213 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 00:56:07.798298 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 00:56:07.798452 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 00:56:07.798568 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 00:56:07.798652 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 00:56:07.798735 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 00:56:07.798819 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1264 00:56:07.798903 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 00:56:07.799211 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 00:56:07.799294 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 00:56:07.799379 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 00:56:07.799464 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 00:56:07.799583 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 00:56:07.799668 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 00:56:07.799752 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 00:56:07.799837 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 00:56:07.799921 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 00:56:07.800005 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 00:56:07.800089 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 00:56:07.800174 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 00:56:07.800258 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1278 00:56:07.800341 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1279 00:56:07.800464 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1280 00:56:07.800548 Total UI for P1: 0, mck2ui 16
1281 00:56:07.800632 best dqsien dly found for B0: ( 0, 14, 6)
1282 00:56:07.800751 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 00:56:07.800836 Total UI for P1: 0, mck2ui 16
1284 00:56:07.800920 best dqsien dly found for B1: ( 0, 14, 10)
1285 00:56:07.801004 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1286 00:56:07.801089 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1287 00:56:07.801172
1288 00:56:07.801281 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1289 00:56:07.801381 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1290 00:56:07.801482 [Gating] SW calibration Done
1291 00:56:07.801581 ==
1292 00:56:07.801665 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 00:56:07.801815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 00:56:07.801932 ==
1295 00:56:07.802016 RX Vref Scan: 0
1296 00:56:07.802099
1297 00:56:07.802183 RX Vref 0 -> 0, step: 1
1298 00:56:07.802267
1299 00:56:07.802351 RX Delay -130 -> 252, step: 16
1300 00:56:07.802471 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1301 00:56:07.802555 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1302 00:56:07.802671 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1303 00:56:07.802755 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1304 00:56:07.802839 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1305 00:56:07.802924 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1306 00:56:07.803008 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1307 00:56:07.803092 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1308 00:56:07.803176 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1309 00:56:07.803279 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1310 00:56:07.803394 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1311 00:56:07.803480 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1312 00:56:07.803579 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1313 00:56:07.803663 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1314 00:56:07.803747 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1315 00:56:07.803831 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1316 00:56:07.803915 ==
1317 00:56:07.803999 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 00:56:07.804100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 00:56:07.804201 ==
1320 00:56:07.804285 DQS Delay:
1321 00:56:07.804369 DQS0 = 0, DQS1 = 0
1322 00:56:07.804452 DQM Delay:
1323 00:56:07.804535 DQM0 = 75, DQM1 = 69
1324 00:56:07.804618 DQ Delay:
1325 00:56:07.804707 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1326 00:56:07.804824 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1327 00:56:07.804908 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1328 00:56:07.804992 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1329 00:56:07.805076
1330 00:56:07.805160
1331 00:56:07.805243 ==
1332 00:56:07.805327 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 00:56:07.805445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 00:56:07.805529 ==
1335 00:56:07.805613
1336 00:56:07.805695
1337 00:56:07.805778 TX Vref Scan disable
1338 00:56:07.805861 == TX Byte 0 ==
1339 00:56:07.805946 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1340 00:56:07.806032 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1341 00:56:07.806116 == TX Byte 1 ==
1342 00:56:07.806200 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1343 00:56:07.806316 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1344 00:56:07.806400 ==
1345 00:56:07.806484 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 00:56:07.806568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 00:56:07.806653 ==
1348 00:56:07.806738 TX Vref=22, minBit 9, minWin=26, winSum=435
1349 00:56:07.806823 TX Vref=24, minBit 1, minWin=27, winSum=438
1350 00:56:07.806907 TX Vref=26, minBit 1, minWin=27, winSum=439
1351 00:56:07.806992 TX Vref=28, minBit 1, minWin=27, winSum=442
1352 00:56:07.807094 TX Vref=30, minBit 1, minWin=27, winSum=445
1353 00:56:07.807181 TX Vref=32, minBit 11, minWin=26, winSum=438
1354 00:56:07.807268 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 30
1355 00:56:07.807367
1356 00:56:07.807451 Final TX Range 1 Vref 30
1357 00:56:07.807536
1358 00:56:07.807620 ==
1359 00:56:07.807704 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 00:56:07.807789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 00:56:07.807879 ==
1362 00:56:07.807990
1363 00:56:07.808067
1364 00:56:07.808148 TX Vref Scan disable
1365 00:56:07.808230 == TX Byte 0 ==
1366 00:56:07.808308 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1367 00:56:07.808386 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1368 00:56:07.808464 == TX Byte 1 ==
1369 00:56:07.808549 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1370 00:56:07.808627 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1371 00:56:07.808744
1372 00:56:07.808852 [DATLAT]
1373 00:56:07.808930 Freq=800, CH0 RK1
1374 00:56:07.809005
1375 00:56:07.809081 DATLAT Default: 0xa
1376 00:56:07.809159 0, 0xFFFF, sum = 0
1377 00:56:07.809237 1, 0xFFFF, sum = 0
1378 00:56:07.809314 2, 0xFFFF, sum = 0
1379 00:56:07.809391 3, 0xFFFF, sum = 0
1380 00:56:07.809469 4, 0xFFFF, sum = 0
1381 00:56:07.809546 5, 0xFFFF, sum = 0
1382 00:56:07.809640 6, 0xFFFF, sum = 0
1383 00:56:07.809734 7, 0xFFFF, sum = 0
1384 00:56:07.809814 8, 0xFFFF, sum = 0
1385 00:56:07.809892 9, 0x0, sum = 1
1386 00:56:07.809969 10, 0x0, sum = 2
1387 00:56:07.810046 11, 0x0, sum = 3
1388 00:56:07.810124 12, 0x0, sum = 4
1389 00:56:07.810201 best_step = 10
1390 00:56:07.810276
1391 00:56:07.810350 ==
1392 00:56:07.810426 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 00:56:07.810519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 00:56:07.810611 ==
1395 00:56:07.810687 RX Vref Scan: 0
1396 00:56:07.810763
1397 00:56:07.810838 RX Vref 0 -> 0, step: 1
1398 00:56:07.810913
1399 00:56:07.810989 RX Delay -111 -> 252, step: 8
1400 00:56:07.811284 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1401 00:56:07.811375 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1402 00:56:07.811457 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1403 00:56:07.811550 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1404 00:56:07.811628 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1405 00:56:07.811706 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1406 00:56:07.811800 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1407 00:56:07.811890 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1408 00:56:07.811966 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1409 00:56:07.812043 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1410 00:56:07.812119 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1411 00:56:07.812195 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1412 00:56:07.812272 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1413 00:56:07.812348 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1414 00:56:07.812424 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1415 00:56:07.812499 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1416 00:56:07.812574 ==
1417 00:56:07.812681 Dram Type= 6, Freq= 0, CH_0, rank 1
1418 00:56:07.812791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 00:56:07.812892 ==
1420 00:56:07.812985 DQS Delay:
1421 00:56:07.813062 DQS0 = 0, DQS1 = 0
1422 00:56:07.813139 DQM Delay:
1423 00:56:07.813215 DQM0 = 78, DQM1 = 71
1424 00:56:07.813291 DQ Delay:
1425 00:56:07.813367 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1426 00:56:07.813444 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1427 00:56:07.813528 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1428 00:56:07.813608 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1429 00:56:07.813714
1430 00:56:07.813789
1431 00:56:07.813866 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1432 00:56:07.813945 CH0 RK1: MR19=606, MR18=4B27
1433 00:56:07.814021 CH0_RK1: MR19=0x606, MR18=0x4B27, DQSOSC=391, MR23=63, INC=96, DEC=64
1434 00:56:07.814098 [RxdqsGatingPostProcess] freq 800
1435 00:56:07.814181 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1436 00:56:07.814259 Pre-setting of DQS Precalculation
1437 00:56:07.814353 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1438 00:56:07.814443 ==
1439 00:56:07.814520 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 00:56:07.814596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 00:56:07.814673 ==
1442 00:56:07.814748 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1443 00:56:07.814829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1444 00:56:07.814910 [CA 0] Center 36 (6~66) winsize 61
1445 00:56:07.815005 [CA 1] Center 36 (6~67) winsize 62
1446 00:56:07.815083 [CA 2] Center 34 (5~64) winsize 60
1447 00:56:07.815160 [CA 3] Center 34 (4~64) winsize 61
1448 00:56:07.815251 [CA 4] Center 34 (4~64) winsize 61
1449 00:56:07.815327 [CA 5] Center 34 (4~64) winsize 61
1450 00:56:07.815403
1451 00:56:07.815478 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1452 00:56:07.815554
1453 00:56:07.815632 [CATrainingPosCal] consider 1 rank data
1454 00:56:07.815711 u2DelayCellTimex100 = 270/100 ps
1455 00:56:07.815787 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1456 00:56:07.815865 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1457 00:56:07.815942 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1458 00:56:07.816018 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1459 00:56:07.816091 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1460 00:56:07.816196 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1461 00:56:07.816268
1462 00:56:07.816340 CA PerBit enable=1, Macro0, CA PI delay=34
1463 00:56:07.816411
1464 00:56:07.816483 [CBTSetCACLKResult] CA Dly = 34
1465 00:56:07.816556 CS Dly: 4 (0~35)
1466 00:56:07.816628 ==
1467 00:56:07.816737 Dram Type= 6, Freq= 0, CH_1, rank 1
1468 00:56:07.816828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 00:56:07.816917 ==
1470 00:56:07.816991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1471 00:56:07.817065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1472 00:56:07.817140 [CA 0] Center 36 (6~67) winsize 62
1473 00:56:07.817214 [CA 1] Center 36 (6~67) winsize 62
1474 00:56:07.817288 [CA 2] Center 35 (5~65) winsize 61
1475 00:56:07.817384 [CA 3] Center 34 (4~64) winsize 61
1476 00:56:07.817496 [CA 4] Center 34 (4~65) winsize 62
1477 00:56:07.817575 [CA 5] Center 33 (3~64) winsize 62
1478 00:56:07.817656
1479 00:56:07.817741 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1480 00:56:07.817827
1481 00:56:07.817911 [CATrainingPosCal] consider 2 rank data
1482 00:56:07.817997 u2DelayCellTimex100 = 270/100 ps
1483 00:56:07.818091 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1484 00:56:07.818181 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1485 00:56:07.818278 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1486 00:56:07.818371 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1487 00:56:07.818448 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1488 00:56:07.818524 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1489 00:56:07.818599
1490 00:56:07.818674 CA PerBit enable=1, Macro0, CA PI delay=34
1491 00:56:07.818750
1492 00:56:07.818825 [CBTSetCACLKResult] CA Dly = 34
1493 00:56:07.818900 CS Dly: 5 (0~37)
1494 00:56:07.819008
1495 00:56:07.819083 ----->DramcWriteLeveling(PI) begin...
1496 00:56:07.819178 ==
1497 00:56:07.819256 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 00:56:07.819334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 00:56:07.819425 ==
1500 00:56:07.819501 Write leveling (Byte 0): 26 => 26
1501 00:56:07.819610 Write leveling (Byte 1): 29 => 29
1502 00:56:07.819685 DramcWriteLeveling(PI) end<-----
1503 00:56:07.819760
1504 00:56:07.819834 ==
1505 00:56:07.819910 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 00:56:07.819985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 00:56:07.820062 ==
1508 00:56:07.820138 [Gating] SW mode calibration
1509 00:56:07.820215 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1510 00:56:07.820293 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1511 00:56:07.820387 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1512 00:56:07.820478 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1513 00:56:07.820555 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1514 00:56:07.820631 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 00:56:07.820747 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 00:56:07.820825 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 00:56:07.821097 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 00:56:07.821179 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 00:56:07.821276 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 00:56:07.821369 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 00:56:07.821446 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:56:07.821523 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:56:07.821599 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:56:07.821676 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:56:07.821752 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 00:56:07.821829 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 00:56:07.821905 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 00:56:07.821981 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1529 00:56:07.822057 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:56:07.822165 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1531 00:56:07.822241 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:56:07.822317 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:56:07.822394 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:56:07.822470 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:56:07.822546 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:56:07.822623 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 00:56:07.822699 0 9 8 | B1->B0 | 2929 2726 | 0 1 | (0 0) (0 0)
1538 00:56:07.822775 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 00:56:07.822851 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 00:56:07.822944 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 00:56:07.823037 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 00:56:07.823113 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 00:56:07.823190 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 00:56:07.823284 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1545 00:56:07.823362 0 10 8 | B1->B0 | 2d2d 2525 | 1 0 | (1 0) (1 0)
1546 00:56:07.823440 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 00:56:07.823531 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 00:56:07.823607 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 00:56:07.823683 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 00:56:07.823759 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 00:56:07.823868 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 00:56:07.823944 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 00:56:07.824021 0 11 8 | B1->B0 | 3636 3838 | 0 0 | (1 1) (0 0)
1554 00:56:07.824097 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 00:56:07.824173 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 00:56:07.824250 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 00:56:07.824326 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 00:56:07.824439 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 00:56:07.824533 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 00:56:07.824611 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1561 00:56:07.824710 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1562 00:56:07.824786 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 00:56:07.824863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 00:56:07.824939 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 00:56:07.825016 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 00:56:07.825109 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 00:56:07.825201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 00:56:07.825277 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 00:56:07.825354 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 00:56:07.825430 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 00:56:07.825506 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 00:56:07.825582 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 00:56:07.825658 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 00:56:07.825751 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 00:56:07.825841 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 00:56:07.825917 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1577 00:56:07.825994 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1578 00:56:07.826069 Total UI for P1: 0, mck2ui 16
1579 00:56:07.826146 best dqsien dly found for B1: ( 0, 14, 4)
1580 00:56:07.826222 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 00:56:07.826298 Total UI for P1: 0, mck2ui 16
1582 00:56:07.826375 best dqsien dly found for B0: ( 0, 14, 6)
1583 00:56:07.826483 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1584 00:56:07.826559 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1585 00:56:07.826633
1586 00:56:07.826709 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1587 00:56:07.826786 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1588 00:56:07.826861 [Gating] SW calibration Done
1589 00:56:07.826936 ==
1590 00:56:07.827011 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 00:56:07.827120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 00:56:07.827214 ==
1593 00:56:07.827291 RX Vref Scan: 0
1594 00:56:07.827368
1595 00:56:07.827459 RX Vref 0 -> 0, step: 1
1596 00:56:07.827533
1597 00:56:07.827609 RX Delay -130 -> 252, step: 16
1598 00:56:07.827703 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1599 00:56:07.827794 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1600 00:56:07.827870 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1601 00:56:07.827946 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1602 00:56:07.828022 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1603 00:56:07.828097 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1604 00:56:07.828173 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1605 00:56:07.828249 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1606 00:56:07.828325 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1607 00:56:07.828591 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1608 00:56:07.828696 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1609 00:56:07.828748 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1610 00:56:07.828798 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1611 00:56:07.828847 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1612 00:56:07.828895 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1613 00:56:07.828944 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1614 00:56:07.828992 ==
1615 00:56:07.829059 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 00:56:07.829122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 00:56:07.829171 ==
1618 00:56:07.829218 DQS Delay:
1619 00:56:07.829267 DQS0 = 0, DQS1 = 0
1620 00:56:07.829346 DQM Delay:
1621 00:56:07.829394 DQM0 = 80, DQM1 = 70
1622 00:56:07.829441 DQ Delay:
1623 00:56:07.829489 DQ0 =85, DQ1 =77, DQ2 =61, DQ3 =77
1624 00:56:07.829537 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1625 00:56:07.829585 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1626 00:56:07.829634 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1627 00:56:07.829682
1628 00:56:07.829756
1629 00:56:07.829817 ==
1630 00:56:07.829864 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 00:56:07.829912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 00:56:07.829960 ==
1633 00:56:07.830007
1634 00:56:07.830055
1635 00:56:07.830103 TX Vref Scan disable
1636 00:56:07.830151 == TX Byte 0 ==
1637 00:56:07.830198 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1638 00:56:07.830247 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1639 00:56:07.830295 == TX Byte 1 ==
1640 00:56:07.830343 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1641 00:56:07.830410 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1642 00:56:07.830470 ==
1643 00:56:07.830518 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 00:56:07.830567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 00:56:07.830615 ==
1646 00:56:07.830662 TX Vref=22, minBit 1, minWin=27, winSum=448
1647 00:56:07.830711 TX Vref=24, minBit 10, minWin=27, winSum=450
1648 00:56:07.830760 TX Vref=26, minBit 1, minWin=27, winSum=453
1649 00:56:07.830808 TX Vref=28, minBit 0, minWin=28, winSum=456
1650 00:56:07.830857 TX Vref=30, minBit 0, minWin=28, winSum=456
1651 00:56:07.830905 TX Vref=32, minBit 6, minWin=27, winSum=454
1652 00:56:07.830953 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
1653 00:56:07.831021
1654 00:56:07.831083 Final TX Range 1 Vref 28
1655 00:56:07.831131
1656 00:56:07.831178 ==
1657 00:56:07.831225 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 00:56:07.831273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 00:56:07.831322 ==
1660 00:56:07.831369
1661 00:56:07.831416
1662 00:56:07.831483 TX Vref Scan disable
1663 00:56:07.831533 == TX Byte 0 ==
1664 00:56:07.831582 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1665 00:56:07.831630 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1666 00:56:07.831702 == TX Byte 1 ==
1667 00:56:07.831782 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1668 00:56:07.831863 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1669 00:56:07.831927
1670 00:56:07.831992 [DATLAT]
1671 00:56:07.832054 Freq=800, CH1 RK0
1672 00:56:07.832102
1673 00:56:07.832149 DATLAT Default: 0xa
1674 00:56:07.832198 0, 0xFFFF, sum = 0
1675 00:56:07.832247 1, 0xFFFF, sum = 0
1676 00:56:07.832296 2, 0xFFFF, sum = 0
1677 00:56:07.832345 3, 0xFFFF, sum = 0
1678 00:56:07.832394 4, 0xFFFF, sum = 0
1679 00:56:07.832443 5, 0xFFFF, sum = 0
1680 00:56:07.832491 6, 0xFFFF, sum = 0
1681 00:56:07.832584 7, 0xFFFF, sum = 0
1682 00:56:07.832668 8, 0xFFFF, sum = 0
1683 00:56:07.832735 9, 0x0, sum = 1
1684 00:56:07.832785 10, 0x0, sum = 2
1685 00:56:07.832834 11, 0x0, sum = 3
1686 00:56:07.832883 12, 0x0, sum = 4
1687 00:56:07.832931 best_step = 10
1688 00:56:07.832979
1689 00:56:07.833027 ==
1690 00:56:07.833074 Dram Type= 6, Freq= 0, CH_1, rank 0
1691 00:56:07.833122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1692 00:56:07.833170 ==
1693 00:56:07.833219 RX Vref Scan: 1
1694 00:56:07.833267
1695 00:56:07.833314 Set Vref Range= 32 -> 127
1696 00:56:07.833363
1697 00:56:07.833428 RX Vref 32 -> 127, step: 1
1698 00:56:07.833490
1699 00:56:07.833538 RX Delay -111 -> 252, step: 8
1700 00:56:07.833586
1701 00:56:07.833634 Set Vref, RX VrefLevel [Byte0]: 32
1702 00:56:07.833682 [Byte1]: 32
1703 00:56:07.833731
1704 00:56:07.833779 Set Vref, RX VrefLevel [Byte0]: 33
1705 00:56:07.833827 [Byte1]: 33
1706 00:56:07.833875
1707 00:56:07.833922 Set Vref, RX VrefLevel [Byte0]: 34
1708 00:56:07.833970 [Byte1]: 34
1709 00:56:07.834018
1710 00:56:07.834065 Set Vref, RX VrefLevel [Byte0]: 35
1711 00:56:07.834112 [Byte1]: 35
1712 00:56:07.834160
1713 00:56:07.834208 Set Vref, RX VrefLevel [Byte0]: 36
1714 00:56:07.834279 [Byte1]: 36
1715 00:56:07.834342
1716 00:56:07.834390 Set Vref, RX VrefLevel [Byte0]: 37
1717 00:56:07.834438 [Byte1]: 37
1718 00:56:07.834486
1719 00:56:07.834534 Set Vref, RX VrefLevel [Byte0]: 38
1720 00:56:07.834582 [Byte1]: 38
1721 00:56:07.834629
1722 00:56:07.834677 Set Vref, RX VrefLevel [Byte0]: 39
1723 00:56:07.834725 [Byte1]: 39
1724 00:56:07.834773
1725 00:56:07.834821 Set Vref, RX VrefLevel [Byte0]: 40
1726 00:56:07.834868 [Byte1]: 40
1727 00:56:07.834916
1728 00:56:07.834964 Set Vref, RX VrefLevel [Byte0]: 41
1729 00:56:07.835012 [Byte1]: 41
1730 00:56:07.835060
1731 00:56:07.835107 Set Vref, RX VrefLevel [Byte0]: 42
1732 00:56:07.835173 [Byte1]: 42
1733 00:56:07.835234
1734 00:56:07.835282 Set Vref, RX VrefLevel [Byte0]: 43
1735 00:56:07.835330 [Byte1]: 43
1736 00:56:07.835378
1737 00:56:07.835426 Set Vref, RX VrefLevel [Byte0]: 44
1738 00:56:07.835473 [Byte1]: 44
1739 00:56:07.835521
1740 00:56:07.835568 Set Vref, RX VrefLevel [Byte0]: 45
1741 00:56:07.835615 [Byte1]: 45
1742 00:56:07.835662
1743 00:56:07.835710 Set Vref, RX VrefLevel [Byte0]: 46
1744 00:56:07.835758 [Byte1]: 46
1745 00:56:07.835829
1746 00:56:07.835891 Set Vref, RX VrefLevel [Byte0]: 47
1747 00:56:07.835939 [Byte1]: 47
1748 00:56:07.836002
1749 00:56:07.836093 Set Vref, RX VrefLevel [Byte0]: 48
1750 00:56:07.836141 [Byte1]: 48
1751 00:56:07.836189
1752 00:56:07.836236 Set Vref, RX VrefLevel [Byte0]: 49
1753 00:56:07.836284 [Byte1]: 49
1754 00:56:07.836332
1755 00:56:07.836398 Set Vref, RX VrefLevel [Byte0]: 50
1756 00:56:07.836463 [Byte1]: 50
1757 00:56:07.836511
1758 00:56:07.836559 Set Vref, RX VrefLevel [Byte0]: 51
1759 00:56:07.836607 [Byte1]: 51
1760 00:56:07.836684
1761 00:56:07.836776 Set Vref, RX VrefLevel [Byte0]: 52
1762 00:56:07.836871 [Byte1]: 52
1763 00:56:07.836959
1764 00:56:07.837035 Set Vref, RX VrefLevel [Byte0]: 53
1765 00:56:07.837111 [Byte1]: 53
1766 00:56:07.837189
1767 00:56:07.837241 Set Vref, RX VrefLevel [Byte0]: 54
1768 00:56:07.837290 [Byte1]: 54
1769 00:56:07.837338
1770 00:56:07.837575 Set Vref, RX VrefLevel [Byte0]: 55
1771 00:56:07.837632 [Byte1]: 55
1772 00:56:07.837699
1773 00:56:07.837762 Set Vref, RX VrefLevel [Byte0]: 56
1774 00:56:07.837811 [Byte1]: 56
1775 00:56:07.837859
1776 00:56:07.837906 Set Vref, RX VrefLevel [Byte0]: 57
1777 00:56:07.837953 [Byte1]: 57
1778 00:56:07.838001
1779 00:56:07.838049 Set Vref, RX VrefLevel [Byte0]: 58
1780 00:56:07.838098 [Byte1]: 58
1781 00:56:07.838146
1782 00:56:07.838194 Set Vref, RX VrefLevel [Byte0]: 59
1783 00:56:07.838242 [Byte1]: 59
1784 00:56:07.838289
1785 00:56:07.838337 Set Vref, RX VrefLevel [Byte0]: 60
1786 00:56:07.838385 [Byte1]: 60
1787 00:56:07.838433
1788 00:56:07.838481 Set Vref, RX VrefLevel [Byte0]: 61
1789 00:56:07.838529 [Byte1]: 61
1790 00:56:07.838577
1791 00:56:07.838625 Set Vref, RX VrefLevel [Byte0]: 62
1792 00:56:07.838673 [Byte1]: 62
1793 00:56:07.838738
1794 00:56:07.838801 Set Vref, RX VrefLevel [Byte0]: 63
1795 00:56:07.838849 [Byte1]: 63
1796 00:56:07.838896
1797 00:56:07.838943 Set Vref, RX VrefLevel [Byte0]: 64
1798 00:56:07.838991 [Byte1]: 64
1799 00:56:07.839039
1800 00:56:07.839087 Set Vref, RX VrefLevel [Byte0]: 65
1801 00:56:07.839135 [Byte1]: 65
1802 00:56:07.839182
1803 00:56:07.839230 Set Vref, RX VrefLevel [Byte0]: 66
1804 00:56:07.839277 [Byte1]: 66
1805 00:56:07.839325
1806 00:56:07.839373 Set Vref, RX VrefLevel [Byte0]: 67
1807 00:56:07.839438 [Byte1]: 67
1808 00:56:07.839555
1809 00:56:07.839654 Set Vref, RX VrefLevel [Byte0]: 68
1810 00:56:07.839731 [Byte1]: 68
1811 00:56:07.839809
1812 00:56:07.839888 Set Vref, RX VrefLevel [Byte0]: 69
1813 00:56:07.839953 [Byte1]: 69
1814 00:56:07.840002
1815 00:56:07.840051 Set Vref, RX VrefLevel [Byte0]: 70
1816 00:56:07.840099 [Byte1]: 70
1817 00:56:07.840163
1818 00:56:07.840212 Set Vref, RX VrefLevel [Byte0]: 71
1819 00:56:07.840262 [Byte1]: 71
1820 00:56:07.840311
1821 00:56:07.840359 Set Vref, RX VrefLevel [Byte0]: 72
1822 00:56:07.840407 [Byte1]: 72
1823 00:56:07.840457
1824 00:56:07.840506 Set Vref, RX VrefLevel [Byte0]: 73
1825 00:56:07.840555 [Byte1]: 73
1826 00:56:07.840604
1827 00:56:07.840663 Final RX Vref Byte 0 = 63 to rank0
1828 00:56:07.840715 Final RX Vref Byte 1 = 54 to rank0
1829 00:56:07.840765 Final RX Vref Byte 0 = 63 to rank1
1830 00:56:07.840815 Final RX Vref Byte 1 = 54 to rank1==
1831 00:56:07.840863 Dram Type= 6, Freq= 0, CH_1, rank 0
1832 00:56:07.840913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1833 00:56:07.840963 ==
1834 00:56:07.841012 DQS Delay:
1835 00:56:07.841061 DQS0 = 0, DQS1 = 0
1836 00:56:07.841109 DQM Delay:
1837 00:56:07.841158 DQM0 = 80, DQM1 = 71
1838 00:56:07.841207 DQ Delay:
1839 00:56:07.841256 DQ0 =88, DQ1 =72, DQ2 =68, DQ3 =76
1840 00:56:07.841307 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1841 00:56:07.841356 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1842 00:56:07.841405 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1843 00:56:07.841455
1844 00:56:07.841504
1845 00:56:07.841554 [DQSOSCAuto] RK0, (LSB)MR18= 0x151f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1846 00:56:07.841605 CH1 RK0: MR19=606, MR18=151F
1847 00:56:07.841655 CH1_RK0: MR19=0x606, MR18=0x151F, DQSOSC=402, MR23=63, INC=91, DEC=60
1848 00:56:07.841705
1849 00:56:07.841754 ----->DramcWriteLeveling(PI) begin...
1850 00:56:07.841804 ==
1851 00:56:07.841853 Dram Type= 6, Freq= 0, CH_1, rank 1
1852 00:56:07.841903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1853 00:56:07.841952 ==
1854 00:56:07.842001 Write leveling (Byte 0): 27 => 27
1855 00:56:07.842051 Write leveling (Byte 1): 32 => 32
1856 00:56:07.842100 DramcWriteLeveling(PI) end<-----
1857 00:56:07.842149
1858 00:56:07.842198 ==
1859 00:56:07.842246 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 00:56:07.842296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 00:56:07.842345 ==
1862 00:56:07.842393 [Gating] SW mode calibration
1863 00:56:07.842444 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1864 00:56:07.842494 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1865 00:56:07.842544 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1866 00:56:07.842594 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1867 00:56:07.842643 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 00:56:07.842693 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 00:56:07.842742 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 00:56:07.842791 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 00:56:07.842840 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 00:56:07.842890 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 00:56:07.842939 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 00:56:07.842988 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 00:56:07.843037 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 00:56:07.843087 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 00:56:07.843137 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 00:56:07.843187 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 00:56:07.843236 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 00:56:07.843286 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 00:56:07.843335 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 00:56:07.843384 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1883 00:56:07.843432 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 00:56:07.843481 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:56:07.843530 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:56:07.843579 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:56:07.843628 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:56:07.843677 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:56:07.843726 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:56:07.843775 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1891 00:56:07.843824 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1892 00:56:07.843874 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 00:56:07.843924 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 00:56:07.844162 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 00:56:07.844217 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 00:56:07.844268 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 00:56:07.844317 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 00:56:07.844367 0 10 4 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
1899 00:56:07.844416 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1900 00:56:07.844466 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:56:07.844516 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:56:07.844565 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:56:07.844615 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:56:07.844677 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 00:56:07.844728 0 11 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1906 00:56:07.844778 0 11 4 | B1->B0 | 2e2e 3a3a | 0 0 | (0 0) (0 0)
1907 00:56:07.844827 0 11 8 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
1908 00:56:07.844877 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 00:56:07.844926 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 00:56:07.844976 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 00:56:07.845025 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 00:56:07.845074 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 00:56:07.845124 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 00:56:07.845173 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1915 00:56:07.845221 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1916 00:56:07.845270 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 00:56:07.845319 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 00:56:07.845368 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 00:56:07.845416 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 00:56:07.845465 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 00:56:07.845514 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 00:56:07.845563 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 00:56:07.845612 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 00:56:07.845661 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 00:56:07.845710 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 00:56:07.845759 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 00:56:07.845809 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 00:56:07.845858 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 00:56:07.845907 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 00:56:07.845956 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 00:56:07.846005 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 00:56:07.846054 Total UI for P1: 0, mck2ui 16
1933 00:56:07.846103 best dqsien dly found for B0: ( 0, 14, 6)
1934 00:56:07.846153 Total UI for P1: 0, mck2ui 16
1935 00:56:07.846202 best dqsien dly found for B1: ( 0, 14, 6)
1936 00:56:07.846251 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1937 00:56:07.846300 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1938 00:56:07.846349
1939 00:56:07.846398 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1940 00:56:07.846447 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1941 00:56:07.846497 [Gating] SW calibration Done
1942 00:56:07.846546 ==
1943 00:56:07.846594 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 00:56:07.846644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 00:56:07.846694 ==
1946 00:56:07.846743 RX Vref Scan: 0
1947 00:56:07.846792
1948 00:56:07.846840 RX Vref 0 -> 0, step: 1
1949 00:56:07.846889
1950 00:56:07.846938 RX Delay -130 -> 252, step: 16
1951 00:56:07.846987 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1952 00:56:07.847036 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1953 00:56:07.847085 iDelay=206, Bit 2, Center 61 (-66 ~ 189) 256
1954 00:56:07.847135 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1955 00:56:07.847184 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1956 00:56:07.847233 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1957 00:56:07.847281 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1958 00:56:07.847330 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1959 00:56:07.847380 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1960 00:56:07.847429 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1961 00:56:07.847478 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1962 00:56:07.847528 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1963 00:56:07.847577 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1964 00:56:07.847626 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1965 00:56:07.847675 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1966 00:56:07.847724 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1967 00:56:07.847773 ==
1968 00:56:07.847822 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 00:56:07.847871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 00:56:07.847921 ==
1971 00:56:07.847970 DQS Delay:
1972 00:56:07.848019 DQS0 = 0, DQS1 = 0
1973 00:56:07.848067 DQM Delay:
1974 00:56:07.848115 DQM0 = 74, DQM1 = 71
1975 00:56:07.848164 DQ Delay:
1976 00:56:07.848213 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =69
1977 00:56:07.848262 DQ4 =69, DQ5 =85, DQ6 =85, DQ7 =69
1978 00:56:07.848312 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1979 00:56:07.848361 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1980 00:56:07.848410
1981 00:56:07.848457
1982 00:56:07.848506 ==
1983 00:56:07.848555 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 00:56:07.848604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 00:56:08.083661 ==
1986 00:56:08.083799
1987 00:56:08.083888
1988 00:56:08.083973 TX Vref Scan disable
1989 00:56:08.084029 == TX Byte 0 ==
1990 00:56:08.084082 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1991 00:56:08.084133 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1992 00:56:08.084223 == TX Byte 1 ==
1993 00:56:08.084301 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1994 00:56:08.084377 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1995 00:56:08.084461 ==
1996 00:56:08.084540 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 00:56:08.084632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 00:56:08.084766 ==
1999 00:56:08.084864 TX Vref=22, minBit 9, minWin=27, winSum=450
2000 00:56:08.084971 TX Vref=24, minBit 1, minWin=28, winSum=454
2001 00:56:08.085073 TX Vref=26, minBit 1, minWin=28, winSum=455
2002 00:56:08.085376 TX Vref=28, minBit 1, minWin=28, winSum=458
2003 00:56:08.085443 TX Vref=30, minBit 5, minWin=27, winSum=460
2004 00:56:08.085504 TX Vref=32, minBit 5, minWin=27, winSum=459
2005 00:56:08.085559 [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 28
2006 00:56:08.085611
2007 00:56:08.085666 Final TX Range 1 Vref 28
2008 00:56:08.085799
2009 00:56:08.085881 ==
2010 00:56:08.085987 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 00:56:08.086047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 00:56:08.086132 ==
2013 00:56:08.086225
2014 00:56:08.086306
2015 00:56:08.086371 TX Vref Scan disable
2016 00:56:08.086424 == TX Byte 0 ==
2017 00:56:08.086473 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2018 00:56:08.086527 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2019 00:56:08.086575 == TX Byte 1 ==
2020 00:56:08.086624 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2021 00:56:08.086672 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2022 00:56:08.086719
2023 00:56:08.086770 [DATLAT]
2024 00:56:08.086818 Freq=800, CH1 RK1
2025 00:56:08.086866
2026 00:56:08.086913 DATLAT Default: 0xa
2027 00:56:08.086959 0, 0xFFFF, sum = 0
2028 00:56:08.087015 1, 0xFFFF, sum = 0
2029 00:56:08.087064 2, 0xFFFF, sum = 0
2030 00:56:08.087113 3, 0xFFFF, sum = 0
2031 00:56:08.087165 4, 0xFFFF, sum = 0
2032 00:56:08.087227 5, 0xFFFF, sum = 0
2033 00:56:08.087284 6, 0xFFFF, sum = 0
2034 00:56:08.087333 7, 0xFFFF, sum = 0
2035 00:56:08.087393 8, 0xFFFF, sum = 0
2036 00:56:08.087443 9, 0x0, sum = 1
2037 00:56:08.087491 10, 0x0, sum = 2
2038 00:56:08.087545 11, 0x0, sum = 3
2039 00:56:08.087594 12, 0x0, sum = 4
2040 00:56:08.087642 best_step = 10
2041 00:56:08.087689
2042 00:56:08.087736 ==
2043 00:56:08.087788 Dram Type= 6, Freq= 0, CH_1, rank 1
2044 00:56:08.087836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2045 00:56:08.087887 ==
2046 00:56:08.087936 RX Vref Scan: 0
2047 00:56:08.087983
2048 00:56:08.088035 RX Vref 0 -> 0, step: 1
2049 00:56:08.088083
2050 00:56:08.088130 RX Delay -111 -> 252, step: 8
2051 00:56:08.088176 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2052 00:56:08.088223 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2053 00:56:08.088276 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2054 00:56:08.088324 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2055 00:56:08.088371 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
2056 00:56:08.088418 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2057 00:56:08.088465 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2058 00:56:08.088518 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2059 00:56:08.088565 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2060 00:56:08.088613 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2061 00:56:08.088698 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2062 00:56:08.088747 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2063 00:56:08.088801 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2064 00:56:08.088848 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2065 00:56:08.088896 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2066 00:56:08.088943 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2067 00:56:08.088990 ==
2068 00:56:08.089044 Dram Type= 6, Freq= 0, CH_1, rank 1
2069 00:56:08.089105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2070 00:56:08.089162 ==
2071 00:56:08.089232 DQS Delay:
2072 00:56:08.089314 DQS0 = 0, DQS1 = 0
2073 00:56:08.089389 DQM Delay:
2074 00:56:08.089463 DQM0 = 77, DQM1 = 74
2075 00:56:08.089543 DQ Delay:
2076 00:56:08.089618 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2077 00:56:08.089692 DQ4 =72, DQ5 =88, DQ6 =88, DQ7 =76
2078 00:56:08.089773 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2079 00:56:08.089848 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2080 00:56:08.089922
2081 00:56:08.089996
2082 00:56:08.090078 [DQSOSCAuto] RK1, (LSB)MR18= 0x233b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2083 00:56:08.090132 CH1 RK1: MR19=606, MR18=233B
2084 00:56:08.090213 CH1_RK1: MR19=0x606, MR18=0x233B, DQSOSC=394, MR23=63, INC=95, DEC=63
2085 00:56:08.090295 [RxdqsGatingPostProcess] freq 800
2086 00:56:08.090409 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2087 00:56:08.090485 Pre-setting of DQS Precalculation
2088 00:56:08.090554 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2089 00:56:08.090605 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2090 00:56:08.090671 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2091 00:56:08.090727
2092 00:56:08.090803
2093 00:56:08.090887 [Calibration Summary] 1600 Mbps
2094 00:56:08.090963 CH 0, Rank 0
2095 00:56:08.091045 SW Impedance : PASS
2096 00:56:08.091121 DUTY Scan : NO K
2097 00:56:08.091214 ZQ Calibration : PASS
2098 00:56:08.091354 Jitter Meter : NO K
2099 00:56:08.091488 CBT Training : PASS
2100 00:56:08.091579 Write leveling : PASS
2101 00:56:08.091678 RX DQS gating : PASS
2102 00:56:08.091744 RX DQ/DQS(RDDQC) : PASS
2103 00:56:08.091792 TX DQ/DQS : PASS
2104 00:56:08.091848 RX DATLAT : PASS
2105 00:56:08.091899 RX DQ/DQS(Engine): PASS
2106 00:56:08.091947 TX OE : NO K
2107 00:56:08.092000 All Pass.
2108 00:56:08.092071
2109 00:56:08.092152 CH 0, Rank 1
2110 00:56:08.092227 SW Impedance : PASS
2111 00:56:08.092309 DUTY Scan : NO K
2112 00:56:08.092385 ZQ Calibration : PASS
2113 00:56:08.092460 Jitter Meter : NO K
2114 00:56:08.092571 CBT Training : PASS
2115 00:56:08.092654 Write leveling : PASS
2116 00:56:08.092731 RX DQS gating : PASS
2117 00:56:08.092799 RX DQ/DQS(RDDQC) : PASS
2118 00:56:08.092849 TX DQ/DQS : PASS
2119 00:56:08.092919 RX DATLAT : PASS
2120 00:56:08.092999 RX DQ/DQS(Engine): PASS
2121 00:56:08.093081 TX OE : NO K
2122 00:56:08.093158 All Pass.
2123 00:56:08.093236
2124 00:56:08.093316 CH 1, Rank 0
2125 00:56:08.093398 SW Impedance : PASS
2126 00:56:08.093474 DUTY Scan : NO K
2127 00:56:08.093563 ZQ Calibration : PASS
2128 00:56:08.093639 Jitter Meter : NO K
2129 00:56:08.093715 CBT Training : PASS
2130 00:56:08.093798 Write leveling : PASS
2131 00:56:08.093876 RX DQS gating : PASS
2132 00:56:08.093951 RX DQ/DQS(RDDQC) : PASS
2133 00:56:08.094041 TX DQ/DQS : PASS
2134 00:56:08.094119 RX DATLAT : PASS
2135 00:56:08.094194 RX DQ/DQS(Engine): PASS
2136 00:56:08.094280 TX OE : NO K
2137 00:56:08.094399 All Pass.
2138 00:56:08.094474
2139 00:56:08.094592 CH 1, Rank 1
2140 00:56:08.094668 SW Impedance : PASS
2141 00:56:08.094751 DUTY Scan : NO K
2142 00:56:08.094833 ZQ Calibration : PASS
2143 00:56:08.094908 Jitter Meter : NO K
2144 00:56:08.094984 CBT Training : PASS
2145 00:56:08.095068 Write leveling : PASS
2146 00:56:08.095143 RX DQS gating : PASS
2147 00:56:08.095224 RX DQ/DQS(RDDQC) : PASS
2148 00:56:08.095306 TX DQ/DQS : PASS
2149 00:56:08.095386 RX DATLAT : PASS
2150 00:56:08.095492 RX DQ/DQS(Engine): PASS
2151 00:56:08.095577 TX OE : NO K
2152 00:56:08.095655 All Pass.
2153 00:56:08.095708
2154 00:56:08.095768 DramC Write-DBI off
2155 00:56:08.095819 PER_BANK_REFRESH: Hybrid Mode
2156 00:56:08.096078 TX_TRACKING: ON
2157 00:56:08.096173 [GetDramInforAfterCalByMRR] Vendor 6.
2158 00:56:08.096260 [GetDramInforAfterCalByMRR] Revision 606.
2159 00:56:08.096342 [GetDramInforAfterCalByMRR] Revision 2 0.
2160 00:56:08.096423 MR0 0x3b3b
2161 00:56:08.096498 MR8 0x5151
2162 00:56:08.096585 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2163 00:56:08.096701
2164 00:56:08.096765 MR0 0x3b3b
2165 00:56:08.096816 MR8 0x5151
2166 00:56:08.096865 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2167 00:56:08.096913
2168 00:56:08.096973 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2169 00:56:08.097058 [FAST_K] Save calibration result to emmc
2170 00:56:08.097138 [FAST_K] Save calibration result to emmc
2171 00:56:08.097217 dram_init: config_dvfs: 1
2172 00:56:08.097303 dramc_set_vcore_voltage set vcore to 662500
2173 00:56:08.097381 Read voltage for 1200, 2
2174 00:56:08.097490 Vio18 = 0
2175 00:56:08.097573 Vcore = 662500
2176 00:56:08.097652 Vdram = 0
2177 00:56:08.097727 Vddq = 0
2178 00:56:08.097815 Vmddr = 0
2179 00:56:08.097901 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2180 00:56:08.098035 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2181 00:56:08.098164 MEM_TYPE=3, freq_sel=15
2182 00:56:08.098241 sv_algorithm_assistance_LP4_1600
2183 00:56:08.098365 ============ PULL DRAM RESETB DOWN ============
2184 00:56:08.098444 ========== PULL DRAM RESETB DOWN end =========
2185 00:56:08.098525 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2186 00:56:08.098601 ===================================
2187 00:56:08.098689 LPDDR4 DRAM CONFIGURATION
2188 00:56:08.098771 ===================================
2189 00:56:08.098847 EX_ROW_EN[0] = 0x0
2190 00:56:08.098933 EX_ROW_EN[1] = 0x0
2191 00:56:08.099009 LP4Y_EN = 0x0
2192 00:56:08.099084 WORK_FSP = 0x0
2193 00:56:08.099207 WL = 0x4
2194 00:56:08.099291 RL = 0x4
2195 00:56:08.099371 BL = 0x2
2196 00:56:08.099453 RPST = 0x0
2197 00:56:08.099530 RD_PRE = 0x0
2198 00:56:08.099588 WR_PRE = 0x1
2199 00:56:08.099638 WR_PST = 0x0
2200 00:56:08.099692 DBI_WR = 0x0
2201 00:56:08.099740 DBI_RD = 0x0
2202 00:56:08.099803 OTF = 0x1
2203 00:56:08.099879 ===================================
2204 00:56:08.099965 ===================================
2205 00:56:08.100071 ANA top config
2206 00:56:08.100156 ===================================
2207 00:56:08.100234 DLL_ASYNC_EN = 0
2208 00:56:08.100313 ALL_SLAVE_EN = 0
2209 00:56:08.100401 NEW_RANK_MODE = 1
2210 00:56:08.100484 DLL_IDLE_MODE = 1
2211 00:56:08.100560 LP45_APHY_COMB_EN = 1
2212 00:56:08.100641 TX_ODT_DIS = 1
2213 00:56:08.100757 NEW_8X_MODE = 1
2214 00:56:08.100841 ===================================
2215 00:56:08.100924 ===================================
2216 00:56:08.101001 data_rate = 2400
2217 00:56:08.101087 CKR = 1
2218 00:56:08.101169 DQ_P2S_RATIO = 8
2219 00:56:08.101245 ===================================
2220 00:56:08.101327 CA_P2S_RATIO = 8
2221 00:56:08.101408 DQ_CA_OPEN = 0
2222 00:56:08.101473 DQ_SEMI_OPEN = 0
2223 00:56:08.101522 CA_SEMI_OPEN = 0
2224 00:56:08.101570 CA_FULL_RATE = 0
2225 00:56:08.101618 DQ_CKDIV4_EN = 0
2226 00:56:08.101690 CA_CKDIV4_EN = 0
2227 00:56:08.101770 CA_PREDIV_EN = 0
2228 00:56:08.101846 PH8_DLY = 17
2229 00:56:08.101934 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2230 00:56:08.102010 DQ_AAMCK_DIV = 4
2231 00:56:08.102094 CA_AAMCK_DIV = 4
2232 00:56:08.102235 CA_ADMCK_DIV = 4
2233 00:56:08.102366 DQ_TRACK_CA_EN = 0
2234 00:56:08.102451 CA_PICK = 1200
2235 00:56:08.102535 CA_MCKIO = 1200
2236 00:56:08.102616 MCKIO_SEMI = 0
2237 00:56:08.102691 PLL_FREQ = 2366
2238 00:56:08.102777 DQ_UI_PI_RATIO = 32
2239 00:56:08.102853 CA_UI_PI_RATIO = 0
2240 00:56:08.102929 ===================================
2241 00:56:08.103018 ===================================
2242 00:56:08.103095 memory_type:LPDDR4
2243 00:56:08.103177 GP_NUM : 10
2244 00:56:08.103252 SRAM_EN : 1
2245 00:56:08.103329 MD32_EN : 0
2246 00:56:08.103419 ===================================
2247 00:56:08.103496 [ANA_INIT] >>>>>>>>>>>>>>
2248 00:56:08.103571 <<<<<< [CONFIGURE PHASE]: ANA_TX
2249 00:56:08.103660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2250 00:56:08.103737 ===================================
2251 00:56:08.103818 data_rate = 2400,PCW = 0X5b00
2252 00:56:08.103901 ===================================
2253 00:56:08.103983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2254 00:56:08.104063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2255 00:56:08.104140 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 00:56:08.104225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2257 00:56:08.104314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2258 00:56:08.104390 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2259 00:56:08.104476 [ANA_INIT] flow start
2260 00:56:08.104557 [ANA_INIT] PLL >>>>>>>>
2261 00:56:08.104640 [ANA_INIT] PLL <<<<<<<<
2262 00:56:08.104739 [ANA_INIT] MIDPI >>>>>>>>
2263 00:56:08.104790 [ANA_INIT] MIDPI <<<<<<<<
2264 00:56:08.104840 [ANA_INIT] DLL >>>>>>>>
2265 00:56:08.104903 [ANA_INIT] DLL <<<<<<<<
2266 00:56:08.104952 [ANA_INIT] flow end
2267 00:56:08.105001 ============ LP4 DIFF to SE enter ============
2268 00:56:08.105067 ============ LP4 DIFF to SE exit ============
2269 00:56:08.105126 [ANA_INIT] <<<<<<<<<<<<<
2270 00:56:08.105176 [Flow] Enable top DCM control >>>>>
2271 00:56:08.105225 [Flow] Enable top DCM control <<<<<
2272 00:56:08.105280 Enable DLL master slave shuffle
2273 00:56:08.105352 ==============================================================
2274 00:56:08.105428 Gating Mode config
2275 00:56:08.105505 ==============================================================
2276 00:56:08.105594 Config description:
2277 00:56:08.105672 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2278 00:56:08.105757 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2279 00:56:08.106037 SELPH_MODE 0: By rank 1: By Phase
2280 00:56:08.106119 ==============================================================
2281 00:56:08.106204 GAT_TRACK_EN = 1
2282 00:56:08.106286 RX_GATING_MODE = 2
2283 00:56:08.106380 RX_GATING_TRACK_MODE = 2
2284 00:56:08.106476 SELPH_MODE = 1
2285 00:56:08.106564 PICG_EARLY_EN = 1
2286 00:56:08.106641 VALID_LAT_VALUE = 1
2287 00:56:08.106717 ==============================================================
2288 00:56:08.106807 Enter into Gating configuration >>>>
2289 00:56:08.106913 Exit from Gating configuration <<<<
2290 00:56:08.107004 Enter into DVFS_PRE_config >>>>>
2291 00:56:08.107095 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2292 00:56:08.107173 Exit from DVFS_PRE_config <<<<<
2293 00:56:08.107262 Enter into PICG configuration >>>>
2294 00:56:08.107339 Exit from PICG configuration <<<<
2295 00:56:08.107420 [RX_INPUT] configuration >>>>>
2296 00:56:08.107496 [RX_INPUT] configuration <<<<<
2297 00:56:08.107579 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2298 00:56:08.107665 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2299 00:56:08.107725 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2300 00:56:08.107781 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2301 00:56:08.107830 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2302 00:56:08.107879 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2303 00:56:08.107928 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2304 00:56:08.107977 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2305 00:56:08.108032 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2306 00:56:08.108101 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2307 00:56:08.108179 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2308 00:56:08.108261 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2309 00:56:08.108349 ===================================
2310 00:56:08.108429 LPDDR4 DRAM CONFIGURATION
2311 00:56:08.108518 ===================================
2312 00:56:08.108613 EX_ROW_EN[0] = 0x0
2313 00:56:08.108706 EX_ROW_EN[1] = 0x0
2314 00:56:08.108763 LP4Y_EN = 0x0
2315 00:56:08.108813 WORK_FSP = 0x0
2316 00:56:08.108861 WL = 0x4
2317 00:56:08.108927 RL = 0x4
2318 00:56:08.109007 BL = 0x2
2319 00:56:08.109089 RPST = 0x0
2320 00:56:08.109170 RD_PRE = 0x0
2321 00:56:08.109246 WR_PRE = 0x1
2322 00:56:08.109327 WR_PST = 0x0
2323 00:56:08.109410 DBI_WR = 0x0
2324 00:56:08.109486 DBI_RD = 0x0
2325 00:56:08.109573 OTF = 0x1
2326 00:56:08.109649 ===================================
2327 00:56:08.109729 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2328 00:56:08.109819 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2329 00:56:08.109897 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2330 00:56:08.109973 ===================================
2331 00:56:08.110061 LPDDR4 DRAM CONFIGURATION
2332 00:56:08.110137 ===================================
2333 00:56:08.110253 EX_ROW_EN[0] = 0x10
2334 00:56:08.110351 EX_ROW_EN[1] = 0x0
2335 00:56:08.110436 LP4Y_EN = 0x0
2336 00:56:08.110539 WORK_FSP = 0x0
2337 00:56:08.110671 WL = 0x4
2338 00:56:08.110760 RL = 0x4
2339 00:56:08.110893 BL = 0x2
2340 00:56:08.111006 RPST = 0x0
2341 00:56:08.111106 RD_PRE = 0x0
2342 00:56:08.111181 WR_PRE = 0x1
2343 00:56:08.111267 WR_PST = 0x0
2344 00:56:08.111343 DBI_WR = 0x0
2345 00:56:08.111418 DBI_RD = 0x0
2346 00:56:08.111506 OTF = 0x1
2347 00:56:08.111589 ===================================
2348 00:56:08.111667 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2349 00:56:08.111765 ==
2350 00:56:08.111857 Dram Type= 6, Freq= 0, CH_0, rank 0
2351 00:56:08.111937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2352 00:56:08.111988 ==
2353 00:56:08.112044 [Duty_Offset_Calibration]
2354 00:56:08.112096 B0:2 B1:0 CA:3
2355 00:56:08.112182
2356 00:56:08.112264 [DutyScan_Calibration_Flow] k_type=0
2357 00:56:08.112358
2358 00:56:08.112451 ==CLK 0==
2359 00:56:08.112537 Final CLK duty delay cell = 0
2360 00:56:08.112615 [0] MAX Duty = 5062%(X100), DQS PI = 12
2361 00:56:08.112720 [0] MIN Duty = 4906%(X100), DQS PI = 54
2362 00:56:08.112817 [0] AVG Duty = 4984%(X100)
2363 00:56:08.112892
2364 00:56:08.112969 CH0 CLK Duty spec in!! Max-Min= 156%
2365 00:56:08.113055 [DutyScan_Calibration_Flow] ====Done====
2366 00:56:08.113130
2367 00:56:08.113245 [DutyScan_Calibration_Flow] k_type=1
2368 00:56:08.113327
2369 00:56:08.113408 ==DQS 0 ==
2370 00:56:08.113484 Final DQS duty delay cell = 0
2371 00:56:08.113573 [0] MAX Duty = 5062%(X100), DQS PI = 28
2372 00:56:08.113655 [0] MIN Duty = 4907%(X100), DQS PI = 2
2373 00:56:08.113732 [0] AVG Duty = 4984%(X100)
2374 00:56:08.113812
2375 00:56:08.113897 ==DQS 1 ==
2376 00:56:08.113972 Final DQS duty delay cell = -4
2377 00:56:08.114094 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2378 00:56:08.114171 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2379 00:56:08.114245 [-4] AVG Duty = 4938%(X100)
2380 00:56:08.114294
2381 00:56:08.114341 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2382 00:56:08.114399
2383 00:56:08.114457 CH0 DQS 1 Duty spec in!! Max-Min= 62%
2384 00:56:08.114515 [DutyScan_Calibration_Flow] ====Done====
2385 00:56:08.114591
2386 00:56:08.114674 [DutyScan_Calibration_Flow] k_type=3
2387 00:56:08.114755
2388 00:56:08.114829 ==DQM 0 ==
2389 00:56:08.114936 Final DQM duty delay cell = 0
2390 00:56:08.115050 [0] MAX Duty = 5124%(X100), DQS PI = 28
2391 00:56:08.115135 [0] MIN Duty = 4876%(X100), DQS PI = 0
2392 00:56:08.115224 [0] AVG Duty = 5000%(X100)
2393 00:56:08.115321
2394 00:56:08.115408 ==DQM 1 ==
2395 00:56:08.115485 Final DQM duty delay cell = 4
2396 00:56:08.115566 [4] MAX Duty = 5093%(X100), DQS PI = 0
2397 00:56:08.115648 [4] MIN Duty = 5000%(X100), DQS PI = 12
2398 00:56:08.115724 [4] AVG Duty = 5046%(X100)
2399 00:56:08.115824
2400 00:56:08.115872 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2401 00:56:08.115938
2402 00:56:08.116014 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2403 00:56:08.116092 [DutyScan_Calibration_Flow] ====Done====
2404 00:56:08.116182
2405 00:56:08.116266 [DutyScan_Calibration_Flow] k_type=2
2406 00:56:08.116340
2407 00:56:08.116427 ==DQ 0 ==
2408 00:56:08.116504 Final DQ duty delay cell = -4
2409 00:56:08.116580 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2410 00:56:08.116712 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2411 00:56:08.116989 [-4] AVG Duty = 4969%(X100)
2412 00:56:08.117076
2413 00:56:08.117158 ==DQ 1 ==
2414 00:56:08.117235 Final DQ duty delay cell = -4
2415 00:56:08.117311 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2416 00:56:08.117390 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2417 00:56:08.117476 [-4] AVG Duty = 4922%(X100)
2418 00:56:08.117553
2419 00:56:08.117637 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2420 00:56:08.117714
2421 00:56:08.117764 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2422 00:56:08.117811 [DutyScan_Calibration_Flow] ====Done====
2423 00:56:08.117859 ==
2424 00:56:08.117906 Dram Type= 6, Freq= 0, CH_1, rank 0
2425 00:56:08.117953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2426 00:56:08.118007 ==
2427 00:56:08.118055 [Duty_Offset_Calibration]
2428 00:56:08.118102 B0:1 B1:-2 CA:0
2429 00:56:08.118148
2430 00:56:08.118195 [DutyScan_Calibration_Flow] k_type=0
2431 00:56:08.118243
2432 00:56:08.118290 ==CLK 0==
2433 00:56:08.118337 Final CLK duty delay cell = 0
2434 00:56:08.118391 [0] MAX Duty = 5031%(X100), DQS PI = 18
2435 00:56:08.118438 [0] MIN Duty = 4875%(X100), DQS PI = 58
2436 00:56:08.118485 [0] AVG Duty = 4953%(X100)
2437 00:56:08.118531
2438 00:56:08.118577 CH1 CLK Duty spec in!! Max-Min= 156%
2439 00:56:08.118624 [DutyScan_Calibration_Flow] ====Done====
2440 00:56:08.118671
2441 00:56:08.118718 [DutyScan_Calibration_Flow] k_type=1
2442 00:56:08.118771
2443 00:56:08.118818 ==DQS 0 ==
2444 00:56:08.118865 Final DQS duty delay cell = -4
2445 00:56:08.118913 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2446 00:56:08.118961 [-4] MIN Duty = 4876%(X100), DQS PI = 52
2447 00:56:08.119015 [-4] AVG Duty = 4938%(X100)
2448 00:56:08.119062
2449 00:56:08.119109 ==DQS 1 ==
2450 00:56:08.119156 Final DQS duty delay cell = 0
2451 00:56:08.119203 [0] MAX Duty = 5093%(X100), DQS PI = 0
2452 00:56:08.119250 [0] MIN Duty = 4875%(X100), DQS PI = 26
2453 00:56:08.119312 [0] AVG Duty = 4984%(X100)
2454 00:56:08.119387
2455 00:56:08.119462 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2456 00:56:08.119542
2457 00:56:08.119617 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2458 00:56:08.119692 [DutyScan_Calibration_Flow] ====Done====
2459 00:56:08.119771
2460 00:56:08.119846 [DutyScan_Calibration_Flow] k_type=3
2461 00:56:08.119921
2462 00:56:08.119994 ==DQM 0 ==
2463 00:56:08.120075 Final DQM duty delay cell = 0
2464 00:56:08.120151 [0] MAX Duty = 5000%(X100), DQS PI = 24
2465 00:56:08.120226 [0] MIN Duty = 4876%(X100), DQS PI = 4
2466 00:56:08.120307 [0] AVG Duty = 4938%(X100)
2467 00:56:08.120381
2468 00:56:08.120459 ==DQM 1 ==
2469 00:56:08.120548 Final DQM duty delay cell = 0
2470 00:56:08.120625 [0] MAX Duty = 5031%(X100), DQS PI = 36
2471 00:56:08.120727 [0] MIN Duty = 4907%(X100), DQS PI = 2
2472 00:56:08.120784 [0] AVG Duty = 4969%(X100)
2473 00:56:08.120833
2474 00:56:08.120881 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2475 00:56:08.120928
2476 00:56:08.120975 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2477 00:56:08.121029 [DutyScan_Calibration_Flow] ====Done====
2478 00:56:08.121077
2479 00:56:08.121123 [DutyScan_Calibration_Flow] k_type=2
2480 00:56:08.121171
2481 00:56:08.121218 ==DQ 0 ==
2482 00:56:08.121270 Final DQ duty delay cell = 0
2483 00:56:08.121319 [0] MAX Duty = 5062%(X100), DQS PI = 12
2484 00:56:08.121367 [0] MIN Duty = 4938%(X100), DQS PI = 54
2485 00:56:08.121414 [0] AVG Duty = 5000%(X100)
2486 00:56:08.121460
2487 00:56:08.121507 ==DQ 1 ==
2488 00:56:08.121560 Final DQ duty delay cell = 0
2489 00:56:08.121609 [0] MAX Duty = 5125%(X100), DQS PI = 36
2490 00:56:08.121656 [0] MIN Duty = 4938%(X100), DQS PI = 26
2491 00:56:08.121702 [0] AVG Duty = 5031%(X100)
2492 00:56:08.121754
2493 00:56:08.121803 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2494 00:56:08.121850
2495 00:56:08.121896 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2496 00:56:08.121943 [DutyScan_Calibration_Flow] ====Done====
2497 00:56:08.121990 nWR fixed to 30
2498 00:56:08.122043 [ModeRegInit_LP4] CH0 RK0
2499 00:56:08.122089 [ModeRegInit_LP4] CH0 RK1
2500 00:56:08.122135 [ModeRegInit_LP4] CH1 RK0
2501 00:56:08.122183 [ModeRegInit_LP4] CH1 RK1
2502 00:56:08.122230 match AC timing 7
2503 00:56:08.122283 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2504 00:56:08.122331 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2505 00:56:08.122378 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2506 00:56:08.122434 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2507 00:56:08.122488 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2508 00:56:08.122543 ==
2509 00:56:08.122590 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 00:56:08.122637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 00:56:08.122685 ==
2512 00:56:08.122732 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2513 00:56:08.122785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2514 00:56:08.122834 [CA 0] Center 40 (10~71) winsize 62
2515 00:56:08.122882 [CA 1] Center 39 (9~70) winsize 62
2516 00:56:08.122934 [CA 2] Center 36 (6~66) winsize 61
2517 00:56:08.122983 [CA 3] Center 35 (5~66) winsize 62
2518 00:56:08.123060 [CA 4] Center 34 (4~65) winsize 62
2519 00:56:08.123109 [CA 5] Center 33 (3~63) winsize 61
2520 00:56:08.123156
2521 00:56:08.123222 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2522 00:56:08.123277
2523 00:56:08.123332 [CATrainingPosCal] consider 1 rank data
2524 00:56:08.123421 u2DelayCellTimex100 = 270/100 ps
2525 00:56:08.123511 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2526 00:56:08.123588 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2527 00:56:08.123668 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2528 00:56:08.123723 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2529 00:56:08.123778 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2530 00:56:08.123826 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2531 00:56:08.123896
2532 00:56:08.123946 CA PerBit enable=1, Macro0, CA PI delay=33
2533 00:56:08.123993
2534 00:56:08.124072 [CBTSetCACLKResult] CA Dly = 33
2535 00:56:08.124148 CS Dly: 7 (0~38)
2536 00:56:08.124222 ==
2537 00:56:08.124317 Dram Type= 6, Freq= 0, CH_0, rank 1
2538 00:56:08.124398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 00:56:08.124476 ==
2540 00:56:08.124567 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2541 00:56:08.124648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2542 00:56:08.124771 [CA 0] Center 40 (10~70) winsize 61
2543 00:56:08.124849 [CA 1] Center 40 (10~70) winsize 61
2544 00:56:08.124926 [CA 2] Center 35 (5~66) winsize 62
2545 00:56:08.124976 [CA 3] Center 35 (5~66) winsize 62
2546 00:56:08.125029 [CA 4] Center 34 (4~65) winsize 62
2547 00:56:08.125085 [CA 5] Center 33 (3~63) winsize 61
2548 00:56:08.125143
2549 00:56:08.125210 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2550 00:56:08.125259
2551 00:56:08.125313 [CATrainingPosCal] consider 2 rank data
2552 00:56:08.125361 u2DelayCellTimex100 = 270/100 ps
2553 00:56:08.125408 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2554 00:56:08.125649 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2555 00:56:08.125729 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2556 00:56:08.125828 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2557 00:56:08.125906 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2558 00:56:08.125981 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2559 00:56:08.126069
2560 00:56:08.126145 CA PerBit enable=1, Macro0, CA PI delay=33
2561 00:56:08.126229
2562 00:56:08.126310 [CBTSetCACLKResult] CA Dly = 33
2563 00:56:08.126391 CS Dly: 7 (0~39)
2564 00:56:08.126482
2565 00:56:08.126564 ----->DramcWriteLeveling(PI) begin...
2566 00:56:08.126647 ==
2567 00:56:08.126723 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 00:56:08.126806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 00:56:08.126895 ==
2570 00:56:08.126971 Write leveling (Byte 0): 33 => 33
2571 00:56:08.127060 Write leveling (Byte 1): 29 => 29
2572 00:56:08.127136 DramcWriteLeveling(PI) end<-----
2573 00:56:08.127212
2574 00:56:08.127281 ==
2575 00:56:08.127348 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 00:56:08.127397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 00:56:08.127445 ==
2578 00:56:08.127505 [Gating] SW mode calibration
2579 00:56:08.127585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2580 00:56:08.127661 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2581 00:56:08.127749 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 00:56:08.127832 0 15 4 | B1->B0 | 2929 3333 | 1 1 | (0 0) (1 1)
2583 00:56:08.127916 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 00:56:08.127992 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 00:56:08.128084 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 00:56:08.128166 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 00:56:08.128248 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 00:56:08.128333 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
2589 00:56:08.128419 1 0 0 | B1->B0 | 3131 2525 | 0 0 | (0 0) (0 0)
2590 00:56:08.128504 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2591 00:56:08.128592 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 00:56:08.128706 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 00:56:08.128791 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 00:56:08.128866 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 00:56:08.128960 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 00:56:08.129045 1 0 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2597 00:56:08.129121 1 1 0 | B1->B0 | 2929 3838 | 0 0 | (0 0) (0 0)
2598 00:56:08.129210 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2599 00:56:08.129288 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 00:56:08.129363 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 00:56:08.129456 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 00:56:08.129533 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 00:56:08.129618 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 00:56:08.129701 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2605 00:56:08.129780 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2606 00:56:08.129869 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2607 00:56:08.129953 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 00:56:08.130033 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 00:56:08.130119 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 00:56:08.130201 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 00:56:08.130287 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 00:56:08.130364 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 00:56:08.130458 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 00:56:08.130536 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 00:56:08.130611 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 00:56:08.130707 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 00:56:08.130788 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 00:56:08.130863 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 00:56:08.130943 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2620 00:56:08.130993 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 00:56:08.131040 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2622 00:56:08.131093 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 00:56:08.131183 Total UI for P1: 0, mck2ui 16
2624 00:56:08.131259 best dqsien dly found for B0: ( 1, 4, 0)
2625 00:56:08.131344 Total UI for P1: 0, mck2ui 16
2626 00:56:08.131430 best dqsien dly found for B1: ( 1, 4, 2)
2627 00:56:08.131516 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2628 00:56:08.131602 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2629 00:56:08.131684
2630 00:56:08.131759 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2631 00:56:08.131835 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2632 00:56:08.131922 [Gating] SW calibration Done
2633 00:56:08.132010 ==
2634 00:56:08.132086 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 00:56:08.132174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 00:56:08.132243 ==
2637 00:56:08.132292 RX Vref Scan: 0
2638 00:56:08.132339
2639 00:56:08.132399 RX Vref 0 -> 0, step: 1
2640 00:56:08.132483
2641 00:56:08.132558 RX Delay -40 -> 252, step: 8
2642 00:56:08.132654 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2643 00:56:08.132768 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2644 00:56:08.132863 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2645 00:56:08.132940 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2646 00:56:08.133030 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2647 00:56:08.133108 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2648 00:56:08.133185 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2649 00:56:08.133280 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2650 00:56:08.133357 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2651 00:56:08.133442 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2652 00:56:08.133524 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2653 00:56:08.133608 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2654 00:56:08.133692 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2655 00:56:08.133781 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2656 00:56:08.134046 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2657 00:56:08.134137 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2658 00:56:08.134213 ==
2659 00:56:08.134304 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 00:56:08.134382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 00:56:08.134470 ==
2662 00:56:08.134559 DQS Delay:
2663 00:56:08.134638 DQS0 = 0, DQS1 = 0
2664 00:56:08.134716 DQM Delay:
2665 00:56:08.134788 DQM0 = 112, DQM1 = 103
2666 00:56:08.134838 DQ Delay:
2667 00:56:08.134886 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2668 00:56:08.134933 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2669 00:56:08.134982 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2670 00:56:08.135036 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2671 00:56:08.135083
2672 00:56:08.135129
2673 00:56:08.135176 ==
2674 00:56:08.135223 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 00:56:08.135277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 00:56:08.135325 ==
2677 00:56:08.135372
2678 00:56:08.135458
2679 00:56:08.135512 TX Vref Scan disable
2680 00:56:08.135561 == TX Byte 0 ==
2681 00:56:08.135608 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2682 00:56:08.135665 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2683 00:56:08.135718 == TX Byte 1 ==
2684 00:56:08.135773 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2685 00:56:08.135822 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2686 00:56:08.135869 ==
2687 00:56:08.135916 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 00:56:08.135964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 00:56:08.136016 ==
2690 00:56:08.136064 TX Vref=22, minBit 4, minWin=25, winSum=419
2691 00:56:08.136112 TX Vref=24, minBit 0, minWin=26, winSum=424
2692 00:56:08.136159 TX Vref=26, minBit 1, minWin=26, winSum=428
2693 00:56:08.136207 TX Vref=28, minBit 7, minWin=26, winSum=431
2694 00:56:08.136259 TX Vref=30, minBit 2, minWin=26, winSum=433
2695 00:56:08.136308 TX Vref=32, minBit 2, minWin=26, winSum=431
2696 00:56:08.136355 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 30
2697 00:56:08.136407
2698 00:56:08.136464 Final TX Range 1 Vref 30
2699 00:56:08.136523
2700 00:56:08.136610 ==
2701 00:56:08.136711 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 00:56:08.136805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 00:56:08.136856 ==
2704 00:56:08.136903
2705 00:56:08.136957
2706 00:56:08.137007 TX Vref Scan disable
2707 00:56:08.137083 == TX Byte 0 ==
2708 00:56:08.137132 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2709 00:56:08.137180 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2710 00:56:08.137251 == TX Byte 1 ==
2711 00:56:08.137334 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2712 00:56:08.137415 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2713 00:56:08.137481
2714 00:56:08.137535 [DATLAT]
2715 00:56:08.137583 Freq=1200, CH0 RK0
2716 00:56:08.137651
2717 00:56:08.137700 DATLAT Default: 0xd
2718 00:56:08.137747 0, 0xFFFF, sum = 0
2719 00:56:08.137828 1, 0xFFFF, sum = 0
2720 00:56:08.137884 2, 0xFFFF, sum = 0
2721 00:56:08.137946 3, 0xFFFF, sum = 0
2722 00:56:08.137994 4, 0xFFFF, sum = 0
2723 00:56:08.138048 5, 0xFFFF, sum = 0
2724 00:56:08.138134 6, 0xFFFF, sum = 0
2725 00:56:08.138211 7, 0xFFFF, sum = 0
2726 00:56:08.138305 8, 0xFFFF, sum = 0
2727 00:56:08.138383 9, 0xFFFF, sum = 0
2728 00:56:08.138476 10, 0xFFFF, sum = 0
2729 00:56:08.138536 11, 0xFFFF, sum = 0
2730 00:56:08.138585 12, 0x0, sum = 1
2731 00:56:08.138633 13, 0x0, sum = 2
2732 00:56:08.138710 14, 0x0, sum = 3
2733 00:56:08.138783 15, 0x0, sum = 4
2734 00:56:08.138832 best_step = 13
2735 00:56:08.138884
2736 00:56:08.138945 ==
2737 00:56:08.138996 Dram Type= 6, Freq= 0, CH_0, rank 0
2738 00:56:08.139044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2739 00:56:08.139092 ==
2740 00:56:08.139161 RX Vref Scan: 1
2741 00:56:08.139211
2742 00:56:08.139265 Set Vref Range= 32 -> 127
2743 00:56:08.139331
2744 00:56:08.139380 RX Vref 32 -> 127, step: 1
2745 00:56:08.139428
2746 00:56:08.139475 RX Delay -37 -> 252, step: 4
2747 00:56:08.139549
2748 00:56:08.139612 Set Vref, RX VrefLevel [Byte0]: 32
2749 00:56:08.139695 [Byte1]: 32
2750 00:56:08.139773
2751 00:56:08.139858 Set Vref, RX VrefLevel [Byte0]: 33
2752 00:56:08.139939 [Byte1]: 33
2753 00:56:08.140027
2754 00:56:08.140103 Set Vref, RX VrefLevel [Byte0]: 34
2755 00:56:08.140185 [Byte1]: 34
2756 00:56:08.140267
2757 00:56:08.140344 Set Vref, RX VrefLevel [Byte0]: 35
2758 00:56:08.140434 [Byte1]: 35
2759 00:56:08.140520
2760 00:56:08.140629 Set Vref, RX VrefLevel [Byte0]: 36
2761 00:56:08.140733 [Byte1]: 36
2762 00:56:08.140840
2763 00:56:08.140916 Set Vref, RX VrefLevel [Byte0]: 37
2764 00:56:08.140965 [Byte1]: 37
2765 00:56:08.141013
2766 00:56:08.141100 Set Vref, RX VrefLevel [Byte0]: 38
2767 00:56:08.141157 [Byte1]: 38
2768 00:56:08.141205
2769 00:56:08.141253 Set Vref, RX VrefLevel [Byte0]: 39
2770 00:56:08.141324 [Byte1]: 39
2771 00:56:08.141378
2772 00:56:08.141427 Set Vref, RX VrefLevel [Byte0]: 40
2773 00:56:08.141497 [Byte1]: 40
2774 00:56:08.141546
2775 00:56:08.141593 Set Vref, RX VrefLevel [Byte0]: 41
2776 00:56:08.141658 [Byte1]: 41
2777 00:56:08.141728
2778 00:56:08.141779 Set Vref, RX VrefLevel [Byte0]: 42
2779 00:56:08.141826 [Byte1]: 42
2780 00:56:08.141879
2781 00:56:08.141950 Set Vref, RX VrefLevel [Byte0]: 43
2782 00:56:08.142001 [Byte1]: 43
2783 00:56:08.142048
2784 00:56:08.142097 Set Vref, RX VrefLevel [Byte0]: 44
2785 00:56:08.142171 [Byte1]: 44
2786 00:56:08.142220
2787 00:56:08.142267 Set Vref, RX VrefLevel [Byte0]: 45
2788 00:56:08.142338 [Byte1]: 45
2789 00:56:08.142393
2790 00:56:08.142442 Set Vref, RX VrefLevel [Byte0]: 46
2791 00:56:08.142500 [Byte1]: 46
2792 00:56:08.142559
2793 00:56:08.142629 Set Vref, RX VrefLevel [Byte0]: 47
2794 00:56:08.142679 [Byte1]: 47
2795 00:56:08.142727
2796 00:56:08.142801 Set Vref, RX VrefLevel [Byte0]: 48
2797 00:56:08.142861 [Byte1]: 48
2798 00:56:08.142926
2799 00:56:08.143004 Set Vref, RX VrefLevel [Byte0]: 49
2800 00:56:08.143054 [Byte1]: 49
2801 00:56:08.143101
2802 00:56:08.143174 Set Vref, RX VrefLevel [Byte0]: 50
2803 00:56:08.143225 [Byte1]: 50
2804 00:56:08.143289
2805 00:56:08.143381 Set Vref, RX VrefLevel [Byte0]: 51
2806 00:56:08.143469 [Byte1]: 51
2807 00:56:08.143545
2808 00:56:08.143633 Set Vref, RX VrefLevel [Byte0]: 52
2809 00:56:08.143711 [Byte1]: 52
2810 00:56:08.143786
2811 00:56:08.143873 Set Vref, RX VrefLevel [Byte0]: 53
2812 00:56:08.143956 [Byte1]: 53
2813 00:56:08.144041
2814 00:56:08.144117 Set Vref, RX VrefLevel [Byte0]: 54
2815 00:56:08.144207 [Byte1]: 54
2816 00:56:08.144288
2817 00:56:08.144369 Set Vref, RX VrefLevel [Byte0]: 55
2818 00:56:08.144457 [Byte1]: 55
2819 00:56:08.144541
2820 00:56:08.144616 Set Vref, RX VrefLevel [Byte0]: 56
2821 00:56:08.144739 [Byte1]: 56
2822 00:56:08.144794
2823 00:56:08.145048 Set Vref, RX VrefLevel [Byte0]: 57
2824 00:56:08.145134 [Byte1]: 57
2825 00:56:08.145219
2826 00:56:08.145301 Set Vref, RX VrefLevel [Byte0]: 58
2827 00:56:08.145376 [Byte1]: 58
2828 00:56:08.145426
2829 00:56:08.145473 Set Vref, RX VrefLevel [Byte0]: 59
2830 00:56:08.145536 [Byte1]: 59
2831 00:56:08.145596
2832 00:56:08.145643 Set Vref, RX VrefLevel [Byte0]: 60
2833 00:56:08.145689 [Byte1]: 60
2834 00:56:08.145765
2835 00:56:08.145815 Set Vref, RX VrefLevel [Byte0]: 61
2836 00:56:08.145863 [Byte1]: 61
2837 00:56:08.145920
2838 00:56:08.145981 Set Vref, RX VrefLevel [Byte0]: 62
2839 00:56:08.146049 [Byte1]: 62
2840 00:56:08.146098
2841 00:56:08.146145 Set Vref, RX VrefLevel [Byte0]: 63
2842 00:56:08.146192 [Byte1]: 63
2843 00:56:08.146239
2844 00:56:08.146292 Set Vref, RX VrefLevel [Byte0]: 64
2845 00:56:08.146340 [Byte1]: 64
2846 00:56:08.146402
2847 00:56:08.146456 Set Vref, RX VrefLevel [Byte0]: 65
2848 00:56:08.146503 [Byte1]: 65
2849 00:56:08.146567
2850 00:56:08.146631 Set Vref, RX VrefLevel [Byte0]: 66
2851 00:56:08.146687 [Byte1]: 66
2852 00:56:08.146735
2853 00:56:08.146789 Set Vref, RX VrefLevel [Byte0]: 67
2854 00:56:08.146861 [Byte1]: 67
2855 00:56:08.146914
2856 00:56:08.146961 Set Vref, RX VrefLevel [Byte0]: 68
2857 00:56:08.147026 [Byte1]: 68
2858 00:56:08.147077
2859 00:56:08.147125 Set Vref, RX VrefLevel [Byte0]: 69
2860 00:56:08.147173 [Byte1]: 69
2861 00:56:08.147219
2862 00:56:08.147284 Set Vref, RX VrefLevel [Byte0]: 70
2863 00:56:08.147340 [Byte1]: 70
2864 00:56:08.147388
2865 00:56:08.147435 Set Vref, RX VrefLevel [Byte0]: 71
2866 00:56:08.147530 [Byte1]: 71
2867 00:56:08.147606
2868 00:56:08.147693 Set Vref, RX VrefLevel [Byte0]: 72
2869 00:56:08.147774 [Byte1]: 72
2870 00:56:08.147860
2871 00:56:08.147945 Set Vref, RX VrefLevel [Byte0]: 73
2872 00:56:08.148028 [Byte1]: 73
2873 00:56:08.148110
2874 00:56:08.148197 Set Vref, RX VrefLevel [Byte0]: 74
2875 00:56:08.148278 [Byte1]: 74
2876 00:56:08.148367
2877 00:56:08.148446 Final RX Vref Byte 0 = 61 to rank0
2878 00:56:08.148538 Final RX Vref Byte 1 = 52 to rank0
2879 00:56:08.148641 Final RX Vref Byte 0 = 61 to rank1
2880 00:56:08.148740 Final RX Vref Byte 1 = 52 to rank1==
2881 00:56:08.148838 Dram Type= 6, Freq= 0, CH_0, rank 0
2882 00:56:08.148916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 00:56:08.149005 ==
2884 00:56:08.149058 DQS Delay:
2885 00:56:08.149107 DQS0 = 0, DQS1 = 0
2886 00:56:08.149166 DQM Delay:
2887 00:56:08.149224 DQM0 = 112, DQM1 = 101
2888 00:56:08.149278 DQ Delay:
2889 00:56:08.149326 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =108
2890 00:56:08.149374 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2891 00:56:08.149435 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2892 00:56:08.149488 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2893 00:56:08.149543
2894 00:56:08.149590
2895 00:56:08.149665 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2896 00:56:08.149717 CH0 RK0: MR19=303, MR18=FDFD
2897 00:56:08.149771 CH0_RK0: MR19=0x303, MR18=0xFDFD, DQSOSC=411, MR23=63, INC=38, DEC=25
2898 00:56:08.149849
2899 00:56:08.149899 ----->DramcWriteLeveling(PI) begin...
2900 00:56:08.149948 ==
2901 00:56:08.149995 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 00:56:08.150057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 00:56:08.150122 ==
2904 00:56:08.150170 Write leveling (Byte 0): 32 => 32
2905 00:56:08.150218 Write leveling (Byte 1): 29 => 29
2906 00:56:08.150314 DramcWriteLeveling(PI) end<-----
2907 00:56:08.150369
2908 00:56:08.150438 ==
2909 00:56:08.150485 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 00:56:08.150539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 00:56:08.150605 ==
2912 00:56:08.150655 [Gating] SW mode calibration
2913 00:56:08.150703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2914 00:56:08.150751 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2915 00:56:08.150813 0 15 0 | B1->B0 | 2a2a 3434 | 1 0 | (0 0) (0 0)
2916 00:56:08.150862 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 00:56:08.150910 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 00:56:08.150956 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 00:56:08.151036 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 00:56:08.151085 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 00:56:08.151133 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2922 00:56:08.151211 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2923 00:56:08.151274 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2924 00:56:08.151324 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 00:56:08.151371 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 00:56:08.151454 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 00:56:08.151537 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 00:56:08.151624 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 00:56:08.151701 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2930 00:56:08.151789 1 0 28 | B1->B0 | 2424 4141 | 0 0 | (0 0) (0 0)
2931 00:56:08.151875 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2932 00:56:08.151954 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 00:56:08.152035 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 00:56:08.152123 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 00:56:08.152200 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 00:56:08.152294 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 00:56:08.152372 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 00:56:08.152454 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2939 00:56:08.152569 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2940 00:56:08.152657 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 00:56:08.152737 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 00:56:08.152799 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 00:56:08.152853 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 00:56:08.152916 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 00:56:08.153162 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 00:56:08.153243 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 00:56:08.153325 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 00:56:08.153416 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 00:56:08.153493 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 00:56:08.153585 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 00:56:08.153657 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 00:56:08.153706 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 00:56:08.153754 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2954 00:56:08.153808 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2955 00:56:08.153855 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2956 00:56:08.153933 Total UI for P1: 0, mck2ui 16
2957 00:56:08.153984 best dqsien dly found for B0: ( 1, 3, 26)
2958 00:56:08.154038 Total UI for P1: 0, mck2ui 16
2959 00:56:08.154086 best dqsien dly found for B1: ( 1, 3, 30)
2960 00:56:08.154134 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2961 00:56:08.154182 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2962 00:56:08.154230
2963 00:56:08.154313 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2964 00:56:08.154363 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2965 00:56:08.154410 [Gating] SW calibration Done
2966 00:56:08.154481 ==
2967 00:56:08.154573 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 00:56:08.154652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 00:56:08.154740 ==
2970 00:56:08.154829 RX Vref Scan: 0
2971 00:56:08.154921
2972 00:56:08.154997 RX Vref 0 -> 0, step: 1
2973 00:56:08.155078
2974 00:56:08.155165 RX Delay -40 -> 252, step: 8
2975 00:56:08.155242 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2976 00:56:08.155318 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2977 00:56:08.155407 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2978 00:56:08.155483 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2979 00:56:08.155576 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2980 00:56:08.155652 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2981 00:56:08.155735 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2982 00:56:08.155826 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2983 00:56:08.155909 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2984 00:56:08.155986 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2985 00:56:08.156072 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2986 00:56:08.156153 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2987 00:56:08.156243 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2988 00:56:08.156319 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2989 00:56:08.156403 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2990 00:56:08.156493 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2991 00:56:08.156585 ==
2992 00:56:08.156714 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 00:56:08.156793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 00:56:08.156891 ==
2995 00:56:08.156967 DQS Delay:
2996 00:56:08.157060 DQS0 = 0, DQS1 = 0
2997 00:56:08.157174 DQM Delay:
2998 00:56:08.157255 DQM0 = 112, DQM1 = 101
2999 00:56:08.157342 DQ Delay:
3000 00:56:08.157417 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3001 00:56:08.157503 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
3002 00:56:08.270097 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3003 00:56:08.270210 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
3004 00:56:08.270271
3005 00:56:08.270326
3006 00:56:08.270383 ==
3007 00:56:08.270436 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 00:56:08.270499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 00:56:08.270559 ==
3010 00:56:08.270635
3011 00:56:08.270712
3012 00:56:08.270788 TX Vref Scan disable
3013 00:56:08.270872 == TX Byte 0 ==
3014 00:56:08.270956 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3015 00:56:08.271034 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3016 00:56:08.271120 == TX Byte 1 ==
3017 00:56:08.271204 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3018 00:56:08.271282 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3019 00:56:08.271348 ==
3020 00:56:08.271406 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 00:56:08.271457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 00:56:08.271517 ==
3023 00:56:08.271568 TX Vref=22, minBit 1, minWin=25, winSum=428
3024 00:56:08.271617 TX Vref=24, minBit 2, minWin=26, winSum=432
3025 00:56:08.271675 TX Vref=26, minBit 5, minWin=26, winSum=434
3026 00:56:08.271744 TX Vref=28, minBit 1, minWin=26, winSum=437
3027 00:56:08.271794 TX Vref=30, minBit 1, minWin=27, winSum=443
3028 00:56:08.271843 TX Vref=32, minBit 8, minWin=26, winSum=442
3029 00:56:08.271909 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 30
3030 00:56:08.271961
3031 00:56:08.272009 Final TX Range 1 Vref 30
3032 00:56:08.272057
3033 00:56:08.272105 ==
3034 00:56:08.272186 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 00:56:08.272263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 00:56:08.272339 ==
3037 00:56:08.272432
3038 00:56:08.272515
3039 00:56:08.272591 TX Vref Scan disable
3040 00:56:08.272706 == TX Byte 0 ==
3041 00:56:08.272772 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3042 00:56:08.272821 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3043 00:56:08.272886 == TX Byte 1 ==
3044 00:56:08.272939 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3045 00:56:08.272987 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3046 00:56:08.273034
3047 00:56:08.273098 [DATLAT]
3048 00:56:08.273168 Freq=1200, CH0 RK1
3049 00:56:08.273217
3050 00:56:08.273264 DATLAT Default: 0xd
3051 00:56:08.273313 0, 0xFFFF, sum = 0
3052 00:56:08.273377 1, 0xFFFF, sum = 0
3053 00:56:08.273428 2, 0xFFFF, sum = 0
3054 00:56:08.273476 3, 0xFFFF, sum = 0
3055 00:56:08.273543 4, 0xFFFF, sum = 0
3056 00:56:08.273594 5, 0xFFFF, sum = 0
3057 00:56:08.273649 6, 0xFFFF, sum = 0
3058 00:56:08.273709 7, 0xFFFF, sum = 0
3059 00:56:08.273761 8, 0xFFFF, sum = 0
3060 00:56:08.273844 9, 0xFFFF, sum = 0
3061 00:56:08.273921 10, 0xFFFF, sum = 0
3062 00:56:08.274006 11, 0xFFFF, sum = 0
3063 00:56:08.274083 12, 0x0, sum = 1
3064 00:56:08.274166 13, 0x0, sum = 2
3065 00:56:08.274246 14, 0x0, sum = 3
3066 00:56:08.274324 15, 0x0, sum = 4
3067 00:56:08.274409 best_step = 13
3068 00:56:08.274483
3069 00:56:08.274564 ==
3070 00:56:08.274650 Dram Type= 6, Freq= 0, CH_0, rank 1
3071 00:56:08.274727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 00:56:08.274817 ==
3073 00:56:08.274894 RX Vref Scan: 0
3074 00:56:08.274968
3075 00:56:08.275064 RX Vref 0 -> 0, step: 1
3076 00:56:08.275146
3077 00:56:08.275221 RX Delay -37 -> 252, step: 4
3078 00:56:08.275303 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3079 00:56:08.275380 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3080 00:56:08.275461 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3081 00:56:08.275547 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3082 00:56:08.275623 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3083 00:56:08.275906 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3084 00:56:08.276034 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3085 00:56:08.276120 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3086 00:56:08.276196 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3087 00:56:08.276283 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3088 00:56:08.276371 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3089 00:56:08.276449 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3090 00:56:08.276565 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3091 00:56:08.276651 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3092 00:56:08.276734 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3093 00:56:08.276814 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3094 00:56:08.276863 ==
3095 00:56:08.276920 Dram Type= 6, Freq= 0, CH_0, rank 1
3096 00:56:08.276972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 00:56:08.277026 ==
3098 00:56:08.277074 DQS Delay:
3099 00:56:08.277144 DQS0 = 0, DQS1 = 0
3100 00:56:08.277198 DQM Delay:
3101 00:56:08.277254 DQM0 = 111, DQM1 = 101
3102 00:56:08.277309 DQ Delay:
3103 00:56:08.277358 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3104 00:56:08.277406 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3105 00:56:08.277455 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =92
3106 00:56:08.277503 DQ12 =110, DQ13 =108, DQ14 =114, DQ15 =110
3107 00:56:08.277557
3108 00:56:08.277626
3109 00:56:08.277676 [DQSOSCAuto] RK1, (LSB)MR18= 0x1801, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 400 ps
3110 00:56:08.277726 CH0 RK1: MR19=404, MR18=1801
3111 00:56:08.277792 CH0_RK1: MR19=0x404, MR18=0x1801, DQSOSC=400, MR23=63, INC=40, DEC=27
3112 00:56:08.277860 [RxdqsGatingPostProcess] freq 1200
3113 00:56:08.277909 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3114 00:56:08.277958 best DQS0 dly(2T, 0.5T) = (0, 12)
3115 00:56:08.278032 best DQS1 dly(2T, 0.5T) = (0, 12)
3116 00:56:08.278102 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3117 00:56:08.278151 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3118 00:56:08.278203 best DQS0 dly(2T, 0.5T) = (0, 11)
3119 00:56:08.278285 best DQS1 dly(2T, 0.5T) = (0, 11)
3120 00:56:08.278361 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3121 00:56:08.278482 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3122 00:56:08.278559 Pre-setting of DQS Precalculation
3123 00:56:08.278635 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3124 00:56:08.278720 ==
3125 00:56:08.278838 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 00:56:08.278923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 00:56:08.278999 ==
3128 00:56:08.279084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3129 00:56:08.279205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3130 00:56:08.279282 [CA 0] Center 37 (8~67) winsize 60
3131 00:56:08.279374 [CA 1] Center 37 (7~68) winsize 62
3132 00:56:08.279482 [CA 2] Center 34 (4~64) winsize 61
3133 00:56:08.279569 [CA 3] Center 33 (3~64) winsize 62
3134 00:56:08.279645 [CA 4] Center 34 (4~64) winsize 61
3135 00:56:08.279728 [CA 5] Center 33 (3~63) winsize 61
3136 00:56:08.279855
3137 00:56:08.279937 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3138 00:56:08.280026
3139 00:56:08.280103 [CATrainingPosCal] consider 1 rank data
3140 00:56:08.280184 u2DelayCellTimex100 = 270/100 ps
3141 00:56:08.280263 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3142 00:56:08.280340 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3143 00:56:08.280431 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3144 00:56:08.280508 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3145 00:56:08.280584 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3146 00:56:08.280684 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3147 00:56:08.280755
3148 00:56:08.280805 CA PerBit enable=1, Macro0, CA PI delay=33
3149 00:56:08.280873
3150 00:56:08.280922 [CBTSetCACLKResult] CA Dly = 33
3151 00:56:08.280970 CS Dly: 6 (0~37)
3152 00:56:08.281038 ==
3153 00:56:08.281089 Dram Type= 6, Freq= 0, CH_1, rank 1
3154 00:56:08.281144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3155 00:56:08.281193 ==
3156 00:56:08.281241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3157 00:56:08.281311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3158 00:56:08.281363 [CA 0] Center 37 (7~67) winsize 61
3159 00:56:08.281412 [CA 1] Center 37 (7~68) winsize 62
3160 00:56:08.281468 [CA 2] Center 35 (5~65) winsize 61
3161 00:56:08.281530 [CA 3] Center 33 (3~64) winsize 62
3162 00:56:08.281578 [CA 4] Center 34 (4~64) winsize 61
3163 00:56:08.281626 [CA 5] Center 32 (2~63) winsize 62
3164 00:56:08.281696
3165 00:56:08.281764 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3166 00:56:08.281815
3167 00:56:08.281863 [CATrainingPosCal] consider 2 rank data
3168 00:56:08.281918 u2DelayCellTimex100 = 270/100 ps
3169 00:56:08.281996 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3170 00:56:08.282044 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3171 00:56:08.282092 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3172 00:56:08.282161 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3173 00:56:08.282212 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3174 00:56:08.282266 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3175 00:56:08.282323
3176 00:56:08.282412 CA PerBit enable=1, Macro0, CA PI delay=33
3177 00:56:08.282490
3178 00:56:08.282570 [CBTSetCACLKResult] CA Dly = 33
3179 00:56:08.282654 CS Dly: 7 (0~40)
3180 00:56:08.282729
3181 00:56:08.282814 ----->DramcWriteLeveling(PI) begin...
3182 00:56:08.282891 ==
3183 00:56:08.282977 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 00:56:08.283068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 00:56:08.283144 ==
3186 00:56:08.283228 Write leveling (Byte 0): 24 => 24
3187 00:56:08.283306 Write leveling (Byte 1): 27 => 27
3188 00:56:08.283391 DramcWriteLeveling(PI) end<-----
3189 00:56:08.283473
3190 00:56:08.283548 ==
3191 00:56:08.283632 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 00:56:08.283715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 00:56:08.283801 ==
3194 00:56:08.283885 [Gating] SW mode calibration
3195 00:56:08.283963 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3196 00:56:08.284052 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3197 00:56:08.284132 0 15 0 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (0 0)
3198 00:56:08.284208 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 00:56:08.284301 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 00:56:08.284379 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 00:56:08.284690 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 00:56:08.284779 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 00:56:08.284830 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 00:56:08.284880 0 15 28 | B1->B0 | 2d2d 3232 | 1 1 | (1 0) (1 0)
3205 00:56:08.284949 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 00:56:08.285004 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 00:56:08.285055 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 00:56:08.285117 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 00:56:08.285170 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 00:56:08.285218 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 00:56:08.285267 1 0 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3212 00:56:08.285339 1 0 28 | B1->B0 | 4242 3f3f | 0 0 | (0 0) (0 0)
3213 00:56:08.285396 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 00:56:08.285490 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 00:56:08.285553 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 00:56:08.285622 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 00:56:08.285671 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 00:56:08.285720 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 00:56:08.285774 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 00:56:08.285823 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3221 00:56:08.285872 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 00:56:08.285920 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 00:56:08.285985 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 00:56:08.286037 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 00:56:08.286085 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 00:56:08.286146 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 00:56:08.286213 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 00:56:08.286291 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 00:56:08.286367 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 00:56:08.286452 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 00:56:08.286535 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 00:56:08.286621 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 00:56:08.286698 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 00:56:08.286783 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 00:56:08.286871 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 00:56:08.286949 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3237 00:56:08.287027 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 00:56:08.287112 Total UI for P1: 0, mck2ui 16
3239 00:56:08.287196 best dqsien dly found for B0: ( 1, 3, 28)
3240 00:56:08.287281 Total UI for P1: 0, mck2ui 16
3241 00:56:08.287358 best dqsien dly found for B1: ( 1, 3, 28)
3242 00:56:08.287448 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3243 00:56:08.287537 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3244 00:56:08.287612
3245 00:56:08.287699 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3246 00:56:08.287779 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3247 00:56:08.287854 [Gating] SW calibration Done
3248 00:56:08.287946 ==
3249 00:56:08.288023 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 00:56:08.288107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 00:56:08.288198 ==
3252 00:56:08.288274 RX Vref Scan: 0
3253 00:56:08.288354
3254 00:56:08.288437 RX Vref 0 -> 0, step: 1
3255 00:56:08.288512
3256 00:56:08.288598 RX Delay -40 -> 252, step: 8
3257 00:56:08.288693 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3258 00:56:08.288778 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3259 00:56:08.288845 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3260 00:56:08.288901 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3261 00:56:08.288950 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3262 00:56:08.289020 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3263 00:56:08.289079 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3264 00:56:08.289128 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3265 00:56:08.289205 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3266 00:56:08.289257 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3267 00:56:08.289306 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3268 00:56:08.289359 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3269 00:56:08.289425 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3270 00:56:08.289474 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3271 00:56:08.289535 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3272 00:56:08.289586 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3273 00:56:08.289665 ==
3274 00:56:08.289743 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 00:56:08.289824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 00:56:08.289919 ==
3277 00:56:08.290005 DQS Delay:
3278 00:56:08.290081 DQS0 = 0, DQS1 = 0
3279 00:56:08.290192 DQM Delay:
3280 00:56:08.290283 DQM0 = 113, DQM1 = 105
3281 00:56:08.290370 DQ Delay:
3282 00:56:08.290453 DQ0 =115, DQ1 =107, DQ2 =103, DQ3 =111
3283 00:56:08.290532 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3284 00:56:08.290622 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3285 00:56:08.290700 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3286 00:56:08.290785
3287 00:56:08.290865
3288 00:56:08.290939 ==
3289 00:56:08.291025 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 00:56:08.291102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 00:56:08.291192 ==
3292 00:56:08.291277
3293 00:56:08.291353
3294 00:56:08.291442 TX Vref Scan disable
3295 00:56:08.291520 == TX Byte 0 ==
3296 00:56:08.291600 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3297 00:56:08.291680 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3298 00:56:08.291759 == TX Byte 1 ==
3299 00:56:08.291811 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3300 00:56:08.291859 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3301 00:56:08.291908 ==
3302 00:56:08.291956 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 00:56:08.292005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 00:56:08.292060 ==
3305 00:56:08.292109 TX Vref=22, minBit 8, minWin=24, winSum=401
3306 00:56:08.292158 TX Vref=24, minBit 11, minWin=24, winSum=412
3307 00:56:08.292207 TX Vref=26, minBit 11, minWin=24, winSum=417
3308 00:56:08.292256 TX Vref=28, minBit 9, minWin=25, winSum=424
3309 00:56:08.292492 TX Vref=30, minBit 9, minWin=24, winSum=419
3310 00:56:08.292547 TX Vref=32, minBit 9, minWin=24, winSum=415
3311 00:56:08.292596 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 28
3312 00:56:08.292702
3313 00:56:08.292800 Final TX Range 1 Vref 28
3314 00:56:08.292876
3315 00:56:08.292951 ==
3316 00:56:08.293032 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 00:56:08.293109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 00:56:08.293185 ==
3319 00:56:08.293260
3320 00:56:08.293335
3321 00:56:08.293416 TX Vref Scan disable
3322 00:56:08.293492 == TX Byte 0 ==
3323 00:56:08.293568 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3324 00:56:08.293644 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3325 00:56:08.293720 == TX Byte 1 ==
3326 00:56:08.293801 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3327 00:56:08.293878 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3328 00:56:08.293953
3329 00:56:08.294027 [DATLAT]
3330 00:56:08.294102 Freq=1200, CH1 RK0
3331 00:56:08.294183
3332 00:56:08.294258 DATLAT Default: 0xd
3333 00:56:08.294333 0, 0xFFFF, sum = 0
3334 00:56:08.294411 1, 0xFFFF, sum = 0
3335 00:56:08.294488 2, 0xFFFF, sum = 0
3336 00:56:08.294570 3, 0xFFFF, sum = 0
3337 00:56:08.294647 4, 0xFFFF, sum = 0
3338 00:56:08.294724 5, 0xFFFF, sum = 0
3339 00:56:08.294801 6, 0xFFFF, sum = 0
3340 00:56:08.294882 7, 0xFFFF, sum = 0
3341 00:56:08.294960 8, 0xFFFF, sum = 0
3342 00:56:08.295026 9, 0xFFFF, sum = 0
3343 00:56:08.295076 10, 0xFFFF, sum = 0
3344 00:56:08.295125 11, 0xFFFF, sum = 0
3345 00:56:08.295174 12, 0x0, sum = 1
3346 00:56:08.295222 13, 0x0, sum = 2
3347 00:56:08.295277 14, 0x0, sum = 3
3348 00:56:08.295326 15, 0x0, sum = 4
3349 00:56:08.295375 best_step = 13
3350 00:56:08.295423
3351 00:56:08.295470 ==
3352 00:56:08.295521 Dram Type= 6, Freq= 0, CH_1, rank 0
3353 00:56:08.295574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3354 00:56:08.295660 ==
3355 00:56:08.295729 RX Vref Scan: 1
3356 00:56:08.295778
3357 00:56:08.295826 Set Vref Range= 32 -> 127
3358 00:56:08.295874
3359 00:56:08.295922 RX Vref 32 -> 127, step: 1
3360 00:56:08.295970
3361 00:56:08.296023 RX Delay -21 -> 252, step: 4
3362 00:56:08.296071
3363 00:56:08.296118 Set Vref, RX VrefLevel [Byte0]: 32
3364 00:56:08.296167 [Byte1]: 32
3365 00:56:08.296214
3366 00:56:08.296261 Set Vref, RX VrefLevel [Byte0]: 33
3367 00:56:08.296308 [Byte1]: 33
3368 00:56:08.296355
3369 00:56:08.296409 Set Vref, RX VrefLevel [Byte0]: 34
3370 00:56:08.296456 [Byte1]: 34
3371 00:56:08.296504
3372 00:56:08.296551 Set Vref, RX VrefLevel [Byte0]: 35
3373 00:56:08.296598 [Byte1]: 35
3374 00:56:08.296651
3375 00:56:08.296701 Set Vref, RX VrefLevel [Byte0]: 36
3376 00:56:08.296753 [Byte1]: 36
3377 00:56:08.296802
3378 00:56:08.296849 Set Vref, RX VrefLevel [Byte0]: 37
3379 00:56:08.296896 [Byte1]: 37
3380 00:56:08.296943
3381 00:56:08.296990 Set Vref, RX VrefLevel [Byte0]: 38
3382 00:56:08.297037 [Byte1]: 38
3383 00:56:08.297085
3384 00:56:08.297138 Set Vref, RX VrefLevel [Byte0]: 39
3385 00:56:08.297186 [Byte1]: 39
3386 00:56:08.297232
3387 00:56:08.297278 Set Vref, RX VrefLevel [Byte0]: 40
3388 00:56:08.297325 [Byte1]: 40
3389 00:56:08.297372
3390 00:56:08.297419 Set Vref, RX VrefLevel [Byte0]: 41
3391 00:56:08.297479 [Byte1]: 41
3392 00:56:08.297563
3393 00:56:08.297626 Set Vref, RX VrefLevel [Byte0]: 42
3394 00:56:08.297674 [Byte1]: 42
3395 00:56:08.297721
3396 00:56:08.297768 Set Vref, RX VrefLevel [Byte0]: 43
3397 00:56:08.297815 [Byte1]: 43
3398 00:56:08.297862
3399 00:56:08.297915 Set Vref, RX VrefLevel [Byte0]: 44
3400 00:56:08.297963 [Byte1]: 44
3401 00:56:08.298010
3402 00:56:08.298056 Set Vref, RX VrefLevel [Byte0]: 45
3403 00:56:08.298104 [Byte1]: 45
3404 00:56:08.298153
3405 00:56:08.298201 Set Vref, RX VrefLevel [Byte0]: 46
3406 00:56:08.298252 [Byte1]: 46
3407 00:56:08.298300
3408 00:56:08.298347 Set Vref, RX VrefLevel [Byte0]: 47
3409 00:56:08.298394 [Byte1]: 47
3410 00:56:08.298441
3411 00:56:08.298487 Set Vref, RX VrefLevel [Byte0]: 48
3412 00:56:08.298534 [Byte1]: 48
3413 00:56:08.298582
3414 00:56:08.298634 Set Vref, RX VrefLevel [Byte0]: 49
3415 00:56:08.298683 [Byte1]: 49
3416 00:56:08.298729
3417 00:56:08.298776 Set Vref, RX VrefLevel [Byte0]: 50
3418 00:56:08.298823 [Byte1]: 50
3419 00:56:08.298870
3420 00:56:08.298922 Set Vref, RX VrefLevel [Byte0]: 51
3421 00:56:08.298970 [Byte1]: 51
3422 00:56:08.299017
3423 00:56:08.299064 Set Vref, RX VrefLevel [Byte0]: 52
3424 00:56:08.299111 [Byte1]: 52
3425 00:56:08.299159
3426 00:56:08.299218 Set Vref, RX VrefLevel [Byte0]: 53
3427 00:56:08.299273 [Byte1]: 53
3428 00:56:08.299320
3429 00:56:08.299367 Set Vref, RX VrefLevel [Byte0]: 54
3430 00:56:08.299414 [Byte1]: 54
3431 00:56:08.299461
3432 00:56:08.299515 Set Vref, RX VrefLevel [Byte0]: 55
3433 00:56:08.299572 [Byte1]: 55
3434 00:56:08.299643
3435 00:56:08.299718 Set Vref, RX VrefLevel [Byte0]: 56
3436 00:56:08.299794 [Byte1]: 56
3437 00:56:08.299874
3438 00:56:08.299949 Set Vref, RX VrefLevel [Byte0]: 57
3439 00:56:08.300025 [Byte1]: 57
3440 00:56:08.300099
3441 00:56:08.300180 Set Vref, RX VrefLevel [Byte0]: 58
3442 00:56:08.300256 [Byte1]: 58
3443 00:56:08.300330
3444 00:56:08.300410 Set Vref, RX VrefLevel [Byte0]: 59
3445 00:56:08.300485 [Byte1]: 59
3446 00:56:08.300560
3447 00:56:08.300635 Set Vref, RX VrefLevel [Byte0]: 60
3448 00:56:08.300694 [Byte1]: 60
3449 00:56:08.300743
3450 00:56:08.300803 Set Vref, RX VrefLevel [Byte0]: 61
3451 00:56:08.300853 [Byte1]: 61
3452 00:56:08.300905
3453 00:56:08.300952 Set Vref, RX VrefLevel [Byte0]: 62
3454 00:56:08.301000 [Byte1]: 62
3455 00:56:08.301054
3456 00:56:08.301101 Set Vref, RX VrefLevel [Byte0]: 63
3457 00:56:08.301148 [Byte1]: 63
3458 00:56:08.301195
3459 00:56:08.301242 Set Vref, RX VrefLevel [Byte0]: 64
3460 00:56:08.301288 [Byte1]: 64
3461 00:56:08.301335
3462 00:56:08.301386 Set Vref, RX VrefLevel [Byte0]: 65
3463 00:56:08.301436 [Byte1]: 65
3464 00:56:08.301482
3465 00:56:08.301533 Set Vref, RX VrefLevel [Byte0]: 66
3466 00:56:08.301581 [Byte1]: 66
3467 00:56:08.301629
3468 00:56:08.301675 Set Vref, RX VrefLevel [Byte0]: 67
3469 00:56:08.301722 [Byte1]: 67
3470 00:56:08.301774
3471 00:56:08.301821 Set Vref, RX VrefLevel [Byte0]: 68
3472 00:56:08.301868 [Byte1]: 68
3473 00:56:08.301914
3474 00:56:08.301962 Final RX Vref Byte 0 = 52 to rank0
3475 00:56:08.302014 Final RX Vref Byte 1 = 56 to rank0
3476 00:56:08.302064 Final RX Vref Byte 0 = 52 to rank1
3477 00:56:08.302111 Final RX Vref Byte 1 = 56 to rank1==
3478 00:56:08.302349 Dram Type= 6, Freq= 0, CH_1, rank 0
3479 00:56:08.302412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 00:56:08.302471 ==
3481 00:56:08.302521 DQS Delay:
3482 00:56:08.302569 DQS0 = 0, DQS1 = 0
3483 00:56:08.302617 DQM Delay:
3484 00:56:08.302671 DQM0 = 112, DQM1 = 107
3485 00:56:08.302720 DQ Delay:
3486 00:56:08.302767 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =110
3487 00:56:08.302815 DQ4 =108, DQ5 =122, DQ6 =122, DQ7 =108
3488 00:56:08.302864 DQ8 =94, DQ9 =98, DQ10 =108, DQ11 =100
3489 00:56:08.302912 DQ12 =114, DQ13 =114, DQ14 =114, DQ15 =114
3490 00:56:08.302959
3491 00:56:08.303012
3492 00:56:08.303061 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3493 00:56:08.303109 CH1 RK0: MR19=303, MR18=F0F7
3494 00:56:08.303157 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3495 00:56:08.303205
3496 00:56:08.303257 ----->DramcWriteLeveling(PI) begin...
3497 00:56:08.303308 ==
3498 00:56:08.303355 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 00:56:08.303402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 00:56:08.303451 ==
3501 00:56:08.303498 Write leveling (Byte 0): 24 => 24
3502 00:56:08.303555 Write leveling (Byte 1): 29 => 29
3503 00:56:08.303633 DramcWriteLeveling(PI) end<-----
3504 00:56:08.303707
3505 00:56:08.303780 ==
3506 00:56:08.303855 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 00:56:08.303936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 00:56:08.304011 ==
3509 00:56:08.304086 [Gating] SW mode calibration
3510 00:56:08.304167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3511 00:56:08.304245 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3512 00:56:08.304320 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 00:56:08.304396 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 00:56:08.304472 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 00:56:08.304553 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 00:56:08.304628 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 00:56:08.304713 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3518 00:56:08.304795 0 15 24 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (1 0)
3519 00:56:08.304874 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 00:56:08.304953 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 00:56:08.305033 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 00:56:08.305106 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 00:56:08.305163 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 00:56:08.305212 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 00:56:08.305261 1 0 20 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
3526 00:56:08.305308 1 0 24 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
3527 00:56:08.305356 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3528 00:56:08.305404 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 00:56:08.305452 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 00:56:08.305504 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 00:56:08.305567 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 00:56:08.305717 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 00:56:08.305825 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3534 00:56:08.305885 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3535 00:56:08.305968 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3536 00:56:08.306054 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 00:56:08.306146 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 00:56:08.306224 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 00:56:08.306300 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 00:56:08.306392 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 00:56:08.306469 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 00:56:08.306557 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 00:56:08.306632 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 00:56:08.306685 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 00:56:08.306762 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 00:56:08.306811 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 00:56:08.306859 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 00:56:08.306907 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 00:56:08.306967 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3550 00:56:08.307024 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3551 00:56:08.307072 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 00:56:08.307126 Total UI for P1: 0, mck2ui 16
3553 00:56:08.307198 best dqsien dly found for B0: ( 1, 3, 22)
3554 00:56:08.307247 Total UI for P1: 0, mck2ui 16
3555 00:56:08.307295 best dqsien dly found for B1: ( 1, 3, 24)
3556 00:56:08.307361 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3557 00:56:08.307421 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3558 00:56:08.307482
3559 00:56:08.307544 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3560 00:56:08.307598 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3561 00:56:08.307685 [Gating] SW calibration Done
3562 00:56:08.307760 ==
3563 00:56:08.307846 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 00:56:08.307928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 00:56:08.307993 ==
3566 00:56:08.308079 RX Vref Scan: 0
3567 00:56:08.308154
3568 00:56:08.308262 RX Vref 0 -> 0, step: 1
3569 00:56:08.308363
3570 00:56:08.308438 RX Delay -40 -> 252, step: 8
3571 00:56:08.308519 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3572 00:56:08.308596 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3573 00:56:08.308720 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3574 00:56:08.308782 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3575 00:56:08.308831 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3576 00:56:08.308917 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3577 00:56:08.308980 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3578 00:56:08.309029 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3579 00:56:08.309077 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3580 00:56:08.309155 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3581 00:56:08.309204 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3582 00:56:08.309441 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3583 00:56:08.309506 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3584 00:56:08.309597 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3585 00:56:08.309664 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3586 00:56:08.309714 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3587 00:56:08.309777 ==
3588 00:56:08.309829 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 00:56:08.309883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 00:56:08.309944 ==
3591 00:56:08.310002 DQS Delay:
3592 00:56:08.310049 DQS0 = 0, DQS1 = 0
3593 00:56:08.310097 DQM Delay:
3594 00:56:08.310176 DQM0 = 110, DQM1 = 108
3595 00:56:08.310251 DQ Delay:
3596 00:56:08.310330 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3597 00:56:08.310432 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3598 00:56:08.310508 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3599 00:56:08.310589 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3600 00:56:08.310670
3601 00:56:08.310744
3602 00:56:08.310830 ==
3603 00:56:08.310913 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 00:56:08.310993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 00:56:08.311086 ==
3606 00:56:08.311166
3607 00:56:08.311249
3608 00:56:08.311327 TX Vref Scan disable
3609 00:56:08.311411 == TX Byte 0 ==
3610 00:56:08.311495 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3611 00:56:08.311576 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3612 00:56:08.311676 == TX Byte 1 ==
3613 00:56:08.311758 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3614 00:56:08.311834 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3615 00:56:08.311920 ==
3616 00:56:08.312003 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 00:56:08.312090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 00:56:08.312168 ==
3619 00:56:08.312245 TX Vref=22, minBit 3, minWin=25, winSum=423
3620 00:56:08.312370 TX Vref=24, minBit 1, minWin=26, winSum=426
3621 00:56:08.312451 TX Vref=26, minBit 1, minWin=26, winSum=431
3622 00:56:08.312543 TX Vref=28, minBit 0, minWin=26, winSum=431
3623 00:56:08.312629 TX Vref=30, minBit 8, minWin=26, winSum=433
3624 00:56:08.312755 TX Vref=32, minBit 0, minWin=26, winSum=429
3625 00:56:08.312833 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
3626 00:56:08.312908
3627 00:56:08.313002 Final TX Range 1 Vref 30
3628 00:56:08.313079
3629 00:56:08.313165 ==
3630 00:56:08.313241 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 00:56:08.313324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 00:56:08.313422 ==
3633 00:56:08.313498
3634 00:56:08.313574
3635 00:56:08.313658 TX Vref Scan disable
3636 00:56:08.313733 == TX Byte 0 ==
3637 00:56:08.313829 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3638 00:56:08.313906 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3639 00:56:08.313993 == TX Byte 1 ==
3640 00:56:08.314077 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3641 00:56:08.314155 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3642 00:56:08.314246
3643 00:56:08.314332 [DATLAT]
3644 00:56:08.314407 Freq=1200, CH1 RK1
3645 00:56:08.314489
3646 00:56:08.314545 DATLAT Default: 0xd
3647 00:56:08.314593 0, 0xFFFF, sum = 0
3648 00:56:08.314663 1, 0xFFFF, sum = 0
3649 00:56:08.314743 2, 0xFFFF, sum = 0
3650 00:56:08.314836 3, 0xFFFF, sum = 0
3651 00:56:08.314914 4, 0xFFFF, sum = 0
3652 00:56:08.314990 5, 0xFFFF, sum = 0
3653 00:56:08.315089 6, 0xFFFF, sum = 0
3654 00:56:08.315175 7, 0xFFFF, sum = 0
3655 00:56:08.315252 8, 0xFFFF, sum = 0
3656 00:56:08.315347 9, 0xFFFF, sum = 0
3657 00:56:08.315434 10, 0xFFFF, sum = 0
3658 00:56:08.315567 11, 0xFFFF, sum = 0
3659 00:56:08.315646 12, 0x0, sum = 1
3660 00:56:08.315735 13, 0x0, sum = 2
3661 00:56:08.315819 14, 0x0, sum = 3
3662 00:56:08.315910 15, 0x0, sum = 4
3663 00:56:08.316000 best_step = 13
3664 00:56:08.316075
3665 00:56:08.316166 ==
3666 00:56:08.316244 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 00:56:08.316319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 00:56:08.316415 ==
3669 00:56:08.316491 RX Vref Scan: 0
3670 00:56:08.316577
3671 00:56:08.316680 RX Vref 0 -> 0, step: 1
3672 00:56:08.316784
3673 00:56:08.316871 RX Delay -21 -> 252, step: 4
3674 00:56:08.316946 iDelay=195, Bit 0, Center 112 (39 ~ 186) 148
3675 00:56:08.317028 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3676 00:56:08.317104 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3677 00:56:08.317180 iDelay=195, Bit 3, Center 106 (35 ~ 178) 144
3678 00:56:08.317275 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3679 00:56:08.317351 iDelay=195, Bit 5, Center 120 (51 ~ 190) 140
3680 00:56:08.317446 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3681 00:56:08.317530 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3682 00:56:08.317606 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3683 00:56:08.317695 iDelay=195, Bit 9, Center 98 (35 ~ 162) 128
3684 00:56:08.317776 iDelay=195, Bit 10, Center 112 (43 ~ 182) 140
3685 00:56:08.317865 iDelay=195, Bit 11, Center 104 (35 ~ 174) 140
3686 00:56:08.317945 iDelay=195, Bit 12, Center 120 (55 ~ 186) 132
3687 00:56:08.318010 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3688 00:56:08.318076 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3689 00:56:08.318125 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3690 00:56:08.318172 ==
3691 00:56:08.318220 Dram Type= 6, Freq= 0, CH_1, rank 1
3692 00:56:08.318302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3693 00:56:08.318354 ==
3694 00:56:08.318402 DQS Delay:
3695 00:56:08.318448 DQS0 = 0, DQS1 = 0
3696 00:56:08.318529 DQM Delay:
3697 00:56:08.318579 DQM0 = 110, DQM1 = 110
3698 00:56:08.318626 DQ Delay:
3699 00:56:08.318679 DQ0 =112, DQ1 =110, DQ2 =100, DQ3 =106
3700 00:56:08.318736 DQ4 =106, DQ5 =120, DQ6 =122, DQ7 =108
3701 00:56:08.318812 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =104
3702 00:56:08.318909 DQ12 =120, DQ13 =116, DQ14 =118, DQ15 =116
3703 00:56:08.319004
3704 00:56:08.319061
3705 00:56:08.319109 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3706 00:56:08.319158 CH1 RK1: MR19=304, MR18=FB0C
3707 00:56:08.319205 CH1_RK1: MR19=0x304, MR18=0xFB0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3708 00:56:08.319298 [RxdqsGatingPostProcess] freq 1200
3709 00:56:08.319359 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3710 00:56:08.319408 best DQS0 dly(2T, 0.5T) = (0, 11)
3711 00:56:08.319456 best DQS1 dly(2T, 0.5T) = (0, 11)
3712 00:56:08.319540 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3713 00:56:08.319591 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3714 00:56:08.319639 best DQS0 dly(2T, 0.5T) = (0, 11)
3715 00:56:08.319729 best DQS1 dly(2T, 0.5T) = (0, 11)
3716 00:56:08.319793 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3717 00:56:08.319841 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3718 00:56:08.319888 Pre-setting of DQS Precalculation
3719 00:56:08.319936 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3720 00:56:08.320182 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3721 00:56:08.320268 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3722 00:56:08.320321
3723 00:56:08.320369
3724 00:56:08.320420 [Calibration Summary] 2400 Mbps
3725 00:56:08.320512 CH 0, Rank 0
3726 00:56:08.320589 SW Impedance : PASS
3727 00:56:08.320706 DUTY Scan : NO K
3728 00:56:08.320799 ZQ Calibration : PASS
3729 00:56:08.320870 Jitter Meter : NO K
3730 00:56:08.320935 CBT Training : PASS
3731 00:56:08.320982 Write leveling : PASS
3732 00:56:08.321036 RX DQS gating : PASS
3733 00:56:08.321114 RX DQ/DQS(RDDQC) : PASS
3734 00:56:08.321163 TX DQ/DQS : PASS
3735 00:56:08.321211 RX DATLAT : PASS
3736 00:56:08.321274 RX DQ/DQS(Engine): PASS
3737 00:56:08.321337 TX OE : NO K
3738 00:56:08.321385 All Pass.
3739 00:56:08.321432
3740 00:56:08.321518 CH 0, Rank 1
3741 00:56:08.321587 SW Impedance : PASS
3742 00:56:08.321635 DUTY Scan : NO K
3743 00:56:08.321681 ZQ Calibration : PASS
3744 00:56:08.321764 Jitter Meter : NO K
3745 00:56:08.321813 CBT Training : PASS
3746 00:56:08.321861 Write leveling : PASS
3747 00:56:08.321935 RX DQS gating : PASS
3748 00:56:08.321987 RX DQ/DQS(RDDQC) : PASS
3749 00:56:08.322041 TX DQ/DQS : PASS
3750 00:56:08.322099 RX DATLAT : PASS
3751 00:56:08.322163 RX DQ/DQS(Engine): PASS
3752 00:56:08.322211 TX OE : NO K
3753 00:56:08.322264 All Pass.
3754 00:56:08.322312
3755 00:56:08.322371 CH 1, Rank 0
3756 00:56:08.322428 SW Impedance : PASS
3757 00:56:08.322481 DUTY Scan : NO K
3758 00:56:08.322547 ZQ Calibration : PASS
3759 00:56:08.322610 Jitter Meter : NO K
3760 00:56:08.322658 CBT Training : PASS
3761 00:56:08.322706 Write leveling : PASS
3762 00:56:08.322784 RX DQS gating : PASS
3763 00:56:08.322861 RX DQ/DQS(RDDQC) : PASS
3764 00:56:08.322937 TX DQ/DQS : PASS
3765 00:56:08.323028 RX DATLAT : PASS
3766 00:56:08.323107 RX DQ/DQS(Engine): PASS
3767 00:56:08.323189 TX OE : NO K
3768 00:56:08.323275 All Pass.
3769 00:56:08.323350
3770 00:56:08.323438 CH 1, Rank 1
3771 00:56:08.323533 SW Impedance : PASS
3772 00:56:08.323608 DUTY Scan : NO K
3773 00:56:08.323698 ZQ Calibration : PASS
3774 00:56:08.323780 Jitter Meter : NO K
3775 00:56:08.323860 CBT Training : PASS
3776 00:56:08.323946 Write leveling : PASS
3777 00:56:08.324029 RX DQS gating : PASS
3778 00:56:08.324115 RX DQ/DQS(RDDQC) : PASS
3779 00:56:08.324190 TX DQ/DQS : PASS
3780 00:56:08.324285 RX DATLAT : PASS
3781 00:56:08.324375 RX DQ/DQS(Engine): PASS
3782 00:56:08.324450 TX OE : NO K
3783 00:56:08.324539 All Pass.
3784 00:56:08.324617
3785 00:56:08.324735 DramC Write-DBI off
3786 00:56:08.324826 PER_BANK_REFRESH: Hybrid Mode
3787 00:56:08.324905 TX_TRACKING: ON
3788 00:56:08.324991 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3789 00:56:08.325075 [FAST_K] Save calibration result to emmc
3790 00:56:08.325168 dramc_set_vcore_voltage set vcore to 650000
3791 00:56:08.325258 Read voltage for 600, 5
3792 00:56:08.325335 Vio18 = 0
3793 00:56:08.325422 Vcore = 650000
3794 00:56:08.325498 Vdram = 0
3795 00:56:08.325633 Vddq = 0
3796 00:56:08.325708 Vmddr = 0
3797 00:56:08.325803 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3798 00:56:08.325881 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3799 00:56:08.325963 MEM_TYPE=3, freq_sel=19
3800 00:56:08.326063 sv_algorithm_assistance_LP4_1600
3801 00:56:08.326140 ============ PULL DRAM RESETB DOWN ============
3802 00:56:08.326218 ========== PULL DRAM RESETB DOWN end =========
3803 00:56:08.326311 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3804 00:56:08.326387 ===================================
3805 00:56:08.326479 LPDDR4 DRAM CONFIGURATION
3806 00:56:08.326561 ===================================
3807 00:56:08.326650 EX_ROW_EN[0] = 0x0
3808 00:56:08.326727 EX_ROW_EN[1] = 0x0
3809 00:56:08.326818 LP4Y_EN = 0x0
3810 00:56:08.326906 WORK_FSP = 0x0
3811 00:56:08.326984 WL = 0x2
3812 00:56:08.327064 RL = 0x2
3813 00:56:08.327140 BL = 0x2
3814 00:56:08.327214 RPST = 0x0
3815 00:56:08.327309 RD_PRE = 0x0
3816 00:56:08.327389 WR_PRE = 0x1
3817 00:56:08.327467 WR_PST = 0x0
3818 00:56:08.327539 DBI_WR = 0x0
3819 00:56:08.327588 DBI_RD = 0x0
3820 00:56:08.327635 OTF = 0x1
3821 00:56:08.327683 ===================================
3822 00:56:08.327771 ===================================
3823 00:56:08.327848 ANA top config
3824 00:56:08.327937 ===================================
3825 00:56:08.328019 DLL_ASYNC_EN = 0
3826 00:56:08.328103 ALL_SLAVE_EN = 1
3827 00:56:08.328197 NEW_RANK_MODE = 1
3828 00:56:08.328281 DLL_IDLE_MODE = 1
3829 00:56:08.328363 LP45_APHY_COMB_EN = 1
3830 00:56:08.328443 TX_ODT_DIS = 1
3831 00:56:08.328534 NEW_8X_MODE = 1
3832 00:56:08.328641 ===================================
3833 00:56:08.328804 ===================================
3834 00:56:08.328913 data_rate = 1200
3835 00:56:08.329025 CKR = 1
3836 00:56:08.329134 DQ_P2S_RATIO = 8
3837 00:56:08.329238 ===================================
3838 00:56:08.329323 CA_P2S_RATIO = 8
3839 00:56:08.329404 DQ_CA_OPEN = 0
3840 00:56:08.329480 DQ_SEMI_OPEN = 0
3841 00:56:08.329562 CA_SEMI_OPEN = 0
3842 00:56:08.329642 CA_FULL_RATE = 0
3843 00:56:08.329718 DQ_CKDIV4_EN = 1
3844 00:56:08.329798 CA_CKDIV4_EN = 1
3845 00:56:08.329879 CA_PREDIV_EN = 0
3846 00:56:08.329955 PH8_DLY = 0
3847 00:56:08.330039 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3848 00:56:08.330115 DQ_AAMCK_DIV = 4
3849 00:56:08.330190 CA_AAMCK_DIV = 4
3850 00:56:08.330273 CA_ADMCK_DIV = 4
3851 00:56:08.330348 DQ_TRACK_CA_EN = 0
3852 00:56:08.330423 CA_PICK = 600
3853 00:56:08.330507 CA_MCKIO = 600
3854 00:56:08.330584 MCKIO_SEMI = 0
3855 00:56:08.330659 PLL_FREQ = 2288
3856 00:56:08.330737 DQ_UI_PI_RATIO = 32
3857 00:56:08.330821 CA_UI_PI_RATIO = 0
3858 00:56:08.330903 ===================================
3859 00:56:08.330986 ===================================
3860 00:56:08.331069 memory_type:LPDDR4
3861 00:56:08.331144 GP_NUM : 10
3862 00:56:08.331200 SRAM_EN : 1
3863 00:56:08.331253 MD32_EN : 0
3864 00:56:08.331303 ===================================
3865 00:56:08.331360 [ANA_INIT] >>>>>>>>>>>>>>
3866 00:56:08.331440 <<<<<< [CONFIGURE PHASE]: ANA_TX
3867 00:56:08.331525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3868 00:56:08.331605 ===================================
3869 00:56:08.331872 data_rate = 1200,PCW = 0X5800
3870 00:56:08.331954 ===================================
3871 00:56:08.332040 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3872 00:56:08.332119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3873 00:56:08.332208 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3874 00:56:08.332291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3875 00:56:08.332368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3876 00:56:08.332444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3877 00:56:08.332531 [ANA_INIT] flow start
3878 00:56:08.332632 [ANA_INIT] PLL >>>>>>>>
3879 00:56:08.332713 [ANA_INIT] PLL <<<<<<<<
3880 00:56:08.332768 [ANA_INIT] MIDPI >>>>>>>>
3881 00:56:08.332818 [ANA_INIT] MIDPI <<<<<<<<
3882 00:56:08.332901 [ANA_INIT] DLL >>>>>>>>
3883 00:56:08.332977 [ANA_INIT] flow end
3884 00:56:08.333058 ============ LP4 DIFF to SE enter ============
3885 00:56:08.333140 ============ LP4 DIFF to SE exit ============
3886 00:56:08.333216 [ANA_INIT] <<<<<<<<<<<<<
3887 00:56:08.333301 [Flow] Enable top DCM control >>>>>
3888 00:56:08.333378 [Flow] Enable top DCM control <<<<<
3889 00:56:08.333445 Enable DLL master slave shuffle
3890 00:56:08.333511 ==============================================================
3891 00:56:08.333593 Gating Mode config
3892 00:56:08.333669 ==============================================================
3893 00:56:08.333753 Config description:
3894 00:56:08.333832 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3895 00:56:08.333911 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3896 00:56:08.333999 SELPH_MODE 0: By rank 1: By Phase
3897 00:56:08.334077 ==============================================================
3898 00:56:08.334158 GAT_TRACK_EN = 1
3899 00:56:08.334233 RX_GATING_MODE = 2
3900 00:56:08.334318 RX_GATING_TRACK_MODE = 2
3901 00:56:08.334396 SELPH_MODE = 1
3902 00:56:08.334474 PICG_EARLY_EN = 1
3903 00:56:08.334555 VALID_LAT_VALUE = 1
3904 00:56:08.335631 ==============================================================
3905 00:56:08.338669 Enter into Gating configuration >>>>
3906 00:56:08.342280 Exit from Gating configuration <<<<
3907 00:56:08.342354 Enter into DVFS_PRE_config >>>>>
3908 00:56:08.355516 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3909 00:56:08.358767 Exit from DVFS_PRE_config <<<<<
3910 00:56:08.361942 Enter into PICG configuration >>>>
3911 00:56:08.365561 Exit from PICG configuration <<<<
3912 00:56:08.365629 [RX_INPUT] configuration >>>>>
3913 00:56:08.368874 [RX_INPUT] configuration <<<<<
3914 00:56:08.375255 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3915 00:56:08.381928 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3916 00:56:08.385315 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3917 00:56:08.391544 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3918 00:56:08.398784 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3919 00:56:08.404863 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3920 00:56:08.408425 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3921 00:56:08.411933 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3922 00:56:08.418487 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3923 00:56:08.421741 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3924 00:56:08.424944 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3925 00:56:08.431509 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3926 00:56:08.434804 ===================================
3927 00:56:08.434871 LPDDR4 DRAM CONFIGURATION
3928 00:56:08.438279 ===================================
3929 00:56:08.441383 EX_ROW_EN[0] = 0x0
3930 00:56:08.441469 EX_ROW_EN[1] = 0x0
3931 00:56:08.444906 LP4Y_EN = 0x0
3932 00:56:08.444971 WORK_FSP = 0x0
3933 00:56:08.448463 WL = 0x2
3934 00:56:08.448553 RL = 0x2
3935 00:56:08.451531 BL = 0x2
3936 00:56:08.455126 RPST = 0x0
3937 00:56:08.455210 RD_PRE = 0x0
3938 00:56:08.458222 WR_PRE = 0x1
3939 00:56:08.458297 WR_PST = 0x0
3940 00:56:08.461748 DBI_WR = 0x0
3941 00:56:08.461824 DBI_RD = 0x0
3942 00:56:08.464713 OTF = 0x1
3943 00:56:08.468125 ===================================
3944 00:56:08.471433 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3945 00:56:08.474768 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3946 00:56:08.478076 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3947 00:56:08.481599 ===================================
3948 00:56:08.484474 LPDDR4 DRAM CONFIGURATION
3949 00:56:08.488093 ===================================
3950 00:56:08.491605 EX_ROW_EN[0] = 0x10
3951 00:56:08.491701 EX_ROW_EN[1] = 0x0
3952 00:56:08.494921 LP4Y_EN = 0x0
3953 00:56:08.495014 WORK_FSP = 0x0
3954 00:56:08.498056 WL = 0x2
3955 00:56:08.498144 RL = 0x2
3956 00:56:08.501215 BL = 0x2
3957 00:56:08.501309 RPST = 0x0
3958 00:56:08.504985 RD_PRE = 0x0
3959 00:56:08.505123 WR_PRE = 0x1
3960 00:56:08.508296 WR_PST = 0x0
3961 00:56:08.508371 DBI_WR = 0x0
3962 00:56:08.511312 DBI_RD = 0x0
3963 00:56:08.514966 OTF = 0x1
3964 00:56:08.517854 ===================================
3965 00:56:08.521564 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3966 00:56:08.526270 nWR fixed to 30
3967 00:56:08.529595 [ModeRegInit_LP4] CH0 RK0
3968 00:56:08.529672 [ModeRegInit_LP4] CH0 RK1
3969 00:56:08.533090 [ModeRegInit_LP4] CH1 RK0
3970 00:56:08.536791 [ModeRegInit_LP4] CH1 RK1
3971 00:56:08.536868 match AC timing 17
3972 00:56:08.543288 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3973 00:56:08.546600 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3974 00:56:08.549543 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3975 00:56:08.556206 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3976 00:56:08.559798 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3977 00:56:08.559879 ==
3978 00:56:08.562832 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 00:56:08.566552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 00:56:08.566631 ==
3981 00:56:08.573187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 00:56:08.579860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3983 00:56:08.583096 [CA 0] Center 37 (7~67) winsize 61
3984 00:56:08.585996 [CA 1] Center 37 (7~67) winsize 61
3985 00:56:08.589617 [CA 2] Center 35 (5~65) winsize 61
3986 00:56:08.593227 [CA 3] Center 35 (5~65) winsize 61
3987 00:56:08.596188 [CA 4] Center 34 (4~64) winsize 61
3988 00:56:08.599340 [CA 5] Center 34 (4~64) winsize 61
3989 00:56:08.599418
3990 00:56:08.602336 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3991 00:56:08.602415
3992 00:56:08.605931 [CATrainingPosCal] consider 1 rank data
3993 00:56:08.609512 u2DelayCellTimex100 = 270/100 ps
3994 00:56:08.612629 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3995 00:56:08.616011 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3996 00:56:08.619499 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3997 00:56:08.622443 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3998 00:56:08.625727 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3999 00:56:08.632371 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4000 00:56:08.632473
4001 00:56:08.636068 CA PerBit enable=1, Macro0, CA PI delay=34
4002 00:56:08.636148
4003 00:56:08.639005 [CBTSetCACLKResult] CA Dly = 34
4004 00:56:08.639084 CS Dly: 6 (0~37)
4005 00:56:08.639161 ==
4006 00:56:08.642454 Dram Type= 6, Freq= 0, CH_0, rank 1
4007 00:56:08.645682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 00:56:08.648951 ==
4009 00:56:08.652141 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4010 00:56:08.659015 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4011 00:56:08.661976 [CA 0] Center 37 (7~67) winsize 61
4012 00:56:08.665624 [CA 1] Center 37 (7~67) winsize 61
4013 00:56:08.668631 [CA 2] Center 35 (5~65) winsize 61
4014 00:56:08.671749 [CA 3] Center 35 (5~65) winsize 61
4015 00:56:08.675271 [CA 4] Center 34 (3~65) winsize 63
4016 00:56:08.678285 [CA 5] Center 33 (3~64) winsize 62
4017 00:56:08.678386
4018 00:56:08.681656 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4019 00:56:08.681754
4020 00:56:08.685251 [CATrainingPosCal] consider 2 rank data
4021 00:56:08.688709 u2DelayCellTimex100 = 270/100 ps
4022 00:56:08.691912 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4023 00:56:08.694907 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4024 00:56:08.701890 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4025 00:56:08.704926 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4026 00:56:08.708522 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4027 00:56:08.711541 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4028 00:56:08.711611
4029 00:56:08.715093 CA PerBit enable=1, Macro0, CA PI delay=34
4030 00:56:08.715194
4031 00:56:08.718568 [CBTSetCACLKResult] CA Dly = 34
4032 00:56:08.718660 CS Dly: 6 (0~38)
4033 00:56:08.718747
4034 00:56:08.721462 ----->DramcWriteLeveling(PI) begin...
4035 00:56:08.724859 ==
4036 00:56:08.728485 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 00:56:08.731600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 00:56:08.731703 ==
4039 00:56:08.734902 Write leveling (Byte 0): 32 => 32
4040 00:56:08.738128 Write leveling (Byte 1): 32 => 32
4041 00:56:08.741619 DramcWriteLeveling(PI) end<-----
4042 00:56:08.741698
4043 00:56:08.741775 ==
4044 00:56:08.744724 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 00:56:08.748205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 00:56:08.748284 ==
4047 00:56:08.751211 [Gating] SW mode calibration
4048 00:56:08.758240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4049 00:56:08.764416 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4050 00:56:08.768163 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 00:56:08.771514 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 00:56:08.777621 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 00:56:08.781328 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 00:56:08.784777 0 9 16 | B1->B0 | 3030 2f2f | 0 1 | (0 0) (0 0)
4055 00:56:08.791240 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 00:56:08.794219 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 00:56:08.797747 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 00:56:08.804187 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 00:56:08.807473 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 00:56:08.811055 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 00:56:08.814639 0 10 12 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
4062 00:56:08.821232 0 10 16 | B1->B0 | 2b2b 3c3c | 0 0 | (0 0) (0 0)
4063 00:56:08.824348 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 00:56:08.828079 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 00:56:08.834417 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 00:56:08.837821 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 00:56:08.841052 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 00:56:08.847629 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 00:56:08.850891 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 00:56:08.854409 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4071 00:56:08.861218 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 00:56:08.864205 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 00:56:08.867851 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 00:56:08.873919 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 00:56:08.877220 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 00:56:08.880557 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 00:56:08.887570 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 00:56:08.890415 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 00:56:08.893982 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 00:56:08.900637 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 00:56:08.903704 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 00:56:08.907152 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 00:56:08.913994 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 00:56:08.917155 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 00:56:08.920691 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4086 00:56:08.926771 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 00:56:08.926851 Total UI for P1: 0, mck2ui 16
4088 00:56:08.933525 best dqsien dly found for B0: ( 0, 13, 12)
4089 00:56:08.933604 Total UI for P1: 0, mck2ui 16
4090 00:56:08.940114 best dqsien dly found for B1: ( 0, 13, 14)
4091 00:56:08.943744 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4092 00:56:08.947115 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4093 00:56:08.947194
4094 00:56:08.950451 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4095 00:56:08.953431 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4096 00:56:08.956844 [Gating] SW calibration Done
4097 00:56:08.956942 ==
4098 00:56:08.960193 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 00:56:08.963456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 00:56:08.963554 ==
4101 00:56:08.966961 RX Vref Scan: 0
4102 00:56:08.967056
4103 00:56:08.967143 RX Vref 0 -> 0, step: 1
4104 00:56:08.967224
4105 00:56:08.969916 RX Delay -230 -> 252, step: 16
4106 00:56:08.977025 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4107 00:56:08.980503 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4108 00:56:08.983438 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4109 00:56:08.986906 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4110 00:56:08.990210 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4111 00:56:08.996628 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4112 00:56:09.000203 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4113 00:56:09.003295 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4114 00:56:09.007036 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4115 00:56:09.013390 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4116 00:56:09.016368 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4117 00:56:09.019742 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4118 00:56:09.023210 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4119 00:56:09.026452 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4120 00:56:09.033062 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4121 00:56:09.036822 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4122 00:56:09.036900 ==
4123 00:56:09.039932 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 00:56:09.042928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 00:56:09.043029 ==
4126 00:56:09.046609 DQS Delay:
4127 00:56:09.046686 DQS0 = 0, DQS1 = 0
4128 00:56:09.049578 DQM Delay:
4129 00:56:09.049681 DQM0 = 38, DQM1 = 30
4130 00:56:09.049769 DQ Delay:
4131 00:56:09.053094 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4132 00:56:09.056417 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4133 00:56:09.059308 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4134 00:56:09.062932 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4135 00:56:09.063024
4136 00:56:09.063116
4137 00:56:09.065983 ==
4138 00:56:09.069619 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 00:56:09.072796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 00:56:09.072868 ==
4141 00:56:09.072931
4142 00:56:09.072990
4143 00:56:09.076136 TX Vref Scan disable
4144 00:56:09.076226 == TX Byte 0 ==
4145 00:56:09.082423 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4146 00:56:09.086053 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4147 00:56:09.086134 == TX Byte 1 ==
4148 00:56:09.092430 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4149 00:56:09.095960 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4150 00:56:09.096057 ==
4151 00:56:09.099422 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 00:56:09.102590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 00:56:09.102677 ==
4154 00:56:09.102776
4155 00:56:09.102870
4156 00:56:09.105820 TX Vref Scan disable
4157 00:56:09.109311 == TX Byte 0 ==
4158 00:56:09.112308 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4159 00:56:09.115722 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4160 00:56:09.119084 == TX Byte 1 ==
4161 00:56:09.122746 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4162 00:56:09.125721 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4163 00:56:09.125818
4164 00:56:09.129135 [DATLAT]
4165 00:56:09.129205 Freq=600, CH0 RK0
4166 00:56:09.129262
4167 00:56:09.132462 DATLAT Default: 0x9
4168 00:56:09.132557 0, 0xFFFF, sum = 0
4169 00:56:09.135861 1, 0xFFFF, sum = 0
4170 00:56:09.135964 2, 0xFFFF, sum = 0
4171 00:56:09.139400 3, 0xFFFF, sum = 0
4172 00:56:09.139500 4, 0xFFFF, sum = 0
4173 00:56:09.142343 5, 0xFFFF, sum = 0
4174 00:56:09.142440 6, 0xFFFF, sum = 0
4175 00:56:09.145919 7, 0xFFFF, sum = 0
4176 00:56:09.146003 8, 0x0, sum = 1
4177 00:56:09.148837 9, 0x0, sum = 2
4178 00:56:09.148937 10, 0x0, sum = 3
4179 00:56:09.152446 11, 0x0, sum = 4
4180 00:56:09.152549 best_step = 9
4181 00:56:09.152632
4182 00:56:09.152756 ==
4183 00:56:09.156093 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 00:56:09.159026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 00:56:09.162425 ==
4186 00:56:09.162502 RX Vref Scan: 1
4187 00:56:09.162561
4188 00:56:09.165908 RX Vref 0 -> 0, step: 1
4189 00:56:09.165984
4190 00:56:09.169017 RX Delay -195 -> 252, step: 8
4191 00:56:09.169095
4192 00:56:09.172034 Set Vref, RX VrefLevel [Byte0]: 61
4193 00:56:09.175515 [Byte1]: 52
4194 00:56:09.175591
4195 00:56:09.179064 Final RX Vref Byte 0 = 61 to rank0
4196 00:56:09.182037 Final RX Vref Byte 1 = 52 to rank0
4197 00:56:09.185373 Final RX Vref Byte 0 = 61 to rank1
4198 00:56:09.188598 Final RX Vref Byte 1 = 52 to rank1==
4199 00:56:09.192108 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 00:56:09.195579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 00:56:09.195675 ==
4202 00:56:09.199005 DQS Delay:
4203 00:56:09.199112 DQS0 = 0, DQS1 = 0
4204 00:56:09.199172 DQM Delay:
4205 00:56:09.201908 DQM0 = 35, DQM1 = 29
4206 00:56:09.202020 DQ Delay:
4207 00:56:09.205351 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4208 00:56:09.208774 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4209 00:56:09.212097 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
4210 00:56:09.215310 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4211 00:56:09.215387
4212 00:56:09.215447
4213 00:56:09.225437 [DQSOSCAuto] RK0, (LSB)MR18= 0x4847, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4214 00:56:09.225519 CH0 RK0: MR19=808, MR18=4847
4215 00:56:09.232191 CH0_RK0: MR19=0x808, MR18=0x4847, DQSOSC=396, MR23=63, INC=167, DEC=111
4216 00:56:09.232268
4217 00:56:09.235197 ----->DramcWriteLeveling(PI) begin...
4218 00:56:09.238699 ==
4219 00:56:09.241994 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 00:56:09.244861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 00:56:09.244992 ==
4222 00:56:09.248463 Write leveling (Byte 0): 33 => 33
4223 00:56:09.251469 Write leveling (Byte 1): 30 => 30
4224 00:56:09.255046 DramcWriteLeveling(PI) end<-----
4225 00:56:09.255121
4226 00:56:09.255181 ==
4227 00:56:09.258669 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 00:56:09.261671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 00:56:09.261751 ==
4230 00:56:09.265250 [Gating] SW mode calibration
4231 00:56:09.271673 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4232 00:56:09.278357 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4233 00:56:09.281318 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 00:56:09.284881 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 00:56:09.291674 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 00:56:09.294601 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4237 00:56:09.297960 0 9 16 | B1->B0 | 3030 2525 | 0 0 | (1 1) (1 1)
4238 00:56:09.304624 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 00:56:09.308125 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 00:56:09.311746 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 00:56:09.314725 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 00:56:09.321504 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 00:56:09.324660 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 00:56:09.327830 0 10 12 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
4245 00:56:09.334634 0 10 16 | B1->B0 | 3737 4343 | 0 0 | (0 0) (0 0)
4246 00:56:09.338174 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 00:56:09.341355 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 00:56:09.348014 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 00:56:09.351273 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 00:56:09.354356 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 00:56:09.361483 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 00:56:09.364495 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4253 00:56:09.367574 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 00:56:09.374682 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 00:56:09.378111 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 00:56:09.381124 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 00:56:09.387500 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 00:56:09.391062 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 00:56:09.394510 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 00:56:09.401119 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 00:56:09.404551 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 00:56:09.407561 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 00:56:09.413988 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 00:56:09.417411 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 00:56:09.421119 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 00:56:09.427729 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 00:56:09.430588 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 00:56:09.434018 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 00:56:09.440727 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4270 00:56:09.440807 Total UI for P1: 0, mck2ui 16
4271 00:56:09.443779 best dqsien dly found for B0: ( 0, 13, 14)
4272 00:56:09.450438 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 00:56:09.453986 Total UI for P1: 0, mck2ui 16
4274 00:56:09.457199 best dqsien dly found for B1: ( 0, 13, 16)
4275 00:56:09.460635 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4276 00:56:09.463672 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4277 00:56:09.463763
4278 00:56:09.467274 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4279 00:56:09.470919 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4280 00:56:09.474039 [Gating] SW calibration Done
4281 00:56:09.474135 ==
4282 00:56:09.476978 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 00:56:09.480811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 00:56:09.480884 ==
4285 00:56:09.483691 RX Vref Scan: 0
4286 00:56:09.483759
4287 00:56:09.487081 RX Vref 0 -> 0, step: 1
4288 00:56:09.487153
4289 00:56:09.490631 RX Delay -230 -> 252, step: 16
4290 00:56:09.494087 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4291 00:56:09.497435 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4292 00:56:09.500899 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4293 00:56:09.503835 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4294 00:56:09.510693 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4295 00:56:09.513641 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4296 00:56:09.517087 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4297 00:56:09.520705 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4298 00:56:09.527268 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4299 00:56:09.530282 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4300 00:56:09.533732 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4301 00:56:09.537112 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4302 00:56:09.540805 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4303 00:56:09.546943 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4304 00:56:09.550391 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4305 00:56:09.553741 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4306 00:56:09.553812 ==
4307 00:56:09.557145 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 00:56:09.563426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 00:56:09.563531 ==
4310 00:56:09.563589 DQS Delay:
4311 00:56:09.563650 DQS0 = 0, DQS1 = 0
4312 00:56:09.566675 DQM Delay:
4313 00:56:09.566743 DQM0 = 39, DQM1 = 28
4314 00:56:09.570505 DQ Delay:
4315 00:56:09.573485 DQ0 =41, DQ1 =33, DQ2 =41, DQ3 =33
4316 00:56:09.573551 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4317 00:56:09.577116 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =17
4318 00:56:09.583695 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4319 00:56:09.583772
4320 00:56:09.583835
4321 00:56:09.583891 ==
4322 00:56:09.587241 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 00:56:09.590141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 00:56:09.590223 ==
4325 00:56:09.590305
4326 00:56:09.590388
4327 00:56:09.593280 TX Vref Scan disable
4328 00:56:09.593345 == TX Byte 0 ==
4329 00:56:09.600174 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4330 00:56:09.603680 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4331 00:56:09.603757 == TX Byte 1 ==
4332 00:56:09.610192 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4333 00:56:09.613630 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4334 00:56:09.613704 ==
4335 00:56:09.616605 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 00:56:09.620146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 00:56:09.620240 ==
4338 00:56:09.620322
4339 00:56:09.620405
4340 00:56:09.623407 TX Vref Scan disable
4341 00:56:09.626502 == TX Byte 0 ==
4342 00:56:09.630088 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4343 00:56:09.636690 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4344 00:56:09.636775 == TX Byte 1 ==
4345 00:56:09.639606 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4346 00:56:09.646729 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4347 00:56:09.646824
4348 00:56:09.646912 [DATLAT]
4349 00:56:09.646996 Freq=600, CH0 RK1
4350 00:56:09.647076
4351 00:56:09.649717 DATLAT Default: 0x9
4352 00:56:09.649806 0, 0xFFFF, sum = 0
4353 00:56:09.653171 1, 0xFFFF, sum = 0
4354 00:56:09.656564 2, 0xFFFF, sum = 0
4355 00:56:09.656680 3, 0xFFFF, sum = 0
4356 00:56:09.659573 4, 0xFFFF, sum = 0
4357 00:56:09.659653 5, 0xFFFF, sum = 0
4358 00:56:09.662709 6, 0xFFFF, sum = 0
4359 00:56:09.662787 7, 0xFFFF, sum = 0
4360 00:56:09.666174 8, 0x0, sum = 1
4361 00:56:09.666251 9, 0x0, sum = 2
4362 00:56:09.669688 10, 0x0, sum = 3
4363 00:56:09.669766 11, 0x0, sum = 4
4364 00:56:09.669826 best_step = 9
4365 00:56:09.669881
4366 00:56:09.672908 ==
4367 00:56:09.676011 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 00:56:09.679481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 00:56:09.679553 ==
4370 00:56:09.679612 RX Vref Scan: 0
4371 00:56:09.679687
4372 00:56:09.682640 RX Vref 0 -> 0, step: 1
4373 00:56:09.682708
4374 00:56:09.686107 RX Delay -195 -> 252, step: 8
4375 00:56:09.692639 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4376 00:56:09.696207 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4377 00:56:09.699456 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4378 00:56:09.702653 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4379 00:56:09.706133 iDelay=205, Bit 4, Center 28 (-131 ~ 188) 320
4380 00:56:09.712911 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4381 00:56:09.716357 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4382 00:56:09.719202 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4383 00:56:09.722913 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4384 00:56:09.725878 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4385 00:56:09.732860 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4386 00:56:09.735941 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4387 00:56:09.739482 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4388 00:56:09.742540 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4389 00:56:09.748919 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4390 00:56:09.752556 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4391 00:56:09.752674 ==
4392 00:56:09.756073 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 00:56:09.759019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 00:56:09.759100 ==
4395 00:56:09.762625 DQS Delay:
4396 00:56:09.762692 DQS0 = 0, DQS1 = 0
4397 00:56:09.765676 DQM Delay:
4398 00:56:09.765744 DQM0 = 33, DQM1 = 28
4399 00:56:09.765802 DQ Delay:
4400 00:56:09.769290 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4401 00:56:09.772288 DQ4 =28, DQ5 =20, DQ6 =44, DQ7 =44
4402 00:56:09.775934 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4403 00:56:09.778746 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4404 00:56:09.778846
4405 00:56:09.778930
4406 00:56:09.788924 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4407 00:56:09.792012 CH0 RK1: MR19=808, MR18=6E3D
4408 00:56:09.798624 CH0_RK1: MR19=0x808, MR18=0x6E3D, DQSOSC=389, MR23=63, INC=173, DEC=115
4409 00:56:09.798717 [RxdqsGatingPostProcess] freq 600
4410 00:56:09.805789 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4411 00:56:09.808698 Pre-setting of DQS Precalculation
4412 00:56:09.811908 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4413 00:56:09.815581 ==
4414 00:56:09.815665 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 00:56:09.822285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 00:56:09.822364 ==
4417 00:56:09.825394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 00:56:09.832110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4419 00:56:09.835494 [CA 0] Center 35 (5~66) winsize 62
4420 00:56:09.839155 [CA 1] Center 36 (6~66) winsize 61
4421 00:56:09.842166 [CA 2] Center 34 (4~65) winsize 62
4422 00:56:09.845788 [CA 3] Center 34 (4~65) winsize 62
4423 00:56:09.848755 [CA 4] Center 34 (4~65) winsize 62
4424 00:56:09.852334 [CA 5] Center 33 (3~64) winsize 62
4425 00:56:09.852427
4426 00:56:09.855372 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4427 00:56:09.855464
4428 00:56:09.859037 [CATrainingPosCal] consider 1 rank data
4429 00:56:09.862420 u2DelayCellTimex100 = 270/100 ps
4430 00:56:09.865404 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4431 00:56:09.872021 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4432 00:56:09.875605 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 00:56:09.878565 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 00:56:09.882076 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 00:56:09.885090 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 00:56:09.885159
4437 00:56:09.888735 CA PerBit enable=1, Macro0, CA PI delay=33
4438 00:56:09.888801
4439 00:56:09.891737 [CBTSetCACLKResult] CA Dly = 33
4440 00:56:09.891820 CS Dly: 5 (0~36)
4441 00:56:09.895165 ==
4442 00:56:09.898504 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 00:56:09.901836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 00:56:09.901931 ==
4445 00:56:09.905086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 00:56:09.911938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4447 00:56:09.916075 [CA 0] Center 36 (6~66) winsize 61
4448 00:56:09.919037 [CA 1] Center 35 (5~66) winsize 62
4449 00:56:09.922596 [CA 2] Center 34 (4~65) winsize 62
4450 00:56:09.925488 [CA 3] Center 34 (4~65) winsize 62
4451 00:56:09.929260 [CA 4] Center 34 (4~65) winsize 62
4452 00:56:09.932585 [CA 5] Center 33 (3~64) winsize 62
4453 00:56:09.932692
4454 00:56:09.935757 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4455 00:56:09.935826
4456 00:56:09.938794 [CATrainingPosCal] consider 2 rank data
4457 00:56:09.942181 u2DelayCellTimex100 = 270/100 ps
4458 00:56:09.945449 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4459 00:56:09.952357 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4460 00:56:09.955807 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4461 00:56:09.958874 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 00:56:09.962456 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 00:56:09.965402 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 00:56:09.965480
4465 00:56:09.968922 CA PerBit enable=1, Macro0, CA PI delay=33
4466 00:56:09.968998
4467 00:56:09.972485 [CBTSetCACLKResult] CA Dly = 33
4468 00:56:09.972601 CS Dly: 5 (0~37)
4469 00:56:09.975545
4470 00:56:09.979186 ----->DramcWriteLeveling(PI) begin...
4471 00:56:09.979264 ==
4472 00:56:09.982166 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 00:56:09.985824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 00:56:09.985901 ==
4475 00:56:09.988833 Write leveling (Byte 0): 29 => 29
4476 00:56:09.992493 Write leveling (Byte 1): 29 => 29
4477 00:56:09.995476 DramcWriteLeveling(PI) end<-----
4478 00:56:09.995576
4479 00:56:09.995668 ==
4480 00:56:09.999086 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 00:56:10.002087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 00:56:10.002164 ==
4483 00:56:10.005537 [Gating] SW mode calibration
4484 00:56:10.012015 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4485 00:56:10.018652 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4486 00:56:10.022247 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 00:56:10.025394 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 00:56:10.032245 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 00:56:10.035558 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (0 0) (1 1)
4490 00:56:10.039090 0 9 16 | B1->B0 | 2d2d 2828 | 0 0 | (1 1) (1 1)
4491 00:56:10.041983 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 00:56:10.048534 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 00:56:10.051815 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 00:56:10.055101 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 00:56:10.061833 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 00:56:10.064995 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 00:56:10.068293 0 10 12 | B1->B0 | 2e2e 3030 | 0 0 | (1 1) (0 0)
4498 00:56:10.075366 0 10 16 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
4499 00:56:10.078432 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 00:56:10.081893 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 00:56:10.088634 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 00:56:10.091690 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 00:56:10.095256 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 00:56:10.102002 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 00:56:10.104974 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4506 00:56:10.108556 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 00:56:10.115227 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 00:56:10.118282 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 00:56:10.121952 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 00:56:10.128488 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 00:56:10.131706 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 00:56:10.135064 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 00:56:10.141469 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 00:56:10.144967 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 00:56:10.148517 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 00:56:10.155104 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 00:56:10.158068 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 00:56:10.161442 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 00:56:10.167993 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 00:56:10.171560 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 00:56:10.174647 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 00:56:10.178451 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 00:56:10.181689 Total UI for P1: 0, mck2ui 16
4524 00:56:10.184766 best dqsien dly found for B0: ( 0, 13, 14)
4525 00:56:10.188239 Total UI for P1: 0, mck2ui 16
4526 00:56:10.191220 best dqsien dly found for B1: ( 0, 13, 14)
4527 00:56:10.194860 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4528 00:56:10.201400 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4529 00:56:10.201470
4530 00:56:10.204985 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4531 00:56:10.208018 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4532 00:56:10.211721 [Gating] SW calibration Done
4533 00:56:10.211800 ==
4534 00:56:10.214670 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 00:56:10.218188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 00:56:10.218262 ==
4537 00:56:10.221038 RX Vref Scan: 0
4538 00:56:10.221139
4539 00:56:10.221202 RX Vref 0 -> 0, step: 1
4540 00:56:10.221258
4541 00:56:10.224754 RX Delay -230 -> 252, step: 16
4542 00:56:10.227641 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4543 00:56:10.234173 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4544 00:56:10.237734 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4545 00:56:10.240785 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4546 00:56:10.244313 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4547 00:56:10.250761 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4548 00:56:10.254117 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4549 00:56:10.257762 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4550 00:56:10.261033 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4551 00:56:10.264276 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4552 00:56:10.270824 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4553 00:56:10.274278 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4554 00:56:10.277644 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4555 00:56:10.280978 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4556 00:56:10.287464 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4557 00:56:10.291207 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4558 00:56:10.291306 ==
4559 00:56:10.294011 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 00:56:10.297566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 00:56:10.297667 ==
4562 00:56:10.300554 DQS Delay:
4563 00:56:10.300652 DQS0 = 0, DQS1 = 0
4564 00:56:10.300731 DQM Delay:
4565 00:56:10.304205 DQM0 = 37, DQM1 = 27
4566 00:56:10.304287 DQ Delay:
4567 00:56:10.307209 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4568 00:56:10.310975 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4569 00:56:10.314030 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4570 00:56:10.317545 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4571 00:56:10.317626
4572 00:56:10.317681
4573 00:56:10.317740 ==
4574 00:56:10.320569 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 00:56:10.327013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 00:56:10.327107 ==
4577 00:56:10.327203
4578 00:56:10.327290
4579 00:56:10.330582 TX Vref Scan disable
4580 00:56:10.330654 == TX Byte 0 ==
4581 00:56:10.333454 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4582 00:56:10.340628 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4583 00:56:10.340720 == TX Byte 1 ==
4584 00:56:10.343629 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4585 00:56:10.350062 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4586 00:56:10.350159 ==
4587 00:56:10.353721 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 00:56:10.356724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 00:56:10.356812 ==
4590 00:56:10.356875
4591 00:56:10.356933
4592 00:56:10.360417 TX Vref Scan disable
4593 00:56:10.363144 == TX Byte 0 ==
4594 00:56:10.367086 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4595 00:56:10.369831 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4596 00:56:10.373636 == TX Byte 1 ==
4597 00:56:10.376937 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4598 00:56:10.380160 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4599 00:56:10.380240
4600 00:56:10.383558 [DATLAT]
4601 00:56:10.383662 Freq=600, CH1 RK0
4602 00:56:10.383750
4603 00:56:10.386429 DATLAT Default: 0x9
4604 00:56:10.386523 0, 0xFFFF, sum = 0
4605 00:56:10.389819 1, 0xFFFF, sum = 0
4606 00:56:10.389919 2, 0xFFFF, sum = 0
4607 00:56:10.392786 3, 0xFFFF, sum = 0
4608 00:56:10.392859 4, 0xFFFF, sum = 0
4609 00:56:10.396901 5, 0xFFFF, sum = 0
4610 00:56:10.396975 6, 0xFFFF, sum = 0
4611 00:56:10.400237 7, 0xFFFF, sum = 0
4612 00:56:10.400328 8, 0x0, sum = 1
4613 00:56:10.403013 9, 0x0, sum = 2
4614 00:56:10.403105 10, 0x0, sum = 3
4615 00:56:10.406666 11, 0x0, sum = 4
4616 00:56:10.406769 best_step = 9
4617 00:56:10.406854
4618 00:56:10.406940 ==
4619 00:56:10.409646 Dram Type= 6, Freq= 0, CH_1, rank 0
4620 00:56:10.413291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 00:56:10.416440 ==
4622 00:56:10.416530 RX Vref Scan: 1
4623 00:56:10.416616
4624 00:56:10.419405 RX Vref 0 -> 0, step: 1
4625 00:56:10.419473
4626 00:56:10.423062 RX Delay -195 -> 252, step: 8
4627 00:56:10.423152
4628 00:56:10.426044 Set Vref, RX VrefLevel [Byte0]: 52
4629 00:56:10.429574 [Byte1]: 56
4630 00:56:10.429668
4631 00:56:10.433115 Final RX Vref Byte 0 = 52 to rank0
4632 00:56:10.436002 Final RX Vref Byte 1 = 56 to rank0
4633 00:56:10.439389 Final RX Vref Byte 0 = 52 to rank1
4634 00:56:10.442643 Final RX Vref Byte 1 = 56 to rank1==
4635 00:56:10.446093 Dram Type= 6, Freq= 0, CH_1, rank 0
4636 00:56:10.449586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 00:56:10.449656 ==
4638 00:56:10.452485 DQS Delay:
4639 00:56:10.452586 DQS0 = 0, DQS1 = 0
4640 00:56:10.452712 DQM Delay:
4641 00:56:10.456111 DQM0 = 38, DQM1 = 28
4642 00:56:10.456200 DQ Delay:
4643 00:56:10.459075 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4644 00:56:10.462203 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4645 00:56:10.465683 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4646 00:56:10.469230 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4647 00:56:10.469300
4648 00:56:10.469360
4649 00:56:10.478920 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
4650 00:56:10.482471 CH1 RK0: MR19=808, MR18=2E3A
4651 00:56:10.485685 CH1_RK0: MR19=0x808, MR18=0x2E3A, DQSOSC=398, MR23=63, INC=165, DEC=110
4652 00:56:10.489031
4653 00:56:10.492198 ----->DramcWriteLeveling(PI) begin...
4654 00:56:10.492295 ==
4655 00:56:10.495524 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 00:56:10.498993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 00:56:10.499089 ==
4658 00:56:10.501933 Write leveling (Byte 0): 31 => 31
4659 00:56:10.505263 Write leveling (Byte 1): 32 => 32
4660 00:56:10.508509 DramcWriteLeveling(PI) end<-----
4661 00:56:10.508578
4662 00:56:10.508676 ==
4663 00:56:10.512135 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 00:56:10.515106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 00:56:10.515201 ==
4666 00:56:10.518805 [Gating] SW mode calibration
4667 00:56:10.525381 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4668 00:56:10.531989 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4669 00:56:10.534929 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4670 00:56:10.538474 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 00:56:10.545083 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4672 00:56:10.548451 0 9 12 | B1->B0 | 3030 2d2d | 0 1 | (0 0) (0 0)
4673 00:56:10.551372 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4674 00:56:10.558325 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 00:56:10.561312 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 00:56:10.564974 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 00:56:10.571481 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 00:56:10.575009 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 00:56:10.577988 0 10 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4680 00:56:10.584819 0 10 12 | B1->B0 | 2f2f 3a3a | 0 1 | (0 0) (0 0)
4681 00:56:10.587874 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 00:56:10.591492 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 00:56:10.597725 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 00:56:10.601319 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 00:56:10.604402 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 00:56:10.611268 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 00:56:10.614467 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 00:56:10.617588 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4689 00:56:10.624670 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 00:56:10.627696 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 00:56:10.631354 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 00:56:10.634421 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 00:56:10.641115 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 00:56:10.644600 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 00:56:10.647467 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 00:56:10.654264 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 00:56:10.657738 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 00:56:10.661069 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 00:56:10.667679 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 00:56:10.670780 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 00:56:10.674358 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 00:56:10.680811 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 00:56:10.684512 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 00:56:10.687452 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4705 00:56:10.693987 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 00:56:10.697630 Total UI for P1: 0, mck2ui 16
4707 00:56:10.701157 best dqsien dly found for B0: ( 0, 13, 12)
4708 00:56:10.701229 Total UI for P1: 0, mck2ui 16
4709 00:56:10.707670 best dqsien dly found for B1: ( 0, 13, 12)
4710 00:56:10.711251 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4711 00:56:10.714034 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4712 00:56:10.714102
4713 00:56:10.717429 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4714 00:56:10.720716 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4715 00:56:10.723962 [Gating] SW calibration Done
4716 00:56:10.724035 ==
4717 00:56:10.727521 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 00:56:10.730832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 00:56:10.730917 ==
4720 00:56:10.734102 RX Vref Scan: 0
4721 00:56:10.734167
4722 00:56:10.734228 RX Vref 0 -> 0, step: 1
4723 00:56:10.736991
4724 00:56:10.737082 RX Delay -230 -> 252, step: 16
4725 00:56:10.744120 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4726 00:56:10.747113 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4727 00:56:10.750759 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4728 00:56:10.753703 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4729 00:56:10.757157 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4730 00:56:10.763759 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4731 00:56:10.767404 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4732 00:56:10.770445 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4733 00:56:10.774186 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4734 00:56:10.780637 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4735 00:56:10.783713 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4736 00:56:10.787325 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4737 00:56:10.790231 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4738 00:56:10.796925 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4739 00:56:10.800536 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4740 00:56:10.803563 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4741 00:56:10.803653 ==
4742 00:56:10.807259 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 00:56:10.810165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 00:56:10.810243 ==
4745 00:56:10.813652 DQS Delay:
4746 00:56:10.813720 DQS0 = 0, DQS1 = 0
4747 00:56:10.817125 DQM Delay:
4748 00:56:10.817195 DQM0 = 37, DQM1 = 30
4749 00:56:10.817254 DQ Delay:
4750 00:56:10.820651 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4751 00:56:10.823640 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4752 00:56:10.827156 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4753 00:56:10.830224 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =41
4754 00:56:10.830289
4755 00:56:10.830346
4756 00:56:10.833869 ==
4757 00:56:10.837192 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 00:56:10.840285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 00:56:10.840378 ==
4760 00:56:10.840460
4761 00:56:10.840547
4762 00:56:10.843479 TX Vref Scan disable
4763 00:56:10.843565 == TX Byte 0 ==
4764 00:56:10.850322 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4765 00:56:10.853395 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4766 00:56:10.853473 == TX Byte 1 ==
4767 00:56:10.859938 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4768 00:56:10.863534 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4769 00:56:10.863613 ==
4770 00:56:10.866958 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 00:56:10.870481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 00:56:10.870557 ==
4773 00:56:10.870615
4774 00:56:10.870667
4775 00:56:10.873336 TX Vref Scan disable
4776 00:56:10.876794 == TX Byte 0 ==
4777 00:56:10.880093 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4778 00:56:10.883668 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4779 00:56:10.887098 == TX Byte 1 ==
4780 00:56:10.890139 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4781 00:56:10.893452 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4782 00:56:10.893543
4783 00:56:10.896974 [DATLAT]
4784 00:56:10.897067 Freq=600, CH1 RK1
4785 00:56:10.897134
4786 00:56:10.899951 DATLAT Default: 0x9
4787 00:56:10.900039 0, 0xFFFF, sum = 0
4788 00:56:10.903238 1, 0xFFFF, sum = 0
4789 00:56:10.903322 2, 0xFFFF, sum = 0
4790 00:56:10.906977 3, 0xFFFF, sum = 0
4791 00:56:10.907071 4, 0xFFFF, sum = 0
4792 00:56:10.909952 5, 0xFFFF, sum = 0
4793 00:56:10.910018 6, 0xFFFF, sum = 0
4794 00:56:10.913466 7, 0xFFFF, sum = 0
4795 00:56:10.913556 8, 0x0, sum = 1
4796 00:56:10.916406 9, 0x0, sum = 2
4797 00:56:10.916472 10, 0x0, sum = 3
4798 00:56:10.919812 11, 0x0, sum = 4
4799 00:56:10.919906 best_step = 9
4800 00:56:10.919988
4801 00:56:10.920076 ==
4802 00:56:10.923398 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 00:56:10.926326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 00:56:10.929849 ==
4805 00:56:10.929922 RX Vref Scan: 0
4806 00:56:10.929982
4807 00:56:10.932925 RX Vref 0 -> 0, step: 1
4808 00:56:10.933009
4809 00:56:10.936516 RX Delay -195 -> 252, step: 8
4810 00:56:10.939554 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4811 00:56:10.946091 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4812 00:56:10.949561 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4813 00:56:10.952892 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4814 00:56:10.956067 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4815 00:56:10.959636 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4816 00:56:10.966354 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4817 00:56:10.969331 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4818 00:56:10.972690 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4819 00:56:10.976277 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4820 00:56:10.982474 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4821 00:56:10.986036 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4822 00:56:10.989426 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4823 00:56:10.992701 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4824 00:56:10.999324 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4825 00:56:11.002560 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4826 00:56:11.002636 ==
4827 00:56:11.005810 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 00:56:11.009072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 00:56:11.009143 ==
4830 00:56:11.012263 DQS Delay:
4831 00:56:11.012333 DQS0 = 0, DQS1 = 0
4832 00:56:11.012392 DQM Delay:
4833 00:56:11.015938 DQM0 = 36, DQM1 = 29
4834 00:56:11.016033 DQ Delay:
4835 00:56:11.018972 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4836 00:56:11.022399 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =32
4837 00:56:11.025529 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4838 00:56:11.029169 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4839 00:56:11.029263
4840 00:56:11.029350
4841 00:56:11.039351 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4842 00:56:11.039427 CH1 RK1: MR19=808, MR18=3D5C
4843 00:56:11.045448 CH1_RK1: MR19=0x808, MR18=0x3D5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4844 00:56:11.049047 [RxdqsGatingPostProcess] freq 600
4845 00:56:11.055655 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4846 00:56:11.059163 Pre-setting of DQS Precalculation
4847 00:56:11.062200 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4848 00:56:11.068944 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4849 00:56:11.079019 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4850 00:56:11.079117
4851 00:56:11.079200
4852 00:56:11.082164 [Calibration Summary] 1200 Mbps
4853 00:56:11.082258 CH 0, Rank 0
4854 00:56:11.085788 SW Impedance : PASS
4855 00:56:11.085882 DUTY Scan : NO K
4856 00:56:11.088799 ZQ Calibration : PASS
4857 00:56:11.088889 Jitter Meter : NO K
4858 00:56:11.091879 CBT Training : PASS
4859 00:56:11.095544 Write leveling : PASS
4860 00:56:11.095640 RX DQS gating : PASS
4861 00:56:11.098467 RX DQ/DQS(RDDQC) : PASS
4862 00:56:11.101989 TX DQ/DQS : PASS
4863 00:56:11.102059 RX DATLAT : PASS
4864 00:56:11.105568 RX DQ/DQS(Engine): PASS
4865 00:56:11.108542 TX OE : NO K
4866 00:56:11.108632 All Pass.
4867 00:56:11.108738
4868 00:56:11.108795 CH 0, Rank 1
4869 00:56:11.112002 SW Impedance : PASS
4870 00:56:11.114982 DUTY Scan : NO K
4871 00:56:11.115050 ZQ Calibration : PASS
4872 00:56:11.118458 Jitter Meter : NO K
4873 00:56:11.121721 CBT Training : PASS
4874 00:56:11.121815 Write leveling : PASS
4875 00:56:11.125385 RX DQS gating : PASS
4876 00:56:11.128399 RX DQ/DQS(RDDQC) : PASS
4877 00:56:11.128509 TX DQ/DQS : PASS
4878 00:56:11.131492 RX DATLAT : PASS
4879 00:56:11.134731 RX DQ/DQS(Engine): PASS
4880 00:56:11.134797 TX OE : NO K
4881 00:56:11.137972 All Pass.
4882 00:56:11.138049
4883 00:56:11.138161 CH 1, Rank 0
4884 00:56:11.141571 SW Impedance : PASS
4885 00:56:11.141642 DUTY Scan : NO K
4886 00:56:11.144681 ZQ Calibration : PASS
4887 00:56:11.148271 Jitter Meter : NO K
4888 00:56:11.148362 CBT Training : PASS
4889 00:56:11.151251 Write leveling : PASS
4890 00:56:11.154878 RX DQS gating : PASS
4891 00:56:11.154969 RX DQ/DQS(RDDQC) : PASS
4892 00:56:11.157869 TX DQ/DQS : PASS
4893 00:56:11.157940 RX DATLAT : PASS
4894 00:56:11.161167 RX DQ/DQS(Engine): PASS
4895 00:56:11.164866 TX OE : NO K
4896 00:56:11.164938 All Pass.
4897 00:56:11.164996
4898 00:56:11.165062 CH 1, Rank 1
4899 00:56:11.167874 SW Impedance : PASS
4900 00:56:11.171414 DUTY Scan : NO K
4901 00:56:11.171511 ZQ Calibration : PASS
4902 00:56:11.174869 Jitter Meter : NO K
4903 00:56:11.177892 CBT Training : PASS
4904 00:56:11.177961 Write leveling : PASS
4905 00:56:11.181534 RX DQS gating : PASS
4906 00:56:11.184711 RX DQ/DQS(RDDQC) : PASS
4907 00:56:11.184781 TX DQ/DQS : PASS
4908 00:56:11.188274 RX DATLAT : PASS
4909 00:56:11.191229 RX DQ/DQS(Engine): PASS
4910 00:56:11.191322 TX OE : NO K
4911 00:56:11.194488 All Pass.
4912 00:56:11.194582
4913 00:56:11.194665 DramC Write-DBI off
4914 00:56:11.198098 PER_BANK_REFRESH: Hybrid Mode
4915 00:56:11.198187 TX_TRACKING: ON
4916 00:56:11.207812 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4917 00:56:11.211414 [FAST_K] Save calibration result to emmc
4918 00:56:11.214315 dramc_set_vcore_voltage set vcore to 662500
4919 00:56:11.217866 Read voltage for 933, 3
4920 00:56:11.217951 Vio18 = 0
4921 00:56:11.220929 Vcore = 662500
4922 00:56:11.220997 Vdram = 0
4923 00:56:11.221055 Vddq = 0
4924 00:56:11.224548 Vmddr = 0
4925 00:56:11.227531 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4926 00:56:11.234582 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4927 00:56:11.234680 MEM_TYPE=3, freq_sel=17
4928 00:56:11.237839 sv_algorithm_assistance_LP4_1600
4929 00:56:11.241065 ============ PULL DRAM RESETB DOWN ============
4930 00:56:11.247542 ========== PULL DRAM RESETB DOWN end =========
4931 00:56:11.251065 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4932 00:56:11.254529 ===================================
4933 00:56:11.257567 LPDDR4 DRAM CONFIGURATION
4934 00:56:11.261202 ===================================
4935 00:56:11.261278 EX_ROW_EN[0] = 0x0
4936 00:56:11.264209 EX_ROW_EN[1] = 0x0
4937 00:56:11.267638 LP4Y_EN = 0x0
4938 00:56:11.267729 WORK_FSP = 0x0
4939 00:56:11.270723 WL = 0x3
4940 00:56:11.270813 RL = 0x3
4941 00:56:11.274160 BL = 0x2
4942 00:56:11.274231 RPST = 0x0
4943 00:56:11.277539 RD_PRE = 0x0
4944 00:56:11.277605 WR_PRE = 0x1
4945 00:56:11.281023 WR_PST = 0x0
4946 00:56:11.281096 DBI_WR = 0x0
4947 00:56:11.283973 DBI_RD = 0x0
4948 00:56:11.284062 OTF = 0x1
4949 00:56:11.287558 ===================================
4950 00:56:11.291116 ===================================
4951 00:56:11.294151 ANA top config
4952 00:56:11.297604 ===================================
4953 00:56:11.297698 DLL_ASYNC_EN = 0
4954 00:56:11.300823 ALL_SLAVE_EN = 1
4955 00:56:11.303822 NEW_RANK_MODE = 1
4956 00:56:11.307686 DLL_IDLE_MODE = 1
4957 00:56:11.310824 LP45_APHY_COMB_EN = 1
4958 00:56:11.310897 TX_ODT_DIS = 1
4959 00:56:11.313949 NEW_8X_MODE = 1
4960 00:56:11.317391 ===================================
4961 00:56:11.320434 ===================================
4962 00:56:11.323733 data_rate = 1866
4963 00:56:11.327394 CKR = 1
4964 00:56:11.330386 DQ_P2S_RATIO = 8
4965 00:56:11.333850 ===================================
4966 00:56:11.333944 CA_P2S_RATIO = 8
4967 00:56:11.336919 DQ_CA_OPEN = 0
4968 00:56:11.340477 DQ_SEMI_OPEN = 0
4969 00:56:11.343886 CA_SEMI_OPEN = 0
4970 00:56:11.346894 CA_FULL_RATE = 0
4971 00:56:11.350332 DQ_CKDIV4_EN = 1
4972 00:56:11.350424 CA_CKDIV4_EN = 1
4973 00:56:11.353783 CA_PREDIV_EN = 0
4974 00:56:11.357014 PH8_DLY = 0
4975 00:56:11.360186 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4976 00:56:11.363554 DQ_AAMCK_DIV = 4
4977 00:56:11.366903 CA_AAMCK_DIV = 4
4978 00:56:11.366999 CA_ADMCK_DIV = 4
4979 00:56:11.370449 DQ_TRACK_CA_EN = 0
4980 00:56:11.373493 CA_PICK = 933
4981 00:56:11.377156 CA_MCKIO = 933
4982 00:56:11.380701 MCKIO_SEMI = 0
4983 00:56:11.383722 PLL_FREQ = 3732
4984 00:56:11.387370 DQ_UI_PI_RATIO = 32
4985 00:56:11.387458 CA_UI_PI_RATIO = 0
4986 00:56:11.390342 ===================================
4987 00:56:11.393453 ===================================
4988 00:56:11.397142 memory_type:LPDDR4
4989 00:56:11.400076 GP_NUM : 10
4990 00:56:11.400148 SRAM_EN : 1
4991 00:56:11.403699 MD32_EN : 0
4992 00:56:11.406637 ===================================
4993 00:56:11.409986 [ANA_INIT] >>>>>>>>>>>>>>
4994 00:56:11.413518 <<<<<< [CONFIGURE PHASE]: ANA_TX
4995 00:56:11.416777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4996 00:56:11.419787 ===================================
4997 00:56:11.419880 data_rate = 1866,PCW = 0X8f00
4998 00:56:11.423180 ===================================
4999 00:56:11.426538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5000 00:56:11.433122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 00:56:11.439956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 00:56:11.442927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5003 00:56:11.446203 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5004 00:56:11.449815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5005 00:56:11.453211 [ANA_INIT] flow start
5006 00:56:11.456239 [ANA_INIT] PLL >>>>>>>>
5007 00:56:11.456339 [ANA_INIT] PLL <<<<<<<<
5008 00:56:11.459764 [ANA_INIT] MIDPI >>>>>>>>
5009 00:56:11.463252 [ANA_INIT] MIDPI <<<<<<<<
5010 00:56:11.463352 [ANA_INIT] DLL >>>>>>>>
5011 00:56:11.466633 [ANA_INIT] flow end
5012 00:56:11.469916 ============ LP4 DIFF to SE enter ============
5013 00:56:11.473195 ============ LP4 DIFF to SE exit ============
5014 00:56:11.475922 [ANA_INIT] <<<<<<<<<<<<<
5015 00:56:11.479240 [Flow] Enable top DCM control >>>>>
5016 00:56:11.482735 [Flow] Enable top DCM control <<<<<
5017 00:56:11.486270 Enable DLL master slave shuffle
5018 00:56:11.492831 ==============================================================
5019 00:56:11.492906 Gating Mode config
5020 00:56:11.499489 ==============================================================
5021 00:56:11.502479 Config description:
5022 00:56:11.508972 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5023 00:56:11.516017 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5024 00:56:11.522542 SELPH_MODE 0: By rank 1: By Phase
5025 00:56:11.528902 ==============================================================
5026 00:56:11.529004 GAT_TRACK_EN = 1
5027 00:56:11.532530 RX_GATING_MODE = 2
5028 00:56:11.535534 RX_GATING_TRACK_MODE = 2
5029 00:56:11.539019 SELPH_MODE = 1
5030 00:56:11.542418 PICG_EARLY_EN = 1
5031 00:56:11.545776 VALID_LAT_VALUE = 1
5032 00:56:11.551955 ==============================================================
5033 00:56:11.555474 Enter into Gating configuration >>>>
5034 00:56:11.558665 Exit from Gating configuration <<<<
5035 00:56:11.561996 Enter into DVFS_PRE_config >>>>>
5036 00:56:11.572065 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5037 00:56:11.575083 Exit from DVFS_PRE_config <<<<<
5038 00:56:11.578522 Enter into PICG configuration >>>>
5039 00:56:11.581961 Exit from PICG configuration <<<<
5040 00:56:11.585222 [RX_INPUT] configuration >>>>>
5041 00:56:11.588521 [RX_INPUT] configuration <<<<<
5042 00:56:11.591900 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5043 00:56:11.598397 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5044 00:56:11.604914 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 00:56:11.608551 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 00:56:11.614943 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5047 00:56:11.621462 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5048 00:56:11.624832 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5049 00:56:11.631875 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5050 00:56:11.634814 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5051 00:56:11.638383 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5052 00:56:11.641797 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5053 00:56:11.648415 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 00:56:11.651386 ===================================
5055 00:56:11.651481 LPDDR4 DRAM CONFIGURATION
5056 00:56:11.655062 ===================================
5057 00:56:11.658041 EX_ROW_EN[0] = 0x0
5058 00:56:11.661359 EX_ROW_EN[1] = 0x0
5059 00:56:11.661431 LP4Y_EN = 0x0
5060 00:56:11.664610 WORK_FSP = 0x0
5061 00:56:11.664733 WL = 0x3
5062 00:56:11.667953 RL = 0x3
5063 00:56:11.668042 BL = 0x2
5064 00:56:11.671667 RPST = 0x0
5065 00:56:11.671748 RD_PRE = 0x0
5066 00:56:11.674776 WR_PRE = 0x1
5067 00:56:11.674845 WR_PST = 0x0
5068 00:56:11.678022 DBI_WR = 0x0
5069 00:56:11.678092 DBI_RD = 0x0
5070 00:56:11.682157 OTF = 0x1
5071 00:56:11.685049 ===================================
5072 00:56:11.687901 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5073 00:56:11.691321 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5074 00:56:11.698121 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5075 00:56:11.701464 ===================================
5076 00:56:11.701534 LPDDR4 DRAM CONFIGURATION
5077 00:56:11.704871 ===================================
5078 00:56:11.707869 EX_ROW_EN[0] = 0x10
5079 00:56:11.707960 EX_ROW_EN[1] = 0x0
5080 00:56:11.711439 LP4Y_EN = 0x0
5081 00:56:11.714476 WORK_FSP = 0x0
5082 00:56:11.714542 WL = 0x3
5083 00:56:11.718158 RL = 0x3
5084 00:56:11.718224 BL = 0x2
5085 00:56:11.721101 RPST = 0x0
5086 00:56:11.721188 RD_PRE = 0x0
5087 00:56:11.724628 WR_PRE = 0x1
5088 00:56:11.724736 WR_PST = 0x0
5089 00:56:11.728253 DBI_WR = 0x0
5090 00:56:11.728375 DBI_RD = 0x0
5091 00:56:11.731222 OTF = 0x1
5092 00:56:11.734923 ===================================
5093 00:56:11.741154 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5094 00:56:11.744703 nWR fixed to 30
5095 00:56:11.744783 [ModeRegInit_LP4] CH0 RK0
5096 00:56:11.748116 [ModeRegInit_LP4] CH0 RK1
5097 00:56:11.751100 [ModeRegInit_LP4] CH1 RK0
5098 00:56:11.751191 [ModeRegInit_LP4] CH1 RK1
5099 00:56:11.754607 match AC timing 9
5100 00:56:11.758130 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5101 00:56:11.761134 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5102 00:56:11.767813 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5103 00:56:11.771311 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5104 00:56:11.777724 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5105 00:56:11.777796 ==
5106 00:56:11.781024 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 00:56:11.784301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 00:56:11.784394 ==
5109 00:56:11.791214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 00:56:11.794052 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5111 00:56:11.798640 [CA 0] Center 38 (8~69) winsize 62
5112 00:56:11.801913 [CA 1] Center 38 (7~69) winsize 63
5113 00:56:11.805379 [CA 2] Center 35 (5~66) winsize 62
5114 00:56:11.808765 [CA 3] Center 35 (4~66) winsize 63
5115 00:56:11.812156 [CA 4] Center 34 (4~65) winsize 62
5116 00:56:11.815091 [CA 5] Center 33 (3~64) winsize 62
5117 00:56:11.815157
5118 00:56:11.818586 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5119 00:56:11.818652
5120 00:56:11.822318 [CATrainingPosCal] consider 1 rank data
5121 00:56:11.825147 u2DelayCellTimex100 = 270/100 ps
5122 00:56:11.828508 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5123 00:56:11.832073 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5124 00:56:11.838740 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5125 00:56:11.842284 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5126 00:56:11.845476 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5127 00:56:11.848898 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5128 00:56:11.848969
5129 00:56:11.852372 CA PerBit enable=1, Macro0, CA PI delay=33
5130 00:56:11.852439
5131 00:56:11.855364 [CBTSetCACLKResult] CA Dly = 33
5132 00:56:11.855431 CS Dly: 7 (0~38)
5133 00:56:11.858814 ==
5134 00:56:11.858904 Dram Type= 6, Freq= 0, CH_0, rank 1
5135 00:56:11.865473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 00:56:11.865574 ==
5137 00:56:11.868479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 00:56:11.875454 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5139 00:56:11.880539 [CA 0] Center 38 (8~69) winsize 62
5140 00:56:11.882172 [CA 1] Center 38 (7~69) winsize 63
5141 00:56:11.885578 [CA 2] Center 35 (5~66) winsize 62
5142 00:56:11.888884 [CA 3] Center 35 (5~66) winsize 62
5143 00:56:11.892316 [CA 4] Center 34 (4~65) winsize 62
5144 00:56:11.895121 [CA 5] Center 33 (3~64) winsize 62
5145 00:56:11.895211
5146 00:56:11.898563 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5147 00:56:11.898654
5148 00:56:11.902009 [CATrainingPosCal] consider 2 rank data
5149 00:56:11.905439 u2DelayCellTimex100 = 270/100 ps
5150 00:56:11.908650 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5151 00:56:11.914945 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5152 00:56:11.918722 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5153 00:56:11.921635 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5154 00:56:11.925298 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5155 00:56:11.928232 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5156 00:56:11.928326
5157 00:56:11.931747 CA PerBit enable=1, Macro0, CA PI delay=33
5158 00:56:11.931823
5159 00:56:11.935141 [CBTSetCACLKResult] CA Dly = 33
5160 00:56:11.938200 CS Dly: 7 (0~38)
5161 00:56:11.938293
5162 00:56:11.941808 ----->DramcWriteLeveling(PI) begin...
5163 00:56:11.941900 ==
5164 00:56:11.945370 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 00:56:11.948389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 00:56:11.948511 ==
5167 00:56:11.951831 Write leveling (Byte 0): 30 => 30
5168 00:56:11.954964 Write leveling (Byte 1): 29 => 29
5169 00:56:11.958418 DramcWriteLeveling(PI) end<-----
5170 00:56:11.958507
5171 00:56:11.958590 ==
5172 00:56:11.961663 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 00:56:11.965263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 00:56:11.965337 ==
5175 00:56:11.968192 [Gating] SW mode calibration
5176 00:56:11.974689 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5177 00:56:11.981887 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5178 00:56:11.984929 0 14 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5179 00:56:11.988457 0 14 4 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
5180 00:56:11.994820 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 00:56:11.998193 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 00:56:12.001550 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 00:56:12.008068 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 00:56:12.011461 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 00:56:12.015006 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5186 00:56:12.021496 0 15 0 | B1->B0 | 3030 2727 | 1 0 | (1 0) (1 0)
5187 00:56:12.024686 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5188 00:56:12.027930 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 00:56:12.034562 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 00:56:12.037956 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 00:56:12.041509 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 00:56:12.047515 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 00:56:12.051144 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 00:56:12.054228 1 0 0 | B1->B0 | 2d2d 4040 | 1 0 | (0 0) (0 0)
5195 00:56:12.060946 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 00:56:12.064305 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 00:56:12.067550 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 00:56:12.074072 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 00:56:12.077560 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 00:56:12.081039 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 00:56:12.084010 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5202 00:56:12.090674 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5203 00:56:12.094201 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5204 00:56:12.097614 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 00:56:12.104153 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 00:56:12.107469 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 00:56:12.110835 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 00:56:12.117338 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 00:56:12.120884 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 00:56:12.123867 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 00:56:12.130446 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 00:56:12.133741 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 00:56:12.137147 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 00:56:12.143581 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 00:56:12.147025 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 00:56:12.150648 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 00:56:12.157374 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 00:56:12.160343 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5219 00:56:12.164020 Total UI for P1: 0, mck2ui 16
5220 00:56:12.167079 best dqsien dly found for B0: ( 1, 2, 30)
5221 00:56:12.170565 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 00:56:12.173994 Total UI for P1: 0, mck2ui 16
5223 00:56:12.177274 best dqsien dly found for B1: ( 1, 3, 2)
5224 00:56:12.180599 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5225 00:56:12.184052 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5226 00:56:12.184133
5227 00:56:12.190566 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5228 00:56:12.193608 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5229 00:56:12.193693 [Gating] SW calibration Done
5230 00:56:12.197109 ==
5231 00:56:12.197181 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 00:56:12.203710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 00:56:12.203782 ==
5234 00:56:12.203846 RX Vref Scan: 0
5235 00:56:12.203902
5236 00:56:12.207171 RX Vref 0 -> 0, step: 1
5237 00:56:12.207236
5238 00:56:12.210476 RX Delay -80 -> 252, step: 8
5239 00:56:12.213622 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5240 00:56:12.217288 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5241 00:56:12.220005 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5242 00:56:12.226921 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5243 00:56:12.230453 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5244 00:56:12.233406 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5245 00:56:12.236797 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5246 00:56:12.239860 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5247 00:56:12.243334 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5248 00:56:12.250095 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5249 00:56:12.253416 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5250 00:56:12.256800 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5251 00:56:12.260226 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5252 00:56:12.263235 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5253 00:56:12.269877 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5254 00:56:12.273411 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5255 00:56:12.273506 ==
5256 00:56:12.276378 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 00:56:12.279857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 00:56:12.279951 ==
5259 00:56:12.283291 DQS Delay:
5260 00:56:12.283383 DQS0 = 0, DQS1 = 0
5261 00:56:12.283469 DQM Delay:
5262 00:56:12.286572 DQM0 = 93, DQM1 = 83
5263 00:56:12.286662 DQ Delay:
5264 00:56:12.289899 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5265 00:56:12.293002 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5266 00:56:12.296491 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5267 00:56:12.299579 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5268 00:56:12.299673
5269 00:56:12.299756
5270 00:56:12.299841 ==
5271 00:56:12.303129 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 00:56:12.309632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 00:56:12.309706 ==
5274 00:56:12.309765
5275 00:56:12.309818
5276 00:56:12.309870 TX Vref Scan disable
5277 00:56:12.313593 == TX Byte 0 ==
5278 00:56:12.316573 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5279 00:56:12.323357 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5280 00:56:12.323452 == TX Byte 1 ==
5281 00:56:12.326580 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5282 00:56:12.333459 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5283 00:56:12.333568 ==
5284 00:56:12.336383 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 00:56:12.339778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 00:56:12.339868 ==
5287 00:56:12.339951
5288 00:56:12.340035
5289 00:56:12.343309 TX Vref Scan disable
5290 00:56:12.343379 == TX Byte 0 ==
5291 00:56:12.349718 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5292 00:56:12.353394 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5293 00:56:12.353513 == TX Byte 1 ==
5294 00:56:12.359529 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5295 00:56:12.362969 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5296 00:56:12.363080
5297 00:56:12.363186 [DATLAT]
5298 00:56:12.366405 Freq=933, CH0 RK0
5299 00:56:12.366474
5300 00:56:12.366544 DATLAT Default: 0xd
5301 00:56:12.369917 0, 0xFFFF, sum = 0
5302 00:56:12.369991 1, 0xFFFF, sum = 0
5303 00:56:12.372996 2, 0xFFFF, sum = 0
5304 00:56:12.376492 3, 0xFFFF, sum = 0
5305 00:56:12.376562 4, 0xFFFF, sum = 0
5306 00:56:12.379470 5, 0xFFFF, sum = 0
5307 00:56:12.379566 6, 0xFFFF, sum = 0
5308 00:56:12.382998 7, 0xFFFF, sum = 0
5309 00:56:12.383158 8, 0xFFFF, sum = 0
5310 00:56:12.385980 9, 0xFFFF, sum = 0
5311 00:56:12.386074 10, 0x0, sum = 1
5312 00:56:12.389625 11, 0x0, sum = 2
5313 00:56:12.389723 12, 0x0, sum = 3
5314 00:56:12.389809 13, 0x0, sum = 4
5315 00:56:12.392735 best_step = 11
5316 00:56:12.392825
5317 00:56:12.392912 ==
5318 00:56:12.396131 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 00:56:12.399562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 00:56:12.399654 ==
5321 00:56:12.402522 RX Vref Scan: 1
5322 00:56:12.402610
5323 00:56:12.406349 RX Vref 0 -> 0, step: 1
5324 00:56:12.406427
5325 00:56:12.406484 RX Delay -69 -> 252, step: 4
5326 00:56:12.406538
5327 00:56:12.409253 Set Vref, RX VrefLevel [Byte0]: 61
5328 00:56:12.412876 [Byte1]: 52
5329 00:56:12.417493
5330 00:56:12.417587 Final RX Vref Byte 0 = 61 to rank0
5331 00:56:12.420536 Final RX Vref Byte 1 = 52 to rank0
5332 00:56:12.424196 Final RX Vref Byte 0 = 61 to rank1
5333 00:56:12.427671 Final RX Vref Byte 1 = 52 to rank1==
5334 00:56:12.430635 Dram Type= 6, Freq= 0, CH_0, rank 0
5335 00:56:12.437019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 00:56:12.437111 ==
5337 00:56:12.437197 DQS Delay:
5338 00:56:12.437287 DQS0 = 0, DQS1 = 0
5339 00:56:12.440396 DQM Delay:
5340 00:56:12.440482 DQM0 = 95, DQM1 = 82
5341 00:56:12.444000 DQ Delay:
5342 00:56:12.447415 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =92
5343 00:56:12.450422 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5344 00:56:12.453995 DQ8 =78, DQ9 =70, DQ10 =82, DQ11 =78
5345 00:56:12.456977 DQ12 =86, DQ13 =86, DQ14 =92, DQ15 =88
5346 00:56:12.457044
5347 00:56:12.457110
5348 00:56:12.464051 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5349 00:56:12.466940 CH0 RK0: MR19=505, MR18=1615
5350 00:56:12.473651 CH0_RK0: MR19=0x505, MR18=0x1615, DQSOSC=414, MR23=63, INC=63, DEC=42
5351 00:56:12.473750
5352 00:56:12.476636 ----->DramcWriteLeveling(PI) begin...
5353 00:56:12.476747 ==
5354 00:56:12.480167 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 00:56:12.483746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 00:56:12.483831 ==
5357 00:56:12.486541 Write leveling (Byte 0): 30 => 30
5358 00:56:12.490086 Write leveling (Byte 1): 29 => 29
5359 00:56:12.493721 DramcWriteLeveling(PI) end<-----
5360 00:56:12.493793
5361 00:56:12.493851 ==
5362 00:56:12.496682 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 00:56:12.499730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 00:56:12.503375 ==
5365 00:56:12.503441 [Gating] SW mode calibration
5366 00:56:12.509799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5367 00:56:12.516851 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5368 00:56:12.519630 0 14 0 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
5369 00:56:12.526623 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 00:56:12.529714 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 00:56:12.533233 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 00:56:12.539904 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 00:56:12.542931 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 00:56:12.546262 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 00:56:12.552846 0 14 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
5376 00:56:12.556250 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5377 00:56:12.560050 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 00:56:12.566299 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 00:56:12.569213 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 00:56:12.572573 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 00:56:12.579533 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 00:56:12.582969 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 00:56:12.586018 0 15 28 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
5384 00:56:12.592465 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5385 00:56:12.596077 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 00:56:12.599120 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 00:56:12.605649 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 00:56:12.609371 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 00:56:12.612409 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 00:56:12.618965 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 00:56:12.622349 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5392 00:56:12.625636 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5393 00:56:12.632028 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 00:56:12.635385 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 00:56:12.638836 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 00:56:12.645454 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 00:56:12.648464 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 00:56:12.652043 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 00:56:12.658678 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 00:56:12.661696 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 00:56:12.665007 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 00:56:12.671597 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 00:56:12.674999 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 00:56:12.678413 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 00:56:12.684723 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 00:56:12.688385 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 00:56:12.691551 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5408 00:56:12.694751 Total UI for P1: 0, mck2ui 16
5409 00:56:12.698466 best dqsien dly found for B0: ( 1, 2, 26)
5410 00:56:12.704547 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5411 00:56:12.708197 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 00:56:12.711175 Total UI for P1: 0, mck2ui 16
5413 00:56:12.714775 best dqsien dly found for B1: ( 1, 3, 0)
5414 00:56:12.718330 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5415 00:56:12.721280 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5416 00:56:12.721373
5417 00:56:12.724901 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5418 00:56:12.727928 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5419 00:56:12.731223 [Gating] SW calibration Done
5420 00:56:12.731313 ==
5421 00:56:12.734631 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 00:56:12.738433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 00:56:12.738508 ==
5424 00:56:12.741252 RX Vref Scan: 0
5425 00:56:12.741317
5426 00:56:12.741373 RX Vref 0 -> 0, step: 1
5427 00:56:12.745175
5428 00:56:12.745239 RX Delay -80 -> 252, step: 8
5429 00:56:12.751224 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5430 00:56:12.754833 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5431 00:56:12.757813 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5432 00:56:12.761240 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5433 00:56:12.764900 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5434 00:56:12.767939 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5435 00:56:12.774449 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5436 00:56:12.777902 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5437 00:56:12.781198 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5438 00:56:12.784616 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5439 00:56:12.787901 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5440 00:56:12.794777 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5441 00:56:12.797553 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5442 00:56:12.800893 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5443 00:56:12.804531 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5444 00:56:12.807738 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5445 00:56:12.807809 ==
5446 00:56:12.811276 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 00:56:12.817573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 00:56:12.817670 ==
5449 00:56:12.817744 DQS Delay:
5450 00:56:12.821195 DQS0 = 0, DQS1 = 0
5451 00:56:12.821264 DQM Delay:
5452 00:56:12.824155 DQM0 = 92, DQM1 = 82
5453 00:56:12.824251 DQ Delay:
5454 00:56:12.827775 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5455 00:56:12.830840 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5456 00:56:12.834457 DQ8 =75, DQ9 =63, DQ10 =83, DQ11 =75
5457 00:56:12.837795 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =87
5458 00:56:12.837886
5459 00:56:12.837974
5460 00:56:12.838054 ==
5461 00:56:12.841027 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 00:56:12.844448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 00:56:12.844541 ==
5464 00:56:12.844632
5465 00:56:12.844732
5466 00:56:12.847933 TX Vref Scan disable
5467 00:56:12.850752 == TX Byte 0 ==
5468 00:56:12.854444 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5469 00:56:12.857451 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5470 00:56:12.860529 == TX Byte 1 ==
5471 00:56:12.864133 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5472 00:56:12.867209 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5473 00:56:12.867301 ==
5474 00:56:12.870860 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 00:56:12.874284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 00:56:12.877280 ==
5477 00:56:12.877347
5478 00:56:12.877405
5479 00:56:12.877468 TX Vref Scan disable
5480 00:56:12.881031 == TX Byte 0 ==
5481 00:56:12.884445 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5482 00:56:12.890845 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5483 00:56:12.890930 == TX Byte 1 ==
5484 00:56:12.894508 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5485 00:56:12.900949 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5486 00:56:12.901052
5487 00:56:12.901137 [DATLAT]
5488 00:56:12.901223 Freq=933, CH0 RK1
5489 00:56:12.901305
5490 00:56:12.904106 DATLAT Default: 0xb
5491 00:56:12.904201 0, 0xFFFF, sum = 0
5492 00:56:12.907571 1, 0xFFFF, sum = 0
5493 00:56:12.907670 2, 0xFFFF, sum = 0
5494 00:56:12.911221 3, 0xFFFF, sum = 0
5495 00:56:12.914042 4, 0xFFFF, sum = 0
5496 00:56:12.914109 5, 0xFFFF, sum = 0
5497 00:56:12.917462 6, 0xFFFF, sum = 0
5498 00:56:12.917547 7, 0xFFFF, sum = 0
5499 00:56:12.921087 8, 0xFFFF, sum = 0
5500 00:56:12.921153 9, 0xFFFF, sum = 0
5501 00:56:12.924201 10, 0x0, sum = 1
5502 00:56:12.924296 11, 0x0, sum = 2
5503 00:56:12.924382 12, 0x0, sum = 3
5504 00:56:12.927450 13, 0x0, sum = 4
5505 00:56:12.927553 best_step = 11
5506 00:56:12.927636
5507 00:56:12.931059 ==
5508 00:56:12.931126 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 00:56:12.937651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 00:56:12.937723 ==
5511 00:56:12.937781 RX Vref Scan: 0
5512 00:56:12.937834
5513 00:56:12.940588 RX Vref 0 -> 0, step: 1
5514 00:56:12.940685
5515 00:56:12.944208 RX Delay -77 -> 252, step: 4
5516 00:56:12.947508 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5517 00:56:12.954039 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5518 00:56:12.957393 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5519 00:56:12.960925 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5520 00:56:12.964004 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5521 00:56:12.967173 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5522 00:56:12.970913 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5523 00:56:12.977480 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5524 00:56:12.980487 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5525 00:56:12.984105 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5526 00:56:12.987085 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5527 00:56:12.990768 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5528 00:56:12.997168 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5529 00:56:13.000781 iDelay=199, Bit 13, Center 90 (-5 ~ 186) 192
5530 00:56:13.003797 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5531 00:56:13.007059 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5532 00:56:13.007150 ==
5533 00:56:13.010494 Dram Type= 6, Freq= 0, CH_0, rank 1
5534 00:56:13.017163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 00:56:13.017232 ==
5536 00:56:13.017302 DQS Delay:
5537 00:56:13.017357 DQS0 = 0, DQS1 = 0
5538 00:56:13.020146 DQM Delay:
5539 00:56:13.020235 DQM0 = 92, DQM1 = 83
5540 00:56:13.023886 DQ Delay:
5541 00:56:13.026914 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5542 00:56:13.030270 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =104
5543 00:56:13.033465 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5544 00:56:13.037207 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5545 00:56:13.037307
5546 00:56:13.037394
5547 00:56:13.043590 [DQSOSCAuto] RK1, (LSB)MR18= 0x3415, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
5548 00:56:13.047333 CH0 RK1: MR19=505, MR18=3415
5549 00:56:13.053975 CH0_RK1: MR19=0x505, MR18=0x3415, DQSOSC=405, MR23=63, INC=66, DEC=44
5550 00:56:13.056835 [RxdqsGatingPostProcess] freq 933
5551 00:56:13.060185 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5552 00:56:13.063420 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 00:56:13.067168 best DQS1 dly(2T, 0.5T) = (0, 11)
5554 00:56:13.070237 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 00:56:13.073616 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5556 00:56:13.076580 best DQS0 dly(2T, 0.5T) = (0, 10)
5557 00:56:13.080157 best DQS1 dly(2T, 0.5T) = (0, 11)
5558 00:56:13.083207 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5559 00:56:13.086781 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5560 00:56:13.090361 Pre-setting of DQS Precalculation
5561 00:56:13.093148 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5562 00:56:13.093247 ==
5563 00:56:13.096640 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 00:56:13.103124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 00:56:13.103222 ==
5566 00:56:13.106613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 00:56:13.113185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5568 00:56:13.116717 [CA 0] Center 37 (7~67) winsize 61
5569 00:56:13.120248 [CA 1] Center 37 (7~67) winsize 61
5570 00:56:13.123053 [CA 2] Center 34 (5~64) winsize 60
5571 00:56:13.126505 [CA 3] Center 34 (5~64) winsize 60
5572 00:56:13.129935 [CA 4] Center 35 (5~65) winsize 61
5573 00:56:13.132911 [CA 5] Center 34 (4~64) winsize 61
5574 00:56:13.132985
5575 00:56:13.136287 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5576 00:56:13.136381
5577 00:56:13.139632 [CATrainingPosCal] consider 1 rank data
5578 00:56:13.142915 u2DelayCellTimex100 = 270/100 ps
5579 00:56:13.146212 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5580 00:56:13.149536 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5581 00:56:13.156768 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5582 00:56:13.159679 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5583 00:56:13.163258 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5584 00:56:13.166201 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5585 00:56:13.166297
5586 00:56:13.169920 CA PerBit enable=1, Macro0, CA PI delay=34
5587 00:56:13.169988
5588 00:56:13.173256 [CBTSetCACLKResult] CA Dly = 34
5589 00:56:13.173353 CS Dly: 6 (0~37)
5590 00:56:13.173437 ==
5591 00:56:13.176420 Dram Type= 6, Freq= 0, CH_1, rank 1
5592 00:56:13.182802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 00:56:13.182876 ==
5594 00:56:13.186773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 00:56:13.192806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5596 00:56:13.196324 [CA 0] Center 37 (8~67) winsize 60
5597 00:56:13.199810 [CA 1] Center 37 (7~68) winsize 62
5598 00:56:13.203350 [CA 2] Center 35 (5~65) winsize 61
5599 00:56:13.206329 [CA 3] Center 34 (4~64) winsize 61
5600 00:56:13.209909 [CA 4] Center 34 (5~64) winsize 60
5601 00:56:13.212947 [CA 5] Center 34 (4~64) winsize 61
5602 00:56:13.213015
5603 00:56:13.216414 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5604 00:56:13.216511
5605 00:56:13.219512 [CATrainingPosCal] consider 2 rank data
5606 00:56:13.222617 u2DelayCellTimex100 = 270/100 ps
5607 00:56:13.226300 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5608 00:56:13.233056 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5609 00:56:13.236007 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5610 00:56:13.239262 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5611 00:56:13.242883 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5612 00:56:13.246344 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5613 00:56:13.246423
5614 00:56:13.249347 CA PerBit enable=1, Macro0, CA PI delay=34
5615 00:56:13.249416
5616 00:56:13.252850 [CBTSetCACLKResult] CA Dly = 34
5617 00:56:13.252919 CS Dly: 7 (0~39)
5618 00:56:13.256210
5619 00:56:13.259067 ----->DramcWriteLeveling(PI) begin...
5620 00:56:13.259140 ==
5621 00:56:13.262650 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 00:56:13.265640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 00:56:13.265711 ==
5624 00:56:13.269111 Write leveling (Byte 0): 26 => 26
5625 00:56:13.272636 Write leveling (Byte 1): 30 => 30
5626 00:56:13.275744 DramcWriteLeveling(PI) end<-----
5627 00:56:13.275815
5628 00:56:13.275874 ==
5629 00:56:13.278852 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 00:56:13.282697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 00:56:13.282789 ==
5632 00:56:13.285575 [Gating] SW mode calibration
5633 00:56:13.292391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5634 00:56:13.299228 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5635 00:56:13.302084 0 14 0 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 1)
5636 00:56:13.305549 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 00:56:13.312027 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 00:56:13.315714 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 00:56:13.318666 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 00:56:13.325311 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 00:56:13.328975 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5642 00:56:13.331957 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (1 0) (0 0)
5643 00:56:13.338465 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
5644 00:56:13.341792 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 00:56:13.345392 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 00:56:13.351967 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 00:56:13.355079 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 00:56:13.358643 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 00:56:13.365420 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 00:56:13.368757 0 15 28 | B1->B0 | 3131 3535 | 1 0 | (0 0) (0 0)
5651 00:56:13.371997 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5652 00:56:13.375427 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 00:56:13.382073 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 00:56:13.384962 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 00:56:13.388403 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 00:56:13.395263 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 00:56:13.398635 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 00:56:13.401929 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5659 00:56:13.408205 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 00:56:13.411671 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 00:56:13.415219 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 00:56:13.421774 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 00:56:13.424892 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 00:56:13.428443 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 00:56:13.435024 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 00:56:13.438104 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 00:56:13.441590 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 00:56:13.448382 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 00:56:13.451570 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 00:56:13.454860 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 00:56:13.461427 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 00:56:13.464608 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 00:56:13.468351 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 00:56:13.474856 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5675 00:56:13.478128 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5676 00:56:13.481500 Total UI for P1: 0, mck2ui 16
5677 00:56:13.484976 best dqsien dly found for B0: ( 1, 2, 28)
5678 00:56:13.487986 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 00:56:13.491563 Total UI for P1: 0, mck2ui 16
5680 00:56:13.494411 best dqsien dly found for B1: ( 1, 2, 30)
5681 00:56:13.497956 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5682 00:56:13.501237 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5683 00:56:13.501332
5684 00:56:13.508076 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5685 00:56:13.511414 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5686 00:56:13.511485 [Gating] SW calibration Done
5687 00:56:13.514473 ==
5688 00:56:13.514548 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 00:56:13.521433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 00:56:13.521514 ==
5691 00:56:13.521582 RX Vref Scan: 0
5692 00:56:13.521638
5693 00:56:13.524450 RX Vref 0 -> 0, step: 1
5694 00:56:13.524546
5695 00:56:13.528056 RX Delay -80 -> 252, step: 8
5696 00:56:13.531081 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5697 00:56:13.534694 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5698 00:56:13.537782 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5699 00:56:13.544471 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5700 00:56:13.547594 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5701 00:56:13.551271 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5702 00:56:13.554320 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5703 00:56:13.557400 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5704 00:56:13.560865 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5705 00:56:13.567621 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5706 00:56:13.570739 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5707 00:56:13.574326 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5708 00:56:13.577790 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5709 00:56:13.580677 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5710 00:56:13.587591 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5711 00:56:13.591137 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5712 00:56:13.591234 ==
5713 00:56:13.594118 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 00:56:13.597681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 00:56:13.597756 ==
5716 00:56:13.601120 DQS Delay:
5717 00:56:13.601195 DQS0 = 0, DQS1 = 0
5718 00:56:13.601256 DQM Delay:
5719 00:56:13.603999 DQM0 = 94, DQM1 = 86
5720 00:56:13.604090 DQ Delay:
5721 00:56:13.607410 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5722 00:56:13.610956 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5723 00:56:13.613985 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5724 00:56:13.617535 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5725 00:56:13.617642
5726 00:56:13.617729
5727 00:56:13.617810 ==
5728 00:56:13.621119 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 00:56:13.627304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 00:56:13.627404 ==
5731 00:56:13.627491
5732 00:56:13.627573
5733 00:56:13.627656 TX Vref Scan disable
5734 00:56:13.630847 == TX Byte 0 ==
5735 00:56:13.634435 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5736 00:56:13.640514 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5737 00:56:13.640609 == TX Byte 1 ==
5738 00:56:13.644099 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5739 00:56:13.650759 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5740 00:56:13.650854 ==
5741 00:56:13.653754 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 00:56:13.657419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 00:56:13.657492 ==
5744 00:56:13.657557
5745 00:56:13.657615
5746 00:56:13.660498 TX Vref Scan disable
5747 00:56:13.660589 == TX Byte 0 ==
5748 00:56:13.667081 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5749 00:56:13.670746 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5750 00:56:13.670845 == TX Byte 1 ==
5751 00:56:13.677168 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5752 00:56:13.680452 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5753 00:56:13.680545
5754 00:56:13.680636 [DATLAT]
5755 00:56:13.684045 Freq=933, CH1 RK0
5756 00:56:13.684137
5757 00:56:13.684219 DATLAT Default: 0xd
5758 00:56:13.687047 0, 0xFFFF, sum = 0
5759 00:56:13.687191 1, 0xFFFF, sum = 0
5760 00:56:13.690485 2, 0xFFFF, sum = 0
5761 00:56:13.690557 3, 0xFFFF, sum = 0
5762 00:56:13.693950 4, 0xFFFF, sum = 0
5763 00:56:13.694024 5, 0xFFFF, sum = 0
5764 00:56:13.697230 6, 0xFFFF, sum = 0
5765 00:56:13.700733 7, 0xFFFF, sum = 0
5766 00:56:13.700829 8, 0xFFFF, sum = 0
5767 00:56:13.703530 9, 0xFFFF, sum = 0
5768 00:56:13.703624 10, 0x0, sum = 1
5769 00:56:13.706941 11, 0x0, sum = 2
5770 00:56:13.707011 12, 0x0, sum = 3
5771 00:56:13.707069 13, 0x0, sum = 4
5772 00:56:13.710281 best_step = 11
5773 00:56:13.710350
5774 00:56:13.710407 ==
5775 00:56:13.713761 Dram Type= 6, Freq= 0, CH_1, rank 0
5776 00:56:13.716958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 00:56:13.717031 ==
5778 00:56:13.720527 RX Vref Scan: 1
5779 00:56:13.720617
5780 00:56:13.720700 RX Vref 0 -> 0, step: 1
5781 00:56:13.723555
5782 00:56:13.723619 RX Delay -69 -> 252, step: 4
5783 00:56:13.723676
5784 00:56:13.727056 Set Vref, RX VrefLevel [Byte0]: 52
5785 00:56:13.730584 [Byte1]: 56
5786 00:56:13.734491
5787 00:56:13.734560 Final RX Vref Byte 0 = 52 to rank0
5788 00:56:13.738138 Final RX Vref Byte 1 = 56 to rank0
5789 00:56:13.741520 Final RX Vref Byte 0 = 52 to rank1
5790 00:56:13.744403 Final RX Vref Byte 1 = 56 to rank1==
5791 00:56:13.747946 Dram Type= 6, Freq= 0, CH_1, rank 0
5792 00:56:13.754501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 00:56:13.754574 ==
5794 00:56:13.754652 DQS Delay:
5795 00:56:13.754735 DQS0 = 0, DQS1 = 0
5796 00:56:13.758218 DQM Delay:
5797 00:56:13.758285 DQM0 = 97, DQM1 = 89
5798 00:56:13.761226 DQ Delay:
5799 00:56:13.764892 DQ0 =102, DQ1 =94, DQ2 =84, DQ3 =92
5800 00:56:13.767937 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5801 00:56:13.771478 DQ8 =76, DQ9 =82, DQ10 =88, DQ11 =82
5802 00:56:13.774258 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =94
5803 00:56:13.774354
5804 00:56:13.774440
5805 00:56:13.780989 [DQSOSCAuto] RK0, (LSB)MR18= 0x70f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 419 ps
5806 00:56:13.784674 CH1 RK0: MR19=505, MR18=70F
5807 00:56:13.791266 CH1_RK0: MR19=0x505, MR18=0x70F, DQSOSC=417, MR23=63, INC=62, DEC=41
5808 00:56:13.791411
5809 00:56:13.794567 ----->DramcWriteLeveling(PI) begin...
5810 00:56:13.794665 ==
5811 00:56:13.797658 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 00:56:13.801248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 00:56:13.801343 ==
5814 00:56:13.804548 Write leveling (Byte 0): 25 => 25
5815 00:56:13.807816 Write leveling (Byte 1): 27 => 27
5816 00:56:13.811099 DramcWriteLeveling(PI) end<-----
5817 00:56:13.811195
5818 00:56:13.811279 ==
5819 00:56:13.814338 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 00:56:13.818017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 00:56:13.818112 ==
5822 00:56:13.821291 [Gating] SW mode calibration
5823 00:56:13.827457 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5824 00:56:13.834583 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5825 00:56:13.837508 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5826 00:56:13.844214 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 00:56:13.847181 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 00:56:13.850841 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 00:56:13.854030 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 00:56:13.860695 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 00:56:13.863798 0 14 24 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
5832 00:56:13.867395 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5833 00:56:13.874127 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 00:56:13.877124 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 00:56:13.880797 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 00:56:13.886773 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 00:56:13.890440 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 00:56:13.897019 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 00:56:13.899981 0 15 24 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
5840 00:56:13.903562 0 15 28 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5841 00:56:13.906848 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 00:56:13.913607 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 00:56:13.917003 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 00:56:13.923369 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 00:56:13.926300 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 00:56:13.929853 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 00:56:13.936483 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5848 00:56:13.939908 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5849 00:56:13.942860 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 00:56:13.946653 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 00:56:13.953083 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 00:56:13.956333 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 00:56:13.959696 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 00:56:13.966105 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 00:56:13.969882 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 00:56:13.972875 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 00:56:13.979425 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 00:56:13.982872 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 00:56:13.985971 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 00:56:13.992851 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 00:56:13.996437 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 00:56:13.999404 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 00:56:14.006135 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5864 00:56:14.009703 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5865 00:56:14.012627 Total UI for P1: 0, mck2ui 16
5866 00:56:14.016048 best dqsien dly found for B0: ( 1, 2, 24)
5867 00:56:14.019267 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 00:56:14.022527 Total UI for P1: 0, mck2ui 16
5869 00:56:14.026166 best dqsien dly found for B1: ( 1, 2, 28)
5870 00:56:14.029493 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5871 00:56:14.032791 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5872 00:56:14.032882
5873 00:56:14.039257 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5874 00:56:14.042641 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5875 00:56:14.042736 [Gating] SW calibration Done
5876 00:56:14.046126 ==
5877 00:56:14.049065 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 00:56:14.052846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 00:56:14.052926 ==
5880 00:56:14.052983 RX Vref Scan: 0
5881 00:56:14.053042
5882 00:56:14.056041 RX Vref 0 -> 0, step: 1
5883 00:56:14.056140
5884 00:56:14.059493 RX Delay -80 -> 252, step: 8
5885 00:56:14.062662 iDelay=200, Bit 0, Center 99 (0 ~ 199) 200
5886 00:56:14.065791 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5887 00:56:14.069268 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5888 00:56:14.076127 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5889 00:56:14.079084 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5890 00:56:14.082711 iDelay=200, Bit 5, Center 99 (0 ~ 199) 200
5891 00:56:14.085590 iDelay=200, Bit 6, Center 99 (0 ~ 199) 200
5892 00:56:14.089170 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5893 00:56:14.092904 iDelay=200, Bit 8, Center 75 (-24 ~ 175) 200
5894 00:56:14.099381 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5895 00:56:14.102417 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5896 00:56:14.106028 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5897 00:56:14.109036 iDelay=200, Bit 12, Center 99 (0 ~ 199) 200
5898 00:56:14.112613 iDelay=200, Bit 13, Center 95 (-8 ~ 199) 208
5899 00:56:14.119267 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5900 00:56:14.122159 iDelay=200, Bit 15, Center 99 (0 ~ 199) 200
5901 00:56:14.122228 ==
5902 00:56:14.125736 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 00:56:14.129234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 00:56:14.129320 ==
5905 00:56:14.129380 DQS Delay:
5906 00:56:14.132557 DQS0 = 0, DQS1 = 0
5907 00:56:14.132679 DQM Delay:
5908 00:56:14.135455 DQM0 = 92, DQM1 = 89
5909 00:56:14.135557 DQ Delay:
5910 00:56:14.139146 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =91
5911 00:56:14.142378 DQ4 =91, DQ5 =99, DQ6 =99, DQ7 =91
5912 00:56:14.145643 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5913 00:56:14.148954 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =99
5914 00:56:14.149047
5915 00:56:14.149129
5916 00:56:14.149214 ==
5917 00:56:14.152118 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 00:56:14.155566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 00:56:14.158772 ==
5920 00:56:14.158841
5921 00:56:14.158911
5922 00:56:14.159021 TX Vref Scan disable
5923 00:56:14.162152 == TX Byte 0 ==
5924 00:56:14.165721 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5925 00:56:14.168717 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5926 00:56:14.172106 == TX Byte 1 ==
5927 00:56:14.175277 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5928 00:56:14.178941 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5929 00:56:14.182153 ==
5930 00:56:14.185388 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 00:56:14.188599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 00:56:14.188717 ==
5933 00:56:14.188786
5934 00:56:14.188842
5935 00:56:14.191661 TX Vref Scan disable
5936 00:56:14.191726 == TX Byte 0 ==
5937 00:56:14.198814 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5938 00:56:14.201848 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5939 00:56:14.201935 == TX Byte 1 ==
5940 00:56:14.208597 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5941 00:56:14.211669 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5942 00:56:14.211760
5943 00:56:14.211845 [DATLAT]
5944 00:56:14.215356 Freq=933, CH1 RK1
5945 00:56:14.215426
5946 00:56:14.215483 DATLAT Default: 0xb
5947 00:56:14.218378 0, 0xFFFF, sum = 0
5948 00:56:14.218444 1, 0xFFFF, sum = 0
5949 00:56:14.221933 2, 0xFFFF, sum = 0
5950 00:56:14.222024 3, 0xFFFF, sum = 0
5951 00:56:14.224900 4, 0xFFFF, sum = 0
5952 00:56:14.224967 5, 0xFFFF, sum = 0
5953 00:56:14.228212 6, 0xFFFF, sum = 0
5954 00:56:14.228307 7, 0xFFFF, sum = 0
5955 00:56:14.231949 8, 0xFFFF, sum = 0
5956 00:56:14.235012 9, 0xFFFF, sum = 0
5957 00:56:14.235123 10, 0x0, sum = 1
5958 00:56:14.235232 11, 0x0, sum = 2
5959 00:56:14.238475 12, 0x0, sum = 3
5960 00:56:14.238571 13, 0x0, sum = 4
5961 00:56:14.241971 best_step = 11
5962 00:56:14.242046
5963 00:56:14.242103 ==
5964 00:56:14.245313 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 00:56:14.248130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 00:56:14.248203 ==
5967 00:56:14.251470 RX Vref Scan: 0
5968 00:56:14.251560
5969 00:56:14.251646 RX Vref 0 -> 0, step: 1
5970 00:56:14.251727
5971 00:56:14.255017 RX Delay -69 -> 252, step: 4
5972 00:56:14.262262 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5973 00:56:14.265473 iDelay=203, Bit 1, Center 88 (-9 ~ 186) 196
5974 00:56:14.269189 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5975 00:56:14.272510 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5976 00:56:14.275524 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5977 00:56:14.282027 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5978 00:56:14.285467 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5979 00:56:14.289214 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5980 00:56:14.292504 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5981 00:56:14.295807 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5982 00:56:14.298868 iDelay=203, Bit 10, Center 94 (-1 ~ 190) 192
5983 00:56:14.305477 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5984 00:56:14.309000 iDelay=203, Bit 12, Center 100 (7 ~ 194) 188
5985 00:56:14.312115 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5986 00:56:14.315671 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5987 00:56:14.318679 iDelay=203, Bit 15, Center 100 (7 ~ 194) 188
5988 00:56:14.318772 ==
5989 00:56:14.322269 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 00:56:14.328804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 00:56:14.328875 ==
5992 00:56:14.328937 DQS Delay:
5993 00:56:14.331657 DQS0 = 0, DQS1 = 0
5994 00:56:14.331750 DQM Delay:
5995 00:56:14.335203 DQM0 = 92, DQM1 = 92
5996 00:56:14.335286 DQ Delay:
5997 00:56:14.338718 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =88
5998 00:56:14.341640 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
5999 00:56:14.345203 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =84
6000 00:56:14.348560 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =100
6001 00:56:14.348657
6002 00:56:14.348724
6003 00:56:14.355544 [DQSOSCAuto] RK1, (LSB)MR18= 0x1428, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
6004 00:56:14.358382 CH1 RK1: MR19=505, MR18=1428
6005 00:56:14.364847 CH1_RK1: MR19=0x505, MR18=0x1428, DQSOSC=409, MR23=63, INC=64, DEC=43
6006 00:56:14.368306 [RxdqsGatingPostProcess] freq 933
6007 00:56:14.375197 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6008 00:56:14.375296 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 00:56:14.378693 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 00:56:14.381578 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 00:56:14.384944 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 00:56:14.388393 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 00:56:14.391914 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 00:56:14.394866 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 00:56:14.398203 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 00:56:14.401901 Pre-setting of DQS Precalculation
6017 00:56:14.408335 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6018 00:56:14.415155 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6019 00:56:14.421720 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6020 00:56:14.421810
6021 00:56:14.421884
6022 00:56:14.425289 [Calibration Summary] 1866 Mbps
6023 00:56:14.425396 CH 0, Rank 0
6024 00:56:14.428415 SW Impedance : PASS
6025 00:56:14.428480 DUTY Scan : NO K
6026 00:56:14.431466 ZQ Calibration : PASS
6027 00:56:14.434957 Jitter Meter : NO K
6028 00:56:14.435021 CBT Training : PASS
6029 00:56:14.438414 Write leveling : PASS
6030 00:56:14.441385 RX DQS gating : PASS
6031 00:56:14.441455 RX DQ/DQS(RDDQC) : PASS
6032 00:56:14.445029 TX DQ/DQS : PASS
6033 00:56:14.448094 RX DATLAT : PASS
6034 00:56:14.448187 RX DQ/DQS(Engine): PASS
6035 00:56:14.451672 TX OE : NO K
6036 00:56:14.451740 All Pass.
6037 00:56:14.451797
6038 00:56:14.455182 CH 0, Rank 1
6039 00:56:14.455246 SW Impedance : PASS
6040 00:56:14.458051 DUTY Scan : NO K
6041 00:56:14.461486 ZQ Calibration : PASS
6042 00:56:14.461578 Jitter Meter : NO K
6043 00:56:14.464747 CBT Training : PASS
6044 00:56:14.468464 Write leveling : PASS
6045 00:56:14.468563 RX DQS gating : PASS
6046 00:56:14.471467 RX DQ/DQS(RDDQC) : PASS
6047 00:56:14.474999 TX DQ/DQS : PASS
6048 00:56:14.475091 RX DATLAT : PASS
6049 00:56:14.477922 RX DQ/DQS(Engine): PASS
6050 00:56:14.477989 TX OE : NO K
6051 00:56:14.481565 All Pass.
6052 00:56:14.481656
6053 00:56:14.481739 CH 1, Rank 0
6054 00:56:14.484514 SW Impedance : PASS
6055 00:56:14.484602 DUTY Scan : NO K
6056 00:56:14.488006 ZQ Calibration : PASS
6057 00:56:14.491165 Jitter Meter : NO K
6058 00:56:14.491255 CBT Training : PASS
6059 00:56:14.494631 Write leveling : PASS
6060 00:56:14.497873 RX DQS gating : PASS
6061 00:56:14.497944 RX DQ/DQS(RDDQC) : PASS
6062 00:56:14.501192 TX DQ/DQS : PASS
6063 00:56:14.504594 RX DATLAT : PASS
6064 00:56:14.504686 RX DQ/DQS(Engine): PASS
6065 00:56:14.507636 TX OE : NO K
6066 00:56:14.507735 All Pass.
6067 00:56:14.507800
6068 00:56:14.511313 CH 1, Rank 1
6069 00:56:14.511407 SW Impedance : PASS
6070 00:56:14.514207 DUTY Scan : NO K
6071 00:56:14.517589 ZQ Calibration : PASS
6072 00:56:14.517688 Jitter Meter : NO K
6073 00:56:14.520962 CBT Training : PASS
6074 00:56:14.524138 Write leveling : PASS
6075 00:56:14.524234 RX DQS gating : PASS
6076 00:56:14.527659 RX DQ/DQS(RDDQC) : PASS
6077 00:56:14.530910 TX DQ/DQS : PASS
6078 00:56:14.530984 RX DATLAT : PASS
6079 00:56:14.534498 RX DQ/DQS(Engine): PASS
6080 00:56:14.534600 TX OE : NO K
6081 00:56:14.537903 All Pass.
6082 00:56:14.537997
6083 00:56:14.538081 DramC Write-DBI off
6084 00:56:14.541235 PER_BANK_REFRESH: Hybrid Mode
6085 00:56:14.544200 TX_TRACKING: ON
6086 00:56:14.550763 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6087 00:56:14.554298 [FAST_K] Save calibration result to emmc
6088 00:56:14.560749 dramc_set_vcore_voltage set vcore to 650000
6089 00:56:14.560828 Read voltage for 400, 6
6090 00:56:14.563745 Vio18 = 0
6091 00:56:14.563840 Vcore = 650000
6092 00:56:14.563930 Vdram = 0
6093 00:56:14.567372 Vddq = 0
6094 00:56:14.567446 Vmddr = 0
6095 00:56:14.570577 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6096 00:56:14.577443 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6097 00:56:14.580549 MEM_TYPE=3, freq_sel=20
6098 00:56:14.580651 sv_algorithm_assistance_LP4_800
6099 00:56:14.587123 ============ PULL DRAM RESETB DOWN ============
6100 00:56:14.590838 ========== PULL DRAM RESETB DOWN end =========
6101 00:56:14.593881 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6102 00:56:14.597351 ===================================
6103 00:56:14.600580 LPDDR4 DRAM CONFIGURATION
6104 00:56:14.604043 ===================================
6105 00:56:14.607233 EX_ROW_EN[0] = 0x0
6106 00:56:14.607306 EX_ROW_EN[1] = 0x0
6107 00:56:14.610513 LP4Y_EN = 0x0
6108 00:56:14.610585 WORK_FSP = 0x0
6109 00:56:14.613490 WL = 0x2
6110 00:56:14.613555 RL = 0x2
6111 00:56:14.617190 BL = 0x2
6112 00:56:14.617287 RPST = 0x0
6113 00:56:14.620213 RD_PRE = 0x0
6114 00:56:14.620305 WR_PRE = 0x1
6115 00:56:14.623757 WR_PST = 0x0
6116 00:56:14.627188 DBI_WR = 0x0
6117 00:56:14.627258 DBI_RD = 0x0
6118 00:56:14.630137 OTF = 0x1
6119 00:56:14.633422 ===================================
6120 00:56:14.636764 ===================================
6121 00:56:14.636836 ANA top config
6122 00:56:14.640056 ===================================
6123 00:56:14.643636 DLL_ASYNC_EN = 0
6124 00:56:14.643708 ALL_SLAVE_EN = 1
6125 00:56:14.646933 NEW_RANK_MODE = 1
6126 00:56:14.650006 DLL_IDLE_MODE = 1
6127 00:56:14.653612 LP45_APHY_COMB_EN = 1
6128 00:56:14.656638 TX_ODT_DIS = 1
6129 00:56:14.656751 NEW_8X_MODE = 1
6130 00:56:14.659777 ===================================
6131 00:56:14.663100 ===================================
6132 00:56:14.666623 data_rate = 800
6133 00:56:14.669631 CKR = 1
6134 00:56:14.673186 DQ_P2S_RATIO = 4
6135 00:56:14.676442 ===================================
6136 00:56:14.679751 CA_P2S_RATIO = 4
6137 00:56:14.683322 DQ_CA_OPEN = 0
6138 00:56:14.683393 DQ_SEMI_OPEN = 1
6139 00:56:14.686451 CA_SEMI_OPEN = 1
6140 00:56:14.689461 CA_FULL_RATE = 0
6141 00:56:14.693132 DQ_CKDIV4_EN = 0
6142 00:56:14.696179 CA_CKDIV4_EN = 1
6143 00:56:14.699785 CA_PREDIV_EN = 0
6144 00:56:14.699852 PH8_DLY = 0
6145 00:56:14.702881 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6146 00:56:14.706271 DQ_AAMCK_DIV = 0
6147 00:56:14.709592 CA_AAMCK_DIV = 0
6148 00:56:14.713158 CA_ADMCK_DIV = 4
6149 00:56:14.716521 DQ_TRACK_CA_EN = 0
6150 00:56:14.716610 CA_PICK = 800
6151 00:56:14.719817 CA_MCKIO = 400
6152 00:56:14.722993 MCKIO_SEMI = 400
6153 00:56:14.726152 PLL_FREQ = 3016
6154 00:56:14.729403 DQ_UI_PI_RATIO = 32
6155 00:56:14.732787 CA_UI_PI_RATIO = 32
6156 00:56:14.736388 ===================================
6157 00:56:14.739357 ===================================
6158 00:56:14.742810 memory_type:LPDDR4
6159 00:56:14.742900 GP_NUM : 10
6160 00:56:14.746197 SRAM_EN : 1
6161 00:56:14.746289 MD32_EN : 0
6162 00:56:14.749433 ===================================
6163 00:56:14.752885 [ANA_INIT] >>>>>>>>>>>>>>
6164 00:56:14.756029 <<<<<< [CONFIGURE PHASE]: ANA_TX
6165 00:56:14.759494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6166 00:56:14.762464 ===================================
6167 00:56:14.766071 data_rate = 800,PCW = 0X7400
6168 00:56:14.769502 ===================================
6169 00:56:14.772489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6170 00:56:14.779482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 00:56:14.789069 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 00:56:14.792572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6173 00:56:14.795672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6174 00:56:14.799287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6175 00:56:14.802800 [ANA_INIT] flow start
6176 00:56:14.805858 [ANA_INIT] PLL >>>>>>>>
6177 00:56:14.805948 [ANA_INIT] PLL <<<<<<<<
6178 00:56:14.809434 [ANA_INIT] MIDPI >>>>>>>>
6179 00:56:14.812430 [ANA_INIT] MIDPI <<<<<<<<
6180 00:56:14.812524 [ANA_INIT] DLL >>>>>>>>
6181 00:56:14.815838 [ANA_INIT] flow end
6182 00:56:14.819258 ============ LP4 DIFF to SE enter ============
6183 00:56:14.825880 ============ LP4 DIFF to SE exit ============
6184 00:56:14.825974 [ANA_INIT] <<<<<<<<<<<<<
6185 00:56:14.829191 [Flow] Enable top DCM control >>>>>
6186 00:56:14.832562 [Flow] Enable top DCM control <<<<<
6187 00:56:14.835390 Enable DLL master slave shuffle
6188 00:56:14.842062 ==============================================================
6189 00:56:14.842131 Gating Mode config
6190 00:56:14.849096 ==============================================================
6191 00:56:14.852309 Config description:
6192 00:56:14.859203 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6193 00:56:14.865685 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6194 00:56:14.872620 SELPH_MODE 0: By rank 1: By Phase
6195 00:56:14.878691 ==============================================================
6196 00:56:14.878766 GAT_TRACK_EN = 0
6197 00:56:14.882254 RX_GATING_MODE = 2
6198 00:56:14.885800 RX_GATING_TRACK_MODE = 2
6199 00:56:14.888753 SELPH_MODE = 1
6200 00:56:14.892099 PICG_EARLY_EN = 1
6201 00:56:14.895473 VALID_LAT_VALUE = 1
6202 00:56:14.902056 ==============================================================
6203 00:56:14.905711 Enter into Gating configuration >>>>
6204 00:56:14.908766 Exit from Gating configuration <<<<
6205 00:56:14.912396 Enter into DVFS_PRE_config >>>>>
6206 00:56:14.922177 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6207 00:56:14.925246 Exit from DVFS_PRE_config <<<<<
6208 00:56:14.928931 Enter into PICG configuration >>>>
6209 00:56:14.931903 Exit from PICG configuration <<<<
6210 00:56:14.935190 [RX_INPUT] configuration >>>>>
6211 00:56:14.935288 [RX_INPUT] configuration <<<<<
6212 00:56:14.941849 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6213 00:56:14.948683 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6214 00:56:14.955085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6215 00:56:14.958590 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6216 00:56:14.965143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6217 00:56:14.971679 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6218 00:56:14.975218 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6219 00:56:14.978456 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6220 00:56:14.985185 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6221 00:56:14.988410 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6222 00:56:14.991419 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6223 00:56:14.998369 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 00:56:15.001634 ===================================
6225 00:56:15.001734 LPDDR4 DRAM CONFIGURATION
6226 00:56:15.005084 ===================================
6227 00:56:15.008102 EX_ROW_EN[0] = 0x0
6228 00:56:15.008197 EX_ROW_EN[1] = 0x0
6229 00:56:15.011649 LP4Y_EN = 0x0
6230 00:56:15.015115 WORK_FSP = 0x0
6231 00:56:15.015212 WL = 0x2
6232 00:56:15.018190 RL = 0x2
6233 00:56:15.018282 BL = 0x2
6234 00:56:15.021741 RPST = 0x0
6235 00:56:15.021838 RD_PRE = 0x0
6236 00:56:15.024668 WR_PRE = 0x1
6237 00:56:15.024780 WR_PST = 0x0
6238 00:56:15.028007 DBI_WR = 0x0
6239 00:56:15.028105 DBI_RD = 0x0
6240 00:56:15.031544 OTF = 0x1
6241 00:56:15.034525 ===================================
6242 00:56:15.038127 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6243 00:56:15.041615 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6244 00:56:15.047904 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6245 00:56:15.051424 ===================================
6246 00:56:15.051521 LPDDR4 DRAM CONFIGURATION
6247 00:56:15.054883 ===================================
6248 00:56:15.058369 EX_ROW_EN[0] = 0x10
6249 00:56:15.058439 EX_ROW_EN[1] = 0x0
6250 00:56:15.061212 LP4Y_EN = 0x0
6251 00:56:15.061306 WORK_FSP = 0x0
6252 00:56:15.064943 WL = 0x2
6253 00:56:15.067906 RL = 0x2
6254 00:56:15.067985 BL = 0x2
6255 00:56:15.071591 RPST = 0x0
6256 00:56:15.071687 RD_PRE = 0x0
6257 00:56:15.074668 WR_PRE = 0x1
6258 00:56:15.074766 WR_PST = 0x0
6259 00:56:15.078200 DBI_WR = 0x0
6260 00:56:15.078298 DBI_RD = 0x0
6261 00:56:15.081119 OTF = 0x1
6262 00:56:15.084533 ===================================
6263 00:56:15.088149 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6264 00:56:15.093582 nWR fixed to 30
6265 00:56:15.096965 [ModeRegInit_LP4] CH0 RK0
6266 00:56:15.097107 [ModeRegInit_LP4] CH0 RK1
6267 00:56:15.100194 [ModeRegInit_LP4] CH1 RK0
6268 00:56:15.103329 [ModeRegInit_LP4] CH1 RK1
6269 00:56:15.103423 match AC timing 19
6270 00:56:15.110199 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6271 00:56:15.113518 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6272 00:56:15.116936 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6273 00:56:15.123655 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6274 00:56:15.126731 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6275 00:56:15.126801 ==
6276 00:56:15.130262 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 00:56:15.133539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 00:56:15.133654 ==
6279 00:56:15.140122 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 00:56:15.146239 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6281 00:56:15.149876 [CA 0] Center 36 (8~64) winsize 57
6282 00:56:15.153431 [CA 1] Center 36 (8~64) winsize 57
6283 00:56:15.156673 [CA 2] Center 36 (8~64) winsize 57
6284 00:56:15.159779 [CA 3] Center 36 (8~64) winsize 57
6285 00:56:15.159848 [CA 4] Center 36 (8~64) winsize 57
6286 00:56:15.163384 [CA 5] Center 36 (8~64) winsize 57
6287 00:56:15.163482
6288 00:56:15.169962 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6289 00:56:15.170039
6290 00:56:15.172985 [CATrainingPosCal] consider 1 rank data
6291 00:56:15.176007 u2DelayCellTimex100 = 270/100 ps
6292 00:56:15.179739 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 00:56:15.182718 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 00:56:15.186213 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 00:56:15.189701 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 00:56:15.192652 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 00:56:15.196186 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 00:56:15.196280
6299 00:56:15.199713 CA PerBit enable=1, Macro0, CA PI delay=36
6300 00:56:15.199805
6301 00:56:15.202699 [CBTSetCACLKResult] CA Dly = 36
6302 00:56:15.206174 CS Dly: 1 (0~32)
6303 00:56:15.206244 ==
6304 00:56:15.209582 Dram Type= 6, Freq= 0, CH_0, rank 1
6305 00:56:15.212488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 00:56:15.212585 ==
6307 00:56:15.219485 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6308 00:56:15.226074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6309 00:56:15.228995 [CA 0] Center 36 (8~64) winsize 57
6310 00:56:15.229094 [CA 1] Center 36 (8~64) winsize 57
6311 00:56:15.232414 [CA 2] Center 36 (8~64) winsize 57
6312 00:56:15.236038 [CA 3] Center 36 (8~64) winsize 57
6313 00:56:15.238838 [CA 4] Center 36 (8~64) winsize 57
6314 00:56:15.242559 [CA 5] Center 36 (8~64) winsize 57
6315 00:56:15.242652
6316 00:56:15.245530 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6317 00:56:15.245603
6318 00:56:15.249228 [CATrainingPosCal] consider 2 rank data
6319 00:56:15.252252 u2DelayCellTimex100 = 270/100 ps
6320 00:56:15.255813 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 00:56:15.262429 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 00:56:15.265771 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 00:56:15.269149 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 00:56:15.272459 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 00:56:15.275298 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 00:56:15.275390
6327 00:56:15.279167 CA PerBit enable=1, Macro0, CA PI delay=36
6328 00:56:15.279259
6329 00:56:15.282051 [CBTSetCACLKResult] CA Dly = 36
6330 00:56:15.285651 CS Dly: 1 (0~32)
6331 00:56:15.285718
6332 00:56:15.288589 ----->DramcWriteLeveling(PI) begin...
6333 00:56:15.288691 ==
6334 00:56:15.292096 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 00:56:15.295658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 00:56:15.295742 ==
6337 00:56:15.298591 Write leveling (Byte 0): 40 => 8
6338 00:56:15.301710 Write leveling (Byte 1): 40 => 8
6339 00:56:15.305422 DramcWriteLeveling(PI) end<-----
6340 00:56:15.305497
6341 00:56:15.305555 ==
6342 00:56:15.308411 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 00:56:15.311850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 00:56:15.311915 ==
6345 00:56:15.315447 [Gating] SW mode calibration
6346 00:56:15.321949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6347 00:56:15.328495 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6348 00:56:15.332081 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 00:56:15.335487 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 00:56:15.341739 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 00:56:15.345304 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 00:56:15.348423 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 00:56:15.355124 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 00:56:15.358358 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 00:56:15.361992 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 00:56:15.368601 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 00:56:15.368709 Total UI for P1: 0, mck2ui 16
6358 00:56:15.371469 best dqsien dly found for B0: ( 0, 14, 24)
6359 00:56:15.374946 Total UI for P1: 0, mck2ui 16
6360 00:56:15.378606 best dqsien dly found for B1: ( 0, 14, 24)
6361 00:56:15.384907 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6362 00:56:15.388210 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6363 00:56:15.388309
6364 00:56:15.391643 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 00:56:15.395290 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 00:56:15.398134 [Gating] SW calibration Done
6367 00:56:15.398204 ==
6368 00:56:15.401553 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 00:56:15.405184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 00:56:15.405254 ==
6371 00:56:15.408196 RX Vref Scan: 0
6372 00:56:15.408286
6373 00:56:15.408370 RX Vref 0 -> 0, step: 1
6374 00:56:15.408456
6375 00:56:15.411315 RX Delay -410 -> 252, step: 16
6376 00:56:15.414773 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6377 00:56:15.421483 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6378 00:56:15.425071 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6379 00:56:15.427964 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6380 00:56:15.431514 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6381 00:56:15.438059 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6382 00:56:15.441679 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6383 00:56:15.444568 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6384 00:56:15.447876 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6385 00:56:15.454615 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6386 00:56:15.458117 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6387 00:56:15.461522 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6388 00:56:15.467839 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6389 00:56:15.471583 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6390 00:56:15.474643 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6391 00:56:15.478096 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6392 00:56:15.478197 ==
6393 00:56:15.481492 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 00:56:15.488043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 00:56:15.488136 ==
6396 00:56:15.488224 DQS Delay:
6397 00:56:15.491482 DQS0 = 59, DQS1 = 59
6398 00:56:15.491571 DQM Delay:
6399 00:56:15.491653 DQM0 = 18, DQM1 = 10
6400 00:56:15.494883 DQ Delay:
6401 00:56:15.498296 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6402 00:56:15.501123 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6403 00:56:15.501223 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6404 00:56:15.508335 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6405 00:56:15.508431
6406 00:56:15.508516
6407 00:56:15.508599 ==
6408 00:56:15.511329 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 00:56:15.514353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 00:56:15.514419 ==
6411 00:56:15.514481
6412 00:56:15.514540
6413 00:56:15.517889 TX Vref Scan disable
6414 00:56:15.517980 == TX Byte 0 ==
6415 00:56:15.521373 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 00:56:15.527873 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 00:56:15.527963 == TX Byte 1 ==
6418 00:56:15.530935 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 00:56:15.537897 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 00:56:15.537997 ==
6421 00:56:15.540917 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 00:56:15.544449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 00:56:15.544562 ==
6424 00:56:15.544652
6425 00:56:15.544731
6426 00:56:15.547572 TX Vref Scan disable
6427 00:56:15.547658 == TX Byte 0 ==
6428 00:56:15.554030 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6429 00:56:15.557350 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6430 00:56:15.557427 == TX Byte 1 ==
6431 00:56:15.563868 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6432 00:56:15.567438 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6433 00:56:15.567532
6434 00:56:15.567619 [DATLAT]
6435 00:56:15.570546 Freq=400, CH0 RK0
6436 00:56:15.570634
6437 00:56:15.570725 DATLAT Default: 0xf
6438 00:56:15.573922 0, 0xFFFF, sum = 0
6439 00:56:15.574011 1, 0xFFFF, sum = 0
6440 00:56:15.577209 2, 0xFFFF, sum = 0
6441 00:56:15.577299 3, 0xFFFF, sum = 0
6442 00:56:15.580784 4, 0xFFFF, sum = 0
6443 00:56:15.580854 5, 0xFFFF, sum = 0
6444 00:56:15.584213 6, 0xFFFF, sum = 0
6445 00:56:15.584278 7, 0xFFFF, sum = 0
6446 00:56:15.587238 8, 0xFFFF, sum = 0
6447 00:56:15.587328 9, 0xFFFF, sum = 0
6448 00:56:15.590604 10, 0xFFFF, sum = 0
6449 00:56:15.593773 11, 0xFFFF, sum = 0
6450 00:56:15.593847 12, 0xFFFF, sum = 0
6451 00:56:15.597180 13, 0x0, sum = 1
6452 00:56:15.597247 14, 0x0, sum = 2
6453 00:56:15.597304 15, 0x0, sum = 3
6454 00:56:15.600506 16, 0x0, sum = 4
6455 00:56:15.600603 best_step = 14
6456 00:56:15.600722
6457 00:56:15.600803 ==
6458 00:56:15.603977 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 00:56:15.610595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 00:56:15.610709 ==
6461 00:56:15.610829 RX Vref Scan: 1
6462 00:56:15.610958
6463 00:56:15.613948 RX Vref 0 -> 0, step: 1
6464 00:56:15.614011
6465 00:56:15.616979 RX Delay -359 -> 252, step: 8
6466 00:56:15.617047
6467 00:56:15.620560 Set Vref, RX VrefLevel [Byte0]: 61
6468 00:56:15.623424 [Byte1]: 52
6469 00:56:15.627097
6470 00:56:15.627191 Final RX Vref Byte 0 = 61 to rank0
6471 00:56:15.630717 Final RX Vref Byte 1 = 52 to rank0
6472 00:56:15.633692 Final RX Vref Byte 0 = 61 to rank1
6473 00:56:15.637203 Final RX Vref Byte 1 = 52 to rank1==
6474 00:56:15.640698 Dram Type= 6, Freq= 0, CH_0, rank 0
6475 00:56:15.647303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 00:56:15.647407 ==
6477 00:56:15.647492 DQS Delay:
6478 00:56:15.650280 DQS0 = 60, DQS1 = 68
6479 00:56:15.650363 DQM Delay:
6480 00:56:15.650420 DQM0 = 14, DQM1 = 14
6481 00:56:15.653927 DQ Delay:
6482 00:56:15.656775 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =16
6483 00:56:15.660352 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6484 00:56:15.660440 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6485 00:56:15.663853 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6486 00:56:15.667282
6487 00:56:15.667354
6488 00:56:15.673385 [DQSOSCAuto] RK0, (LSB)MR18= 0x8f8e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6489 00:56:15.676962 CH0 RK0: MR19=C0C, MR18=8F8E
6490 00:56:15.683477 CH0_RK0: MR19=0xC0C, MR18=0x8F8E, DQSOSC=391, MR23=63, INC=386, DEC=257
6491 00:56:15.683569 ==
6492 00:56:15.686744 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 00:56:15.690041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 00:56:15.690130 ==
6495 00:56:15.693267 [Gating] SW mode calibration
6496 00:56:15.700212 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6497 00:56:15.706598 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6498 00:56:15.709953 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 00:56:15.713488 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 00:56:15.719866 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 00:56:15.723525 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 00:56:15.726396 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 00:56:15.733381 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 00:56:15.736433 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 00:56:15.740034 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 00:56:15.746453 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 00:56:15.746553 Total UI for P1: 0, mck2ui 16
6508 00:56:15.752911 best dqsien dly found for B0: ( 0, 14, 24)
6509 00:56:15.753000 Total UI for P1: 0, mck2ui 16
6510 00:56:15.756558 best dqsien dly found for B1: ( 0, 14, 24)
6511 00:56:15.763106 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6512 00:56:15.766059 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6513 00:56:15.766152
6514 00:56:15.769650 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 00:56:15.773060 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 00:56:15.776062 [Gating] SW calibration Done
6517 00:56:15.776153 ==
6518 00:56:15.779680 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 00:56:15.782701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 00:56:15.782795 ==
6521 00:56:15.786216 RX Vref Scan: 0
6522 00:56:15.786289
6523 00:56:15.786346 RX Vref 0 -> 0, step: 1
6524 00:56:15.786400
6525 00:56:15.789249 RX Delay -410 -> 252, step: 16
6526 00:56:15.795854 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6527 00:56:15.799881 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6528 00:56:15.802837 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6529 00:56:15.806320 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6530 00:56:15.812869 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6531 00:56:15.816374 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6532 00:56:15.819376 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6533 00:56:15.822442 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6534 00:56:15.829374 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6535 00:56:15.832624 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6536 00:56:15.835885 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6537 00:56:15.839378 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6538 00:56:15.846110 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6539 00:56:15.849147 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6540 00:56:15.852534 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6541 00:56:15.856028 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6542 00:56:15.859128 ==
6543 00:56:15.862153 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 00:56:15.865647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 00:56:15.865721 ==
6546 00:56:15.865779 DQS Delay:
6547 00:56:15.869290 DQS0 = 59, DQS1 = 59
6548 00:56:15.869362 DQM Delay:
6549 00:56:15.872351 DQM0 = 16, DQM1 = 10
6550 00:56:15.872440 DQ Delay:
6551 00:56:15.875674 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6552 00:56:15.879047 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6553 00:56:15.882056 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6554 00:56:15.885721 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6555 00:56:15.885809
6556 00:56:15.885894
6557 00:56:15.885951 ==
6558 00:56:15.888766 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 00:56:15.892270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 00:56:15.892369 ==
6561 00:56:15.892452
6562 00:56:15.892535
6563 00:56:15.895806 TX Vref Scan disable
6564 00:56:15.895894 == TX Byte 0 ==
6565 00:56:15.902153 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6566 00:56:15.905899 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6567 00:56:15.905972 == TX Byte 1 ==
6568 00:56:15.912001 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6569 00:56:15.915509 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6570 00:56:15.915576 ==
6571 00:56:15.918934 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 00:56:15.922282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 00:56:15.922371 ==
6574 00:56:15.922462
6575 00:56:15.922546
6576 00:56:15.925175 TX Vref Scan disable
6577 00:56:15.925246 == TX Byte 0 ==
6578 00:56:15.932142 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6579 00:56:15.935531 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6580 00:56:15.935675 == TX Byte 1 ==
6581 00:56:15.941949 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6582 00:56:15.945047 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6583 00:56:15.945114
6584 00:56:15.945171 [DATLAT]
6585 00:56:15.948317 Freq=400, CH0 RK1
6586 00:56:15.948405
6587 00:56:15.948494 DATLAT Default: 0xe
6588 00:56:15.951887 0, 0xFFFF, sum = 0
6589 00:56:15.951982 1, 0xFFFF, sum = 0
6590 00:56:15.955407 2, 0xFFFF, sum = 0
6591 00:56:15.955501 3, 0xFFFF, sum = 0
6592 00:56:15.958843 4, 0xFFFF, sum = 0
6593 00:56:15.958935 5, 0xFFFF, sum = 0
6594 00:56:15.961881 6, 0xFFFF, sum = 0
6595 00:56:15.961952 7, 0xFFFF, sum = 0
6596 00:56:15.965560 8, 0xFFFF, sum = 0
6597 00:56:15.965628 9, 0xFFFF, sum = 0
6598 00:56:15.968472 10, 0xFFFF, sum = 0
6599 00:56:15.971938 11, 0xFFFF, sum = 0
6600 00:56:15.972036 12, 0xFFFF, sum = 0
6601 00:56:15.974999 13, 0x0, sum = 1
6602 00:56:15.975092 14, 0x0, sum = 2
6603 00:56:15.978612 15, 0x0, sum = 3
6604 00:56:15.978704 16, 0x0, sum = 4
6605 00:56:15.978792 best_step = 14
6606 00:56:15.978875
6607 00:56:15.981516 ==
6608 00:56:15.984868 Dram Type= 6, Freq= 0, CH_0, rank 1
6609 00:56:15.988415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 00:56:15.988507 ==
6611 00:56:15.988591 RX Vref Scan: 0
6612 00:56:15.988680
6613 00:56:15.992015 RX Vref 0 -> 0, step: 1
6614 00:56:15.992106
6615 00:56:15.995097 RX Delay -359 -> 252, step: 8
6616 00:56:16.002016 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6617 00:56:16.005462 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6618 00:56:16.008454 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6619 00:56:16.012129 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6620 00:56:16.018697 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6621 00:56:16.022195 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6622 00:56:16.025122 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6623 00:56:16.028686 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6624 00:56:16.035420 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6625 00:56:16.038862 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6626 00:56:16.041772 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6627 00:56:16.045107 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6628 00:56:16.051858 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6629 00:56:16.055519 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6630 00:56:16.058444 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6631 00:56:16.064941 iDelay=217, Bit 15, Center -52 (-303 ~ 200) 504
6632 00:56:16.065011 ==
6633 00:56:16.068399 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 00:56:16.071889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 00:56:16.071985 ==
6636 00:56:16.072075 DQS Delay:
6637 00:56:16.075383 DQS0 = 60, DQS1 = 72
6638 00:56:16.075480 DQM Delay:
6639 00:56:16.078365 DQM0 = 11, DQM1 = 16
6640 00:56:16.078456 DQ Delay:
6641 00:56:16.081973 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6642 00:56:16.084953 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6643 00:56:16.088740 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6644 00:56:16.092072 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =20
6645 00:56:16.092164
6646 00:56:16.092250
6647 00:56:16.098681 [DQSOSCAuto] RK1, (LSB)MR18= 0xd086, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6648 00:56:16.101812 CH0 RK1: MR19=C0C, MR18=D086
6649 00:56:16.108616 CH0_RK1: MR19=0xC0C, MR18=0xD086, DQSOSC=384, MR23=63, INC=400, DEC=267
6650 00:56:16.111469 [RxdqsGatingPostProcess] freq 400
6651 00:56:16.118043 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6652 00:56:16.118116 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 00:56:16.121587 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 00:56:16.125119 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 00:56:16.128473 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 00:56:16.131550 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 00:56:16.135138 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 00:56:16.138120 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 00:56:16.141702 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 00:56:16.145060 Pre-setting of DQS Precalculation
6661 00:56:16.148087 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6662 00:56:16.151725 ==
6663 00:56:16.155076 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 00:56:16.158148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 00:56:16.158239 ==
6666 00:56:16.164706 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 00:56:16.168023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6668 00:56:16.171409 [CA 0] Center 36 (8~64) winsize 57
6669 00:56:16.175108 [CA 1] Center 36 (8~64) winsize 57
6670 00:56:16.178228 [CA 2] Center 36 (8~64) winsize 57
6671 00:56:16.181263 [CA 3] Center 36 (8~64) winsize 57
6672 00:56:16.184850 [CA 4] Center 36 (8~64) winsize 57
6673 00:56:16.188433 [CA 5] Center 36 (8~64) winsize 57
6674 00:56:16.188533
6675 00:56:16.191433 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6676 00:56:16.191528
6677 00:56:16.194928 [CATrainingPosCal] consider 1 rank data
6678 00:56:16.197870 u2DelayCellTimex100 = 270/100 ps
6679 00:56:16.201438 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 00:56:16.204437 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 00:56:16.208073 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 00:56:16.210901 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 00:56:16.217715 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 00:56:16.221264 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 00:56:16.221340
6686 00:56:16.224244 CA PerBit enable=1, Macro0, CA PI delay=36
6687 00:56:16.224315
6688 00:56:16.227856 [CBTSetCACLKResult] CA Dly = 36
6689 00:56:16.227950 CS Dly: 1 (0~32)
6690 00:56:16.228037 ==
6691 00:56:16.231368 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 00:56:16.237391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 00:56:16.237468 ==
6694 00:56:16.241024 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6695 00:56:16.247573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6696 00:56:16.250563 [CA 0] Center 36 (8~64) winsize 57
6697 00:56:16.254190 [CA 1] Center 36 (8~64) winsize 57
6698 00:56:16.257665 [CA 2] Center 36 (8~64) winsize 57
6699 00:56:16.260616 [CA 3] Center 36 (8~64) winsize 57
6700 00:56:16.264050 [CA 4] Center 36 (8~64) winsize 57
6701 00:56:16.267009 [CA 5] Center 36 (8~64) winsize 57
6702 00:56:16.267104
6703 00:56:16.270680 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6704 00:56:16.270778
6705 00:56:16.274194 [CATrainingPosCal] consider 2 rank data
6706 00:56:16.277060 u2DelayCellTimex100 = 270/100 ps
6707 00:56:16.280686 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 00:56:16.284217 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 00:56:16.287382 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 00:56:16.290383 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 00:56:16.293861 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 00:56:16.296938 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 00:56:16.300525
6714 00:56:16.304091 CA PerBit enable=1, Macro0, CA PI delay=36
6715 00:56:16.304189
6716 00:56:16.307082 [CBTSetCACLKResult] CA Dly = 36
6717 00:56:16.307174 CS Dly: 1 (0~32)
6718 00:56:16.307262
6719 00:56:16.310353 ----->DramcWriteLeveling(PI) begin...
6720 00:56:16.310454 ==
6721 00:56:16.314015 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 00:56:16.317298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 00:56:16.317395 ==
6724 00:56:16.320706 Write leveling (Byte 0): 40 => 8
6725 00:56:16.323954 Write leveling (Byte 1): 40 => 8
6726 00:56:16.327442 DramcWriteLeveling(PI) end<-----
6727 00:56:16.327539
6728 00:56:16.327627 ==
6729 00:56:16.330423 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 00:56:16.337375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 00:56:16.337475 ==
6732 00:56:16.337562 [Gating] SW mode calibration
6733 00:56:16.346892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6734 00:56:16.350507 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6735 00:56:16.353976 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6736 00:56:16.360497 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6737 00:56:16.363499 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 00:56:16.367024 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 00:56:16.373722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 00:56:16.376793 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 00:56:16.380251 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 00:56:16.386929 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 00:56:16.389912 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 00:56:16.393529 Total UI for P1: 0, mck2ui 16
6745 00:56:16.397023 best dqsien dly found for B0: ( 0, 14, 24)
6746 00:56:16.400132 Total UI for P1: 0, mck2ui 16
6747 00:56:16.403477 best dqsien dly found for B1: ( 0, 14, 24)
6748 00:56:16.407076 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6749 00:56:16.409927 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6750 00:56:16.410022
6751 00:56:16.413516 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 00:56:16.416962 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 00:56:16.420323 [Gating] SW calibration Done
6754 00:56:16.420420 ==
6755 00:56:16.423316 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 00:56:16.430104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 00:56:16.430210 ==
6758 00:56:16.430299 RX Vref Scan: 0
6759 00:56:16.430391
6760 00:56:16.433646 RX Vref 0 -> 0, step: 1
6761 00:56:16.433736
6762 00:56:16.436747 RX Delay -410 -> 252, step: 16
6763 00:56:16.439935 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6764 00:56:16.443463 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6765 00:56:16.446644 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6766 00:56:16.453252 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6767 00:56:16.456947 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6768 00:56:16.459954 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6769 00:56:16.462990 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6770 00:56:16.470004 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6771 00:56:16.473471 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6772 00:56:16.476507 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6773 00:56:16.480098 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6774 00:56:16.486455 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6775 00:56:16.489507 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6776 00:56:16.493130 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6777 00:56:16.499743 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6778 00:56:16.503328 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6779 00:56:16.503399 ==
6780 00:56:16.506232 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 00:56:16.509558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 00:56:16.509634 ==
6783 00:56:16.512906 DQS Delay:
6784 00:56:16.512975 DQS0 = 51, DQS1 = 67
6785 00:56:16.513033 DQM Delay:
6786 00:56:16.515895 DQM0 = 13, DQM1 = 19
6787 00:56:16.515984 DQ Delay:
6788 00:56:16.519493 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6789 00:56:16.522645 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6790 00:56:16.526089 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6791 00:56:16.529716 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6792 00:56:16.529785
6793 00:56:16.529847
6794 00:56:16.529902 ==
6795 00:56:16.532740 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 00:56:16.536101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 00:56:16.539215 ==
6798 00:56:16.539288
6799 00:56:16.539346
6800 00:56:16.539401 TX Vref Scan disable
6801 00:56:16.542527 == TX Byte 0 ==
6802 00:56:16.545922 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 00:56:16.549534 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 00:56:16.552632 == TX Byte 1 ==
6805 00:56:16.556041 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 00:56:16.559326 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 00:56:16.559468 ==
6808 00:56:16.562736 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 00:56:16.565980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 00:56:16.569161 ==
6811 00:56:16.569238
6812 00:56:16.569299
6813 00:56:16.569354 TX Vref Scan disable
6814 00:56:16.572749 == TX Byte 0 ==
6815 00:56:16.576054 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6816 00:56:16.579485 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6817 00:56:16.582560 == TX Byte 1 ==
6818 00:56:16.586221 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 00:56:16.589611 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 00:56:16.589682
6821 00:56:16.592615 [DATLAT]
6822 00:56:16.592711 Freq=400, CH1 RK0
6823 00:56:16.592797
6824 00:56:16.596158 DATLAT Default: 0xf
6825 00:56:16.596250 0, 0xFFFF, sum = 0
6826 00:56:16.599200 1, 0xFFFF, sum = 0
6827 00:56:16.599310 2, 0xFFFF, sum = 0
6828 00:56:16.602298 3, 0xFFFF, sum = 0
6829 00:56:16.602388 4, 0xFFFF, sum = 0
6830 00:56:16.606006 5, 0xFFFF, sum = 0
6831 00:56:16.606097 6, 0xFFFF, sum = 0
6832 00:56:16.608991 7, 0xFFFF, sum = 0
6833 00:56:16.609056 8, 0xFFFF, sum = 0
6834 00:56:16.612566 9, 0xFFFF, sum = 0
6835 00:56:16.612706 10, 0xFFFF, sum = 0
6836 00:56:16.615981 11, 0xFFFF, sum = 0
6837 00:56:16.616062 12, 0xFFFF, sum = 0
6838 00:56:16.619093 13, 0x0, sum = 1
6839 00:56:16.619160 14, 0x0, sum = 2
6840 00:56:16.622604 15, 0x0, sum = 3
6841 00:56:16.622673 16, 0x0, sum = 4
6842 00:56:16.625683 best_step = 14
6843 00:56:16.625748
6844 00:56:16.625802 ==
6845 00:56:16.629045 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 00:56:16.632230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 00:56:16.632301 ==
6848 00:56:16.635876 RX Vref Scan: 1
6849 00:56:16.635942
6850 00:56:16.635996 RX Vref 0 -> 0, step: 1
6851 00:56:16.636050
6852 00:56:16.639331 RX Delay -375 -> 252, step: 8
6853 00:56:16.639419
6854 00:56:16.642327 Set Vref, RX VrefLevel [Byte0]: 52
6855 00:56:16.645767 [Byte1]: 56
6856 00:56:16.650592
6857 00:56:16.650682 Final RX Vref Byte 0 = 52 to rank0
6858 00:56:16.654155 Final RX Vref Byte 1 = 56 to rank0
6859 00:56:16.657306 Final RX Vref Byte 0 = 52 to rank1
6860 00:56:16.660322 Final RX Vref Byte 1 = 56 to rank1==
6861 00:56:16.663965 Dram Type= 6, Freq= 0, CH_1, rank 0
6862 00:56:16.670639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 00:56:16.670710 ==
6864 00:56:16.670767 DQS Delay:
6865 00:56:16.673815 DQS0 = 56, DQS1 = 72
6866 00:56:16.673895 DQM Delay:
6867 00:56:16.673948 DQM0 = 13, DQM1 = 17
6868 00:56:16.677264 DQ Delay:
6869 00:56:16.680086 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6870 00:56:16.683634 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =12
6871 00:56:16.686944 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =12
6872 00:56:16.690241 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6873 00:56:16.690305
6874 00:56:16.690359
6875 00:56:16.696933 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e70, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6876 00:56:16.700271 CH1 RK0: MR19=C0C, MR18=5E70
6877 00:56:16.706894 CH1_RK0: MR19=0xC0C, MR18=0x5E70, DQSOSC=395, MR23=63, INC=378, DEC=252
6878 00:56:16.706979 ==
6879 00:56:16.710433 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 00:56:16.713460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 00:56:16.713539 ==
6882 00:56:16.716537 [Gating] SW mode calibration
6883 00:56:16.723213 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6884 00:56:16.729656 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6885 00:56:16.732942 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 00:56:16.736581 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 00:56:16.743105 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 00:56:16.746127 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 00:56:16.749605 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 00:56:16.756098 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 00:56:16.759693 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 00:56:16.762775 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 00:56:16.769388 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 00:56:16.769474 Total UI for P1: 0, mck2ui 16
6895 00:56:16.776008 best dqsien dly found for B0: ( 0, 14, 24)
6896 00:56:16.776092 Total UI for P1: 0, mck2ui 16
6897 00:56:16.782642 best dqsien dly found for B1: ( 0, 14, 24)
6898 00:56:16.786331 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6899 00:56:16.789227 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6900 00:56:16.789308
6901 00:56:16.792784 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 00:56:16.796194 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 00:56:16.799112 [Gating] SW calibration Done
6904 00:56:16.799192 ==
6905 00:56:16.802599 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 00:56:16.805814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 00:56:16.805894 ==
6908 00:56:16.809157 RX Vref Scan: 0
6909 00:56:16.809237
6910 00:56:16.809339 RX Vref 0 -> 0, step: 1
6911 00:56:16.812339
6912 00:56:16.812416 RX Delay -410 -> 252, step: 16
6913 00:56:16.819028 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6914 00:56:16.822693 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6915 00:56:16.825656 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6916 00:56:16.828789 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6917 00:56:16.835639 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6918 00:56:16.839039 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6919 00:56:16.842274 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6920 00:56:16.845798 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6921 00:56:16.852113 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6922 00:56:16.855713 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6923 00:56:16.858732 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6924 00:56:16.865242 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6925 00:56:16.868870 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6926 00:56:16.872384 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6927 00:56:16.875398 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6928 00:56:16.882015 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6929 00:56:16.882099 ==
6930 00:56:16.885082 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 00:56:16.888906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 00:56:16.888988 ==
6933 00:56:16.889059 DQS Delay:
6934 00:56:16.891931 DQS0 = 59, DQS1 = 67
6935 00:56:16.892007 DQM Delay:
6936 00:56:16.894869 DQM0 = 19, DQM1 = 21
6937 00:56:16.894945 DQ Delay:
6938 00:56:16.898557 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6939 00:56:16.901593 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6940 00:56:16.905169 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6941 00:56:16.908067 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6942 00:56:16.908169
6943 00:56:16.908279
6944 00:56:16.908372 ==
6945 00:56:16.911692 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 00:56:16.915300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 00:56:16.915378 ==
6948 00:56:16.918451
6949 00:56:16.918530
6950 00:56:16.918597 TX Vref Scan disable
6951 00:56:16.921904 == TX Byte 0 ==
6952 00:56:16.924751 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6953 00:56:16.928333 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6954 00:56:16.931192 == TX Byte 1 ==
6955 00:56:16.934974 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6956 00:56:16.938090 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6957 00:56:16.938169 ==
6958 00:56:16.941518 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 00:56:16.944800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 00:56:16.947947 ==
6961 00:56:16.948040
6962 00:56:16.948109
6963 00:56:16.948176 TX Vref Scan disable
6964 00:56:16.951553 == TX Byte 0 ==
6965 00:56:16.954591 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6966 00:56:16.958337 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6967 00:56:16.961407 == TX Byte 1 ==
6968 00:56:16.964477 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6969 00:56:16.967835 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6970 00:56:16.967907
6971 00:56:16.967964 [DATLAT]
6972 00:56:16.971390 Freq=400, CH1 RK1
6973 00:56:16.971458
6974 00:56:16.974319 DATLAT Default: 0xe
6975 00:56:16.974388 0, 0xFFFF, sum = 0
6976 00:56:16.977909 1, 0xFFFF, sum = 0
6977 00:56:16.977976 2, 0xFFFF, sum = 0
6978 00:56:16.980965 3, 0xFFFF, sum = 0
6979 00:56:16.981041 4, 0xFFFF, sum = 0
6980 00:56:16.984586 5, 0xFFFF, sum = 0
6981 00:56:16.984727 6, 0xFFFF, sum = 0
6982 00:56:16.987705 7, 0xFFFF, sum = 0
6983 00:56:16.987782 8, 0xFFFF, sum = 0
6984 00:56:16.991273 9, 0xFFFF, sum = 0
6985 00:56:16.991350 10, 0xFFFF, sum = 0
6986 00:56:16.994297 11, 0xFFFF, sum = 0
6987 00:56:16.994374 12, 0xFFFF, sum = 0
6988 00:56:16.997925 13, 0x0, sum = 1
6989 00:56:16.998002 14, 0x0, sum = 2
6990 00:56:17.000870 15, 0x0, sum = 3
6991 00:56:17.000946 16, 0x0, sum = 4
6992 00:56:17.004484 best_step = 14
6993 00:56:17.004559
6994 00:56:17.004618 ==
6995 00:56:17.007451 Dram Type= 6, Freq= 0, CH_1, rank 1
6996 00:56:17.011161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6997 00:56:17.011273 ==
6998 00:56:17.014687 RX Vref Scan: 0
6999 00:56:17.014801
7000 00:56:17.014893 RX Vref 0 -> 0, step: 1
7001 00:56:17.014977
7002 00:56:17.017558 RX Delay -375 -> 252, step: 8
7003 00:56:17.025496 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7004 00:56:17.028819 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7005 00:56:17.032229 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
7006 00:56:17.035891 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7007 00:56:17.042525 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
7008 00:56:17.045423 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7009 00:56:17.049072 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7010 00:56:17.052374 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7011 00:56:17.058713 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7012 00:56:17.062462 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7013 00:56:17.065355 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7014 00:56:17.068883 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
7015 00:56:17.075656 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7016 00:56:17.078891 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7017 00:56:17.082253 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7018 00:56:17.088982 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7019 00:56:17.089106 ==
7020 00:56:17.092227 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 00:56:17.095540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 00:56:17.095673 ==
7023 00:56:17.095801 DQS Delay:
7024 00:56:17.098625 DQS0 = 56, DQS1 = 64
7025 00:56:17.098714 DQM Delay:
7026 00:56:17.102274 DQM0 = 9, DQM1 = 10
7027 00:56:17.102370 DQ Delay:
7028 00:56:17.105186 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
7029 00:56:17.108674 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =4
7030 00:56:17.111794 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7031 00:56:17.115364 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7032 00:56:17.115444
7033 00:56:17.115505
7034 00:56:17.121977 [DQSOSCAuto] RK1, (LSB)MR18= 0x86b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
7035 00:56:17.125015 CH1 RK1: MR19=C0C, MR18=86B5
7036 00:56:17.131750 CH1_RK1: MR19=0xC0C, MR18=0x86B5, DQSOSC=387, MR23=63, INC=394, DEC=262
7037 00:56:17.135175 [RxdqsGatingPostProcess] freq 400
7038 00:56:17.141693 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7039 00:56:17.144796 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 00:56:17.144884 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 00:56:17.148281 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 00:56:17.151873 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 00:56:17.154907 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 00:56:17.158319 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 00:56:17.161620 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 00:56:17.165019 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 00:56:17.168430 Pre-setting of DQS Precalculation
7048 00:56:17.174495 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7049 00:56:17.181081 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7050 00:56:17.188296 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7051 00:56:17.188368
7052 00:56:17.188426
7053 00:56:17.191180 [Calibration Summary] 800 Mbps
7054 00:56:17.191245 CH 0, Rank 0
7055 00:56:17.194625 SW Impedance : PASS
7056 00:56:17.197854 DUTY Scan : NO K
7057 00:56:17.197919 ZQ Calibration : PASS
7058 00:56:17.201369 Jitter Meter : NO K
7059 00:56:17.204461 CBT Training : PASS
7060 00:56:17.204550 Write leveling : PASS
7061 00:56:17.207914 RX DQS gating : PASS
7062 00:56:17.207978 RX DQ/DQS(RDDQC) : PASS
7063 00:56:17.211104 TX DQ/DQS : PASS
7064 00:56:17.214299 RX DATLAT : PASS
7065 00:56:17.214366 RX DQ/DQS(Engine): PASS
7066 00:56:17.218199 TX OE : NO K
7067 00:56:17.218264 All Pass.
7068 00:56:17.218317
7069 00:56:17.221438 CH 0, Rank 1
7070 00:56:17.221512 SW Impedance : PASS
7071 00:56:17.224490 DUTY Scan : NO K
7072 00:56:17.228128 ZQ Calibration : PASS
7073 00:56:17.228195 Jitter Meter : NO K
7074 00:56:17.231206 CBT Training : PASS
7075 00:56:17.234534 Write leveling : NO K
7076 00:56:17.234597 RX DQS gating : PASS
7077 00:56:17.238074 RX DQ/DQS(RDDQC) : PASS
7078 00:56:17.240862 TX DQ/DQS : PASS
7079 00:56:17.240925 RX DATLAT : PASS
7080 00:56:17.244790 RX DQ/DQS(Engine): PASS
7081 00:56:17.247788 TX OE : NO K
7082 00:56:17.247852 All Pass.
7083 00:56:17.247904
7084 00:56:17.247972 CH 1, Rank 0
7085 00:56:17.250831 SW Impedance : PASS
7086 00:56:17.254476 DUTY Scan : NO K
7087 00:56:17.254538 ZQ Calibration : PASS
7088 00:56:17.257465 Jitter Meter : NO K
7089 00:56:17.261166 CBT Training : PASS
7090 00:56:17.261229 Write leveling : PASS
7091 00:56:17.264562 RX DQS gating : PASS
7092 00:56:17.264657 RX DQ/DQS(RDDQC) : PASS
7093 00:56:17.267522 TX DQ/DQS : PASS
7094 00:56:17.270910 RX DATLAT : PASS
7095 00:56:17.270988 RX DQ/DQS(Engine): PASS
7096 00:56:17.274150 TX OE : NO K
7097 00:56:17.274211 All Pass.
7098 00:56:17.274267
7099 00:56:17.277584 CH 1, Rank 1
7100 00:56:17.277645 SW Impedance : PASS
7101 00:56:17.280638 DUTY Scan : NO K
7102 00:56:17.284392 ZQ Calibration : PASS
7103 00:56:17.284453 Jitter Meter : NO K
7104 00:56:17.287360 CBT Training : PASS
7105 00:56:17.290917 Write leveling : NO K
7106 00:56:17.290992 RX DQS gating : PASS
7107 00:56:17.294499 RX DQ/DQS(RDDQC) : PASS
7108 00:56:17.297542 TX DQ/DQS : PASS
7109 00:56:17.297603 RX DATLAT : PASS
7110 00:56:17.300600 RX DQ/DQS(Engine): PASS
7111 00:56:17.304254 TX OE : NO K
7112 00:56:17.304314 All Pass.
7113 00:56:17.304380
7114 00:56:17.304445 DramC Write-DBI off
7115 00:56:17.307655 PER_BANK_REFRESH: Hybrid Mode
7116 00:56:17.310646 TX_TRACKING: ON
7117 00:56:17.317693 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7118 00:56:17.321007 [FAST_K] Save calibration result to emmc
7119 00:56:17.327479 dramc_set_vcore_voltage set vcore to 725000
7120 00:56:17.327554 Read voltage for 1600, 0
7121 00:56:17.331297 Vio18 = 0
7122 00:56:17.331374 Vcore = 725000
7123 00:56:17.331441 Vdram = 0
7124 00:56:17.331492 Vddq = 0
7125 00:56:17.334165 Vmddr = 0
7126 00:56:17.337164 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7127 00:56:17.344222 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7128 00:56:17.347265 MEM_TYPE=3, freq_sel=13
7129 00:56:17.347334 sv_algorithm_assistance_LP4_3733
7130 00:56:17.354015 ============ PULL DRAM RESETB DOWN ============
7131 00:56:17.357492 ========== PULL DRAM RESETB DOWN end =========
7132 00:56:17.360486 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7133 00:56:17.364099 ===================================
7134 00:56:17.367116 LPDDR4 DRAM CONFIGURATION
7135 00:56:17.370495 ===================================
7136 00:56:17.374069 EX_ROW_EN[0] = 0x0
7137 00:56:17.374132 EX_ROW_EN[1] = 0x0
7138 00:56:17.376998 LP4Y_EN = 0x0
7139 00:56:17.377075 WORK_FSP = 0x1
7140 00:56:17.380322 WL = 0x5
7141 00:56:17.380398 RL = 0x5
7142 00:56:17.384175 BL = 0x2
7143 00:56:17.384253 RPST = 0x0
7144 00:56:17.387351 RD_PRE = 0x0
7145 00:56:17.387429 WR_PRE = 0x1
7146 00:56:17.390294 WR_PST = 0x1
7147 00:56:17.390372 DBI_WR = 0x0
7148 00:56:17.393883 DBI_RD = 0x0
7149 00:56:17.396742 OTF = 0x1
7150 00:56:17.400277 ===================================
7151 00:56:17.403348 ===================================
7152 00:56:17.403425 ANA top config
7153 00:56:17.406944 ===================================
7154 00:56:17.410421 DLL_ASYNC_EN = 0
7155 00:56:17.410498 ALL_SLAVE_EN = 0
7156 00:56:17.413534 NEW_RANK_MODE = 1
7157 00:56:17.417005 DLL_IDLE_MODE = 1
7158 00:56:17.420101 LP45_APHY_COMB_EN = 1
7159 00:56:17.423732 TX_ODT_DIS = 0
7160 00:56:17.423824 NEW_8X_MODE = 1
7161 00:56:17.426702 ===================================
7162 00:56:17.429706 ===================================
7163 00:56:17.433497 data_rate = 3200
7164 00:56:17.436909 CKR = 1
7165 00:56:17.439842 DQ_P2S_RATIO = 8
7166 00:56:17.443214 ===================================
7167 00:56:17.446488 CA_P2S_RATIO = 8
7168 00:56:17.449884 DQ_CA_OPEN = 0
7169 00:56:17.449953 DQ_SEMI_OPEN = 0
7170 00:56:17.453095 CA_SEMI_OPEN = 0
7171 00:56:17.456674 CA_FULL_RATE = 0
7172 00:56:17.459863 DQ_CKDIV4_EN = 0
7173 00:56:17.462962 CA_CKDIV4_EN = 0
7174 00:56:17.466448 CA_PREDIV_EN = 0
7175 00:56:17.466551 PH8_DLY = 12
7176 00:56:17.469606 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7177 00:56:17.472969 DQ_AAMCK_DIV = 4
7178 00:56:17.476464 CA_AAMCK_DIV = 4
7179 00:56:17.479945 CA_ADMCK_DIV = 4
7180 00:56:17.482975 DQ_TRACK_CA_EN = 0
7181 00:56:17.486448 CA_PICK = 1600
7182 00:56:17.486519 CA_MCKIO = 1600
7183 00:56:17.489628 MCKIO_SEMI = 0
7184 00:56:17.493123 PLL_FREQ = 3068
7185 00:56:17.496105 DQ_UI_PI_RATIO = 32
7186 00:56:17.499721 CA_UI_PI_RATIO = 0
7187 00:56:17.502521 ===================================
7188 00:56:17.506027 ===================================
7189 00:56:17.509655 memory_type:LPDDR4
7190 00:56:17.509746 GP_NUM : 10
7191 00:56:17.512613 SRAM_EN : 1
7192 00:56:17.512697 MD32_EN : 0
7193 00:56:17.515960 ===================================
7194 00:56:17.519599 [ANA_INIT] >>>>>>>>>>>>>>
7195 00:56:17.522664 <<<<<< [CONFIGURE PHASE]: ANA_TX
7196 00:56:17.526230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7197 00:56:17.529238 ===================================
7198 00:56:17.533008 data_rate = 3200,PCW = 0X7600
7199 00:56:17.536020 ===================================
7200 00:56:17.539518 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7201 00:56:17.545897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 00:56:17.549071 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 00:56:17.556119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7204 00:56:17.559092 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7205 00:56:17.562564 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7206 00:56:17.562646 [ANA_INIT] flow start
7207 00:56:17.565946 [ANA_INIT] PLL >>>>>>>>
7208 00:56:17.568871 [ANA_INIT] PLL <<<<<<<<
7209 00:56:17.568965 [ANA_INIT] MIDPI >>>>>>>>
7210 00:56:17.572463 [ANA_INIT] MIDPI <<<<<<<<
7211 00:56:17.576004 [ANA_INIT] DLL >>>>>>>>
7212 00:56:17.576075 [ANA_INIT] DLL <<<<<<<<
7213 00:56:17.579110 [ANA_INIT] flow end
7214 00:56:17.582274 ============ LP4 DIFF to SE enter ============
7215 00:56:17.588649 ============ LP4 DIFF to SE exit ============
7216 00:56:17.588721 [ANA_INIT] <<<<<<<<<<<<<
7217 00:56:17.592152 [Flow] Enable top DCM control >>>>>
7218 00:56:17.595701 [Flow] Enable top DCM control <<<<<
7219 00:56:17.598691 Enable DLL master slave shuffle
7220 00:56:17.605218 ==============================================================
7221 00:56:17.605296 Gating Mode config
7222 00:56:17.612092 ==============================================================
7223 00:56:17.615167 Config description:
7224 00:56:17.625156 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7225 00:56:17.631797 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7226 00:56:17.635309 SELPH_MODE 0: By rank 1: By Phase
7227 00:56:17.641902 ==============================================================
7228 00:56:17.645479 GAT_TRACK_EN = 1
7229 00:56:17.645557 RX_GATING_MODE = 2
7230 00:56:17.648387 RX_GATING_TRACK_MODE = 2
7231 00:56:17.651941 SELPH_MODE = 1
7232 00:56:17.655358 PICG_EARLY_EN = 1
7233 00:56:17.658370 VALID_LAT_VALUE = 1
7234 00:56:17.665056 ==============================================================
7235 00:56:17.668560 Enter into Gating configuration >>>>
7236 00:56:17.671550 Exit from Gating configuration <<<<
7237 00:56:17.674979 Enter into DVFS_PRE_config >>>>>
7238 00:56:17.685081 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7239 00:56:17.688118 Exit from DVFS_PRE_config <<<<<
7240 00:56:17.691707 Enter into PICG configuration >>>>
7241 00:56:17.694635 Exit from PICG configuration <<<<
7242 00:56:17.698041 [RX_INPUT] configuration >>>>>
7243 00:56:17.701291 [RX_INPUT] configuration <<<<<
7244 00:56:17.704940 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7245 00:56:17.711430 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7246 00:56:17.717882 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7247 00:56:17.724822 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7248 00:56:17.727645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7249 00:56:17.734724 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7250 00:56:17.737953 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7251 00:56:17.744626 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7252 00:56:17.747576 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7253 00:56:17.751076 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7254 00:56:17.754583 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7255 00:56:17.761110 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 00:56:17.764146 ===================================
7257 00:56:17.764220 LPDDR4 DRAM CONFIGURATION
7258 00:56:17.767926 ===================================
7259 00:56:17.770774 EX_ROW_EN[0] = 0x0
7260 00:56:17.774314 EX_ROW_EN[1] = 0x0
7261 00:56:17.774412 LP4Y_EN = 0x0
7262 00:56:17.777842 WORK_FSP = 0x1
7263 00:56:17.777933 WL = 0x5
7264 00:56:17.780749 RL = 0x5
7265 00:56:17.780815 BL = 0x2
7266 00:56:17.784446 RPST = 0x0
7267 00:56:17.784541 RD_PRE = 0x0
7268 00:56:17.787440 WR_PRE = 0x1
7269 00:56:17.787534 WR_PST = 0x1
7270 00:56:17.790582 DBI_WR = 0x0
7271 00:56:17.790668 DBI_RD = 0x0
7272 00:56:17.794286 OTF = 0x1
7273 00:56:17.797802 ===================================
7274 00:56:17.800714 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7275 00:56:17.804204 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7276 00:56:17.810923 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7277 00:56:17.814443 ===================================
7278 00:56:17.814573 LPDDR4 DRAM CONFIGURATION
7279 00:56:17.817622 ===================================
7280 00:56:17.820542 EX_ROW_EN[0] = 0x10
7281 00:56:17.824092 EX_ROW_EN[1] = 0x0
7282 00:56:17.824184 LP4Y_EN = 0x0
7283 00:56:17.827562 WORK_FSP = 0x1
7284 00:56:17.827638 WL = 0x5
7285 00:56:17.830527 RL = 0x5
7286 00:56:17.830602 BL = 0x2
7287 00:56:17.834024 RPST = 0x0
7288 00:56:17.834093 RD_PRE = 0x0
7289 00:56:17.837415 WR_PRE = 0x1
7290 00:56:17.837513 WR_PST = 0x1
7291 00:56:17.840549 DBI_WR = 0x0
7292 00:56:17.840640 DBI_RD = 0x0
7293 00:56:17.843655 OTF = 0x1
7294 00:56:17.847218 ===================================
7295 00:56:17.853857 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7296 00:56:17.853929 ==
7297 00:56:17.857203 Dram Type= 6, Freq= 0, CH_0, rank 0
7298 00:56:17.860514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 00:56:17.860591 ==
7300 00:56:17.863632 [Duty_Offset_Calibration]
7301 00:56:17.863708 B0:2 B1:0 CA:3
7302 00:56:17.863767
7303 00:56:17.867116 [DutyScan_Calibration_Flow] k_type=0
7304 00:56:17.878116
7305 00:56:17.878194 ==CLK 0==
7306 00:56:17.881102 Final CLK duty delay cell = 0
7307 00:56:17.884561 [0] MAX Duty = 5062%(X100), DQS PI = 20
7308 00:56:17.887465 [0] MIN Duty = 4875%(X100), DQS PI = 54
7309 00:56:17.887541 [0] AVG Duty = 4968%(X100)
7310 00:56:17.891109
7311 00:56:17.894145 CH0 CLK Duty spec in!! Max-Min= 187%
7312 00:56:17.897769 [DutyScan_Calibration_Flow] ====Done====
7313 00:56:17.897846
7314 00:56:17.901404 [DutyScan_Calibration_Flow] k_type=1
7315 00:56:17.917989
7316 00:56:17.918067 ==DQS 0 ==
7317 00:56:17.921127 Final DQS duty delay cell = 0
7318 00:56:17.924477 [0] MAX Duty = 5094%(X100), DQS PI = 28
7319 00:56:17.928049 [0] MIN Duty = 4875%(X100), DQS PI = 50
7320 00:56:17.930884 [0] AVG Duty = 4984%(X100)
7321 00:56:17.930960
7322 00:56:17.931019 ==DQS 1 ==
7323 00:56:17.934461 Final DQS duty delay cell = 0
7324 00:56:17.937537 [0] MAX Duty = 5156%(X100), DQS PI = 30
7325 00:56:17.941193 [0] MIN Duty = 5062%(X100), DQS PI = 0
7326 00:56:17.944306 [0] AVG Duty = 5109%(X100)
7327 00:56:17.944382
7328 00:56:17.947280 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7329 00:56:17.947356
7330 00:56:17.951008 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7331 00:56:17.953937 [DutyScan_Calibration_Flow] ====Done====
7332 00:56:17.954013
7333 00:56:17.957192 [DutyScan_Calibration_Flow] k_type=3
7334 00:56:17.975808
7335 00:56:17.975889 ==DQM 0 ==
7336 00:56:17.978827 Final DQM duty delay cell = 0
7337 00:56:17.982230 [0] MAX Duty = 5187%(X100), DQS PI = 30
7338 00:56:17.985755 [0] MIN Duty = 4875%(X100), DQS PI = 2
7339 00:56:17.988749 [0] AVG Duty = 5031%(X100)
7340 00:56:17.988825
7341 00:56:17.988885 ==DQM 1 ==
7342 00:56:17.992415 Final DQM duty delay cell = 4
7343 00:56:17.995611 [4] MAX Duty = 5187%(X100), DQS PI = 62
7344 00:56:17.999039 [4] MIN Duty = 5000%(X100), DQS PI = 38
7345 00:56:18.002014 [4] AVG Duty = 5093%(X100)
7346 00:56:18.002090
7347 00:56:18.005562 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7348 00:56:18.005639
7349 00:56:18.008616 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7350 00:56:18.012225 [DutyScan_Calibration_Flow] ====Done====
7351 00:56:18.012301
7352 00:56:18.015169 [DutyScan_Calibration_Flow] k_type=2
7353 00:56:18.032110
7354 00:56:18.032223 ==DQ 0 ==
7355 00:56:18.035446 Final DQ duty delay cell = -4
7356 00:56:18.038985 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7357 00:56:18.042004 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7358 00:56:18.045561 [-4] AVG Duty = 4938%(X100)
7359 00:56:18.045652
7360 00:56:18.045738 ==DQ 1 ==
7361 00:56:18.048574 Final DQ duty delay cell = 0
7362 00:56:18.052249 [0] MAX Duty = 5156%(X100), DQS PI = 60
7363 00:56:18.055259 [0] MIN Duty = 5000%(X100), DQS PI = 16
7364 00:56:18.058906 [0] AVG Duty = 5078%(X100)
7365 00:56:18.059002
7366 00:56:18.061881 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7367 00:56:18.061975
7368 00:56:18.065505 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7369 00:56:18.068379 [DutyScan_Calibration_Flow] ====Done====
7370 00:56:18.068477 ==
7371 00:56:18.071585 Dram Type= 6, Freq= 0, CH_1, rank 0
7372 00:56:18.075191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7373 00:56:18.075268 ==
7374 00:56:18.078260 [Duty_Offset_Calibration]
7375 00:56:18.078349 B0:1 B1:-2 CA:1
7376 00:56:18.078446
7377 00:56:18.081750 [DutyScan_Calibration_Flow] k_type=0
7378 00:56:18.092956
7379 00:56:18.093033 ==CLK 0==
7380 00:56:18.096250 Final CLK duty delay cell = 0
7381 00:56:18.099474 [0] MAX Duty = 5093%(X100), DQS PI = 32
7382 00:56:18.102859 [0] MIN Duty = 4844%(X100), DQS PI = 58
7383 00:56:18.102960 [0] AVG Duty = 4968%(X100)
7384 00:56:18.106076
7385 00:56:18.106169 CH1 CLK Duty spec in!! Max-Min= 249%
7386 00:56:18.112513 [DutyScan_Calibration_Flow] ====Done====
7387 00:56:18.112609
7388 00:56:18.116232 [DutyScan_Calibration_Flow] k_type=1
7389 00:56:18.131791
7390 00:56:18.131870 ==DQS 0 ==
7391 00:56:18.135089 Final DQS duty delay cell = -4
7392 00:56:18.138379 [-4] MAX Duty = 4969%(X100), DQS PI = 26
7393 00:56:18.141442 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7394 00:56:18.144749 [-4] AVG Duty = 4906%(X100)
7395 00:56:18.144843
7396 00:56:18.144932 ==DQS 1 ==
7397 00:56:18.148395 Final DQS duty delay cell = 0
7398 00:56:18.151426 [0] MAX Duty = 5093%(X100), DQS PI = 0
7399 00:56:18.154440 [0] MIN Duty = 4844%(X100), DQS PI = 24
7400 00:56:18.158118 [0] AVG Duty = 4968%(X100)
7401 00:56:18.158214
7402 00:56:18.161635 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7403 00:56:18.161729
7404 00:56:18.164708 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7405 00:56:18.167698 [DutyScan_Calibration_Flow] ====Done====
7406 00:56:18.167784
7407 00:56:18.171402 [DutyScan_Calibration_Flow] k_type=3
7408 00:56:18.188655
7409 00:56:18.188753 ==DQM 0 ==
7410 00:56:18.192238 Final DQM duty delay cell = 0
7411 00:56:18.195233 [0] MAX Duty = 5031%(X100), DQS PI = 24
7412 00:56:18.198798 [0] MIN Duty = 4813%(X100), DQS PI = 56
7413 00:56:18.201907 [0] AVG Duty = 4922%(X100)
7414 00:56:18.201983
7415 00:56:18.202043 ==DQM 1 ==
7416 00:56:18.205385 Final DQM duty delay cell = 0
7417 00:56:18.208876 [0] MAX Duty = 5062%(X100), DQS PI = 34
7418 00:56:18.211777 [0] MIN Duty = 4875%(X100), DQS PI = 24
7419 00:56:18.215335 [0] AVG Duty = 4968%(X100)
7420 00:56:18.215411
7421 00:56:18.218742 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7422 00:56:18.218818
7423 00:56:18.222067 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7424 00:56:18.225278 [DutyScan_Calibration_Flow] ====Done====
7425 00:56:18.225369
7426 00:56:18.228354 [DutyScan_Calibration_Flow] k_type=2
7427 00:56:18.245637
7428 00:56:18.245715 ==DQ 0 ==
7429 00:56:18.249017 Final DQ duty delay cell = 0
7430 00:56:18.252453 [0] MAX Duty = 5093%(X100), DQS PI = 22
7431 00:56:18.255775 [0] MIN Duty = 4907%(X100), DQS PI = 62
7432 00:56:18.255852 [0] AVG Duty = 5000%(X100)
7433 00:56:18.258751
7434 00:56:18.258888 ==DQ 1 ==
7435 00:56:18.262423 Final DQ duty delay cell = 0
7436 00:56:18.265536 [0] MAX Duty = 5125%(X100), DQS PI = 34
7437 00:56:18.269126 [0] MIN Duty = 4938%(X100), DQS PI = 24
7438 00:56:18.269203 [0] AVG Duty = 5031%(X100)
7439 00:56:18.269263
7440 00:56:18.272091 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7441 00:56:18.275717
7442 00:56:18.278679 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7443 00:56:18.282269 [DutyScan_Calibration_Flow] ====Done====
7444 00:56:18.285094 nWR fixed to 30
7445 00:56:18.285171 [ModeRegInit_LP4] CH0 RK0
7446 00:56:18.288935 [ModeRegInit_LP4] CH0 RK1
7447 00:56:18.292285 [ModeRegInit_LP4] CH1 RK0
7448 00:56:18.295573 [ModeRegInit_LP4] CH1 RK1
7449 00:56:18.295650 match AC timing 5
7450 00:56:18.298684 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7451 00:56:18.305148 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7452 00:56:18.308662 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7453 00:56:18.315107 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7454 00:56:18.318487 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7455 00:56:18.318564 [MiockJmeterHQA]
7456 00:56:18.318623
7457 00:56:18.322163 [DramcMiockJmeter] u1RxGatingPI = 0
7458 00:56:18.325123 0 : 4260, 4031
7459 00:56:18.325201 4 : 4253, 4027
7460 00:56:18.328586 8 : 4361, 4138
7461 00:56:18.328700 12 : 4253, 4027
7462 00:56:18.328761 16 : 4252, 4027
7463 00:56:18.331516 20 : 4363, 4137
7464 00:56:18.331593 24 : 4365, 4140
7465 00:56:18.335278 28 : 4252, 4027
7466 00:56:18.335399 32 : 4253, 4026
7467 00:56:18.338361 36 : 4252, 4027
7468 00:56:18.338438 40 : 4361, 4137
7469 00:56:18.341838 44 : 4252, 4027
7470 00:56:18.341975 48 : 4360, 4137
7471 00:56:18.342036 52 : 4250, 4026
7472 00:56:18.345024 56 : 4250, 4027
7473 00:56:18.345102 60 : 4250, 4026
7474 00:56:18.348752 64 : 4250, 4027
7475 00:56:18.348829 68 : 4360, 4138
7476 00:56:18.351888 72 : 4250, 4027
7477 00:56:18.351978 76 : 4361, 4138
7478 00:56:18.352038 80 : 4250, 4026
7479 00:56:18.355083 84 : 4250, 4027
7480 00:56:18.355163 88 : 4250, 4027
7481 00:56:18.358192 92 : 4361, 4137
7482 00:56:18.358287 96 : 4250, 4027
7483 00:56:18.361930 100 : 4360, 4137
7484 00:56:18.362008 104 : 4361, 3629
7485 00:56:18.364961 108 : 4248, 2
7486 00:56:18.365098 112 : 4250, 0
7487 00:56:18.365159 116 : 4250, 0
7488 00:56:18.368440 120 : 4250, 0
7489 00:56:18.368519 124 : 4361, 0
7490 00:56:18.368579 128 : 4360, 0
7491 00:56:18.371949 132 : 4248, 0
7492 00:56:18.372072 136 : 4250, 0
7493 00:56:18.374874 140 : 4360, 0
7494 00:56:18.374951 144 : 4361, 0
7495 00:56:18.375041 148 : 4250, 0
7496 00:56:18.378438 152 : 4250, 0
7497 00:56:18.378517 156 : 4250, 0
7498 00:56:18.381527 160 : 4250, 0
7499 00:56:18.381606 164 : 4250, 0
7500 00:56:18.381668 168 : 4250, 0
7501 00:56:18.385076 172 : 4250, 0
7502 00:56:18.385156 176 : 4361, 0
7503 00:56:18.388103 180 : 4360, 0
7504 00:56:18.388181 184 : 4248, 0
7505 00:56:18.388243 188 : 4250, 0
7506 00:56:18.391717 192 : 4361, 0
7507 00:56:18.391796 196 : 4360, 0
7508 00:56:18.391857 200 : 4250, 0
7509 00:56:18.394973 204 : 4250, 0
7510 00:56:18.395052 208 : 4250, 0
7511 00:56:18.398221 212 : 4250, 0
7512 00:56:18.398298 216 : 4250, 0
7513 00:56:18.398359 220 : 4250, 0
7514 00:56:18.401374 224 : 4252, 0
7515 00:56:18.401451 228 : 4250, 0
7516 00:56:18.404624 232 : 4250, 0
7517 00:56:18.404755 236 : 4250, 893
7518 00:56:18.408094 240 : 4360, 4137
7519 00:56:18.408171 244 : 4360, 4137
7520 00:56:18.408232 248 : 4250, 4027
7521 00:56:18.411709 252 : 4363, 4140
7522 00:56:18.411831 256 : 4360, 4137
7523 00:56:18.414522 260 : 4250, 4026
7524 00:56:18.414599 264 : 4250, 4027
7525 00:56:18.418177 268 : 4250, 4027
7526 00:56:18.418254 272 : 4250, 4027
7527 00:56:18.421050 276 : 4250, 4026
7528 00:56:18.421127 280 : 4250, 4027
7529 00:56:18.424767 284 : 4250, 4027
7530 00:56:18.424844 288 : 4250, 4027
7531 00:56:18.427805 292 : 4360, 4137
7532 00:56:18.427881 296 : 4361, 4137
7533 00:56:18.431429 300 : 4248, 4025
7534 00:56:18.431507 304 : 4361, 4138
7535 00:56:18.434473 308 : 4360, 4137
7536 00:56:18.434550 312 : 4250, 4026
7537 00:56:18.434611 316 : 4250, 4027
7538 00:56:18.437967 320 : 4250, 4027
7539 00:56:18.438044 324 : 4250, 4027
7540 00:56:18.440967 328 : 4250, 4026
7541 00:56:18.441046 332 : 4250, 4027
7542 00:56:18.444515 336 : 4250, 4027
7543 00:56:18.444594 340 : 4250, 4027
7544 00:56:18.448098 344 : 4360, 4137
7545 00:56:18.448175 348 : 4361, 4137
7546 00:56:18.451099 352 : 4250, 4017
7547 00:56:18.451176 356 : 4361, 3004
7548 00:56:18.454649 360 : 4360, 1
7549 00:56:18.454726
7550 00:56:18.454785 MIOCK jitter meter ch=0
7551 00:56:18.454856
7552 00:56:18.457491 1T = (360-108) = 252 dly cells
7553 00:56:18.464492 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7554 00:56:18.464569 ==
7555 00:56:18.467996 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 00:56:18.470893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 00:56:18.470971 ==
7558 00:56:18.477423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 00:56:18.480896 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 00:56:18.484262 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 00:56:18.490691 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 00:56:18.500286 [CA 0] Center 44 (14~74) winsize 61
7563 00:56:18.503688 [CA 1] Center 43 (13~74) winsize 62
7564 00:56:18.507015 [CA 2] Center 39 (10~68) winsize 59
7565 00:56:18.510824 [CA 3] Center 38 (9~68) winsize 60
7566 00:56:18.514080 [CA 4] Center 36 (7~66) winsize 60
7567 00:56:18.517137 [CA 5] Center 36 (7~66) winsize 60
7568 00:56:18.517214
7569 00:56:18.520614 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7570 00:56:18.520726
7571 00:56:18.523556 [CATrainingPosCal] consider 1 rank data
7572 00:56:18.527195 u2DelayCellTimex100 = 258/100 ps
7573 00:56:18.530716 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7574 00:56:18.537306 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7575 00:56:18.540746 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7576 00:56:18.543671 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7577 00:56:18.547294 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7578 00:56:18.550348 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7579 00:56:18.550424
7580 00:56:18.553981 CA PerBit enable=1, Macro0, CA PI delay=36
7581 00:56:18.554119
7582 00:56:18.556978 [CBTSetCACLKResult] CA Dly = 36
7583 00:56:18.560587 CS Dly: 11 (0~42)
7584 00:56:18.563700 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 00:56:18.566764 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 00:56:18.566856 ==
7587 00:56:18.570272 Dram Type= 6, Freq= 0, CH_0, rank 1
7588 00:56:18.576856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 00:56:18.576937 ==
7590 00:56:18.580106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7591 00:56:18.583405 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7592 00:56:18.590184 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7593 00:56:18.596593 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7594 00:56:18.603991 [CA 0] Center 43 (13~74) winsize 62
7595 00:56:18.607640 [CA 1] Center 43 (13~74) winsize 62
7596 00:56:18.611010 [CA 2] Center 39 (10~68) winsize 59
7597 00:56:18.613894 [CA 3] Center 39 (10~68) winsize 59
7598 00:56:18.617533 [CA 4] Center 36 (6~66) winsize 61
7599 00:56:18.620639 [CA 5] Center 36 (6~66) winsize 61
7600 00:56:18.620723
7601 00:56:18.624005 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7602 00:56:18.624083
7603 00:56:18.630435 [CATrainingPosCal] consider 2 rank data
7604 00:56:18.630515 u2DelayCellTimex100 = 258/100 ps
7605 00:56:18.637593 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7606 00:56:18.640500 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7607 00:56:18.643966 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7608 00:56:18.647033 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7609 00:56:18.650646 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7610 00:56:18.653671 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7611 00:56:18.653750
7612 00:56:18.657408 CA PerBit enable=1, Macro0, CA PI delay=36
7613 00:56:18.657486
7614 00:56:18.660245 [CBTSetCACLKResult] CA Dly = 36
7615 00:56:18.663921 CS Dly: 11 (0~43)
7616 00:56:18.666942 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7617 00:56:18.670515 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7618 00:56:18.670592
7619 00:56:18.673622 ----->DramcWriteLeveling(PI) begin...
7620 00:56:18.673702 ==
7621 00:56:18.677048 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 00:56:18.683707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 00:56:18.683785 ==
7624 00:56:18.687103 Write leveling (Byte 0): 35 => 35
7625 00:56:18.690496 Write leveling (Byte 1): 28 => 28
7626 00:56:18.690574 DramcWriteLeveling(PI) end<-----
7627 00:56:18.693672
7628 00:56:18.693765 ==
7629 00:56:18.697330 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 00:56:18.700226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 00:56:18.700335 ==
7632 00:56:18.703742 [Gating] SW mode calibration
7633 00:56:18.710410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7634 00:56:18.713612 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7635 00:56:18.720148 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 00:56:18.723661 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 00:56:18.726682 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 00:56:18.733230 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 00:56:18.736531 1 4 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
7640 00:56:18.739958 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7641 00:56:18.746662 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7642 00:56:18.750202 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7643 00:56:18.753146 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 00:56:18.759864 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 00:56:18.762925 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 00:56:18.766531 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7647 00:56:18.773123 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
7648 00:56:18.776148 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7649 00:56:18.779709 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7650 00:56:18.786147 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 00:56:18.789678 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 00:56:18.793344 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 00:56:18.800173 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 00:56:18.802977 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 00:56:18.806357 1 6 16 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7656 00:56:18.812979 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (1 1) (0 0)
7657 00:56:18.816063 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7658 00:56:18.819678 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 00:56:18.826392 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 00:56:18.829377 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 00:56:18.833150 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 00:56:18.839510 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 00:56:18.842899 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7664 00:56:18.846139 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7665 00:56:18.852754 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7666 00:56:18.855921 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 00:56:18.859316 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 00:56:18.862788 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 00:56:18.869554 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 00:56:18.872495 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 00:56:18.876039 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 00:56:18.882739 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 00:56:18.886218 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 00:56:18.889071 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 00:56:18.896301 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 00:56:18.899295 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 00:56:18.902422 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 00:56:18.909436 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 00:56:18.912773 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7680 00:56:18.915843 Total UI for P1: 0, mck2ui 16
7681 00:56:18.918893 best dqsien dly found for B0: ( 1, 9, 14)
7682 00:56:18.922492 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7683 00:56:18.929150 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7684 00:56:18.932086 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7685 00:56:18.935403 Total UI for P1: 0, mck2ui 16
7686 00:56:18.939112 best dqsien dly found for B1: ( 1, 9, 24)
7687 00:56:18.942292 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7688 00:56:18.945527 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7689 00:56:18.945600
7690 00:56:18.949093 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7691 00:56:18.955317 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7692 00:56:18.955390 [Gating] SW calibration Done
7693 00:56:18.955487 ==
7694 00:56:18.958708 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 00:56:18.965647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 00:56:18.965726 ==
7697 00:56:18.965786 RX Vref Scan: 0
7698 00:56:18.965842
7699 00:56:18.968914 RX Vref 0 -> 0, step: 1
7700 00:56:18.968991
7701 00:56:18.971993 RX Delay 0 -> 252, step: 8
7702 00:56:18.975110 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7703 00:56:18.978506 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7704 00:56:18.981910 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7705 00:56:18.985406 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7706 00:56:18.991796 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7707 00:56:18.995322 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7708 00:56:18.998390 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7709 00:56:19.002016 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7710 00:56:19.005045 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7711 00:56:19.011668 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7712 00:56:19.015276 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7713 00:56:19.018754 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7714 00:56:19.021669 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7715 00:56:19.025535 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7716 00:56:19.031676 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7717 00:56:19.035230 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7718 00:56:19.035322 ==
7719 00:56:19.038765 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 00:56:19.041670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 00:56:19.041746 ==
7722 00:56:19.045091 DQS Delay:
7723 00:56:19.045167 DQS0 = 0, DQS1 = 0
7724 00:56:19.045226 DQM Delay:
7725 00:56:19.048489 DQM0 = 128, DQM1 = 124
7726 00:56:19.048565 DQ Delay:
7727 00:56:19.051955 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7728 00:56:19.055105 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7729 00:56:19.061578 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7730 00:56:19.064969 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7731 00:56:19.065072
7732 00:56:19.065177
7733 00:56:19.065237 ==
7734 00:56:19.068563 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 00:56:19.071462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 00:56:19.071570 ==
7737 00:56:19.071681
7738 00:56:19.071783
7739 00:56:19.075088 TX Vref Scan disable
7740 00:56:19.078595 == TX Byte 0 ==
7741 00:56:19.081721 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7742 00:56:19.084691 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7743 00:56:19.088333 == TX Byte 1 ==
7744 00:56:19.091480 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7745 00:56:19.094850 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7746 00:56:19.094953 ==
7747 00:56:19.098519 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 00:56:19.101421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 00:56:19.104781 ==
7750 00:56:19.116532
7751 00:56:19.119605 TX Vref early break, caculate TX vref
7752 00:56:19.123332 TX Vref=16, minBit 5, minWin=21, winSum=357
7753 00:56:19.126319 TX Vref=18, minBit 8, minWin=22, winSum=368
7754 00:56:19.129909 TX Vref=20, minBit 4, minWin=23, winSum=379
7755 00:56:19.132873 TX Vref=22, minBit 4, minWin=23, winSum=388
7756 00:56:19.136263 TX Vref=24, minBit 4, minWin=24, winSum=395
7757 00:56:19.142661 TX Vref=26, minBit 8, minWin=24, winSum=400
7758 00:56:19.146034 TX Vref=28, minBit 4, minWin=24, winSum=405
7759 00:56:19.149707 TX Vref=30, minBit 4, minWin=24, winSum=394
7760 00:56:19.152633 TX Vref=32, minBit 8, minWin=23, winSum=390
7761 00:56:19.156061 TX Vref=34, minBit 8, minWin=22, winSum=383
7762 00:56:19.162966 [TxChooseVref] Worse bit 4, Min win 24, Win sum 405, Final Vref 28
7763 00:56:19.163036
7764 00:56:19.165917 Final TX Range 0 Vref 28
7765 00:56:19.165988
7766 00:56:19.166046 ==
7767 00:56:19.169827 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 00:56:19.172895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 00:56:19.172974 ==
7770 00:56:19.173034
7771 00:56:19.173090
7772 00:56:19.176542 TX Vref Scan disable
7773 00:56:19.182871 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7774 00:56:19.182949 == TX Byte 0 ==
7775 00:56:19.186462 u2DelayCellOfst[0]=15 cells (4 PI)
7776 00:56:19.189359 u2DelayCellOfst[1]=18 cells (5 PI)
7777 00:56:19.192964 u2DelayCellOfst[2]=11 cells (3 PI)
7778 00:56:19.195992 u2DelayCellOfst[3]=15 cells (4 PI)
7779 00:56:19.199621 u2DelayCellOfst[4]=11 cells (3 PI)
7780 00:56:19.202617 u2DelayCellOfst[5]=0 cells (0 PI)
7781 00:56:19.206191 u2DelayCellOfst[6]=22 cells (6 PI)
7782 00:56:19.209287 u2DelayCellOfst[7]=22 cells (6 PI)
7783 00:56:19.212675 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7784 00:56:19.216043 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7785 00:56:19.219331 == TX Byte 1 ==
7786 00:56:19.222767 u2DelayCellOfst[8]=0 cells (0 PI)
7787 00:56:19.222845 u2DelayCellOfst[9]=7 cells (2 PI)
7788 00:56:19.225749 u2DelayCellOfst[10]=11 cells (3 PI)
7789 00:56:19.229201 u2DelayCellOfst[11]=7 cells (2 PI)
7790 00:56:19.232321 u2DelayCellOfst[12]=15 cells (4 PI)
7791 00:56:19.236237 u2DelayCellOfst[13]=15 cells (4 PI)
7792 00:56:19.239241 u2DelayCellOfst[14]=18 cells (5 PI)
7793 00:56:19.242690 u2DelayCellOfst[15]=15 cells (4 PI)
7794 00:56:19.245580 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7795 00:56:19.252616 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7796 00:56:19.252726 DramC Write-DBI on
7797 00:56:19.252786 ==
7798 00:56:19.255658 Dram Type= 6, Freq= 0, CH_0, rank 0
7799 00:56:19.262075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7800 00:56:19.262195 ==
7801 00:56:19.262254
7802 00:56:19.262307
7803 00:56:19.262359 TX Vref Scan disable
7804 00:56:19.266346 == TX Byte 0 ==
7805 00:56:19.269659 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7806 00:56:19.272877 == TX Byte 1 ==
7807 00:56:19.275906 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7808 00:56:19.279362 DramC Write-DBI off
7809 00:56:19.279437
7810 00:56:19.279496 [DATLAT]
7811 00:56:19.279551 Freq=1600, CH0 RK0
7812 00:56:19.279604
7813 00:56:19.282687 DATLAT Default: 0xf
7814 00:56:19.282762 0, 0xFFFF, sum = 0
7815 00:56:19.286185 1, 0xFFFF, sum = 0
7816 00:56:19.289740 2, 0xFFFF, sum = 0
7817 00:56:19.289816 3, 0xFFFF, sum = 0
7818 00:56:19.292697 4, 0xFFFF, sum = 0
7819 00:56:19.292774 5, 0xFFFF, sum = 0
7820 00:56:19.296263 6, 0xFFFF, sum = 0
7821 00:56:19.296341 7, 0xFFFF, sum = 0
7822 00:56:19.299258 8, 0xFFFF, sum = 0
7823 00:56:19.299335 9, 0xFFFF, sum = 0
7824 00:56:19.302899 10, 0xFFFF, sum = 0
7825 00:56:19.302975 11, 0xFFFF, sum = 0
7826 00:56:19.305981 12, 0xFFFF, sum = 0
7827 00:56:19.306108 13, 0xCFFF, sum = 0
7828 00:56:19.308946 14, 0x0, sum = 1
7829 00:56:19.309023 15, 0x0, sum = 2
7830 00:56:19.312594 16, 0x0, sum = 3
7831 00:56:19.312707 17, 0x0, sum = 4
7832 00:56:19.315574 best_step = 15
7833 00:56:19.315650
7834 00:56:19.315708 ==
7835 00:56:19.319316 Dram Type= 6, Freq= 0, CH_0, rank 0
7836 00:56:19.322401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7837 00:56:19.322476 ==
7838 00:56:19.326034 RX Vref Scan: 1
7839 00:56:19.326125
7840 00:56:19.326200 Set Vref Range= 24 -> 127
7841 00:56:19.326293
7842 00:56:19.328961 RX Vref 24 -> 127, step: 1
7843 00:56:19.329035
7844 00:56:19.332480 RX Delay 11 -> 252, step: 4
7845 00:56:19.332560
7846 00:56:19.335551 Set Vref, RX VrefLevel [Byte0]: 24
7847 00:56:19.339340 [Byte1]: 24
7848 00:56:19.339415
7849 00:56:19.342420 Set Vref, RX VrefLevel [Byte0]: 25
7850 00:56:19.345380 [Byte1]: 25
7851 00:56:19.348975
7852 00:56:19.349050 Set Vref, RX VrefLevel [Byte0]: 26
7853 00:56:19.351979 [Byte1]: 26
7854 00:56:19.356633
7855 00:56:19.356727 Set Vref, RX VrefLevel [Byte0]: 27
7856 00:56:19.360143 [Byte1]: 27
7857 00:56:19.364417
7858 00:56:19.364492 Set Vref, RX VrefLevel [Byte0]: 28
7859 00:56:19.367232 [Byte1]: 28
7860 00:56:19.371561
7861 00:56:19.371637 Set Vref, RX VrefLevel [Byte0]: 29
7862 00:56:19.375111 [Byte1]: 29
7863 00:56:19.379324
7864 00:56:19.379399 Set Vref, RX VrefLevel [Byte0]: 30
7865 00:56:19.382774 [Byte1]: 30
7866 00:56:19.387167
7867 00:56:19.387242 Set Vref, RX VrefLevel [Byte0]: 31
7868 00:56:19.390187 [Byte1]: 31
7869 00:56:19.394665
7870 00:56:19.394739 Set Vref, RX VrefLevel [Byte0]: 32
7871 00:56:19.398092 [Byte1]: 32
7872 00:56:19.402058
7873 00:56:19.402133 Set Vref, RX VrefLevel [Byte0]: 33
7874 00:56:19.405743 [Byte1]: 33
7875 00:56:19.409935
7876 00:56:19.410012 Set Vref, RX VrefLevel [Byte0]: 34
7877 00:56:19.412987 [Byte1]: 34
7878 00:56:19.417143
7879 00:56:19.417220 Set Vref, RX VrefLevel [Byte0]: 35
7880 00:56:19.420799 [Byte1]: 35
7881 00:56:19.425031
7882 00:56:19.425106 Set Vref, RX VrefLevel [Byte0]: 36
7883 00:56:19.428064 [Byte1]: 36
7884 00:56:19.432862
7885 00:56:19.432938 Set Vref, RX VrefLevel [Byte0]: 37
7886 00:56:19.435869 [Byte1]: 37
7887 00:56:19.440008
7888 00:56:19.440084 Set Vref, RX VrefLevel [Byte0]: 38
7889 00:56:19.443656 [Byte1]: 38
7890 00:56:19.447872
7891 00:56:19.447966 Set Vref, RX VrefLevel [Byte0]: 39
7892 00:56:19.451242 [Byte1]: 39
7893 00:56:19.455631
7894 00:56:19.455707 Set Vref, RX VrefLevel [Byte0]: 40
7895 00:56:19.458920 [Byte1]: 40
7896 00:56:19.463110
7897 00:56:19.463186 Set Vref, RX VrefLevel [Byte0]: 41
7898 00:56:19.466437 [Byte1]: 41
7899 00:56:19.470665
7900 00:56:19.470740 Set Vref, RX VrefLevel [Byte0]: 42
7901 00:56:19.474151 [Byte1]: 42
7902 00:56:19.478712
7903 00:56:19.478788 Set Vref, RX VrefLevel [Byte0]: 43
7904 00:56:19.481905 [Byte1]: 43
7905 00:56:19.485872
7906 00:56:19.485948 Set Vref, RX VrefLevel [Byte0]: 44
7907 00:56:19.489538 [Byte1]: 44
7908 00:56:19.493692
7909 00:56:19.496677 Set Vref, RX VrefLevel [Byte0]: 45
7910 00:56:19.496753 [Byte1]: 45
7911 00:56:19.501065
7912 00:56:19.501139 Set Vref, RX VrefLevel [Byte0]: 46
7913 00:56:19.504689 [Byte1]: 46
7914 00:56:19.508562
7915 00:56:19.508637 Set Vref, RX VrefLevel [Byte0]: 47
7916 00:56:19.511781 [Byte1]: 47
7917 00:56:19.516279
7918 00:56:19.516355 Set Vref, RX VrefLevel [Byte0]: 48
7919 00:56:19.519894 [Byte1]: 48
7920 00:56:19.523953
7921 00:56:19.524028 Set Vref, RX VrefLevel [Byte0]: 49
7922 00:56:19.527578 [Byte1]: 49
7923 00:56:19.531858
7924 00:56:19.531933 Set Vref, RX VrefLevel [Byte0]: 50
7925 00:56:19.534752 [Byte1]: 50
7926 00:56:19.539298
7927 00:56:19.539373 Set Vref, RX VrefLevel [Byte0]: 51
7928 00:56:19.542316 [Byte1]: 51
7929 00:56:19.547127
7930 00:56:19.547219 Set Vref, RX VrefLevel [Byte0]: 52
7931 00:56:19.550132 [Byte1]: 52
7932 00:56:19.554407
7933 00:56:19.554484 Set Vref, RX VrefLevel [Byte0]: 53
7934 00:56:19.557744 [Byte1]: 53
7935 00:56:19.561813
7936 00:56:19.561890 Set Vref, RX VrefLevel [Byte0]: 54
7937 00:56:19.565710 [Byte1]: 54
7938 00:56:19.569694
7939 00:56:19.569769 Set Vref, RX VrefLevel [Byte0]: 55
7940 00:56:19.573039 [Byte1]: 55
7941 00:56:19.577101
7942 00:56:19.577177 Set Vref, RX VrefLevel [Byte0]: 56
7943 00:56:19.580267 [Byte1]: 56
7944 00:56:19.585022
7945 00:56:19.585098 Set Vref, RX VrefLevel [Byte0]: 57
7946 00:56:19.588596 [Byte1]: 57
7947 00:56:19.592603
7948 00:56:19.592718 Set Vref, RX VrefLevel [Byte0]: 58
7949 00:56:19.595892 [Byte1]: 58
7950 00:56:19.600318
7951 00:56:19.600392 Set Vref, RX VrefLevel [Byte0]: 59
7952 00:56:19.603317 [Byte1]: 59
7953 00:56:19.607597
7954 00:56:19.607673 Set Vref, RX VrefLevel [Byte0]: 60
7955 00:56:19.611166 [Byte1]: 60
7956 00:56:19.615175
7957 00:56:19.615250 Set Vref, RX VrefLevel [Byte0]: 61
7958 00:56:19.618544 [Byte1]: 61
7959 00:56:19.622716
7960 00:56:19.622791 Set Vref, RX VrefLevel [Byte0]: 62
7961 00:56:19.626346 [Byte1]: 62
7962 00:56:19.630470
7963 00:56:19.630545 Set Vref, RX VrefLevel [Byte0]: 63
7964 00:56:19.634045 [Byte1]: 63
7965 00:56:19.638214
7966 00:56:19.638289 Set Vref, RX VrefLevel [Byte0]: 64
7967 00:56:19.641182 [Byte1]: 64
7968 00:56:19.645901
7969 00:56:19.645976 Set Vref, RX VrefLevel [Byte0]: 65
7970 00:56:19.648888 [Byte1]: 65
7971 00:56:19.653129
7972 00:56:19.653204 Set Vref, RX VrefLevel [Byte0]: 66
7973 00:56:19.656690 [Byte1]: 66
7974 00:56:19.661298
7975 00:56:19.661373 Set Vref, RX VrefLevel [Byte0]: 67
7976 00:56:19.664261 [Byte1]: 67
7977 00:56:19.668473
7978 00:56:19.668572 Set Vref, RX VrefLevel [Byte0]: 68
7979 00:56:19.671852 [Byte1]: 68
7980 00:56:19.676426
7981 00:56:19.676501 Set Vref, RX VrefLevel [Byte0]: 69
7982 00:56:19.679214 [Byte1]: 69
7983 00:56:19.683843
7984 00:56:19.683919 Set Vref, RX VrefLevel [Byte0]: 70
7985 00:56:19.687161 [Byte1]: 70
7986 00:56:19.691245
7987 00:56:19.691320 Set Vref, RX VrefLevel [Byte0]: 71
7988 00:56:19.694904 [Byte1]: 71
7989 00:56:19.698998
7990 00:56:19.699073 Set Vref, RX VrefLevel [Byte0]: 72
7991 00:56:19.702494 [Byte1]: 72
7992 00:56:19.706587
7993 00:56:19.706662 Set Vref, RX VrefLevel [Byte0]: 73
7994 00:56:19.710070 [Byte1]: 73
7995 00:56:19.714133
7996 00:56:19.714208 Set Vref, RX VrefLevel [Byte0]: 74
7997 00:56:19.717658 [Byte1]: 74
7998 00:56:19.721750
7999 00:56:19.721841 Set Vref, RX VrefLevel [Byte0]: 75
8000 00:56:19.725278 [Byte1]: 75
8001 00:56:19.729760
8002 00:56:19.729844 Set Vref, RX VrefLevel [Byte0]: 76
8003 00:56:19.732565 [Byte1]: 76
8004 00:56:19.737073
8005 00:56:19.737167 Set Vref, RX VrefLevel [Byte0]: 77
8006 00:56:19.740413 [Byte1]: 77
8007 00:56:19.744845
8008 00:56:19.744917 Final RX Vref Byte 0 = 63 to rank0
8009 00:56:19.747832 Final RX Vref Byte 1 = 59 to rank0
8010 00:56:19.751456 Final RX Vref Byte 0 = 63 to rank1
8011 00:56:19.754456 Final RX Vref Byte 1 = 59 to rank1==
8012 00:56:19.758033 Dram Type= 6, Freq= 0, CH_0, rank 0
8013 00:56:19.764584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 00:56:19.764686 ==
8015 00:56:19.764747 DQS Delay:
8016 00:56:19.764803 DQS0 = 0, DQS1 = 0
8017 00:56:19.768263 DQM Delay:
8018 00:56:19.768339 DQM0 = 126, DQM1 = 119
8019 00:56:19.771265 DQ Delay:
8020 00:56:19.774863 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8021 00:56:19.778118 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8022 00:56:19.780890 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8023 00:56:19.784856 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8024 00:56:19.784947
8025 00:56:19.785007
8026 00:56:19.785062
8027 00:56:19.787860 [DramC_TX_OE_Calibration] TA2
8028 00:56:19.791331 Original DQ_B0 (3 6) =30, OEN = 27
8029 00:56:19.794687 Original DQ_B1 (3 6) =30, OEN = 27
8030 00:56:19.797656 24, 0x0, End_B0=24 End_B1=24
8031 00:56:19.797735 25, 0x0, End_B0=25 End_B1=25
8032 00:56:19.801273 26, 0x0, End_B0=26 End_B1=26
8033 00:56:19.804214 27, 0x0, End_B0=27 End_B1=27
8034 00:56:19.807858 28, 0x0, End_B0=28 End_B1=28
8035 00:56:19.811382 29, 0x0, End_B0=29 End_B1=29
8036 00:56:19.811460 30, 0x0, End_B0=30 End_B1=30
8037 00:56:19.814422 31, 0x4141, End_B0=30 End_B1=30
8038 00:56:19.817454 Byte0 end_step=30 best_step=27
8039 00:56:19.821214 Byte1 end_step=30 best_step=27
8040 00:56:19.824031 Byte0 TX OE(2T, 0.5T) = (3, 3)
8041 00:56:19.827590 Byte1 TX OE(2T, 0.5T) = (3, 3)
8042 00:56:19.827665
8043 00:56:19.827724
8044 00:56:19.834028 [DQSOSCAuto] RK0, (LSB)MR18= 0x1817, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
8045 00:56:19.837725 CH0 RK0: MR19=303, MR18=1817
8046 00:56:19.844264 CH0_RK0: MR19=0x303, MR18=0x1817, DQSOSC=397, MR23=63, INC=23, DEC=15
8047 00:56:19.844342
8048 00:56:19.847562 ----->DramcWriteLeveling(PI) begin...
8049 00:56:19.847639 ==
8050 00:56:19.850755 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 00:56:19.853913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 00:56:19.853990 ==
8053 00:56:19.857363 Write leveling (Byte 0): 34 => 34
8054 00:56:19.860859 Write leveling (Byte 1): 28 => 28
8055 00:56:19.863834 DramcWriteLeveling(PI) end<-----
8056 00:56:19.863907
8057 00:56:19.863992 ==
8058 00:56:19.867332 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 00:56:19.870830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 00:56:19.870909 ==
8061 00:56:19.873859 [Gating] SW mode calibration
8062 00:56:19.880920 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8063 00:56:19.887053 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8064 00:56:19.890534 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 00:56:19.896945 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 00:56:19.900358 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 00:56:19.903960 1 4 12 | B1->B0 | 2323 302f | 0 1 | (0 0) (1 1)
8068 00:56:19.910470 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8069 00:56:19.913935 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 00:56:19.916884 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 00:56:19.920481 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 00:56:19.926852 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 00:56:19.930542 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 00:56:19.933726 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8075 00:56:19.940041 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
8076 00:56:19.943574 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8077 00:56:19.947241 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8078 00:56:19.953885 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 00:56:19.956775 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 00:56:19.960146 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 00:56:19.966904 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 00:56:19.970298 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8083 00:56:19.973506 1 6 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
8084 00:56:19.980331 1 6 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8085 00:56:19.983443 1 6 20 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
8086 00:56:19.986390 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 00:56:19.993136 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 00:56:19.996892 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 00:56:19.999779 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 00:56:20.006901 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8091 00:56:20.009742 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8092 00:56:20.013297 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 00:56:20.020187 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 00:56:20.023152 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 00:56:20.026785 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 00:56:20.032950 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 00:56:20.036483 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 00:56:20.040038 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 00:56:20.046441 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 00:56:20.049830 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 00:56:20.053240 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 00:56:20.059967 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 00:56:20.063020 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 00:56:20.066142 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 00:56:20.073330 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 00:56:20.076006 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 00:56:20.079579 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8108 00:56:20.082734 Total UI for P1: 0, mck2ui 16
8109 00:56:20.086225 best dqsien dly found for B0: ( 1, 9, 10)
8110 00:56:20.089340 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8111 00:56:20.096121 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8112 00:56:20.099184 Total UI for P1: 0, mck2ui 16
8113 00:56:20.102599 best dqsien dly found for B1: ( 1, 9, 16)
8114 00:56:20.105885 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8115 00:56:20.109170 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8116 00:56:20.109246
8117 00:56:20.112560 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8118 00:56:20.116048 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8119 00:56:20.119492 [Gating] SW calibration Done
8120 00:56:20.119585 ==
8121 00:56:20.122552 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 00:56:20.126114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 00:56:20.126183 ==
8124 00:56:20.129061 RX Vref Scan: 0
8125 00:56:20.129143
8126 00:56:20.132720 RX Vref 0 -> 0, step: 1
8127 00:56:20.132785
8128 00:56:20.132839 RX Delay 0 -> 252, step: 8
8129 00:56:20.139340 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8130 00:56:20.142281 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8131 00:56:20.145917 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8132 00:56:20.148936 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8133 00:56:20.152575 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8134 00:56:20.158987 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8135 00:56:20.162324 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8136 00:56:20.165522 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8137 00:56:20.169006 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8138 00:56:20.172555 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8139 00:56:20.179056 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8140 00:56:20.182091 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8141 00:56:20.185665 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8142 00:56:20.189026 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8143 00:56:20.192222 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8144 00:56:20.198677 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8145 00:56:20.198753 ==
8146 00:56:20.202136 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 00:56:20.205420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 00:56:20.205496 ==
8149 00:56:20.205555 DQS Delay:
8150 00:56:20.208916 DQS0 = 0, DQS1 = 0
8151 00:56:20.208994 DQM Delay:
8152 00:56:20.212075 DQM0 = 127, DQM1 = 120
8153 00:56:20.212150 DQ Delay:
8154 00:56:20.215358 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8155 00:56:20.218546 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8156 00:56:20.222187 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
8157 00:56:20.225537 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8158 00:56:20.229019
8159 00:56:20.229096
8160 00:56:20.229155 ==
8161 00:56:20.232137 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 00:56:20.235255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 00:56:20.235332 ==
8164 00:56:20.235391
8165 00:56:20.235445
8166 00:56:20.238960 TX Vref Scan disable
8167 00:56:20.239035 == TX Byte 0 ==
8168 00:56:20.245557 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8169 00:56:20.248528 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8170 00:56:20.248604 == TX Byte 1 ==
8171 00:56:20.255738 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8172 00:56:20.258731 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8173 00:56:20.258807 ==
8174 00:56:20.262325 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 00:56:20.265309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 00:56:20.265386 ==
8177 00:56:20.279654
8178 00:56:20.282678 TX Vref early break, caculate TX vref
8179 00:56:20.285823 TX Vref=16, minBit 0, minWin=22, winSum=366
8180 00:56:20.289150 TX Vref=18, minBit 1, minWin=22, winSum=372
8181 00:56:20.292623 TX Vref=20, minBit 8, minWin=22, winSum=382
8182 00:56:20.295589 TX Vref=22, minBit 0, minWin=24, winSum=395
8183 00:56:20.299218 TX Vref=24, minBit 0, minWin=24, winSum=402
8184 00:56:20.305915 TX Vref=26, minBit 0, minWin=25, winSum=408
8185 00:56:20.308935 TX Vref=28, minBit 3, minWin=24, winSum=411
8186 00:56:20.312268 TX Vref=30, minBit 8, minWin=23, winSum=404
8187 00:56:20.316053 TX Vref=32, minBit 8, minWin=24, winSum=397
8188 00:56:20.319070 TX Vref=34, minBit 8, minWin=22, winSum=389
8189 00:56:20.325736 [TxChooseVref] Worse bit 0, Min win 25, Win sum 408, Final Vref 26
8190 00:56:20.325814
8191 00:56:20.329219 Final TX Range 0 Vref 26
8192 00:56:20.329295
8193 00:56:20.329355 ==
8194 00:56:20.332247 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 00:56:20.335827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 00:56:20.335903 ==
8197 00:56:20.335963
8198 00:56:20.336017
8199 00:56:20.338922 TX Vref Scan disable
8200 00:56:20.345625 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8201 00:56:20.345760 == TX Byte 0 ==
8202 00:56:20.349344 u2DelayCellOfst[0]=15 cells (4 PI)
8203 00:56:20.352284 u2DelayCellOfst[1]=22 cells (6 PI)
8204 00:56:20.355921 u2DelayCellOfst[2]=15 cells (4 PI)
8205 00:56:20.358795 u2DelayCellOfst[3]=15 cells (4 PI)
8206 00:56:20.362402 u2DelayCellOfst[4]=11 cells (3 PI)
8207 00:56:20.365967 u2DelayCellOfst[5]=0 cells (0 PI)
8208 00:56:20.368992 u2DelayCellOfst[6]=22 cells (6 PI)
8209 00:56:20.372027 u2DelayCellOfst[7]=22 cells (6 PI)
8210 00:56:20.375570 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8211 00:56:20.379268 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8212 00:56:20.382222 == TX Byte 1 ==
8213 00:56:20.382298 u2DelayCellOfst[8]=0 cells (0 PI)
8214 00:56:20.385684 u2DelayCellOfst[9]=0 cells (0 PI)
8215 00:56:20.388934 u2DelayCellOfst[10]=7 cells (2 PI)
8216 00:56:20.392302 u2DelayCellOfst[11]=7 cells (2 PI)
8217 00:56:20.395656 u2DelayCellOfst[12]=15 cells (4 PI)
8218 00:56:20.398848 u2DelayCellOfst[13]=11 cells (3 PI)
8219 00:56:20.401972 u2DelayCellOfst[14]=15 cells (4 PI)
8220 00:56:20.405492 u2DelayCellOfst[15]=11 cells (3 PI)
8221 00:56:20.408959 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8222 00:56:20.415516 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8223 00:56:20.415593 DramC Write-DBI on
8224 00:56:20.415652 ==
8225 00:56:20.418572 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 00:56:20.422339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 00:56:20.425141 ==
8228 00:56:20.425245
8229 00:56:20.425332
8230 00:56:20.425414 TX Vref Scan disable
8231 00:56:20.429041 == TX Byte 0 ==
8232 00:56:20.432307 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8233 00:56:20.435568 == TX Byte 1 ==
8234 00:56:20.438747 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8235 00:56:20.442034 DramC Write-DBI off
8236 00:56:20.442110
8237 00:56:20.442170 [DATLAT]
8238 00:56:20.442224 Freq=1600, CH0 RK1
8239 00:56:20.442278
8240 00:56:20.445318 DATLAT Default: 0xf
8241 00:56:20.445394 0, 0xFFFF, sum = 0
8242 00:56:20.448654 1, 0xFFFF, sum = 0
8243 00:56:20.451899 2, 0xFFFF, sum = 0
8244 00:56:20.451977 3, 0xFFFF, sum = 0
8245 00:56:20.455309 4, 0xFFFF, sum = 0
8246 00:56:20.455415 5, 0xFFFF, sum = 0
8247 00:56:20.458944 6, 0xFFFF, sum = 0
8248 00:56:20.459021 7, 0xFFFF, sum = 0
8249 00:56:20.462230 8, 0xFFFF, sum = 0
8250 00:56:20.462322 9, 0xFFFF, sum = 0
8251 00:56:20.465279 10, 0xFFFF, sum = 0
8252 00:56:20.465357 11, 0xFFFF, sum = 0
8253 00:56:20.468777 12, 0xFFFF, sum = 0
8254 00:56:20.468854 13, 0xCFFF, sum = 0
8255 00:56:20.471900 14, 0x0, sum = 1
8256 00:56:20.471976 15, 0x0, sum = 2
8257 00:56:20.475465 16, 0x0, sum = 3
8258 00:56:20.475565 17, 0x0, sum = 4
8259 00:56:20.478473 best_step = 15
8260 00:56:20.478565
8261 00:56:20.478639 ==
8262 00:56:20.481980 Dram Type= 6, Freq= 0, CH_0, rank 1
8263 00:56:20.484953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 00:56:20.485030 ==
8265 00:56:20.488573 RX Vref Scan: 0
8266 00:56:20.488671
8267 00:56:20.488777 RX Vref 0 -> 0, step: 1
8268 00:56:20.488833
8269 00:56:20.491503 RX Delay 3 -> 252, step: 4
8270 00:56:20.494983 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8271 00:56:20.501882 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8272 00:56:20.504957 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8273 00:56:20.508491 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8274 00:56:20.511804 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8275 00:56:20.515119 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8276 00:56:20.521481 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8277 00:56:20.525072 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8278 00:56:20.528010 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8279 00:56:20.531541 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8280 00:56:20.534581 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8281 00:56:20.541550 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8282 00:56:20.544997 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8283 00:56:20.547845 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8284 00:56:20.551046 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8285 00:56:20.558336 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8286 00:56:20.558413 ==
8287 00:56:20.561310 Dram Type= 6, Freq= 0, CH_0, rank 1
8288 00:56:20.564632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8289 00:56:20.564747 ==
8290 00:56:20.564806 DQS Delay:
8291 00:56:20.567898 DQS0 = 0, DQS1 = 0
8292 00:56:20.567973 DQM Delay:
8293 00:56:20.571397 DQM0 = 124, DQM1 = 118
8294 00:56:20.571473 DQ Delay:
8295 00:56:20.574856 DQ0 =124, DQ1 =124, DQ2 =120, DQ3 =122
8296 00:56:20.578140 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8297 00:56:20.581171 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8298 00:56:20.584781 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8299 00:56:20.584856
8300 00:56:20.584914
8301 00:56:20.584968
8302 00:56:20.587781 [DramC_TX_OE_Calibration] TA2
8303 00:56:20.591444 Original DQ_B0 (3 6) =30, OEN = 27
8304 00:56:20.594306 Original DQ_B1 (3 6) =30, OEN = 27
8305 00:56:20.597932 24, 0x0, End_B0=24 End_B1=24
8306 00:56:20.601434 25, 0x0, End_B0=25 End_B1=25
8307 00:56:20.604763 26, 0x0, End_B0=26 End_B1=26
8308 00:56:20.604840 27, 0x0, End_B0=27 End_B1=27
8309 00:56:20.608058 28, 0x0, End_B0=28 End_B1=28
8310 00:56:20.611080 29, 0x0, End_B0=29 End_B1=29
8311 00:56:20.614724 30, 0x0, End_B0=30 End_B1=30
8312 00:56:20.614801 31, 0x4141, End_B0=30 End_B1=30
8313 00:56:20.617786 Byte0 end_step=30 best_step=27
8314 00:56:20.621357 Byte1 end_step=30 best_step=27
8315 00:56:20.624681 Byte0 TX OE(2T, 0.5T) = (3, 3)
8316 00:56:20.627923 Byte1 TX OE(2T, 0.5T) = (3, 3)
8317 00:56:20.627999
8318 00:56:20.628058
8319 00:56:20.634898 [DQSOSCAuto] RK1, (LSB)MR18= 0x2916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
8320 00:56:20.637745 CH0 RK1: MR19=303, MR18=2916
8321 00:56:20.644670 CH0_RK1: MR19=0x303, MR18=0x2916, DQSOSC=389, MR23=63, INC=24, DEC=16
8322 00:56:20.648063 [RxdqsGatingPostProcess] freq 1600
8323 00:56:20.654557 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8324 00:56:20.654648 best DQS0 dly(2T, 0.5T) = (1, 1)
8325 00:56:20.657759 best DQS1 dly(2T, 0.5T) = (1, 1)
8326 00:56:20.661067 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8327 00:56:20.664598 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8328 00:56:20.667711 best DQS0 dly(2T, 0.5T) = (1, 1)
8329 00:56:20.671346 best DQS1 dly(2T, 0.5T) = (1, 1)
8330 00:56:20.674401 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8331 00:56:20.677858 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8332 00:56:20.681030 Pre-setting of DQS Precalculation
8333 00:56:20.684215 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8334 00:56:20.684315 ==
8335 00:56:20.687909 Dram Type= 6, Freq= 0, CH_1, rank 0
8336 00:56:20.694192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8337 00:56:20.694270 ==
8338 00:56:20.697940 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8339 00:56:20.704529 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8340 00:56:20.707461 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8341 00:56:20.714124 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8342 00:56:20.721861 [CA 0] Center 42 (13~71) winsize 59
8343 00:56:20.725448 [CA 1] Center 42 (12~72) winsize 61
8344 00:56:20.728464 [CA 2] Center 37 (9~66) winsize 58
8345 00:56:20.731962 [CA 3] Center 37 (8~66) winsize 59
8346 00:56:20.735475 [CA 4] Center 37 (8~67) winsize 60
8347 00:56:20.738377 [CA 5] Center 36 (7~66) winsize 60
8348 00:56:20.738453
8349 00:56:20.741796 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8350 00:56:20.741872
8351 00:56:20.745155 [CATrainingPosCal] consider 1 rank data
8352 00:56:20.748639 u2DelayCellTimex100 = 258/100 ps
8353 00:56:20.751881 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8354 00:56:20.758275 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8355 00:56:20.761439 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8356 00:56:20.765046 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8357 00:56:20.768341 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8358 00:56:20.771857 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8359 00:56:20.771933
8360 00:56:20.774862 CA PerBit enable=1, Macro0, CA PI delay=36
8361 00:56:20.774940
8362 00:56:20.778480 [CBTSetCACLKResult] CA Dly = 36
8363 00:56:20.781502 CS Dly: 9 (0~40)
8364 00:56:20.785100 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8365 00:56:20.788030 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8366 00:56:20.788105 ==
8367 00:56:20.791539 Dram Type= 6, Freq= 0, CH_1, rank 1
8368 00:56:20.794673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 00:56:20.798029 ==
8370 00:56:20.801563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8371 00:56:20.805149 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8372 00:56:20.811360 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8373 00:56:20.814998 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8374 00:56:20.825162 [CA 0] Center 42 (13~71) winsize 59
8375 00:56:20.828172 [CA 1] Center 42 (12~72) winsize 61
8376 00:56:20.831650 [CA 2] Center 37 (8~67) winsize 60
8377 00:56:20.835263 [CA 3] Center 36 (7~66) winsize 60
8378 00:56:20.838286 [CA 4] Center 38 (8~68) winsize 61
8379 00:56:20.841880 [CA 5] Center 36 (6~67) winsize 62
8380 00:56:20.841955
8381 00:56:20.844899 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8382 00:56:20.844974
8383 00:56:20.848418 [CATrainingPosCal] consider 2 rank data
8384 00:56:20.851453 u2DelayCellTimex100 = 258/100 ps
8385 00:56:20.854935 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8386 00:56:20.861770 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8387 00:56:20.864976 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8388 00:56:20.867998 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8389 00:56:20.871218 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8390 00:56:20.874522 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8391 00:56:20.874631
8392 00:56:20.878439 CA PerBit enable=1, Macro0, CA PI delay=36
8393 00:56:20.878514
8394 00:56:20.881274 [CBTSetCACLKResult] CA Dly = 36
8395 00:56:20.884627 CS Dly: 10 (0~43)
8396 00:56:20.888207 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8397 00:56:20.891047 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8398 00:56:20.891187
8399 00:56:20.894602 ----->DramcWriteLeveling(PI) begin...
8400 00:56:20.894681 ==
8401 00:56:20.898167 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 00:56:20.904543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 00:56:20.904622 ==
8404 00:56:20.907981 Write leveling (Byte 0): 26 => 26
8405 00:56:20.908057 Write leveling (Byte 1): 27 => 27
8406 00:56:20.911526 DramcWriteLeveling(PI) end<-----
8407 00:56:20.911603
8408 00:56:20.911662 ==
8409 00:56:20.914504 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 00:56:20.920943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 00:56:20.921022 ==
8412 00:56:20.924549 [Gating] SW mode calibration
8413 00:56:20.931153 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8414 00:56:20.934558 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8415 00:56:20.941168 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 00:56:20.944540 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 00:56:20.947664 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 00:56:20.954238 1 4 12 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8419 00:56:20.957800 1 4 16 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
8420 00:56:20.960718 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 00:56:20.967374 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 00:56:20.970812 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 00:56:20.974143 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 00:56:20.980711 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 00:56:20.984239 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 00:56:20.987402 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8427 00:56:20.994337 1 5 16 | B1->B0 | 2424 2424 | 0 0 | (0 0) (1 0)
8428 00:56:20.997532 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 00:56:21.000477 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 00:56:21.007453 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 00:56:21.010693 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 00:56:21.014042 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 00:56:21.017247 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 00:56:21.024375 1 6 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8435 00:56:21.027327 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 00:56:21.030895 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 00:56:21.037422 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 00:56:21.040660 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 00:56:21.044339 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 00:56:21.050680 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 00:56:21.053744 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 00:56:21.057338 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8443 00:56:21.063859 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8444 00:56:21.067307 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8445 00:56:21.070341 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 00:56:21.077412 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 00:56:21.080362 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 00:56:21.083908 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 00:56:21.090106 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 00:56:21.093806 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 00:56:21.096669 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 00:56:21.103780 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 00:56:21.107200 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 00:56:21.110470 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 00:56:21.116951 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 00:56:21.120049 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 00:56:21.123788 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 00:56:21.130721 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8459 00:56:21.133451 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8460 00:56:21.136576 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 00:56:21.139726 Total UI for P1: 0, mck2ui 16
8462 00:56:21.143457 best dqsien dly found for B0: ( 1, 9, 14)
8463 00:56:21.146720 Total UI for P1: 0, mck2ui 16
8464 00:56:21.150202 best dqsien dly found for B1: ( 1, 9, 14)
8465 00:56:21.153080 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8466 00:56:21.156603 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8467 00:56:21.156702
8468 00:56:21.163246 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8469 00:56:21.166774 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8470 00:56:21.166851 [Gating] SW calibration Done
8471 00:56:21.169663 ==
8472 00:56:21.173426 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 00:56:21.176505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 00:56:21.176585 ==
8475 00:56:21.176654 RX Vref Scan: 0
8476 00:56:21.176728
8477 00:56:21.180138 RX Vref 0 -> 0, step: 1
8478 00:56:21.180243
8479 00:56:21.183171 RX Delay 0 -> 252, step: 8
8480 00:56:21.186528 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8481 00:56:21.190116 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8482 00:56:21.193120 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8483 00:56:21.199743 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8484 00:56:21.203400 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8485 00:56:21.206902 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8486 00:56:21.209816 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8487 00:56:21.213378 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8488 00:56:21.220060 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8489 00:56:21.223083 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8490 00:56:21.226564 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8491 00:56:21.229804 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8492 00:56:21.233075 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8493 00:56:21.239812 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8494 00:56:21.243422 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8495 00:56:21.246096 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8496 00:56:21.246173 ==
8497 00:56:21.250113 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 00:56:21.252944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 00:56:21.253046 ==
8500 00:56:21.256218 DQS Delay:
8501 00:56:21.256294 DQS0 = 0, DQS1 = 0
8502 00:56:21.259674 DQM Delay:
8503 00:56:21.259749 DQM0 = 131, DQM1 = 125
8504 00:56:21.259809 DQ Delay:
8505 00:56:21.266312 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8506 00:56:21.269369 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =131
8507 00:56:21.272854 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8508 00:56:21.276136 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8509 00:56:21.276229
8510 00:56:21.276288
8511 00:56:21.276343 ==
8512 00:56:21.279741 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 00:56:21.282761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 00:56:21.282837 ==
8515 00:56:21.282896
8516 00:56:21.282951
8517 00:56:21.286325 TX Vref Scan disable
8518 00:56:21.289824 == TX Byte 0 ==
8519 00:56:21.292605 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8520 00:56:21.296346 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8521 00:56:21.299343 == TX Byte 1 ==
8522 00:56:21.302980 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8523 00:56:21.305971 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8524 00:56:21.306046 ==
8525 00:56:21.309564 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 00:56:21.313132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 00:56:21.316069 ==
8528 00:56:21.328605
8529 00:56:21.331589 TX Vref early break, caculate TX vref
8530 00:56:21.335010 TX Vref=16, minBit 1, minWin=22, winSum=362
8531 00:56:21.338346 TX Vref=18, minBit 8, minWin=22, winSum=378
8532 00:56:21.341406 TX Vref=20, minBit 1, minWin=23, winSum=383
8533 00:56:21.345047 TX Vref=22, minBit 0, minWin=24, winSum=394
8534 00:56:21.348127 TX Vref=24, minBit 1, minWin=24, winSum=403
8535 00:56:21.354819 TX Vref=26, minBit 0, minWin=25, winSum=415
8536 00:56:21.358427 TX Vref=28, minBit 8, minWin=25, winSum=417
8537 00:56:21.361384 TX Vref=30, minBit 0, minWin=25, winSum=412
8538 00:56:21.364765 TX Vref=32, minBit 0, minWin=24, winSum=402
8539 00:56:21.368232 TX Vref=34, minBit 0, minWin=23, winSum=396
8540 00:56:21.371331 TX Vref=36, minBit 1, minWin=22, winSum=379
8541 00:56:21.377632 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
8542 00:56:21.377730
8543 00:56:21.381048 Final TX Range 0 Vref 28
8544 00:56:21.381125
8545 00:56:21.381185 ==
8546 00:56:21.384272 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 00:56:21.387909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 00:56:21.388000 ==
8549 00:56:21.390949
8550 00:56:21.391018
8551 00:56:21.391075 TX Vref Scan disable
8552 00:56:21.397912 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8553 00:56:21.398026 == TX Byte 0 ==
8554 00:56:21.401186 u2DelayCellOfst[0]=22 cells (6 PI)
8555 00:56:21.404117 u2DelayCellOfst[1]=15 cells (4 PI)
8556 00:56:21.407682 u2DelayCellOfst[2]=0 cells (0 PI)
8557 00:56:21.411281 u2DelayCellOfst[3]=7 cells (2 PI)
8558 00:56:21.414188 u2DelayCellOfst[4]=11 cells (3 PI)
8559 00:56:21.417700 u2DelayCellOfst[5]=22 cells (6 PI)
8560 00:56:21.420775 u2DelayCellOfst[6]=22 cells (6 PI)
8561 00:56:21.424338 u2DelayCellOfst[7]=7 cells (2 PI)
8562 00:56:21.427472 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8563 00:56:21.431268 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8564 00:56:21.434262 == TX Byte 1 ==
8565 00:56:21.437364 u2DelayCellOfst[8]=0 cells (0 PI)
8566 00:56:21.440853 u2DelayCellOfst[9]=7 cells (2 PI)
8567 00:56:21.444089 u2DelayCellOfst[10]=15 cells (4 PI)
8568 00:56:21.444166 u2DelayCellOfst[11]=11 cells (3 PI)
8569 00:56:21.447690 u2DelayCellOfst[12]=18 cells (5 PI)
8570 00:56:21.450690 u2DelayCellOfst[13]=22 cells (6 PI)
8571 00:56:21.454290 u2DelayCellOfst[14]=22 cells (6 PI)
8572 00:56:21.457912 u2DelayCellOfst[15]=22 cells (6 PI)
8573 00:56:21.464060 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8574 00:56:21.467744 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8575 00:56:21.467820 DramC Write-DBI on
8576 00:56:21.467880 ==
8577 00:56:21.470858 Dram Type= 6, Freq= 0, CH_1, rank 0
8578 00:56:21.477605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8579 00:56:21.477682 ==
8580 00:56:21.477742
8581 00:56:21.477829
8582 00:56:21.477882 TX Vref Scan disable
8583 00:56:21.481626 == TX Byte 0 ==
8584 00:56:21.484746 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8585 00:56:21.488334 == TX Byte 1 ==
8586 00:56:21.491843 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8587 00:56:21.495192 DramC Write-DBI off
8588 00:56:21.495267
8589 00:56:21.495326 [DATLAT]
8590 00:56:21.495381 Freq=1600, CH1 RK0
8591 00:56:21.495435
8592 00:56:21.498184 DATLAT Default: 0xf
8593 00:56:21.498275 0, 0xFFFF, sum = 0
8594 00:56:21.501377 1, 0xFFFF, sum = 0
8595 00:56:21.504918 2, 0xFFFF, sum = 0
8596 00:56:21.504995 3, 0xFFFF, sum = 0
8597 00:56:21.508305 4, 0xFFFF, sum = 0
8598 00:56:21.508383 5, 0xFFFF, sum = 0
8599 00:56:21.511224 6, 0xFFFF, sum = 0
8600 00:56:21.511302 7, 0xFFFF, sum = 0
8601 00:56:21.514458 8, 0xFFFF, sum = 0
8602 00:56:21.514559 9, 0xFFFF, sum = 0
8603 00:56:21.518375 10, 0xFFFF, sum = 0
8604 00:56:21.518452 11, 0xFFFF, sum = 0
8605 00:56:21.521207 12, 0xFFFF, sum = 0
8606 00:56:21.521285 13, 0x8FFF, sum = 0
8607 00:56:21.524708 14, 0x0, sum = 1
8608 00:56:21.524843 15, 0x0, sum = 2
8609 00:56:21.527786 16, 0x0, sum = 3
8610 00:56:21.527863 17, 0x0, sum = 4
8611 00:56:21.531307 best_step = 15
8612 00:56:21.531382
8613 00:56:21.531441 ==
8614 00:56:21.534327 Dram Type= 6, Freq= 0, CH_1, rank 0
8615 00:56:21.537930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8616 00:56:21.538010 ==
8617 00:56:21.540906 RX Vref Scan: 1
8618 00:56:21.540981
8619 00:56:21.541040 Set Vref Range= 24 -> 127
8620 00:56:21.541095
8621 00:56:21.544376 RX Vref 24 -> 127, step: 1
8622 00:56:21.544451
8623 00:56:21.547738 RX Delay 11 -> 252, step: 4
8624 00:56:21.547813
8625 00:56:21.551127 Set Vref, RX VrefLevel [Byte0]: 24
8626 00:56:21.554695 [Byte1]: 24
8627 00:56:21.554770
8628 00:56:21.557707 Set Vref, RX VrefLevel [Byte0]: 25
8629 00:56:21.560782 [Byte1]: 25
8630 00:56:21.564482
8631 00:56:21.564557 Set Vref, RX VrefLevel [Byte0]: 26
8632 00:56:21.567925 [Byte1]: 26
8633 00:56:21.571736
8634 00:56:21.571812 Set Vref, RX VrefLevel [Byte0]: 27
8635 00:56:21.575452 [Byte1]: 27
8636 00:56:21.579600
8637 00:56:21.579676 Set Vref, RX VrefLevel [Byte0]: 28
8638 00:56:21.583239 [Byte1]: 28
8639 00:56:21.587317
8640 00:56:21.587393 Set Vref, RX VrefLevel [Byte0]: 29
8641 00:56:21.590329 [Byte1]: 29
8642 00:56:21.595077
8643 00:56:21.595153 Set Vref, RX VrefLevel [Byte0]: 30
8644 00:56:21.598218 [Byte1]: 30
8645 00:56:21.602426
8646 00:56:21.602522 Set Vref, RX VrefLevel [Byte0]: 31
8647 00:56:21.606059 [Byte1]: 31
8648 00:56:21.610327
8649 00:56:21.610399 Set Vref, RX VrefLevel [Byte0]: 32
8650 00:56:21.613633 [Byte1]: 32
8651 00:56:21.617765
8652 00:56:21.617838 Set Vref, RX VrefLevel [Byte0]: 33
8653 00:56:21.621229 [Byte1]: 33
8654 00:56:21.625246
8655 00:56:21.625316 Set Vref, RX VrefLevel [Byte0]: 34
8656 00:56:21.628511 [Byte1]: 34
8657 00:56:21.633149
8658 00:56:21.633220 Set Vref, RX VrefLevel [Byte0]: 35
8659 00:56:21.635988 [Byte1]: 35
8660 00:56:21.640759
8661 00:56:21.640833 Set Vref, RX VrefLevel [Byte0]: 36
8662 00:56:21.643890 [Byte1]: 36
8663 00:56:21.648107
8664 00:56:21.648189 Set Vref, RX VrefLevel [Byte0]: 37
8665 00:56:21.651305 [Byte1]: 37
8666 00:56:21.655623
8667 00:56:21.655694 Set Vref, RX VrefLevel [Byte0]: 38
8668 00:56:21.658941 [Byte1]: 38
8669 00:56:21.663231
8670 00:56:21.663303 Set Vref, RX VrefLevel [Byte0]: 39
8671 00:56:21.666848 [Byte1]: 39
8672 00:56:21.671079
8673 00:56:21.671157 Set Vref, RX VrefLevel [Byte0]: 40
8674 00:56:21.674019 [Byte1]: 40
8675 00:56:21.678493
8676 00:56:21.678570 Set Vref, RX VrefLevel [Byte0]: 41
8677 00:56:21.682021 [Byte1]: 41
8678 00:56:21.686206
8679 00:56:21.686302 Set Vref, RX VrefLevel [Byte0]: 42
8680 00:56:21.689677 [Byte1]: 42
8681 00:56:21.693931
8682 00:56:21.694010 Set Vref, RX VrefLevel [Byte0]: 43
8683 00:56:21.696869 [Byte1]: 43
8684 00:56:21.701588
8685 00:56:21.701659 Set Vref, RX VrefLevel [Byte0]: 44
8686 00:56:21.704532 [Byte1]: 44
8687 00:56:21.709308
8688 00:56:21.709379 Set Vref, RX VrefLevel [Byte0]: 45
8689 00:56:21.712425 [Byte1]: 45
8690 00:56:21.716616
8691 00:56:21.716737 Set Vref, RX VrefLevel [Byte0]: 46
8692 00:56:21.720161 [Byte1]: 46
8693 00:56:21.724124
8694 00:56:21.724202 Set Vref, RX VrefLevel [Byte0]: 47
8695 00:56:21.727726 [Byte1]: 47
8696 00:56:21.731976
8697 00:56:21.732045 Set Vref, RX VrefLevel [Byte0]: 48
8698 00:56:21.735014 [Byte1]: 48
8699 00:56:21.739579
8700 00:56:21.739659 Set Vref, RX VrefLevel [Byte0]: 49
8701 00:56:21.743040 [Byte1]: 49
8702 00:56:21.746856
8703 00:56:21.746935 Set Vref, RX VrefLevel [Byte0]: 50
8704 00:56:21.750406 [Byte1]: 50
8705 00:56:21.754583
8706 00:56:21.754653 Set Vref, RX VrefLevel [Byte0]: 51
8707 00:56:21.758187 [Byte1]: 51
8708 00:56:21.762108
8709 00:56:21.762179 Set Vref, RX VrefLevel [Byte0]: 52
8710 00:56:21.765365 [Byte1]: 52
8711 00:56:21.769890
8712 00:56:21.769974 Set Vref, RX VrefLevel [Byte0]: 53
8713 00:56:21.773083 [Byte1]: 53
8714 00:56:21.777700
8715 00:56:21.777777 Set Vref, RX VrefLevel [Byte0]: 54
8716 00:56:21.781226 [Byte1]: 54
8717 00:56:21.785072
8718 00:56:21.785143 Set Vref, RX VrefLevel [Byte0]: 55
8719 00:56:21.788563 [Byte1]: 55
8720 00:56:21.792852
8721 00:56:21.792926 Set Vref, RX VrefLevel [Byte0]: 56
8722 00:56:21.796265 [Byte1]: 56
8723 00:56:21.800462
8724 00:56:21.800533 Set Vref, RX VrefLevel [Byte0]: 57
8725 00:56:21.803570 [Byte1]: 57
8726 00:56:21.807869
8727 00:56:21.807938 Set Vref, RX VrefLevel [Byte0]: 58
8728 00:56:21.814326 [Byte1]: 58
8729 00:56:21.814398
8730 00:56:21.817863 Set Vref, RX VrefLevel [Byte0]: 59
8731 00:56:21.820901 [Byte1]: 59
8732 00:56:21.820972
8733 00:56:21.824476 Set Vref, RX VrefLevel [Byte0]: 60
8734 00:56:21.827375 [Byte1]: 60
8735 00:56:21.830776
8736 00:56:21.830846 Set Vref, RX VrefLevel [Byte0]: 61
8737 00:56:21.834425 [Byte1]: 61
8738 00:56:21.838661
8739 00:56:21.838731 Set Vref, RX VrefLevel [Byte0]: 62
8740 00:56:21.841555 [Byte1]: 62
8741 00:56:21.845816
8742 00:56:21.845890 Set Vref, RX VrefLevel [Byte0]: 63
8743 00:56:21.849403 [Byte1]: 63
8744 00:56:21.853417
8745 00:56:21.853497 Set Vref, RX VrefLevel [Byte0]: 64
8746 00:56:21.856764 [Byte1]: 64
8747 00:56:21.861398
8748 00:56:21.861470 Set Vref, RX VrefLevel [Byte0]: 65
8749 00:56:21.864731 [Byte1]: 65
8750 00:56:21.869153
8751 00:56:21.869235 Set Vref, RX VrefLevel [Byte0]: 66
8752 00:56:21.872196 [Byte1]: 66
8753 00:56:21.876539
8754 00:56:21.876622 Set Vref, RX VrefLevel [Byte0]: 67
8755 00:56:21.880137 [Byte1]: 67
8756 00:56:21.884308
8757 00:56:21.884391 Set Vref, RX VrefLevel [Byte0]: 68
8758 00:56:21.887309 [Byte1]: 68
8759 00:56:21.891425
8760 00:56:21.891501 Set Vref, RX VrefLevel [Byte0]: 69
8761 00:56:21.894695 [Byte1]: 69
8762 00:56:21.899478
8763 00:56:21.899558 Set Vref, RX VrefLevel [Byte0]: 70
8764 00:56:21.902778 [Byte1]: 70
8765 00:56:21.906840
8766 00:56:21.906948 Set Vref, RX VrefLevel [Byte0]: 71
8767 00:56:21.910414 [Byte1]: 71
8768 00:56:21.914483
8769 00:56:21.914572 Final RX Vref Byte 0 = 59 to rank0
8770 00:56:21.918029 Final RX Vref Byte 1 = 53 to rank0
8771 00:56:21.921061 Final RX Vref Byte 0 = 59 to rank1
8772 00:56:21.924515 Final RX Vref Byte 1 = 53 to rank1==
8773 00:56:21.927941 Dram Type= 6, Freq= 0, CH_1, rank 0
8774 00:56:21.934536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 00:56:21.934609 ==
8776 00:56:21.934665 DQS Delay:
8777 00:56:21.934725 DQS0 = 0, DQS1 = 0
8778 00:56:21.937644 DQM Delay:
8779 00:56:21.937708 DQM0 = 131, DQM1 = 123
8780 00:56:21.941211 DQ Delay:
8781 00:56:21.944789 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8782 00:56:21.947711 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8783 00:56:21.951366 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8784 00:56:21.954398 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8785 00:56:21.954462
8786 00:56:21.954517
8787 00:56:21.954595
8788 00:56:21.957962 [DramC_TX_OE_Calibration] TA2
8789 00:56:21.960942 Original DQ_B0 (3 6) =30, OEN = 27
8790 00:56:21.964548 Original DQ_B1 (3 6) =30, OEN = 27
8791 00:56:21.967606 24, 0x0, End_B0=24 End_B1=24
8792 00:56:21.967707 25, 0x0, End_B0=25 End_B1=25
8793 00:56:21.970836 26, 0x0, End_B0=26 End_B1=26
8794 00:56:21.974350 27, 0x0, End_B0=27 End_B1=27
8795 00:56:21.977950 28, 0x0, End_B0=28 End_B1=28
8796 00:56:21.978053 29, 0x0, End_B0=29 End_B1=29
8797 00:56:21.980963 30, 0x0, End_B0=30 End_B1=30
8798 00:56:21.984537 31, 0x4141, End_B0=30 End_B1=30
8799 00:56:21.987494 Byte0 end_step=30 best_step=27
8800 00:56:21.990729 Byte1 end_step=30 best_step=27
8801 00:56:21.994344 Byte0 TX OE(2T, 0.5T) = (3, 3)
8802 00:56:21.994437 Byte1 TX OE(2T, 0.5T) = (3, 3)
8803 00:56:21.997378
8804 00:56:21.997443
8805 00:56:22.004266 [DQSOSCAuto] RK0, (LSB)MR18= 0xe12, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
8806 00:56:22.007620 CH1 RK0: MR19=303, MR18=E12
8807 00:56:22.014100 CH1_RK0: MR19=0x303, MR18=0xE12, DQSOSC=400, MR23=63, INC=23, DEC=15
8808 00:56:22.014170
8809 00:56:22.017545 ----->DramcWriteLeveling(PI) begin...
8810 00:56:22.017617 ==
8811 00:56:22.021049 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 00:56:22.024221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 00:56:22.024301 ==
8814 00:56:22.027605 Write leveling (Byte 0): 25 => 25
8815 00:56:22.031080 Write leveling (Byte 1): 28 => 28
8816 00:56:22.034177 DramcWriteLeveling(PI) end<-----
8817 00:56:22.034269
8818 00:56:22.034327 ==
8819 00:56:22.037762 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 00:56:22.040668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 00:56:22.040757 ==
8822 00:56:22.044276 [Gating] SW mode calibration
8823 00:56:22.050605 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8824 00:56:22.057791 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8825 00:56:22.060682 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 00:56:22.064155 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 00:56:22.070925 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
8828 00:56:22.073911 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8829 00:56:22.077399 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 00:56:22.084190 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 00:56:22.087099 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 00:56:22.090680 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 00:56:22.096970 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 00:56:22.100262 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8835 00:56:22.103889 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8836 00:56:22.110538 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8837 00:56:22.114050 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 00:56:22.116965 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 00:56:22.123642 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 00:56:22.126934 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 00:56:22.130195 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 00:56:22.136904 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8843 00:56:22.139920 1 6 8 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8844 00:56:22.143514 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8845 00:56:22.150180 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 00:56:22.153206 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 00:56:22.156711 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 00:56:22.163196 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 00:56:22.166617 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 00:56:22.170176 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 00:56:22.176755 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8852 00:56:22.179886 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8853 00:56:22.183460 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 00:56:22.189714 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 00:56:22.193270 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 00:56:22.196228 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 00:56:22.203117 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 00:56:22.206317 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 00:56:22.209896 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 00:56:22.212888 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 00:56:22.219885 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 00:56:22.222772 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 00:56:22.226312 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 00:56:22.233087 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 00:56:22.236451 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 00:56:22.239766 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 00:56:22.246514 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8868 00:56:22.249911 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8869 00:56:22.253171 Total UI for P1: 0, mck2ui 16
8870 00:56:22.256371 best dqsien dly found for B0: ( 1, 9, 8)
8871 00:56:22.259402 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 00:56:22.262651 Total UI for P1: 0, mck2ui 16
8873 00:56:22.266359 best dqsien dly found for B1: ( 1, 9, 10)
8874 00:56:22.269890 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8875 00:56:22.272773 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8876 00:56:22.272897
8877 00:56:22.279354 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8878 00:56:22.282867 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8879 00:56:22.286305 [Gating] SW calibration Done
8880 00:56:22.286371 ==
8881 00:56:22.289223 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 00:56:22.292798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 00:56:22.292872 ==
8884 00:56:22.292929 RX Vref Scan: 0
8885 00:56:22.292998
8886 00:56:22.296118 RX Vref 0 -> 0, step: 1
8887 00:56:22.296209
8888 00:56:22.299156 RX Delay 0 -> 252, step: 8
8889 00:56:22.302725 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8890 00:56:22.305706 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8891 00:56:22.312542 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8892 00:56:22.315848 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8893 00:56:22.318858 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8894 00:56:22.322583 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8895 00:56:22.325587 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8896 00:56:22.332362 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8897 00:56:22.335378 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8898 00:56:22.339007 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8899 00:56:22.342014 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8900 00:56:22.345321 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8901 00:56:22.352094 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8902 00:56:22.355057 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8903 00:56:22.358637 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8904 00:56:22.362102 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8905 00:56:22.362176 ==
8906 00:56:22.364962 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 00:56:22.371911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 00:56:22.371986 ==
8909 00:56:22.372046 DQS Delay:
8910 00:56:22.375274 DQS0 = 0, DQS1 = 0
8911 00:56:22.375355 DQM Delay:
8912 00:56:22.378477 DQM0 = 131, DQM1 = 129
8913 00:56:22.378557 DQ Delay:
8914 00:56:22.382158 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8915 00:56:22.385176 DQ4 =123, DQ5 =143, DQ6 =143, DQ7 =131
8916 00:56:22.388240 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8917 00:56:22.391737 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8918 00:56:22.391813
8919 00:56:22.391898
8920 00:56:22.391970 ==
8921 00:56:22.395278 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 00:56:22.401577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 00:56:22.401662 ==
8924 00:56:22.401739
8925 00:56:22.401810
8926 00:56:22.401886 TX Vref Scan disable
8927 00:56:22.404719 == TX Byte 0 ==
8928 00:56:22.408440 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8929 00:56:22.411828 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8930 00:56:22.414696 == TX Byte 1 ==
8931 00:56:22.418047 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8932 00:56:22.424717 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8933 00:56:22.424807 ==
8934 00:56:22.428374 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 00:56:22.431337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 00:56:22.431409 ==
8937 00:56:22.444583
8938 00:56:22.448166 TX Vref early break, caculate TX vref
8939 00:56:22.451496 TX Vref=16, minBit 0, minWin=22, winSum=381
8940 00:56:22.454913 TX Vref=18, minBit 0, minWin=23, winSum=388
8941 00:56:22.458369 TX Vref=20, minBit 0, minWin=23, winSum=400
8942 00:56:22.461321 TX Vref=22, minBit 0, minWin=23, winSum=407
8943 00:56:22.464762 TX Vref=24, minBit 0, minWin=25, winSum=414
8944 00:56:22.471308 TX Vref=26, minBit 0, minWin=26, winSum=427
8945 00:56:22.474625 TX Vref=28, minBit 0, minWin=25, winSum=427
8946 00:56:22.478106 TX Vref=30, minBit 5, minWin=25, winSum=419
8947 00:56:22.480888 TX Vref=32, minBit 1, minWin=24, winSum=413
8948 00:56:22.484558 TX Vref=34, minBit 1, minWin=24, winSum=406
8949 00:56:22.487872 TX Vref=36, minBit 1, minWin=22, winSum=391
8950 00:56:22.494358 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
8951 00:56:22.494434
8952 00:56:22.497840 Final TX Range 0 Vref 26
8953 00:56:22.497917
8954 00:56:22.497993 ==
8955 00:56:22.500856 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 00:56:22.504444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 00:56:22.504528 ==
8958 00:56:22.507369
8959 00:56:22.507438
8960 00:56:22.507520 TX Vref Scan disable
8961 00:56:22.514492 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8962 00:56:22.514574 == TX Byte 0 ==
8963 00:56:22.517408 u2DelayCellOfst[0]=18 cells (5 PI)
8964 00:56:22.521129 u2DelayCellOfst[1]=15 cells (4 PI)
8965 00:56:22.524060 u2DelayCellOfst[2]=0 cells (0 PI)
8966 00:56:22.527398 u2DelayCellOfst[3]=7 cells (2 PI)
8967 00:56:22.530587 u2DelayCellOfst[4]=11 cells (3 PI)
8968 00:56:22.534110 u2DelayCellOfst[5]=22 cells (6 PI)
8969 00:56:22.537642 u2DelayCellOfst[6]=18 cells (5 PI)
8970 00:56:22.540651 u2DelayCellOfst[7]=7 cells (2 PI)
8971 00:56:22.544184 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8972 00:56:22.547503 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8973 00:56:22.550928 == TX Byte 1 ==
8974 00:56:22.553860 u2DelayCellOfst[8]=0 cells (0 PI)
8975 00:56:22.557673 u2DelayCellOfst[9]=7 cells (2 PI)
8976 00:56:22.560529 u2DelayCellOfst[10]=15 cells (4 PI)
8977 00:56:22.560620 u2DelayCellOfst[11]=7 cells (2 PI)
8978 00:56:22.564268 u2DelayCellOfst[12]=15 cells (4 PI)
8979 00:56:22.567311 u2DelayCellOfst[13]=18 cells (5 PI)
8980 00:56:22.570728 u2DelayCellOfst[14]=18 cells (5 PI)
8981 00:56:22.574255 u2DelayCellOfst[15]=18 cells (5 PI)
8982 00:56:22.580739 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8983 00:56:22.583703 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8984 00:56:22.583783 DramC Write-DBI on
8985 00:56:22.583867 ==
8986 00:56:22.587331 Dram Type= 6, Freq= 0, CH_1, rank 1
8987 00:56:22.593968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8988 00:56:22.594051 ==
8989 00:56:22.594138
8990 00:56:22.594209
8991 00:56:22.594280 TX Vref Scan disable
8992 00:56:22.597908 == TX Byte 0 ==
8993 00:56:22.601076 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8994 00:56:22.604905 == TX Byte 1 ==
8995 00:56:22.607882 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8996 00:56:22.611451 DramC Write-DBI off
8997 00:56:22.611521
8998 00:56:22.611604 [DATLAT]
8999 00:56:22.611674 Freq=1600, CH1 RK1
9000 00:56:22.611751
9001 00:56:22.614721 DATLAT Default: 0xf
9002 00:56:22.614796 0, 0xFFFF, sum = 0
9003 00:56:22.617795 1, 0xFFFF, sum = 0
9004 00:56:22.621437 2, 0xFFFF, sum = 0
9005 00:56:22.621508 3, 0xFFFF, sum = 0
9006 00:56:22.624463 4, 0xFFFF, sum = 0
9007 00:56:22.624534 5, 0xFFFF, sum = 0
9008 00:56:22.628174 6, 0xFFFF, sum = 0
9009 00:56:22.628244 7, 0xFFFF, sum = 0
9010 00:56:22.631059 8, 0xFFFF, sum = 0
9011 00:56:22.631162 9, 0xFFFF, sum = 0
9012 00:56:22.634554 10, 0xFFFF, sum = 0
9013 00:56:22.634623 11, 0xFFFF, sum = 0
9014 00:56:22.637850 12, 0xFFFF, sum = 0
9015 00:56:22.637920 13, 0x8FFF, sum = 0
9016 00:56:22.641448 14, 0x0, sum = 1
9017 00:56:22.641531 15, 0x0, sum = 2
9018 00:56:22.644417 16, 0x0, sum = 3
9019 00:56:22.644486 17, 0x0, sum = 4
9020 00:56:22.647945 best_step = 15
9021 00:56:22.648015
9022 00:56:22.648087 ==
9023 00:56:22.651376 Dram Type= 6, Freq= 0, CH_1, rank 1
9024 00:56:22.654301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9025 00:56:22.654380 ==
9026 00:56:22.657640 RX Vref Scan: 0
9027 00:56:22.657709
9028 00:56:22.657788 RX Vref 0 -> 0, step: 1
9029 00:56:22.657857
9030 00:56:22.661029 RX Delay 11 -> 252, step: 4
9031 00:56:22.664500 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9032 00:56:22.671170 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9033 00:56:22.674283 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9034 00:56:22.677784 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9035 00:56:22.680724 iDelay=195, Bit 4, Center 124 (71 ~ 178) 108
9036 00:56:22.684263 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9037 00:56:22.690833 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9038 00:56:22.694510 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
9039 00:56:22.697370 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9040 00:56:22.700596 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9041 00:56:22.703988 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9042 00:56:22.710949 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9043 00:56:22.714157 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9044 00:56:22.717698 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9045 00:56:22.720593 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9046 00:56:22.727081 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9047 00:56:22.727165 ==
9048 00:56:22.730741 Dram Type= 6, Freq= 0, CH_1, rank 1
9049 00:56:22.733710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9050 00:56:22.733776 ==
9051 00:56:22.733858 DQS Delay:
9052 00:56:22.737320 DQS0 = 0, DQS1 = 0
9053 00:56:22.737387 DQM Delay:
9054 00:56:22.740192 DQM0 = 130, DQM1 = 125
9055 00:56:22.740278 DQ Delay:
9056 00:56:22.743588 DQ0 =134, DQ1 =130, DQ2 =118, DQ3 =126
9057 00:56:22.746902 DQ4 =124, DQ5 =142, DQ6 =142, DQ7 =126
9058 00:56:22.750414 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9059 00:56:22.753981 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =136
9060 00:56:22.754047
9061 00:56:22.754103
9062 00:56:22.756988
9063 00:56:22.757065 [DramC_TX_OE_Calibration] TA2
9064 00:56:22.760478 Original DQ_B0 (3 6) =30, OEN = 27
9065 00:56:22.764004 Original DQ_B1 (3 6) =30, OEN = 27
9066 00:56:22.766855 24, 0x0, End_B0=24 End_B1=24
9067 00:56:22.770592 25, 0x0, End_B0=25 End_B1=25
9068 00:56:22.770668 26, 0x0, End_B0=26 End_B1=26
9069 00:56:22.773565 27, 0x0, End_B0=27 End_B1=27
9070 00:56:22.777129 28, 0x0, End_B0=28 End_B1=28
9071 00:56:22.780428 29, 0x0, End_B0=29 End_B1=29
9072 00:56:22.783589 30, 0x0, End_B0=30 End_B1=30
9073 00:56:22.783667 31, 0x4141, End_B0=30 End_B1=30
9074 00:56:22.786728 Byte0 end_step=30 best_step=27
9075 00:56:22.790096 Byte1 end_step=30 best_step=27
9076 00:56:22.793702 Byte0 TX OE(2T, 0.5T) = (3, 3)
9077 00:56:22.796741 Byte1 TX OE(2T, 0.5T) = (3, 3)
9078 00:56:22.796816
9079 00:56:22.796894
9080 00:56:22.803297 [DQSOSCAuto] RK1, (LSB)MR18= 0x1320, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
9081 00:56:22.806660 CH1 RK1: MR19=303, MR18=1320
9082 00:56:22.813541 CH1_RK1: MR19=0x303, MR18=0x1320, DQSOSC=393, MR23=63, INC=23, DEC=15
9083 00:56:22.817083 [RxdqsGatingPostProcess] freq 1600
9084 00:56:22.823350 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9085 00:56:22.826668 best DQS0 dly(2T, 0.5T) = (1, 1)
9086 00:56:22.826751 best DQS1 dly(2T, 0.5T) = (1, 1)
9087 00:56:22.830271 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9088 00:56:22.833924 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9089 00:56:22.836880 best DQS0 dly(2T, 0.5T) = (1, 1)
9090 00:56:22.839887 best DQS1 dly(2T, 0.5T) = (1, 1)
9091 00:56:22.843453 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9092 00:56:22.846410 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9093 00:56:22.850032 Pre-setting of DQS Precalculation
9094 00:56:22.853345 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9095 00:56:22.863120 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9096 00:56:22.869829 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9097 00:56:22.869910
9098 00:56:22.869992
9099 00:56:22.873351 [Calibration Summary] 3200 Mbps
9100 00:56:22.873427 CH 0, Rank 0
9101 00:56:22.876773 SW Impedance : PASS
9102 00:56:22.876844 DUTY Scan : NO K
9103 00:56:22.880040 ZQ Calibration : PASS
9104 00:56:22.883562 Jitter Meter : NO K
9105 00:56:22.883645 CBT Training : PASS
9106 00:56:22.886504 Write leveling : PASS
9107 00:56:22.889974 RX DQS gating : PASS
9108 00:56:22.890045 RX DQ/DQS(RDDQC) : PASS
9109 00:56:22.893276 TX DQ/DQS : PASS
9110 00:56:22.896403 RX DATLAT : PASS
9111 00:56:22.896473 RX DQ/DQS(Engine): PASS
9112 00:56:22.899944 TX OE : PASS
9113 00:56:22.900028 All Pass.
9114 00:56:22.900101
9115 00:56:22.903456 CH 0, Rank 1
9116 00:56:22.903534 SW Impedance : PASS
9117 00:56:22.906574 DUTY Scan : NO K
9118 00:56:22.909616 ZQ Calibration : PASS
9119 00:56:22.909683 Jitter Meter : NO K
9120 00:56:22.913154 CBT Training : PASS
9121 00:56:22.913231 Write leveling : PASS
9122 00:56:22.916557 RX DQS gating : PASS
9123 00:56:22.919975 RX DQ/DQS(RDDQC) : PASS
9124 00:56:22.920040 TX DQ/DQS : PASS
9125 00:56:22.922876 RX DATLAT : PASS
9126 00:56:22.926667 RX DQ/DQS(Engine): PASS
9127 00:56:22.926731 TX OE : PASS
9128 00:56:22.929922 All Pass.
9129 00:56:22.929987
9130 00:56:22.930042 CH 1, Rank 0
9131 00:56:22.933057 SW Impedance : PASS
9132 00:56:22.933125 DUTY Scan : NO K
9133 00:56:22.936608 ZQ Calibration : PASS
9134 00:56:22.939597 Jitter Meter : NO K
9135 00:56:22.939662 CBT Training : PASS
9136 00:56:22.942693 Write leveling : PASS
9137 00:56:22.946379 RX DQS gating : PASS
9138 00:56:22.946443 RX DQ/DQS(RDDQC) : PASS
9139 00:56:22.949436 TX DQ/DQS : PASS
9140 00:56:22.953136 RX DATLAT : PASS
9141 00:56:22.953203 RX DQ/DQS(Engine): PASS
9142 00:56:22.956045 TX OE : PASS
9143 00:56:22.956122 All Pass.
9144 00:56:22.956196
9145 00:56:22.959552 CH 1, Rank 1
9146 00:56:22.959622 SW Impedance : PASS
9147 00:56:22.962708 DUTY Scan : NO K
9148 00:56:22.966053 ZQ Calibration : PASS
9149 00:56:22.966129 Jitter Meter : NO K
9150 00:56:22.969068 CBT Training : PASS
9151 00:56:22.972621 Write leveling : PASS
9152 00:56:22.972736 RX DQS gating : PASS
9153 00:56:22.975697 RX DQ/DQS(RDDQC) : PASS
9154 00:56:22.975764 TX DQ/DQS : PASS
9155 00:56:22.979411 RX DATLAT : PASS
9156 00:56:22.982272 RX DQ/DQS(Engine): PASS
9157 00:56:22.982350 TX OE : PASS
9158 00:56:22.985622 All Pass.
9159 00:56:22.985694
9160 00:56:22.985768 DramC Write-DBI on
9161 00:56:22.989106 PER_BANK_REFRESH: Hybrid Mode
9162 00:56:22.992691 TX_TRACKING: ON
9163 00:56:22.999306 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9164 00:56:23.009040 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9165 00:56:23.015768 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9166 00:56:23.019277 [FAST_K] Save calibration result to emmc
9167 00:56:23.022675 sync common calibartion params.
9168 00:56:23.022754 sync cbt_mode0:1, 1:1
9169 00:56:23.025798 dram_init: ddr_geometry: 2
9170 00:56:23.028827 dram_init: ddr_geometry: 2
9171 00:56:23.032133 dram_init: ddr_geometry: 2
9172 00:56:23.032200 0:dram_rank_size:100000000
9173 00:56:23.035567 1:dram_rank_size:100000000
9174 00:56:23.042190 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9175 00:56:23.042265 DFS_SHUFFLE_HW_MODE: ON
9176 00:56:23.048811 dramc_set_vcore_voltage set vcore to 725000
9177 00:56:23.048879 Read voltage for 1600, 0
9178 00:56:23.051712 Vio18 = 0
9179 00:56:23.051799 Vcore = 725000
9180 00:56:23.051885 Vdram = 0
9181 00:56:23.055300 Vddq = 0
9182 00:56:23.055368 Vmddr = 0
9183 00:56:23.058356 switch to 3200 Mbps bootup
9184 00:56:23.058420 [DramcRunTimeConfig]
9185 00:56:23.058474 PHYPLL
9186 00:56:23.061945 DPM_CONTROL_AFTERK: ON
9187 00:56:23.064863 PER_BANK_REFRESH: ON
9188 00:56:23.064924 REFRESH_OVERHEAD_REDUCTION: ON
9189 00:56:23.068257 CMD_PICG_NEW_MODE: OFF
9190 00:56:23.072010 XRTWTW_NEW_MODE: ON
9191 00:56:23.072098 XRTRTR_NEW_MODE: ON
9192 00:56:23.074930 TX_TRACKING: ON
9193 00:56:23.075021 RDSEL_TRACKING: OFF
9194 00:56:23.078397 DQS Precalculation for DVFS: ON
9195 00:56:23.078467 RX_TRACKING: OFF
9196 00:56:23.082011 HW_GATING DBG: ON
9197 00:56:23.082074 ZQCS_ENABLE_LP4: ON
9198 00:56:23.084961 RX_PICG_NEW_MODE: ON
9199 00:56:23.088352 TX_PICG_NEW_MODE: ON
9200 00:56:23.088445 ENABLE_RX_DCM_DPHY: ON
9201 00:56:23.091900 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9202 00:56:23.095225 DUMMY_READ_FOR_TRACKING: OFF
9203 00:56:23.098256 !!! SPM_CONTROL_AFTERK: OFF
9204 00:56:23.101924 !!! SPM could not control APHY
9205 00:56:23.102008 IMPEDANCE_TRACKING: ON
9206 00:56:23.104845 TEMP_SENSOR: ON
9207 00:56:23.104907 HW_SAVE_FOR_SR: OFF
9208 00:56:23.108546 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9209 00:56:23.111386 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9210 00:56:23.114904 Read ODT Tracking: ON
9211 00:56:23.114973 Refresh Rate DeBounce: ON
9212 00:56:23.118415 DFS_NO_QUEUE_FLUSH: ON
9213 00:56:23.121163 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9214 00:56:23.124540 ENABLE_DFS_RUNTIME_MRW: OFF
9215 00:56:23.124631 DDR_RESERVE_NEW_MODE: ON
9216 00:56:23.127961 MR_CBT_SWITCH_FREQ: ON
9217 00:56:23.131374 =========================
9218 00:56:23.149405 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9219 00:56:23.152656 dram_init: ddr_geometry: 2
9220 00:56:23.170801 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9221 00:56:23.174406 dram_init: dram init end (result: 0)
9222 00:56:23.181064 DRAM-K: Full calibration passed in 24549 msecs
9223 00:56:23.184576 MRC: failed to locate region type 0.
9224 00:56:23.184672 DRAM rank0 size:0x100000000,
9225 00:56:23.187525 DRAM rank1 size=0x100000000
9226 00:56:23.197502 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9227 00:56:23.204442 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9228 00:56:23.210950 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9229 00:56:23.217418 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9230 00:56:23.220826 DRAM rank0 size:0x100000000,
9231 00:56:23.223870 DRAM rank1 size=0x100000000
9232 00:56:23.223934 CBMEM:
9233 00:56:23.227359 IMD: root @ 0xfffff000 254 entries.
9234 00:56:23.230927 IMD: root @ 0xffffec00 62 entries.
9235 00:56:23.233818 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9236 00:56:23.237337 WARNING: RO_VPD is uninitialized or empty.
9237 00:56:23.243587 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9238 00:56:23.250810 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9239 00:56:23.264078 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9240 00:56:23.275398 BS: romstage times (exec / console): total (unknown) / 24015 ms
9241 00:56:23.275472
9242 00:56:23.275537
9243 00:56:23.285308 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9244 00:56:23.288547 ARM64: Exception handlers installed.
9245 00:56:23.292081 ARM64: Testing exception
9246 00:56:23.295074 ARM64: Done test exception
9247 00:56:23.295149 Enumerating buses...
9248 00:56:23.298626 Show all devs... Before device enumeration.
9249 00:56:23.301629 Root Device: enabled 1
9250 00:56:23.305097 CPU_CLUSTER: 0: enabled 1
9251 00:56:23.305172 CPU: 00: enabled 1
9252 00:56:23.308583 Compare with tree...
9253 00:56:23.308708 Root Device: enabled 1
9254 00:56:23.311641 CPU_CLUSTER: 0: enabled 1
9255 00:56:23.315341 CPU: 00: enabled 1
9256 00:56:23.315416 Root Device scanning...
9257 00:56:23.318365 scan_static_bus for Root Device
9258 00:56:23.321969 CPU_CLUSTER: 0 enabled
9259 00:56:23.325448 scan_static_bus for Root Device done
9260 00:56:23.328398 scan_bus: bus Root Device finished in 8 msecs
9261 00:56:23.328473 done
9262 00:56:23.335012 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9263 00:56:23.338467 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9264 00:56:23.344996 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9265 00:56:23.348260 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9266 00:56:23.351808 Allocating resources...
9267 00:56:23.354845 Reading resources...
9268 00:56:23.358177 Root Device read_resources bus 0 link: 0
9269 00:56:23.358278 DRAM rank0 size:0x100000000,
9270 00:56:23.361346 DRAM rank1 size=0x100000000
9271 00:56:23.365088 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9272 00:56:23.368007 CPU: 00 missing read_resources
9273 00:56:23.371297 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9274 00:56:23.378125 Root Device read_resources bus 0 link: 0 done
9275 00:56:23.378241 Done reading resources.
9276 00:56:23.384649 Show resources in subtree (Root Device)...After reading.
9277 00:56:23.388326 Root Device child on link 0 CPU_CLUSTER: 0
9278 00:56:23.391222 CPU_CLUSTER: 0 child on link 0 CPU: 00
9279 00:56:23.401521 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9280 00:56:23.401597 CPU: 00
9281 00:56:23.404950 Root Device assign_resources, bus 0 link: 0
9282 00:56:23.407964 CPU_CLUSTER: 0 missing set_resources
9283 00:56:23.411450 Root Device assign_resources, bus 0 link: 0 done
9284 00:56:23.414740 Done setting resources.
9285 00:56:23.421402 Show resources in subtree (Root Device)...After assigning values.
9286 00:56:23.425039 Root Device child on link 0 CPU_CLUSTER: 0
9287 00:56:23.427946 CPU_CLUSTER: 0 child on link 0 CPU: 00
9288 00:56:23.438122 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9289 00:56:23.438194 CPU: 00
9290 00:56:23.441353 Done allocating resources.
9291 00:56:23.444419 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9292 00:56:23.447875 Enabling resources...
9293 00:56:23.447943 done.
9294 00:56:23.454672 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9295 00:56:23.454785 Initializing devices...
9296 00:56:23.457781 Root Device init
9297 00:56:23.457850 init hardware done!
9298 00:56:23.460730 0x00000018: ctrlr->caps
9299 00:56:23.464360 52.000 MHz: ctrlr->f_max
9300 00:56:23.464463 0.400 MHz: ctrlr->f_min
9301 00:56:23.467790 0x40ff8080: ctrlr->voltages
9302 00:56:23.467863 sclk: 390625
9303 00:56:23.470932 Bus Width = 1
9304 00:56:23.471005 sclk: 390625
9305 00:56:23.474140 Bus Width = 1
9306 00:56:23.474204 Early init status = 3
9307 00:56:23.480554 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9308 00:56:23.484045 in-header: 03 fc 00 00 01 00 00 00
9309 00:56:23.487526 in-data: 00
9310 00:56:23.490481 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9311 00:56:23.495966 in-header: 03 fd 00 00 00 00 00 00
9312 00:56:23.499560 in-data:
9313 00:56:23.502306 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9314 00:56:23.506841 in-header: 03 fc 00 00 01 00 00 00
9315 00:56:23.510147 in-data: 00
9316 00:56:23.513482 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9317 00:56:23.518981 in-header: 03 fd 00 00 00 00 00 00
9318 00:56:23.522449 in-data:
9319 00:56:23.525741 [SSUSB] Setting up USB HOST controller...
9320 00:56:23.528728 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9321 00:56:23.532506 [SSUSB] phy power-on done.
9322 00:56:23.535554 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9323 00:56:23.542441 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9324 00:56:23.545435 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9325 00:56:23.552424 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9326 00:56:23.558911 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9327 00:56:23.565495 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9328 00:56:23.571657 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9329 00:56:23.578664 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9330 00:56:23.581942 SPM: binary array size = 0x9dc
9331 00:56:23.584961 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9332 00:56:23.592110 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9333 00:56:23.598260 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9334 00:56:23.605282 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9335 00:56:23.608181 configure_display: Starting display init
9336 00:56:23.642126 anx7625_power_on_init: Init interface.
9337 00:56:23.645751 anx7625_disable_pd_protocol: Disabled PD feature.
9338 00:56:23.649108 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9339 00:56:23.676664 anx7625_start_dp_work: Secure OCM version=00
9340 00:56:23.680197 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9341 00:56:23.695010 sp_tx_get_edid_block: EDID Block = 1
9342 00:56:23.797338 Extracted contents:
9343 00:56:23.800777 header: 00 ff ff ff ff ff ff 00
9344 00:56:23.803836 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9345 00:56:23.807475 version: 01 04
9346 00:56:23.810434 basic params: 95 1f 11 78 0a
9347 00:56:23.813972 chroma info: 76 90 94 55 54 90 27 21 50 54
9348 00:56:23.816994 established: 00 00 00
9349 00:56:23.823698 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9350 00:56:23.830131 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9351 00:56:23.833692 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9352 00:56:23.840071 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9353 00:56:23.847072 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9354 00:56:23.850171 extensions: 00
9355 00:56:23.850246 checksum: fb
9356 00:56:23.850304
9357 00:56:23.853490 Manufacturer: IVO Model 57d Serial Number 0
9358 00:56:23.856736 Made week 0 of 2020
9359 00:56:23.859600 EDID version: 1.4
9360 00:56:23.859675 Digital display
9361 00:56:23.863220 6 bits per primary color channel
9362 00:56:23.866247 DisplayPort interface
9363 00:56:23.866321 Maximum image size: 31 cm x 17 cm
9364 00:56:23.869936 Gamma: 220%
9365 00:56:23.870010 Check DPMS levels
9366 00:56:23.876452 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9367 00:56:23.879624 First detailed timing is preferred timing
9368 00:56:23.879713 Established timings supported:
9369 00:56:23.883339 Standard timings supported:
9370 00:56:23.886329 Detailed timings
9371 00:56:23.889775 Hex of detail: 383680a07038204018303c0035ae10000019
9372 00:56:23.896363 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9373 00:56:23.899898 0780 0798 07c8 0820 hborder 0
9374 00:56:23.902697 0438 043b 0447 0458 vborder 0
9375 00:56:23.906043 -hsync -vsync
9376 00:56:23.906117 Did detailed timing
9377 00:56:23.912536 Hex of detail: 000000000000000000000000000000000000
9378 00:56:23.916118 Manufacturer-specified data, tag 0
9379 00:56:23.919709 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9380 00:56:23.922708 ASCII string: InfoVision
9381 00:56:23.925758 Hex of detail: 000000fe00523134304e574635205248200a
9382 00:56:23.929355 ASCII string: R140NWF5 RH
9383 00:56:23.929428 Checksum
9384 00:56:23.932792 Checksum: 0xfb (valid)
9385 00:56:23.935716 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9386 00:56:23.939233 DSI data_rate: 832800000 bps
9387 00:56:23.945613 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9388 00:56:23.948925 anx7625_parse_edid: pixelclock(138800).
9389 00:56:23.952203 hactive(1920), hsync(48), hfp(24), hbp(88)
9390 00:56:23.955331 vactive(1080), vsync(12), vfp(3), vbp(17)
9391 00:56:23.958632 anx7625_dsi_config: config dsi.
9392 00:56:23.965614 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9393 00:56:23.979517 anx7625_dsi_config: success to config DSI
9394 00:56:23.982434 anx7625_dp_start: MIPI phy setup OK.
9395 00:56:23.985784 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9396 00:56:23.989174 mtk_ddp_mode_set invalid vrefresh 60
9397 00:56:23.992561 main_disp_path_setup
9398 00:56:23.992671 ovl_layer_smi_id_en
9399 00:56:23.996205 ovl_layer_smi_id_en
9400 00:56:23.996269 ccorr_config
9401 00:56:23.996322 aal_config
9402 00:56:23.999190 gamma_config
9403 00:56:23.999255 postmask_config
9404 00:56:24.002379 dither_config
9405 00:56:24.006004 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9406 00:56:24.012894 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9407 00:56:24.016158 Root Device init finished in 555 msecs
9408 00:56:24.019116 CPU_CLUSTER: 0 init
9409 00:56:24.025776 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9410 00:56:24.029356 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9411 00:56:24.032362 APU_MBOX 0x190000b0 = 0x10001
9412 00:56:24.035727 APU_MBOX 0x190001b0 = 0x10001
9413 00:56:24.039276 APU_MBOX 0x190005b0 = 0x10001
9414 00:56:24.042109 APU_MBOX 0x190006b0 = 0x10001
9415 00:56:24.045553 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9416 00:56:24.058304 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9417 00:56:24.070700 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9418 00:56:24.077100 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9419 00:56:24.089141 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9420 00:56:24.098279 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9421 00:56:24.101236 CPU_CLUSTER: 0 init finished in 81 msecs
9422 00:56:24.104913 Devices initialized
9423 00:56:24.108398 Show all devs... After init.
9424 00:56:24.108474 Root Device: enabled 1
9425 00:56:24.111473 CPU_CLUSTER: 0: enabled 1
9426 00:56:24.114484 CPU: 00: enabled 1
9427 00:56:24.118261 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9428 00:56:24.121514 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9429 00:56:24.124929 ELOG: NV offset 0x57f000 size 0x1000
9430 00:56:24.131458 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9431 00:56:24.137562 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9432 00:56:24.140953 ELOG: Event(17) added with size 13 at 2024-06-16 00:56:23 UTC
9433 00:56:24.147550 out: cmd=0x121: 03 db 21 01 00 00 00 00
9434 00:56:24.151020 in-header: 03 9b 00 00 2c 00 00 00
9435 00:56:24.161013 in-data: a2 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9436 00:56:24.167574 ELOG: Event(A1) added with size 10 at 2024-06-16 00:56:23 UTC
9437 00:56:24.173933 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9438 00:56:24.180665 ELOG: Event(A0) added with size 9 at 2024-06-16 00:56:23 UTC
9439 00:56:24.184302 elog_add_boot_reason: Logged dev mode boot
9440 00:56:24.190576 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9441 00:56:24.190646 Finalize devices...
9442 00:56:24.194342 Devices finalized
9443 00:56:24.197142 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9444 00:56:24.200514 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9445 00:56:24.203778 in-header: 03 07 00 00 08 00 00 00
9446 00:56:24.207420 in-data: aa e4 47 04 13 02 00 00
9447 00:56:24.210555 Chrome EC: UHEPI supported
9448 00:56:24.217215 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9449 00:56:24.220924 in-header: 03 a9 00 00 08 00 00 00
9450 00:56:24.223833 in-data: 84 60 60 08 00 00 00 00
9451 00:56:24.230467 ELOG: Event(91) added with size 10 at 2024-06-16 00:56:23 UTC
9452 00:56:24.234043 Chrome EC: clear events_b mask to 0x0000000020004000
9453 00:56:24.240537 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9454 00:56:24.244025 in-header: 03 fd 00 00 00 00 00 00
9455 00:56:24.244096 in-data:
9456 00:56:24.250505 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9457 00:56:24.254075 Writing coreboot table at 0xffe64000
9458 00:56:24.257476 0. 000000000010a000-0000000000113fff: RAMSTAGE
9459 00:56:24.260865 1. 0000000040000000-00000000400fffff: RAM
9460 00:56:24.266967 2. 0000000040100000-000000004032afff: RAMSTAGE
9461 00:56:24.270550 3. 000000004032b000-00000000545fffff: RAM
9462 00:56:24.273941 4. 0000000054600000-000000005465ffff: BL31
9463 00:56:24.277414 5. 0000000054660000-00000000ffe63fff: RAM
9464 00:56:24.283581 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9465 00:56:24.287434 7. 0000000100000000-000000023fffffff: RAM
9466 00:56:24.290414 Passing 5 GPIOs to payload:
9467 00:56:24.294009 NAME | PORT | POLARITY | VALUE
9468 00:56:24.296864 EC in RW | 0x000000aa | low | undefined
9469 00:56:24.303838 EC interrupt | 0x00000005 | low | undefined
9470 00:56:24.307104 TPM interrupt | 0x000000ab | high | undefined
9471 00:56:24.313812 SD card detect | 0x00000011 | high | undefined
9472 00:56:24.317020 speaker enable | 0x00000093 | high | undefined
9473 00:56:24.320386 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9474 00:56:24.323433 in-header: 03 f9 00 00 02 00 00 00
9475 00:56:24.327069 in-data: 02 00
9476 00:56:24.327144 ADC[4]: Raw value=894821 ID=7
9477 00:56:24.330060 ADC[3]: Raw value=212330 ID=1
9478 00:56:24.333547 RAM Code: 0x71
9479 00:56:24.333621 ADC[6]: Raw value=74722 ID=0
9480 00:56:24.336968 ADC[5]: Raw value=212700 ID=1
9481 00:56:24.340077 SKU Code: 0x1
9482 00:56:24.343755 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 35d1
9483 00:56:24.346710 coreboot table: 964 bytes.
9484 00:56:24.350052 IMD ROOT 0. 0xfffff000 0x00001000
9485 00:56:24.353554 IMD SMALL 1. 0xffffe000 0x00001000
9486 00:56:24.356567 RO MCACHE 2. 0xffffc000 0x00001104
9487 00:56:24.360160 CONSOLE 3. 0xfff7c000 0x00080000
9488 00:56:24.363689 FMAP 4. 0xfff7b000 0x00000452
9489 00:56:24.366528 TIME STAMP 5. 0xfff7a000 0x00000910
9490 00:56:24.369955 VBOOT WORK 6. 0xfff66000 0x00014000
9491 00:56:24.373426 RAMOOPS 7. 0xffe66000 0x00100000
9492 00:56:24.376435 COREBOOT 8. 0xffe64000 0x00002000
9493 00:56:24.379638 IMD small region:
9494 00:56:24.383325 IMD ROOT 0. 0xffffec00 0x00000400
9495 00:56:24.386395 VPD 1. 0xffffeb80 0x0000006c
9496 00:56:24.389756 MMC STATUS 2. 0xffffeb60 0x00000004
9497 00:56:24.393053 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9498 00:56:24.399582 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9499 00:56:24.440391 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9500 00:56:24.443841 Checking segment from ROM address 0x40100000
9501 00:56:24.447198 Checking segment from ROM address 0x4010001c
9502 00:56:24.453732 Loading segment from ROM address 0x40100000
9503 00:56:24.453808 code (compression=0)
9504 00:56:24.460672 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9505 00:56:24.470563 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9506 00:56:24.470639 it's not compressed!
9507 00:56:24.476836 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9508 00:56:24.480387 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9509 00:56:24.500577 Loading segment from ROM address 0x4010001c
9510 00:56:24.500656 Entry Point 0x80000000
9511 00:56:24.503998 Loaded segments
9512 00:56:24.506953 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9513 00:56:24.514046 Jumping to boot code at 0x80000000(0xffe64000)
9514 00:56:24.520430 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9515 00:56:24.527281 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9516 00:56:24.535199 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9517 00:56:24.538301 Checking segment from ROM address 0x40100000
9518 00:56:24.541906 Checking segment from ROM address 0x4010001c
9519 00:56:24.548452 Loading segment from ROM address 0x40100000
9520 00:56:24.548517 code (compression=1)
9521 00:56:24.554678 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9522 00:56:24.564788 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9523 00:56:24.564858 using LZMA
9524 00:56:24.573584 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9525 00:56:24.580544 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9526 00:56:24.584023 Loading segment from ROM address 0x4010001c
9527 00:56:24.584494 Entry Point 0x54601000
9528 00:56:24.587032 Loaded segments
9529 00:56:24.590616 NOTICE: MT8192 bl31_setup
9530 00:56:24.597728 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9531 00:56:24.600883 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9532 00:56:24.603895 WARNING: region 0:
9533 00:56:24.607271 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9534 00:56:24.607714 WARNING: region 1:
9535 00:56:24.613957 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9536 00:56:24.617633 WARNING: region 2:
9537 00:56:24.620626 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9538 00:56:24.624280 WARNING: region 3:
9539 00:56:24.627117 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9540 00:56:24.630316 WARNING: region 4:
9541 00:56:24.637353 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9542 00:56:24.637832 WARNING: region 5:
9543 00:56:24.640387 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 00:56:24.643801 WARNING: region 6:
9545 00:56:24.647122 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 00:56:24.650560 WARNING: region 7:
9547 00:56:24.653677 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 00:56:24.660001 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9549 00:56:24.663576 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9550 00:56:24.666811 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9551 00:56:24.673695 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9552 00:56:24.676377 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9553 00:56:24.682937 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9554 00:56:24.686282 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9555 00:56:24.689856 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9556 00:56:24.696368 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9557 00:56:24.699866 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9558 00:56:24.702926 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9559 00:56:24.709488 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9560 00:56:24.713030 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9561 00:56:24.719553 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9562 00:56:24.722760 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9563 00:56:24.726355 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9564 00:56:24.732983 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9565 00:56:24.735877 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9566 00:56:24.743023 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9567 00:56:24.745664 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9568 00:56:24.749137 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9569 00:56:24.756088 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9570 00:56:24.758917 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9571 00:56:24.765931 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9572 00:56:24.769387 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9573 00:56:24.772337 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9574 00:56:24.779005 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9575 00:56:24.782752 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9576 00:56:24.789277 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9577 00:56:24.792776 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9578 00:56:24.795661 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9579 00:56:24.802751 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9580 00:56:24.806124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9581 00:56:24.809159 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9582 00:56:24.812193 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9583 00:56:24.819428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9584 00:56:24.822269 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9585 00:56:24.825691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9586 00:56:24.828984 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9587 00:56:24.835760 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9588 00:56:24.839333 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9589 00:56:24.842256 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9590 00:56:24.845849 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9591 00:56:24.852160 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9592 00:56:24.855469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9593 00:56:24.858680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9594 00:56:24.862091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9595 00:56:24.868760 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9596 00:56:24.872134 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9597 00:56:24.879098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9598 00:56:24.882000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9599 00:56:24.885434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9600 00:56:24.892066 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9601 00:56:24.895640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9602 00:56:24.901956 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9603 00:56:24.905602 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9604 00:56:24.911923 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9605 00:56:24.915615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9606 00:56:24.918704 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9607 00:56:24.925183 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9608 00:56:24.928713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9609 00:56:24.935206 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9610 00:56:24.938584 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9611 00:56:24.944971 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9612 00:56:24.948414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9613 00:56:24.954931 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9614 00:56:24.958368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9615 00:56:24.961598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9616 00:56:24.968041 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9617 00:56:24.971903 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9618 00:56:24.978209 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9619 00:56:24.981324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9620 00:56:24.988163 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9621 00:56:24.991552 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9622 00:56:24.998189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9623 00:56:25.001393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9624 00:56:25.004757 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9625 00:56:25.011266 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9626 00:56:25.014296 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9627 00:56:25.020842 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9628 00:56:25.024492 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9629 00:56:25.031091 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9630 00:56:25.034077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9631 00:56:25.041280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9632 00:56:25.044304 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9633 00:56:25.050614 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9634 00:56:25.053886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9635 00:56:25.057061 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9636 00:56:25.063641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9637 00:56:25.067237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9638 00:56:25.073747 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9639 00:56:25.076996 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9640 00:56:25.083600 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9641 00:56:25.087205 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9642 00:56:25.093544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9643 00:56:25.096871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9644 00:56:25.100198 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9645 00:56:25.106934 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9646 00:56:25.110256 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9647 00:56:25.113908 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9648 00:56:25.116910 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9649 00:56:25.123328 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9650 00:56:25.126911 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9651 00:56:25.133493 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9652 00:56:25.136434 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9653 00:56:25.140009 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9654 00:56:25.146349 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9655 00:56:25.149730 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9656 00:56:25.156382 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9657 00:56:25.159806 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9658 00:56:25.163018 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9659 00:56:25.169691 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9660 00:56:25.173399 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9661 00:56:25.179551 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9662 00:56:25.182847 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9663 00:56:25.186259 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9664 00:56:25.193123 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9665 00:56:25.195854 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9666 00:56:25.199575 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9667 00:56:25.205876 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9668 00:56:25.209642 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9669 00:56:25.212489 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9670 00:56:25.216005 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9671 00:56:25.222983 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9672 00:56:25.225879 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9673 00:56:25.229334 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9674 00:56:25.236011 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9675 00:56:25.239536 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9676 00:56:25.246250 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9677 00:56:25.249196 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9678 00:56:25.252671 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9679 00:56:25.259397 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9680 00:56:25.262383 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9681 00:56:25.265962 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9682 00:56:25.272606 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9683 00:56:25.275956 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9684 00:56:25.282425 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9685 00:56:25.285839 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9686 00:56:25.289335 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9687 00:56:25.295691 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9688 00:56:25.299278 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9689 00:56:25.305701 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9690 00:56:25.309051 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9691 00:56:25.312361 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9692 00:56:25.318901 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9693 00:56:25.322474 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9694 00:56:25.328540 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9695 00:56:25.332295 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9696 00:56:25.335744 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9697 00:56:25.342296 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9698 00:56:25.345210 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9699 00:56:25.351897 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9700 00:56:25.355418 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9701 00:56:25.358502 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9702 00:56:25.365076 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9703 00:56:25.368688 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9704 00:56:25.375449 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9705 00:56:25.378806 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9706 00:56:25.381908 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9707 00:56:25.388827 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9708 00:56:25.391675 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9709 00:56:25.395249 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9710 00:56:25.402017 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9711 00:56:25.405332 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9712 00:56:25.412006 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9713 00:56:25.415367 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9714 00:56:25.418428 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9715 00:56:25.424806 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9716 00:56:25.428157 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9717 00:56:25.435262 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9718 00:56:25.438318 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9719 00:56:25.441638 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9720 00:56:25.448392 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9721 00:56:25.451402 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9722 00:56:25.457959 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9723 00:56:25.461210 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9724 00:56:25.464915 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9725 00:56:25.471555 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9726 00:56:25.474562 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9727 00:56:25.481277 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9728 00:56:25.484697 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9729 00:56:25.488082 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9730 00:56:25.494683 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9731 00:56:25.497972 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9732 00:56:25.504503 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9733 00:56:25.507408 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9734 00:56:25.511345 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9735 00:56:25.517628 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9736 00:56:25.521097 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9737 00:56:25.527412 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9738 00:56:25.531060 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9739 00:56:25.534033 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9740 00:56:25.540576 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9741 00:56:25.544040 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9742 00:56:25.550870 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9743 00:56:25.553892 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9744 00:56:25.560789 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9745 00:56:25.564180 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9746 00:56:25.567230 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9747 00:56:25.573986 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9748 00:56:25.577533 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9749 00:56:25.584190 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9750 00:56:25.587278 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9751 00:56:25.590783 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9752 00:56:25.597120 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9753 00:56:25.600547 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9754 00:56:25.606712 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9755 00:56:25.610235 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9756 00:56:25.617084 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9757 00:56:25.620260 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9758 00:56:25.623612 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9759 00:56:25.630454 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9760 00:56:25.633350 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9761 00:56:25.639871 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9762 00:56:25.643615 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9763 00:56:25.650054 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9764 00:56:25.653063 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9765 00:56:25.656585 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9766 00:56:25.663530 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9767 00:56:25.666822 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9768 00:56:25.673232 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9769 00:56:25.676581 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9770 00:56:25.680097 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9771 00:56:25.686872 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9772 00:56:25.689896 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9773 00:56:25.696384 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9774 00:56:25.699933 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9775 00:56:25.706545 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9776 00:56:25.710115 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9777 00:56:25.713518 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9778 00:56:25.716640 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9779 00:56:25.723129 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9780 00:56:25.726420 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9781 00:56:25.729681 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9782 00:56:25.733031 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9783 00:56:25.739742 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9784 00:56:25.742685 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9785 00:56:25.749338 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9786 00:56:25.752667 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9787 00:56:25.756254 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9788 00:56:25.762903 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9789 00:56:25.765813 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9790 00:56:25.772356 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9791 00:56:25.775895 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9792 00:56:25.779232 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9793 00:56:25.785578 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9794 00:56:25.788961 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9795 00:56:25.792447 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9796 00:56:25.799029 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9797 00:56:25.802550 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9798 00:56:25.805580 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9799 00:56:25.812210 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9800 00:56:25.815232 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9801 00:56:25.818832 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9802 00:56:25.825669 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9803 00:56:25.828831 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9804 00:56:25.835414 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9805 00:56:25.838500 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9806 00:56:25.841643 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9807 00:56:25.848603 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9808 00:56:25.851544 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9809 00:56:25.858009 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9810 00:56:25.861620 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9811 00:56:25.864580 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9812 00:56:25.871314 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9813 00:56:25.874823 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9814 00:56:25.878139 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9815 00:56:25.884512 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9816 00:56:25.887883 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9817 00:56:25.891457 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9818 00:56:25.897992 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9819 00:56:25.901369 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9820 00:56:25.904749 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9821 00:56:25.907736 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9822 00:56:25.914306 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9823 00:56:25.917947 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9824 00:56:25.920869 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9825 00:56:25.924476 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9826 00:56:25.931043 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9827 00:56:25.934045 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9828 00:56:25.937508 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9829 00:56:25.940408 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9830 00:56:25.947415 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9831 00:56:25.950588 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9832 00:56:25.957126 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9833 00:56:25.960289 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9834 00:56:25.967346 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9835 00:56:25.970402 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9836 00:56:25.973896 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9837 00:56:25.980553 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9838 00:56:25.983385 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9839 00:56:25.990078 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9840 00:56:25.993552 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9841 00:56:25.997130 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9842 00:56:26.003553 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9843 00:56:26.006878 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9844 00:56:26.013717 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9845 00:56:26.017004 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9846 00:56:26.020027 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9847 00:56:26.027099 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9848 00:56:26.030160 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9849 00:56:26.036719 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9850 00:56:26.040069 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9851 00:56:26.046662 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9852 00:56:26.050107 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9853 00:56:26.053026 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9854 00:56:26.059729 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9855 00:56:26.063122 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9856 00:56:26.069762 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9857 00:56:26.072987 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9858 00:56:26.079366 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9859 00:56:26.082993 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9860 00:56:26.086143 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9861 00:56:26.093004 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9862 00:56:26.096118 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9863 00:56:26.102662 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9864 00:56:26.105775 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9865 00:56:26.109382 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9866 00:56:26.115727 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9867 00:56:26.119122 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9868 00:56:26.125729 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9869 00:56:26.129381 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9870 00:56:26.132332 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9871 00:56:26.138984 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9872 00:56:26.142502 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9873 00:56:26.148828 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9874 00:56:26.152344 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9875 00:56:26.158789 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9876 00:56:26.162236 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9877 00:56:26.165539 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9878 00:56:26.172142 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9879 00:56:26.175376 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9880 00:56:26.182086 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9881 00:56:26.185526 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9882 00:56:26.188569 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9883 00:56:26.195245 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9884 00:56:26.198716 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9885 00:56:26.205262 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9886 00:56:26.208404 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9887 00:56:26.214939 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9888 00:56:26.218571 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9889 00:56:26.221530 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9890 00:56:26.228658 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9891 00:56:26.231574 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9892 00:56:26.238432 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9893 00:56:26.241144 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9894 00:56:26.244956 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9895 00:56:26.251419 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9896 00:56:26.254520 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9897 00:56:26.261073 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9898 00:56:26.264278 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9899 00:56:26.271035 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9900 00:56:26.274405 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9901 00:56:26.277744 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9902 00:56:26.284514 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9903 00:56:26.287904 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9904 00:56:26.294410 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9905 00:56:26.297575 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9906 00:56:26.304457 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9907 00:56:26.307412 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9908 00:56:26.313878 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9909 00:56:26.317650 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9910 00:56:26.320745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9911 00:56:26.327659 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9912 00:56:26.330680 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9913 00:56:26.337454 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9914 00:56:26.340872 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9915 00:56:26.347127 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9916 00:56:26.350411 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9917 00:56:26.353874 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9918 00:56:26.360187 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9919 00:56:26.363541 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9920 00:56:26.370298 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9921 00:56:26.373870 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9922 00:56:26.380206 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9923 00:56:26.383573 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9924 00:56:26.389946 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9925 00:56:26.393667 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9926 00:56:26.397137 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9927 00:56:26.403518 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9928 00:56:26.406550 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9929 00:56:26.413423 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9930 00:56:26.417011 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9931 00:56:26.423217 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9932 00:56:26.426959 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9933 00:56:26.430111 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9934 00:56:26.436857 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9935 00:56:26.439988 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9936 00:56:26.446849 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9937 00:56:26.449928 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9938 00:56:26.456826 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9939 00:56:26.459985 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9940 00:56:26.463267 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9941 00:56:26.469817 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9942 00:56:26.473339 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9943 00:56:26.479691 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9944 00:56:26.483319 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9945 00:56:26.489541 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9946 00:56:26.493260 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9947 00:56:26.499475 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9948 00:56:26.502731 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9949 00:56:26.506118 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9950 00:56:26.513087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9951 00:56:26.516124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9952 00:56:26.522827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9953 00:56:26.526214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9954 00:56:26.529394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9955 00:56:26.536454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9956 00:56:26.539416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9957 00:56:26.546107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9958 00:56:26.549572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9959 00:56:26.556171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9960 00:56:26.559115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9961 00:56:26.566247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9962 00:56:26.569304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9963 00:56:26.576177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9964 00:56:26.579045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9965 00:56:26.585943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9966 00:56:26.589191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9967 00:56:26.595853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9968 00:56:26.599448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9969 00:56:26.605738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9970 00:56:26.608907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9971 00:56:26.615661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9972 00:56:26.618911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9973 00:56:26.625727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9974 00:56:26.628658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9975 00:56:26.635571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9976 00:56:26.639016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9977 00:56:26.645104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9978 00:56:26.648884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9979 00:56:26.655555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9980 00:56:26.658697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9981 00:56:26.665057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9982 00:56:26.668318 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9983 00:56:26.672102 INFO: [APUAPC] vio 0
9984 00:56:26.675062 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9985 00:56:26.681981 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9986 00:56:26.684806 INFO: [APUAPC] D0_APC_0: 0x400510
9987 00:56:26.688576 INFO: [APUAPC] D0_APC_1: 0x0
9988 00:56:26.688675 INFO: [APUAPC] D0_APC_2: 0x1540
9989 00:56:26.691680 INFO: [APUAPC] D0_APC_3: 0x0
9990 00:56:26.694719 INFO: [APUAPC] D1_APC_0: 0xffffffff
9991 00:56:26.698618 INFO: [APUAPC] D1_APC_1: 0xffffffff
9992 00:56:26.701653 INFO: [APUAPC] D1_APC_2: 0x3fffff
9993 00:56:26.704919 INFO: [APUAPC] D1_APC_3: 0x0
9994 00:56:26.707892 INFO: [APUAPC] D2_APC_0: 0xffffffff
9995 00:56:26.711354 INFO: [APUAPC] D2_APC_1: 0xffffffff
9996 00:56:26.714701 INFO: [APUAPC] D2_APC_2: 0x3fffff
9997 00:56:26.718058 INFO: [APUAPC] D2_APC_3: 0x0
9998 00:56:26.721513 INFO: [APUAPC] D3_APC_0: 0xffffffff
9999 00:56:26.724575 INFO: [APUAPC] D3_APC_1: 0xffffffff
10000 00:56:26.727965 INFO: [APUAPC] D3_APC_2: 0x3fffff
10001 00:56:26.731248 INFO: [APUAPC] D3_APC_3: 0x0
10002 00:56:26.734621 INFO: [APUAPC] D4_APC_0: 0xffffffff
10003 00:56:26.738010 INFO: [APUAPC] D4_APC_1: 0xffffffff
10004 00:56:26.740957 INFO: [APUAPC] D4_APC_2: 0x3fffff
10005 00:56:26.744338 INFO: [APUAPC] D4_APC_3: 0x0
10006 00:56:26.747607 INFO: [APUAPC] D5_APC_0: 0xffffffff
10007 00:56:26.751302 INFO: [APUAPC] D5_APC_1: 0xffffffff
10008 00:56:26.754269 INFO: [APUAPC] D5_APC_2: 0x3fffff
10009 00:56:26.757835 INFO: [APUAPC] D5_APC_3: 0x0
10010 00:56:26.760850 INFO: [APUAPC] D6_APC_0: 0xffffffff
10011 00:56:26.764352 INFO: [APUAPC] D6_APC_1: 0xffffffff
10012 00:56:26.767970 INFO: [APUAPC] D6_APC_2: 0x3fffff
10013 00:56:26.770983 INFO: [APUAPC] D6_APC_3: 0x0
10014 00:56:26.774623 INFO: [APUAPC] D7_APC_0: 0xffffffff
10015 00:56:26.777603 INFO: [APUAPC] D7_APC_1: 0xffffffff
10016 00:56:26.781142 INFO: [APUAPC] D7_APC_2: 0x3fffff
10017 00:56:26.784130 INFO: [APUAPC] D7_APC_3: 0x0
10018 00:56:26.787757 INFO: [APUAPC] D8_APC_0: 0xffffffff
10019 00:56:26.791143 INFO: [APUAPC] D8_APC_1: 0xffffffff
10020 00:56:26.794058 INFO: [APUAPC] D8_APC_2: 0x3fffff
10021 00:56:26.797623 INFO: [APUAPC] D8_APC_3: 0x0
10022 00:56:26.800461 INFO: [APUAPC] D9_APC_0: 0xffffffff
10023 00:56:26.804191 INFO: [APUAPC] D9_APC_1: 0xffffffff
10024 00:56:26.807136 INFO: [APUAPC] D9_APC_2: 0x3fffff
10025 00:56:26.810792 INFO: [APUAPC] D9_APC_3: 0x0
10026 00:56:26.814053 INFO: [APUAPC] D10_APC_0: 0xffffffff
10027 00:56:26.817067 INFO: [APUAPC] D10_APC_1: 0xffffffff
10028 00:56:26.820636 INFO: [APUAPC] D10_APC_2: 0x3fffff
10029 00:56:26.824103 INFO: [APUAPC] D10_APC_3: 0x0
10030 00:56:26.827527 INFO: [APUAPC] D11_APC_0: 0xffffffff
10031 00:56:26.830505 INFO: [APUAPC] D11_APC_1: 0xffffffff
10032 00:56:26.833936 INFO: [APUAPC] D11_APC_2: 0x3fffff
10033 00:56:26.837300 INFO: [APUAPC] D11_APC_3: 0x0
10034 00:56:26.840406 INFO: [APUAPC] D12_APC_0: 0xffffffff
10035 00:56:26.844076 INFO: [APUAPC] D12_APC_1: 0xffffffff
10036 00:56:26.846963 INFO: [APUAPC] D12_APC_2: 0x3fffff
10037 00:56:26.850595 INFO: [APUAPC] D12_APC_3: 0x0
10038 00:56:26.853838 INFO: [APUAPC] D13_APC_0: 0xffffffff
10039 00:56:26.857039 INFO: [APUAPC] D13_APC_1: 0xffffffff
10040 00:56:26.860280 INFO: [APUAPC] D13_APC_2: 0x3fffff
10041 00:56:26.863629 INFO: [APUAPC] D13_APC_3: 0x0
10042 00:56:26.866952 INFO: [APUAPC] D14_APC_0: 0xffffffff
10043 00:56:26.870364 INFO: [APUAPC] D14_APC_1: 0xffffffff
10044 00:56:26.873472 INFO: [APUAPC] D14_APC_2: 0x3fffff
10045 00:56:26.878453 INFO: [APUAPC] D14_APC_3: 0x0
10046 00:56:26.880095 INFO: [APUAPC] D15_APC_0: 0xffffffff
10047 00:56:26.883922 INFO: [APUAPC] D15_APC_1: 0xffffffff
10048 00:56:26.886995 INFO: [APUAPC] D15_APC_2: 0x3fffff
10049 00:56:26.890072 INFO: [APUAPC] D15_APC_3: 0x0
10050 00:56:26.893768 INFO: [APUAPC] APC_CON: 0x4
10051 00:56:26.897035 INFO: [NOCDAPC] D0_APC_0: 0x0
10052 00:56:26.897151 INFO: [NOCDAPC] D0_APC_1: 0x0
10053 00:56:26.899991 INFO: [NOCDAPC] D1_APC_0: 0x0
10054 00:56:26.903491 INFO: [NOCDAPC] D1_APC_1: 0xfff
10055 00:56:26.906466 INFO: [NOCDAPC] D2_APC_0: 0x0
10056 00:56:26.910319 INFO: [NOCDAPC] D2_APC_1: 0xfff
10057 00:56:26.913358 INFO: [NOCDAPC] D3_APC_0: 0x0
10058 00:56:26.917114 INFO: [NOCDAPC] D3_APC_1: 0xfff
10059 00:56:26.920142 INFO: [NOCDAPC] D4_APC_0: 0x0
10060 00:56:26.923108 INFO: [NOCDAPC] D4_APC_1: 0xfff
10061 00:56:26.926849 INFO: [NOCDAPC] D5_APC_0: 0x0
10062 00:56:26.929833 INFO: [NOCDAPC] D5_APC_1: 0xfff
10063 00:56:26.932911 INFO: [NOCDAPC] D6_APC_0: 0x0
10064 00:56:26.933013 INFO: [NOCDAPC] D6_APC_1: 0xfff
10065 00:56:26.936546 INFO: [NOCDAPC] D7_APC_0: 0x0
10066 00:56:26.939690 INFO: [NOCDAPC] D7_APC_1: 0xfff
10067 00:56:26.943330 INFO: [NOCDAPC] D8_APC_0: 0x0
10068 00:56:26.946366 INFO: [NOCDAPC] D8_APC_1: 0xfff
10069 00:56:26.949965 INFO: [NOCDAPC] D9_APC_0: 0x0
10070 00:56:26.953000 INFO: [NOCDAPC] D9_APC_1: 0xfff
10071 00:56:26.956539 INFO: [NOCDAPC] D10_APC_0: 0x0
10072 00:56:26.959950 INFO: [NOCDAPC] D10_APC_1: 0xfff
10073 00:56:26.962921 INFO: [NOCDAPC] D11_APC_0: 0x0
10074 00:56:26.966738 INFO: [NOCDAPC] D11_APC_1: 0xfff
10075 00:56:26.969617 INFO: [NOCDAPC] D12_APC_0: 0x0
10076 00:56:26.972954 INFO: [NOCDAPC] D12_APC_1: 0xfff
10077 00:56:26.973046 INFO: [NOCDAPC] D13_APC_0: 0x0
10078 00:56:26.976102 INFO: [NOCDAPC] D13_APC_1: 0xfff
10079 00:56:26.979665 INFO: [NOCDAPC] D14_APC_0: 0x0
10080 00:56:26.982821 INFO: [NOCDAPC] D14_APC_1: 0xfff
10081 00:56:26.985962 INFO: [NOCDAPC] D15_APC_0: 0x0
10082 00:56:26.989588 INFO: [NOCDAPC] D15_APC_1: 0xfff
10083 00:56:26.992851 INFO: [NOCDAPC] APC_CON: 0x4
10084 00:56:26.996422 INFO: [APUAPC] set_apusys_apc done
10085 00:56:26.999453 INFO: [DEVAPC] devapc_init done
10086 00:56:27.002592 INFO: GICv3 without legacy support detected.
10087 00:56:27.006209 INFO: ARM GICv3 driver initialized in EL3
10088 00:56:27.012985 INFO: Maximum SPI INTID supported: 639
10089 00:56:27.016198 INFO: BL31: Initializing runtime services
10090 00:56:27.022359 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10091 00:56:27.022465 INFO: SPM: enable CPC mode
10092 00:56:27.029180 INFO: mcdi ready for mcusys-off-idle and system suspend
10093 00:56:27.032373 INFO: BL31: Preparing for EL3 exit to normal world
10094 00:56:27.035866 INFO: Entry point address = 0x80000000
10095 00:56:27.038898 INFO: SPSR = 0x8
10096 00:56:27.045090
10097 00:56:27.045191
10098 00:56:27.045275
10099 00:56:27.048044 Starting depthcharge on Spherion...
10100 00:56:27.048139
10101 00:56:27.048228 Wipe memory regions:
10102 00:56:27.048308
10103 00:56:27.049047 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10104 00:56:27.049197 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10105 00:56:27.049306 Setting prompt string to ['asurada:']
10106 00:56:27.049411 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10107 00:56:27.051681 [0x00000040000000, 0x00000054600000)
10108 00:56:27.173670
10109 00:56:27.173810 [0x00000054660000, 0x00000080000000)
10110 00:56:27.434200
10111 00:56:27.434345 [0x000000821a7280, 0x000000ffe64000)
10112 00:56:28.177956
10113 00:56:28.178070 [0x00000100000000, 0x00000240000000)
10114 00:56:30.066367
10115 00:56:30.069582 Initializing XHCI USB controller at 0x11200000.
10116 00:56:31.108620
10117 00:56:31.111426 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10118 00:56:31.111519
10119 00:56:31.111610
10120 00:56:31.111911 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10122 00:56:31.212201 asurada: tftpboot 192.168.201.1 14368602/tftp-deploy-22_ggd8q/kernel/image.itb 14368602/tftp-deploy-22_ggd8q/kernel/cmdline
10123 00:56:31.212407 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10124 00:56:31.212513 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10125 00:56:31.216667 tftpboot 192.168.201.1 14368602/tftp-deploy-22_ggd8q/kernel/image.itp-deploy-22_ggd8q/kernel/cmdline
10126 00:56:31.216759
10127 00:56:31.216818 Waiting for link
10128 00:56:31.374488
10129 00:56:31.374614 R8152: Initializing
10130 00:56:31.374674
10131 00:56:31.377855 Version 6 (ocp_data = 5c30)
10132 00:56:31.377953
10133 00:56:31.381487 R8152: Done initializing
10134 00:56:31.381562
10135 00:56:31.381620 Adding net device
10136 00:56:33.287788
10137 00:56:33.287919 done.
10138 00:56:33.287979
10139 00:56:33.288035 MAC: 00:24:32:30:78:ff
10140 00:56:33.288088
10141 00:56:33.291490 Sending DHCP discover... done.
10142 00:56:33.291565
10143 00:56:37.259954 Waiting for reply... done.
10144 00:56:37.260100
10145 00:56:37.260176 Sending DHCP request... done.
10146 00:56:37.263531
10147 00:56:37.263599 Waiting for reply... done.
10148 00:56:37.263655
10149 00:56:37.266783 My ip is 192.168.201.21
10150 00:56:37.266861
10151 00:56:37.270445 The DHCP server ip is 192.168.201.1
10152 00:56:37.270539
10153 00:56:37.273395 TFTP server IP predefined by user: 192.168.201.1
10154 00:56:37.273485
10155 00:56:37.280013 Bootfile predefined by user: 14368602/tftp-deploy-22_ggd8q/kernel/image.itb
10156 00:56:37.280094
10157 00:56:37.283546 Sending tftp read request... done.
10158 00:56:37.283616
10159 00:56:37.287155 Waiting for the transfer...
10160 00:56:37.287261
10161 00:56:37.917106 00000000 ################################################################
10162 00:56:37.917331
10163 00:56:38.539574 00080000 ################################################################
10164 00:56:38.539703
10165 00:56:39.169409 00100000 ################################################################
10166 00:56:39.169567
10167 00:56:39.792511 00180000 ################################################################
10168 00:56:39.792671
10169 00:56:40.425647 00200000 ################################################################
10170 00:56:40.425764
10171 00:56:41.055421 00280000 ################################################################
10172 00:56:41.055560
10173 00:56:41.685230 00300000 ################################################################
10174 00:56:41.685346
10175 00:56:42.325553 00380000 ################################################################
10176 00:56:42.325670
10177 00:56:42.954224 00400000 ################################################################
10178 00:56:42.954353
10179 00:56:43.575017 00480000 ################################################################
10180 00:56:43.575158
10181 00:56:44.202055 00500000 ################################################################
10182 00:56:44.202177
10183 00:56:44.837076 00580000 ################################################################
10184 00:56:44.837196
10185 00:56:45.514241 00600000 ################################################################
10186 00:56:45.514378
10187 00:56:46.216729 00680000 ################################################################
10188 00:56:46.216844
10189 00:56:46.905900 00700000 ################################################################
10190 00:56:46.906018
10191 00:56:47.605050 00780000 ################################################################
10192 00:56:47.605174
10193 00:56:48.279272 00800000 ################################################################
10194 00:56:48.279411
10195 00:56:48.961575 00880000 ################################################################
10196 00:56:48.961720
10197 00:56:49.638468 00900000 ################################################################
10198 00:56:49.638618
10199 00:56:50.229870 00980000 ################################################################
10200 00:56:50.230014
10201 00:56:50.873945 00a00000 ################################################################
10202 00:56:50.874669
10203 00:56:51.612280 00a80000 ################################################################
10204 00:56:51.612754
10205 00:56:52.347785 00b00000 ################################################################
10206 00:56:52.348299
10207 00:56:53.084801 00b80000 ################################################################
10208 00:56:53.085278
10209 00:56:53.756091 00c00000 ################################################################
10210 00:56:53.756593
10211 00:56:54.516680 00c80000 ################################################################
10212 00:56:54.517178
10213 00:56:55.265001 00d00000 ################################################################
10214 00:56:55.265481
10215 00:56:55.999774 00d80000 ################################################################
10216 00:56:56.000228
10217 00:56:56.723749 00e00000 ################################################################
10218 00:56:56.724224
10219 00:56:57.417405 00e80000 ################################################################
10220 00:56:57.417547
10221 00:56:58.090993 00f00000 ################################################################
10222 00:56:58.091486
10223 00:56:58.795667 00f80000 ################################################################
10224 00:56:58.796138
10225 00:56:59.498156 01000000 ################################################################
10226 00:56:59.498366
10227 00:57:00.080088 01080000 ################################################################
10228 00:57:00.080217
10229 00:57:00.792756 01100000 ################################################################
10230 00:57:00.793352
10231 00:57:01.503545 01180000 ################################################################
10232 00:57:01.504153
10233 00:57:02.168789 01200000 ################################################################
10234 00:57:02.169254
10235 00:57:02.833462 01280000 ################################################################
10236 00:57:02.833615
10237 00:57:03.395706 01300000 ################################################################
10238 00:57:03.395846
10239 00:57:03.928854 01380000 ################################################################
10240 00:57:03.928991
10241 00:57:04.487310 01400000 ################################################################
10242 00:57:04.487459
10243 00:57:05.043130 01480000 ################################################################
10244 00:57:05.043253
10245 00:57:05.661318 01500000 ################################################################
10246 00:57:05.661845
10247 00:57:06.269074 01580000 ################################################################
10248 00:57:06.269201
10249 00:57:06.799966 01600000 ################################################################
10250 00:57:06.800083
10251 00:57:07.348309 01680000 ################################################################
10252 00:57:07.348466
10253 00:57:07.996723 01700000 ################################################################
10254 00:57:07.997191
10255 00:57:08.688625 01780000 ################################################################
10256 00:57:08.689269
10257 00:57:09.407658 01800000 ################################################################
10258 00:57:09.408177
10259 00:57:10.098651 01880000 ################################################################
10260 00:57:10.099153
10261 00:57:10.821659 01900000 ################################################################
10262 00:57:10.822169
10263 00:57:11.508758 01980000 ################################################################
10264 00:57:11.509231
10265 00:57:12.171323 01a00000 ################################################################
10266 00:57:12.171785
10267 00:57:12.886056 01a80000 ################################################################
10268 00:57:12.886499
10269 00:57:13.598101 01b00000 ################################################################
10270 00:57:13.598571
10271 00:57:14.234621 01b80000 ################################################################
10272 00:57:14.234751
10273 00:57:14.817090 01c00000 ################################################################
10274 00:57:14.817218
10275 00:57:15.471271 01c80000 ################################################################
10276 00:57:15.471402
10277 00:57:16.084667 01d00000 ################################################################
10278 00:57:16.085177
10279 00:57:16.718143 01d80000 ################################################################
10280 00:57:16.718274
10281 00:57:17.216253 01e00000 ######################################################## done.
10282 00:57:17.216377
10283 00:57:17.219235 The bootfile was 31909326 bytes long.
10284 00:57:17.219313
10285 00:57:17.222907 Sending tftp read request... done.
10286 00:57:17.222984
10287 00:57:17.226398 Waiting for the transfer...
10288 00:57:17.226479
10289 00:57:17.226537 00000000 # done.
10290 00:57:17.226594
10291 00:57:17.236396 Command line loaded dynamically from TFTP file: 14368602/tftp-deploy-22_ggd8q/kernel/cmdline
10292 00:57:17.236484
10293 00:57:17.256051 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368602/extract-nfsrootfs-0wliq_c2,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10294 00:57:17.256179
10295 00:57:17.259170 Loading FIT.
10296 00:57:17.259317
10297 00:57:17.262664 Image ramdisk-1 has 18734994 bytes.
10298 00:57:17.262790
10299 00:57:17.262889 Image fdt-1 has 47258 bytes.
10300 00:57:17.266093
10301 00:57:17.266160 Image kernel-1 has 13125045 bytes.
10302 00:57:17.266215
10303 00:57:17.276230 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10304 00:57:17.276319
10305 00:57:17.292567 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10306 00:57:17.296066
10307 00:57:17.299419 Choosing best match conf-1 for compat google,spherion-rev2.
10308 00:57:17.303725
10309 00:57:17.308291 Connected to device vid:did:rid of 1ae0:0028:00
10310 00:57:17.316568
10311 00:57:17.319476 tpm_get_response: command 0x17b, return code 0x0
10312 00:57:17.319711
10313 00:57:17.322871 ec_init: CrosEC protocol v3 supported (256, 248)
10314 00:57:17.326532
10315 00:57:17.329593 tpm_cleanup: add release locality here.
10316 00:57:17.329963
10317 00:57:17.333296 Shutting down all USB controllers.
10318 00:57:17.333684
10319 00:57:17.336220 Removing current net device
10320 00:57:17.336699
10321 00:57:17.339663 Exiting depthcharge with code 4 at timestamp: 79631935
10322 00:57:17.340061
10323 00:57:17.343225 LZMA decompressing kernel-1 to 0x821a6718
10324 00:57:17.346063
10325 00:57:17.349575 LZMA decompressing kernel-1 to 0x40000000
10326 00:57:18.965277
10327 00:57:18.965753 jumping to kernel
10328 00:57:18.967395 end: 2.2.4 bootloader-commands (duration 00:00:52) [common]
10329 00:57:18.967859 start: 2.2.5 auto-login-action (timeout 00:03:35) [common]
10330 00:57:18.968205 Setting prompt string to ['Linux version [0-9]']
10331 00:57:18.968526 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10332 00:57:18.968946 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10333 00:57:19.047185
10334 00:57:19.050581 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10335 00:57:19.053976 start: 2.2.5.1 login-action (timeout 00:03:35) [common]
10336 00:57:19.054445 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10337 00:57:19.054787 Setting prompt string to []
10338 00:57:19.055157 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10339 00:57:19.055490 Using line separator: #'\n'#
10340 00:57:19.055773 No login prompt set.
10341 00:57:19.056068 Parsing kernel messages
10342 00:57:19.056326 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10343 00:57:19.056887 [login-action] Waiting for messages, (timeout 00:03:35)
10344 00:57:19.057219 Waiting using forced prompt support (timeout 00:01:47)
10345 00:57:19.073410 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
10346 00:57:19.076881 [ 0.000000] random: crng init done
10347 00:57:19.083294 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10348 00:57:19.086792 [ 0.000000] efi: UEFI not found.
10349 00:57:19.093107 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10350 00:57:19.099887 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10351 00:57:19.109405 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10352 00:57:19.119784 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10353 00:57:19.126131 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10354 00:57:19.132769 [ 0.000000] printk: bootconsole [mtk8250] enabled
10355 00:57:19.139209 [ 0.000000] NUMA: No NUMA configuration found
10356 00:57:19.145895 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10357 00:57:19.149421 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10358 00:57:19.152370 [ 0.000000] Zone ranges:
10359 00:57:19.159308 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10360 00:57:19.162145 [ 0.000000] DMA32 empty
10361 00:57:19.169173 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10362 00:57:19.172326 [ 0.000000] Movable zone start for each node
10363 00:57:19.175733 [ 0.000000] Early memory node ranges
10364 00:57:19.182244 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10365 00:57:19.188843 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10366 00:57:19.195401 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10367 00:57:19.202546 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10368 00:57:19.208795 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10369 00:57:19.214938 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10370 00:57:19.271169 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10371 00:57:19.277969 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10372 00:57:19.284279 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10373 00:57:19.287846 [ 0.000000] psci: probing for conduit method from DT.
10374 00:57:19.294544 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10375 00:57:19.298123 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10376 00:57:19.303755 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10377 00:57:19.307330 [ 0.000000] psci: SMC Calling Convention v1.2
10378 00:57:19.314393 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10379 00:57:19.317077 [ 0.000000] Detected VIPT I-cache on CPU0
10380 00:57:19.323791 [ 0.000000] CPU features: detected: GIC system register CPU interface
10381 00:57:19.330121 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10382 00:57:19.337150 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10383 00:57:19.343445 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10384 00:57:19.353545 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10385 00:57:19.360207 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10386 00:57:19.363552 [ 0.000000] alternatives: applying boot alternatives
10387 00:57:19.370104 [ 0.000000] Fallback order for Node 0: 0
10388 00:57:19.376827 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10389 00:57:19.380187 [ 0.000000] Policy zone: Normal
10390 00:57:19.402880 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368602/extract-nfsrootfs-0wliq_c2,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10391 00:57:19.412802 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10392 00:57:19.424514 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10393 00:57:19.434521 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10394 00:57:19.440957 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10395 00:57:19.444595 <6>[ 0.000000] software IO TLB: area num 8.
10396 00:57:19.501046 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10397 00:57:19.650870 <6>[ 0.000000] Memory: 7945764K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407004K reserved, 32768K cma-reserved)
10398 00:57:19.656894 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10399 00:57:19.663932 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10400 00:57:19.666805 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10401 00:57:19.673842 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10402 00:57:19.680253 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10403 00:57:19.683457 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10404 00:57:19.693374 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10405 00:57:19.700575 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10406 00:57:19.706456 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10407 00:57:19.713901 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10408 00:57:19.716787 <6>[ 0.000000] GICv3: 608 SPIs implemented
10409 00:57:19.719746 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10410 00:57:19.726574 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10411 00:57:19.729835 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10412 00:57:19.736944 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10413 00:57:19.749775 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10414 00:57:19.759464 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10415 00:57:19.769756 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10416 00:57:19.777401 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10417 00:57:19.790276 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10418 00:57:19.797088 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10419 00:57:19.803616 <6>[ 0.009181] Console: colour dummy device 80x25
10420 00:57:19.813580 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10421 00:57:19.817142 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10422 00:57:19.823347 <6>[ 0.029223] LSM: Security Framework initializing
10423 00:57:19.829924 <6>[ 0.034191] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10424 00:57:19.839876 <6>[ 0.042005] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10425 00:57:19.846931 <6>[ 0.051411] cblist_init_generic: Setting adjustable number of callback queues.
10426 00:57:19.853226 <6>[ 0.058855] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 00:57:19.863406 <6>[ 0.065193] cblist_init_generic: Setting adjustable number of callback queues.
10428 00:57:19.866758 <6>[ 0.072620] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 00:57:19.873682 <6>[ 0.079020] rcu: Hierarchical SRCU implementation.
10430 00:57:19.879840 <6>[ 0.084036] rcu: Max phase no-delay instances is 1000.
10431 00:57:19.886261 <6>[ 0.091073] EFI services will not be available.
10432 00:57:19.889424 <6>[ 0.096059] smp: Bringing up secondary CPUs ...
10433 00:57:19.897929 <6>[ 0.101110] Detected VIPT I-cache on CPU1
10434 00:57:19.904286 <6>[ 0.101183] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10435 00:57:19.910871 <6>[ 0.101214] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10436 00:57:19.914159 <6>[ 0.101546] Detected VIPT I-cache on CPU2
10437 00:57:19.921231 <6>[ 0.101597] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10438 00:57:19.930660 <6>[ 0.101615] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10439 00:57:19.934191 <6>[ 0.101870] Detected VIPT I-cache on CPU3
10440 00:57:19.940879 <6>[ 0.101916] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10441 00:57:19.947724 <6>[ 0.101930] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10442 00:57:19.950643 <6>[ 0.102216] CPU features: detected: Spectre-v4
10443 00:57:19.957149 <6>[ 0.102221] CPU features: detected: Spectre-BHB
10444 00:57:19.960754 <6>[ 0.102226] Detected PIPT I-cache on CPU4
10445 00:57:19.967082 <6>[ 0.102277] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10446 00:57:19.973675 <6>[ 0.102292] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10447 00:57:19.980605 <6>[ 0.102573] Detected PIPT I-cache on CPU5
10448 00:57:19.986760 <6>[ 0.102638] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10449 00:57:19.993943 <6>[ 0.102655] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10450 00:57:19.996882 <6>[ 0.102935] Detected PIPT I-cache on CPU6
10451 00:57:20.003659 <6>[ 0.103001] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10452 00:57:20.010373 <6>[ 0.103017] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10453 00:57:20.016508 <6>[ 0.103313] Detected PIPT I-cache on CPU7
10454 00:57:20.023481 <6>[ 0.103379] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10455 00:57:20.030077 <6>[ 0.103395] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10456 00:57:20.033314 <6>[ 0.103443] smp: Brought up 1 node, 8 CPUs
10457 00:57:20.039853 <6>[ 0.244732] SMP: Total of 8 processors activated.
10458 00:57:20.043149 <6>[ 0.249654] CPU features: detected: 32-bit EL0 Support
10459 00:57:20.053256 <6>[ 0.255050] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10460 00:57:20.060469 <6>[ 0.263850] CPU features: detected: Common not Private translations
10461 00:57:20.063794 <6>[ 0.270326] CPU features: detected: CRC32 instructions
10462 00:57:20.070046 <6>[ 0.275677] CPU features: detected: RCpc load-acquire (LDAPR)
10463 00:57:20.076380 <6>[ 0.281637] CPU features: detected: LSE atomic instructions
10464 00:57:20.083133 <6>[ 0.287419] CPU features: detected: Privileged Access Never
10465 00:57:20.089446 <6>[ 0.293199] CPU features: detected: RAS Extension Support
10466 00:57:20.096423 <6>[ 0.298807] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10467 00:57:20.100013 <6>[ 0.306024] CPU: All CPU(s) started at EL2
10468 00:57:20.106400 <6>[ 0.310341] alternatives: applying system-wide alternatives
10469 00:57:20.115681 <6>[ 0.321230] devtmpfs: initialized
10470 00:57:20.127540 <6>[ 0.330015] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10471 00:57:20.137287 <6>[ 0.339978] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10472 00:57:20.144192 <6>[ 0.347991] pinctrl core: initialized pinctrl subsystem
10473 00:57:20.147096 <6>[ 0.354655] DMI not present or invalid.
10474 00:57:20.153864 <6>[ 0.359063] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10475 00:57:20.164214 <6>[ 0.365912] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10476 00:57:20.170619 <6>[ 0.373503] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10477 00:57:20.180705 <6>[ 0.381723] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10478 00:57:20.183987 <6>[ 0.389965] audit: initializing netlink subsys (disabled)
10479 00:57:20.193487 <5>[ 0.395660] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10480 00:57:20.200460 <6>[ 0.396370] thermal_sys: Registered thermal governor 'step_wise'
10481 00:57:20.207180 <6>[ 0.403624] thermal_sys: Registered thermal governor 'power_allocator'
10482 00:57:20.210573 <6>[ 0.409881] cpuidle: using governor menu
10483 00:57:20.216684 <6>[ 0.420833] NET: Registered PF_QIPCRTR protocol family
10484 00:57:20.223346 <6>[ 0.426318] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10485 00:57:20.229983 <6>[ 0.433421] ASID allocator initialised with 32768 entries
10486 00:57:20.233281 <6>[ 0.439998] Serial: AMBA PL011 UART driver
10487 00:57:20.242838 <4>[ 0.448824] Trying to register duplicate clock ID: 134
10488 00:57:20.301202 <6>[ 0.510212] KASLR enabled
10489 00:57:20.315506 <6>[ 0.517833] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10490 00:57:20.322173 <6>[ 0.524846] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10491 00:57:20.328806 <6>[ 0.531336] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10492 00:57:20.335412 <6>[ 0.538339] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10493 00:57:20.341887 <6>[ 0.544827] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10494 00:57:20.348560 <6>[ 0.551831] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10495 00:57:20.354917 <6>[ 0.558318] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10496 00:57:20.362045 <6>[ 0.565325] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10497 00:57:20.364747 <6>[ 0.572787] ACPI: Interpreter disabled.
10498 00:57:20.373416 <6>[ 0.579237] iommu: Default domain type: Translated
10499 00:57:20.380539 <6>[ 0.584350] iommu: DMA domain TLB invalidation policy: strict mode
10500 00:57:20.383474 <5>[ 0.591008] SCSI subsystem initialized
10501 00:57:20.389849 <6>[ 0.595255] usbcore: registered new interface driver usbfs
10502 00:57:20.396770 <6>[ 0.600985] usbcore: registered new interface driver hub
10503 00:57:20.399611 <6>[ 0.606535] usbcore: registered new device driver usb
10504 00:57:20.406741 <6>[ 0.612652] pps_core: LinuxPPS API ver. 1 registered
10505 00:57:20.416708 <6>[ 0.617845] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10506 00:57:20.420171 <6>[ 0.627185] PTP clock support registered
10507 00:57:20.423255 <6>[ 0.631426] EDAC MC: Ver: 3.0.0
10508 00:57:20.430602 <6>[ 0.636599] FPGA manager framework
10509 00:57:20.434463 <6>[ 0.640274] Advanced Linux Sound Architecture Driver Initialized.
10510 00:57:20.437771 <6>[ 0.647047] vgaarb: loaded
10511 00:57:20.444619 <6>[ 0.650201] clocksource: Switched to clocksource arch_sys_counter
10512 00:57:20.451515 <5>[ 0.656644] VFS: Disk quotas dquot_6.6.0
10513 00:57:20.457792 <6>[ 0.660834] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10514 00:57:20.461045 <6>[ 0.668023] pnp: PnP ACPI: disabled
10515 00:57:20.468971 <6>[ 0.674686] NET: Registered PF_INET protocol family
10516 00:57:20.478559 <6>[ 0.680276] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10517 00:57:20.490008 <6>[ 0.692611] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10518 00:57:20.500181 <6>[ 0.701424] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10519 00:57:20.506965 <6>[ 0.709393] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10520 00:57:20.513397 <6>[ 0.718094] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10521 00:57:20.525173 <6>[ 0.727843] TCP: Hash tables configured (established 65536 bind 65536)
10522 00:57:20.532365 <6>[ 0.734715] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10523 00:57:20.538887 <6>[ 0.741915] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10524 00:57:20.545043 <6>[ 0.749622] NET: Registered PF_UNIX/PF_LOCAL protocol family
10525 00:57:20.552270 <6>[ 0.755722] RPC: Registered named UNIX socket transport module.
10526 00:57:20.554990 <6>[ 0.761875] RPC: Registered udp transport module.
10527 00:57:20.561893 <6>[ 0.766808] RPC: Registered tcp transport module.
10528 00:57:20.568007 <6>[ 0.771740] RPC: Registered tcp NFSv4.1 backchannel transport module.
10529 00:57:20.571437 <6>[ 0.778408] PCI: CLS 0 bytes, default 64
10530 00:57:20.575181 <6>[ 0.782737] Unpacking initramfs...
10531 00:57:20.592392 <6>[ 0.794697] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10532 00:57:20.602083 <6>[ 0.803342] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10533 00:57:20.605125 <6>[ 0.812162] kvm [1]: IPA Size Limit: 40 bits
10534 00:57:20.611816 <6>[ 0.816688] kvm [1]: GICv3: no GICV resource entry
10535 00:57:20.615210 <6>[ 0.821710] kvm [1]: disabling GICv2 emulation
10536 00:57:20.621686 <6>[ 0.826394] kvm [1]: GIC system register CPU interface enabled
10537 00:57:20.626038 <6>[ 0.832555] kvm [1]: vgic interrupt IRQ18
10538 00:57:20.631876 <6>[ 0.836909] kvm [1]: VHE mode initialized successfully
10539 00:57:20.638211 <5>[ 0.843396] Initialise system trusted keyrings
10540 00:57:20.645282 <6>[ 0.848204] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10541 00:57:20.652555 <6>[ 0.858178] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10542 00:57:20.659061 <5>[ 0.864571] NFS: Registering the id_resolver key type
10543 00:57:20.662595 <5>[ 0.869873] Key type id_resolver registered
10544 00:57:20.669148 <5>[ 0.874287] Key type id_legacy registered
10545 00:57:20.675420 <6>[ 0.878564] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10546 00:57:20.682362 <6>[ 0.885486] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10547 00:57:20.688511 <6>[ 0.893183] 9p: Installing v9fs 9p2000 file system support
10548 00:57:20.724641 <5>[ 0.930463] Key type asymmetric registered
10549 00:57:20.728192 <5>[ 0.934792] Asymmetric key parser 'x509' registered
10550 00:57:20.737635 <6>[ 0.939920] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10551 00:57:20.741194 <6>[ 0.947533] io scheduler mq-deadline registered
10552 00:57:20.744974 <6>[ 0.952293] io scheduler kyber registered
10553 00:57:20.763519 <6>[ 0.969164] EINJ: ACPI disabled.
10554 00:57:20.796328 <4>[ 0.995197] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10555 00:57:20.805830 <4>[ 1.005825] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 00:57:20.820963 <6>[ 1.026684] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10557 00:57:20.828539 <6>[ 1.034607] printk: console [ttyS0] disabled
10558 00:57:20.857078 <6>[ 1.059231] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10559 00:57:20.863593 <6>[ 1.068706] printk: console [ttyS0] enabled
10560 00:57:20.866561 <6>[ 1.068706] printk: console [ttyS0] enabled
10561 00:57:20.873434 <6>[ 1.077602] printk: bootconsole [mtk8250] disabled
10562 00:57:20.876354 <6>[ 1.077602] printk: bootconsole [mtk8250] disabled
10563 00:57:20.883484 <6>[ 1.088636] SuperH (H)SCI(F) driver initialized
10564 00:57:20.886419 <6>[ 1.093898] msm_serial: driver initialized
10565 00:57:20.900748 <6>[ 1.102793] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10566 00:57:20.910521 <6>[ 1.111336] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10567 00:57:20.917339 <6>[ 1.119878] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10568 00:57:20.926699 <6>[ 1.128505] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10569 00:57:20.936607 <6>[ 1.137210] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10570 00:57:20.943026 <6>[ 1.145929] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10571 00:57:20.952982 <6>[ 1.154469] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10572 00:57:20.959923 <6>[ 1.163262] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10573 00:57:20.969249 <6>[ 1.171803] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10574 00:57:20.981660 <6>[ 1.187242] loop: module loaded
10575 00:57:20.987919 <6>[ 1.192955] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10576 00:57:21.010307 <4>[ 1.216118] mtk-pmic-keys: Failed to locate of_node [id: -1]
10577 00:57:21.016857 <6>[ 1.222932] megasas: 07.719.03.00-rc1
10578 00:57:21.026793 <6>[ 1.232714] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10579 00:57:21.039978 <6>[ 1.245594] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10580 00:57:21.056466 <6>[ 1.262294] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10581 00:57:21.113058 <6>[ 1.312149] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10582 00:57:21.361732 <6>[ 1.567651] Freeing initrd memory: 18292K
10583 00:57:21.373163 <6>[ 1.579328] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10584 00:57:21.384125 <6>[ 1.590224] tun: Universal TUN/TAP device driver, 1.6
10585 00:57:21.387702 <6>[ 1.596276] thunder_xcv, ver 1.0
10586 00:57:21.390995 <6>[ 1.599785] thunder_bgx, ver 1.0
10587 00:57:21.394334 <6>[ 1.603282] nicpf, ver 1.0
10588 00:57:21.404817 <6>[ 1.607285] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10589 00:57:21.408306 <6>[ 1.614760] hns3: Copyright (c) 2017 Huawei Corporation.
10590 00:57:21.411254 <6>[ 1.620345] hclge is initializing
10591 00:57:21.418197 <6>[ 1.623924] e1000: Intel(R) PRO/1000 Network Driver
10592 00:57:21.424471 <6>[ 1.629054] e1000: Copyright (c) 1999-2006 Intel Corporation.
10593 00:57:21.428127 <6>[ 1.635066] e1000e: Intel(R) PRO/1000 Network Driver
10594 00:57:21.434348 <6>[ 1.640281] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10595 00:57:21.441152 <6>[ 1.646464] igb: Intel(R) Gigabit Ethernet Network Driver
10596 00:57:21.448131 <6>[ 1.652115] igb: Copyright (c) 2007-2014 Intel Corporation.
10597 00:57:21.454961 <6>[ 1.657954] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10598 00:57:21.461446 <6>[ 1.664472] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10599 00:57:21.464883 <6>[ 1.670926] sky2: driver version 1.30
10600 00:57:21.471218 <6>[ 1.675864] usbcore: registered new device driver r8152-cfgselector
10601 00:57:21.478067 <6>[ 1.682399] usbcore: registered new interface driver r8152
10602 00:57:21.481613 <6>[ 1.688208] VFIO - User Level meta-driver version: 0.3
10603 00:57:21.490795 <6>[ 1.696423] usbcore: registered new interface driver usb-storage
10604 00:57:21.497272 <6>[ 1.702861] usbcore: registered new device driver onboard-usb-hub
10605 00:57:21.506026 <6>[ 1.711969] mt6397-rtc mt6359-rtc: registered as rtc0
10606 00:57:21.515926 <6>[ 1.717434] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:57:21 UTC (1718499441)
10607 00:57:21.519338 <6>[ 1.726992] i2c_dev: i2c /dev entries driver
10608 00:57:21.532876 <4>[ 1.738918] cpu cpu0: supply cpu not found, using dummy regulator
10609 00:57:21.539268 <4>[ 1.745333] cpu cpu1: supply cpu not found, using dummy regulator
10610 00:57:21.546102 <4>[ 1.751739] cpu cpu2: supply cpu not found, using dummy regulator
10611 00:57:21.552756 <4>[ 1.758153] cpu cpu3: supply cpu not found, using dummy regulator
10612 00:57:21.559182 <4>[ 1.764552] cpu cpu4: supply cpu not found, using dummy regulator
10613 00:57:21.566289 <4>[ 1.770952] cpu cpu5: supply cpu not found, using dummy regulator
10614 00:57:21.572919 <4>[ 1.777352] cpu cpu6: supply cpu not found, using dummy regulator
10615 00:57:21.579139 <4>[ 1.783747] cpu cpu7: supply cpu not found, using dummy regulator
10616 00:57:21.598021 <6>[ 1.804406] cpu cpu0: EM: created perf domain
10617 00:57:21.601550 <6>[ 1.809327] cpu cpu4: EM: created perf domain
10618 00:57:21.608782 <6>[ 1.814925] sdhci: Secure Digital Host Controller Interface driver
10619 00:57:21.615155 <6>[ 1.821356] sdhci: Copyright(c) Pierre Ossman
10620 00:57:21.622147 <6>[ 1.826302] Synopsys Designware Multimedia Card Interface Driver
10621 00:57:21.628600 <6>[ 1.832952] sdhci-pltfm: SDHCI platform and OF driver helper
10622 00:57:21.632000 <6>[ 1.833025] mmc0: CQHCI version 5.10
10623 00:57:21.638875 <6>[ 1.842990] ledtrig-cpu: registered to indicate activity on CPUs
10624 00:57:21.645154 <6>[ 1.850027] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10625 00:57:21.652200 <6>[ 1.857085] usbcore: registered new interface driver usbhid
10626 00:57:21.655143 <6>[ 1.862907] usbhid: USB HID core driver
10627 00:57:21.662146 <6>[ 1.867103] spi_master spi0: will run message pump with realtime priority
10628 00:57:21.709100 <6>[ 1.908839] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10629 00:57:21.729099 <6>[ 1.925223] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10630 00:57:21.732590 <6>[ 1.938908] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16014
10631 00:57:21.739486 <6>[ 1.939929] cros-ec-spi spi0.0: Chrome EC device registered
10632 00:57:21.745812 <6>[ 1.950985] mmc0: Command Queue Engine enabled
10633 00:57:21.752499 <6>[ 1.955736] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10634 00:57:21.759531 <6>[ 1.962821] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10635 00:57:21.765998 <6>[ 1.962980] mmcblk0: mmc0:0001 DA4128 116 GiB
10636 00:57:21.772341 <6>[ 1.973045] NET: Registered PF_PACKET protocol family
10637 00:57:21.775866 <6>[ 1.982214] 9pnet: Installing 9P2000 support
10638 00:57:21.782385 <6>[ 1.984946] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10639 00:57:21.785551 <5>[ 1.986787] Key type dns_resolver registered
10640 00:57:21.792329 <6>[ 1.994103] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10641 00:57:21.795852 <6>[ 1.997450] registered taskstats version 1
10642 00:57:21.799006 <6>[ 2.003050] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10643 00:57:21.805935 <5>[ 2.006759] Loading compiled-in X.509 certificates
10644 00:57:21.812351 <6>[ 2.012588] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10645 00:57:21.833283 <4>[ 2.033120] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10646 00:57:21.843573 <4>[ 2.043824] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10647 00:57:21.857198 <6>[ 2.063406] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10648 00:57:21.864172 <6>[ 2.070217] xhci-mtk 11200000.usb: xHCI Host Controller
10649 00:57:21.870738 <6>[ 2.075743] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10650 00:57:21.880385 <6>[ 2.083597] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10651 00:57:21.887453 <6>[ 2.093034] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10652 00:57:21.893948 <6>[ 2.099203] xhci-mtk 11200000.usb: xHCI Host Controller
10653 00:57:21.900513 <6>[ 2.104695] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10654 00:57:21.907468 <6>[ 2.112362] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10655 00:57:21.914271 <6>[ 2.120200] hub 1-0:1.0: USB hub found
10656 00:57:21.917401 <6>[ 2.124241] hub 1-0:1.0: 1 port detected
10657 00:57:21.924115 <6>[ 2.128550] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10658 00:57:21.930925 <6>[ 2.137387] hub 2-0:1.0: USB hub found
10659 00:57:21.934230 <6>[ 2.141415] hub 2-0:1.0: 1 port detected
10660 00:57:21.942197 <6>[ 2.148777] mtk-msdc 11f70000.mmc: Got CD GPIO
10661 00:57:21.955098 <6>[ 2.157673] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10662 00:57:21.965197 <6>[ 2.166098] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10663 00:57:21.971649 <6>[ 2.174453] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10664 00:57:21.981517 <6>[ 2.182793] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10665 00:57:21.988446 <6>[ 2.191132] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10666 00:57:21.998861 <6>[ 2.199470] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10667 00:57:22.005449 <6>[ 2.207808] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10668 00:57:22.014911 <6>[ 2.216146] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10669 00:57:22.021317 <6>[ 2.224485] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10670 00:57:22.031773 <6>[ 2.232823] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10671 00:57:22.038293 <6>[ 2.241161] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10672 00:57:22.048524 <6>[ 2.249498] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10673 00:57:22.054418 <6>[ 2.257836] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10674 00:57:22.064374 <6>[ 2.266173] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10675 00:57:22.071321 <6>[ 2.274511] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10676 00:57:22.077759 <6>[ 2.283240] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10677 00:57:22.084587 <6>[ 2.290458] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10678 00:57:22.091250 <6>[ 2.297269] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10679 00:57:22.101553 <6>[ 2.304039] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10680 00:57:22.107956 <6>[ 2.311005] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10681 00:57:22.114692 <6>[ 2.317856] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10682 00:57:22.124936 <6>[ 2.326988] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10683 00:57:22.134828 <6>[ 2.336111] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10684 00:57:22.144347 <6>[ 2.345405] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10685 00:57:22.154717 <6>[ 2.354871] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10686 00:57:22.160796 <6>[ 2.364338] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10687 00:57:22.171220 <6>[ 2.373457] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10688 00:57:22.180991 <6>[ 2.382923] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10689 00:57:22.191069 <6>[ 2.392050] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10690 00:57:22.200544 <6>[ 2.401344] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10691 00:57:22.210540 <6>[ 2.411505] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10692 00:57:22.220309 <6>[ 2.423176] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10693 00:57:22.227872 <6>[ 2.433924] Trying to probe devices needed for running init ...
10694 00:57:22.238806 <3>[ 2.441192] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10695 00:57:22.324478 <6>[ 2.526847] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10696 00:57:22.352461 <6>[ 2.558359] hub 2-1:1.0: USB hub found
10697 00:57:22.355875 <6>[ 2.562868] hub 2-1:1.0: 3 ports detected
10698 00:57:22.366337 <6>[ 2.572602] hub 2-1:1.0: USB hub found
10699 00:57:22.369715 <6>[ 2.577062] hub 2-1:1.0: 3 ports detected
10700 00:57:22.476157 <6>[ 2.678496] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10701 00:57:22.634170 <6>[ 2.840498] hub 1-1:1.0: USB hub found
10702 00:57:22.637532 <6>[ 2.845008] hub 1-1:1.0: 4 ports detected
10703 00:57:22.650731 <6>[ 2.856666] hub 1-1:1.0: USB hub found
10704 00:57:22.653648 <6>[ 2.861049] hub 1-1:1.0: 4 ports detected
10705 00:57:22.712386 <6>[ 2.914749] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10706 00:57:22.820567 <6>[ 3.023197] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10707 00:57:22.857664 <4>[ 3.059948] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10708 00:57:22.867320 <4>[ 3.069112] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10709 00:57:22.905656 <6>[ 3.111818] r8152 2-1.3:1.0 eth0: v1.12.13
10710 00:57:22.979887 <6>[ 3.182526] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10711 00:57:23.112627 <6>[ 3.318638] hub 1-1.4:1.0: USB hub found
10712 00:57:23.115785 <6>[ 3.323324] hub 1-1.4:1.0: 2 ports detected
10713 00:57:23.130813 <6>[ 3.337013] hub 1-1.4:1.0: USB hub found
10714 00:57:23.134129 <6>[ 3.341656] hub 1-1.4:1.0: 2 ports detected
10715 00:57:23.431521 <6>[ 3.634525] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10716 00:57:23.628089 <6>[ 3.830573] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10717 00:57:24.635831 <6>[ 4.842445] r8152 2-1.3:1.0 eth0: carrier on
10718 00:57:27.335508 <5>[ 4.870269] Sending DHCP requests .., OK
10719 00:57:27.341716 <6>[ 7.546687] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10720 00:57:27.345173 <6>[ 7.554985] IP-Config: Complete:
10721 00:57:27.358338 <6>[ 7.558491] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10722 00:57:27.365307 <6>[ 7.569247] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10723 00:57:27.372042 <6>[ 7.577874] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10724 00:57:27.378174 <6>[ 7.577885] nameserver0=192.168.201.1
10725 00:57:27.381679 <6>[ 7.590037] clk: Disabling unused clocks
10726 00:57:27.385220 <6>[ 7.595645] ALSA device list:
10727 00:57:27.391657 <6>[ 7.598911] No soundcards found.
10728 00:57:27.399337 <6>[ 7.606412] Freeing unused kernel memory: 8512K
10729 00:57:27.402834 <6>[ 7.611308] Run /init as init process
10730 00:57:27.411748 Loading, please wait...
10731 00:57:27.441155 Starting systemd-udevd version 252.22-1~deb12u1
10732 00:57:27.708351 <6>[ 7.912093] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10733 00:57:27.721256 <6>[ 7.924723] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10734 00:57:27.727455 <6>[ 7.927608] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10735 00:57:27.737781 <6>[ 7.932791] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10736 00:57:27.740752 <6>[ 7.937595] remoteproc remoteproc0: scp is available
10737 00:57:27.747445 <6>[ 7.937667] remoteproc remoteproc0: powering up scp
10738 00:57:27.757725 <6>[ 7.937673] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10739 00:57:27.761241 <6>[ 7.937702] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10740 00:57:27.770988 <6>[ 7.950146] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10741 00:57:27.777387 <6>[ 7.954402] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10742 00:57:27.787629 <6>[ 7.959702] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10743 00:57:27.790861 <6>[ 7.960004] mc: Linux media interface: v0.10
10744 00:57:27.819378 <6>[ 7.995653] videodev: Linux video capture interface: v2.00
10745 00:57:27.819497 <3>[ 7.998899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 00:57:27.819560 <4>[ 7.999085] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10747 00:57:27.820790 <6>[ 7.999586] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10748 00:57:27.830633 <6>[ 7.999589] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10749 00:57:27.836949 <6>[ 8.004062] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10750 00:57:27.843780 <4>[ 8.004137] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10751 00:57:27.853705 <4>[ 8.004255] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10752 00:57:27.860133 <3>[ 8.008825] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 00:57:27.870081 <3>[ 8.008830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 00:57:27.876917 <6>[ 8.011069] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10755 00:57:27.883115 <6>[ 8.017078] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10756 00:57:27.893322 <3>[ 8.037352] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 00:57:27.900034 <6>[ 8.042307] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10758 00:57:27.909430 <3>[ 8.050211] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 00:57:27.916276 <6>[ 8.057574] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10760 00:57:27.922816 <6>[ 8.062965] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10761 00:57:27.933182 <3>[ 8.064644] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 00:57:27.939629 <6>[ 8.072787] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10763 00:57:27.949277 <3>[ 8.080812] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 00:57:27.955830 <6>[ 8.088480] remoteproc remoteproc0: remote processor scp is now up
10765 00:57:27.962601 <6>[ 8.089681] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10766 00:57:27.972394 <6>[ 8.092004] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10767 00:57:27.979266 <6>[ 8.095535] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10768 00:57:27.985805 <6>[ 8.095541] pci_bus 0000:00: root bus resource [bus 00-ff]
10769 00:57:27.992739 <6>[ 8.095548] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10770 00:57:28.002257 <6>[ 8.095553] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10771 00:57:28.009843 <6>[ 8.095587] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10772 00:57:28.016259 <6>[ 8.095606] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10773 00:57:28.019690 <6>[ 8.095687] pci 0000:00:00.0: supports D1 D2
10774 00:57:28.026359 <6>[ 8.095691] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10775 00:57:28.036594 <3>[ 8.096315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 00:57:28.042949 <6>[ 8.097242] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10777 00:57:28.050338 <6>[ 8.097348] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10778 00:57:28.056776 <6>[ 8.097378] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10779 00:57:28.063670 <6>[ 8.097398] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10780 00:57:28.073499 <6>[ 8.097416] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10781 00:57:28.076832 <6>[ 8.097529] pci 0000:01:00.0: supports D1 D2
10782 00:57:28.083163 <6>[ 8.097532] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10783 00:57:28.090143 <6>[ 8.106270] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10784 00:57:28.099953 <3>[ 8.112196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10785 00:57:28.106747 <3>[ 8.112240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10786 00:57:28.113095 <6>[ 8.120333] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10787 00:57:28.122865 <3>[ 8.129403] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10788 00:57:28.129719 <3>[ 8.129406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 00:57:28.139826 <3>[ 8.129442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 00:57:28.146083 <6>[ 8.136467] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10791 00:57:28.156389 <3>[ 8.144530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 00:57:28.163123 <3>[ 8.144532] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 00:57:28.172867 <3>[ 8.144535] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 00:57:28.179122 <3>[ 8.144537] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10795 00:57:28.186101 <3>[ 8.144550] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 00:57:28.195775 <6>[ 8.176177] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10797 00:57:28.205834 <6>[ 8.184378] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10798 00:57:28.215456 <6>[ 8.185864] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10799 00:57:28.222035 <6>[ 8.186445] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10800 00:57:28.232212 <4>[ 8.193709] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10801 00:57:28.238553 <4>[ 8.193709] Fallback method does not support PEC.
10802 00:57:28.245231 <6>[ 8.197667] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10803 00:57:28.248535 <6>[ 8.220938] Bluetooth: Core ver 2.22
10804 00:57:28.258231 <3>[ 8.223798] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10805 00:57:28.265097 <6>[ 8.227646] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10806 00:57:28.271745 <6>[ 8.227666] pci 0000:00:00.0: PCI bridge to [bus 01]
10807 00:57:28.274787 <6>[ 8.232472] NET: Registered PF_BLUETOOTH protocol family
10808 00:57:28.284904 <6>[ 8.232730] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10809 00:57:28.291558 <6>[ 8.239047] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10810 00:57:28.297874 <6>[ 8.239432] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10811 00:57:28.311315 <6>[ 8.239723] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10812 00:57:28.318163 <6>[ 8.240074] usbcore: registered new interface driver uvcvideo
10813 00:57:28.324544 <6>[ 8.247152] Bluetooth: HCI device and connection manager initialized
10814 00:57:28.327978 <6>[ 8.256227] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10815 00:57:28.334398 <6>[ 8.261699] Bluetooth: HCI socket layer initialized
10816 00:57:28.341074 <6>[ 8.269329] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10817 00:57:28.347542 <6>[ 8.270109] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10818 00:57:28.354404 <3>[ 8.270523] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10819 00:57:28.361143 <6>[ 8.276711] Bluetooth: L2CAP socket layer initialized
10820 00:57:28.367838 <5>[ 8.304996] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10821 00:57:28.373863 <6>[ 8.310496] Bluetooth: SCO socket layer initialized
10822 00:57:28.380920 <5>[ 8.332950] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10823 00:57:28.387079 <6>[ 8.375730] usbcore: registered new interface driver btusb
10824 00:57:28.397004 <4>[ 8.376587] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10825 00:57:28.403821 <3>[ 8.376597] Bluetooth: hci0: Failed to load firmware file (-2)
10826 00:57:28.407031 <3>[ 8.376600] Bluetooth: hci0: Failed to set up firmware (-2)
10827 00:57:28.420205 <4>[ 8.376603] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10828 00:57:28.427050 <5>[ 8.383545] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10829 00:57:28.436912 <4>[ 8.639588] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10830 00:57:28.440214 <6>[ 8.648468] cfg80211: failed to load regulatory.db
10831 00:57:28.482750 <6>[ 8.686095] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10832 00:57:28.489298 <6>[ 8.693588] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10833 00:57:28.513190 <6>[ 8.720225] mt7921e 0000:01:00.0: ASIC revision: 79610010
10834 00:57:28.614553 <6>[ 8.818141] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10835 00:57:28.617898 <6>[ 8.818141]
10836 00:57:28.632358 Begin: Loading essential drivers ... done.
10837 00:57:28.635633 Begin: Running /scripts/init-premount ... done.
10838 00:57:28.641926 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10839 00:57:28.651938 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10840 00:57:28.655164 Device /sys/class/net/eth0 found
10841 00:57:28.655283 done.
10842 00:57:28.687787 Begin: Waiting up to 180 secs for any network device to become available ... done.
10843 00:57:28.735683 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10844 00:57:28.769100 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10845 00:57:28.776135 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10846 00:57:28.782517 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10847 00:57:28.788795 host : mt8192-asurada-spherion-r0-cbg-8
10848 00:57:28.795650 domain : lava-rack
10849 00:57:28.798892 rootserver: 192.168.201.1 rootpath:
10850 00:57:28.802301 filename :
10851 00:57:28.802379 done.
10852 00:57:28.805706 Begin: Running /scripts/nfs-bottom ... done.
10853 00:57:28.822063 Begin: Running /scripts/init-bottom ... done.
10854 00:57:28.882040 <6>[ 9.085942] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10855 00:57:30.185980 <6>[ 10.393321] NET: Registered PF_INET6 protocol family
10856 00:57:30.193893 <6>[ 10.401158] Segment Routing with IPv6
10857 00:57:30.197214 <6>[ 10.405166] In-situ OAM (IOAM) with IPv6
10858 00:57:30.380763 <30>[ 10.561869] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10859 00:57:30.388029 <30>[ 10.595021] systemd[1]: Detected architecture arm64.
10860 00:57:30.396789
10861 00:57:30.400015 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10862 00:57:30.400092
10863 00:57:30.424589 <30>[ 10.632168] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10864 00:57:31.632050 <30>[ 11.836083] systemd[1]: Queued start job for default target graphical.target.
10865 00:57:31.680206 <30>[ 11.884524] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10866 00:57:31.686863 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10867 00:57:31.708754 <30>[ 11.912642] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10868 00:57:31.718199 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10869 00:57:31.736751 <30>[ 11.940613] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10870 00:57:31.746361 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10871 00:57:31.764389 <30>[ 11.968098] systemd[1]: Created slice user.slice - User and Session Slice.
10872 00:57:31.770757 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10873 00:57:31.794713 <30>[ 11.995474] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10874 00:57:31.804266 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10875 00:57:31.826524 <30>[ 12.027426] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10876 00:57:31.833198 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10877 00:57:31.860413 <30>[ 12.054810] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10878 00:57:31.870538 <30>[ 12.074668] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10879 00:57:31.877247 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10880 00:57:31.894901 <30>[ 12.098933] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10881 00:57:31.904577 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10882 00:57:31.922756 <30>[ 12.126667] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10883 00:57:31.932414 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10884 00:57:31.947635 <30>[ 12.155022] systemd[1]: Reached target paths.target - Path Units.
10885 00:57:31.957741 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10886 00:57:31.974825 <30>[ 12.178893] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10887 00:57:31.981200 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10888 00:57:31.995392 <30>[ 12.202451] systemd[1]: Reached target slices.target - Slice Units.
10889 00:57:32.005404 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10890 00:57:32.019375 <30>[ 12.226930] systemd[1]: Reached target swap.target - Swaps.
10891 00:57:32.025968 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10892 00:57:32.046877 <30>[ 12.250982] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10893 00:57:32.056524 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10894 00:57:32.074980 <30>[ 12.278933] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10895 00:57:32.084964 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10896 00:57:32.105414 <30>[ 12.309192] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10897 00:57:32.114866 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10898 00:57:32.131687 <30>[ 12.335887] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10899 00:57:32.141706 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10900 00:57:32.158845 <30>[ 12.363105] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10901 00:57:32.165522 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10902 00:57:32.184228 <30>[ 12.388088] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10903 00:57:32.193815 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10904 00:57:32.213232 <30>[ 12.417435] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10905 00:57:32.223211 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10906 00:57:32.238729 <30>[ 12.442965] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10907 00:57:32.248541 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10908 00:57:32.306705 <30>[ 12.510551] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10909 00:57:32.312774 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10910 00:57:32.334791 <30>[ 12.539184] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10911 00:57:32.341659 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10912 00:57:32.398473 <30>[ 12.602833] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10913 00:57:32.405029 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10914 00:57:32.433236 <30>[ 12.631129] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10915 00:57:32.449195 <30>[ 12.653522] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10916 00:57:32.459196 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10917 00:57:32.478402 <30>[ 12.682726] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10918 00:57:32.485042 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10919 00:57:32.511643 <30>[ 12.715970] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10920 00:57:32.518196 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10921 00:57:32.542213 <30>[ 12.746645] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10922 00:57:32.548999 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10923 00:57:32.559568 <6>[ 12.763938] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10924 00:57:32.599279 <30>[ 12.803381] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10925 00:57:32.609152 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10926 00:57:32.632324 <30>[ 12.836618] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10927 00:57:32.639211 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10928 00:57:32.662992 <30>[ 12.867187] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10929 00:57:32.672563 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 12.880869] fuse: init (API version 7.37)
10930 00:57:32.672698 el Module loop...
10931 00:57:32.702947 <30>[ 12.906978] systemd[1]: Starting systemd-journald.service - Journal Service...
10932 00:57:32.709424 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10933 00:57:32.734097 <30>[ 12.938532] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10934 00:57:32.741141 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10935 00:57:32.766227 <30>[ 12.967198] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10936 00:57:32.772515 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10937 00:57:32.796001 <30>[ 13.000005] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10938 00:57:32.805491 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10939 00:57:32.827573 <30>[ 13.031996] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10940 00:57:32.834416 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10941 00:57:32.857475 <30>[ 13.061445] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10942 00:57:32.863858 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10943 00:57:32.882678 <30>[ 13.087234] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10944 00:57:32.889309 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10945 00:57:32.912124 <3>[ 13.116407] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 00:57:32.921703 <30>[ 13.126160] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10947 00:57:32.928823 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10948 00:57:32.943008 <3>[ 13.147345] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 00:57:32.953031 <30>[ 13.157096] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10950 00:57:32.963097 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10951 00:57:32.975529 <3>[ 13.179985] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 00:57:32.985525 <30>[ 13.189989] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10953 00:57:32.992346 <30>[ 13.197969] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10954 00:57:33.009469 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 13.210933] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 00:57:33.012381 Load Kernel Module configfs.
10956 00:57:33.028630 <30>[ 13.235823] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10957 00:57:33.039535 <30>[ 13.243699] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10958 00:57:33.049346 <3>[ 13.245084] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 00:57:33.056095 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10960 00:57:33.072815 <30>[ 13.280147] systemd[1]: modprobe@drm.service: Deactivated successfully.
10961 00:57:33.082736 <3>[ 13.284917] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 00:57:33.092687 <30>[ 13.288489] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10963 00:57:33.099082 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10964 00:57:33.116154 <3>[ 13.320323] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 00:57:33.127213 <30>[ 13.331478] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10966 00:57:33.138180 <30>[ 13.340128] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10967 00:57:33.151006 [[0;32m OK [0m] Finished [0;1;39mmodprobe@e<3>[ 13.352269] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 00:57:33.154250 fi_psto…m - Load Kernel Module efi_pstore.
10969 00:57:33.169797 <30>[ 13.376602] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10970 00:57:33.179620 <30>[ 13.384112] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10971 00:57:33.189934 <3>[ 13.385244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 00:57:33.196088 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10973 00:57:33.217157 <30>[ 13.421260] systemd[1]: modprobe@loop.service: Deactivated successfully.
10974 00:57:33.223840 <30>[ 13.429484] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10975 00:57:33.233865 <3>[ 13.437551] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 00:57:33.240172 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10977 00:57:33.265138 <30>[ 13.469020] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10978 00:57:33.274524 <3>[ 13.477455] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 00:57:33.281075 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10980 00:57:33.303557 <30>[ 13.504334] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10981 00:57:33.310438 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10982 00:57:33.321030 <3>[ 13.525133] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 00:57:33.330895 <3>[ 13.525950] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10984 00:57:33.347187 <4>[ 13.533933] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10985 00:57:33.354017 <3>[ 13.533937] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10986 00:57:33.363948 <30>[ 13.560572] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10987 00:57:33.371134 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10988 00:57:33.384768 <3>[ 13.588914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 00:57:33.395544 <30>[ 13.599741] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10990 00:57:33.405120 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10991 00:57:33.424333 <30>[ 13.628476] systemd[1]: Reached target network-pre.target - Preparation for Network.
10992 00:57:33.430816 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10993 00:57:33.470803 <30>[ 13.675119] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10994 00:57:33.477397 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10995 00:57:33.504029 <30>[ 13.708224] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10996 00:57:33.513654 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10997 00:57:33.533612 <30>[ 13.734785] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10998 00:57:33.550909 <30>[ 13.748497] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10999 00:57:33.595121 <30>[ 13.799355] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
11000 00:57:33.601849 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11001 00:57:33.628058 <30>[ 13.829358] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
11002 00:57:33.641004 <30>[ 13.845413] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
11003 00:57:33.647613 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11004 00:57:33.674406 <30>[ 13.878486] systemd[1]: Starting systemd-sysusers.service - Create System Users...
11005 00:57:33.680899 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11006 00:57:33.712102 <30>[ 13.916169] systemd[1]: Started systemd-journald.service - Journal Service.
11007 00:57:33.718300 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11008 00:57:33.744138 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11009 00:57:33.762647 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11010 00:57:33.779670 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11011 00:57:33.799776 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11012 00:57:33.819849 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11013 00:57:33.875665 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11014 00:57:33.897090 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11015 00:57:33.932189 <46>[ 14.136616] systemd-journald[302]: Received client request to flush runtime journal.
11016 00:57:35.061082 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11017 00:57:35.078763 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11018 00:57:35.098736 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11019 00:57:35.366858 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11020 00:57:35.388467 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11021 00:57:35.412821 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11022 00:57:35.550851 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11023 00:57:35.610100 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11024 00:57:35.677895 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11025 00:57:35.971065 <6>[ 16.179148] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11026 00:57:35.991638 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11027 00:57:36.012190 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11028 00:57:36.079940 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11029 00:57:36.159744 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11030 00:57:36.215765 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11031 00:57:36.235987 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11032 00:57:36.258328 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11033 00:57:36.282879 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11034 00:57:36.334860 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11035 00:57:36.395073 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11036 00:57:36.421213 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11037 00:57:36.442442 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11038 00:57:36.485051 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11039 00:57:36.569662 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11040 00:57:36.590041 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11041 00:57:36.610227 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11042 00:57:36.625791 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11043 00:57:36.652519 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11044 00:57:36.673351 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11045 00:57:36.690106 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11046 00:57:36.709331 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11047 00:57:36.729712 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11048 00:57:36.745683 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11049 00:57:36.764595 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11050 00:57:36.781810 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11051 00:57:36.797991 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11052 00:57:36.851266 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11053 00:57:36.899221 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11054 00:57:36.994912 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11055 00:57:37.024237 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11056 00:57:37.161819 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11057 00:57:37.215183 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11058 00:57:37.236813 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11059 00:57:37.255903 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11060 00:57:37.294737 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11061 00:57:37.318204 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11062 00:57:37.344784 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11063 00:57:37.368999 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11064 00:57:37.387657 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11065 00:57:37.449801 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11066 00:57:37.535626 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11067 00:57:37.641250
11068 00:57:37.644443 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11069 00:57:37.644557
11070 00:57:37.647758 debian-bookworm-arm64 login: root (automatic login)
11071 00:57:37.647859
11072 00:57:37.982638 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
11073 00:57:37.982805
11074 00:57:37.989171 The programs included with the Debian GNU/Linux system are free software;
11075 00:57:37.995890 the exact distribution terms for each program are described in the
11076 00:57:37.998906 individual files in /usr/share/doc/*/copyright.
11077 00:57:37.999016
11078 00:57:38.005719 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11079 00:57:38.008614 permitted by applicable law.
11080 00:57:39.152463 Matched prompt #10: / #
11082 00:57:39.152867 Setting prompt string to ['/ #']
11083 00:57:39.152996 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11085 00:57:39.153273 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11086 00:57:39.153394 start: 2.2.6 expect-shell-connection (timeout 00:03:15) [common]
11087 00:57:39.153498 Setting prompt string to ['/ #']
11088 00:57:39.153584 Forcing a shell prompt, looking for ['/ #']
11090 00:57:39.203843 / #
11091 00:57:39.204110 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11092 00:57:39.204216 Waiting using forced prompt support (timeout 00:02:30)
11093 00:57:39.209303
11094 00:57:39.209613 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11095 00:57:39.209745 start: 2.2.7 export-device-env (timeout 00:03:15) [common]
11097 00:57:39.310132 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368602/extract-nfsrootfs-0wliq_c2'
11098 00:57:39.315892 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368602/extract-nfsrootfs-0wliq_c2'
11100 00:57:39.416520 / # export NFS_SERVER_IP='192.168.201.1'
11101 00:57:39.421815 export NFS_SERVER_IP='192.168.201.1'
11102 00:57:39.422116 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11103 00:57:39.422209 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
11104 00:57:39.422295 end: 2 depthcharge-action (duration 00:01:46) [common]
11105 00:57:39.422379 start: 3 lava-test-retry (timeout 00:07:33) [common]
11106 00:57:39.422463 start: 3.1 lava-test-shell (timeout 00:07:33) [common]
11107 00:57:39.422533 Using namespace: common
11109 00:57:39.522875 / # #
11110 00:57:39.523096 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11111 00:57:39.527975 #
11112 00:57:39.528238 Using /lava-14368602
11114 00:57:39.628596 / # export SHELL=/bin/bash
11115 00:57:39.634374 export SHELL=/bin/bash
11117 00:57:39.734915 / # . /lava-14368602/environment
11118 00:57:39.740013 . /lava-14368602/environment
11120 00:57:39.847663 / # /lava-14368602/bin/lava-test-runner /lava-14368602/0
11121 00:57:39.847878 Test shell timeout: 10s (minimum of the action and connection timeout)
11122 00:57:39.852942 /lava-14368602/bin/lava-test-runner /lava-14368602/0
11123 00:57:40.156171 + export TESTRUN_ID=0_timesync-off
11124 00:57:40.159490 + TESTRUN_ID=0_timesync-off
11125 00:57:40.162812 + cd /lava-14368602/0/tests/0_timesync-off
11126 00:57:40.166196 ++ cat uuid
11127 00:57:40.172437 + UUID=14368602_1.6.2.3.1
11128 00:57:40.172536 + set +x
11129 00:57:40.179210 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368602_1.6.2.3.1>
11130 00:57:40.179519 Received signal: <STARTRUN> 0_timesync-off 14368602_1.6.2.3.1
11131 00:57:40.179624 Starting test lava.0_timesync-off (14368602_1.6.2.3.1)
11132 00:57:40.179745 Skipping test definition patterns.
11133 00:57:40.182368 + systemctl stop systemd-timesyncd
11134 00:57:40.250001 + set +x
11135 00:57:40.253132 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368602_1.6.2.3.1>
11136 00:57:40.253420 Received signal: <ENDRUN> 0_timesync-off 14368602_1.6.2.3.1
11137 00:57:40.253534 Ending use of test pattern.
11138 00:57:40.253620 Ending test lava.0_timesync-off (14368602_1.6.2.3.1), duration 0.07
11140 00:57:40.338663 + export TESTRUN_ID=1_kselftest-tpm2
11141 00:57:40.342005 + TESTRUN_ID=1_kselftest-tpm2
11142 00:57:40.345328 + cd /lava-14368602/0/tests/1_kselftest-tpm2
11143 00:57:40.348222 ++ cat uuid
11144 00:57:40.357083 + UUID=14368602_1.6.2.3.5
11145 00:57:40.357216 + set +x
11146 00:57:40.363787 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14368602_1.6.2.3.5>
11147 00:57:40.364075 Received signal: <STARTRUN> 1_kselftest-tpm2 14368602_1.6.2.3.5
11148 00:57:40.364171 Starting test lava.1_kselftest-tpm2 (14368602_1.6.2.3.5)
11149 00:57:40.364280 Skipping test definition patterns.
11150 00:57:40.367253 + cd ./automated/linux/kselftest/
11151 00:57:40.393866 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11152 00:57:40.440780 INFO: install_deps skipped
11153 00:57:40.964148 --2024-06-16 00:57:40-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11154 00:57:40.970327 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11155 00:57:41.094923 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11156 00:57:41.220288 HTTP request sent, awaiting response... 200 OK
11157 00:57:41.223788 Length: 1647948 (1.6M) [application/octet-stream]
11158 00:57:41.227141 Saving to: 'kselftest_armhf.tar.gz'
11159 00:57:41.227220
11160 00:57:41.227279
11161 00:57:41.470833 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11162 00:57:41.720888 kselftest_armhf.tar 2%[ ] 47.81K 192KB/s
11163 00:57:41.971086 kselftest_armhf.tar 13%[=> ] 214.67K 430KB/s
11164 00:57:42.227679 kselftest_armhf.tar 55%[==========> ] 896.25K 1.17MB/s
11165 00:57:42.477608 kselftest_armhf.tar 86%[================> ] 1.35M 1.34MB/s
11166 00:57:42.727769 kselftest_armhf.tar 86%[================> ] 1.36M 1.08MB/s
11167 00:57:42.979117 kselftest_armhf.tar 87%[================> ] 1.37M 932KB/s
11168 00:57:43.107849 kselftest_armhf.tar 90%[=================> ] 1.43M 831KB/s
11169 00:57:43.114230 kselftest_armhf.tar 100%[===================>] 1.57M 853KB/s in 1.9s
11170 00:57:43.114311
11171 00:57:43.260359 2024-06-16 00:57:43 (853 KB/s) - 'kselftest_armhf.tar.gz' saved [1647948/1647948]
11172 00:57:43.260490
11173 00:57:48.263687 skiplist:
11174 00:57:48.267095 ========================================
11175 00:57:48.270371 ========================================
11176 00:57:48.321967 tpm2:test_smoke.sh
11177 00:57:48.325352 tpm2:test_space.sh
11178 00:57:48.350746 ============== Tests to run ===============
11179 00:57:48.354120 tpm2:test_smoke.sh
11180 00:57:48.354205 tpm2:test_space.sh
11181 00:57:48.357483 ===========End Tests to run ===============
11182 00:57:48.360862 shardfile-tpm2 pass
11183 00:57:48.483661 <12>[ 28.693242] kselftest: Running tests in tpm2
11184 00:57:48.494748 TAP version 13
11185 00:57:48.510724 1..2
11186 00:57:48.547086 # selftests: tpm2: test_smoke.sh
11187 00:57:50.502718 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11188 00:57:50.509045 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11189 00:57:50.515894 # Exception ignored in: <function Client.__del__ at 0xffff90ccccc0>
11190 00:57:50.518738 # Traceback (most recent call last):
11191 00:57:50.528665 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11192 00:57:50.528812 # if self.tpm:
11193 00:57:50.532283 # ^^^^^^^^
11194 00:57:50.535750 # AttributeError: 'Client' object has no attribute 'tpm'
11195 00:57:50.541952 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11196 00:57:50.548673 # Exception ignored in: <function Client.__del__ at 0xffff90ccccc0>
11197 00:57:50.552028 # Traceback (most recent call last):
11198 00:57:50.562057 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11199 00:57:50.562160 # if self.tpm:
11200 00:57:50.565605 # ^^^^^^^^
11201 00:57:50.568513 # AttributeError: 'Client' object has no attribute 'tpm'
11202 00:57:50.575471 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11203 00:57:50.581754 # Exception ignored in: <function Client.__del__ at 0xffff90ccccc0>
11204 00:57:50.585509 # Traceback (most recent call last):
11205 00:57:50.595581 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11206 00:57:50.598615 # if self.tpm:
11207 00:57:50.598695 # ^^^^^^^^
11208 00:57:50.605335 # AttributeError: 'Client' object has no attribute 'tpm'
11209 00:57:50.611707 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11210 00:57:50.618606 # Exception ignored in: <function Client.__del__ at 0xffff90ccccc0>
11211 00:57:50.622070 # Traceback (most recent call last):
11212 00:57:50.631741 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11213 00:57:50.631859 # if self.tpm:
11214 00:57:50.635083 # ^^^^^^^^
11215 00:57:50.638723 # AttributeError: 'Client' object has no attribute 'tpm'
11216 00:57:50.644991 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11217 00:57:50.652344 # Exception ignored in: <function Client.__del__ at 0xffff90ccccc0>
11218 00:57:50.655120 # Traceback (most recent call last):
11219 00:57:50.665518 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11220 00:57:50.668562 # if self.tpm:
11221 00:57:50.668640 # ^^^^^^^^
11222 00:57:50.675663 # AttributeError: 'Client' object has no attribute 'tpm'
11223 00:57:50.681732 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11224 00:57:50.685388 # Exception ignored in: <function Client.__del__ at 0xffff90ccccc0>
11225 00:57:50.688333 # Traceback (most recent call last):
11226 00:57:50.698478 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11227 00:57:50.701831 # if self.tpm:
11228 00:57:50.701936 # ^^^^^^^^
11229 00:57:50.708488 # AttributeError: 'Client' object has no attribute 'tpm'
11230 00:57:50.715260 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11231 00:57:50.721873 # Exception ignored in: <function Client.__del__ at 0xffff90ccccc0>
11232 00:57:50.725263 # Traceback (most recent call last):
11233 00:57:50.735147 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11234 00:57:50.738493 # if self.tpm:
11235 00:57:50.738974 # ^^^^^^^^
11236 00:57:50.745205 # AttributeError: 'Client' object has no attribute 'tpm'
11237 00:57:50.751392 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11238 00:57:50.758275 # Exception ignored in: <function Client.__del__ at 0xffff90ccccc0>
11239 00:57:50.761799 # Traceback (most recent call last):
11240 00:57:50.771610 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11241 00:57:50.772093 # if self.tpm:
11242 00:57:50.774964 # ^^^^^^^^
11243 00:57:50.778402 # AttributeError: 'Client' object has no attribute 'tpm'
11244 00:57:50.778796 #
11245 00:57:50.784760 # ======================================================================
11246 00:57:50.794729 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11247 00:57:50.801596 # ----------------------------------------------------------------------
11248 00:57:50.804887 # Traceback (most recent call last):
11249 00:57:50.814322 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11250 00:57:50.817727 # self.root_key = self.client.create_root_key()
11251 00:57:50.820952 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11252 00:57:50.834064 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11253 00:57:50.837507 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11254 00:57:50.844525 # ^^^^^^^^^^^^^^^^^^
11255 00:57:50.854066 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11256 00:57:50.857752 # raise ProtocolError(cc, rc)
11257 00:57:50.860692 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11258 00:57:50.860776 #
11259 00:57:50.867723 # ======================================================================
11260 00:57:50.874722 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11261 00:57:50.881127 # ----------------------------------------------------------------------
11262 00:57:50.884357 # Traceback (most recent call last):
11263 00:57:50.894467 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11264 00:57:50.898842 # self.client = tpm2.Client()
11265 00:57:50.901856 # ^^^^^^^^^^^^^
11266 00:57:50.912447 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11267 00:57:50.915897 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11268 00:57:50.922355 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11269 00:57:50.925874 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11270 00:57:50.925961 #
11271 00:57:50.932113 # ======================================================================
11272 00:57:50.938737 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11273 00:57:50.945635 # ----------------------------------------------------------------------
11274 00:57:50.948584 # Traceback (most recent call last):
11275 00:57:50.958661 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11276 00:57:50.961929 # self.client = tpm2.Client()
11277 00:57:50.965244 # ^^^^^^^^^^^^^
11278 00:57:50.975613 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11279 00:57:50.979120 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11280 00:57:50.985312 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11281 00:57:50.988674 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11282 00:57:50.992591 #
11283 00:57:50.995531 # ======================================================================
11284 00:57:51.001820 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11285 00:57:51.009068 # ----------------------------------------------------------------------
11286 00:57:51.012136 # Traceback (most recent call last):
11287 00:57:51.022018 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11288 00:57:51.025506 # self.client = tpm2.Client()
11289 00:57:51.029166 # ^^^^^^^^^^^^^
11290 00:57:51.038869 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11291 00:57:51.045847 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11292 00:57:51.048767 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11293 00:57:51.055763 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11294 00:57:51.055842 #
11295 00:57:51.061890 # ======================================================================
11296 00:57:51.068699 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11297 00:57:51.075854 # ----------------------------------------------------------------------
11298 00:57:51.079008 # Traceback (most recent call last):
11299 00:57:51.089227 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11300 00:57:51.092594 # self.client = tpm2.Client()
11301 00:57:51.095776 # ^^^^^^^^^^^^^
11302 00:57:51.106019 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11303 00:57:51.109002 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11304 00:57:51.115827 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11305 00:57:51.119163 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11306 00:57:51.119571 #
11307 00:57:51.125607 # ======================================================================
11308 00:57:51.132377 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11309 00:57:51.138869 # ----------------------------------------------------------------------
11310 00:57:51.142308 # Traceback (most recent call last):
11311 00:57:51.151793 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11312 00:57:51.155210 # self.client = tpm2.Client()
11313 00:57:51.158701 # ^^^^^^^^^^^^^
11314 00:57:51.168930 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11315 00:57:51.175099 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11316 00:57:51.178302 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11317 00:57:51.185449 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11318 00:57:51.185841 #
11319 00:57:51.191799 # ======================================================================
11320 00:57:51.195324 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11321 00:57:51.201640 # ----------------------------------------------------------------------
11322 00:57:51.205151 # Traceback (most recent call last):
11323 00:57:51.215225 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11324 00:57:51.218514 # self.client = tpm2.Client()
11325 00:57:51.222051 # ^^^^^^^^^^^^^
11326 00:57:51.231768 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11327 00:57:51.238758 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11328 00:57:51.242195 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11329 00:57:51.249026 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11330 00:57:51.249502 #
11331 00:57:51.255474 # ======================================================================
11332 00:57:51.262510 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11333 00:57:51.268642 # ----------------------------------------------------------------------
11334 00:57:51.272112 # Traceback (most recent call last):
11335 00:57:51.281954 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11336 00:57:51.285139 # self.client = tpm2.Client()
11337 00:57:51.288586 # ^^^^^^^^^^^^^
11338 00:57:51.296139 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11339 00:57:51.303122 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11340 00:57:51.306319 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11341 00:57:51.313378 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11342 00:57:51.313873 #
11343 00:57:51.320604 # ======================================================================
11344 00:57:51.326704 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11345 00:57:51.333962 # ----------------------------------------------------------------------
11346 00:57:51.337557 # Traceback (most recent call last):
11347 00:57:51.348737 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11348 00:57:51.352298 # self.client = tpm2.Client()
11349 00:57:51.352817 # ^^^^^^^^^^^^^
11350 00:57:51.362599 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11351 00:57:51.369726 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11352 00:57:51.375002 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11353 00:57:51.378374 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11354 00:57:51.378864 #
11355 00:57:51.385288 # ----------------------------------------------------------------------
11356 00:57:51.388554 # Ran 9 tests in 0.061s
11357 00:57:51.389054 #
11358 00:57:51.389366 # FAILED (errors=9)
11359 00:57:51.395083 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11360 00:57:51.401960 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11361 00:57:51.402359 #
11362 00:57:51.408526 # ----------------------------------------------------------------------
11363 00:57:51.412183 # Ran 2 tests in 0.032s
11364 00:57:51.412699 #
11365 00:57:51.413023 # OK
11366 00:57:51.415295 ok 1 selftests: tpm2: test_smoke.sh
11367 00:57:51.418211 # selftests: tpm2: test_space.sh
11368 00:57:51.424879 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11369 00:57:51.431836 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11370 00:57:51.435129 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11371 00:57:51.441964 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11372 00:57:51.442445 #
11373 00:57:51.448351 # ======================================================================
11374 00:57:51.455193 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11375 00:57:51.461545 # ----------------------------------------------------------------------
11376 00:57:51.465172 # Traceback (most recent call last):
11377 00:57:51.478238 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11378 00:57:51.481073 # root1 = space1.create_root_key()
11379 00:57:51.484571 # ^^^^^^^^^^^^^^^^^^^^^^^^
11380 00:57:51.494925 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11381 00:57:51.501062 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11382 00:57:51.504324 # ^^^^^^^^^^^^^^^^^^
11383 00:57:51.514665 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11384 00:57:51.517917 # raise ProtocolError(cc, rc)
11385 00:57:51.524468 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11386 00:57:51.524987 #
11387 00:57:51.531421 # ======================================================================
11388 00:57:51.534685 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11389 00:57:51.541184 # ----------------------------------------------------------------------
11390 00:57:51.544607 # Traceback (most recent call last):
11391 00:57:51.557481 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11392 00:57:51.560873 # space1.create_root_key()
11393 00:57:51.571093 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11394 00:57:51.574300 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11395 00:57:51.581224 # ^^^^^^^^^^^^^^^^^^
11396 00:57:51.591256 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11397 00:57:51.594219 # raise ProtocolError(cc, rc)
11398 00:57:51.598022 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11399 00:57:51.601162 #
11400 00:57:51.607901 # ======================================================================
11401 00:57:51.611035 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11402 00:57:51.617634 # ----------------------------------------------------------------------
11403 00:57:51.620750 # Traceback (most recent call last):
11404 00:57:51.630541 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11405 00:57:51.637730 # root1 = space1.create_root_key()
11406 00:57:51.640595 # ^^^^^^^^^^^^^^^^^^^^^^^^
11407 00:57:51.651405 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11408 00:57:51.653769 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11409 00:57:51.660854 # ^^^^^^^^^^^^^^^^^^
11410 00:57:51.670599 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11411 00:57:51.673821 # raise ProtocolError(cc, rc)
11412 00:57:51.680736 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11413 00:57:51.681241 #
11414 00:57:51.687404 # ======================================================================
11415 00:57:51.693933 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11416 00:57:51.697240 # ----------------------------------------------------------------------
11417 00:57:51.700751 # Traceback (most recent call last):
11418 00:57:51.713533 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11419 00:57:51.716896 # root1 = space1.create_root_key()
11420 00:57:51.720734 # ^^^^^^^^^^^^^^^^^^^^^^^^
11421 00:57:51.730498 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11422 00:57:51.736982 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11423 00:57:51.740124 # ^^^^^^^^^^^^^^^^^^
11424 00:57:51.750716 # File "/lava-14368602/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11425 00:57:51.753479 # raise ProtocolError(cc, rc)
11426 00:57:51.760360 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11427 00:57:51.760795 #
11428 00:57:51.766968 # ----------------------------------------------------------------------
11429 00:57:51.769941 # Ran 4 tests in 0.102s
11430 00:57:51.770355 #
11431 00:57:51.770662 # FAILED (errors=4)
11432 00:57:51.776632 not ok 2 selftests: tpm2: test_space.sh # exit=1
11433 00:57:52.137550 tpm2_test_smoke_sh pass
11434 00:57:52.140707 tpm2_test_space_sh fail
11435 00:57:52.210991 + ../../utils/send-to-lava.sh ./output/result.txt
11436 00:57:52.305552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11437 00:57:52.306300 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11439 00:57:52.381580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11440 00:57:52.382354 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11442 00:57:52.453642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11443 00:57:52.454319 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11445 00:57:52.456820 + set +x
11446 00:57:52.460095 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14368602_1.6.2.3.5>
11447 00:57:52.460594 Received signal: <ENDRUN> 1_kselftest-tpm2 14368602_1.6.2.3.5
11448 00:57:52.460876 Ending use of test pattern.
11449 00:57:52.461087 Ending test lava.1_kselftest-tpm2 (14368602_1.6.2.3.5), duration 12.10
11451 00:57:52.463091 <LAVA_TEST_RUNNER EXIT>
11452 00:57:52.463493 ok: lava_test_shell seems to have completed
11453 00:57:52.463768 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11454 00:57:52.463987 end: 3.1 lava-test-shell (duration 00:00:13) [common]
11455 00:57:52.464241 end: 3 lava-test-retry (duration 00:00:13) [common]
11456 00:57:52.464468 start: 4 finalize (timeout 00:07:20) [common]
11457 00:57:52.464711 start: 4.1 power-off (timeout 00:00:30) [common]
11458 00:57:52.465065 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11459 00:57:52.684748 >> Command sent successfully.
11460 00:57:52.698064 Returned 0 in 0 seconds
11461 00:57:52.799414 end: 4.1 power-off (duration 00:00:00) [common]
11463 00:57:52.800761 start: 4.2 read-feedback (timeout 00:07:20) [common]
11464 00:57:52.801923 Listened to connection for namespace 'common' for up to 1s
11465 00:57:53.802752 Finalising connection for namespace 'common'
11466 00:57:53.803399 Disconnecting from shell: Finalise
11467 00:57:53.803793 / #
11468 00:57:53.904816 end: 4.2 read-feedback (duration 00:00:01) [common]
11469 00:57:53.905429 end: 4 finalize (duration 00:00:01) [common]
11470 00:57:53.905998 Cleaning after the job
11471 00:57:53.906465 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/ramdisk
11472 00:57:53.911124 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/kernel
11473 00:57:53.921095 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/dtb
11474 00:57:53.921260 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/nfsrootfs
11475 00:57:53.980172 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368602/tftp-deploy-22_ggd8q/modules
11476 00:57:53.985433 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368602
11477 00:57:54.511759 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368602
11478 00:57:54.511932 Job finished correctly