Boot log: mt8192-asurada-spherion-r0
- Errors: 3
- Kernel Errors: 35
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 25
1 00:59:36.655303 lava-dispatcher, installed at version: 2024.03
2 00:59:36.655517 start: 0 validate
3 00:59:36.655655 Start time: 2024-06-16 00:59:36.655648+00:00 (UTC)
4 00:59:36.655777 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:59:36.655906 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:59:36.919178 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:59:36.919358 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:59:37.170112 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:59:37.170340 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:59:37.422209 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:59:37.422894 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:59:37.675860 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:59:37.676594 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:59:37.938121 validate duration: 1.28
16 00:59:37.939429 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:59:37.939974 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:59:37.940424 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:59:37.940996 Not decompressing ramdisk as can be used compressed.
20 00:59:37.941444 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 00:59:37.941778 saving as /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/ramdisk/initrd.cpio.gz
22 00:59:37.942105 total size: 5628151 (5 MB)
23 00:59:37.946981 progress 0 % (0 MB)
24 00:59:37.955321 progress 5 % (0 MB)
25 00:59:37.962857 progress 10 % (0 MB)
26 00:59:37.967563 progress 15 % (0 MB)
27 00:59:37.971778 progress 20 % (1 MB)
28 00:59:37.974900 progress 25 % (1 MB)
29 00:59:37.978052 progress 30 % (1 MB)
30 00:59:37.980888 progress 35 % (1 MB)
31 00:59:37.983161 progress 40 % (2 MB)
32 00:59:37.985584 progress 45 % (2 MB)
33 00:59:37.987628 progress 50 % (2 MB)
34 00:59:37.989738 progress 55 % (2 MB)
35 00:59:37.991841 progress 60 % (3 MB)
36 00:59:37.993589 progress 65 % (3 MB)
37 00:59:37.995532 progress 70 % (3 MB)
38 00:59:37.997227 progress 75 % (4 MB)
39 00:59:37.998949 progress 80 % (4 MB)
40 00:59:38.000475 progress 85 % (4 MB)
41 00:59:38.002148 progress 90 % (4 MB)
42 00:59:38.003717 progress 95 % (5 MB)
43 00:59:38.005131 progress 100 % (5 MB)
44 00:59:38.005342 5 MB downloaded in 0.06 s (84.85 MB/s)
45 00:59:38.005493 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:59:38.005738 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:59:38.005828 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:59:38.005918 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:59:38.006057 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:59:38.006129 saving as /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/kernel/Image
52 00:59:38.006202 total size: 54813184 (52 MB)
53 00:59:38.006266 No compression specified
54 00:59:38.007422 progress 0 % (0 MB)
55 00:59:38.021763 progress 5 % (2 MB)
56 00:59:38.035906 progress 10 % (5 MB)
57 00:59:38.049681 progress 15 % (7 MB)
58 00:59:38.063540 progress 20 % (10 MB)
59 00:59:38.077423 progress 25 % (13 MB)
60 00:59:38.091187 progress 30 % (15 MB)
61 00:59:38.105228 progress 35 % (18 MB)
62 00:59:38.119252 progress 40 % (20 MB)
63 00:59:38.132975 progress 45 % (23 MB)
64 00:59:38.146930 progress 50 % (26 MB)
65 00:59:38.160936 progress 55 % (28 MB)
66 00:59:38.174552 progress 60 % (31 MB)
67 00:59:38.188296 progress 65 % (34 MB)
68 00:59:38.202074 progress 70 % (36 MB)
69 00:59:38.216062 progress 75 % (39 MB)
70 00:59:38.230054 progress 80 % (41 MB)
71 00:59:38.243804 progress 85 % (44 MB)
72 00:59:38.257809 progress 90 % (47 MB)
73 00:59:38.271639 progress 95 % (49 MB)
74 00:59:38.285049 progress 100 % (52 MB)
75 00:59:38.285277 52 MB downloaded in 0.28 s (187.31 MB/s)
76 00:59:38.285431 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:59:38.285666 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:59:38.285754 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:59:38.285840 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:59:38.285976 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:59:38.286054 saving as /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/dtb/mt8192-asurada-spherion-r0.dtb
83 00:59:38.286115 total size: 47258 (0 MB)
84 00:59:38.286183 No compression specified
85 00:59:38.287296 progress 69 % (0 MB)
86 00:59:38.287568 progress 100 % (0 MB)
87 00:59:38.287722 0 MB downloaded in 0.00 s (28.08 MB/s)
88 00:59:38.287846 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:59:38.288067 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:59:38.288152 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:59:38.288235 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:59:38.288351 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 00:59:38.288420 saving as /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/nfsrootfs/full.rootfs.tar
95 00:59:38.288480 total size: 69067788 (65 MB)
96 00:59:38.288541 Using unxz to decompress xz
97 00:59:38.292505 progress 0 % (0 MB)
98 00:59:38.483327 progress 5 % (3 MB)
99 00:59:38.688151 progress 10 % (6 MB)
100 00:59:38.890735 progress 15 % (9 MB)
101 00:59:39.053170 progress 20 % (13 MB)
102 00:59:39.229370 progress 25 % (16 MB)
103 00:59:39.429040 progress 30 % (19 MB)
104 00:59:39.546192 progress 35 % (23 MB)
105 00:59:39.641967 progress 40 % (26 MB)
106 00:59:39.841441 progress 45 % (29 MB)
107 00:59:40.049969 progress 50 % (32 MB)
108 00:59:40.255226 progress 55 % (36 MB)
109 00:59:40.473035 progress 60 % (39 MB)
110 00:59:40.660212 progress 65 % (42 MB)
111 00:59:40.854057 progress 70 % (46 MB)
112 00:59:41.044885 progress 75 % (49 MB)
113 00:59:41.256375 progress 80 % (52 MB)
114 00:59:41.441993 progress 85 % (56 MB)
115 00:59:41.631623 progress 90 % (59 MB)
116 00:59:41.832535 progress 95 % (62 MB)
117 00:59:42.031466 progress 100 % (65 MB)
118 00:59:42.037378 65 MB downloaded in 3.75 s (17.57 MB/s)
119 00:59:42.037625 end: 1.4.1 http-download (duration 00:00:04) [common]
121 00:59:42.037894 end: 1.4 download-retry (duration 00:00:04) [common]
122 00:59:42.037985 start: 1.5 download-retry (timeout 00:09:56) [common]
123 00:59:42.038075 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 00:59:42.038232 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:59:42.038307 saving as /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/modules/modules.tar
126 00:59:42.038370 total size: 8617404 (8 MB)
127 00:59:42.038433 Using unxz to decompress xz
128 00:59:42.042664 progress 0 % (0 MB)
129 00:59:42.061394 progress 5 % (0 MB)
130 00:59:42.088503 progress 10 % (0 MB)
131 00:59:42.117761 progress 15 % (1 MB)
132 00:59:42.141568 progress 20 % (1 MB)
133 00:59:42.164931 progress 25 % (2 MB)
134 00:59:42.188288 progress 30 % (2 MB)
135 00:59:42.214422 progress 35 % (2 MB)
136 00:59:42.239056 progress 40 % (3 MB)
137 00:59:42.261520 progress 45 % (3 MB)
138 00:59:42.285552 progress 50 % (4 MB)
139 00:59:42.310471 progress 55 % (4 MB)
140 00:59:42.334749 progress 60 % (4 MB)
141 00:59:42.358546 progress 65 % (5 MB)
142 00:59:42.385079 progress 70 % (5 MB)
143 00:59:42.408679 progress 75 % (6 MB)
144 00:59:42.434433 progress 80 % (6 MB)
145 00:59:42.458642 progress 85 % (7 MB)
146 00:59:42.483869 progress 90 % (7 MB)
147 00:59:42.509157 progress 95 % (7 MB)
148 00:59:42.534466 progress 100 % (8 MB)
149 00:59:42.540403 8 MB downloaded in 0.50 s (16.37 MB/s)
150 00:59:42.540643 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:59:42.540921 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:59:42.541020 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 00:59:42.541114 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 00:59:44.066138 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368620/extract-nfsrootfs-3_3i9sun
156 00:59:44.066357 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 00:59:44.066458 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 00:59:44.066621 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq
159 00:59:44.066758 makedir: /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin
160 00:59:44.066867 makedir: /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/tests
161 00:59:44.066965 makedir: /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/results
162 00:59:44.067066 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-add-keys
163 00:59:44.067204 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-add-sources
164 00:59:44.067331 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-background-process-start
165 00:59:44.067460 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-background-process-stop
166 00:59:44.067585 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-common-functions
167 00:59:44.067709 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-echo-ipv4
168 00:59:44.067834 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-install-packages
169 00:59:44.067957 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-installed-packages
170 00:59:44.068079 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-os-build
171 00:59:44.068202 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-probe-channel
172 00:59:44.068327 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-probe-ip
173 00:59:44.068449 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-target-ip
174 00:59:44.068572 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-target-mac
175 00:59:44.068693 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-target-storage
176 00:59:44.068819 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-test-case
177 00:59:44.068942 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-test-event
178 00:59:44.069065 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-test-feedback
179 00:59:44.069187 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-test-raise
180 00:59:44.069309 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-test-reference
181 00:59:44.069432 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-test-runner
182 00:59:44.069553 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-test-set
183 00:59:44.069677 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-test-shell
184 00:59:44.069801 Updating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-install-packages (oe)
185 00:59:44.069952 Updating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/bin/lava-installed-packages (oe)
186 00:59:44.070078 Creating /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/environment
187 00:59:44.070187 LAVA metadata
188 00:59:44.070255 - LAVA_JOB_ID=14368620
189 00:59:44.070318 - LAVA_DISPATCHER_IP=192.168.201.1
190 00:59:44.070417 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 00:59:44.070484 skipped lava-vland-overlay
192 00:59:44.070558 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 00:59:44.070637 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 00:59:44.070698 skipped lava-multinode-overlay
195 00:59:44.070770 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 00:59:44.070848 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 00:59:44.070921 Loading test definitions
198 00:59:44.071009 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 00:59:44.071079 Using /lava-14368620 at stage 0
200 00:59:44.071367 uuid=14368620_1.6.2.3.1 testdef=None
201 00:59:44.071456 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 00:59:44.071540 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 00:59:44.072025 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 00:59:44.072243 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 00:59:44.072838 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 00:59:44.073063 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 00:59:44.073643 runner path: /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/0/tests/0_lc-compliance test_uuid 14368620_1.6.2.3.1
210 00:59:44.073800 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 00:59:44.074001 Creating lava-test-runner.conf files
213 00:59:44.074063 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368620/lava-overlay-m4q279qq/lava-14368620/0 for stage 0
214 00:59:44.074151 - 0_lc-compliance
215 00:59:44.074253 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 00:59:44.074338 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 00:59:44.080411 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 00:59:44.080513 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 00:59:44.080615 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 00:59:44.080705 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 00:59:44.080791 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 00:59:44.243513 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 00:59:44.243929 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 00:59:44.244042 extracting modules file /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368620/extract-nfsrootfs-3_3i9sun
225 00:59:44.458783 extracting modules file /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368620/extract-overlay-ramdisk-22wrpzzb/ramdisk
226 00:59:44.675682 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 00:59:44.675884 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 00:59:44.675983 [common] Applying overlay to NFS
229 00:59:44.676054 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368620/compress-overlay-icheg7m8/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368620/extract-nfsrootfs-3_3i9sun
230 00:59:44.682592 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 00:59:44.682705 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 00:59:44.682794 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 00:59:44.682887 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 00:59:44.682966 Building ramdisk /var/lib/lava/dispatcher/tmp/14368620/extract-overlay-ramdisk-22wrpzzb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368620/extract-overlay-ramdisk-22wrpzzb/ramdisk
235 00:59:44.985350 >> 130405 blocks
236 00:59:46.994432 rename /var/lib/lava/dispatcher/tmp/14368620/extract-overlay-ramdisk-22wrpzzb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/ramdisk/ramdisk.cpio.gz
237 00:59:46.994936 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 00:59:46.995064 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 00:59:46.995169 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 00:59:46.995277 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/kernel/Image']
241 00:59:59.893529 Returned 0 in 12 seconds
242 00:59:59.994533 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/kernel/image.itb
243 01:00:00.386887 output: FIT description: Kernel Image image with one or more FDT blobs
244 01:00:00.387260 output: Created: Sun Jun 16 02:00:00 2024
245 01:00:00.387336 output: Image 0 (kernel-1)
246 01:00:00.387400 output: Description:
247 01:00:00.387463 output: Created: Sun Jun 16 02:00:00 2024
248 01:00:00.387523 output: Type: Kernel Image
249 01:00:00.387581 output: Compression: lzma compressed
250 01:00:00.387641 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
251 01:00:00.387699 output: Architecture: AArch64
252 01:00:00.387759 output: OS: Linux
253 01:00:00.387820 output: Load Address: 0x00000000
254 01:00:00.387878 output: Entry Point: 0x00000000
255 01:00:00.387937 output: Hash algo: crc32
256 01:00:00.387995 output: Hash value: f6f06660
257 01:00:00.388052 output: Image 1 (fdt-1)
258 01:00:00.388109 output: Description: mt8192-asurada-spherion-r0
259 01:00:00.388162 output: Created: Sun Jun 16 02:00:00 2024
260 01:00:00.388220 output: Type: Flat Device Tree
261 01:00:00.388274 output: Compression: uncompressed
262 01:00:00.388327 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 01:00:00.388380 output: Architecture: AArch64
264 01:00:00.388433 output: Hash algo: crc32
265 01:00:00.388485 output: Hash value: 0f8e4d2e
266 01:00:00.388538 output: Image 2 (ramdisk-1)
267 01:00:00.388590 output: Description: unavailable
268 01:00:00.388643 output: Created: Sun Jun 16 02:00:00 2024
269 01:00:00.388696 output: Type: RAMDisk Image
270 01:00:00.388749 output: Compression: Unknown Compression
271 01:00:00.388802 output: Data Size: 18743351 Bytes = 18304.05 KiB = 17.88 MiB
272 01:00:00.388855 output: Architecture: AArch64
273 01:00:00.388907 output: OS: Linux
274 01:00:00.388959 output: Load Address: unavailable
275 01:00:00.389012 output: Entry Point: unavailable
276 01:00:00.389064 output: Hash algo: crc32
277 01:00:00.389116 output: Hash value: 59c29d67
278 01:00:00.389169 output: Default Configuration: 'conf-1'
279 01:00:00.389221 output: Configuration 0 (conf-1)
280 01:00:00.389290 output: Description: mt8192-asurada-spherion-r0
281 01:00:00.389346 output: Kernel: kernel-1
282 01:00:00.389399 output: Init Ramdisk: ramdisk-1
283 01:00:00.389452 output: FDT: fdt-1
284 01:00:00.389505 output: Loadables: kernel-1
285 01:00:00.389557 output:
286 01:00:00.389760 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 01:00:00.389860 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 01:00:00.389967 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 01:00:00.390063 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:38) [common]
290 01:00:00.390143 No LXC device requested
291 01:00:00.390234 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 01:00:00.390358 start: 1.8 deploy-device-env (timeout 00:09:38) [common]
293 01:00:00.390436 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 01:00:00.390505 Checking files for TFTP limit of 4294967296 bytes.
295 01:00:00.391001 end: 1 tftp-deploy (duration 00:00:22) [common]
296 01:00:00.391105 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 01:00:00.391200 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 01:00:00.391329 substitutions:
299 01:00:00.391396 - {DTB}: 14368620/tftp-deploy-he9vtqyu/dtb/mt8192-asurada-spherion-r0.dtb
300 01:00:00.391464 - {INITRD}: 14368620/tftp-deploy-he9vtqyu/ramdisk/ramdisk.cpio.gz
301 01:00:00.391524 - {KERNEL}: 14368620/tftp-deploy-he9vtqyu/kernel/Image
302 01:00:00.391583 - {LAVA_MAC}: None
303 01:00:00.391640 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368620/extract-nfsrootfs-3_3i9sun
304 01:00:00.391696 - {NFS_SERVER_IP}: 192.168.201.1
305 01:00:00.391751 - {PRESEED_CONFIG}: None
306 01:00:00.391804 - {PRESEED_LOCAL}: None
307 01:00:00.391859 - {RAMDISK}: 14368620/tftp-deploy-he9vtqyu/ramdisk/ramdisk.cpio.gz
308 01:00:00.391913 - {ROOT_PART}: None
309 01:00:00.391967 - {ROOT}: None
310 01:00:00.392021 - {SERVER_IP}: 192.168.201.1
311 01:00:00.392074 - {TEE}: None
312 01:00:00.392128 Parsed boot commands:
313 01:00:00.392182 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 01:00:00.392361 Parsed boot commands: tftpboot 192.168.201.1 14368620/tftp-deploy-he9vtqyu/kernel/image.itb 14368620/tftp-deploy-he9vtqyu/kernel/cmdline
315 01:00:00.392449 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 01:00:00.392537 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 01:00:00.392627 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 01:00:00.392715 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 01:00:00.392791 Not connected, no need to disconnect.
320 01:00:00.392867 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 01:00:00.392946 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 01:00:00.393016 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
323 01:00:00.396746 Setting prompt string to ['lava-test: # ']
324 01:00:00.397106 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 01:00:00.397212 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 01:00:00.397316 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 01:00:00.397405 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 01:00:00.397585 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
329 01:00:14.542830 Returned 0 in 14 seconds
330 01:00:14.643680 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
332 01:00:14.644386 end: 2.2.2 reset-device (duration 00:00:14) [common]
333 01:00:14.644628 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
334 01:00:14.644815 Setting prompt string to 'Starting depthcharge on Spherion...'
335 01:00:14.644960 Changing prompt to 'Starting depthcharge on Spherion...'
336 01:00:14.645103 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
337 01:00:14.645990 [Enter `^Ec?' for help]
338 01:00:14.646218
339 01:00:14.646392 F0: 102B 0000
340 01:00:14.646557
341 01:00:14.646713 F3: 1001 0000 [0200]
342 01:00:14.646862
343 01:00:14.647012 F3: 1001 0000
344 01:00:14.647160
345 01:00:14.647301 F7: 102D 0000
346 01:00:14.647441
347 01:00:14.647578 F1: 0000 0000
348 01:00:14.647716
349 01:00:14.647850 V0: 0000 0000 [0001]
350 01:00:14.647985
351 01:00:14.648120 00: 0007 8000
352 01:00:14.648264
353 01:00:14.648397 01: 0000 0000
354 01:00:14.648536
355 01:00:14.648670 BP: 0C00 0209 [0000]
356 01:00:14.648806
357 01:00:14.648938 G0: 1182 0000
358 01:00:14.649071
359 01:00:14.649203 EC: 0000 0021 [4000]
360 01:00:14.649335
361 01:00:14.649468 S7: 0000 0000 [0000]
362 01:00:14.649601
363 01:00:14.649734 CC: 0000 0000 [0001]
364 01:00:14.649866
365 01:00:14.649997 T0: 0000 0040 [010F]
366 01:00:14.650130
367 01:00:14.650278 Jump to BL
368 01:00:14.650430
369 01:00:14.650587
370 01:00:14.650745
371 01:00:14.650905 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
372 01:00:14.651074 ARM64: Exception handlers installed.
373 01:00:14.651244 ARM64: Testing exception
374 01:00:14.651405 ARM64: Done test exception
375 01:00:14.651565 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
376 01:00:14.651728 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
377 01:00:14.651891 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
378 01:00:14.652052 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
379 01:00:14.652216 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
380 01:00:14.652378 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
381 01:00:14.652540 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
382 01:00:14.652702 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
383 01:00:14.652863 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
384 01:00:14.653024 WDT: Last reset was cold boot
385 01:00:14.653184 SPI1(PAD0) initialized at 2873684 Hz
386 01:00:14.653346 SPI5(PAD0) initialized at 992727 Hz
387 01:00:14.653506 VBOOT: Loading verstage.
388 01:00:14.653667 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
389 01:00:14.653829 FMAP: Found "FLASH" version 1.1 at 0x20000.
390 01:00:14.653990 FMAP: base = 0x0 size = 0x800000 #areas = 25
391 01:00:14.654152 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
392 01:00:14.654326 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
393 01:00:14.654489 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
394 01:00:14.654653 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
395 01:00:14.654813
396 01:00:14.654972
397 01:00:14.655132 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
398 01:00:14.655296 ARM64: Exception handlers installed.
399 01:00:14.655457 ARM64: Testing exception
400 01:00:14.655618 ARM64: Done test exception
401 01:00:14.655777 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
402 01:00:14.655939 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
403 01:00:14.656101 Probing TPM: . done!
404 01:00:14.656261 TPM ready after 0 ms
405 01:00:14.656421 Connected to device vid:did:rid of 1ae0:0028:00
406 01:00:14.656583 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
407 01:00:14.656745 Initialized TPM device CR50 revision 0
408 01:00:14.656906 tlcl_send_startup: Startup return code is 0
409 01:00:14.657068 TPM: setup succeeded
410 01:00:14.657227 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
411 01:00:14.657388 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
412 01:00:14.657549 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
413 01:00:14.657710 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 01:00:14.657870 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
415 01:00:14.658033 in-header: 03 07 00 00 08 00 00 00
416 01:00:14.658204 in-data: aa e4 47 04 13 02 00 00
417 01:00:14.658367 Chrome EC: UHEPI supported
418 01:00:14.658527 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
419 01:00:14.658689 in-header: 03 a9 00 00 08 00 00 00
420 01:00:14.658847 in-data: 84 60 60 08 00 00 00 00
421 01:00:14.659005 Phase 1
422 01:00:14.659166 FMAP: area GBB found @ 3f5000 (12032 bytes)
423 01:00:14.659327 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
424 01:00:14.659489 VB2:vb2_check_recovery() Recovery was requested manually
425 01:00:14.659649 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
426 01:00:14.659810 Recovery requested (1009000e)
427 01:00:14.659971 TPM: Extending digest for VBOOT: boot mode into PCR 0
428 01:00:14.660133 tlcl_extend: response is 0
429 01:00:14.660293 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
430 01:00:14.660454 tlcl_extend: response is 0
431 01:00:14.660613 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
432 01:00:14.660772 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
433 01:00:14.660933 BS: bootblock times (exec / console): total (unknown) / 148 ms
434 01:00:14.661095
435 01:00:14.661253
436 01:00:14.661412 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
437 01:00:14.661575 ARM64: Exception handlers installed.
438 01:00:14.661734 ARM64: Testing exception
439 01:00:14.661911 ARM64: Done test exception
440 01:00:14.662093 pmic_efuse_setting: Set efuses in 11 msecs
441 01:00:14.662288 pmwrap_interface_init: Select PMIF_VLD_RDY
442 01:00:14.662453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
443 01:00:14.662877 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
444 01:00:14.663066 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
445 01:00:14.663234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
446 01:00:14.663398 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
447 01:00:14.663561 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
448 01:00:14.663724 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
449 01:00:14.663887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
450 01:00:14.664087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
451 01:00:14.664253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
452 01:00:14.664417 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
453 01:00:14.664578 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
454 01:00:14.664740 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
455 01:00:14.664901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
456 01:00:14.665063 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
457 01:00:14.665223 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
458 01:00:14.665517 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
459 01:00:14.665772 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
460 01:00:14.666023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
461 01:00:14.666300 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
462 01:00:14.666551 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
463 01:00:14.666801 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
464 01:00:14.667051 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
465 01:00:14.667299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
466 01:00:14.667549 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
467 01:00:14.667799 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
468 01:00:14.668047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
469 01:00:14.668296 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
470 01:00:14.668552 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
471 01:00:14.668804 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
472 01:00:14.669054 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
473 01:00:14.669304 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
474 01:00:14.669552 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
475 01:00:14.669800 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
476 01:00:14.670050 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
477 01:00:14.670276 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
478 01:00:14.670444 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
479 01:00:14.670607 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
480 01:00:14.670769 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
481 01:00:14.670930 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
482 01:00:14.671092 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
483 01:00:14.671253 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
484 01:00:14.671412 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
485 01:00:14.671572 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
486 01:00:14.671733 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
487 01:00:14.671912 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
488 01:00:14.672154 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
489 01:00:14.672403 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
490 01:00:14.672575 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
491 01:00:14.672737 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
492 01:00:14.672900 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
493 01:00:14.673061 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
494 01:00:14.673225 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
495 01:00:14.673389 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
496 01:00:14.673552 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
497 01:00:14.673716 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
498 01:00:14.673877 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
499 01:00:14.674039 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
500 01:00:14.674220 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 01:00:14.674386 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x29
502 01:00:14.674548 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
503 01:00:14.674712 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
504 01:00:14.674873 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
505 01:00:14.675032 [RTC]rtc_get_frequency_meter,154: input=15, output=834
506 01:00:14.675192 [RTC]rtc_get_frequency_meter,154: input=7, output=709
507 01:00:14.675364 [RTC]rtc_get_frequency_meter,154: input=11, output=772
508 01:00:14.675522 [RTC]rtc_get_frequency_meter,154: input=13, output=803
509 01:00:14.675649 [RTC]rtc_get_frequency_meter,154: input=12, output=787
510 01:00:14.675776 [RTC]rtc_get_frequency_meter,154: input=12, output=788
511 01:00:14.675904 [RTC]rtc_get_frequency_meter,154: input=13, output=804
512 01:00:14.676031 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
513 01:00:14.676397 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
514 01:00:14.676660 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
515 01:00:14.676943 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
516 01:00:14.677225 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
517 01:00:14.677458 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
518 01:00:14.677661 ADC[4]: Raw value=904879 ID=7
519 01:00:14.677862 ADC[3]: Raw value=213282 ID=1
520 01:00:14.678060 RAM Code: 0x71
521 01:00:14.678281 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
522 01:00:14.678484 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
523 01:00:14.678692 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
524 01:00:14.678896 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
525 01:00:14.679094 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
526 01:00:14.679294 in-header: 03 07 00 00 08 00 00 00
527 01:00:14.679491 in-data: aa e4 47 04 13 02 00 00
528 01:00:14.679688 Chrome EC: UHEPI supported
529 01:00:14.679887 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
530 01:00:14.680086 in-header: 03 a9 00 00 08 00 00 00
531 01:00:14.680283 in-data: 84 60 60 08 00 00 00 00
532 01:00:14.680477 MRC: failed to locate region type 0.
533 01:00:14.680642 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
534 01:00:14.680806 DRAM-K: Running full calibration
535 01:00:14.680971 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
536 01:00:14.681134 header.status = 0x0
537 01:00:14.681297 header.version = 0x6 (expected: 0x6)
538 01:00:14.681460 header.size = 0xd00 (expected: 0xd00)
539 01:00:14.681622 header.flags = 0x0
540 01:00:14.681786 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
541 01:00:14.681959 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
542 01:00:14.682137 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
543 01:00:14.682270 dram_init: ddr_geometry: 2
544 01:00:14.682378 [EMI] MDL number = 2
545 01:00:14.682485 [EMI] Get MDL freq = 0
546 01:00:14.682608 dram_init: ddr_type: 0
547 01:00:14.682716 is_discrete_lpddr4: 1
548 01:00:14.682821 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
549 01:00:14.682951
550 01:00:14.683060
551 01:00:14.683167 [Bian_co] ETT version 0.0.0.1
552 01:00:14.683285 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
553 01:00:14.683404
554 01:00:14.683511 dramc_set_vcore_voltage set vcore to 650000
555 01:00:14.683617 Read voltage for 800, 4
556 01:00:14.683732 Vio18 = 0
557 01:00:14.683838 Vcore = 650000
558 01:00:14.683943 Vdram = 0
559 01:00:14.684048 Vddq = 0
560 01:00:14.684153 Vmddr = 0
561 01:00:14.684258 dram_init: config_dvfs: 1
562 01:00:14.684364 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
563 01:00:14.684470 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
564 01:00:14.684576 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
565 01:00:14.684683 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
566 01:00:14.684790 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
567 01:00:14.684895 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
568 01:00:14.685001 MEM_TYPE=3, freq_sel=18
569 01:00:14.685104 sv_algorithm_assistance_LP4_1600
570 01:00:14.685209 ============ PULL DRAM RESETB DOWN ============
571 01:00:14.685315 ========== PULL DRAM RESETB DOWN end =========
572 01:00:14.685429 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
573 01:00:14.685530 ===================================
574 01:00:14.685622 LPDDR4 DRAM CONFIGURATION
575 01:00:14.685711 ===================================
576 01:00:14.685802 EX_ROW_EN[0] = 0x0
577 01:00:14.685892 EX_ROW_EN[1] = 0x0
578 01:00:14.685983 LP4Y_EN = 0x0
579 01:00:14.686072 WORK_FSP = 0x0
580 01:00:14.686171 WL = 0x2
581 01:00:14.686266 RL = 0x2
582 01:00:14.686356 BL = 0x2
583 01:00:14.686445 RPST = 0x0
584 01:00:14.686535 RD_PRE = 0x0
585 01:00:14.686624 WR_PRE = 0x1
586 01:00:14.686713 WR_PST = 0x0
587 01:00:14.686802 DBI_WR = 0x0
588 01:00:14.686891 DBI_RD = 0x0
589 01:00:14.686980 OTF = 0x1
590 01:00:14.687070 ===================================
591 01:00:14.687160 ===================================
592 01:00:14.687250 ANA top config
593 01:00:14.687339 ===================================
594 01:00:14.687429 DLL_ASYNC_EN = 0
595 01:00:14.687518 ALL_SLAVE_EN = 1
596 01:00:14.687607 NEW_RANK_MODE = 1
597 01:00:14.687697 DLL_IDLE_MODE = 1
598 01:00:14.687786 LP45_APHY_COMB_EN = 1
599 01:00:14.687875 TX_ODT_DIS = 1
600 01:00:14.687964 NEW_8X_MODE = 1
601 01:00:14.688054 ===================================
602 01:00:14.688143 ===================================
603 01:00:14.688232 data_rate = 1600
604 01:00:14.688321 CKR = 1
605 01:00:14.688419 DQ_P2S_RATIO = 8
606 01:00:14.688509 ===================================
607 01:00:14.688598 CA_P2S_RATIO = 8
608 01:00:14.688702 DQ_CA_OPEN = 0
609 01:00:14.688793 DQ_SEMI_OPEN = 0
610 01:00:14.688891 CA_SEMI_OPEN = 0
611 01:00:14.688983 CA_FULL_RATE = 0
612 01:00:14.689073 DQ_CKDIV4_EN = 1
613 01:00:14.689163 CA_CKDIV4_EN = 1
614 01:00:14.689253 CA_PREDIV_EN = 0
615 01:00:14.689342 PH8_DLY = 0
616 01:00:14.689432 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
617 01:00:14.689521 DQ_AAMCK_DIV = 4
618 01:00:14.689610 CA_AAMCK_DIV = 4
619 01:00:14.689700 CA_ADMCK_DIV = 4
620 01:00:14.689790 DQ_TRACK_CA_EN = 0
621 01:00:14.689879 CA_PICK = 800
622 01:00:14.689969 CA_MCKIO = 800
623 01:00:14.690060 MCKIO_SEMI = 0
624 01:00:14.690149 PLL_FREQ = 3068
625 01:00:14.690255 DQ_UI_PI_RATIO = 32
626 01:00:14.690346 CA_UI_PI_RATIO = 0
627 01:00:14.690443 ===================================
628 01:00:14.690521 ===================================
629 01:00:14.690599 memory_type:LPDDR4
630 01:00:14.690678 GP_NUM : 10
631 01:00:14.690756 SRAM_EN : 1
632 01:00:14.690835 MD32_EN : 0
633 01:00:14.691147 ===================================
634 01:00:14.691298 [ANA_INIT] >>>>>>>>>>>>>>
635 01:00:14.691458 <<<<<< [CONFIGURE PHASE]: ANA_TX
636 01:00:14.691623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
637 01:00:14.691783 ===================================
638 01:00:14.691930 data_rate = 1600,PCW = 0X7600
639 01:00:14.692061 ===================================
640 01:00:14.692186 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
641 01:00:14.692311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
642 01:00:14.692436 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 01:00:14.692559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
644 01:00:14.692682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
645 01:00:14.692804 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
646 01:00:14.692926 [ANA_INIT] flow start
647 01:00:14.693047 [ANA_INIT] PLL >>>>>>>>
648 01:00:14.693168 [ANA_INIT] PLL <<<<<<<<
649 01:00:14.693289 [ANA_INIT] MIDPI >>>>>>>>
650 01:00:14.693410 [ANA_INIT] MIDPI <<<<<<<<
651 01:00:14.693532 [ANA_INIT] DLL >>>>>>>>
652 01:00:14.693652 [ANA_INIT] flow end
653 01:00:14.693774 ============ LP4 DIFF to SE enter ============
654 01:00:14.693896 ============ LP4 DIFF to SE exit ============
655 01:00:14.694018 [ANA_INIT] <<<<<<<<<<<<<
656 01:00:14.694152 [Flow] Enable top DCM control >>>>>
657 01:00:14.694252 [Flow] Enable top DCM control <<<<<
658 01:00:14.694332 Enable DLL master slave shuffle
659 01:00:14.694411 ==============================================================
660 01:00:14.694491 Gating Mode config
661 01:00:14.694570 ==============================================================
662 01:00:14.694649 Config description:
663 01:00:14.694728 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
664 01:00:14.694808 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
665 01:00:14.694887 SELPH_MODE 0: By rank 1: By Phase
666 01:00:14.694967 ==============================================================
667 01:00:14.695046 GAT_TRACK_EN = 1
668 01:00:14.695125 RX_GATING_MODE = 2
669 01:00:14.695210 RX_GATING_TRACK_MODE = 2
670 01:00:14.695290 SELPH_MODE = 1
671 01:00:14.695369 PICG_EARLY_EN = 1
672 01:00:14.695455 VALID_LAT_VALUE = 1
673 01:00:14.695524 ==============================================================
674 01:00:14.695594 Enter into Gating configuration >>>>
675 01:00:14.695664 Exit from Gating configuration <<<<
676 01:00:14.695733 Enter into DVFS_PRE_config >>>>>
677 01:00:14.695802 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
678 01:00:14.695875 Exit from DVFS_PRE_config <<<<<
679 01:00:14.695944 Enter into PICG configuration >>>>
680 01:00:14.696014 Exit from PICG configuration <<<<
681 01:00:14.696082 [RX_INPUT] configuration >>>>>
682 01:00:14.696150 [RX_INPUT] configuration <<<<<
683 01:00:14.696242 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
684 01:00:14.696317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
685 01:00:14.696388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
686 01:00:14.696459 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
687 01:00:14.696529 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
688 01:00:14.696598 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
689 01:00:14.696667 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
690 01:00:14.696737 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
691 01:00:14.696807 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
692 01:00:14.696876 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
693 01:00:14.696946 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
694 01:00:14.697015 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
695 01:00:14.697085 ===================================
696 01:00:14.697154 LPDDR4 DRAM CONFIGURATION
697 01:00:14.697223 ===================================
698 01:00:14.697293 EX_ROW_EN[0] = 0x0
699 01:00:14.697361 EX_ROW_EN[1] = 0x0
700 01:00:14.697430 LP4Y_EN = 0x0
701 01:00:14.697499 WORK_FSP = 0x0
702 01:00:14.697568 WL = 0x2
703 01:00:14.697636 RL = 0x2
704 01:00:14.697705 BL = 0x2
705 01:00:14.697773 RPST = 0x0
706 01:00:14.697841 RD_PRE = 0x0
707 01:00:14.697909 WR_PRE = 0x1
708 01:00:14.697977 WR_PST = 0x0
709 01:00:14.698045 DBI_WR = 0x0
710 01:00:14.698114 DBI_RD = 0x0
711 01:00:14.698192 OTF = 0x1
712 01:00:14.698302 ===================================
713 01:00:14.698402 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
714 01:00:14.698475 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
715 01:00:14.698551 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
716 01:00:14.698624 ===================================
717 01:00:14.698695 LPDDR4 DRAM CONFIGURATION
718 01:00:14.698764 ===================================
719 01:00:14.698833 EX_ROW_EN[0] = 0x10
720 01:00:14.698903 EX_ROW_EN[1] = 0x0
721 01:00:14.698972 LP4Y_EN = 0x0
722 01:00:14.699041 WORK_FSP = 0x0
723 01:00:14.699110 WL = 0x2
724 01:00:14.699180 RL = 0x2
725 01:00:14.699248 BL = 0x2
726 01:00:14.699317 RPST = 0x0
727 01:00:14.699386 RD_PRE = 0x0
728 01:00:14.699455 WR_PRE = 0x1
729 01:00:14.699524 WR_PST = 0x0
730 01:00:14.699592 DBI_WR = 0x0
731 01:00:14.699661 DBI_RD = 0x0
732 01:00:14.699730 OTF = 0x1
733 01:00:14.699799 ===================================
734 01:00:14.699869 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
735 01:00:14.699939 nWR fixed to 40
736 01:00:14.700009 [ModeRegInit_LP4] CH0 RK0
737 01:00:14.700077 [ModeRegInit_LP4] CH0 RK1
738 01:00:14.700146 [ModeRegInit_LP4] CH1 RK0
739 01:00:14.700218 [ModeRegInit_LP4] CH1 RK1
740 01:00:14.700288 match AC timing 13
741 01:00:14.700557 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
742 01:00:14.700671 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
743 01:00:14.700799 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
744 01:00:14.700927 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
745 01:00:14.701054 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
746 01:00:14.701163 [EMI DOE] emi_dcm 0
747 01:00:14.701266 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
748 01:00:14.701338 ==
749 01:00:14.701438 Dram Type= 6, Freq= 0, CH_0, rank 0
750 01:00:14.701538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
751 01:00:14.701606 ==
752 01:00:14.701670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
753 01:00:14.701736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
754 01:00:14.701799 [CA 0] Center 37 (7~68) winsize 62
755 01:00:14.701862 [CA 1] Center 37 (6~68) winsize 63
756 01:00:14.701929 [CA 2] Center 34 (4~65) winsize 62
757 01:00:14.701993 [CA 3] Center 34 (4~65) winsize 62
758 01:00:14.702056 [CA 4] Center 33 (3~64) winsize 62
759 01:00:14.702119 [CA 5] Center 33 (3~64) winsize 62
760 01:00:14.702191
761 01:00:14.702260 [CmdBusTrainingLP45] Vref(ca) range 1: 32
762 01:00:14.702328
763 01:00:14.702390 [CATrainingPosCal] consider 1 rank data
764 01:00:14.702454 u2DelayCellTimex100 = 270/100 ps
765 01:00:14.702516 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
766 01:00:14.702579 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
767 01:00:14.702642 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
768 01:00:14.702704 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
769 01:00:14.702766 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
770 01:00:14.702828 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
771 01:00:14.702890
772 01:00:14.702952 CA PerBit enable=1, Macro0, CA PI delay=33
773 01:00:14.703014
774 01:00:14.703075 [CBTSetCACLKResult] CA Dly = 33
775 01:00:14.703137 CS Dly: 6 (0~37)
776 01:00:14.703199 ==
777 01:00:14.703261 Dram Type= 6, Freq= 0, CH_0, rank 1
778 01:00:14.703323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 01:00:14.703386 ==
780 01:00:14.703448 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
781 01:00:14.703510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
782 01:00:14.703574 [CA 0] Center 37 (6~68) winsize 63
783 01:00:14.703636 [CA 1] Center 37 (6~68) winsize 63
784 01:00:14.703698 [CA 2] Center 34 (4~65) winsize 62
785 01:00:14.703761 [CA 3] Center 34 (4~65) winsize 62
786 01:00:14.703823 [CA 4] Center 33 (3~64) winsize 62
787 01:00:14.703885 [CA 5] Center 33 (3~64) winsize 62
788 01:00:14.703947
789 01:00:14.704009 [CmdBusTrainingLP45] Vref(ca) range 1: 34
790 01:00:14.704071
791 01:00:14.704133 [CATrainingPosCal] consider 2 rank data
792 01:00:14.704195 u2DelayCellTimex100 = 270/100 ps
793 01:00:14.704257 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
794 01:00:14.704319 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
795 01:00:14.704381 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
796 01:00:14.704444 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
797 01:00:14.704505 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
798 01:00:14.704567 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
799 01:00:14.704629
800 01:00:14.704691 CA PerBit enable=1, Macro0, CA PI delay=33
801 01:00:14.704753
802 01:00:14.704815 [CBTSetCACLKResult] CA Dly = 33
803 01:00:14.704877 CS Dly: 6 (0~38)
804 01:00:14.704939
805 01:00:14.705000 ----->DramcWriteLeveling(PI) begin...
806 01:00:14.705065 ==
807 01:00:14.705127 Dram Type= 6, Freq= 0, CH_0, rank 0
808 01:00:14.705190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
809 01:00:14.705252 ==
810 01:00:14.705314 Write leveling (Byte 0): 33 => 33
811 01:00:14.705377 Write leveling (Byte 1): 33 => 33
812 01:00:14.705451 DramcWriteLeveling(PI) end<-----
813 01:00:14.705513
814 01:00:14.705570 ==
815 01:00:14.705627 Dram Type= 6, Freq= 0, CH_0, rank 0
816 01:00:14.705684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
817 01:00:14.705740 ==
818 01:00:14.705797 [Gating] SW mode calibration
819 01:00:14.705867 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
820 01:00:14.705927 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
821 01:00:14.705985 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
822 01:00:14.706042 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
823 01:00:14.706099 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
824 01:00:14.706156 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
825 01:00:14.706219 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 01:00:14.706276 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 01:00:14.706333 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 01:00:14.706390 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 01:00:14.706446 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 01:00:14.706503 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 01:00:14.706560 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 01:00:14.706616 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 01:00:14.706673 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 01:00:14.706730 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 01:00:14.706786 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 01:00:14.706843 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 01:00:14.706899 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 01:00:14.706956 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 01:00:14.707012 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
840 01:00:14.707068 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
841 01:00:14.707125 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 01:00:14.707182 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 01:00:14.707238 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 01:00:14.707296 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 01:00:14.707352 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 01:00:14.707409 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
847 01:00:14.707466 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
848 01:00:14.707523 0 9 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
849 01:00:14.707776 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 01:00:14.707874 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 01:00:14.707990 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 01:00:14.708104 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 01:00:14.708218 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 01:00:14.708318 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
855 01:00:14.708414 0 10 8 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 1)
856 01:00:14.708504 0 10 12 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
857 01:00:14.708593 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 01:00:14.708682 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:00:14.708743 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 01:00:14.708801 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 01:00:14.708858 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 01:00:14.708916 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
863 01:00:14.708973 0 11 8 | B1->B0 | 2828 3b3b | 1 1 | (0 0) (0 0)
864 01:00:14.709029 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
865 01:00:14.709085 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 01:00:14.709142 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 01:00:14.709198 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 01:00:14.709255 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 01:00:14.709311 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 01:00:14.709367 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 01:00:14.709424 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
872 01:00:14.709480 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 01:00:14.709536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 01:00:14.709592 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 01:00:14.709649 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 01:00:14.709705 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 01:00:14.709761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 01:00:14.709818 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 01:00:14.709874 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 01:00:14.709931 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 01:00:14.709987 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 01:00:14.710044 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 01:00:14.710099 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 01:00:14.710156 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 01:00:14.710226 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 01:00:14.710283 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 01:00:14.710339 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
888 01:00:14.710396 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 01:00:14.710463 Total UI for P1: 0, mck2ui 16
890 01:00:14.710517 best dqsien dly found for B0: ( 0, 14, 8)
891 01:00:14.710572 Total UI for P1: 0, mck2ui 16
892 01:00:14.710626 best dqsien dly found for B1: ( 0, 14, 8)
893 01:00:14.710680 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
894 01:00:14.710734 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
895 01:00:14.710787
896 01:00:14.710841 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
897 01:00:14.710895 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
898 01:00:14.710948 [Gating] SW calibration Done
899 01:00:14.711002 ==
900 01:00:14.711055 Dram Type= 6, Freq= 0, CH_0, rank 0
901 01:00:14.711110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
902 01:00:14.711165 ==
903 01:00:14.711219 RX Vref Scan: 0
904 01:00:14.711273
905 01:00:14.711325 RX Vref 0 -> 0, step: 1
906 01:00:14.711379
907 01:00:14.711432 RX Delay -130 -> 252, step: 16
908 01:00:14.711486 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
909 01:00:14.711540 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
910 01:00:14.711594 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
911 01:00:14.711647 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
912 01:00:14.711708 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
913 01:00:14.711763 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
914 01:00:14.711817 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
915 01:00:14.711871 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
916 01:00:14.711925 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
917 01:00:14.711979 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
918 01:00:14.712032 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
919 01:00:14.712086 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
920 01:00:14.712141 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
921 01:00:14.712195 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
922 01:00:14.712249 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
923 01:00:14.712303 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
924 01:00:14.712356 ==
925 01:00:14.712409 Dram Type= 6, Freq= 0, CH_0, rank 0
926 01:00:14.712464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 01:00:14.712518 ==
928 01:00:14.712572 DQS Delay:
929 01:00:14.712625 DQS0 = 0, DQS1 = 0
930 01:00:14.712680 DQM Delay:
931 01:00:14.712733 DQM0 = 85, DQM1 = 72
932 01:00:14.712787 DQ Delay:
933 01:00:14.712841 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
934 01:00:14.712895 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
935 01:00:14.712949 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
936 01:00:14.713003 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
937 01:00:14.713057
938 01:00:14.713111
939 01:00:14.713168 ==
940 01:00:14.713222 Dram Type= 6, Freq= 0, CH_0, rank 0
941 01:00:14.713276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
942 01:00:14.713331 ==
943 01:00:14.713384
944 01:00:14.713437
945 01:00:14.713490 TX Vref Scan disable
946 01:00:14.713555 == TX Byte 0 ==
947 01:00:14.713651 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
948 01:00:14.713711 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
949 01:00:14.713766 == TX Byte 1 ==
950 01:00:14.713820 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
951 01:00:14.713875 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
952 01:00:14.713929 ==
953 01:00:14.713984 Dram Type= 6, Freq= 0, CH_0, rank 0
954 01:00:14.714038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
955 01:00:14.714093 ==
956 01:00:14.714147 TX Vref=22, minBit 2, minWin=27, winSum=442
957 01:00:14.714440 TX Vref=24, minBit 4, minWin=27, winSum=446
958 01:00:14.714525 TX Vref=26, minBit 12, minWin=27, winSum=447
959 01:00:14.714635 TX Vref=28, minBit 15, minWin=27, winSum=453
960 01:00:14.714744 TX Vref=30, minBit 8, minWin=27, winSum=451
961 01:00:14.714853 TX Vref=32, minBit 7, minWin=27, winSum=448
962 01:00:14.714959 [TxChooseVref] Worse bit 15, Min win 27, Win sum 453, Final Vref 28
963 01:00:14.715048
964 01:00:14.715134 Final TX Range 1 Vref 28
965 01:00:14.715218
966 01:00:14.715301 ==
967 01:00:14.715386 Dram Type= 6, Freq= 0, CH_0, rank 0
968 01:00:14.715470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
969 01:00:14.715554 ==
970 01:00:14.715637
971 01:00:14.715720
972 01:00:14.715802 TX Vref Scan disable
973 01:00:14.715886 == TX Byte 0 ==
974 01:00:14.715969 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
975 01:00:14.716054 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
976 01:00:14.716137 == TX Byte 1 ==
977 01:00:14.716221 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
978 01:00:14.716305 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
979 01:00:14.716388
980 01:00:14.716471 [DATLAT]
981 01:00:14.716554 Freq=800, CH0 RK0
982 01:00:14.716637
983 01:00:14.716720 DATLAT Default: 0xa
984 01:00:14.716803 0, 0xFFFF, sum = 0
985 01:00:14.716888 1, 0xFFFF, sum = 0
986 01:00:14.716974 2, 0xFFFF, sum = 0
987 01:00:14.717059 3, 0xFFFF, sum = 0
988 01:00:14.717143 4, 0xFFFF, sum = 0
989 01:00:14.717228 5, 0xFFFF, sum = 0
990 01:00:14.717313 6, 0xFFFF, sum = 0
991 01:00:14.717397 7, 0xFFFF, sum = 0
992 01:00:14.717482 8, 0xFFFF, sum = 0
993 01:00:14.717571 9, 0x0, sum = 1
994 01:00:14.717661 10, 0x0, sum = 2
995 01:00:14.717747 11, 0x0, sum = 3
996 01:00:14.717832 12, 0x0, sum = 4
997 01:00:14.717917 best_step = 10
998 01:00:14.718000
999 01:00:14.718083 ==
1000 01:00:14.718172 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 01:00:14.718296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 01:00:14.718380 ==
1003 01:00:14.718464 RX Vref Scan: 1
1004 01:00:14.718546
1005 01:00:14.718629 Set Vref Range= 32 -> 127
1006 01:00:14.718712
1007 01:00:14.718795 RX Vref 32 -> 127, step: 1
1008 01:00:14.718878
1009 01:00:14.718961 RX Delay -111 -> 252, step: 8
1010 01:00:14.719045
1011 01:00:14.719128 Set Vref, RX VrefLevel [Byte0]: 32
1012 01:00:14.719213 [Byte1]: 32
1013 01:00:14.719296
1014 01:00:14.719379 Set Vref, RX VrefLevel [Byte0]: 33
1015 01:00:14.719463 [Byte1]: 33
1016 01:00:14.719546
1017 01:00:14.719630 Set Vref, RX VrefLevel [Byte0]: 34
1018 01:00:14.719714 [Byte1]: 34
1019 01:00:14.719797
1020 01:00:14.719880 Set Vref, RX VrefLevel [Byte0]: 35
1021 01:00:14.719963 [Byte1]: 35
1022 01:00:14.720046
1023 01:00:14.720129 Set Vref, RX VrefLevel [Byte0]: 36
1024 01:00:14.720213 [Byte1]: 36
1025 01:00:14.720302
1026 01:00:14.720380 Set Vref, RX VrefLevel [Byte0]: 37
1027 01:00:14.720438 [Byte1]: 37
1028 01:00:14.720493
1029 01:00:14.720547 Set Vref, RX VrefLevel [Byte0]: 38
1030 01:00:14.720602 [Byte1]: 38
1031 01:00:14.720656
1032 01:00:14.720710 Set Vref, RX VrefLevel [Byte0]: 39
1033 01:00:14.720763 [Byte1]: 39
1034 01:00:14.720817
1035 01:00:14.720870 Set Vref, RX VrefLevel [Byte0]: 40
1036 01:00:14.720923 [Byte1]: 40
1037 01:00:14.720977
1038 01:00:14.721030 Set Vref, RX VrefLevel [Byte0]: 41
1039 01:00:14.721084 [Byte1]: 41
1040 01:00:14.721137
1041 01:00:14.721190 Set Vref, RX VrefLevel [Byte0]: 42
1042 01:00:14.721243 [Byte1]: 42
1043 01:00:14.721296
1044 01:00:14.721350 Set Vref, RX VrefLevel [Byte0]: 43
1045 01:00:14.721403 [Byte1]: 43
1046 01:00:14.721456
1047 01:00:14.721509 Set Vref, RX VrefLevel [Byte0]: 44
1048 01:00:14.721563 [Byte1]: 44
1049 01:00:14.721616
1050 01:00:14.721669 Set Vref, RX VrefLevel [Byte0]: 45
1051 01:00:14.721722 [Byte1]: 45
1052 01:00:14.721775
1053 01:00:14.721828 Set Vref, RX VrefLevel [Byte0]: 46
1054 01:00:14.721881 [Byte1]: 46
1055 01:00:14.721934
1056 01:00:14.721988 Set Vref, RX VrefLevel [Byte0]: 47
1057 01:00:14.722041 [Byte1]: 47
1058 01:00:14.722095
1059 01:00:14.722148 Set Vref, RX VrefLevel [Byte0]: 48
1060 01:00:14.722244 [Byte1]: 48
1061 01:00:14.722298
1062 01:00:14.722361 Set Vref, RX VrefLevel [Byte0]: 49
1063 01:00:14.722432 [Byte1]: 49
1064 01:00:14.722516
1065 01:00:14.722573 Set Vref, RX VrefLevel [Byte0]: 50
1066 01:00:14.722628 [Byte1]: 50
1067 01:00:14.722682
1068 01:00:14.722735 Set Vref, RX VrefLevel [Byte0]: 51
1069 01:00:14.722789 [Byte1]: 51
1070 01:00:14.722842
1071 01:00:14.722896 Set Vref, RX VrefLevel [Byte0]: 52
1072 01:00:14.722950 [Byte1]: 52
1073 01:00:14.723003
1074 01:00:14.723057 Set Vref, RX VrefLevel [Byte0]: 53
1075 01:00:14.723110 [Byte1]: 53
1076 01:00:14.723163
1077 01:00:14.723216 Set Vref, RX VrefLevel [Byte0]: 54
1078 01:00:14.723269 [Byte1]: 54
1079 01:00:14.723322
1080 01:00:14.723375 Set Vref, RX VrefLevel [Byte0]: 55
1081 01:00:14.723428 [Byte1]: 55
1082 01:00:14.723481
1083 01:00:14.723534 Set Vref, RX VrefLevel [Byte0]: 56
1084 01:00:14.723588 [Byte1]: 56
1085 01:00:14.723641
1086 01:00:14.723694 Set Vref, RX VrefLevel [Byte0]: 57
1087 01:00:14.723747 [Byte1]: 57
1088 01:00:14.723800
1089 01:00:14.723853 Set Vref, RX VrefLevel [Byte0]: 58
1090 01:00:14.723906 [Byte1]: 58
1091 01:00:14.723959
1092 01:00:14.724012 Set Vref, RX VrefLevel [Byte0]: 59
1093 01:00:14.724065 [Byte1]: 59
1094 01:00:14.724118
1095 01:00:14.724171 Set Vref, RX VrefLevel [Byte0]: 60
1096 01:00:14.724224 [Byte1]: 60
1097 01:00:14.724277
1098 01:00:14.724331 Set Vref, RX VrefLevel [Byte0]: 61
1099 01:00:14.724384 [Byte1]: 61
1100 01:00:14.724437
1101 01:00:14.724490 Set Vref, RX VrefLevel [Byte0]: 62
1102 01:00:14.724543 [Byte1]: 62
1103 01:00:14.724596
1104 01:00:14.724649 Set Vref, RX VrefLevel [Byte0]: 63
1105 01:00:14.724702 [Byte1]: 63
1106 01:00:14.724754
1107 01:00:14.724807 Set Vref, RX VrefLevel [Byte0]: 64
1108 01:00:14.724860 [Byte1]: 64
1109 01:00:14.724913
1110 01:00:14.724965 Set Vref, RX VrefLevel [Byte0]: 65
1111 01:00:14.725018 [Byte1]: 65
1112 01:00:14.725071
1113 01:00:14.725124 Set Vref, RX VrefLevel [Byte0]: 66
1114 01:00:14.725177 [Byte1]: 66
1115 01:00:14.725230
1116 01:00:14.725292 Set Vref, RX VrefLevel [Byte0]: 67
1117 01:00:14.725377 [Byte1]: 67
1118 01:00:14.725459
1119 01:00:14.725542 Set Vref, RX VrefLevel [Byte0]: 68
1120 01:00:14.725625 [Byte1]: 68
1121 01:00:14.725706
1122 01:00:14.725788 Set Vref, RX VrefLevel [Byte0]: 69
1123 01:00:14.725871 [Byte1]: 69
1124 01:00:14.725952
1125 01:00:14.726242 Set Vref, RX VrefLevel [Byte0]: 70
1126 01:00:14.726359 [Byte1]: 70
1127 01:00:14.726466
1128 01:00:14.726573 Set Vref, RX VrefLevel [Byte0]: 71
1129 01:00:14.726677 [Byte1]: 71
1130 01:00:14.726768
1131 01:00:14.726861 Set Vref, RX VrefLevel [Byte0]: 72
1132 01:00:14.726945 [Byte1]: 72
1133 01:00:14.727028
1134 01:00:14.727111 Set Vref, RX VrefLevel [Byte0]: 73
1135 01:00:14.727193 [Byte1]: 73
1136 01:00:14.727275
1137 01:00:14.727358 Set Vref, RX VrefLevel [Byte0]: 74
1138 01:00:14.727441 [Byte1]: 74
1139 01:00:14.727523
1140 01:00:14.727605 Set Vref, RX VrefLevel [Byte0]: 75
1141 01:00:14.727688 [Byte1]: 75
1142 01:00:14.727770
1143 01:00:14.727852 Set Vref, RX VrefLevel [Byte0]: 76
1144 01:00:14.727935 [Byte1]: 76
1145 01:00:14.728019
1146 01:00:14.728103 Set Vref, RX VrefLevel [Byte0]: 77
1147 01:00:14.728185 [Byte1]: 77
1148 01:00:14.728267
1149 01:00:14.728350 Set Vref, RX VrefLevel [Byte0]: 78
1150 01:00:14.728432 [Byte1]: 78
1151 01:00:14.728514
1152 01:00:14.728596 Set Vref, RX VrefLevel [Byte0]: 79
1153 01:00:14.728678 [Byte1]: 79
1154 01:00:14.728761
1155 01:00:14.728843 Set Vref, RX VrefLevel [Byte0]: 80
1156 01:00:14.728926 [Byte1]: 80
1157 01:00:14.729007
1158 01:00:14.729090 Set Vref, RX VrefLevel [Byte0]: 81
1159 01:00:14.729172 [Byte1]: 81
1160 01:00:14.729254
1161 01:00:14.729336 Set Vref, RX VrefLevel [Byte0]: 82
1162 01:00:14.729418 [Byte1]: 82
1163 01:00:14.729499
1164 01:00:14.729582 Set Vref, RX VrefLevel [Byte0]: 83
1165 01:00:14.729651 [Byte1]: 83
1166 01:00:14.729706
1167 01:00:14.729766 Set Vref, RX VrefLevel [Byte0]: 84
1168 01:00:14.729821 [Byte1]: 84
1169 01:00:14.729874
1170 01:00:14.729928 Final RX Vref Byte 0 = 69 to rank0
1171 01:00:14.729982 Final RX Vref Byte 1 = 51 to rank0
1172 01:00:14.730035 Final RX Vref Byte 0 = 69 to rank1
1173 01:00:14.730089 Final RX Vref Byte 1 = 51 to rank1==
1174 01:00:14.730143 Dram Type= 6, Freq= 0, CH_0, rank 0
1175 01:00:14.730241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 01:00:14.730296 ==
1177 01:00:14.730349 DQS Delay:
1178 01:00:14.730403 DQS0 = 0, DQS1 = 0
1179 01:00:14.730456 DQM Delay:
1180 01:00:14.730509 DQM0 = 88, DQM1 = 76
1181 01:00:14.730563 DQ Delay:
1182 01:00:14.730616 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1183 01:00:14.730669 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1184 01:00:14.730722 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1185 01:00:14.730775 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1186 01:00:14.730828
1187 01:00:14.730881
1188 01:00:14.730933 [DQSOSCAuto] RK0, (LSB)MR18= 0x4122, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1189 01:00:14.730988 CH0 RK0: MR19=606, MR18=4122
1190 01:00:14.731041 CH0_RK0: MR19=0x606, MR18=0x4122, DQSOSC=393, MR23=63, INC=95, DEC=63
1191 01:00:14.731094
1192 01:00:14.731147 ----->DramcWriteLeveling(PI) begin...
1193 01:00:14.731201 ==
1194 01:00:14.731255 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 01:00:14.731312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 01:00:14.731366 ==
1197 01:00:14.731420 Write leveling (Byte 0): 33 => 33
1198 01:00:14.731473 Write leveling (Byte 1): 31 => 31
1199 01:00:14.731526 DramcWriteLeveling(PI) end<-----
1200 01:00:14.731578
1201 01:00:14.731631 ==
1202 01:00:14.731685 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 01:00:14.731738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 01:00:14.731792 ==
1205 01:00:14.731845 [Gating] SW mode calibration
1206 01:00:14.731898 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1207 01:00:14.731952 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1208 01:00:14.732006 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1209 01:00:14.732059 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1210 01:00:14.732113 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1211 01:00:14.732166 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 01:00:14.732220 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 01:00:14.732273 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 01:00:14.732326 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 01:00:14.732379 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 01:00:14.732431 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 01:00:14.732484 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 01:00:14.732537 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 01:00:14.732590 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 01:00:14.732649 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 01:00:14.732711 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 01:00:14.732766 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 01:00:14.732819 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 01:00:14.732873 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 01:00:14.732926 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1226 01:00:14.732979 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1227 01:00:14.733033 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1228 01:00:14.733086 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 01:00:14.733139 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 01:00:14.733192 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 01:00:14.733245 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 01:00:14.733298 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 01:00:14.733351 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 01:00:14.733404 0 9 8 | B1->B0 | 2323 2c2b | 1 1 | (1 1) (1 1)
1235 01:00:14.733457 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1236 01:00:14.733511 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 01:00:14.733563 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 01:00:14.733616 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 01:00:14.733701 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 01:00:14.733784 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 01:00:14.733870 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1242 01:00:14.733953 0 10 8 | B1->B0 | 3232 2b2b | 0 1 | (0 1) (1 0)
1243 01:00:14.734231 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 01:00:14.734391 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 01:00:14.734500 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 01:00:14.734608 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 01:00:14.734713 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 01:00:14.734801 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 01:00:14.734885 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1250 01:00:14.734968 0 11 8 | B1->B0 | 2e2e 3b3b | 0 1 | (0 0) (0 0)
1251 01:00:14.735051 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1252 01:00:14.735134 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 01:00:14.735217 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 01:00:14.735300 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 01:00:14.735382 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 01:00:14.735465 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 01:00:14.735548 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 01:00:14.735630 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1259 01:00:14.735713 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 01:00:14.735796 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 01:00:14.735878 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 01:00:14.735961 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 01:00:14.736043 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 01:00:14.736125 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 01:00:14.736208 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 01:00:14.736290 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 01:00:14.736373 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 01:00:14.736455 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 01:00:14.736538 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 01:00:14.736620 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 01:00:14.736703 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 01:00:14.736785 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 01:00:14.736867 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 01:00:14.736949 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1275 01:00:14.737031 Total UI for P1: 0, mck2ui 16
1276 01:00:14.737114 best dqsien dly found for B0: ( 0, 14, 6)
1277 01:00:14.737197 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1278 01:00:14.737280 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 01:00:14.737362 Total UI for P1: 0, mck2ui 16
1280 01:00:14.737444 best dqsien dly found for B1: ( 0, 14, 10)
1281 01:00:14.737526 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1282 01:00:14.737609 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1283 01:00:14.737690
1284 01:00:14.737775 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1285 01:00:14.737859 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1286 01:00:14.737941 [Gating] SW calibration Done
1287 01:00:14.738023 ==
1288 01:00:14.738105 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 01:00:14.738200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 01:00:14.738258 ==
1291 01:00:14.738312 RX Vref Scan: 0
1292 01:00:14.738366
1293 01:00:14.738419 RX Vref 0 -> 0, step: 1
1294 01:00:14.738473
1295 01:00:14.738526 RX Delay -130 -> 252, step: 16
1296 01:00:14.738579 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1297 01:00:14.738633 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1298 01:00:14.738687 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1299 01:00:14.738740 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1300 01:00:14.738793 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1301 01:00:14.738846 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1302 01:00:14.738899 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1303 01:00:14.738952 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1304 01:00:14.739005 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1305 01:00:14.739057 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1306 01:00:14.739110 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1307 01:00:14.739164 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1308 01:00:14.739217 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1309 01:00:14.739269 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1310 01:00:14.739322 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1311 01:00:14.739375 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1312 01:00:14.739427 ==
1313 01:00:14.739480 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 01:00:14.739533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 01:00:14.739586 ==
1316 01:00:14.739639 DQS Delay:
1317 01:00:14.739691 DQS0 = 0, DQS1 = 0
1318 01:00:14.739745 DQM Delay:
1319 01:00:14.739798 DQM0 = 82, DQM1 = 77
1320 01:00:14.739851 DQ Delay:
1321 01:00:14.739903 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1322 01:00:14.739956 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =101
1323 01:00:14.740009 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1324 01:00:14.740062 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1325 01:00:14.740115
1326 01:00:14.740167
1327 01:00:14.740220 ==
1328 01:00:14.740273 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 01:00:14.740326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 01:00:14.740379 ==
1331 01:00:14.740431
1332 01:00:14.740483
1333 01:00:14.740536 TX Vref Scan disable
1334 01:00:14.740588 == TX Byte 0 ==
1335 01:00:14.740641 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1336 01:00:14.740694 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1337 01:00:14.740747 == TX Byte 1 ==
1338 01:00:14.740800 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1339 01:00:14.740852 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1340 01:00:14.740905 ==
1341 01:00:14.740957 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 01:00:14.741010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 01:00:14.741062 ==
1344 01:00:14.741115 TX Vref=22, minBit 8, minWin=27, winSum=443
1345 01:00:14.741168 TX Vref=24, minBit 3, minWin=27, winSum=445
1346 01:00:14.741221 TX Vref=26, minBit 3, minWin=27, winSum=449
1347 01:00:14.741282 TX Vref=28, minBit 12, minWin=27, winSum=447
1348 01:00:14.741336 TX Vref=30, minBit 8, minWin=27, winSum=449
1349 01:00:14.741389 TX Vref=32, minBit 9, minWin=27, winSum=448
1350 01:00:14.741441 [TxChooseVref] Worse bit 3, Min win 27, Win sum 449, Final Vref 26
1351 01:00:14.741494
1352 01:00:14.741742 Final TX Range 1 Vref 26
1353 01:00:14.741833
1354 01:00:14.741938 ==
1355 01:00:14.742045 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 01:00:14.742152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 01:00:14.742277 ==
1358 01:00:14.742360
1359 01:00:14.742442
1360 01:00:14.742523 TX Vref Scan disable
1361 01:00:14.742606 == TX Byte 0 ==
1362 01:00:14.742689 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1363 01:00:14.742772 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1364 01:00:14.742853 == TX Byte 1 ==
1365 01:00:14.742935 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1366 01:00:14.743018 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1367 01:00:14.743099
1368 01:00:14.743180 [DATLAT]
1369 01:00:14.743262 Freq=800, CH0 RK1
1370 01:00:14.743344
1371 01:00:14.743425 DATLAT Default: 0xa
1372 01:00:14.743506 0, 0xFFFF, sum = 0
1373 01:00:14.743591 1, 0xFFFF, sum = 0
1374 01:00:14.743675 2, 0xFFFF, sum = 0
1375 01:00:14.743758 3, 0xFFFF, sum = 0
1376 01:00:14.743841 4, 0xFFFF, sum = 0
1377 01:00:14.743924 5, 0xFFFF, sum = 0
1378 01:00:14.744007 6, 0xFFFF, sum = 0
1379 01:00:14.744090 7, 0xFFFF, sum = 0
1380 01:00:14.744173 8, 0xFFFF, sum = 0
1381 01:00:14.744256 9, 0x0, sum = 1
1382 01:00:14.744339 10, 0x0, sum = 2
1383 01:00:14.744422 11, 0x0, sum = 3
1384 01:00:14.744505 12, 0x0, sum = 4
1385 01:00:14.744592 best_step = 10
1386 01:00:14.744673
1387 01:00:14.744754 ==
1388 01:00:14.744836 Dram Type= 6, Freq= 0, CH_0, rank 1
1389 01:00:14.744918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 01:00:14.744999 ==
1391 01:00:14.745081 RX Vref Scan: 0
1392 01:00:14.745162
1393 01:00:14.745244 RX Vref 0 -> 0, step: 1
1394 01:00:14.745325
1395 01:00:14.745407 RX Delay -111 -> 252, step: 8
1396 01:00:14.745489 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1397 01:00:14.745571 iDelay=217, Bit 1, Center 88 (-23 ~ 200) 224
1398 01:00:14.745653 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1399 01:00:14.745735 iDelay=217, Bit 3, Center 80 (-31 ~ 192) 224
1400 01:00:14.745817 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1401 01:00:14.745899 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1402 01:00:14.745981 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1403 01:00:14.746063 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1404 01:00:14.746145 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1405 01:00:14.746271 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1406 01:00:14.746353 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1407 01:00:14.746436 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1408 01:00:14.746518 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1409 01:00:14.746600 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1410 01:00:14.746682 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1411 01:00:14.746764 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1412 01:00:14.746845 ==
1413 01:00:14.746926 Dram Type= 6, Freq= 0, CH_0, rank 1
1414 01:00:14.747010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 01:00:14.747092 ==
1416 01:00:14.747174 DQS Delay:
1417 01:00:14.747255 DQS0 = 0, DQS1 = 0
1418 01:00:14.747337 DQM Delay:
1419 01:00:14.747416 DQM0 = 86, DQM1 = 76
1420 01:00:14.747471 DQ Delay:
1421 01:00:14.747525 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1422 01:00:14.747578 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =100
1423 01:00:14.747639 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1424 01:00:14.747697 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1425 01:00:14.747750
1426 01:00:14.747802
1427 01:00:14.747854 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c03, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1428 01:00:14.747909 CH0 RK1: MR19=606, MR18=3C03
1429 01:00:14.747961 CH0_RK1: MR19=0x606, MR18=0x3C03, DQSOSC=394, MR23=63, INC=95, DEC=63
1430 01:00:14.748014 [RxdqsGatingPostProcess] freq 800
1431 01:00:14.748067 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1432 01:00:14.748120 Pre-setting of DQS Precalculation
1433 01:00:14.748172 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1434 01:00:14.748225 ==
1435 01:00:14.748278 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 01:00:14.748331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 01:00:14.748385 ==
1438 01:00:14.748437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1439 01:00:14.748490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1440 01:00:14.748544 [CA 0] Center 36 (6~67) winsize 62
1441 01:00:14.748596 [CA 1] Center 36 (6~67) winsize 62
1442 01:00:14.748649 [CA 2] Center 34 (4~65) winsize 62
1443 01:00:14.748701 [CA 3] Center 34 (3~65) winsize 63
1444 01:00:14.748753 [CA 4] Center 34 (4~65) winsize 62
1445 01:00:14.748805 [CA 5] Center 34 (3~65) winsize 63
1446 01:00:14.748857
1447 01:00:14.748910 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1448 01:00:14.748962
1449 01:00:14.749014 [CATrainingPosCal] consider 1 rank data
1450 01:00:14.749067 u2DelayCellTimex100 = 270/100 ps
1451 01:00:14.749119 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 01:00:14.749172 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1453 01:00:14.749226 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 01:00:14.749279 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1455 01:00:14.749331 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 01:00:14.749383 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1457 01:00:14.749436
1458 01:00:14.749488 CA PerBit enable=1, Macro0, CA PI delay=34
1459 01:00:14.749540
1460 01:00:14.749592 [CBTSetCACLKResult] CA Dly = 34
1461 01:00:14.749646 CS Dly: 5 (0~36)
1462 01:00:14.749698 ==
1463 01:00:14.749751 Dram Type= 6, Freq= 0, CH_1, rank 1
1464 01:00:14.749803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 01:00:14.749856 ==
1466 01:00:14.749909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1467 01:00:14.749962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1468 01:00:14.750014 [CA 0] Center 37 (7~67) winsize 61
1469 01:00:14.750066 [CA 1] Center 37 (6~68) winsize 63
1470 01:00:14.750119 [CA 2] Center 34 (4~65) winsize 62
1471 01:00:14.750179 [CA 3] Center 34 (3~65) winsize 63
1472 01:00:14.750233 [CA 4] Center 34 (4~65) winsize 62
1473 01:00:14.750286 [CA 5] Center 34 (3~65) winsize 63
1474 01:00:14.750338
1475 01:00:14.750391 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1476 01:00:14.750444
1477 01:00:14.750496 [CATrainingPosCal] consider 2 rank data
1478 01:00:14.750549 u2DelayCellTimex100 = 270/100 ps
1479 01:00:14.750601 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1480 01:00:14.750654 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 01:00:14.750706 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 01:00:14.750759 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1483 01:00:14.750815 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 01:00:14.750869 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1485 01:00:14.750921
1486 01:00:14.751168 CA PerBit enable=1, Macro0, CA PI delay=34
1487 01:00:14.751255
1488 01:00:14.751353 [CBTSetCACLKResult] CA Dly = 34
1489 01:00:14.751444 CS Dly: 6 (0~38)
1490 01:00:14.751505
1491 01:00:14.751559 ----->DramcWriteLeveling(PI) begin...
1492 01:00:14.751613 ==
1493 01:00:14.751667 Dram Type= 6, Freq= 0, CH_1, rank 0
1494 01:00:14.751721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1495 01:00:14.751774 ==
1496 01:00:14.751826 Write leveling (Byte 0): 29 => 29
1497 01:00:14.751880 Write leveling (Byte 1): 29 => 29
1498 01:00:14.751933 DramcWriteLeveling(PI) end<-----
1499 01:00:14.751985
1500 01:00:14.752037 ==
1501 01:00:14.752089 Dram Type= 6, Freq= 0, CH_1, rank 0
1502 01:00:14.752142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1503 01:00:14.752195 ==
1504 01:00:14.752248 [Gating] SW mode calibration
1505 01:00:14.752300 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1506 01:00:14.752354 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1507 01:00:14.752407 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1508 01:00:14.752460 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1509 01:00:14.752513 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1510 01:00:14.752566 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 01:00:14.752618 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 01:00:14.752671 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 01:00:14.752723 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 01:00:14.752775 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 01:00:14.752828 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 01:00:14.752880 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 01:00:14.752933 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 01:00:14.752986 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 01:00:14.753038 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 01:00:14.753091 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 01:00:14.753143 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 01:00:14.753196 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 01:00:14.753248 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1524 01:00:14.753301 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1525 01:00:14.753353 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1526 01:00:14.753405 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 01:00:14.753458 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 01:00:14.753510 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 01:00:14.753563 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 01:00:14.753616 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 01:00:14.753668 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 01:00:14.753720 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 01:00:14.753773 0 9 8 | B1->B0 | 302f 2f2f | 1 1 | (0 0) (0 0)
1534 01:00:14.753826 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 01:00:14.753878 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 01:00:14.753930 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 01:00:14.753983 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 01:00:14.754035 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 01:00:14.754087 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 01:00:14.754139 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (0 0) (1 0)
1541 01:00:14.754198 0 10 8 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
1542 01:00:14.754288 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 01:00:14.754340 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 01:00:14.754392 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 01:00:14.754444 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 01:00:14.754496 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 01:00:14.754549 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 01:00:14.754601 0 11 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (1 1)
1549 01:00:14.754654 0 11 8 | B1->B0 | 3a39 3a3a | 1 1 | (0 0) (0 0)
1550 01:00:14.754707 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 01:00:14.754759 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 01:00:14.754812 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 01:00:14.754864 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 01:00:14.754916 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 01:00:14.754968 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 01:00:14.755021 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1557 01:00:14.755073 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1558 01:00:14.755125 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 01:00:14.755177 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 01:00:14.755230 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 01:00:14.755283 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 01:00:14.755336 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 01:00:14.755388 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 01:00:14.755441 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 01:00:14.755493 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 01:00:14.755545 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 01:00:14.755598 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 01:00:14.755650 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 01:00:14.755703 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 01:00:14.755755 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 01:00:14.755807 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 01:00:14.755860 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1573 01:00:14.755913 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 01:00:14.755965 Total UI for P1: 0, mck2ui 16
1575 01:00:14.756018 best dqsien dly found for B0: ( 0, 14, 4)
1576 01:00:14.756071 Total UI for P1: 0, mck2ui 16
1577 01:00:14.756317 best dqsien dly found for B1: ( 0, 14, 6)
1578 01:00:14.756376 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1579 01:00:14.756431 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1580 01:00:14.756484
1581 01:00:14.756538 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1582 01:00:14.756591 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1583 01:00:14.756644 [Gating] SW calibration Done
1584 01:00:14.756697 ==
1585 01:00:14.756750 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 01:00:14.756804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 01:00:14.756856 ==
1588 01:00:14.756909 RX Vref Scan: 0
1589 01:00:14.756962
1590 01:00:14.757015 RX Vref 0 -> 0, step: 1
1591 01:00:14.757067
1592 01:00:14.757120 RX Delay -130 -> 252, step: 16
1593 01:00:14.757173 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1594 01:00:14.757225 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1595 01:00:14.757277 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1596 01:00:14.757329 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1597 01:00:14.757382 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1598 01:00:14.757434 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1599 01:00:14.757488 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1600 01:00:14.757540 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1601 01:00:14.757593 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1602 01:00:14.757645 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1603 01:00:14.757697 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1604 01:00:14.757749 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1605 01:00:14.757802 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1606 01:00:14.757854 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1607 01:00:14.757907 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1608 01:00:14.757960 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1609 01:00:14.758012 ==
1610 01:00:14.758064 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 01:00:14.758116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 01:00:14.758174 ==
1613 01:00:14.758227 DQS Delay:
1614 01:00:14.758280 DQS0 = 0, DQS1 = 0
1615 01:00:14.758332 DQM Delay:
1616 01:00:14.758384 DQM0 = 89, DQM1 = 78
1617 01:00:14.758437 DQ Delay:
1618 01:00:14.758489 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1619 01:00:14.758542 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1620 01:00:14.758595 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1621 01:00:14.758647 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1622 01:00:14.758699
1623 01:00:14.758752
1624 01:00:14.758804 ==
1625 01:00:14.758856 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 01:00:14.758909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 01:00:14.758962 ==
1628 01:00:14.759015
1629 01:00:14.759067
1630 01:00:14.759118 TX Vref Scan disable
1631 01:00:14.759171 == TX Byte 0 ==
1632 01:00:14.759223 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1633 01:00:14.759276 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1634 01:00:14.759329 == TX Byte 1 ==
1635 01:00:14.759381 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1636 01:00:14.759434 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1637 01:00:14.759486 ==
1638 01:00:14.759539 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 01:00:14.759592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 01:00:14.759646 ==
1641 01:00:14.759699 TX Vref=22, minBit 10, minWin=26, winSum=443
1642 01:00:14.759752 TX Vref=24, minBit 9, minWin=27, winSum=448
1643 01:00:14.759805 TX Vref=26, minBit 9, minWin=27, winSum=448
1644 01:00:14.759858 TX Vref=28, minBit 8, minWin=27, winSum=446
1645 01:00:14.759911 TX Vref=30, minBit 10, minWin=27, winSum=449
1646 01:00:14.759964 TX Vref=32, minBit 8, minWin=27, winSum=446
1647 01:00:14.760016 [TxChooseVref] Worse bit 10, Min win 27, Win sum 449, Final Vref 30
1648 01:00:14.760069
1649 01:00:14.760122 Final TX Range 1 Vref 30
1650 01:00:14.760175
1651 01:00:14.760227 ==
1652 01:00:14.760280 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 01:00:14.760333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 01:00:14.760386 ==
1655 01:00:14.760438
1656 01:00:14.760490
1657 01:00:14.760542 TX Vref Scan disable
1658 01:00:14.760594 == TX Byte 0 ==
1659 01:00:14.760647 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1660 01:00:14.760699 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1661 01:00:14.760751 == TX Byte 1 ==
1662 01:00:14.760803 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1663 01:00:14.760856 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1664 01:00:14.760908
1665 01:00:14.760960 [DATLAT]
1666 01:00:14.761012 Freq=800, CH1 RK0
1667 01:00:14.761065
1668 01:00:14.761117 DATLAT Default: 0xa
1669 01:00:14.761170 0, 0xFFFF, sum = 0
1670 01:00:14.761223 1, 0xFFFF, sum = 0
1671 01:00:14.761277 2, 0xFFFF, sum = 0
1672 01:00:14.761329 3, 0xFFFF, sum = 0
1673 01:00:14.761383 4, 0xFFFF, sum = 0
1674 01:00:14.761436 5, 0xFFFF, sum = 0
1675 01:00:14.761488 6, 0xFFFF, sum = 0
1676 01:00:14.761541 7, 0xFFFF, sum = 0
1677 01:00:14.761594 8, 0xFFFF, sum = 0
1678 01:00:14.761647 9, 0x0, sum = 1
1679 01:00:14.761700 10, 0x0, sum = 2
1680 01:00:14.761753 11, 0x0, sum = 3
1681 01:00:14.761807 12, 0x0, sum = 4
1682 01:00:14.761860 best_step = 10
1683 01:00:14.761912
1684 01:00:14.761965 ==
1685 01:00:14.762017 Dram Type= 6, Freq= 0, CH_1, rank 0
1686 01:00:14.762070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1687 01:00:14.762123 ==
1688 01:00:14.762182 RX Vref Scan: 1
1689 01:00:14.762236
1690 01:00:14.762288 Set Vref Range= 32 -> 127
1691 01:00:14.762340
1692 01:00:14.762392 RX Vref 32 -> 127, step: 1
1693 01:00:14.762444
1694 01:00:14.762497 RX Delay -95 -> 252, step: 8
1695 01:00:14.762549
1696 01:00:14.762601 Set Vref, RX VrefLevel [Byte0]: 32
1697 01:00:14.762654 [Byte1]: 32
1698 01:00:14.762706
1699 01:00:14.762759 Set Vref, RX VrefLevel [Byte0]: 33
1700 01:00:14.762812 [Byte1]: 33
1701 01:00:14.762864
1702 01:00:14.762917 Set Vref, RX VrefLevel [Byte0]: 34
1703 01:00:14.762969 [Byte1]: 34
1704 01:00:14.763021
1705 01:00:14.763073 Set Vref, RX VrefLevel [Byte0]: 35
1706 01:00:14.763126 [Byte1]: 35
1707 01:00:14.763179
1708 01:00:14.763232 Set Vref, RX VrefLevel [Byte0]: 36
1709 01:00:14.763284 [Byte1]: 36
1710 01:00:14.763337
1711 01:00:14.763389 Set Vref, RX VrefLevel [Byte0]: 37
1712 01:00:14.763442 [Byte1]: 37
1713 01:00:14.763494
1714 01:00:14.763546 Set Vref, RX VrefLevel [Byte0]: 38
1715 01:00:14.763599 [Byte1]: 38
1716 01:00:14.763651
1717 01:00:14.763703 Set Vref, RX VrefLevel [Byte0]: 39
1718 01:00:14.763755 [Byte1]: 39
1719 01:00:14.763808
1720 01:00:14.763859 Set Vref, RX VrefLevel [Byte0]: 40
1721 01:00:14.763912 [Byte1]: 40
1722 01:00:14.763963
1723 01:00:14.764015 Set Vref, RX VrefLevel [Byte0]: 41
1724 01:00:14.764068 [Byte1]: 41
1725 01:00:14.764121
1726 01:00:14.764174 Set Vref, RX VrefLevel [Byte0]: 42
1727 01:00:14.764227 [Byte1]: 42
1728 01:00:14.764279
1729 01:00:14.764331 Set Vref, RX VrefLevel [Byte0]: 43
1730 01:00:14.764384 [Byte1]: 43
1731 01:00:14.764435
1732 01:00:14.764677 Set Vref, RX VrefLevel [Byte0]: 44
1733 01:00:14.764739 [Byte1]: 44
1734 01:00:14.764793
1735 01:00:14.764846 Set Vref, RX VrefLevel [Byte0]: 45
1736 01:00:14.764900 [Byte1]: 45
1737 01:00:14.764952
1738 01:00:14.765005 Set Vref, RX VrefLevel [Byte0]: 46
1739 01:00:14.765058 [Byte1]: 46
1740 01:00:14.765111
1741 01:00:14.765164 Set Vref, RX VrefLevel [Byte0]: 47
1742 01:00:14.765217 [Byte1]: 47
1743 01:00:14.765270
1744 01:00:14.765322 Set Vref, RX VrefLevel [Byte0]: 48
1745 01:00:14.765375 [Byte1]: 48
1746 01:00:14.765427
1747 01:00:14.765479 Set Vref, RX VrefLevel [Byte0]: 49
1748 01:00:14.765532 [Byte1]: 49
1749 01:00:14.765584
1750 01:00:14.765637 Set Vref, RX VrefLevel [Byte0]: 50
1751 01:00:14.765689 [Byte1]: 50
1752 01:00:14.765741
1753 01:00:14.765793 Set Vref, RX VrefLevel [Byte0]: 51
1754 01:00:14.765846 [Byte1]: 51
1755 01:00:14.765898
1756 01:00:14.765950 Set Vref, RX VrefLevel [Byte0]: 52
1757 01:00:14.766003 [Byte1]: 52
1758 01:00:14.766055
1759 01:00:14.766108 Set Vref, RX VrefLevel [Byte0]: 53
1760 01:00:14.766167 [Byte1]: 53
1761 01:00:14.766221
1762 01:00:14.766273 Set Vref, RX VrefLevel [Byte0]: 54
1763 01:00:14.766326 [Byte1]: 54
1764 01:00:14.766378
1765 01:00:14.766430 Set Vref, RX VrefLevel [Byte0]: 55
1766 01:00:14.766483 [Byte1]: 55
1767 01:00:14.766541
1768 01:00:14.766594 Set Vref, RX VrefLevel [Byte0]: 56
1769 01:00:14.766646 [Byte1]: 56
1770 01:00:14.766698
1771 01:00:14.766750 Set Vref, RX VrefLevel [Byte0]: 57
1772 01:00:14.766803 [Byte1]: 57
1773 01:00:14.766855
1774 01:00:14.766907 Set Vref, RX VrefLevel [Byte0]: 58
1775 01:00:14.766960 [Byte1]: 58
1776 01:00:14.767012
1777 01:00:14.767064 Set Vref, RX VrefLevel [Byte0]: 59
1778 01:00:14.767117 [Byte1]: 59
1779 01:00:14.767169
1780 01:00:14.767221 Set Vref, RX VrefLevel [Byte0]: 60
1781 01:00:14.767274 [Byte1]: 60
1782 01:00:14.767326
1783 01:00:14.767378 Set Vref, RX VrefLevel [Byte0]: 61
1784 01:00:14.767431 [Byte1]: 61
1785 01:00:14.767483
1786 01:00:14.767535 Set Vref, RX VrefLevel [Byte0]: 62
1787 01:00:14.767588 [Byte1]: 62
1788 01:00:14.767640
1789 01:00:14.767693 Set Vref, RX VrefLevel [Byte0]: 63
1790 01:00:14.767745 [Byte1]: 63
1791 01:00:14.767797
1792 01:00:14.767849 Set Vref, RX VrefLevel [Byte0]: 64
1793 01:00:14.767902 [Byte1]: 64
1794 01:00:14.767954
1795 01:00:14.768006 Set Vref, RX VrefLevel [Byte0]: 65
1796 01:00:14.768059 [Byte1]: 65
1797 01:00:14.768111
1798 01:00:14.768163 Set Vref, RX VrefLevel [Byte0]: 66
1799 01:00:14.768216 [Byte1]: 66
1800 01:00:14.768268
1801 01:00:14.768320 Set Vref, RX VrefLevel [Byte0]: 67
1802 01:00:14.768372 [Byte1]: 67
1803 01:00:14.768424
1804 01:00:14.768476 Set Vref, RX VrefLevel [Byte0]: 68
1805 01:00:14.768529 [Byte1]: 68
1806 01:00:14.768581
1807 01:00:14.768633 Set Vref, RX VrefLevel [Byte0]: 69
1808 01:00:14.768685 [Byte1]: 69
1809 01:00:14.768738
1810 01:00:14.768791 Set Vref, RX VrefLevel [Byte0]: 70
1811 01:00:14.768843 [Byte1]: 70
1812 01:00:14.768895
1813 01:00:14.768947 Set Vref, RX VrefLevel [Byte0]: 71
1814 01:00:14.769000 [Byte1]: 71
1815 01:00:14.769052
1816 01:00:14.769104 Set Vref, RX VrefLevel [Byte0]: 72
1817 01:00:14.769156 [Byte1]: 72
1818 01:00:14.769208
1819 01:00:14.769260 Set Vref, RX VrefLevel [Byte0]: 73
1820 01:00:14.769312 [Byte1]: 73
1821 01:00:14.769364
1822 01:00:14.769416 Set Vref, RX VrefLevel [Byte0]: 74
1823 01:00:14.769468 [Byte1]: 74
1824 01:00:14.769521
1825 01:00:14.769573 Set Vref, RX VrefLevel [Byte0]: 75
1826 01:00:14.769626 [Byte1]: 75
1827 01:00:14.769678
1828 01:00:14.769730 Set Vref, RX VrefLevel [Byte0]: 76
1829 01:00:14.769783 [Byte1]: 76
1830 01:00:14.769835
1831 01:00:14.769887 Set Vref, RX VrefLevel [Byte0]: 77
1832 01:00:14.769940 [Byte1]: 77
1833 01:00:14.769992
1834 01:00:14.770044 Final RX Vref Byte 0 = 56 to rank0
1835 01:00:14.770097 Final RX Vref Byte 1 = 67 to rank0
1836 01:00:14.770150 Final RX Vref Byte 0 = 56 to rank1
1837 01:00:14.770247 Final RX Vref Byte 1 = 67 to rank1==
1838 01:00:14.770299 Dram Type= 6, Freq= 0, CH_1, rank 0
1839 01:00:14.770352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1840 01:00:14.770405 ==
1841 01:00:14.770457 DQS Delay:
1842 01:00:14.770509 DQS0 = 0, DQS1 = 0
1843 01:00:14.770561 DQM Delay:
1844 01:00:14.770613 DQM0 = 86, DQM1 = 78
1845 01:00:14.770665 DQ Delay:
1846 01:00:14.770717 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1847 01:00:14.770769 DQ4 =80, DQ5 =96, DQ6 =100, DQ7 =80
1848 01:00:14.770821 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1849 01:00:14.770873 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1850 01:00:14.770925
1851 01:00:14.770978
1852 01:00:14.771030 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f1b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1853 01:00:14.771084 CH1 RK0: MR19=606, MR18=2F1B
1854 01:00:14.771136 CH1_RK0: MR19=0x606, MR18=0x2F1B, DQSOSC=397, MR23=63, INC=93, DEC=62
1855 01:00:14.771190
1856 01:00:14.771242 ----->DramcWriteLeveling(PI) begin...
1857 01:00:14.771296 ==
1858 01:00:14.771349 Dram Type= 6, Freq= 0, CH_1, rank 1
1859 01:00:14.771402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 01:00:14.771454 ==
1861 01:00:14.771507 Write leveling (Byte 0): 27 => 27
1862 01:00:14.771560 Write leveling (Byte 1): 30 => 30
1863 01:00:14.771612 DramcWriteLeveling(PI) end<-----
1864 01:00:14.771664
1865 01:00:14.771716 ==
1866 01:00:14.771769 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 01:00:14.771822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 01:00:14.771875 ==
1869 01:00:14.771927 [Gating] SW mode calibration
1870 01:00:14.771979 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1871 01:00:14.772032 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1872 01:00:14.772085 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1873 01:00:14.772157 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1874 01:00:14.772212 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1875 01:00:14.772266 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 01:00:14.772318 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 01:00:14.772371 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 01:00:14.772612 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 01:00:14.772671 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 01:00:14.772724 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 01:00:14.772777 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 01:00:14.772830 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 01:00:14.772883 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 01:00:14.772936 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 01:00:14.772988 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 01:00:14.773041 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 01:00:14.773094 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 01:00:14.773147 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1889 01:00:14.773200 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1890 01:00:14.773252 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 01:00:14.773304 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 01:00:14.773356 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 01:00:14.773408 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 01:00:14.773461 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 01:00:14.773513 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 01:00:14.773566 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 01:00:14.773618 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 01:00:14.773671 0 9 8 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
1899 01:00:14.773724 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1900 01:00:14.773776 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 01:00:14.773829 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 01:00:14.773881 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 01:00:14.773933 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 01:00:14.773986 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 01:00:14.774038 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
1906 01:00:14.774090 0 10 8 | B1->B0 | 2b2b 2f2f | 0 1 | (0 0) (1 0)
1907 01:00:14.774169 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 01:00:14.774260 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 01:00:14.774312 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 01:00:14.774365 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 01:00:14.774418 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 01:00:14.774470 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 01:00:14.774522 0 11 4 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
1914 01:00:14.774575 0 11 8 | B1->B0 | 4444 3e3e | 0 0 | (0 0) (0 0)
1915 01:00:14.774628 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 01:00:14.774680 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 01:00:14.774732 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 01:00:14.774785 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 01:00:14.774837 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 01:00:14.774890 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 01:00:14.774942 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1922 01:00:14.774994 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1923 01:00:14.775047 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 01:00:14.775099 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 01:00:14.775151 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 01:00:14.775204 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 01:00:14.775256 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 01:00:14.775309 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 01:00:14.775362 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 01:00:14.775414 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 01:00:14.775467 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 01:00:14.775519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 01:00:14.775572 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 01:00:14.775624 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 01:00:14.775677 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 01:00:14.775729 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 01:00:14.775781 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1938 01:00:14.775833 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 01:00:14.775886 Total UI for P1: 0, mck2ui 16
1940 01:00:14.775939 best dqsien dly found for B0: ( 0, 14, 4)
1941 01:00:14.775992 Total UI for P1: 0, mck2ui 16
1942 01:00:14.776044 best dqsien dly found for B1: ( 0, 14, 4)
1943 01:00:14.776115 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1944 01:00:14.776207 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1945 01:00:14.776263
1946 01:00:14.776316 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1947 01:00:14.776370 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1948 01:00:14.776423 [Gating] SW calibration Done
1949 01:00:14.776475 ==
1950 01:00:14.776528 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 01:00:14.776581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 01:00:14.776633 ==
1953 01:00:14.776685 RX Vref Scan: 0
1954 01:00:14.776737
1955 01:00:14.776790 RX Vref 0 -> 0, step: 1
1956 01:00:14.776842
1957 01:00:14.776894 RX Delay -130 -> 252, step: 16
1958 01:00:15.315615 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1959 01:00:15.316137 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1960 01:00:15.316766 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1961 01:00:15.317198 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1962 01:00:15.317550 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1963 01:00:15.317883 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1964 01:00:15.318248 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1965 01:00:15.318578 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1966 01:00:15.318895 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1967 01:00:15.319298 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1968 01:00:15.320145 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1969 01:00:15.320721 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1970 01:00:15.321411 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1971 01:00:15.322072 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1972 01:00:15.322757 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1973 01:00:15.323278 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1974 01:00:15.323776 ==
1975 01:00:15.324278 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 01:00:15.324760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 01:00:15.325234 ==
1978 01:00:15.325705 DQS Delay:
1979 01:00:15.326202 DQS0 = 0, DQS1 = 0
1980 01:00:15.326633 DQM Delay:
1981 01:00:15.326986 DQM0 = 87, DQM1 = 80
1982 01:00:15.327460 DQ Delay:
1983 01:00:15.327951 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1984 01:00:15.328301 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1985 01:00:15.328610 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1986 01:00:15.328946 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1987 01:00:15.329249
1988 01:00:15.329551
1989 01:00:15.330033 ==
1990 01:00:15.330432 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 01:00:15.330769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 01:00:15.331077 ==
1993 01:00:15.331378
1994 01:00:15.331675
1995 01:00:15.331973 TX Vref Scan disable
1996 01:00:15.332274 == TX Byte 0 ==
1997 01:00:15.332576 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1998 01:00:15.332877 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1999 01:00:15.333177 == TX Byte 1 ==
2000 01:00:15.333479 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2001 01:00:15.333808 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2002 01:00:15.334331 ==
2003 01:00:15.334658 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 01:00:15.334966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 01:00:15.335334 ==
2006 01:00:15.335655 TX Vref=22, minBit 1, minWin=27, winSum=443
2007 01:00:15.335965 TX Vref=24, minBit 8, minWin=27, winSum=448
2008 01:00:15.336273 TX Vref=26, minBit 13, minWin=27, winSum=451
2009 01:00:15.336576 TX Vref=28, minBit 13, minWin=27, winSum=451
2010 01:00:15.336909 TX Vref=30, minBit 15, minWin=27, winSum=451
2011 01:00:15.337216 TX Vref=32, minBit 8, minWin=27, winSum=447
2012 01:00:15.337529 [TxChooseVref] Worse bit 13, Min win 27, Win sum 451, Final Vref 26
2013 01:00:15.337807
2014 01:00:15.338079 Final TX Range 1 Vref 26
2015 01:00:15.338403
2016 01:00:15.338682 ==
2017 01:00:15.338957 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 01:00:15.339234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 01:00:15.339511 ==
2020 01:00:15.339785
2021 01:00:15.340074
2022 01:00:15.340353 TX Vref Scan disable
2023 01:00:15.340575 == TX Byte 0 ==
2024 01:00:15.340772 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2025 01:00:15.340968 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2026 01:00:15.341165 == TX Byte 1 ==
2027 01:00:15.341359 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2028 01:00:15.341555 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2029 01:00:15.341766
2030 01:00:15.342068 [DATLAT]
2031 01:00:15.342336 Freq=800, CH1 RK1
2032 01:00:15.342565
2033 01:00:15.342763 DATLAT Default: 0xa
2034 01:00:15.342962 0, 0xFFFF, sum = 0
2035 01:00:15.343163 1, 0xFFFF, sum = 0
2036 01:00:15.343365 2, 0xFFFF, sum = 0
2037 01:00:15.343565 3, 0xFFFF, sum = 0
2038 01:00:15.343764 4, 0xFFFF, sum = 0
2039 01:00:15.343988 5, 0xFFFF, sum = 0
2040 01:00:15.344192 6, 0xFFFF, sum = 0
2041 01:00:15.344391 7, 0xFFFF, sum = 0
2042 01:00:15.344591 8, 0xFFFF, sum = 0
2043 01:00:15.344790 9, 0x0, sum = 1
2044 01:00:15.344991 10, 0x0, sum = 2
2045 01:00:15.345193 11, 0x0, sum = 3
2046 01:00:15.345394 12, 0x0, sum = 4
2047 01:00:15.345569 best_step = 10
2048 01:00:15.345717
2049 01:00:15.345864 ==
2050 01:00:15.346012 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 01:00:15.346180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 01:00:15.346342 ==
2053 01:00:15.346600 RX Vref Scan: 0
2054 01:00:15.346764
2055 01:00:15.346930 RX Vref 0 -> 0, step: 1
2056 01:00:15.347083
2057 01:00:15.347230 RX Delay -95 -> 252, step: 8
2058 01:00:15.347381 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2059 01:00:15.347530 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2060 01:00:15.347680 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2061 01:00:15.347828 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2062 01:00:15.347976 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2063 01:00:15.348125 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2064 01:00:15.348273 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2065 01:00:15.348420 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2066 01:00:15.348570 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2067 01:00:15.348721 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2068 01:00:15.348870 iDelay=217, Bit 10, Center 80 (-31 ~ 192) 224
2069 01:00:15.349018 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2070 01:00:15.349164 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2071 01:00:15.349312 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2072 01:00:15.349461 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2073 01:00:15.349608 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
2074 01:00:15.349756 ==
2075 01:00:15.349906 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 01:00:15.350114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 01:00:15.350308 ==
2078 01:00:15.350462 DQS Delay:
2079 01:00:15.350582 DQS0 = 0, DQS1 = 0
2080 01:00:15.350703 DQM Delay:
2081 01:00:15.350822 DQM0 = 87, DQM1 = 78
2082 01:00:15.350941 DQ Delay:
2083 01:00:15.351060 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2084 01:00:15.351180 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2085 01:00:15.351299 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =68
2086 01:00:15.351418 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =84
2087 01:00:15.351537
2088 01:00:15.351656
2089 01:00:15.351774 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2090 01:00:15.351896 CH1 RK1: MR19=606, MR18=1C15
2091 01:00:15.352015 CH1_RK1: MR19=0x606, MR18=0x1C15, DQSOSC=402, MR23=63, INC=91, DEC=60
2092 01:00:15.352134 [RxdqsGatingPostProcess] freq 800
2093 01:00:15.352252 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2094 01:00:15.352371 Pre-setting of DQS Precalculation
2095 01:00:15.352489 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2096 01:00:15.352609 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2097 01:00:15.352730 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2098 01:00:15.352849
2099 01:00:15.352967
2100 01:00:15.353084 [Calibration Summary] 1600 Mbps
2101 01:00:15.353203 CH 0, Rank 0
2102 01:00:15.353337 SW Impedance : PASS
2103 01:00:15.353457 DUTY Scan : NO K
2104 01:00:15.353577 ZQ Calibration : PASS
2105 01:00:15.353696 Jitter Meter : NO K
2106 01:00:15.353816 CBT Training : PASS
2107 01:00:15.353935 Write leveling : PASS
2108 01:00:15.354054 RX DQS gating : PASS
2109 01:00:15.354438 RX DQ/DQS(RDDQC) : PASS
2110 01:00:15.354692 TX DQ/DQS : PASS
2111 01:00:15.354946 RX DATLAT : PASS
2112 01:00:15.355197 RX DQ/DQS(Engine): PASS
2113 01:00:15.355442 TX OE : NO K
2114 01:00:15.355600 All Pass.
2115 01:00:15.355755
2116 01:00:15.355909 CH 0, Rank 1
2117 01:00:15.356064 SW Impedance : PASS
2118 01:00:15.356218 DUTY Scan : NO K
2119 01:00:15.356372 ZQ Calibration : PASS
2120 01:00:15.356525 Jitter Meter : NO K
2121 01:00:15.356679 CBT Training : PASS
2122 01:00:15.356831 Write leveling : PASS
2123 01:00:15.356984 RX DQS gating : PASS
2124 01:00:15.357142 RX DQ/DQS(RDDQC) : PASS
2125 01:00:15.357289 TX DQ/DQS : PASS
2126 01:00:15.357394 RX DATLAT : PASS
2127 01:00:15.357495 RX DQ/DQS(Engine): PASS
2128 01:00:15.357595 TX OE : NO K
2129 01:00:15.357696 All Pass.
2130 01:00:15.357796
2131 01:00:15.357895 CH 1, Rank 0
2132 01:00:15.357993 SW Impedance : PASS
2133 01:00:15.358093 DUTY Scan : NO K
2134 01:00:15.358202 ZQ Calibration : PASS
2135 01:00:15.358304 Jitter Meter : NO K
2136 01:00:15.358403 CBT Training : PASS
2137 01:00:15.358503 Write leveling : PASS
2138 01:00:15.358602 RX DQS gating : PASS
2139 01:00:15.358701 RX DQ/DQS(RDDQC) : PASS
2140 01:00:15.358799 TX DQ/DQS : PASS
2141 01:00:15.358899 RX DATLAT : PASS
2142 01:00:15.358998 RX DQ/DQS(Engine): PASS
2143 01:00:15.359097 TX OE : NO K
2144 01:00:15.359197 All Pass.
2145 01:00:15.359297
2146 01:00:15.359396 CH 1, Rank 1
2147 01:00:15.359495 SW Impedance : PASS
2148 01:00:15.359594 DUTY Scan : NO K
2149 01:00:15.359693 ZQ Calibration : PASS
2150 01:00:15.359793 Jitter Meter : NO K
2151 01:00:15.359898 CBT Training : PASS
2152 01:00:15.360002 Write leveling : PASS
2153 01:00:15.360101 RX DQS gating : PASS
2154 01:00:15.360200 RX DQ/DQS(RDDQC) : PASS
2155 01:00:15.360298 TX DQ/DQS : PASS
2156 01:00:15.360410 RX DATLAT : PASS
2157 01:00:15.360496 RX DQ/DQS(Engine): PASS
2158 01:00:15.360580 TX OE : NO K
2159 01:00:15.360666 All Pass.
2160 01:00:15.360751
2161 01:00:15.360836 DramC Write-DBI off
2162 01:00:15.360921 PER_BANK_REFRESH: Hybrid Mode
2163 01:00:15.361007 TX_TRACKING: ON
2164 01:00:15.361092 [GetDramInforAfterCalByMRR] Vendor 6.
2165 01:00:15.361177 [GetDramInforAfterCalByMRR] Revision 606.
2166 01:00:15.361262 [GetDramInforAfterCalByMRR] Revision 2 0.
2167 01:00:15.361348 MR0 0x3b3b
2168 01:00:15.361434 MR8 0x5151
2169 01:00:15.361518 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 01:00:15.361603
2171 01:00:15.361688 MR0 0x3b3b
2172 01:00:15.361772 MR8 0x5151
2173 01:00:15.361856 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 01:00:15.361942
2175 01:00:15.362028 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2176 01:00:15.362115 [FAST_K] Save calibration result to emmc
2177 01:00:15.362208 [FAST_K] Save calibration result to emmc
2178 01:00:15.362294 dram_init: config_dvfs: 1
2179 01:00:15.362379 dramc_set_vcore_voltage set vcore to 662500
2180 01:00:15.362465 Read voltage for 1200, 2
2181 01:00:15.362549 Vio18 = 0
2182 01:00:15.362635 Vcore = 662500
2183 01:00:15.362720 Vdram = 0
2184 01:00:15.362805 Vddq = 0
2185 01:00:15.362889 Vmddr = 0
2186 01:00:15.362974 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2187 01:00:15.363060 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2188 01:00:15.363146 MEM_TYPE=3, freq_sel=15
2189 01:00:15.363241 sv_algorithm_assistance_LP4_1600
2190 01:00:15.363327 ============ PULL DRAM RESETB DOWN ============
2191 01:00:15.363413 ========== PULL DRAM RESETB DOWN end =========
2192 01:00:15.363498 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2193 01:00:15.363583 ===================================
2194 01:00:15.363668 LPDDR4 DRAM CONFIGURATION
2195 01:00:15.363754 ===================================
2196 01:00:15.363838 EX_ROW_EN[0] = 0x0
2197 01:00:15.363923 EX_ROW_EN[1] = 0x0
2198 01:00:15.364008 LP4Y_EN = 0x0
2199 01:00:15.364094 WORK_FSP = 0x0
2200 01:00:15.364178 WL = 0x4
2201 01:00:15.364263 RL = 0x4
2202 01:00:15.364348 BL = 0x2
2203 01:00:15.364433 RPST = 0x0
2204 01:00:15.364518 RD_PRE = 0x0
2205 01:00:15.364603 WR_PRE = 0x1
2206 01:00:15.364687 WR_PST = 0x0
2207 01:00:15.364772 DBI_WR = 0x0
2208 01:00:15.364856 DBI_RD = 0x0
2209 01:00:15.364940 OTF = 0x1
2210 01:00:15.365024 ===================================
2211 01:00:15.365109 ===================================
2212 01:00:15.365195 ANA top config
2213 01:00:15.365280 ===================================
2214 01:00:15.365365 DLL_ASYNC_EN = 0
2215 01:00:15.365459 ALL_SLAVE_EN = 0
2216 01:00:15.365533 NEW_RANK_MODE = 1
2217 01:00:15.365609 DLL_IDLE_MODE = 1
2218 01:00:15.365684 LP45_APHY_COMB_EN = 1
2219 01:00:15.365757 TX_ODT_DIS = 1
2220 01:00:15.365832 NEW_8X_MODE = 1
2221 01:00:15.365907 ===================================
2222 01:00:15.365982 ===================================
2223 01:00:15.366057 data_rate = 2400
2224 01:00:15.366131 CKR = 1
2225 01:00:15.366216 DQ_P2S_RATIO = 8
2226 01:00:15.366291 ===================================
2227 01:00:15.366376 CA_P2S_RATIO = 8
2228 01:00:15.366452 DQ_CA_OPEN = 0
2229 01:00:15.366527 DQ_SEMI_OPEN = 0
2230 01:00:15.366602 CA_SEMI_OPEN = 0
2231 01:00:15.366675 CA_FULL_RATE = 0
2232 01:00:15.366750 DQ_CKDIV4_EN = 0
2233 01:00:15.366824 CA_CKDIV4_EN = 0
2234 01:00:15.366898 CA_PREDIV_EN = 0
2235 01:00:15.366973 PH8_DLY = 17
2236 01:00:15.367048 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2237 01:00:15.367123 DQ_AAMCK_DIV = 4
2238 01:00:15.367197 CA_AAMCK_DIV = 4
2239 01:00:15.367272 CA_ADMCK_DIV = 4
2240 01:00:15.367346 DQ_TRACK_CA_EN = 0
2241 01:00:15.367420 CA_PICK = 1200
2242 01:00:15.367495 CA_MCKIO = 1200
2243 01:00:15.367569 MCKIO_SEMI = 0
2244 01:00:15.367644 PLL_FREQ = 2366
2245 01:00:15.367718 DQ_UI_PI_RATIO = 32
2246 01:00:15.367793 CA_UI_PI_RATIO = 0
2247 01:00:15.367867 ===================================
2248 01:00:15.367942 ===================================
2249 01:00:15.368017 memory_type:LPDDR4
2250 01:00:15.368092 GP_NUM : 10
2251 01:00:15.368165 SRAM_EN : 1
2252 01:00:15.368240 MD32_EN : 0
2253 01:00:15.368313 ===================================
2254 01:00:15.368388 [ANA_INIT] >>>>>>>>>>>>>>
2255 01:00:15.368463 <<<<<< [CONFIGURE PHASE]: ANA_TX
2256 01:00:15.368538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2257 01:00:15.368612 ===================================
2258 01:00:15.368687 data_rate = 2400,PCW = 0X5b00
2259 01:00:15.368976 ===================================
2260 01:00:15.369118 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2261 01:00:15.369270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 01:00:15.369396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 01:00:15.369516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2264 01:00:15.369633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2265 01:00:15.369750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2266 01:00:15.369866 [ANA_INIT] flow start
2267 01:00:15.369981 [ANA_INIT] PLL >>>>>>>>
2268 01:00:15.370097 [ANA_INIT] PLL <<<<<<<<
2269 01:00:15.370224 [ANA_INIT] MIDPI >>>>>>>>
2270 01:00:15.370341 [ANA_INIT] MIDPI <<<<<<<<
2271 01:00:15.370464 [ANA_INIT] DLL >>>>>>>>
2272 01:00:15.370567 [ANA_INIT] DLL <<<<<<<<
2273 01:00:15.370669 [ANA_INIT] flow end
2274 01:00:15.370772 ============ LP4 DIFF to SE enter ============
2275 01:00:15.370876 ============ LP4 DIFF to SE exit ============
2276 01:00:15.370980 [ANA_INIT] <<<<<<<<<<<<<
2277 01:00:15.371083 [Flow] Enable top DCM control >>>>>
2278 01:00:15.371186 [Flow] Enable top DCM control <<<<<
2279 01:00:15.371289 Enable DLL master slave shuffle
2280 01:00:15.371392 ==============================================================
2281 01:00:15.371496 Gating Mode config
2282 01:00:15.371599 ==============================================================
2283 01:00:15.371703 Config description:
2284 01:00:15.371808 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2285 01:00:15.371913 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2286 01:00:15.372018 SELPH_MODE 0: By rank 1: By Phase
2287 01:00:15.372122 ==============================================================
2288 01:00:15.372226 GAT_TRACK_EN = 1
2289 01:00:15.372332 RX_GATING_MODE = 2
2290 01:00:15.372404 RX_GATING_TRACK_MODE = 2
2291 01:00:15.372470 SELPH_MODE = 1
2292 01:00:15.372537 PICG_EARLY_EN = 1
2293 01:00:15.372603 VALID_LAT_VALUE = 1
2294 01:00:15.372669 ==============================================================
2295 01:00:15.372736 Enter into Gating configuration >>>>
2296 01:00:15.372802 Exit from Gating configuration <<<<
2297 01:00:15.372870 Enter into DVFS_PRE_config >>>>>
2298 01:00:15.372936 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2299 01:00:15.373004 Exit from DVFS_PRE_config <<<<<
2300 01:00:15.373070 Enter into PICG configuration >>>>
2301 01:00:15.373136 Exit from PICG configuration <<<<
2302 01:00:15.373202 [RX_INPUT] configuration >>>>>
2303 01:00:15.373268 [RX_INPUT] configuration <<<<<
2304 01:00:15.373333 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2305 01:00:15.373399 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2306 01:00:15.373465 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 01:00:15.373532 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 01:00:15.373599 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 01:00:15.373666 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 01:00:15.373731 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2311 01:00:15.373798 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2312 01:00:15.373864 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2313 01:00:15.373931 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2314 01:00:15.373997 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2315 01:00:15.374063 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 01:00:15.374130 ===================================
2317 01:00:15.374204 LPDDR4 DRAM CONFIGURATION
2318 01:00:15.374271 ===================================
2319 01:00:15.374337 EX_ROW_EN[0] = 0x0
2320 01:00:15.374403 EX_ROW_EN[1] = 0x0
2321 01:00:15.374469 LP4Y_EN = 0x0
2322 01:00:15.374535 WORK_FSP = 0x0
2323 01:00:15.374601 WL = 0x4
2324 01:00:15.374667 RL = 0x4
2325 01:00:15.374732 BL = 0x2
2326 01:00:15.374798 RPST = 0x0
2327 01:00:15.374872 RD_PRE = 0x0
2328 01:00:15.374939 WR_PRE = 0x1
2329 01:00:15.375059 WR_PST = 0x0
2330 01:00:15.375234 DBI_WR = 0x0
2331 01:00:15.375361 DBI_RD = 0x0
2332 01:00:15.375449 OTF = 0x1
2333 01:00:15.375514 ===================================
2334 01:00:15.375580 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2335 01:00:15.375641 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2336 01:00:15.375701 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2337 01:00:15.375766 ===================================
2338 01:00:15.375826 LPDDR4 DRAM CONFIGURATION
2339 01:00:15.375885 ===================================
2340 01:00:15.375945 EX_ROW_EN[0] = 0x10
2341 01:00:15.376004 EX_ROW_EN[1] = 0x0
2342 01:00:15.376063 LP4Y_EN = 0x0
2343 01:00:15.376121 WORK_FSP = 0x0
2344 01:00:15.376180 WL = 0x4
2345 01:00:15.376239 RL = 0x4
2346 01:00:15.376298 BL = 0x2
2347 01:00:15.376357 RPST = 0x0
2348 01:00:15.376416 RD_PRE = 0x0
2349 01:00:15.376475 WR_PRE = 0x1
2350 01:00:15.376533 WR_PST = 0x0
2351 01:00:15.376592 DBI_WR = 0x0
2352 01:00:15.376651 DBI_RD = 0x0
2353 01:00:15.376709 OTF = 0x1
2354 01:00:15.376768 ===================================
2355 01:00:15.376828 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2356 01:00:15.376888 ==
2357 01:00:15.376948 Dram Type= 6, Freq= 0, CH_0, rank 0
2358 01:00:15.377008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 01:00:15.377068 ==
2360 01:00:15.377127 [Duty_Offset_Calibration]
2361 01:00:15.377186 B0:1 B1:-1 CA:0
2362 01:00:15.377245
2363 01:00:15.377304 [DutyScan_Calibration_Flow] k_type=0
2364 01:00:15.377363
2365 01:00:15.377422 ==CLK 0==
2366 01:00:15.377481 Final CLK duty delay cell = 0
2367 01:00:15.377540 [0] MAX Duty = 5094%(X100), DQS PI = 22
2368 01:00:15.377599 [0] MIN Duty = 4875%(X100), DQS PI = 8
2369 01:00:15.377658 [0] AVG Duty = 4984%(X100)
2370 01:00:15.377717
2371 01:00:15.377776 CH0 CLK Duty spec in!! Max-Min= 219%
2372 01:00:15.378039 [DutyScan_Calibration_Flow] ====Done====
2373 01:00:15.378141
2374 01:00:15.378221 [DutyScan_Calibration_Flow] k_type=1
2375 01:00:15.378283
2376 01:00:15.378344 ==DQS 0 ==
2377 01:00:15.378405 Final DQS duty delay cell = -4
2378 01:00:15.378465 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2379 01:00:15.378525 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2380 01:00:15.378585 [-4] AVG Duty = 4968%(X100)
2381 01:00:15.378645
2382 01:00:15.378704 ==DQS 1 ==
2383 01:00:15.378764 Final DQS duty delay cell = 0
2384 01:00:15.378824 [0] MAX Duty = 5124%(X100), DQS PI = 6
2385 01:00:15.378883 [0] MIN Duty = 5000%(X100), DQS PI = 22
2386 01:00:15.378942 [0] AVG Duty = 5062%(X100)
2387 01:00:15.379000
2388 01:00:15.379060 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2389 01:00:15.379120
2390 01:00:15.379180 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2391 01:00:15.379239 [DutyScan_Calibration_Flow] ====Done====
2392 01:00:15.379299
2393 01:00:15.379358 [DutyScan_Calibration_Flow] k_type=3
2394 01:00:15.379418
2395 01:00:15.379477 ==DQM 0 ==
2396 01:00:15.379536 Final DQM duty delay cell = 0
2397 01:00:15.379595 [0] MAX Duty = 5062%(X100), DQS PI = 20
2398 01:00:15.379655 [0] MIN Duty = 4875%(X100), DQS PI = 8
2399 01:00:15.379715 [0] AVG Duty = 4968%(X100)
2400 01:00:15.379773
2401 01:00:15.379833 ==DQM 1 ==
2402 01:00:15.379892 Final DQM duty delay cell = 4
2403 01:00:15.379951 [4] MAX Duty = 5187%(X100), DQS PI = 16
2404 01:00:15.380011 [4] MIN Duty = 4969%(X100), DQS PI = 26
2405 01:00:15.380070 [4] AVG Duty = 5078%(X100)
2406 01:00:15.380129
2407 01:00:15.380189 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2408 01:00:15.380248
2409 01:00:15.380307 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2410 01:00:15.380366 [DutyScan_Calibration_Flow] ====Done====
2411 01:00:15.380437
2412 01:00:15.380491 [DutyScan_Calibration_Flow] k_type=2
2413 01:00:15.380545
2414 01:00:15.380599 ==DQ 0 ==
2415 01:00:15.380653 Final DQ duty delay cell = -4
2416 01:00:15.380709 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2417 01:00:15.380763 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2418 01:00:15.380817 [-4] AVG Duty = 4969%(X100)
2419 01:00:15.380870
2420 01:00:15.380924 ==DQ 1 ==
2421 01:00:15.380978 Final DQ duty delay cell = -4
2422 01:00:15.381031 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2423 01:00:15.381085 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2424 01:00:15.381139 [-4] AVG Duty = 4922%(X100)
2425 01:00:15.381192
2426 01:00:15.381246 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2427 01:00:15.381300
2428 01:00:15.381353 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2429 01:00:15.381407 [DutyScan_Calibration_Flow] ====Done====
2430 01:00:15.381461 ==
2431 01:00:15.381515 Dram Type= 6, Freq= 0, CH_1, rank 0
2432 01:00:15.381569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2433 01:00:15.381623 ==
2434 01:00:15.381676 [Duty_Offset_Calibration]
2435 01:00:15.381730 B0:-1 B1:1 CA:1
2436 01:00:15.381783
2437 01:00:15.381837 [DutyScan_Calibration_Flow] k_type=0
2438 01:00:15.381891
2439 01:00:15.381944 ==CLK 0==
2440 01:00:15.381999 Final CLK duty delay cell = 0
2441 01:00:15.382054 [0] MAX Duty = 5156%(X100), DQS PI = 22
2442 01:00:15.382108 [0] MIN Duty = 4969%(X100), DQS PI = 60
2443 01:00:15.382170 [0] AVG Duty = 5062%(X100)
2444 01:00:15.382227
2445 01:00:15.382282 CH1 CLK Duty spec in!! Max-Min= 187%
2446 01:00:15.382336 [DutyScan_Calibration_Flow] ====Done====
2447 01:00:15.382390
2448 01:00:15.382443 [DutyScan_Calibration_Flow] k_type=1
2449 01:00:15.382497
2450 01:00:15.382551 ==DQS 0 ==
2451 01:00:15.382605 Final DQS duty delay cell = 0
2452 01:00:15.382659 [0] MAX Duty = 5125%(X100), DQS PI = 48
2453 01:00:15.382713 [0] MIN Duty = 4875%(X100), DQS PI = 8
2454 01:00:15.382767 [0] AVG Duty = 5000%(X100)
2455 01:00:15.382821
2456 01:00:15.382874 ==DQS 1 ==
2457 01:00:15.382928 Final DQS duty delay cell = 0
2458 01:00:15.382982 [0] MAX Duty = 5062%(X100), DQS PI = 12
2459 01:00:15.383037 [0] MIN Duty = 4969%(X100), DQS PI = 56
2460 01:00:15.383091 [0] AVG Duty = 5015%(X100)
2461 01:00:15.383145
2462 01:00:15.383199 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2463 01:00:15.383252
2464 01:00:15.383307 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2465 01:00:15.383360 [DutyScan_Calibration_Flow] ====Done====
2466 01:00:15.383414
2467 01:00:15.383467 [DutyScan_Calibration_Flow] k_type=3
2468 01:00:15.383521
2469 01:00:15.383574 ==DQM 0 ==
2470 01:00:15.383629 Final DQM duty delay cell = 0
2471 01:00:15.383683 [0] MAX Duty = 5187%(X100), DQS PI = 34
2472 01:00:15.383736 [0] MIN Duty = 5031%(X100), DQS PI = 6
2473 01:00:15.383790 [0] AVG Duty = 5109%(X100)
2474 01:00:15.383844
2475 01:00:15.383897 ==DQM 1 ==
2476 01:00:15.383951 Final DQM duty delay cell = 0
2477 01:00:15.384005 [0] MAX Duty = 5156%(X100), DQS PI = 8
2478 01:00:15.384058 [0] MIN Duty = 4969%(X100), DQS PI = 28
2479 01:00:15.384112 [0] AVG Duty = 5062%(X100)
2480 01:00:15.384165
2481 01:00:15.384219 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2482 01:00:15.384273
2483 01:00:15.384327 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2484 01:00:15.384381 [DutyScan_Calibration_Flow] ====Done====
2485 01:00:15.384435
2486 01:00:15.384488 [DutyScan_Calibration_Flow] k_type=2
2487 01:00:15.384542
2488 01:00:15.384595 ==DQ 0 ==
2489 01:00:15.384649 Final DQ duty delay cell = 0
2490 01:00:15.384704 [0] MAX Duty = 5187%(X100), DQS PI = 32
2491 01:00:15.384757 [0] MIN Duty = 4907%(X100), DQS PI = 6
2492 01:00:15.384811 [0] AVG Duty = 5047%(X100)
2493 01:00:15.384865
2494 01:00:15.384918 ==DQ 1 ==
2495 01:00:15.384972 Final DQ duty delay cell = 0
2496 01:00:15.385026 [0] MAX Duty = 5124%(X100), DQS PI = 10
2497 01:00:15.385079 [0] MIN Duty = 4969%(X100), DQS PI = 0
2498 01:00:15.385133 [0] AVG Duty = 5046%(X100)
2499 01:00:15.385186
2500 01:00:15.385239 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2501 01:00:15.385294
2502 01:00:15.385348 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2503 01:00:15.385401 [DutyScan_Calibration_Flow] ====Done====
2504 01:00:15.385467 nWR fixed to 30
2505 01:00:15.385520 [ModeRegInit_LP4] CH0 RK0
2506 01:00:15.385573 [ModeRegInit_LP4] CH0 RK1
2507 01:00:15.385625 [ModeRegInit_LP4] CH1 RK0
2508 01:00:15.385677 [ModeRegInit_LP4] CH1 RK1
2509 01:00:15.385729 match AC timing 7
2510 01:00:15.385781 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2511 01:00:15.385834 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2512 01:00:15.385886 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2513 01:00:15.385939 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2514 01:00:15.385992 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2515 01:00:15.386044 ==
2516 01:00:15.386097 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 01:00:15.386150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 01:00:15.386210 ==
2519 01:00:15.386264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 01:00:15.386317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2521 01:00:15.386371 [CA 0] Center 39 (9~70) winsize 62
2522 01:00:15.386424 [CA 1] Center 39 (9~70) winsize 62
2523 01:00:15.386477 [CA 2] Center 35 (5~66) winsize 62
2524 01:00:15.386529 [CA 3] Center 35 (5~66) winsize 62
2525 01:00:15.386775 [CA 4] Center 33 (3~64) winsize 62
2526 01:00:15.386834 [CA 5] Center 33 (4~63) winsize 60
2527 01:00:15.386889
2528 01:00:15.386942 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2529 01:00:15.386995
2530 01:00:15.387048 [CATrainingPosCal] consider 1 rank data
2531 01:00:15.387101 u2DelayCellTimex100 = 270/100 ps
2532 01:00:15.387162 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2533 01:00:15.387216 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2534 01:00:15.387269 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 01:00:15.387322 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2536 01:00:15.387374 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2537 01:00:15.387427 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2538 01:00:15.387479
2539 01:00:15.387531 CA PerBit enable=1, Macro0, CA PI delay=33
2540 01:00:15.387585
2541 01:00:15.387638 [CBTSetCACLKResult] CA Dly = 33
2542 01:00:15.387691 CS Dly: 8 (0~39)
2543 01:00:15.387744 ==
2544 01:00:15.387796 Dram Type= 6, Freq= 0, CH_0, rank 1
2545 01:00:15.387848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 01:00:15.387902 ==
2547 01:00:15.387954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2548 01:00:15.388007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2549 01:00:15.388060 [CA 0] Center 39 (9~70) winsize 62
2550 01:00:15.388113 [CA 1] Center 39 (9~70) winsize 62
2551 01:00:15.388165 [CA 2] Center 35 (5~66) winsize 62
2552 01:00:15.388218 [CA 3] Center 34 (4~65) winsize 62
2553 01:00:15.388270 [CA 4] Center 33 (3~64) winsize 62
2554 01:00:15.388323 [CA 5] Center 33 (3~63) winsize 61
2555 01:00:15.388375
2556 01:00:15.388428 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2557 01:00:15.388480
2558 01:00:15.388533 [CATrainingPosCal] consider 2 rank data
2559 01:00:15.388585 u2DelayCellTimex100 = 270/100 ps
2560 01:00:15.388638 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2561 01:00:15.388691 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2562 01:00:15.388743 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 01:00:15.388796 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2564 01:00:15.388848 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2565 01:00:15.388901 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2566 01:00:15.388953
2567 01:00:15.389005 CA PerBit enable=1, Macro0, CA PI delay=33
2568 01:00:15.389057
2569 01:00:15.389110 [CBTSetCACLKResult] CA Dly = 33
2570 01:00:15.389161 CS Dly: 8 (0~40)
2571 01:00:15.389213
2572 01:00:15.389265 ----->DramcWriteLeveling(PI) begin...
2573 01:00:15.389319 ==
2574 01:00:15.389372 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 01:00:15.389425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 01:00:15.389478 ==
2577 01:00:15.389531 Write leveling (Byte 0): 32 => 32
2578 01:00:15.389584 Write leveling (Byte 1): 29 => 29
2579 01:00:15.389636 DramcWriteLeveling(PI) end<-----
2580 01:00:15.389690
2581 01:00:15.389742 ==
2582 01:00:15.389794 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 01:00:15.389846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 01:00:15.389899 ==
2585 01:00:15.389951 [Gating] SW mode calibration
2586 01:00:15.390004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2587 01:00:15.390056 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2588 01:00:15.390109 0 15 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
2589 01:00:15.390168 0 15 4 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
2590 01:00:15.390263 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2591 01:00:15.390323 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 01:00:15.390458 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 01:00:15.390579 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 01:00:15.390670 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 01:00:15.390729 0 15 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
2596 01:00:15.390784 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
2597 01:00:15.390839 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 01:00:15.390893 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 01:00:15.390947 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 01:00:15.391000 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 01:00:15.391053 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 01:00:15.391106 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 01:00:15.391160 1 0 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2604 01:00:15.391213 1 1 0 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2605 01:00:15.391266 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2606 01:00:15.391319 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 01:00:15.391373 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 01:00:15.391426 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 01:00:15.391478 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 01:00:15.391531 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 01:00:15.391584 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2612 01:00:15.391637 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2613 01:00:15.391689 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 01:00:15.391742 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 01:00:15.391795 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 01:00:15.391849 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 01:00:15.391901 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 01:00:15.391954 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 01:00:15.392007 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 01:00:15.392059 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 01:00:15.392112 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 01:00:15.392164 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 01:00:15.392217 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 01:00:15.392270 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 01:00:15.392323 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 01:00:15.392375 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 01:00:15.392428 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2628 01:00:15.392481 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2629 01:00:15.392533 Total UI for P1: 0, mck2ui 16
2630 01:00:15.392779 best dqsien dly found for B0: ( 1, 3, 28)
2631 01:00:15.392838 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2632 01:00:15.392893 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 01:00:15.392946 Total UI for P1: 0, mck2ui 16
2634 01:00:15.393000 best dqsien dly found for B1: ( 1, 4, 2)
2635 01:00:15.393052 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2636 01:00:15.393106 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2637 01:00:15.393158
2638 01:00:15.393211 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2639 01:00:15.393264 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2640 01:00:15.393317 [Gating] SW calibration Done
2641 01:00:15.393370 ==
2642 01:00:15.393423 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 01:00:15.393477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 01:00:15.393530 ==
2645 01:00:15.393583 RX Vref Scan: 0
2646 01:00:15.393635
2647 01:00:15.393687 RX Vref 0 -> 0, step: 1
2648 01:00:15.393740
2649 01:00:15.393792 RX Delay -40 -> 252, step: 8
2650 01:00:15.393845 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2651 01:00:15.393897 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2652 01:00:15.393951 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2653 01:00:15.394004 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2654 01:00:15.394056 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2655 01:00:15.394108 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2656 01:00:15.394183 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2657 01:00:15.394242 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2658 01:00:15.394301 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2659 01:00:15.394355 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2660 01:00:15.394408 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2661 01:00:15.394460 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2662 01:00:15.394513 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2663 01:00:15.394565 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2664 01:00:15.394617 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2665 01:00:15.394670 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2666 01:00:15.394722 ==
2667 01:00:15.394775 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 01:00:15.394828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 01:00:15.394881 ==
2670 01:00:15.394934 DQS Delay:
2671 01:00:15.394986 DQS0 = 0, DQS1 = 0
2672 01:00:15.395038 DQM Delay:
2673 01:00:15.395090 DQM0 = 119, DQM1 = 106
2674 01:00:15.395143 DQ Delay:
2675 01:00:15.395194 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2676 01:00:15.395247 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2677 01:00:15.395300 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2678 01:00:15.395352 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2679 01:00:15.395404
2680 01:00:15.395456
2681 01:00:15.395565 ==
2682 01:00:15.395706 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 01:00:15.395797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 01:00:15.395855 ==
2685 01:00:15.395909
2686 01:00:15.395962
2687 01:00:15.396025 TX Vref Scan disable
2688 01:00:15.396207 == TX Byte 0 ==
2689 01:00:15.396304 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2690 01:00:15.396364 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2691 01:00:15.396419 == TX Byte 1 ==
2692 01:00:15.396474 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2693 01:00:15.396528 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2694 01:00:15.396581 ==
2695 01:00:15.396634 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 01:00:15.396687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 01:00:15.396740 ==
2698 01:00:15.396794 TX Vref=22, minBit 5, minWin=25, winSum=415
2699 01:00:15.396847 TX Vref=24, minBit 13, minWin=25, winSum=426
2700 01:00:15.396901 TX Vref=26, minBit 1, minWin=26, winSum=429
2701 01:00:15.396954 TX Vref=28, minBit 13, minWin=26, winSum=434
2702 01:00:15.397007 TX Vref=30, minBit 5, minWin=26, winSum=432
2703 01:00:15.397061 TX Vref=32, minBit 4, minWin=26, winSum=427
2704 01:00:15.397114 [TxChooseVref] Worse bit 13, Min win 26, Win sum 434, Final Vref 28
2705 01:00:15.397167
2706 01:00:15.397220 Final TX Range 1 Vref 28
2707 01:00:15.397273
2708 01:00:15.397326 ==
2709 01:00:15.397379 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 01:00:15.397431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 01:00:15.397484 ==
2712 01:00:15.397537
2713 01:00:15.397589
2714 01:00:15.397641 TX Vref Scan disable
2715 01:00:15.397694 == TX Byte 0 ==
2716 01:00:15.397746 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2717 01:00:15.397800 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2718 01:00:15.397853 == TX Byte 1 ==
2719 01:00:15.397905 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2720 01:00:15.397958 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2721 01:00:15.398010
2722 01:00:15.398062 [DATLAT]
2723 01:00:15.398115 Freq=1200, CH0 RK0
2724 01:00:15.398175
2725 01:00:15.398266 DATLAT Default: 0xd
2726 01:00:15.398319 0, 0xFFFF, sum = 0
2727 01:00:15.398373 1, 0xFFFF, sum = 0
2728 01:00:15.398427 2, 0xFFFF, sum = 0
2729 01:00:15.398481 3, 0xFFFF, sum = 0
2730 01:00:15.398534 4, 0xFFFF, sum = 0
2731 01:00:15.398587 5, 0xFFFF, sum = 0
2732 01:00:15.398641 6, 0xFFFF, sum = 0
2733 01:00:15.398695 7, 0xFFFF, sum = 0
2734 01:00:15.398749 8, 0xFFFF, sum = 0
2735 01:00:15.398803 9, 0xFFFF, sum = 0
2736 01:00:15.398856 10, 0xFFFF, sum = 0
2737 01:00:15.398910 11, 0xFFFF, sum = 0
2738 01:00:15.398963 12, 0x0, sum = 1
2739 01:00:15.399017 13, 0x0, sum = 2
2740 01:00:15.399070 14, 0x0, sum = 3
2741 01:00:15.399123 15, 0x0, sum = 4
2742 01:00:15.399176 best_step = 13
2743 01:00:15.399228
2744 01:00:15.399281 ==
2745 01:00:15.399334 Dram Type= 6, Freq= 0, CH_0, rank 0
2746 01:00:15.399386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2747 01:00:15.399439 ==
2748 01:00:15.399491 RX Vref Scan: 1
2749 01:00:15.399544
2750 01:00:15.399595 Set Vref Range= 32 -> 127
2751 01:00:15.399648
2752 01:00:15.399700 RX Vref 32 -> 127, step: 1
2753 01:00:15.399752
2754 01:00:15.399805 RX Delay -21 -> 252, step: 4
2755 01:00:15.399857
2756 01:00:15.399910 Set Vref, RX VrefLevel [Byte0]: 32
2757 01:00:15.399963 [Byte1]: 32
2758 01:00:15.400016
2759 01:00:15.400068 Set Vref, RX VrefLevel [Byte0]: 33
2760 01:00:15.400120 [Byte1]: 33
2761 01:00:15.400172
2762 01:00:15.400224 Set Vref, RX VrefLevel [Byte0]: 34
2763 01:00:15.400277 [Byte1]: 34
2764 01:00:15.400329
2765 01:00:15.400381 Set Vref, RX VrefLevel [Byte0]: 35
2766 01:00:15.400433 [Byte1]: 35
2767 01:00:15.400485
2768 01:00:15.400538 Set Vref, RX VrefLevel [Byte0]: 36
2769 01:00:15.400590 [Byte1]: 36
2770 01:00:15.400642
2771 01:00:15.400694 Set Vref, RX VrefLevel [Byte0]: 37
2772 01:00:15.400746 [Byte1]: 37
2773 01:00:15.400799
2774 01:00:15.400850 Set Vref, RX VrefLevel [Byte0]: 38
2775 01:00:15.400903 [Byte1]: 38
2776 01:00:15.400955
2777 01:00:15.401007 Set Vref, RX VrefLevel [Byte0]: 39
2778 01:00:15.401061 [Byte1]: 39
2779 01:00:15.401114
2780 01:00:15.401167 Set Vref, RX VrefLevel [Byte0]: 40
2781 01:00:15.401219 [Byte1]: 40
2782 01:00:15.401271
2783 01:00:15.401516 Set Vref, RX VrefLevel [Byte0]: 41
2784 01:00:15.401578 [Byte1]: 41
2785 01:00:15.401633
2786 01:00:15.401687 Set Vref, RX VrefLevel [Byte0]: 42
2787 01:00:15.401740 [Byte1]: 42
2788 01:00:15.401793
2789 01:00:15.401846 Set Vref, RX VrefLevel [Byte0]: 43
2790 01:00:15.401900 [Byte1]: 43
2791 01:00:15.401953
2792 01:00:15.402006 Set Vref, RX VrefLevel [Byte0]: 44
2793 01:00:15.402059 [Byte1]: 44
2794 01:00:15.402112
2795 01:00:15.402188 Set Vref, RX VrefLevel [Byte0]: 45
2796 01:00:15.402260 [Byte1]: 45
2797 01:00:15.402312
2798 01:00:15.402365 Set Vref, RX VrefLevel [Byte0]: 46
2799 01:00:15.402418 [Byte1]: 46
2800 01:00:15.402470
2801 01:00:15.402522 Set Vref, RX VrefLevel [Byte0]: 47
2802 01:00:15.402574 [Byte1]: 47
2803 01:00:15.402627
2804 01:00:15.402680 Set Vref, RX VrefLevel [Byte0]: 48
2805 01:00:15.402733 [Byte1]: 48
2806 01:00:15.402785
2807 01:00:15.402838 Set Vref, RX VrefLevel [Byte0]: 49
2808 01:00:15.402891 [Byte1]: 49
2809 01:00:15.402943
2810 01:00:15.402995 Set Vref, RX VrefLevel [Byte0]: 50
2811 01:00:15.403048 [Byte1]: 50
2812 01:00:15.403100
2813 01:00:15.403152 Set Vref, RX VrefLevel [Byte0]: 51
2814 01:00:15.403204 [Byte1]: 51
2815 01:00:15.403257
2816 01:00:15.403309 Set Vref, RX VrefLevel [Byte0]: 52
2817 01:00:15.403362 [Byte1]: 52
2818 01:00:15.403414
2819 01:00:15.403466 Set Vref, RX VrefLevel [Byte0]: 53
2820 01:00:15.403520 [Byte1]: 53
2821 01:00:15.403572
2822 01:00:15.403625 Set Vref, RX VrefLevel [Byte0]: 54
2823 01:00:15.403677 [Byte1]: 54
2824 01:00:15.403730
2825 01:00:15.403782 Set Vref, RX VrefLevel [Byte0]: 55
2826 01:00:15.403834 [Byte1]: 55
2827 01:00:15.403886
2828 01:00:15.403958 Set Vref, RX VrefLevel [Byte0]: 56
2829 01:00:15.404012 [Byte1]: 56
2830 01:00:15.404066
2831 01:00:15.404128 Set Vref, RX VrefLevel [Byte0]: 57
2832 01:00:15.404182 [Byte1]: 57
2833 01:00:15.404234
2834 01:00:15.404287 Set Vref, RX VrefLevel [Byte0]: 58
2835 01:00:15.404339 [Byte1]: 58
2836 01:00:15.404391
2837 01:00:15.404444 Set Vref, RX VrefLevel [Byte0]: 59
2838 01:00:15.404497 [Byte1]: 59
2839 01:00:15.404550
2840 01:00:15.404602 Set Vref, RX VrefLevel [Byte0]: 60
2841 01:00:15.404655 [Byte1]: 60
2842 01:00:15.404707
2843 01:00:15.404759 Set Vref, RX VrefLevel [Byte0]: 61
2844 01:00:15.404812 [Byte1]: 61
2845 01:00:15.404865
2846 01:00:15.404917 Set Vref, RX VrefLevel [Byte0]: 62
2847 01:00:15.404970 [Byte1]: 62
2848 01:00:15.405022
2849 01:00:15.405075 Set Vref, RX VrefLevel [Byte0]: 63
2850 01:00:15.405127 [Byte1]: 63
2851 01:00:15.405180
2852 01:00:15.405232 Set Vref, RX VrefLevel [Byte0]: 64
2853 01:00:15.405285 [Byte1]: 64
2854 01:00:15.405338
2855 01:00:15.405390 Set Vref, RX VrefLevel [Byte0]: 65
2856 01:00:15.405443 [Byte1]: 65
2857 01:00:15.405495
2858 01:00:15.405548 Set Vref, RX VrefLevel [Byte0]: 66
2859 01:00:15.405600 [Byte1]: 66
2860 01:00:15.405653
2861 01:00:15.405705 Set Vref, RX VrefLevel [Byte0]: 67
2862 01:00:15.405758 [Byte1]: 67
2863 01:00:15.405811
2864 01:00:15.405864 Set Vref, RX VrefLevel [Byte0]: 68
2865 01:00:15.405917 [Byte1]: 68
2866 01:00:15.405969
2867 01:00:15.406021 Set Vref, RX VrefLevel [Byte0]: 69
2868 01:00:15.406074 [Byte1]: 69
2869 01:00:15.406133
2870 01:00:15.406246 Set Vref, RX VrefLevel [Byte0]: 70
2871 01:00:15.406331 [Byte1]: 70
2872 01:00:15.406387
2873 01:00:15.406441 Set Vref, RX VrefLevel [Byte0]: 71
2874 01:00:15.406495 [Byte1]: 71
2875 01:00:15.406548
2876 01:00:15.406602 Set Vref, RX VrefLevel [Byte0]: 72
2877 01:00:15.406656 [Byte1]: 72
2878 01:00:15.406709
2879 01:00:15.406762 Set Vref, RX VrefLevel [Byte0]: 73
2880 01:00:15.406815 [Byte1]: 73
2881 01:00:15.406867
2882 01:00:15.406920 Set Vref, RX VrefLevel [Byte0]: 74
2883 01:00:15.406973 [Byte1]: 74
2884 01:00:15.407026
2885 01:00:15.407079 Set Vref, RX VrefLevel [Byte0]: 75
2886 01:00:15.407139 [Byte1]: 75
2887 01:00:15.407195
2888 01:00:15.407249 Set Vref, RX VrefLevel [Byte0]: 76
2889 01:00:15.407301 [Byte1]: 76
2890 01:00:15.407354
2891 01:00:15.407407 Set Vref, RX VrefLevel [Byte0]: 77
2892 01:00:15.407459 [Byte1]: 77
2893 01:00:15.407512
2894 01:00:15.407565 Set Vref, RX VrefLevel [Byte0]: 78
2895 01:00:15.407639 [Byte1]: 78
2896 01:00:15.407697
2897 01:00:15.407808 Set Vref, RX VrefLevel [Byte0]: 79
2898 01:00:15.407955 [Byte1]: 79
2899 01:00:15.408055
2900 01:00:15.408147 Final RX Vref Byte 0 = 57 to rank0
2901 01:00:15.408240 Final RX Vref Byte 1 = 58 to rank0
2902 01:00:15.408325 Final RX Vref Byte 0 = 57 to rank1
2903 01:00:15.408407 Final RX Vref Byte 1 = 58 to rank1==
2904 01:00:15.408492 Dram Type= 6, Freq= 0, CH_0, rank 0
2905 01:00:15.408575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 01:00:15.408657 ==
2907 01:00:15.408739 DQS Delay:
2908 01:00:15.408822 DQS0 = 0, DQS1 = 0
2909 01:00:15.408903 DQM Delay:
2910 01:00:15.408985 DQM0 = 118, DQM1 = 108
2911 01:00:15.409067 DQ Delay:
2912 01:00:15.409149 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =114
2913 01:00:15.409231 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2914 01:00:15.409314 DQ8 =96, DQ9 =94, DQ10 =112, DQ11 =102
2915 01:00:15.409396 DQ12 =114, DQ13 =112, DQ14 =122, DQ15 =114
2916 01:00:15.409478
2917 01:00:15.409566
2918 01:00:15.409653 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2919 01:00:15.409802 CH0 RK0: MR19=403, MR18=11FD
2920 01:00:15.409930 CH0_RK0: MR19=0x403, MR18=0x11FD, DQSOSC=403, MR23=63, INC=40, DEC=26
2921 01:00:15.410026
2922 01:00:15.410144 ----->DramcWriteLeveling(PI) begin...
2923 01:00:15.410232 ==
2924 01:00:15.410288 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 01:00:15.410343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 01:00:15.410398 ==
2927 01:00:15.410451 Write leveling (Byte 0): 32 => 32
2928 01:00:15.410505 Write leveling (Byte 1): 29 => 29
2929 01:00:15.410558 DramcWriteLeveling(PI) end<-----
2930 01:00:15.410611
2931 01:00:15.410664 ==
2932 01:00:15.410717 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 01:00:15.410770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 01:00:15.410823 ==
2935 01:00:15.410876 [Gating] SW mode calibration
2936 01:00:15.410929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2937 01:00:15.411177 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2938 01:00:15.411256 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2939 01:00:15.411350 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2940 01:00:15.411439 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2941 01:00:15.411495 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2942 01:00:15.411549 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2943 01:00:15.411603 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2944 01:00:15.411657 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2945 01:00:15.411710 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
2946 01:00:15.411762 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2947 01:00:15.411816 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2948 01:00:15.411869 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2949 01:00:15.411922 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2950 01:00:15.411974 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2951 01:00:15.412027 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2952 01:00:15.412080 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2953 01:00:15.412132 1 0 28 | B1->B0 | 2424 3535 | 0 1 | (0 0) (0 0)
2954 01:00:15.412185 1 1 0 | B1->B0 | 3332 4444 | 1 0 | (0 0) (0 0)
2955 01:00:15.412238 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2956 01:00:15.412291 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 01:00:15.412345 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2958 01:00:15.412397 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2959 01:00:15.412450 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 01:00:15.412503 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 01:00:15.412556 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2962 01:00:15.412608 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 01:00:15.412661 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 01:00:15.412714 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 01:00:15.412767 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 01:00:15.412820 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 01:00:15.412872 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 01:00:15.412926 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 01:00:15.412978 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 01:00:15.413030 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 01:00:15.413082 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 01:00:15.413135 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 01:00:15.413188 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 01:00:15.413241 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 01:00:15.413297 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 01:00:15.595536 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2977 01:00:15.596102 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2978 01:00:15.596487 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2979 01:00:15.596825 Total UI for P1: 0, mck2ui 16
2980 01:00:15.597197 best dqsien dly found for B0: ( 1, 3, 26)
2981 01:00:15.597545 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 01:00:15.597866 Total UI for P1: 0, mck2ui 16
2983 01:00:15.598258 best dqsien dly found for B1: ( 1, 4, 0)
2984 01:00:15.598607 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2985 01:00:15.598903 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2986 01:00:15.599189
2987 01:00:15.599499 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2988 01:00:15.599807 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2989 01:00:15.600112 [Gating] SW calibration Done
2990 01:00:15.600415 ==
2991 01:00:15.600722 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 01:00:15.601026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 01:00:15.601330 ==
2994 01:00:15.601633 RX Vref Scan: 0
2995 01:00:15.601934
2996 01:00:15.602240 RX Vref 0 -> 0, step: 1
2997 01:00:15.602587
2998 01:00:15.602874 RX Delay -40 -> 252, step: 8
2999 01:00:15.603152 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3000 01:00:15.603471 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3001 01:00:15.603751 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3002 01:00:15.604028 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3003 01:00:15.604358 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3004 01:00:15.604654 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3005 01:00:15.604953 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3006 01:00:15.605229 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3007 01:00:15.605504 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3008 01:00:15.605780 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3009 01:00:15.606053 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3010 01:00:15.606372 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3011 01:00:15.606652 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3012 01:00:15.606927 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3013 01:00:15.607198 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3014 01:00:15.607498 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3015 01:00:15.607794 ==
3016 01:00:15.608088 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 01:00:15.608375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 01:00:15.608654 ==
3019 01:00:15.608929 DQS Delay:
3020 01:00:15.609202 DQS0 = 0, DQS1 = 0
3021 01:00:15.609477 DQM Delay:
3022 01:00:15.609753 DQM0 = 117, DQM1 = 108
3023 01:00:15.610028 DQ Delay:
3024 01:00:15.610349 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3025 01:00:15.610628 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
3026 01:00:15.610905 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3027 01:00:15.611181 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3028 01:00:15.611483
3029 01:00:15.611760
3030 01:00:15.612032 ==
3031 01:00:15.612306 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 01:00:15.612581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 01:00:15.612858 ==
3034 01:00:15.613184
3035 01:00:15.613463
3036 01:00:15.613735 TX Vref Scan disable
3037 01:00:15.614012 == TX Byte 0 ==
3038 01:00:15.614329 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3039 01:00:15.614611 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3040 01:00:15.614884 == TX Byte 1 ==
3041 01:00:15.615725 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3042 01:00:15.616237 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3043 01:00:15.616700 ==
3044 01:00:15.617296 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 01:00:15.617909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 01:00:15.618416 ==
3047 01:00:15.618858 TX Vref=22, minBit 1, minWin=25, winSum=422
3048 01:00:15.619294 TX Vref=24, minBit 13, minWin=25, winSum=425
3049 01:00:15.619758 TX Vref=26, minBit 1, minWin=26, winSum=428
3050 01:00:15.620200 TX Vref=28, minBit 1, minWin=26, winSum=433
3051 01:00:15.620569 TX Vref=30, minBit 8, minWin=26, winSum=433
3052 01:00:15.620872 TX Vref=32, minBit 12, minWin=26, winSum=433
3053 01:00:15.621177 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 28
3054 01:00:15.621390
3055 01:00:15.621587 Final TX Range 1 Vref 28
3056 01:00:15.621788
3057 01:00:15.621985 ==
3058 01:00:15.622205 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 01:00:15.622413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 01:00:15.622612 ==
3061 01:00:15.622810
3062 01:00:15.623005
3063 01:00:15.623200 TX Vref Scan disable
3064 01:00:15.623396 == TX Byte 0 ==
3065 01:00:15.623592 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3066 01:00:15.623788 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3067 01:00:15.623984 == TX Byte 1 ==
3068 01:00:15.624179 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3069 01:00:15.624374 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3070 01:00:15.624568
3071 01:00:15.624787 [DATLAT]
3072 01:00:15.624985 Freq=1200, CH0 RK1
3073 01:00:15.625182
3074 01:00:15.625392 DATLAT Default: 0xd
3075 01:00:15.625539 0, 0xFFFF, sum = 0
3076 01:00:15.625691 1, 0xFFFF, sum = 0
3077 01:00:15.625842 2, 0xFFFF, sum = 0
3078 01:00:15.625993 3, 0xFFFF, sum = 0
3079 01:00:15.626144 4, 0xFFFF, sum = 0
3080 01:00:15.626390 5, 0xFFFF, sum = 0
3081 01:00:15.626623 6, 0xFFFF, sum = 0
3082 01:00:15.626857 7, 0xFFFF, sum = 0
3083 01:00:15.627036 8, 0xFFFF, sum = 0
3084 01:00:15.627190 9, 0xFFFF, sum = 0
3085 01:00:15.627342 10, 0xFFFF, sum = 0
3086 01:00:15.627493 11, 0xFFFF, sum = 0
3087 01:00:15.627643 12, 0x0, sum = 1
3088 01:00:15.627794 13, 0x0, sum = 2
3089 01:00:15.627944 14, 0x0, sum = 3
3090 01:00:15.628112 15, 0x0, sum = 4
3091 01:00:15.628346 best_step = 13
3092 01:00:15.628551
3093 01:00:15.628706 ==
3094 01:00:15.628857 Dram Type= 6, Freq= 0, CH_0, rank 1
3095 01:00:15.629007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 01:00:15.629158 ==
3097 01:00:15.629305 RX Vref Scan: 0
3098 01:00:15.629455
3099 01:00:15.629603 RX Vref 0 -> 0, step: 1
3100 01:00:15.629751
3101 01:00:15.629897 RX Delay -21 -> 252, step: 4
3102 01:00:15.630045 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3103 01:00:15.630217 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3104 01:00:15.630371 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3105 01:00:15.630505 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3106 01:00:15.630625 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3107 01:00:15.630743 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3108 01:00:15.630862 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3109 01:00:15.630981 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3110 01:00:15.631113 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3111 01:00:15.631233 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3112 01:00:15.631352 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3113 01:00:15.631472 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3114 01:00:15.631591 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3115 01:00:15.631708 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3116 01:00:15.631827 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3117 01:00:15.631947 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3118 01:00:15.632065 ==
3119 01:00:15.632183 Dram Type= 6, Freq= 0, CH_0, rank 1
3120 01:00:15.632301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 01:00:15.632420 ==
3122 01:00:15.632539 DQS Delay:
3123 01:00:15.632656 DQS0 = 0, DQS1 = 0
3124 01:00:15.632774 DQM Delay:
3125 01:00:15.632892 DQM0 = 116, DQM1 = 109
3126 01:00:15.633010 DQ Delay:
3127 01:00:15.633130 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =112
3128 01:00:15.633249 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3129 01:00:15.633367 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =104
3130 01:00:15.633486 DQ12 =116, DQ13 =114, DQ14 =120, DQ15 =116
3131 01:00:15.633604
3132 01:00:15.633721
3133 01:00:15.633840 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3134 01:00:15.633963 CH0 RK1: MR19=403, MR18=BE6
3135 01:00:15.634082 CH0_RK1: MR19=0x403, MR18=0xBE6, DQSOSC=405, MR23=63, INC=39, DEC=26
3136 01:00:15.634230 [RxdqsGatingPostProcess] freq 1200
3137 01:00:15.634425 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3138 01:00:15.634610 best DQS0 dly(2T, 0.5T) = (0, 11)
3139 01:00:15.634805 best DQS1 dly(2T, 0.5T) = (0, 12)
3140 01:00:15.634936 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3141 01:00:15.635056 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3142 01:00:15.635176 best DQS0 dly(2T, 0.5T) = (0, 11)
3143 01:00:15.635295 best DQS1 dly(2T, 0.5T) = (0, 12)
3144 01:00:15.635414 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3145 01:00:15.635528 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3146 01:00:15.635627 Pre-setting of DQS Precalculation
3147 01:00:15.635725 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3148 01:00:15.635824 ==
3149 01:00:15.635923 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 01:00:15.636022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 01:00:15.636121 ==
3152 01:00:15.636219 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3153 01:00:15.636319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3154 01:00:15.636419 [CA 0] Center 37 (7~68) winsize 62
3155 01:00:15.636517 [CA 1] Center 37 (7~68) winsize 62
3156 01:00:15.636615 [CA 2] Center 34 (4~64) winsize 61
3157 01:00:15.636713 [CA 3] Center 33 (3~64) winsize 62
3158 01:00:15.636813 [CA 4] Center 34 (4~64) winsize 61
3159 01:00:15.636912 [CA 5] Center 33 (3~64) winsize 62
3160 01:00:15.637015
3161 01:00:15.637115 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3162 01:00:15.637214
3163 01:00:15.637313 [CATrainingPosCal] consider 1 rank data
3164 01:00:15.637412 u2DelayCellTimex100 = 270/100 ps
3165 01:00:15.637512 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3166 01:00:15.637611 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3167 01:00:15.637710 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3168 01:00:15.637808 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3169 01:00:15.637906 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3170 01:00:15.638005 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3171 01:00:15.638110
3172 01:00:15.638245 CA PerBit enable=1, Macro0, CA PI delay=33
3173 01:00:15.638347
3174 01:00:15.638446 [CBTSetCACLKResult] CA Dly = 33
3175 01:00:15.638783 CS Dly: 6 (0~37)
3176 01:00:15.638978 ==
3177 01:00:15.639188 Dram Type= 6, Freq= 0, CH_1, rank 1
3178 01:00:15.639397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 01:00:15.639598 ==
3180 01:00:15.639757 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3181 01:00:15.639914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3182 01:00:15.640070 [CA 0] Center 38 (8~68) winsize 61
3183 01:00:15.640224 [CA 1] Center 38 (8~68) winsize 61
3184 01:00:15.640378 [CA 2] Center 34 (4~65) winsize 62
3185 01:00:15.640524 [CA 3] Center 33 (3~64) winsize 62
3186 01:00:15.640655 [CA 4] Center 34 (3~65) winsize 63
3187 01:00:15.640787 [CA 5] Center 33 (3~64) winsize 62
3188 01:00:15.640917
3189 01:00:15.641053 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3190 01:00:15.641158
3191 01:00:15.641245 [CATrainingPosCal] consider 2 rank data
3192 01:00:15.641332 u2DelayCellTimex100 = 270/100 ps
3193 01:00:15.641420 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3194 01:00:15.641506 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3195 01:00:15.641591 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3196 01:00:15.641677 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3197 01:00:15.641762 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3198 01:00:15.641847 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3199 01:00:15.641931
3200 01:00:15.642016 CA PerBit enable=1, Macro0, CA PI delay=33
3201 01:00:15.642101
3202 01:00:15.642199 [CBTSetCACLKResult] CA Dly = 33
3203 01:00:15.642288 CS Dly: 7 (0~40)
3204 01:00:15.642373
3205 01:00:15.642458 ----->DramcWriteLeveling(PI) begin...
3206 01:00:15.642546 ==
3207 01:00:15.642631 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 01:00:15.642716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 01:00:15.642802 ==
3210 01:00:15.642887 Write leveling (Byte 0): 24 => 24
3211 01:00:15.642972 Write leveling (Byte 1): 27 => 27
3212 01:00:15.643058 DramcWriteLeveling(PI) end<-----
3213 01:00:15.643143
3214 01:00:15.643228 ==
3215 01:00:15.643313 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 01:00:15.643400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 01:00:15.643486 ==
3218 01:00:15.643572 [Gating] SW mode calibration
3219 01:00:15.643664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3220 01:00:15.643754 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3221 01:00:15.643849 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
3222 01:00:15.643939 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3223 01:00:15.644025 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3224 01:00:15.644119 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3225 01:00:15.644205 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3226 01:00:15.644292 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3227 01:00:15.644377 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
3228 01:00:15.644463 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
3229 01:00:15.644548 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3230 01:00:15.644634 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3231 01:00:15.644719 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3232 01:00:15.644804 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3233 01:00:15.644889 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3234 01:00:15.644976 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3235 01:00:15.645061 1 0 24 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
3236 01:00:15.645147 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3237 01:00:15.645231 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 01:00:15.645316 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 01:00:15.645402 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3240 01:00:15.645492 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 01:00:15.645567 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3242 01:00:15.645641 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3243 01:00:15.645715 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3244 01:00:15.645789 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3245 01:00:15.645862 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 01:00:15.645937 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 01:00:15.646012 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 01:00:15.646087 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 01:00:15.646173 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 01:00:15.646252 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 01:00:15.646326 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 01:00:15.646401 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 01:00:15.646475 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 01:00:15.646550 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 01:00:15.646625 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 01:00:15.646699 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 01:00:15.646773 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 01:00:15.646847 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 01:00:15.646922 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3260 01:00:15.646997 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3261 01:00:15.647071 Total UI for P1: 0, mck2ui 16
3262 01:00:15.647146 best dqsien dly found for B0: ( 1, 3, 24)
3263 01:00:15.647221 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3264 01:00:15.647296 Total UI for P1: 0, mck2ui 16
3265 01:00:15.647370 best dqsien dly found for B1: ( 1, 3, 28)
3266 01:00:15.647444 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3267 01:00:15.647528 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3268 01:00:15.647603
3269 01:00:15.647686 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3270 01:00:15.647762 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3271 01:00:15.647837 [Gating] SW calibration Done
3272 01:00:15.647919 ==
3273 01:00:15.647996 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 01:00:15.648071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 01:00:15.648146 ==
3276 01:00:15.648220 RX Vref Scan: 0
3277 01:00:15.648294
3278 01:00:15.648368 RX Vref 0 -> 0, step: 1
3279 01:00:15.648443
3280 01:00:15.648518 RX Delay -40 -> 252, step: 8
3281 01:00:15.648593 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3282 01:00:15.648881 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3283 01:00:15.649018 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3284 01:00:15.649172 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3285 01:00:15.649322 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3286 01:00:15.649452 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3287 01:00:15.649572 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3288 01:00:15.649689 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3289 01:00:15.649805 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3290 01:00:15.649922 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3291 01:00:15.650039 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3292 01:00:15.650155 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3293 01:00:15.650283 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3294 01:00:15.650413 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3295 01:00:15.650517 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3296 01:00:15.650621 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3297 01:00:15.650723 ==
3298 01:00:15.650827 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 01:00:15.650931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 01:00:15.651023 ==
3301 01:00:15.651097 DQS Delay:
3302 01:00:15.651166 DQS0 = 0, DQS1 = 0
3303 01:00:15.651233 DQM Delay:
3304 01:00:15.651300 DQM0 = 117, DQM1 = 108
3305 01:00:15.651366 DQ Delay:
3306 01:00:15.651433 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3307 01:00:15.651500 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3308 01:00:15.651566 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3309 01:00:15.651632 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3310 01:00:15.651698
3311 01:00:15.651764
3312 01:00:15.651830 ==
3313 01:00:15.651896 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 01:00:15.651963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 01:00:15.652030 ==
3316 01:00:15.652096
3317 01:00:15.652162
3318 01:00:15.652227 TX Vref Scan disable
3319 01:00:15.652294 == TX Byte 0 ==
3320 01:00:15.652360 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3321 01:00:15.652427 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3322 01:00:15.652493 == TX Byte 1 ==
3323 01:00:15.652559 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3324 01:00:15.652626 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3325 01:00:15.652693 ==
3326 01:00:15.652759 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 01:00:15.652826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 01:00:15.652894 ==
3329 01:00:15.652961 TX Vref=22, minBit 8, minWin=25, winSum=418
3330 01:00:15.653028 TX Vref=24, minBit 9, minWin=25, winSum=421
3331 01:00:15.653095 TX Vref=26, minBit 10, minWin=26, winSum=434
3332 01:00:15.653162 TX Vref=28, minBit 9, minWin=26, winSum=436
3333 01:00:15.653228 TX Vref=30, minBit 9, minWin=26, winSum=431
3334 01:00:15.653294 TX Vref=32, minBit 11, minWin=25, winSum=431
3335 01:00:15.653359 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 28
3336 01:00:15.653426
3337 01:00:15.653491 Final TX Range 1 Vref 28
3338 01:00:15.653558
3339 01:00:15.653623 ==
3340 01:00:15.653689 Dram Type= 6, Freq= 0, CH_1, rank 0
3341 01:00:15.653754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3342 01:00:15.653820 ==
3343 01:00:15.653884
3344 01:00:15.653949
3345 01:00:15.654014 TX Vref Scan disable
3346 01:00:15.654080 == TX Byte 0 ==
3347 01:00:15.654176 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3348 01:00:15.654253 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3349 01:00:15.654320 == TX Byte 1 ==
3350 01:00:15.654387 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3351 01:00:15.654453 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3352 01:00:15.654519
3353 01:00:15.654584 [DATLAT]
3354 01:00:15.654650 Freq=1200, CH1 RK0
3355 01:00:15.654717
3356 01:00:15.654782 DATLAT Default: 0xd
3357 01:00:15.654848 0, 0xFFFF, sum = 0
3358 01:00:15.654916 1, 0xFFFF, sum = 0
3359 01:00:15.654982 2, 0xFFFF, sum = 0
3360 01:00:15.655048 3, 0xFFFF, sum = 0
3361 01:00:15.655114 4, 0xFFFF, sum = 0
3362 01:00:15.655181 5, 0xFFFF, sum = 0
3363 01:00:15.655247 6, 0xFFFF, sum = 0
3364 01:00:15.655314 7, 0xFFFF, sum = 0
3365 01:00:15.655380 8, 0xFFFF, sum = 0
3366 01:00:15.655457 9, 0xFFFF, sum = 0
3367 01:00:15.655517 10, 0xFFFF, sum = 0
3368 01:00:15.655577 11, 0xFFFF, sum = 0
3369 01:00:15.655638 12, 0x0, sum = 1
3370 01:00:15.655698 13, 0x0, sum = 2
3371 01:00:15.655757 14, 0x0, sum = 3
3372 01:00:15.655817 15, 0x0, sum = 4
3373 01:00:15.655876 best_step = 13
3374 01:00:15.655938
3375 01:00:15.655997 ==
3376 01:00:15.656056 Dram Type= 6, Freq= 0, CH_1, rank 0
3377 01:00:15.656115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3378 01:00:15.656175 ==
3379 01:00:15.656234 RX Vref Scan: 1
3380 01:00:15.656293
3381 01:00:15.656352 Set Vref Range= 32 -> 127
3382 01:00:15.656412
3383 01:00:15.656471 RX Vref 32 -> 127, step: 1
3384 01:00:15.656529
3385 01:00:15.656588 RX Delay -21 -> 252, step: 4
3386 01:00:15.656647
3387 01:00:15.656705 Set Vref, RX VrefLevel [Byte0]: 32
3388 01:00:15.656765 [Byte1]: 32
3389 01:00:15.656824
3390 01:00:15.656882 Set Vref, RX VrefLevel [Byte0]: 33
3391 01:00:15.656941 [Byte1]: 33
3392 01:00:15.656999
3393 01:00:15.657058 Set Vref, RX VrefLevel [Byte0]: 34
3394 01:00:15.657118 [Byte1]: 34
3395 01:00:15.657176
3396 01:00:15.657235 Set Vref, RX VrefLevel [Byte0]: 35
3397 01:00:15.657294 [Byte1]: 35
3398 01:00:15.657354
3399 01:00:15.657413 Set Vref, RX VrefLevel [Byte0]: 36
3400 01:00:15.657472 [Byte1]: 36
3401 01:00:15.657540
3402 01:00:15.657637 Set Vref, RX VrefLevel [Byte0]: 37
3403 01:00:15.657730 [Byte1]: 37
3404 01:00:15.657827
3405 01:00:15.657891 Set Vref, RX VrefLevel [Byte0]: 38
3406 01:00:15.657952 [Byte1]: 38
3407 01:00:15.658012
3408 01:00:15.658072 Set Vref, RX VrefLevel [Byte0]: 39
3409 01:00:15.658131 [Byte1]: 39
3410 01:00:15.658200
3411 01:00:15.658261 Set Vref, RX VrefLevel [Byte0]: 40
3412 01:00:15.658320 [Byte1]: 40
3413 01:00:15.658379
3414 01:00:15.658438 Set Vref, RX VrefLevel [Byte0]: 41
3415 01:00:15.658498 [Byte1]: 41
3416 01:00:15.658557
3417 01:00:15.658616 Set Vref, RX VrefLevel [Byte0]: 42
3418 01:00:15.658676 [Byte1]: 42
3419 01:00:15.658735
3420 01:00:15.658794 Set Vref, RX VrefLevel [Byte0]: 43
3421 01:00:15.658853 [Byte1]: 43
3422 01:00:15.658912
3423 01:00:15.658971 Set Vref, RX VrefLevel [Byte0]: 44
3424 01:00:15.659030 [Byte1]: 44
3425 01:00:15.659089
3426 01:00:15.659148 Set Vref, RX VrefLevel [Byte0]: 45
3427 01:00:15.659207 [Byte1]: 45
3428 01:00:15.659266
3429 01:00:15.659325 Set Vref, RX VrefLevel [Byte0]: 46
3430 01:00:15.659384 [Byte1]: 46
3431 01:00:15.659442
3432 01:00:15.659501 Set Vref, RX VrefLevel [Byte0]: 47
3433 01:00:15.659560 [Byte1]: 47
3434 01:00:15.659619
3435 01:00:15.659678 Set Vref, RX VrefLevel [Byte0]: 48
3436 01:00:15.659737 [Byte1]: 48
3437 01:00:15.659795
3438 01:00:15.660059 Set Vref, RX VrefLevel [Byte0]: 49
3439 01:00:15.660130 [Byte1]: 49
3440 01:00:15.660190
3441 01:00:15.660250 Set Vref, RX VrefLevel [Byte0]: 50
3442 01:00:15.660310 [Byte1]: 50
3443 01:00:15.660370
3444 01:00:15.660440 Set Vref, RX VrefLevel [Byte0]: 51
3445 01:00:15.660495 [Byte1]: 51
3446 01:00:15.660549
3447 01:00:15.660603 Set Vref, RX VrefLevel [Byte0]: 52
3448 01:00:15.660658 [Byte1]: 52
3449 01:00:15.660711
3450 01:00:15.660765 Set Vref, RX VrefLevel [Byte0]: 53
3451 01:00:15.660819 [Byte1]: 53
3452 01:00:15.660873
3453 01:00:15.660926 Set Vref, RX VrefLevel [Byte0]: 54
3454 01:00:15.660984 [Byte1]: 54
3455 01:00:15.661039
3456 01:00:15.661098 Set Vref, RX VrefLevel [Byte0]: 55
3457 01:00:15.661153 [Byte1]: 55
3458 01:00:15.661207
3459 01:00:15.661260 Set Vref, RX VrefLevel [Byte0]: 56
3460 01:00:15.661315 [Byte1]: 56
3461 01:00:15.661370
3462 01:00:15.661424 Set Vref, RX VrefLevel [Byte0]: 57
3463 01:00:15.661478 [Byte1]: 57
3464 01:00:15.661533
3465 01:00:15.661586 Set Vref, RX VrefLevel [Byte0]: 58
3466 01:00:15.661646 [Byte1]: 58
3467 01:00:15.661701
3468 01:00:15.661755 Set Vref, RX VrefLevel [Byte0]: 59
3469 01:00:15.661815 [Byte1]: 59
3470 01:00:15.661870
3471 01:00:15.661924 Set Vref, RX VrefLevel [Byte0]: 60
3472 01:00:15.661978 [Byte1]: 60
3473 01:00:15.662032
3474 01:00:15.662086 Set Vref, RX VrefLevel [Byte0]: 61
3475 01:00:15.662139 [Byte1]: 61
3476 01:00:15.662204
3477 01:00:15.662264 Set Vref, RX VrefLevel [Byte0]: 62
3478 01:00:15.662319 [Byte1]: 62
3479 01:00:15.662373
3480 01:00:15.662429 Set Vref, RX VrefLevel [Byte0]: 63
3481 01:00:15.662484 [Byte1]: 63
3482 01:00:15.662538
3483 01:00:15.662591 Set Vref, RX VrefLevel [Byte0]: 64
3484 01:00:15.662645 [Byte1]: 64
3485 01:00:15.662698
3486 01:00:15.662751 Set Vref, RX VrefLevel [Byte0]: 65
3487 01:00:15.662805 [Byte1]: 65
3488 01:00:15.662858
3489 01:00:15.662911 Set Vref, RX VrefLevel [Byte0]: 66
3490 01:00:15.662965 [Byte1]: 66
3491 01:00:15.663019
3492 01:00:15.663072 Set Vref, RX VrefLevel [Byte0]: 67
3493 01:00:15.663126 [Byte1]: 67
3494 01:00:15.663180
3495 01:00:15.663233 Set Vref, RX VrefLevel [Byte0]: 68
3496 01:00:15.663286 [Byte1]: 68
3497 01:00:15.663340
3498 01:00:15.663393 Set Vref, RX VrefLevel [Byte0]: 69
3499 01:00:15.663446 [Byte1]: 69
3500 01:00:15.663500
3501 01:00:15.663554 Final RX Vref Byte 0 = 51 to rank0
3502 01:00:15.663609 Final RX Vref Byte 1 = 61 to rank0
3503 01:00:15.663664 Final RX Vref Byte 0 = 51 to rank1
3504 01:00:15.663718 Final RX Vref Byte 1 = 61 to rank1==
3505 01:00:15.663772 Dram Type= 6, Freq= 0, CH_1, rank 0
3506 01:00:15.663826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 01:00:15.663880 ==
3508 01:00:15.663935 DQS Delay:
3509 01:00:15.663988 DQS0 = 0, DQS1 = 0
3510 01:00:15.664042 DQM Delay:
3511 01:00:15.664096 DQM0 = 116, DQM1 = 111
3512 01:00:15.664149 DQ Delay:
3513 01:00:15.664203 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =112
3514 01:00:15.664258 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3515 01:00:15.664317 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =102
3516 01:00:15.664376 DQ12 =118, DQ13 =120, DQ14 =118, DQ15 =122
3517 01:00:15.664431
3518 01:00:15.664485
3519 01:00:15.664538 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3520 01:00:15.664593 CH1 RK0: MR19=403, MR18=1F4
3521 01:00:15.664647 CH1_RK0: MR19=0x403, MR18=0x1F4, DQSOSC=409, MR23=63, INC=39, DEC=26
3522 01:00:15.664702
3523 01:00:15.664755 ----->DramcWriteLeveling(PI) begin...
3524 01:00:15.664810 ==
3525 01:00:15.664864 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 01:00:15.664919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 01:00:15.664973 ==
3528 01:00:15.665027 Write leveling (Byte 0): 25 => 25
3529 01:00:15.665082 Write leveling (Byte 1): 28 => 28
3530 01:00:15.665136 DramcWriteLeveling(PI) end<-----
3531 01:00:15.665189
3532 01:00:15.665246 ==
3533 01:00:15.665299 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 01:00:15.665353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 01:00:15.665420 ==
3536 01:00:15.665472 [Gating] SW mode calibration
3537 01:00:15.665525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3538 01:00:15.665579 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3539 01:00:15.665632 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
3540 01:00:15.665685 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 01:00:15.665737 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 01:00:15.665791 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 01:00:15.665845 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3544 01:00:15.665898 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3545 01:00:15.665951 0 15 24 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
3546 01:00:15.666003 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (1 0) (0 0)
3547 01:00:15.666056 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 01:00:15.666108 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 01:00:15.666166 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 01:00:15.666258 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 01:00:15.666311 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3552 01:00:15.666364 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3553 01:00:15.666416 1 0 24 | B1->B0 | 3b3b 2929 | 0 0 | (0 0) (0 0)
3554 01:00:15.666470 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 01:00:15.666522 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 01:00:15.666574 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 01:00:15.666627 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 01:00:15.666680 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 01:00:15.666732 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 01:00:15.666785 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 01:00:15.666838 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3562 01:00:15.666890 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3563 01:00:15.666943 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 01:00:15.666996 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 01:00:15.667243 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 01:00:15.667304 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 01:00:15.667359 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 01:00:15.667412 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 01:00:15.667470 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 01:00:15.667524 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 01:00:15.667582 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 01:00:15.667636 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 01:00:15.667689 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 01:00:15.667742 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 01:00:15.667796 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 01:00:15.667850 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 01:00:15.667902 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3578 01:00:15.667955 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3579 01:00:15.668008 Total UI for P1: 0, mck2ui 16
3580 01:00:15.668061 best dqsien dly found for B1: ( 1, 3, 24)
3581 01:00:15.668114 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3582 01:00:15.668168 Total UI for P1: 0, mck2ui 16
3583 01:00:15.668221 best dqsien dly found for B0: ( 1, 3, 26)
3584 01:00:15.668274 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3585 01:00:15.668327 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3586 01:00:15.668380
3587 01:00:15.668433 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3588 01:00:15.668487 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3589 01:00:15.668539 [Gating] SW calibration Done
3590 01:00:15.668592 ==
3591 01:00:15.668644 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 01:00:15.668698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 01:00:15.668751 ==
3594 01:00:15.668805 RX Vref Scan: 0
3595 01:00:15.668857
3596 01:00:15.668910 RX Vref 0 -> 0, step: 1
3597 01:00:15.668963
3598 01:00:15.669015 RX Delay -40 -> 252, step: 8
3599 01:00:15.669068 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3600 01:00:15.669121 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3601 01:00:15.669173 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3602 01:00:15.669226 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3603 01:00:15.669279 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3604 01:00:15.669331 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3605 01:00:15.669384 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3606 01:00:15.669437 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3607 01:00:15.669489 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3608 01:00:15.669542 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3609 01:00:15.669595 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3610 01:00:15.669647 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3611 01:00:15.669699 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3612 01:00:15.669752 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3613 01:00:15.669806 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3614 01:00:15.669859 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3615 01:00:15.669911 ==
3616 01:00:15.669964 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 01:00:15.670017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 01:00:15.670070 ==
3619 01:00:15.670122 DQS Delay:
3620 01:00:15.670182 DQS0 = 0, DQS1 = 0
3621 01:00:15.670237 DQM Delay:
3622 01:00:15.670290 DQM0 = 116, DQM1 = 110
3623 01:00:15.670343 DQ Delay:
3624 01:00:15.670396 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3625 01:00:15.670448 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3626 01:00:15.670501 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3627 01:00:15.670553 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3628 01:00:15.670606
3629 01:00:15.670658
3630 01:00:15.670713 ==
3631 01:00:15.670798 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 01:00:15.670883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 01:00:15.670966 ==
3634 01:00:15.671047
3635 01:00:15.671117
3636 01:00:15.671170 TX Vref Scan disable
3637 01:00:15.671224 == TX Byte 0 ==
3638 01:00:15.671276 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3639 01:00:15.671334 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3640 01:00:15.671388 == TX Byte 1 ==
3641 01:00:15.671441 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3642 01:00:15.671495 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3643 01:00:15.671547 ==
3644 01:00:15.671600 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 01:00:15.671653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 01:00:15.671707 ==
3647 01:00:15.671760 TX Vref=22, minBit 8, minWin=25, winSum=421
3648 01:00:15.671813 TX Vref=24, minBit 8, minWin=26, winSum=431
3649 01:00:15.671867 TX Vref=26, minBit 8, minWin=25, winSum=432
3650 01:00:15.671920 TX Vref=28, minBit 9, minWin=26, winSum=433
3651 01:00:15.671973 TX Vref=30, minBit 8, minWin=26, winSum=432
3652 01:00:15.672025 TX Vref=32, minBit 8, minWin=26, winSum=431
3653 01:00:15.672078 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
3654 01:00:15.672132
3655 01:00:15.672185 Final TX Range 1 Vref 28
3656 01:00:15.672238
3657 01:00:15.672290 ==
3658 01:00:15.672343 Dram Type= 6, Freq= 0, CH_1, rank 1
3659 01:00:15.672396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3660 01:00:15.672449 ==
3661 01:00:15.672502
3662 01:00:15.672554
3663 01:00:15.672605 TX Vref Scan disable
3664 01:00:15.672659 == TX Byte 0 ==
3665 01:00:15.672711 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3666 01:00:15.672764 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3667 01:00:15.672816 == TX Byte 1 ==
3668 01:00:15.672869 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3669 01:00:15.672921 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3670 01:00:15.672974
3671 01:00:15.673026 [DATLAT]
3672 01:00:15.673078 Freq=1200, CH1 RK1
3673 01:00:15.673130
3674 01:00:15.673183 DATLAT Default: 0xd
3675 01:00:15.673235 0, 0xFFFF, sum = 0
3676 01:00:15.673289 1, 0xFFFF, sum = 0
3677 01:00:15.673402 2, 0xFFFF, sum = 0
3678 01:00:15.673490 3, 0xFFFF, sum = 0
3679 01:00:15.673547 4, 0xFFFF, sum = 0
3680 01:00:15.673601 5, 0xFFFF, sum = 0
3681 01:00:15.673661 6, 0xFFFF, sum = 0
3682 01:00:15.673715 7, 0xFFFF, sum = 0
3683 01:00:15.673769 8, 0xFFFF, sum = 0
3684 01:00:15.673832 9, 0xFFFF, sum = 0
3685 01:00:15.673891 10, 0xFFFF, sum = 0
3686 01:00:15.673946 11, 0xFFFF, sum = 0
3687 01:00:15.673999 12, 0x0, sum = 1
3688 01:00:15.674077 13, 0x0, sum = 2
3689 01:00:15.674188 14, 0x0, sum = 3
3690 01:00:15.674260 15, 0x0, sum = 4
3691 01:00:15.674314 best_step = 13
3692 01:00:15.674367
3693 01:00:15.674421 ==
3694 01:00:15.674474 Dram Type= 6, Freq= 0, CH_1, rank 1
3695 01:00:15.674527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3696 01:00:15.674581 ==
3697 01:00:15.674634 RX Vref Scan: 0
3698 01:00:15.674689
3699 01:00:15.674742 RX Vref 0 -> 0, step: 1
3700 01:00:15.674794
3701 01:00:15.674847 RX Delay -21 -> 252, step: 4
3702 01:00:15.675094 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3703 01:00:15.675154 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3704 01:00:15.675209 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3705 01:00:15.675263 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3706 01:00:15.675316 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3707 01:00:15.675369 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3708 01:00:15.675422 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3709 01:00:15.675475 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3710 01:00:15.675527 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3711 01:00:15.675580 iDelay=199, Bit 9, Center 98 (35 ~ 162) 128
3712 01:00:15.675633 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3713 01:00:15.675686 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3714 01:00:15.675739 iDelay=199, Bit 12, Center 118 (55 ~ 182) 128
3715 01:00:15.675791 iDelay=199, Bit 13, Center 118 (55 ~ 182) 128
3716 01:00:15.675845 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3717 01:00:15.675898 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3718 01:00:15.675950 ==
3719 01:00:15.676003 Dram Type= 6, Freq= 0, CH_1, rank 1
3720 01:00:15.676057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3721 01:00:15.676110 ==
3722 01:00:15.676163 DQS Delay:
3723 01:00:15.676216 DQS0 = 0, DQS1 = 0
3724 01:00:15.676269 DQM Delay:
3725 01:00:15.676321 DQM0 = 116, DQM1 = 110
3726 01:00:15.676374 DQ Delay:
3727 01:00:15.676427 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3728 01:00:15.676480 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =116
3729 01:00:15.676532 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =102
3730 01:00:15.676585 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =120
3731 01:00:15.676637
3732 01:00:15.676690
3733 01:00:15.676742 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6f1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3734 01:00:15.676797 CH1 RK1: MR19=303, MR18=F6F1
3735 01:00:15.676849 CH1_RK1: MR19=0x303, MR18=0xF6F1, DQSOSC=414, MR23=63, INC=38, DEC=25
3736 01:00:15.676903 [RxdqsGatingPostProcess] freq 1200
3737 01:00:15.676956 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3738 01:00:15.677010 best DQS0 dly(2T, 0.5T) = (0, 11)
3739 01:00:15.677064 best DQS1 dly(2T, 0.5T) = (0, 11)
3740 01:00:15.677116 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3741 01:00:15.677168 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3742 01:00:15.677221 best DQS0 dly(2T, 0.5T) = (0, 11)
3743 01:00:15.677280 best DQS1 dly(2T, 0.5T) = (0, 11)
3744 01:00:15.677334 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3745 01:00:15.677392 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3746 01:00:15.677445 Pre-setting of DQS Precalculation
3747 01:00:15.677498 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3748 01:00:15.677552 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3749 01:00:15.677606 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3750 01:00:15.677659
3751 01:00:15.677712
3752 01:00:15.677765 [Calibration Summary] 2400 Mbps
3753 01:00:15.677818 CH 0, Rank 0
3754 01:00:15.677872 SW Impedance : PASS
3755 01:00:15.677925 DUTY Scan : NO K
3756 01:00:15.677979 ZQ Calibration : PASS
3757 01:00:15.678031 Jitter Meter : NO K
3758 01:00:15.678084 CBT Training : PASS
3759 01:00:15.678137 Write leveling : PASS
3760 01:00:15.678223 RX DQS gating : PASS
3761 01:00:15.678290 RX DQ/DQS(RDDQC) : PASS
3762 01:00:15.678343 TX DQ/DQS : PASS
3763 01:00:15.678397 RX DATLAT : PASS
3764 01:00:15.678450 RX DQ/DQS(Engine): PASS
3765 01:00:15.678503 TX OE : NO K
3766 01:00:15.678555 All Pass.
3767 01:00:15.678609
3768 01:00:15.678662 CH 0, Rank 1
3769 01:00:15.678714 SW Impedance : PASS
3770 01:00:15.678767 DUTY Scan : NO K
3771 01:00:15.678819 ZQ Calibration : PASS
3772 01:00:15.678872 Jitter Meter : NO K
3773 01:00:15.678925 CBT Training : PASS
3774 01:00:15.678978 Write leveling : PASS
3775 01:00:15.679030 RX DQS gating : PASS
3776 01:00:15.679084 RX DQ/DQS(RDDQC) : PASS
3777 01:00:15.679137 TX DQ/DQS : PASS
3778 01:00:15.679190 RX DATLAT : PASS
3779 01:00:15.679243 RX DQ/DQS(Engine): PASS
3780 01:00:15.679296 TX OE : NO K
3781 01:00:15.679348 All Pass.
3782 01:00:15.679434
3783 01:00:15.679487 CH 1, Rank 0
3784 01:00:15.679540 SW Impedance : PASS
3785 01:00:15.679594 DUTY Scan : NO K
3786 01:00:15.679646 ZQ Calibration : PASS
3787 01:00:15.679699 Jitter Meter : NO K
3788 01:00:15.679752 CBT Training : PASS
3789 01:00:15.679804 Write leveling : PASS
3790 01:00:15.679856 RX DQS gating : PASS
3791 01:00:15.679909 RX DQ/DQS(RDDQC) : PASS
3792 01:00:15.679961 TX DQ/DQS : PASS
3793 01:00:15.680014 RX DATLAT : PASS
3794 01:00:15.680067 RX DQ/DQS(Engine): PASS
3795 01:00:15.680120 TX OE : NO K
3796 01:00:15.680172 All Pass.
3797 01:00:15.680225
3798 01:00:15.680278 CH 1, Rank 1
3799 01:00:15.680333 SW Impedance : PASS
3800 01:00:15.680388 DUTY Scan : NO K
3801 01:00:15.680444 ZQ Calibration : PASS
3802 01:00:15.680498 Jitter Meter : NO K
3803 01:00:15.680551 CBT Training : PASS
3804 01:00:15.680604 Write leveling : PASS
3805 01:00:15.680656 RX DQS gating : PASS
3806 01:00:15.680709 RX DQ/DQS(RDDQC) : PASS
3807 01:00:15.680761 TX DQ/DQS : PASS
3808 01:00:15.680814 RX DATLAT : PASS
3809 01:00:15.680867 RX DQ/DQS(Engine): PASS
3810 01:00:15.680919 TX OE : NO K
3811 01:00:15.680973 All Pass.
3812 01:00:15.681025
3813 01:00:15.681078 DramC Write-DBI off
3814 01:00:15.681131 PER_BANK_REFRESH: Hybrid Mode
3815 01:00:15.681184 TX_TRACKING: ON
3816 01:00:15.681238 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3817 01:00:15.681292 [FAST_K] Save calibration result to emmc
3818 01:00:15.681345 dramc_set_vcore_voltage set vcore to 650000
3819 01:00:15.681398 Read voltage for 600, 5
3820 01:00:15.681452 Vio18 = 0
3821 01:00:15.681506 Vcore = 650000
3822 01:00:15.681559 Vdram = 0
3823 01:00:15.681612 Vddq = 0
3824 01:00:15.681665 Vmddr = 0
3825 01:00:15.681718 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3826 01:00:15.681771 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3827 01:00:15.681825 MEM_TYPE=3, freq_sel=19
3828 01:00:15.681877 sv_algorithm_assistance_LP4_1600
3829 01:00:15.681930 ============ PULL DRAM RESETB DOWN ============
3830 01:00:15.681994 ========== PULL DRAM RESETB DOWN end =========
3831 01:00:15.682081 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3832 01:00:15.682171 ===================================
3833 01:00:15.682250 LPDDR4 DRAM CONFIGURATION
3834 01:00:15.682333 ===================================
3835 01:00:15.682416 EX_ROW_EN[0] = 0x0
3836 01:00:15.682498 EX_ROW_EN[1] = 0x0
3837 01:00:15.682776 LP4Y_EN = 0x0
3838 01:00:15.682868 WORK_FSP = 0x0
3839 01:00:15.682925 WL = 0x2
3840 01:00:15.682978 RL = 0x2
3841 01:00:15.683031 BL = 0x2
3842 01:00:15.683084 RPST = 0x0
3843 01:00:15.683137 RD_PRE = 0x0
3844 01:00:15.683189 WR_PRE = 0x1
3845 01:00:15.683241 WR_PST = 0x0
3846 01:00:15.683294 DBI_WR = 0x0
3847 01:00:15.683381 DBI_RD = 0x0
3848 01:00:15.683468 OTF = 0x1
3849 01:00:15.683550 ===================================
3850 01:00:15.683606 ===================================
3851 01:00:15.683659 ANA top config
3852 01:00:15.683713 ===================================
3853 01:00:15.683766 DLL_ASYNC_EN = 0
3854 01:00:15.683819 ALL_SLAVE_EN = 1
3855 01:00:15.683872 NEW_RANK_MODE = 1
3856 01:00:15.683926 DLL_IDLE_MODE = 1
3857 01:00:15.683984 LP45_APHY_COMB_EN = 1
3858 01:00:15.684038 TX_ODT_DIS = 1
3859 01:00:15.684094 NEW_8X_MODE = 1
3860 01:00:15.684148 ===================================
3861 01:00:15.684203 ===================================
3862 01:00:15.684256 data_rate = 1200
3863 01:00:15.684309 CKR = 1
3864 01:00:15.684362 DQ_P2S_RATIO = 8
3865 01:00:15.684415 ===================================
3866 01:00:15.684468 CA_P2S_RATIO = 8
3867 01:00:15.684521 DQ_CA_OPEN = 0
3868 01:00:15.684573 DQ_SEMI_OPEN = 0
3869 01:00:15.684626 CA_SEMI_OPEN = 0
3870 01:00:15.684678 CA_FULL_RATE = 0
3871 01:00:15.684731 DQ_CKDIV4_EN = 1
3872 01:00:15.684784 CA_CKDIV4_EN = 1
3873 01:00:15.684836 CA_PREDIV_EN = 0
3874 01:00:15.684888 PH8_DLY = 0
3875 01:00:15.684941 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3876 01:00:15.684995 DQ_AAMCK_DIV = 4
3877 01:00:15.685047 CA_AAMCK_DIV = 4
3878 01:00:15.685100 CA_ADMCK_DIV = 4
3879 01:00:15.685152 DQ_TRACK_CA_EN = 0
3880 01:00:15.685204 CA_PICK = 600
3881 01:00:15.685257 CA_MCKIO = 600
3882 01:00:15.685309 MCKIO_SEMI = 0
3883 01:00:15.685362 PLL_FREQ = 2288
3884 01:00:15.685415 DQ_UI_PI_RATIO = 32
3885 01:00:15.685471 CA_UI_PI_RATIO = 0
3886 01:00:15.685531 ===================================
3887 01:00:15.685585 ===================================
3888 01:00:15.685638 memory_type:LPDDR4
3889 01:00:15.685691 GP_NUM : 10
3890 01:00:15.685747 SRAM_EN : 1
3891 01:00:15.685802 MD32_EN : 0
3892 01:00:15.685854 ===================================
3893 01:00:15.685907 [ANA_INIT] >>>>>>>>>>>>>>
3894 01:00:15.685960 <<<<<< [CONFIGURE PHASE]: ANA_TX
3895 01:00:15.686013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3896 01:00:15.686066 ===================================
3897 01:00:15.686119 data_rate = 1200,PCW = 0X5800
3898 01:00:15.686179 ===================================
3899 01:00:15.686234 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3900 01:00:15.686288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3901 01:00:15.686342 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3902 01:00:15.686394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3903 01:00:15.686447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3904 01:00:15.686500 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3905 01:00:15.686553 [ANA_INIT] flow start
3906 01:00:15.686605 [ANA_INIT] PLL >>>>>>>>
3907 01:00:15.686658 [ANA_INIT] PLL <<<<<<<<
3908 01:00:15.686711 [ANA_INIT] MIDPI >>>>>>>>
3909 01:00:15.686764 [ANA_INIT] MIDPI <<<<<<<<
3910 01:00:15.686816 [ANA_INIT] DLL >>>>>>>>
3911 01:00:15.686868 [ANA_INIT] flow end
3912 01:00:15.686921 ============ LP4 DIFF to SE enter ============
3913 01:00:15.686974 ============ LP4 DIFF to SE exit ============
3914 01:00:15.687027 [ANA_INIT] <<<<<<<<<<<<<
3915 01:00:15.687085 [Flow] Enable top DCM control >>>>>
3916 01:00:15.687139 [Flow] Enable top DCM control <<<<<
3917 01:00:15.687197 Enable DLL master slave shuffle
3918 01:00:15.687251 ==============================================================
3919 01:00:15.687305 Gating Mode config
3920 01:00:15.687358 ==============================================================
3921 01:00:15.687411 Config description:
3922 01:00:15.687464 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3923 01:00:15.687517 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3924 01:00:15.687571 SELPH_MODE 0: By rank 1: By Phase
3925 01:00:15.687624 ==============================================================
3926 01:00:15.687677 GAT_TRACK_EN = 1
3927 01:00:15.687730 RX_GATING_MODE = 2
3928 01:00:15.687783 RX_GATING_TRACK_MODE = 2
3929 01:00:15.687835 SELPH_MODE = 1
3930 01:00:15.687888 PICG_EARLY_EN = 1
3931 01:00:15.687941 VALID_LAT_VALUE = 1
3932 01:00:15.687993 ==============================================================
3933 01:00:15.688046 Enter into Gating configuration >>>>
3934 01:00:15.688099 Exit from Gating configuration <<<<
3935 01:00:15.688152 Enter into DVFS_PRE_config >>>>>
3936 01:00:15.688206 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3937 01:00:15.688263 Exit from DVFS_PRE_config <<<<<
3938 01:00:15.688317 Enter into PICG configuration >>>>
3939 01:00:15.688369 Exit from PICG configuration <<<<
3940 01:00:15.688421 [RX_INPUT] configuration >>>>>
3941 01:00:15.688474 [RX_INPUT] configuration <<<<<
3942 01:00:15.688526 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3943 01:00:15.688579 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3944 01:00:15.688632 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3945 01:00:15.688684 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3946 01:00:15.688737 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3947 01:00:15.688980 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3948 01:00:15.689039 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3949 01:00:15.689094 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3950 01:00:15.689147 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3951 01:00:15.689200 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3952 01:00:15.689254 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3953 01:00:15.689307 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3954 01:00:15.689416 ===================================
3955 01:00:15.689483 LPDDR4 DRAM CONFIGURATION
3956 01:00:15.689535 ===================================
3957 01:00:15.689588 EX_ROW_EN[0] = 0x0
3958 01:00:15.689641 EX_ROW_EN[1] = 0x0
3959 01:00:15.689693 LP4Y_EN = 0x0
3960 01:00:15.689746 WORK_FSP = 0x0
3961 01:00:15.689798 WL = 0x2
3962 01:00:15.689851 RL = 0x2
3963 01:00:15.689903 BL = 0x2
3964 01:00:15.689955 RPST = 0x0
3965 01:00:15.690008 RD_PRE = 0x0
3966 01:00:15.690060 WR_PRE = 0x1
3967 01:00:15.690112 WR_PST = 0x0
3968 01:00:15.690169 DBI_WR = 0x0
3969 01:00:15.690263 DBI_RD = 0x0
3970 01:00:15.690315 OTF = 0x1
3971 01:00:15.690368 ===================================
3972 01:00:15.690421 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3973 01:00:16.017267 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3974 01:00:16.017809 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3975 01:00:16.018222 ===================================
3976 01:00:16.018581 LPDDR4 DRAM CONFIGURATION
3977 01:00:16.018913 ===================================
3978 01:00:16.019238 EX_ROW_EN[0] = 0x10
3979 01:00:16.019557 EX_ROW_EN[1] = 0x0
3980 01:00:16.019867 LP4Y_EN = 0x0
3981 01:00:16.020174 WORK_FSP = 0x0
3982 01:00:16.020550 WL = 0x2
3983 01:00:16.020883 RL = 0x2
3984 01:00:16.021208 BL = 0x2
3985 01:00:16.021533 RPST = 0x0
3986 01:00:16.021840 RD_PRE = 0x0
3987 01:00:16.022146 WR_PRE = 0x1
3988 01:00:16.022482 WR_PST = 0x0
3989 01:00:16.022785 DBI_WR = 0x0
3990 01:00:16.023084 DBI_RD = 0x0
3991 01:00:16.023383 OTF = 0x1
3992 01:00:16.023687 ===================================
3993 01:00:16.023989 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3994 01:00:16.024295 nWR fixed to 30
3995 01:00:16.024601 [ModeRegInit_LP4] CH0 RK0
3996 01:00:16.024903 [ModeRegInit_LP4] CH0 RK1
3997 01:00:16.025200 [ModeRegInit_LP4] CH1 RK0
3998 01:00:16.025637 [ModeRegInit_LP4] CH1 RK1
3999 01:00:16.026070 match AC timing 17
4000 01:00:16.026405 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4001 01:00:16.026692 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4002 01:00:16.027055 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4003 01:00:16.027528 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4004 01:00:16.027875 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4005 01:00:16.028161 ==
4006 01:00:16.028441 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 01:00:16.028719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 01:00:16.028999 ==
4009 01:00:16.029342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4010 01:00:16.029668 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4011 01:00:16.029974 [CA 0] Center 36 (6~66) winsize 61
4012 01:00:16.030320 [CA 1] Center 36 (6~66) winsize 61
4013 01:00:16.030838 [CA 2] Center 34 (3~65) winsize 63
4014 01:00:16.031217 [CA 3] Center 34 (4~65) winsize 62
4015 01:00:16.031530 [CA 4] Center 33 (3~64) winsize 62
4016 01:00:16.031832 [CA 5] Center 33 (3~64) winsize 62
4017 01:00:16.032137
4018 01:00:16.032456 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4019 01:00:16.032732
4020 01:00:16.033005 [CATrainingPosCal] consider 1 rank data
4021 01:00:16.033280 u2DelayCellTimex100 = 270/100 ps
4022 01:00:16.033555 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4023 01:00:16.033831 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4024 01:00:16.034107 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4025 01:00:16.034424 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4026 01:00:16.034700 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4027 01:00:16.034971 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4028 01:00:16.035245
4029 01:00:16.035519 CA PerBit enable=1, Macro0, CA PI delay=33
4030 01:00:16.035882
4031 01:00:16.036250 [CBTSetCACLKResult] CA Dly = 33
4032 01:00:16.036548 CS Dly: 5 (0~36)
4033 01:00:16.036830 ==
4034 01:00:16.037104 Dram Type= 6, Freq= 0, CH_0, rank 1
4035 01:00:16.037379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 01:00:16.037655 ==
4037 01:00:16.037928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4038 01:00:16.038235 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4039 01:00:16.038520 [CA 0] Center 36 (6~66) winsize 61
4040 01:00:16.038809 [CA 1] Center 36 (6~66) winsize 61
4041 01:00:16.039120 [CA 2] Center 33 (3~64) winsize 62
4042 01:00:16.039394 [CA 3] Center 33 (3~64) winsize 62
4043 01:00:16.039667 [CA 4] Center 33 (2~64) winsize 63
4044 01:00:16.039941 [CA 5] Center 33 (3~64) winsize 62
4045 01:00:16.040212
4046 01:00:16.040481 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4047 01:00:16.040753
4048 01:00:16.041024 [CATrainingPosCal] consider 2 rank data
4049 01:00:16.041299 u2DelayCellTimex100 = 270/100 ps
4050 01:00:16.041570 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4051 01:00:16.041842 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4052 01:00:16.042113 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4053 01:00:16.042420 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4054 01:00:16.042696 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4055 01:00:16.042968 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4056 01:00:16.043242
4057 01:00:16.043514 CA PerBit enable=1, Macro0, CA PI delay=33
4058 01:00:16.043789
4059 01:00:16.044060 [CBTSetCACLKResult] CA Dly = 33
4060 01:00:16.044333 CS Dly: 5 (0~37)
4061 01:00:16.044606
4062 01:00:16.044879 ----->DramcWriteLeveling(PI) begin...
4063 01:00:16.045196 ==
4064 01:00:16.045487 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 01:00:16.045697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 01:00:16.045896 ==
4067 01:00:16.046093 Write leveling (Byte 0): 33 => 33
4068 01:00:16.046318 Write leveling (Byte 1): 28 => 28
4069 01:00:16.046517 DramcWriteLeveling(PI) end<-----
4070 01:00:16.046722
4071 01:00:16.046918 ==
4072 01:00:16.047113 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 01:00:16.047312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 01:00:16.047512 ==
4075 01:00:16.047729 [Gating] SW mode calibration
4076 01:00:16.048319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4077 01:00:16.048556 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4078 01:00:16.048765 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4079 01:00:16.048970 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4080 01:00:16.049171 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4081 01:00:16.049371 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4082 01:00:16.049571 0 9 16 | B1->B0 | 2d2d 2727 | 1 0 | (1 0) (0 0)
4083 01:00:16.049769 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 01:00:16.049968 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 01:00:16.050192 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 01:00:16.050432 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 01:00:16.050661 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 01:00:16.050820 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4089 01:00:16.050971 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4090 01:00:16.051119 0 10 16 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (0 0)
4091 01:00:16.051269 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 01:00:16.051419 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 01:00:16.051614 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 01:00:16.051769 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 01:00:16.051918 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 01:00:16.052068 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 01:00:16.052216 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4098 01:00:16.052365 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 01:00:16.052513 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 01:00:16.052661 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 01:00:16.052807 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 01:00:16.052956 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 01:00:16.053103 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 01:00:16.053251 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 01:00:16.053397 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 01:00:16.053545 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 01:00:16.053694 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 01:00:16.053894 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 01:00:16.054080 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 01:00:16.054258 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 01:00:16.054411 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 01:00:16.054561 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 01:00:16.054708 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 01:00:16.054857 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4115 01:00:16.055014 Total UI for P1: 0, mck2ui 16
4116 01:00:16.055167 best dqsien dly found for B0: ( 0, 13, 14)
4117 01:00:16.055315 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4118 01:00:16.055460 Total UI for P1: 0, mck2ui 16
4119 01:00:16.055578 best dqsien dly found for B1: ( 0, 13, 16)
4120 01:00:16.055698 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4121 01:00:16.055815 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4122 01:00:16.055935
4123 01:00:16.056054 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4124 01:00:16.056174 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4125 01:00:16.056292 [Gating] SW calibration Done
4126 01:00:16.056411 ==
4127 01:00:16.056530 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 01:00:16.056649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 01:00:16.056769 ==
4130 01:00:16.056887 RX Vref Scan: 0
4131 01:00:16.057005
4132 01:00:16.057123 RX Vref 0 -> 0, step: 1
4133 01:00:16.057241
4134 01:00:16.057359 RX Delay -230 -> 252, step: 16
4135 01:00:16.057478 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4136 01:00:16.057598 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4137 01:00:16.057717 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4138 01:00:16.057834 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4139 01:00:16.057952 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4140 01:00:16.058099 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4141 01:00:16.058268 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4142 01:00:16.061170 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4143 01:00:16.064314 iDelay=218, Bit 8, Center 33 (-134 ~ 201) 336
4144 01:00:16.067501 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4145 01:00:16.074524 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4146 01:00:16.077858 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4147 01:00:16.080690 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4148 01:00:16.084310 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4149 01:00:16.091102 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4150 01:00:16.094607 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4151 01:00:16.094929 ==
4152 01:00:16.097673 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 01:00:16.100867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 01:00:16.101206 ==
4155 01:00:16.104172 DQS Delay:
4156 01:00:16.104424 DQS0 = 0, DQS1 = 0
4157 01:00:16.104618 DQM Delay:
4158 01:00:16.107165 DQM0 = 41, DQM1 = 34
4159 01:00:16.107405 DQ Delay:
4160 01:00:16.110657 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4161 01:00:16.114448 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4162 01:00:16.117594 DQ8 =33, DQ9 =25, DQ10 =33, DQ11 =33
4163 01:00:16.120362 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4164 01:00:16.120917
4165 01:00:16.121295
4166 01:00:16.121715 ==
4167 01:00:16.124090 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 01:00:16.130489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 01:00:16.130964 ==
4170 01:00:16.131332
4171 01:00:16.131676
4172 01:00:16.132006 TX Vref Scan disable
4173 01:00:16.134287 == TX Byte 0 ==
4174 01:00:16.137696 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4175 01:00:16.144410 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4176 01:00:16.144923 == TX Byte 1 ==
4177 01:00:16.147179 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4178 01:00:16.154071 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4179 01:00:16.154620 ==
4180 01:00:16.157290 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 01:00:16.160366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 01:00:16.160796 ==
4183 01:00:16.161130
4184 01:00:16.161440
4185 01:00:16.164156 TX Vref Scan disable
4186 01:00:16.167014 == TX Byte 0 ==
4187 01:00:16.170735 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4188 01:00:16.173564 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4189 01:00:16.177239 == TX Byte 1 ==
4190 01:00:16.180084 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4191 01:00:16.183741 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4192 01:00:16.184262
4193 01:00:16.186833 [DATLAT]
4194 01:00:16.187350 Freq=600, CH0 RK0
4195 01:00:16.187690
4196 01:00:16.190199 DATLAT Default: 0x9
4197 01:00:16.190623 0, 0xFFFF, sum = 0
4198 01:00:16.193533 1, 0xFFFF, sum = 0
4199 01:00:16.194051 2, 0xFFFF, sum = 0
4200 01:00:16.196641 3, 0xFFFF, sum = 0
4201 01:00:16.197164 4, 0xFFFF, sum = 0
4202 01:00:16.200035 5, 0xFFFF, sum = 0
4203 01:00:16.200463 6, 0xFFFF, sum = 0
4204 01:00:16.203265 7, 0xFFFF, sum = 0
4205 01:00:16.203692 8, 0x0, sum = 1
4206 01:00:16.206654 9, 0x0, sum = 2
4207 01:00:16.207082 10, 0x0, sum = 3
4208 01:00:16.210254 11, 0x0, sum = 4
4209 01:00:16.210751 best_step = 9
4210 01:00:16.211089
4211 01:00:16.211403 ==
4212 01:00:16.213257 Dram Type= 6, Freq= 0, CH_0, rank 0
4213 01:00:16.217122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 01:00:16.217659 ==
4215 01:00:16.220352 RX Vref Scan: 1
4216 01:00:16.220773
4217 01:00:16.223264 RX Vref 0 -> 0, step: 1
4218 01:00:16.223686
4219 01:00:16.224022 RX Delay -179 -> 252, step: 8
4220 01:00:16.226975
4221 01:00:16.227393 Set Vref, RX VrefLevel [Byte0]: 57
4222 01:00:16.229603 [Byte1]: 58
4223 01:00:16.234666
4224 01:00:16.235087 Final RX Vref Byte 0 = 57 to rank0
4225 01:00:16.238006 Final RX Vref Byte 1 = 58 to rank0
4226 01:00:16.241398 Final RX Vref Byte 0 = 57 to rank1
4227 01:00:16.245058 Final RX Vref Byte 1 = 58 to rank1==
4228 01:00:16.247904 Dram Type= 6, Freq= 0, CH_0, rank 0
4229 01:00:16.254830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 01:00:16.255391 ==
4231 01:00:16.255794 DQS Delay:
4232 01:00:16.257758 DQS0 = 0, DQS1 = 0
4233 01:00:16.258201 DQM Delay:
4234 01:00:16.258552 DQM0 = 43, DQM1 = 32
4235 01:00:16.261479 DQ Delay:
4236 01:00:16.264873 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4237 01:00:16.267860 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4238 01:00:16.271114 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4239 01:00:16.274782 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4240 01:00:16.275306
4241 01:00:16.275643
4242 01:00:16.281131 [DQSOSCAuto] RK0, (LSB)MR18= 0x6942, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4243 01:00:16.284228 CH0 RK0: MR19=808, MR18=6942
4244 01:00:16.290763 CH0_RK0: MR19=0x808, MR18=0x6942, DQSOSC=390, MR23=63, INC=172, DEC=114
4245 01:00:16.291185
4246 01:00:16.294145 ----->DramcWriteLeveling(PI) begin...
4247 01:00:16.294710 ==
4248 01:00:16.297053 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 01:00:16.300717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 01:00:16.301294 ==
4251 01:00:16.303841 Write leveling (Byte 0): 34 => 34
4252 01:00:16.306888 Write leveling (Byte 1): 31 => 31
4253 01:00:16.310609 DramcWriteLeveling(PI) end<-----
4254 01:00:16.311138
4255 01:00:16.311479 ==
4256 01:00:16.313684 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 01:00:16.320200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 01:00:16.320710 ==
4259 01:00:16.321045 [Gating] SW mode calibration
4260 01:00:16.330206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4261 01:00:16.333659 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4262 01:00:16.336729 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4263 01:00:16.343342 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4264 01:00:16.346661 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4265 01:00:16.350130 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 1) (1 0)
4266 01:00:16.356483 0 9 16 | B1->B0 | 2e2e 2828 | 1 1 | (1 0) (1 0)
4267 01:00:16.359588 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 01:00:16.366319 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 01:00:16.369946 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 01:00:16.373245 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 01:00:16.379435 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 01:00:16.382736 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4273 01:00:16.386005 0 10 12 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
4274 01:00:16.389575 0 10 16 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
4275 01:00:16.396276 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 01:00:16.399487 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 01:00:16.402903 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 01:00:16.409481 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 01:00:16.412942 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 01:00:16.415960 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 01:00:16.422305 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 01:00:16.425767 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 01:00:16.429493 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 01:00:16.435504 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 01:00:16.438781 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 01:00:16.442097 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 01:00:16.449102 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 01:00:16.452334 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 01:00:16.455561 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 01:00:16.462243 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 01:00:16.465399 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 01:00:16.468951 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 01:00:16.475042 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 01:00:16.478411 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 01:00:16.481828 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 01:00:16.488094 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 01:00:16.492233 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4298 01:00:16.495125 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 01:00:16.498094 Total UI for P1: 0, mck2ui 16
4300 01:00:16.501663 best dqsien dly found for B0: ( 0, 13, 12)
4301 01:00:16.504667 Total UI for P1: 0, mck2ui 16
4302 01:00:16.508187 best dqsien dly found for B1: ( 0, 13, 14)
4303 01:00:16.511643 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4304 01:00:16.517875 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4305 01:00:16.518410
4306 01:00:16.521269 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4307 01:00:16.524376 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4308 01:00:16.528310 [Gating] SW calibration Done
4309 01:00:16.528860 ==
4310 01:00:16.531116 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 01:00:16.534438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 01:00:16.534871 ==
4313 01:00:16.537813 RX Vref Scan: 0
4314 01:00:16.538268
4315 01:00:16.538613 RX Vref 0 -> 0, step: 1
4316 01:00:16.538930
4317 01:00:16.540821 RX Delay -230 -> 252, step: 16
4318 01:00:16.547464 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4319 01:00:16.551352 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4320 01:00:16.553864 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4321 01:00:16.557609 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4322 01:00:16.560952 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4323 01:00:16.567650 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4324 01:00:16.570687 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4325 01:00:16.574007 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4326 01:00:16.577450 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4327 01:00:16.583934 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4328 01:00:16.587553 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4329 01:00:16.590263 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4330 01:00:16.593562 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4331 01:00:16.600381 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4332 01:00:16.603531 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4333 01:00:16.606863 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4334 01:00:16.607284 ==
4335 01:00:16.610100 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 01:00:16.613174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 01:00:16.616763 ==
4338 01:00:16.617063 DQS Delay:
4339 01:00:16.617301 DQS0 = 0, DQS1 = 0
4340 01:00:16.620025 DQM Delay:
4341 01:00:16.620322 DQM0 = 42, DQM1 = 36
4342 01:00:16.623208 DQ Delay:
4343 01:00:16.623432 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4344 01:00:16.626541 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4345 01:00:16.629598 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4346 01:00:16.633021 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4347 01:00:16.636405
4348 01:00:16.636628
4349 01:00:16.636806 ==
4350 01:00:16.639566 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 01:00:16.643016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 01:00:16.643243 ==
4353 01:00:16.643422
4354 01:00:16.643590
4355 01:00:16.646032 TX Vref Scan disable
4356 01:00:16.646436 == TX Byte 0 ==
4357 01:00:16.652691 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4358 01:00:16.656234 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4359 01:00:16.656591 == TX Byte 1 ==
4360 01:00:16.662775 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4361 01:00:16.666322 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4362 01:00:16.666743 ==
4363 01:00:16.669267 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 01:00:16.672753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 01:00:16.673271 ==
4366 01:00:16.673606
4367 01:00:16.675942
4368 01:00:16.676359 TX Vref Scan disable
4369 01:00:16.679590 == TX Byte 0 ==
4370 01:00:16.682687 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4371 01:00:16.689257 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4372 01:00:16.689678 == TX Byte 1 ==
4373 01:00:16.692563 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4374 01:00:16.699032 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4375 01:00:16.699475
4376 01:00:16.699812 [DATLAT]
4377 01:00:16.700123 Freq=600, CH0 RK1
4378 01:00:16.700425
4379 01:00:16.702530 DATLAT Default: 0x9
4380 01:00:16.702949 0, 0xFFFF, sum = 0
4381 01:00:16.706093 1, 0xFFFF, sum = 0
4382 01:00:16.709223 2, 0xFFFF, sum = 0
4383 01:00:16.709808 3, 0xFFFF, sum = 0
4384 01:00:16.712272 4, 0xFFFF, sum = 0
4385 01:00:16.712692 5, 0xFFFF, sum = 0
4386 01:00:16.715834 6, 0xFFFF, sum = 0
4387 01:00:16.716255 7, 0xFFFF, sum = 0
4388 01:00:16.719410 8, 0x0, sum = 1
4389 01:00:16.719829 9, 0x0, sum = 2
4390 01:00:16.720164 10, 0x0, sum = 3
4391 01:00:16.722502 11, 0x0, sum = 4
4392 01:00:16.722955 best_step = 9
4393 01:00:16.723318
4394 01:00:16.725513 ==
4395 01:00:16.725959 Dram Type= 6, Freq= 0, CH_0, rank 1
4396 01:00:16.732327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 01:00:16.732881 ==
4398 01:00:16.733362 RX Vref Scan: 0
4399 01:00:16.733819
4400 01:00:16.735543 RX Vref 0 -> 0, step: 1
4401 01:00:16.735960
4402 01:00:16.738822 RX Delay -195 -> 252, step: 8
4403 01:00:16.745530 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4404 01:00:16.748564 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4405 01:00:16.752273 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4406 01:00:16.755595 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4407 01:00:16.759061 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4408 01:00:16.765441 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4409 01:00:16.768876 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4410 01:00:16.772171 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4411 01:00:16.775595 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4412 01:00:16.781827 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4413 01:00:16.785004 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4414 01:00:16.788277 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4415 01:00:16.791439 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4416 01:00:16.798021 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4417 01:00:16.801509 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4418 01:00:16.805145 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4419 01:00:16.805706 ==
4420 01:00:16.808362 Dram Type= 6, Freq= 0, CH_0, rank 1
4421 01:00:16.811849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 01:00:16.814578 ==
4423 01:00:16.815040 DQS Delay:
4424 01:00:16.815411 DQS0 = 0, DQS1 = 0
4425 01:00:16.817916 DQM Delay:
4426 01:00:16.818673 DQM0 = 41, DQM1 = 35
4427 01:00:16.821523 DQ Delay:
4428 01:00:16.824695 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4429 01:00:16.825259 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4430 01:00:16.827744 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4431 01:00:16.834274 DQ12 =40, DQ13 =44, DQ14 =44, DQ15 =40
4432 01:00:16.834743
4433 01:00:16.835110
4434 01:00:16.841100 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4435 01:00:16.844506 CH0 RK1: MR19=808, MR18=5E12
4436 01:00:16.851359 CH0_RK1: MR19=0x808, MR18=0x5E12, DQSOSC=392, MR23=63, INC=170, DEC=113
4437 01:00:16.854123 [RxdqsGatingPostProcess] freq 600
4438 01:00:16.857775 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4439 01:00:16.860809 Pre-setting of DQS Precalculation
4440 01:00:16.867458 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4441 01:00:16.868009 ==
4442 01:00:16.870494 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 01:00:16.874515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 01:00:16.875075 ==
4445 01:00:16.880577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 01:00:16.887237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4447 01:00:16.890746 [CA 0] Center 35 (5~66) winsize 62
4448 01:00:16.893981 [CA 1] Center 35 (5~66) winsize 62
4449 01:00:16.897218 [CA 2] Center 34 (3~65) winsize 63
4450 01:00:16.900557 [CA 3] Center 33 (3~64) winsize 62
4451 01:00:16.903640 [CA 4] Center 34 (4~65) winsize 62
4452 01:00:16.907444 [CA 5] Center 33 (3~64) winsize 62
4453 01:00:16.908008
4454 01:00:16.910432 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4455 01:00:16.910897
4456 01:00:16.913815 [CATrainingPosCal] consider 1 rank data
4457 01:00:16.916962 u2DelayCellTimex100 = 270/100 ps
4458 01:00:16.920243 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4459 01:00:16.923564 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4460 01:00:16.927008 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4461 01:00:16.930140 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4462 01:00:16.933427 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 01:00:16.936489 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 01:00:16.936967
4465 01:00:16.943362 CA PerBit enable=1, Macro0, CA PI delay=33
4466 01:00:16.943862
4467 01:00:16.944195 [CBTSetCACLKResult] CA Dly = 33
4468 01:00:16.946814 CS Dly: 3 (0~34)
4469 01:00:16.947233 ==
4470 01:00:16.949979 Dram Type= 6, Freq= 0, CH_1, rank 1
4471 01:00:16.952819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 01:00:16.953243 ==
4473 01:00:16.959969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4474 01:00:16.966640 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4475 01:00:16.970273 [CA 0] Center 35 (5~66) winsize 62
4476 01:00:16.972914 [CA 1] Center 36 (6~66) winsize 61
4477 01:00:16.976548 [CA 2] Center 34 (4~65) winsize 62
4478 01:00:16.979515 [CA 3] Center 34 (4~65) winsize 62
4479 01:00:16.982840 [CA 4] Center 34 (4~65) winsize 62
4480 01:00:16.986056 [CA 5] Center 34 (3~65) winsize 63
4481 01:00:16.986531
4482 01:00:16.989654 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4483 01:00:16.990243
4484 01:00:16.992644 [CATrainingPosCal] consider 2 rank data
4485 01:00:16.995989 u2DelayCellTimex100 = 270/100 ps
4486 01:00:16.999216 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4487 01:00:17.002439 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4488 01:00:17.005679 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4489 01:00:17.009200 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4490 01:00:17.015864 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4491 01:00:17.018968 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4492 01:00:17.019470
4493 01:00:17.022023 CA PerBit enable=1, Macro0, CA PI delay=33
4494 01:00:17.022543
4495 01:00:17.025697 [CBTSetCACLKResult] CA Dly = 33
4496 01:00:17.026120 CS Dly: 4 (0~37)
4497 01:00:17.026489
4498 01:00:17.028961 ----->DramcWriteLeveling(PI) begin...
4499 01:00:17.029479 ==
4500 01:00:17.032101 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 01:00:17.039127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 01:00:17.039684 ==
4503 01:00:17.042012 Write leveling (Byte 0): 29 => 29
4504 01:00:17.045346 Write leveling (Byte 1): 30 => 30
4505 01:00:17.048559 DramcWriteLeveling(PI) end<-----
4506 01:00:17.049029
4507 01:00:17.049585 ==
4508 01:00:17.051995 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 01:00:17.055185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 01:00:17.055654 ==
4511 01:00:17.058338 [Gating] SW mode calibration
4512 01:00:17.065427 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4513 01:00:17.071844 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4514 01:00:17.074891 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4515 01:00:17.078203 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4516 01:00:17.085024 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4517 01:00:17.088044 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4518 01:00:17.091567 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 01:00:17.098395 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 01:00:17.101646 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 01:00:17.104262 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 01:00:17.111187 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 01:00:17.114864 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4524 01:00:17.117986 0 10 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
4525 01:00:17.121478 0 10 12 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (0 0)
4526 01:00:17.128041 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4527 01:00:17.130839 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 01:00:17.134434 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 01:00:17.141030 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 01:00:17.144618 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 01:00:17.147889 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 01:00:17.154111 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 01:00:17.157416 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4534 01:00:17.161019 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 01:00:17.167585 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 01:00:17.170767 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 01:00:17.173871 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 01:00:17.180476 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 01:00:17.184490 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 01:00:17.187459 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 01:00:17.193868 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 01:00:17.197413 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 01:00:17.200781 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 01:00:17.207006 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 01:00:17.210336 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 01:00:17.214035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 01:00:17.220840 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 01:00:17.223704 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 01:00:17.227111 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4550 01:00:17.233723 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4551 01:00:17.237183 Total UI for P1: 0, mck2ui 16
4552 01:00:17.240132 best dqsien dly found for B0: ( 0, 13, 12)
4553 01:00:17.240598 Total UI for P1: 0, mck2ui 16
4554 01:00:17.246820 best dqsien dly found for B1: ( 0, 13, 12)
4555 01:00:17.250548 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4556 01:00:17.253481 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4557 01:00:17.254046
4558 01:00:17.256354 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4559 01:00:17.259944 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4560 01:00:17.263294 [Gating] SW calibration Done
4561 01:00:17.263757 ==
4562 01:00:17.266390 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 01:00:17.269910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 01:00:17.270553 ==
4565 01:00:17.272743 RX Vref Scan: 0
4566 01:00:17.273222
4567 01:00:17.276306 RX Vref 0 -> 0, step: 1
4568 01:00:17.276802
4569 01:00:17.277189 RX Delay -230 -> 252, step: 16
4570 01:00:17.283177 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4571 01:00:17.286366 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4572 01:00:17.289399 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4573 01:00:17.292777 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4574 01:00:17.299492 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4575 01:00:17.302898 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4576 01:00:17.306120 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4577 01:00:17.309377 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4578 01:00:17.316277 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4579 01:00:17.319020 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4580 01:00:17.322562 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4581 01:00:17.325883 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4582 01:00:17.332528 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4583 01:00:17.335902 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4584 01:00:17.339013 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4585 01:00:17.342275 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4586 01:00:17.342745 ==
4587 01:00:17.345473 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 01:00:17.352391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 01:00:17.352957 ==
4590 01:00:17.353330 DQS Delay:
4591 01:00:17.355608 DQS0 = 0, DQS1 = 0
4592 01:00:17.356075 DQM Delay:
4593 01:00:17.356443 DQM0 = 42, DQM1 = 32
4594 01:00:17.358741 DQ Delay:
4595 01:00:17.362027 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4596 01:00:17.365556 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4597 01:00:17.368693 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4598 01:00:17.371985 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4599 01:00:17.372460
4600 01:00:17.372828
4601 01:00:17.373171 ==
4602 01:00:17.375464 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 01:00:17.378668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 01:00:17.379139 ==
4605 01:00:17.379513
4606 01:00:17.379854
4607 01:00:17.382058 TX Vref Scan disable
4608 01:00:17.385373 == TX Byte 0 ==
4609 01:00:17.388352 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4610 01:00:17.391981 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4611 01:00:17.395079 == TX Byte 1 ==
4612 01:00:17.398585 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4613 01:00:17.401818 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4614 01:00:17.402421 ==
4615 01:00:17.405001 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 01:00:17.411524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 01:00:17.412085 ==
4618 01:00:17.412457
4619 01:00:17.412799
4620 01:00:17.413128 TX Vref Scan disable
4621 01:00:17.415605 == TX Byte 0 ==
4622 01:00:17.418783 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4623 01:00:17.425516 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4624 01:00:17.426395 == TX Byte 1 ==
4625 01:00:17.428553 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4626 01:00:17.435288 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4627 01:00:17.435772
4628 01:00:17.436140 [DATLAT]
4629 01:00:17.436487 Freq=600, CH1 RK0
4630 01:00:17.436821
4631 01:00:17.438831 DATLAT Default: 0x9
4632 01:00:17.439305 0, 0xFFFF, sum = 0
4633 01:00:17.441686 1, 0xFFFF, sum = 0
4634 01:00:17.444839 2, 0xFFFF, sum = 0
4635 01:00:17.445310 3, 0xFFFF, sum = 0
4636 01:00:17.448244 4, 0xFFFF, sum = 0
4637 01:00:17.448834 5, 0xFFFF, sum = 0
4638 01:00:17.451839 6, 0xFFFF, sum = 0
4639 01:00:17.452271 7, 0xFFFF, sum = 0
4640 01:00:17.454824 8, 0x0, sum = 1
4641 01:00:17.455251 9, 0x0, sum = 2
4642 01:00:17.458572 10, 0x0, sum = 3
4643 01:00:17.458999 11, 0x0, sum = 4
4644 01:00:17.459345 best_step = 9
4645 01:00:17.459972
4646 01:00:17.461760 ==
4647 01:00:17.462484 Dram Type= 6, Freq= 0, CH_1, rank 0
4648 01:00:17.468006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 01:00:17.468469 ==
4650 01:00:17.468806 RX Vref Scan: 1
4651 01:00:17.469116
4652 01:00:17.471553 RX Vref 0 -> 0, step: 1
4653 01:00:17.471973
4654 01:00:17.474616 RX Delay -195 -> 252, step: 8
4655 01:00:17.475040
4656 01:00:17.478117 Set Vref, RX VrefLevel [Byte0]: 51
4657 01:00:17.480780 [Byte1]: 61
4658 01:00:17.481007
4659 01:00:17.484212 Final RX Vref Byte 0 = 51 to rank0
4660 01:00:17.487775 Final RX Vref Byte 1 = 61 to rank0
4661 01:00:17.490847 Final RX Vref Byte 0 = 51 to rank1
4662 01:00:17.494035 Final RX Vref Byte 1 = 61 to rank1==
4663 01:00:17.497337 Dram Type= 6, Freq= 0, CH_1, rank 0
4664 01:00:17.503942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 01:00:17.504063 ==
4666 01:00:17.504156 DQS Delay:
4667 01:00:17.504243 DQS0 = 0, DQS1 = 0
4668 01:00:17.507021 DQM Delay:
4669 01:00:17.507128 DQM0 = 45, DQM1 = 34
4670 01:00:17.510416 DQ Delay:
4671 01:00:17.514049 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4672 01:00:17.516975 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =44
4673 01:00:17.520381 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4674 01:00:17.523931 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4675 01:00:17.524018
4676 01:00:17.524084
4677 01:00:17.529960 [DQSOSCAuto] RK0, (LSB)MR18= 0x5237, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4678 01:00:17.533335 CH1 RK0: MR19=808, MR18=5237
4679 01:00:17.540397 CH1_RK0: MR19=0x808, MR18=0x5237, DQSOSC=394, MR23=63, INC=168, DEC=112
4680 01:00:17.540489
4681 01:00:17.543015 ----->DramcWriteLeveling(PI) begin...
4682 01:00:17.543100 ==
4683 01:00:17.546648 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 01:00:17.549883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 01:00:17.549993 ==
4686 01:00:17.553232 Write leveling (Byte 0): 30 => 30
4687 01:00:17.556596 Write leveling (Byte 1): 29 => 29
4688 01:00:17.560041 DramcWriteLeveling(PI) end<-----
4689 01:00:17.560123
4690 01:00:17.560188 ==
4691 01:00:17.563020 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 01:00:17.566789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 01:00:17.570051 ==
4694 01:00:17.570506 [Gating] SW mode calibration
4695 01:00:17.580050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4696 01:00:17.583260 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4697 01:00:17.586447 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4698 01:00:17.593054 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4699 01:00:17.596244 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4700 01:00:17.599851 0 9 12 | B1->B0 | 3030 3232 | 0 0 | (0 0) (0 0)
4701 01:00:17.605923 0 9 16 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
4702 01:00:17.609361 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 01:00:17.612495 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 01:00:17.619182 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 01:00:17.622424 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 01:00:17.626074 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4707 01:00:17.632221 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4708 01:00:17.635609 0 10 12 | B1->B0 | 3636 2c2c | 0 0 | (0 0) (0 0)
4709 01:00:17.638648 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4710 01:00:17.645295 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 01:00:17.648663 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 01:00:17.652149 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 01:00:17.658619 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 01:00:17.661802 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 01:00:17.665012 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 01:00:17.671548 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4717 01:00:17.674974 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 01:00:17.678420 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 01:00:17.684772 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 01:00:17.688123 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 01:00:17.691486 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 01:00:17.698234 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 01:00:17.701789 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 01:00:17.704947 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 01:00:17.711711 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 01:00:17.714835 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 01:00:17.718094 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 01:00:17.724462 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 01:00:17.727804 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 01:00:17.731319 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 01:00:17.738040 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 01:00:17.741307 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4733 01:00:17.744407 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4734 01:00:17.747569 Total UI for P1: 0, mck2ui 16
4735 01:00:17.750982 best dqsien dly found for B0: ( 0, 13, 14)
4736 01:00:17.754305 Total UI for P1: 0, mck2ui 16
4737 01:00:17.757308 best dqsien dly found for B1: ( 0, 13, 12)
4738 01:00:17.761130 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4739 01:00:17.764213 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4740 01:00:17.767563
4741 01:00:17.770905 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4742 01:00:17.774079 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4743 01:00:17.777407 [Gating] SW calibration Done
4744 01:00:17.777572 ==
4745 01:00:17.780756 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 01:00:17.784080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 01:00:17.784240 ==
4748 01:00:17.784367 RX Vref Scan: 0
4749 01:00:17.787778
4750 01:00:17.787938 RX Vref 0 -> 0, step: 1
4751 01:00:17.788065
4752 01:00:17.790501 RX Delay -230 -> 252, step: 16
4753 01:00:17.794002 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4754 01:00:17.800679 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4755 01:00:17.803709 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4756 01:00:17.806918 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4757 01:00:17.810129 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4758 01:00:17.816915 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4759 01:00:17.820689 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4760 01:00:17.823608 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4761 01:00:17.826948 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4762 01:00:17.830454 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4763 01:00:17.837402 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4764 01:00:17.840067 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4765 01:00:17.843428 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4766 01:00:17.846864 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4767 01:00:17.853436 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4768 01:00:17.856907 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4769 01:00:17.857329 ==
4770 01:00:17.860409 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 01:00:17.863636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 01:00:17.864063 ==
4773 01:00:17.866891 DQS Delay:
4774 01:00:17.867608 DQS0 = 0, DQS1 = 0
4775 01:00:17.869908 DQM Delay:
4776 01:00:17.870627 DQM0 = 39, DQM1 = 37
4777 01:00:17.871235 DQ Delay:
4778 01:00:17.873557 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4779 01:00:17.876475 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4780 01:00:17.880107 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4781 01:00:17.883169 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4782 01:00:17.883591
4783 01:00:17.883922
4784 01:00:17.886738 ==
4785 01:00:17.887291 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 01:00:17.893171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 01:00:17.893604 ==
4788 01:00:17.893945
4789 01:00:17.894291
4790 01:00:17.896580 TX Vref Scan disable
4791 01:00:17.897170 == TX Byte 0 ==
4792 01:00:17.902659 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4793 01:00:17.906180 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4794 01:00:17.906607 == TX Byte 1 ==
4795 01:00:17.912957 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4796 01:00:17.915935 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4797 01:00:17.916358 ==
4798 01:00:17.919443 Dram Type= 6, Freq= 0, CH_1, rank 1
4799 01:00:17.922482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4800 01:00:17.922909 ==
4801 01:00:17.923246
4802 01:00:17.923555
4803 01:00:17.926262 TX Vref Scan disable
4804 01:00:17.929329 == TX Byte 0 ==
4805 01:00:17.932864 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4806 01:00:17.936305 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4807 01:00:17.939349 == TX Byte 1 ==
4808 01:00:17.942604 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4809 01:00:17.946366 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4810 01:00:17.946931
4811 01:00:17.949418 [DATLAT]
4812 01:00:17.949882 Freq=600, CH1 RK1
4813 01:00:17.950303
4814 01:00:17.952229 DATLAT Default: 0x9
4815 01:00:17.952692 0, 0xFFFF, sum = 0
4816 01:00:17.955792 1, 0xFFFF, sum = 0
4817 01:00:17.956367 2, 0xFFFF, sum = 0
4818 01:00:17.959417 3, 0xFFFF, sum = 0
4819 01:00:17.960185 4, 0xFFFF, sum = 0
4820 01:00:17.962276 5, 0xFFFF, sum = 0
4821 01:00:17.962745 6, 0xFFFF, sum = 0
4822 01:00:17.966108 7, 0xFFFF, sum = 0
4823 01:00:17.966612 8, 0x0, sum = 1
4824 01:00:17.969192 9, 0x0, sum = 2
4825 01:00:17.969661 10, 0x0, sum = 3
4826 01:00:17.972767 11, 0x0, sum = 4
4827 01:00:17.973339 best_step = 9
4828 01:00:17.973711
4829 01:00:17.974052 ==
4830 01:00:17.975855 Dram Type= 6, Freq= 0, CH_1, rank 1
4831 01:00:17.981914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4832 01:00:17.982411 ==
4833 01:00:17.982765 RX Vref Scan: 0
4834 01:00:17.983079
4835 01:00:17.985348 RX Vref 0 -> 0, step: 1
4836 01:00:17.985769
4837 01:00:17.988853 RX Delay -179 -> 252, step: 8
4838 01:00:17.991997 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4839 01:00:17.998712 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4840 01:00:18.001950 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4841 01:00:18.005318 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4842 01:00:18.008360 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4843 01:00:18.015459 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4844 01:00:18.018751 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4845 01:00:18.021703 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4846 01:00:18.025222 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4847 01:00:18.028241 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4848 01:00:18.034872 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4849 01:00:18.038428 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4850 01:00:18.041515 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4851 01:00:18.044932 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4852 01:00:18.051435 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4853 01:00:18.054654 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4854 01:00:18.055122 ==
4855 01:00:18.058624 Dram Type= 6, Freq= 0, CH_1, rank 1
4856 01:00:18.061250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4857 01:00:18.061728 ==
4858 01:00:18.064952 DQS Delay:
4859 01:00:18.065525 DQS0 = 0, DQS1 = 0
4860 01:00:18.068164 DQM Delay:
4861 01:00:18.068795 DQM0 = 42, DQM1 = 35
4862 01:00:18.069356 DQ Delay:
4863 01:00:18.071424 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4864 01:00:18.074346 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4865 01:00:18.077816 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4866 01:00:18.080973 DQ12 =48, DQ13 =40, DQ14 =44, DQ15 =44
4867 01:00:18.081450
4868 01:00:18.081785
4869 01:00:18.091179 [DQSOSCAuto] RK1, (LSB)MR18= 0x281d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4870 01:00:18.094489 CH1 RK1: MR19=808, MR18=281D
4871 01:00:18.101000 CH1_RK1: MR19=0x808, MR18=0x281D, DQSOSC=402, MR23=63, INC=162, DEC=108
4872 01:00:18.101426 [RxdqsGatingPostProcess] freq 600
4873 01:00:18.107730 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4874 01:00:18.110898 Pre-setting of DQS Precalculation
4875 01:00:18.114412 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4876 01:00:18.124727 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4877 01:00:18.130409 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4878 01:00:18.130879
4879 01:00:18.131244
4880 01:00:18.133848 [Calibration Summary] 1200 Mbps
4881 01:00:18.134355 CH 0, Rank 0
4882 01:00:18.137126 SW Impedance : PASS
4883 01:00:18.140274 DUTY Scan : NO K
4884 01:00:18.140700 ZQ Calibration : PASS
4885 01:00:18.143396 Jitter Meter : NO K
4886 01:00:18.143811 CBT Training : PASS
4887 01:00:18.146955 Write leveling : PASS
4888 01:00:18.150267 RX DQS gating : PASS
4889 01:00:18.150827 RX DQ/DQS(RDDQC) : PASS
4890 01:00:18.154113 TX DQ/DQS : PASS
4891 01:00:18.157055 RX DATLAT : PASS
4892 01:00:18.157630 RX DQ/DQS(Engine): PASS
4893 01:00:18.160561 TX OE : NO K
4894 01:00:18.161129 All Pass.
4895 01:00:18.161499
4896 01:00:18.163540 CH 0, Rank 1
4897 01:00:18.164125 SW Impedance : PASS
4898 01:00:18.166937 DUTY Scan : NO K
4899 01:00:18.169992 ZQ Calibration : PASS
4900 01:00:18.170500 Jitter Meter : NO K
4901 01:00:18.173289 CBT Training : PASS
4902 01:00:18.176641 Write leveling : PASS
4903 01:00:18.177104 RX DQS gating : PASS
4904 01:00:18.179827 RX DQ/DQS(RDDQC) : PASS
4905 01:00:18.183679 TX DQ/DQS : PASS
4906 01:00:18.184275 RX DATLAT : PASS
4907 01:00:18.186566 RX DQ/DQS(Engine): PASS
4908 01:00:18.189668 TX OE : NO K
4909 01:00:18.190128 All Pass.
4910 01:00:18.190580
4911 01:00:18.191136 CH 1, Rank 0
4912 01:00:18.193664 SW Impedance : PASS
4913 01:00:18.196269 DUTY Scan : NO K
4914 01:00:18.196726 ZQ Calibration : PASS
4915 01:00:18.200060 Jitter Meter : NO K
4916 01:00:18.203048 CBT Training : PASS
4917 01:00:18.203604 Write leveling : PASS
4918 01:00:18.206347 RX DQS gating : PASS
4919 01:00:18.209562 RX DQ/DQS(RDDQC) : PASS
4920 01:00:18.210021 TX DQ/DQS : PASS
4921 01:00:18.212929 RX DATLAT : PASS
4922 01:00:18.213341 RX DQ/DQS(Engine): PASS
4923 01:00:18.216430 TX OE : NO K
4924 01:00:18.216946 All Pass.
4925 01:00:18.217277
4926 01:00:18.219440 CH 1, Rank 1
4927 01:00:18.219853 SW Impedance : PASS
4928 01:00:18.222896 DUTY Scan : NO K
4929 01:00:18.226228 ZQ Calibration : PASS
4930 01:00:18.226647 Jitter Meter : NO K
4931 01:00:18.229453 CBT Training : PASS
4932 01:00:18.233014 Write leveling : PASS
4933 01:00:18.233535 RX DQS gating : PASS
4934 01:00:18.235921 RX DQ/DQS(RDDQC) : PASS
4935 01:00:18.239248 TX DQ/DQS : PASS
4936 01:00:18.239668 RX DATLAT : PASS
4937 01:00:18.242637 RX DQ/DQS(Engine): PASS
4938 01:00:18.245895 TX OE : NO K
4939 01:00:18.246338 All Pass.
4940 01:00:18.246671
4941 01:00:18.249303 DramC Write-DBI off
4942 01:00:18.249715 PER_BANK_REFRESH: Hybrid Mode
4943 01:00:18.252443 TX_TRACKING: ON
4944 01:00:18.262442 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4945 01:00:18.265674 [FAST_K] Save calibration result to emmc
4946 01:00:18.269324 dramc_set_vcore_voltage set vcore to 662500
4947 01:00:18.269865 Read voltage for 933, 3
4948 01:00:18.272101 Vio18 = 0
4949 01:00:18.272537 Vcore = 662500
4950 01:00:18.272981 Vdram = 0
4951 01:00:18.275641 Vddq = 0
4952 01:00:18.276170 Vmddr = 0
4953 01:00:18.278851 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4954 01:00:18.285470 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4955 01:00:18.288656 MEM_TYPE=3, freq_sel=17
4956 01:00:18.292074 sv_algorithm_assistance_LP4_1600
4957 01:00:18.295465 ============ PULL DRAM RESETB DOWN ============
4958 01:00:18.298598 ========== PULL DRAM RESETB DOWN end =========
4959 01:00:18.305130 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4960 01:00:18.308089 ===================================
4961 01:00:18.308554 LPDDR4 DRAM CONFIGURATION
4962 01:00:18.312166 ===================================
4963 01:00:18.315408 EX_ROW_EN[0] = 0x0
4964 01:00:18.318608 EX_ROW_EN[1] = 0x0
4965 01:00:18.319229 LP4Y_EN = 0x0
4966 01:00:18.321812 WORK_FSP = 0x0
4967 01:00:18.322425 WL = 0x3
4968 01:00:18.325210 RL = 0x3
4969 01:00:18.325780 BL = 0x2
4970 01:00:18.328251 RPST = 0x0
4971 01:00:18.328717 RD_PRE = 0x0
4972 01:00:18.331478 WR_PRE = 0x1
4973 01:00:18.331939 WR_PST = 0x0
4974 01:00:18.334733 DBI_WR = 0x0
4975 01:00:18.335197 DBI_RD = 0x0
4976 01:00:18.338557 OTF = 0x1
4977 01:00:18.341715 ===================================
4978 01:00:18.344664 ===================================
4979 01:00:18.345130 ANA top config
4980 01:00:18.348150 ===================================
4981 01:00:18.351191 DLL_ASYNC_EN = 0
4982 01:00:18.354741 ALL_SLAVE_EN = 1
4983 01:00:18.357904 NEW_RANK_MODE = 1
4984 01:00:18.358480 DLL_IDLE_MODE = 1
4985 01:00:18.361357 LP45_APHY_COMB_EN = 1
4986 01:00:18.364610 TX_ODT_DIS = 1
4987 01:00:18.367835 NEW_8X_MODE = 1
4988 01:00:18.371599 ===================================
4989 01:00:18.374484 ===================================
4990 01:00:18.378238 data_rate = 1866
4991 01:00:18.378781 CKR = 1
4992 01:00:18.381383 DQ_P2S_RATIO = 8
4993 01:00:18.384212 ===================================
4994 01:00:18.387954 CA_P2S_RATIO = 8
4995 01:00:18.391174 DQ_CA_OPEN = 0
4996 01:00:18.394788 DQ_SEMI_OPEN = 0
4997 01:00:18.398077 CA_SEMI_OPEN = 0
4998 01:00:18.398644 CA_FULL_RATE = 0
4999 01:00:18.401339 DQ_CKDIV4_EN = 1
5000 01:00:18.404156 CA_CKDIV4_EN = 1
5001 01:00:18.407716 CA_PREDIV_EN = 0
5002 01:00:18.410984 PH8_DLY = 0
5003 01:00:18.414265 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5004 01:00:18.414846 DQ_AAMCK_DIV = 4
5005 01:00:18.417913 CA_AAMCK_DIV = 4
5006 01:00:18.420805 CA_ADMCK_DIV = 4
5007 01:00:18.424365 DQ_TRACK_CA_EN = 0
5008 01:00:18.427386 CA_PICK = 933
5009 01:00:18.430508 CA_MCKIO = 933
5010 01:00:18.433903 MCKIO_SEMI = 0
5011 01:00:18.434524 PLL_FREQ = 3732
5012 01:00:18.437368 DQ_UI_PI_RATIO = 32
5013 01:00:18.440678 CA_UI_PI_RATIO = 0
5014 01:00:18.443729 ===================================
5015 01:00:18.447250 ===================================
5016 01:00:18.450276 memory_type:LPDDR4
5017 01:00:18.453558 GP_NUM : 10
5018 01:00:18.454024 SRAM_EN : 1
5019 01:00:18.457025 MD32_EN : 0
5020 01:00:18.459962 ===================================
5021 01:00:18.460429 [ANA_INIT] >>>>>>>>>>>>>>
5022 01:00:18.463494 <<<<<< [CONFIGURE PHASE]: ANA_TX
5023 01:00:18.466874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5024 01:00:18.470046 ===================================
5025 01:00:18.473421 data_rate = 1866,PCW = 0X8f00
5026 01:00:18.476812 ===================================
5027 01:00:18.479948 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5028 01:00:18.486514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5029 01:00:18.493232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5030 01:00:18.496512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5031 01:00:18.499776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5032 01:00:18.503201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5033 01:00:18.506282 [ANA_INIT] flow start
5034 01:00:18.506847 [ANA_INIT] PLL >>>>>>>>
5035 01:00:18.509532 [ANA_INIT] PLL <<<<<<<<
5036 01:00:18.512752 [ANA_INIT] MIDPI >>>>>>>>
5037 01:00:18.515878 [ANA_INIT] MIDPI <<<<<<<<
5038 01:00:18.516344 [ANA_INIT] DLL >>>>>>>>
5039 01:00:18.519169 [ANA_INIT] flow end
5040 01:00:18.522840 ============ LP4 DIFF to SE enter ============
5041 01:00:18.525736 ============ LP4 DIFF to SE exit ============
5042 01:00:18.529181 [ANA_INIT] <<<<<<<<<<<<<
5043 01:00:18.532726 [Flow] Enable top DCM control >>>>>
5044 01:00:18.535666 [Flow] Enable top DCM control <<<<<
5045 01:00:18.539176 Enable DLL master slave shuffle
5046 01:00:18.546308 ==============================================================
5047 01:00:18.546855 Gating Mode config
5048 01:00:18.552343 ==============================================================
5049 01:00:18.552775 Config description:
5050 01:00:18.562085 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5051 01:00:18.569114 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5052 01:00:18.575421 SELPH_MODE 0: By rank 1: By Phase
5053 01:00:18.578697 ==============================================================
5054 01:00:18.582050 GAT_TRACK_EN = 1
5055 01:00:18.585271 RX_GATING_MODE = 2
5056 01:00:18.588749 RX_GATING_TRACK_MODE = 2
5057 01:00:18.591677 SELPH_MODE = 1
5058 01:00:18.595357 PICG_EARLY_EN = 1
5059 01:00:18.598508 VALID_LAT_VALUE = 1
5060 01:00:18.605155 ==============================================================
5061 01:00:18.608622 Enter into Gating configuration >>>>
5062 01:00:18.612068 Exit from Gating configuration <<<<
5063 01:00:18.615016 Enter into DVFS_PRE_config >>>>>
5064 01:00:18.624595 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5065 01:00:18.628432 Exit from DVFS_PRE_config <<<<<
5066 01:00:18.631705 Enter into PICG configuration >>>>
5067 01:00:18.634769 Exit from PICG configuration <<<<
5068 01:00:18.638661 [RX_INPUT] configuration >>>>>
5069 01:00:18.639172 [RX_INPUT] configuration <<<<<
5070 01:00:18.644698 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5071 01:00:18.651113 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5072 01:00:18.657884 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5073 01:00:18.661245 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5074 01:00:18.668078 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5075 01:00:18.674559 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5076 01:00:18.677743 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5077 01:00:18.684398 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5078 01:00:18.687888 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5079 01:00:18.691085 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5080 01:00:18.694272 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5081 01:00:18.700953 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5082 01:00:18.703872 ===================================
5083 01:00:18.704336 LPDDR4 DRAM CONFIGURATION
5084 01:00:18.707533 ===================================
5085 01:00:18.710669 EX_ROW_EN[0] = 0x0
5086 01:00:18.714216 EX_ROW_EN[1] = 0x0
5087 01:00:18.714730 LP4Y_EN = 0x0
5088 01:00:18.717292 WORK_FSP = 0x0
5089 01:00:18.717857 WL = 0x3
5090 01:00:18.720557 RL = 0x3
5091 01:00:18.721271 BL = 0x2
5092 01:00:18.723774 RPST = 0x0
5093 01:00:18.724237 RD_PRE = 0x0
5094 01:00:18.726826 WR_PRE = 0x1
5095 01:00:18.727290 WR_PST = 0x0
5096 01:00:18.730554 DBI_WR = 0x0
5097 01:00:18.731023 DBI_RD = 0x0
5098 01:00:18.733718 OTF = 0x1
5099 01:00:18.736797 ===================================
5100 01:00:18.740145 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5101 01:00:18.743648 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5102 01:00:18.750307 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5103 01:00:18.753714 ===================================
5104 01:00:18.754139 LPDDR4 DRAM CONFIGURATION
5105 01:00:18.756964 ===================================
5106 01:00:18.760134 EX_ROW_EN[0] = 0x10
5107 01:00:18.763722 EX_ROW_EN[1] = 0x0
5108 01:00:18.764391 LP4Y_EN = 0x0
5109 01:00:18.766443 WORK_FSP = 0x0
5110 01:00:18.766865 WL = 0x3
5111 01:00:18.769712 RL = 0x3
5112 01:00:18.770135 BL = 0x2
5113 01:00:18.772859 RPST = 0x0
5114 01:00:18.773283 RD_PRE = 0x0
5115 01:00:18.776196 WR_PRE = 0x1
5116 01:00:18.776618 WR_PST = 0x0
5117 01:00:18.780296 DBI_WR = 0x0
5118 01:00:18.780824 DBI_RD = 0x0
5119 01:00:18.782856 OTF = 0x1
5120 01:00:18.786378 ===================================
5121 01:00:18.793026 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5122 01:00:18.796844 nWR fixed to 30
5123 01:00:18.799680 [ModeRegInit_LP4] CH0 RK0
5124 01:00:18.800208 [ModeRegInit_LP4] CH0 RK1
5125 01:00:18.802860 [ModeRegInit_LP4] CH1 RK0
5126 01:00:18.806106 [ModeRegInit_LP4] CH1 RK1
5127 01:00:18.806682 match AC timing 9
5128 01:00:18.812682 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5129 01:00:18.816292 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5130 01:00:18.819530 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5131 01:00:18.825820 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5132 01:00:18.829085 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5133 01:00:18.829541 ==
5134 01:00:18.832482 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 01:00:18.835531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 01:00:18.836038 ==
5137 01:00:18.842569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 01:00:18.849227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5139 01:00:18.852609 [CA 0] Center 37 (7~68) winsize 62
5140 01:00:18.855528 [CA 1] Center 37 (7~68) winsize 62
5141 01:00:18.858615 [CA 2] Center 34 (4~65) winsize 62
5142 01:00:18.862033 [CA 3] Center 35 (5~65) winsize 61
5143 01:00:18.865185 [CA 4] Center 34 (4~64) winsize 61
5144 01:00:18.868826 [CA 5] Center 33 (4~63) winsize 60
5145 01:00:18.869352
5146 01:00:18.872252 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5147 01:00:18.872968
5148 01:00:18.875347 [CATrainingPosCal] consider 1 rank data
5149 01:00:18.878404 u2DelayCellTimex100 = 270/100 ps
5150 01:00:18.881902 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5151 01:00:18.885205 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5152 01:00:18.888499 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5153 01:00:18.895128 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5154 01:00:18.898538 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5155 01:00:18.902017 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5156 01:00:18.902634
5157 01:00:18.905533 CA PerBit enable=1, Macro0, CA PI delay=33
5158 01:00:18.906099
5159 01:00:18.908566 [CBTSetCACLKResult] CA Dly = 33
5160 01:00:18.909136 CS Dly: 7 (0~38)
5161 01:00:18.909512 ==
5162 01:00:18.911654 Dram Type= 6, Freq= 0, CH_0, rank 1
5163 01:00:18.918334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 01:00:18.918915 ==
5165 01:00:18.921739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5166 01:00:18.927932 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5167 01:00:18.931501 [CA 0] Center 37 (7~68) winsize 62
5168 01:00:18.934647 [CA 1] Center 37 (7~68) winsize 62
5169 01:00:18.937775 [CA 2] Center 34 (4~65) winsize 62
5170 01:00:18.941296 [CA 3] Center 34 (4~65) winsize 62
5171 01:00:18.944293 [CA 4] Center 33 (3~64) winsize 62
5172 01:00:18.948012 [CA 5] Center 33 (3~63) winsize 61
5173 01:00:18.948496
5174 01:00:18.951150 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5175 01:00:18.951571
5176 01:00:18.954150 [CATrainingPosCal] consider 2 rank data
5177 01:00:18.957606 u2DelayCellTimex100 = 270/100 ps
5178 01:00:18.961048 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5179 01:00:18.967482 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5180 01:00:18.971049 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5181 01:00:18.974054 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5182 01:00:18.977321 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5183 01:00:18.980611 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5184 01:00:18.981081
5185 01:00:18.984253 CA PerBit enable=1, Macro0, CA PI delay=33
5186 01:00:18.984678
5187 01:00:18.987503 [CBTSetCACLKResult] CA Dly = 33
5188 01:00:18.990516 CS Dly: 7 (0~39)
5189 01:00:18.990937
5190 01:00:18.993780 ----->DramcWriteLeveling(PI) begin...
5191 01:00:18.994265 ==
5192 01:00:18.997397 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 01:00:19.000521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 01:00:19.000948 ==
5195 01:00:19.004136 Write leveling (Byte 0): 31 => 31
5196 01:00:19.007252 Write leveling (Byte 1): 31 => 31
5197 01:00:19.010538 DramcWriteLeveling(PI) end<-----
5198 01:00:19.010961
5199 01:00:19.011293 ==
5200 01:00:19.013686 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 01:00:19.017222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 01:00:19.017776 ==
5203 01:00:19.020427 [Gating] SW mode calibration
5204 01:00:19.027168 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5205 01:00:19.033265 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5206 01:00:19.036801 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5207 01:00:19.039888 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5208 01:00:19.046666 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 01:00:19.050026 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 01:00:19.053417 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 01:00:19.059718 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5212 01:00:19.063510 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5213 01:00:19.066321 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
5214 01:00:19.072858 0 15 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
5215 01:00:19.076245 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5216 01:00:19.079787 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 01:00:19.085927 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 01:00:19.089512 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 01:00:19.092568 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5220 01:00:19.099405 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5221 01:00:19.102629 0 15 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5222 01:00:19.106028 1 0 0 | B1->B0 | 3232 4545 | 0 0 | (0 0) (0 0)
5223 01:00:19.112480 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5224 01:00:19.116054 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 01:00:19.122515 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 01:00:19.125924 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 01:00:19.129092 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 01:00:19.135637 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5229 01:00:19.138715 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5230 01:00:19.141955 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5231 01:00:19.148506 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 01:00:19.151877 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 01:00:19.155450 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 01:00:19.161662 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 01:00:19.165382 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 01:00:19.168669 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 01:00:19.174857 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 01:00:19.178302 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 01:00:19.181386 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 01:00:19.188314 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 01:00:19.191200 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 01:00:19.194936 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 01:00:19.201227 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 01:00:19.204657 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 01:00:19.208176 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5246 01:00:19.214580 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5247 01:00:19.215012 Total UI for P1: 0, mck2ui 16
5248 01:00:19.221161 best dqsien dly found for B0: ( 1, 2, 28)
5249 01:00:19.224530 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5250 01:00:19.227957 Total UI for P1: 0, mck2ui 16
5251 01:00:19.231107 best dqsien dly found for B1: ( 1, 3, 2)
5252 01:00:19.234090 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5253 01:00:19.237856 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5254 01:00:19.238323
5255 01:00:19.241193 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5256 01:00:19.244364 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5257 01:00:19.247482 [Gating] SW calibration Done
5258 01:00:19.247957 ==
5259 01:00:19.250950 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 01:00:19.254044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 01:00:19.254502 ==
5262 01:00:19.257301 RX Vref Scan: 0
5263 01:00:19.257720
5264 01:00:19.260415 RX Vref 0 -> 0, step: 1
5265 01:00:19.260839
5266 01:00:19.261178 RX Delay -80 -> 252, step: 8
5267 01:00:19.267173 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5268 01:00:19.271003 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5269 01:00:19.274034 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5270 01:00:19.277259 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5271 01:00:19.280237 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5272 01:00:19.286933 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5273 01:00:19.290246 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5274 01:00:19.293658 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5275 01:00:19.297250 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5276 01:00:19.300175 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5277 01:00:19.306807 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5278 01:00:19.309883 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5279 01:00:19.313277 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5280 01:00:19.316429 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5281 01:00:19.320213 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5282 01:00:19.326987 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5283 01:00:19.327593 ==
5284 01:00:19.329823 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 01:00:19.332904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 01:00:19.333330 ==
5287 01:00:19.333781 DQS Delay:
5288 01:00:19.336495 DQS0 = 0, DQS1 = 0
5289 01:00:19.336935 DQM Delay:
5290 01:00:19.339860 DQM0 = 96, DQM1 = 86
5291 01:00:19.340410 DQ Delay:
5292 01:00:19.342851 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5293 01:00:19.346564 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5294 01:00:19.349992 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5295 01:00:19.352907 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5296 01:00:19.353428
5297 01:00:19.353765
5298 01:00:19.354132 ==
5299 01:00:19.356523 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 01:00:19.360209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 01:00:19.360739 ==
5302 01:00:19.362755
5303 01:00:19.363173
5304 01:00:19.363503 TX Vref Scan disable
5305 01:00:19.366667 == TX Byte 0 ==
5306 01:00:19.369805 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5307 01:00:19.372916 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5308 01:00:19.376091 == TX Byte 1 ==
5309 01:00:19.379861 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5310 01:00:19.383072 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5311 01:00:19.383500 ==
5312 01:00:19.386214 Dram Type= 6, Freq= 0, CH_0, rank 0
5313 01:00:19.392868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 01:00:19.393292 ==
5315 01:00:19.393626
5316 01:00:19.393940
5317 01:00:19.394328 TX Vref Scan disable
5318 01:00:19.397064 == TX Byte 0 ==
5319 01:00:19.400564 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5320 01:00:19.406731 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5321 01:00:19.407159 == TX Byte 1 ==
5322 01:00:19.410012 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5323 01:00:19.417152 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5324 01:00:19.417698
5325 01:00:19.418039 [DATLAT]
5326 01:00:19.418390 Freq=933, CH0 RK0
5327 01:00:19.418700
5328 01:00:19.419918 DATLAT Default: 0xd
5329 01:00:19.423320 0, 0xFFFF, sum = 0
5330 01:00:19.423759 1, 0xFFFF, sum = 0
5331 01:00:19.426431 2, 0xFFFF, sum = 0
5332 01:00:19.426857 3, 0xFFFF, sum = 0
5333 01:00:19.429731 4, 0xFFFF, sum = 0
5334 01:00:19.430154 5, 0xFFFF, sum = 0
5335 01:00:19.433183 6, 0xFFFF, sum = 0
5336 01:00:19.433628 7, 0xFFFF, sum = 0
5337 01:00:19.436390 8, 0xFFFF, sum = 0
5338 01:00:19.436811 9, 0xFFFF, sum = 0
5339 01:00:19.439873 10, 0x0, sum = 1
5340 01:00:19.440296 11, 0x0, sum = 2
5341 01:00:19.443125 12, 0x0, sum = 3
5342 01:00:19.443760 13, 0x0, sum = 4
5343 01:00:19.446059 best_step = 11
5344 01:00:19.446507
5345 01:00:19.446840 ==
5346 01:00:19.449635 Dram Type= 6, Freq= 0, CH_0, rank 0
5347 01:00:19.452461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 01:00:19.452762 ==
5349 01:00:19.452998 RX Vref Scan: 1
5350 01:00:19.456126
5351 01:00:19.456523 RX Vref 0 -> 0, step: 1
5352 01:00:19.456799
5353 01:00:19.459857 RX Delay -61 -> 252, step: 4
5354 01:00:19.460280
5355 01:00:19.462930 Set Vref, RX VrefLevel [Byte0]: 57
5356 01:00:19.466264 [Byte1]: 58
5357 01:00:19.469881
5358 01:00:19.470320 Final RX Vref Byte 0 = 57 to rank0
5359 01:00:19.472900 Final RX Vref Byte 1 = 58 to rank0
5360 01:00:19.476203 Final RX Vref Byte 0 = 57 to rank1
5361 01:00:19.480018 Final RX Vref Byte 1 = 58 to rank1==
5362 01:00:19.482928 Dram Type= 6, Freq= 0, CH_0, rank 0
5363 01:00:19.489645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 01:00:19.490044 ==
5365 01:00:19.490315 DQS Delay:
5366 01:00:19.492619 DQS0 = 0, DQS1 = 0
5367 01:00:19.492918 DQM Delay:
5368 01:00:19.493156 DQM0 = 97, DQM1 = 86
5369 01:00:19.496127 DQ Delay:
5370 01:00:19.499505 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5371 01:00:19.502481 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5372 01:00:19.506102 DQ8 =80, DQ9 =76, DQ10 =86, DQ11 =84
5373 01:00:19.509381 DQ12 =90, DQ13 =90, DQ14 =92, DQ15 =90
5374 01:00:19.509810
5375 01:00:19.510066
5376 01:00:19.515724 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5377 01:00:19.518794 CH0 RK0: MR19=505, MR18=2D14
5378 01:00:19.525940 CH0_RK0: MR19=0x505, MR18=0x2D14, DQSOSC=407, MR23=63, INC=65, DEC=43
5379 01:00:19.526489
5380 01:00:19.529122 ----->DramcWriteLeveling(PI) begin...
5381 01:00:19.529514 ==
5382 01:00:19.532606 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 01:00:19.535556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 01:00:19.535950 ==
5385 01:00:19.538669 Write leveling (Byte 0): 37 => 37
5386 01:00:19.542078 Write leveling (Byte 1): 30 => 30
5387 01:00:19.545343 DramcWriteLeveling(PI) end<-----
5388 01:00:19.545730
5389 01:00:19.546032 ==
5390 01:00:19.548778 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 01:00:19.552123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 01:00:19.555763 ==
5393 01:00:19.556147 [Gating] SW mode calibration
5394 01:00:19.561961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5395 01:00:19.568694 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5396 01:00:19.571846 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5397 01:00:19.578899 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 01:00:19.581954 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 01:00:19.585150 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 01:00:19.591908 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 01:00:19.594711 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 01:00:19.598347 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5403 01:00:19.604787 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 0)
5404 01:00:19.607935 0 15 0 | B1->B0 | 2f2f 2929 | 0 0 | (1 0) (1 0)
5405 01:00:19.611559 0 15 4 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
5406 01:00:19.618361 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 01:00:19.621204 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 01:00:19.624729 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 01:00:19.631339 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5410 01:00:19.634020 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5411 01:00:19.637254 0 15 28 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5412 01:00:19.643846 1 0 0 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
5413 01:00:19.647022 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 01:00:19.654230 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 01:00:19.657341 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 01:00:19.660794 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 01:00:19.663940 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 01:00:19.670407 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 01:00:19.673865 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5420 01:00:19.676958 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5421 01:00:19.683710 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 01:00:19.686910 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 01:00:19.690608 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 01:00:19.697031 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 01:00:19.700332 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 01:00:19.703823 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 01:00:19.710764 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 01:00:19.713164 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 01:00:19.716744 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 01:00:19.723400 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 01:00:19.727001 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 01:00:19.729385 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 01:00:19.736594 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 01:00:19.739363 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 01:00:19.746209 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 01:00:19.749654 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5437 01:00:19.752443 Total UI for P1: 0, mck2ui 16
5438 01:00:19.756281 best dqsien dly found for B0: ( 1, 2, 30)
5439 01:00:19.759583 Total UI for P1: 0, mck2ui 16
5440 01:00:19.762797 best dqsien dly found for B1: ( 1, 2, 30)
5441 01:00:19.765809 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5442 01:00:19.769226 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5443 01:00:19.769781
5444 01:00:19.772525 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5445 01:00:19.775526 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5446 01:00:19.779130 [Gating] SW calibration Done
5447 01:00:19.779596 ==
5448 01:00:19.782036 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 01:00:19.785687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 01:00:19.788960 ==
5451 01:00:19.789522 RX Vref Scan: 0
5452 01:00:19.789891
5453 01:00:19.792262 RX Vref 0 -> 0, step: 1
5454 01:00:19.792826
5455 01:00:19.795460 RX Delay -80 -> 252, step: 8
5456 01:00:19.798275 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5457 01:00:19.802261 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5458 01:00:19.805309 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5459 01:00:19.809169 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5460 01:00:19.811851 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5461 01:00:19.818405 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5462 01:00:19.821805 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5463 01:00:19.825069 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5464 01:00:19.828290 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5465 01:00:19.831409 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5466 01:00:19.838114 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5467 01:00:19.841938 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5468 01:00:19.845105 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5469 01:00:19.848512 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5470 01:00:19.851554 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5471 01:00:19.854499 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5472 01:00:19.857901 ==
5473 01:00:19.858403 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 01:00:19.864522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 01:00:19.865080 ==
5476 01:00:19.865457 DQS Delay:
5477 01:00:19.867976 DQS0 = 0, DQS1 = 0
5478 01:00:19.868536 DQM Delay:
5479 01:00:19.870977 DQM0 = 96, DQM1 = 90
5480 01:00:19.871442 DQ Delay:
5481 01:00:19.874579 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5482 01:00:19.877861 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5483 01:00:19.881523 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5484 01:00:19.884345 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5485 01:00:19.884874
5486 01:00:19.885216
5487 01:00:19.885530 ==
5488 01:00:19.887798 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 01:00:19.890925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 01:00:19.891351 ==
5491 01:00:19.891692
5492 01:00:19.892004
5493 01:00:19.894345 TX Vref Scan disable
5494 01:00:19.898133 == TX Byte 0 ==
5495 01:00:19.900989 Update DQ dly =721 (2 ,6, 17) DQ OEN =(2 ,3)
5496 01:00:19.904387 Update DQM dly =721 (2 ,6, 17) DQM OEN =(2 ,3)
5497 01:00:19.907451 == TX Byte 1 ==
5498 01:00:19.910581 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5499 01:00:19.913819 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5500 01:00:19.914282 ==
5501 01:00:19.917951 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 01:00:19.923885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 01:00:19.924323 ==
5504 01:00:19.924661
5505 01:00:19.924973
5506 01:00:19.925272 TX Vref Scan disable
5507 01:00:19.928028 == TX Byte 0 ==
5508 01:00:19.931421 Update DQ dly =720 (2 ,6, 16) DQ OEN =(2 ,3)
5509 01:00:19.938451 Update DQM dly =720 (2 ,6, 16) DQM OEN =(2 ,3)
5510 01:00:19.938873 == TX Byte 1 ==
5511 01:00:19.941237 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5512 01:00:19.948230 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5513 01:00:19.948757
5514 01:00:19.949093 [DATLAT]
5515 01:00:19.949399 Freq=933, CH0 RK1
5516 01:00:19.949701
5517 01:00:19.951046 DATLAT Default: 0xb
5518 01:00:19.954489 0, 0xFFFF, sum = 0
5519 01:00:19.954913 1, 0xFFFF, sum = 0
5520 01:00:19.957628 2, 0xFFFF, sum = 0
5521 01:00:19.958199 3, 0xFFFF, sum = 0
5522 01:00:19.961310 4, 0xFFFF, sum = 0
5523 01:00:19.961848 5, 0xFFFF, sum = 0
5524 01:00:19.965140 6, 0xFFFF, sum = 0
5525 01:00:19.965686 7, 0xFFFF, sum = 0
5526 01:00:19.967671 8, 0xFFFF, sum = 0
5527 01:00:19.968258 9, 0xFFFF, sum = 0
5528 01:00:19.970967 10, 0x0, sum = 1
5529 01:00:19.971440 11, 0x0, sum = 2
5530 01:00:19.974414 12, 0x0, sum = 3
5531 01:00:19.974980 13, 0x0, sum = 4
5532 01:00:19.977804 best_step = 11
5533 01:00:19.978427
5534 01:00:19.978810 ==
5535 01:00:19.981295 Dram Type= 6, Freq= 0, CH_0, rank 1
5536 01:00:19.984706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 01:00:19.985277 ==
5538 01:00:19.985647 RX Vref Scan: 0
5539 01:00:19.985992
5540 01:00:19.987837 RX Vref 0 -> 0, step: 1
5541 01:00:19.988304
5542 01:00:19.991160 RX Delay -61 -> 252, step: 4
5543 01:00:19.997962 iDelay=203, Bit 0, Center 92 (3 ~ 182) 180
5544 01:00:20.000837 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5545 01:00:20.004306 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5546 01:00:20.007397 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5547 01:00:20.010691 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5548 01:00:20.014101 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5549 01:00:20.020959 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5550 01:00:20.024421 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5551 01:00:20.027222 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5552 01:00:20.030677 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5553 01:00:20.033730 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5554 01:00:20.040537 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5555 01:00:20.043845 iDelay=203, Bit 12, Center 90 (-5 ~ 186) 192
5556 01:00:20.047374 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5557 01:00:20.050403 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5558 01:00:20.053505 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5559 01:00:20.053928 ==
5560 01:00:20.056982 Dram Type= 6, Freq= 0, CH_0, rank 1
5561 01:00:20.063600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 01:00:20.064192 ==
5563 01:00:20.064574 DQS Delay:
5564 01:00:20.066895 DQS0 = 0, DQS1 = 0
5565 01:00:20.067363 DQM Delay:
5566 01:00:20.070415 DQM0 = 95, DQM1 = 87
5567 01:00:20.070838 DQ Delay:
5568 01:00:20.073364 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =92
5569 01:00:20.077000 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5570 01:00:20.080449 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =82
5571 01:00:20.083280 DQ12 =90, DQ13 =92, DQ14 =94, DQ15 =92
5572 01:00:20.083701
5573 01:00:20.084035
5574 01:00:20.090321 [DQSOSCAuto] RK1, (LSB)MR18= 0x29fa, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 408 ps
5575 01:00:20.093374 CH0 RK1: MR19=504, MR18=29FA
5576 01:00:20.099935 CH0_RK1: MR19=0x504, MR18=0x29FA, DQSOSC=408, MR23=63, INC=65, DEC=43
5577 01:00:20.103438 [RxdqsGatingPostProcess] freq 933
5578 01:00:20.110054 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5579 01:00:20.113409 best DQS0 dly(2T, 0.5T) = (0, 10)
5580 01:00:20.113885 best DQS1 dly(2T, 0.5T) = (0, 11)
5581 01:00:20.116593 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5582 01:00:20.119965 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5583 01:00:20.123076 best DQS0 dly(2T, 0.5T) = (0, 10)
5584 01:00:20.126343 best DQS1 dly(2T, 0.5T) = (0, 10)
5585 01:00:20.129333 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5586 01:00:20.132525 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5587 01:00:20.136030 Pre-setting of DQS Precalculation
5588 01:00:20.142839 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5589 01:00:20.143310 ==
5590 01:00:20.145986 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 01:00:20.149191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 01:00:20.149799 ==
5593 01:00:20.155916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5594 01:00:20.162458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5595 01:00:20.166339 [CA 0] Center 36 (6~67) winsize 62
5596 01:00:20.169203 [CA 1] Center 36 (6~67) winsize 62
5597 01:00:20.172574 [CA 2] Center 34 (4~65) winsize 62
5598 01:00:20.175932 [CA 3] Center 33 (3~64) winsize 62
5599 01:00:20.178896 [CA 4] Center 34 (4~64) winsize 61
5600 01:00:20.179363 [CA 5] Center 33 (3~64) winsize 62
5601 01:00:20.182539
5602 01:00:20.185776 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5603 01:00:20.186385
5604 01:00:20.188886 [CATrainingPosCal] consider 1 rank data
5605 01:00:20.191927 u2DelayCellTimex100 = 270/100 ps
5606 01:00:20.195673 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5607 01:00:20.199025 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5608 01:00:20.202112 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5609 01:00:20.205523 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5610 01:00:20.208690 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5611 01:00:20.211989 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5612 01:00:20.212575
5613 01:00:20.219023 CA PerBit enable=1, Macro0, CA PI delay=33
5614 01:00:20.219591
5615 01:00:20.219966 [CBTSetCACLKResult] CA Dly = 33
5616 01:00:20.221823 CS Dly: 6 (0~37)
5617 01:00:20.222443 ==
5618 01:00:20.225122 Dram Type= 6, Freq= 0, CH_1, rank 1
5619 01:00:20.228288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 01:00:20.228868 ==
5621 01:00:20.234716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5622 01:00:20.241312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5623 01:00:20.244561 [CA 0] Center 36 (6~67) winsize 62
5624 01:00:20.247949 [CA 1] Center 36 (6~67) winsize 62
5625 01:00:20.251375 [CA 2] Center 34 (4~65) winsize 62
5626 01:00:20.254775 [CA 3] Center 33 (3~64) winsize 62
5627 01:00:20.258038 [CA 4] Center 34 (3~65) winsize 63
5628 01:00:20.261169 [CA 5] Center 33 (3~64) winsize 62
5629 01:00:20.261715
5630 01:00:20.264851 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5631 01:00:20.265392
5632 01:00:20.268051 [CATrainingPosCal] consider 2 rank data
5633 01:00:20.271314 u2DelayCellTimex100 = 270/100 ps
5634 01:00:20.274606 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5635 01:00:20.278078 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5636 01:00:20.281657 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5637 01:00:20.284021 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5638 01:00:20.287756 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5639 01:00:20.294457 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5640 01:00:20.295001
5641 01:00:20.297158 CA PerBit enable=1, Macro0, CA PI delay=33
5642 01:00:20.297728
5643 01:00:20.300689 [CBTSetCACLKResult] CA Dly = 33
5644 01:00:20.301109 CS Dly: 7 (0~39)
5645 01:00:20.301444
5646 01:00:20.304026 ----->DramcWriteLeveling(PI) begin...
5647 01:00:20.304453 ==
5648 01:00:20.307126 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 01:00:20.313687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 01:00:20.314114 ==
5651 01:00:20.317115 Write leveling (Byte 0): 28 => 28
5652 01:00:20.320305 Write leveling (Byte 1): 29 => 29
5653 01:00:20.320816 DramcWriteLeveling(PI) end<-----
5654 01:00:20.323758
5655 01:00:20.324212 ==
5656 01:00:20.326970 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 01:00:20.330098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 01:00:20.330568 ==
5659 01:00:20.333406 [Gating] SW mode calibration
5660 01:00:20.340019 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5661 01:00:20.343430 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5662 01:00:20.350018 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5663 01:00:20.353349 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 01:00:20.356526 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 01:00:20.363144 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 01:00:20.366371 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 01:00:20.370019 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5668 01:00:20.376159 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5669 01:00:20.379415 0 14 28 | B1->B0 | 2e2e 2929 | 1 0 | (1 0) (0 0)
5670 01:00:20.382841 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5671 01:00:20.389362 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 01:00:20.392931 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 01:00:20.396303 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 01:00:20.402474 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 01:00:20.406046 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5676 01:00:20.409094 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5677 01:00:20.416311 0 15 28 | B1->B0 | 3a3a 3c3c | 0 1 | (1 1) (1 1)
5678 01:00:20.419230 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
5679 01:00:20.422428 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 01:00:20.429449 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 01:00:20.432892 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 01:00:20.435456 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 01:00:20.442083 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 01:00:20.445734 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5685 01:00:20.448954 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5686 01:00:20.455726 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 01:00:20.458641 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 01:00:20.462098 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 01:00:20.468991 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 01:00:20.472071 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 01:00:20.478461 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 01:00:20.481854 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 01:00:20.484788 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 01:00:20.491310 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 01:00:20.494610 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 01:00:20.498188 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 01:00:20.505364 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 01:00:20.508076 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 01:00:20.511578 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 01:00:20.517958 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5701 01:00:20.521095 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5702 01:00:20.524984 Total UI for P1: 0, mck2ui 16
5703 01:00:20.528298 best dqsien dly found for B0: ( 1, 2, 24)
5704 01:00:20.531331 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5705 01:00:20.534234 Total UI for P1: 0, mck2ui 16
5706 01:00:20.537561 best dqsien dly found for B1: ( 1, 2, 26)
5707 01:00:20.540831 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5708 01:00:20.544151 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5709 01:00:20.544576
5710 01:00:20.547920 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5711 01:00:20.554377 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5712 01:00:20.554910 [Gating] SW calibration Done
5713 01:00:20.555256 ==
5714 01:00:20.557412 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 01:00:20.563899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 01:00:20.564540 ==
5717 01:00:20.564924 RX Vref Scan: 0
5718 01:00:20.565247
5719 01:00:20.567758 RX Vref 0 -> 0, step: 1
5720 01:00:20.568183
5721 01:00:20.570825 RX Delay -80 -> 252, step: 8
5722 01:00:20.573689 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5723 01:00:20.577261 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5724 01:00:20.580644 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5725 01:00:20.587163 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5726 01:00:20.590482 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5727 01:00:20.593700 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5728 01:00:20.597052 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5729 01:00:20.600634 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5730 01:00:20.603745 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5731 01:00:20.610761 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5732 01:00:20.613998 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5733 01:00:20.616917 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5734 01:00:20.619993 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5735 01:00:20.623420 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5736 01:00:20.630038 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5737 01:00:20.633549 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5738 01:00:20.634432 ==
5739 01:00:20.636748 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 01:00:20.639951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 01:00:20.640622 ==
5742 01:00:20.643240 DQS Delay:
5743 01:00:20.643701 DQS0 = 0, DQS1 = 0
5744 01:00:20.644260 DQM Delay:
5745 01:00:20.646372 DQM0 = 101, DQM1 = 90
5746 01:00:20.646837 DQ Delay:
5747 01:00:20.649846 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =103
5748 01:00:20.653593 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5749 01:00:20.656681 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5750 01:00:20.660145 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5751 01:00:20.660710
5752 01:00:20.661080
5753 01:00:20.663155 ==
5754 01:00:20.663620 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 01:00:20.669773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 01:00:20.670288 ==
5757 01:00:20.670671
5758 01:00:20.671016
5759 01:00:20.672620 TX Vref Scan disable
5760 01:00:20.673085 == TX Byte 0 ==
5761 01:00:20.676267 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5762 01:00:20.683079 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5763 01:00:20.683701 == TX Byte 1 ==
5764 01:00:20.686240 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5765 01:00:20.693322 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5766 01:00:20.693889 ==
5767 01:00:20.696003 Dram Type= 6, Freq= 0, CH_1, rank 0
5768 01:00:20.698892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 01:00:20.699360 ==
5770 01:00:20.699732
5771 01:00:20.700073
5772 01:00:20.702631 TX Vref Scan disable
5773 01:00:20.706110 == TX Byte 0 ==
5774 01:00:20.709237 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5775 01:00:20.712305 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5776 01:00:20.715792 == TX Byte 1 ==
5777 01:00:20.719541 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5778 01:00:20.722238 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5779 01:00:20.722774
5780 01:00:20.725432 [DATLAT]
5781 01:00:20.725949 Freq=933, CH1 RK0
5782 01:00:20.726332
5783 01:00:20.729169 DATLAT Default: 0xd
5784 01:00:20.729692 0, 0xFFFF, sum = 0
5785 01:00:20.732105 1, 0xFFFF, sum = 0
5786 01:00:20.732534 2, 0xFFFF, sum = 0
5787 01:00:20.735546 3, 0xFFFF, sum = 0
5788 01:00:20.735975 4, 0xFFFF, sum = 0
5789 01:00:20.738624 5, 0xFFFF, sum = 0
5790 01:00:20.739093 6, 0xFFFF, sum = 0
5791 01:00:20.742237 7, 0xFFFF, sum = 0
5792 01:00:20.742666 8, 0xFFFF, sum = 0
5793 01:00:20.745220 9, 0xFFFF, sum = 0
5794 01:00:20.745799 10, 0x0, sum = 1
5795 01:00:20.749030 11, 0x0, sum = 2
5796 01:00:20.749562 12, 0x0, sum = 3
5797 01:00:20.751652 13, 0x0, sum = 4
5798 01:00:20.752080 best_step = 11
5799 01:00:20.752413
5800 01:00:20.752725 ==
5801 01:00:20.754983 Dram Type= 6, Freq= 0, CH_1, rank 0
5802 01:00:20.762092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 01:00:20.762689 ==
5804 01:00:20.763034 RX Vref Scan: 1
5805 01:00:20.763464
5806 01:00:20.765016 RX Vref 0 -> 0, step: 1
5807 01:00:20.765438
5808 01:00:20.768730 RX Delay -69 -> 252, step: 4
5809 01:00:20.769254
5810 01:00:20.771631 Set Vref, RX VrefLevel [Byte0]: 51
5811 01:00:20.775105 [Byte1]: 61
5812 01:00:20.775633
5813 01:00:20.778097 Final RX Vref Byte 0 = 51 to rank0
5814 01:00:20.781309 Final RX Vref Byte 1 = 61 to rank0
5815 01:00:20.784693 Final RX Vref Byte 0 = 51 to rank1
5816 01:00:20.788079 Final RX Vref Byte 1 = 61 to rank1==
5817 01:00:20.791407 Dram Type= 6, Freq= 0, CH_1, rank 0
5818 01:00:20.794512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 01:00:20.794937 ==
5820 01:00:20.798085 DQS Delay:
5821 01:00:20.798649 DQS0 = 0, DQS1 = 0
5822 01:00:20.801349 DQM Delay:
5823 01:00:20.801888 DQM0 = 101, DQM1 = 95
5824 01:00:20.802407 DQ Delay:
5825 01:00:20.804889 DQ0 =104, DQ1 =98, DQ2 =92, DQ3 =98
5826 01:00:20.807740 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =98
5827 01:00:20.811410 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5828 01:00:20.817876 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5829 01:00:20.818372
5830 01:00:20.818721
5831 01:00:20.824795 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5832 01:00:20.827927 CH1 RK0: MR19=505, MR18=1F0F
5833 01:00:20.834614 CH1_RK0: MR19=0x505, MR18=0x1F0F, DQSOSC=412, MR23=63, INC=63, DEC=42
5834 01:00:20.835335
5835 01:00:20.837670 ----->DramcWriteLeveling(PI) begin...
5836 01:00:20.838114 ==
5837 01:00:20.840946 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 01:00:20.844033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 01:00:20.844562 ==
5840 01:00:20.847590 Write leveling (Byte 0): 26 => 26
5841 01:00:20.850683 Write leveling (Byte 1): 28 => 28
5842 01:00:20.854257 DramcWriteLeveling(PI) end<-----
5843 01:00:20.854794
5844 01:00:20.855167 ==
5845 01:00:20.857230 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 01:00:20.861093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 01:00:20.861654 ==
5848 01:00:20.863810 [Gating] SW mode calibration
5849 01:00:20.870365 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5850 01:00:20.877761 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5851 01:00:20.880681 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5852 01:00:20.887507 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5853 01:00:20.890599 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 01:00:20.893881 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 01:00:20.900688 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 01:00:20.903797 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5857 01:00:20.907145 0 14 24 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
5858 01:00:20.913201 0 14 28 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (1 0)
5859 01:00:20.917065 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5860 01:00:20.920449 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5861 01:00:20.926483 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 01:00:20.930053 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 01:00:20.933454 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 01:00:20.940001 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5865 01:00:20.943355 0 15 24 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
5866 01:00:20.946280 0 15 28 | B1->B0 | 3a3a 3434 | 1 0 | (0 0) (1 1)
5867 01:00:20.953320 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5868 01:00:20.956642 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 01:00:20.959685 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 01:00:20.966369 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 01:00:20.970533 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 01:00:20.972623 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 01:00:20.979613 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 01:00:20.982722 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 01:00:20.985734 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5876 01:00:20.992588 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 01:00:20.995667 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 01:00:20.999708 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 01:00:21.006333 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 01:00:21.009436 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 01:00:21.012501 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 01:00:21.019037 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 01:00:21.022324 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 01:00:21.025632 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 01:00:21.032659 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 01:00:21.035228 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 01:00:21.038752 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 01:00:21.045472 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5889 01:00:21.048872 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5890 01:00:21.051916 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5891 01:00:21.058892 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5892 01:00:21.059462 Total UI for P1: 0, mck2ui 16
5893 01:00:21.065296 best dqsien dly found for B0: ( 1, 2, 28)
5894 01:00:21.065855 Total UI for P1: 0, mck2ui 16
5895 01:00:21.071511 best dqsien dly found for B1: ( 1, 2, 24)
5896 01:00:21.074784 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5897 01:00:21.078327 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5898 01:00:21.078883
5899 01:00:21.081374 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5900 01:00:21.084577 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5901 01:00:21.087922 [Gating] SW calibration Done
5902 01:00:21.088387 ==
5903 01:00:21.091162 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 01:00:21.094270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 01:00:21.094737 ==
5906 01:00:21.098030 RX Vref Scan: 0
5907 01:00:21.098480
5908 01:00:21.098818 RX Vref 0 -> 0, step: 1
5909 01:00:21.101484
5910 01:00:21.101997 RX Delay -80 -> 252, step: 8
5911 01:00:21.107799 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5912 01:00:21.110921 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5913 01:00:21.114442 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5914 01:00:21.117557 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5915 01:00:21.120792 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5916 01:00:21.124492 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5917 01:00:21.131122 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5918 01:00:21.134444 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5919 01:00:21.137529 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5920 01:00:21.141130 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5921 01:00:21.144768 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5922 01:00:21.150529 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5923 01:00:21.154114 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5924 01:00:21.157242 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5925 01:00:21.160554 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5926 01:00:21.163617 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5927 01:00:21.164075 ==
5928 01:00:21.167234 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 01:00:21.174353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 01:00:21.174909 ==
5931 01:00:21.175274 DQS Delay:
5932 01:00:21.176663 DQS0 = 0, DQS1 = 0
5933 01:00:21.177116 DQM Delay:
5934 01:00:21.179908 DQM0 = 100, DQM1 = 91
5935 01:00:21.180365 DQ Delay:
5936 01:00:21.183859 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5937 01:00:21.186495 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5938 01:00:21.189923 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5939 01:00:21.193091 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5940 01:00:21.193548
5941 01:00:21.193913
5942 01:00:21.194295 ==
5943 01:00:21.196878 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 01:00:21.199832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 01:00:21.200407 ==
5946 01:00:21.200775
5947 01:00:21.201108
5948 01:00:21.202855 TX Vref Scan disable
5949 01:00:21.206729 == TX Byte 0 ==
5950 01:00:21.210131 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5951 01:00:21.213332 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5952 01:00:21.216189 == TX Byte 1 ==
5953 01:00:21.219752 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5954 01:00:21.222992 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5955 01:00:21.223548 ==
5956 01:00:21.226545 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 01:00:21.232884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 01:00:21.233436 ==
5959 01:00:21.233806
5960 01:00:21.234143
5961 01:00:21.234519 TX Vref Scan disable
5962 01:00:21.237027 == TX Byte 0 ==
5963 01:00:21.240112 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5964 01:00:21.247004 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5965 01:00:21.247561 == TX Byte 1 ==
5966 01:00:21.250102 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5967 01:00:21.256387 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5968 01:00:21.256886
5969 01:00:21.257277 [DATLAT]
5970 01:00:21.257618 Freq=933, CH1 RK1
5971 01:00:21.257946
5972 01:00:21.260016 DATLAT Default: 0xb
5973 01:00:21.263265 0, 0xFFFF, sum = 0
5974 01:00:21.263784 1, 0xFFFF, sum = 0
5975 01:00:21.266323 2, 0xFFFF, sum = 0
5976 01:00:21.266746 3, 0xFFFF, sum = 0
5977 01:00:21.270262 4, 0xFFFF, sum = 0
5978 01:00:21.270781 5, 0xFFFF, sum = 0
5979 01:00:21.273445 6, 0xFFFF, sum = 0
5980 01:00:21.273964 7, 0xFFFF, sum = 0
5981 01:00:21.276731 8, 0xFFFF, sum = 0
5982 01:00:21.277249 9, 0xFFFF, sum = 0
5983 01:00:21.280087 10, 0x0, sum = 1
5984 01:00:21.280606 11, 0x0, sum = 2
5985 01:00:21.282954 12, 0x0, sum = 3
5986 01:00:21.283374 13, 0x0, sum = 4
5987 01:00:21.286712 best_step = 11
5988 01:00:21.287138
5989 01:00:21.287495 ==
5990 01:00:21.289706 Dram Type= 6, Freq= 0, CH_1, rank 1
5991 01:00:21.293047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5992 01:00:21.293464 ==
5993 01:00:21.293790 RX Vref Scan: 0
5994 01:00:21.294224
5995 01:00:21.296136 RX Vref 0 -> 0, step: 1
5996 01:00:21.296549
5997 01:00:21.299960 RX Delay -61 -> 252, step: 4
5998 01:00:21.306579 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5999 01:00:21.309791 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6000 01:00:21.312932 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
6001 01:00:21.316137 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6002 01:00:21.319784 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6003 01:00:21.323399 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6004 01:00:21.329640 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6005 01:00:21.332290 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6006 01:00:21.336366 iDelay=207, Bit 8, Center 82 (-5 ~ 170) 176
6007 01:00:21.338791 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6008 01:00:21.342515 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6009 01:00:21.349084 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6010 01:00:21.352169 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6011 01:00:21.355593 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
6012 01:00:21.358844 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6013 01:00:21.362016 iDelay=207, Bit 15, Center 100 (7 ~ 194) 188
6014 01:00:21.365339 ==
6015 01:00:21.368986 Dram Type= 6, Freq= 0, CH_1, rank 1
6016 01:00:21.372157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6017 01:00:21.372620 ==
6018 01:00:21.372982 DQS Delay:
6019 01:00:21.375459 DQS0 = 0, DQS1 = 0
6020 01:00:21.376017 DQM Delay:
6021 01:00:21.378844 DQM0 = 100, DQM1 = 93
6022 01:00:21.379300 DQ Delay:
6023 01:00:21.382079 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =98
6024 01:00:21.385293 DQ4 =98, DQ5 =110, DQ6 =116, DQ7 =98
6025 01:00:21.388700 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
6026 01:00:21.392342 DQ12 =102, DQ13 =102, DQ14 =98, DQ15 =100
6027 01:00:21.392855
6028 01:00:21.393221
6029 01:00:21.401710 [DQSOSCAuto] RK1, (LSB)MR18= 0x904, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 419 ps
6030 01:00:21.402134 CH1 RK1: MR19=505, MR18=904
6031 01:00:21.408488 CH1_RK1: MR19=0x505, MR18=0x904, DQSOSC=419, MR23=63, INC=61, DEC=41
6032 01:00:21.411920 [RxdqsGatingPostProcess] freq 933
6033 01:00:21.417817 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6034 01:00:21.421703 best DQS0 dly(2T, 0.5T) = (0, 10)
6035 01:00:21.425015 best DQS1 dly(2T, 0.5T) = (0, 10)
6036 01:00:21.428063 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6037 01:00:21.431406 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6038 01:00:21.431865 best DQS0 dly(2T, 0.5T) = (0, 10)
6039 01:00:21.434916 best DQS1 dly(2T, 0.5T) = (0, 10)
6040 01:00:21.438057 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6041 01:00:21.441031 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6042 01:00:21.444312 Pre-setting of DQS Precalculation
6043 01:00:21.451327 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6044 01:00:21.457655 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6045 01:00:21.464439 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6046 01:00:21.464865
6047 01:00:21.465205
6048 01:00:21.467671 [Calibration Summary] 1866 Mbps
6049 01:00:21.468120 CH 0, Rank 0
6050 01:00:21.470948 SW Impedance : PASS
6051 01:00:21.474407 DUTY Scan : NO K
6052 01:00:21.474950 ZQ Calibration : PASS
6053 01:00:21.477626 Jitter Meter : NO K
6054 01:00:21.480607 CBT Training : PASS
6055 01:00:21.481030 Write leveling : PASS
6056 01:00:21.484057 RX DQS gating : PASS
6057 01:00:21.487341 RX DQ/DQS(RDDQC) : PASS
6058 01:00:21.487779 TX DQ/DQS : PASS
6059 01:00:21.491061 RX DATLAT : PASS
6060 01:00:21.494265 RX DQ/DQS(Engine): PASS
6061 01:00:21.494688 TX OE : NO K
6062 01:00:21.497471 All Pass.
6063 01:00:21.497880
6064 01:00:21.498242 CH 0, Rank 1
6065 01:00:21.500828 SW Impedance : PASS
6066 01:00:21.501240 DUTY Scan : NO K
6067 01:00:21.503958 ZQ Calibration : PASS
6068 01:00:21.507544 Jitter Meter : NO K
6069 01:00:21.507983 CBT Training : PASS
6070 01:00:21.510985 Write leveling : PASS
6071 01:00:21.513800 RX DQS gating : PASS
6072 01:00:21.514345 RX DQ/DQS(RDDQC) : PASS
6073 01:00:21.517343 TX DQ/DQS : PASS
6074 01:00:21.520419 RX DATLAT : PASS
6075 01:00:21.520940 RX DQ/DQS(Engine): PASS
6076 01:00:21.523954 TX OE : NO K
6077 01:00:21.524392 All Pass.
6078 01:00:21.524737
6079 01:00:21.526827 CH 1, Rank 0
6080 01:00:21.527242 SW Impedance : PASS
6081 01:00:21.530301 DUTY Scan : NO K
6082 01:00:21.533807 ZQ Calibration : PASS
6083 01:00:21.534273 Jitter Meter : NO K
6084 01:00:21.536790 CBT Training : PASS
6085 01:00:21.537203 Write leveling : PASS
6086 01:00:21.539975 RX DQS gating : PASS
6087 01:00:21.543320 RX DQ/DQS(RDDQC) : PASS
6088 01:00:21.543733 TX DQ/DQS : PASS
6089 01:00:21.546517 RX DATLAT : PASS
6090 01:00:21.549891 RX DQ/DQS(Engine): PASS
6091 01:00:21.550347 TX OE : NO K
6092 01:00:21.553570 All Pass.
6093 01:00:21.553980
6094 01:00:21.554349 CH 1, Rank 1
6095 01:00:21.556474 SW Impedance : PASS
6096 01:00:21.556887 DUTY Scan : NO K
6097 01:00:21.559744 ZQ Calibration : PASS
6098 01:00:21.563017 Jitter Meter : NO K
6099 01:00:21.563431 CBT Training : PASS
6100 01:00:21.566853 Write leveling : PASS
6101 01:00:21.569884 RX DQS gating : PASS
6102 01:00:21.570354 RX DQ/DQS(RDDQC) : PASS
6103 01:00:21.573059 TX DQ/DQS : PASS
6104 01:00:21.576691 RX DATLAT : PASS
6105 01:00:21.577219 RX DQ/DQS(Engine): PASS
6106 01:00:21.579401 TX OE : NO K
6107 01:00:21.579958 All Pass.
6108 01:00:21.580475
6109 01:00:21.582987 DramC Write-DBI off
6110 01:00:21.586219 PER_BANK_REFRESH: Hybrid Mode
6111 01:00:21.586764 TX_TRACKING: ON
6112 01:00:21.596053 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6113 01:00:21.599414 [FAST_K] Save calibration result to emmc
6114 01:00:21.602744 dramc_set_vcore_voltage set vcore to 650000
6115 01:00:21.606028 Read voltage for 400, 6
6116 01:00:21.606472 Vio18 = 0
6117 01:00:21.606803 Vcore = 650000
6118 01:00:21.610080 Vdram = 0
6119 01:00:21.610649 Vddq = 0
6120 01:00:21.610988 Vmddr = 0
6121 01:00:21.615663 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6122 01:00:21.618940 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6123 01:00:21.622382 MEM_TYPE=3, freq_sel=20
6124 01:00:21.625873 sv_algorithm_assistance_LP4_800
6125 01:00:21.629093 ============ PULL DRAM RESETB DOWN ============
6126 01:00:21.632584 ========== PULL DRAM RESETB DOWN end =========
6127 01:00:21.639326 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6128 01:00:21.642377 ===================================
6129 01:00:21.645753 LPDDR4 DRAM CONFIGURATION
6130 01:00:21.648954 ===================================
6131 01:00:21.649488 EX_ROW_EN[0] = 0x0
6132 01:00:21.652041 EX_ROW_EN[1] = 0x0
6133 01:00:21.652452 LP4Y_EN = 0x0
6134 01:00:21.655367 WORK_FSP = 0x0
6135 01:00:21.655779 WL = 0x2
6136 01:00:21.658809 RL = 0x2
6137 01:00:21.659303 BL = 0x2
6138 01:00:21.661852 RPST = 0x0
6139 01:00:21.665262 RD_PRE = 0x0
6140 01:00:21.665676 WR_PRE = 0x1
6141 01:00:21.668862 WR_PST = 0x0
6142 01:00:21.669274 DBI_WR = 0x0
6143 01:00:21.671661 DBI_RD = 0x0
6144 01:00:21.672069 OTF = 0x1
6145 01:00:21.674879 ===================================
6146 01:00:21.678827 ===================================
6147 01:00:21.682001 ANA top config
6148 01:00:21.685089 ===================================
6149 01:00:21.685501 DLL_ASYNC_EN = 0
6150 01:00:21.688375 ALL_SLAVE_EN = 1
6151 01:00:21.691805 NEW_RANK_MODE = 1
6152 01:00:21.695202 DLL_IDLE_MODE = 1
6153 01:00:21.695649 LP45_APHY_COMB_EN = 1
6154 01:00:21.698227 TX_ODT_DIS = 1
6155 01:00:21.701623 NEW_8X_MODE = 1
6156 01:00:21.704949 ===================================
6157 01:00:21.708052 ===================================
6158 01:00:21.711121 data_rate = 800
6159 01:00:21.714572 CKR = 1
6160 01:00:21.718020 DQ_P2S_RATIO = 4
6161 01:00:21.721563 ===================================
6162 01:00:21.722072 CA_P2S_RATIO = 4
6163 01:00:21.724301 DQ_CA_OPEN = 0
6164 01:00:21.727650 DQ_SEMI_OPEN = 1
6165 01:00:21.730786 CA_SEMI_OPEN = 1
6166 01:00:21.734293 CA_FULL_RATE = 0
6167 01:00:21.737876 DQ_CKDIV4_EN = 0
6168 01:00:21.738438 CA_CKDIV4_EN = 1
6169 01:00:21.741016 CA_PREDIV_EN = 0
6170 01:00:21.744686 PH8_DLY = 0
6171 01:00:21.747333 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6172 01:00:21.750754 DQ_AAMCK_DIV = 0
6173 01:00:21.754052 CA_AAMCK_DIV = 0
6174 01:00:21.754687 CA_ADMCK_DIV = 4
6175 01:00:21.757403 DQ_TRACK_CA_EN = 0
6176 01:00:21.760608 CA_PICK = 800
6177 01:00:21.764100 CA_MCKIO = 400
6178 01:00:21.767261 MCKIO_SEMI = 400
6179 01:00:21.770856 PLL_FREQ = 3016
6180 01:00:21.774117 DQ_UI_PI_RATIO = 32
6181 01:00:21.777819 CA_UI_PI_RATIO = 32
6182 01:00:21.781168 ===================================
6183 01:00:21.783853 ===================================
6184 01:00:21.784310 memory_type:LPDDR4
6185 01:00:21.787682 GP_NUM : 10
6186 01:00:21.790727 SRAM_EN : 1
6187 01:00:21.791188 MD32_EN : 0
6188 01:00:21.793904 ===================================
6189 01:00:21.797072 [ANA_INIT] >>>>>>>>>>>>>>
6190 01:00:21.801204 <<<<<< [CONFIGURE PHASE]: ANA_TX
6191 01:00:21.804099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6192 01:00:21.807431 ===================================
6193 01:00:21.810480 data_rate = 800,PCW = 0X7400
6194 01:00:21.814270 ===================================
6195 01:00:21.816806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6196 01:00:21.820628 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6197 01:00:21.833628 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6198 01:00:21.837153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6199 01:00:21.840287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6200 01:00:21.843457 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6201 01:00:21.846678 [ANA_INIT] flow start
6202 01:00:21.850158 [ANA_INIT] PLL >>>>>>>>
6203 01:00:21.850780 [ANA_INIT] PLL <<<<<<<<
6204 01:00:21.853904 [ANA_INIT] MIDPI >>>>>>>>
6205 01:00:21.856749 [ANA_INIT] MIDPI <<<<<<<<
6206 01:00:21.857343 [ANA_INIT] DLL >>>>>>>>
6207 01:00:21.859975 [ANA_INIT] flow end
6208 01:00:21.863434 ============ LP4 DIFF to SE enter ============
6209 01:00:21.866830 ============ LP4 DIFF to SE exit ============
6210 01:00:21.869953 [ANA_INIT] <<<<<<<<<<<<<
6211 01:00:21.873449 [Flow] Enable top DCM control >>>>>
6212 01:00:21.876605 [Flow] Enable top DCM control <<<<<
6213 01:00:21.879933 Enable DLL master slave shuffle
6214 01:00:21.886799 ==============================================================
6215 01:00:21.887363 Gating Mode config
6216 01:00:21.893214 ==============================================================
6217 01:00:21.893790 Config description:
6218 01:00:21.903144 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6219 01:00:21.909910 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6220 01:00:21.916256 SELPH_MODE 0: By rank 1: By Phase
6221 01:00:21.922497 ==============================================================
6222 01:00:21.922958 GAT_TRACK_EN = 0
6223 01:00:21.925666 RX_GATING_MODE = 2
6224 01:00:21.929114 RX_GATING_TRACK_MODE = 2
6225 01:00:21.932575 SELPH_MODE = 1
6226 01:00:21.935902 PICG_EARLY_EN = 1
6227 01:00:21.939112 VALID_LAT_VALUE = 1
6228 01:00:21.945770 ==============================================================
6229 01:00:21.948954 Enter into Gating configuration >>>>
6230 01:00:21.952566 Exit from Gating configuration <<<<
6231 01:00:21.956027 Enter into DVFS_PRE_config >>>>>
6232 01:00:21.965532 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6233 01:00:21.968650 Exit from DVFS_PRE_config <<<<<
6234 01:00:21.972341 Enter into PICG configuration >>>>
6235 01:00:21.975426 Exit from PICG configuration <<<<
6236 01:00:21.978755 [RX_INPUT] configuration >>>>>
6237 01:00:21.982156 [RX_INPUT] configuration <<<<<
6238 01:00:21.985088 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6239 01:00:21.991743 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6240 01:00:21.998403 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6241 01:00:22.005156 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6242 01:00:22.008267 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6243 01:00:22.014891 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6244 01:00:22.018284 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6245 01:00:22.024928 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6246 01:00:22.028417 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6247 01:00:22.031806 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6248 01:00:22.034601 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6249 01:00:22.040906 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6250 01:00:22.044643 ===================================
6251 01:00:22.047822 LPDDR4 DRAM CONFIGURATION
6252 01:00:22.050944 ===================================
6253 01:00:22.051417 EX_ROW_EN[0] = 0x0
6254 01:00:22.054137 EX_ROW_EN[1] = 0x0
6255 01:00:22.054655 LP4Y_EN = 0x0
6256 01:00:22.057501 WORK_FSP = 0x0
6257 01:00:22.057973 WL = 0x2
6258 01:00:22.060807 RL = 0x2
6259 01:00:22.061295 BL = 0x2
6260 01:00:22.064443 RPST = 0x0
6261 01:00:22.065068 RD_PRE = 0x0
6262 01:00:22.067533 WR_PRE = 0x1
6263 01:00:22.068003 WR_PST = 0x0
6264 01:00:22.070744 DBI_WR = 0x0
6265 01:00:22.073820 DBI_RD = 0x0
6266 01:00:22.074331 OTF = 0x1
6267 01:00:22.077410 ===================================
6268 01:00:22.081222 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6269 01:00:22.083874 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6270 01:00:22.090633 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6271 01:00:22.094239 ===================================
6272 01:00:22.097107 LPDDR4 DRAM CONFIGURATION
6273 01:00:22.100095 ===================================
6274 01:00:22.100567 EX_ROW_EN[0] = 0x10
6275 01:00:22.104152 EX_ROW_EN[1] = 0x0
6276 01:00:22.104734 LP4Y_EN = 0x0
6277 01:00:22.107302 WORK_FSP = 0x0
6278 01:00:22.107805 WL = 0x2
6279 01:00:22.110556 RL = 0x2
6280 01:00:22.111126 BL = 0x2
6281 01:00:22.113479 RPST = 0x0
6282 01:00:22.116591 RD_PRE = 0x0
6283 01:00:22.117059 WR_PRE = 0x1
6284 01:00:22.120259 WR_PST = 0x0
6285 01:00:22.120720 DBI_WR = 0x0
6286 01:00:22.123198 DBI_RD = 0x0
6287 01:00:22.123655 OTF = 0x1
6288 01:00:22.127076 ===================================
6289 01:00:22.133804 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6290 01:00:22.137464 nWR fixed to 30
6291 01:00:22.140401 [ModeRegInit_LP4] CH0 RK0
6292 01:00:22.140919 [ModeRegInit_LP4] CH0 RK1
6293 01:00:22.144291 [ModeRegInit_LP4] CH1 RK0
6294 01:00:22.146979 [ModeRegInit_LP4] CH1 RK1
6295 01:00:22.147436 match AC timing 19
6296 01:00:22.153806 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6297 01:00:22.157986 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6298 01:00:22.160028 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6299 01:00:22.166865 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6300 01:00:22.170051 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6301 01:00:22.170661 ==
6302 01:00:22.173468 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 01:00:22.176521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 01:00:22.177093 ==
6305 01:00:22.183275 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6306 01:00:22.189750 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6307 01:00:22.193421 [CA 0] Center 36 (8~64) winsize 57
6308 01:00:22.196095 [CA 1] Center 36 (8~64) winsize 57
6309 01:00:22.199566 [CA 2] Center 36 (8~64) winsize 57
6310 01:00:22.203216 [CA 3] Center 36 (8~64) winsize 57
6311 01:00:22.206813 [CA 4] Center 36 (8~64) winsize 57
6312 01:00:22.207380 [CA 5] Center 36 (8~64) winsize 57
6313 01:00:22.209666
6314 01:00:22.213290 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6315 01:00:22.213868
6316 01:00:22.216650 [CATrainingPosCal] consider 1 rank data
6317 01:00:22.219545 u2DelayCellTimex100 = 270/100 ps
6318 01:00:22.222872 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 01:00:22.226375 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 01:00:22.229863 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 01:00:22.233146 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 01:00:22.236378 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 01:00:22.239348 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 01:00:22.239835
6325 01:00:22.242745 CA PerBit enable=1, Macro0, CA PI delay=36
6326 01:00:22.243219
6327 01:00:22.246082 [CBTSetCACLKResult] CA Dly = 36
6328 01:00:22.249430 CS Dly: 1 (0~32)
6329 01:00:22.249901 ==
6330 01:00:22.252883 Dram Type= 6, Freq= 0, CH_0, rank 1
6331 01:00:22.256623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 01:00:22.257219 ==
6333 01:00:22.262643 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6334 01:00:22.269110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6335 01:00:22.272713 [CA 0] Center 36 (8~64) winsize 57
6336 01:00:22.275786 [CA 1] Center 36 (8~64) winsize 57
6337 01:00:22.276068 [CA 2] Center 36 (8~64) winsize 57
6338 01:00:22.279304 [CA 3] Center 36 (8~64) winsize 57
6339 01:00:22.282365 [CA 4] Center 36 (8~64) winsize 57
6340 01:00:22.285375 [CA 5] Center 36 (8~64) winsize 57
6341 01:00:22.285610
6342 01:00:22.288802 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6343 01:00:22.292203
6344 01:00:22.295311 [CATrainingPosCal] consider 2 rank data
6345 01:00:22.298461 u2DelayCellTimex100 = 270/100 ps
6346 01:00:22.302048 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 01:00:22.305370 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 01:00:22.308642 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 01:00:22.311654 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 01:00:22.315476 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 01:00:22.318385 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6352 01:00:22.318555
6353 01:00:22.321871 CA PerBit enable=1, Macro0, CA PI delay=36
6354 01:00:22.322136
6355 01:00:22.325119 [CBTSetCACLKResult] CA Dly = 36
6356 01:00:22.328411 CS Dly: 1 (0~32)
6357 01:00:22.328733
6358 01:00:22.332014 ----->DramcWriteLeveling(PI) begin...
6359 01:00:22.332500 ==
6360 01:00:22.335412 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 01:00:22.338472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 01:00:22.338989 ==
6363 01:00:22.341711 Write leveling (Byte 0): 40 => 8
6364 01:00:22.345149 Write leveling (Byte 1): 32 => 0
6365 01:00:22.348368 DramcWriteLeveling(PI) end<-----
6366 01:00:22.348745
6367 01:00:22.349044 ==
6368 01:00:22.351592 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 01:00:22.354970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 01:00:22.355348 ==
6371 01:00:22.358831 [Gating] SW mode calibration
6372 01:00:22.364700 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6373 01:00:22.372189 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6374 01:00:22.374705 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6375 01:00:22.378763 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6376 01:00:22.384754 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6377 01:00:22.387845 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6378 01:00:22.391653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6379 01:00:22.398358 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 01:00:22.401687 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 01:00:22.404955 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6382 01:00:22.411298 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6383 01:00:22.414896 Total UI for P1: 0, mck2ui 16
6384 01:00:22.417837 best dqsien dly found for B0: ( 0, 14, 24)
6385 01:00:22.421021 Total UI for P1: 0, mck2ui 16
6386 01:00:22.424736 best dqsien dly found for B1: ( 0, 14, 24)
6387 01:00:22.428024 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6388 01:00:22.431040 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6389 01:00:22.431592
6390 01:00:22.434106 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6391 01:00:22.437859 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6392 01:00:22.441224 [Gating] SW calibration Done
6393 01:00:22.441887 ==
6394 01:00:22.444016 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 01:00:22.447195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 01:00:22.447655 ==
6397 01:00:22.450572 RX Vref Scan: 0
6398 01:00:22.451050
6399 01:00:22.453984 RX Vref 0 -> 0, step: 1
6400 01:00:22.454623
6401 01:00:22.457221 RX Delay -410 -> 252, step: 16
6402 01:00:22.460493 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6403 01:00:22.463831 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6404 01:00:22.467132 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6405 01:00:22.473833 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6406 01:00:22.476975 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6407 01:00:22.480498 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6408 01:00:22.483892 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6409 01:00:22.490349 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6410 01:00:22.493753 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6411 01:00:22.496730 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6412 01:00:22.500274 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6413 01:00:22.507030 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6414 01:00:22.509647 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6415 01:00:22.512902 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6416 01:00:22.520008 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6417 01:00:22.523114 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6418 01:00:22.523670 ==
6419 01:00:22.526866 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 01:00:22.529817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 01:00:22.530419 ==
6422 01:00:22.532793 DQS Delay:
6423 01:00:22.533244 DQS0 = 43, DQS1 = 59
6424 01:00:22.536803 DQM Delay:
6425 01:00:22.537361 DQM0 = 8, DQM1 = 11
6426 01:00:22.537727 DQ Delay:
6427 01:00:22.539704 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6428 01:00:22.542664 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6429 01:00:22.545751 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6430 01:00:22.549287 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6431 01:00:22.549894
6432 01:00:22.550448
6433 01:00:22.550798 ==
6434 01:00:22.552777 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 01:00:22.559484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 01:00:22.560004 ==
6437 01:00:22.560386
6438 01:00:22.560729
6439 01:00:22.561086 TX Vref Scan disable
6440 01:00:22.562210 == TX Byte 0 ==
6441 01:00:22.565661 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6442 01:00:22.569556 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6443 01:00:22.572027 == TX Byte 1 ==
6444 01:00:22.575916 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6445 01:00:22.578885 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6446 01:00:22.579405 ==
6447 01:00:22.582250 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 01:00:22.588822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 01:00:22.589252 ==
6450 01:00:22.589582
6451 01:00:22.589935
6452 01:00:22.590260 TX Vref Scan disable
6453 01:00:22.592217 == TX Byte 0 ==
6454 01:00:22.595835 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6455 01:00:22.599064 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6456 01:00:22.602360 == TX Byte 1 ==
6457 01:00:22.605577 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6458 01:00:22.608764 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6459 01:00:22.612591
6460 01:00:22.613202 [DATLAT]
6461 01:00:22.613652 Freq=400, CH0 RK0
6462 01:00:22.614007
6463 01:00:22.615603 DATLAT Default: 0xf
6464 01:00:22.616159 0, 0xFFFF, sum = 0
6465 01:00:22.618751 1, 0xFFFF, sum = 0
6466 01:00:22.619284 2, 0xFFFF, sum = 0
6467 01:00:22.622078 3, 0xFFFF, sum = 0
6468 01:00:22.625304 4, 0xFFFF, sum = 0
6469 01:00:22.625876 5, 0xFFFF, sum = 0
6470 01:00:22.628958 6, 0xFFFF, sum = 0
6471 01:00:22.629529 7, 0xFFFF, sum = 0
6472 01:00:22.632323 8, 0xFFFF, sum = 0
6473 01:00:22.632898 9, 0xFFFF, sum = 0
6474 01:00:22.635193 10, 0xFFFF, sum = 0
6475 01:00:22.635667 11, 0xFFFF, sum = 0
6476 01:00:22.638398 12, 0xFFFF, sum = 0
6477 01:00:22.638974 13, 0x0, sum = 1
6478 01:00:22.642062 14, 0x0, sum = 2
6479 01:00:22.642579 15, 0x0, sum = 3
6480 01:00:22.644925 16, 0x0, sum = 4
6481 01:00:22.645424 best_step = 14
6482 01:00:22.645828
6483 01:00:22.646209 ==
6484 01:00:22.648316 Dram Type= 6, Freq= 0, CH_0, rank 0
6485 01:00:22.651820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 01:00:22.654981 ==
6487 01:00:22.655461 RX Vref Scan: 1
6488 01:00:22.655832
6489 01:00:22.657990 RX Vref 0 -> 0, step: 1
6490 01:00:22.658477
6491 01:00:22.661469 RX Delay -359 -> 252, step: 8
6492 01:00:22.661933
6493 01:00:22.664612 Set Vref, RX VrefLevel [Byte0]: 57
6494 01:00:22.667897 [Byte1]: 58
6495 01:00:22.668466
6496 01:00:22.671250 Final RX Vref Byte 0 = 57 to rank0
6497 01:00:22.674604 Final RX Vref Byte 1 = 58 to rank0
6498 01:00:22.677687 Final RX Vref Byte 0 = 57 to rank1
6499 01:00:22.681250 Final RX Vref Byte 1 = 58 to rank1==
6500 01:00:22.684826 Dram Type= 6, Freq= 0, CH_0, rank 0
6501 01:00:22.687856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 01:00:22.690981 ==
6503 01:00:22.691483 DQS Delay:
6504 01:00:22.691852 DQS0 = 48, DQS1 = 60
6505 01:00:22.694250 DQM Delay:
6506 01:00:22.694714 DQM0 = 12, DQM1 = 10
6507 01:00:22.697963 DQ Delay:
6508 01:00:22.698500 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6509 01:00:22.701027 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6510 01:00:22.704469 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6511 01:00:22.707361 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6512 01:00:22.707795
6513 01:00:22.708123
6514 01:00:22.717359 [DQSOSCAuto] RK0, (LSB)MR18= 0xb97d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6515 01:00:22.720926 CH0 RK0: MR19=C0C, MR18=B97D
6516 01:00:22.727185 CH0_RK0: MR19=0xC0C, MR18=0xB97D, DQSOSC=386, MR23=63, INC=396, DEC=264
6517 01:00:22.727637 ==
6518 01:00:22.730700 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 01:00:22.733776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 01:00:22.734253 ==
6521 01:00:22.737515 [Gating] SW mode calibration
6522 01:00:22.744038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6523 01:00:22.750522 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6524 01:00:22.753841 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6525 01:00:22.757201 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6526 01:00:22.763504 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6527 01:00:22.767421 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6528 01:00:22.770271 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6529 01:00:22.777046 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 01:00:22.780593 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 01:00:22.783703 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6532 01:00:22.790090 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6533 01:00:22.790700 Total UI for P1: 0, mck2ui 16
6534 01:00:22.796716 best dqsien dly found for B0: ( 0, 14, 24)
6535 01:00:22.797264 Total UI for P1: 0, mck2ui 16
6536 01:00:22.800118 best dqsien dly found for B1: ( 0, 14, 24)
6537 01:00:22.806246 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6538 01:00:22.809516 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6539 01:00:22.809903
6540 01:00:22.812757 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6541 01:00:22.816469 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6542 01:00:22.819696 [Gating] SW calibration Done
6543 01:00:22.820118 ==
6544 01:00:22.823082 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 01:00:22.826049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 01:00:22.826532 ==
6547 01:00:22.829439 RX Vref Scan: 0
6548 01:00:22.829853
6549 01:00:22.830224 RX Vref 0 -> 0, step: 1
6550 01:00:22.830563
6551 01:00:22.833014 RX Delay -410 -> 252, step: 16
6552 01:00:22.839293 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6553 01:00:22.842539 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6554 01:00:22.845966 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6555 01:00:22.849371 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6556 01:00:22.855893 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6557 01:00:22.858966 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6558 01:00:22.862667 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6559 01:00:22.865521 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6560 01:00:22.872312 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6561 01:00:22.875710 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6562 01:00:22.878918 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6563 01:00:22.882506 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6564 01:00:22.889426 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6565 01:00:22.892798 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6566 01:00:22.895798 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6567 01:00:22.902103 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6568 01:00:22.902574 ==
6569 01:00:22.905584 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 01:00:22.909142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 01:00:22.909660 ==
6572 01:00:22.909995 DQS Delay:
6573 01:00:22.911996 DQS0 = 43, DQS1 = 51
6574 01:00:22.912416 DQM Delay:
6575 01:00:22.915457 DQM0 = 10, DQM1 = 8
6576 01:00:22.915988 DQ Delay:
6577 01:00:22.918688 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6578 01:00:22.921787 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6579 01:00:22.925472 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6580 01:00:22.928850 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6581 01:00:22.929377
6582 01:00:22.929713
6583 01:00:22.930018 ==
6584 01:00:22.932042 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 01:00:22.935140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 01:00:22.935704 ==
6587 01:00:22.936058
6588 01:00:22.936372
6589 01:00:22.938454 TX Vref Scan disable
6590 01:00:22.938871 == TX Byte 0 ==
6591 01:00:22.944781 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6592 01:00:22.948667 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6593 01:00:22.949184 == TX Byte 1 ==
6594 01:00:22.955086 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6595 01:00:22.958420 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6596 01:00:22.958946 ==
6597 01:00:22.961308 Dram Type= 6, Freq= 0, CH_0, rank 1
6598 01:00:22.965169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 01:00:22.965704 ==
6600 01:00:22.966152
6601 01:00:22.966636
6602 01:00:22.968350 TX Vref Scan disable
6603 01:00:22.971264 == TX Byte 0 ==
6604 01:00:22.975061 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6605 01:00:22.978305 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6606 01:00:22.978822 == TX Byte 1 ==
6607 01:00:22.984602 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6608 01:00:22.987620 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6609 01:00:22.988040
6610 01:00:22.988369 [DATLAT]
6611 01:00:22.991060 Freq=400, CH0 RK1
6612 01:00:22.991478
6613 01:00:22.991823 DATLAT Default: 0xe
6614 01:00:22.994546 0, 0xFFFF, sum = 0
6615 01:00:22.994971 1, 0xFFFF, sum = 0
6616 01:00:22.997669 2, 0xFFFF, sum = 0
6617 01:00:22.998133 3, 0xFFFF, sum = 0
6618 01:00:23.000914 4, 0xFFFF, sum = 0
6619 01:00:23.004141 5, 0xFFFF, sum = 0
6620 01:00:23.004568 6, 0xFFFF, sum = 0
6621 01:00:23.007985 7, 0xFFFF, sum = 0
6622 01:00:23.008407 8, 0xFFFF, sum = 0
6623 01:00:23.011111 9, 0xFFFF, sum = 0
6624 01:00:23.011630 10, 0xFFFF, sum = 0
6625 01:00:23.014051 11, 0xFFFF, sum = 0
6626 01:00:23.014515 12, 0xFFFF, sum = 0
6627 01:00:23.017739 13, 0x0, sum = 1
6628 01:00:23.018305 14, 0x0, sum = 2
6629 01:00:23.020684 15, 0x0, sum = 3
6630 01:00:23.021107 16, 0x0, sum = 4
6631 01:00:23.024163 best_step = 14
6632 01:00:23.024823
6633 01:00:23.025171 ==
6634 01:00:23.027456 Dram Type= 6, Freq= 0, CH_0, rank 1
6635 01:00:23.030538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 01:00:23.030960 ==
6637 01:00:23.033940 RX Vref Scan: 0
6638 01:00:23.034402
6639 01:00:23.034739 RX Vref 0 -> 0, step: 1
6640 01:00:23.035051
6641 01:00:23.037641 RX Delay -343 -> 252, step: 8
6642 01:00:23.045025 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6643 01:00:23.047870 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6644 01:00:23.051228 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6645 01:00:23.058035 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6646 01:00:23.061007 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6647 01:00:23.064686 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6648 01:00:23.068346 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6649 01:00:23.074411 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6650 01:00:23.077792 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6651 01:00:23.080910 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6652 01:00:23.084425 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6653 01:00:23.091069 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6654 01:00:23.094317 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6655 01:00:23.097457 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6656 01:00:23.100867 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6657 01:00:23.107582 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6658 01:00:23.108139 ==
6659 01:00:23.110672 Dram Type= 6, Freq= 0, CH_0, rank 1
6660 01:00:23.114043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 01:00:23.114735 ==
6662 01:00:23.117558 DQS Delay:
6663 01:00:23.118112 DQS0 = 44, DQS1 = 60
6664 01:00:23.118559 DQM Delay:
6665 01:00:23.120352 DQM0 = 7, DQM1 = 14
6666 01:00:23.120844 DQ Delay:
6667 01:00:23.123770 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6668 01:00:23.127250 DQ4 =4, DQ5 =0, DQ6 =16, DQ7 =16
6669 01:00:23.130315 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =4
6670 01:00:23.134002 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6671 01:00:23.134618
6672 01:00:23.134991
6673 01:00:23.141001 [DQSOSCAuto] RK1, (LSB)MR18= 0xb03c, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 387 ps
6674 01:00:23.143987 CH0 RK1: MR19=C0C, MR18=B03C
6675 01:00:23.150148 CH0_RK1: MR19=0xC0C, MR18=0xB03C, DQSOSC=387, MR23=63, INC=394, DEC=262
6676 01:00:23.153236 [RxdqsGatingPostProcess] freq 400
6677 01:00:23.160163 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6678 01:00:23.163036 best DQS0 dly(2T, 0.5T) = (0, 10)
6679 01:00:23.166560 best DQS1 dly(2T, 0.5T) = (0, 10)
6680 01:00:23.169662 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6681 01:00:23.172926 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6682 01:00:23.176096 best DQS0 dly(2T, 0.5T) = (0, 10)
6683 01:00:23.179875 best DQS1 dly(2T, 0.5T) = (0, 10)
6684 01:00:23.183382 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6685 01:00:23.183955 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6686 01:00:23.186267 Pre-setting of DQS Precalculation
6687 01:00:23.192732 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6688 01:00:23.193271 ==
6689 01:00:23.196499 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 01:00:23.199407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 01:00:23.199876 ==
6692 01:00:23.206237 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6693 01:00:23.212699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6694 01:00:23.215748 [CA 0] Center 36 (8~64) winsize 57
6695 01:00:23.218820 [CA 1] Center 36 (8~64) winsize 57
6696 01:00:23.222706 [CA 2] Center 36 (8~64) winsize 57
6697 01:00:23.225980 [CA 3] Center 36 (8~64) winsize 57
6698 01:00:23.229040 [CA 4] Center 36 (8~64) winsize 57
6699 01:00:23.229602 [CA 5] Center 36 (8~64) winsize 57
6700 01:00:23.232032
6701 01:00:23.235476 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6702 01:00:23.236139
6703 01:00:23.239099 [CATrainingPosCal] consider 1 rank data
6704 01:00:23.242101 u2DelayCellTimex100 = 270/100 ps
6705 01:00:23.245230 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 01:00:23.248512 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 01:00:23.251877 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 01:00:23.255796 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 01:00:23.258496 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 01:00:23.261899 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 01:00:23.262502
6712 01:00:23.265122 CA PerBit enable=1, Macro0, CA PI delay=36
6713 01:00:23.268538
6714 01:00:23.269060 [CBTSetCACLKResult] CA Dly = 36
6715 01:00:23.271499 CS Dly: 1 (0~32)
6716 01:00:23.272000 ==
6717 01:00:23.274854 Dram Type= 6, Freq= 0, CH_1, rank 1
6718 01:00:23.278254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 01:00:23.278675 ==
6720 01:00:23.284604 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6721 01:00:23.291401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6722 01:00:23.294395 [CA 0] Center 36 (8~64) winsize 57
6723 01:00:23.297866 [CA 1] Center 36 (8~64) winsize 57
6724 01:00:23.301014 [CA 2] Center 36 (8~64) winsize 57
6725 01:00:23.304636 [CA 3] Center 36 (8~64) winsize 57
6726 01:00:23.305143 [CA 4] Center 36 (8~64) winsize 57
6727 01:00:23.307999 [CA 5] Center 36 (8~64) winsize 57
6728 01:00:23.308515
6729 01:00:23.314336 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6730 01:00:23.314760
6731 01:00:23.317908 [CATrainingPosCal] consider 2 rank data
6732 01:00:23.321102 u2DelayCellTimex100 = 270/100 ps
6733 01:00:23.324996 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 01:00:23.327537 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 01:00:23.331394 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 01:00:23.334326 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 01:00:23.338006 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 01:00:23.340846 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6739 01:00:23.341359
6740 01:00:23.344376 CA PerBit enable=1, Macro0, CA PI delay=36
6741 01:00:23.344891
6742 01:00:23.347402 [CBTSetCACLKResult] CA Dly = 36
6743 01:00:23.350553 CS Dly: 1 (0~32)
6744 01:00:23.350964
6745 01:00:23.353972 ----->DramcWriteLeveling(PI) begin...
6746 01:00:23.354614 ==
6747 01:00:23.357427 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 01:00:23.361138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 01:00:23.361711 ==
6750 01:00:23.364052 Write leveling (Byte 0): 40 => 8
6751 01:00:23.367365 Write leveling (Byte 1): 40 => 8
6752 01:00:23.370546 DramcWriteLeveling(PI) end<-----
6753 01:00:23.371017
6754 01:00:23.371493 ==
6755 01:00:23.373882 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 01:00:23.377033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 01:00:23.377508 ==
6758 01:00:23.380536 [Gating] SW mode calibration
6759 01:00:23.386829 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6760 01:00:23.393598 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6761 01:00:23.396843 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6762 01:00:23.403530 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6763 01:00:23.406630 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6764 01:00:23.409778 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6765 01:00:23.416752 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6766 01:00:23.419635 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 01:00:23.423056 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 01:00:23.429646 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6769 01:00:23.432972 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6770 01:00:23.436415 Total UI for P1: 0, mck2ui 16
6771 01:00:23.440152 best dqsien dly found for B0: ( 0, 14, 24)
6772 01:00:23.443193 Total UI for P1: 0, mck2ui 16
6773 01:00:23.446277 best dqsien dly found for B1: ( 0, 14, 24)
6774 01:00:23.449499 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6775 01:00:23.453114 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6776 01:00:23.453571
6777 01:00:23.456332 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6778 01:00:23.459943 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6779 01:00:23.462705 [Gating] SW calibration Done
6780 01:00:23.463225 ==
6781 01:00:23.465591 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 01:00:23.472462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 01:00:23.473042 ==
6784 01:00:23.473411 RX Vref Scan: 0
6785 01:00:23.473755
6786 01:00:23.475957 RX Vref 0 -> 0, step: 1
6787 01:00:23.476412
6788 01:00:23.479041 RX Delay -410 -> 252, step: 16
6789 01:00:23.482644 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6790 01:00:23.486123 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6791 01:00:23.492228 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6792 01:00:23.495480 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6793 01:00:23.498562 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6794 01:00:23.502477 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6795 01:00:23.508802 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6796 01:00:23.512014 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6797 01:00:23.515153 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6798 01:00:23.518337 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6799 01:00:23.525638 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6800 01:00:23.528561 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6801 01:00:23.532302 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6802 01:00:23.535249 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6803 01:00:23.541842 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6804 01:00:23.545528 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6805 01:00:23.546098 ==
6806 01:00:23.548602 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 01:00:23.552037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 01:00:23.552521 ==
6809 01:00:23.555225 DQS Delay:
6810 01:00:23.555754 DQS0 = 43, DQS1 = 51
6811 01:00:23.558303 DQM Delay:
6812 01:00:23.558774 DQM0 = 12, DQM1 = 14
6813 01:00:23.559145 DQ Delay:
6814 01:00:23.561529 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6815 01:00:23.565069 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6816 01:00:23.568078 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6817 01:00:23.571902 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6818 01:00:23.572471
6819 01:00:23.572837
6820 01:00:23.573174 ==
6821 01:00:23.574774 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 01:00:23.581514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 01:00:23.582076 ==
6824 01:00:23.582504
6825 01:00:23.582849
6826 01:00:23.583279 TX Vref Scan disable
6827 01:00:23.584811 == TX Byte 0 ==
6828 01:00:23.588253 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6829 01:00:23.591550 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6830 01:00:23.595011 == TX Byte 1 ==
6831 01:00:23.597928 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6832 01:00:23.601020 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6833 01:00:23.601478 ==
6834 01:00:23.604580 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 01:00:23.611522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 01:00:23.612089 ==
6837 01:00:23.612459
6838 01:00:23.612797
6839 01:00:23.614351 TX Vref Scan disable
6840 01:00:23.614827 == TX Byte 0 ==
6841 01:00:23.617583 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6842 01:00:23.624334 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6843 01:00:23.624948 == TX Byte 1 ==
6844 01:00:23.627613 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6845 01:00:23.634018 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6846 01:00:23.634614
6847 01:00:23.634983 [DATLAT]
6848 01:00:23.635323 Freq=400, CH1 RK0
6849 01:00:23.635649
6850 01:00:23.637412 DATLAT Default: 0xf
6851 01:00:23.637974 0, 0xFFFF, sum = 0
6852 01:00:23.640509 1, 0xFFFF, sum = 0
6853 01:00:23.640976 2, 0xFFFF, sum = 0
6854 01:00:23.643866 3, 0xFFFF, sum = 0
6855 01:00:23.647264 4, 0xFFFF, sum = 0
6856 01:00:23.647733 5, 0xFFFF, sum = 0
6857 01:00:23.650626 6, 0xFFFF, sum = 0
6858 01:00:23.651089 7, 0xFFFF, sum = 0
6859 01:00:23.654072 8, 0xFFFF, sum = 0
6860 01:00:23.654586 9, 0xFFFF, sum = 0
6861 01:00:23.657528 10, 0xFFFF, sum = 0
6862 01:00:23.658107 11, 0xFFFF, sum = 0
6863 01:00:23.660472 12, 0xFFFF, sum = 0
6864 01:00:23.661053 13, 0x0, sum = 1
6865 01:00:23.663803 14, 0x0, sum = 2
6866 01:00:23.664272 15, 0x0, sum = 3
6867 01:00:23.666692 16, 0x0, sum = 4
6868 01:00:23.667162 best_step = 14
6869 01:00:23.667530
6870 01:00:23.667867 ==
6871 01:00:23.670598 Dram Type= 6, Freq= 0, CH_1, rank 0
6872 01:00:23.677315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 01:00:23.678018 ==
6874 01:00:23.678532 RX Vref Scan: 1
6875 01:00:23.678913
6876 01:00:23.680155 RX Vref 0 -> 0, step: 1
6877 01:00:23.680622
6878 01:00:23.683287 RX Delay -343 -> 252, step: 8
6879 01:00:23.683777
6880 01:00:23.686752 Set Vref, RX VrefLevel [Byte0]: 51
6881 01:00:23.690215 [Byte1]: 61
6882 01:00:23.690684
6883 01:00:23.693196 Final RX Vref Byte 0 = 51 to rank0
6884 01:00:23.696713 Final RX Vref Byte 1 = 61 to rank0
6885 01:00:23.699763 Final RX Vref Byte 0 = 51 to rank1
6886 01:00:23.703682 Final RX Vref Byte 1 = 61 to rank1==
6887 01:00:23.706872 Dram Type= 6, Freq= 0, CH_1, rank 0
6888 01:00:23.710107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 01:00:23.713570 ==
6890 01:00:23.714083 DQS Delay:
6891 01:00:23.714483 DQS0 = 44, DQS1 = 56
6892 01:00:23.716668 DQM Delay:
6893 01:00:23.717180 DQM0 = 7, DQM1 = 11
6894 01:00:23.719827 DQ Delay:
6895 01:00:23.720239 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
6896 01:00:23.722555 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =0
6897 01:00:23.726406 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6898 01:00:23.729886 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6899 01:00:23.730533
6900 01:00:23.730878
6901 01:00:23.739290 [DQSOSCAuto] RK0, (LSB)MR18= 0x956b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6902 01:00:23.743148 CH1 RK0: MR19=C0C, MR18=956B
6903 01:00:23.749209 CH1_RK0: MR19=0xC0C, MR18=0x956B, DQSOSC=391, MR23=63, INC=386, DEC=257
6904 01:00:23.749822 ==
6905 01:00:23.752165 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 01:00:23.755517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 01:00:23.756033 ==
6908 01:00:23.758871 [Gating] SW mode calibration
6909 01:00:23.765449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6910 01:00:23.771857 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6911 01:00:23.775027 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6912 01:00:23.778516 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6913 01:00:23.785441 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6914 01:00:23.788293 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6915 01:00:23.791713 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6916 01:00:23.798296 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 01:00:23.801615 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 01:00:23.804954 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6919 01:00:23.812113 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6920 01:00:23.812629 Total UI for P1: 0, mck2ui 16
6921 01:00:23.818594 best dqsien dly found for B0: ( 0, 14, 24)
6922 01:00:23.819147 Total UI for P1: 0, mck2ui 16
6923 01:00:23.825228 best dqsien dly found for B1: ( 0, 14, 24)
6924 01:00:23.828244 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6925 01:00:23.831437 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6926 01:00:23.831869
6927 01:00:23.834862 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6928 01:00:23.838196 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6929 01:00:23.841303 [Gating] SW calibration Done
6930 01:00:23.841716 ==
6931 01:00:23.845085 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 01:00:23.848590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 01:00:23.849124 ==
6934 01:00:23.851071 RX Vref Scan: 0
6935 01:00:23.851486
6936 01:00:23.851813 RX Vref 0 -> 0, step: 1
6937 01:00:23.852149
6938 01:00:23.854408 RX Delay -410 -> 252, step: 16
6939 01:00:23.861106 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6940 01:00:23.864501 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6941 01:00:23.868044 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6942 01:00:23.870875 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6943 01:00:23.877647 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6944 01:00:23.880605 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6945 01:00:23.884170 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6946 01:00:23.887360 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6947 01:00:23.894018 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6948 01:00:23.897316 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6949 01:00:23.900785 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6950 01:00:23.907034 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6951 01:00:23.910852 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6952 01:00:23.913656 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6953 01:00:23.917082 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6954 01:00:23.923517 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6955 01:00:23.923936 ==
6956 01:00:23.926929 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 01:00:23.930250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 01:00:23.930707 ==
6959 01:00:23.931072 DQS Delay:
6960 01:00:23.933603 DQS0 = 51, DQS1 = 59
6961 01:00:23.934157 DQM Delay:
6962 01:00:23.936654 DQM0 = 19, DQM1 = 22
6963 01:00:23.937081 DQ Delay:
6964 01:00:23.940581 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6965 01:00:23.943436 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6966 01:00:23.947114 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6967 01:00:23.949972 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6968 01:00:23.950506
6969 01:00:23.951034
6970 01:00:23.951457 ==
6971 01:00:23.953357 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 01:00:23.956644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 01:00:23.959862 ==
6974 01:00:23.960356
6975 01:00:23.960784
6976 01:00:23.961188 TX Vref Scan disable
6977 01:00:23.962990 == TX Byte 0 ==
6978 01:00:23.966397 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6979 01:00:23.969776 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6980 01:00:23.973078 == TX Byte 1 ==
6981 01:00:23.976283 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6982 01:00:23.979927 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6983 01:00:23.980447 ==
6984 01:00:23.982993 Dram Type= 6, Freq= 0, CH_1, rank 1
6985 01:00:23.989247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6986 01:00:23.989662 ==
6987 01:00:23.989990
6988 01:00:23.990348
6989 01:00:23.990738 TX Vref Scan disable
6990 01:00:23.993020 == TX Byte 0 ==
6991 01:00:23.996742 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6992 01:00:23.999527 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6993 01:00:24.002874 == TX Byte 1 ==
6994 01:00:24.006095 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6995 01:00:24.009486 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6996 01:00:24.010020
6997 01:00:24.012573 [DATLAT]
6998 01:00:24.013084 Freq=400, CH1 RK1
6999 01:00:24.013410
7000 01:00:24.015818 DATLAT Default: 0xe
7001 01:00:24.016232 0, 0xFFFF, sum = 0
7002 01:00:24.019066 1, 0xFFFF, sum = 0
7003 01:00:24.019517 2, 0xFFFF, sum = 0
7004 01:00:24.022281 3, 0xFFFF, sum = 0
7005 01:00:24.022718 4, 0xFFFF, sum = 0
7006 01:00:24.025922 5, 0xFFFF, sum = 0
7007 01:00:24.026610 6, 0xFFFF, sum = 0
7008 01:00:24.029179 7, 0xFFFF, sum = 0
7009 01:00:24.029697 8, 0xFFFF, sum = 0
7010 01:00:24.032364 9, 0xFFFF, sum = 0
7011 01:00:24.035783 10, 0xFFFF, sum = 0
7012 01:00:24.036308 11, 0xFFFF, sum = 0
7013 01:00:24.038800 12, 0xFFFF, sum = 0
7014 01:00:24.039220 13, 0x0, sum = 1
7015 01:00:24.042245 14, 0x0, sum = 2
7016 01:00:24.042674 15, 0x0, sum = 3
7017 01:00:24.043013 16, 0x0, sum = 4
7018 01:00:24.045360 best_step = 14
7019 01:00:24.045924
7020 01:00:24.046422 ==
7021 01:00:24.049255 Dram Type= 6, Freq= 0, CH_1, rank 1
7022 01:00:24.052375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7023 01:00:24.052790 ==
7024 01:00:24.055550 RX Vref Scan: 0
7025 01:00:24.055962
7026 01:00:24.058696 RX Vref 0 -> 0, step: 1
7027 01:00:24.059164
7028 01:00:24.059494 RX Delay -359 -> 252, step: 8
7029 01:00:24.067715 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7030 01:00:24.070614 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7031 01:00:24.074437 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
7032 01:00:24.077760 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7033 01:00:24.084446 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7034 01:00:24.087276 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7035 01:00:24.090368 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7036 01:00:24.097343 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7037 01:00:24.100262 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
7038 01:00:24.103595 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7039 01:00:24.107187 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7040 01:00:24.113546 iDelay=225, Bit 11, Center -48 (-295 ~ 200) 496
7041 01:00:24.117082 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
7042 01:00:24.120177 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7043 01:00:24.123339 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7044 01:00:24.130409 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7045 01:00:24.130925 ==
7046 01:00:24.133352 Dram Type= 6, Freq= 0, CH_1, rank 1
7047 01:00:24.137131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7048 01:00:24.137549 ==
7049 01:00:24.137877 DQS Delay:
7050 01:00:24.139921 DQS0 = 48, DQS1 = 60
7051 01:00:24.140349 DQM Delay:
7052 01:00:24.143254 DQM0 = 12, DQM1 = 14
7053 01:00:24.143666 DQ Delay:
7054 01:00:24.146681 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
7055 01:00:24.150364 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =12
7056 01:00:24.153426 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
7057 01:00:24.156500 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
7058 01:00:24.156914
7059 01:00:24.157239
7060 01:00:24.166626 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7061 01:00:24.167043 CH1 RK1: MR19=C0C, MR18=6A5B
7062 01:00:24.173855 CH1_RK1: MR19=0xC0C, MR18=0x6A5B, DQSOSC=396, MR23=63, INC=376, DEC=251
7063 01:00:24.176403 [RxdqsGatingPostProcess] freq 400
7064 01:00:24.183058 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7065 01:00:24.186244 best DQS0 dly(2T, 0.5T) = (0, 10)
7066 01:00:24.189672 best DQS1 dly(2T, 0.5T) = (0, 10)
7067 01:00:24.192720 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7068 01:00:24.196420 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7069 01:00:24.199328 best DQS0 dly(2T, 0.5T) = (0, 10)
7070 01:00:24.199743 best DQS1 dly(2T, 0.5T) = (0, 10)
7071 01:00:24.202864 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7072 01:00:24.206308 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7073 01:00:24.209435 Pre-setting of DQS Precalculation
7074 01:00:24.216130 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7075 01:00:24.222406 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7076 01:00:24.229181 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7077 01:00:24.229619
7078 01:00:24.229947
7079 01:00:24.232807 [Calibration Summary] 800 Mbps
7080 01:00:24.235953 CH 0, Rank 0
7081 01:00:24.236477 SW Impedance : PASS
7082 01:00:24.239006 DUTY Scan : NO K
7083 01:00:24.242030 ZQ Calibration : PASS
7084 01:00:24.242607 Jitter Meter : NO K
7085 01:00:24.245320 CBT Training : PASS
7086 01:00:24.248892 Write leveling : PASS
7087 01:00:24.249305 RX DQS gating : PASS
7088 01:00:24.252203 RX DQ/DQS(RDDQC) : PASS
7089 01:00:24.252635 TX DQ/DQS : PASS
7090 01:00:24.255374 RX DATLAT : PASS
7091 01:00:24.258773 RX DQ/DQS(Engine): PASS
7092 01:00:24.259183 TX OE : NO K
7093 01:00:24.262227 All Pass.
7094 01:00:24.262639
7095 01:00:24.262967 CH 0, Rank 1
7096 01:00:24.265454 SW Impedance : PASS
7097 01:00:24.265866 DUTY Scan : NO K
7098 01:00:24.269419 ZQ Calibration : PASS
7099 01:00:24.272001 Jitter Meter : NO K
7100 01:00:24.272417 CBT Training : PASS
7101 01:00:24.275296 Write leveling : NO K
7102 01:00:24.278791 RX DQS gating : PASS
7103 01:00:24.279215 RX DQ/DQS(RDDQC) : PASS
7104 01:00:24.281894 TX DQ/DQS : PASS
7105 01:00:24.285307 RX DATLAT : PASS
7106 01:00:24.285815 RX DQ/DQS(Engine): PASS
7107 01:00:24.288877 TX OE : NO K
7108 01:00:24.289389 All Pass.
7109 01:00:24.289718
7110 01:00:24.291766 CH 1, Rank 0
7111 01:00:24.292178 SW Impedance : PASS
7112 01:00:24.295186 DUTY Scan : NO K
7113 01:00:24.298492 ZQ Calibration : PASS
7114 01:00:24.298906 Jitter Meter : NO K
7115 01:00:24.302008 CBT Training : PASS
7116 01:00:24.304879 Write leveling : PASS
7117 01:00:24.305292 RX DQS gating : PASS
7118 01:00:24.308381 RX DQ/DQS(RDDQC) : PASS
7119 01:00:24.311919 TX DQ/DQS : PASS
7120 01:00:24.312435 RX DATLAT : PASS
7121 01:00:24.315258 RX DQ/DQS(Engine): PASS
7122 01:00:24.315778 TX OE : NO K
7123 01:00:24.318150 All Pass.
7124 01:00:24.318601
7125 01:00:24.318928 CH 1, Rank 1
7126 01:00:24.321605 SW Impedance : PASS
7127 01:00:24.322017 DUTY Scan : NO K
7128 01:00:24.324843 ZQ Calibration : PASS
7129 01:00:24.328325 Jitter Meter : NO K
7130 01:00:24.328738 CBT Training : PASS
7131 01:00:24.331932 Write leveling : NO K
7132 01:00:24.334956 RX DQS gating : PASS
7133 01:00:24.335369 RX DQ/DQS(RDDQC) : PASS
7134 01:00:24.338078 TX DQ/DQS : PASS
7135 01:00:24.341599 RX DATLAT : PASS
7136 01:00:24.342143 RX DQ/DQS(Engine): PASS
7137 01:00:24.344974 TX OE : NO K
7138 01:00:24.345385 All Pass.
7139 01:00:24.345711
7140 01:00:24.348286 DramC Write-DBI off
7141 01:00:24.351481 PER_BANK_REFRESH: Hybrid Mode
7142 01:00:24.352010 TX_TRACKING: ON
7143 01:00:24.361299 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7144 01:00:24.364588 [FAST_K] Save calibration result to emmc
7145 01:00:24.367701 dramc_set_vcore_voltage set vcore to 725000
7146 01:00:24.370895 Read voltage for 1600, 0
7147 01:00:24.371307 Vio18 = 0
7148 01:00:24.374272 Vcore = 725000
7149 01:00:24.374683 Vdram = 0
7150 01:00:24.375007 Vddq = 0
7151 01:00:24.375310 Vmddr = 0
7152 01:00:24.381473 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7153 01:00:24.387946 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7154 01:00:24.388491 MEM_TYPE=3, freq_sel=13
7155 01:00:24.391100 sv_algorithm_assistance_LP4_3733
7156 01:00:24.393979 ============ PULL DRAM RESETB DOWN ============
7157 01:00:24.400774 ========== PULL DRAM RESETB DOWN end =========
7158 01:00:24.403996 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7159 01:00:24.407646 ===================================
7160 01:00:24.410809 LPDDR4 DRAM CONFIGURATION
7161 01:00:24.413729 ===================================
7162 01:00:24.414154 EX_ROW_EN[0] = 0x0
7163 01:00:24.417052 EX_ROW_EN[1] = 0x0
7164 01:00:24.417467 LP4Y_EN = 0x0
7165 01:00:24.420268 WORK_FSP = 0x1
7166 01:00:24.420713 WL = 0x5
7167 01:00:24.423568 RL = 0x5
7168 01:00:24.427595 BL = 0x2
7169 01:00:24.428133 RPST = 0x0
7170 01:00:24.430354 RD_PRE = 0x0
7171 01:00:24.430930 WR_PRE = 0x1
7172 01:00:24.433789 WR_PST = 0x1
7173 01:00:24.434297 DBI_WR = 0x0
7174 01:00:24.437065 DBI_RD = 0x0
7175 01:00:24.437554 OTF = 0x1
7176 01:00:24.440691 ===================================
7177 01:00:24.444040 ===================================
7178 01:00:24.446853 ANA top config
7179 01:00:24.450233 ===================================
7180 01:00:24.450720 DLL_ASYNC_EN = 0
7181 01:00:24.453378 ALL_SLAVE_EN = 0
7182 01:00:24.456700 NEW_RANK_MODE = 1
7183 01:00:24.460183 DLL_IDLE_MODE = 1
7184 01:00:24.463555 LP45_APHY_COMB_EN = 1
7185 01:00:24.464042 TX_ODT_DIS = 0
7186 01:00:24.466436 NEW_8X_MODE = 1
7187 01:00:24.470236 ===================================
7188 01:00:24.473505 ===================================
7189 01:00:24.476602 data_rate = 3200
7190 01:00:24.480090 CKR = 1
7191 01:00:24.483214 DQ_P2S_RATIO = 8
7192 01:00:24.486503 ===================================
7193 01:00:24.487073 CA_P2S_RATIO = 8
7194 01:00:24.489674 DQ_CA_OPEN = 0
7195 01:00:24.493138 DQ_SEMI_OPEN = 0
7196 01:00:24.497037 CA_SEMI_OPEN = 0
7197 01:00:24.499785 CA_FULL_RATE = 0
7198 01:00:24.503202 DQ_CKDIV4_EN = 0
7199 01:00:24.503673 CA_CKDIV4_EN = 0
7200 01:00:24.506695 CA_PREDIV_EN = 0
7201 01:00:24.509874 PH8_DLY = 12
7202 01:00:24.513070 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7203 01:00:24.516433 DQ_AAMCK_DIV = 4
7204 01:00:24.519869 CA_AAMCK_DIV = 4
7205 01:00:24.520339 CA_ADMCK_DIV = 4
7206 01:00:24.522949 DQ_TRACK_CA_EN = 0
7207 01:00:24.526040 CA_PICK = 1600
7208 01:00:24.529483 CA_MCKIO = 1600
7209 01:00:24.532957 MCKIO_SEMI = 0
7210 01:00:24.536548 PLL_FREQ = 3068
7211 01:00:24.539278 DQ_UI_PI_RATIO = 32
7212 01:00:24.542767 CA_UI_PI_RATIO = 0
7213 01:00:24.546037 ===================================
7214 01:00:24.549828 ===================================
7215 01:00:24.550455 memory_type:LPDDR4
7216 01:00:24.552588 GP_NUM : 10
7217 01:00:24.556147 SRAM_EN : 1
7218 01:00:24.556627 MD32_EN : 0
7219 01:00:24.559654 ===================================
7220 01:00:24.562606 [ANA_INIT] >>>>>>>>>>>>>>
7221 01:00:24.566201 <<<<<< [CONFIGURE PHASE]: ANA_TX
7222 01:00:24.569272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7223 01:00:24.572599 ===================================
7224 01:00:24.575761 data_rate = 3200,PCW = 0X7600
7225 01:00:24.579579 ===================================
7226 01:00:24.582454 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7227 01:00:24.585745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7228 01:00:24.592160 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7229 01:00:24.596242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7230 01:00:24.598998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7231 01:00:24.602471 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7232 01:00:24.605308 [ANA_INIT] flow start
7233 01:00:24.608863 [ANA_INIT] PLL >>>>>>>>
7234 01:00:24.609427 [ANA_INIT] PLL <<<<<<<<
7235 01:00:24.612321 [ANA_INIT] MIDPI >>>>>>>>
7236 01:00:24.615209 [ANA_INIT] MIDPI <<<<<<<<
7237 01:00:24.618825 [ANA_INIT] DLL >>>>>>>>
7238 01:00:24.619287 [ANA_INIT] DLL <<<<<<<<
7239 01:00:24.622113 [ANA_INIT] flow end
7240 01:00:24.625250 ============ LP4 DIFF to SE enter ============
7241 01:00:24.628765 ============ LP4 DIFF to SE exit ============
7242 01:00:24.632505 [ANA_INIT] <<<<<<<<<<<<<
7243 01:00:24.635404 [Flow] Enable top DCM control >>>>>
7244 01:00:24.638631 [Flow] Enable top DCM control <<<<<
7245 01:00:24.641894 Enable DLL master slave shuffle
7246 01:00:24.648331 ==============================================================
7247 01:00:24.648921 Gating Mode config
7248 01:00:24.654620 ==============================================================
7249 01:00:24.655082 Config description:
7250 01:00:24.664948 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7251 01:00:24.671828 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7252 01:00:24.678008 SELPH_MODE 0: By rank 1: By Phase
7253 01:00:24.681408 ==============================================================
7254 01:00:24.684226 GAT_TRACK_EN = 1
7255 01:00:24.688373 RX_GATING_MODE = 2
7256 01:00:24.691242 RX_GATING_TRACK_MODE = 2
7257 01:00:24.694508 SELPH_MODE = 1
7258 01:00:24.697865 PICG_EARLY_EN = 1
7259 01:00:24.700863 VALID_LAT_VALUE = 1
7260 01:00:24.707652 ==============================================================
7261 01:00:24.710791 Enter into Gating configuration >>>>
7262 01:00:24.714233 Exit from Gating configuration <<<<
7263 01:00:24.717507 Enter into DVFS_PRE_config >>>>>
7264 01:00:24.727389 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7265 01:00:24.730789 Exit from DVFS_PRE_config <<<<<
7266 01:00:24.734321 Enter into PICG configuration >>>>
7267 01:00:24.737001 Exit from PICG configuration <<<<
7268 01:00:24.740654 [RX_INPUT] configuration >>>>>
7269 01:00:24.743675 [RX_INPUT] configuration <<<<<
7270 01:00:24.747193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7271 01:00:24.753589 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7272 01:00:24.760644 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7273 01:00:24.767463 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7274 01:00:24.769984 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7275 01:00:24.776637 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7276 01:00:24.779906 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7277 01:00:24.786570 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7278 01:00:24.789662 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7279 01:00:24.793220 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7280 01:00:24.796647 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7281 01:00:24.803221 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7282 01:00:24.806865 ===================================
7283 01:00:24.809676 LPDDR4 DRAM CONFIGURATION
7284 01:00:24.813176 ===================================
7285 01:00:24.813733 EX_ROW_EN[0] = 0x0
7286 01:00:24.816566 EX_ROW_EN[1] = 0x0
7287 01:00:24.817155 LP4Y_EN = 0x0
7288 01:00:24.819566 WORK_FSP = 0x1
7289 01:00:24.820115 WL = 0x5
7290 01:00:24.822785 RL = 0x5
7291 01:00:24.823360 BL = 0x2
7292 01:00:24.825987 RPST = 0x0
7293 01:00:24.826498 RD_PRE = 0x0
7294 01:00:24.829426 WR_PRE = 0x1
7295 01:00:24.829996 WR_PST = 0x1
7296 01:00:24.832750 DBI_WR = 0x0
7297 01:00:24.835811 DBI_RD = 0x0
7298 01:00:24.836367 OTF = 0x1
7299 01:00:24.839062 ===================================
7300 01:00:24.842612 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7301 01:00:24.845659 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7302 01:00:24.852407 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7303 01:00:24.855689 ===================================
7304 01:00:24.858658 LPDDR4 DRAM CONFIGURATION
7305 01:00:24.862037 ===================================
7306 01:00:24.862639 EX_ROW_EN[0] = 0x10
7307 01:00:24.865788 EX_ROW_EN[1] = 0x0
7308 01:00:24.866288 LP4Y_EN = 0x0
7309 01:00:24.868768 WORK_FSP = 0x1
7310 01:00:24.869228 WL = 0x5
7311 01:00:24.871919 RL = 0x5
7312 01:00:24.872377 BL = 0x2
7313 01:00:24.875577 RPST = 0x0
7314 01:00:24.876110 RD_PRE = 0x0
7315 01:00:24.878650 WR_PRE = 0x1
7316 01:00:24.881838 WR_PST = 0x1
7317 01:00:24.882292 DBI_WR = 0x0
7318 01:00:24.885175 DBI_RD = 0x0
7319 01:00:24.885667 OTF = 0x1
7320 01:00:24.888638 ===================================
7321 01:00:24.895093 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7322 01:00:24.895514 ==
7323 01:00:24.898120 Dram Type= 6, Freq= 0, CH_0, rank 0
7324 01:00:24.901965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7325 01:00:24.902524 ==
7326 01:00:24.905341 [Duty_Offset_Calibration]
7327 01:00:24.908855 B0:1 B1:-1 CA:0
7328 01:00:24.909366
7329 01:00:24.911784 [DutyScan_Calibration_Flow] k_type=0
7330 01:00:24.919804
7331 01:00:24.920232 ==CLK 0==
7332 01:00:24.923202 Final CLK duty delay cell = 0
7333 01:00:24.926485 [0] MAX Duty = 5124%(X100), DQS PI = 22
7334 01:00:24.929827 [0] MIN Duty = 4907%(X100), DQS PI = 4
7335 01:00:24.933003 [0] AVG Duty = 5015%(X100)
7336 01:00:24.933433
7337 01:00:24.936280 CH0 CLK Duty spec in!! Max-Min= 217%
7338 01:00:24.939925 [DutyScan_Calibration_Flow] ====Done====
7339 01:00:24.940342
7340 01:00:24.942826 [DutyScan_Calibration_Flow] k_type=1
7341 01:00:24.959324
7342 01:00:24.959942 ==DQS 0 ==
7343 01:00:24.962274 Final DQS duty delay cell = -4
7344 01:00:24.965510 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7345 01:00:24.969116 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7346 01:00:24.972136 [-4] AVG Duty = 4906%(X100)
7347 01:00:24.972553
7348 01:00:24.972881 ==DQS 1 ==
7349 01:00:24.975561 Final DQS duty delay cell = 0
7350 01:00:24.978716 [0] MAX Duty = 5156%(X100), DQS PI = 2
7351 01:00:24.982199 [0] MIN Duty = 5000%(X100), DQS PI = 22
7352 01:00:24.985678 [0] AVG Duty = 5078%(X100)
7353 01:00:24.986088
7354 01:00:24.988860 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7355 01:00:24.989273
7356 01:00:24.992086 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7357 01:00:24.995187 [DutyScan_Calibration_Flow] ====Done====
7358 01:00:24.995624
7359 01:00:24.998648 [DutyScan_Calibration_Flow] k_type=3
7360 01:00:25.016864
7361 01:00:25.017417 ==DQM 0 ==
7362 01:00:25.020078 Final DQM duty delay cell = 0
7363 01:00:25.023341 [0] MAX Duty = 5124%(X100), DQS PI = 40
7364 01:00:25.026836 [0] MIN Duty = 4907%(X100), DQS PI = 8
7365 01:00:25.027404 [0] AVG Duty = 5015%(X100)
7366 01:00:25.030340
7367 01:00:25.030924 ==DQM 1 ==
7368 01:00:25.033394 Final DQM duty delay cell = 0
7369 01:00:25.036942 [0] MAX Duty = 5000%(X100), DQS PI = 10
7370 01:00:25.039762 [0] MIN Duty = 4782%(X100), DQS PI = 20
7371 01:00:25.043523 [0] AVG Duty = 4891%(X100)
7372 01:00:25.044116
7373 01:00:25.046485 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7374 01:00:25.046948
7375 01:00:25.049526 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7376 01:00:25.052788 [DutyScan_Calibration_Flow] ====Done====
7377 01:00:25.053244
7378 01:00:25.056222 [DutyScan_Calibration_Flow] k_type=2
7379 01:00:25.073161
7380 01:00:25.073942 ==DQ 0 ==
7381 01:00:25.076296 Final DQ duty delay cell = -4
7382 01:00:25.079369 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7383 01:00:25.082813 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7384 01:00:25.086316 [-4] AVG Duty = 4953%(X100)
7385 01:00:25.086878
7386 01:00:25.087243 ==DQ 1 ==
7387 01:00:25.089543 Final DQ duty delay cell = 0
7388 01:00:25.092537 [0] MAX Duty = 5125%(X100), DQS PI = 48
7389 01:00:25.095892 [0] MIN Duty = 4969%(X100), DQS PI = 38
7390 01:00:25.099058 [0] AVG Duty = 5047%(X100)
7391 01:00:25.099616
7392 01:00:25.102307 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7393 01:00:25.102789
7394 01:00:25.105717 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7395 01:00:25.109024 [DutyScan_Calibration_Flow] ====Done====
7396 01:00:25.109487 ==
7397 01:00:25.112583 Dram Type= 6, Freq= 0, CH_1, rank 0
7398 01:00:25.115872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7399 01:00:25.116436 ==
7400 01:00:25.119041 [Duty_Offset_Calibration]
7401 01:00:25.119499 B0:-1 B1:1 CA:1
7402 01:00:25.122069
7403 01:00:25.125410 [DutyScan_Calibration_Flow] k_type=0
7404 01:00:25.133816
7405 01:00:25.134410 ==CLK 0==
7406 01:00:25.137192 Final CLK duty delay cell = 0
7407 01:00:25.140032 [0] MAX Duty = 5187%(X100), DQS PI = 22
7408 01:00:25.143415 [0] MIN Duty = 5000%(X100), DQS PI = 0
7409 01:00:25.143964 [0] AVG Duty = 5093%(X100)
7410 01:00:25.147294
7411 01:00:25.150787 CH1 CLK Duty spec in!! Max-Min= 187%
7412 01:00:25.153950 [DutyScan_Calibration_Flow] ====Done====
7413 01:00:25.154458
7414 01:00:25.156702 [DutyScan_Calibration_Flow] k_type=1
7415 01:00:25.173376
7416 01:00:25.173952 ==DQS 0 ==
7417 01:00:25.177055 Final DQS duty delay cell = 0
7418 01:00:25.179674 [0] MAX Duty = 5124%(X100), DQS PI = 16
7419 01:00:25.182931 [0] MIN Duty = 4907%(X100), DQS PI = 8
7420 01:00:25.186700 [0] AVG Duty = 5015%(X100)
7421 01:00:25.187257
7422 01:00:25.187615 ==DQS 1 ==
7423 01:00:25.190004 Final DQS duty delay cell = 0
7424 01:00:25.193098 [0] MAX Duty = 5093%(X100), DQS PI = 32
7425 01:00:25.196065 [0] MIN Duty = 4969%(X100), DQS PI = 56
7426 01:00:25.199771 [0] AVG Duty = 5031%(X100)
7427 01:00:25.200345
7428 01:00:25.202736 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7429 01:00:25.203193
7430 01:00:25.206285 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7431 01:00:25.210070 [DutyScan_Calibration_Flow] ====Done====
7432 01:00:25.210679
7433 01:00:25.212670 [DutyScan_Calibration_Flow] k_type=3
7434 01:00:25.230370
7435 01:00:25.230937 ==DQM 0 ==
7436 01:00:25.233546 Final DQM duty delay cell = 0
7437 01:00:25.236476 [0] MAX Duty = 5218%(X100), DQS PI = 18
7438 01:00:25.239759 [0] MIN Duty = 5031%(X100), DQS PI = 8
7439 01:00:25.243445 [0] AVG Duty = 5124%(X100)
7440 01:00:25.244000
7441 01:00:25.244369 ==DQM 1 ==
7442 01:00:25.246928 Final DQM duty delay cell = 0
7443 01:00:25.249697 [0] MAX Duty = 5156%(X100), DQS PI = 6
7444 01:00:25.253276 [0] MIN Duty = 4969%(X100), DQS PI = 28
7445 01:00:25.256683 [0] AVG Duty = 5062%(X100)
7446 01:00:25.257254
7447 01:00:25.260021 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7448 01:00:25.260606
7449 01:00:25.263246 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7450 01:00:25.266452 [DutyScan_Calibration_Flow] ====Done====
7451 01:00:25.266918
7452 01:00:25.269649 [DutyScan_Calibration_Flow] k_type=2
7453 01:00:25.287067
7454 01:00:25.287622 ==DQ 0 ==
7455 01:00:25.290311 Final DQ duty delay cell = 0
7456 01:00:25.293369 [0] MAX Duty = 5156%(X100), DQS PI = 30
7457 01:00:25.296988 [0] MIN Duty = 4906%(X100), DQS PI = 8
7458 01:00:25.297546 [0] AVG Duty = 5031%(X100)
7459 01:00:25.300000
7460 01:00:25.300465 ==DQ 1 ==
7461 01:00:25.302989 Final DQ duty delay cell = 0
7462 01:00:25.306401 [0] MAX Duty = 5156%(X100), DQS PI = 10
7463 01:00:25.309652 [0] MIN Duty = 4969%(X100), DQS PI = 56
7464 01:00:25.312680 [0] AVG Duty = 5062%(X100)
7465 01:00:25.313106
7466 01:00:25.316068 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7467 01:00:25.316491
7468 01:00:25.319785 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7469 01:00:25.322651 [DutyScan_Calibration_Flow] ====Done====
7470 01:00:25.326210 nWR fixed to 30
7471 01:00:25.330038 [ModeRegInit_LP4] CH0 RK0
7472 01:00:25.330619 [ModeRegInit_LP4] CH0 RK1
7473 01:00:25.333193 [ModeRegInit_LP4] CH1 RK0
7474 01:00:25.335928 [ModeRegInit_LP4] CH1 RK1
7475 01:00:25.336355 match AC timing 5
7476 01:00:25.342479 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7477 01:00:25.345599 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7478 01:00:25.349509 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7479 01:00:25.355528 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7480 01:00:25.359020 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7481 01:00:25.359444 [MiockJmeterHQA]
7482 01:00:25.362748
7483 01:00:25.363254 [DramcMiockJmeter] u1RxGatingPI = 0
7484 01:00:25.366085 0 : 4363, 4137
7485 01:00:25.366544 4 : 4253, 4027
7486 01:00:25.369214 8 : 4253, 4027
7487 01:00:25.369643 12 : 4252, 4027
7488 01:00:25.372749 16 : 4255, 4029
7489 01:00:25.373298 20 : 4363, 4138
7490 01:00:25.375547 24 : 4360, 4137
7491 01:00:25.375977 28 : 4252, 4027
7492 01:00:25.376316 32 : 4253, 4026
7493 01:00:25.378962 36 : 4255, 4029
7494 01:00:25.379391 40 : 4252, 4027
7495 01:00:25.382068 44 : 4253, 4026
7496 01:00:25.382555 48 : 4363, 4138
7497 01:00:25.385214 52 : 4250, 4026
7498 01:00:25.385639 56 : 4252, 4027
7499 01:00:25.386067 60 : 4250, 4027
7500 01:00:25.388828 64 : 4250, 4026
7501 01:00:25.389349 68 : 4250, 4027
7502 01:00:25.392379 72 : 4361, 4137
7503 01:00:25.392856 76 : 4361, 4137
7504 01:00:25.395507 80 : 4250, 4027
7505 01:00:25.395932 84 : 4250, 4027
7506 01:00:25.398585 88 : 4250, 4027
7507 01:00:25.399012 92 : 4250, 1101
7508 01:00:25.399491 96 : 4252, 0
7509 01:00:25.402116 100 : 4252, 0
7510 01:00:25.402566 104 : 4250, 0
7511 01:00:25.405574 108 : 4250, 0
7512 01:00:25.405994 112 : 4250, 0
7513 01:00:25.406388 116 : 4253, 0
7514 01:00:25.408523 120 : 4250, 0
7515 01:00:25.408945 124 : 4252, 0
7516 01:00:25.411904 128 : 4360, 0
7517 01:00:25.412329 132 : 4360, 0
7518 01:00:25.412664 136 : 4361, 0
7519 01:00:25.414808 140 : 4250, 0
7520 01:00:25.415231 144 : 4361, 0
7521 01:00:25.418271 148 : 4250, 0
7522 01:00:25.418693 152 : 4250, 0
7523 01:00:25.419089 156 : 4250, 0
7524 01:00:25.421571 160 : 4250, 0
7525 01:00:25.422100 164 : 4252, 0
7526 01:00:25.422498 168 : 4250, 0
7527 01:00:25.424963 172 : 4250, 0
7528 01:00:25.425413 176 : 4252, 0
7529 01:00:25.428852 180 : 4361, 0
7530 01:00:25.429668 184 : 4360, 0
7531 01:00:25.430226 188 : 4250, 0
7532 01:00:25.431534 192 : 4250, 0
7533 01:00:25.431969 196 : 4250, 0
7534 01:00:25.435042 200 : 4363, 0
7535 01:00:25.435480 204 : 4250, 0
7536 01:00:25.435919 208 : 4250, 0
7537 01:00:25.438623 212 : 4250, 0
7538 01:00:25.439058 216 : 4252, 0
7539 01:00:25.441703 220 : 4250, 0
7540 01:00:25.442152 224 : 4250, 15
7541 01:00:25.442626 228 : 4250, 2903
7542 01:00:25.444930 232 : 4363, 4140
7543 01:00:25.445364 236 : 4250, 4027
7544 01:00:25.448385 240 : 4250, 4027
7545 01:00:25.448933 244 : 4250, 4027
7546 01:00:25.451341 248 : 4250, 4026
7547 01:00:25.451782 252 : 4250, 4027
7548 01:00:25.454695 256 : 4250, 4027
7549 01:00:25.455133 260 : 4360, 4137
7550 01:00:25.457993 264 : 4250, 4027
7551 01:00:25.458518 268 : 4250, 4027
7552 01:00:25.461269 272 : 4360, 4138
7553 01:00:25.461705 276 : 4250, 4027
7554 01:00:25.464853 280 : 4250, 4027
7555 01:00:25.465295 284 : 4361, 4137
7556 01:00:25.467786 288 : 4250, 4027
7557 01:00:25.468215 292 : 4250, 4027
7558 01:00:25.468555 296 : 4250, 4027
7559 01:00:25.471569 300 : 4250, 4026
7560 01:00:25.472090 304 : 4250, 4027
7561 01:00:25.474747 308 : 4250, 4027
7562 01:00:25.475180 312 : 4361, 4137
7563 01:00:25.478292 316 : 4250, 4026
7564 01:00:25.478820 320 : 4250, 4027
7565 01:00:25.481446 324 : 4360, 4138
7566 01:00:25.481873 328 : 4250, 4027
7567 01:00:25.484655 332 : 4250, 4027
7568 01:00:25.485189 336 : 4361, 4079
7569 01:00:25.487696 340 : 4250, 2696
7570 01:00:25.488128 344 : 4250, 221
7571 01:00:25.488467
7572 01:00:25.490835 MIOCK jitter meter ch=0
7573 01:00:25.491255
7574 01:00:25.494301 1T = (344-92) = 252 dly cells
7575 01:00:25.497950 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7576 01:00:25.498523 ==
7577 01:00:25.501136 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 01:00:25.507106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 01:00:25.507531 ==
7580 01:00:25.510533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7581 01:00:25.517203 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7582 01:00:25.520743 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7583 01:00:25.527478 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7584 01:00:25.535729 [CA 0] Center 43 (13~74) winsize 62
7585 01:00:25.539026 [CA 1] Center 43 (13~73) winsize 61
7586 01:00:25.541967 [CA 2] Center 38 (9~68) winsize 60
7587 01:00:25.545154 [CA 3] Center 38 (9~68) winsize 60
7588 01:00:25.548994 [CA 4] Center 37 (8~66) winsize 59
7589 01:00:25.551955 [CA 5] Center 36 (6~66) winsize 61
7590 01:00:25.552422
7591 01:00:25.555299 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7592 01:00:25.555857
7593 01:00:25.561905 [CATrainingPosCal] consider 1 rank data
7594 01:00:25.562426 u2DelayCellTimex100 = 258/100 ps
7595 01:00:25.568479 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7596 01:00:25.571914 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7597 01:00:25.574867 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7598 01:00:25.578704 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7599 01:00:25.581418 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7600 01:00:25.584772 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7601 01:00:25.585237
7602 01:00:25.588784 CA PerBit enable=1, Macro0, CA PI delay=36
7603 01:00:25.589341
7604 01:00:25.592022 [CBTSetCACLKResult] CA Dly = 36
7605 01:00:25.595174 CS Dly: 11 (0~42)
7606 01:00:25.598084 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7607 01:00:25.601830 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7608 01:00:25.602473 ==
7609 01:00:25.604628 Dram Type= 6, Freq= 0, CH_0, rank 1
7610 01:00:25.611466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 01:00:25.612027 ==
7612 01:00:25.614368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7613 01:00:25.620733 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7614 01:00:25.623936 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7615 01:00:25.631157 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7616 01:00:25.639107 [CA 0] Center 43 (13~74) winsize 62
7617 01:00:25.642381 [CA 1] Center 44 (14~74) winsize 61
7618 01:00:25.645629 [CA 2] Center 38 (9~68) winsize 60
7619 01:00:25.648756 [CA 3] Center 38 (9~68) winsize 60
7620 01:00:25.652290 [CA 4] Center 36 (7~66) winsize 60
7621 01:00:25.655057 [CA 5] Center 36 (6~66) winsize 61
7622 01:00:25.655527
7623 01:00:25.658547 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7624 01:00:25.659011
7625 01:00:25.665275 [CATrainingPosCal] consider 2 rank data
7626 01:00:25.665917 u2DelayCellTimex100 = 258/100 ps
7627 01:00:25.671569 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7628 01:00:25.674995 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7629 01:00:25.678543 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7630 01:00:25.681724 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7631 01:00:25.684742 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7632 01:00:25.688005 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7633 01:00:25.688535
7634 01:00:25.691184 CA PerBit enable=1, Macro0, CA PI delay=36
7635 01:00:25.691607
7636 01:00:25.694684 [CBTSetCACLKResult] CA Dly = 36
7637 01:00:25.698187 CS Dly: 12 (0~44)
7638 01:00:25.701268 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7639 01:00:25.704524 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7640 01:00:25.705044
7641 01:00:25.707798 ----->DramcWriteLeveling(PI) begin...
7642 01:00:25.708285 ==
7643 01:00:25.711474 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 01:00:25.717922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 01:00:25.718496 ==
7646 01:00:25.721297 Write leveling (Byte 0): 34 => 34
7647 01:00:25.725066 Write leveling (Byte 1): 26 => 26
7648 01:00:25.727731 DramcWriteLeveling(PI) end<-----
7649 01:00:25.728152
7650 01:00:25.728488 ==
7651 01:00:25.731000 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 01:00:25.734048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 01:00:25.734677 ==
7654 01:00:25.737362 [Gating] SW mode calibration
7655 01:00:25.744256 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7656 01:00:25.750668 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7657 01:00:25.754260 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 01:00:25.757276 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 01:00:25.763649 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 01:00:25.767363 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7661 01:00:25.770603 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7662 01:00:25.776937 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7663 01:00:25.780167 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7664 01:00:25.783421 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7665 01:00:25.790101 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7666 01:00:25.793446 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7667 01:00:25.796493 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7668 01:00:25.803617 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7669 01:00:25.806376 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7670 01:00:25.809633 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7671 01:00:25.816604 1 5 24 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
7672 01:00:25.819833 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 01:00:25.823122 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 01:00:25.829870 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7675 01:00:25.833271 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7676 01:00:25.836578 1 6 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7677 01:00:25.842753 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7678 01:00:25.846403 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7679 01:00:25.849673 1 6 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7680 01:00:25.855825 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 01:00:25.859581 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7682 01:00:25.862360 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7683 01:00:25.868919 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7684 01:00:25.872657 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7685 01:00:25.875621 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7686 01:00:25.882343 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7687 01:00:25.885764 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 01:00:25.889033 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 01:00:25.895256 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 01:00:25.898542 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 01:00:25.902321 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 01:00:25.908669 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 01:00:25.911815 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 01:00:25.914954 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 01:00:25.921957 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 01:00:25.925045 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 01:00:25.928314 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 01:00:25.935107 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 01:00:25.938698 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7700 01:00:25.941669 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7701 01:00:25.948560 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7702 01:00:25.949107 Total UI for P1: 0, mck2ui 16
7703 01:00:25.955112 best dqsien dly found for B0: ( 1, 9, 10)
7704 01:00:25.957948 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7705 01:00:25.961270 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7706 01:00:25.964736 Total UI for P1: 0, mck2ui 16
7707 01:00:25.967822 best dqsien dly found for B1: ( 1, 9, 18)
7708 01:00:25.971547 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7709 01:00:25.974728 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7710 01:00:25.975287
7711 01:00:25.981042 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7712 01:00:25.984780 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7713 01:00:25.987880 [Gating] SW calibration Done
7714 01:00:25.988346 ==
7715 01:00:25.991173 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 01:00:25.994092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 01:00:25.994600 ==
7718 01:00:25.994975 RX Vref Scan: 0
7719 01:00:25.997278
7720 01:00:25.997739 RX Vref 0 -> 0, step: 1
7721 01:00:25.998137
7722 01:00:26.001146 RX Delay 0 -> 252, step: 8
7723 01:00:26.003850 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7724 01:00:26.007309 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7725 01:00:26.013852 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7726 01:00:26.017238 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7727 01:00:26.020259 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7728 01:00:26.023451 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7729 01:00:26.026920 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7730 01:00:26.033631 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7731 01:00:26.037172 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7732 01:00:26.040047 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7733 01:00:26.043510 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7734 01:00:26.050034 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7735 01:00:26.053240 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7736 01:00:26.056575 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7737 01:00:26.059819 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7738 01:00:26.063619 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7739 01:00:26.066316 ==
7740 01:00:26.066877 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 01:00:26.072813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 01:00:26.073281 ==
7743 01:00:26.073647 DQS Delay:
7744 01:00:26.076182 DQS0 = 0, DQS1 = 0
7745 01:00:26.076650 DQM Delay:
7746 01:00:26.079883 DQM0 = 134, DQM1 = 126
7747 01:00:26.080444 DQ Delay:
7748 01:00:26.082921 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7749 01:00:26.086113 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7750 01:00:26.089505 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7751 01:00:26.092487 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7752 01:00:26.092951
7753 01:00:26.093322
7754 01:00:26.095868 ==
7755 01:00:26.096336 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 01:00:26.102303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 01:00:26.102731 ==
7758 01:00:26.103069
7759 01:00:26.103385
7760 01:00:26.105751 TX Vref Scan disable
7761 01:00:26.106202 == TX Byte 0 ==
7762 01:00:26.109330 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7763 01:00:26.115783 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7764 01:00:26.116302 == TX Byte 1 ==
7765 01:00:26.118884 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7766 01:00:26.125592 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7767 01:00:26.126096 ==
7768 01:00:26.128796 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 01:00:26.132242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 01:00:26.132754 ==
7771 01:00:26.146064
7772 01:00:26.149700 TX Vref early break, caculate TX vref
7773 01:00:26.152757 TX Vref=16, minBit 4, minWin=22, winSum=371
7774 01:00:26.156237 TX Vref=18, minBit 4, minWin=23, winSum=378
7775 01:00:26.159605 TX Vref=20, minBit 0, minWin=24, winSum=391
7776 01:00:26.162326 TX Vref=22, minBit 6, minWin=24, winSum=401
7777 01:00:26.166131 TX Vref=24, minBit 4, minWin=24, winSum=407
7778 01:00:26.172339 TX Vref=26, minBit 3, minWin=25, winSum=413
7779 01:00:26.175743 TX Vref=28, minBit 1, minWin=25, winSum=414
7780 01:00:26.178678 TX Vref=30, minBit 4, minWin=25, winSum=410
7781 01:00:26.182463 TX Vref=32, minBit 0, minWin=24, winSum=395
7782 01:00:26.185267 TX Vref=34, minBit 7, minWin=22, winSum=386
7783 01:00:26.191902 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 28
7784 01:00:26.192467
7785 01:00:26.195752 Final TX Range 0 Vref 28
7786 01:00:26.196229
7787 01:00:26.196703 ==
7788 01:00:26.198551 Dram Type= 6, Freq= 0, CH_0, rank 0
7789 01:00:26.202056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7790 01:00:26.202528 ==
7791 01:00:26.202966
7792 01:00:26.203451
7793 01:00:26.205334 TX Vref Scan disable
7794 01:00:26.211748 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7795 01:00:26.212271 == TX Byte 0 ==
7796 01:00:26.215146 u2DelayCellOfst[0]=18 cells (5 PI)
7797 01:00:26.218489 u2DelayCellOfst[1]=18 cells (5 PI)
7798 01:00:26.221680 u2DelayCellOfst[2]=15 cells (4 PI)
7799 01:00:26.224940 u2DelayCellOfst[3]=15 cells (4 PI)
7800 01:00:26.228310 u2DelayCellOfst[4]=11 cells (3 PI)
7801 01:00:26.231315 u2DelayCellOfst[5]=0 cells (0 PI)
7802 01:00:26.235074 u2DelayCellOfst[6]=18 cells (5 PI)
7803 01:00:26.238079 u2DelayCellOfst[7]=22 cells (6 PI)
7804 01:00:26.241810 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7805 01:00:26.244694 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7806 01:00:26.248341 == TX Byte 1 ==
7807 01:00:26.251114 u2DelayCellOfst[8]=0 cells (0 PI)
7808 01:00:26.254433 u2DelayCellOfst[9]=3 cells (1 PI)
7809 01:00:26.258392 u2DelayCellOfst[10]=7 cells (2 PI)
7810 01:00:26.260936 u2DelayCellOfst[11]=3 cells (1 PI)
7811 01:00:26.264315 u2DelayCellOfst[12]=15 cells (4 PI)
7812 01:00:26.268046 u2DelayCellOfst[13]=15 cells (4 PI)
7813 01:00:26.268607 u2DelayCellOfst[14]=15 cells (4 PI)
7814 01:00:26.271167 u2DelayCellOfst[15]=15 cells (4 PI)
7815 01:00:26.277441 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7816 01:00:26.280832 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7817 01:00:26.284217 DramC Write-DBI on
7818 01:00:26.284674 ==
7819 01:00:26.287494 Dram Type= 6, Freq= 0, CH_0, rank 0
7820 01:00:26.290937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7821 01:00:26.291431 ==
7822 01:00:26.291891
7823 01:00:26.292209
7824 01:00:26.293838 TX Vref Scan disable
7825 01:00:26.294317 == TX Byte 0 ==
7826 01:00:26.300581 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7827 01:00:26.301113 == TX Byte 1 ==
7828 01:00:26.304476 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7829 01:00:26.307459 DramC Write-DBI off
7830 01:00:26.308035
7831 01:00:26.308518 [DATLAT]
7832 01:00:26.310553 Freq=1600, CH0 RK0
7833 01:00:26.311028
7834 01:00:26.311617 DATLAT Default: 0xf
7835 01:00:26.313774 0, 0xFFFF, sum = 0
7836 01:00:26.317096 1, 0xFFFF, sum = 0
7837 01:00:26.317639 2, 0xFFFF, sum = 0
7838 01:00:26.320615 3, 0xFFFF, sum = 0
7839 01:00:26.321160 4, 0xFFFF, sum = 0
7840 01:00:26.323711 5, 0xFFFF, sum = 0
7841 01:00:26.324157 6, 0xFFFF, sum = 0
7842 01:00:26.327198 7, 0xFFFF, sum = 0
7843 01:00:26.327733 8, 0xFFFF, sum = 0
7844 01:00:26.330595 9, 0xFFFF, sum = 0
7845 01:00:26.331134 10, 0xFFFF, sum = 0
7846 01:00:26.333695 11, 0xFFFF, sum = 0
7847 01:00:26.334279 12, 0xFFFF, sum = 0
7848 01:00:26.337182 13, 0xFFFF, sum = 0
7849 01:00:26.337725 14, 0x0, sum = 1
7850 01:00:26.340145 15, 0x0, sum = 2
7851 01:00:26.340585 16, 0x0, sum = 3
7852 01:00:26.343755 17, 0x0, sum = 4
7853 01:00:26.344196 best_step = 15
7854 01:00:26.344627
7855 01:00:26.345036 ==
7856 01:00:26.346638 Dram Type= 6, Freq= 0, CH_0, rank 0
7857 01:00:26.353554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7858 01:00:26.354088 ==
7859 01:00:26.354584 RX Vref Scan: 1
7860 01:00:26.355007
7861 01:00:26.357458 Set Vref Range= 24 -> 127
7862 01:00:26.357993
7863 01:00:26.360021 RX Vref 24 -> 127, step: 1
7864 01:00:26.360454
7865 01:00:26.360893 RX Delay 11 -> 252, step: 4
7866 01:00:26.363186
7867 01:00:26.363617 Set Vref, RX VrefLevel [Byte0]: 24
7868 01:00:26.366480 [Byte1]: 24
7869 01:00:26.370761
7870 01:00:26.371280 Set Vref, RX VrefLevel [Byte0]: 25
7871 01:00:26.373817 [Byte1]: 25
7872 01:00:26.378625
7873 01:00:26.379194 Set Vref, RX VrefLevel [Byte0]: 26
7874 01:00:26.381724 [Byte1]: 26
7875 01:00:26.385965
7876 01:00:26.386504 Set Vref, RX VrefLevel [Byte0]: 27
7877 01:00:26.389481 [Byte1]: 27
7878 01:00:26.393562
7879 01:00:26.394078 Set Vref, RX VrefLevel [Byte0]: 28
7880 01:00:26.397079 [Byte1]: 28
7881 01:00:26.401621
7882 01:00:26.402254 Set Vref, RX VrefLevel [Byte0]: 29
7883 01:00:26.404831 [Byte1]: 29
7884 01:00:26.408813
7885 01:00:26.409382 Set Vref, RX VrefLevel [Byte0]: 30
7886 01:00:26.412092 [Byte1]: 30
7887 01:00:26.416223
7888 01:00:26.416682 Set Vref, RX VrefLevel [Byte0]: 31
7889 01:00:26.419926 [Byte1]: 31
7890 01:00:26.424082
7891 01:00:26.424681 Set Vref, RX VrefLevel [Byte0]: 32
7892 01:00:26.431011 [Byte1]: 32
7893 01:00:26.431695
7894 01:00:26.434066 Set Vref, RX VrefLevel [Byte0]: 33
7895 01:00:26.437471 [Byte1]: 33
7896 01:00:26.438046
7897 01:00:26.440669 Set Vref, RX VrefLevel [Byte0]: 34
7898 01:00:26.443703 [Byte1]: 34
7899 01:00:26.446744
7900 01:00:26.447196 Set Vref, RX VrefLevel [Byte0]: 35
7901 01:00:26.450397 [Byte1]: 35
7902 01:00:26.454141
7903 01:00:26.454683 Set Vref, RX VrefLevel [Byte0]: 36
7904 01:00:26.457570 [Byte1]: 36
7905 01:00:26.461819
7906 01:00:26.462268 Set Vref, RX VrefLevel [Byte0]: 37
7907 01:00:26.465096 [Byte1]: 37
7908 01:00:26.469883
7909 01:00:26.470337 Set Vref, RX VrefLevel [Byte0]: 38
7910 01:00:26.472720 [Byte1]: 38
7911 01:00:26.477133
7912 01:00:26.477967 Set Vref, RX VrefLevel [Byte0]: 39
7913 01:00:26.480719 [Byte1]: 39
7914 01:00:26.484906
7915 01:00:26.485318 Set Vref, RX VrefLevel [Byte0]: 40
7916 01:00:26.488288 [Byte1]: 40
7917 01:00:26.492510
7918 01:00:26.492961 Set Vref, RX VrefLevel [Byte0]: 41
7919 01:00:26.495645 [Byte1]: 41
7920 01:00:26.500933
7921 01:00:26.501465 Set Vref, RX VrefLevel [Byte0]: 42
7922 01:00:26.503977 [Byte1]: 42
7923 01:00:26.507676
7924 01:00:26.508106 Set Vref, RX VrefLevel [Byte0]: 43
7925 01:00:26.511129 [Byte1]: 43
7926 01:00:26.515329
7927 01:00:26.515744 Set Vref, RX VrefLevel [Byte0]: 44
7928 01:00:26.518762 [Byte1]: 44
7929 01:00:26.522744
7930 01:00:26.523175 Set Vref, RX VrefLevel [Byte0]: 45
7931 01:00:26.526285 [Byte1]: 45
7932 01:00:26.530417
7933 01:00:26.530886 Set Vref, RX VrefLevel [Byte0]: 46
7934 01:00:26.533679 [Byte1]: 46
7935 01:00:26.538027
7936 01:00:26.538507 Set Vref, RX VrefLevel [Byte0]: 47
7937 01:00:26.541372 [Byte1]: 47
7938 01:00:26.545845
7939 01:00:26.546311 Set Vref, RX VrefLevel [Byte0]: 48
7940 01:00:26.549061 [Byte1]: 48
7941 01:00:26.553231
7942 01:00:26.553657 Set Vref, RX VrefLevel [Byte0]: 49
7943 01:00:26.556765 [Byte1]: 49
7944 01:00:26.560882
7945 01:00:26.561313 Set Vref, RX VrefLevel [Byte0]: 50
7946 01:00:26.564132 [Byte1]: 50
7947 01:00:26.568353
7948 01:00:26.568771 Set Vref, RX VrefLevel [Byte0]: 51
7949 01:00:26.572247 [Byte1]: 51
7950 01:00:26.576364
7951 01:00:26.576876 Set Vref, RX VrefLevel [Byte0]: 52
7952 01:00:26.579627 [Byte1]: 52
7953 01:00:26.584172
7954 01:00:26.584592 Set Vref, RX VrefLevel [Byte0]: 53
7955 01:00:26.587312 [Byte1]: 53
7956 01:00:26.591400
7957 01:00:26.591828 Set Vref, RX VrefLevel [Byte0]: 54
7958 01:00:26.594894 [Byte1]: 54
7959 01:00:26.598828
7960 01:00:26.599259 Set Vref, RX VrefLevel [Byte0]: 55
7961 01:00:26.602525 [Byte1]: 55
7962 01:00:26.606809
7963 01:00:26.607318 Set Vref, RX VrefLevel [Byte0]: 56
7964 01:00:26.610141 [Byte1]: 56
7965 01:00:26.614282
7966 01:00:26.614708 Set Vref, RX VrefLevel [Byte0]: 57
7967 01:00:26.617625 [Byte1]: 57
7968 01:00:26.622056
7969 01:00:26.622653 Set Vref, RX VrefLevel [Byte0]: 58
7970 01:00:26.625316 [Byte1]: 58
7971 01:00:26.629312
7972 01:00:26.629740 Set Vref, RX VrefLevel [Byte0]: 59
7973 01:00:26.633215 [Byte1]: 59
7974 01:00:26.637069
7975 01:00:26.637642 Set Vref, RX VrefLevel [Byte0]: 60
7976 01:00:26.640673 [Byte1]: 60
7977 01:00:26.644744
7978 01:00:26.645217 Set Vref, RX VrefLevel [Byte0]: 61
7979 01:00:26.648260 [Byte1]: 61
7980 01:00:26.652619
7981 01:00:26.653173 Set Vref, RX VrefLevel [Byte0]: 62
7982 01:00:26.655845 [Byte1]: 62
7983 01:00:26.659869
7984 01:00:26.660430 Set Vref, RX VrefLevel [Byte0]: 63
7985 01:00:26.663524 [Byte1]: 63
7986 01:00:26.667425
7987 01:00:26.667843 Set Vref, RX VrefLevel [Byte0]: 64
7988 01:00:26.670807 [Byte1]: 64
7989 01:00:26.675466
7990 01:00:26.676030 Set Vref, RX VrefLevel [Byte0]: 65
7991 01:00:26.678654 [Byte1]: 65
7992 01:00:26.682857
7993 01:00:26.683272 Set Vref, RX VrefLevel [Byte0]: 66
7994 01:00:26.686271 [Byte1]: 66
7995 01:00:26.690663
7996 01:00:26.691215 Set Vref, RX VrefLevel [Byte0]: 67
7997 01:00:26.694011 [Byte1]: 67
7998 01:00:26.697949
7999 01:00:26.698394 Set Vref, RX VrefLevel [Byte0]: 68
8000 01:00:26.701831 [Byte1]: 68
8001 01:00:26.706257
8002 01:00:26.706840 Set Vref, RX VrefLevel [Byte0]: 69
8003 01:00:26.709062 [Byte1]: 69
8004 01:00:26.713121
8005 01:00:26.713578 Set Vref, RX VrefLevel [Byte0]: 70
8006 01:00:26.716678 [Byte1]: 70
8007 01:00:26.721051
8008 01:00:26.721602 Set Vref, RX VrefLevel [Byte0]: 71
8009 01:00:26.724270 [Byte1]: 71
8010 01:00:26.728369
8011 01:00:26.728828 Set Vref, RX VrefLevel [Byte0]: 72
8012 01:00:26.732300 [Byte1]: 72
8013 01:00:26.736745
8014 01:00:26.737298 Set Vref, RX VrefLevel [Byte0]: 73
8015 01:00:26.739698 [Byte1]: 73
8016 01:00:26.743712
8017 01:00:26.744170 Set Vref, RX VrefLevel [Byte0]: 74
8018 01:00:26.747249 [Byte1]: 74
8019 01:00:26.751592
8020 01:00:26.752197 Set Vref, RX VrefLevel [Byte0]: 75
8021 01:00:26.754973 [Byte1]: 75
8022 01:00:26.758789
8023 01:00:26.759245 Set Vref, RX VrefLevel [Byte0]: 76
8024 01:00:26.762812 [Byte1]: 76
8025 01:00:26.766683
8026 01:00:26.767231 Set Vref, RX VrefLevel [Byte0]: 77
8027 01:00:26.770061 [Byte1]: 77
8028 01:00:26.774055
8029 01:00:26.774661 Set Vref, RX VrefLevel [Byte0]: 78
8030 01:00:26.777584 [Byte1]: 78
8031 01:00:26.781901
8032 01:00:26.782572 Set Vref, RX VrefLevel [Byte0]: 79
8033 01:00:26.785294 [Byte1]: 79
8034 01:00:26.789753
8035 01:00:26.790331 Final RX Vref Byte 0 = 62 to rank0
8036 01:00:26.792770 Final RX Vref Byte 1 = 58 to rank0
8037 01:00:26.796105 Final RX Vref Byte 0 = 62 to rank1
8038 01:00:26.799314 Final RX Vref Byte 1 = 58 to rank1==
8039 01:00:26.802944 Dram Type= 6, Freq= 0, CH_0, rank 0
8040 01:00:26.809266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 01:00:26.809831 ==
8042 01:00:26.810231 DQS Delay:
8043 01:00:26.812594 DQS0 = 0, DQS1 = 0
8044 01:00:26.813150 DQM Delay:
8045 01:00:26.813518 DQM0 = 132, DQM1 = 124
8046 01:00:26.815889 DQ Delay:
8047 01:00:26.818866 DQ0 =130, DQ1 =132, DQ2 =130, DQ3 =130
8048 01:00:26.822387 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
8049 01:00:26.825672 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8050 01:00:26.829179 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =128
8051 01:00:26.829746
8052 01:00:26.830110
8053 01:00:26.830503
8054 01:00:26.832446 [DramC_TX_OE_Calibration] TA2
8055 01:00:26.835665 Original DQ_B0 (3 6) =30, OEN = 27
8056 01:00:26.838873 Original DQ_B1 (3 6) =30, OEN = 27
8057 01:00:26.842237 24, 0x0, End_B0=24 End_B1=24
8058 01:00:26.842949 25, 0x0, End_B0=25 End_B1=25
8059 01:00:26.845519 26, 0x0, End_B0=26 End_B1=26
8060 01:00:26.848919 27, 0x0, End_B0=27 End_B1=27
8061 01:00:26.852344 28, 0x0, End_B0=28 End_B1=28
8062 01:00:26.855416 29, 0x0, End_B0=29 End_B1=29
8063 01:00:26.855882 30, 0x0, End_B0=30 End_B1=30
8064 01:00:26.858745 31, 0x4141, End_B0=30 End_B1=30
8065 01:00:26.862108 Byte0 end_step=30 best_step=27
8066 01:00:26.865278 Byte1 end_step=30 best_step=27
8067 01:00:26.868578 Byte0 TX OE(2T, 0.5T) = (3, 3)
8068 01:00:26.871761 Byte1 TX OE(2T, 0.5T) = (3, 3)
8069 01:00:26.872220
8070 01:00:26.872580
8071 01:00:26.878539 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8072 01:00:26.882131 CH0 RK0: MR19=303, MR18=2011
8073 01:00:26.889008 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8074 01:00:26.889587
8075 01:00:26.892159 ----->DramcWriteLeveling(PI) begin...
8076 01:00:26.892740 ==
8077 01:00:26.894948 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 01:00:26.898506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 01:00:26.898968 ==
8080 01:00:26.901517 Write leveling (Byte 0): 33 => 33
8081 01:00:26.904696 Write leveling (Byte 1): 28 => 28
8082 01:00:26.908229 DramcWriteLeveling(PI) end<-----
8083 01:00:26.908774
8084 01:00:26.909106 ==
8085 01:00:26.911717 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 01:00:26.914632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 01:00:26.918452 ==
8088 01:00:26.918966 [Gating] SW mode calibration
8089 01:00:26.927892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8090 01:00:26.931472 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8091 01:00:26.934562 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 01:00:26.941192 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 01:00:26.944912 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 01:00:26.948232 1 4 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
8095 01:00:26.954610 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8096 01:00:26.957904 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
8097 01:00:26.960807 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8098 01:00:26.967728 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8099 01:00:26.970998 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8100 01:00:26.974116 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8101 01:00:26.980900 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8102 01:00:26.984438 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8103 01:00:26.987489 1 5 16 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8104 01:00:26.994488 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8105 01:00:26.997263 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8106 01:00:27.000822 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8107 01:00:27.007405 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 01:00:27.010652 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 01:00:27.014015 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8110 01:00:27.020864 1 6 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8111 01:00:27.024062 1 6 16 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
8112 01:00:27.027055 1 6 20 | B1->B0 | 3635 4646 | 1 0 | (0 0) (0 0)
8113 01:00:27.033731 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8114 01:00:27.037223 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 01:00:27.040295 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 01:00:27.047076 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8117 01:00:27.050058 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8118 01:00:27.053643 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8119 01:00:27.060052 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8120 01:00:27.063153 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8121 01:00:27.066845 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8122 01:00:27.072923 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 01:00:27.076595 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 01:00:27.079676 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 01:00:27.086106 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 01:00:27.089788 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 01:00:27.093023 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 01:00:27.099389 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 01:00:27.102912 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 01:00:27.106011 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 01:00:27.112788 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 01:00:27.116363 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 01:00:27.119373 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8134 01:00:27.125973 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8135 01:00:27.129428 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8136 01:00:27.132463 Total UI for P1: 0, mck2ui 16
8137 01:00:27.136235 best dqsien dly found for B0: ( 1, 9, 10)
8138 01:00:27.139421 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8139 01:00:27.145756 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 01:00:27.146355 Total UI for P1: 0, mck2ui 16
8141 01:00:27.152761 best dqsien dly found for B1: ( 1, 9, 18)
8142 01:00:27.155573 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8143 01:00:27.158793 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8144 01:00:27.159249
8145 01:00:27.162249 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8146 01:00:27.165358 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8147 01:00:27.168893 [Gating] SW calibration Done
8148 01:00:27.169347 ==
8149 01:00:27.172371 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 01:00:27.175417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 01:00:27.175979 ==
8152 01:00:27.178645 RX Vref Scan: 0
8153 01:00:27.179101
8154 01:00:27.181937 RX Vref 0 -> 0, step: 1
8155 01:00:27.182546
8156 01:00:27.182920 RX Delay 0 -> 252, step: 8
8157 01:00:27.188333 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8158 01:00:27.191832 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8159 01:00:27.194888 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8160 01:00:27.198284 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8161 01:00:27.201712 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8162 01:00:27.208270 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8163 01:00:27.211424 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8164 01:00:27.214560 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8165 01:00:27.218237 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8166 01:00:27.221367 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8167 01:00:27.227870 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8168 01:00:27.230816 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8169 01:00:27.234472 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8170 01:00:27.237584 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8171 01:00:27.244076 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8172 01:00:27.247765 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8173 01:00:27.248320 ==
8174 01:00:27.250793 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 01:00:27.254288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 01:00:27.254868 ==
8177 01:00:27.257236 DQS Delay:
8178 01:00:27.257689 DQS0 = 0, DQS1 = 0
8179 01:00:27.258226 DQM Delay:
8180 01:00:27.260831 DQM0 = 133, DQM1 = 128
8181 01:00:27.261300 DQ Delay:
8182 01:00:27.264099 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8183 01:00:27.267730 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8184 01:00:27.270874 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8185 01:00:27.277457 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8186 01:00:27.277918
8187 01:00:27.278363
8188 01:00:27.278711 ==
8189 01:00:27.280650 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 01:00:27.283985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 01:00:27.284446 ==
8192 01:00:27.284811
8193 01:00:27.285143
8194 01:00:27.287513 TX Vref Scan disable
8195 01:00:27.287967 == TX Byte 0 ==
8196 01:00:27.294070 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8197 01:00:27.296990 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8198 01:00:27.300349 == TX Byte 1 ==
8199 01:00:27.303823 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8200 01:00:27.306805 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8201 01:00:27.307343 ==
8202 01:00:27.310199 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 01:00:27.313672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 01:00:27.316926 ==
8205 01:00:27.328374
8206 01:00:27.331171 TX Vref early break, caculate TX vref
8207 01:00:27.334770 TX Vref=16, minBit 1, minWin=22, winSum=377
8208 01:00:27.337988 TX Vref=18, minBit 1, minWin=23, winSum=386
8209 01:00:27.341474 TX Vref=20, minBit 6, minWin=23, winSum=395
8210 01:00:27.344291 TX Vref=22, minBit 0, minWin=24, winSum=402
8211 01:00:27.347839 TX Vref=24, minBit 1, minWin=24, winSum=411
8212 01:00:27.354756 TX Vref=26, minBit 1, minWin=24, winSum=413
8213 01:00:27.357904 TX Vref=28, minBit 1, minWin=24, winSum=412
8214 01:00:27.361285 TX Vref=30, minBit 1, minWin=23, winSum=405
8215 01:00:27.364140 TX Vref=32, minBit 0, minWin=24, winSum=399
8216 01:00:27.367656 TX Vref=34, minBit 1, minWin=23, winSum=386
8217 01:00:27.374522 [TxChooseVref] Worse bit 1, Min win 24, Win sum 413, Final Vref 26
8218 01:00:27.375101
8219 01:00:27.377929 Final TX Range 0 Vref 26
8220 01:00:27.378561
8221 01:00:27.378938 ==
8222 01:00:27.381018 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 01:00:27.383961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 01:00:27.384426 ==
8225 01:00:27.384794
8226 01:00:27.385133
8227 01:00:27.387702 TX Vref Scan disable
8228 01:00:27.394444 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8229 01:00:27.395021 == TX Byte 0 ==
8230 01:00:27.396990 u2DelayCellOfst[0]=15 cells (4 PI)
8231 01:00:27.401011 u2DelayCellOfst[1]=22 cells (6 PI)
8232 01:00:27.403601 u2DelayCellOfst[2]=15 cells (4 PI)
8233 01:00:27.406802 u2DelayCellOfst[3]=15 cells (4 PI)
8234 01:00:27.410498 u2DelayCellOfst[4]=11 cells (3 PI)
8235 01:00:27.413751 u2DelayCellOfst[5]=0 cells (0 PI)
8236 01:00:27.417129 u2DelayCellOfst[6]=22 cells (6 PI)
8237 01:00:27.420940 u2DelayCellOfst[7]=18 cells (5 PI)
8238 01:00:27.423480 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8239 01:00:27.426661 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8240 01:00:27.430398 == TX Byte 1 ==
8241 01:00:27.434033 u2DelayCellOfst[8]=0 cells (0 PI)
8242 01:00:27.436832 u2DelayCellOfst[9]=3 cells (1 PI)
8243 01:00:27.439984 u2DelayCellOfst[10]=7 cells (2 PI)
8244 01:00:27.443597 u2DelayCellOfst[11]=3 cells (1 PI)
8245 01:00:27.444056 u2DelayCellOfst[12]=15 cells (4 PI)
8246 01:00:27.446888 u2DelayCellOfst[13]=11 cells (3 PI)
8247 01:00:27.450029 u2DelayCellOfst[14]=18 cells (5 PI)
8248 01:00:27.453254 u2DelayCellOfst[15]=11 cells (3 PI)
8249 01:00:27.460160 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8250 01:00:27.463141 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8251 01:00:27.463656 DramC Write-DBI on
8252 01:00:27.466663 ==
8253 01:00:27.469942 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 01:00:27.472949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 01:00:27.473417 ==
8256 01:00:27.473812
8257 01:00:27.474149
8258 01:00:27.476541 TX Vref Scan disable
8259 01:00:27.477166 == TX Byte 0 ==
8260 01:00:27.482962 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8261 01:00:27.483520 == TX Byte 1 ==
8262 01:00:27.486530 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8263 01:00:27.489436 DramC Write-DBI off
8264 01:00:27.489904
8265 01:00:27.490323 [DATLAT]
8266 01:00:27.493110 Freq=1600, CH0 RK1
8267 01:00:27.493675
8268 01:00:27.494040 DATLAT Default: 0xf
8269 01:00:27.496547 0, 0xFFFF, sum = 0
8270 01:00:27.497125 1, 0xFFFF, sum = 0
8271 01:00:27.499704 2, 0xFFFF, sum = 0
8272 01:00:27.500338 3, 0xFFFF, sum = 0
8273 01:00:27.502697 4, 0xFFFF, sum = 0
8274 01:00:27.506189 5, 0xFFFF, sum = 0
8275 01:00:27.506769 6, 0xFFFF, sum = 0
8276 01:00:27.509509 7, 0xFFFF, sum = 0
8277 01:00:27.510320 8, 0xFFFF, sum = 0
8278 01:00:27.512664 9, 0xFFFF, sum = 0
8279 01:00:27.513148 10, 0xFFFF, sum = 0
8280 01:00:27.515568 11, 0xFFFF, sum = 0
8281 01:00:27.516043 12, 0xFFFF, sum = 0
8282 01:00:27.518854 13, 0xFFFF, sum = 0
8283 01:00:27.519325 14, 0x0, sum = 1
8284 01:00:27.522022 15, 0x0, sum = 2
8285 01:00:27.522542 16, 0x0, sum = 3
8286 01:00:27.525402 17, 0x0, sum = 4
8287 01:00:27.525855 best_step = 15
8288 01:00:27.526213
8289 01:00:27.526538 ==
8290 01:00:27.528917 Dram Type= 6, Freq= 0, CH_0, rank 1
8291 01:00:27.535676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 01:00:27.536212 ==
8293 01:00:27.536557 RX Vref Scan: 0
8294 01:00:27.536872
8295 01:00:27.538762 RX Vref 0 -> 0, step: 1
8296 01:00:27.539183
8297 01:00:27.542613 RX Delay 11 -> 252, step: 4
8298 01:00:27.545705 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8299 01:00:27.548677 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8300 01:00:27.551959 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8301 01:00:27.558507 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8302 01:00:27.561947 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8303 01:00:27.565061 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8304 01:00:27.568377 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8305 01:00:27.571466 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8306 01:00:27.578458 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8307 01:00:27.582037 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8308 01:00:27.584635 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8309 01:00:27.588369 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8310 01:00:27.595105 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
8311 01:00:27.598430 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8312 01:00:27.601450 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8313 01:00:27.604715 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8314 01:00:27.605270 ==
8315 01:00:27.608126 Dram Type= 6, Freq= 0, CH_0, rank 1
8316 01:00:27.614521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 01:00:27.614993 ==
8318 01:00:27.615360 DQS Delay:
8319 01:00:27.617839 DQS0 = 0, DQS1 = 0
8320 01:00:27.618489 DQM Delay:
8321 01:00:27.618923 DQM0 = 130, DQM1 = 124
8322 01:00:27.620963 DQ Delay:
8323 01:00:27.624191 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8324 01:00:27.627690 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8325 01:00:27.630851 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =120
8326 01:00:27.634217 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132
8327 01:00:27.634684
8328 01:00:27.635045
8329 01:00:27.635381
8330 01:00:27.637604 [DramC_TX_OE_Calibration] TA2
8331 01:00:27.640990 Original DQ_B0 (3 6) =30, OEN = 27
8332 01:00:27.644354 Original DQ_B1 (3 6) =30, OEN = 27
8333 01:00:27.647469 24, 0x0, End_B0=24 End_B1=24
8334 01:00:27.650787 25, 0x0, End_B0=25 End_B1=25
8335 01:00:27.651213 26, 0x0, End_B0=26 End_B1=26
8336 01:00:27.654263 27, 0x0, End_B0=27 End_B1=27
8337 01:00:27.657379 28, 0x0, End_B0=28 End_B1=28
8338 01:00:27.660435 29, 0x0, End_B0=29 End_B1=29
8339 01:00:27.660852 30, 0x0, End_B0=30 End_B1=30
8340 01:00:27.663824 31, 0x4141, End_B0=30 End_B1=30
8341 01:00:27.667016 Byte0 end_step=30 best_step=27
8342 01:00:27.670197 Byte1 end_step=30 best_step=27
8343 01:00:27.673590 Byte0 TX OE(2T, 0.5T) = (3, 3)
8344 01:00:27.677728 Byte1 TX OE(2T, 0.5T) = (3, 3)
8345 01:00:27.678278
8346 01:00:27.678615
8347 01:00:27.683402 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8348 01:00:27.686706 CH0 RK1: MR19=303, MR18=1E01
8349 01:00:27.693533 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8350 01:00:27.696676 [RxdqsGatingPostProcess] freq 1600
8351 01:00:27.703191 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8352 01:00:27.703608 best DQS0 dly(2T, 0.5T) = (1, 1)
8353 01:00:27.706544 best DQS1 dly(2T, 0.5T) = (1, 1)
8354 01:00:27.710011 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8355 01:00:27.713503 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8356 01:00:27.716889 best DQS0 dly(2T, 0.5T) = (1, 1)
8357 01:00:27.719582 best DQS1 dly(2T, 0.5T) = (1, 1)
8358 01:00:27.722938 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8359 01:00:27.726042 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8360 01:00:27.729644 Pre-setting of DQS Precalculation
8361 01:00:27.732981 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8362 01:00:27.736132 ==
8363 01:00:27.739509 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 01:00:27.742779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 01:00:27.743200 ==
8366 01:00:27.746138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8367 01:00:27.752705 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8368 01:00:27.756431 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8369 01:00:27.762651 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8370 01:00:27.770691 [CA 0] Center 41 (12~71) winsize 60
8371 01:00:27.774036 [CA 1] Center 42 (12~72) winsize 61
8372 01:00:27.777110 [CA 2] Center 37 (8~66) winsize 59
8373 01:00:27.780354 [CA 3] Center 36 (7~65) winsize 59
8374 01:00:27.784019 [CA 4] Center 36 (7~66) winsize 60
8375 01:00:27.787313 [CA 5] Center 36 (7~66) winsize 60
8376 01:00:27.787734
8377 01:00:27.790652 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8378 01:00:27.791070
8379 01:00:27.793704 [CATrainingPosCal] consider 1 rank data
8380 01:00:27.797166 u2DelayCellTimex100 = 258/100 ps
8381 01:00:27.803826 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8382 01:00:27.807221 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8383 01:00:27.810108 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8384 01:00:27.813552 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8385 01:00:27.817336 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8386 01:00:27.820267 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8387 01:00:27.820680
8388 01:00:27.823445 CA PerBit enable=1, Macro0, CA PI delay=36
8389 01:00:27.823874
8390 01:00:27.826608 [CBTSetCACLKResult] CA Dly = 36
8391 01:00:27.830383 CS Dly: 9 (0~40)
8392 01:00:27.833540 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8393 01:00:27.836970 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8394 01:00:27.837541 ==
8395 01:00:27.840204 Dram Type= 6, Freq= 0, CH_1, rank 1
8396 01:00:27.846486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 01:00:27.846997 ==
8398 01:00:27.849861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8399 01:00:27.856535 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8400 01:00:27.860259 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8401 01:00:27.866271 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8402 01:00:27.874386 [CA 0] Center 42 (13~72) winsize 60
8403 01:00:27.877221 [CA 1] Center 43 (13~73) winsize 61
8404 01:00:27.880705 [CA 2] Center 38 (9~67) winsize 59
8405 01:00:27.884124 [CA 3] Center 37 (8~67) winsize 60
8406 01:00:27.887276 [CA 4] Center 37 (8~67) winsize 60
8407 01:00:27.890499 [CA 5] Center 37 (8~67) winsize 60
8408 01:00:27.890958
8409 01:00:27.894331 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8410 01:00:27.894889
8411 01:00:27.897282 [CATrainingPosCal] consider 2 rank data
8412 01:00:27.900275 u2DelayCellTimex100 = 258/100 ps
8413 01:00:27.907614 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8414 01:00:27.910591 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8415 01:00:27.913645 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8416 01:00:27.917107 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8417 01:00:27.920274 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8418 01:00:27.923566 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8419 01:00:27.924029
8420 01:00:27.926936 CA PerBit enable=1, Macro0, CA PI delay=36
8421 01:00:27.927402
8422 01:00:27.930005 [CBTSetCACLKResult] CA Dly = 36
8423 01:00:27.933175 CS Dly: 10 (0~43)
8424 01:00:27.936948 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8425 01:00:27.939985 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8426 01:00:27.940557
8427 01:00:27.943447 ----->DramcWriteLeveling(PI) begin...
8428 01:00:27.944029 ==
8429 01:00:27.946650 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 01:00:27.953143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 01:00:27.953694 ==
8432 01:00:27.956488 Write leveling (Byte 0): 23 => 23
8433 01:00:27.959883 Write leveling (Byte 1): 27 => 27
8434 01:00:27.960444 DramcWriteLeveling(PI) end<-----
8435 01:00:27.963335
8436 01:00:27.963888 ==
8437 01:00:27.966438 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 01:00:27.969496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 01:00:27.969962 ==
8440 01:00:27.973195 [Gating] SW mode calibration
8441 01:00:27.979444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8442 01:00:27.982938 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8443 01:00:27.989133 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 01:00:27.992646 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 01:00:27.996209 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8446 01:00:28.002697 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8447 01:00:28.006594 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8448 01:00:28.009452 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8449 01:00:28.015962 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8450 01:00:28.019523 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8451 01:00:28.022885 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8452 01:00:28.029647 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 01:00:28.032396 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8454 01:00:28.035739 1 5 12 | B1->B0 | 3131 2e2e | 1 0 | (1 0) (0 1)
8455 01:00:28.042538 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8456 01:00:28.045205 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8457 01:00:28.048729 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8458 01:00:28.055136 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8459 01:00:28.058476 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8460 01:00:28.062304 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 01:00:28.068652 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 01:00:28.071694 1 6 12 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
8463 01:00:28.075101 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 01:00:28.081194 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8465 01:00:28.084590 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8466 01:00:28.087964 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8467 01:00:28.094838 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 01:00:28.098030 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 01:00:28.104679 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8470 01:00:28.107726 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8471 01:00:28.110940 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8472 01:00:28.118278 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 01:00:28.121576 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 01:00:28.124844 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 01:00:28.131087 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 01:00:28.134708 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 01:00:28.137666 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 01:00:28.144140 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 01:00:28.147111 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 01:00:28.150588 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 01:00:28.157295 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 01:00:28.160564 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 01:00:28.164000 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 01:00:28.170728 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8485 01:00:28.173872 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8486 01:00:28.176786 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8487 01:00:28.183385 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 01:00:28.183932 Total UI for P1: 0, mck2ui 16
8489 01:00:28.190121 best dqsien dly found for B0: ( 1, 9, 8)
8490 01:00:28.190630 Total UI for P1: 0, mck2ui 16
8491 01:00:28.193829 best dqsien dly found for B1: ( 1, 9, 12)
8492 01:00:28.196606 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8493 01:00:28.203362 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8494 01:00:28.203837
8495 01:00:28.206565 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8496 01:00:28.209972 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8497 01:00:28.213054 [Gating] SW calibration Done
8498 01:00:28.213514 ==
8499 01:00:28.216606 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 01:00:28.220217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 01:00:28.220729 ==
8502 01:00:28.222921 RX Vref Scan: 0
8503 01:00:28.223337
8504 01:00:28.223664 RX Vref 0 -> 0, step: 1
8505 01:00:28.223976
8506 01:00:28.226770 RX Delay 0 -> 252, step: 8
8507 01:00:28.229816 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8508 01:00:28.236545 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8509 01:00:28.239802 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8510 01:00:28.243626 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8511 01:00:28.246574 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8512 01:00:28.249630 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8513 01:00:28.255933 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8514 01:00:28.259535 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8515 01:00:28.262458 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8516 01:00:28.266037 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8517 01:00:28.269375 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8518 01:00:28.275779 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8519 01:00:28.279076 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8520 01:00:28.282227 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8521 01:00:28.285599 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8522 01:00:28.292380 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8523 01:00:28.292894 ==
8524 01:00:28.295654 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 01:00:28.299002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 01:00:28.299575 ==
8527 01:00:28.299932 DQS Delay:
8528 01:00:28.302283 DQS0 = 0, DQS1 = 0
8529 01:00:28.302652 DQM Delay:
8530 01:00:28.305814 DQM0 = 137, DQM1 = 128
8531 01:00:28.306406 DQ Delay:
8532 01:00:28.308752 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8533 01:00:28.312228 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8534 01:00:28.315272 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8535 01:00:28.318682 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8536 01:00:28.319212
8537 01:00:28.319595
8538 01:00:28.321886 ==
8539 01:00:28.325242 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 01:00:28.328458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 01:00:28.328904 ==
8542 01:00:28.329239
8543 01:00:28.329544
8544 01:00:28.331967 TX Vref Scan disable
8545 01:00:28.332419 == TX Byte 0 ==
8546 01:00:28.338526 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8547 01:00:28.342009 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8548 01:00:28.342569 == TX Byte 1 ==
8549 01:00:28.348194 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8550 01:00:28.351778 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8551 01:00:28.352345 ==
8552 01:00:28.354882 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 01:00:28.358448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 01:00:28.358979 ==
8555 01:00:28.372017
8556 01:00:28.375438 TX Vref early break, caculate TX vref
8557 01:00:28.378550 TX Vref=16, minBit 5, minWin=21, winSum=373
8558 01:00:28.381979 TX Vref=18, minBit 5, minWin=21, winSum=380
8559 01:00:28.384923 TX Vref=20, minBit 0, minWin=22, winSum=392
8560 01:00:28.388470 TX Vref=22, minBit 5, minWin=23, winSum=403
8561 01:00:28.391629 TX Vref=24, minBit 0, minWin=24, winSum=411
8562 01:00:28.398414 TX Vref=26, minBit 0, minWin=24, winSum=415
8563 01:00:28.401493 TX Vref=28, minBit 0, minWin=24, winSum=417
8564 01:00:28.404889 TX Vref=30, minBit 0, minWin=24, winSum=409
8565 01:00:28.408198 TX Vref=32, minBit 0, minWin=23, winSum=404
8566 01:00:28.411342 TX Vref=34, minBit 0, minWin=23, winSum=392
8567 01:00:28.418196 [TxChooseVref] Worse bit 0, Min win 24, Win sum 417, Final Vref 28
8568 01:00:28.418711
8569 01:00:28.421138 Final TX Range 0 Vref 28
8570 01:00:28.421557
8571 01:00:28.421888 ==
8572 01:00:28.424464 Dram Type= 6, Freq= 0, CH_1, rank 0
8573 01:00:28.428099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8574 01:00:28.428527 ==
8575 01:00:28.428930
8576 01:00:28.429321
8577 01:00:28.430899 TX Vref Scan disable
8578 01:00:28.437821 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8579 01:00:28.438373 == TX Byte 0 ==
8580 01:00:28.441467 u2DelayCellOfst[0]=18 cells (5 PI)
8581 01:00:28.444028 u2DelayCellOfst[1]=11 cells (3 PI)
8582 01:00:28.447789 u2DelayCellOfst[2]=0 cells (0 PI)
8583 01:00:28.451057 u2DelayCellOfst[3]=3 cells (1 PI)
8584 01:00:28.454133 u2DelayCellOfst[4]=7 cells (2 PI)
8585 01:00:28.457530 u2DelayCellOfst[5]=18 cells (5 PI)
8586 01:00:28.460750 u2DelayCellOfst[6]=18 cells (5 PI)
8587 01:00:28.463917 u2DelayCellOfst[7]=3 cells (1 PI)
8588 01:00:28.467288 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8589 01:00:28.470787 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8590 01:00:28.473946 == TX Byte 1 ==
8591 01:00:28.477552 u2DelayCellOfst[8]=0 cells (0 PI)
8592 01:00:28.480193 u2DelayCellOfst[9]=3 cells (1 PI)
8593 01:00:28.480613 u2DelayCellOfst[10]=11 cells (3 PI)
8594 01:00:28.483678 u2DelayCellOfst[11]=3 cells (1 PI)
8595 01:00:28.487232 u2DelayCellOfst[12]=15 cells (4 PI)
8596 01:00:28.490247 u2DelayCellOfst[13]=18 cells (5 PI)
8597 01:00:28.493923 u2DelayCellOfst[14]=22 cells (6 PI)
8598 01:00:28.496979 u2DelayCellOfst[15]=18 cells (5 PI)
8599 01:00:28.503431 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8600 01:00:28.506980 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8601 01:00:28.507395 DramC Write-DBI on
8602 01:00:28.510143 ==
8603 01:00:28.510598 Dram Type= 6, Freq= 0, CH_1, rank 0
8604 01:00:28.516639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8605 01:00:28.517078 ==
8606 01:00:28.517414
8607 01:00:28.517728
8608 01:00:28.519839 TX Vref Scan disable
8609 01:00:28.520374 == TX Byte 0 ==
8610 01:00:28.526438 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8611 01:00:28.526860 == TX Byte 1 ==
8612 01:00:28.529622 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8613 01:00:28.533172 DramC Write-DBI off
8614 01:00:28.533587
8615 01:00:28.533918 [DATLAT]
8616 01:00:28.536832 Freq=1600, CH1 RK0
8617 01:00:28.537349
8618 01:00:28.537682 DATLAT Default: 0xf
8619 01:00:28.539617 0, 0xFFFF, sum = 0
8620 01:00:28.540040 1, 0xFFFF, sum = 0
8621 01:00:28.542869 2, 0xFFFF, sum = 0
8622 01:00:28.543293 3, 0xFFFF, sum = 0
8623 01:00:28.546417 4, 0xFFFF, sum = 0
8624 01:00:28.546841 5, 0xFFFF, sum = 0
8625 01:00:28.549680 6, 0xFFFF, sum = 0
8626 01:00:28.550238 7, 0xFFFF, sum = 0
8627 01:00:28.552908 8, 0xFFFF, sum = 0
8628 01:00:28.556096 9, 0xFFFF, sum = 0
8629 01:00:28.556566 10, 0xFFFF, sum = 0
8630 01:00:28.559809 11, 0xFFFF, sum = 0
8631 01:00:28.560230 12, 0xFFFF, sum = 0
8632 01:00:28.563069 13, 0xFFFF, sum = 0
8633 01:00:28.563599 14, 0x0, sum = 1
8634 01:00:28.566190 15, 0x0, sum = 2
8635 01:00:28.566721 16, 0x0, sum = 3
8636 01:00:28.569708 17, 0x0, sum = 4
8637 01:00:28.570293 best_step = 15
8638 01:00:28.570643
8639 01:00:28.570955 ==
8640 01:00:28.572815 Dram Type= 6, Freq= 0, CH_1, rank 0
8641 01:00:28.575959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8642 01:00:28.576390 ==
8643 01:00:28.579513 RX Vref Scan: 1
8644 01:00:28.579928
8645 01:00:28.582372 Set Vref Range= 24 -> 127
8646 01:00:28.582790
8647 01:00:28.583122 RX Vref 24 -> 127, step: 1
8648 01:00:28.586041
8649 01:00:28.586510 RX Delay 11 -> 252, step: 4
8650 01:00:28.586846
8651 01:00:28.589122 Set Vref, RX VrefLevel [Byte0]: 24
8652 01:00:28.592551 [Byte1]: 24
8653 01:00:28.596227
8654 01:00:28.596646 Set Vref, RX VrefLevel [Byte0]: 25
8655 01:00:28.599561 [Byte1]: 25
8656 01:00:28.603818
8657 01:00:28.604286 Set Vref, RX VrefLevel [Byte0]: 26
8658 01:00:28.606996 [Byte1]: 26
8659 01:00:28.611678
8660 01:00:28.612097 Set Vref, RX VrefLevel [Byte0]: 27
8661 01:00:28.614818 [Byte1]: 27
8662 01:00:28.619008
8663 01:00:28.619421 Set Vref, RX VrefLevel [Byte0]: 28
8664 01:00:28.622474 [Byte1]: 28
8665 01:00:28.626384
8666 01:00:28.626800 Set Vref, RX VrefLevel [Byte0]: 29
8667 01:00:28.629855 [Byte1]: 29
8668 01:00:28.634601
8669 01:00:28.635014 Set Vref, RX VrefLevel [Byte0]: 30
8670 01:00:28.637511 [Byte1]: 30
8671 01:00:28.642066
8672 01:00:28.642641 Set Vref, RX VrefLevel [Byte0]: 31
8673 01:00:28.645477 [Byte1]: 31
8674 01:00:28.649431
8675 01:00:28.650018 Set Vref, RX VrefLevel [Byte0]: 32
8676 01:00:28.653056 [Byte1]: 32
8677 01:00:28.657387
8678 01:00:28.657903 Set Vref, RX VrefLevel [Byte0]: 33
8679 01:00:28.660653 [Byte1]: 33
8680 01:00:28.664702
8681 01:00:28.665143 Set Vref, RX VrefLevel [Byte0]: 34
8682 01:00:28.667844 [Byte1]: 34
8683 01:00:28.672323
8684 01:00:28.672740 Set Vref, RX VrefLevel [Byte0]: 35
8685 01:00:28.675404 [Byte1]: 35
8686 01:00:28.680286
8687 01:00:28.680809 Set Vref, RX VrefLevel [Byte0]: 36
8688 01:00:28.683278 [Byte1]: 36
8689 01:00:28.687496
8690 01:00:28.687986 Set Vref, RX VrefLevel [Byte0]: 37
8691 01:00:28.690663 [Byte1]: 37
8692 01:00:28.695480
8693 01:00:28.696009 Set Vref, RX VrefLevel [Byte0]: 38
8694 01:00:28.698285 [Byte1]: 38
8695 01:00:28.702681
8696 01:00:28.703194 Set Vref, RX VrefLevel [Byte0]: 39
8697 01:00:28.706104 [Byte1]: 39
8698 01:00:28.710314
8699 01:00:28.710863 Set Vref, RX VrefLevel [Byte0]: 40
8700 01:00:28.713647 [Byte1]: 40
8701 01:00:28.717780
8702 01:00:28.718226 Set Vref, RX VrefLevel [Byte0]: 41
8703 01:00:28.721368 [Byte1]: 41
8704 01:00:28.725813
8705 01:00:28.726402 Set Vref, RX VrefLevel [Byte0]: 42
8706 01:00:28.728845 [Byte1]: 42
8707 01:00:28.733109
8708 01:00:28.733665 Set Vref, RX VrefLevel [Byte0]: 43
8709 01:00:28.736546 [Byte1]: 43
8710 01:00:28.740881
8711 01:00:28.741475 Set Vref, RX VrefLevel [Byte0]: 44
8712 01:00:28.743929 [Byte1]: 44
8713 01:00:28.748629
8714 01:00:28.749176 Set Vref, RX VrefLevel [Byte0]: 45
8715 01:00:28.751770 [Byte1]: 45
8716 01:00:28.756125
8717 01:00:28.756694 Set Vref, RX VrefLevel [Byte0]: 46
8718 01:00:28.759660 [Byte1]: 46
8719 01:00:28.763485
8720 01:00:28.763943 Set Vref, RX VrefLevel [Byte0]: 47
8721 01:00:28.767520 [Byte1]: 47
8722 01:00:28.771402
8723 01:00:28.771953 Set Vref, RX VrefLevel [Byte0]: 48
8724 01:00:28.774443 [Byte1]: 48
8725 01:00:28.778826
8726 01:00:28.779285 Set Vref, RX VrefLevel [Byte0]: 49
8727 01:00:28.782304 [Byte1]: 49
8728 01:00:28.786330
8729 01:00:28.786790 Set Vref, RX VrefLevel [Byte0]: 50
8730 01:00:28.789644 [Byte1]: 50
8731 01:00:28.794313
8732 01:00:28.794864 Set Vref, RX VrefLevel [Byte0]: 51
8733 01:00:28.797082 [Byte1]: 51
8734 01:00:28.801917
8735 01:00:28.802531 Set Vref, RX VrefLevel [Byte0]: 52
8736 01:00:28.804881 [Byte1]: 52
8737 01:00:28.809699
8738 01:00:28.810317 Set Vref, RX VrefLevel [Byte0]: 53
8739 01:00:28.812615 [Byte1]: 53
8740 01:00:28.817104
8741 01:00:28.817720 Set Vref, RX VrefLevel [Byte0]: 54
8742 01:00:28.820601 [Byte1]: 54
8743 01:00:28.824842
8744 01:00:28.825326 Set Vref, RX VrefLevel [Byte0]: 55
8745 01:00:28.827705 [Byte1]: 55
8746 01:00:28.831982
8747 01:00:28.832437 Set Vref, RX VrefLevel [Byte0]: 56
8748 01:00:28.838620 [Byte1]: 56
8749 01:00:28.839162
8750 01:00:28.841665 Set Vref, RX VrefLevel [Byte0]: 57
8751 01:00:28.844832 [Byte1]: 57
8752 01:00:28.845412
8753 01:00:28.848435 Set Vref, RX VrefLevel [Byte0]: 58
8754 01:00:28.851566 [Byte1]: 58
8755 01:00:28.854985
8756 01:00:28.855444 Set Vref, RX VrefLevel [Byte0]: 59
8757 01:00:28.858345 [Byte1]: 59
8758 01:00:28.862710
8759 01:00:28.863169 Set Vref, RX VrefLevel [Byte0]: 60
8760 01:00:28.865600 [Byte1]: 60
8761 01:00:28.870346
8762 01:00:28.870820 Set Vref, RX VrefLevel [Byte0]: 61
8763 01:00:28.873313 [Byte1]: 61
8764 01:00:28.877713
8765 01:00:28.878132 Set Vref, RX VrefLevel [Byte0]: 62
8766 01:00:28.880889 [Byte1]: 62
8767 01:00:28.885278
8768 01:00:28.885875 Set Vref, RX VrefLevel [Byte0]: 63
8769 01:00:28.888464 [Byte1]: 63
8770 01:00:28.892996
8771 01:00:28.893428 Set Vref, RX VrefLevel [Byte0]: 64
8772 01:00:28.896193 [Byte1]: 64
8773 01:00:28.900592
8774 01:00:28.901006 Set Vref, RX VrefLevel [Byte0]: 65
8775 01:00:28.904250 [Byte1]: 65
8776 01:00:28.908324
8777 01:00:28.908835 Set Vref, RX VrefLevel [Byte0]: 66
8778 01:00:28.911459 [Byte1]: 66
8779 01:00:28.915859
8780 01:00:28.916274 Set Vref, RX VrefLevel [Byte0]: 67
8781 01:00:28.919106 [Byte1]: 67
8782 01:00:28.923790
8783 01:00:28.924320 Set Vref, RX VrefLevel [Byte0]: 68
8784 01:00:28.927168 [Byte1]: 68
8785 01:00:28.930908
8786 01:00:28.931328 Set Vref, RX VrefLevel [Byte0]: 69
8787 01:00:28.937320 [Byte1]: 69
8788 01:00:28.937918
8789 01:00:28.940998 Set Vref, RX VrefLevel [Byte0]: 70
8790 01:00:28.944006 [Byte1]: 70
8791 01:00:28.944443
8792 01:00:28.947442 Set Vref, RX VrefLevel [Byte0]: 71
8793 01:00:28.950799 [Byte1]: 71
8794 01:00:28.954089
8795 01:00:28.954547 Set Vref, RX VrefLevel [Byte0]: 72
8796 01:00:28.957048 [Byte1]: 72
8797 01:00:28.961657
8798 01:00:28.962245 Set Vref, RX VrefLevel [Byte0]: 73
8799 01:00:28.964987 [Byte1]: 73
8800 01:00:28.969362
8801 01:00:28.969781 Set Vref, RX VrefLevel [Byte0]: 74
8802 01:00:28.972505 [Byte1]: 74
8803 01:00:28.976725
8804 01:00:28.977160 Set Vref, RX VrefLevel [Byte0]: 75
8805 01:00:28.980288 [Byte1]: 75
8806 01:00:28.984294
8807 01:00:28.984709 Final RX Vref Byte 0 = 53 to rank0
8808 01:00:28.987809 Final RX Vref Byte 1 = 61 to rank0
8809 01:00:28.991331 Final RX Vref Byte 0 = 53 to rank1
8810 01:00:28.994239 Final RX Vref Byte 1 = 61 to rank1==
8811 01:00:28.997616 Dram Type= 6, Freq= 0, CH_1, rank 0
8812 01:00:29.004433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 01:00:29.004950 ==
8814 01:00:29.005285 DQS Delay:
8815 01:00:29.007538 DQS0 = 0, DQS1 = 0
8816 01:00:29.008104 DQM Delay:
8817 01:00:29.008456 DQM0 = 133, DQM1 = 127
8818 01:00:29.010592 DQ Delay:
8819 01:00:29.014328 DQ0 =140, DQ1 =126, DQ2 =124, DQ3 =130
8820 01:00:29.017412 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8821 01:00:29.020276 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8822 01:00:29.024123 DQ12 =136, DQ13 =134, DQ14 =136, DQ15 =138
8823 01:00:29.024539
8824 01:00:29.024870
8825 01:00:29.025177
8826 01:00:29.026893 [DramC_TX_OE_Calibration] TA2
8827 01:00:29.030760 Original DQ_B0 (3 6) =30, OEN = 27
8828 01:00:29.033777 Original DQ_B1 (3 6) =30, OEN = 27
8829 01:00:29.036913 24, 0x0, End_B0=24 End_B1=24
8830 01:00:29.040380 25, 0x0, End_B0=25 End_B1=25
8831 01:00:29.040901 26, 0x0, End_B0=26 End_B1=26
8832 01:00:29.043700 27, 0x0, End_B0=27 End_B1=27
8833 01:00:29.047121 28, 0x0, End_B0=28 End_B1=28
8834 01:00:29.050663 29, 0x0, End_B0=29 End_B1=29
8835 01:00:29.051188 30, 0x0, End_B0=30 End_B1=30
8836 01:00:29.053328 31, 0x4141, End_B0=30 End_B1=30
8837 01:00:29.056503 Byte0 end_step=30 best_step=27
8838 01:00:29.060181 Byte1 end_step=30 best_step=27
8839 01:00:29.063407 Byte0 TX OE(2T, 0.5T) = (3, 3)
8840 01:00:29.066706 Byte1 TX OE(2T, 0.5T) = (3, 3)
8841 01:00:29.067123
8842 01:00:29.067455
8843 01:00:29.073147 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8844 01:00:29.076547 CH1 RK0: MR19=303, MR18=180E
8845 01:00:29.083285 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8846 01:00:29.083756
8847 01:00:29.086562 ----->DramcWriteLeveling(PI) begin...
8848 01:00:29.087024 ==
8849 01:00:29.089673 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 01:00:29.093038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 01:00:29.093609 ==
8852 01:00:29.096610 Write leveling (Byte 0): 25 => 25
8853 01:00:29.099775 Write leveling (Byte 1): 27 => 27
8854 01:00:29.102568 DramcWriteLeveling(PI) end<-----
8855 01:00:29.103027
8856 01:00:29.103389 ==
8857 01:00:29.105765 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 01:00:29.112443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 01:00:29.112928 ==
8860 01:00:29.113297 [Gating] SW mode calibration
8861 01:00:29.122609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8862 01:00:29.125941 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8863 01:00:29.133181 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 01:00:29.135886 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 01:00:29.139113 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 01:00:29.145598 1 4 12 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8867 01:00:29.148833 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8868 01:00:29.152010 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8869 01:00:29.158716 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8870 01:00:29.162126 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8871 01:00:29.165189 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8872 01:00:29.171906 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8873 01:00:29.175483 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8874 01:00:29.178319 1 5 12 | B1->B0 | 2b2b 3434 | 0 1 | (1 0) (1 0)
8875 01:00:29.185267 1 5 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8876 01:00:29.188208 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 01:00:29.192359 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 01:00:29.198146 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8879 01:00:29.201142 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8880 01:00:29.205069 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8881 01:00:29.211701 1 6 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8882 01:00:29.215015 1 6 12 | B1->B0 | 4545 2626 | 0 0 | (0 0) (0 0)
8883 01:00:29.218379 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8884 01:00:29.224921 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 01:00:29.227708 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8886 01:00:29.231345 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 01:00:29.237685 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8888 01:00:29.241394 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 01:00:29.244300 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 01:00:29.251472 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8891 01:00:29.254790 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 01:00:29.257925 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 01:00:29.264105 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 01:00:29.267588 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 01:00:29.270832 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 01:00:29.277892 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 01:00:29.280808 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 01:00:29.284261 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 01:00:29.290485 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 01:00:29.294054 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 01:00:29.296901 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 01:00:29.303433 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 01:00:29.306768 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 01:00:29.310418 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 01:00:29.316486 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8906 01:00:29.320079 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8907 01:00:29.323836 Total UI for P1: 0, mck2ui 16
8908 01:00:29.326685 best dqsien dly found for B1: ( 1, 9, 8)
8909 01:00:29.330051 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8910 01:00:29.336901 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8911 01:00:29.337515 Total UI for P1: 0, mck2ui 16
8912 01:00:29.343071 best dqsien dly found for B0: ( 1, 9, 14)
8913 01:00:29.346592 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8914 01:00:29.349929 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8915 01:00:29.350494
8916 01:00:29.352977 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8917 01:00:29.356412 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8918 01:00:29.359728 [Gating] SW calibration Done
8919 01:00:29.360275 ==
8920 01:00:29.363094 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 01:00:29.366359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 01:00:29.366821 ==
8923 01:00:29.370053 RX Vref Scan: 0
8924 01:00:29.370673
8925 01:00:29.371044 RX Vref 0 -> 0, step: 1
8926 01:00:29.371386
8927 01:00:29.373022 RX Delay 0 -> 252, step: 8
8928 01:00:29.376211 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8929 01:00:29.382865 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8930 01:00:29.385769 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8931 01:00:29.389879 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8932 01:00:29.392813 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8933 01:00:29.395891 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8934 01:00:29.402439 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8935 01:00:29.406029 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8936 01:00:29.409568 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8937 01:00:29.412689 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8938 01:00:29.415610 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8939 01:00:29.422107 iDelay=208, Bit 11, Center 119 (56 ~ 183) 128
8940 01:00:29.425503 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8941 01:00:29.428902 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8942 01:00:29.431818 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8943 01:00:29.438921 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8944 01:00:29.439479 ==
8945 01:00:29.442795 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 01:00:29.445475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 01:00:29.445937 ==
8948 01:00:29.446356 DQS Delay:
8949 01:00:29.449333 DQS0 = 0, DQS1 = 0
8950 01:00:29.449889 DQM Delay:
8951 01:00:29.451784 DQM0 = 136, DQM1 = 128
8952 01:00:29.452240 DQ Delay:
8953 01:00:29.455466 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8954 01:00:29.458394 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8955 01:00:29.461814 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8956 01:00:29.465214 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8957 01:00:29.465843
8958 01:00:29.468897
8959 01:00:29.469478 ==
8960 01:00:29.471874 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 01:00:29.474902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 01:00:29.475359 ==
8963 01:00:29.475723
8964 01:00:29.476059
8965 01:00:29.478469 TX Vref Scan disable
8966 01:00:29.479158 == TX Byte 0 ==
8967 01:00:29.485042 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8968 01:00:29.488598 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8969 01:00:29.489152 == TX Byte 1 ==
8970 01:00:29.494702 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8971 01:00:29.498281 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8972 01:00:29.498905 ==
8973 01:00:29.501522 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 01:00:29.505072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 01:00:29.505651 ==
8976 01:00:29.518322
8977 01:00:29.521742 TX Vref early break, caculate TX vref
8978 01:00:29.524548 TX Vref=16, minBit 1, minWin=23, winSum=389
8979 01:00:29.527977 TX Vref=18, minBit 1, minWin=24, winSum=400
8980 01:00:29.531164 TX Vref=20, minBit 8, minWin=24, winSum=407
8981 01:00:29.534871 TX Vref=22, minBit 1, minWin=25, winSum=416
8982 01:00:29.538418 TX Vref=24, minBit 5, minWin=25, winSum=420
8983 01:00:29.544340 TX Vref=26, minBit 0, minWin=26, winSum=431
8984 01:00:29.547660 TX Vref=28, minBit 0, minWin=26, winSum=431
8985 01:00:29.550984 TX Vref=30, minBit 0, minWin=25, winSum=420
8986 01:00:29.554488 TX Vref=32, minBit 0, minWin=24, winSum=412
8987 01:00:29.558107 TX Vref=34, minBit 0, minWin=24, winSum=403
8988 01:00:29.564614 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 26
8989 01:00:29.565236
8990 01:00:29.567816 Final TX Range 0 Vref 26
8991 01:00:29.568389
8992 01:00:29.568758 ==
8993 01:00:29.571392 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 01:00:29.574054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 01:00:29.574651 ==
8996 01:00:29.575028
8997 01:00:29.575402
8998 01:00:29.577815 TX Vref Scan disable
8999 01:00:29.583886 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
9000 01:00:29.584356 == TX Byte 0 ==
9001 01:00:29.587303 u2DelayCellOfst[0]=22 cells (6 PI)
9002 01:00:29.590293 u2DelayCellOfst[1]=15 cells (4 PI)
9003 01:00:29.593874 u2DelayCellOfst[2]=0 cells (0 PI)
9004 01:00:29.597162 u2DelayCellOfst[3]=7 cells (2 PI)
9005 01:00:29.600245 u2DelayCellOfst[4]=11 cells (3 PI)
9006 01:00:29.603665 u2DelayCellOfst[5]=22 cells (6 PI)
9007 01:00:29.607163 u2DelayCellOfst[6]=22 cells (6 PI)
9008 01:00:29.610565 u2DelayCellOfst[7]=7 cells (2 PI)
9009 01:00:29.613517 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9010 01:00:29.616954 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9011 01:00:29.620528 == TX Byte 1 ==
9012 01:00:29.623900 u2DelayCellOfst[8]=0 cells (0 PI)
9013 01:00:29.626957 u2DelayCellOfst[9]=7 cells (2 PI)
9014 01:00:29.630044 u2DelayCellOfst[10]=15 cells (4 PI)
9015 01:00:29.630501 u2DelayCellOfst[11]=7 cells (2 PI)
9016 01:00:29.633671 u2DelayCellOfst[12]=15 cells (4 PI)
9017 01:00:29.636838 u2DelayCellOfst[13]=18 cells (5 PI)
9018 01:00:29.640235 u2DelayCellOfst[14]=22 cells (6 PI)
9019 01:00:29.643595 u2DelayCellOfst[15]=18 cells (5 PI)
9020 01:00:29.650343 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9021 01:00:29.653717 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9022 01:00:29.654380 DramC Write-DBI on
9023 01:00:29.656285 ==
9024 01:00:29.659783 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 01:00:29.662937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 01:00:29.663406 ==
9027 01:00:29.663778
9028 01:00:29.664116
9029 01:00:29.666330 TX Vref Scan disable
9030 01:00:29.666909 == TX Byte 0 ==
9031 01:00:29.673035 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9032 01:00:29.673594 == TX Byte 1 ==
9033 01:00:29.676332 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9034 01:00:29.679649 DramC Write-DBI off
9035 01:00:29.680122
9036 01:00:29.680491 [DATLAT]
9037 01:00:29.682878 Freq=1600, CH1 RK1
9038 01:00:29.683343
9039 01:00:29.683707 DATLAT Default: 0xf
9040 01:00:29.686110 0, 0xFFFF, sum = 0
9041 01:00:29.686628 1, 0xFFFF, sum = 0
9042 01:00:29.689377 2, 0xFFFF, sum = 0
9043 01:00:29.689947 3, 0xFFFF, sum = 0
9044 01:00:29.692805 4, 0xFFFF, sum = 0
9045 01:00:29.693402 5, 0xFFFF, sum = 0
9046 01:00:29.696199 6, 0xFFFF, sum = 0
9047 01:00:29.699322 7, 0xFFFF, sum = 0
9048 01:00:29.699791 8, 0xFFFF, sum = 0
9049 01:00:29.702797 9, 0xFFFF, sum = 0
9050 01:00:29.703265 10, 0xFFFF, sum = 0
9051 01:00:29.705602 11, 0xFFFF, sum = 0
9052 01:00:29.706071 12, 0xFFFF, sum = 0
9053 01:00:29.709532 13, 0xFFFF, sum = 0
9054 01:00:29.710108 14, 0x0, sum = 1
9055 01:00:29.712304 15, 0x0, sum = 2
9056 01:00:29.712779 16, 0x0, sum = 3
9057 01:00:29.715852 17, 0x0, sum = 4
9058 01:00:29.716321 best_step = 15
9059 01:00:29.716785
9060 01:00:29.717143 ==
9061 01:00:29.718859 Dram Type= 6, Freq= 0, CH_1, rank 1
9062 01:00:29.725218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9063 01:00:29.725773 ==
9064 01:00:29.726143 RX Vref Scan: 0
9065 01:00:29.726529
9066 01:00:29.728849 RX Vref 0 -> 0, step: 1
9067 01:00:29.729311
9068 01:00:29.731895 RX Delay 11 -> 252, step: 4
9069 01:00:29.735262 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9070 01:00:29.738796 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9071 01:00:29.742156 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9072 01:00:29.748426 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9073 01:00:29.751677 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9074 01:00:29.755193 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9075 01:00:29.758540 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9076 01:00:29.762486 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9077 01:00:29.768342 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9078 01:00:29.772023 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9079 01:00:29.774738 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9080 01:00:29.778157 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9081 01:00:29.785291 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9082 01:00:29.787872 iDelay=203, Bit 13, Center 132 (79 ~ 186) 108
9083 01:00:29.791419 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9084 01:00:29.794543 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9085 01:00:29.795010 ==
9086 01:00:29.797932 Dram Type= 6, Freq= 0, CH_1, rank 1
9087 01:00:29.804969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9088 01:00:29.805530 ==
9089 01:00:29.805902 DQS Delay:
9090 01:00:29.807956 DQS0 = 0, DQS1 = 0
9091 01:00:29.808517 DQM Delay:
9092 01:00:29.808890 DQM0 = 133, DQM1 = 126
9093 01:00:29.811181 DQ Delay:
9094 01:00:29.814503 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9095 01:00:29.817750 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9096 01:00:29.820937 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9097 01:00:29.824885 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =138
9098 01:00:29.825452
9099 01:00:29.825826
9100 01:00:29.826189
9101 01:00:29.827718 [DramC_TX_OE_Calibration] TA2
9102 01:00:29.831012 Original DQ_B0 (3 6) =30, OEN = 27
9103 01:00:29.834580 Original DQ_B1 (3 6) =30, OEN = 27
9104 01:00:29.838020 24, 0x0, End_B0=24 End_B1=24
9105 01:00:29.838721 25, 0x0, End_B0=25 End_B1=25
9106 01:00:29.841023 26, 0x0, End_B0=26 End_B1=26
9107 01:00:29.843903 27, 0x0, End_B0=27 End_B1=27
9108 01:00:29.847332 28, 0x0, End_B0=28 End_B1=28
9109 01:00:29.850792 29, 0x0, End_B0=29 End_B1=29
9110 01:00:29.851369 30, 0x0, End_B0=30 End_B1=30
9111 01:00:29.854033 31, 0x4545, End_B0=30 End_B1=30
9112 01:00:29.857297 Byte0 end_step=30 best_step=27
9113 01:00:29.860510 Byte1 end_step=30 best_step=27
9114 01:00:29.864099 Byte0 TX OE(2T, 0.5T) = (3, 3)
9115 01:00:29.867312 Byte1 TX OE(2T, 0.5T) = (3, 3)
9116 01:00:29.867776
9117 01:00:29.868147
9118 01:00:29.874051 [DQSOSCAuto] RK1, (LSB)MR18= 0xb08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
9119 01:00:29.877088 CH1 RK1: MR19=303, MR18=B08
9120 01:00:29.883740 CH1_RK1: MR19=0x303, MR18=0xB08, DQSOSC=404, MR23=63, INC=22, DEC=15
9121 01:00:29.886970 [RxdqsGatingPostProcess] freq 1600
9122 01:00:29.890020 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9123 01:00:29.893593 best DQS0 dly(2T, 0.5T) = (1, 1)
9124 01:00:29.897002 best DQS1 dly(2T, 0.5T) = (1, 1)
9125 01:00:29.900265 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9126 01:00:29.903859 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9127 01:00:29.906755 best DQS0 dly(2T, 0.5T) = (1, 1)
9128 01:00:29.909991 best DQS1 dly(2T, 0.5T) = (1, 1)
9129 01:00:29.913605 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9130 01:00:29.916562 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9131 01:00:29.919936 Pre-setting of DQS Precalculation
9132 01:00:29.923027 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9133 01:00:29.933312 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9134 01:00:29.939957 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9135 01:00:29.940519
9136 01:00:29.940894
9137 01:00:29.942848 [Calibration Summary] 3200 Mbps
9138 01:00:29.943310 CH 0, Rank 0
9139 01:00:29.946498 SW Impedance : PASS
9140 01:00:29.947137 DUTY Scan : NO K
9141 01:00:29.949694 ZQ Calibration : PASS
9142 01:00:29.953092 Jitter Meter : NO K
9143 01:00:29.953553 CBT Training : PASS
9144 01:00:29.956528 Write leveling : PASS
9145 01:00:29.959859 RX DQS gating : PASS
9146 01:00:29.960423 RX DQ/DQS(RDDQC) : PASS
9147 01:00:29.963050 TX DQ/DQS : PASS
9148 01:00:29.966350 RX DATLAT : PASS
9149 01:00:29.966940 RX DQ/DQS(Engine): PASS
9150 01:00:29.969255 TX OE : PASS
9151 01:00:29.969722 All Pass.
9152 01:00:29.970088
9153 01:00:29.972765 CH 0, Rank 1
9154 01:00:29.973225 SW Impedance : PASS
9155 01:00:29.976031 DUTY Scan : NO K
9156 01:00:29.979138 ZQ Calibration : PASS
9157 01:00:29.979602 Jitter Meter : NO K
9158 01:00:29.982623 CBT Training : PASS
9159 01:00:29.983084 Write leveling : PASS
9160 01:00:29.985598 RX DQS gating : PASS
9161 01:00:29.989597 RX DQ/DQS(RDDQC) : PASS
9162 01:00:29.990193 TX DQ/DQS : PASS
9163 01:00:29.992349 RX DATLAT : PASS
9164 01:00:29.995716 RX DQ/DQS(Engine): PASS
9165 01:00:29.996280 TX OE : PASS
9166 01:00:29.998923 All Pass.
9167 01:00:29.999388
9168 01:00:29.999758 CH 1, Rank 0
9169 01:00:30.002349 SW Impedance : PASS
9170 01:00:30.002815 DUTY Scan : NO K
9171 01:00:30.005802 ZQ Calibration : PASS
9172 01:00:30.008962 Jitter Meter : NO K
9173 01:00:30.009518 CBT Training : PASS
9174 01:00:30.011931 Write leveling : PASS
9175 01:00:30.015319 RX DQS gating : PASS
9176 01:00:30.015784 RX DQ/DQS(RDDQC) : PASS
9177 01:00:30.018479 TX DQ/DQS : PASS
9178 01:00:30.022122 RX DATLAT : PASS
9179 01:00:30.022703 RX DQ/DQS(Engine): PASS
9180 01:00:30.025329 TX OE : PASS
9181 01:00:30.025751 All Pass.
9182 01:00:30.026083
9183 01:00:30.028600 CH 1, Rank 1
9184 01:00:30.029018 SW Impedance : PASS
9185 01:00:30.031751 DUTY Scan : NO K
9186 01:00:30.035008 ZQ Calibration : PASS
9187 01:00:30.035430 Jitter Meter : NO K
9188 01:00:30.038673 CBT Training : PASS
9189 01:00:30.041836 Write leveling : PASS
9190 01:00:30.042400 RX DQS gating : PASS
9191 01:00:30.044796 RX DQ/DQS(RDDQC) : PASS
9192 01:00:30.048167 TX DQ/DQS : PASS
9193 01:00:30.048609 RX DATLAT : PASS
9194 01:00:30.051630 RX DQ/DQS(Engine): PASS
9195 01:00:30.054808 TX OE : PASS
9196 01:00:30.055231 All Pass.
9197 01:00:30.055645
9198 01:00:30.055964 DramC Write-DBI on
9199 01:00:30.058298 PER_BANK_REFRESH: Hybrid Mode
9200 01:00:30.061287 TX_TRACKING: ON
9201 01:00:30.068143 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9202 01:00:30.078141 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9203 01:00:30.084538 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9204 01:00:30.088246 [FAST_K] Save calibration result to emmc
9205 01:00:30.090983 sync common calibartion params.
9206 01:00:30.094457 sync cbt_mode0:1, 1:1
9207 01:00:30.094917 dram_init: ddr_geometry: 2
9208 01:00:30.097526 dram_init: ddr_geometry: 2
9209 01:00:30.100858 dram_init: ddr_geometry: 2
9210 01:00:30.104516 0:dram_rank_size:100000000
9211 01:00:30.105096 1:dram_rank_size:100000000
9212 01:00:30.111318 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9213 01:00:30.113973 DFS_SHUFFLE_HW_MODE: ON
9214 01:00:30.117171 dramc_set_vcore_voltage set vcore to 725000
9215 01:00:30.117705 Read voltage for 1600, 0
9216 01:00:30.120606 Vio18 = 0
9217 01:00:30.121068 Vcore = 725000
9218 01:00:30.121436 Vdram = 0
9219 01:00:30.124211 Vddq = 0
9220 01:00:30.124632 Vmddr = 0
9221 01:00:30.126989 switch to 3200 Mbps bootup
9222 01:00:30.127410 [DramcRunTimeConfig]
9223 01:00:30.130391 PHYPLL
9224 01:00:30.130831 DPM_CONTROL_AFTERK: ON
9225 01:00:30.133770 PER_BANK_REFRESH: ON
9226 01:00:30.137059 REFRESH_OVERHEAD_REDUCTION: ON
9227 01:00:30.137500 CMD_PICG_NEW_MODE: OFF
9228 01:00:30.140596 XRTWTW_NEW_MODE: ON
9229 01:00:30.141211 XRTRTR_NEW_MODE: ON
9230 01:00:30.143482 TX_TRACKING: ON
9231 01:00:30.143907 RDSEL_TRACKING: OFF
9232 01:00:30.147102 DQS Precalculation for DVFS: ON
9233 01:00:30.149983 RX_TRACKING: OFF
9234 01:00:30.150445 HW_GATING DBG: ON
9235 01:00:30.153297 ZQCS_ENABLE_LP4: ON
9236 01:00:30.153716 RX_PICG_NEW_MODE: ON
9237 01:00:30.156768 TX_PICG_NEW_MODE: ON
9238 01:00:30.157185 ENABLE_RX_DCM_DPHY: ON
9239 01:00:30.160022 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9240 01:00:30.163363 DUMMY_READ_FOR_TRACKING: OFF
9241 01:00:30.166635 !!! SPM_CONTROL_AFTERK: OFF
9242 01:00:30.170000 !!! SPM could not control APHY
9243 01:00:30.170564 IMPEDANCE_TRACKING: ON
9244 01:00:30.173352 TEMP_SENSOR: ON
9245 01:00:30.173776 HW_SAVE_FOR_SR: OFF
9246 01:00:30.176660 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9247 01:00:30.179865 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9248 01:00:30.183159 Read ODT Tracking: ON
9249 01:00:30.186707 Refresh Rate DeBounce: ON
9250 01:00:30.187122 DFS_NO_QUEUE_FLUSH: ON
9251 01:00:30.189818 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9252 01:00:30.192908 ENABLE_DFS_RUNTIME_MRW: OFF
9253 01:00:30.196666 DDR_RESERVE_NEW_MODE: ON
9254 01:00:30.197191 MR_CBT_SWITCH_FREQ: ON
9255 01:00:30.199974 =========================
9256 01:00:30.219002 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9257 01:00:30.222584 dram_init: ddr_geometry: 2
9258 01:00:30.240264 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9259 01:00:30.243585 dram_init: dram init end (result: 0)
9260 01:00:30.250035 DRAM-K: Full calibration passed in 24698 msecs
9261 01:00:30.253154 MRC: failed to locate region type 0.
9262 01:00:30.253649 DRAM rank0 size:0x100000000,
9263 01:00:30.256755 DRAM rank1 size=0x100000000
9264 01:00:30.266523 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9265 01:00:30.273320 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9266 01:00:30.282936 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9267 01:00:30.289734 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9268 01:00:30.290373 DRAM rank0 size:0x100000000,
9269 01:00:30.292928 DRAM rank1 size=0x100000000
9270 01:00:30.293464 CBMEM:
9271 01:00:30.296131 IMD: root @ 0xfffff000 254 entries.
9272 01:00:30.299569 IMD: root @ 0xffffec00 62 entries.
9273 01:00:30.306550 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9274 01:00:30.309670 WARNING: RO_VPD is uninitialized or empty.
9275 01:00:30.312386 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9276 01:00:30.320891 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9277 01:00:30.332978 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9278 01:00:30.344775 BS: romstage times (exec / console): total (unknown) / 24175 ms
9279 01:00:30.345355
9280 01:00:30.345799
9281 01:00:30.354851 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9282 01:00:30.358129 ARM64: Exception handlers installed.
9283 01:00:30.361413 ARM64: Testing exception
9284 01:00:30.364892 ARM64: Done test exception
9285 01:00:30.365450 Enumerating buses...
9286 01:00:30.367843 Show all devs... Before device enumeration.
9287 01:00:30.371558 Root Device: enabled 1
9288 01:00:30.374735 CPU_CLUSTER: 0: enabled 1
9289 01:00:30.375309 CPU: 00: enabled 1
9290 01:00:30.377767 Compare with tree...
9291 01:00:30.378267 Root Device: enabled 1
9292 01:00:30.380985 CPU_CLUSTER: 0: enabled 1
9293 01:00:30.384262 CPU: 00: enabled 1
9294 01:00:30.384727 Root Device scanning...
9295 01:00:30.387543 scan_static_bus for Root Device
9296 01:00:30.390925 CPU_CLUSTER: 0 enabled
9297 01:00:30.394228 scan_static_bus for Root Device done
9298 01:00:30.397660 scan_bus: bus Root Device finished in 8 msecs
9299 01:00:30.398126 done
9300 01:00:30.404038 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9301 01:00:30.407188 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9302 01:00:30.414406 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9303 01:00:30.417229 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9304 01:00:30.420392 Allocating resources...
9305 01:00:30.423984 Reading resources...
9306 01:00:30.427239 Root Device read_resources bus 0 link: 0
9307 01:00:30.430440 DRAM rank0 size:0x100000000,
9308 01:00:30.430861 DRAM rank1 size=0x100000000
9309 01:00:30.436792 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9310 01:00:30.437216 CPU: 00 missing read_resources
9311 01:00:30.443542 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9312 01:00:30.446581 Root Device read_resources bus 0 link: 0 done
9313 01:00:30.449869 Done reading resources.
9314 01:00:30.453590 Show resources in subtree (Root Device)...After reading.
9315 01:00:30.456659 Root Device child on link 0 CPU_CLUSTER: 0
9316 01:00:30.459781 CPU_CLUSTER: 0 child on link 0 CPU: 00
9317 01:00:30.470378 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9318 01:00:30.470938 CPU: 00
9319 01:00:30.473346 Root Device assign_resources, bus 0 link: 0
9320 01:00:30.476715 CPU_CLUSTER: 0 missing set_resources
9321 01:00:30.483022 Root Device assign_resources, bus 0 link: 0 done
9322 01:00:30.483493 Done setting resources.
9323 01:00:30.489656 Show resources in subtree (Root Device)...After assigning values.
9324 01:00:30.493150 Root Device child on link 0 CPU_CLUSTER: 0
9325 01:00:30.496256 CPU_CLUSTER: 0 child on link 0 CPU: 00
9326 01:00:30.506591 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9327 01:00:30.507059 CPU: 00
9328 01:00:30.509438 Done allocating resources.
9329 01:00:30.516674 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9330 01:00:30.517226 Enabling resources...
9331 01:00:30.519283 done.
9332 01:00:30.522458 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9333 01:00:30.525710 Initializing devices...
9334 01:00:30.526126 Root Device init
9335 01:00:30.529148 init hardware done!
9336 01:00:30.529567 0x00000018: ctrlr->caps
9337 01:00:30.532446 52.000 MHz: ctrlr->f_max
9338 01:00:30.535629 0.400 MHz: ctrlr->f_min
9339 01:00:30.536057 0x40ff8080: ctrlr->voltages
9340 01:00:30.538944 sclk: 390625
9341 01:00:30.539362 Bus Width = 1
9342 01:00:30.542148 sclk: 390625
9343 01:00:30.542607 Bus Width = 1
9344 01:00:30.545715 Early init status = 3
9345 01:00:30.549032 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9346 01:00:30.553097 in-header: 03 fc 00 00 01 00 00 00
9347 01:00:30.556353 in-data: 00
9348 01:00:30.559615 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9349 01:00:30.565571 in-header: 03 fd 00 00 00 00 00 00
9350 01:00:30.568416 in-data:
9351 01:00:30.571985 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9352 01:00:30.576712 in-header: 03 fc 00 00 01 00 00 00
9353 01:00:30.579493 in-data: 00
9354 01:00:30.583386 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9355 01:00:30.588432 in-header: 03 fd 00 00 00 00 00 00
9356 01:00:30.591832 in-data:
9357 01:00:30.595214 [SSUSB] Setting up USB HOST controller...
9358 01:00:30.598590 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9359 01:00:30.601998 [SSUSB] phy power-on done.
9360 01:00:30.605097 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9361 01:00:30.612310 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9362 01:00:30.614934 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9363 01:00:30.621639 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9364 01:00:30.627996 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9365 01:00:30.634954 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9366 01:00:30.641750 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9367 01:00:30.648087 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9368 01:00:30.651499 SPM: binary array size = 0x9dc
9369 01:00:30.654836 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9370 01:00:30.661476 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9371 01:00:30.667862 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9372 01:00:30.674450 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9373 01:00:30.677804 configure_display: Starting display init
9374 01:00:30.711827 anx7625_power_on_init: Init interface.
9375 01:00:30.715002 anx7625_disable_pd_protocol: Disabled PD feature.
9376 01:00:30.718283 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9377 01:00:30.746500 anx7625_start_dp_work: Secure OCM version=00
9378 01:00:30.749126 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9379 01:00:30.764466 sp_tx_get_edid_block: EDID Block = 1
9380 01:00:30.867042 Extracted contents:
9381 01:00:30.870630 header: 00 ff ff ff ff ff ff 00
9382 01:00:30.873728 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9383 01:00:30.877288 version: 01 04
9384 01:00:30.880344 basic params: 95 1f 11 78 0a
9385 01:00:30.883792 chroma info: 76 90 94 55 54 90 27 21 50 54
9386 01:00:30.886588 established: 00 00 00
9387 01:00:30.893507 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9388 01:00:30.896803 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9389 01:00:30.903088 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9390 01:00:30.909800 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9391 01:00:30.916328 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9392 01:00:30.919845 extensions: 00
9393 01:00:30.920327 checksum: fb
9394 01:00:30.920708
9395 01:00:30.926676 Manufacturer: IVO Model 57d Serial Number 0
9396 01:00:30.927271 Made week 0 of 2020
9397 01:00:30.929847 EDID version: 1.4
9398 01:00:30.930433 Digital display
9399 01:00:30.932836 6 bits per primary color channel
9400 01:00:30.935992 DisplayPort interface
9401 01:00:30.936563 Maximum image size: 31 cm x 17 cm
9402 01:00:30.939392 Gamma: 220%
9403 01:00:30.939857 Check DPMS levels
9404 01:00:30.945901 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9405 01:00:30.949366 First detailed timing is preferred timing
9406 01:00:30.952396 Established timings supported:
9407 01:00:30.952864 Standard timings supported:
9408 01:00:30.955649 Detailed timings
9409 01:00:30.958759 Hex of detail: 383680a07038204018303c0035ae10000019
9410 01:00:30.965494 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9411 01:00:30.969226 0780 0798 07c8 0820 hborder 0
9412 01:00:30.972498 0438 043b 0447 0458 vborder 0
9413 01:00:30.975836 -hsync -vsync
9414 01:00:30.976390 Did detailed timing
9415 01:00:30.982475 Hex of detail: 000000000000000000000000000000000000
9416 01:00:30.985459 Manufacturer-specified data, tag 0
9417 01:00:30.988846 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9418 01:00:30.992024 ASCII string: InfoVision
9419 01:00:30.995086 Hex of detail: 000000fe00523134304e574635205248200a
9420 01:00:30.998488 ASCII string: R140NWF5 RH
9421 01:00:30.998952 Checksum
9422 01:00:31.001729 Checksum: 0xfb (valid)
9423 01:00:31.005007 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9424 01:00:31.008558 DSI data_rate: 832800000 bps
9425 01:00:31.014854 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9426 01:00:31.018296 anx7625_parse_edid: pixelclock(138800).
9427 01:00:31.021780 hactive(1920), hsync(48), hfp(24), hbp(88)
9428 01:00:31.025206 vactive(1080), vsync(12), vfp(3), vbp(17)
9429 01:00:31.028208 anx7625_dsi_config: config dsi.
9430 01:00:31.034718 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9431 01:00:31.048890 anx7625_dsi_config: success to config DSI
9432 01:00:31.052132 anx7625_dp_start: MIPI phy setup OK.
9433 01:00:31.055442 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9434 01:00:31.058773 mtk_ddp_mode_set invalid vrefresh 60
9435 01:00:31.062226 main_disp_path_setup
9436 01:00:31.062772 ovl_layer_smi_id_en
9437 01:00:31.065522 ovl_layer_smi_id_en
9438 01:00:31.066083 ccorr_config
9439 01:00:31.066508 aal_config
9440 01:00:31.068503 gamma_config
9441 01:00:31.068965 postmask_config
9442 01:00:31.071743 dither_config
9443 01:00:31.075481 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9444 01:00:31.081799 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9445 01:00:31.085419 Root Device init finished in 555 msecs
9446 01:00:31.088489 CPU_CLUSTER: 0 init
9447 01:00:31.095720 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9448 01:00:31.101695 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9449 01:00:31.102304 APU_MBOX 0x190000b0 = 0x10001
9450 01:00:31.105045 APU_MBOX 0x190001b0 = 0x10001
9451 01:00:31.108143 APU_MBOX 0x190005b0 = 0x10001
9452 01:00:31.111911 APU_MBOX 0x190006b0 = 0x10001
9453 01:00:31.118018 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9454 01:00:31.128544 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9455 01:00:31.140516 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9456 01:00:31.147022 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9457 01:00:31.158892 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9458 01:00:31.167847 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9459 01:00:31.170812 CPU_CLUSTER: 0 init finished in 81 msecs
9460 01:00:31.174129 Devices initialized
9461 01:00:31.177775 Show all devs... After init.
9462 01:00:31.178437 Root Device: enabled 1
9463 01:00:31.181359 CPU_CLUSTER: 0: enabled 1
9464 01:00:31.184375 CPU: 00: enabled 1
9465 01:00:31.187618 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9466 01:00:31.190694 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9467 01:00:31.194266 ELOG: NV offset 0x57f000 size 0x1000
9468 01:00:31.200663 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9469 01:00:31.207225 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9470 01:00:31.210850 ELOG: Event(17) added with size 13 at 2024-06-16 01:00:31 UTC
9471 01:00:31.217594 out: cmd=0x121: 03 db 21 01 00 00 00 00
9472 01:00:31.220774 in-header: 03 e3 00 00 2c 00 00 00
9473 01:00:31.234032 in-data: 59 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9474 01:00:31.236808 ELOG: Event(A1) added with size 10 at 2024-06-16 01:00:31 UTC
9475 01:00:31.243676 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9476 01:00:31.250316 ELOG: Event(A0) added with size 9 at 2024-06-16 01:00:31 UTC
9477 01:00:31.253731 elog_add_boot_reason: Logged dev mode boot
9478 01:00:31.260888 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9479 01:00:31.261462 Finalize devices...
9480 01:00:31.264047 Devices finalized
9481 01:00:31.267079 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9482 01:00:31.270385 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9483 01:00:31.273758 in-header: 03 07 00 00 08 00 00 00
9484 01:00:31.277272 in-data: aa e4 47 04 13 02 00 00
9485 01:00:31.280177 Chrome EC: UHEPI supported
9486 01:00:31.287154 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9487 01:00:31.289965 in-header: 03 a9 00 00 08 00 00 00
9488 01:00:31.293118 in-data: 84 60 60 08 00 00 00 00
9489 01:00:31.300244 ELOG: Event(91) added with size 10 at 2024-06-16 01:00:31 UTC
9490 01:00:31.303260 Chrome EC: clear events_b mask to 0x0000000020004000
9491 01:00:31.309584 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9492 01:00:31.313444 in-header: 03 fd 00 00 00 00 00 00
9493 01:00:31.316560 in-data:
9494 01:00:31.319416 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9495 01:00:31.322887 Writing coreboot table at 0xffe64000
9496 01:00:31.329768 0. 000000000010a000-0000000000113fff: RAMSTAGE
9497 01:00:31.333161 1. 0000000040000000-00000000400fffff: RAM
9498 01:00:31.336210 2. 0000000040100000-000000004032afff: RAMSTAGE
9499 01:00:31.339382 3. 000000004032b000-00000000545fffff: RAM
9500 01:00:31.342746 4. 0000000054600000-000000005465ffff: BL31
9501 01:00:31.349144 5. 0000000054660000-00000000ffe63fff: RAM
9502 01:00:31.352970 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9503 01:00:31.355837 7. 0000000100000000-000000023fffffff: RAM
9504 01:00:31.359464 Passing 5 GPIOs to payload:
9505 01:00:31.362288 NAME | PORT | POLARITY | VALUE
9506 01:00:31.369372 EC in RW | 0x000000aa | low | undefined
9507 01:00:31.372422 EC interrupt | 0x00000005 | low | undefined
9508 01:00:31.379447 TPM interrupt | 0x000000ab | high | undefined
9509 01:00:31.382247 SD card detect | 0x00000011 | high | undefined
9510 01:00:31.385979 speaker enable | 0x00000093 | high | undefined
9511 01:00:31.392267 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9512 01:00:31.395479 in-header: 03 f9 00 00 02 00 00 00
9513 01:00:31.395942 in-data: 02 00
9514 01:00:31.398974 ADC[4]: Raw value=900443 ID=7
9515 01:00:31.402241 ADC[3]: Raw value=213282 ID=1
9516 01:00:31.402693 RAM Code: 0x71
9517 01:00:31.405287 ADC[6]: Raw value=75036 ID=0
9518 01:00:31.408943 ADC[5]: Raw value=212912 ID=1
9519 01:00:31.409359 SKU Code: 0x1
9520 01:00:31.415611 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 81b9
9521 01:00:31.418729 coreboot table: 964 bytes.
9522 01:00:31.421730 IMD ROOT 0. 0xfffff000 0x00001000
9523 01:00:31.425444 IMD SMALL 1. 0xffffe000 0x00001000
9524 01:00:31.425865 RO MCACHE 2. 0xffffc000 0x00001104
9525 01:00:31.429250 CONSOLE 3. 0xfff7c000 0x00080000
9526 01:00:31.432242 FMAP 4. 0xfff7b000 0x00000452
9527 01:00:31.435277 TIME STAMP 5. 0xfff7a000 0x00000910
9528 01:00:31.438722 VBOOT WORK 6. 0xfff66000 0x00014000
9529 01:00:31.441842 RAMOOPS 7. 0xffe66000 0x00100000
9530 01:00:31.444917 COREBOOT 8. 0xffe64000 0x00002000
9531 01:00:31.448290 IMD small region:
9532 01:00:31.451660 IMD ROOT 0. 0xffffec00 0x00000400
9533 01:00:31.454671 VPD 1. 0xffffeb80 0x0000006c
9534 01:00:31.458240 MMC STATUS 2. 0xffffeb60 0x00000004
9535 01:00:31.464726 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9536 01:00:31.471755 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9537 01:00:31.510563 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9538 01:00:31.513400 Checking segment from ROM address 0x40100000
9539 01:00:31.520182 Checking segment from ROM address 0x4010001c
9540 01:00:31.523402 Loading segment from ROM address 0x40100000
9541 01:00:31.523845 code (compression=0)
9542 01:00:31.533500 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9543 01:00:31.539957 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9544 01:00:31.542791 it's not compressed!
9545 01:00:31.546449 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9546 01:00:31.553122 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9547 01:00:31.570950 Loading segment from ROM address 0x4010001c
9548 01:00:31.571493 Entry Point 0x80000000
9549 01:00:31.573811 Loaded segments
9550 01:00:31.577207 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9551 01:00:31.584528 Jumping to boot code at 0x80000000(0xffe64000)
9552 01:00:31.590651 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9553 01:00:31.597459 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9554 01:00:31.605728 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9555 01:00:31.608592 Checking segment from ROM address 0x40100000
9556 01:00:31.611496 Checking segment from ROM address 0x4010001c
9557 01:00:31.618265 Loading segment from ROM address 0x40100000
9558 01:00:31.618778 code (compression=1)
9559 01:00:31.624847 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9560 01:00:31.634872 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9561 01:00:31.635435 using LZMA
9562 01:00:31.643636 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9563 01:00:31.650280 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9564 01:00:31.653350 Loading segment from ROM address 0x4010001c
9565 01:00:31.653810 Entry Point 0x54601000
9566 01:00:31.657111 Loaded segments
9567 01:00:31.659756 NOTICE: MT8192 bl31_setup
9568 01:00:31.667124 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9569 01:00:31.670972 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9570 01:00:31.673983 WARNING: region 0:
9571 01:00:31.677315 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9572 01:00:31.677872 WARNING: region 1:
9573 01:00:31.684409 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9574 01:00:31.686840 WARNING: region 2:
9575 01:00:31.690552 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9576 01:00:31.693688 WARNING: region 3:
9577 01:00:31.697061 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9578 01:00:31.700436 WARNING: region 4:
9579 01:00:31.706986 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9580 01:00:31.707556 WARNING: region 5:
9581 01:00:31.710192 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9582 01:00:31.713669 WARNING: region 6:
9583 01:00:31.716775 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9584 01:00:31.719981 WARNING: region 7:
9585 01:00:31.723371 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9586 01:00:31.729953 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9587 01:00:31.733462 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9588 01:00:31.739983 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9589 01:00:31.743164 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9590 01:00:31.746666 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9591 01:00:31.752939 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9592 01:00:31.756425 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9593 01:00:31.759442 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9594 01:00:31.766617 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9595 01:00:31.769495 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9596 01:00:31.776381 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9597 01:00:31.779673 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9598 01:00:31.783002 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9599 01:00:31.789415 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9600 01:00:31.792474 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9601 01:00:31.795974 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9602 01:00:31.802622 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9603 01:00:31.806217 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9604 01:00:31.813079 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9605 01:00:31.816175 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9606 01:00:31.819117 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9607 01:00:31.826212 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9608 01:00:31.829069 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9609 01:00:31.835574 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9610 01:00:31.838773 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9611 01:00:31.842091 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9612 01:00:31.848851 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9613 01:00:31.852304 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9614 01:00:31.858757 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9615 01:00:31.861921 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9616 01:00:31.865374 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9617 01:00:31.872301 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9618 01:00:31.875337 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9619 01:00:31.878689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9620 01:00:31.885120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9621 01:00:31.888593 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9622 01:00:31.891503 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9623 01:00:31.894995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9624 01:00:31.902072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9625 01:00:31.904578 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9626 01:00:31.908115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9627 01:00:31.911327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9628 01:00:31.918404 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9629 01:00:31.921591 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9630 01:00:31.924864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9631 01:00:31.931212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9632 01:00:31.934855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9633 01:00:31.938554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9634 01:00:31.944401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9635 01:00:31.947856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9636 01:00:31.950867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9637 01:00:31.958043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9638 01:00:31.960715 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9639 01:00:31.967912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9640 01:00:31.971140 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9641 01:00:31.977864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9642 01:00:31.980650 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9643 01:00:31.983990 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9644 01:00:31.991121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9645 01:00:31.993591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9646 01:00:32.000567 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9647 01:00:32.004032 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9648 01:00:32.010402 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9649 01:00:32.013585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9650 01:00:32.020315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9651 01:00:32.023350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9652 01:00:32.030728 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9653 01:00:32.033529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9654 01:00:32.036835 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9655 01:00:32.043222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9656 01:00:32.046510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9657 01:00:32.053748 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9658 01:00:32.056977 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9659 01:00:32.063585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9660 01:00:32.066715 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9661 01:00:32.073147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9662 01:00:32.076464 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9663 01:00:32.079728 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9664 01:00:32.086412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9665 01:00:32.090280 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9666 01:00:32.096638 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9667 01:00:32.099917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9668 01:00:32.106256 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9669 01:00:32.109817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9670 01:00:32.116615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9671 01:00:32.119680 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9672 01:00:32.122852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9673 01:00:32.129532 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9674 01:00:32.132741 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9675 01:00:32.139393 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9676 01:00:32.142820 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9677 01:00:32.149439 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9678 01:00:32.153263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9679 01:00:32.156125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9680 01:00:32.162451 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9681 01:00:32.166358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9682 01:00:32.172293 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9683 01:00:32.176011 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9684 01:00:32.179021 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9685 01:00:32.182243 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9686 01:00:32.189287 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9687 01:00:32.192264 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9688 01:00:32.198743 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9689 01:00:32.202540 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9690 01:00:32.205614 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9691 01:00:32.212282 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9692 01:00:32.215352 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9693 01:00:32.222085 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9694 01:00:32.225738 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9695 01:00:32.228779 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9696 01:00:32.234903 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9697 01:00:32.238839 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9698 01:00:32.245165 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9699 01:00:32.248526 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9700 01:00:32.254875 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9701 01:00:32.258369 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9702 01:00:32.261471 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9703 01:00:32.265093 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9704 01:00:32.271602 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9705 01:00:32.275010 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9706 01:00:32.278892 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9707 01:00:32.281733 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9708 01:00:32.288124 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9709 01:00:32.291284 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9710 01:00:32.294487 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9711 01:00:32.300917 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9712 01:00:32.304501 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9713 01:00:32.310921 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9714 01:00:32.314568 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9715 01:00:32.317427 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9716 01:00:32.324266 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9717 01:00:32.327944 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9718 01:00:32.334056 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9719 01:00:32.337584 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9720 01:00:32.340635 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9721 01:00:32.347163 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9722 01:00:32.350883 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9723 01:00:32.357698 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9724 01:00:32.360516 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9725 01:00:32.363795 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9726 01:00:32.370255 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9727 01:00:32.373919 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9728 01:00:32.380218 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9729 01:00:32.384307 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9730 01:00:32.386939 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9731 01:00:32.393354 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9732 01:00:32.396458 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9733 01:00:32.403294 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9734 01:00:32.407153 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9735 01:00:32.409845 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9736 01:00:32.416487 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9737 01:00:32.420210 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9738 01:00:32.426610 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9739 01:00:32.430286 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9740 01:00:32.433391 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9741 01:00:32.439726 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9742 01:00:32.443115 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9743 01:00:32.449947 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9744 01:00:32.453076 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9745 01:00:32.456398 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9746 01:00:32.463286 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9747 01:00:32.465933 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9748 01:00:32.472901 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9749 01:00:32.476053 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9750 01:00:32.479507 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9751 01:00:32.486064 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9752 01:00:32.489809 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9753 01:00:32.495790 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9754 01:00:32.499639 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9755 01:00:32.502324 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9756 01:00:32.509103 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9757 01:00:32.512205 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9758 01:00:32.519139 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9759 01:00:32.522384 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9760 01:00:32.525329 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9761 01:00:32.531925 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9762 01:00:32.535443 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9763 01:00:32.542270 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9764 01:00:32.545249 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9765 01:00:32.548316 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9766 01:00:32.555774 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9767 01:00:32.558707 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9768 01:00:32.565507 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9769 01:00:32.568223 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9770 01:00:32.571878 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9771 01:00:32.578522 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9772 01:00:32.581890 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9773 01:00:32.588151 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9774 01:00:32.591702 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9775 01:00:32.595198 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9776 01:00:32.601764 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9777 01:00:32.605035 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9778 01:00:32.611730 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9779 01:00:32.615079 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9780 01:00:32.618095 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9781 01:00:32.624515 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9782 01:00:32.627745 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9783 01:00:32.634677 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9784 01:00:32.637786 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9785 01:00:32.644817 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9786 01:00:32.648393 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9787 01:00:32.650733 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9788 01:00:32.657405 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9789 01:00:32.660789 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9790 01:00:32.667861 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9791 01:00:32.670597 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9792 01:00:32.676998 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9793 01:00:32.681015 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9794 01:00:32.687215 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9795 01:00:32.690638 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9796 01:00:32.693526 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9797 01:00:32.700340 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9798 01:00:32.703879 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9799 01:00:32.710232 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9800 01:00:32.714117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9801 01:00:32.717050 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9802 01:00:32.723237 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9803 01:00:32.726563 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9804 01:00:32.733502 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9805 01:00:32.737013 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9806 01:00:32.743293 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9807 01:00:32.747126 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9808 01:00:32.749998 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9809 01:00:32.756962 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9810 01:00:32.759823 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9811 01:00:32.766657 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9812 01:00:32.769476 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9813 01:00:32.776768 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9814 01:00:32.780276 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9815 01:00:32.783178 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9816 01:00:32.785982 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9817 01:00:32.793069 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9818 01:00:32.796248 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9819 01:00:32.799394 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9820 01:00:32.802766 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9821 01:00:32.809460 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9822 01:00:32.813192 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9823 01:00:32.819942 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9824 01:00:32.823142 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9825 01:00:32.826271 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9826 01:00:32.833215 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9827 01:00:32.836110 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9828 01:00:32.842501 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9829 01:00:32.846277 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9830 01:00:32.849411 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9831 01:00:32.855590 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9832 01:00:32.859219 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9833 01:00:32.862118 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9834 01:00:32.869434 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9835 01:00:32.872243 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9836 01:00:32.875783 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9837 01:00:32.882106 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9838 01:00:32.885487 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9839 01:00:32.892136 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9840 01:00:32.895998 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9841 01:00:32.898716 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9842 01:00:32.905777 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9843 01:00:32.908837 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9844 01:00:32.912337 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9845 01:00:32.919061 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9846 01:00:32.922214 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9847 01:00:32.928847 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9848 01:00:32.932851 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9849 01:00:32.935463 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9850 01:00:32.942000 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9851 01:00:32.945087 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9852 01:00:32.948623 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9853 01:00:32.954819 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9854 01:00:32.958331 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9855 01:00:32.961923 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9856 01:00:32.968089 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9857 01:00:32.971813 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9858 01:00:32.975056 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9859 01:00:32.978391 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9860 01:00:32.981623 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9861 01:00:32.987781 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9862 01:00:32.991362 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9863 01:00:32.994755 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9864 01:00:33.001102 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9865 01:00:33.004358 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9866 01:00:33.007508 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9867 01:00:33.010743 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9868 01:00:33.017888 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9869 01:00:33.021538 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9870 01:00:33.027632 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9871 01:00:33.030941 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9872 01:00:33.037569 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9873 01:00:33.040357 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9874 01:00:33.044059 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9875 01:00:33.050498 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9876 01:00:33.053926 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9877 01:00:33.060148 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9878 01:00:33.063797 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9879 01:00:33.070438 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9880 01:00:33.073738 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9881 01:00:33.076853 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9882 01:00:33.083582 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9883 01:00:33.086522 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9884 01:00:33.093705 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9885 01:00:33.096649 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9886 01:00:33.099776 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9887 01:00:33.106288 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9888 01:00:33.109491 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9889 01:00:33.116209 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9890 01:00:33.119559 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9891 01:00:33.122745 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9892 01:00:33.129535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9893 01:00:33.132981 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9894 01:00:33.139321 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9895 01:00:33.142559 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9896 01:00:33.149024 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9897 01:00:33.152829 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9898 01:00:33.158848 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9899 01:00:33.162479 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9900 01:00:33.165928 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9901 01:00:33.172701 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9902 01:00:33.176113 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9903 01:00:33.182568 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9904 01:00:33.186054 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9905 01:00:33.189200 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9906 01:00:33.195915 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9907 01:00:33.198650 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9908 01:00:33.205164 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9909 01:00:33.208984 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9910 01:00:33.212208 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9911 01:00:33.218344 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9912 01:00:33.221938 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9913 01:00:33.228589 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9914 01:00:33.231679 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9915 01:00:33.234987 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9916 01:00:33.241892 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9917 01:00:33.244868 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9918 01:00:33.251600 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9919 01:00:33.254666 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9920 01:00:33.261199 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9921 01:00:33.264645 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9922 01:00:33.271104 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9923 01:00:33.274628 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9924 01:00:33.277546 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9925 01:00:33.284366 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9926 01:00:33.287814 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9927 01:00:33.294520 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9928 01:00:33.297498 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9929 01:00:33.300862 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9930 01:00:33.307399 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9931 01:00:33.310672 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9932 01:00:33.317475 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9933 01:00:33.320997 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9934 01:00:33.327400 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9935 01:00:33.330837 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9936 01:00:33.334086 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9937 01:00:33.340822 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9938 01:00:33.343791 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9939 01:00:33.347706 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9940 01:00:33.354123 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9941 01:00:33.357443 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9942 01:00:33.363557 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9943 01:00:33.367282 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9944 01:00:33.373609 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9945 01:00:33.377140 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9946 01:00:33.383627 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9947 01:00:33.387057 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9948 01:00:33.390327 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9949 01:00:33.397073 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9950 01:00:33.400049 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9951 01:00:33.406745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9952 01:00:33.410023 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9953 01:00:33.417058 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9954 01:00:33.419825 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9955 01:00:33.426654 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9956 01:00:33.430070 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9957 01:00:33.433643 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9958 01:00:33.440060 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9959 01:00:33.442972 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9960 01:00:33.450391 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9961 01:00:33.452969 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9962 01:00:33.459815 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9963 01:00:33.462824 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9964 01:00:33.469679 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9965 01:00:33.472647 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9966 01:00:33.476013 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9967 01:00:33.482753 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9968 01:00:33.485847 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9969 01:00:33.492571 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9970 01:00:33.495944 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9971 01:00:33.502293 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9972 01:00:33.505749 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9973 01:00:33.512351 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9974 01:00:33.515635 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9975 01:00:33.519046 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9976 01:00:33.525776 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9977 01:00:33.529003 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9978 01:00:33.535410 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9979 01:00:33.538863 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9980 01:00:33.545520 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9981 01:00:33.549446 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9982 01:00:33.552111 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9983 01:00:33.558891 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9984 01:00:33.562091 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9985 01:00:33.568951 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9986 01:00:33.571868 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9987 01:00:33.578713 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9988 01:00:33.582521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9989 01:00:33.585269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9990 01:00:33.592086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9991 01:00:33.595684 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9992 01:00:33.601850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9993 01:00:33.604941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9994 01:00:33.611789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9995 01:00:33.615057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9996 01:00:33.621545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9997 01:00:33.624904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9998 01:00:33.631102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9999 01:00:33.634966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10000 01:00:33.641305 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10001 01:00:33.644631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10002 01:00:33.651189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10003 01:00:33.654648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10004 01:00:33.660879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10005 01:00:33.664272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10006 01:00:33.670876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10007 01:00:33.674287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10008 01:00:33.680753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10009 01:00:33.683755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10010 01:00:33.690662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10011 01:00:33.694303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10012 01:00:33.700543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10013 01:00:33.703570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10014 01:00:33.710341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10015 01:00:33.713472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10016 01:00:33.720066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10017 01:00:33.723245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10018 01:00:33.730277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10019 01:00:33.733478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10020 01:00:33.739964 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10021 01:00:33.740467 INFO: [APUAPC] vio 0
10022 01:00:33.747038 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10023 01:00:33.750247 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10024 01:00:33.753604 INFO: [APUAPC] D0_APC_0: 0x400510
10025 01:00:33.756804 INFO: [APUAPC] D0_APC_1: 0x0
10026 01:00:33.759784 INFO: [APUAPC] D0_APC_2: 0x1540
10027 01:00:33.763565 INFO: [APUAPC] D0_APC_3: 0x0
10028 01:00:33.767054 INFO: [APUAPC] D1_APC_0: 0xffffffff
10029 01:00:33.770538 INFO: [APUAPC] D1_APC_1: 0xffffffff
10030 01:00:33.773204 INFO: [APUAPC] D1_APC_2: 0x3fffff
10031 01:00:33.776632 INFO: [APUAPC] D1_APC_3: 0x0
10032 01:00:33.780021 INFO: [APUAPC] D2_APC_0: 0xffffffff
10033 01:00:33.783159 INFO: [APUAPC] D2_APC_1: 0xffffffff
10034 01:00:33.786754 INFO: [APUAPC] D2_APC_2: 0x3fffff
10035 01:00:33.789833 INFO: [APUAPC] D2_APC_3: 0x0
10036 01:00:33.793521 INFO: [APUAPC] D3_APC_0: 0xffffffff
10037 01:00:33.796716 INFO: [APUAPC] D3_APC_1: 0xffffffff
10038 01:00:33.799881 INFO: [APUAPC] D3_APC_2: 0x3fffff
10039 01:00:33.803129 INFO: [APUAPC] D3_APC_3: 0x0
10040 01:00:33.806465 INFO: [APUAPC] D4_APC_0: 0xffffffff
10041 01:00:33.809703 INFO: [APUAPC] D4_APC_1: 0xffffffff
10042 01:00:33.813205 INFO: [APUAPC] D4_APC_2: 0x3fffff
10043 01:00:33.816174 INFO: [APUAPC] D4_APC_3: 0x0
10044 01:00:33.820082 INFO: [APUAPC] D5_APC_0: 0xffffffff
10045 01:00:33.822851 INFO: [APUAPC] D5_APC_1: 0xffffffff
10046 01:00:33.826126 INFO: [APUAPC] D5_APC_2: 0x3fffff
10047 01:00:33.826649 INFO: [APUAPC] D5_APC_3: 0x0
10048 01:00:33.833235 INFO: [APUAPC] D6_APC_0: 0xffffffff
10049 01:00:33.835977 INFO: [APUAPC] D6_APC_1: 0xffffffff
10050 01:00:33.839296 INFO: [APUAPC] D6_APC_2: 0x3fffff
10051 01:00:33.839722 INFO: [APUAPC] D6_APC_3: 0x0
10052 01:00:33.842739 INFO: [APUAPC] D7_APC_0: 0xffffffff
10053 01:00:33.846430 INFO: [APUAPC] D7_APC_1: 0xffffffff
10054 01:00:33.850013 INFO: [APUAPC] D7_APC_2: 0x3fffff
10055 01:00:33.852744 INFO: [APUAPC] D7_APC_3: 0x0
10056 01:00:33.856099 INFO: [APUAPC] D8_APC_0: 0xffffffff
10057 01:00:33.859058 INFO: [APUAPC] D8_APC_1: 0xffffffff
10058 01:00:33.862868 INFO: [APUAPC] D8_APC_2: 0x3fffff
10059 01:00:33.866013 INFO: [APUAPC] D8_APC_3: 0x0
10060 01:00:33.869269 INFO: [APUAPC] D9_APC_0: 0xffffffff
10061 01:00:33.872569 INFO: [APUAPC] D9_APC_1: 0xffffffff
10062 01:00:33.875594 INFO: [APUAPC] D9_APC_2: 0x3fffff
10063 01:00:33.879453 INFO: [APUAPC] D9_APC_3: 0x0
10064 01:00:33.882404 INFO: [APUAPC] D10_APC_0: 0xffffffff
10065 01:00:33.885661 INFO: [APUAPC] D10_APC_1: 0xffffffff
10066 01:00:33.889252 INFO: [APUAPC] D10_APC_2: 0x3fffff
10067 01:00:33.892714 INFO: [APUAPC] D10_APC_3: 0x0
10068 01:00:33.895849 INFO: [APUAPC] D11_APC_0: 0xffffffff
10069 01:00:33.898965 INFO: [APUAPC] D11_APC_1: 0xffffffff
10070 01:00:33.902651 INFO: [APUAPC] D11_APC_2: 0x3fffff
10071 01:00:33.905541 INFO: [APUAPC] D11_APC_3: 0x0
10072 01:00:33.908605 INFO: [APUAPC] D12_APC_0: 0xffffffff
10073 01:00:33.912012 INFO: [APUAPC] D12_APC_1: 0xffffffff
10074 01:00:33.916064 INFO: [APUAPC] D12_APC_2: 0x3fffff
10075 01:00:33.918617 INFO: [APUAPC] D12_APC_3: 0x0
10076 01:00:33.921833 INFO: [APUAPC] D13_APC_0: 0xffffffff
10077 01:00:33.928810 INFO: [APUAPC] D13_APC_1: 0xffffffff
10078 01:00:33.931727 INFO: [APUAPC] D13_APC_2: 0x3fffff
10079 01:00:33.932198 INFO: [APUAPC] D13_APC_3: 0x0
10080 01:00:33.935429 INFO: [APUAPC] D14_APC_0: 0xffffffff
10081 01:00:33.942219 INFO: [APUAPC] D14_APC_1: 0xffffffff
10082 01:00:33.945255 INFO: [APUAPC] D14_APC_2: 0x3fffff
10083 01:00:33.945809 INFO: [APUAPC] D14_APC_3: 0x0
10084 01:00:33.951803 INFO: [APUAPC] D15_APC_0: 0xffffffff
10085 01:00:33.955060 INFO: [APUAPC] D15_APC_1: 0xffffffff
10086 01:00:33.958681 INFO: [APUAPC] D15_APC_2: 0x3fffff
10087 01:00:33.959237 INFO: [APUAPC] D15_APC_3: 0x0
10088 01:00:33.961638 INFO: [APUAPC] APC_CON: 0x4
10089 01:00:33.965097 INFO: [NOCDAPC] D0_APC_0: 0x0
10090 01:00:33.968299 INFO: [NOCDAPC] D0_APC_1: 0x0
10091 01:00:33.972201 INFO: [NOCDAPC] D1_APC_0: 0x0
10092 01:00:33.974789 INFO: [NOCDAPC] D1_APC_1: 0xfff
10093 01:00:33.978055 INFO: [NOCDAPC] D2_APC_0: 0x0
10094 01:00:33.981835 INFO: [NOCDAPC] D2_APC_1: 0xfff
10095 01:00:33.985284 INFO: [NOCDAPC] D3_APC_0: 0x0
10096 01:00:33.988071 INFO: [NOCDAPC] D3_APC_1: 0xfff
10097 01:00:33.988530 INFO: [NOCDAPC] D4_APC_0: 0x0
10098 01:00:33.991168 INFO: [NOCDAPC] D4_APC_1: 0xfff
10099 01:00:33.995125 INFO: [NOCDAPC] D5_APC_0: 0x0
10100 01:00:33.998043 INFO: [NOCDAPC] D5_APC_1: 0xfff
10101 01:00:34.001492 INFO: [NOCDAPC] D6_APC_0: 0x0
10102 01:00:34.004705 INFO: [NOCDAPC] D6_APC_1: 0xfff
10103 01:00:34.007637 INFO: [NOCDAPC] D7_APC_0: 0x0
10104 01:00:34.011267 INFO: [NOCDAPC] D7_APC_1: 0xfff
10105 01:00:34.014808 INFO: [NOCDAPC] D8_APC_0: 0x0
10106 01:00:34.018016 INFO: [NOCDAPC] D8_APC_1: 0xfff
10107 01:00:34.021285 INFO: [NOCDAPC] D9_APC_0: 0x0
10108 01:00:34.024985 INFO: [NOCDAPC] D9_APC_1: 0xfff
10109 01:00:34.025543 INFO: [NOCDAPC] D10_APC_0: 0x0
10110 01:00:34.027797 INFO: [NOCDAPC] D10_APC_1: 0xfff
10111 01:00:34.030931 INFO: [NOCDAPC] D11_APC_0: 0x0
10112 01:00:34.034431 INFO: [NOCDAPC] D11_APC_1: 0xfff
10113 01:00:34.038052 INFO: [NOCDAPC] D12_APC_0: 0x0
10114 01:00:34.041102 INFO: [NOCDAPC] D12_APC_1: 0xfff
10115 01:00:34.044378 INFO: [NOCDAPC] D13_APC_0: 0x0
10116 01:00:34.047697 INFO: [NOCDAPC] D13_APC_1: 0xfff
10117 01:00:34.051117 INFO: [NOCDAPC] D14_APC_0: 0x0
10118 01:00:34.054325 INFO: [NOCDAPC] D14_APC_1: 0xfff
10119 01:00:34.057813 INFO: [NOCDAPC] D15_APC_0: 0x0
10120 01:00:34.060996 INFO: [NOCDAPC] D15_APC_1: 0xfff
10121 01:00:34.063824 INFO: [NOCDAPC] APC_CON: 0x4
10122 01:00:34.067350 INFO: [APUAPC] set_apusys_apc done
10123 01:00:34.070567 INFO: [DEVAPC] devapc_init done
10124 01:00:34.073921 INFO: GICv3 without legacy support detected.
10125 01:00:34.077331 INFO: ARM GICv3 driver initialized in EL3
10126 01:00:34.081174 INFO: Maximum SPI INTID supported: 639
10127 01:00:34.083906 INFO: BL31: Initializing runtime services
10128 01:00:34.090921 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10129 01:00:34.094205 INFO: SPM: enable CPC mode
10130 01:00:34.100663 INFO: mcdi ready for mcusys-off-idle and system suspend
10131 01:00:34.103732 INFO: BL31: Preparing for EL3 exit to normal world
10132 01:00:34.107170 INFO: Entry point address = 0x80000000
10133 01:00:34.110688 INFO: SPSR = 0x8
10134 01:00:34.115217
10135 01:00:34.115812
10136 01:00:34.116188
10137 01:00:34.118491 Starting depthcharge on Spherion...
10138 01:00:34.119060
10139 01:00:34.119432 Wipe memory regions:
10140 01:00:34.119778
10141 01:00:34.122203 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10142 01:00:34.122755 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10143 01:00:34.123209 Setting prompt string to ['asurada:']
10144 01:00:34.123673 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10145 01:00:34.124483 [0x00000040000000, 0x00000054600000)
10146 01:00:34.243939
10147 01:00:34.244515 [0x00000054660000, 0x00000080000000)
10148 01:00:34.504758
10149 01:00:34.505524 [0x000000821a7280, 0x000000ffe64000)
10150 01:00:35.249204
10151 01:00:35.249767 [0x00000100000000, 0x00000240000000)
10152 01:00:37.138929
10153 01:00:37.142216 Initializing XHCI USB controller at 0x11200000.
10154 01:00:38.179889
10155 01:00:38.182896 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10156 01:00:38.182991
10157 01:00:38.183056
10158 01:00:38.183339 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10160 01:00:38.283725 asurada: tftpboot 192.168.201.1 14368620/tftp-deploy-he9vtqyu/kernel/image.itb 14368620/tftp-deploy-he9vtqyu/kernel/cmdline
10161 01:00:38.283894 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10162 01:00:38.283988 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10163 01:00:38.288158 tftpboot 192.168.201.1 14368620/tftp-deploy-he9vtqyu/kernel/image.itp-deploy-he9vtqyu/kernel/cmdline
10164 01:00:38.288244
10165 01:00:38.288309 Waiting for link
10166 01:00:38.446063
10167 01:00:38.446258 R8152: Initializing
10168 01:00:38.446330
10169 01:00:38.449359 Version 6 (ocp_data = 5c30)
10170 01:00:38.449443
10171 01:00:38.452889 R8152: Done initializing
10172 01:00:38.452972
10173 01:00:38.453039 Adding net device
10174 01:00:40.563198
10175 01:00:40.563399 done.
10176 01:00:40.563503
10177 01:00:40.563598 MAC: 00:e0:4c:68:02:81
10178 01:00:40.563691
10179 01:00:40.566725 Sending DHCP discover... done.
10180 01:00:40.566840
10181 01:00:40.569776 Waiting for reply... done.
10182 01:00:40.569886
10183 01:00:40.574230 Sending DHCP request... done.
10184 01:00:40.574341
10185 01:00:40.579225 Waiting for reply... done.
10186 01:00:40.579334
10187 01:00:40.579430 My ip is 192.168.201.14
10188 01:00:40.579524
10189 01:00:40.582418 The DHCP server ip is 192.168.201.1
10190 01:00:40.582525
10191 01:00:40.589064 TFTP server IP predefined by user: 192.168.201.1
10192 01:00:40.589175
10193 01:00:40.595594 Bootfile predefined by user: 14368620/tftp-deploy-he9vtqyu/kernel/image.itb
10194 01:00:40.595709
10195 01:00:40.599080 Sending tftp read request... done.
10196 01:00:40.599193
10197 01:00:40.603120 Waiting for the transfer...
10198 01:00:40.603232
10199 01:00:41.187885 00000000 ################################################################
10200 01:00:41.188069
10201 01:00:41.773336 00080000 ################################################################
10202 01:00:41.773533
10203 01:00:42.351514 00100000 ################################################################
10204 01:00:42.351705
10205 01:00:42.931832 00180000 ################################################################
10206 01:00:42.931983
10207 01:00:43.507005 00200000 ################################################################
10208 01:00:43.507149
10209 01:00:44.087396 00280000 ################################################################
10210 01:00:44.087551
10211 01:00:44.674724 00300000 ################################################################
10212 01:00:44.674882
10213 01:00:45.248369 00380000 ################################################################
10214 01:00:45.248512
10215 01:00:45.831186 00400000 ################################################################
10216 01:00:45.831337
10217 01:00:46.426332 00480000 ################################################################
10218 01:00:46.426485
10219 01:00:47.021019 00500000 ################################################################
10220 01:00:47.021171
10221 01:00:47.602904 00580000 ################################################################
10222 01:00:47.603053
10223 01:00:48.189054 00600000 ################################################################
10224 01:00:48.189210
10225 01:00:48.767568 00680000 ################################################################
10226 01:00:48.767717
10227 01:00:49.414216 00700000 ################################################################
10228 01:00:49.414806
10229 01:00:49.984285 00780000 ################################################################
10230 01:00:49.984474
10231 01:00:50.538069 00800000 ################################################################
10232 01:00:50.538263
10233 01:00:51.116832 00880000 ################################################################
10234 01:00:51.116996
10235 01:00:51.721446 00900000 ################################################################
10236 01:00:51.721597
10237 01:00:52.306014 00980000 ################################################################
10238 01:00:52.306174
10239 01:00:52.894892 00a00000 ################################################################
10240 01:00:52.895039
10241 01:00:53.491133 00a80000 ################################################################
10242 01:00:53.491278
10243 01:00:54.091264 00b00000 ################################################################
10244 01:00:54.091416
10245 01:00:54.685432 00b80000 ################################################################
10246 01:00:54.685578
10247 01:00:55.273460 00c00000 ################################################################
10248 01:00:55.273605
10249 01:00:55.853321 00c80000 ################################################################
10250 01:00:55.853473
10251 01:00:56.460467 00d00000 ################################################################
10252 01:00:56.460613
10253 01:00:57.047896 00d80000 ################################################################
10254 01:00:57.048043
10255 01:00:57.650841 00e00000 ################################################################
10256 01:00:57.650989
10257 01:00:58.242496 00e80000 ################################################################
10258 01:00:58.242643
10259 01:00:58.817158 00f00000 ################################################################
10260 01:00:58.817313
10261 01:00:59.413688 00f80000 ################################################################
10262 01:00:59.413831
10263 01:01:00.003040 01000000 ################################################################
10264 01:01:00.003189
10265 01:01:00.604629 01080000 ################################################################
10266 01:01:00.604804
10267 01:01:01.202677 01100000 ################################################################
10268 01:01:01.202822
10269 01:01:01.797395 01180000 ################################################################
10270 01:01:01.797546
10271 01:01:02.397407 01200000 ################################################################
10272 01:01:02.397558
10273 01:01:02.987642 01280000 ################################################################
10274 01:01:02.987792
10275 01:01:03.576473 01300000 ################################################################
10276 01:01:03.576629
10277 01:01:04.181424 01380000 ################################################################
10278 01:01:04.181582
10279 01:01:04.777737 01400000 ################################################################
10280 01:01:04.777891
10281 01:01:05.370817 01480000 ################################################################
10282 01:01:05.370976
10283 01:01:05.970761 01500000 ################################################################
10284 01:01:05.970920
10285 01:01:06.567772 01580000 ################################################################
10286 01:01:06.567934
10287 01:01:07.143209 01600000 ################################################################
10288 01:01:07.143368
10289 01:01:07.703858 01680000 ################################################################
10290 01:01:07.704026
10291 01:01:08.298451 01700000 ################################################################
10292 01:01:08.298608
10293 01:01:08.895446 01780000 ################################################################
10294 01:01:08.895603
10295 01:01:09.445930 01800000 ################################################################
10296 01:01:09.446082
10297 01:01:10.044400 01880000 ################################################################
10298 01:01:10.044566
10299 01:01:10.632583 01900000 ################################################################
10300 01:01:10.632748
10301 01:01:11.221847 01980000 ################################################################
10302 01:01:11.222001
10303 01:01:11.805958 01a00000 ################################################################
10304 01:01:11.806110
10305 01:01:12.403137 01a80000 ################################################################
10306 01:01:12.403289
10307 01:01:12.996610 01b00000 ################################################################
10308 01:01:12.996764
10309 01:01:13.590306 01b80000 ################################################################
10310 01:01:13.590461
10311 01:01:14.187448 01c00000 ################################################################
10312 01:01:14.187601
10313 01:01:14.734329 01c80000 ################################################################
10314 01:01:14.734479
10315 01:01:15.271887 01d00000 ################################################################
10316 01:01:15.272039
10317 01:01:15.812667 01d80000 ################################################################
10318 01:01:15.812820
10319 01:01:16.332808 01e00000 ######################################################### done.
10320 01:01:16.333092
10321 01:01:16.336224 The bootfile was 31917690 bytes long.
10322 01:01:16.336440
10323 01:01:16.339249 Sending tftp read request... done.
10324 01:01:16.339470
10325 01:01:16.342895 Waiting for the transfer...
10326 01:01:16.343098
10327 01:01:16.343280 00000000 # done.
10328 01:01:16.343459
10329 01:01:16.352591 Command line loaded dynamically from TFTP file: 14368620/tftp-deploy-he9vtqyu/kernel/cmdline
10330 01:01:16.352806
10331 01:01:16.375223 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368620/extract-nfsrootfs-3_3i9sun,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10332 01:01:16.375423
10333 01:01:16.375549 Loading FIT.
10334 01:01:16.375696
10335 01:01:16.378602 Image ramdisk-1 has 18743351 bytes.
10336 01:01:16.378720
10337 01:01:16.381733 Image fdt-1 has 47258 bytes.
10338 01:01:16.381866
10339 01:01:16.385183 Image kernel-1 has 13125045 bytes.
10340 01:01:16.385316
10341 01:01:16.391701 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10342 01:01:16.391842
10343 01:01:16.411520 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10344 01:01:16.411708
10345 01:01:16.415624 Choosing best match conf-1 for compat google,spherion-rev2.
10346 01:01:16.419981
10347 01:01:16.424017 Connected to device vid:did:rid of 1ae0:0028:00
10348 01:01:16.431666
10349 01:01:16.435153 tpm_get_response: command 0x17b, return code 0x0
10350 01:01:16.435254
10351 01:01:16.438325 ec_init: CrosEC protocol v3 supported (256, 248)
10352 01:01:16.442391
10353 01:01:16.445489 tpm_cleanup: add release locality here.
10354 01:01:16.445582
10355 01:01:16.445646 Shutting down all USB controllers.
10356 01:01:16.448630
10357 01:01:16.448714 Removing current net device
10358 01:01:16.448779
10359 01:01:16.455474 Exiting depthcharge with code 4 at timestamp: 71856240
10360 01:01:16.455591
10361 01:01:16.458446 LZMA decompressing kernel-1 to 0x821a6718
10362 01:01:16.458531
10363 01:01:16.461748 LZMA decompressing kernel-1 to 0x40000000
10364 01:01:18.078521
10365 01:01:18.079026 jumping to kernel
10366 01:01:18.080600 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10367 01:01:18.081082 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10368 01:01:18.081458 Setting prompt string to ['Linux version [0-9]']
10369 01:01:18.081795 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10370 01:01:18.082139 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10371 01:01:18.161676
10372 01:01:18.165689 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10373 01:01:18.168797 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10374 01:01:18.169287 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10375 01:01:18.169689 Setting prompt string to []
10376 01:01:18.170060 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10377 01:01:18.170461 Using line separator: #'\n'#
10378 01:01:18.170763 No login prompt set.
10379 01:01:18.171103 Parsing kernel messages
10380 01:01:18.171388 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10381 01:01:18.172024 [login-action] Waiting for messages, (timeout 00:03:42)
10382 01:01:18.172366 Waiting using forced prompt support (timeout 00:01:51)
10383 01:01:18.188329 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
10384 01:01:18.191613 [ 0.000000] random: crng init done
10385 01:01:18.197623 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10386 01:01:18.201664 [ 0.000000] efi: UEFI not found.
10387 01:01:18.207896 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10388 01:01:18.217545 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10389 01:01:18.227312 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10390 01:01:18.234254 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10391 01:01:18.240502 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10392 01:01:18.247056 [ 0.000000] printk: bootconsole [mtk8250] enabled
10393 01:01:18.253963 [ 0.000000] NUMA: No NUMA configuration found
10394 01:01:18.260215 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10395 01:01:18.266821 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10396 01:01:18.267242 [ 0.000000] Zone ranges:
10397 01:01:18.273503 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10398 01:01:18.276685 [ 0.000000] DMA32 empty
10399 01:01:18.283310 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10400 01:01:18.286553 [ 0.000000] Movable zone start for each node
10401 01:01:18.289808 [ 0.000000] Early memory node ranges
10402 01:01:18.297020 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10403 01:01:18.303356 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10404 01:01:18.309944 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10405 01:01:18.316381 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10406 01:01:18.323101 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10407 01:01:18.329547 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10408 01:01:18.386427 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10409 01:01:18.393366 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10410 01:01:18.399561 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10411 01:01:18.402901 [ 0.000000] psci: probing for conduit method from DT.
10412 01:01:18.409273 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10413 01:01:18.412864 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10414 01:01:18.418977 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10415 01:01:18.422338 [ 0.000000] psci: SMC Calling Convention v1.2
10416 01:01:18.429180 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10417 01:01:18.432721 [ 0.000000] Detected VIPT I-cache on CPU0
10418 01:01:18.438843 [ 0.000000] CPU features: detected: GIC system register CPU interface
10419 01:01:18.446032 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10420 01:01:18.451972 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10421 01:01:18.458714 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10422 01:01:18.468604 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10423 01:01:18.474982 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10424 01:01:18.478364 [ 0.000000] alternatives: applying boot alternatives
10425 01:01:18.485182 [ 0.000000] Fallback order for Node 0: 0
10426 01:01:18.491444 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10427 01:01:18.494650 [ 0.000000] Policy zone: Normal
10428 01:01:18.517845 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368620/extract-nfsrootfs-3_3i9sun,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10429 01:01:18.527502 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10430 01:01:18.539198 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10431 01:01:18.549271 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10432 01:01:18.555463 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10433 01:01:18.558873 <6>[ 0.000000] software IO TLB: area num 8.
10434 01:01:18.615634 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10435 01:01:18.764704 <6>[ 0.000000] Memory: 7945756K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407012K reserved, 32768K cma-reserved)
10436 01:01:18.771648 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10437 01:01:18.777835 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10438 01:01:18.781290 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10439 01:01:18.787698 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10440 01:01:18.794857 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10441 01:01:18.797604 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10442 01:01:18.807626 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10443 01:01:18.814102 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10444 01:01:18.820788 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10445 01:01:18.827231 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10446 01:01:18.830856 <6>[ 0.000000] GICv3: 608 SPIs implemented
10447 01:01:18.833986 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10448 01:01:18.840629 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10449 01:01:18.844437 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10450 01:01:18.850615 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10451 01:01:18.863511 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10452 01:01:18.876873 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10453 01:01:18.883812 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10454 01:01:18.891271 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10455 01:01:18.904352 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10456 01:01:18.910805 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10457 01:01:18.917769 <6>[ 0.009188] Console: colour dummy device 80x25
10458 01:01:18.927518 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10459 01:01:18.934252 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10460 01:01:18.937745 <6>[ 0.029221] LSM: Security Framework initializing
10461 01:01:18.944354 <6>[ 0.034161] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10462 01:01:18.954055 <6>[ 0.042023] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10463 01:01:18.964287 <6>[ 0.051440] cblist_init_generic: Setting adjustable number of callback queues.
10464 01:01:18.967501 <6>[ 0.058929] cblist_init_generic: Setting shift to 3 and lim to 1.
10465 01:01:18.977258 <6>[ 0.065307] cblist_init_generic: Setting adjustable number of callback queues.
10466 01:01:18.983919 <6>[ 0.072781] cblist_init_generic: Setting shift to 3 and lim to 1.
10467 01:01:18.986968 <6>[ 0.079182] rcu: Hierarchical SRCU implementation.
10468 01:01:18.993719 <6>[ 0.084228] rcu: Max phase no-delay instances is 1000.
10469 01:01:19.000239 <6>[ 0.091268] EFI services will not be available.
10470 01:01:19.003354 <6>[ 0.096222] smp: Bringing up secondary CPUs ...
10471 01:01:19.012168 <6>[ 0.101273] Detected VIPT I-cache on CPU1
10472 01:01:19.019126 <6>[ 0.101346] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10473 01:01:19.025723 <6>[ 0.101380] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10474 01:01:19.028842 <6>[ 0.101716] Detected VIPT I-cache on CPU2
10475 01:01:19.038609 <6>[ 0.101766] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10476 01:01:19.044851 <6>[ 0.101782] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10477 01:01:19.048364 <6>[ 0.102043] Detected VIPT I-cache on CPU3
10478 01:01:19.054995 <6>[ 0.102089] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10479 01:01:19.061505 <6>[ 0.102104] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10480 01:01:19.067758 <6>[ 0.102403] CPU features: detected: Spectre-v4
10481 01:01:19.071113 <6>[ 0.102409] CPU features: detected: Spectre-BHB
10482 01:01:19.074661 <6>[ 0.102414] Detected PIPT I-cache on CPU4
10483 01:01:19.081101 <6>[ 0.102472] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10484 01:01:19.091336 <6>[ 0.102488] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10485 01:01:19.094319 <6>[ 0.102782] Detected PIPT I-cache on CPU5
10486 01:01:19.101359 <6>[ 0.102844] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10487 01:01:19.107810 <6>[ 0.102860] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10488 01:01:19.111371 <6>[ 0.103140] Detected PIPT I-cache on CPU6
10489 01:01:19.120816 <6>[ 0.103204] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10490 01:01:19.127390 <6>[ 0.103220] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10491 01:01:19.130773 <6>[ 0.103513] Detected PIPT I-cache on CPU7
10492 01:01:19.137190 <6>[ 0.103578] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10493 01:01:19.143712 <6>[ 0.103594] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10494 01:01:19.147084 <6>[ 0.103641] smp: Brought up 1 node, 8 CPUs
10495 01:01:19.153773 <6>[ 0.244899] SMP: Total of 8 processors activated.
10496 01:01:19.160646 <6>[ 0.249850] CPU features: detected: 32-bit EL0 Support
10497 01:01:19.167037 <6>[ 0.255214] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10498 01:01:19.173822 <6>[ 0.264069] CPU features: detected: Common not Private translations
10499 01:01:19.180309 <6>[ 0.270585] CPU features: detected: CRC32 instructions
10500 01:01:19.186585 <6>[ 0.275937] CPU features: detected: RCpc load-acquire (LDAPR)
10501 01:01:19.190377 <6>[ 0.281896] CPU features: detected: LSE atomic instructions
10502 01:01:19.196583 <6>[ 0.287678] CPU features: detected: Privileged Access Never
10503 01:01:19.203112 <6>[ 0.293493] CPU features: detected: RAS Extension Support
10504 01:01:19.210118 <6>[ 0.299102] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10505 01:01:19.213258 <6>[ 0.306366] CPU: All CPU(s) started at EL2
10506 01:01:19.219633 <6>[ 0.310710] alternatives: applying system-wide alternatives
10507 01:01:19.230231 <6>[ 0.321596] devtmpfs: initialized
10508 01:01:19.245506 <6>[ 0.330445] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10509 01:01:19.252591 <6>[ 0.340408] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10510 01:01:19.258701 <6>[ 0.348433] pinctrl core: initialized pinctrl subsystem
10511 01:01:19.261976 <6>[ 0.355119] DMI not present or invalid.
10512 01:01:19.268822 <6>[ 0.359529] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10513 01:01:19.278684 <6>[ 0.366324] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10514 01:01:19.285235 <6>[ 0.373913] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10515 01:01:19.294733 <6>[ 0.382135] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10516 01:01:19.298208 <6>[ 0.390380] audit: initializing netlink subsys (disabled)
10517 01:01:19.308465 <5>[ 0.396074] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10518 01:01:19.315328 <6>[ 0.396792] thermal_sys: Registered thermal governor 'step_wise'
10519 01:01:19.321527 <6>[ 0.404039] thermal_sys: Registered thermal governor 'power_allocator'
10520 01:01:19.324580 <6>[ 0.410296] cpuidle: using governor menu
10521 01:01:19.331138 <6>[ 0.421256] NET: Registered PF_QIPCRTR protocol family
10522 01:01:19.338367 <6>[ 0.426745] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10523 01:01:19.344423 <6>[ 0.433848] ASID allocator initialised with 32768 entries
10524 01:01:19.347290 <6>[ 0.440429] Serial: AMBA PL011 UART driver
10525 01:01:19.357705 <4>[ 0.449269] Trying to register duplicate clock ID: 134
10526 01:01:19.416245 <6>[ 0.510819] KASLR enabled
10527 01:01:19.429855 <6>[ 0.518512] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10528 01:01:19.436523 <6>[ 0.525525] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10529 01:01:19.443306 <6>[ 0.532011] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10530 01:01:19.449683 <6>[ 0.539018] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10531 01:01:19.456413 <6>[ 0.545506] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10532 01:01:19.462810 <6>[ 0.552512] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10533 01:01:19.469558 <6>[ 0.559000] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10534 01:01:19.476039 <6>[ 0.566003] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10535 01:01:19.479276 <6>[ 0.573517] ACPI: Interpreter disabled.
10536 01:01:19.487881 <6>[ 0.579946] iommu: Default domain type: Translated
10537 01:01:19.494683 <6>[ 0.585059] iommu: DMA domain TLB invalidation policy: strict mode
10538 01:01:19.497814 <5>[ 0.591716] SCSI subsystem initialized
10539 01:01:19.504714 <6>[ 0.595882] usbcore: registered new interface driver usbfs
10540 01:01:19.511304 <6>[ 0.601612] usbcore: registered new interface driver hub
10541 01:01:19.514345 <6>[ 0.607166] usbcore: registered new device driver usb
10542 01:01:19.521599 <6>[ 0.613265] pps_core: LinuxPPS API ver. 1 registered
10543 01:01:19.531517 <6>[ 0.618458] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10544 01:01:19.534813 <6>[ 0.627803] PTP clock support registered
10545 01:01:19.537542 <6>[ 0.632048] EDAC MC: Ver: 3.0.0
10546 01:01:19.545296 <6>[ 0.637196] FPGA manager framework
10547 01:01:19.551680 <6>[ 0.640882] Advanced Linux Sound Architecture Driver Initialized.
10548 01:01:19.554861 <6>[ 0.647649] vgaarb: loaded
10549 01:01:19.561798 <6>[ 0.650749] clocksource: Switched to clocksource arch_sys_counter
10550 01:01:19.565011 <5>[ 0.657186] VFS: Disk quotas dquot_6.6.0
10551 01:01:19.571599 <6>[ 0.661369] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10552 01:01:19.575202 <6>[ 0.668557] pnp: PnP ACPI: disabled
10553 01:01:19.583559 <6>[ 0.675272] NET: Registered PF_INET protocol family
10554 01:01:19.593408 <6>[ 0.680868] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10555 01:01:19.604465 <6>[ 0.693205] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10556 01:01:19.614314 <6>[ 0.702019] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10557 01:01:19.620975 <6>[ 0.709994] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10558 01:01:19.630692 <6>[ 0.718699] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10559 01:01:19.637455 <6>[ 0.728454] TCP: Hash tables configured (established 65536 bind 65536)
10560 01:01:19.643939 <6>[ 0.735318] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10561 01:01:19.654183 <6>[ 0.742517] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10562 01:01:19.660760 <6>[ 0.750220] NET: Registered PF_UNIX/PF_LOCAL protocol family
10563 01:01:19.666967 <6>[ 0.756370] RPC: Registered named UNIX socket transport module.
10564 01:01:19.670483 <6>[ 0.762524] RPC: Registered udp transport module.
10565 01:01:19.676787 <6>[ 0.767459] RPC: Registered tcp transport module.
10566 01:01:19.683550 <6>[ 0.772391] RPC: Registered tcp NFSv4.1 backchannel transport module.
10567 01:01:19.686623 <6>[ 0.779059] PCI: CLS 0 bytes, default 64
10568 01:01:19.690392 <6>[ 0.783389] Unpacking initramfs...
10569 01:01:19.714176 <6>[ 0.802872] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10570 01:01:19.724657 <6>[ 0.811516] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10571 01:01:19.727557 <6>[ 0.820359] kvm [1]: IPA Size Limit: 40 bits
10572 01:01:19.734678 <6>[ 0.824887] kvm [1]: GICv3: no GICV resource entry
10573 01:01:19.737352 <6>[ 0.829909] kvm [1]: disabling GICv2 emulation
10574 01:01:19.743982 <6>[ 0.834598] kvm [1]: GIC system register CPU interface enabled
10575 01:01:19.747389 <6>[ 0.840756] kvm [1]: vgic interrupt IRQ18
10576 01:01:19.753912 <6>[ 0.845106] kvm [1]: VHE mode initialized successfully
10577 01:01:19.760137 <5>[ 0.851575] Initialise system trusted keyrings
10578 01:01:19.766995 <6>[ 0.856419] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10579 01:01:19.774432 <6>[ 0.866382] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10580 01:01:19.781138 <5>[ 0.872765] NFS: Registering the id_resolver key type
10581 01:01:19.784585 <5>[ 0.878086] Key type id_resolver registered
10582 01:01:19.791312 <5>[ 0.882500] Key type id_legacy registered
10583 01:01:19.797208 <6>[ 0.886790] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10584 01:01:19.804048 <6>[ 0.893715] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10585 01:01:19.810684 <6>[ 0.901446] 9p: Installing v9fs 9p2000 file system support
10586 01:01:19.848337 <5>[ 0.940053] Key type asymmetric registered
10587 01:01:19.851502 <5>[ 0.944385] Asymmetric key parser 'x509' registered
10588 01:01:19.861609 <6>[ 0.949533] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10589 01:01:19.864560 <6>[ 0.957145] io scheduler mq-deadline registered
10590 01:01:19.868166 <6>[ 0.961924] io scheduler kyber registered
10591 01:01:19.886719 <6>[ 0.978985] EINJ: ACPI disabled.
10592 01:01:19.920574 <4>[ 1.005400] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 01:01:19.930232 <4>[ 1.016046] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 01:01:19.945238 <6>[ 1.037107] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10595 01:01:19.953293 <6>[ 1.045182] printk: console [ttyS0] disabled
10596 01:01:19.981553 <6>[ 1.069831] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10597 01:01:19.988071 <6>[ 1.079327] printk: console [ttyS0] enabled
10598 01:01:19.991289 <6>[ 1.079327] printk: console [ttyS0] enabled
10599 01:01:19.997983 <6>[ 1.088224] printk: bootconsole [mtk8250] disabled
10600 01:01:20.001067 <6>[ 1.088224] printk: bootconsole [mtk8250] disabled
10601 01:01:20.007952 <6>[ 1.099489] SuperH (H)SCI(F) driver initialized
10602 01:01:20.011120 <6>[ 1.104777] msm_serial: driver initialized
10603 01:01:20.025380 <6>[ 1.113730] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10604 01:01:20.035556 <6>[ 1.122277] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10605 01:01:20.042018 <6>[ 1.130821] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10606 01:01:20.051827 <6>[ 1.139450] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10607 01:01:20.061532 <6>[ 1.148156] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10608 01:01:20.068339 <6>[ 1.156876] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10609 01:01:20.078071 <6>[ 1.165417] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10610 01:01:20.085044 <6>[ 1.174221] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10611 01:01:20.094566 <6>[ 1.182765] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10612 01:01:20.106836 <6>[ 1.198433] loop: module loaded
10613 01:01:20.113348 <6>[ 1.204416] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10614 01:01:20.136381 <4>[ 1.227850] mtk-pmic-keys: Failed to locate of_node [id: -1]
10615 01:01:20.143007 <6>[ 1.234624] megasas: 07.719.03.00-rc1
10616 01:01:20.152802 <6>[ 1.244238] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10617 01:01:20.159264 <6>[ 1.250129] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10618 01:01:20.175084 <6>[ 1.266767] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10619 01:01:20.236003 <6>[ 1.320607] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10620 01:01:20.478093 <6>[ 1.569626] Freeing initrd memory: 18300K
10621 01:01:20.489737 <6>[ 1.581292] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10622 01:01:20.500503 <6>[ 1.592145] tun: Universal TUN/TAP device driver, 1.6
10623 01:01:20.504109 <6>[ 1.598190] thunder_xcv, ver 1.0
10624 01:01:20.506825 <6>[ 1.601696] thunder_bgx, ver 1.0
10625 01:01:20.510357 <6>[ 1.605196] nicpf, ver 1.0
10626 01:01:20.521054 <6>[ 1.609193] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10627 01:01:20.524233 <6>[ 1.616669] hns3: Copyright (c) 2017 Huawei Corporation.
10628 01:01:20.527975 <6>[ 1.622255] hclge is initializing
10629 01:01:20.534720 <6>[ 1.625835] e1000: Intel(R) PRO/1000 Network Driver
10630 01:01:20.540892 <6>[ 1.630964] e1000: Copyright (c) 1999-2006 Intel Corporation.
10631 01:01:20.544560 <6>[ 1.636976] e1000e: Intel(R) PRO/1000 Network Driver
10632 01:01:20.550515 <6>[ 1.642191] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10633 01:01:20.557517 <6>[ 1.648375] igb: Intel(R) Gigabit Ethernet Network Driver
10634 01:01:20.563650 <6>[ 1.654025] igb: Copyright (c) 2007-2014 Intel Corporation.
10635 01:01:20.570098 <6>[ 1.659863] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10636 01:01:20.576950 <6>[ 1.666381] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10637 01:01:20.580489 <6>[ 1.672836] sky2: driver version 1.30
10638 01:01:20.587181 <6>[ 1.677766] usbcore: registered new device driver r8152-cfgselector
10639 01:01:20.593839 <6>[ 1.684299] usbcore: registered new interface driver r8152
10640 01:01:20.599577 <6>[ 1.690108] VFIO - User Level meta-driver version: 0.3
10641 01:01:20.606923 <6>[ 1.698326] usbcore: registered new interface driver usb-storage
10642 01:01:20.613623 <6>[ 1.704771] usbcore: registered new device driver onboard-usb-hub
10643 01:01:20.622288 <6>[ 1.713883] mt6397-rtc mt6359-rtc: registered as rtc0
10644 01:01:20.632040 <6>[ 1.719345] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T01:01:20 UTC (1718499680)
10645 01:01:20.635310 <6>[ 1.728899] i2c_dev: i2c /dev entries driver
10646 01:01:20.649630 <4>[ 1.740844] cpu cpu0: supply cpu not found, using dummy regulator
10647 01:01:20.655611 <4>[ 1.747275] cpu cpu1: supply cpu not found, using dummy regulator
10648 01:01:20.662284 <4>[ 1.753681] cpu cpu2: supply cpu not found, using dummy regulator
10649 01:01:20.668880 <4>[ 1.760101] cpu cpu3: supply cpu not found, using dummy regulator
10650 01:01:20.675508 <4>[ 1.766503] cpu cpu4: supply cpu not found, using dummy regulator
10651 01:01:20.682364 <4>[ 1.772898] cpu cpu5: supply cpu not found, using dummy regulator
10652 01:01:20.688843 <4>[ 1.779298] cpu cpu6: supply cpu not found, using dummy regulator
10653 01:01:20.695011 <4>[ 1.785695] cpu cpu7: supply cpu not found, using dummy regulator
10654 01:01:20.714838 <6>[ 1.806341] cpu cpu0: EM: created perf domain
10655 01:01:20.718047 <6>[ 1.811283] cpu cpu4: EM: created perf domain
10656 01:01:20.724962 <6>[ 1.816846] sdhci: Secure Digital Host Controller Interface driver
10657 01:01:20.731919 <6>[ 1.823278] sdhci: Copyright(c) Pierre Ossman
10658 01:01:20.738804 <6>[ 1.828222] Synopsys Designware Multimedia Card Interface Driver
10659 01:01:20.745239 <6>[ 1.834856] sdhci-pltfm: SDHCI platform and OF driver helper
10660 01:01:20.748675 <6>[ 1.834891] mmc0: CQHCI version 5.10
10661 01:01:20.755102 <6>[ 1.845107] ledtrig-cpu: registered to indicate activity on CPUs
10662 01:01:20.761782 <6>[ 1.852197] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10663 01:01:20.768527 <6>[ 1.859250] usbcore: registered new interface driver usbhid
10664 01:01:20.772235 <6>[ 1.865071] usbhid: USB HID core driver
10665 01:01:20.778359 <6>[ 1.869265] spi_master spi0: will run message pump with realtime priority
10666 01:01:20.823593 <6>[ 1.908910] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10667 01:01:20.842524 <6>[ 1.924025] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10668 01:01:20.845772 <6>[ 1.936285] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16814
10669 01:01:20.853328 <6>[ 1.944874] cros-ec-spi spi0.0: Chrome EC device registered
10670 01:01:20.860038 <6>[ 1.950941] mmc0: Command Queue Engine enabled
10671 01:01:20.866486 <6>[ 1.955712] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10672 01:01:20.872863 <6>[ 1.963611] mmcblk0: mmc0:0001 DA4128 116 GiB
10673 01:01:20.880701 <6>[ 1.972367] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10674 01:01:20.887854 <6>[ 1.979537] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10675 01:01:20.898250 <6>[ 1.984141] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10676 01:01:20.901292 <6>[ 1.985462] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10677 01:01:20.907566 <6>[ 1.995344] NET: Registered PF_PACKET protocol family
10678 01:01:20.914314 <6>[ 1.999928] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10679 01:01:20.917643 <6>[ 2.004676] 9pnet: Installing 9P2000 support
10680 01:01:20.923987 <5>[ 2.015666] Key type dns_resolver registered
10681 01:01:20.927720 <6>[ 2.020628] registered taskstats version 1
10682 01:01:20.934526 <5>[ 2.024996] Loading compiled-in X.509 certificates
10683 01:01:20.963453 <4>[ 2.048552] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10684 01:01:20.973455 <4>[ 2.059306] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10685 01:01:20.989920 <6>[ 2.081271] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10686 01:01:20.996746 <6>[ 2.088172] xhci-mtk 11200000.usb: xHCI Host Controller
10687 01:01:21.002915 <6>[ 2.093691] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10688 01:01:21.013546 <6>[ 2.101569] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10689 01:01:21.019859 <6>[ 2.111023] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10690 01:01:21.026716 <6>[ 2.117224] xhci-mtk 11200000.usb: xHCI Host Controller
10691 01:01:21.033108 <6>[ 2.122726] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10692 01:01:21.039640 <6>[ 2.130383] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10693 01:01:21.046384 <6>[ 2.138206] hub 1-0:1.0: USB hub found
10694 01:01:21.050199 <6>[ 2.142224] hub 1-0:1.0: 1 port detected
10695 01:01:21.060150 <6>[ 2.146546] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10696 01:01:21.063501 <6>[ 2.155276] hub 2-0:1.0: USB hub found
10697 01:01:21.066546 <6>[ 2.159300] hub 2-0:1.0: 1 port detected
10698 01:01:21.074406 <6>[ 2.166335] mtk-msdc 11f70000.mmc: Got CD GPIO
10699 01:01:21.087940 <6>[ 2.176383] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10700 01:01:21.098318 <6>[ 2.184772] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10701 01:01:21.104632 <6>[ 2.193113] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10702 01:01:21.114399 <6>[ 2.201455] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10703 01:01:21.120976 <6>[ 2.209793] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10704 01:01:21.130914 <6>[ 2.218133] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10705 01:01:21.137931 <6>[ 2.226471] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10706 01:01:21.147650 <6>[ 2.234809] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10707 01:01:21.154250 <6>[ 2.243158] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10708 01:01:21.164048 <6>[ 2.251497] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10709 01:01:21.170631 <6>[ 2.259834] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10710 01:01:21.180427 <6>[ 2.268178] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10711 01:01:21.187326 <6>[ 2.276515] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10712 01:01:21.197142 <6>[ 2.284857] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10713 01:01:21.203679 <6>[ 2.293195] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10714 01:01:21.210377 <6>[ 2.301896] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10715 01:01:21.217323 <6>[ 2.309049] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10716 01:01:21.224215 <6>[ 2.315869] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10717 01:01:21.234241 <6>[ 2.322640] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10718 01:01:21.240642 <6>[ 2.329569] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10719 01:01:21.247297 <6>[ 2.336445] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10720 01:01:21.257389 <6>[ 2.345578] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10721 01:01:21.267363 <6>[ 2.354709] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10722 01:01:21.277096 <6>[ 2.364003] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10723 01:01:21.286942 <6>[ 2.373470] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10724 01:01:21.296851 <6>[ 2.382937] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10725 01:01:21.303654 <6>[ 2.392056] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10726 01:01:21.313196 <6>[ 2.401522] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10727 01:01:21.323060 <6>[ 2.410641] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10728 01:01:21.333378 <6>[ 2.419940] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10729 01:01:21.343075 <6>[ 2.430100] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10730 01:01:21.353318 <6>[ 2.441723] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10731 01:01:21.361201 <6>[ 2.452772] Trying to probe devices needed for running init ...
10732 01:01:21.371287 <3>[ 2.460019] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10733 01:01:21.478701 <6>[ 2.567037] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10734 01:01:21.633357 <6>[ 2.724978] hub 1-1:1.0: USB hub found
10735 01:01:21.636911 <6>[ 2.729509] hub 1-1:1.0: 4 ports detected
10736 01:01:21.649046 <6>[ 2.740419] hub 1-1:1.0: USB hub found
10737 01:01:21.652142 <6>[ 2.744844] hub 1-1:1.0: 4 ports detected
10738 01:01:21.758558 <6>[ 2.847082] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10739 01:01:21.785859 <6>[ 2.877345] hub 2-1:1.0: USB hub found
10740 01:01:21.788604 <6>[ 2.881893] hub 2-1:1.0: 3 ports detected
10741 01:01:21.801269 <6>[ 2.893043] hub 2-1:1.0: USB hub found
10742 01:01:21.804633 <6>[ 2.897486] hub 2-1:1.0: 3 ports detected
10743 01:01:21.974369 <6>[ 3.063080] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10744 01:01:22.107281 <6>[ 3.199076] hub 1-1.4:1.0: USB hub found
10745 01:01:22.110444 <6>[ 3.203753] hub 1-1.4:1.0: 2 ports detected
10746 01:01:22.123940 <6>[ 3.215549] hub 1-1.4:1.0: USB hub found
10747 01:01:22.127192 <6>[ 3.220157] hub 1-1.4:1.0: 2 ports detected
10748 01:01:22.187437 <6>[ 3.275289] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10749 01:01:22.295159 <6>[ 3.383762] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10750 01:01:22.332396 <4>[ 3.420862] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10751 01:01:22.342214 <4>[ 3.429977] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10752 01:01:22.381067 <6>[ 3.472714] r8152 2-1.3:1.0 eth0: v1.12.13
10753 01:01:22.434651 <6>[ 3.523006] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10754 01:01:22.626196 <6>[ 3.714885] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10755 01:01:23.976627 <6>[ 5.068288] r8152 2-1.3:1.0 eth0: carrier on
10756 01:01:26.130600 <5>[ 5.095024] Sending DHCP requests .., OK
10757 01:01:26.137480 <6>[ 7.227213] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10758 01:01:26.140801 <6>[ 7.235528] IP-Config: Complete:
10759 01:01:26.153605 <6>[ 7.239026] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10760 01:01:26.160719 <6>[ 7.249740] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10761 01:01:26.169953 <6>[ 7.258362] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10762 01:01:26.173259 <6>[ 7.258373] nameserver0=192.168.201.1
10763 01:01:26.176813 <6>[ 7.270522] clk: Disabling unused clocks
10764 01:01:26.181042 <6>[ 7.276128] ALSA device list:
10765 01:01:26.186981 <6>[ 7.279395] No soundcards found.
10766 01:01:26.194912 <6>[ 7.287204] Freeing unused kernel memory: 8512K
10767 01:01:26.198003 <6>[ 7.292192] Run /init as init process
10768 01:01:26.209368 Loading, please wait...
10769 01:01:26.243353 Starting systemd-udevd version 252.22-1~deb12u1
10770 01:01:26.518447 <6>[ 7.607455] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10771 01:01:26.528619 <6>[ 7.617322] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10772 01:01:26.538509 <6>[ 7.619061] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10773 01:01:26.545294 <6>[ 7.626096] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10774 01:01:26.555032 <6>[ 7.638881] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10775 01:01:26.558245 <6>[ 7.643269] mc: Linux media interface: v0.10
10776 01:01:26.564793 <6>[ 7.650938] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10777 01:01:26.574265 <4>[ 7.651322] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10778 01:01:26.585065 <6>[ 7.673846] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10779 01:01:26.591910 <4>[ 7.678375] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10780 01:01:26.601599 <6>[ 7.682011] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10781 01:01:26.608133 <6>[ 7.697834] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10782 01:01:26.617526 <6>[ 7.705813] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10783 01:01:26.624331 <6>[ 7.713634] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10784 01:01:26.631303 <4>[ 7.714192] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10785 01:01:26.637531 <6>[ 7.714539] videodev: Linux video capture interface: v2.00
10786 01:01:26.647500 <6>[ 7.721497] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10787 01:01:26.685708 <6>[ 7.771462] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10788 01:01:26.695643 <3>[ 7.784588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10789 01:01:26.702088 <3>[ 7.792957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10790 01:01:26.712514 <3>[ 7.801247] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10791 01:01:26.719019 <6>[ 7.809784] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10792 01:01:26.726239 <6>[ 7.816674] pci_bus 0000:00: root bus resource [bus 00-ff]
10793 01:01:26.732205 <6>[ 7.822484] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10794 01:01:26.742022 <6>[ 7.822770] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10795 01:01:26.752232 <6>[ 7.829623] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10796 01:01:26.758768 <6>[ 7.829657] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10797 01:01:26.765174 <6>[ 7.854854] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10798 01:01:26.768330 <6>[ 7.862415] pci 0000:00:00.0: supports D1 D2
10799 01:01:26.778556 <6>[ 7.862890] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10800 01:01:26.785099 <6>[ 7.866938] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10801 01:01:26.791724 <6>[ 7.868377] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10802 01:01:26.801469 <3>[ 7.876500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10803 01:01:26.808600 <6>[ 7.881591] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10804 01:01:26.814593 <3>[ 7.890596] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10805 01:01:26.821169 <6>[ 7.897846] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10806 01:01:26.831168 <3>[ 7.904995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10807 01:01:26.837664 <6>[ 7.912185] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10808 01:01:26.844325 <6>[ 7.912200] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10809 01:01:26.854392 <3>[ 7.919721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10810 01:01:26.863914 <6>[ 7.921952] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10811 01:01:26.867456 <6>[ 7.927837] pci 0000:01:00.0: supports D1 D2
10812 01:01:26.877331 <3>[ 7.935262] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10813 01:01:26.884173 <6>[ 7.942689] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10814 01:01:26.887409 <6>[ 7.952885] Bluetooth: Core ver 2.22
10815 01:01:26.893970 <6>[ 7.953393] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10816 01:01:26.900512 <6>[ 7.958125] remoteproc remoteproc0: scp is available
10817 01:01:26.903584 <6>[ 7.958230] remoteproc remoteproc0: powering up scp
10818 01:01:26.913959 <6>[ 7.958235] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10819 01:01:26.916979 <6>[ 7.958260] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10820 01:01:26.927394 <3>[ 7.972960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10821 01:01:26.934070 <6>[ 7.976670] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10822 01:01:26.940456 <6>[ 7.976700] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10823 01:01:26.951136 <6>[ 7.976703] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10824 01:01:26.958225 <6>[ 7.976711] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10825 01:01:26.964627 <6>[ 7.976724] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10826 01:01:26.974216 <6>[ 7.976736] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10827 01:01:26.977364 <6>[ 7.976748] pci 0000:00:00.0: PCI bridge to [bus 01]
10828 01:01:26.987702 <6>[ 7.976753] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10829 01:01:26.994156 <6>[ 7.976893] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10830 01:01:26.997674 <6>[ 7.977386] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10831 01:01:27.004135 <6>[ 7.977598] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10832 01:01:27.010458 <6>[ 7.979985] NET: Registered PF_BLUETOOTH protocol family
10833 01:01:27.017195 <3>[ 7.983661] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10834 01:01:27.023913 <6>[ 7.990975] Bluetooth: HCI device and connection manager initialized
10835 01:01:27.033859 <3>[ 7.996169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10836 01:01:27.040464 <3>[ 7.996175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10837 01:01:27.050323 <5>[ 7.998550] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10838 01:01:27.053638 <6>[ 8.001371] Bluetooth: HCI socket layer initialized
10839 01:01:27.060522 <6>[ 8.003103] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10840 01:01:27.070300 <4>[ 8.006995] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10841 01:01:27.077063 <4>[ 8.006995] Fallback method does not support PEC.
10842 01:01:27.083377 <3>[ 8.009818] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10843 01:01:27.090539 <6>[ 8.015428] Bluetooth: L2CAP socket layer initialized
10844 01:01:27.099880 <6>[ 8.015609] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10845 01:01:27.107096 <6>[ 8.015882] usbcore: registered new interface driver uvcvideo
10846 01:01:27.116523 <3>[ 8.023492] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10847 01:01:27.122868 <5>[ 8.024728] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10848 01:01:27.129435 <5>[ 8.025635] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10849 01:01:27.139631 <4>[ 8.025727] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10850 01:01:27.142810 <6>[ 8.025737] cfg80211: failed to load regulatory.db
10851 01:01:27.152707 <3>[ 8.025926] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10852 01:01:27.159295 <6>[ 8.030370] Bluetooth: SCO socket layer initialized
10853 01:01:27.165690 <3>[ 8.038430] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10854 01:01:27.175673 <3>[ 8.048448] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10855 01:01:27.182265 <6>[ 8.049153] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10856 01:01:27.188984 <3>[ 8.054418] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10857 01:01:27.198738 <3>[ 8.054423] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10858 01:01:27.205261 <3>[ 8.054461] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10859 01:01:27.212099 <6>[ 8.083977] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10860 01:01:27.221557 <6>[ 8.090038] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10861 01:01:27.225154 <6>[ 8.097142] usbcore: registered new interface driver btusb
10862 01:01:27.238313 <4>[ 8.097778] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10863 01:01:27.245010 <3>[ 8.097787] Bluetooth: hci0: Failed to load firmware file (-2)
10864 01:01:27.247920 <3>[ 8.097790] Bluetooth: hci0: Failed to set up firmware (-2)
10865 01:01:27.257982 <4>[ 8.097794] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10866 01:01:27.265348 <6>[ 8.102098] remoteproc remoteproc0: remote processor scp is now up
10867 01:01:27.275025 <6>[ 8.104534] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10868 01:01:27.280969 <6>[ 8.130081] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10869 01:01:27.291504 <6>[ 8.134688] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10870 01:01:27.297852 <6>[ 8.138769] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10871 01:01:27.321608 <6>[ 8.413851] mt7921e 0000:01:00.0: ASIC revision: 79610010
10872 01:01:27.425571 <6>[ 8.514418] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10873 01:01:27.428389 <6>[ 8.514418]
10874 01:01:27.432183 Begin: Loading essential drivers ... done.
10875 01:01:27.438499 Begin: Running /scripts/init-premount ... done.
10876 01:01:27.445317 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10877 01:01:27.451779 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10878 01:01:27.454800 Device /sys/class/net/eth0 found
10879 01:01:27.455218 done.
10880 01:01:27.465287 Begin: Waiting up to 180 secs for any network device to become available ... done.
10881 01:01:27.506508 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10882 01:01:27.515328 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10883 01:01:27.521654 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10884 01:01:27.528455 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10885 01:01:27.535042 host : mt8192-asurada-spherion-r0-cbg-9
10886 01:01:27.541379 domain : lava-rack
10887 01:01:27.545048 rootserver: 192.168.201.1 rootpath:
10888 01:01:27.547853 filename :
10889 01:01:27.691412 <6>[ 8.780653] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10890 01:01:27.694601 done.
10891 01:01:27.703151 Begin: Running /scripts/nfs-bottom ... done.
10892 01:01:27.719034 Begin: Running /scripts/init-bottom ... done.
10893 01:01:29.123777 <6>[ 10.216547] NET: Registered PF_INET6 protocol family
10894 01:01:29.131055 <6>[ 10.223730] Segment Routing with IPv6
10895 01:01:29.134573 <6>[ 10.227719] In-situ OAM (IOAM) with IPv6
10896 01:01:29.318719 <30>[ 10.384544] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10897 01:01:29.325064 <30>[ 10.417661] systemd[1]: Detected architecture arm64.
10898 01:01:29.335372
10899 01:01:29.338894 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10900 01:01:29.339488
10901 01:01:29.369145 <30>[ 10.461759] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10902 01:01:30.612980 <30>[ 11.702156] systemd[1]: Queued start job for default target graphical.target.
10903 01:01:30.655421 <30>[ 11.745071] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10904 01:01:30.662135 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10905 01:01:30.683834 <30>[ 11.773182] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10906 01:01:30.693762 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10907 01:01:30.711895 <30>[ 11.801121] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10908 01:01:30.721499 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10909 01:01:30.739908 <30>[ 11.829468] systemd[1]: Created slice user.slice - User and Session Slice.
10910 01:01:30.746777 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10911 01:01:30.769770 <30>[ 11.855879] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10912 01:01:30.780142 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10913 01:01:30.797578 <30>[ 11.883346] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10914 01:01:30.803716 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10915 01:01:30.832452 <30>[ 11.911765] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10916 01:01:30.842572 <30>[ 11.931723] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10917 01:01:30.848691 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10918 01:01:30.866077 <30>[ 11.955462] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10919 01:01:30.875554 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10920 01:01:30.893404 <30>[ 11.983156] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10921 01:01:30.903424 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10922 01:01:30.918770 <30>[ 12.011628] systemd[1]: Reached target paths.target - Path Units.
10923 01:01:30.929119 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10924 01:01:30.946656 <30>[ 12.035555] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10925 01:01:30.952603 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10926 01:01:30.966279 <30>[ 12.059056] systemd[1]: Reached target slices.target - Slice Units.
10927 01:01:30.976542 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10928 01:01:30.991106 <30>[ 12.083580] systemd[1]: Reached target swap.target - Swaps.
10929 01:01:30.997656 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10930 01:01:31.018619 <30>[ 12.107617] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10931 01:01:31.027984 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10932 01:01:31.046407 <30>[ 12.135593] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10933 01:01:31.056163 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10934 01:01:31.077472 <30>[ 12.167096] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10935 01:01:31.087595 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10936 01:01:31.107672 <30>[ 12.196848] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10937 01:01:31.117335 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10938 01:01:31.134372 <30>[ 12.223902] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10939 01:01:31.140794 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10940 01:01:31.159301 <30>[ 12.249035] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10941 01:01:31.169634 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10942 01:01:31.190024 <30>[ 12.279523] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10943 01:01:31.199888 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10944 01:01:31.218260 <30>[ 12.307652] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10945 01:01:31.228442 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10946 01:01:31.278017 <30>[ 12.367561] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10947 01:01:31.284760 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10948 01:01:31.304717 <30>[ 12.393854] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10949 01:01:31.310936 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10950 01:01:31.333163 <30>[ 12.422983] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10951 01:01:31.340058 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10952 01:01:31.365147 <30>[ 12.447694] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10953 01:01:31.380964 <30>[ 12.470486] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10954 01:01:31.391751 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10955 01:01:31.416035 <30>[ 12.505374] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10956 01:01:31.425624 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10957 01:01:31.447700 <30>[ 12.537318] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10958 01:01:31.454676 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10959 01:01:31.479634 <30>[ 12.569315] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10960 01:01:31.486219 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10961 01:01:31.496566 <6>[ 12.585907] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10962 01:01:31.512544 <30>[ 12.602032] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10963 01:01:31.522651 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10964 01:01:31.566464 <30>[ 12.656035] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10965 01:01:31.572903 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10966 01:01:31.600068 <30>[ 12.689696] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10967 01:01:31.606558 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10968 01:01:31.614101 <6>[ 12.707192] fuse: init (API version 7.37)
10969 01:01:31.670468 <30>[ 12.760086] systemd[1]: Starting systemd-journald.service - Journal Service...
10970 01:01:31.677078 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10971 01:01:31.713378 <30>[ 12.802672] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10972 01:01:31.719770 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10973 01:01:31.746447 <30>[ 12.832321] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10974 01:01:31.752481 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10975 01:01:31.774632 <30>[ 12.864130] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10976 01:01:31.784519 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10977 01:01:31.834674 <30>[ 12.924148] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10978 01:01:31.841405 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10979 01:01:31.860620 <3>[ 12.949705] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 01:01:31.874818 <30>[ 12.964359] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10981 01:01:31.881251 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10982 01:01:31.891544 <3>[ 12.981103] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 01:01:31.901920 <30>[ 12.991499] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10984 01:01:31.908557 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10985 01:01:31.926401 <30>[ 13.015601] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10986 01:01:31.932932 <3>[ 13.019952] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 01:01:31.943219 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10988 01:01:31.962690 <30>[ 13.051747] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10989 01:01:31.972736 <3>[ 13.052717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 01:01:31.978980 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10991 01:01:32.001408 <3>[ 13.090792] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 01:01:32.008182 <30>[ 13.092647] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10993 01:01:32.018245 <30>[ 13.107967] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10994 01:01:32.028524 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10995 01:01:32.045127 <3>[ 13.134393] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 01:01:32.055533 <30>[ 13.145024] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10997 01:01:32.062000 <30>[ 13.153314] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10998 01:01:32.072285 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10999 01:01:32.090672 <30>[ 13.179904] systemd[1]: modprobe@drm.service: Deactivated successfully.
11000 01:01:32.097606 <3>[ 13.183378] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 01:01:32.107078 <30>[ 13.187578] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11002 01:01:32.113598 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11003 01:01:32.126859 <3>[ 13.216143] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 01:01:32.137561 <30>[ 13.227043] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11005 01:01:32.147881 <30>[ 13.235367] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11006 01:01:32.157825 [[0;32m OK [0m] Finished [0<3>[ 13.245930] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 01:01:32.164342 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11008 01:01:32.180115 <30>[ 13.272111] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11009 01:01:32.189759 <3>[ 13.276260] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 01:01:32.199476 <30>[ 13.279915] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11011 01:01:32.205855 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11012 01:01:32.219657 <3>[ 13.309011] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11013 01:01:32.229427 <30>[ 13.319175] systemd[1]: modprobe@loop.service: Deactivated successfully.
11014 01:01:32.236160 <30>[ 13.326575] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11015 01:01:32.252719 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Mo<3>[ 13.340647] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11016 01:01:32.253214 dule loop.
11017 01:01:32.270505 <30>[ 13.359794] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11018 01:01:32.280754 <3>[ 13.367961] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11019 01:01:32.294227 <4>[ 13.376769] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11020 01:01:32.301241 <3>[ 13.392405] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11021 01:01:32.310488 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11022 01:01:32.334230 <30>[ 13.420190] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
11023 01:01:32.340488 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11024 01:01:32.358455 <30>[ 13.447795] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
11025 01:01:32.369251 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11026 01:01:32.385954 <30>[ 13.475420] systemd[1]: Started systemd-journald.service - Journal Service.
11027 01:01:32.392191 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11028 01:01:32.416353 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11029 01:01:32.436209 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11030 01:01:32.498261 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11031 01:01:32.520263 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11032 01:01:32.544626 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11033 01:01:32.602569 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11034 01:01:32.613768 <46>[ 13.703454] systemd-journald[308]: Received client request to flush runtime journal.
11035 01:01:32.682530 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11036 01:01:32.886488 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11037 01:01:32.908224 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11038 01:01:32.925566 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11039 01:01:33.216245 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11040 01:01:33.764965 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11041 01:01:34.044950 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11042 01:01:34.063204 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11043 01:01:34.129973 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11044 01:01:34.236802 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11045 01:01:34.254072 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11046 01:01:34.277462 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11047 01:01:34.330979 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11048 01:01:34.352281 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11049 01:01:34.565134 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11050 01:01:34.622707 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11051 01:01:34.697286 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11052 01:01:34.888685 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11053 01:01:34.982682 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11054 01:01:35.004276 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11055 01:01:35.038325 <6>[ 16.131943] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11056 01:01:35.096418 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11057 01:01:35.117785 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11058 01:01:35.185777 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11059 01:01:35.240033 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11060 01:01:35.257140 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11061 01:01:35.272978 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11062 01:01:35.297282 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11063 01:01:35.315123 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11064 01:01:35.373373 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11065 01:01:35.393236 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11066 01:01:35.414782 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11067 01:01:35.433392 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11068 01:01:35.448987 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11069 01:01:35.472110 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11070 01:01:35.492083 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11071 01:01:35.509314 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11072 01:01:35.527781 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11073 01:01:35.547979 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11074 01:01:35.564922 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11075 01:01:35.591229 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11076 01:01:35.608629 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11077 01:01:35.625039 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11078 01:01:35.670618 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11079 01:01:35.705284 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11080 01:01:35.806072 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11081 01:01:35.833455 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11082 01:01:35.854452 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11083 01:01:35.960944 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11084 01:01:35.977765 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11085 01:01:36.053964 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11086 01:01:36.079575 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11087 01:01:36.097113 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11088 01:01:36.115162 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11089 01:01:36.210180 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11090 01:01:36.229661 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11091 01:01:36.246932 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11092 01:01:36.285051 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11093 01:01:36.338136 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11094 01:01:36.415113
11095 01:01:36.418284 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11096 01:01:36.418374
11097 01:01:36.421538 debian-bookworm-arm64 login: root (automatic login)
11098 01:01:36.421619
11099 01:01:36.701361 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
11100 01:01:36.701500
11101 01:01:36.708419 The programs included with the Debian GNU/Linux system are free software;
11102 01:01:36.714402 the exact distribution terms for each program are described in the
11103 01:01:36.717731 individual files in /usr/share/doc/*/copyright.
11104 01:01:36.717813
11105 01:01:36.724304 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11106 01:01:36.727646 permitted by applicable law.
11107 01:01:36.820749 Matched prompt #10: / #
11109 01:01:36.821112 Setting prompt string to ['/ #']
11110 01:01:36.821240 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11112 01:01:36.821543 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11113 01:01:36.821665 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
11114 01:01:36.821762 Setting prompt string to ['/ #']
11115 01:01:36.821850 Forcing a shell prompt, looking for ['/ #']
11117 01:01:36.872096 / #
11118 01:01:36.872233 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11119 01:01:36.872334 Waiting using forced prompt support (timeout 00:02:30)
11120 01:01:36.877536
11121 01:01:36.877838 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11122 01:01:36.877966 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
11124 01:01:36.978356 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368620/extract-nfsrootfs-3_3i9sun'
11125 01:01:36.983448 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368620/extract-nfsrootfs-3_3i9sun'
11127 01:01:37.083988 / # export NFS_SERVER_IP='192.168.201.1'
11128 01:01:37.089071 export NFS_SERVER_IP='192.168.201.1'
11129 01:01:37.089385 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11130 01:01:37.089484 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
11131 01:01:37.089571 end: 2 depthcharge-action (duration 00:01:37) [common]
11132 01:01:37.089665 start: 3 lava-test-retry (timeout 00:30:00) [common]
11133 01:01:37.089757 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11134 01:01:37.089832 Using namespace: common
11136 01:01:37.190142 / # #
11137 01:01:37.190335 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11138 01:01:37.195658 #
11139 01:01:37.195921 Using /lava-14368620
11141 01:01:37.296282 / # export SHELL=/bin/sh
11142 01:01:37.301602 export SHELL=/bin/sh
11144 01:01:37.402115 / # . /lava-14368620/environment
11145 01:01:37.407131 . /lava-14368620/environment
11147 01:01:37.513642 / # /lava-14368620/bin/lava-test-runner /lava-14368620/0
11148 01:01:37.513761 Test shell timeout: 10s (minimum of the action and connection timeout)
11149 01:01:37.519203 /lava-14368620/bin/lava-test-runner /lava-14368620/0
11150 01:01:37.772714 + export TESTRUN_ID=0_lc-compliance
11151 01:01:37.778926 + cd /lava-14368620/0/tests/0_lc-compliance
11152 01:01:37.779044 + cat uuid
11153 01:01:37.788698 + UUID=14368620_1.6.2.3.1
11154 01:01:37.792154 + set +x
11155 01:01:37.795494 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14368620_1.6.2.3.1>
11156 01:01:37.795755 Received signal: <STARTRUN> 0_lc-compliance 14368620_1.6.2.3.1
11157 01:01:37.795830 Starting test lava.0_lc-compliance (14368620_1.6.2.3.1)
11158 01:01:37.795914 Skipping test definition patterns.
11159 01:01:37.798544 + /usr/bin/lc-compliance-parser.sh
11160 01:01:39.457543 [0:00:20.472622076] [415] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11161 01:01:39.461024 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11162 01:01:39.475710 [0:00:20.491005233] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11163 01:01:39.531224 [0:00:20.547192714] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11164 01:01:39.539122 [==========] Running 120 tests from 1 test suite.
11165 01:01:39.584489 [0:00:20.600625564] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11166 01:01:39.618758 [----------] Global test environment set-up.
11167 01:01:39.637629 [0:00:20.654875318] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11168 01:01:39.702436 [----------] 120 tests from CaptureTests/SingleStream
11169 01:01:39.782116 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11170 01:01:39.845502 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11171 01:01:39.845821 Received signal: <TESTSET> START CaptureTests/SingleStream
11172 01:01:39.845899 Starting test_set CaptureTests/SingleStream
11173 01:01:39.848383 Camera needs 4 requests, can't test only 1
11174 01:01:39.932786 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11175 01:01:40.018979
11176 01:01:40.069554 [0:00:21.091005064] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11177 01:01:40.112869 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (55 ms)
11178 01:01:40.229443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11179 01:01:40.229741 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11181 01:01:40.247866 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11182 01:01:40.302065 Camera needs 4 requests, can't test only 2
11183 01:01:40.390603 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11184 01:01:40.477864
11185 01:01:40.563298 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (54 ms)
11186 01:01:40.659232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11187 01:01:40.659543 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11189 01:01:40.676940 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11190 01:01:40.737655 Camera needs 4 requests, can't test only 3
11191 01:01:40.764246 [0:00:21.791736466] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11192 01:01:40.826345 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11193 01:01:40.906673
11194 01:01:40.992049 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (52 ms)
11195 01:01:41.092781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11196 01:01:41.093085 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11198 01:01:41.109882 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11199 01:01:41.163858 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (436 ms)
11200 01:01:41.253291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11201 01:01:41.253580 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11203 01:01:41.269238 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11204 01:01:41.322029 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (700 ms)
11205 01:01:41.420906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11206 01:01:41.421207 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11208 01:01:41.437490 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11209 01:01:42.012911 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1267 ms)
11210 01:01:42.022553 [0:00:23.059785108] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11211 01:01:42.123111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11212 01:01:42.123452 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11214 01:01:42.141473 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11215 01:01:43.831601 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1830 ms)
11216 01:01:43.841925 [0:00:24.890022185] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11217 01:01:43.933813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11218 01:01:43.934138 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11220 01:01:43.951699 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11221 01:01:46.558302 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2739 ms)
11222 01:01:46.568205 [0:00:27.629638901] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11223 01:01:46.663528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11224 01:01:46.663899 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11226 01:01:46.681240 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11227 01:01:50.755941 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4209 ms)
11228 01:01:50.765824 [0:00:31.839583677] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11229 01:01:50.890000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11230 01:01:50.890815 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11232 01:01:50.911279 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11233 01:01:56.757429 <6>[ 37.856492] vpu: disabling
11234 01:01:56.762879 <6>[ 37.861327] vproc2: disabling
11235 01:01:56.766053 <6>[ 37.865239] vproc1: disabling
11236 01:01:56.772407 <6>[ 37.871559] vaud18: disabling
11237 01:01:56.779954 <6>[ 37.875724] vsram_others: disabling
11238 01:01:56.785899 <6>[ 37.884762] va09: disabling
11239 01:01:56.792656 <6>[ 37.888261] vsram_md: disabling
11240 01:01:56.796021 <6>[ 37.892995] Vgpu: disabling
11241 01:01:57.333035 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6587 ms)
11242 01:01:57.342743 [0:00:38.426857876] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11243 01:01:57.395427 [0:00:38.480997351] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11244 01:01:57.452308 [0:00:38.537636536] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11245 01:01:57.464661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11246 01:01:57.465470 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11248 01:01:57.486152 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11249 01:01:57.508883 [0:00:38.594394905] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11250 01:01:57.558004 Camera needs 4 requests, can't test only 1
11251 01:01:57.662629 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11252 01:01:57.763905
11253 01:01:57.868656 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (54 ms)
11254 01:01:57.989246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11255 01:01:57.990006 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11257 01:01:58.011824 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11258 01:01:58.083641 Camera needs 4 requests, can't test only 2
11259 01:01:58.183494 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11260 01:01:58.206382 [0:00:39.292306134] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11261 01:01:58.287061
11262 01:01:58.392143 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (55 ms)
11263 01:01:58.516123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11264 01:01:58.516922 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11266 01:01:58.538601 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11267 01:01:58.608680 Camera needs 4 requests, can't test only 3
11268 01:01:58.715796 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11269 01:01:58.827510
11270 01:01:58.943434 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (56 ms)
11271 01:01:59.069137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11272 01:01:59.069911 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11274 01:01:59.093340 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11275 01:01:59.114773 [0:00:40.201658527] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11276 01:01:59.164127 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (697 ms)
11277 01:01:59.287331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11278 01:01:59.288096 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11280 01:01:59.309397 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11281 01:01:59.384993 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (909 ms)
11282 01:01:59.508893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11283 01:01:59.509662 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11285 01:01:59.528325 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11286 01:02:00.363285 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1258 ms)
11287 01:02:00.376429 [0:00:41.459980907] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11288 01:02:00.493857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11289 01:02:00.494804 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11291 01:02:00.513928 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11292 01:02:02.180023 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1817 ms)
11293 01:02:02.193594 [0:00:43.278064789] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11294 01:02:02.304955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11295 01:02:02.305711 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11297 01:02:02.327476 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11298 01:02:04.908650 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2730 ms)
11299 01:02:04.921984 [0:00:46.008239635] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11300 01:02:05.038158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11301 01:02:05.038955 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11303 01:02:05.059875 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11304 01:02:09.105060 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4197 ms)
11305 01:02:09.117915 [0:00:50.206377894] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11306 01:02:09.243427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11307 01:02:09.244170 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11309 01:02:09.263498 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11310 01:02:15.680902 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6577 ms)
11311 01:02:15.694057 [0:00:56.784679802] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11312 01:02:15.748116 [0:00:56.841633591] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11313 01:02:15.804627 [0:00:56.898230736] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11314 01:02:15.819826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11315 01:02:15.820525 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11317 01:02:15.840456 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11318 01:02:15.860619 [0:00:56.954431157] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11319 01:02:15.907507 Camera needs 4 requests, can't test only 1
11320 01:02:16.007195 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11321 01:02:16.109038
11322 01:02:16.216414 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (57 ms)
11323 01:02:16.333796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11324 01:02:16.334841 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11326 01:02:16.352849 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11327 01:02:16.417149 Camera needs 4 requests, can't test only 2
11328 01:02:16.513591 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11329 01:02:16.559485 [0:00:57.653495657] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11330 01:02:16.618680
11331 01:02:16.716485 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (56 ms)
11332 01:02:16.828432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11333 01:02:16.829198 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11335 01:02:16.850266 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11336 01:02:16.915103 Camera needs 4 requests, can't test only 3
11337 01:02:17.016317 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11338 01:02:17.111516
11339 01:02:17.215677 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (56 ms)
11340 01:02:17.333705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11341 01:02:17.334485 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11343 01:02:17.353314 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11344 01:02:17.412270 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (698 ms)
11345 01:02:17.467965 [0:00:58.562215716] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11346 01:02:17.536844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11347 01:02:17.537626 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11349 01:02:17.561398 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11350 01:02:17.629090 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (908 ms)
11351 01:02:17.743373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11352 01:02:17.743698 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11354 01:02:17.764304 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11355 01:02:18.715758 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1257 ms)
11356 01:02:18.728897 [0:00:59.819767474] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11357 01:02:18.838058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11358 01:02:18.838432 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11360 01:02:18.860316 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11361 01:02:20.531954 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1816 ms)
11362 01:02:20.544971 [0:01:01.636041550] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11363 01:02:20.650489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11364 01:02:20.651217 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11366 01:02:20.672038 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11367 01:02:23.260354 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2728 ms)
11368 01:02:23.273841 [0:01:04.364723018] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11369 01:02:23.379907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11370 01:02:23.380635 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11372 01:02:23.400194 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11373 01:02:27.457066 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4196 ms)
11374 01:02:27.470455 [0:01:08.561880870] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11375 01:02:27.575573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11376 01:02:27.576479 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11378 01:02:27.596358 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11379 01:02:34.033755 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6577 ms)
11380 01:02:34.046578 [0:01:15.139266363] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11381 01:02:34.098028 [0:01:15.194533027] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11382 01:02:34.154791 [0:01:15.251314239] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11383 01:02:34.167414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11384 01:02:34.168141 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11386 01:02:34.189777 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11387 01:02:34.211806 [0:01:15.308413222] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11388 01:02:34.256292 Camera needs 4 requests, can't test only 1
11389 01:02:34.357782 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11390 01:02:34.452230
11391 01:02:34.562483 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (54 ms)
11392 01:02:34.687628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11393 01:02:34.688394 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11395 01:02:34.711246 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11396 01:02:34.780180 Camera needs 4 requests, can't test only 2
11397 01:02:34.880444 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11398 01:02:34.907452 [0:01:16.004242086] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11399 01:02:34.992536
11400 01:02:35.103545 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (56 ms)
11401 01:02:35.224492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11402 01:02:35.225274 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11404 01:02:35.244091 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11405 01:02:35.313515 Camera needs 4 requests, can't test only 3
11406 01:02:35.416756 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11407 01:02:35.513265
11408 01:02:35.617944 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (57 ms)
11409 01:02:35.736769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11410 01:02:35.737547 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11412 01:02:35.760465 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11413 01:02:35.813378 [0:01:16.909791656] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11414 01:02:35.830584 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (697 ms)
11415 01:02:35.947566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11416 01:02:35.948494 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11418 01:02:35.966952 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11419 01:02:36.033369 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (903 ms)
11420 01:02:36.161244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11421 01:02:36.161981 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11423 01:02:36.184557 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11424 01:02:37.060083 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1256 ms)
11425 01:02:37.073279 [0:01:18.166948956] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11426 01:02:37.189696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11427 01:02:37.190536 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11429 01:02:37.212489 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11430 01:02:38.879107 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1818 ms)
11431 01:02:38.891921 [0:01:19.985698250] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11432 01:02:39.007222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11433 01:02:39.007979 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11435 01:02:39.027844 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11436 01:02:41.607404 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2728 ms)
11437 01:02:41.620468 [0:01:22.714167361] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11438 01:02:41.736074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11439 01:02:41.736833 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11441 01:02:41.759472 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11442 01:02:45.805574 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4199 ms)
11443 01:02:45.818589 [0:01:26.913903238] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11444 01:02:45.932628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11445 01:02:45.933447 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11447 01:02:45.952574 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11448 01:02:52.385092 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6579 ms)
11449 01:02:52.398391 [0:01:33.494058471] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11450 01:02:52.452927 [0:01:33.551441812] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11451 01:02:52.509589 [0:01:33.608036229] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11452 01:02:52.515812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11453 01:02:52.516545 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11455 01:02:52.533658 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11456 01:02:52.564159 [0:01:33.663000184] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11457 01:02:52.605197 Camera needs 4 requests, can't test only 1
11458 01:02:52.708276 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11459 01:02:52.812379
11460 01:02:52.915792 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (57 ms)
11461 01:02:53.037238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11462 01:02:53.038036 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11464 01:02:53.058258 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11465 01:02:53.125302 Camera needs 4 requests, can't test only 2
11466 01:02:53.234518 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11467 01:02:53.339611
11468 01:02:53.438862 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (58 ms)
11469 01:02:53.555814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11470 01:02:53.556580 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11472 01:02:53.577557 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11473 01:02:53.644343 Camera needs 4 requests, can't test only 3
11474 01:02:53.751456 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11475 01:02:53.849043
11476 01:02:53.953004 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (53 ms)
11477 01:02:54.069156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11478 01:02:54.069929 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11480 01:02:54.088309 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11481 01:02:54.635961 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2080 ms)
11482 01:02:54.649310 [0:01:35.744765313] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11483 01:02:54.753730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11484 01:02:54.754508 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11486 01:02:54.773646 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11487 01:02:57.356116 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2720 ms)
11488 01:02:57.368713 [0:01:38.465078621] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11489 01:02:57.479145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11490 01:02:57.479892 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11492 01:02:57.501749 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11493 01:03:01.120419 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3764 ms)
11494 01:03:01.133163 [0:01:42.229887524] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11495 01:03:01.249465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11496 01:03:01.250347 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11498 01:03:01.268855 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11499 01:03:06.563933 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5444 ms)
11500 01:03:06.577132 [0:01:47.673923236] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11501 01:03:06.699372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11502 01:03:06.700198 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11504 01:03:06.718996 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11505 01:03:14.740179 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8176 ms)
11506 01:03:14.752998 [0:01:55.851262834] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11507 01:03:14.886333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11508 01:03:14.887073 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11510 01:03:14.907516 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11511 01:03:27.324628 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12585 ms)
11512 01:03:27.337589 [0:02:08.437211093] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11513 01:03:27.456501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11514 01:03:27.457290 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11516 01:03:27.475261 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11517 01:03:47.049580 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19726 ms)
11518 01:03:47.062739 [0:02:28.164152133] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11519 01:03:47.115698 [0:02:28.220288672] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11520 01:03:47.174856 [0:02:28.279438210] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11521 01:03:47.181476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11522 01:03:47.182221 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11524 01:03:47.200215 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11525 01:03:47.230039 [0:02:28.334947518] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11526 01:03:47.267633 Camera needs 4 requests, can't test only 1
11527 01:03:47.370269 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11528 01:03:47.468363
11529 01:03:47.577125 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (56 ms)
11530 01:03:47.697275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11531 01:03:47.698039 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11533 01:03:47.715976 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11534 01:03:47.784363 Camera needs 4 requests, can't test only 2
11535 01:03:47.890624 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11536 01:03:47.989598
11537 01:03:48.090453 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (58 ms)
11538 01:03:48.207769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11539 01:03:48.208529 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11541 01:03:48.226365 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11542 01:03:48.294054 Camera needs 4 requests, can't test only 3
11543 01:03:48.401368 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11544 01:03:48.506158
11545 01:03:48.617210 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (57 ms)
11546 01:03:48.732557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11547 01:03:48.733469 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11549 01:03:48.748454 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11550 01:03:49.302645 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2077 ms)
11551 01:03:49.312809 [0:02:30.413928750] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11552 01:03:49.431404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11553 01:03:49.432157 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11555 01:03:49.450120 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11556 01:03:52.016156 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2713 ms)
11557 01:03:52.025672 [0:02:33.127953827] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11558 01:03:52.146744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11559 01:03:52.147627 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11561 01:03:52.166751 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11562 01:03:55.780037 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3763 ms)
11563 01:03:55.789405 [0:02:36.891994367] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11564 01:03:55.903532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11565 01:03:55.904346 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11567 01:03:55.920413 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11568 01:04:01.223042 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5443 ms)
11569 01:04:01.232641 [0:02:42.335817752] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11570 01:04:01.350261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11571 01:04:01.351146 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11573 01:04:01.368684 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11574 01:04:09.398958 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8177 ms)
11575 01:04:09.408659 [0:02:50.512647214] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11576 01:04:09.530152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11577 01:04:09.530962 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11579 01:04:09.543791 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11580 01:04:21.982906 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12585 ms)
11581 01:04:21.992719 [0:03:03.098236754] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11582 01:04:22.131025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11583 01:04:22.131783 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11585 01:04:22.150278 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11586 01:04:41.707877 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19727 ms)
11587 01:04:41.717645 [0:03:22.825628370] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11588 01:04:41.771756 [0:03:22.882856832] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11589 01:04:41.828444 [0:03:22.939590755] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11590 01:04:41.835256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11591 01:04:41.836101 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11593 01:04:41.857095 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11594 01:04:41.885429 [0:03:22.996431370] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11595 01:04:41.927887 Camera needs 4 requests, can't test only 1
11596 01:04:42.036359 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11597 01:04:42.137587
11598 01:04:42.245904 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (57 ms)
11599 01:04:42.361201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11600 01:04:42.362062 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11602 01:04:42.377627 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11603 01:04:42.444568 Camera needs 4 requests, can't test only 2
11604 01:04:42.550738 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11605 01:04:42.658647
11606 01:04:42.773891 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (57 ms)
11607 01:04:42.896487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11608 01:04:42.897219 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11610 01:04:42.914854 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11611 01:04:42.980063 Camera needs 4 requests, can't test only 3
11612 01:04:43.082869 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11613 01:04:43.176618
11614 01:04:43.290602 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (56 ms)
11615 01:04:43.416387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11616 01:04:43.417335 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11618 01:04:43.435252 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11619 01:04:43.965898 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2086 ms)
11620 01:04:43.975107 [0:03:25.083168447] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11621 01:04:44.101268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11622 01:04:44.102048 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11624 01:04:44.118270 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11625 01:04:46.680079 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2714 ms)
11626 01:04:46.690194 [0:03:27.798048140] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11627 01:04:46.810048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11628 01:04:46.810844 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11630 01:04:46.829775 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11631 01:04:50.443296 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3763 ms)
11632 01:04:50.452918 [0:03:31.561926832] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11633 01:04:50.573775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11634 01:04:50.574657 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11636 01:04:50.592896 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11637 01:04:55.886792 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5444 ms)
11638 01:04:55.896771 [0:03:37.005871217] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11639 01:04:56.016296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11640 01:04:56.017067 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11642 01:04:56.033907 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11643 01:05:04.062977 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8176 ms)
11644 01:05:04.073118 [0:03:45.183284218] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11645 01:05:04.188796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11646 01:05:04.189624 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11648 01:05:04.209215 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11649 01:05:16.646752 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12584 ms)
11650 01:05:16.656597 [0:03:57.768161296] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11651 01:05:16.775957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11652 01:05:16.776723 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11654 01:05:16.793830 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11655 01:31:37.090067 Marking unfinished test run as failed
11658 01:31:37.091661 end: 3.1 lava-test-shell (duration 00:30:00) [common]
11660 01:31:37.092624 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 1800 seconds'
11662 01:31:37.093435 end: 3 lava-test-retry (duration 00:30:00) [common]
11664 01:31:37.094748 Cleaning after the job
11665 01:31:37.095219 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/ramdisk
11666 01:31:37.105563 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/kernel
11667 01:31:37.135213 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/dtb
11668 01:31:37.135540 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/nfsrootfs
11669 01:31:37.181268 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368620/tftp-deploy-he9vtqyu/modules
11670 01:31:37.186958 start: 4.1 power-off (timeout 00:00:30) [common]
11671 01:31:37.187147 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11672 01:31:37.398685 >> Command sent successfully.
11673 01:31:37.408708 Returned 0 in 0 seconds
11674 01:31:37.509977 end: 4.1 power-off (duration 00:00:00) [common]
11676 01:31:37.511942 start: 4.2 read-feedback (timeout 00:10:00) [common]
11677 01:31:37.513348 Listened to connection for namespace 'common' for up to 1s
11678 01:31:38.513978 Finalising connection for namespace 'common'
11679 01:31:38.514731 Disconnecting from shell: Finalise
11680 01:31:38.615936 end: 4.2 read-feedback (duration 00:00:01) [common]
11681 01:31:38.616557 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368620
11682 01:31:38.911479 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368620
11683 01:31:38.911677 TestError: A test failed to run, look at the error message.