Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 00:54:45.595264 lava-dispatcher, installed at version: 2024.03
2 00:54:45.595475 start: 0 validate
3 00:54:45.595609 Start time: 2024-06-16 00:54:45.595602+00:00 (UTC)
4 00:54:45.595736 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:54:45.595866 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:54:45.848634 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:54:45.849454 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:55:15.617933 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:55:15.618607 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:55:15.871900 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:55:15.872630 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:55:18.621939 validate duration: 33.03
14 00:55:18.622595 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:55:18.622875 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:55:18.623085 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:55:18.623352 Not decompressing ramdisk as can be used compressed.
18 00:55:18.623540 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 00:55:18.623684 saving as /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/ramdisk/rootfs.cpio.gz
20 00:55:18.623832 total size: 28105535 (26 MB)
21 00:55:18.874275 progress 0 % (0 MB)
22 00:55:18.881574 progress 5 % (1 MB)
23 00:55:18.888904 progress 10 % (2 MB)
24 00:55:18.896190 progress 15 % (4 MB)
25 00:55:18.903468 progress 20 % (5 MB)
26 00:55:18.910834 progress 25 % (6 MB)
27 00:55:18.918095 progress 30 % (8 MB)
28 00:55:18.925415 progress 35 % (9 MB)
29 00:55:18.932614 progress 40 % (10 MB)
30 00:55:18.939761 progress 45 % (12 MB)
31 00:55:18.947088 progress 50 % (13 MB)
32 00:55:18.954361 progress 55 % (14 MB)
33 00:55:18.961609 progress 60 % (16 MB)
34 00:55:18.968855 progress 65 % (17 MB)
35 00:55:18.976223 progress 70 % (18 MB)
36 00:55:18.983524 progress 75 % (20 MB)
37 00:55:18.990933 progress 80 % (21 MB)
38 00:55:18.998335 progress 85 % (22 MB)
39 00:55:19.005412 progress 90 % (24 MB)
40 00:55:19.012582 progress 95 % (25 MB)
41 00:55:19.019701 progress 100 % (26 MB)
42 00:55:19.019997 26 MB downloaded in 0.40 s (67.66 MB/s)
43 00:55:19.020155 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:55:19.020394 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:55:19.020481 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:55:19.020565 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:55:19.020700 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:55:19.020770 saving as /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/kernel/Image
50 00:55:19.020833 total size: 54813184 (52 MB)
51 00:55:19.020895 No compression specified
52 00:55:19.022067 progress 0 % (0 MB)
53 00:55:19.036069 progress 5 % (2 MB)
54 00:55:19.050512 progress 10 % (5 MB)
55 00:55:19.064972 progress 15 % (7 MB)
56 00:55:19.079776 progress 20 % (10 MB)
57 00:55:19.094653 progress 25 % (13 MB)
58 00:55:19.110251 progress 30 % (15 MB)
59 00:55:19.125272 progress 35 % (18 MB)
60 00:55:19.140063 progress 40 % (20 MB)
61 00:55:19.154959 progress 45 % (23 MB)
62 00:55:19.169989 progress 50 % (26 MB)
63 00:55:19.184760 progress 55 % (28 MB)
64 00:55:19.199144 progress 60 % (31 MB)
65 00:55:19.213711 progress 65 % (34 MB)
66 00:55:19.228159 progress 70 % (36 MB)
67 00:55:19.243235 progress 75 % (39 MB)
68 00:55:19.257603 progress 80 % (41 MB)
69 00:55:19.271866 progress 85 % (44 MB)
70 00:55:19.286522 progress 90 % (47 MB)
71 00:55:19.301014 progress 95 % (49 MB)
72 00:55:19.316096 progress 100 % (52 MB)
73 00:55:19.316400 52 MB downloaded in 0.30 s (176.86 MB/s)
74 00:55:19.316559 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:55:19.316799 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:55:19.316907 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:55:19.317031 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:55:19.317198 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:55:19.317303 saving as /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/dtb/mt8192-asurada-spherion-r0.dtb
81 00:55:19.317369 total size: 47258 (0 MB)
82 00:55:19.317437 No compression specified
83 00:55:19.318609 progress 69 % (0 MB)
84 00:55:19.318892 progress 100 % (0 MB)
85 00:55:19.319053 0 MB downloaded in 0.00 s (26.80 MB/s)
86 00:55:19.319213 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:55:19.319492 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:55:19.319586 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:55:19.319672 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:55:19.319791 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:55:19.319862 saving as /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/modules/modules.tar
93 00:55:19.319926 total size: 8617404 (8 MB)
94 00:55:19.319993 Using unxz to decompress xz
95 00:55:19.324570 progress 0 % (0 MB)
96 00:55:19.344623 progress 5 % (0 MB)
97 00:55:19.373868 progress 10 % (0 MB)
98 00:55:19.404148 progress 15 % (1 MB)
99 00:55:19.428986 progress 20 % (1 MB)
100 00:55:19.453436 progress 25 % (2 MB)
101 00:55:19.477841 progress 30 % (2 MB)
102 00:55:19.505002 progress 35 % (2 MB)
103 00:55:19.530613 progress 40 % (3 MB)
104 00:55:19.554211 progress 45 % (3 MB)
105 00:55:19.579145 progress 50 % (4 MB)
106 00:55:19.605389 progress 55 % (4 MB)
107 00:55:19.630929 progress 60 % (4 MB)
108 00:55:19.656130 progress 65 % (5 MB)
109 00:55:19.683975 progress 70 % (5 MB)
110 00:55:19.708789 progress 75 % (6 MB)
111 00:55:19.735397 progress 80 % (6 MB)
112 00:55:19.761236 progress 85 % (7 MB)
113 00:55:19.788308 progress 90 % (7 MB)
114 00:55:19.814564 progress 95 % (7 MB)
115 00:55:19.840427 progress 100 % (8 MB)
116 00:55:19.846656 8 MB downloaded in 0.53 s (15.60 MB/s)
117 00:55:19.846932 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:55:19.847196 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:55:19.847310 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:55:19.847464 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:55:19.847551 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:55:19.847645 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:55:19.847879 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd
125 00:55:19.848013 makedir: /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin
126 00:55:19.848121 makedir: /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/tests
127 00:55:19.848220 makedir: /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/results
128 00:55:19.848337 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-add-keys
129 00:55:19.848484 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-add-sources
130 00:55:19.848617 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-background-process-start
131 00:55:19.848769 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-background-process-stop
132 00:55:19.848915 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-common-functions
133 00:55:19.849060 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-echo-ipv4
134 00:55:19.849211 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-install-packages
135 00:55:19.849382 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-installed-packages
136 00:55:19.849529 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-os-build
137 00:55:19.849677 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-probe-channel
138 00:55:19.849851 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-probe-ip
139 00:55:19.850020 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-target-ip
140 00:55:19.850165 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-target-mac
141 00:55:19.850309 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-target-storage
142 00:55:19.850460 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-test-case
143 00:55:19.850632 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-test-event
144 00:55:19.850777 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-test-feedback
145 00:55:19.850922 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-test-raise
146 00:55:19.851069 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-test-reference
147 00:55:19.851241 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-test-runner
148 00:55:19.851410 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-test-set
149 00:55:19.851558 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-test-shell
150 00:55:19.851712 Updating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-install-packages (oe)
151 00:55:19.851910 Updating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/bin/lava-installed-packages (oe)
152 00:55:19.852050 Creating /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/environment
153 00:55:19.852167 LAVA metadata
154 00:55:19.852253 - LAVA_JOB_ID=14368601
155 00:55:19.852357 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:55:19.852515 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:55:19.852619 skipped lava-vland-overlay
158 00:55:19.852739 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:55:19.852873 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:55:19.852984 skipped lava-multinode-overlay
161 00:55:19.853103 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:55:19.853244 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:55:19.853368 Loading test definitions
164 00:55:19.853508 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:55:19.853623 Using /lava-14368601 at stage 0
166 00:55:19.854065 uuid=14368601_1.5.2.3.1 testdef=None
167 00:55:19.854192 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:55:19.854328 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:55:19.855068 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:55:19.855448 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:55:19.856087 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:55:19.856349 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:55:19.857223 runner path: /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14368601_1.5.2.3.1
176 00:55:19.857440 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:55:19.857799 Creating lava-test-runner.conf files
179 00:55:19.857883 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368601/lava-overlay-agxtv3pd/lava-14368601/0 for stage 0
180 00:55:19.858003 - 0_v4l2-compliance-mtk-vcodec-enc
181 00:55:19.858121 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:55:19.858258 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:55:19.865703 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:55:19.865842 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:55:19.865958 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:55:19.866065 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:55:19.866171 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:55:20.807550 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:55:20.807943 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 00:55:20.808105 extracting modules file /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368601/extract-overlay-ramdisk-81tuz3m2/ramdisk
191 00:55:21.041215 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:55:21.041474 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 00:55:21.041609 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368601/compress-overlay-3m_qnbpo/overlay-1.5.2.4.tar.gz to ramdisk
194 00:55:21.041692 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368601/compress-overlay-3m_qnbpo/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368601/extract-overlay-ramdisk-81tuz3m2/ramdisk
195 00:55:21.048708 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:55:21.048846 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 00:55:21.048989 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:55:21.049100 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 00:55:21.049225 Building ramdisk /var/lib/lava/dispatcher/tmp/14368601/extract-overlay-ramdisk-81tuz3m2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368601/extract-overlay-ramdisk-81tuz3m2/ramdisk
200 00:55:21.785910 >> 275951 blocks
201 00:55:25.955062 rename /var/lib/lava/dispatcher/tmp/14368601/extract-overlay-ramdisk-81tuz3m2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/ramdisk/ramdisk.cpio.gz
202 00:55:25.955552 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 00:55:25.955722 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 00:55:25.955872 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 00:55:25.956030 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/kernel/Image']
206 00:55:40.322673 Returned 0 in 14 seconds
207 00:55:40.423326 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/kernel/image.itb
208 00:55:41.074070 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:55:41.074565 output: Created: Sun Jun 16 01:55:40 2024
210 00:55:41.074691 output: Image 0 (kernel-1)
211 00:55:41.074795 output: Description:
212 00:55:41.074902 output: Created: Sun Jun 16 01:55:40 2024
213 00:55:41.075016 output: Type: Kernel Image
214 00:55:41.075128 output: Compression: lzma compressed
215 00:55:41.075237 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
216 00:55:41.075351 output: Architecture: AArch64
217 00:55:41.075465 output: OS: Linux
218 00:55:41.075576 output: Load Address: 0x00000000
219 00:55:41.075686 output: Entry Point: 0x00000000
220 00:55:41.075798 output: Hash algo: crc32
221 00:55:41.075908 output: Hash value: f6f06660
222 00:55:41.076018 output: Image 1 (fdt-1)
223 00:55:41.076121 output: Description: mt8192-asurada-spherion-r0
224 00:55:41.076227 output: Created: Sun Jun 16 01:55:40 2024
225 00:55:41.076334 output: Type: Flat Device Tree
226 00:55:41.076441 output: Compression: uncompressed
227 00:55:41.076545 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:55:41.076650 output: Architecture: AArch64
229 00:55:41.076753 output: Hash algo: crc32
230 00:55:41.076856 output: Hash value: 0f8e4d2e
231 00:55:41.076958 output: Image 2 (ramdisk-1)
232 00:55:41.077088 output: Description: unavailable
233 00:55:41.077192 output: Created: Sun Jun 16 01:55:40 2024
234 00:55:41.077319 output: Type: RAMDisk Image
235 00:55:41.077424 output: Compression: Unknown Compression
236 00:55:41.077529 output: Data Size: 41212186 Bytes = 40246.28 KiB = 39.30 MiB
237 00:55:41.077632 output: Architecture: AArch64
238 00:55:41.077735 output: OS: Linux
239 00:55:41.077840 output: Load Address: unavailable
240 00:55:41.077944 output: Entry Point: unavailable
241 00:55:41.078049 output: Hash algo: crc32
242 00:55:41.078191 output: Hash value: 9adffc38
243 00:55:41.078323 output: Default Configuration: 'conf-1'
244 00:55:41.078425 output: Configuration 0 (conf-1)
245 00:55:41.078528 output: Description: mt8192-asurada-spherion-r0
246 00:55:41.078630 output: Kernel: kernel-1
247 00:55:41.078732 output: Init Ramdisk: ramdisk-1
248 00:55:41.078835 output: FDT: fdt-1
249 00:55:41.078939 output: Loadables: kernel-1
250 00:55:41.079043 output:
251 00:55:41.079361 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 00:55:41.079535 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 00:55:41.079710 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 00:55:41.079869 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 00:55:41.080000 No LXC device requested
256 00:55:41.080152 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:55:41.080319 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 00:55:41.080452 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:55:41.080574 Checking files for TFTP limit of 4294967296 bytes.
260 00:55:41.081379 end: 1 tftp-deploy (duration 00:00:22) [common]
261 00:55:41.081539 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:55:41.081688 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:55:41.081886 substitutions:
264 00:55:41.082002 - {DTB}: 14368601/tftp-deploy-kt0gpwp2/dtb/mt8192-asurada-spherion-r0.dtb
265 00:55:41.082115 - {INITRD}: 14368601/tftp-deploy-kt0gpwp2/ramdisk/ramdisk.cpio.gz
266 00:55:41.082222 - {KERNEL}: 14368601/tftp-deploy-kt0gpwp2/kernel/Image
267 00:55:41.082328 - {LAVA_MAC}: None
268 00:55:41.082435 - {PRESEED_CONFIG}: None
269 00:55:41.082540 - {PRESEED_LOCAL}: None
270 00:55:41.082645 - {RAMDISK}: 14368601/tftp-deploy-kt0gpwp2/ramdisk/ramdisk.cpio.gz
271 00:55:41.082752 - {ROOT_PART}: None
272 00:55:41.082858 - {ROOT}: None
273 00:55:41.082962 - {SERVER_IP}: 192.168.201.1
274 00:55:41.083067 - {TEE}: None
275 00:55:41.083172 Parsed boot commands:
276 00:55:41.083276 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:55:41.083590 Parsed boot commands: tftpboot 192.168.201.1 14368601/tftp-deploy-kt0gpwp2/kernel/image.itb 14368601/tftp-deploy-kt0gpwp2/kernel/cmdline
278 00:55:41.083756 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:55:41.083918 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:55:41.084074 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:55:41.084222 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:55:41.084346 Not connected, no need to disconnect.
283 00:55:41.084476 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:55:41.084617 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:55:41.084740 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 00:55:41.089446 Setting prompt string to ['lava-test: # ']
287 00:55:41.089980 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:55:41.090172 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:55:41.090370 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:55:41.090555 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:55:41.090872 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
292 00:55:55.064221 Returned 0 in 13 seconds
293 00:55:55.165188 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 00:55:55.165560 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 00:55:55.165663 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 00:55:55.165751 Setting prompt string to 'Starting depthcharge on Spherion...'
298 00:55:55.165820 Changing prompt to 'Starting depthcharge on Spherion...'
299 00:55:55.165890 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 00:55:55.166288 [Enter `^Ec?' for help]
301 00:55:55.166371
302 00:55:55.166442
303 00:55:55.166507 F0: 102B 0000
304 00:55:55.166568
305 00:55:55.166628 F3: 1001 0000 [0200]
306 00:55:55.166688
307 00:55:55.166747 F3: 1001 0000
308 00:55:55.166808
309 00:55:55.166867 F7: 102D 0000
310 00:55:55.166960
311 00:55:55.167079 F1: 0000 0000
312 00:55:55.167205
313 00:55:55.167263 V0: 0000 0000 [0001]
314 00:55:55.167318
315 00:55:55.167373 00: 0007 8000
316 00:55:55.167432
317 00:55:55.167490 01: 0000 0000
318 00:55:55.167547
319 00:55:55.167601 BP: 0C00 0209 [0000]
320 00:55:55.167655
321 00:55:55.167709 G0: 1182 0000
322 00:55:55.167763
323 00:55:55.167816 EC: 0000 0021 [4000]
324 00:55:55.167870
325 00:55:55.167923 S7: 0000 0000 [0000]
326 00:55:55.167979
327 00:55:55.168033 CC: 0000 0000 [0001]
328 00:55:55.168087
329 00:55:55.168140 T0: 0000 0040 [010F]
330 00:55:55.168194
331 00:55:55.168246 Jump to BL
332 00:55:55.168300
333 00:55:55.168354
334 00:55:55.168407
335 00:55:55.168460 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 00:55:55.168520 ARM64: Exception handlers installed.
337 00:55:55.168576 ARM64: Testing exception
338 00:55:55.168630 ARM64: Done test exception
339 00:55:55.168683 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 00:55:55.168738 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 00:55:55.168793 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 00:55:55.168847 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 00:55:55.168902 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 00:55:55.168956 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 00:55:55.169010 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 00:55:55.169068 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 00:55:55.169123 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 00:55:55.169177 WDT: Last reset was cold boot
349 00:55:55.169246 SPI1(PAD0) initialized at 2873684 Hz
350 00:55:55.169331 SPI5(PAD0) initialized at 992727 Hz
351 00:55:55.169386 VBOOT: Loading verstage.
352 00:55:55.169441 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 00:55:55.169495 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 00:55:55.169550 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 00:55:55.169608 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 00:55:55.169664 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 00:55:55.169719 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 00:55:55.169773 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 00:55:55.169827
360 00:55:55.169881
361 00:55:55.169934 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 00:55:55.169990 ARM64: Exception handlers installed.
363 00:55:55.170044 ARM64: Testing exception
364 00:55:55.170098 ARM64: Done test exception
365 00:55:55.170155 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 00:55:55.170210 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 00:55:55.170264 Probing TPM: . done!
368 00:55:55.170317 TPM ready after 0 ms
369 00:55:55.170372 Connected to device vid:did:rid of 1ae0:0028:00
370 00:55:55.170427 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
371 00:55:55.170482 Initialized TPM device CR50 revision 0
372 00:55:55.170536 tlcl_send_startup: Startup return code is 0
373 00:55:55.170591 TPM: setup succeeded
374 00:55:55.170645 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 00:55:55.170699 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 00:55:55.170756 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 00:55:55.170812 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:55:55.170867 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 00:55:55.170921 in-header: 03 07 00 00 08 00 00 00
380 00:55:55.170975 in-data: aa e4 47 04 13 02 00 00
381 00:55:55.171028 Chrome EC: UHEPI supported
382 00:55:55.171082 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 00:55:55.171136 in-header: 03 a9 00 00 08 00 00 00
384 00:55:55.171190 in-data: 84 60 60 08 00 00 00 00
385 00:55:55.171243 Phase 1
386 00:55:55.171299 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 00:55:55.171353 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 00:55:55.171407 VB2:vb2_check_recovery() Recovery was requested manually
389 00:55:55.171462 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 00:55:55.171516 Recovery requested (1009000e)
391 00:55:55.171569 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:55:55.171624 tlcl_extend: response is 0
393 00:55:55.171678 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:55:55.171731 tlcl_extend: response is 0
395 00:55:55.171785 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:55:55.171839 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 00:55:55.171896 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 00:55:55.171953
399 00:55:55.172006
400 00:55:55.172060 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:55:55.172114 ARM64: Exception handlers installed.
402 00:55:55.172168 ARM64: Testing exception
403 00:55:55.172222 ARM64: Done test exception
404 00:55:55.172275 pmic_efuse_setting: Set efuses in 11 msecs
405 00:55:55.172332 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:55:55.172386 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:55:55.172442 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:55:55.172689 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:55:55.172759 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:55:55.172816 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:55:55.172871 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:55:55.172926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:55:55.173028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:55:55.173088 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:55:55.173144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:55:55.173199 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:55:55.173254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:55:55.173337 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:55:55.173391 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:55:55.173446 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:55:55.173500 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:55:55.173558 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:55:55.173644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:55:55.173729 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:55:55.173814 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:55:55.173898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:55:55.173982 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:55:55.174067 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:55:55.174153 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:55:55.174240 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:55:55.174325 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:55:55.174409 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:55:55.174493 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:55:55.174577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:55:55.174660 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:55:55.174737 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:55:55.174793 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:55:55.174847 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:55:55.174901 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:55:55.174955 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:55:55.175008 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:55:55.175062 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:55:55.175115 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:55:55.175169 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:55:55.175229 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:55:55.175329 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:55:55.175399 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:55:55.175456 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:55:55.175510 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:55:55.175565 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:55:55.175620 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:55:55.175673 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:55:55.175727 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:55:55.175785 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:55:55.175840 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:55:55.175893 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:55:55.175946 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 00:55:55.176001 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:55:55.176056 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:55:55.176110 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:55:55.176165 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:55:55.176219 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:55:55.176275 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:55:55.176330 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:55:55.176386 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
466 00:55:55.176440 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:55:55.176494 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
468 00:55:55.176548 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:55:55.176602 [RTC]rtc_get_frequency_meter,154: input=15, output=854
470 00:55:55.176656 [RTC]rtc_get_frequency_meter,154: input=7, output=725
471 00:55:55.176710 [RTC]rtc_get_frequency_meter,154: input=11, output=788
472 00:55:55.176763 [RTC]rtc_get_frequency_meter,154: input=13, output=821
473 00:55:55.176820 [RTC]rtc_get_frequency_meter,154: input=12, output=806
474 00:55:55.176874 [RTC]rtc_get_frequency_meter,154: input=11, output=789
475 00:55:55.176927 [RTC]rtc_get_frequency_meter,154: input=12, output=806
476 00:55:55.176980 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
477 00:55:55.177034 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
478 00:55:55.177339 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 00:55:55.177407 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 00:55:55.177466 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 00:55:55.177521 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 00:55:55.177576 ADC[4]: Raw value=904802 ID=7
483 00:55:55.177630 ADC[3]: Raw value=213546 ID=1
484 00:55:55.177685 RAM Code: 0x71
485 00:55:55.177739 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 00:55:55.177795 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 00:55:55.177850 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 00:55:55.177905 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 00:55:55.177964 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 00:55:55.178019 in-header: 03 07 00 00 08 00 00 00
491 00:55:55.178073 in-data: aa e4 47 04 13 02 00 00
492 00:55:55.178126 Chrome EC: UHEPI supported
493 00:55:55.178180 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 00:55:55.178235 in-header: 03 a9 00 00 08 00 00 00
495 00:55:55.178289 in-data: 84 60 60 08 00 00 00 00
496 00:55:55.178343 MRC: failed to locate region type 0.
497 00:55:55.178397 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 00:55:55.178454 DRAM-K: Running full calibration
499 00:55:55.178511 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 00:55:55.178566 header.status = 0x0
501 00:55:55.178620 header.version = 0x6 (expected: 0x6)
502 00:55:55.178674 header.size = 0xd00 (expected: 0xd00)
503 00:55:55.178728 header.flags = 0x0
504 00:55:55.178782 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 00:55:55.178836 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 00:55:55.178891 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 00:55:55.178945 dram_init: ddr_geometry: 2
508 00:55:55.179002 [EMI] MDL number = 2
509 00:55:55.179056 [EMI] Get MDL freq = 0
510 00:55:55.179109 dram_init: ddr_type: 0
511 00:55:55.179162 is_discrete_lpddr4: 1
512 00:55:55.179215 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 00:55:55.179269
514 00:55:55.179322
515 00:55:55.179375 [Bian_co] ETT version 0.0.0.1
516 00:55:55.179429 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 00:55:55.179483
518 00:55:55.179550 dramc_set_vcore_voltage set vcore to 650000
519 00:55:55.179636 Read voltage for 800, 4
520 00:55:55.179719 Vio18 = 0
521 00:55:55.179802 Vcore = 650000
522 00:55:55.179885 Vdram = 0
523 00:55:55.179967 Vddq = 0
524 00:55:55.180050 Vmddr = 0
525 00:55:55.180115 dram_init: config_dvfs: 1
526 00:55:55.180170 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 00:55:55.180224 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 00:55:55.180279 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 00:55:55.180333 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 00:55:55.180388 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 00:55:55.180441 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 00:55:55.180496 MEM_TYPE=3, freq_sel=18
533 00:55:55.180549 sv_algorithm_assistance_LP4_1600
534 00:55:55.180602 ============ PULL DRAM RESETB DOWN ============
535 00:55:55.180671 ========== PULL DRAM RESETB DOWN end =========
536 00:55:55.180758 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 00:55:55.180842 ===================================
538 00:55:55.180930 LPDDR4 DRAM CONFIGURATION
539 00:55:55.181022 ===================================
540 00:55:55.181106 EX_ROW_EN[0] = 0x0
541 00:55:55.181190 EX_ROW_EN[1] = 0x0
542 00:55:55.181300 LP4Y_EN = 0x0
543 00:55:55.181373 WORK_FSP = 0x0
544 00:55:55.181427 WL = 0x2
545 00:55:55.181481 RL = 0x2
546 00:55:55.181535 BL = 0x2
547 00:55:55.181588 RPST = 0x0
548 00:55:55.181642 RD_PRE = 0x0
549 00:55:55.181695 WR_PRE = 0x1
550 00:55:55.181749 WR_PST = 0x0
551 00:55:55.181805 DBI_WR = 0x0
552 00:55:55.181861 DBI_RD = 0x0
553 00:55:55.181915 OTF = 0x1
554 00:55:55.181969 ===================================
555 00:55:55.182024 ===================================
556 00:55:55.182078 ANA top config
557 00:55:55.182131 ===================================
558 00:55:55.182185 DLL_ASYNC_EN = 0
559 00:55:55.182238 ALL_SLAVE_EN = 1
560 00:55:55.182296 NEW_RANK_MODE = 1
561 00:55:55.182355 DLL_IDLE_MODE = 1
562 00:55:55.182409 LP45_APHY_COMB_EN = 1
563 00:55:55.182462 TX_ODT_DIS = 1
564 00:55:55.182516 NEW_8X_MODE = 1
565 00:55:55.182570 ===================================
566 00:55:55.182623 ===================================
567 00:55:55.182676 data_rate = 1600
568 00:55:55.182730 CKR = 1
569 00:55:55.182783 DQ_P2S_RATIO = 8
570 00:55:55.182840 ===================================
571 00:55:55.182898 CA_P2S_RATIO = 8
572 00:55:55.182952 DQ_CA_OPEN = 0
573 00:55:55.183006 DQ_SEMI_OPEN = 0
574 00:55:55.183058 CA_SEMI_OPEN = 0
575 00:55:55.183112 CA_FULL_RATE = 0
576 00:55:55.183165 DQ_CKDIV4_EN = 1
577 00:55:55.183219 CA_CKDIV4_EN = 1
578 00:55:55.183272 CA_PREDIV_EN = 0
579 00:55:55.183326 PH8_DLY = 0
580 00:55:55.183383 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 00:55:55.183436 DQ_AAMCK_DIV = 4
582 00:55:55.183490 CA_AAMCK_DIV = 4
583 00:55:55.183543 CA_ADMCK_DIV = 4
584 00:55:55.183596 DQ_TRACK_CA_EN = 0
585 00:55:55.183649 CA_PICK = 800
586 00:55:55.183702 CA_MCKIO = 800
587 00:55:55.183755 MCKIO_SEMI = 0
588 00:55:55.183809 PLL_FREQ = 3068
589 00:55:55.183868 DQ_UI_PI_RATIO = 32
590 00:55:55.183953 CA_UI_PI_RATIO = 0
591 00:55:55.184037 ===================================
592 00:55:55.184121 ===================================
593 00:55:55.184204 memory_type:LPDDR4
594 00:55:55.184287 GP_NUM : 10
595 00:55:55.184370 SRAM_EN : 1
596 00:55:55.184428 MD32_EN : 0
597 00:55:55.184482 ===================================
598 00:55:55.184752 [ANA_INIT] >>>>>>>>>>>>>>
599 00:55:55.184812 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 00:55:55.184871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 00:55:55.184988 ===================================
602 00:55:55.185099 data_rate = 1600,PCW = 0X7600
603 00:55:55.185188 ===================================
604 00:55:55.185308 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 00:55:55.185396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 00:55:55.185452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:55:55.185512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 00:55:55.185567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 00:55:55.185621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:55:55.185675 [ANA_INIT] flow start
611 00:55:55.185728 [ANA_INIT] PLL >>>>>>>>
612 00:55:55.185782 [ANA_INIT] PLL <<<<<<<<
613 00:55:55.185835 [ANA_INIT] MIDPI >>>>>>>>
614 00:55:55.185889 [ANA_INIT] MIDPI <<<<<<<<
615 00:55:55.185943 [ANA_INIT] DLL >>>>>>>>
616 00:55:55.185997 [ANA_INIT] flow end
617 00:55:55.186054 ============ LP4 DIFF to SE enter ============
618 00:55:55.186112 ============ LP4 DIFF to SE exit ============
619 00:55:55.186166 [ANA_INIT] <<<<<<<<<<<<<
620 00:55:55.186220 [Flow] Enable top DCM control >>>>>
621 00:55:55.186274 [Flow] Enable top DCM control <<<<<
622 00:55:55.186327 Enable DLL master slave shuffle
623 00:55:55.186381 ==============================================================
624 00:55:55.186435 Gating Mode config
625 00:55:55.186489 ==============================================================
626 00:55:55.186543 Config description:
627 00:55:55.186603 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 00:55:55.186690 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 00:55:55.186775 SELPH_MODE 0: By rank 1: By Phase
630 00:55:55.186860 ==============================================================
631 00:55:55.186944 GAT_TRACK_EN = 1
632 00:55:55.187028 RX_GATING_MODE = 2
633 00:55:55.187111 RX_GATING_TRACK_MODE = 2
634 00:55:55.187173 SELPH_MODE = 1
635 00:55:55.187231 PICG_EARLY_EN = 1
636 00:55:55.187285 VALID_LAT_VALUE = 1
637 00:55:55.187338 ==============================================================
638 00:55:55.187392 Enter into Gating configuration >>>>
639 00:55:55.187446 Exit from Gating configuration <<<<
640 00:55:55.187500 Enter into DVFS_PRE_config >>>>>
641 00:55:55.187553 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 00:55:55.187611 Exit from DVFS_PRE_config <<<<<
643 00:55:55.187673 Enter into PICG configuration >>>>
644 00:55:55.187757 Exit from PICG configuration <<<<
645 00:55:55.187840 [RX_INPUT] configuration >>>>>
646 00:55:55.187926 [RX_INPUT] configuration <<<<<
647 00:55:55.187992 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 00:55:55.188047 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 00:55:55.188102 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 00:55:55.188157 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 00:55:55.188235 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 00:55:55.188321 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 00:55:55.188405 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 00:55:55.188490 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 00:55:55.188575 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 00:55:55.188659 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 00:55:55.188715 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 00:55:55.188774 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 00:55:55.188829 ===================================
660 00:55:55.188884 LPDDR4 DRAM CONFIGURATION
661 00:55:55.188938 ===================================
662 00:55:55.188992 EX_ROW_EN[0] = 0x0
663 00:55:55.189046 EX_ROW_EN[1] = 0x0
664 00:55:55.189100 LP4Y_EN = 0x0
665 00:55:55.189153 WORK_FSP = 0x0
666 00:55:55.189206 WL = 0x2
667 00:55:55.189288 RL = 0x2
668 00:55:55.189363 BL = 0x2
669 00:55:55.189417 RPST = 0x0
670 00:55:55.189470 RD_PRE = 0x0
671 00:55:55.189524 WR_PRE = 0x1
672 00:55:55.189577 WR_PST = 0x0
673 00:55:55.189631 DBI_WR = 0x0
674 00:55:55.189684 DBI_RD = 0x0
675 00:55:55.189737 OTF = 0x1
676 00:55:55.189794 ===================================
677 00:55:55.189849 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 00:55:55.189903 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 00:55:55.189956 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 00:55:55.190010 ===================================
681 00:55:55.190064 LPDDR4 DRAM CONFIGURATION
682 00:55:55.190117 ===================================
683 00:55:55.190171 EX_ROW_EN[0] = 0x10
684 00:55:55.190224 EX_ROW_EN[1] = 0x0
685 00:55:55.190277 LP4Y_EN = 0x0
686 00:55:55.190335 WORK_FSP = 0x0
687 00:55:55.190392 WL = 0x2
688 00:55:55.190446 RL = 0x2
689 00:55:55.190500 BL = 0x2
690 00:55:55.190553 RPST = 0x0
691 00:55:55.190607 RD_PRE = 0x0
692 00:55:55.190660 WR_PRE = 0x1
693 00:55:55.190713 WR_PST = 0x0
694 00:55:55.190766 DBI_WR = 0x0
695 00:55:55.190819 DBI_RD = 0x0
696 00:55:55.190875 OTF = 0x1
697 00:55:55.190928 ===================================
698 00:55:55.190982 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 00:55:55.191036 nWR fixed to 40
700 00:55:55.191091 [ModeRegInit_LP4] CH0 RK0
701 00:55:55.191144 [ModeRegInit_LP4] CH0 RK1
702 00:55:55.191197 [ModeRegInit_LP4] CH1 RK0
703 00:55:55.191250 [ModeRegInit_LP4] CH1 RK1
704 00:55:55.191303 match AC timing 13
705 00:55:55.191359 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 00:55:55.191641 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 00:55:55.191704 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 00:55:55.191795 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 00:55:55.191887 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 00:55:55.191974 [EMI DOE] emi_dcm 0
711 00:55:55.192060 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 00:55:55.192158 ==
713 00:55:55.192243 Dram Type= 6, Freq= 0, CH_0, rank 0
714 00:55:55.192327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 00:55:55.192407 ==
716 00:55:55.192465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 00:55:55.192521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 00:55:55.192575 [CA 0] Center 37 (7~68) winsize 62
719 00:55:55.192629 [CA 1] Center 37 (6~68) winsize 63
720 00:55:55.192683 [CA 2] Center 34 (4~65) winsize 62
721 00:55:55.192736 [CA 3] Center 34 (4~65) winsize 62
722 00:55:55.192790 [CA 4] Center 33 (3~64) winsize 62
723 00:55:55.192843 [CA 5] Center 33 (3~64) winsize 62
724 00:55:55.192897
725 00:55:55.192950 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 00:55:55.193034
727 00:55:55.193118 [CATrainingPosCal] consider 1 rank data
728 00:55:55.193201 u2DelayCellTimex100 = 270/100 ps
729 00:55:55.193324 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 00:55:55.193381 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 00:55:55.193435 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 00:55:55.193489 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 00:55:55.193546 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 00:55:55.193603 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 00:55:55.193657
736 00:55:55.193710 CA PerBit enable=1, Macro0, CA PI delay=33
737 00:55:55.193764
738 00:55:55.193818 [CBTSetCACLKResult] CA Dly = 33
739 00:55:55.193871 CS Dly: 6 (0~37)
740 00:55:55.193924 ==
741 00:55:55.193978 Dram Type= 6, Freq= 0, CH_0, rank 1
742 00:55:55.194032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 00:55:55.194086 ==
744 00:55:55.194143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 00:55:55.194199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 00:55:55.194253 [CA 0] Center 38 (7~69) winsize 63
747 00:55:55.194307 [CA 1] Center 37 (7~68) winsize 62
748 00:55:55.194360 [CA 2] Center 35 (4~66) winsize 63
749 00:55:55.194413 [CA 3] Center 35 (4~66) winsize 63
750 00:55:55.194467 [CA 4] Center 34 (3~65) winsize 63
751 00:55:55.194520 [CA 5] Center 33 (3~64) winsize 62
752 00:55:55.194574
753 00:55:55.194627 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 00:55:55.194681
755 00:55:55.194737 [CATrainingPosCal] consider 2 rank data
756 00:55:55.194794 u2DelayCellTimex100 = 270/100 ps
757 00:55:55.194848 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 00:55:55.194902 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 00:55:55.194956 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 00:55:55.195009 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 00:55:55.195075 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 00:55:55.195143 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 00:55:55.195197
764 00:55:55.195251 CA PerBit enable=1, Macro0, CA PI delay=33
765 00:55:55.195336
766 00:55:55.195419 [CBTSetCACLKResult] CA Dly = 33
767 00:55:55.195502 CS Dly: 6 (0~38)
768 00:55:55.195585
769 00:55:55.195668 ----->DramcWriteLeveling(PI) begin...
770 00:55:55.195753 ==
771 00:55:55.195838 Dram Type= 6, Freq= 0, CH_0, rank 0
772 00:55:55.195924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 00:55:55.196008 ==
774 00:55:55.196092 Write leveling (Byte 0): 31 => 31
775 00:55:55.196175 Write leveling (Byte 1): 27 => 27
776 00:55:55.196259 DramcWriteLeveling(PI) end<-----
777 00:55:55.196342
778 00:55:55.196424 ==
779 00:55:55.196481 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:55:55.196535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:55:55.196589 ==
782 00:55:55.196643 [Gating] SW mode calibration
783 00:55:55.196697 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 00:55:55.196752 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 00:55:55.196806 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 00:55:55.196860 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 00:55:55.196914 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 00:55:55.196968 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:55:55.197028 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:55:55.197115 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:55:55.197199 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:55:55.197307 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:55:55.197377 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:55:55.197431 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:55:55.197484 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:55:55.197539 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:55:55.197596 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:55:55.197649 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:55:55.197703 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:55:55.197757 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:55:55.197810 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:55:55.197863 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
803 00:55:55.197917 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
804 00:55:55.197971 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 00:55:55.198024 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:55:55.198078 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:55:55.198134 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:55:55.198191 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:55:55.198245 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:55:55.198299 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:55:55.198352 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
812 00:55:55.198406 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
813 00:55:55.198463 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 00:55:55.198753 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:55:55.198817 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:55:55.198874 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:55:55.198930 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:55:55.198985 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
819 00:55:55.199054 0 10 8 | B1->B0 | 3131 2727 | 1 0 | (1 0) (0 0)
820 00:55:55.199123 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
821 00:55:55.199181 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:55:55.199242 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:55:55.199327 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:55:55.199412 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:55:55.199496 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:55:55.199580 0 11 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
827 00:55:55.199664 0 11 8 | B1->B0 | 2a2a 4242 | 1 0 | (0 0) (0 0)
828 00:55:55.199751 0 11 12 | B1->B0 | 3c3c 4646 | 1 0 | (1 1) (0 0)
829 00:55:55.199836 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 00:55:55.199920 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:55:55.200004 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:55:55.200088 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:55:55.200172 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:55:55.200255 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:55:55.200325 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
836 00:55:55.200383 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 00:55:55.200437 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:55:55.200490 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:55:55.200544 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:55:55.200598 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:55:55.200651 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:55:55.200705 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:55:55.200758 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:55:55.200812 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:55:55.200874 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:55:55.200960 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:55:55.201095 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:55:55.201201 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:55:55.201314 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:55:55.201391 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 00:55:55.201464 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 00:55:55.201537 Total UI for P1: 0, mck2ui 16
853 00:55:55.201594 best dqsien dly found for B0: ( 0, 14, 4)
854 00:55:55.201649 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 00:55:55.201704 Total UI for P1: 0, mck2ui 16
856 00:55:55.201759 best dqsien dly found for B1: ( 0, 14, 8)
857 00:55:55.201815 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
858 00:55:55.201906 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 00:55:55.202017
860 00:55:55.202122 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
861 00:55:55.202221 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 00:55:55.202331 [Gating] SW calibration Done
863 00:55:55.202435 ==
864 00:55:55.202545 Dram Type= 6, Freq= 0, CH_0, rank 0
865 00:55:55.202654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 00:55:55.202760 ==
867 00:55:55.202853 RX Vref Scan: 0
868 00:55:55.202950
869 00:55:55.203051 RX Vref 0 -> 0, step: 1
870 00:55:55.203141
871 00:55:55.203238 RX Delay -130 -> 252, step: 16
872 00:55:55.203327 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 00:55:55.203414 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 00:55:55.203501 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 00:55:55.203591 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 00:55:55.203678 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 00:55:55.203765 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 00:55:55.203858 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 00:55:55.203946 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
880 00:55:55.204032 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 00:55:55.204120 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
882 00:55:55.204206 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 00:55:55.204292 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 00:55:55.204378 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 00:55:55.204464 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 00:55:55.204550 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 00:55:55.204626 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 00:55:55.204703 ==
889 00:55:55.204789 Dram Type= 6, Freq= 0, CH_0, rank 0
890 00:55:55.204875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 00:55:55.204961 ==
892 00:55:55.205048 DQS Delay:
893 00:55:55.205135 DQS0 = 0, DQS1 = 0
894 00:55:55.205234 DQM Delay:
895 00:55:55.205315 DQM0 = 88, DQM1 = 75
896 00:55:55.205373 DQ Delay:
897 00:55:55.205428 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 00:55:55.205484 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
899 00:55:55.205540 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
900 00:55:55.205596 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 00:55:55.205653
902 00:55:55.205711
903 00:55:55.205766 ==
904 00:55:55.205821 Dram Type= 6, Freq= 0, CH_0, rank 0
905 00:55:55.205877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 00:55:55.205932 ==
907 00:55:55.205988
908 00:55:55.206042
909 00:55:55.206110 TX Vref Scan disable
910 00:55:55.206164 == TX Byte 0 ==
911 00:55:55.206222 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 00:55:55.206277 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 00:55:55.206330 == TX Byte 1 ==
914 00:55:55.206384 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
915 00:55:55.206437 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
916 00:55:55.206490 ==
917 00:55:55.206544 Dram Type= 6, Freq= 0, CH_0, rank 0
918 00:55:55.206598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 00:55:55.206651 ==
920 00:55:55.206707 TX Vref=22, minBit 1, minWin=26, winSum=438
921 00:55:55.206763 TX Vref=24, minBit 5, minWin=26, winSum=439
922 00:55:55.207051 TX Vref=26, minBit 0, minWin=27, winSum=442
923 00:55:55.207195 TX Vref=28, minBit 2, minWin=27, winSum=450
924 00:55:55.207306 TX Vref=30, minBit 2, minWin=27, winSum=450
925 00:55:55.207414 TX Vref=32, minBit 1, minWin=27, winSum=448
926 00:55:55.207523 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 28
927 00:55:55.207626
928 00:55:55.207719 Final TX Range 1 Vref 28
929 00:55:55.207806
930 00:55:55.207890 ==
931 00:55:55.207975 Dram Type= 6, Freq= 0, CH_0, rank 0
932 00:55:55.208059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 00:55:55.208143 ==
934 00:55:55.208226
935 00:55:55.208302
936 00:55:55.208357 TX Vref Scan disable
937 00:55:55.208412 == TX Byte 0 ==
938 00:55:55.208465 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
939 00:55:55.208520 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
940 00:55:55.208574 == TX Byte 1 ==
941 00:55:55.208628 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
942 00:55:55.208681 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
943 00:55:55.208784
944 00:55:55.208874 [DATLAT]
945 00:55:55.208961 Freq=800, CH0 RK0
946 00:55:55.209050
947 00:55:55.209135 DATLAT Default: 0xa
948 00:55:55.209220 0, 0xFFFF, sum = 0
949 00:55:55.209320 1, 0xFFFF, sum = 0
950 00:55:55.209377 2, 0xFFFF, sum = 0
951 00:55:55.209435 3, 0xFFFF, sum = 0
952 00:55:55.209491 4, 0xFFFF, sum = 0
953 00:55:55.209545 5, 0xFFFF, sum = 0
954 00:55:55.209599 6, 0xFFFF, sum = 0
955 00:55:55.209653 7, 0xFFFF, sum = 0
956 00:55:55.209707 8, 0xFFFF, sum = 0
957 00:55:55.209761 9, 0x0, sum = 1
958 00:55:55.209816 10, 0x0, sum = 2
959 00:55:55.209870 11, 0x0, sum = 3
960 00:55:55.209924 12, 0x0, sum = 4
961 00:55:55.209982 best_step = 10
962 00:55:55.210052
963 00:55:55.210134 ==
964 00:55:55.210218 Dram Type= 6, Freq= 0, CH_0, rank 0
965 00:55:55.210302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 00:55:55.210386 ==
967 00:55:55.210469 RX Vref Scan: 1
968 00:55:55.210539
969 00:55:55.210593 Set Vref Range= 32 -> 127
970 00:55:55.210647
971 00:55:55.210700 RX Vref 32 -> 127, step: 1
972 00:55:55.210753
973 00:55:55.210806 RX Delay -111 -> 252, step: 8
974 00:55:55.210860
975 00:55:55.210913 Set Vref, RX VrefLevel [Byte0]: 32
976 00:55:55.210966 [Byte1]: 32
977 00:55:55.211020
978 00:55:55.211076 Set Vref, RX VrefLevel [Byte0]: 33
979 00:55:55.211132 [Byte1]: 33
980 00:55:55.211186
981 00:55:55.211240 Set Vref, RX VrefLevel [Byte0]: 34
982 00:55:55.211293 [Byte1]: 34
983 00:55:55.211346
984 00:55:55.211399 Set Vref, RX VrefLevel [Byte0]: 35
985 00:55:55.211453 [Byte1]: 35
986 00:55:55.211506
987 00:55:55.211560 Set Vref, RX VrefLevel [Byte0]: 36
988 00:55:55.211614 [Byte1]: 36
989 00:55:55.211671
990 00:55:55.211725 Set Vref, RX VrefLevel [Byte0]: 37
991 00:55:55.211779 [Byte1]: 37
992 00:55:55.211832
993 00:55:55.211886 Set Vref, RX VrefLevel [Byte0]: 38
994 00:55:55.211940 [Byte1]: 38
995 00:55:55.211993
996 00:55:55.212047 Set Vref, RX VrefLevel [Byte0]: 39
997 00:55:55.212100 [Byte1]: 39
998 00:55:55.212157
999 00:55:55.212216 Set Vref, RX VrefLevel [Byte0]: 40
1000 00:55:55.212290 [Byte1]: 40
1001 00:55:55.212373
1002 00:55:55.212456 Set Vref, RX VrefLevel [Byte0]: 41
1003 00:55:55.212539 [Byte1]: 41
1004 00:55:55.212621
1005 00:55:55.212704 Set Vref, RX VrefLevel [Byte0]: 42
1006 00:55:55.212790 [Byte1]: 42
1007 00:55:55.212872
1008 00:55:55.212956 Set Vref, RX VrefLevel [Byte0]: 43
1009 00:55:55.213040 [Byte1]: 43
1010 00:55:55.213122
1011 00:55:55.213205 Set Vref, RX VrefLevel [Byte0]: 44
1012 00:55:55.213324 [Byte1]: 44
1013 00:55:55.213383
1014 00:55:55.213439 Set Vref, RX VrefLevel [Byte0]: 45
1015 00:55:55.213494 [Byte1]: 45
1016 00:55:55.213573
1017 00:55:55.213630 Set Vref, RX VrefLevel [Byte0]: 46
1018 00:55:55.213717 [Byte1]: 46
1019 00:55:55.213802
1020 00:55:55.213885 Set Vref, RX VrefLevel [Byte0]: 47
1021 00:55:55.213956 [Byte1]: 47
1022 00:55:55.214028
1023 00:55:55.214113 Set Vref, RX VrefLevel [Byte0]: 48
1024 00:55:55.214168 [Byte1]: 48
1025 00:55:55.214230
1026 00:55:55.214288 Set Vref, RX VrefLevel [Byte0]: 49
1027 00:55:55.214345 [Byte1]: 49
1028 00:55:55.214401
1029 00:55:55.214456 Set Vref, RX VrefLevel [Byte0]: 50
1030 00:55:55.214515 [Byte1]: 50
1031 00:55:55.214573
1032 00:55:55.214627 Set Vref, RX VrefLevel [Byte0]: 51
1033 00:55:55.214682 [Byte1]: 51
1034 00:55:55.214736
1035 00:55:55.214790 Set Vref, RX VrefLevel [Byte0]: 52
1036 00:55:55.214845 [Byte1]: 52
1037 00:55:55.214899
1038 00:55:55.214953 Set Vref, RX VrefLevel [Byte0]: 53
1039 00:55:55.215017 [Byte1]: 53
1040 00:55:55.215073
1041 00:55:55.215127 Set Vref, RX VrefLevel [Byte0]: 54
1042 00:55:55.215208 [Byte1]: 54
1043 00:55:55.215263
1044 00:55:55.215317 Set Vref, RX VrefLevel [Byte0]: 55
1045 00:55:55.215371 [Byte1]: 55
1046 00:55:55.215425
1047 00:55:55.215478 Set Vref, RX VrefLevel [Byte0]: 56
1048 00:55:55.215537 [Byte1]: 56
1049 00:55:55.215609
1050 00:55:55.215694 Set Vref, RX VrefLevel [Byte0]: 57
1051 00:55:55.215778 [Byte1]: 57
1052 00:55:55.215862
1053 00:55:55.215945 Set Vref, RX VrefLevel [Byte0]: 58
1054 00:55:55.216032 [Byte1]: 58
1055 00:55:55.216116
1056 00:55:55.216199 Set Vref, RX VrefLevel [Byte0]: 59
1057 00:55:55.216283 [Byte1]: 59
1058 00:55:55.216366
1059 00:55:55.216450 Set Vref, RX VrefLevel [Byte0]: 60
1060 00:55:55.216534 [Byte1]: 60
1061 00:55:55.216599
1062 00:55:55.216657 Set Vref, RX VrefLevel [Byte0]: 61
1063 00:55:55.216712 [Byte1]: 61
1064 00:55:55.216766
1065 00:55:55.216820 Set Vref, RX VrefLevel [Byte0]: 62
1066 00:55:55.216874 [Byte1]: 62
1067 00:55:55.216928
1068 00:55:55.216982 Set Vref, RX VrefLevel [Byte0]: 63
1069 00:55:55.217036 [Byte1]: 63
1070 00:55:55.217096
1071 00:55:55.217181 Set Vref, RX VrefLevel [Byte0]: 64
1072 00:55:55.217276 [Byte1]: 64
1073 00:55:55.217340
1074 00:55:55.217396 Set Vref, RX VrefLevel [Byte0]: 65
1075 00:55:55.217450 [Byte1]: 65
1076 00:55:55.217505
1077 00:55:55.217559 Set Vref, RX VrefLevel [Byte0]: 66
1078 00:55:55.217629 [Byte1]: 66
1079 00:55:55.217685
1080 00:55:55.217739 Set Vref, RX VrefLevel [Byte0]: 67
1081 00:55:55.217806 [Byte1]: 67
1082 00:55:55.217889
1083 00:55:55.217970 Set Vref, RX VrefLevel [Byte0]: 68
1084 00:55:55.218028 [Byte1]: 68
1085 00:55:55.218098
1086 00:55:55.218156 Set Vref, RX VrefLevel [Byte0]: 69
1087 00:55:55.218226 [Byte1]: 69
1088 00:55:55.218309
1089 00:55:55.218364 Set Vref, RX VrefLevel [Byte0]: 70
1090 00:55:55.218641 [Byte1]: 70
1091 00:55:55.218766
1092 00:55:55.218878 Set Vref, RX VrefLevel [Byte0]: 71
1093 00:55:55.219029 [Byte1]: 71
1094 00:55:55.219151
1095 00:55:55.219255 Set Vref, RX VrefLevel [Byte0]: 72
1096 00:55:55.219346 [Byte1]: 72
1097 00:55:55.219443
1098 00:55:55.219527 Set Vref, RX VrefLevel [Byte0]: 73
1099 00:55:55.219610 [Byte1]: 73
1100 00:55:55.219692
1101 00:55:55.219769 Set Vref, RX VrefLevel [Byte0]: 74
1102 00:55:55.219827 [Byte1]: 74
1103 00:55:55.219882
1104 00:55:55.219935 Set Vref, RX VrefLevel [Byte0]: 75
1105 00:55:55.219989 [Byte1]: 75
1106 00:55:55.220042
1107 00:55:55.220096 Set Vref, RX VrefLevel [Byte0]: 76
1108 00:55:55.220149 [Byte1]: 76
1109 00:55:55.220202
1110 00:55:55.220284 Set Vref, RX VrefLevel [Byte0]: 77
1111 00:55:55.220370 [Byte1]: 77
1112 00:55:55.220423
1113 00:55:55.220476 Final RX Vref Byte 0 = 59 to rank0
1114 00:55:55.220530 Final RX Vref Byte 1 = 61 to rank0
1115 00:55:55.220583 Final RX Vref Byte 0 = 59 to rank1
1116 00:55:55.220636 Final RX Vref Byte 1 = 61 to rank1==
1117 00:55:55.220690 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 00:55:55.220743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 00:55:55.220797 ==
1120 00:55:55.220850 DQS Delay:
1121 00:55:55.220923 DQS0 = 0, DQS1 = 0
1122 00:55:55.221006 DQM Delay:
1123 00:55:55.221088 DQM0 = 88, DQM1 = 75
1124 00:55:55.221170 DQ Delay:
1125 00:55:55.221252 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1126 00:55:55.221357 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1127 00:55:55.221414 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1128 00:55:55.221468 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1129 00:55:55.221528
1130 00:55:55.221583
1131 00:55:55.221635 [DQSOSCAuto] RK0, (LSB)MR18= 0x3832, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
1132 00:55:55.221691 CH0 RK0: MR19=606, MR18=3832
1133 00:55:55.221745 CH0_RK0: MR19=0x606, MR18=0x3832, DQSOSC=395, MR23=63, INC=94, DEC=63
1134 00:55:55.221799
1135 00:55:55.221852 ----->DramcWriteLeveling(PI) begin...
1136 00:55:55.221907 ==
1137 00:55:55.221965 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 00:55:55.222022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 00:55:55.222076 ==
1140 00:55:55.222130 Write leveling (Byte 0): 31 => 31
1141 00:55:55.222184 Write leveling (Byte 1): 26 => 26
1142 00:55:55.222349 DramcWriteLeveling(PI) end<-----
1143 00:55:55.222438
1144 00:55:55.222516 ==
1145 00:55:55.222590 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 00:55:55.222675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 00:55:55.222772 ==
1148 00:55:55.222863 [Gating] SW mode calibration
1149 00:55:55.222967 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 00:55:55.223084 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 00:55:55.223143 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 00:55:55.223199 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1153 00:55:55.223253 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1154 00:55:55.223307 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 00:55:55.223361 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 00:55:55.223415 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:55:55.223468 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:55:55.223522 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:55:55.223575 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:55:55.223674 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:55:55.223759 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:55:55.223849 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:55:55.223992 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:55:55.224082 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:55:55.224186 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:55:55.224338 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:55:55.224503 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:55:55.224646 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1169 00:55:55.224775 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1170 00:55:55.224856 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:55:55.224946 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:55:55.225035 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:55:55.225124 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:55:55.225213 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:55:55.225337 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:55:55.225444 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1177 00:55:55.225533 0 9 8 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
1178 00:55:55.225624 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 00:55:55.225725 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 00:55:55.225819 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 00:55:55.225911 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 00:55:55.225999 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 00:55:55.226085 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 00:55:55.226171 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1185 00:55:55.226269 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
1186 00:55:55.226333 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 00:55:55.226395 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:55:55.226483 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:55:55.226569 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:55:55.226681 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:55:55.226766 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:55:55.226851 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1193 00:55:55.226939 0 11 8 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
1194 00:55:55.227024 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 00:55:55.227109 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 00:55:55.227194 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 00:55:55.227495 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 00:55:55.227587 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 00:55:55.227674 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:55:55.227759 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1201 00:55:55.227845 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1202 00:55:55.227929 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 00:55:55.228017 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:55:55.228102 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:55:55.228191 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:55:55.228277 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:55:55.228387 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:55:55.228499 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:55:55.228590 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:55:55.228676 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:55:55.228760 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:55:55.228845 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:55:55.228930 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:55:55.229016 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:55:55.229102 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:55:55.229187 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1217 00:55:55.229288 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1218 00:55:55.229377 Total UI for P1: 0, mck2ui 16
1219 00:55:55.229433 best dqsien dly found for B0: ( 0, 14, 4)
1220 00:55:55.229491 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1221 00:55:55.229550 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 00:55:55.229629 Total UI for P1: 0, mck2ui 16
1223 00:55:55.229684 best dqsien dly found for B1: ( 0, 14, 8)
1224 00:55:55.229739 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1225 00:55:55.229793 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 00:55:55.229847
1227 00:55:55.229900 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1228 00:55:55.229954 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 00:55:55.230008 [Gating] SW calibration Done
1230 00:55:55.230076 ==
1231 00:55:55.230147 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 00:55:55.230202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 00:55:55.230256 ==
1234 00:55:55.230309 RX Vref Scan: 0
1235 00:55:55.230362
1236 00:55:55.230415 RX Vref 0 -> 0, step: 1
1237 00:55:55.230469
1238 00:55:55.230521 RX Delay -130 -> 252, step: 16
1239 00:55:55.230575 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1240 00:55:55.230643 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1241 00:55:55.230714 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1242 00:55:55.230790 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1243 00:55:55.230873 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1244 00:55:55.230956 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1245 00:55:55.231039 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1246 00:55:55.231121 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1247 00:55:55.231234 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1248 00:55:55.231317 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1249 00:55:55.231400 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1250 00:55:55.231483 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1251 00:55:55.231565 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1252 00:55:55.231666 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1253 00:55:55.231752 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1254 00:55:55.231840 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1255 00:55:55.231924 ==
1256 00:55:55.232008 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 00:55:55.232093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 00:55:55.232177 ==
1259 00:55:55.232261 DQS Delay:
1260 00:55:55.232323 DQS0 = 0, DQS1 = 0
1261 00:55:55.232378 DQM Delay:
1262 00:55:55.232446 DQM0 = 84, DQM1 = 75
1263 00:55:55.232515 DQ Delay:
1264 00:55:55.232569 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1265 00:55:55.232624 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1266 00:55:55.232709 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1267 00:55:55.232764 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1268 00:55:55.232823
1269 00:55:55.232909
1270 00:55:55.232992 ==
1271 00:55:55.233091 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 00:55:55.233180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 00:55:55.233274 ==
1274 00:55:55.233346
1275 00:55:55.233423
1276 00:55:55.233491 TX Vref Scan disable
1277 00:55:55.233545 == TX Byte 0 ==
1278 00:55:55.233612 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1279 00:55:55.233681 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1280 00:55:55.233764 == TX Byte 1 ==
1281 00:55:55.233849 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1282 00:55:55.233934 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1283 00:55:55.233989 ==
1284 00:55:55.234045 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 00:55:55.234099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 00:55:55.234153 ==
1287 00:55:55.234206 TX Vref=22, minBit 0, minWin=27, winSum=438
1288 00:55:55.234261 TX Vref=24, minBit 0, minWin=27, winSum=446
1289 00:55:55.234336 TX Vref=26, minBit 1, minWin=27, winSum=450
1290 00:55:55.234416 TX Vref=28, minBit 6, minWin=27, winSum=451
1291 00:55:55.234503 TX Vref=30, minBit 7, minWin=27, winSum=452
1292 00:55:55.234607 TX Vref=32, minBit 1, minWin=27, winSum=447
1293 00:55:55.234696 [TxChooseVref] Worse bit 7, Min win 27, Win sum 452, Final Vref 30
1294 00:55:55.234782
1295 00:55:55.234868 Final TX Range 1 Vref 30
1296 00:55:55.234955
1297 00:55:55.235039 ==
1298 00:55:55.235139 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 00:55:55.235222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 00:55:55.235335 ==
1301 00:55:55.235416
1302 00:55:55.235515
1303 00:55:55.235600 TX Vref Scan disable
1304 00:55:55.235685 == TX Byte 0 ==
1305 00:55:55.235770 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1306 00:55:55.235854 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1307 00:55:55.235938 == TX Byte 1 ==
1308 00:55:55.236022 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1309 00:55:55.236107 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1310 00:55:55.236194
1311 00:55:55.236277 [DATLAT]
1312 00:55:55.236361 Freq=800, CH0 RK1
1313 00:55:55.236445
1314 00:55:55.236528 DATLAT Default: 0xa
1315 00:55:55.236611 0, 0xFFFF, sum = 0
1316 00:55:55.236681 1, 0xFFFF, sum = 0
1317 00:55:55.236738 2, 0xFFFF, sum = 0
1318 00:55:55.236793 3, 0xFFFF, sum = 0
1319 00:55:55.236848 4, 0xFFFF, sum = 0
1320 00:55:55.236904 5, 0xFFFF, sum = 0
1321 00:55:55.236958 6, 0xFFFF, sum = 0
1322 00:55:55.237286 7, 0xFFFF, sum = 0
1323 00:55:55.237400 8, 0xFFFF, sum = 0
1324 00:55:55.237510 9, 0x0, sum = 1
1325 00:55:55.237619 10, 0x0, sum = 2
1326 00:55:55.237731 11, 0x0, sum = 3
1327 00:55:55.237840 12, 0x0, sum = 4
1328 00:55:55.237963 best_step = 10
1329 00:55:55.238065
1330 00:55:55.238185 ==
1331 00:55:55.238292 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 00:55:55.238399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 00:55:55.238496 ==
1334 00:55:55.238581 RX Vref Scan: 0
1335 00:55:55.238678
1336 00:55:55.238789 RX Vref 0 -> 0, step: 1
1337 00:55:55.238869
1338 00:55:55.238924 RX Delay -95 -> 252, step: 8
1339 00:55:55.238993 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1340 00:55:55.239083 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1341 00:55:55.239137 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1342 00:55:55.239214 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1343 00:55:55.239298 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1344 00:55:55.239368 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1345 00:55:55.239423 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1346 00:55:55.239476 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1347 00:55:55.239528 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1348 00:55:55.239580 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1349 00:55:55.239633 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1350 00:55:55.239685 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1351 00:55:55.239737 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1352 00:55:55.239790 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1353 00:55:55.239841 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1354 00:55:55.239923 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1355 00:55:55.239998 ==
1356 00:55:55.240080 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 00:55:55.240161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 00:55:55.240243 ==
1359 00:55:55.240324 DQS Delay:
1360 00:55:55.240405 DQS0 = 0, DQS1 = 0
1361 00:55:55.240516 DQM Delay:
1362 00:55:55.240585 DQM0 = 86, DQM1 = 76
1363 00:55:55.240642 DQ Delay:
1364 00:55:55.240695 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1365 00:55:55.240748 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1366 00:55:55.240800 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1367 00:55:55.240853 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1368 00:55:55.240905
1369 00:55:55.240973
1370 00:55:55.241099 [DQSOSCAuto] RK1, (LSB)MR18= 0x302d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1371 00:55:55.241188 CH0 RK1: MR19=606, MR18=302D
1372 00:55:55.241297 CH0_RK1: MR19=0x606, MR18=0x302D, DQSOSC=397, MR23=63, INC=93, DEC=62
1373 00:55:55.241395 [RxdqsGatingPostProcess] freq 800
1374 00:55:55.241479 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 00:55:55.241561 Pre-setting of DQS Precalculation
1376 00:55:55.241645 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 00:55:55.241702 ==
1378 00:55:55.241758 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 00:55:55.241812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 00:55:55.241865 ==
1381 00:55:55.241918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 00:55:55.241971 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 00:55:55.242023 [CA 0] Center 37 (6~68) winsize 63
1384 00:55:55.242076 [CA 1] Center 37 (6~68) winsize 63
1385 00:55:55.242128 [CA 2] Center 35 (5~65) winsize 61
1386 00:55:55.242180 [CA 3] Center 34 (4~65) winsize 62
1387 00:55:55.242232 [CA 4] Center 34 (4~65) winsize 62
1388 00:55:55.242284 [CA 5] Center 33 (3~64) winsize 62
1389 00:55:55.242339
1390 00:55:55.242392 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 00:55:55.242444
1392 00:55:55.242496 [CATrainingPosCal] consider 1 rank data
1393 00:55:55.242551 u2DelayCellTimex100 = 270/100 ps
1394 00:55:55.242603 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1395 00:55:55.242656 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1396 00:55:55.242708 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1397 00:55:55.242760 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1398 00:55:55.242812 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1399 00:55:55.242865 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1400 00:55:55.242917
1401 00:55:55.242972 CA PerBit enable=1, Macro0, CA PI delay=33
1402 00:55:55.243045
1403 00:55:55.243169 [CBTSetCACLKResult] CA Dly = 33
1404 00:55:55.243268 CS Dly: 4 (0~35)
1405 00:55:55.243351 ==
1406 00:55:55.243433 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 00:55:55.243547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 00:55:55.243631 ==
1409 00:55:55.243714 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 00:55:55.243797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 00:55:55.243879 [CA 0] Center 36 (6~67) winsize 62
1412 00:55:55.243961 [CA 1] Center 37 (6~68) winsize 63
1413 00:55:55.244042 [CA 2] Center 34 (4~65) winsize 62
1414 00:55:55.244123 [CA 3] Center 34 (3~65) winsize 63
1415 00:55:55.244207 [CA 4] Center 34 (3~65) winsize 63
1416 00:55:55.244289 [CA 5] Center 34 (3~65) winsize 63
1417 00:55:55.244370
1418 00:55:55.244451 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 00:55:55.244532
1420 00:55:55.244614 [CATrainingPosCal] consider 2 rank data
1421 00:55:55.244695 u2DelayCellTimex100 = 270/100 ps
1422 00:55:55.244779 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1423 00:55:55.244863 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1424 00:55:55.244945 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1425 00:55:55.245026 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1426 00:55:55.245108 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1427 00:55:55.245189 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1428 00:55:55.245313
1429 00:55:55.245403 CA PerBit enable=1, Macro0, CA PI delay=33
1430 00:55:55.245462
1431 00:55:55.245514 [CBTSetCACLKResult] CA Dly = 33
1432 00:55:55.245567 CS Dly: 5 (0~37)
1433 00:55:55.245618
1434 00:55:55.245671 ----->DramcWriteLeveling(PI) begin...
1435 00:55:55.245725 ==
1436 00:55:55.245778 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 00:55:55.245830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 00:55:55.245883 ==
1439 00:55:55.245935 Write leveling (Byte 0): 27 => 27
1440 00:55:55.245987 Write leveling (Byte 1): 28 => 28
1441 00:55:55.246041 DramcWriteLeveling(PI) end<-----
1442 00:55:55.246094
1443 00:55:55.246148 ==
1444 00:55:55.246200 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 00:55:55.246253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 00:55:55.246305 ==
1447 00:55:55.246357 [Gating] SW mode calibration
1448 00:55:55.246409 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 00:55:55.246463 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 00:55:55.246719 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 00:55:55.246779 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1452 00:55:55.246833 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 00:55:55.246886 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 00:55:55.246939 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 00:55:55.246992 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:55:55.247045 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:55:55.247097 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:55:55.247149 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:55:55.247202 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:55:55.247258 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:55:55.247311 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:55:55.247366 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:55:55.247418 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:55:55.247470 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:55:55.247523 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:55:55.247575 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:55:55.247627 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1468 00:55:55.247679 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:55:55.247732 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:55:55.247784 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:55:55.247836 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:55:55.247894 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:55:55.247977 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:55:55.248059 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:55:55.248140 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:55:55.248222 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (0 0)
1477 00:55:55.248304 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 00:55:55.248389 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 00:55:55.248464 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 00:55:55.248520 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 00:55:55.248573 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 00:55:55.248626 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 00:55:55.248678 0 10 4 | B1->B0 | 3232 3030 | 1 1 | (1 1) (1 0)
1484 00:55:55.248730 0 10 8 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1485 00:55:55.248782 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:55:55.248835 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:55:55.248887 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:55:55.248941 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:55:55.248993 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:55:55.249051 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:55:55.249159 0 11 4 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
1492 00:55:55.249243 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1493 00:55:55.249326 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 00:55:55.249379 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 00:55:55.249432 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:55:55.249484 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:55:55.249536 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 00:55:55.249589 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 00:55:55.249644 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 00:55:55.249700 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 00:55:55.249753 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 00:55:55.249805 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:55:55.249857 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:55:55.249909 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:55:55.249962 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:55:55.250014 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:55:55.250067 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:55:55.250118 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:55:55.250171 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:55:55.250223 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:55:55.250278 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:55:55.250330 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:55:55.250382 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:55:55.250434 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:55:55.250486 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 00:55:55.250539 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1517 00:55:55.250591 Total UI for P1: 0, mck2ui 16
1518 00:55:55.250643 best dqsien dly found for B0: ( 0, 14, 4)
1519 00:55:55.250697 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 00:55:55.250750 Total UI for P1: 0, mck2ui 16
1521 00:55:55.250802 best dqsien dly found for B1: ( 0, 14, 6)
1522 00:55:55.250857 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1523 00:55:55.250913 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1524 00:55:55.250966
1525 00:55:55.251017 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 00:55:55.251070 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 00:55:55.251122 [Gating] SW calibration Done
1528 00:55:55.251174 ==
1529 00:55:55.251227 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 00:55:55.251278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 00:55:55.251331 ==
1532 00:55:55.251383 RX Vref Scan: 0
1533 00:55:55.251437
1534 00:55:55.251489 RX Vref 0 -> 0, step: 1
1535 00:55:55.251549
1536 00:55:55.251640 RX Delay -130 -> 252, step: 16
1537 00:55:55.251728 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1538 00:55:55.251811 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1539 00:55:55.252100 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1540 00:55:55.252191 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1541 00:55:55.252277 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1542 00:55:55.252360 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1543 00:55:55.252439 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1544 00:55:55.252495 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1545 00:55:55.252577 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1546 00:55:55.252635 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1547 00:55:55.252688 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1548 00:55:55.252742 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1549 00:55:55.252854 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1550 00:55:55.253002 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1551 00:55:55.253097 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1552 00:55:55.253184 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1553 00:55:55.253274 ==
1554 00:55:55.253344 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 00:55:55.253397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 00:55:55.253451 ==
1557 00:55:55.253503 DQS Delay:
1558 00:55:55.253556 DQS0 = 0, DQS1 = 0
1559 00:55:55.253608 DQM Delay:
1560 00:55:55.253661 DQM0 = 86, DQM1 = 78
1561 00:55:55.253714 DQ Delay:
1562 00:55:55.253771 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1563 00:55:55.253826 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =77
1564 00:55:55.253879 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1565 00:55:55.253932 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1566 00:55:55.253984
1567 00:55:55.254036
1568 00:55:55.254087 ==
1569 00:55:55.254140 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 00:55:55.254192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 00:55:55.254245 ==
1572 00:55:55.254296
1573 00:55:55.254351
1574 00:55:55.254404 TX Vref Scan disable
1575 00:55:55.254456 == TX Byte 0 ==
1576 00:55:55.254509 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1577 00:55:55.254562 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1578 00:55:55.254615 == TX Byte 1 ==
1579 00:55:55.254667 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1580 00:55:55.254720 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1581 00:55:55.254772 ==
1582 00:55:55.254824 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 00:55:55.254877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 00:55:55.254932 ==
1585 00:55:55.254985 TX Vref=22, minBit 4, minWin=27, winSum=446
1586 00:55:55.255069 TX Vref=24, minBit 5, minWin=27, winSum=449
1587 00:55:55.255152 TX Vref=26, minBit 6, minWin=27, winSum=454
1588 00:55:55.255234 TX Vref=28, minBit 5, minWin=27, winSum=454
1589 00:55:55.255316 TX Vref=30, minBit 0, minWin=28, winSum=455
1590 00:55:55.255398 TX Vref=32, minBit 0, minWin=27, winSum=448
1591 00:55:55.255481 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1592 00:55:55.255564
1593 00:55:55.255646 Final TX Range 1 Vref 30
1594 00:55:55.255727
1595 00:55:55.255807 ==
1596 00:55:55.255889 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 00:55:55.255971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 00:55:55.256053 ==
1599 00:55:55.256135
1600 00:55:55.256218
1601 00:55:55.256299 TX Vref Scan disable
1602 00:55:55.256380 == TX Byte 0 ==
1603 00:55:55.256467 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1604 00:55:55.256550 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1605 00:55:55.256631 == TX Byte 1 ==
1606 00:55:55.256711 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1607 00:55:55.256766 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1608 00:55:55.256818
1609 00:55:55.256870 [DATLAT]
1610 00:55:55.256922 Freq=800, CH1 RK0
1611 00:55:55.256975
1612 00:55:55.257027 DATLAT Default: 0xa
1613 00:55:55.257079 0, 0xFFFF, sum = 0
1614 00:55:55.257134 1, 0xFFFF, sum = 0
1615 00:55:55.257187 2, 0xFFFF, sum = 0
1616 00:55:55.257241 3, 0xFFFF, sum = 0
1617 00:55:55.257340 4, 0xFFFF, sum = 0
1618 00:55:55.257398 5, 0xFFFF, sum = 0
1619 00:55:55.257452 6, 0xFFFF, sum = 0
1620 00:55:55.257540 7, 0xFFFF, sum = 0
1621 00:55:55.257593 8, 0xFFFF, sum = 0
1622 00:55:55.257646 9, 0x0, sum = 1
1623 00:55:55.257699 10, 0x0, sum = 2
1624 00:55:55.257752 11, 0x0, sum = 3
1625 00:55:55.257805 12, 0x0, sum = 4
1626 00:55:55.257858 best_step = 10
1627 00:55:55.257914
1628 00:55:55.257966 ==
1629 00:55:55.258018 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 00:55:55.258071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 00:55:55.258124 ==
1632 00:55:55.258176 RX Vref Scan: 1
1633 00:55:55.258228
1634 00:55:55.258280 Set Vref Range= 32 -> 127
1635 00:55:55.258332
1636 00:55:55.258384 RX Vref 32 -> 127, step: 1
1637 00:55:55.258439
1638 00:55:55.258493 RX Delay -95 -> 252, step: 8
1639 00:55:55.258546
1640 00:55:55.258598 Set Vref, RX VrefLevel [Byte0]: 32
1641 00:55:55.258651 [Byte1]: 32
1642 00:55:55.258703
1643 00:55:55.258755 Set Vref, RX VrefLevel [Byte0]: 33
1644 00:55:55.258807 [Byte1]: 33
1645 00:55:55.258859
1646 00:55:55.258912 Set Vref, RX VrefLevel [Byte0]: 34
1647 00:55:55.258967 [Byte1]: 34
1648 00:55:55.259021
1649 00:55:55.259074 Set Vref, RX VrefLevel [Byte0]: 35
1650 00:55:55.259126 [Byte1]: 35
1651 00:55:55.259178
1652 00:55:55.259230 Set Vref, RX VrefLevel [Byte0]: 36
1653 00:55:55.259282 [Byte1]: 36
1654 00:55:55.259335
1655 00:55:55.259387 Set Vref, RX VrefLevel [Byte0]: 37
1656 00:55:55.259439 [Byte1]: 37
1657 00:55:55.259495
1658 00:55:55.259566 Set Vref, RX VrefLevel [Byte0]: 38
1659 00:55:55.259621 [Byte1]: 38
1660 00:55:55.259675
1661 00:55:55.259728 Set Vref, RX VrefLevel [Byte0]: 39
1662 00:55:55.259794 [Byte1]: 39
1663 00:55:55.259846
1664 00:55:55.259898 Set Vref, RX VrefLevel [Byte0]: 40
1665 00:55:55.259950 [Byte1]: 40
1666 00:55:55.260005
1667 00:55:55.260057 Set Vref, RX VrefLevel [Byte0]: 41
1668 00:55:55.260109 [Byte1]: 41
1669 00:55:55.260193
1670 00:55:55.260312 Set Vref, RX VrefLevel [Byte0]: 42
1671 00:55:55.260394 [Byte1]: 42
1672 00:55:55.260475
1673 00:55:55.260582 Set Vref, RX VrefLevel [Byte0]: 43
1674 00:55:55.260683 [Byte1]: 43
1675 00:55:55.260737
1676 00:55:55.260800 Set Vref, RX VrefLevel [Byte0]: 44
1677 00:55:55.260893 [Byte1]: 44
1678 00:55:55.260977
1679 00:55:55.261066 Set Vref, RX VrefLevel [Byte0]: 45
1680 00:55:55.261160 [Byte1]: 45
1681 00:55:55.261267
1682 00:55:55.261354 Set Vref, RX VrefLevel [Byte0]: 46
1683 00:55:55.261412 [Byte1]: 46
1684 00:55:55.261466
1685 00:55:55.261560 Set Vref, RX VrefLevel [Byte0]: 47
1686 00:55:55.261656 [Byte1]: 47
1687 00:55:55.261752
1688 00:55:55.261852 Set Vref, RX VrefLevel [Byte0]: 48
1689 00:55:55.261952 [Byte1]: 48
1690 00:55:55.262046
1691 00:55:55.262133 Set Vref, RX VrefLevel [Byte0]: 49
1692 00:55:55.262221 [Byte1]: 49
1693 00:55:55.262306
1694 00:55:55.262390 Set Vref, RX VrefLevel [Byte0]: 50
1695 00:55:55.262692 [Byte1]: 50
1696 00:55:55.262783
1697 00:55:55.262871 Set Vref, RX VrefLevel [Byte0]: 51
1698 00:55:55.262956 [Byte1]: 51
1699 00:55:55.263041
1700 00:55:55.263125 Set Vref, RX VrefLevel [Byte0]: 52
1701 00:55:55.263212 [Byte1]: 52
1702 00:55:55.263295
1703 00:55:55.263379 Set Vref, RX VrefLevel [Byte0]: 53
1704 00:55:55.263464 [Byte1]: 53
1705 00:55:55.263546
1706 00:55:55.263630 Set Vref, RX VrefLevel [Byte0]: 54
1707 00:55:55.263715 [Byte1]: 54
1708 00:55:55.263799
1709 00:55:55.263883 Set Vref, RX VrefLevel [Byte0]: 55
1710 00:55:55.263966 [Byte1]: 55
1711 00:55:55.264048
1712 00:55:55.264132 Set Vref, RX VrefLevel [Byte0]: 56
1713 00:55:55.264217 [Byte1]: 56
1714 00:55:55.264300
1715 00:55:55.264383 Set Vref, RX VrefLevel [Byte0]: 57
1716 00:55:55.264467 [Byte1]: 57
1717 00:55:55.264549
1718 00:55:55.264632 Set Vref, RX VrefLevel [Byte0]: 58
1719 00:55:55.264717 [Byte1]: 58
1720 00:55:55.264802
1721 00:55:55.264885 Set Vref, RX VrefLevel [Byte0]: 59
1722 00:55:55.264969 [Byte1]: 59
1723 00:55:55.265051
1724 00:55:55.265135 Set Vref, RX VrefLevel [Byte0]: 60
1725 00:55:55.265218 [Byte1]: 60
1726 00:55:55.265315
1727 00:55:55.265369 Set Vref, RX VrefLevel [Byte0]: 61
1728 00:55:55.265422 [Byte1]: 61
1729 00:55:55.265474
1730 00:55:55.265527 Set Vref, RX VrefLevel [Byte0]: 62
1731 00:55:55.265580 [Byte1]: 62
1732 00:55:55.265633
1733 00:55:55.265686 Set Vref, RX VrefLevel [Byte0]: 63
1734 00:55:55.265738 [Byte1]: 63
1735 00:55:55.265818
1736 00:55:55.265874 Set Vref, RX VrefLevel [Byte0]: 64
1737 00:55:55.265931 [Byte1]: 64
1738 00:55:55.265982
1739 00:55:55.266035 Set Vref, RX VrefLevel [Byte0]: 65
1740 00:55:55.266087 [Byte1]: 65
1741 00:55:55.266139
1742 00:55:55.266191 Set Vref, RX VrefLevel [Byte0]: 66
1743 00:55:55.266244 [Byte1]: 66
1744 00:55:55.266296
1745 00:55:55.266348 Set Vref, RX VrefLevel [Byte0]: 67
1746 00:55:55.266402 [Byte1]: 67
1747 00:55:55.266454
1748 00:55:55.266506 Set Vref, RX VrefLevel [Byte0]: 68
1749 00:55:55.266559 [Byte1]: 68
1750 00:55:55.266611
1751 00:55:55.266663 Set Vref, RX VrefLevel [Byte0]: 69
1752 00:55:55.266715 [Byte1]: 69
1753 00:55:55.266767
1754 00:55:55.266819 Set Vref, RX VrefLevel [Byte0]: 70
1755 00:55:55.266871 [Byte1]: 70
1756 00:55:55.266923
1757 00:55:55.266974 Set Vref, RX VrefLevel [Byte0]: 71
1758 00:55:55.267030 [Byte1]: 71
1759 00:55:55.267103
1760 00:55:55.267169 Set Vref, RX VrefLevel [Byte0]: 72
1761 00:55:55.267222 [Byte1]: 72
1762 00:55:55.267274
1763 00:55:55.267325 Set Vref, RX VrefLevel [Byte0]: 73
1764 00:55:55.267377 [Byte1]: 73
1765 00:55:55.267429
1766 00:55:55.267481 Set Vref, RX VrefLevel [Byte0]: 74
1767 00:55:55.267533 [Byte1]: 74
1768 00:55:55.267588
1769 00:55:55.267640 Set Vref, RX VrefLevel [Byte0]: 75
1770 00:55:55.267693 [Byte1]: 75
1771 00:55:55.267744
1772 00:55:55.267796 Final RX Vref Byte 0 = 57 to rank0
1773 00:55:55.267849 Final RX Vref Byte 1 = 57 to rank0
1774 00:55:55.267903 Final RX Vref Byte 0 = 57 to rank1
1775 00:55:55.267956 Final RX Vref Byte 1 = 57 to rank1==
1776 00:55:55.268008 Dram Type= 6, Freq= 0, CH_1, rank 0
1777 00:55:55.268061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1778 00:55:55.268114 ==
1779 00:55:55.268176 DQS Delay:
1780 00:55:55.268260 DQS0 = 0, DQS1 = 0
1781 00:55:55.268341 DQM Delay:
1782 00:55:55.268422 DQM0 = 85, DQM1 = 80
1783 00:55:55.268502 DQ Delay:
1784 00:55:55.268583 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1785 00:55:55.268665 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1786 00:55:55.268748 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1787 00:55:55.268830 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1788 00:55:55.268911
1789 00:55:55.268991
1790 00:55:55.269074 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e32, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1791 00:55:55.269156 CH1 RK0: MR19=606, MR18=1E32
1792 00:55:55.269239 CH1_RK0: MR19=0x606, MR18=0x1E32, DQSOSC=397, MR23=63, INC=93, DEC=62
1793 00:55:55.269342
1794 00:55:55.269399 ----->DramcWriteLeveling(PI) begin...
1795 00:55:55.269453 ==
1796 00:55:55.269506 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 00:55:55.269558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 00:55:55.269611 ==
1799 00:55:55.269663 Write leveling (Byte 0): 28 => 28
1800 00:55:55.269716 Write leveling (Byte 1): 28 => 28
1801 00:55:55.269769 DramcWriteLeveling(PI) end<-----
1802 00:55:55.269821
1803 00:55:55.269872 ==
1804 00:55:55.269928 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 00:55:55.269981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 00:55:55.270033 ==
1807 00:55:55.270085 [Gating] SW mode calibration
1808 00:55:55.270137 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1809 00:55:55.270191 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1810 00:55:55.270243 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1811 00:55:55.270296 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1812 00:55:55.270348 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1813 00:55:55.270417 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 00:55:55.270488 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:55:55.270545 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:55:55.270598 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:55:55.270650 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:55:55.270702 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:55:55.270755 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:55:55.270807 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:55:55.270859 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:55:55.270912 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 00:55:55.270964 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 00:55:55.271016 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 00:55:55.271073 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 00:55:55.271126 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:55:55.271178 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1828 00:55:55.271230 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1829 00:55:55.271282 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:55:55.271539 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:55:55.271635 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:55:55.271720 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:55:55.271803 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:55:55.271885 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:55:55.271967 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1836 00:55:55.272050 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1837 00:55:55.272132 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 00:55:55.272212 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 00:55:55.272268 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 00:55:55.272321 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 00:55:55.272374 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 00:55:55.272425 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 00:55:55.272478 0 10 4 | B1->B0 | 3030 2828 | 1 1 | (1 1) (1 0)
1844 00:55:55.272530 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
1845 00:55:55.272614 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 00:55:55.272697 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 00:55:55.272816 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 00:55:55.272874 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 00:55:55.272931 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 00:55:55.273014 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 00:55:55.273122 0 11 4 | B1->B0 | 2b2b 3f3e | 0 1 | (0 0) (0 0)
1852 00:55:55.273211 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1853 00:55:55.273316 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 00:55:55.273372 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 00:55:55.273445 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 00:55:55.273528 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 00:55:55.273604 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 00:55:55.273658 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 00:55:55.273711 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1860 00:55:55.273767 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1861 00:55:55.273820 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 00:55:55.273873 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 00:55:55.273925 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 00:55:55.274006 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 00:55:55.274088 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 00:55:55.274172 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 00:55:55.274254 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 00:55:55.274338 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 00:55:55.274420 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 00:55:55.274492 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 00:55:55.274546 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 00:55:55.274598 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 00:55:55.274651 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 00:55:55.274703 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 00:55:55.274755 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1876 00:55:55.274808 Total UI for P1: 0, mck2ui 16
1877 00:55:55.274861 best dqsien dly found for B0: ( 0, 14, 2)
1878 00:55:55.274913 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1879 00:55:55.274966 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 00:55:55.275023 Total UI for P1: 0, mck2ui 16
1881 00:55:55.275109 best dqsien dly found for B1: ( 0, 14, 6)
1882 00:55:55.275192 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1883 00:55:55.275274 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1884 00:55:55.275355
1885 00:55:55.275441 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1886 00:55:55.275539 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1887 00:55:55.275627 [Gating] SW calibration Done
1888 00:55:55.275708 ==
1889 00:55:55.275791 Dram Type= 6, Freq= 0, CH_1, rank 1
1890 00:55:55.275873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1891 00:55:55.275955 ==
1892 00:55:55.276052 RX Vref Scan: 0
1893 00:55:55.276149
1894 00:55:55.276232 RX Vref 0 -> 0, step: 1
1895 00:55:55.276313
1896 00:55:55.276427 RX Delay -130 -> 252, step: 16
1897 00:55:55.276509 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1898 00:55:55.276592 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1899 00:55:55.276674 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1900 00:55:55.276745 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1901 00:55:55.276799 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1902 00:55:55.276851 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1903 00:55:55.276904 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1904 00:55:55.276957 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1905 00:55:55.277009 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1906 00:55:55.277063 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1907 00:55:55.277115 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1908 00:55:55.277167 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1909 00:55:55.277220 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1910 00:55:55.277313 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1911 00:55:55.277369 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1912 00:55:55.277422 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1913 00:55:55.277475 ==
1914 00:55:55.277527 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 00:55:55.277580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 00:55:55.277634 ==
1917 00:55:55.277686 DQS Delay:
1918 00:55:55.277738 DQS0 = 0, DQS1 = 0
1919 00:55:55.277791 DQM Delay:
1920 00:55:55.417204 DQM0 = 83, DQM1 = 82
1921 00:55:55.417392 DQ Delay:
1922 00:55:55.417462 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1923 00:55:55.417524 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1924 00:55:55.417583 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1925 00:55:55.417653 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1926 00:55:55.417789
1927 00:55:55.417851
1928 00:55:55.417907 ==
1929 00:55:55.417963 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 00:55:55.418228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 00:55:55.418318 ==
1932 00:55:55.418404
1933 00:55:55.418486
1934 00:55:55.418569 TX Vref Scan disable
1935 00:55:55.418652 == TX Byte 0 ==
1936 00:55:55.418735 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1937 00:55:55.418796 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1938 00:55:55.418885 == TX Byte 1 ==
1939 00:55:55.418991 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1940 00:55:55.419096 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1941 00:55:55.419234 ==
1942 00:55:55.419357 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 00:55:55.419455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 00:55:55.419538 ==
1945 00:55:55.419620 TX Vref=22, minBit 6, minWin=27, winSum=449
1946 00:55:55.419704 TX Vref=24, minBit 0, minWin=28, winSum=453
1947 00:55:55.419787 TX Vref=26, minBit 6, minWin=27, winSum=452
1948 00:55:55.419872 TX Vref=28, minBit 0, minWin=28, winSum=455
1949 00:55:55.419956 TX Vref=30, minBit 0, minWin=28, winSum=455
1950 00:55:55.420039 TX Vref=32, minBit 0, minWin=27, winSum=452
1951 00:55:55.420122 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 28
1952 00:55:55.420203
1953 00:55:55.420284 Final TX Range 1 Vref 28
1954 00:55:55.420365
1955 00:55:55.420448 ==
1956 00:55:55.420530 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 00:55:55.420612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 00:55:55.420694 ==
1959 00:55:55.420775
1960 00:55:55.420855
1961 00:55:55.420937 TX Vref Scan disable
1962 00:55:55.421020 == TX Byte 0 ==
1963 00:55:55.421102 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1964 00:55:55.421185 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1965 00:55:55.421287 == TX Byte 1 ==
1966 00:55:55.421358 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1967 00:55:55.421411 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1968 00:55:55.421464
1969 00:55:55.421519 [DATLAT]
1970 00:55:55.421572 Freq=800, CH1 RK1
1971 00:55:55.421625
1972 00:55:55.421677 DATLAT Default: 0xa
1973 00:55:55.421730 0, 0xFFFF, sum = 0
1974 00:55:55.421784 1, 0xFFFF, sum = 0
1975 00:55:55.421837 2, 0xFFFF, sum = 0
1976 00:55:55.421891 3, 0xFFFF, sum = 0
1977 00:55:55.421944 4, 0xFFFF, sum = 0
1978 00:55:55.421997 5, 0xFFFF, sum = 0
1979 00:55:55.422054 6, 0xFFFF, sum = 0
1980 00:55:55.422110 7, 0xFFFF, sum = 0
1981 00:55:55.422164 8, 0xFFFF, sum = 0
1982 00:55:55.422218 9, 0x0, sum = 1
1983 00:55:55.422271 10, 0x0, sum = 2
1984 00:55:55.422324 11, 0x0, sum = 3
1985 00:55:55.422378 12, 0x0, sum = 4
1986 00:55:55.422431 best_step = 10
1987 00:55:55.422483
1988 00:55:55.422535 ==
1989 00:55:55.422590 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 00:55:55.422643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 00:55:55.422696 ==
1992 00:55:55.422749 RX Vref Scan: 0
1993 00:55:55.422801
1994 00:55:55.422853 RX Vref 0 -> 0, step: 1
1995 00:55:55.422905
1996 00:55:55.422957 RX Delay -95 -> 252, step: 8
1997 00:55:55.423009 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1998 00:55:55.423062 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1999 00:55:55.423114 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2000 00:55:55.423170 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2001 00:55:55.423226 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2002 00:55:55.423279 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2003 00:55:55.423331 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2004 00:55:55.423384 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2005 00:55:55.423437 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2006 00:55:55.423490 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2007 00:55:55.423542 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2008 00:55:55.423595 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2009 00:55:55.423648 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2010 00:55:55.423704 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2011 00:55:55.423757 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2012 00:55:55.423810 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2013 00:55:55.423862 ==
2014 00:55:55.423914 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 00:55:55.423967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 00:55:55.424020 ==
2017 00:55:55.424073 DQS Delay:
2018 00:55:55.424125 DQS0 = 0, DQS1 = 0
2019 00:55:55.424178 DQM Delay:
2020 00:55:55.424234 DQM0 = 86, DQM1 = 81
2021 00:55:55.424291 DQ Delay:
2022 00:55:55.424344 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2023 00:55:55.424397 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2024 00:55:55.424449 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
2025 00:55:55.424502 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2026 00:55:55.424555
2027 00:55:55.424607
2028 00:55:55.424659 [DQSOSCAuto] RK1, (LSB)MR18= 0x2743, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2029 00:55:55.424713 CH1 RK1: MR19=606, MR18=2743
2030 00:55:55.424782 CH1_RK1: MR19=0x606, MR18=0x2743, DQSOSC=393, MR23=63, INC=95, DEC=63
2031 00:55:55.424864 [RxdqsGatingPostProcess] freq 800
2032 00:55:55.424947 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2033 00:55:55.425029 Pre-setting of DQS Precalculation
2034 00:55:55.425112 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2035 00:55:55.425211 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2036 00:55:55.425318 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2037 00:55:55.425402
2038 00:55:55.425519
2039 00:55:55.425601 [Calibration Summary] 1600 Mbps
2040 00:55:55.425683 CH 0, Rank 0
2041 00:55:55.425764 SW Impedance : PASS
2042 00:55:55.425846 DUTY Scan : NO K
2043 00:55:55.425902 ZQ Calibration : PASS
2044 00:55:55.425955 Jitter Meter : NO K
2045 00:55:55.426008 CBT Training : PASS
2046 00:55:55.426061 Write leveling : PASS
2047 00:55:55.426113 RX DQS gating : PASS
2048 00:55:55.426166 RX DQ/DQS(RDDQC) : PASS
2049 00:55:55.426219 TX DQ/DQS : PASS
2050 00:55:55.426272 RX DATLAT : PASS
2051 00:55:55.426325 RX DQ/DQS(Engine): PASS
2052 00:55:55.426385 TX OE : NO K
2053 00:55:55.426468 All Pass.
2054 00:55:55.426550
2055 00:55:55.426605 CH 0, Rank 1
2056 00:55:55.426658 SW Impedance : PASS
2057 00:55:55.426711 DUTY Scan : NO K
2058 00:55:55.426764 ZQ Calibration : PASS
2059 00:55:55.426816 Jitter Meter : NO K
2060 00:55:55.426870 CBT Training : PASS
2061 00:55:55.426925 Write leveling : PASS
2062 00:55:55.426979 RX DQS gating : PASS
2063 00:55:55.427031 RX DQ/DQS(RDDQC) : PASS
2064 00:55:55.427084 TX DQ/DQS : PASS
2065 00:55:55.427137 RX DATLAT : PASS
2066 00:55:55.427189 RX DQ/DQS(Engine): PASS
2067 00:55:55.427242 TX OE : NO K
2068 00:55:55.427295 All Pass.
2069 00:55:55.427347
2070 00:55:55.427400 CH 1, Rank 0
2071 00:55:55.427452 SW Impedance : PASS
2072 00:55:55.427508 DUTY Scan : NO K
2073 00:55:55.427564 ZQ Calibration : PASS
2074 00:55:55.427618 Jitter Meter : NO K
2075 00:55:55.427670 CBT Training : PASS
2076 00:55:55.427723 Write leveling : PASS
2077 00:55:55.427990 RX DQS gating : PASS
2078 00:55:55.428051 RX DQ/DQS(RDDQC) : PASS
2079 00:55:55.428106 TX DQ/DQS : PASS
2080 00:55:55.428160 RX DATLAT : PASS
2081 00:55:55.428213 RX DQ/DQS(Engine): PASS
2082 00:55:55.428266 TX OE : NO K
2083 00:55:55.428319 All Pass.
2084 00:55:55.428372
2085 00:55:55.428425 CH 1, Rank 1
2086 00:55:55.428478 SW Impedance : PASS
2087 00:55:55.428535 DUTY Scan : NO K
2088 00:55:55.428591 ZQ Calibration : PASS
2089 00:55:55.428645 Jitter Meter : NO K
2090 00:55:55.428698 CBT Training : PASS
2091 00:55:55.428751 Write leveling : PASS
2092 00:55:55.428803 RX DQS gating : PASS
2093 00:55:55.428856 RX DQ/DQS(RDDQC) : PASS
2094 00:55:55.428909 TX DQ/DQS : PASS
2095 00:55:55.428962 RX DATLAT : PASS
2096 00:55:55.429015 RX DQ/DQS(Engine): PASS
2097 00:55:55.429071 TX OE : NO K
2098 00:55:55.429125 All Pass.
2099 00:55:55.429177
2100 00:55:55.429230 DramC Write-DBI off
2101 00:55:55.429322 PER_BANK_REFRESH: Hybrid Mode
2102 00:55:55.429375 TX_TRACKING: ON
2103 00:55:55.429429 [GetDramInforAfterCalByMRR] Vendor 6.
2104 00:55:55.429482 [GetDramInforAfterCalByMRR] Revision 606.
2105 00:55:55.429535 [GetDramInforAfterCalByMRR] Revision 2 0.
2106 00:55:55.429590 MR0 0x3b3b
2107 00:55:55.429646 MR8 0x5151
2108 00:55:55.429699 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 00:55:55.429752
2110 00:55:55.429804 MR0 0x3b3b
2111 00:55:55.429856 MR8 0x5151
2112 00:55:55.429909 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 00:55:55.429962
2114 00:55:55.430014 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2115 00:55:55.430081 [FAST_K] Save calibration result to emmc
2116 00:55:55.430152 [FAST_K] Save calibration result to emmc
2117 00:55:55.430205 dram_init: config_dvfs: 1
2118 00:55:55.430258 dramc_set_vcore_voltage set vcore to 662500
2119 00:55:55.430340 Read voltage for 1200, 2
2120 00:55:55.430393 Vio18 = 0
2121 00:55:55.430445 Vcore = 662500
2122 00:55:55.430498 Vdram = 0
2123 00:55:55.430550 Vddq = 0
2124 00:55:55.430602 Vmddr = 0
2125 00:55:55.430655 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2126 00:55:55.430711 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2127 00:55:55.430766 MEM_TYPE=3, freq_sel=15
2128 00:55:55.430819 sv_algorithm_assistance_LP4_1600
2129 00:55:55.430871 ============ PULL DRAM RESETB DOWN ============
2130 00:55:55.430925 ========== PULL DRAM RESETB DOWN end =========
2131 00:55:55.430978 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 00:55:55.431030 ===================================
2133 00:55:55.431083 LPDDR4 DRAM CONFIGURATION
2134 00:55:55.431136 ===================================
2135 00:55:55.431189 EX_ROW_EN[0] = 0x0
2136 00:55:55.431247 EX_ROW_EN[1] = 0x0
2137 00:55:55.431300 LP4Y_EN = 0x0
2138 00:55:55.431352 WORK_FSP = 0x0
2139 00:55:55.431405 WL = 0x4
2140 00:55:55.431457 RL = 0x4
2141 00:55:55.431510 BL = 0x2
2142 00:55:55.431562 RPST = 0x0
2143 00:55:55.431615 RD_PRE = 0x0
2144 00:55:55.431667 WR_PRE = 0x1
2145 00:55:55.431720 WR_PST = 0x0
2146 00:55:55.431775 DBI_WR = 0x0
2147 00:55:55.431831 DBI_RD = 0x0
2148 00:55:55.431913 OTF = 0x1
2149 00:55:55.431996 ===================================
2150 00:55:55.432079 ===================================
2151 00:55:55.432161 ANA top config
2152 00:55:55.432243 ===================================
2153 00:55:55.432325 DLL_ASYNC_EN = 0
2154 00:55:55.432383 ALL_SLAVE_EN = 0
2155 00:55:55.432436 NEW_RANK_MODE = 1
2156 00:55:55.432490 DLL_IDLE_MODE = 1
2157 00:55:55.432543 LP45_APHY_COMB_EN = 1
2158 00:55:55.432595 TX_ODT_DIS = 1
2159 00:55:55.432648 NEW_8X_MODE = 1
2160 00:55:55.432701 ===================================
2161 00:55:55.432755 ===================================
2162 00:55:55.432808 data_rate = 2400
2163 00:55:55.432861 CKR = 1
2164 00:55:55.432931 DQ_P2S_RATIO = 8
2165 00:55:55.433014 ===================================
2166 00:55:55.433097 CA_P2S_RATIO = 8
2167 00:55:55.433179 DQ_CA_OPEN = 0
2168 00:55:55.433267 DQ_SEMI_OPEN = 0
2169 00:55:55.433356 CA_SEMI_OPEN = 0
2170 00:55:55.433410 CA_FULL_RATE = 0
2171 00:55:55.433467 DQ_CKDIV4_EN = 0
2172 00:55:55.433521 CA_CKDIV4_EN = 0
2173 00:55:55.433574 CA_PREDIV_EN = 0
2174 00:55:55.433626 PH8_DLY = 17
2175 00:55:55.433679 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2176 00:55:55.433732 DQ_AAMCK_DIV = 4
2177 00:55:55.433785 CA_AAMCK_DIV = 4
2178 00:55:55.433837 CA_ADMCK_DIV = 4
2179 00:55:55.433890 DQ_TRACK_CA_EN = 0
2180 00:55:55.433942 CA_PICK = 1200
2181 00:55:55.433998 CA_MCKIO = 1200
2182 00:55:55.434054 MCKIO_SEMI = 0
2183 00:55:55.434107 PLL_FREQ = 2366
2184 00:55:55.434160 DQ_UI_PI_RATIO = 32
2185 00:55:55.434213 CA_UI_PI_RATIO = 0
2186 00:55:55.434266 ===================================
2187 00:55:55.434319 ===================================
2188 00:55:55.434372 memory_type:LPDDR4
2189 00:55:55.434425 GP_NUM : 10
2190 00:55:55.434477 SRAM_EN : 1
2191 00:55:55.434530 MD32_EN : 0
2192 00:55:55.434588 ===================================
2193 00:55:55.434642 [ANA_INIT] >>>>>>>>>>>>>>
2194 00:55:55.434695 <<<<<< [CONFIGURE PHASE]: ANA_TX
2195 00:55:55.434748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2196 00:55:55.434801 ===================================
2197 00:55:55.434854 data_rate = 2400,PCW = 0X5b00
2198 00:55:55.434907 ===================================
2199 00:55:55.434960 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2200 00:55:55.435013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 00:55:55.435069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 00:55:55.435125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2203 00:55:55.435179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2204 00:55:55.435248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2205 00:55:55.435329 [ANA_INIT] flow start
2206 00:55:55.435396 [ANA_INIT] PLL >>>>>>>>
2207 00:55:55.435464 [ANA_INIT] PLL <<<<<<<<
2208 00:55:55.435531 [ANA_INIT] MIDPI >>>>>>>>
2209 00:55:55.435586 [ANA_INIT] MIDPI <<<<<<<<
2210 00:55:55.435640 [ANA_INIT] DLL >>>>>>>>
2211 00:55:55.435693 [ANA_INIT] DLL <<<<<<<<
2212 00:55:55.435745 [ANA_INIT] flow end
2213 00:55:55.435797 ============ LP4 DIFF to SE enter ============
2214 00:55:55.436047 ============ LP4 DIFF to SE exit ============
2215 00:55:55.436106 [ANA_INIT] <<<<<<<<<<<<<
2216 00:55:55.436163 [Flow] Enable top DCM control >>>>>
2217 00:55:55.436220 [Flow] Enable top DCM control <<<<<
2218 00:55:55.436273 Enable DLL master slave shuffle
2219 00:55:55.436327 ==============================================================
2220 00:55:55.436380 Gating Mode config
2221 00:55:55.436433 ==============================================================
2222 00:55:55.436486 Config description:
2223 00:55:55.436539 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2224 00:55:55.436593 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2225 00:55:55.436646 SELPH_MODE 0: By rank 1: By Phase
2226 00:55:55.436703 ==============================================================
2227 00:55:55.436757 GAT_TRACK_EN = 1
2228 00:55:55.436809 RX_GATING_MODE = 2
2229 00:55:55.436862 RX_GATING_TRACK_MODE = 2
2230 00:55:55.436915 SELPH_MODE = 1
2231 00:55:55.436967 PICG_EARLY_EN = 1
2232 00:55:55.437020 VALID_LAT_VALUE = 1
2233 00:55:55.437072 ==============================================================
2234 00:55:55.437125 Enter into Gating configuration >>>>
2235 00:55:55.437178 Exit from Gating configuration <<<<
2236 00:55:55.437230 Enter into DVFS_PRE_config >>>>>
2237 00:55:55.437338 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2238 00:55:55.437395 Exit from DVFS_PRE_config <<<<<
2239 00:55:55.437448 Enter into PICG configuration >>>>
2240 00:55:55.437501 Exit from PICG configuration <<<<
2241 00:55:55.437554 [RX_INPUT] configuration >>>>>
2242 00:55:55.437606 [RX_INPUT] configuration <<<<<
2243 00:55:55.437659 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2244 00:55:55.437712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2245 00:55:55.437765 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 00:55:55.437823 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 00:55:55.437877 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 00:55:55.437930 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 00:55:55.437983 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2250 00:55:55.438036 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2251 00:55:55.438089 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2252 00:55:55.438141 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2253 00:55:55.438194 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2254 00:55:55.438247 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2255 00:55:55.438300 ===================================
2256 00:55:55.438357 LPDDR4 DRAM CONFIGURATION
2257 00:55:55.438412 ===================================
2258 00:55:55.438466 EX_ROW_EN[0] = 0x0
2259 00:55:55.438519 EX_ROW_EN[1] = 0x0
2260 00:55:55.438602 LP4Y_EN = 0x0
2261 00:55:55.438655 WORK_FSP = 0x0
2262 00:55:55.438707 WL = 0x4
2263 00:55:55.438760 RL = 0x4
2264 00:55:55.438812 BL = 0x2
2265 00:55:55.438864 RPST = 0x0
2266 00:55:55.438921 RD_PRE = 0x0
2267 00:55:55.438975 WR_PRE = 0x1
2268 00:55:55.439028 WR_PST = 0x0
2269 00:55:55.439080 DBI_WR = 0x0
2270 00:55:55.439133 DBI_RD = 0x0
2271 00:55:55.439184 OTF = 0x1
2272 00:55:55.439237 ===================================
2273 00:55:55.439290 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2274 00:55:55.439344 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2275 00:55:55.439397 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2276 00:55:55.439453 ===================================
2277 00:55:55.439509 LPDDR4 DRAM CONFIGURATION
2278 00:55:55.439563 ===================================
2279 00:55:55.439616 EX_ROW_EN[0] = 0x10
2280 00:55:55.439668 EX_ROW_EN[1] = 0x0
2281 00:55:55.439721 LP4Y_EN = 0x0
2282 00:55:55.439773 WORK_FSP = 0x0
2283 00:55:55.439825 WL = 0x4
2284 00:55:55.439878 RL = 0x4
2285 00:55:55.439930 BL = 0x2
2286 00:55:55.439983 RPST = 0x0
2287 00:55:55.440040 RD_PRE = 0x0
2288 00:55:55.440093 WR_PRE = 0x1
2289 00:55:55.440145 WR_PST = 0x0
2290 00:55:55.440198 DBI_WR = 0x0
2291 00:55:55.440250 DBI_RD = 0x0
2292 00:55:55.440303 OTF = 0x1
2293 00:55:55.440355 ===================================
2294 00:55:55.440408 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2295 00:55:55.440461 ==
2296 00:55:55.440513 Dram Type= 6, Freq= 0, CH_0, rank 0
2297 00:55:55.440566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2298 00:55:55.440641 ==
2299 00:55:55.440698 [Duty_Offset_Calibration]
2300 00:55:55.440751 B0:2 B1:0 CA:4
2301 00:55:55.440804
2302 00:55:55.440856 [DutyScan_Calibration_Flow] k_type=0
2303 00:55:55.440907
2304 00:55:55.440959 ==CLK 0==
2305 00:55:55.441012 Final CLK duty delay cell = 0
2306 00:55:55.441065 [0] MAX Duty = 5156%(X100), DQS PI = 14
2307 00:55:55.441122 [0] MIN Duty = 5000%(X100), DQS PI = 8
2308 00:55:55.441220 [0] AVG Duty = 5078%(X100)
2309 00:55:55.441323
2310 00:55:55.441405 CH0 CLK Duty spec in!! Max-Min= 156%
2311 00:55:55.441487 [DutyScan_Calibration_Flow] ====Done====
2312 00:55:55.441568
2313 00:55:55.441653 [DutyScan_Calibration_Flow] k_type=1
2314 00:55:55.441718
2315 00:55:55.441771 ==DQS 0 ==
2316 00:55:55.441825 Final DQS duty delay cell = 0
2317 00:55:55.441878 [0] MAX Duty = 5156%(X100), DQS PI = 18
2318 00:55:55.441930 [0] MIN Duty = 5093%(X100), DQS PI = 0
2319 00:55:55.441983 [0] AVG Duty = 5124%(X100)
2320 00:55:55.442035
2321 00:55:55.442087 ==DQS 1 ==
2322 00:55:55.442166 Final DQS duty delay cell = 0
2323 00:55:55.442218 [0] MAX Duty = 5125%(X100), DQS PI = 50
2324 00:55:55.442275 [0] MIN Duty = 4969%(X100), DQS PI = 62
2325 00:55:55.442328 [0] AVG Duty = 5047%(X100)
2326 00:55:55.442380
2327 00:55:55.442432 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2328 00:55:55.442485
2329 00:55:55.442537 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2330 00:55:55.442590 [DutyScan_Calibration_Flow] ====Done====
2331 00:55:55.442642
2332 00:55:55.442694 [DutyScan_Calibration_Flow] k_type=3
2333 00:55:55.442746
2334 00:55:55.442798 ==DQM 0 ==
2335 00:55:55.442854 Final DQM duty delay cell = 0
2336 00:55:55.443106 [0] MAX Duty = 5062%(X100), DQS PI = 18
2337 00:55:55.443167 [0] MIN Duty = 4844%(X100), DQS PI = 44
2338 00:55:55.443222 [0] AVG Duty = 4953%(X100)
2339 00:55:55.443301
2340 00:55:55.443382 ==DQM 1 ==
2341 00:55:55.443468 Final DQM duty delay cell = 0
2342 00:55:55.443523 [0] MAX Duty = 4969%(X100), DQS PI = 2
2343 00:55:55.443577 [0] MIN Duty = 4875%(X100), DQS PI = 18
2344 00:55:55.443630 [0] AVG Duty = 4922%(X100)
2345 00:55:55.443684
2346 00:55:55.443751 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2347 00:55:55.443804
2348 00:55:55.443855 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2349 00:55:55.443921 [DutyScan_Calibration_Flow] ====Done====
2350 00:55:55.443992
2351 00:55:55.444048 [DutyScan_Calibration_Flow] k_type=2
2352 00:55:55.444101
2353 00:55:55.444153 ==DQ 0 ==
2354 00:55:55.444206 Final DQ duty delay cell = 0
2355 00:55:55.444258 [0] MAX Duty = 5125%(X100), DQS PI = 18
2356 00:55:55.444311 [0] MIN Duty = 4969%(X100), DQS PI = 58
2357 00:55:55.444363 [0] AVG Duty = 5047%(X100)
2358 00:55:55.444416
2359 00:55:55.444467 ==DQ 1 ==
2360 00:55:55.444524 Final DQ duty delay cell = 0
2361 00:55:55.444577 [0] MAX Duty = 5156%(X100), DQS PI = 4
2362 00:55:55.444630 [0] MIN Duty = 4938%(X100), DQS PI = 16
2363 00:55:55.444681 [0] AVG Duty = 5047%(X100)
2364 00:55:55.444734
2365 00:55:55.444786 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2366 00:55:55.444839
2367 00:55:55.444891 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2368 00:55:55.444943 [DutyScan_Calibration_Flow] ====Done====
2369 00:55:55.444996 ==
2370 00:55:55.445051 Dram Type= 6, Freq= 0, CH_1, rank 0
2371 00:55:55.445104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 00:55:55.445186 ==
2373 00:55:55.445290 [Duty_Offset_Calibration]
2374 00:55:55.445361 B0:0 B1:-1 CA:3
2375 00:55:55.445414
2376 00:55:55.445467 [DutyScan_Calibration_Flow] k_type=0
2377 00:55:55.445520
2378 00:55:55.445594 ==CLK 0==
2379 00:55:55.445662 Final CLK duty delay cell = -4
2380 00:55:55.445719 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2381 00:55:55.445773 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2382 00:55:55.445825 [-4] AVG Duty = 4938%(X100)
2383 00:55:55.445877
2384 00:55:55.445929 CH1 CLK Duty spec in!! Max-Min= 124%
2385 00:55:55.445982 [DutyScan_Calibration_Flow] ====Done====
2386 00:55:55.446035
2387 00:55:55.446087 [DutyScan_Calibration_Flow] k_type=1
2388 00:55:55.446140
2389 00:55:55.446192 ==DQS 0 ==
2390 00:55:55.446314 Final DQS duty delay cell = 0
2391 00:55:55.446370 [0] MAX Duty = 5187%(X100), DQS PI = 18
2392 00:55:55.446435 [0] MIN Duty = 4907%(X100), DQS PI = 38
2393 00:55:55.446496 [0] AVG Duty = 5047%(X100)
2394 00:55:55.446553
2395 00:55:55.446624 ==DQS 1 ==
2396 00:55:55.446707 Final DQS duty delay cell = 0
2397 00:55:55.446794 [0] MAX Duty = 5156%(X100), DQS PI = 8
2398 00:55:55.446877 [0] MIN Duty = 5031%(X100), DQS PI = 18
2399 00:55:55.446962 [0] AVG Duty = 5093%(X100)
2400 00:55:55.447044
2401 00:55:55.447129 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2402 00:55:55.447212
2403 00:55:55.447293 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2404 00:55:55.447381 [DutyScan_Calibration_Flow] ====Done====
2405 00:55:55.447462
2406 00:55:55.447548 [DutyScan_Calibration_Flow] k_type=3
2407 00:55:55.447630
2408 00:55:55.447713 ==DQM 0 ==
2409 00:55:55.447796 Final DQM duty delay cell = 0
2410 00:55:55.447880 [0] MAX Duty = 5031%(X100), DQS PI = 28
2411 00:55:55.447963 [0] MIN Duty = 4813%(X100), DQS PI = 38
2412 00:55:55.448044 [0] AVG Duty = 4922%(X100)
2413 00:55:55.448126
2414 00:55:55.448207 ==DQM 1 ==
2415 00:55:55.448289 Final DQM duty delay cell = 0
2416 00:55:55.448367 [0] MAX Duty = 5000%(X100), DQS PI = 32
2417 00:55:55.448422 [0] MIN Duty = 4844%(X100), DQS PI = 0
2418 00:55:55.448475 [0] AVG Duty = 4922%(X100)
2419 00:55:55.448528
2420 00:55:55.448580 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2421 00:55:55.448632
2422 00:55:55.448686 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2423 00:55:55.448739 [DutyScan_Calibration_Flow] ====Done====
2424 00:55:55.448791
2425 00:55:55.448843 [DutyScan_Calibration_Flow] k_type=2
2426 00:55:55.448896
2427 00:55:55.448974 ==DQ 0 ==
2428 00:55:55.449056 Final DQ duty delay cell = -4
2429 00:55:55.449138 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2430 00:55:55.449220 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2431 00:55:55.449357 [-4] AVG Duty = 4922%(X100)
2432 00:55:55.449412
2433 00:55:55.449465 ==DQ 1 ==
2434 00:55:55.449521 Final DQ duty delay cell = 4
2435 00:55:55.449576 [4] MAX Duty = 5156%(X100), DQS PI = 26
2436 00:55:55.449629 [4] MIN Duty = 5031%(X100), DQS PI = 62
2437 00:55:55.449681 [4] AVG Duty = 5093%(X100)
2438 00:55:55.449734
2439 00:55:55.449786 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2440 00:55:55.449839
2441 00:55:55.449891 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2442 00:55:55.449943 [DutyScan_Calibration_Flow] ====Done====
2443 00:55:55.449995 nWR fixed to 30
2444 00:55:55.450049 [ModeRegInit_LP4] CH0 RK0
2445 00:55:55.450100 [ModeRegInit_LP4] CH0 RK1
2446 00:55:55.450157 [ModeRegInit_LP4] CH1 RK0
2447 00:55:55.450209 [ModeRegInit_LP4] CH1 RK1
2448 00:55:55.450262 match AC timing 7
2449 00:55:55.450314 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2450 00:55:55.450367 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2451 00:55:55.450420 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2452 00:55:55.450473 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2453 00:55:55.450526 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2454 00:55:55.450579 ==
2455 00:55:55.450632 Dram Type= 6, Freq= 0, CH_0, rank 0
2456 00:55:55.450685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2457 00:55:55.450741 ==
2458 00:55:55.450794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2459 00:55:55.450848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2460 00:55:55.450900 [CA 0] Center 39 (9~70) winsize 62
2461 00:55:55.450954 [CA 1] Center 38 (8~69) winsize 62
2462 00:55:55.451008 [CA 2] Center 35 (5~66) winsize 62
2463 00:55:55.451060 [CA 3] Center 35 (4~66) winsize 63
2464 00:55:55.451113 [CA 4] Center 33 (3~64) winsize 62
2465 00:55:55.451165 [CA 5] Center 33 (3~63) winsize 61
2466 00:55:55.451217
2467 00:55:55.451270 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2468 00:55:55.451327
2469 00:55:55.451422 [CATrainingPosCal] consider 1 rank data
2470 00:55:55.451480 u2DelayCellTimex100 = 270/100 ps
2471 00:55:55.451533 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2472 00:55:55.451586 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2473 00:55:55.451639 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2474 00:55:55.451691 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2475 00:55:55.451743 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2476 00:55:55.451796 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2477 00:55:55.451891
2478 00:55:55.451961 CA PerBit enable=1, Macro0, CA PI delay=33
2479 00:55:55.452014
2480 00:55:55.452067 [CBTSetCACLKResult] CA Dly = 33
2481 00:55:55.452119 CS Dly: 7 (0~38)
2482 00:55:55.452171 ==
2483 00:55:55.452223 Dram Type= 6, Freq= 0, CH_0, rank 1
2484 00:55:55.452276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 00:55:55.452328 ==
2486 00:55:55.452583 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 00:55:55.452643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2488 00:55:55.452697 [CA 0] Center 39 (9~70) winsize 62
2489 00:55:55.452752 [CA 1] Center 39 (9~70) winsize 62
2490 00:55:55.452805 [CA 2] Center 35 (5~66) winsize 62
2491 00:55:55.452858 [CA 3] Center 35 (5~66) winsize 62
2492 00:55:55.452911 [CA 4] Center 34 (3~65) winsize 63
2493 00:55:55.452963 [CA 5] Center 33 (3~63) winsize 61
2494 00:55:55.453015
2495 00:55:55.453068 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2496 00:55:55.453120
2497 00:55:55.453220 [CATrainingPosCal] consider 2 rank data
2498 00:55:55.453315 u2DelayCellTimex100 = 270/100 ps
2499 00:55:55.453370 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2500 00:55:55.453431 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2501 00:55:55.453518 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 00:55:55.453588 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 00:55:55.453643 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2504 00:55:55.453698 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2505 00:55:55.453752
2506 00:55:55.453805 CA PerBit enable=1, Macro0, CA PI delay=33
2507 00:55:55.453858
2508 00:55:55.453911 [CBTSetCACLKResult] CA Dly = 33
2509 00:55:55.453964 CS Dly: 8 (0~40)
2510 00:55:55.454017
2511 00:55:55.454069 ----->DramcWriteLeveling(PI) begin...
2512 00:55:55.454123 ==
2513 00:55:55.454176 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 00:55:55.454228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 00:55:55.454284 ==
2516 00:55:55.454338 Write leveling (Byte 0): 29 => 29
2517 00:55:55.454391 Write leveling (Byte 1): 25 => 25
2518 00:55:55.454443 DramcWriteLeveling(PI) end<-----
2519 00:55:55.454495
2520 00:55:55.454547 ==
2521 00:55:55.454599 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 00:55:55.454651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 00:55:55.454703 ==
2524 00:55:55.454755 [Gating] SW mode calibration
2525 00:55:55.454808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2526 00:55:55.454865 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2527 00:55:55.454918 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2528 00:55:55.454971 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2529 00:55:55.455024 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 00:55:55.455077 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 00:55:55.455129 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 00:55:55.455181 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 00:55:55.455233 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2534 00:55:55.455286 0 15 28 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
2535 00:55:55.455338 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
2536 00:55:55.455391 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2537 00:55:55.455443 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 00:55:55.455499 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 00:55:55.455553 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 00:55:55.455606 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 00:55:55.455658 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2542 00:55:55.455710 1 0 28 | B1->B0 | 2323 4444 | 0 1 | (0 0) (0 0)
2543 00:55:55.455762 1 1 0 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2544 00:55:55.455814 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 00:55:55.455866 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 00:55:55.455919 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 00:55:55.455971 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 00:55:55.456023 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 00:55:55.456080 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2550 00:55:55.456133 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2551 00:55:55.456185 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2552 00:55:55.456237 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 00:55:55.456290 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 00:55:55.456342 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 00:55:55.456393 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 00:55:55.456446 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 00:55:55.456498 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 00:55:55.456551 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 00:55:55.456603 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 00:55:55.456660 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 00:55:55.456713 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 00:55:55.456765 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 00:55:55.456817 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 00:55:55.456870 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 00:55:55.456923 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2566 00:55:55.456975 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2567 00:55:55.457028 Total UI for P1: 0, mck2ui 16
2568 00:55:55.457081 best dqsien dly found for B0: ( 1, 3, 24)
2569 00:55:55.457135 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 00:55:55.457188 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 00:55:55.457244 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 00:55:55.457340 Total UI for P1: 0, mck2ui 16
2573 00:55:55.457394 best dqsien dly found for B1: ( 1, 4, 0)
2574 00:55:55.457447 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2575 00:55:55.457500 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2576 00:55:55.457553
2577 00:55:55.457605 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2578 00:55:55.457658 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2579 00:55:55.457710 [Gating] SW calibration Done
2580 00:55:55.457763 ==
2581 00:55:55.457816 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 00:55:55.457873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 00:55:55.457927 ==
2584 00:55:55.457979 RX Vref Scan: 0
2585 00:55:55.458031
2586 00:55:55.458084 RX Vref 0 -> 0, step: 1
2587 00:55:55.458136
2588 00:55:55.458188 RX Delay -40 -> 252, step: 8
2589 00:55:55.458241 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2590 00:55:55.458492 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2591 00:55:55.458551 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2592 00:55:55.458606 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2593 00:55:55.458658 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2594 00:55:55.458711 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2595 00:55:55.458764 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2596 00:55:55.458817 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2597 00:55:55.458869 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2598 00:55:55.458922 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2599 00:55:55.459004 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2600 00:55:55.459061 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2601 00:55:55.459115 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2602 00:55:55.459167 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2603 00:55:55.459220 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2604 00:55:55.459272 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2605 00:55:55.459325 ==
2606 00:55:55.459377 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 00:55:55.459429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 00:55:55.459482 ==
2609 00:55:55.459551 DQS Delay:
2610 00:55:55.459622 DQS0 = 0, DQS1 = 0
2611 00:55:55.459675 DQM Delay:
2612 00:55:55.459729 DQM0 = 119, DQM1 = 106
2613 00:55:55.459781 DQ Delay:
2614 00:55:55.459834 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2615 00:55:55.459886 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2616 00:55:55.459940 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2617 00:55:55.459992 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =111
2618 00:55:55.460045
2619 00:55:55.460111
2620 00:55:55.460180 ==
2621 00:55:55.460232 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 00:55:55.460285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 00:55:55.460338 ==
2624 00:55:55.460391
2625 00:55:55.460442
2626 00:55:55.460494 TX Vref Scan disable
2627 00:55:55.460546 == TX Byte 0 ==
2628 00:55:55.460599 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2629 00:55:55.460669 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2630 00:55:55.460735 == TX Byte 1 ==
2631 00:55:55.460791 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2632 00:55:55.460844 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2633 00:55:55.460897 ==
2634 00:55:55.460948 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 00:55:55.461001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 00:55:55.461054 ==
2637 00:55:55.461106 TX Vref=22, minBit 0, minWin=25, winSum=414
2638 00:55:55.461159 TX Vref=24, minBit 1, minWin=25, winSum=420
2639 00:55:55.461212 TX Vref=26, minBit 8, minWin=25, winSum=423
2640 00:55:55.461304 TX Vref=28, minBit 1, minWin=26, winSum=428
2641 00:55:55.461361 TX Vref=30, minBit 2, minWin=26, winSum=429
2642 00:55:55.461413 TX Vref=32, minBit 0, minWin=26, winSum=429
2643 00:55:55.461466 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
2644 00:55:55.461519
2645 00:55:55.461571 Final TX Range 1 Vref 30
2646 00:55:55.461624
2647 00:55:55.461675 ==
2648 00:55:55.461728 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 00:55:55.461780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 00:55:55.461836 ==
2651 00:55:55.461889
2652 00:55:55.461941
2653 00:55:55.461992 TX Vref Scan disable
2654 00:55:55.462069 == TX Byte 0 ==
2655 00:55:55.462134 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2656 00:55:55.462187 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2657 00:55:55.462240 == TX Byte 1 ==
2658 00:55:55.462293 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2659 00:55:55.462346 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2660 00:55:55.462398
2661 00:55:55.462453 [DATLAT]
2662 00:55:55.462506 Freq=1200, CH0 RK0
2663 00:55:55.462559
2664 00:55:55.462611 DATLAT Default: 0xd
2665 00:55:55.462663 0, 0xFFFF, sum = 0
2666 00:55:55.462717 1, 0xFFFF, sum = 0
2667 00:55:55.462771 2, 0xFFFF, sum = 0
2668 00:55:55.462824 3, 0xFFFF, sum = 0
2669 00:55:55.462878 4, 0xFFFF, sum = 0
2670 00:55:55.462931 5, 0xFFFF, sum = 0
2671 00:55:55.462985 6, 0xFFFF, sum = 0
2672 00:55:55.463042 7, 0xFFFF, sum = 0
2673 00:55:55.463096 8, 0xFFFF, sum = 0
2674 00:55:55.463149 9, 0xFFFF, sum = 0
2675 00:55:55.463202 10, 0xFFFF, sum = 0
2676 00:55:55.463255 11, 0xFFFF, sum = 0
2677 00:55:55.463308 12, 0x0, sum = 1
2678 00:55:55.463362 13, 0x0, sum = 2
2679 00:55:55.463414 14, 0x0, sum = 3
2680 00:55:55.463468 15, 0x0, sum = 4
2681 00:55:55.463521 best_step = 13
2682 00:55:55.463573
2683 00:55:55.463629 ==
2684 00:55:55.463682 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 00:55:55.463735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 00:55:55.463788 ==
2687 00:55:55.463840 RX Vref Scan: 1
2688 00:55:55.463892
2689 00:55:55.463944 Set Vref Range= 32 -> 127
2690 00:55:55.463997
2691 00:55:55.464050 RX Vref 32 -> 127, step: 1
2692 00:55:55.464102
2693 00:55:55.464154 RX Delay -21 -> 252, step: 4
2694 00:55:55.464211
2695 00:55:55.464263 Set Vref, RX VrefLevel [Byte0]: 32
2696 00:55:55.464316 [Byte1]: 32
2697 00:55:55.464368
2698 00:55:55.464420 Set Vref, RX VrefLevel [Byte0]: 33
2699 00:55:55.464473 [Byte1]: 33
2700 00:55:55.464525
2701 00:55:55.464577 Set Vref, RX VrefLevel [Byte0]: 34
2702 00:55:55.464630 [Byte1]: 34
2703 00:55:55.464682
2704 00:55:55.464734 Set Vref, RX VrefLevel [Byte0]: 35
2705 00:55:55.464789 [Byte1]: 35
2706 00:55:55.464842
2707 00:55:55.464894 Set Vref, RX VrefLevel [Byte0]: 36
2708 00:55:55.464947 [Byte1]: 36
2709 00:55:55.464999
2710 00:55:55.465050 Set Vref, RX VrefLevel [Byte0]: 37
2711 00:55:55.465103 [Byte1]: 37
2712 00:55:55.465155
2713 00:55:55.465206 Set Vref, RX VrefLevel [Byte0]: 38
2714 00:55:55.465265 [Byte1]: 38
2715 00:55:55.465355
2716 00:55:55.465409 Set Vref, RX VrefLevel [Byte0]: 39
2717 00:55:55.465461 [Byte1]: 39
2718 00:55:55.465513
2719 00:55:55.465565 Set Vref, RX VrefLevel [Byte0]: 40
2720 00:55:55.465618 [Byte1]: 40
2721 00:55:55.465670
2722 00:55:55.465721 Set Vref, RX VrefLevel [Byte0]: 41
2723 00:55:55.465773 [Byte1]: 41
2724 00:55:55.465825
2725 00:55:55.465877 Set Vref, RX VrefLevel [Byte0]: 42
2726 00:55:55.465933 [Byte1]: 42
2727 00:55:55.465986
2728 00:55:55.466039 Set Vref, RX VrefLevel [Byte0]: 43
2729 00:55:55.466091 [Byte1]: 43
2730 00:55:55.466143
2731 00:55:55.466195 Set Vref, RX VrefLevel [Byte0]: 44
2732 00:55:55.466248 [Byte1]: 44
2733 00:55:55.466300
2734 00:55:55.466352 Set Vref, RX VrefLevel [Byte0]: 45
2735 00:55:55.466404 [Byte1]: 45
2736 00:55:55.466459
2737 00:55:55.466511 Set Vref, RX VrefLevel [Byte0]: 46
2738 00:55:55.466563 [Byte1]: 46
2739 00:55:55.466615
2740 00:55:55.466667 Set Vref, RX VrefLevel [Byte0]: 47
2741 00:55:55.466720 [Byte1]: 47
2742 00:55:55.466772
2743 00:55:55.466824 Set Vref, RX VrefLevel [Byte0]: 48
2744 00:55:55.466876 [Byte1]: 48
2745 00:55:55.466929
2746 00:55:55.466981 Set Vref, RX VrefLevel [Byte0]: 49
2747 00:55:55.467230 [Byte1]: 49
2748 00:55:55.467289
2749 00:55:55.467342 Set Vref, RX VrefLevel [Byte0]: 50
2750 00:55:55.467396 [Byte1]: 50
2751 00:55:55.467448
2752 00:55:55.467500 Set Vref, RX VrefLevel [Byte0]: 51
2753 00:55:55.467555 [Byte1]: 51
2754 00:55:55.467609
2755 00:55:55.467661 Set Vref, RX VrefLevel [Byte0]: 52
2756 00:55:55.467714 [Byte1]: 52
2757 00:55:55.467766
2758 00:55:55.467818 Set Vref, RX VrefLevel [Byte0]: 53
2759 00:55:55.467870 [Byte1]: 53
2760 00:55:55.467922
2761 00:55:55.467974 Set Vref, RX VrefLevel [Byte0]: 54
2762 00:55:55.468026 [Byte1]: 54
2763 00:55:55.468078
2764 00:55:55.468133 Set Vref, RX VrefLevel [Byte0]: 55
2765 00:55:55.468186 [Byte1]: 55
2766 00:55:55.468238
2767 00:55:55.468290 Set Vref, RX VrefLevel [Byte0]: 56
2768 00:55:55.468342 [Byte1]: 56
2769 00:55:55.468394
2770 00:55:55.468446 Set Vref, RX VrefLevel [Byte0]: 57
2771 00:55:55.468498 [Byte1]: 57
2772 00:55:55.468550
2773 00:55:55.468601 Set Vref, RX VrefLevel [Byte0]: 58
2774 00:55:55.468653 [Byte1]: 58
2775 00:55:55.468709
2776 00:55:55.468762 Set Vref, RX VrefLevel [Byte0]: 59
2777 00:55:55.468814 [Byte1]: 59
2778 00:55:55.468866
2779 00:55:55.468918 Set Vref, RX VrefLevel [Byte0]: 60
2780 00:55:55.468971 [Byte1]: 60
2781 00:55:55.469023
2782 00:55:55.469074 Set Vref, RX VrefLevel [Byte0]: 61
2783 00:55:55.469127 [Byte1]: 61
2784 00:55:55.469180
2785 00:55:55.469240 Set Vref, RX VrefLevel [Byte0]: 62
2786 00:55:55.469346 [Byte1]: 62
2787 00:55:55.469399
2788 00:55:55.469451 Set Vref, RX VrefLevel [Byte0]: 63
2789 00:55:55.469504 [Byte1]: 63
2790 00:55:55.469557
2791 00:55:55.469609 Set Vref, RX VrefLevel [Byte0]: 64
2792 00:55:55.469661 [Byte1]: 64
2793 00:55:55.469713
2794 00:55:55.469768 Set Vref, RX VrefLevel [Byte0]: 65
2795 00:55:55.469821 [Byte1]: 65
2796 00:55:55.469874
2797 00:55:55.469926 Set Vref, RX VrefLevel [Byte0]: 66
2798 00:55:55.469978 [Byte1]: 66
2799 00:55:55.470031
2800 00:55:55.470083 Set Vref, RX VrefLevel [Byte0]: 67
2801 00:55:55.470135 [Byte1]: 67
2802 00:55:55.470187
2803 00:55:55.470238 Set Vref, RX VrefLevel [Byte0]: 68
2804 00:55:55.470290 [Byte1]: 68
2805 00:55:55.470347
2806 00:55:55.470399 Set Vref, RX VrefLevel [Byte0]: 69
2807 00:55:55.470451 [Byte1]: 69
2808 00:55:55.470503
2809 00:55:55.470556 Final RX Vref Byte 0 = 58 to rank0
2810 00:55:55.470608 Final RX Vref Byte 1 = 50 to rank0
2811 00:55:55.470661 Final RX Vref Byte 0 = 58 to rank1
2812 00:55:55.470713 Final RX Vref Byte 1 = 50 to rank1==
2813 00:55:55.470765 Dram Type= 6, Freq= 0, CH_0, rank 0
2814 00:55:55.470817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2815 00:55:55.470875 ==
2816 00:55:55.470928 DQS Delay:
2817 00:55:55.470980 DQS0 = 0, DQS1 = 0
2818 00:55:55.471032 DQM Delay:
2819 00:55:55.471085 DQM0 = 119, DQM1 = 105
2820 00:55:55.471138 DQ Delay:
2821 00:55:55.471189 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =116
2822 00:55:55.471242 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =122
2823 00:55:55.471295 DQ8 =94, DQ9 =92, DQ10 =104, DQ11 =100
2824 00:55:55.471348 DQ12 =112, DQ13 =108, DQ14 =116, DQ15 =114
2825 00:55:55.471404
2826 00:55:55.471458
2827 00:55:55.471510 [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2828 00:55:55.471564 CH0 RK0: MR19=403, MR18=4FF
2829 00:55:55.471616 CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2830 00:55:55.471668
2831 00:55:55.471720 ----->DramcWriteLeveling(PI) begin...
2832 00:55:55.471773 ==
2833 00:55:55.471826 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 00:55:55.471878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 00:55:55.471933 ==
2836 00:55:55.472016 Write leveling (Byte 0): 33 => 33
2837 00:55:55.472098 Write leveling (Byte 1): 27 => 27
2838 00:55:55.472180 DramcWriteLeveling(PI) end<-----
2839 00:55:55.472261
2840 00:55:55.472342 ==
2841 00:55:55.472424 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 00:55:55.472504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 00:55:55.472560 ==
2844 00:55:55.472613 [Gating] SW mode calibration
2845 00:55:55.472666 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2846 00:55:55.472719 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2847 00:55:55.472773 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2848 00:55:55.472826 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 00:55:55.472878 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 00:55:55.472931 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 00:55:55.472984 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 00:55:55.473037 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2853 00:55:55.473123 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
2854 00:55:55.473207 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
2855 00:55:55.473320 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2856 00:55:55.473376 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 00:55:55.473430 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 00:55:55.473483 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 00:55:55.473535 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 00:55:55.473588 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 00:55:55.473644 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2862 00:55:55.473698 1 0 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
2863 00:55:55.473751 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2864 00:55:55.473803 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 00:55:55.473855 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 00:55:55.473908 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 00:55:55.473960 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 00:55:55.474012 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 00:55:55.474065 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2870 00:55:55.474117 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2871 00:55:55.474172 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2872 00:55:55.474225 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 00:55:55.474472 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 00:55:55.474532 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 00:55:55.474586 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 00:55:55.474640 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 00:55:55.474696 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 00:55:55.474779 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 00:55:55.474862 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 00:55:55.474962 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 00:55:55.475046 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 00:55:55.475144 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 00:55:55.475226 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 00:55:55.475281 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2885 00:55:55.475335 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2886 00:55:55.475387 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2887 00:55:55.475440 Total UI for P1: 0, mck2ui 16
2888 00:55:55.475494 best dqsien dly found for B0: ( 1, 3, 22)
2889 00:55:55.475547 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2890 00:55:55.475600 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 00:55:55.475652 Total UI for P1: 0, mck2ui 16
2892 00:55:55.475705 best dqsien dly found for B1: ( 1, 3, 30)
2893 00:55:55.475796 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2894 00:55:55.475876 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2895 00:55:55.475931
2896 00:55:55.475986 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2897 00:55:55.476039 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2898 00:55:55.476092 [Gating] SW calibration Done
2899 00:55:55.476145 ==
2900 00:55:55.476197 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 00:55:55.476253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 00:55:55.476307 ==
2903 00:55:55.476359 RX Vref Scan: 0
2904 00:55:55.476412
2905 00:55:55.476464 RX Vref 0 -> 0, step: 1
2906 00:55:55.476517
2907 00:55:55.476568 RX Delay -40 -> 252, step: 8
2908 00:55:55.476620 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2909 00:55:55.476673 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2910 00:55:55.476725 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2911 00:55:55.476780 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2912 00:55:55.476834 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2913 00:55:55.476886 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2914 00:55:55.476938 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2915 00:55:55.476990 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2916 00:55:55.477043 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2917 00:55:55.477096 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2918 00:55:55.477148 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2919 00:55:55.477201 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2920 00:55:55.477253 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2921 00:55:55.477349 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2922 00:55:55.477403 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2923 00:55:55.477492 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2924 00:55:55.477544 ==
2925 00:55:55.477597 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 00:55:55.477650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 00:55:55.477703 ==
2928 00:55:55.477755 DQS Delay:
2929 00:55:55.477807 DQS0 = 0, DQS1 = 0
2930 00:55:55.477859 DQM Delay:
2931 00:55:55.477914 DQM0 = 118, DQM1 = 106
2932 00:55:55.477966 DQ Delay:
2933 00:55:55.478018 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2934 00:55:55.478071 DQ4 =123, DQ5 =107, DQ6 =127, DQ7 =127
2935 00:55:55.478123 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2936 00:55:55.720448 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2937 00:55:55.720587
2938 00:55:55.720652
2939 00:55:55.720712 ==
2940 00:55:55.720770 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 00:55:55.720827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 00:55:55.720884 ==
2943 00:55:55.720938
2944 00:55:55.720992
2945 00:55:55.721047 TX Vref Scan disable
2946 00:55:55.721103 == TX Byte 0 ==
2947 00:55:55.721157 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2948 00:55:55.721211 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2949 00:55:55.721291 == TX Byte 1 ==
2950 00:55:55.721361 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2951 00:55:55.721415 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2952 00:55:55.721468 ==
2953 00:55:55.721521 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 00:55:55.721574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 00:55:55.721628 ==
2956 00:55:55.721684 TX Vref=22, minBit 9, minWin=25, winSum=416
2957 00:55:55.721738 TX Vref=24, minBit 13, minWin=25, winSum=423
2958 00:55:55.721792 TX Vref=26, minBit 13, minWin=25, winSum=426
2959 00:55:55.721845 TX Vref=28, minBit 12, minWin=26, winSum=429
2960 00:55:55.721899 TX Vref=30, minBit 8, minWin=26, winSum=430
2961 00:55:55.721951 TX Vref=32, minBit 4, minWin=26, winSum=427
2962 00:55:55.722004 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 30
2963 00:55:55.722057
2964 00:55:55.722110 Final TX Range 1 Vref 30
2965 00:55:55.722163
2966 00:55:55.722215 ==
2967 00:55:55.722271 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 00:55:55.722324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 00:55:55.722377 ==
2970 00:55:55.722430
2971 00:55:55.722482
2972 00:55:55.722534 TX Vref Scan disable
2973 00:55:55.722586 == TX Byte 0 ==
2974 00:55:55.722646 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2975 00:55:55.722700 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2976 00:55:55.722753 == TX Byte 1 ==
2977 00:55:55.722846 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2978 00:55:55.722904 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2979 00:55:55.722957
2980 00:55:55.723009 [DATLAT]
2981 00:55:55.723062 Freq=1200, CH0 RK1
2982 00:55:55.723114
2983 00:55:55.723166 DATLAT Default: 0xd
2984 00:55:55.723218 0, 0xFFFF, sum = 0
2985 00:55:55.723272 1, 0xFFFF, sum = 0
2986 00:55:55.723326 2, 0xFFFF, sum = 0
2987 00:55:55.723379 3, 0xFFFF, sum = 0
2988 00:55:55.723432 4, 0xFFFF, sum = 0
2989 00:55:55.723489 5, 0xFFFF, sum = 0
2990 00:55:55.723542 6, 0xFFFF, sum = 0
2991 00:55:55.723596 7, 0xFFFF, sum = 0
2992 00:55:55.723649 8, 0xFFFF, sum = 0
2993 00:55:55.723702 9, 0xFFFF, sum = 0
2994 00:55:55.723755 10, 0xFFFF, sum = 0
2995 00:55:55.723808 11, 0xFFFF, sum = 0
2996 00:55:55.723861 12, 0x0, sum = 1
2997 00:55:55.723915 13, 0x0, sum = 2
2998 00:55:55.723967 14, 0x0, sum = 3
2999 00:55:55.724024 15, 0x0, sum = 4
3000 00:55:55.724078 best_step = 13
3001 00:55:55.724130
3002 00:55:55.724182 ==
3003 00:55:55.724235 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 00:55:55.724287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 00:55:55.724341 ==
3006 00:55:55.724393 RX Vref Scan: 0
3007 00:55:55.724445
3008 00:55:55.724497 RX Vref 0 -> 0, step: 1
3009 00:55:55.724550
3010 00:55:55.724810 RX Delay -21 -> 252, step: 4
3011 00:55:55.724870 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3012 00:55:55.724925 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3013 00:55:55.724979 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3014 00:55:55.725032 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3015 00:55:55.725085 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3016 00:55:55.725176 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3017 00:55:55.725305 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3018 00:55:55.725404 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3019 00:55:55.725495 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3020 00:55:55.725556 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3021 00:55:55.725610 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3022 00:55:55.725663 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3023 00:55:55.725716 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3024 00:55:55.725769 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3025 00:55:55.725845 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3026 00:55:55.725928 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3027 00:55:55.726009 ==
3028 00:55:55.726091 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 00:55:55.726174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 00:55:55.726255 ==
3031 00:55:55.726337 DQS Delay:
3032 00:55:55.726417 DQS0 = 0, DQS1 = 0
3033 00:55:55.726472 DQM Delay:
3034 00:55:55.726525 DQM0 = 118, DQM1 = 107
3035 00:55:55.726577 DQ Delay:
3036 00:55:55.726630 DQ0 =116, DQ1 =120, DQ2 =114, DQ3 =116
3037 00:55:55.726683 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3038 00:55:55.726735 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3039 00:55:55.726788 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =116
3040 00:55:55.726840
3041 00:55:55.726905
3042 00:55:55.726958 [DQSOSCAuto] RK1, (LSB)MR18= 0x301, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 408 ps
3043 00:55:55.727017 CH0 RK1: MR19=404, MR18=301
3044 00:55:55.727070 CH0_RK1: MR19=0x404, MR18=0x301, DQSOSC=408, MR23=63, INC=39, DEC=26
3045 00:55:55.727123 [RxdqsGatingPostProcess] freq 1200
3046 00:55:55.727176 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3047 00:55:55.727229 best DQS0 dly(2T, 0.5T) = (0, 11)
3048 00:55:55.727281 best DQS1 dly(2T, 0.5T) = (0, 12)
3049 00:55:55.727334 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3050 00:55:55.727386 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3051 00:55:55.727438 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 00:55:55.727490 best DQS1 dly(2T, 0.5T) = (0, 11)
3053 00:55:55.727543 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 00:55:55.727600 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3055 00:55:55.727653 Pre-setting of DQS Precalculation
3056 00:55:55.727706 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3057 00:55:55.727785 ==
3058 00:55:55.727856 Dram Type= 6, Freq= 0, CH_1, rank 0
3059 00:55:55.727910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 00:55:55.727971 ==
3061 00:55:55.728025 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3062 00:55:55.728079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3063 00:55:55.728162 [CA 0] Center 37 (7~68) winsize 62
3064 00:55:55.728218 [CA 1] Center 37 (7~68) winsize 62
3065 00:55:55.728270 [CA 2] Center 35 (6~65) winsize 60
3066 00:55:55.728323 [CA 3] Center 34 (4~64) winsize 61
3067 00:55:55.728375 [CA 4] Center 35 (5~65) winsize 61
3068 00:55:55.728427 [CA 5] Center 33 (3~63) winsize 61
3069 00:55:55.728479
3070 00:55:55.728532 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3071 00:55:55.728585
3072 00:55:55.728637 [CATrainingPosCal] consider 1 rank data
3073 00:55:55.728691 u2DelayCellTimex100 = 270/100 ps
3074 00:55:55.728744 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3075 00:55:55.728800 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3076 00:55:55.728853 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3077 00:55:55.728907 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3078 00:55:55.728960 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3079 00:55:55.729012 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3080 00:55:55.729065
3081 00:55:55.729118 CA PerBit enable=1, Macro0, CA PI delay=33
3082 00:55:55.729170
3083 00:55:55.729222 [CBTSetCACLKResult] CA Dly = 33
3084 00:55:55.729301 CS Dly: 4 (0~35)
3085 00:55:55.729372 ==
3086 00:55:55.729426 Dram Type= 6, Freq= 0, CH_1, rank 1
3087 00:55:55.729479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 00:55:55.729532 ==
3089 00:55:55.729585 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3090 00:55:55.729638 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3091 00:55:55.729692 [CA 0] Center 37 (7~68) winsize 62
3092 00:55:55.729745 [CA 1] Center 38 (8~68) winsize 61
3093 00:55:55.729797 [CA 2] Center 35 (5~65) winsize 61
3094 00:55:55.729850 [CA 3] Center 33 (3~64) winsize 62
3095 00:55:55.729902 [CA 4] Center 34 (4~64) winsize 61
3096 00:55:55.729963 [CA 5] Center 33 (3~63) winsize 61
3097 00:55:55.730044
3098 00:55:55.730099 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3099 00:55:55.730153
3100 00:55:55.730206 [CATrainingPosCal] consider 2 rank data
3101 00:55:55.730259 u2DelayCellTimex100 = 270/100 ps
3102 00:55:55.730312 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3103 00:55:55.730365 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3104 00:55:55.730418 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3105 00:55:55.730471 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3106 00:55:55.730524 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3107 00:55:55.730581 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3108 00:55:55.730635
3109 00:55:55.730687 CA PerBit enable=1, Macro0, CA PI delay=33
3110 00:55:55.730741
3111 00:55:55.730794 [CBTSetCACLKResult] CA Dly = 33
3112 00:55:55.730846 CS Dly: 6 (0~39)
3113 00:55:55.730899
3114 00:55:55.730951 ----->DramcWriteLeveling(PI) begin...
3115 00:55:55.731004 ==
3116 00:55:55.731057 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 00:55:55.731110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 00:55:55.731166 ==
3119 00:55:55.731219 Write leveling (Byte 0): 27 => 27
3120 00:55:55.731272 Write leveling (Byte 1): 29 => 29
3121 00:55:55.731325 DramcWriteLeveling(PI) end<-----
3122 00:55:55.731377
3123 00:55:55.731430 ==
3124 00:55:55.731482 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 00:55:55.731535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 00:55:55.731589 ==
3127 00:55:55.731642 [Gating] SW mode calibration
3128 00:55:55.731695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3129 00:55:55.731949 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3130 00:55:55.732009 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3131 00:55:55.732064 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 00:55:55.732118 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 00:55:55.732171 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 00:55:55.732224 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 00:55:55.732277 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 00:55:55.732333 0 15 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
3137 00:55:55.732387 0 15 28 | B1->B0 | 2929 2525 | 0 0 | (1 0) (1 0)
3138 00:55:55.732440 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3139 00:55:55.732493 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 00:55:55.732546 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 00:55:55.732599 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 00:55:55.732652 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 00:55:55.732705 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 00:55:55.732757 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3145 00:55:55.732809 1 0 28 | B1->B0 | 3636 4444 | 0 0 | (0 0) (0 0)
3146 00:55:55.732862 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 00:55:55.732915 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 00:55:55.732972 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 00:55:55.733025 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 00:55:55.733078 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 00:55:55.733131 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 00:55:55.733183 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 00:55:55.733236 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3154 00:55:55.733317 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 00:55:55.733384 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 00:55:55.733437 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 00:55:55.733491 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 00:55:55.733546 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 00:55:55.733600 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 00:55:55.733654 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 00:55:55.733734 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 00:55:55.733833 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 00:55:55.733911 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 00:55:55.733966 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 00:55:55.734019 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 00:55:55.734073 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 00:55:55.734126 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 00:55:55.734184 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3169 00:55:55.734238 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3170 00:55:55.734292 Total UI for P1: 0, mck2ui 16
3171 00:55:55.734346 best dqsien dly found for B0: ( 1, 3, 24)
3172 00:55:55.734400 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 00:55:55.734454 Total UI for P1: 0, mck2ui 16
3174 00:55:55.734508 best dqsien dly found for B1: ( 1, 3, 28)
3175 00:55:55.734561 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3176 00:55:55.734615 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3177 00:55:55.734669
3178 00:55:55.734722 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3179 00:55:55.734778 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3180 00:55:55.734831 [Gating] SW calibration Done
3181 00:55:55.734884 ==
3182 00:55:55.734937 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 00:55:55.734991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 00:55:55.735044 ==
3185 00:55:55.735097 RX Vref Scan: 0
3186 00:55:55.735150
3187 00:55:55.735203 RX Vref 0 -> 0, step: 1
3188 00:55:55.735256
3189 00:55:55.735309 RX Delay -40 -> 252, step: 8
3190 00:55:55.735366 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3191 00:55:55.735419 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3192 00:55:55.735472 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3193 00:55:55.735525 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3194 00:55:55.735578 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3195 00:55:55.735631 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3196 00:55:55.735685 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3197 00:55:55.735738 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3198 00:55:55.735812 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3199 00:55:55.735941 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3200 00:55:55.736025 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3201 00:55:55.736085 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3202 00:55:55.736139 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3203 00:55:55.736192 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3204 00:55:55.736245 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3205 00:55:55.736298 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3206 00:55:55.736351 ==
3207 00:55:55.736404 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 00:55:55.736460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 00:55:55.736514 ==
3210 00:55:55.736567 DQS Delay:
3211 00:55:55.736620 DQS0 = 0, DQS1 = 0
3212 00:55:55.736673 DQM Delay:
3213 00:55:55.736725 DQM0 = 115, DQM1 = 112
3214 00:55:55.736778 DQ Delay:
3215 00:55:55.736831 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3216 00:55:55.736884 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3217 00:55:55.736937 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3218 00:55:55.736990 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3219 00:55:55.737048
3220 00:55:55.737101
3221 00:55:55.737153 ==
3222 00:55:55.737206 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 00:55:55.737266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 00:55:55.737355 ==
3225 00:55:55.737407
3226 00:55:55.737460
3227 00:55:55.737512 TX Vref Scan disable
3228 00:55:55.737570 == TX Byte 0 ==
3229 00:55:55.737623 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3230 00:55:55.737677 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3231 00:55:55.737731 == TX Byte 1 ==
3232 00:55:55.737783 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3233 00:55:55.737835 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3234 00:55:55.737888 ==
3235 00:55:55.738136 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 00:55:55.738197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 00:55:55.738252 ==
3238 00:55:55.738306 TX Vref=22, minBit 1, minWin=25, winSum=411
3239 00:55:55.738361 TX Vref=24, minBit 3, minWin=25, winSum=415
3240 00:55:55.738414 TX Vref=26, minBit 3, minWin=25, winSum=422
3241 00:55:55.738468 TX Vref=28, minBit 1, minWin=26, winSum=429
3242 00:55:55.738521 TX Vref=30, minBit 10, minWin=26, winSum=430
3243 00:55:55.738575 TX Vref=32, minBit 15, minWin=25, winSum=427
3244 00:55:55.738628 [TxChooseVref] Worse bit 10, Min win 26, Win sum 430, Final Vref 30
3245 00:55:55.738685
3246 00:55:55.738739 Final TX Range 1 Vref 30
3247 00:55:55.738792
3248 00:55:55.738845 ==
3249 00:55:55.738898 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 00:55:55.738952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 00:55:55.739005 ==
3252 00:55:55.739057
3253 00:55:55.739109
3254 00:55:55.739162 TX Vref Scan disable
3255 00:55:55.739242 == TX Byte 0 ==
3256 00:55:55.739326 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3257 00:55:55.739383 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3258 00:55:55.739499 == TX Byte 1 ==
3259 00:55:55.739553 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3260 00:55:55.739606 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3261 00:55:55.739659
3262 00:55:55.739711 [DATLAT]
3263 00:55:55.739764 Freq=1200, CH1 RK0
3264 00:55:55.739821
3265 00:55:55.739873 DATLAT Default: 0xd
3266 00:55:55.739926 0, 0xFFFF, sum = 0
3267 00:55:55.739980 1, 0xFFFF, sum = 0
3268 00:55:55.740034 2, 0xFFFF, sum = 0
3269 00:55:55.740087 3, 0xFFFF, sum = 0
3270 00:55:55.740141 4, 0xFFFF, sum = 0
3271 00:55:55.740195 5, 0xFFFF, sum = 0
3272 00:55:55.740248 6, 0xFFFF, sum = 0
3273 00:55:55.740302 7, 0xFFFF, sum = 0
3274 00:55:55.740360 8, 0xFFFF, sum = 0
3275 00:55:55.740414 9, 0xFFFF, sum = 0
3276 00:55:55.740468 10, 0xFFFF, sum = 0
3277 00:55:55.740522 11, 0xFFFF, sum = 0
3278 00:55:55.740576 12, 0x0, sum = 1
3279 00:55:55.740630 13, 0x0, sum = 2
3280 00:55:55.740683 14, 0x0, sum = 3
3281 00:55:55.740736 15, 0x0, sum = 4
3282 00:55:55.740789 best_step = 13
3283 00:55:55.740842
3284 00:55:55.740906 ==
3285 00:55:55.740989 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 00:55:55.741077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 00:55:55.741161 ==
3288 00:55:55.741243 RX Vref Scan: 1
3289 00:55:55.741343
3290 00:55:55.741397 Set Vref Range= 32 -> 127
3291 00:55:55.741453
3292 00:55:55.741507 RX Vref 32 -> 127, step: 1
3293 00:55:55.741559
3294 00:55:55.741612 RX Delay -13 -> 252, step: 4
3295 00:55:55.741664
3296 00:55:55.741716 Set Vref, RX VrefLevel [Byte0]: 32
3297 00:55:55.741769 [Byte1]: 32
3298 00:55:55.741822
3299 00:55:55.741874 Set Vref, RX VrefLevel [Byte0]: 33
3300 00:55:55.741926 [Byte1]: 33
3301 00:55:55.741983
3302 00:55:55.742064 Set Vref, RX VrefLevel [Byte0]: 34
3303 00:55:55.742118 [Byte1]: 34
3304 00:55:55.742171
3305 00:55:55.742224 Set Vref, RX VrefLevel [Byte0]: 35
3306 00:55:55.742277 [Byte1]: 35
3307 00:55:55.742330
3308 00:55:55.742382 Set Vref, RX VrefLevel [Byte0]: 36
3309 00:55:55.742435 [Byte1]: 36
3310 00:55:55.742488
3311 00:55:55.742543 Set Vref, RX VrefLevel [Byte0]: 37
3312 00:55:55.742597 [Byte1]: 37
3313 00:55:55.742650
3314 00:55:55.742707 Set Vref, RX VrefLevel [Byte0]: 38
3315 00:55:55.742766 [Byte1]: 38
3316 00:55:55.742819
3317 00:55:55.742872 Set Vref, RX VrefLevel [Byte0]: 39
3318 00:55:55.742925 [Byte1]: 39
3319 00:55:55.742977
3320 00:55:55.743029 Set Vref, RX VrefLevel [Byte0]: 40
3321 00:55:55.743082 [Byte1]: 40
3322 00:55:55.743137
3323 00:55:55.743189 Set Vref, RX VrefLevel [Byte0]: 41
3324 00:55:55.743242 [Byte1]: 41
3325 00:55:55.743295
3326 00:55:55.743347 Set Vref, RX VrefLevel [Byte0]: 42
3327 00:55:55.743399 [Byte1]: 42
3328 00:55:55.743451
3329 00:55:55.743504 Set Vref, RX VrefLevel [Byte0]: 43
3330 00:55:55.743556 [Byte1]: 43
3331 00:55:55.743608
3332 00:55:55.743663 Set Vref, RX VrefLevel [Byte0]: 44
3333 00:55:55.743716 [Byte1]: 44
3334 00:55:55.743768
3335 00:55:55.743819 Set Vref, RX VrefLevel [Byte0]: 45
3336 00:55:55.743872 [Byte1]: 45
3337 00:55:55.743925
3338 00:55:55.743977 Set Vref, RX VrefLevel [Byte0]: 46
3339 00:55:55.744030 [Byte1]: 46
3340 00:55:55.744082
3341 00:55:55.744134 Set Vref, RX VrefLevel [Byte0]: 47
3342 00:55:55.744186 [Byte1]: 47
3343 00:55:55.744243
3344 00:55:55.744295 Set Vref, RX VrefLevel [Byte0]: 48
3345 00:55:55.744348 [Byte1]: 48
3346 00:55:55.744400
3347 00:55:55.744452 Set Vref, RX VrefLevel [Byte0]: 49
3348 00:55:55.744504 [Byte1]: 49
3349 00:55:55.744557
3350 00:55:55.744613 Set Vref, RX VrefLevel [Byte0]: 50
3351 00:55:55.744669 [Byte1]: 50
3352 00:55:55.744723
3353 00:55:55.744777 Set Vref, RX VrefLevel [Byte0]: 51
3354 00:55:55.744831 [Byte1]: 51
3355 00:55:55.744883
3356 00:55:55.744935 Set Vref, RX VrefLevel [Byte0]: 52
3357 00:55:55.744988 [Byte1]: 52
3358 00:55:55.745040
3359 00:55:55.745092 Set Vref, RX VrefLevel [Byte0]: 53
3360 00:55:55.745144 [Byte1]: 53
3361 00:55:55.745196
3362 00:55:55.745247 Set Vref, RX VrefLevel [Byte0]: 54
3363 00:55:55.745327 [Byte1]: 54
3364 00:55:55.745398
3365 00:55:55.745450 Set Vref, RX VrefLevel [Byte0]: 55
3366 00:55:55.745503 [Byte1]: 55
3367 00:55:55.745555
3368 00:55:55.745607 Set Vref, RX VrefLevel [Byte0]: 56
3369 00:55:55.745660 [Byte1]: 56
3370 00:55:55.745712
3371 00:55:55.745764 Set Vref, RX VrefLevel [Byte0]: 57
3372 00:55:55.745891 [Byte1]: 57
3373 00:55:55.746013
3374 00:55:55.746112 Set Vref, RX VrefLevel [Byte0]: 58
3375 00:55:55.746204 [Byte1]: 58
3376 00:55:55.746287
3377 00:55:55.746374 Set Vref, RX VrefLevel [Byte0]: 59
3378 00:55:55.746457 [Byte1]: 59
3379 00:55:55.746541
3380 00:55:55.746624 Set Vref, RX VrefLevel [Byte0]: 60
3381 00:55:55.746704 [Byte1]: 60
3382 00:55:55.746759
3383 00:55:55.746812 Set Vref, RX VrefLevel [Byte0]: 61
3384 00:55:55.746868 [Byte1]: 61
3385 00:55:55.746921
3386 00:55:55.746974 Set Vref, RX VrefLevel [Byte0]: 62
3387 00:55:55.747027 [Byte1]: 62
3388 00:55:55.747082
3389 00:55:55.747135 Set Vref, RX VrefLevel [Byte0]: 63
3390 00:55:55.747187 [Byte1]: 63
3391 00:55:55.747241
3392 00:55:55.747301 Set Vref, RX VrefLevel [Byte0]: 64
3393 00:55:55.747353 [Byte1]: 64
3394 00:55:55.747405
3395 00:55:55.747461 Set Vref, RX VrefLevel [Byte0]: 65
3396 00:55:55.747514 [Byte1]: 65
3397 00:55:55.747566
3398 00:55:55.747621 Final RX Vref Byte 0 = 52 to rank0
3399 00:55:55.747675 Final RX Vref Byte 1 = 50 to rank0
3400 00:55:55.747728 Final RX Vref Byte 0 = 52 to rank1
3401 00:55:55.747987 Final RX Vref Byte 1 = 50 to rank1==
3402 00:55:55.748048 Dram Type= 6, Freq= 0, CH_1, rank 0
3403 00:55:55.748102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3404 00:55:55.748157 ==
3405 00:55:55.748211 DQS Delay:
3406 00:55:55.748264 DQS0 = 0, DQS1 = 0
3407 00:55:55.748320 DQM Delay:
3408 00:55:55.748374 DQM0 = 114, DQM1 = 112
3409 00:55:55.748426 DQ Delay:
3410 00:55:55.748479 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3411 00:55:55.748532 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3412 00:55:55.748584 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3413 00:55:55.748636 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3414 00:55:55.748689
3415 00:55:55.748742
3416 00:55:55.748794 [DQSOSCAuto] RK0, (LSB)MR18= 0xf905, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 412 ps
3417 00:55:55.748848 CH1 RK0: MR19=304, MR18=F905
3418 00:55:55.748903 CH1_RK0: MR19=0x304, MR18=0xF905, DQSOSC=408, MR23=63, INC=39, DEC=26
3419 00:55:55.748958
3420 00:55:55.749012 ----->DramcWriteLeveling(PI) begin...
3421 00:55:55.749066 ==
3422 00:55:55.749118 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 00:55:55.749171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 00:55:55.749225 ==
3425 00:55:55.749313 Write leveling (Byte 0): 24 => 24
3426 00:55:55.749381 Write leveling (Byte 1): 28 => 28
3427 00:55:55.749434 DramcWriteLeveling(PI) end<-----
3428 00:55:55.749490
3429 00:55:55.749543 ==
3430 00:55:55.749596 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 00:55:55.749648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 00:55:55.749702 ==
3433 00:55:55.749760 [Gating] SW mode calibration
3434 00:55:55.749814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3435 00:55:55.749872 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3436 00:55:55.749927 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3437 00:55:55.749980 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 00:55:55.750038 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 00:55:55.750091 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 00:55:55.750145 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 00:55:55.750198 0 15 20 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3442 00:55:55.750251 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
3443 00:55:55.750304 0 15 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
3444 00:55:55.750356 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 00:55:55.750409 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 00:55:55.750462 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 00:55:55.750514 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 00:55:55.750569 1 0 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3449 00:55:55.750623 1 0 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3450 00:55:55.750675 1 0 24 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
3451 00:55:55.750728 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3452 00:55:55.750780 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 00:55:55.750833 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 00:55:55.750886 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 00:55:55.750938 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 00:55:55.750992 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 00:55:55.751045 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3458 00:55:55.751097 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3459 00:55:55.751153 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3460 00:55:55.751206 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 00:55:55.751258 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 00:55:55.751311 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 00:55:55.751363 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 00:55:55.751416 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 00:55:55.751468 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 00:55:55.751519 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 00:55:55.751571 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 00:55:55.751623 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 00:55:55.751675 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 00:55:55.751731 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 00:55:55.751783 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 00:55:55.751835 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 00:55:55.751888 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 00:55:55.751940 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3475 00:55:55.751992 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3476 00:55:55.752044 Total UI for P1: 0, mck2ui 16
3477 00:55:55.752097 best dqsien dly found for B0: ( 1, 3, 24)
3478 00:55:55.752151 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 00:55:55.752203 Total UI for P1: 0, mck2ui 16
3480 00:55:55.752256 best dqsien dly found for B1: ( 1, 3, 28)
3481 00:55:55.752312 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3482 00:55:55.752365 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3483 00:55:55.752417
3484 00:55:55.752469 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3485 00:55:55.752522 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3486 00:55:55.752575 [Gating] SW calibration Done
3487 00:55:55.752627 ==
3488 00:55:55.752679 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 00:55:55.752732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 00:55:55.752784 ==
3491 00:55:55.752839 RX Vref Scan: 0
3492 00:55:55.752893
3493 00:55:55.752946 RX Vref 0 -> 0, step: 1
3494 00:55:55.752998
3495 00:55:55.753051 RX Delay -40 -> 252, step: 8
3496 00:55:55.753103 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3497 00:55:55.753155 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3498 00:55:55.753208 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3499 00:55:55.753268 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3500 00:55:55.753323 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3501 00:55:55.753375 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3502 00:55:55.753430 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3503 00:55:55.753484 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3504 00:55:55.753537 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3505 00:55:55.753820 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3506 00:55:55.753881 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3507 00:55:55.753935 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3508 00:55:55.753989 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3509 00:55:55.754046 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3510 00:55:55.754098 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3511 00:55:55.754151 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3512 00:55:55.754204 ==
3513 00:55:55.754257 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 00:55:55.754310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 00:55:55.754363 ==
3516 00:55:55.754415 DQS Delay:
3517 00:55:55.754467 DQS0 = 0, DQS1 = 0
3518 00:55:55.754520 DQM Delay:
3519 00:55:55.754604 DQM0 = 115, DQM1 = 111
3520 00:55:55.754658 DQ Delay:
3521 00:55:55.754709 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =111
3522 00:55:55.754762 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3523 00:55:55.754814 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =103
3524 00:55:55.754867 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3525 00:55:55.754919
3526 00:55:55.754971
3527 00:55:55.755022 ==
3528 00:55:55.755075 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 00:55:55.755127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 00:55:55.755182 ==
3531 00:55:55.755235
3532 00:55:55.755287
3533 00:55:55.755340 TX Vref Scan disable
3534 00:55:55.755392 == TX Byte 0 ==
3535 00:55:55.755444 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3536 00:55:55.755498 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3537 00:55:55.755550 == TX Byte 1 ==
3538 00:55:55.755602 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3539 00:55:55.755654 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3540 00:55:55.755706 ==
3541 00:55:55.755758 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 00:55:55.755816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 00:55:55.755869 ==
3544 00:55:55.755922 TX Vref=22, minBit 3, minWin=24, winSum=421
3545 00:55:55.755975 TX Vref=24, minBit 7, minWin=25, winSum=423
3546 00:55:55.756028 TX Vref=26, minBit 1, minWin=26, winSum=426
3547 00:55:55.756080 TX Vref=28, minBit 2, minWin=26, winSum=429
3548 00:55:55.756132 TX Vref=30, minBit 7, minWin=26, winSum=432
3549 00:55:55.756185 TX Vref=32, minBit 3, minWin=26, winSum=428
3550 00:55:55.756237 [TxChooseVref] Worse bit 7, Min win 26, Win sum 432, Final Vref 30
3551 00:55:55.756290
3552 00:55:55.756342 Final TX Range 1 Vref 30
3553 00:55:55.756394
3554 00:55:55.756450 ==
3555 00:55:55.756501 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 00:55:55.756554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 00:55:55.756607 ==
3558 00:55:55.756659
3559 00:55:55.756711
3560 00:55:55.756762 TX Vref Scan disable
3561 00:55:55.756814 == TX Byte 0 ==
3562 00:55:55.756866 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3563 00:55:55.756939 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3564 00:55:55.756996 == TX Byte 1 ==
3565 00:55:55.757060 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3566 00:55:55.757144 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3567 00:55:55.757225
3568 00:55:55.757325 [DATLAT]
3569 00:55:55.757393 Freq=1200, CH1 RK1
3570 00:55:55.757446
3571 00:55:55.757509 DATLAT Default: 0xd
3572 00:55:55.757572 0, 0xFFFF, sum = 0
3573 00:55:55.757627 1, 0xFFFF, sum = 0
3574 00:55:55.757682 2, 0xFFFF, sum = 0
3575 00:55:55.757736 3, 0xFFFF, sum = 0
3576 00:55:55.757789 4, 0xFFFF, sum = 0
3577 00:55:55.757843 5, 0xFFFF, sum = 0
3578 00:55:55.757944 6, 0xFFFF, sum = 0
3579 00:55:55.758013 7, 0xFFFF, sum = 0
3580 00:55:55.758066 8, 0xFFFF, sum = 0
3581 00:55:55.758122 9, 0xFFFF, sum = 0
3582 00:55:55.758176 10, 0xFFFF, sum = 0
3583 00:55:55.758229 11, 0xFFFF, sum = 0
3584 00:55:55.758282 12, 0x0, sum = 1
3585 00:55:55.758335 13, 0x0, sum = 2
3586 00:55:55.758388 14, 0x0, sum = 3
3587 00:55:55.758441 15, 0x0, sum = 4
3588 00:55:55.758494 best_step = 13
3589 00:55:55.758546
3590 00:55:55.758598 ==
3591 00:55:55.758650 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 00:55:55.758708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 00:55:55.758761 ==
3594 00:55:55.758814 RX Vref Scan: 0
3595 00:55:55.758866
3596 00:55:55.758919 RX Vref 0 -> 0, step: 1
3597 00:55:55.758971
3598 00:55:55.759023 RX Delay -13 -> 252, step: 4
3599 00:55:55.759076 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3600 00:55:55.759129 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3601 00:55:55.759181 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3602 00:55:55.759234 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3603 00:55:55.759289 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3604 00:55:55.759342 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3605 00:55:55.759394 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3606 00:55:55.759447 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3607 00:55:55.759499 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3608 00:55:55.759551 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3609 00:55:55.759603 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3610 00:55:55.759656 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3611 00:55:55.759708 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3612 00:55:55.759760 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3613 00:55:55.759813 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3614 00:55:55.759865 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3615 00:55:55.759922 ==
3616 00:55:55.759975 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 00:55:55.760028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 00:55:55.760116 ==
3619 00:55:55.760168 DQS Delay:
3620 00:55:55.760220 DQS0 = 0, DQS1 = 0
3621 00:55:55.760273 DQM Delay:
3622 00:55:55.760324 DQM0 = 115, DQM1 = 112
3623 00:55:55.760377 DQ Delay:
3624 00:55:55.760429 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3625 00:55:55.760485 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =112
3626 00:55:55.760539 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3627 00:55:55.760592 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3628 00:55:55.760644
3629 00:55:55.760696
3630 00:55:55.760749 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0d, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3631 00:55:55.760803 CH1 RK1: MR19=304, MR18=FA0D
3632 00:55:55.760855 CH1_RK1: MR19=0x304, MR18=0xFA0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3633 00:55:55.760907 [RxdqsGatingPostProcess] freq 1200
3634 00:55:55.760960 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3635 00:55:55.761016 best DQS0 dly(2T, 0.5T) = (0, 11)
3636 00:55:55.761068 best DQS1 dly(2T, 0.5T) = (0, 11)
3637 00:55:55.761120 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3638 00:55:55.761173 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3639 00:55:55.761226 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 00:55:55.761319 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 00:55:55.761373 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 00:55:55.761425 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 00:55:55.761477 Pre-setting of DQS Precalculation
3644 00:55:55.761776 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3645 00:55:55.761839 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3646 00:55:55.761896 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3647 00:55:55.761949
3648 00:55:55.762002
3649 00:55:55.762057 [Calibration Summary] 2400 Mbps
3650 00:55:55.762112 CH 0, Rank 0
3651 00:55:55.762164 SW Impedance : PASS
3652 00:55:55.762217 DUTY Scan : NO K
3653 00:55:55.762269 ZQ Calibration : PASS
3654 00:55:55.762323 Jitter Meter : NO K
3655 00:55:55.762376 CBT Training : PASS
3656 00:55:55.762428 Write leveling : PASS
3657 00:55:55.762480 RX DQS gating : PASS
3658 00:55:55.762533 RX DQ/DQS(RDDQC) : PASS
3659 00:55:55.762585 TX DQ/DQS : PASS
3660 00:55:55.762642 RX DATLAT : PASS
3661 00:55:55.762695 RX DQ/DQS(Engine): PASS
3662 00:55:55.762747 TX OE : NO K
3663 00:55:55.762799 All Pass.
3664 00:55:55.762852
3665 00:55:55.762904 CH 0, Rank 1
3666 00:55:55.762956 SW Impedance : PASS
3667 00:55:55.763008 DUTY Scan : NO K
3668 00:55:55.763061 ZQ Calibration : PASS
3669 00:55:55.763113 Jitter Meter : NO K
3670 00:55:55.763168 CBT Training : PASS
3671 00:55:55.763221 Write leveling : PASS
3672 00:55:55.763273 RX DQS gating : PASS
3673 00:55:55.763325 RX DQ/DQS(RDDQC) : PASS
3674 00:55:55.763377 TX DQ/DQS : PASS
3675 00:55:55.763430 RX DATLAT : PASS
3676 00:55:55.763481 RX DQ/DQS(Engine): PASS
3677 00:55:55.763533 TX OE : NO K
3678 00:55:55.763586 All Pass.
3679 00:55:55.763638
3680 00:55:55.763690 CH 1, Rank 0
3681 00:55:55.763748 SW Impedance : PASS
3682 00:55:55.763820 DUTY Scan : NO K
3683 00:55:55.763875 ZQ Calibration : PASS
3684 00:55:55.763927 Jitter Meter : NO K
3685 00:55:55.763980 CBT Training : PASS
3686 00:55:55.764032 Write leveling : PASS
3687 00:55:55.764084 RX DQS gating : PASS
3688 00:55:55.764136 RX DQ/DQS(RDDQC) : PASS
3689 00:55:55.764188 TX DQ/DQS : PASS
3690 00:55:55.764241 RX DATLAT : PASS
3691 00:55:55.764296 RX DQ/DQS(Engine): PASS
3692 00:55:55.764347 TX OE : NO K
3693 00:55:55.764400 All Pass.
3694 00:55:55.764452
3695 00:55:55.764504 CH 1, Rank 1
3696 00:55:55.764556 SW Impedance : PASS
3697 00:55:55.764608 DUTY Scan : NO K
3698 00:55:55.764660 ZQ Calibration : PASS
3699 00:55:55.764712 Jitter Meter : NO K
3700 00:55:55.764764 CBT Training : PASS
3701 00:55:55.764819 Write leveling : PASS
3702 00:55:55.764872 RX DQS gating : PASS
3703 00:55:55.764924 RX DQ/DQS(RDDQC) : PASS
3704 00:55:55.764976 TX DQ/DQS : PASS
3705 00:55:55.765028 RX DATLAT : PASS
3706 00:55:55.765081 RX DQ/DQS(Engine): PASS
3707 00:55:55.765161 TX OE : NO K
3708 00:55:55.765242 All Pass.
3709 00:55:55.765368
3710 00:55:55.765440 DramC Write-DBI off
3711 00:55:55.765493 PER_BANK_REFRESH: Hybrid Mode
3712 00:55:55.765546 TX_TRACKING: ON
3713 00:55:55.765599 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3714 00:55:55.765661 [FAST_K] Save calibration result to emmc
3715 00:55:55.765718 dramc_set_vcore_voltage set vcore to 650000
3716 00:55:55.765790 Read voltage for 600, 5
3717 00:55:55.765877 Vio18 = 0
3718 00:55:55.765938 Vcore = 650000
3719 00:55:55.766020 Vdram = 0
3720 00:55:55.766101 Vddq = 0
3721 00:55:55.766182 Vmddr = 0
3722 00:55:55.766264 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3723 00:55:55.766347 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3724 00:55:55.766429 MEM_TYPE=3, freq_sel=19
3725 00:55:55.766511 sv_algorithm_assistance_LP4_1600
3726 00:55:55.766595 ============ PULL DRAM RESETB DOWN ============
3727 00:55:55.766679 ========== PULL DRAM RESETB DOWN end =========
3728 00:55:55.766762 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3729 00:55:55.766844 ===================================
3730 00:55:55.766926 LPDDR4 DRAM CONFIGURATION
3731 00:55:55.767008 ===================================
3732 00:55:55.767090 EX_ROW_EN[0] = 0x0
3733 00:55:55.767172 EX_ROW_EN[1] = 0x0
3734 00:55:55.767254 LP4Y_EN = 0x0
3735 00:55:55.767335 WORK_FSP = 0x0
3736 00:55:55.767416 WL = 0x2
3737 00:55:55.767497 RL = 0x2
3738 00:55:55.767578 BL = 0x2
3739 00:55:55.767657 RPST = 0x0
3740 00:55:55.767716 RD_PRE = 0x0
3741 00:55:55.767773 WR_PRE = 0x1
3742 00:55:55.767826 WR_PST = 0x0
3743 00:55:55.767879 DBI_WR = 0x0
3744 00:55:55.767931 DBI_RD = 0x0
3745 00:55:55.767983 OTF = 0x1
3746 00:55:55.768035 ===================================
3747 00:55:55.768088 ===================================
3748 00:55:55.768140 ANA top config
3749 00:55:55.768193 ===================================
3750 00:55:55.768245 DLL_ASYNC_EN = 0
3751 00:55:55.768300 ALL_SLAVE_EN = 1
3752 00:55:55.768352 NEW_RANK_MODE = 1
3753 00:55:55.768405 DLL_IDLE_MODE = 1
3754 00:55:55.768457 LP45_APHY_COMB_EN = 1
3755 00:55:55.768509 TX_ODT_DIS = 1
3756 00:55:55.768561 NEW_8X_MODE = 1
3757 00:55:55.768615 ===================================
3758 00:55:55.768667 ===================================
3759 00:55:55.768720 data_rate = 1200
3760 00:55:55.768773 CKR = 1
3761 00:55:55.768825 DQ_P2S_RATIO = 8
3762 00:55:55.768879 ===================================
3763 00:55:55.768933 CA_P2S_RATIO = 8
3764 00:55:55.768987 DQ_CA_OPEN = 0
3765 00:55:55.769040 DQ_SEMI_OPEN = 0
3766 00:55:55.769092 CA_SEMI_OPEN = 0
3767 00:55:55.769145 CA_FULL_RATE = 0
3768 00:55:55.769196 DQ_CKDIV4_EN = 1
3769 00:55:55.769248 CA_CKDIV4_EN = 1
3770 00:55:55.769345 CA_PREDIV_EN = 0
3771 00:55:55.769397 PH8_DLY = 0
3772 00:55:55.769450 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3773 00:55:55.769506 DQ_AAMCK_DIV = 4
3774 00:55:55.769557 CA_AAMCK_DIV = 4
3775 00:55:55.769609 CA_ADMCK_DIV = 4
3776 00:55:55.769662 DQ_TRACK_CA_EN = 0
3777 00:55:55.769714 CA_PICK = 600
3778 00:55:55.769766 CA_MCKIO = 600
3779 00:55:55.769820 MCKIO_SEMI = 0
3780 00:55:55.769871 PLL_FREQ = 2288
3781 00:55:55.769923 DQ_UI_PI_RATIO = 32
3782 00:55:55.769975 CA_UI_PI_RATIO = 0
3783 00:55:55.770030 ===================================
3784 00:55:55.770085 ===================================
3785 00:55:55.770138 memory_type:LPDDR4
3786 00:55:55.770190 GP_NUM : 10
3787 00:55:55.770242 SRAM_EN : 1
3788 00:55:55.770294 MD32_EN : 0
3789 00:55:55.770346 ===================================
3790 00:55:55.770399 [ANA_INIT] >>>>>>>>>>>>>>
3791 00:55:55.770648 <<<<<< [CONFIGURE PHASE]: ANA_TX
3792 00:55:55.770708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3793 00:55:55.770763 ===================================
3794 00:55:55.770823 data_rate = 1200,PCW = 0X5800
3795 00:55:55.770882 ===================================
3796 00:55:55.770941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3797 00:55:55.771063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 00:55:55.771182 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 00:55:55.771267 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3800 00:55:55.771351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3801 00:55:55.771433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3802 00:55:55.771515 [ANA_INIT] flow start
3803 00:55:55.771597 [ANA_INIT] PLL >>>>>>>>
3804 00:55:55.771678 [ANA_INIT] PLL <<<<<<<<
3805 00:55:55.771759 [ANA_INIT] MIDPI >>>>>>>>
3806 00:55:55.771843 [ANA_INIT] MIDPI <<<<<<<<
3807 00:55:55.771924 [ANA_INIT] DLL >>>>>>>>
3808 00:55:55.772005 [ANA_INIT] flow end
3809 00:55:55.772087 ============ LP4 DIFF to SE enter ============
3810 00:55:55.772170 ============ LP4 DIFF to SE exit ============
3811 00:55:55.772252 [ANA_INIT] <<<<<<<<<<<<<
3812 00:55:55.772334 [Flow] Enable top DCM control >>>>>
3813 00:55:55.772416 [Flow] Enable top DCM control <<<<<
3814 00:55:55.772495 Enable DLL master slave shuffle
3815 00:55:55.772550 ==============================================================
3816 00:55:55.772604 Gating Mode config
3817 00:55:55.772657 ==============================================================
3818 00:55:55.772710 Config description:
3819 00:55:55.772763 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3820 00:55:55.772816 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3821 00:55:55.772869 SELPH_MODE 0: By rank 1: By Phase
3822 00:55:55.772922 ==============================================================
3823 00:55:55.772975 GAT_TRACK_EN = 1
3824 00:55:55.773031 RX_GATING_MODE = 2
3825 00:55:55.773084 RX_GATING_TRACK_MODE = 2
3826 00:55:55.773136 SELPH_MODE = 1
3827 00:55:55.773188 PICG_EARLY_EN = 1
3828 00:55:55.773241 VALID_LAT_VALUE = 1
3829 00:55:55.773328 ==============================================================
3830 00:55:55.773427 Enter into Gating configuration >>>>
3831 00:55:55.774264 Exit from Gating configuration <<<<
3832 00:55:55.777841 Enter into DVFS_PRE_config >>>>>
3833 00:55:55.788031 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3834 00:55:55.791076 Exit from DVFS_PRE_config <<<<<
3835 00:55:55.793931 Enter into PICG configuration >>>>
3836 00:55:55.797407 Exit from PICG configuration <<<<
3837 00:55:55.800411 [RX_INPUT] configuration >>>>>
3838 00:55:55.804508 [RX_INPUT] configuration <<<<<
3839 00:55:55.807469 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3840 00:55:55.813794 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3841 00:55:55.820520 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 00:55:55.827225 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 00:55:55.834056 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 00:55:55.840655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 00:55:55.843536 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3846 00:55:55.847230 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3847 00:55:55.850168 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3848 00:55:55.856793 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3849 00:55:55.859803 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3850 00:55:55.863621 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3851 00:55:55.866780 ===================================
3852 00:55:55.870470 LPDDR4 DRAM CONFIGURATION
3853 00:55:55.873381 ===================================
3854 00:55:55.873485 EX_ROW_EN[0] = 0x0
3855 00:55:55.876610 EX_ROW_EN[1] = 0x0
3856 00:55:55.879626 LP4Y_EN = 0x0
3857 00:55:55.879726 WORK_FSP = 0x0
3858 00:55:55.883137 WL = 0x2
3859 00:55:55.883244 RL = 0x2
3860 00:55:55.886456 BL = 0x2
3861 00:55:55.886558 RPST = 0x0
3862 00:55:55.889729 RD_PRE = 0x0
3863 00:55:55.889801 WR_PRE = 0x1
3864 00:55:55.893018 WR_PST = 0x0
3865 00:55:55.893086 DBI_WR = 0x0
3866 00:55:55.896286 DBI_RD = 0x0
3867 00:55:55.896370 OTF = 0x1
3868 00:55:55.899993 ===================================
3869 00:55:55.904299 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3870 00:55:55.909563 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3871 00:55:55.913219 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 00:55:55.916120 ===================================
3873 00:55:55.920023 LPDDR4 DRAM CONFIGURATION
3874 00:55:55.922906 ===================================
3875 00:55:55.922991 EX_ROW_EN[0] = 0x10
3876 00:55:55.926418 EX_ROW_EN[1] = 0x0
3877 00:55:55.929194 LP4Y_EN = 0x0
3878 00:55:55.929333 WORK_FSP = 0x0
3879 00:55:55.932890 WL = 0x2
3880 00:55:55.932973 RL = 0x2
3881 00:55:55.935988 BL = 0x2
3882 00:55:55.936075 RPST = 0x0
3883 00:55:55.938923 RD_PRE = 0x0
3884 00:55:55.939006 WR_PRE = 0x1
3885 00:55:55.942228 WR_PST = 0x0
3886 00:55:55.942324 DBI_WR = 0x0
3887 00:55:55.945543 DBI_RD = 0x0
3888 00:55:55.945653 OTF = 0x1
3889 00:55:55.949145 ===================================
3890 00:55:55.955525 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3891 00:55:55.961073 nWR fixed to 30
3892 00:55:55.963629 [ModeRegInit_LP4] CH0 RK0
3893 00:55:55.963714 [ModeRegInit_LP4] CH0 RK1
3894 00:55:55.966646 [ModeRegInit_LP4] CH1 RK0
3895 00:55:55.969867 [ModeRegInit_LP4] CH1 RK1
3896 00:55:55.969956 match AC timing 17
3897 00:55:55.977035 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3898 00:55:55.980365 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3899 00:55:55.983095 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3900 00:55:55.989999 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3901 00:55:55.993181 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3902 00:55:55.993292 ==
3903 00:55:55.996899 Dram Type= 6, Freq= 0, CH_0, rank 0
3904 00:55:55.999930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3905 00:55:56.000015 ==
3906 00:55:56.006209 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3907 00:55:56.012664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3908 00:55:56.016117 [CA 0] Center 36 (6~67) winsize 62
3909 00:55:56.019985 [CA 1] Center 36 (6~67) winsize 62
3910 00:55:56.023611 [CA 2] Center 34 (4~65) winsize 62
3911 00:55:56.026855 [CA 3] Center 34 (3~65) winsize 63
3912 00:55:56.029301 [CA 4] Center 33 (3~64) winsize 62
3913 00:55:56.032428 [CA 5] Center 33 (3~64) winsize 62
3914 00:55:56.032512
3915 00:55:56.035725 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3916 00:55:56.035809
3917 00:55:56.039038 [CATrainingPosCal] consider 1 rank data
3918 00:55:56.042327 u2DelayCellTimex100 = 270/100 ps
3919 00:55:56.045841 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3920 00:55:56.049483 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3921 00:55:56.052359 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3922 00:55:56.059110 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3923 00:55:56.062198 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3924 00:55:56.065457 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3925 00:55:56.065543
3926 00:55:56.068978 CA PerBit enable=1, Macro0, CA PI delay=33
3927 00:55:56.069057
3928 00:55:56.071920 [CBTSetCACLKResult] CA Dly = 33
3929 00:55:56.071996 CS Dly: 4 (0~35)
3930 00:55:56.072060 ==
3931 00:55:56.075392 Dram Type= 6, Freq= 0, CH_0, rank 1
3932 00:55:56.082243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 00:55:56.082337 ==
3934 00:55:56.085096 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 00:55:56.091713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3936 00:55:56.095787 [CA 0] Center 36 (6~67) winsize 62
3937 00:55:56.099012 [CA 1] Center 36 (6~67) winsize 62
3938 00:55:56.102175 [CA 2] Center 34 (4~65) winsize 62
3939 00:55:56.105154 [CA 3] Center 34 (4~65) winsize 62
3940 00:55:56.108577 [CA 4] Center 34 (3~65) winsize 63
3941 00:55:56.111879 [CA 5] Center 33 (3~64) winsize 62
3942 00:55:56.111964
3943 00:55:56.115552 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3944 00:55:56.115635
3945 00:55:56.118909 [CATrainingPosCal] consider 2 rank data
3946 00:55:56.121734 u2DelayCellTimex100 = 270/100 ps
3947 00:55:56.125576 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3948 00:55:56.132055 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3949 00:55:56.135514 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3950 00:55:56.138697 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 00:55:56.141878 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3952 00:55:56.145708 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 00:55:56.145795
3954 00:55:56.149083 CA PerBit enable=1, Macro0, CA PI delay=33
3955 00:55:56.149167
3956 00:55:56.151616 [CBTSetCACLKResult] CA Dly = 33
3957 00:55:56.155184 CS Dly: 5 (0~37)
3958 00:55:56.155269
3959 00:55:56.158327 ----->DramcWriteLeveling(PI) begin...
3960 00:55:56.158415 ==
3961 00:55:56.161613 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 00:55:56.164825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 00:55:56.164908 ==
3964 00:55:56.168293 Write leveling (Byte 0): 31 => 31
3965 00:55:56.171269 Write leveling (Byte 1): 30 => 30
3966 00:55:56.174931 DramcWriteLeveling(PI) end<-----
3967 00:55:56.175015
3968 00:55:56.175081 ==
3969 00:55:56.177819 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 00:55:56.181254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 00:55:56.181378 ==
3972 00:55:56.184648 [Gating] SW mode calibration
3973 00:55:56.190833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3974 00:55:56.197490 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3975 00:55:56.200811 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 00:55:56.204144 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 00:55:56.210650 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 00:55:56.214564 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
3979 00:55:56.217538 0 9 16 | B1->B0 | 2f2f 2a2a | 1 0 | (1 1) (0 0)
3980 00:55:56.224298 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 00:55:56.227231 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 00:55:56.230413 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 00:55:56.237207 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 00:55:56.240397 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 00:55:56.243778 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 00:55:56.250550 0 10 12 | B1->B0 | 2424 3030 | 1 0 | (0 0) (0 0)
3987 00:55:56.253810 0 10 16 | B1->B0 | 3939 4343 | 0 0 | (1 1) (0 0)
3988 00:55:56.257173 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 00:55:56.263758 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 00:55:56.266578 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 00:55:56.269862 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 00:55:56.276897 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 00:55:56.280359 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 00:55:56.286280 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 00:55:56.289704 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 00:55:56.292970 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 00:55:56.299608 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 00:55:56.302803 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 00:55:56.306059 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 00:55:56.312588 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:55:56.315937 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 00:55:56.319206 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:55:56.326276 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:55:56.329706 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 00:55:56.332461 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 00:55:56.339453 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 00:55:56.342504 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 00:55:56.345448 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:55:56.352248 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:55:56.355507 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4011 00:55:56.358944 Total UI for P1: 0, mck2ui 16
4012 00:55:56.361914 best dqsien dly found for B0: ( 0, 13, 10)
4013 00:55:56.365790 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 00:55:56.368612 Total UI for P1: 0, mck2ui 16
4015 00:55:56.372094 best dqsien dly found for B1: ( 0, 13, 14)
4016 00:55:56.375582 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4017 00:55:56.379278 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4018 00:55:56.379367
4019 00:55:56.386084 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4020 00:55:56.388705 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4021 00:55:56.388791 [Gating] SW calibration Done
4022 00:55:56.391699 ==
4023 00:55:56.394878 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 00:55:56.398411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 00:55:56.398495 ==
4026 00:55:56.398561 RX Vref Scan: 0
4027 00:55:56.398622
4028 00:55:56.401818 RX Vref 0 -> 0, step: 1
4029 00:55:56.401888
4030 00:55:56.404999 RX Delay -230 -> 252, step: 16
4031 00:55:56.408471 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4032 00:55:56.411616 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4033 00:55:56.417883 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4034 00:55:56.421396 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4035 00:55:56.424653 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4036 00:55:56.428310 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4037 00:55:56.434592 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4038 00:55:56.438229 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4039 00:55:56.441185 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4040 00:55:56.444352 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4041 00:55:56.451064 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4042 00:55:56.454440 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4043 00:55:56.457713 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4044 00:55:56.461476 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4045 00:55:56.467463 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4046 00:55:56.471219 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4047 00:55:56.471304 ==
4048 00:55:56.474311 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 00:55:56.477208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 00:55:56.477368 ==
4051 00:55:56.480771 DQS Delay:
4052 00:55:56.480855 DQS0 = 0, DQS1 = 0
4053 00:55:56.480920 DQM Delay:
4054 00:55:56.484345 DQM0 = 44, DQM1 = 35
4055 00:55:56.484428 DQ Delay:
4056 00:55:56.487825 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4057 00:55:56.490698 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =57
4058 00:55:56.494263 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4059 00:55:56.497612 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4060 00:55:56.497695
4061 00:55:56.497767
4062 00:55:56.497827 ==
4063 00:55:56.500785 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 00:55:56.507283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 00:55:56.507371 ==
4066 00:55:56.507437
4067 00:55:56.507497
4068 00:55:56.507556 TX Vref Scan disable
4069 00:55:56.510635 == TX Byte 0 ==
4070 00:55:56.514514 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4071 00:55:56.520906 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4072 00:55:56.520995 == TX Byte 1 ==
4073 00:55:56.524108 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4074 00:55:56.530463 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4075 00:55:56.530552 ==
4076 00:55:56.533725 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 00:55:56.537550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 00:55:56.537632 ==
4079 00:55:56.537696
4080 00:55:56.537754
4081 00:55:56.540817 TX Vref Scan disable
4082 00:55:56.543681 == TX Byte 0 ==
4083 00:55:56.547789 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4084 00:55:56.550831 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4085 00:55:56.553597 == TX Byte 1 ==
4086 00:55:56.557206 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4087 00:55:56.560152 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4088 00:55:56.560228
4089 00:55:56.560290 [DATLAT]
4090 00:55:56.563247 Freq=600, CH0 RK0
4091 00:55:56.563352
4092 00:55:56.566913 DATLAT Default: 0x9
4093 00:55:56.566989 0, 0xFFFF, sum = 0
4094 00:55:56.570329 1, 0xFFFF, sum = 0
4095 00:55:56.570403 2, 0xFFFF, sum = 0
4096 00:55:56.573141 3, 0xFFFF, sum = 0
4097 00:55:56.573218 4, 0xFFFF, sum = 0
4098 00:55:56.576820 5, 0xFFFF, sum = 0
4099 00:55:56.576894 6, 0xFFFF, sum = 0
4100 00:55:56.580318 7, 0xFFFF, sum = 0
4101 00:55:56.580394 8, 0x0, sum = 1
4102 00:55:56.583233 9, 0x0, sum = 2
4103 00:55:56.583309 10, 0x0, sum = 3
4104 00:55:56.586303 11, 0x0, sum = 4
4105 00:55:56.586375 best_step = 9
4106 00:55:56.586433
4107 00:55:56.586490 ==
4108 00:55:56.589547 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 00:55:56.593013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 00:55:56.593087 ==
4111 00:55:56.596221 RX Vref Scan: 1
4112 00:55:56.596292
4113 00:55:56.599952 RX Vref 0 -> 0, step: 1
4114 00:55:56.600021
4115 00:55:56.600081 RX Delay -179 -> 252, step: 8
4116 00:55:56.603296
4117 00:55:56.603369 Set Vref, RX VrefLevel [Byte0]: 58
4118 00:55:56.606327 [Byte1]: 50
4119 00:55:56.611158
4120 00:55:56.611261 Final RX Vref Byte 0 = 58 to rank0
4121 00:55:56.614290 Final RX Vref Byte 1 = 50 to rank0
4122 00:55:56.617584 Final RX Vref Byte 0 = 58 to rank1
4123 00:55:56.621196 Final RX Vref Byte 1 = 50 to rank1==
4124 00:55:56.624800 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 00:55:56.631002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 00:55:56.631087 ==
4127 00:55:56.631160 DQS Delay:
4128 00:55:56.634593 DQS0 = 0, DQS1 = 0
4129 00:55:56.634673 DQM Delay:
4130 00:55:56.634735 DQM0 = 44, DQM1 = 37
4131 00:55:56.637576 DQ Delay:
4132 00:55:56.640743 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =44
4133 00:55:56.644453 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4134 00:55:56.647327 DQ8 =28, DQ9 =28, DQ10 =36, DQ11 =32
4135 00:55:56.650394 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4136 00:55:56.650471
4137 00:55:56.650532
4138 00:55:56.657582 [DQSOSCAuto] RK0, (LSB)MR18= 0x554c, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 393 ps
4139 00:55:56.660372 CH0 RK0: MR19=808, MR18=554C
4140 00:55:56.667052 CH0_RK0: MR19=0x808, MR18=0x554C, DQSOSC=393, MR23=63, INC=169, DEC=113
4141 00:55:56.667137
4142 00:55:56.670121 ----->DramcWriteLeveling(PI) begin...
4143 00:55:56.670202 ==
4144 00:55:56.673696 Dram Type= 6, Freq= 0, CH_0, rank 1
4145 00:55:56.676952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 00:55:56.677028 ==
4147 00:55:56.680048 Write leveling (Byte 0): 33 => 33
4148 00:55:56.684067 Write leveling (Byte 1): 32 => 32
4149 00:55:56.686629 DramcWriteLeveling(PI) end<-----
4150 00:55:56.686715
4151 00:55:56.686779 ==
4152 00:55:56.689994 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 00:55:56.696916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 00:55:56.697008 ==
4155 00:55:56.697075 [Gating] SW mode calibration
4156 00:55:56.707040 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4157 00:55:56.710341 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4158 00:55:56.713076 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 00:55:56.720319 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 00:55:56.723626 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 00:55:56.726510 0 9 12 | B1->B0 | 3434 3030 | 0 1 | (0 1) (0 1)
4162 00:55:56.733058 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4163 00:55:56.736267 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 00:55:56.739855 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 00:55:56.746212 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 00:55:56.749882 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 00:55:56.752985 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 00:55:56.759521 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 00:55:56.763228 0 10 12 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
4170 00:55:56.766084 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4171 00:55:56.772575 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 00:55:56.777222 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 00:55:56.779313 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 00:55:56.785642 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 00:55:56.789087 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 00:55:56.792833 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 00:55:56.799275 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4178 00:55:56.802763 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4179 00:55:56.805582 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 00:55:56.812415 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 00:55:56.815999 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 00:55:56.818920 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 00:55:56.825534 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 00:55:56.828683 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 00:55:56.832172 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 00:55:56.838835 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 00:55:56.841686 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 00:55:56.844826 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 00:55:56.851800 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 00:55:56.855053 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 00:55:56.858216 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 00:55:56.864509 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 00:55:56.868599 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4194 00:55:56.871654 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 00:55:56.875418 Total UI for P1: 0, mck2ui 16
4196 00:55:56.877883 best dqsien dly found for B0: ( 0, 13, 12)
4197 00:55:56.881174 Total UI for P1: 0, mck2ui 16
4198 00:55:56.884494 best dqsien dly found for B1: ( 0, 13, 14)
4199 00:55:56.891099 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4200 00:55:56.894451 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4201 00:55:56.894536
4202 00:55:56.897854 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4203 00:55:56.901078 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4204 00:55:56.904701 [Gating] SW calibration Done
4205 00:55:56.904785 ==
4206 00:55:56.907422 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 00:55:56.910718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 00:55:56.910803 ==
4209 00:55:56.914054 RX Vref Scan: 0
4210 00:55:56.914138
4211 00:55:56.914209 RX Vref 0 -> 0, step: 1
4212 00:55:56.914270
4213 00:55:56.917698 RX Delay -230 -> 252, step: 16
4214 00:55:56.921074 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4215 00:55:56.927312 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4216 00:55:56.930586 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4217 00:55:56.934426 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4218 00:55:56.937393 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4219 00:55:56.943788 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4220 00:55:56.947431 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4221 00:55:56.950844 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4222 00:55:56.954234 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4223 00:55:56.960362 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4224 00:55:56.963554 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4225 00:55:56.966694 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4226 00:55:56.970230 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4227 00:55:56.976654 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4228 00:55:56.980344 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4229 00:55:56.983314 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4230 00:55:56.983394 ==
4231 00:55:56.987156 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 00:55:56.990066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 00:55:56.990159 ==
4234 00:55:56.993506 DQS Delay:
4235 00:55:56.993599 DQS0 = 0, DQS1 = 0
4236 00:55:56.996447 DQM Delay:
4237 00:55:56.996529 DQM0 = 45, DQM1 = 36
4238 00:55:57.000373 DQ Delay:
4239 00:55:57.000450 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4240 00:55:57.003170 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4241 00:55:57.006346 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4242 00:55:57.009820 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4243 00:55:57.009924
4244 00:55:57.013236
4245 00:55:57.013349 ==
4246 00:55:57.016303 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 00:55:57.019568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 00:55:57.019642 ==
4249 00:55:57.019703
4250 00:55:57.019768
4251 00:55:57.023354 TX Vref Scan disable
4252 00:55:57.023486 == TX Byte 0 ==
4253 00:55:57.029715 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4254 00:55:57.033311 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4255 00:55:57.033393 == TX Byte 1 ==
4256 00:55:57.039960 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4257 00:55:57.042974 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4258 00:55:57.043069 ==
4259 00:55:57.046126 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 00:55:57.049612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 00:55:57.049694 ==
4262 00:55:57.049759
4263 00:55:57.049817
4264 00:55:57.052849 TX Vref Scan disable
4265 00:55:57.056963 == TX Byte 0 ==
4266 00:55:57.059878 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4267 00:55:57.065820 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4268 00:55:57.065899 == TX Byte 1 ==
4269 00:55:57.069953 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4270 00:55:57.075728 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4271 00:55:57.075809
4272 00:55:57.075875 [DATLAT]
4273 00:55:57.075935 Freq=600, CH0 RK1
4274 00:55:57.075994
4275 00:55:57.078819 DATLAT Default: 0x9
4276 00:55:57.082156 0, 0xFFFF, sum = 0
4277 00:55:57.082263 1, 0xFFFF, sum = 0
4278 00:55:57.085646 2, 0xFFFF, sum = 0
4279 00:55:57.085722 3, 0xFFFF, sum = 0
4280 00:55:57.089198 4, 0xFFFF, sum = 0
4281 00:55:57.089333 5, 0xFFFF, sum = 0
4282 00:55:57.092744 6, 0xFFFF, sum = 0
4283 00:55:57.092817 7, 0xFFFF, sum = 0
4284 00:55:57.095361 8, 0x0, sum = 1
4285 00:55:57.095460 9, 0x0, sum = 2
4286 00:55:57.098414 10, 0x0, sum = 3
4287 00:55:57.098488 11, 0x0, sum = 4
4288 00:55:57.098550 best_step = 9
4289 00:55:57.098608
4290 00:55:57.102258 ==
4291 00:55:57.105433 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 00:55:57.108514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 00:55:57.108590 ==
4294 00:55:57.108651 RX Vref Scan: 0
4295 00:55:57.108709
4296 00:55:57.111996 RX Vref 0 -> 0, step: 1
4297 00:55:57.112095
4298 00:55:57.115436 RX Delay -179 -> 252, step: 8
4299 00:55:57.122021 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4300 00:55:57.125004 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4301 00:55:57.128406 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4302 00:55:57.131973 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4303 00:55:57.135239 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4304 00:55:57.141730 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4305 00:55:57.144720 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4306 00:55:57.147918 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4307 00:55:57.151870 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4308 00:55:57.158137 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4309 00:55:57.161394 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4310 00:55:57.164528 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4311 00:55:57.167911 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4312 00:55:57.174538 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4313 00:55:57.178106 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4314 00:55:57.181506 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4315 00:55:57.181585 ==
4316 00:55:57.184697 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 00:55:57.187800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 00:55:57.187904 ==
4319 00:55:57.191468 DQS Delay:
4320 00:55:57.191566 DQS0 = 0, DQS1 = 0
4321 00:55:57.194475 DQM Delay:
4322 00:55:57.194546 DQM0 = 43, DQM1 = 36
4323 00:55:57.194606 DQ Delay:
4324 00:55:57.197530 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4325 00:55:57.201392 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =48
4326 00:55:57.204307 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4327 00:55:57.207558 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4328 00:55:57.207698
4329 00:55:57.207791
4330 00:55:57.218139 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c47, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4331 00:55:57.221189 CH0 RK1: MR19=808, MR18=4C47
4332 00:55:57.227543 CH0_RK1: MR19=0x808, MR18=0x4C47, DQSOSC=395, MR23=63, INC=168, DEC=112
4333 00:55:57.227623 [RxdqsGatingPostProcess] freq 600
4334 00:55:57.234098 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4335 00:55:57.237614 Pre-setting of DQS Precalculation
4336 00:55:57.240751 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4337 00:55:57.244487 ==
4338 00:55:57.247192 Dram Type= 6, Freq= 0, CH_1, rank 0
4339 00:55:57.250381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 00:55:57.250453 ==
4341 00:55:57.257184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4342 00:55:57.260241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4343 00:55:57.264743 [CA 0] Center 35 (5~66) winsize 62
4344 00:55:57.267940 [CA 1] Center 35 (5~66) winsize 62
4345 00:55:57.271260 [CA 2] Center 35 (5~65) winsize 61
4346 00:55:57.274211 [CA 3] Center 34 (4~65) winsize 62
4347 00:55:57.278046 [CA 4] Center 34 (4~65) winsize 62
4348 00:55:57.281216 [CA 5] Center 34 (3~65) winsize 63
4349 00:55:57.281346
4350 00:55:57.284447 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4351 00:55:57.284531
4352 00:55:57.287446 [CATrainingPosCal] consider 1 rank data
4353 00:55:57.290995 u2DelayCellTimex100 = 270/100 ps
4354 00:55:57.294797 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4355 00:55:57.301041 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4356 00:55:57.304256 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4357 00:55:57.307306 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4358 00:55:57.310664 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4359 00:55:57.313981 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4360 00:55:57.314066
4361 00:55:57.317500 CA PerBit enable=1, Macro0, CA PI delay=34
4362 00:55:57.317592
4363 00:55:57.320945 [CBTSetCACLKResult] CA Dly = 34
4364 00:55:57.324230 CS Dly: 4 (0~35)
4365 00:55:57.324314 ==
4366 00:55:57.327149 Dram Type= 6, Freq= 0, CH_1, rank 1
4367 00:55:57.330266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 00:55:57.330349 ==
4369 00:55:57.337509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4370 00:55:57.340504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4371 00:55:57.344602 [CA 0] Center 36 (6~66) winsize 61
4372 00:55:57.347751 [CA 1] Center 35 (5~66) winsize 62
4373 00:55:57.350885 [CA 2] Center 34 (4~65) winsize 62
4374 00:55:57.354669 [CA 3] Center 34 (3~65) winsize 63
4375 00:55:57.357892 [CA 4] Center 34 (4~65) winsize 62
4376 00:55:57.360776 [CA 5] Center 33 (3~64) winsize 62
4377 00:55:57.360866
4378 00:55:57.364510 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4379 00:55:57.364605
4380 00:55:57.367898 [CATrainingPosCal] consider 2 rank data
4381 00:55:57.370573 u2DelayCellTimex100 = 270/100 ps
4382 00:55:57.373893 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4383 00:55:57.380637 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4384 00:55:57.383659 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4385 00:55:57.387237 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 00:55:57.390725 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 00:55:57.393673 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 00:55:57.393825
4389 00:55:57.397066 CA PerBit enable=1, Macro0, CA PI delay=33
4390 00:55:57.397339
4391 00:55:57.400031 [CBTSetCACLKResult] CA Dly = 33
4392 00:55:57.403735 CS Dly: 5 (0~37)
4393 00:55:57.403943
4394 00:55:57.407266 ----->DramcWriteLeveling(PI) begin...
4395 00:55:57.407531 ==
4396 00:55:57.410228 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 00:55:57.413644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 00:55:57.413998 ==
4399 00:55:57.416852 Write leveling (Byte 0): 29 => 29
4400 00:55:57.420239 Write leveling (Byte 1): 30 => 30
4401 00:55:57.423251 DramcWriteLeveling(PI) end<-----
4402 00:55:57.423573
4403 00:55:57.423887 ==
4404 00:55:57.426448 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 00:55:57.429792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 00:55:57.430002 ==
4407 00:55:57.433106 [Gating] SW mode calibration
4408 00:55:57.439914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4409 00:55:57.446628 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4410 00:55:57.449575 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 00:55:57.456022 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 00:55:57.459438 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 00:55:57.462718 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (1 0) (0 0)
4414 00:55:57.468929 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 00:55:57.472826 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 00:55:57.475670 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 00:55:57.482676 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 00:55:57.486010 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 00:55:57.489101 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 00:55:57.495557 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 00:55:57.498994 0 10 12 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
4422 00:55:57.501844 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 00:55:57.508928 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 00:55:57.512133 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 00:55:57.515666 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 00:55:57.522078 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 00:55:57.525218 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 00:55:57.528542 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 00:55:57.535512 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4430 00:55:57.538343 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4431 00:55:57.541737 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 00:55:57.548203 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 00:55:57.551284 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 00:55:57.554939 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 00:55:57.561444 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 00:55:57.564340 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:55:57.567990 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:55:57.574312 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:55:57.577805 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 00:55:57.581143 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 00:55:57.588578 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 00:55:57.590844 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 00:55:57.594306 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 00:55:57.600870 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:55:57.604019 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4446 00:55:57.607740 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 00:55:57.610578 Total UI for P1: 0, mck2ui 16
4448 00:55:57.613860 best dqsien dly found for B0: ( 0, 13, 12)
4449 00:55:57.617233 Total UI for P1: 0, mck2ui 16
4450 00:55:57.620295 best dqsien dly found for B1: ( 0, 13, 14)
4451 00:55:57.623776 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4452 00:55:57.627227 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4453 00:55:57.630145
4454 00:55:57.633739 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4455 00:55:57.637267 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4456 00:55:57.639990 [Gating] SW calibration Done
4457 00:55:57.640072 ==
4458 00:55:57.643548 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 00:55:57.646853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 00:55:57.646939 ==
4461 00:55:57.647005 RX Vref Scan: 0
4462 00:55:57.650253
4463 00:55:57.650335 RX Vref 0 -> 0, step: 1
4464 00:55:57.650400
4465 00:55:57.653330 RX Delay -230 -> 252, step: 16
4466 00:55:57.657046 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4467 00:55:57.663806 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4468 00:55:57.666651 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4469 00:55:57.669712 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4470 00:55:57.672939 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4471 00:55:57.679884 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4472 00:55:57.683252 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4473 00:55:57.686184 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4474 00:55:57.689646 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4475 00:55:57.693360 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4476 00:55:57.699425 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4477 00:55:57.702934 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4478 00:55:57.706066 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4479 00:55:57.709907 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4480 00:55:57.716002 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4481 00:55:57.719350 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4482 00:55:57.719433 ==
4483 00:55:57.722730 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 00:55:57.725992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 00:55:57.726075 ==
4486 00:55:57.728883 DQS Delay:
4487 00:55:57.728965 DQS0 = 0, DQS1 = 0
4488 00:55:57.732229 DQM Delay:
4489 00:55:57.732313 DQM0 = 43, DQM1 = 37
4490 00:55:57.732378 DQ Delay:
4491 00:55:57.735661 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4492 00:55:57.739235 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4493 00:55:57.742616 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4494 00:55:57.745609 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4495 00:55:57.745693
4496 00:55:57.745757
4497 00:55:57.748842 ==
4498 00:55:57.752185 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 00:55:57.755213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 00:55:57.755297 ==
4501 00:55:57.755362
4502 00:55:57.755421
4503 00:55:57.759160 TX Vref Scan disable
4504 00:55:57.759242 == TX Byte 0 ==
4505 00:55:57.765373 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4506 00:55:57.768791 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4507 00:55:57.768874 == TX Byte 1 ==
4508 00:55:57.774896 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4509 00:55:57.778548 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4510 00:55:57.778632 ==
4511 00:55:57.781581 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 00:55:57.785528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 00:55:57.785645 ==
4514 00:55:57.785740
4515 00:55:57.785828
4516 00:55:57.788518 TX Vref Scan disable
4517 00:55:57.791679 == TX Byte 0 ==
4518 00:55:57.794699 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4519 00:55:57.798271 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4520 00:55:57.801548 == TX Byte 1 ==
4521 00:55:57.804674 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4522 00:55:57.811127 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4523 00:55:57.811330
4524 00:55:57.811426 [DATLAT]
4525 00:55:57.811529 Freq=600, CH1 RK0
4526 00:55:57.811652
4527 00:55:57.814195 DATLAT Default: 0x9
4528 00:55:57.814314 0, 0xFFFF, sum = 0
4529 00:55:57.817635 1, 0xFFFF, sum = 0
4530 00:55:57.821696 2, 0xFFFF, sum = 0
4531 00:55:57.821829 3, 0xFFFF, sum = 0
4532 00:55:57.824291 4, 0xFFFF, sum = 0
4533 00:55:57.824385 5, 0xFFFF, sum = 0
4534 00:55:57.827899 6, 0xFFFF, sum = 0
4535 00:55:57.828012 7, 0xFFFF, sum = 0
4536 00:55:57.831101 8, 0x0, sum = 1
4537 00:55:57.831187 9, 0x0, sum = 2
4538 00:55:57.831255 10, 0x0, sum = 3
4539 00:55:57.834329 11, 0x0, sum = 4
4540 00:55:57.834414 best_step = 9
4541 00:55:57.834480
4542 00:55:57.837587 ==
4543 00:55:57.837703 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 00:55:57.844135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 00:55:57.844296 ==
4546 00:55:57.844395 RX Vref Scan: 1
4547 00:55:57.844486
4548 00:55:57.847553 RX Vref 0 -> 0, step: 1
4549 00:55:57.847639
4550 00:55:57.850765 RX Delay -179 -> 252, step: 8
4551 00:55:57.850855
4552 00:55:57.854076 Set Vref, RX VrefLevel [Byte0]: 52
4553 00:55:57.857197 [Byte1]: 50
4554 00:55:57.857319
4555 00:55:57.860777 Final RX Vref Byte 0 = 52 to rank0
4556 00:55:57.864053 Final RX Vref Byte 1 = 50 to rank0
4557 00:55:57.867087 Final RX Vref Byte 0 = 52 to rank1
4558 00:55:57.870370 Final RX Vref Byte 1 = 50 to rank1==
4559 00:55:57.873679 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 00:55:57.876993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 00:55:57.880416 ==
4562 00:55:57.880510 DQS Delay:
4563 00:55:57.880576 DQS0 = 0, DQS1 = 0
4564 00:55:57.883524 DQM Delay:
4565 00:55:57.883615 DQM0 = 41, DQM1 = 34
4566 00:55:57.886964 DQ Delay:
4567 00:55:57.890596 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4568 00:55:57.890683 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4569 00:55:57.893932 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4570 00:55:57.896863 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4571 00:55:57.900379
4572 00:55:57.900475
4573 00:55:57.906529 [DQSOSCAuto] RK0, (LSB)MR18= 0x304a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4574 00:55:57.909876 CH1 RK0: MR19=808, MR18=304A
4575 00:55:57.916763 CH1_RK0: MR19=0x808, MR18=0x304A, DQSOSC=395, MR23=63, INC=168, DEC=112
4576 00:55:57.916853
4577 00:55:57.919694 ----->DramcWriteLeveling(PI) begin...
4578 00:55:57.919779 ==
4579 00:55:57.923173 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 00:55:57.926738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 00:55:57.926834 ==
4582 00:55:57.929696 Write leveling (Byte 0): 28 => 28
4583 00:55:57.933235 Write leveling (Byte 1): 29 => 29
4584 00:55:57.936073 DramcWriteLeveling(PI) end<-----
4585 00:55:57.936163
4586 00:55:57.936229 ==
4587 00:55:57.939471 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 00:55:57.942645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 00:55:57.942760 ==
4590 00:55:57.946275 [Gating] SW mode calibration
4591 00:55:57.952696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4592 00:55:57.959153 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4593 00:55:57.962696 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 00:55:57.969408 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 00:55:57.972889 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4596 00:55:57.976095 0 9 12 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (0 0)
4597 00:55:57.982254 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4598 00:55:57.985792 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 00:55:57.989233 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 00:55:57.995351 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 00:55:57.999403 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 00:55:58.002443 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 00:55:58.008967 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4604 00:55:58.012205 0 10 12 | B1->B0 | 3131 4040 | 0 1 | (1 1) (0 0)
4605 00:55:58.015508 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 00:55:58.022267 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 00:55:58.025717 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 00:55:58.028735 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 00:55:58.035188 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 00:55:58.038535 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 00:55:58.041944 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 00:55:58.048816 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4613 00:55:58.051879 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 00:55:58.055133 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 00:55:58.061987 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 00:55:58.065230 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 00:55:58.068711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 00:55:58.074717 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 00:55:58.078263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 00:55:58.081760 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 00:55:58.088087 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 00:55:58.091393 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 00:55:58.094808 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 00:55:58.101247 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 00:55:58.104251 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 00:55:58.107621 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 00:55:58.114092 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4628 00:55:58.117510 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4629 00:55:58.121076 Total UI for P1: 0, mck2ui 16
4630 00:55:58.124184 best dqsien dly found for B0: ( 0, 13, 8)
4631 00:55:58.127724 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 00:55:58.130967 Total UI for P1: 0, mck2ui 16
4633 00:55:58.133881 best dqsien dly found for B1: ( 0, 13, 14)
4634 00:55:58.137067 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4635 00:55:58.140394 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4636 00:55:58.144014
4637 00:55:58.146952 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4638 00:55:58.150488 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4639 00:55:58.153999 [Gating] SW calibration Done
4640 00:55:58.154165 ==
4641 00:55:58.157061 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 00:55:58.160311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 00:55:58.160459 ==
4644 00:55:58.160560 RX Vref Scan: 0
4645 00:55:58.163625
4646 00:55:58.163742 RX Vref 0 -> 0, step: 1
4647 00:55:58.163837
4648 00:55:58.166898 RX Delay -230 -> 252, step: 16
4649 00:55:58.170473 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4650 00:55:58.176462 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4651 00:55:58.180071 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4652 00:55:58.183427 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4653 00:55:58.186299 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4654 00:55:58.189964 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4655 00:55:58.196267 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4656 00:55:58.199552 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4657 00:55:58.203180 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4658 00:55:58.206353 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4659 00:55:58.213436 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4660 00:55:58.216018 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4661 00:55:58.219286 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4662 00:55:58.222818 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4663 00:55:58.229197 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4664 00:55:58.232183 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4665 00:55:58.232337 ==
4666 00:55:58.236138 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 00:55:58.239463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 00:55:58.239596 ==
4669 00:55:58.242897 DQS Delay:
4670 00:55:58.243025 DQS0 = 0, DQS1 = 0
4671 00:55:58.245794 DQM Delay:
4672 00:55:58.245935 DQM0 = 43, DQM1 = 39
4673 00:55:58.246039 DQ Delay:
4674 00:55:58.248780 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4675 00:55:58.252140 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4676 00:55:58.255511 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4677 00:55:58.258868 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4678 00:55:58.258985
4679 00:55:58.259074
4680 00:55:58.262189 ==
4681 00:55:58.265705 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 00:55:58.268879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 00:55:58.268973 ==
4684 00:55:58.269046
4685 00:55:58.269112
4686 00:55:58.272250 TX Vref Scan disable
4687 00:55:58.272336 == TX Byte 0 ==
4688 00:55:58.278553 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4689 00:55:58.281930 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4690 00:55:58.282027 == TX Byte 1 ==
4691 00:55:58.288546 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4692 00:55:58.291950 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4693 00:55:58.292061 ==
4694 00:55:58.295132 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 00:55:58.298168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 00:55:58.298244 ==
4697 00:55:58.298306
4698 00:55:58.298364
4699 00:55:58.301554 TX Vref Scan disable
4700 00:55:58.305078 == TX Byte 0 ==
4701 00:55:58.307993 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4702 00:55:58.311313 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4703 00:55:58.315014 == TX Byte 1 ==
4704 00:55:58.317979 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4705 00:55:58.321201 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4706 00:55:58.324619
4707 00:55:58.324707 [DATLAT]
4708 00:55:58.324772 Freq=600, CH1 RK1
4709 00:55:58.324832
4710 00:55:58.327847 DATLAT Default: 0x9
4711 00:55:58.327955 0, 0xFFFF, sum = 0
4712 00:55:58.332034 1, 0xFFFF, sum = 0
4713 00:55:58.332166 2, 0xFFFF, sum = 0
4714 00:55:58.334695 3, 0xFFFF, sum = 0
4715 00:55:58.334802 4, 0xFFFF, sum = 0
4716 00:55:58.337960 5, 0xFFFF, sum = 0
4717 00:55:58.341318 6, 0xFFFF, sum = 0
4718 00:55:58.341412 7, 0xFFFF, sum = 0
4719 00:55:58.344148 8, 0x0, sum = 1
4720 00:55:58.344234 9, 0x0, sum = 2
4721 00:55:58.344301 10, 0x0, sum = 3
4722 00:55:58.348138 11, 0x0, sum = 4
4723 00:55:58.348233 best_step = 9
4724 00:55:58.348299
4725 00:55:58.348359 ==
4726 00:55:58.351090 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 00:55:58.357211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 00:55:58.357371 ==
4729 00:55:58.357471 RX Vref Scan: 0
4730 00:55:58.357532
4731 00:55:58.360566 RX Vref 0 -> 0, step: 1
4732 00:55:58.360654
4733 00:55:58.363952 RX Delay -179 -> 252, step: 8
4734 00:55:58.367437 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4735 00:55:58.374468 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4736 00:55:58.377189 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4737 00:55:58.380654 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4738 00:55:58.384063 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4739 00:55:58.390762 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4740 00:55:58.393873 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4741 00:55:58.397005 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4742 00:55:58.400514 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4743 00:55:58.407192 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4744 00:55:58.410406 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4745 00:55:58.413750 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4746 00:55:58.416786 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4747 00:55:58.423643 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4748 00:55:58.426877 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4749 00:55:58.430459 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4750 00:55:58.430595 ==
4751 00:55:58.433770 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 00:55:58.436876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 00:55:58.437050 ==
4754 00:55:58.440754 DQS Delay:
4755 00:55:58.440924 DQS0 = 0, DQS1 = 0
4756 00:55:58.443177 DQM Delay:
4757 00:55:58.443471 DQM0 = 38, DQM1 = 34
4758 00:55:58.443714 DQ Delay:
4759 00:55:58.446894 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4760 00:55:58.450054 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4761 00:55:58.453170 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4762 00:55:58.457013 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4763 00:55:58.457404
4764 00:55:58.457692
4765 00:55:58.466691 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d63, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4766 00:55:58.470380 CH1 RK1: MR19=808, MR18=3D63
4767 00:55:58.476322 CH1_RK1: MR19=0x808, MR18=0x3D63, DQSOSC=391, MR23=63, INC=171, DEC=114
4768 00:55:58.480366 [RxdqsGatingPostProcess] freq 600
4769 00:55:58.483117 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4770 00:55:58.486475 Pre-setting of DQS Precalculation
4771 00:55:58.493148 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4772 00:55:58.499713 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4773 00:55:58.506645 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4774 00:55:58.507033
4775 00:55:58.507336
4776 00:55:58.509858 [Calibration Summary] 1200 Mbps
4777 00:55:58.510344 CH 0, Rank 0
4778 00:55:58.512719 SW Impedance : PASS
4779 00:55:58.515907 DUTY Scan : NO K
4780 00:55:58.516304 ZQ Calibration : PASS
4781 00:55:58.519324 Jitter Meter : NO K
4782 00:55:58.522623 CBT Training : PASS
4783 00:55:58.523018 Write leveling : PASS
4784 00:55:58.525774 RX DQS gating : PASS
4785 00:55:58.529692 RX DQ/DQS(RDDQC) : PASS
4786 00:55:58.530137 TX DQ/DQS : PASS
4787 00:55:58.532387 RX DATLAT : PASS
4788 00:55:58.535872 RX DQ/DQS(Engine): PASS
4789 00:55:58.536306 TX OE : NO K
4790 00:55:58.536708 All Pass.
4791 00:55:58.539167
4792 00:55:58.539559 CH 0, Rank 1
4793 00:55:58.542881 SW Impedance : PASS
4794 00:55:58.543275 DUTY Scan : NO K
4795 00:55:58.545611 ZQ Calibration : PASS
4796 00:55:58.549476 Jitter Meter : NO K
4797 00:55:58.549871 CBT Training : PASS
4798 00:55:58.552293 Write leveling : PASS
4799 00:55:58.552779 RX DQS gating : PASS
4800 00:55:58.555162 RX DQ/DQS(RDDQC) : PASS
4801 00:55:58.558879 TX DQ/DQS : PASS
4802 00:55:58.559306 RX DATLAT : PASS
4803 00:55:58.562145 RX DQ/DQS(Engine): PASS
4804 00:55:58.565045 TX OE : NO K
4805 00:55:58.565494 All Pass.
4806 00:55:58.565895
4807 00:55:58.566271 CH 1, Rank 0
4808 00:55:58.568649 SW Impedance : PASS
4809 00:55:58.571957 DUTY Scan : NO K
4810 00:55:58.572351 ZQ Calibration : PASS
4811 00:55:58.575504 Jitter Meter : NO K
4812 00:55:58.578397 CBT Training : PASS
4813 00:55:58.578778 Write leveling : PASS
4814 00:55:58.581921 RX DQS gating : PASS
4815 00:55:58.584868 RX DQ/DQS(RDDQC) : PASS
4816 00:55:58.585251 TX DQ/DQS : PASS
4817 00:55:58.588435 RX DATLAT : PASS
4818 00:55:58.591952 RX DQ/DQS(Engine): PASS
4819 00:55:58.592337 TX OE : NO K
4820 00:55:58.594639 All Pass.
4821 00:55:58.595019
4822 00:55:58.595320 CH 1, Rank 1
4823 00:55:58.598456 SW Impedance : PASS
4824 00:55:58.598844 DUTY Scan : NO K
4825 00:55:58.601206 ZQ Calibration : PASS
4826 00:55:58.604886 Jitter Meter : NO K
4827 00:55:58.605446 CBT Training : PASS
4828 00:55:58.608000 Write leveling : PASS
4829 00:55:58.611147 RX DQS gating : PASS
4830 00:55:58.611533 RX DQ/DQS(RDDQC) : PASS
4831 00:55:58.614635 TX DQ/DQS : PASS
4832 00:55:58.617647 RX DATLAT : PASS
4833 00:55:58.618046 RX DQ/DQS(Engine): PASS
4834 00:55:58.620903 TX OE : NO K
4835 00:55:58.621334 All Pass.
4836 00:55:58.621738
4837 00:55:58.624177 DramC Write-DBI off
4838 00:55:58.627464 PER_BANK_REFRESH: Hybrid Mode
4839 00:55:58.627751 TX_TRACKING: ON
4840 00:55:58.637302 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4841 00:55:58.640616 [FAST_K] Save calibration result to emmc
4842 00:55:58.644000 dramc_set_vcore_voltage set vcore to 662500
4843 00:55:58.647315 Read voltage for 933, 3
4844 00:55:58.647447 Vio18 = 0
4845 00:55:58.647578 Vcore = 662500
4846 00:55:58.650463 Vdram = 0
4847 00:55:58.650592 Vddq = 0
4848 00:55:58.650724 Vmddr = 0
4849 00:55:58.657081 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4850 00:55:58.660545 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4851 00:55:58.663546 MEM_TYPE=3, freq_sel=17
4852 00:55:58.666976 sv_algorithm_assistance_LP4_1600
4853 00:55:58.670576 ============ PULL DRAM RESETB DOWN ============
4854 00:55:58.673573 ========== PULL DRAM RESETB DOWN end =========
4855 00:55:58.680001 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4856 00:55:58.683431 ===================================
4857 00:55:58.686843 LPDDR4 DRAM CONFIGURATION
4858 00:55:58.690011 ===================================
4859 00:55:58.690100 EX_ROW_EN[0] = 0x0
4860 00:55:58.693155 EX_ROW_EN[1] = 0x0
4861 00:55:58.693243 LP4Y_EN = 0x0
4862 00:55:58.696269 WORK_FSP = 0x0
4863 00:55:58.696361 WL = 0x3
4864 00:55:58.699727 RL = 0x3
4865 00:55:58.699814 BL = 0x2
4866 00:55:58.703355 RPST = 0x0
4867 00:55:58.703440 RD_PRE = 0x0
4868 00:55:58.706821 WR_PRE = 0x1
4869 00:55:58.710265 WR_PST = 0x0
4870 00:55:58.710349 DBI_WR = 0x0
4871 00:55:58.712775 DBI_RD = 0x0
4872 00:55:58.712859 OTF = 0x1
4873 00:55:58.716099 ===================================
4874 00:55:58.719367 ===================================
4875 00:55:58.719452 ANA top config
4876 00:55:58.723157 ===================================
4877 00:55:58.726217 DLL_ASYNC_EN = 0
4878 00:55:58.729427 ALL_SLAVE_EN = 1
4879 00:55:58.733087 NEW_RANK_MODE = 1
4880 00:55:58.735988 DLL_IDLE_MODE = 1
4881 00:55:58.736072 LP45_APHY_COMB_EN = 1
4882 00:55:58.739532 TX_ODT_DIS = 1
4883 00:55:58.742498 NEW_8X_MODE = 1
4884 00:55:58.745699 ===================================
4885 00:55:58.749153 ===================================
4886 00:55:58.752742 data_rate = 1866
4887 00:55:58.756176 CKR = 1
4888 00:55:58.758757 DQ_P2S_RATIO = 8
4889 00:55:58.762663 ===================================
4890 00:55:58.762803 CA_P2S_RATIO = 8
4891 00:55:58.765813 DQ_CA_OPEN = 0
4892 00:55:58.768955 DQ_SEMI_OPEN = 0
4893 00:55:58.772214 CA_SEMI_OPEN = 0
4894 00:55:58.775429 CA_FULL_RATE = 0
4895 00:55:58.779030 DQ_CKDIV4_EN = 1
4896 00:55:58.779239 CA_CKDIV4_EN = 1
4897 00:55:58.781924 CA_PREDIV_EN = 0
4898 00:55:58.785467 PH8_DLY = 0
4899 00:55:58.788947 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4900 00:55:58.792335 DQ_AAMCK_DIV = 4
4901 00:55:58.795516 CA_AAMCK_DIV = 4
4902 00:55:58.795881 CA_ADMCK_DIV = 4
4903 00:55:58.798999 DQ_TRACK_CA_EN = 0
4904 00:55:58.802055 CA_PICK = 933
4905 00:55:58.805714 CA_MCKIO = 933
4906 00:55:58.808722 MCKIO_SEMI = 0
4907 00:55:58.811897 PLL_FREQ = 3732
4908 00:55:58.815317 DQ_UI_PI_RATIO = 32
4909 00:55:58.815712 CA_UI_PI_RATIO = 0
4910 00:55:58.818428 ===================================
4911 00:55:58.821901 ===================================
4912 00:55:58.825577 memory_type:LPDDR4
4913 00:55:58.828636 GP_NUM : 10
4914 00:55:58.829046 SRAM_EN : 1
4915 00:55:58.832179 MD32_EN : 0
4916 00:55:58.835148 ===================================
4917 00:55:58.838276 [ANA_INIT] >>>>>>>>>>>>>>
4918 00:55:58.841990 <<<<<< [CONFIGURE PHASE]: ANA_TX
4919 00:55:58.845026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4920 00:55:58.848430 ===================================
4921 00:55:58.851916 data_rate = 1866,PCW = 0X8f00
4922 00:55:58.854702 ===================================
4923 00:55:58.858074 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4924 00:55:58.861249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 00:55:58.867870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 00:55:58.871075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4927 00:55:58.874520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4928 00:55:58.877870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4929 00:55:58.881283 [ANA_INIT] flow start
4930 00:55:58.884382 [ANA_INIT] PLL >>>>>>>>
4931 00:55:58.884778 [ANA_INIT] PLL <<<<<<<<
4932 00:55:58.887972 [ANA_INIT] MIDPI >>>>>>>>
4933 00:55:58.891265 [ANA_INIT] MIDPI <<<<<<<<
4934 00:55:58.894490 [ANA_INIT] DLL >>>>>>>>
4935 00:55:58.894883 [ANA_INIT] flow end
4936 00:55:58.897617 ============ LP4 DIFF to SE enter ============
4937 00:55:58.905061 ============ LP4 DIFF to SE exit ============
4938 00:55:58.905464 [ANA_INIT] <<<<<<<<<<<<<
4939 00:55:58.907810 [Flow] Enable top DCM control >>>>>
4940 00:55:58.910984 [Flow] Enable top DCM control <<<<<
4941 00:55:58.914030 Enable DLL master slave shuffle
4942 00:55:58.921169 ==============================================================
4943 00:55:58.921615 Gating Mode config
4944 00:55:58.927175 ==============================================================
4945 00:55:58.930204 Config description:
4946 00:55:58.940498 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4947 00:55:58.946614 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4948 00:55:58.949982 SELPH_MODE 0: By rank 1: By Phase
4949 00:55:58.956621 ==============================================================
4950 00:55:58.960156 GAT_TRACK_EN = 1
4951 00:55:58.963712 RX_GATING_MODE = 2
4952 00:55:58.966457 RX_GATING_TRACK_MODE = 2
4953 00:55:58.966605 SELPH_MODE = 1
4954 00:55:58.969880 PICG_EARLY_EN = 1
4955 00:55:58.973238 VALID_LAT_VALUE = 1
4956 00:55:58.979848 ==============================================================
4957 00:55:58.983087 Enter into Gating configuration >>>>
4958 00:55:58.986774 Exit from Gating configuration <<<<
4959 00:55:58.989655 Enter into DVFS_PRE_config >>>>>
4960 00:55:58.999421 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4961 00:55:59.002616 Exit from DVFS_PRE_config <<<<<
4962 00:55:59.006185 Enter into PICG configuration >>>>
4963 00:55:59.009336 Exit from PICG configuration <<<<
4964 00:55:59.012661 [RX_INPUT] configuration >>>>>
4965 00:55:59.016049 [RX_INPUT] configuration <<<<<
4966 00:55:59.019020 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4967 00:55:59.025700 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4968 00:55:59.032912 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4969 00:55:59.039081 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4970 00:55:59.045664 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 00:55:59.052186 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 00:55:59.055533 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4973 00:55:59.059101 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4974 00:55:59.062198 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4975 00:55:59.068920 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4976 00:55:59.072183 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4977 00:55:59.075508 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4978 00:55:59.078445 ===================================
4979 00:55:59.081903 LPDDR4 DRAM CONFIGURATION
4980 00:55:59.085201 ===================================
4981 00:55:59.085747 EX_ROW_EN[0] = 0x0
4982 00:55:59.089067 EX_ROW_EN[1] = 0x0
4983 00:55:59.091811 LP4Y_EN = 0x0
4984 00:55:59.092300 WORK_FSP = 0x0
4985 00:55:59.095180 WL = 0x3
4986 00:55:59.095595 RL = 0x3
4987 00:55:59.098489 BL = 0x2
4988 00:55:59.098905 RPST = 0x0
4989 00:55:59.102059 RD_PRE = 0x0
4990 00:55:59.102455 WR_PRE = 0x1
4991 00:55:59.105670 WR_PST = 0x0
4992 00:55:59.106180 DBI_WR = 0x0
4993 00:55:59.108757 DBI_RD = 0x0
4994 00:55:59.109227 OTF = 0x1
4995 00:55:59.111568 ===================================
4996 00:55:59.114673 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4997 00:55:59.121222 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4998 00:55:59.124669 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4999 00:55:59.128118 ===================================
5000 00:55:59.131425 LPDDR4 DRAM CONFIGURATION
5001 00:55:59.134427 ===================================
5002 00:55:59.134729 EX_ROW_EN[0] = 0x10
5003 00:55:59.137739 EX_ROW_EN[1] = 0x0
5004 00:55:59.141437 LP4Y_EN = 0x0
5005 00:55:59.141689 WORK_FSP = 0x0
5006 00:55:59.144237 WL = 0x3
5007 00:55:59.144503 RL = 0x3
5008 00:55:59.147719 BL = 0x2
5009 00:55:59.147978 RPST = 0x0
5010 00:55:59.150799 RD_PRE = 0x0
5011 00:55:59.150985 WR_PRE = 0x1
5012 00:55:59.154027 WR_PST = 0x0
5013 00:55:59.154152 DBI_WR = 0x0
5014 00:55:59.157272 DBI_RD = 0x0
5015 00:55:59.157382 OTF = 0x1
5016 00:55:59.161083 ===================================
5017 00:55:59.167640 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5018 00:55:59.171788 nWR fixed to 30
5019 00:55:59.175512 [ModeRegInit_LP4] CH0 RK0
5020 00:55:59.175615 [ModeRegInit_LP4] CH0 RK1
5021 00:55:59.178830 [ModeRegInit_LP4] CH1 RK0
5022 00:55:59.181710 [ModeRegInit_LP4] CH1 RK1
5023 00:55:59.181822 match AC timing 9
5024 00:55:59.188391 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5025 00:55:59.191700 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5026 00:55:59.194848 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5027 00:55:59.201943 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5028 00:55:59.205503 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5029 00:55:59.205585 ==
5030 00:55:59.208001 Dram Type= 6, Freq= 0, CH_0, rank 0
5031 00:55:59.211352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5032 00:55:59.211440 ==
5033 00:55:59.218351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5034 00:55:59.224790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5035 00:55:59.227789 [CA 0] Center 38 (7~69) winsize 63
5036 00:55:59.231414 [CA 1] Center 37 (7~68) winsize 62
5037 00:55:59.235133 [CA 2] Center 34 (4~65) winsize 62
5038 00:55:59.238317 [CA 3] Center 34 (3~65) winsize 63
5039 00:55:59.241294 [CA 4] Center 33 (3~64) winsize 62
5040 00:55:59.244882 [CA 5] Center 33 (3~63) winsize 61
5041 00:55:59.245007
5042 00:55:59.248183 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5043 00:55:59.248277
5044 00:55:59.251438 [CATrainingPosCal] consider 1 rank data
5045 00:55:59.254275 u2DelayCellTimex100 = 270/100 ps
5046 00:55:59.257662 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5047 00:55:59.261010 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5048 00:55:59.264834 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5049 00:55:59.267414 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5050 00:55:59.274154 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5051 00:55:59.277326 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5052 00:55:59.277409
5053 00:55:59.280790 CA PerBit enable=1, Macro0, CA PI delay=33
5054 00:55:59.280871
5055 00:55:59.284004 [CBTSetCACLKResult] CA Dly = 33
5056 00:55:59.284086 CS Dly: 6 (0~37)
5057 00:55:59.284150 ==
5058 00:55:59.287562 Dram Type= 6, Freq= 0, CH_0, rank 1
5059 00:55:59.293863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5060 00:55:59.293944 ==
5061 00:55:59.297160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5062 00:55:59.303806 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5063 00:55:59.306872 [CA 0] Center 38 (7~69) winsize 63
5064 00:55:59.310870 [CA 1] Center 37 (7~68) winsize 62
5065 00:55:59.313652 [CA 2] Center 34 (4~65) winsize 62
5066 00:55:59.317339 [CA 3] Center 34 (4~65) winsize 62
5067 00:55:59.320656 [CA 4] Center 33 (3~64) winsize 62
5068 00:55:59.323494 [CA 5] Center 33 (3~63) winsize 61
5069 00:55:59.323873
5070 00:55:59.327168 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5071 00:55:59.327547
5072 00:55:59.330953 [CATrainingPosCal] consider 2 rank data
5073 00:55:59.333532 u2DelayCellTimex100 = 270/100 ps
5074 00:55:59.336937 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5075 00:55:59.343619 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5076 00:55:59.347413 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5077 00:55:59.350072 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5078 00:55:59.353648 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5079 00:55:59.356769 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5080 00:55:59.357150
5081 00:55:59.359942 CA PerBit enable=1, Macro0, CA PI delay=33
5082 00:55:59.360379
5083 00:55:59.363393 [CBTSetCACLKResult] CA Dly = 33
5084 00:55:59.366683 CS Dly: 7 (0~39)
5085 00:55:59.367063
5086 00:55:59.369748 ----->DramcWriteLeveling(PI) begin...
5087 00:55:59.370168 ==
5088 00:55:59.373332 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 00:55:59.376190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 00:55:59.376564 ==
5091 00:55:59.379420 Write leveling (Byte 0): 31 => 31
5092 00:55:59.382720 Write leveling (Byte 1): 27 => 27
5093 00:55:59.386028 DramcWriteLeveling(PI) end<-----
5094 00:55:59.386211
5095 00:55:59.386349 ==
5096 00:55:59.389272 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 00:55:59.392562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 00:55:59.392700 ==
5099 00:55:59.396154 [Gating] SW mode calibration
5100 00:55:59.402780 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5101 00:55:59.409218 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5102 00:55:59.412592 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5103 00:55:59.415990 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5104 00:55:59.422696 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 00:55:59.425761 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 00:55:59.429078 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 00:55:59.435605 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 00:55:59.438754 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5109 00:55:59.442246 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5110 00:55:59.448621 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5111 00:55:59.451992 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5112 00:55:59.454881 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 00:55:59.461957 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 00:55:59.465096 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 00:55:59.468707 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 00:55:59.475291 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5117 00:55:59.478746 0 15 28 | B1->B0 | 2323 3938 | 0 1 | (0 0) (0 0)
5118 00:55:59.482032 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5119 00:55:59.488327 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 00:55:59.491786 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 00:55:59.494977 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 00:55:59.501680 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 00:55:59.504852 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 00:55:59.508254 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 00:55:59.514982 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5126 00:55:59.518232 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5127 00:55:59.521534 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 00:55:59.528746 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 00:55:59.531470 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 00:55:59.534574 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 00:55:59.540855 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 00:55:59.544076 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 00:55:59.547597 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 00:55:59.554070 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 00:55:59.557269 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 00:55:59.560623 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 00:55:59.567357 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 00:55:59.570813 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 00:55:59.576886 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 00:55:59.580256 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5141 00:55:59.583728 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5142 00:55:59.587004 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5143 00:55:59.593626 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 00:55:59.597248 Total UI for P1: 0, mck2ui 16
5145 00:55:59.600374 best dqsien dly found for B0: ( 1, 2, 28)
5146 00:55:59.603271 Total UI for P1: 0, mck2ui 16
5147 00:55:59.606438 best dqsien dly found for B1: ( 1, 3, 0)
5148 00:55:59.610113 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5149 00:55:59.613229 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5150 00:55:59.613389
5151 00:55:59.616377 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5152 00:55:59.619830 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5153 00:55:59.623050 [Gating] SW calibration Done
5154 00:55:59.623148 ==
5155 00:55:59.626393 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 00:55:59.630272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 00:55:59.630382 ==
5158 00:55:59.632922 RX Vref Scan: 0
5159 00:55:59.633009
5160 00:55:59.636180 RX Vref 0 -> 0, step: 1
5161 00:55:59.636277
5162 00:55:59.636347 RX Delay -80 -> 252, step: 8
5163 00:55:59.643096 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5164 00:55:59.646007 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5165 00:55:59.649457 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5166 00:55:59.652953 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5167 00:55:59.656219 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5168 00:55:59.662640 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5169 00:55:59.665865 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5170 00:55:59.669676 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5171 00:55:59.672464 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5172 00:55:59.675595 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5173 00:55:59.682574 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5174 00:55:59.685987 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5175 00:55:59.689151 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5176 00:55:59.692352 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5177 00:55:59.695474 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5178 00:55:59.698620 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5179 00:55:59.702151 ==
5180 00:55:59.705130 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 00:55:59.708571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 00:55:59.708649 ==
5183 00:55:59.708716 DQS Delay:
5184 00:55:59.711920 DQS0 = 0, DQS1 = 0
5185 00:55:59.711995 DQM Delay:
5186 00:55:59.715298 DQM0 = 103, DQM1 = 89
5187 00:55:59.715375 DQ Delay:
5188 00:55:59.718346 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5189 00:55:59.721466 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =107
5190 00:55:59.724948 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5191 00:55:59.728375 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =95
5192 00:55:59.728499
5193 00:55:59.728588
5194 00:55:59.728661 ==
5195 00:55:59.731616 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 00:55:59.735156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 00:55:59.737945 ==
5198 00:55:59.738036
5199 00:55:59.738104
5200 00:55:59.738164 TX Vref Scan disable
5201 00:55:59.742000 == TX Byte 0 ==
5202 00:55:59.744766 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5203 00:55:59.747875 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5204 00:55:59.751414 == TX Byte 1 ==
5205 00:55:59.754784 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5206 00:55:59.761167 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5207 00:55:59.761323 ==
5208 00:55:59.764349 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 00:55:59.767989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 00:55:59.768098 ==
5211 00:55:59.768189
5212 00:55:59.768276
5213 00:55:59.771062 TX Vref Scan disable
5214 00:55:59.771133 == TX Byte 0 ==
5215 00:55:59.777718 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5216 00:55:59.780926 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5217 00:55:59.784521 == TX Byte 1 ==
5218 00:55:59.787544 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5219 00:55:59.791109 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5220 00:55:59.791200
5221 00:55:59.791269 [DATLAT]
5222 00:55:59.794271 Freq=933, CH0 RK0
5223 00:55:59.794345
5224 00:55:59.794410 DATLAT Default: 0xd
5225 00:55:59.798067 0, 0xFFFF, sum = 0
5226 00:55:59.801122 1, 0xFFFF, sum = 0
5227 00:55:59.801212 2, 0xFFFF, sum = 0
5228 00:55:59.804452 3, 0xFFFF, sum = 0
5229 00:55:59.804539 4, 0xFFFF, sum = 0
5230 00:55:59.807677 5, 0xFFFF, sum = 0
5231 00:55:59.807760 6, 0xFFFF, sum = 0
5232 00:55:59.811004 7, 0xFFFF, sum = 0
5233 00:55:59.811087 8, 0xFFFF, sum = 0
5234 00:55:59.814256 9, 0xFFFF, sum = 0
5235 00:55:59.814338 10, 0x0, sum = 1
5236 00:55:59.817408 11, 0x0, sum = 2
5237 00:55:59.817490 12, 0x0, sum = 3
5238 00:55:59.820711 13, 0x0, sum = 4
5239 00:55:59.820794 best_step = 11
5240 00:55:59.820857
5241 00:55:59.820916 ==
5242 00:55:59.824150 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 00:55:59.827758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 00:55:59.827841 ==
5245 00:55:59.830583 RX Vref Scan: 1
5246 00:55:59.830664
5247 00:55:59.833801 RX Vref 0 -> 0, step: 1
5248 00:55:59.833882
5249 00:55:59.833946 RX Delay -61 -> 252, step: 4
5250 00:55:59.834006
5251 00:55:59.837202 Set Vref, RX VrefLevel [Byte0]: 58
5252 00:55:59.840096 [Byte1]: 50
5253 00:55:59.845245
5254 00:55:59.845381 Final RX Vref Byte 0 = 58 to rank0
5255 00:55:59.848811 Final RX Vref Byte 1 = 50 to rank0
5256 00:55:59.852066 Final RX Vref Byte 0 = 58 to rank1
5257 00:55:59.855559 Final RX Vref Byte 1 = 50 to rank1==
5258 00:55:59.858518 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 00:55:59.865288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 00:55:59.865380 ==
5261 00:55:59.865444 DQS Delay:
5262 00:55:59.865503 DQS0 = 0, DQS1 = 0
5263 00:55:59.868471 DQM Delay:
5264 00:55:59.868553 DQM0 = 102, DQM1 = 89
5265 00:55:59.871745 DQ Delay:
5266 00:55:59.875125 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =98
5267 00:55:59.878044 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =108
5268 00:55:59.881775 DQ8 =78, DQ9 =76, DQ10 =92, DQ11 =86
5269 00:55:59.884952 DQ12 =98, DQ13 =92, DQ14 =96, DQ15 =98
5270 00:55:59.885048
5271 00:55:59.885127
5272 00:55:59.891714 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5273 00:55:59.895171 CH0 RK0: MR19=505, MR18=1D18
5274 00:55:59.901554 CH0_RK0: MR19=0x505, MR18=0x1D18, DQSOSC=412, MR23=63, INC=63, DEC=42
5275 00:55:59.901703
5276 00:55:59.904488 ----->DramcWriteLeveling(PI) begin...
5277 00:55:59.904581 ==
5278 00:55:59.907859 Dram Type= 6, Freq= 0, CH_0, rank 1
5279 00:55:59.911119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 00:55:59.914280 ==
5281 00:55:59.914364 Write leveling (Byte 0): 34 => 34
5282 00:55:59.917688 Write leveling (Byte 1): 28 => 28
5283 00:55:59.921142 DramcWriteLeveling(PI) end<-----
5284 00:55:59.921239
5285 00:55:59.921332 ==
5286 00:55:59.924279 Dram Type= 6, Freq= 0, CH_0, rank 1
5287 00:55:59.931096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 00:55:59.931178 ==
5289 00:55:59.934619 [Gating] SW mode calibration
5290 00:55:59.941102 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5291 00:55:59.944200 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5292 00:55:59.950881 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5293 00:55:59.953959 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 00:55:59.957393 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 00:55:59.964002 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 00:55:59.967079 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 00:55:59.970591 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 00:55:59.976880 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 00:55:59.980640 0 14 28 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
5300 00:55:59.984251 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
5301 00:55:59.990081 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 00:55:59.993770 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 00:55:59.996979 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 00:56:00.003789 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 00:56:00.006603 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 00:56:00.010132 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 00:56:00.016324 0 15 28 | B1->B0 | 2828 4141 | 0 0 | (0 0) (0 0)
5308 00:56:00.020277 1 0 0 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
5309 00:56:00.023577 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 00:56:00.029800 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 00:56:00.033232 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 00:56:00.036362 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 00:56:00.042946 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 00:56:00.046658 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 00:56:00.049311 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5316 00:56:00.056223 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5317 00:56:00.059349 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 00:56:00.062877 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 00:56:00.069235 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 00:56:00.072523 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 00:56:00.075749 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 00:56:00.082442 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 00:56:00.085982 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 00:56:00.088959 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 00:56:00.095399 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 00:56:00.098948 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 00:56:00.102545 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 00:56:00.108833 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 00:56:00.112115 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 00:56:00.115013 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 00:56:00.121843 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5332 00:56:00.125403 Total UI for P1: 0, mck2ui 16
5333 00:56:00.128804 best dqsien dly found for B0: ( 1, 2, 26)
5334 00:56:00.132089 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 00:56:00.135555 Total UI for P1: 0, mck2ui 16
5336 00:56:00.138106 best dqsien dly found for B1: ( 1, 2, 28)
5337 00:56:00.141856 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5338 00:56:00.145175 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5339 00:56:00.145747
5340 00:56:00.148672 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5341 00:56:00.151644 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5342 00:56:00.154733 [Gating] SW calibration Done
5343 00:56:00.155168 ==
5344 00:56:00.158408 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 00:56:00.164914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 00:56:00.165409 ==
5347 00:56:00.165794 RX Vref Scan: 0
5348 00:56:00.166111
5349 00:56:00.168235 RX Vref 0 -> 0, step: 1
5350 00:56:00.168673
5351 00:56:00.171290 RX Delay -80 -> 252, step: 8
5352 00:56:00.174810 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5353 00:56:00.178070 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5354 00:56:00.181331 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5355 00:56:00.184667 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5356 00:56:00.191087 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5357 00:56:00.194240 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5358 00:56:00.197404 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5359 00:56:00.201446 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5360 00:56:00.204233 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5361 00:56:00.210934 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5362 00:56:00.214298 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5363 00:56:00.217211 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5364 00:56:00.220568 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5365 00:56:00.224161 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5366 00:56:00.227628 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5367 00:56:00.233747 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5368 00:56:00.234151 ==
5369 00:56:00.237038 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 00:56:00.240528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 00:56:00.241130 ==
5372 00:56:00.241581 DQS Delay:
5373 00:56:00.243896 DQS0 = 0, DQS1 = 0
5374 00:56:00.244339 DQM Delay:
5375 00:56:00.247315 DQM0 = 100, DQM1 = 89
5376 00:56:00.247736 DQ Delay:
5377 00:56:00.250234 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =99
5378 00:56:00.253507 DQ4 =99, DQ5 =87, DQ6 =111, DQ7 =107
5379 00:56:00.257190 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5380 00:56:00.260476 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =95
5381 00:56:00.261104
5382 00:56:00.261573
5383 00:56:00.261894 ==
5384 00:56:00.263676 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 00:56:00.270009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 00:56:00.270434 ==
5387 00:56:00.270793
5388 00:56:00.271103
5389 00:56:00.271412 TX Vref Scan disable
5390 00:56:00.273535 == TX Byte 0 ==
5391 00:56:00.277085 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5392 00:56:00.283532 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5393 00:56:00.284020 == TX Byte 1 ==
5394 00:56:00.287215 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5395 00:56:00.293566 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5396 00:56:00.293986 ==
5397 00:56:00.297201 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 00:56:00.300195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 00:56:00.300704 ==
5400 00:56:00.301100
5401 00:56:00.301516
5402 00:56:00.303210 TX Vref Scan disable
5403 00:56:00.306731 == TX Byte 0 ==
5404 00:56:00.309965 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5405 00:56:00.313384 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5406 00:56:00.316594 == TX Byte 1 ==
5407 00:56:00.319937 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5408 00:56:00.323156 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5409 00:56:00.323573
5410 00:56:00.323930 [DATLAT]
5411 00:56:00.326280 Freq=933, CH0 RK1
5412 00:56:00.326732
5413 00:56:00.327062 DATLAT Default: 0xb
5414 00:56:00.329508 0, 0xFFFF, sum = 0
5415 00:56:00.333429 1, 0xFFFF, sum = 0
5416 00:56:00.333853 2, 0xFFFF, sum = 0
5417 00:56:00.336453 3, 0xFFFF, sum = 0
5418 00:56:00.336905 4, 0xFFFF, sum = 0
5419 00:56:00.339875 5, 0xFFFF, sum = 0
5420 00:56:00.340338 6, 0xFFFF, sum = 0
5421 00:56:00.343105 7, 0xFFFF, sum = 0
5422 00:56:00.343546 8, 0xFFFF, sum = 0
5423 00:56:00.346308 9, 0xFFFF, sum = 0
5424 00:56:00.346813 10, 0x0, sum = 1
5425 00:56:00.349737 11, 0x0, sum = 2
5426 00:56:00.350156 12, 0x0, sum = 3
5427 00:56:00.353300 13, 0x0, sum = 4
5428 00:56:00.353866 best_step = 11
5429 00:56:00.354209
5430 00:56:00.354553 ==
5431 00:56:00.356044 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 00:56:00.359789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 00:56:00.360267 ==
5434 00:56:00.362683 RX Vref Scan: 0
5435 00:56:00.363101
5436 00:56:00.366039 RX Vref 0 -> 0, step: 1
5437 00:56:00.366456
5438 00:56:00.369499 RX Delay -61 -> 252, step: 4
5439 00:56:00.372188 iDelay=195, Bit 0, Center 100 (15 ~ 186) 172
5440 00:56:00.375716 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5441 00:56:00.382343 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5442 00:56:00.385549 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5443 00:56:00.389156 iDelay=195, Bit 4, Center 104 (19 ~ 190) 172
5444 00:56:00.392556 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5445 00:56:00.395692 iDelay=195, Bit 6, Center 112 (31 ~ 194) 164
5446 00:56:00.398597 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5447 00:56:00.405452 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5448 00:56:00.408759 iDelay=195, Bit 9, Center 78 (-9 ~ 166) 176
5449 00:56:00.411870 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5450 00:56:00.415735 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5451 00:56:00.418445 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5452 00:56:00.425373 iDelay=195, Bit 13, Center 96 (11 ~ 182) 172
5453 00:56:00.428594 iDelay=195, Bit 14, Center 104 (19 ~ 190) 172
5454 00:56:00.431467 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5455 00:56:00.431943 ==
5456 00:56:00.434957 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 00:56:00.438134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 00:56:00.441685 ==
5459 00:56:00.442115 DQS Delay:
5460 00:56:00.442529 DQS0 = 0, DQS1 = 0
5461 00:56:00.444769 DQM Delay:
5462 00:56:00.445326 DQM0 = 101, DQM1 = 90
5463 00:56:00.447836 DQ Delay:
5464 00:56:00.451283 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =98
5465 00:56:00.454802 DQ4 =104, DQ5 =92, DQ6 =112, DQ7 =108
5466 00:56:00.457767 DQ8 =82, DQ9 =78, DQ10 =92, DQ11 =82
5467 00:56:00.461165 DQ12 =96, DQ13 =96, DQ14 =104, DQ15 =96
5468 00:56:00.461611
5469 00:56:00.461940
5470 00:56:00.467481 [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5471 00:56:00.471041 CH0 RK1: MR19=505, MR18=1412
5472 00:56:00.477570 CH0_RK1: MR19=0x505, MR18=0x1412, DQSOSC=415, MR23=63, INC=62, DEC=41
5473 00:56:00.480871 [RxdqsGatingPostProcess] freq 933
5474 00:56:00.487464 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5475 00:56:00.487932 best DQS0 dly(2T, 0.5T) = (0, 10)
5476 00:56:00.491146 best DQS1 dly(2T, 0.5T) = (0, 11)
5477 00:56:00.494455 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5478 00:56:00.497100 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5479 00:56:00.500711 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 00:56:00.504173 best DQS1 dly(2T, 0.5T) = (0, 10)
5481 00:56:00.507384 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 00:56:00.510159 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5483 00:56:00.513450 Pre-setting of DQS Precalculation
5484 00:56:00.520293 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5485 00:56:00.520804 ==
5486 00:56:00.523697 Dram Type= 6, Freq= 0, CH_1, rank 0
5487 00:56:00.526699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 00:56:00.527137 ==
5489 00:56:00.533318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5490 00:56:00.536734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5491 00:56:00.540947 [CA 0] Center 36 (6~67) winsize 62
5492 00:56:00.544375 [CA 1] Center 36 (6~67) winsize 62
5493 00:56:00.547769 [CA 2] Center 34 (4~65) winsize 62
5494 00:56:00.551120 [CA 3] Center 33 (3~64) winsize 62
5495 00:56:00.553883 [CA 4] Center 34 (4~65) winsize 62
5496 00:56:00.557426 [CA 5] Center 33 (3~64) winsize 62
5497 00:56:00.557847
5498 00:56:00.560813 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5499 00:56:00.561314
5500 00:56:00.564188 [CATrainingPosCal] consider 1 rank data
5501 00:56:00.567889 u2DelayCellTimex100 = 270/100 ps
5502 00:56:00.570804 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5503 00:56:00.577123 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5504 00:56:00.580159 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 00:56:00.583500 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5506 00:56:00.586814 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5507 00:56:00.590314 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5508 00:56:00.590758
5509 00:56:00.593672 CA PerBit enable=1, Macro0, CA PI delay=33
5510 00:56:00.594177
5511 00:56:00.596564 [CBTSetCACLKResult] CA Dly = 33
5512 00:56:00.599899 CS Dly: 5 (0~36)
5513 00:56:00.600338 ==
5514 00:56:00.603602 Dram Type= 6, Freq= 0, CH_1, rank 1
5515 00:56:00.606749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 00:56:00.607199 ==
5517 00:56:00.613401 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5518 00:56:00.616973 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5519 00:56:00.621176 [CA 0] Center 36 (6~66) winsize 61
5520 00:56:00.623951 [CA 1] Center 36 (6~67) winsize 62
5521 00:56:00.627645 [CA 2] Center 34 (4~65) winsize 62
5522 00:56:00.631045 [CA 3] Center 33 (3~64) winsize 62
5523 00:56:00.633911 [CA 4] Center 34 (4~64) winsize 61
5524 00:56:00.637253 [CA 5] Center 33 (3~64) winsize 62
5525 00:56:00.637745
5526 00:56:00.640802 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5527 00:56:00.641241
5528 00:56:00.643915 [CATrainingPosCal] consider 2 rank data
5529 00:56:00.647383 u2DelayCellTimex100 = 270/100 ps
5530 00:56:00.651269 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5531 00:56:00.657135 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 00:56:00.660239 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5533 00:56:00.663603 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5534 00:56:00.667020 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5535 00:56:00.670264 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5536 00:56:00.670709
5537 00:56:00.673390 CA PerBit enable=1, Macro0, CA PI delay=33
5538 00:56:00.673857
5539 00:56:00.676698 [CBTSetCACLKResult] CA Dly = 33
5540 00:56:00.680213 CS Dly: 6 (0~38)
5541 00:56:00.680661
5542 00:56:00.683377 ----->DramcWriteLeveling(PI) begin...
5543 00:56:00.683820 ==
5544 00:56:00.686879 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 00:56:00.690145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 00:56:00.690579 ==
5547 00:56:00.693388 Write leveling (Byte 0): 27 => 27
5548 00:56:00.696699 Write leveling (Byte 1): 27 => 27
5549 00:56:00.700233 DramcWriteLeveling(PI) end<-----
5550 00:56:00.700656
5551 00:56:00.701002 ==
5552 00:56:00.703168 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 00:56:00.706325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 00:56:00.706747 ==
5555 00:56:00.710000 [Gating] SW mode calibration
5556 00:56:00.716313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5557 00:56:00.722835 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5558 00:56:00.726622 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5559 00:56:00.729864 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 00:56:00.735953 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 00:56:00.739521 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 00:56:00.742815 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 00:56:00.749179 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 00:56:00.752615 0 14 24 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 1)
5565 00:56:00.759473 0 14 28 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
5566 00:56:00.762202 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 00:56:00.765667 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 00:56:00.772306 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 00:56:00.775397 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 00:56:00.778662 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 00:56:00.785407 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 00:56:00.788574 0 15 24 | B1->B0 | 2525 2b2b | 0 0 | (1 1) (0 0)
5573 00:56:00.791834 0 15 28 | B1->B0 | 3b3b 4040 | 0 0 | (0 0) (0 0)
5574 00:56:00.798646 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 00:56:00.801808 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 00:56:00.805181 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 00:56:00.811604 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 00:56:00.814708 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 00:56:00.818094 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 00:56:00.825245 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5581 00:56:00.828083 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5582 00:56:00.831763 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 00:56:00.837889 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 00:56:00.841505 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 00:56:00.844624 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 00:56:00.851124 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 00:56:00.854455 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 00:56:00.857674 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 00:56:00.864246 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 00:56:00.867487 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 00:56:00.871104 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 00:56:00.877344 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 00:56:00.880792 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 00:56:00.884525 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 00:56:00.890641 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 00:56:00.893839 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5597 00:56:00.897131 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5598 00:56:00.900520 Total UI for P1: 0, mck2ui 16
5599 00:56:00.904247 best dqsien dly found for B0: ( 1, 2, 24)
5600 00:56:00.910741 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 00:56:00.911163 Total UI for P1: 0, mck2ui 16
5602 00:56:00.914030 best dqsien dly found for B1: ( 1, 2, 26)
5603 00:56:00.920517 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5604 00:56:00.923563 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5605 00:56:00.923982
5606 00:56:00.927061 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5607 00:56:00.930902 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5608 00:56:00.933393 [Gating] SW calibration Done
5609 00:56:00.933806 ==
5610 00:56:00.936546 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 00:56:00.940337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 00:56:00.940778 ==
5613 00:56:00.943356 RX Vref Scan: 0
5614 00:56:00.943769
5615 00:56:00.944132 RX Vref 0 -> 0, step: 1
5616 00:56:00.944449
5617 00:56:00.946763 RX Delay -80 -> 252, step: 8
5618 00:56:00.949821 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5619 00:56:00.957194 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5620 00:56:00.959771 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5621 00:56:00.962956 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5622 00:56:00.966247 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5623 00:56:00.969656 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5624 00:56:00.973341 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5625 00:56:00.979567 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5626 00:56:00.983300 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5627 00:56:00.986499 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5628 00:56:00.989456 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5629 00:56:00.993051 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5630 00:56:00.999511 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5631 00:56:01.002599 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5632 00:56:01.006023 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5633 00:56:01.009118 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5634 00:56:01.009575 ==
5635 00:56:01.012604 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 00:56:01.019589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 00:56:01.020009 ==
5638 00:56:01.020338 DQS Delay:
5639 00:56:01.020642 DQS0 = 0, DQS1 = 0
5640 00:56:01.022603 DQM Delay:
5641 00:56:01.023018 DQM0 = 99, DQM1 = 95
5642 00:56:01.025955 DQ Delay:
5643 00:56:01.029411 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5644 00:56:01.032379 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5645 00:56:01.035507 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5646 00:56:01.039231 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5647 00:56:01.039647
5648 00:56:01.039974
5649 00:56:01.040276 ==
5650 00:56:01.042539 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 00:56:01.046011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 00:56:01.046431 ==
5653 00:56:01.046761
5654 00:56:01.047066
5655 00:56:01.048845 TX Vref Scan disable
5656 00:56:01.051978 == TX Byte 0 ==
5657 00:56:01.055476 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5658 00:56:01.058956 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5659 00:56:01.062001 == TX Byte 1 ==
5660 00:56:01.065529 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5661 00:56:01.068625 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5662 00:56:01.069061 ==
5663 00:56:01.072023 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 00:56:01.078435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 00:56:01.078974 ==
5666 00:56:01.079459
5667 00:56:01.079796
5668 00:56:01.080172 TX Vref Scan disable
5669 00:56:01.082169 == TX Byte 0 ==
5670 00:56:01.085709 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5671 00:56:01.092114 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5672 00:56:01.092538 == TX Byte 1 ==
5673 00:56:01.095276 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5674 00:56:01.102018 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5675 00:56:01.102448
5676 00:56:01.102886 [DATLAT]
5677 00:56:01.103295 Freq=933, CH1 RK0
5678 00:56:01.103741
5679 00:56:01.105037 DATLAT Default: 0xd
5680 00:56:01.108337 0, 0xFFFF, sum = 0
5681 00:56:01.108777 1, 0xFFFF, sum = 0
5682 00:56:01.111990 2, 0xFFFF, sum = 0
5683 00:56:01.112422 3, 0xFFFF, sum = 0
5684 00:56:01.115174 4, 0xFFFF, sum = 0
5685 00:56:01.115607 5, 0xFFFF, sum = 0
5686 00:56:01.118403 6, 0xFFFF, sum = 0
5687 00:56:01.118839 7, 0xFFFF, sum = 0
5688 00:56:01.121715 8, 0xFFFF, sum = 0
5689 00:56:01.122151 9, 0xFFFF, sum = 0
5690 00:56:01.125143 10, 0x0, sum = 1
5691 00:56:01.125625 11, 0x0, sum = 2
5692 00:56:01.128397 12, 0x0, sum = 3
5693 00:56:01.128832 13, 0x0, sum = 4
5694 00:56:01.131604 best_step = 11
5695 00:56:01.132031
5696 00:56:01.132464 ==
5697 00:56:01.134937 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 00:56:01.137846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 00:56:01.138276 ==
5700 00:56:01.141198 RX Vref Scan: 1
5701 00:56:01.141657
5702 00:56:01.141982 RX Vref 0 -> 0, step: 1
5703 00:56:01.142289
5704 00:56:01.144370 RX Delay -53 -> 252, step: 4
5705 00:56:01.144798
5706 00:56:01.148535 Set Vref, RX VrefLevel [Byte0]: 52
5707 00:56:01.151235 [Byte1]: 50
5708 00:56:01.154925
5709 00:56:01.155443 Final RX Vref Byte 0 = 52 to rank0
5710 00:56:01.158044 Final RX Vref Byte 1 = 50 to rank0
5711 00:56:01.161568 Final RX Vref Byte 0 = 52 to rank1
5712 00:56:01.164754 Final RX Vref Byte 1 = 50 to rank1==
5713 00:56:01.168094 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 00:56:01.175026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 00:56:01.175460 ==
5716 00:56:01.175895 DQS Delay:
5717 00:56:01.177790 DQS0 = 0, DQS1 = 0
5718 00:56:01.178220 DQM Delay:
5719 00:56:01.178656 DQM0 = 98, DQM1 = 94
5720 00:56:01.181011 DQ Delay:
5721 00:56:01.184345 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =100
5722 00:56:01.188313 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5723 00:56:01.191395 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5724 00:56:01.194355 DQ12 =102, DQ13 =104, DQ14 =100, DQ15 =104
5725 00:56:01.194786
5726 00:56:01.195219
5727 00:56:01.201250 [DQSOSCAuto] RK0, (LSB)MR18= 0x818, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5728 00:56:01.204403 CH1 RK0: MR19=505, MR18=818
5729 00:56:01.210775 CH1_RK0: MR19=0x505, MR18=0x818, DQSOSC=414, MR23=63, INC=63, DEC=42
5730 00:56:01.211204
5731 00:56:01.214077 ----->DramcWriteLeveling(PI) begin...
5732 00:56:01.214561 ==
5733 00:56:01.217657 Dram Type= 6, Freq= 0, CH_1, rank 1
5734 00:56:01.221068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 00:56:01.221529 ==
5736 00:56:01.224047 Write leveling (Byte 0): 25 => 25
5737 00:56:01.227434 Write leveling (Byte 1): 27 => 27
5738 00:56:01.230748 DramcWriteLeveling(PI) end<-----
5739 00:56:01.231177
5740 00:56:01.231613 ==
5741 00:56:01.234564 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 00:56:01.240754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 00:56:01.241179 ==
5744 00:56:01.241629 [Gating] SW mode calibration
5745 00:56:01.251054 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5746 00:56:01.254072 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5747 00:56:01.257056 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5748 00:56:01.264286 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 00:56:01.267079 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 00:56:01.270366 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 00:56:01.277385 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 00:56:01.280385 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 00:56:01.283466 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5754 00:56:01.290274 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5755 00:56:01.293701 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5756 00:56:01.296735 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 00:56:01.303008 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 00:56:01.306589 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 00:56:01.313084 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 00:56:01.316397 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 00:56:01.319746 0 15 24 | B1->B0 | 2727 3636 | 0 1 | (0 0) (0 0)
5762 00:56:01.322931 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5763 00:56:01.329387 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 00:56:01.333084 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 00:56:01.336035 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 00:56:01.342636 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 00:56:01.346049 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 00:56:01.349383 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 00:56:01.355730 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5770 00:56:01.359041 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5771 00:56:01.365731 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 00:56:01.368858 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 00:56:01.372208 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 00:56:01.378716 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 00:56:01.381997 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 00:56:01.385438 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 00:56:01.391720 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 00:56:01.395649 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 00:56:01.398422 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 00:56:01.405101 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 00:56:01.408353 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 00:56:01.412090 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 00:56:01.418066 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 00:56:01.421606 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 00:56:01.424927 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 00:56:01.431792 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5787 00:56:01.435090 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 00:56:01.438312 Total UI for P1: 0, mck2ui 16
5789 00:56:01.441523 best dqsien dly found for B0: ( 1, 2, 28)
5790 00:56:01.444376 Total UI for P1: 0, mck2ui 16
5791 00:56:01.448000 best dqsien dly found for B1: ( 1, 2, 28)
5792 00:56:01.451410 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5793 00:56:01.454698 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5794 00:56:01.455116
5795 00:56:01.458189 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5796 00:56:01.461184 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5797 00:56:01.464489 [Gating] SW calibration Done
5798 00:56:01.464903 ==
5799 00:56:01.467696 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 00:56:01.471306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 00:56:01.474626 ==
5802 00:56:01.475056 RX Vref Scan: 0
5803 00:56:01.475390
5804 00:56:01.477914 RX Vref 0 -> 0, step: 1
5805 00:56:01.478330
5806 00:56:01.480902 RX Delay -80 -> 252, step: 8
5807 00:56:01.484405 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5808 00:56:01.487698 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5809 00:56:01.490990 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5810 00:56:01.493912 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5811 00:56:01.497011 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5812 00:56:01.504121 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5813 00:56:01.507827 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5814 00:56:01.510785 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5815 00:56:01.513950 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5816 00:56:01.516767 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5817 00:56:01.523372 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5818 00:56:01.526702 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5819 00:56:01.530237 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5820 00:56:01.533517 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5821 00:56:01.536963 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5822 00:56:01.543308 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5823 00:56:01.543725 ==
5824 00:56:01.546401 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 00:56:01.549688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 00:56:01.550152 ==
5827 00:56:01.550487 DQS Delay:
5828 00:56:01.552863 DQS0 = 0, DQS1 = 0
5829 00:56:01.553312 DQM Delay:
5830 00:56:01.556331 DQM0 = 97, DQM1 = 94
5831 00:56:01.556744 DQ Delay:
5832 00:56:01.559380 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5833 00:56:01.563081 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5834 00:56:01.566090 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5835 00:56:01.569838 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5836 00:56:01.570259
5837 00:56:01.570587
5838 00:56:01.570893 ==
5839 00:56:01.572926 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 00:56:01.579255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 00:56:01.579676 ==
5842 00:56:01.580006
5843 00:56:01.580325
5844 00:56:01.580666 TX Vref Scan disable
5845 00:56:01.582820 == TX Byte 0 ==
5846 00:56:01.586387 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5847 00:56:01.589226 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5848 00:56:01.592777 == TX Byte 1 ==
5849 00:56:01.595876 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5850 00:56:01.602774 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5851 00:56:01.603193 ==
5852 00:56:01.605754 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 00:56:01.609285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 00:56:01.609814 ==
5855 00:56:01.610148
5856 00:56:01.610455
5857 00:56:01.612924 TX Vref Scan disable
5858 00:56:01.613378 == TX Byte 0 ==
5859 00:56:01.619062 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5860 00:56:01.622557 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5861 00:56:01.622977 == TX Byte 1 ==
5862 00:56:01.629037 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5863 00:56:01.632259 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5864 00:56:01.632678
5865 00:56:01.633003 [DATLAT]
5866 00:56:01.635525 Freq=933, CH1 RK1
5867 00:56:01.635942
5868 00:56:01.636266 DATLAT Default: 0xb
5869 00:56:01.638681 0, 0xFFFF, sum = 0
5870 00:56:01.639102 1, 0xFFFF, sum = 0
5871 00:56:01.642335 2, 0xFFFF, sum = 0
5872 00:56:01.642756 3, 0xFFFF, sum = 0
5873 00:56:01.645841 4, 0xFFFF, sum = 0
5874 00:56:01.648884 5, 0xFFFF, sum = 0
5875 00:56:01.649326 6, 0xFFFF, sum = 0
5876 00:56:01.652284 7, 0xFFFF, sum = 0
5877 00:56:01.652703 8, 0xFFFF, sum = 0
5878 00:56:01.655233 9, 0xFFFF, sum = 0
5879 00:56:01.655654 10, 0x0, sum = 1
5880 00:56:01.658658 11, 0x0, sum = 2
5881 00:56:01.659084 12, 0x0, sum = 3
5882 00:56:01.662213 13, 0x0, sum = 4
5883 00:56:01.662637 best_step = 11
5884 00:56:01.662966
5885 00:56:01.663289 ==
5886 00:56:01.665130 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 00:56:01.668669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 00:56:01.669088 ==
5889 00:56:01.671687 RX Vref Scan: 0
5890 00:56:01.672101
5891 00:56:01.674967 RX Vref 0 -> 0, step: 1
5892 00:56:01.675383
5893 00:56:01.675713 RX Delay -53 -> 252, step: 4
5894 00:56:01.683077 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5895 00:56:01.686097 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5896 00:56:01.689871 iDelay=199, Bit 2, Center 88 (-1 ~ 178) 180
5897 00:56:01.693090 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5898 00:56:01.695885 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5899 00:56:01.702533 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5900 00:56:01.705613 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5901 00:56:01.708815 iDelay=199, Bit 7, Center 96 (3 ~ 190) 188
5902 00:56:01.712336 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5903 00:56:01.715490 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5904 00:56:01.722434 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5905 00:56:01.725869 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5906 00:56:01.728926 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5907 00:56:01.732205 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5908 00:56:01.735661 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5909 00:56:01.741794 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5910 00:56:01.742240 ==
5911 00:56:01.745384 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 00:56:01.748850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 00:56:01.749416 ==
5914 00:56:01.749769 DQS Delay:
5915 00:56:01.751815 DQS0 = 0, DQS1 = 0
5916 00:56:01.752504 DQM Delay:
5917 00:56:01.755437 DQM0 = 97, DQM1 = 92
5918 00:56:01.755856 DQ Delay:
5919 00:56:01.758386 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
5920 00:56:01.761423 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =96
5921 00:56:01.765153 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =84
5922 00:56:01.768161 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =100
5923 00:56:01.768713
5924 00:56:01.769054
5925 00:56:01.778023 [DQSOSCAuto] RK1, (LSB)MR18= 0xf27, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 417 ps
5926 00:56:01.778447 CH1 RK1: MR19=505, MR18=F27
5927 00:56:01.784718 CH1_RK1: MR19=0x505, MR18=0xF27, DQSOSC=409, MR23=63, INC=64, DEC=43
5928 00:56:01.787797 [RxdqsGatingPostProcess] freq 933
5929 00:56:01.794499 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5930 00:56:01.798099 best DQS0 dly(2T, 0.5T) = (0, 10)
5931 00:56:01.801645 best DQS1 dly(2T, 0.5T) = (0, 10)
5932 00:56:01.804413 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5933 00:56:01.807767 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5934 00:56:01.810885 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 00:56:01.814236 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 00:56:01.817922 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 00:56:01.821050 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 00:56:01.821524 Pre-setting of DQS Precalculation
5939 00:56:01.827597 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5940 00:56:01.834056 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5941 00:56:01.840636 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5942 00:56:01.841054
5943 00:56:01.841438
5944 00:56:01.844130 [Calibration Summary] 1866 Mbps
5945 00:56:01.847650 CH 0, Rank 0
5946 00:56:01.848216 SW Impedance : PASS
5947 00:56:01.850600 DUTY Scan : NO K
5948 00:56:01.854387 ZQ Calibration : PASS
5949 00:56:01.854839 Jitter Meter : NO K
5950 00:56:01.857284 CBT Training : PASS
5951 00:56:01.860361 Write leveling : PASS
5952 00:56:01.860913 RX DQS gating : PASS
5953 00:56:01.864030 RX DQ/DQS(RDDQC) : PASS
5954 00:56:01.867238 TX DQ/DQS : PASS
5955 00:56:01.867657 RX DATLAT : PASS
5956 00:56:01.870593 RX DQ/DQS(Engine): PASS
5957 00:56:01.873706 TX OE : NO K
5958 00:56:01.874123 All Pass.
5959 00:56:01.874455
5960 00:56:01.874760 CH 0, Rank 1
5961 00:56:01.876833 SW Impedance : PASS
5962 00:56:01.879993 DUTY Scan : NO K
5963 00:56:01.880487 ZQ Calibration : PASS
5964 00:56:01.883592 Jitter Meter : NO K
5965 00:56:01.884088 CBT Training : PASS
5966 00:56:01.887164 Write leveling : PASS
5967 00:56:01.889866 RX DQS gating : PASS
5968 00:56:01.890377 RX DQ/DQS(RDDQC) : PASS
5969 00:56:01.893723 TX DQ/DQS : PASS
5970 00:56:01.896569 RX DATLAT : PASS
5971 00:56:01.896981 RX DQ/DQS(Engine): PASS
5972 00:56:01.900312 TX OE : NO K
5973 00:56:01.900727 All Pass.
5974 00:56:01.901052
5975 00:56:01.903268 CH 1, Rank 0
5976 00:56:01.903763 SW Impedance : PASS
5977 00:56:01.906465 DUTY Scan : NO K
5978 00:56:01.909753 ZQ Calibration : PASS
5979 00:56:01.910235 Jitter Meter : NO K
5980 00:56:01.912959 CBT Training : PASS
5981 00:56:01.916764 Write leveling : PASS
5982 00:56:01.917222 RX DQS gating : PASS
5983 00:56:01.919635 RX DQ/DQS(RDDQC) : PASS
5984 00:56:01.922973 TX DQ/DQS : PASS
5985 00:56:01.923391 RX DATLAT : PASS
5986 00:56:01.926186 RX DQ/DQS(Engine): PASS
5987 00:56:01.929706 TX OE : NO K
5988 00:56:01.930121 All Pass.
5989 00:56:01.930483
5990 00:56:01.930791 CH 1, Rank 1
5991 00:56:01.932744 SW Impedance : PASS
5992 00:56:01.936256 DUTY Scan : NO K
5993 00:56:01.936673 ZQ Calibration : PASS
5994 00:56:01.939593 Jitter Meter : NO K
5995 00:56:01.942862 CBT Training : PASS
5996 00:56:01.943281 Write leveling : PASS
5997 00:56:01.946109 RX DQS gating : PASS
5998 00:56:01.949365 RX DQ/DQS(RDDQC) : PASS
5999 00:56:01.949779 TX DQ/DQS : PASS
6000 00:56:01.952535 RX DATLAT : PASS
6001 00:56:01.955876 RX DQ/DQS(Engine): PASS
6002 00:56:01.956292 TX OE : NO K
6003 00:56:01.956623 All Pass.
6004 00:56:01.959135
6005 00:56:01.959548 DramC Write-DBI off
6006 00:56:01.962513 PER_BANK_REFRESH: Hybrid Mode
6007 00:56:01.962940 TX_TRACKING: ON
6008 00:56:01.972598 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6009 00:56:01.975727 [FAST_K] Save calibration result to emmc
6010 00:56:01.979033 dramc_set_vcore_voltage set vcore to 650000
6011 00:56:01.982232 Read voltage for 400, 6
6012 00:56:01.982649 Vio18 = 0
6013 00:56:01.985794 Vcore = 650000
6014 00:56:01.986207 Vdram = 0
6015 00:56:01.986536 Vddq = 0
6016 00:56:01.986842 Vmddr = 0
6017 00:56:01.992357 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6018 00:56:01.998927 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6019 00:56:01.999361 MEM_TYPE=3, freq_sel=20
6020 00:56:02.001971 sv_algorithm_assistance_LP4_800
6021 00:56:02.005608 ============ PULL DRAM RESETB DOWN ============
6022 00:56:02.012149 ========== PULL DRAM RESETB DOWN end =========
6023 00:56:02.015224 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6024 00:56:02.018654 ===================================
6025 00:56:02.021838 LPDDR4 DRAM CONFIGURATION
6026 00:56:02.025530 ===================================
6027 00:56:02.026015 EX_ROW_EN[0] = 0x0
6028 00:56:02.028449 EX_ROW_EN[1] = 0x0
6029 00:56:02.031872 LP4Y_EN = 0x0
6030 00:56:02.032432 WORK_FSP = 0x0
6031 00:56:02.035249 WL = 0x2
6032 00:56:02.035611 RL = 0x2
6033 00:56:02.038361 BL = 0x2
6034 00:56:02.038750 RPST = 0x0
6035 00:56:02.041795 RD_PRE = 0x0
6036 00:56:02.042352 WR_PRE = 0x1
6037 00:56:02.045159 WR_PST = 0x0
6038 00:56:02.045810 DBI_WR = 0x0
6039 00:56:02.048512 DBI_RD = 0x0
6040 00:56:02.048995 OTF = 0x1
6041 00:56:02.051835 ===================================
6042 00:56:02.054848 ===================================
6043 00:56:02.058029 ANA top config
6044 00:56:02.061849 ===================================
6045 00:56:02.062354 DLL_ASYNC_EN = 0
6046 00:56:02.064765 ALL_SLAVE_EN = 1
6047 00:56:02.068336 NEW_RANK_MODE = 1
6048 00:56:02.071581 DLL_IDLE_MODE = 1
6049 00:56:02.074775 LP45_APHY_COMB_EN = 1
6050 00:56:02.075386 TX_ODT_DIS = 1
6051 00:56:02.078108 NEW_8X_MODE = 1
6052 00:56:02.081338 ===================================
6053 00:56:02.084755 ===================================
6054 00:56:02.088265 data_rate = 800
6055 00:56:02.091216 CKR = 1
6056 00:56:02.095428 DQ_P2S_RATIO = 4
6057 00:56:02.097698 ===================================
6058 00:56:02.101124 CA_P2S_RATIO = 4
6059 00:56:02.101638 DQ_CA_OPEN = 0
6060 00:56:02.105179 DQ_SEMI_OPEN = 1
6061 00:56:02.107889 CA_SEMI_OPEN = 1
6062 00:56:02.111090 CA_FULL_RATE = 0
6063 00:56:02.114728 DQ_CKDIV4_EN = 0
6064 00:56:02.117655 CA_CKDIV4_EN = 1
6065 00:56:02.118134 CA_PREDIV_EN = 0
6066 00:56:02.120966 PH8_DLY = 0
6067 00:56:02.124212 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6068 00:56:02.127732 DQ_AAMCK_DIV = 0
6069 00:56:02.131073 CA_AAMCK_DIV = 0
6070 00:56:02.134195 CA_ADMCK_DIV = 4
6071 00:56:02.134617 DQ_TRACK_CA_EN = 0
6072 00:56:02.137556 CA_PICK = 800
6073 00:56:02.140615 CA_MCKIO = 400
6074 00:56:02.143937 MCKIO_SEMI = 400
6075 00:56:02.146853 PLL_FREQ = 3016
6076 00:56:02.150504 DQ_UI_PI_RATIO = 32
6077 00:56:02.153682 CA_UI_PI_RATIO = 32
6078 00:56:02.156930 ===================================
6079 00:56:02.160474 ===================================
6080 00:56:02.160894 memory_type:LPDDR4
6081 00:56:02.163715 GP_NUM : 10
6082 00:56:02.167116 SRAM_EN : 1
6083 00:56:02.167534 MD32_EN : 0
6084 00:56:02.170417 ===================================
6085 00:56:02.173610 [ANA_INIT] >>>>>>>>>>>>>>
6086 00:56:02.177045 <<<<<< [CONFIGURE PHASE]: ANA_TX
6087 00:56:02.180406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6088 00:56:02.183282 ===================================
6089 00:56:02.186877 data_rate = 800,PCW = 0X7400
6090 00:56:02.189759 ===================================
6091 00:56:02.192991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6092 00:56:02.199780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6093 00:56:02.209804 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 00:56:02.213577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6095 00:56:02.216897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6096 00:56:02.219638 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6097 00:56:02.223328 [ANA_INIT] flow start
6098 00:56:02.226327 [ANA_INIT] PLL >>>>>>>>
6099 00:56:02.226745 [ANA_INIT] PLL <<<<<<<<
6100 00:56:02.229639 [ANA_INIT] MIDPI >>>>>>>>
6101 00:56:02.233085 [ANA_INIT] MIDPI <<<<<<<<
6102 00:56:02.236350 [ANA_INIT] DLL >>>>>>>>
6103 00:56:02.236769 [ANA_INIT] flow end
6104 00:56:02.239159 ============ LP4 DIFF to SE enter ============
6105 00:56:02.246151 ============ LP4 DIFF to SE exit ============
6106 00:56:02.246586 [ANA_INIT] <<<<<<<<<<<<<
6107 00:56:02.249066 [Flow] Enable top DCM control >>>>>
6108 00:56:02.252625 [Flow] Enable top DCM control <<<<<
6109 00:56:02.256154 Enable DLL master slave shuffle
6110 00:56:02.262230 ==============================================================
6111 00:56:02.262654 Gating Mode config
6112 00:56:02.269373 ==============================================================
6113 00:56:02.272235 Config description:
6114 00:56:02.281976 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6115 00:56:02.288668 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6116 00:56:02.292095 SELPH_MODE 0: By rank 1: By Phase
6117 00:56:02.298972 ==============================================================
6118 00:56:02.302217 GAT_TRACK_EN = 0
6119 00:56:02.305380 RX_GATING_MODE = 2
6120 00:56:02.308351 RX_GATING_TRACK_MODE = 2
6121 00:56:02.311717 SELPH_MODE = 1
6122 00:56:02.312255 PICG_EARLY_EN = 1
6123 00:56:02.315126 VALID_LAT_VALUE = 1
6124 00:56:02.321714 ==============================================================
6125 00:56:02.325825 Enter into Gating configuration >>>>
6126 00:56:02.328176 Exit from Gating configuration <<<<
6127 00:56:02.331574 Enter into DVFS_PRE_config >>>>>
6128 00:56:02.341424 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6129 00:56:02.344962 Exit from DVFS_PRE_config <<<<<
6130 00:56:02.348072 Enter into PICG configuration >>>>
6131 00:56:02.351258 Exit from PICG configuration <<<<
6132 00:56:02.354673 [RX_INPUT] configuration >>>>>
6133 00:56:02.357849 [RX_INPUT] configuration <<<<<
6134 00:56:02.364713 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6135 00:56:02.367473 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6136 00:56:02.373948 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 00:56:02.380569 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 00:56:02.387322 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 00:56:02.393549 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 00:56:02.396941 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6141 00:56:02.400246 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6142 00:56:02.403437 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6143 00:56:02.410024 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6144 00:56:02.413227 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6145 00:56:02.416987 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6146 00:56:02.420024 ===================================
6147 00:56:02.423615 LPDDR4 DRAM CONFIGURATION
6148 00:56:02.426788 ===================================
6149 00:56:02.429863 EX_ROW_EN[0] = 0x0
6150 00:56:02.430255 EX_ROW_EN[1] = 0x0
6151 00:56:02.433303 LP4Y_EN = 0x0
6152 00:56:02.433678 WORK_FSP = 0x0
6153 00:56:02.436669 WL = 0x2
6154 00:56:02.437033 RL = 0x2
6155 00:56:02.439778 BL = 0x2
6156 00:56:02.440205 RPST = 0x0
6157 00:56:02.443286 RD_PRE = 0x0
6158 00:56:02.443684 WR_PRE = 0x1
6159 00:56:02.446372 WR_PST = 0x0
6160 00:56:02.446796 DBI_WR = 0x0
6161 00:56:02.449813 DBI_RD = 0x0
6162 00:56:02.450298 OTF = 0x1
6163 00:56:02.453212 ===================================
6164 00:56:02.459727 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6165 00:56:02.462927 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6166 00:56:02.466520 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6167 00:56:02.469638 ===================================
6168 00:56:02.472996 LPDDR4 DRAM CONFIGURATION
6169 00:56:02.476195 ===================================
6170 00:56:02.479300 EX_ROW_EN[0] = 0x10
6171 00:56:02.479721 EX_ROW_EN[1] = 0x0
6172 00:56:02.482495 LP4Y_EN = 0x0
6173 00:56:02.482915 WORK_FSP = 0x0
6174 00:56:02.485996 WL = 0x2
6175 00:56:02.486418 RL = 0x2
6176 00:56:02.489596 BL = 0x2
6177 00:56:02.490015 RPST = 0x0
6178 00:56:02.492364 RD_PRE = 0x0
6179 00:56:02.492782 WR_PRE = 0x1
6180 00:56:02.496295 WR_PST = 0x0
6181 00:56:02.496719 DBI_WR = 0x0
6182 00:56:02.499610 DBI_RD = 0x0
6183 00:56:02.500028 OTF = 0x1
6184 00:56:02.502785 ===================================
6185 00:56:02.508879 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6186 00:56:02.514260 nWR fixed to 30
6187 00:56:02.518166 [ModeRegInit_LP4] CH0 RK0
6188 00:56:02.518583 [ModeRegInit_LP4] CH0 RK1
6189 00:56:02.521155 [ModeRegInit_LP4] CH1 RK0
6190 00:56:02.523844 [ModeRegInit_LP4] CH1 RK1
6191 00:56:02.524373 match AC timing 19
6192 00:56:02.530402 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6193 00:56:02.534165 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6194 00:56:02.537344 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6195 00:56:02.543838 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6196 00:56:02.547027 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6197 00:56:02.547448 ==
6198 00:56:02.550310 Dram Type= 6, Freq= 0, CH_0, rank 0
6199 00:56:02.553517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6200 00:56:02.553944 ==
6201 00:56:02.560380 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6202 00:56:02.566780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6203 00:56:02.570479 [CA 0] Center 36 (8~64) winsize 57
6204 00:56:02.573334 [CA 1] Center 36 (8~64) winsize 57
6205 00:56:02.576789 [CA 2] Center 36 (8~64) winsize 57
6206 00:56:02.579918 [CA 3] Center 36 (8~64) winsize 57
6207 00:56:02.583148 [CA 4] Center 36 (8~64) winsize 57
6208 00:56:02.586409 [CA 5] Center 36 (8~64) winsize 57
6209 00:56:02.586902
6210 00:56:02.589758 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6211 00:56:02.590178
6212 00:56:02.592995 [CATrainingPosCal] consider 1 rank data
6213 00:56:02.596519 u2DelayCellTimex100 = 270/100 ps
6214 00:56:02.600028 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 00:56:02.603208 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 00:56:02.606363 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 00:56:02.609782 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 00:56:02.612962 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 00:56:02.616688 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 00:56:02.617109
6221 00:56:02.619522 CA PerBit enable=1, Macro0, CA PI delay=36
6222 00:56:02.623114
6223 00:56:02.623530 [CBTSetCACLKResult] CA Dly = 36
6224 00:56:02.626064 CS Dly: 1 (0~32)
6225 00:56:02.626482 ==
6226 00:56:02.629320 Dram Type= 6, Freq= 0, CH_0, rank 1
6227 00:56:02.632843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 00:56:02.633300 ==
6229 00:56:02.639433 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 00:56:02.646253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6231 00:56:02.649190 [CA 0] Center 36 (8~64) winsize 57
6232 00:56:02.652537 [CA 1] Center 36 (8~64) winsize 57
6233 00:56:02.656483 [CA 2] Center 36 (8~64) winsize 57
6234 00:56:02.658938 [CA 3] Center 36 (8~64) winsize 57
6235 00:56:02.659358 [CA 4] Center 36 (8~64) winsize 57
6236 00:56:02.662569 [CA 5] Center 36 (8~64) winsize 57
6237 00:56:02.662988
6238 00:56:02.669161 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6239 00:56:02.669642
6240 00:56:02.672268 [CATrainingPosCal] consider 2 rank data
6241 00:56:02.675356 u2DelayCellTimex100 = 270/100 ps
6242 00:56:02.678868 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 00:56:02.682032 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 00:56:02.685416 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 00:56:02.688848 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 00:56:02.691988 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 00:56:02.695229 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 00:56:02.695711
6249 00:56:02.698373 CA PerBit enable=1, Macro0, CA PI delay=36
6250 00:56:02.698830
6251 00:56:02.701638 [CBTSetCACLKResult] CA Dly = 36
6252 00:56:02.705080 CS Dly: 1 (0~32)
6253 00:56:02.705617
6254 00:56:02.708442 ----->DramcWriteLeveling(PI) begin...
6255 00:56:02.708867 ==
6256 00:56:02.712042 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 00:56:02.715095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 00:56:02.715520 ==
6259 00:56:02.718030 Write leveling (Byte 0): 40 => 8
6260 00:56:02.721680 Write leveling (Byte 1): 40 => 8
6261 00:56:02.724675 DramcWriteLeveling(PI) end<-----
6262 00:56:02.725095
6263 00:56:02.725495 ==
6264 00:56:02.728081 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 00:56:02.731472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 00:56:02.731896 ==
6267 00:56:02.734632 [Gating] SW mode calibration
6268 00:56:02.741379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6269 00:56:02.748153 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6270 00:56:02.751251 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 00:56:02.758022 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 00:56:02.761359 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 00:56:02.764324 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 00:56:02.771743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 00:56:02.774555 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 00:56:02.777362 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 00:56:02.784350 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 00:56:02.788092 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 00:56:02.790527 Total UI for P1: 0, mck2ui 16
6280 00:56:02.793807 best dqsien dly found for B0: ( 0, 14, 24)
6281 00:56:02.797661 Total UI for P1: 0, mck2ui 16
6282 00:56:02.800589 best dqsien dly found for B1: ( 0, 14, 24)
6283 00:56:02.803741 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6284 00:56:02.807268 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6285 00:56:02.807747
6286 00:56:02.810480 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6287 00:56:02.813979 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 00:56:02.817334 [Gating] SW calibration Done
6289 00:56:02.817771 ==
6290 00:56:02.820423 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 00:56:02.826857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 00:56:02.827280 ==
6293 00:56:02.827615 RX Vref Scan: 0
6294 00:56:02.827924
6295 00:56:02.830613 RX Vref 0 -> 0, step: 1
6296 00:56:02.831029
6297 00:56:02.833524 RX Delay -410 -> 252, step: 16
6298 00:56:02.836859 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6299 00:56:02.840109 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6300 00:56:02.846789 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6301 00:56:02.850145 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6302 00:56:02.853531 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6303 00:56:02.856830 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6304 00:56:02.863099 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6305 00:56:02.866233 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6306 00:56:02.869777 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6307 00:56:02.872942 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6308 00:56:02.879710 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6309 00:56:02.882497 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6310 00:56:02.886088 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6311 00:56:02.892567 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6312 00:56:02.895870 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6313 00:56:02.898936 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6314 00:56:02.899010 ==
6315 00:56:02.902584 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 00:56:02.905594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 00:56:02.908871 ==
6318 00:56:02.908980 DQS Delay:
6319 00:56:02.909071 DQS0 = 43, DQS1 = 59
6320 00:56:02.911915 DQM Delay:
6321 00:56:02.911986 DQM0 = 11, DQM1 = 16
6322 00:56:02.915123 DQ Delay:
6323 00:56:02.915237 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6324 00:56:02.918715 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6325 00:56:02.922033 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6326 00:56:02.925280 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6327 00:56:02.925367
6328 00:56:02.925427
6329 00:56:02.925484 ==
6330 00:56:02.928726 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 00:56:02.935249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 00:56:02.935326 ==
6333 00:56:02.935388
6334 00:56:02.935451
6335 00:56:02.938223 TX Vref Scan disable
6336 00:56:02.938313 == TX Byte 0 ==
6337 00:56:02.941714 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 00:56:02.948469 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 00:56:02.948559 == TX Byte 1 ==
6340 00:56:02.951499 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 00:56:02.958419 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 00:56:02.958504 ==
6343 00:56:02.961634 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 00:56:02.964634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 00:56:02.964722 ==
6346 00:56:02.964793
6347 00:56:02.964865
6348 00:56:02.968040 TX Vref Scan disable
6349 00:56:02.968132 == TX Byte 0 ==
6350 00:56:02.971180 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 00:56:02.978184 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 00:56:02.978283 == TX Byte 1 ==
6353 00:56:02.981496 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 00:56:02.988048 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 00:56:02.988184
6356 00:56:02.988290 [DATLAT]
6357 00:56:02.988389 Freq=400, CH0 RK0
6358 00:56:02.991466
6359 00:56:02.991623 DATLAT Default: 0xf
6360 00:56:02.994526 0, 0xFFFF, sum = 0
6361 00:56:02.994679 1, 0xFFFF, sum = 0
6362 00:56:02.997835 2, 0xFFFF, sum = 0
6363 00:56:02.998060 3, 0xFFFF, sum = 0
6364 00:56:03.000832 4, 0xFFFF, sum = 0
6365 00:56:03.000984 5, 0xFFFF, sum = 0
6366 00:56:03.004390 6, 0xFFFF, sum = 0
6367 00:56:03.004562 7, 0xFFFF, sum = 0
6368 00:56:03.007563 8, 0xFFFF, sum = 0
6369 00:56:03.007787 9, 0xFFFF, sum = 0
6370 00:56:03.011821 10, 0xFFFF, sum = 0
6371 00:56:03.012150 11, 0xFFFF, sum = 0
6372 00:56:03.014723 12, 0xFFFF, sum = 0
6373 00:56:03.015083 13, 0x0, sum = 1
6374 00:56:03.018038 14, 0x0, sum = 2
6375 00:56:03.018438 15, 0x0, sum = 3
6376 00:56:03.021370 16, 0x0, sum = 4
6377 00:56:03.021805 best_step = 14
6378 00:56:03.022192
6379 00:56:03.022493 ==
6380 00:56:03.024551 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 00:56:03.031149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 00:56:03.031602 ==
6383 00:56:03.031930 RX Vref Scan: 1
6384 00:56:03.032321
6385 00:56:03.034634 RX Vref 0 -> 0, step: 1
6386 00:56:03.035246
6387 00:56:03.037900 RX Delay -359 -> 252, step: 8
6388 00:56:03.038363
6389 00:56:03.041198 Set Vref, RX VrefLevel [Byte0]: 58
6390 00:56:03.044391 [Byte1]: 50
6391 00:56:03.047613
6392 00:56:03.048131 Final RX Vref Byte 0 = 58 to rank0
6393 00:56:03.051050 Final RX Vref Byte 1 = 50 to rank0
6394 00:56:03.054189 Final RX Vref Byte 0 = 58 to rank1
6395 00:56:03.057427 Final RX Vref Byte 1 = 50 to rank1==
6396 00:56:03.060437 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 00:56:03.067243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 00:56:03.067831 ==
6399 00:56:03.068275 DQS Delay:
6400 00:56:03.070930 DQS0 = 44, DQS1 = 56
6401 00:56:03.071520 DQM Delay:
6402 00:56:03.071946 DQM0 = 10, DQM1 = 14
6403 00:56:03.073580 DQ Delay:
6404 00:56:03.077337 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6405 00:56:03.080291 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6406 00:56:03.080812 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6407 00:56:03.087375 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6408 00:56:03.087787
6409 00:56:03.088138
6410 00:56:03.093445 [DQSOSCAuto] RK0, (LSB)MR18= 0x958a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6411 00:56:03.096910 CH0 RK0: MR19=C0C, MR18=958A
6412 00:56:03.103645 CH0_RK0: MR19=0xC0C, MR18=0x958A, DQSOSC=391, MR23=63, INC=386, DEC=257
6413 00:56:03.104096 ==
6414 00:56:03.106521 Dram Type= 6, Freq= 0, CH_0, rank 1
6415 00:56:03.110011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 00:56:03.110456 ==
6417 00:56:03.112920 [Gating] SW mode calibration
6418 00:56:03.120097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6419 00:56:03.126341 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6420 00:56:03.129508 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 00:56:03.133162 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 00:56:03.139428 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 00:56:03.142831 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 00:56:03.149372 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 00:56:03.152507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 00:56:03.155651 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 00:56:03.162749 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 00:56:03.165826 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 00:56:03.169230 Total UI for P1: 0, mck2ui 16
6430 00:56:03.172469 best dqsien dly found for B0: ( 0, 14, 24)
6431 00:56:03.175547 Total UI for P1: 0, mck2ui 16
6432 00:56:03.179070 best dqsien dly found for B1: ( 0, 14, 24)
6433 00:56:03.182256 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6434 00:56:03.185788 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6435 00:56:03.186256
6436 00:56:03.189102 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6437 00:56:03.192383 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 00:56:03.195607 [Gating] SW calibration Done
6439 00:56:03.196019 ==
6440 00:56:03.198818 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 00:56:03.201978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 00:56:03.205420 ==
6443 00:56:03.206019 RX Vref Scan: 0
6444 00:56:03.206633
6445 00:56:03.208849 RX Vref 0 -> 0, step: 1
6446 00:56:03.209465
6447 00:56:03.211728 RX Delay -410 -> 252, step: 16
6448 00:56:03.215548 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6449 00:56:03.218389 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6450 00:56:03.221900 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6451 00:56:03.228314 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6452 00:56:03.232062 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6453 00:56:03.235094 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6454 00:56:03.238648 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6455 00:56:03.244795 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6456 00:56:03.248112 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6457 00:56:03.251767 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6458 00:56:03.254603 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6459 00:56:03.261477 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6460 00:56:03.264860 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6461 00:56:03.267971 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6462 00:56:03.274277 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6463 00:56:03.277844 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6464 00:56:03.278260 ==
6465 00:56:03.281209 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 00:56:03.284715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 00:56:03.285132 ==
6468 00:56:03.287672 DQS Delay:
6469 00:56:03.288080 DQS0 = 35, DQS1 = 59
6470 00:56:03.290936 DQM Delay:
6471 00:56:03.291346 DQM0 = 6, DQM1 = 17
6472 00:56:03.291672 DQ Delay:
6473 00:56:03.294494 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6474 00:56:03.297298 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6475 00:56:03.301026 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6476 00:56:03.304112 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6477 00:56:03.304527
6478 00:56:03.304849
6479 00:56:03.305146 ==
6480 00:56:03.307813 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 00:56:03.313912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 00:56:03.314326 ==
6483 00:56:03.314651
6484 00:56:03.314948
6485 00:56:03.315237 TX Vref Scan disable
6486 00:56:03.317528 == TX Byte 0 ==
6487 00:56:03.320395 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6488 00:56:03.324232 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6489 00:56:03.327551 == TX Byte 1 ==
6490 00:56:03.330817 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6491 00:56:03.333791 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6492 00:56:03.334223 ==
6493 00:56:03.336938 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 00:56:03.344048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 00:56:03.344562 ==
6496 00:56:03.345003
6497 00:56:03.345513
6498 00:56:03.345915 TX Vref Scan disable
6499 00:56:03.347245 == TX Byte 0 ==
6500 00:56:03.350393 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6501 00:56:03.353827 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6502 00:56:03.357195 == TX Byte 1 ==
6503 00:56:03.360179 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6504 00:56:03.363763 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6505 00:56:03.364193
6506 00:56:03.366577 [DATLAT]
6507 00:56:03.367001 Freq=400, CH0 RK1
6508 00:56:03.367431
6509 00:56:03.370491 DATLAT Default: 0xe
6510 00:56:03.371034 0, 0xFFFF, sum = 0
6511 00:56:03.373106 1, 0xFFFF, sum = 0
6512 00:56:03.373592 2, 0xFFFF, sum = 0
6513 00:56:03.376333 3, 0xFFFF, sum = 0
6514 00:56:03.376873 4, 0xFFFF, sum = 0
6515 00:56:03.380097 5, 0xFFFF, sum = 0
6516 00:56:03.380523 6, 0xFFFF, sum = 0
6517 00:56:03.383446 7, 0xFFFF, sum = 0
6518 00:56:03.386763 8, 0xFFFF, sum = 0
6519 00:56:03.387190 9, 0xFFFF, sum = 0
6520 00:56:03.389811 10, 0xFFFF, sum = 0
6521 00:56:03.390237 11, 0xFFFF, sum = 0
6522 00:56:03.393095 12, 0xFFFF, sum = 0
6523 00:56:03.393666 13, 0x0, sum = 1
6524 00:56:03.396206 14, 0x0, sum = 2
6525 00:56:03.396630 15, 0x0, sum = 3
6526 00:56:03.399728 16, 0x0, sum = 4
6527 00:56:03.400211 best_step = 14
6528 00:56:03.400550
6529 00:56:03.400859 ==
6530 00:56:03.403242 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 00:56:03.406161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 00:56:03.406612 ==
6533 00:56:03.409442 RX Vref Scan: 0
6534 00:56:03.409860
6535 00:56:03.412893 RX Vref 0 -> 0, step: 1
6536 00:56:03.413338
6537 00:56:03.416173 RX Delay -359 -> 252, step: 8
6538 00:56:03.422924 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6539 00:56:03.425783 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6540 00:56:03.429073 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6541 00:56:03.432804 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6542 00:56:03.439166 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6543 00:56:03.442132 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6544 00:56:03.445766 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6545 00:56:03.449125 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6546 00:56:03.455378 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6547 00:56:03.459004 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6548 00:56:03.462717 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6549 00:56:03.465491 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6550 00:56:03.472628 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6551 00:56:03.475241 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6552 00:56:03.478490 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6553 00:56:03.481826 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6554 00:56:03.485127 ==
6555 00:56:03.488639 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 00:56:03.491813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 00:56:03.492238 ==
6558 00:56:03.492570 DQS Delay:
6559 00:56:03.495408 DQS0 = 44, DQS1 = 60
6560 00:56:03.495838 DQM Delay:
6561 00:56:03.498499 DQM0 = 9, DQM1 = 15
6562 00:56:03.499009 DQ Delay:
6563 00:56:03.501900 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6564 00:56:03.504933 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6565 00:56:03.508574 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6566 00:56:03.511497 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6567 00:56:03.511924
6568 00:56:03.512354
6569 00:56:03.518035 [DQSOSCAuto] RK1, (LSB)MR18= 0x8a84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6570 00:56:03.521227 CH0 RK1: MR19=C0C, MR18=8A84
6571 00:56:03.528067 CH0_RK1: MR19=0xC0C, MR18=0x8A84, DQSOSC=392, MR23=63, INC=384, DEC=256
6572 00:56:03.531228 [RxdqsGatingPostProcess] freq 400
6573 00:56:03.538229 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6574 00:56:03.538744 best DQS0 dly(2T, 0.5T) = (0, 10)
6575 00:56:03.541547 best DQS1 dly(2T, 0.5T) = (0, 10)
6576 00:56:03.544753 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6577 00:56:03.547521 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6578 00:56:03.551009 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 00:56:03.554369 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 00:56:03.557789 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 00:56:03.561122 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 00:56:03.564498 Pre-setting of DQS Precalculation
6583 00:56:03.570670 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6584 00:56:03.571106 ==
6585 00:56:03.574179 Dram Type= 6, Freq= 0, CH_1, rank 0
6586 00:56:03.577507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 00:56:03.577933 ==
6588 00:56:03.584155 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6589 00:56:03.587277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6590 00:56:03.590564 [CA 0] Center 36 (8~64) winsize 57
6591 00:56:03.594230 [CA 1] Center 36 (8~64) winsize 57
6592 00:56:03.597737 [CA 2] Center 36 (8~64) winsize 57
6593 00:56:03.600352 [CA 3] Center 36 (8~64) winsize 57
6594 00:56:03.603874 [CA 4] Center 36 (8~64) winsize 57
6595 00:56:03.606980 [CA 5] Center 36 (8~64) winsize 57
6596 00:56:03.607484
6597 00:56:03.610635 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6598 00:56:03.611132
6599 00:56:03.613534 [CATrainingPosCal] consider 1 rank data
6600 00:56:03.616847 u2DelayCellTimex100 = 270/100 ps
6601 00:56:03.620140 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 00:56:03.626674 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 00:56:03.629962 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 00:56:03.633886 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 00:56:03.636860 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 00:56:03.639910 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 00:56:03.640387
6608 00:56:03.643562 CA PerBit enable=1, Macro0, CA PI delay=36
6609 00:56:03.644091
6610 00:56:03.646640 [CBTSetCACLKResult] CA Dly = 36
6611 00:56:03.649652 CS Dly: 1 (0~32)
6612 00:56:03.650117 ==
6613 00:56:03.653249 Dram Type= 6, Freq= 0, CH_1, rank 1
6614 00:56:03.656301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 00:56:03.656726 ==
6616 00:56:03.663479 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 00:56:03.666107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6618 00:56:03.669673 [CA 0] Center 36 (8~64) winsize 57
6619 00:56:03.672978 [CA 1] Center 36 (8~64) winsize 57
6620 00:56:03.675897 [CA 2] Center 36 (8~64) winsize 57
6621 00:56:03.679280 [CA 3] Center 36 (8~64) winsize 57
6622 00:56:03.682842 [CA 4] Center 36 (8~64) winsize 57
6623 00:56:03.685701 [CA 5] Center 36 (8~64) winsize 57
6624 00:56:03.686122
6625 00:56:03.689900 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6626 00:56:03.690321
6627 00:56:03.692609 [CATrainingPosCal] consider 2 rank data
6628 00:56:03.695733 u2DelayCellTimex100 = 270/100 ps
6629 00:56:03.699363 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 00:56:03.702675 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 00:56:03.709048 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 00:56:03.712260 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 00:56:03.715659 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 00:56:03.719094 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 00:56:03.719516
6636 00:56:03.722188 CA PerBit enable=1, Macro0, CA PI delay=36
6637 00:56:03.722613
6638 00:56:03.725482 [CBTSetCACLKResult] CA Dly = 36
6639 00:56:03.725904 CS Dly: 1 (0~32)
6640 00:56:03.729028
6641 00:56:03.732304 ----->DramcWriteLeveling(PI) begin...
6642 00:56:03.732732 ==
6643 00:56:03.735280 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 00:56:03.738957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 00:56:03.739382 ==
6646 00:56:03.741717 Write leveling (Byte 0): 40 => 8
6647 00:56:03.745618 Write leveling (Byte 1): 40 => 8
6648 00:56:03.748711 DramcWriteLeveling(PI) end<-----
6649 00:56:03.749133
6650 00:56:03.749604 ==
6651 00:56:03.751660 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 00:56:03.755135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 00:56:03.755560 ==
6654 00:56:03.758312 [Gating] SW mode calibration
6655 00:56:03.765193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6656 00:56:03.772076 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6657 00:56:03.774864 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 00:56:03.778230 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 00:56:03.784893 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 00:56:03.788375 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 00:56:03.791107 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 00:56:03.797975 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 00:56:03.801461 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 00:56:03.804922 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 00:56:03.810973 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 00:56:03.811409 Total UI for P1: 0, mck2ui 16
6667 00:56:03.817593 best dqsien dly found for B0: ( 0, 14, 24)
6668 00:56:03.818015 Total UI for P1: 0, mck2ui 16
6669 00:56:03.824298 best dqsien dly found for B1: ( 0, 14, 24)
6670 00:56:03.827633 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6671 00:56:03.830865 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6672 00:56:03.831286
6673 00:56:03.833973 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6674 00:56:03.837828 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 00:56:03.840816 [Gating] SW calibration Done
6676 00:56:03.841235 ==
6677 00:56:03.843777 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 00:56:03.847118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 00:56:03.847542 ==
6680 00:56:03.850619 RX Vref Scan: 0
6681 00:56:03.851040
6682 00:56:03.853940 RX Vref 0 -> 0, step: 1
6683 00:56:03.854359
6684 00:56:03.854691 RX Delay -410 -> 252, step: 16
6685 00:56:03.860454 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6686 00:56:03.863827 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6687 00:56:03.866888 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6688 00:56:03.873783 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6689 00:56:03.876886 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6690 00:56:03.880600 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6691 00:56:03.883880 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6692 00:56:03.890478 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6693 00:56:03.893511 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6694 00:56:03.896813 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6695 00:56:03.899943 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6696 00:56:03.906812 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6697 00:56:03.909743 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6698 00:56:03.913320 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6699 00:56:03.916699 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6700 00:56:03.923574 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6701 00:56:03.923994 ==
6702 00:56:03.926447 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 00:56:03.929951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 00:56:03.930377 ==
6705 00:56:03.930711 DQS Delay:
6706 00:56:03.933156 DQS0 = 35, DQS1 = 51
6707 00:56:03.933633 DQM Delay:
6708 00:56:03.936426 DQM0 = 6, DQM1 = 13
6709 00:56:03.936845 DQ Delay:
6710 00:56:03.939824 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6711 00:56:03.943039 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6712 00:56:03.946101 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6713 00:56:03.949445 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6714 00:56:03.949972
6715 00:56:03.950312
6716 00:56:03.950680 ==
6717 00:56:03.952456 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 00:56:03.955995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 00:56:03.956439 ==
6720 00:56:03.959513
6721 00:56:03.959966
6722 00:56:03.960301 TX Vref Scan disable
6723 00:56:03.962398 == TX Byte 0 ==
6724 00:56:03.966008 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 00:56:03.968971 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 00:56:03.972523 == TX Byte 1 ==
6727 00:56:03.975617 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 00:56:03.978907 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 00:56:03.979328 ==
6730 00:56:03.982081 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 00:56:03.988676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 00:56:03.989099 ==
6733 00:56:03.989482
6734 00:56:03.989870
6735 00:56:03.990185 TX Vref Scan disable
6736 00:56:03.992821 == TX Byte 0 ==
6737 00:56:03.995418 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 00:56:03.998975 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 00:56:04.002286 == TX Byte 1 ==
6740 00:56:04.005883 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 00:56:04.008491 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 00:56:04.008914
6743 00:56:04.012056 [DATLAT]
6744 00:56:04.012471 Freq=400, CH1 RK0
6745 00:56:04.012801
6746 00:56:04.015492 DATLAT Default: 0xf
6747 00:56:04.015909 0, 0xFFFF, sum = 0
6748 00:56:04.018235 1, 0xFFFF, sum = 0
6749 00:56:04.018761 2, 0xFFFF, sum = 0
6750 00:56:04.022247 3, 0xFFFF, sum = 0
6751 00:56:04.022702 4, 0xFFFF, sum = 0
6752 00:56:04.025219 5, 0xFFFF, sum = 0
6753 00:56:04.025712 6, 0xFFFF, sum = 0
6754 00:56:04.028440 7, 0xFFFF, sum = 0
6755 00:56:04.028862 8, 0xFFFF, sum = 0
6756 00:56:04.031953 9, 0xFFFF, sum = 0
6757 00:56:04.032381 10, 0xFFFF, sum = 0
6758 00:56:04.035076 11, 0xFFFF, sum = 0
6759 00:56:04.038510 12, 0xFFFF, sum = 0
6760 00:56:04.039053 13, 0x0, sum = 1
6761 00:56:04.041877 14, 0x0, sum = 2
6762 00:56:04.042307 15, 0x0, sum = 3
6763 00:56:04.042645 16, 0x0, sum = 4
6764 00:56:04.045677 best_step = 14
6765 00:56:04.046092
6766 00:56:04.046420 ==
6767 00:56:04.048645 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 00:56:04.051574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 00:56:04.052026 ==
6770 00:56:04.054608 RX Vref Scan: 1
6771 00:56:04.055029
6772 00:56:04.058231 RX Vref 0 -> 0, step: 1
6773 00:56:04.058648
6774 00:56:04.058978 RX Delay -343 -> 252, step: 8
6775 00:56:04.059290
6776 00:56:04.061366 Set Vref, RX VrefLevel [Byte0]: 52
6777 00:56:04.064292 [Byte1]: 50
6778 00:56:04.069946
6779 00:56:04.070376 Final RX Vref Byte 0 = 52 to rank0
6780 00:56:04.073474 Final RX Vref Byte 1 = 50 to rank0
6781 00:56:04.076721 Final RX Vref Byte 0 = 52 to rank1
6782 00:56:04.079673 Final RX Vref Byte 1 = 50 to rank1==
6783 00:56:04.082905 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 00:56:04.089912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 00:56:04.090360 ==
6786 00:56:04.090695 DQS Delay:
6787 00:56:04.093360 DQS0 = 44, DQS1 = 56
6788 00:56:04.093780 DQM Delay:
6789 00:56:04.094114 DQM0 = 10, DQM1 = 13
6790 00:56:04.096662 DQ Delay:
6791 00:56:04.099978 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6792 00:56:04.103123 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6793 00:56:04.103545 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6794 00:56:04.109474 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6795 00:56:04.109896
6796 00:56:04.110225
6797 00:56:04.116476 [DQSOSCAuto] RK0, (LSB)MR18= 0x749b, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6798 00:56:04.119865 CH1 RK0: MR19=C0C, MR18=749B
6799 00:56:04.125787 CH1_RK0: MR19=0xC0C, MR18=0x749B, DQSOSC=390, MR23=63, INC=388, DEC=258
6800 00:56:04.126224 ==
6801 00:56:04.129088 Dram Type= 6, Freq= 0, CH_1, rank 1
6802 00:56:04.132692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 00:56:04.133115 ==
6804 00:56:04.135733 [Gating] SW mode calibration
6805 00:56:04.142473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6806 00:56:04.148970 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6807 00:56:04.152209 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6808 00:56:04.155501 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 00:56:04.162411 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 00:56:04.165328 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 00:56:04.169071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 00:56:04.175016 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 00:56:04.178580 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 00:56:04.181936 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 00:56:04.188469 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 00:56:04.191542 Total UI for P1: 0, mck2ui 16
6817 00:56:04.195085 best dqsien dly found for B0: ( 0, 14, 24)
6818 00:56:04.198439 Total UI for P1: 0, mck2ui 16
6819 00:56:04.201522 best dqsien dly found for B1: ( 0, 14, 24)
6820 00:56:04.205093 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6821 00:56:04.208178 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6822 00:56:04.208599
6823 00:56:04.211825 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6824 00:56:04.215629 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 00:56:04.217939 [Gating] SW calibration Done
6826 00:56:04.218468 ==
6827 00:56:04.221581 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 00:56:04.224739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 00:56:04.225237 ==
6830 00:56:04.228205 RX Vref Scan: 0
6831 00:56:04.228750
6832 00:56:04.231143 RX Vref 0 -> 0, step: 1
6833 00:56:04.231569
6834 00:56:04.231991 RX Delay -410 -> 252, step: 16
6835 00:56:04.238402 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6836 00:56:04.241650 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6837 00:56:04.244844 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6838 00:56:04.251295 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6839 00:56:04.254529 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6840 00:56:04.257806 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6841 00:56:04.261341 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6842 00:56:04.268064 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6843 00:56:04.271391 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6844 00:56:04.275033 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6845 00:56:04.277900 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6846 00:56:04.284348 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6847 00:56:04.288066 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6848 00:56:04.290939 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6849 00:56:04.293838 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6850 00:56:04.300784 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6851 00:56:04.301207 ==
6852 00:56:04.304517 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 00:56:04.307311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 00:56:04.307734 ==
6855 00:56:04.308064 DQS Delay:
6856 00:56:04.310945 DQS0 = 43, DQS1 = 51
6857 00:56:04.311572 DQM Delay:
6858 00:56:04.313646 DQM0 = 8, DQM1 = 13
6859 00:56:04.314269 DQ Delay:
6860 00:56:04.316968 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6861 00:56:04.320421 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6862 00:56:04.323745 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6863 00:56:04.326840 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6864 00:56:04.327417
6865 00:56:04.327899
6866 00:56:04.328222 ==
6867 00:56:04.330559 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 00:56:04.333439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 00:56:04.333864 ==
6870 00:56:04.336693
6871 00:56:04.337108
6872 00:56:04.337472 TX Vref Scan disable
6873 00:56:04.340072 == TX Byte 0 ==
6874 00:56:04.343362 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6875 00:56:04.346774 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6876 00:56:04.350835 == TX Byte 1 ==
6877 00:56:04.353602 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6878 00:56:04.356461 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6879 00:56:04.356880 ==
6880 00:56:04.359652 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 00:56:04.366526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 00:56:04.366950 ==
6883 00:56:04.367284
6884 00:56:04.367593
6885 00:56:04.367888 TX Vref Scan disable
6886 00:56:04.369536 == TX Byte 0 ==
6887 00:56:04.372702 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6888 00:56:04.376128 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6889 00:56:04.379542 == TX Byte 1 ==
6890 00:56:04.382995 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6891 00:56:04.386325 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6892 00:56:04.386750
6893 00:56:04.389299 [DATLAT]
6894 00:56:04.389746 Freq=400, CH1 RK1
6895 00:56:04.390173
6896 00:56:04.392941 DATLAT Default: 0xe
6897 00:56:04.393459 0, 0xFFFF, sum = 0
6898 00:56:04.395753 1, 0xFFFF, sum = 0
6899 00:56:04.396294 2, 0xFFFF, sum = 0
6900 00:56:04.399306 3, 0xFFFF, sum = 0
6901 00:56:04.399796 4, 0xFFFF, sum = 0
6902 00:56:04.402468 5, 0xFFFF, sum = 0
6903 00:56:04.403028 6, 0xFFFF, sum = 0
6904 00:56:04.406154 7, 0xFFFF, sum = 0
6905 00:56:04.406691 8, 0xFFFF, sum = 0
6906 00:56:04.409087 9, 0xFFFF, sum = 0
6907 00:56:04.412317 10, 0xFFFF, sum = 0
6908 00:56:04.412784 11, 0xFFFF, sum = 0
6909 00:56:04.415774 12, 0xFFFF, sum = 0
6910 00:56:04.416202 13, 0x0, sum = 1
6911 00:56:04.419299 14, 0x0, sum = 2
6912 00:56:04.419785 15, 0x0, sum = 3
6913 00:56:04.420136 16, 0x0, sum = 4
6914 00:56:04.422139 best_step = 14
6915 00:56:04.422613
6916 00:56:04.422962 ==
6917 00:56:04.425407 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 00:56:04.429002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 00:56:04.429488 ==
6920 00:56:04.432280 RX Vref Scan: 0
6921 00:56:04.432699
6922 00:56:04.435958 RX Vref 0 -> 0, step: 1
6923 00:56:04.436396
6924 00:56:04.436730 RX Delay -343 -> 252, step: 8
6925 00:56:04.443948 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6926 00:56:04.447049 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6927 00:56:04.450685 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6928 00:56:04.457704 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6929 00:56:04.460659 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6930 00:56:04.463921 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6931 00:56:04.466758 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6932 00:56:04.473756 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6933 00:56:04.477024 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6934 00:56:04.480497 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6935 00:56:04.483759 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6936 00:56:04.490126 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6937 00:56:04.493709 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6938 00:56:04.496816 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6939 00:56:04.503256 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6940 00:56:04.506661 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6941 00:56:04.507082 ==
6942 00:56:04.509715 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 00:56:04.512994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 00:56:04.513449 ==
6945 00:56:04.516498 DQS Delay:
6946 00:56:04.517067 DQS0 = 48, DQS1 = 56
6947 00:56:04.517536 DQM Delay:
6948 00:56:04.519812 DQM0 = 10, DQM1 = 13
6949 00:56:04.520230 DQ Delay:
6950 00:56:04.523009 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6951 00:56:04.526411 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6952 00:56:04.529731 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6953 00:56:04.532643 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6954 00:56:04.533064
6955 00:56:04.533432
6956 00:56:04.542545 [DQSOSCAuto] RK1, (LSB)MR18= 0x76ae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6957 00:56:04.542971 CH1 RK1: MR19=C0C, MR18=76AE
6958 00:56:04.549406 CH1_RK1: MR19=0xC0C, MR18=0x76AE, DQSOSC=388, MR23=63, INC=392, DEC=261
6959 00:56:04.552744 [RxdqsGatingPostProcess] freq 400
6960 00:56:04.559332 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6961 00:56:04.562224 best DQS0 dly(2T, 0.5T) = (0, 10)
6962 00:56:04.566312 best DQS1 dly(2T, 0.5T) = (0, 10)
6963 00:56:04.569552 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6964 00:56:04.572571 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6965 00:56:04.575817 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 00:56:04.576241 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 00:56:04.579151 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 00:56:04.582631 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 00:56:04.585733 Pre-setting of DQS Precalculation
6970 00:56:04.592009 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6971 00:56:04.598639 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6972 00:56:04.605918 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6973 00:56:04.606342
6974 00:56:04.606687
6975 00:56:04.608800 [Calibration Summary] 800 Mbps
6976 00:56:04.612264 CH 0, Rank 0
6977 00:56:04.612796 SW Impedance : PASS
6978 00:56:04.615354 DUTY Scan : NO K
6979 00:56:04.618494 ZQ Calibration : PASS
6980 00:56:04.618914 Jitter Meter : NO K
6981 00:56:04.622106 CBT Training : PASS
6982 00:56:04.622523 Write leveling : PASS
6983 00:56:04.625090 RX DQS gating : PASS
6984 00:56:04.628560 RX DQ/DQS(RDDQC) : PASS
6985 00:56:04.629039 TX DQ/DQS : PASS
6986 00:56:04.631900 RX DATLAT : PASS
6987 00:56:04.635307 RX DQ/DQS(Engine): PASS
6988 00:56:04.635728 TX OE : NO K
6989 00:56:04.638284 All Pass.
6990 00:56:04.638761
6991 00:56:04.639138 CH 0, Rank 1
6992 00:56:04.642430 SW Impedance : PASS
6993 00:56:04.642949 DUTY Scan : NO K
6994 00:56:04.644890 ZQ Calibration : PASS
6995 00:56:04.648508 Jitter Meter : NO K
6996 00:56:04.648921 CBT Training : PASS
6997 00:56:04.651885 Write leveling : NO K
6998 00:56:04.655136 RX DQS gating : PASS
6999 00:56:04.655626 RX DQ/DQS(RDDQC) : PASS
7000 00:56:04.658678 TX DQ/DQS : PASS
7001 00:56:04.661764 RX DATLAT : PASS
7002 00:56:04.662218 RX DQ/DQS(Engine): PASS
7003 00:56:04.664750 TX OE : NO K
7004 00:56:04.665204 All Pass.
7005 00:56:04.665669
7006 00:56:04.667959 CH 1, Rank 0
7007 00:56:04.668406 SW Impedance : PASS
7008 00:56:04.671504 DUTY Scan : NO K
7009 00:56:04.674446 ZQ Calibration : PASS
7010 00:56:04.674948 Jitter Meter : NO K
7011 00:56:04.678030 CBT Training : PASS
7012 00:56:04.681193 Write leveling : PASS
7013 00:56:04.681794 RX DQS gating : PASS
7014 00:56:04.684592 RX DQ/DQS(RDDQC) : PASS
7015 00:56:04.687792 TX DQ/DQS : PASS
7016 00:56:04.688214 RX DATLAT : PASS
7017 00:56:04.691005 RX DQ/DQS(Engine): PASS
7018 00:56:04.694757 TX OE : NO K
7019 00:56:04.695201 All Pass.
7020 00:56:04.695534
7021 00:56:04.695842 CH 1, Rank 1
7022 00:56:04.697452 SW Impedance : PASS
7023 00:56:04.701249 DUTY Scan : NO K
7024 00:56:04.701790 ZQ Calibration : PASS
7025 00:56:04.704535 Jitter Meter : NO K
7026 00:56:04.704995 CBT Training : PASS
7027 00:56:04.707619 Write leveling : NO K
7028 00:56:04.711247 RX DQS gating : PASS
7029 00:56:04.711666 RX DQ/DQS(RDDQC) : PASS
7030 00:56:04.714475 TX DQ/DQS : PASS
7031 00:56:04.717486 RX DATLAT : PASS
7032 00:56:04.717905 RX DQ/DQS(Engine): PASS
7033 00:56:04.720595 TX OE : NO K
7034 00:56:04.721017 All Pass.
7035 00:56:04.721381
7036 00:56:04.724450 DramC Write-DBI off
7037 00:56:04.727916 PER_BANK_REFRESH: Hybrid Mode
7038 00:56:04.728340 TX_TRACKING: ON
7039 00:56:04.737380 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7040 00:56:04.740573 [FAST_K] Save calibration result to emmc
7041 00:56:04.743924 dramc_set_vcore_voltage set vcore to 725000
7042 00:56:04.747205 Read voltage for 1600, 0
7043 00:56:04.747773 Vio18 = 0
7044 00:56:04.750695 Vcore = 725000
7045 00:56:04.751129 Vdram = 0
7046 00:56:04.751457 Vddq = 0
7047 00:56:04.751921 Vmddr = 0
7048 00:56:04.757165 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7049 00:56:04.763728 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7050 00:56:04.764231 MEM_TYPE=3, freq_sel=13
7051 00:56:04.767196 sv_algorithm_assistance_LP4_3733
7052 00:56:04.770122 ============ PULL DRAM RESETB DOWN ============
7053 00:56:04.776991 ========== PULL DRAM RESETB DOWN end =========
7054 00:56:04.780184 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7055 00:56:04.783539 ===================================
7056 00:56:04.786931 LPDDR4 DRAM CONFIGURATION
7057 00:56:04.790131 ===================================
7058 00:56:04.790747 EX_ROW_EN[0] = 0x0
7059 00:56:04.793412 EX_ROW_EN[1] = 0x0
7060 00:56:04.793833 LP4Y_EN = 0x0
7061 00:56:04.796751 WORK_FSP = 0x1
7062 00:56:04.797245 WL = 0x5
7063 00:56:04.800044 RL = 0x5
7064 00:56:04.803334 BL = 0x2
7065 00:56:04.803754 RPST = 0x0
7066 00:56:04.807110 RD_PRE = 0x0
7067 00:56:04.807534 WR_PRE = 0x1
7068 00:56:04.809781 WR_PST = 0x1
7069 00:56:04.810201 DBI_WR = 0x0
7070 00:56:04.813718 DBI_RD = 0x0
7071 00:56:04.814135 OTF = 0x1
7072 00:56:04.816898 ===================================
7073 00:56:04.819783 ===================================
7074 00:56:04.823255 ANA top config
7075 00:56:04.826591 ===================================
7076 00:56:04.827049 DLL_ASYNC_EN = 0
7077 00:56:04.831592 ALL_SLAVE_EN = 0
7078 00:56:04.833076 NEW_RANK_MODE = 1
7079 00:56:04.836218 DLL_IDLE_MODE = 1
7080 00:56:04.836636 LP45_APHY_COMB_EN = 1
7081 00:56:04.839655 TX_ODT_DIS = 0
7082 00:56:04.843359 NEW_8X_MODE = 1
7083 00:56:04.846645 ===================================
7084 00:56:04.849427 ===================================
7085 00:56:04.853153 data_rate = 3200
7086 00:56:04.856680 CKR = 1
7087 00:56:04.859887 DQ_P2S_RATIO = 8
7088 00:56:04.862555 ===================================
7089 00:56:04.862969 CA_P2S_RATIO = 8
7090 00:56:04.866047 DQ_CA_OPEN = 0
7091 00:56:04.869056 DQ_SEMI_OPEN = 0
7092 00:56:04.872859 CA_SEMI_OPEN = 0
7093 00:56:04.876036 CA_FULL_RATE = 0
7094 00:56:04.879850 DQ_CKDIV4_EN = 0
7095 00:56:04.880365 CA_CKDIV4_EN = 0
7096 00:56:04.882550 CA_PREDIV_EN = 0
7097 00:56:04.885996 PH8_DLY = 12
7098 00:56:04.889519 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7099 00:56:04.892503 DQ_AAMCK_DIV = 4
7100 00:56:04.895602 CA_AAMCK_DIV = 4
7101 00:56:04.899152 CA_ADMCK_DIV = 4
7102 00:56:04.899604 DQ_TRACK_CA_EN = 0
7103 00:56:04.902230 CA_PICK = 1600
7104 00:56:04.905497 CA_MCKIO = 1600
7105 00:56:04.909028 MCKIO_SEMI = 0
7106 00:56:04.912289 PLL_FREQ = 3068
7107 00:56:04.915718 DQ_UI_PI_RATIO = 32
7108 00:56:04.918383 CA_UI_PI_RATIO = 0
7109 00:56:04.921885 ===================================
7110 00:56:04.925230 ===================================
7111 00:56:04.925696 memory_type:LPDDR4
7112 00:56:04.928317 GP_NUM : 10
7113 00:56:04.931707 SRAM_EN : 1
7114 00:56:04.932127 MD32_EN : 0
7115 00:56:04.935427 ===================================
7116 00:56:04.938070 [ANA_INIT] >>>>>>>>>>>>>>
7117 00:56:04.941950 <<<<<< [CONFIGURE PHASE]: ANA_TX
7118 00:56:04.945195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7119 00:56:04.948672 ===================================
7120 00:56:04.951657 data_rate = 3200,PCW = 0X7600
7121 00:56:04.954807 ===================================
7122 00:56:04.958090 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7123 00:56:04.961777 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7124 00:56:04.968340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 00:56:04.971621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7126 00:56:04.975102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7127 00:56:04.978267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7128 00:56:04.981525 [ANA_INIT] flow start
7129 00:56:04.985325 [ANA_INIT] PLL >>>>>>>>
7130 00:56:04.985746 [ANA_INIT] PLL <<<<<<<<
7131 00:56:04.988361 [ANA_INIT] MIDPI >>>>>>>>
7132 00:56:04.991355 [ANA_INIT] MIDPI <<<<<<<<
7133 00:56:04.994664 [ANA_INIT] DLL >>>>>>>>
7134 00:56:04.995118 [ANA_INIT] DLL <<<<<<<<
7135 00:56:04.998302 [ANA_INIT] flow end
7136 00:56:05.001723 ============ LP4 DIFF to SE enter ============
7137 00:56:05.004657 ============ LP4 DIFF to SE exit ============
7138 00:56:05.008214 [ANA_INIT] <<<<<<<<<<<<<
7139 00:56:05.011469 [Flow] Enable top DCM control >>>>>
7140 00:56:05.014867 [Flow] Enable top DCM control <<<<<
7141 00:56:05.017648 Enable DLL master slave shuffle
7142 00:56:05.024450 ==============================================================
7143 00:56:05.024749 Gating Mode config
7144 00:56:05.030747 ==============================================================
7145 00:56:05.030978 Config description:
7146 00:56:05.040854 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7147 00:56:05.047220 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7148 00:56:05.053466 SELPH_MODE 0: By rank 1: By Phase
7149 00:56:05.060401 ==============================================================
7150 00:56:05.060538 GAT_TRACK_EN = 1
7151 00:56:05.063823 RX_GATING_MODE = 2
7152 00:56:05.066896 RX_GATING_TRACK_MODE = 2
7153 00:56:05.069981 SELPH_MODE = 1
7154 00:56:05.073149 PICG_EARLY_EN = 1
7155 00:56:05.076617 VALID_LAT_VALUE = 1
7156 00:56:05.083503 ==============================================================
7157 00:56:05.086502 Enter into Gating configuration >>>>
7158 00:56:05.089736 Exit from Gating configuration <<<<
7159 00:56:05.093225 Enter into DVFS_PRE_config >>>>>
7160 00:56:05.103126 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7161 00:56:05.106788 Exit from DVFS_PRE_config <<<<<
7162 00:56:05.110017 Enter into PICG configuration >>>>
7163 00:56:05.113137 Exit from PICG configuration <<<<
7164 00:56:05.116449 [RX_INPUT] configuration >>>>>
7165 00:56:05.119724 [RX_INPUT] configuration <<<<<
7166 00:56:05.123703 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7167 00:56:05.129835 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7168 00:56:05.136253 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 00:56:05.142667 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 00:56:05.145783 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 00:56:05.152523 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 00:56:05.156192 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7173 00:56:05.162473 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7174 00:56:05.165610 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7175 00:56:05.169150 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7176 00:56:05.172310 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7177 00:56:05.178696 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7178 00:56:05.182016 ===================================
7179 00:56:05.185191 LPDDR4 DRAM CONFIGURATION
7180 00:56:05.188911 ===================================
7181 00:56:05.189069 EX_ROW_EN[0] = 0x0
7182 00:56:05.192139 EX_ROW_EN[1] = 0x0
7183 00:56:05.192297 LP4Y_EN = 0x0
7184 00:56:05.195111 WORK_FSP = 0x1
7185 00:56:05.195276 WL = 0x5
7186 00:56:05.198651 RL = 0x5
7187 00:56:05.198815 BL = 0x2
7188 00:56:05.201856 RPST = 0x0
7189 00:56:05.202012 RD_PRE = 0x0
7190 00:56:05.204806 WR_PRE = 0x1
7191 00:56:05.208177 WR_PST = 0x1
7192 00:56:05.208355 DBI_WR = 0x0
7193 00:56:05.211814 DBI_RD = 0x0
7194 00:56:05.212021 OTF = 0x1
7195 00:56:05.215118 ===================================
7196 00:56:05.218140 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7197 00:56:05.225059 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7198 00:56:05.228521 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7199 00:56:05.231767 ===================================
7200 00:56:05.234924 LPDDR4 DRAM CONFIGURATION
7201 00:56:05.238412 ===================================
7202 00:56:05.238837 EX_ROW_EN[0] = 0x10
7203 00:56:05.241943 EX_ROW_EN[1] = 0x0
7204 00:56:05.242362 LP4Y_EN = 0x0
7205 00:56:05.245019 WORK_FSP = 0x1
7206 00:56:05.245588 WL = 0x5
7207 00:56:05.248097 RL = 0x5
7208 00:56:05.248514 BL = 0x2
7209 00:56:05.251541 RPST = 0x0
7210 00:56:05.254770 RD_PRE = 0x0
7211 00:56:05.255186 WR_PRE = 0x1
7212 00:56:05.258098 WR_PST = 0x1
7213 00:56:05.258551 DBI_WR = 0x0
7214 00:56:05.261724 DBI_RD = 0x0
7215 00:56:05.262142 OTF = 0x1
7216 00:56:05.264835 ===================================
7217 00:56:05.271602 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7218 00:56:05.272024 ==
7219 00:56:05.274961 Dram Type= 6, Freq= 0, CH_0, rank 0
7220 00:56:05.278014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7221 00:56:05.278480 ==
7222 00:56:05.281372 [Duty_Offset_Calibration]
7223 00:56:05.284573 B0:2 B1:0 CA:4
7224 00:56:05.285036
7225 00:56:05.288095 [DutyScan_Calibration_Flow] k_type=0
7226 00:56:05.295489
7227 00:56:05.295938 ==CLK 0==
7228 00:56:05.299056 Final CLK duty delay cell = -4
7229 00:56:05.301781 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7230 00:56:05.305523 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7231 00:56:05.308999 [-4] AVG Duty = 4937%(X100)
7232 00:56:05.309505
7233 00:56:05.312180 CH0 CLK Duty spec in!! Max-Min= 187%
7234 00:56:05.315116 [DutyScan_Calibration_Flow] ====Done====
7235 00:56:05.315571
7236 00:56:05.318939 [DutyScan_Calibration_Flow] k_type=1
7237 00:56:05.335742
7238 00:56:05.336192 ==DQS 0 ==
7239 00:56:05.338890 Final DQS duty delay cell = 0
7240 00:56:05.342099 [0] MAX Duty = 5187%(X100), DQS PI = 20
7241 00:56:05.345614 [0] MIN Duty = 5062%(X100), DQS PI = 12
7242 00:56:05.349369 [0] AVG Duty = 5124%(X100)
7243 00:56:05.349823
7244 00:56:05.350277 ==DQS 1 ==
7245 00:56:05.352042 Final DQS duty delay cell = 0
7246 00:56:05.355539 [0] MAX Duty = 5187%(X100), DQS PI = 2
7247 00:56:05.359118 [0] MIN Duty = 4938%(X100), DQS PI = 12
7248 00:56:05.362090 [0] AVG Duty = 5062%(X100)
7249 00:56:05.362524
7250 00:56:05.365673 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7251 00:56:05.366115
7252 00:56:05.369459 CH0 DQS 1 Duty spec in!! Max-Min= 249%
7253 00:56:05.371897 [DutyScan_Calibration_Flow] ====Done====
7254 00:56:05.372402
7255 00:56:05.375628 [DutyScan_Calibration_Flow] k_type=3
7256 00:56:05.392620
7257 00:56:05.393119 ==DQM 0 ==
7258 00:56:05.396335 Final DQM duty delay cell = 0
7259 00:56:05.399319 [0] MAX Duty = 5124%(X100), DQS PI = 22
7260 00:56:05.402481 [0] MIN Duty = 4844%(X100), DQS PI = 56
7261 00:56:05.406449 [0] AVG Duty = 4984%(X100)
7262 00:56:05.406858
7263 00:56:05.407395 ==DQM 1 ==
7264 00:56:05.409164 Final DQM duty delay cell = 0
7265 00:56:05.412668 [0] MAX Duty = 4969%(X100), DQS PI = 2
7266 00:56:05.415941 [0] MIN Duty = 4813%(X100), DQS PI = 34
7267 00:56:05.419272 [0] AVG Duty = 4891%(X100)
7268 00:56:05.419684
7269 00:56:05.422580 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7270 00:56:05.423117
7271 00:56:05.425743 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7272 00:56:05.428831 [DutyScan_Calibration_Flow] ====Done====
7273 00:56:05.429244
7274 00:56:05.432189 [DutyScan_Calibration_Flow] k_type=2
7275 00:56:05.449888
7276 00:56:05.450350 ==DQ 0 ==
7277 00:56:05.453210 Final DQ duty delay cell = 0
7278 00:56:05.456292 [0] MAX Duty = 5124%(X100), DQS PI = 20
7279 00:56:05.459854 [0] MIN Duty = 4938%(X100), DQS PI = 12
7280 00:56:05.462976 [0] AVG Duty = 5031%(X100)
7281 00:56:05.463391
7282 00:56:05.463971 ==DQ 1 ==
7283 00:56:05.466248 Final DQ duty delay cell = 0
7284 00:56:05.469814 [0] MAX Duty = 5187%(X100), DQS PI = 2
7285 00:56:05.473478 [0] MIN Duty = 4938%(X100), DQS PI = 12
7286 00:56:05.473896 [0] AVG Duty = 5062%(X100)
7287 00:56:05.476884
7288 00:56:05.479719 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7289 00:56:05.480397
7290 00:56:05.482759 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7291 00:56:05.486002 [DutyScan_Calibration_Flow] ====Done====
7292 00:56:05.486452 ==
7293 00:56:05.489559 Dram Type= 6, Freq= 0, CH_1, rank 0
7294 00:56:05.493197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 00:56:05.493658 ==
7296 00:56:05.495774 [Duty_Offset_Calibration]
7297 00:56:05.496180 B0:0 B1:-1 CA:3
7298 00:56:05.496500
7299 00:56:05.499054 [DutyScan_Calibration_Flow] k_type=0
7300 00:56:05.510292
7301 00:56:05.510515 ==CLK 0==
7302 00:56:05.513501 Final CLK duty delay cell = 0
7303 00:56:05.516307 [0] MAX Duty = 5187%(X100), DQS PI = 26
7304 00:56:05.520041 [0] MIN Duty = 5000%(X100), DQS PI = 38
7305 00:56:05.522824 [0] AVG Duty = 5093%(X100)
7306 00:56:05.523002
7307 00:56:05.526241 CH1 CLK Duty spec in!! Max-Min= 187%
7308 00:56:05.529875 [DutyScan_Calibration_Flow] ====Done====
7309 00:56:05.530052
7310 00:56:05.532779 [DutyScan_Calibration_Flow] k_type=1
7311 00:56:05.548795
7312 00:56:05.549045 ==DQS 0 ==
7313 00:56:05.551920 Final DQS duty delay cell = 0
7314 00:56:05.555845 [0] MAX Duty = 5250%(X100), DQS PI = 30
7315 00:56:05.558712 [0] MIN Duty = 4907%(X100), DQS PI = 40
7316 00:56:05.562135 [0] AVG Duty = 5078%(X100)
7317 00:56:05.562588
7318 00:56:05.562944 ==DQS 1 ==
7319 00:56:05.565634 Final DQS duty delay cell = -4
7320 00:56:05.568660 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7321 00:56:05.572221 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7322 00:56:05.575343 [-4] AVG Duty = 4906%(X100)
7323 00:56:05.575751
7324 00:56:05.579041 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7325 00:56:05.579470
7326 00:56:05.582026 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7327 00:56:05.585188 [DutyScan_Calibration_Flow] ====Done====
7328 00:56:05.585645
7329 00:56:05.588844 [DutyScan_Calibration_Flow] k_type=3
7330 00:56:05.606654
7331 00:56:05.607140 ==DQM 0 ==
7332 00:56:05.609722 Final DQM duty delay cell = 0
7333 00:56:05.613169 [0] MAX Duty = 5062%(X100), DQS PI = 30
7334 00:56:05.616366 [0] MIN Duty = 4782%(X100), DQS PI = 40
7335 00:56:05.619265 [0] AVG Duty = 4922%(X100)
7336 00:56:05.619715
7337 00:56:05.620073 ==DQM 1 ==
7338 00:56:05.622723 Final DQM duty delay cell = 0
7339 00:56:05.625867 [0] MAX Duty = 4969%(X100), DQS PI = 30
7340 00:56:05.629336 [0] MIN Duty = 4813%(X100), DQS PI = 0
7341 00:56:05.632980 [0] AVG Duty = 4891%(X100)
7342 00:56:05.633437
7343 00:56:05.636115 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7344 00:56:05.636531
7345 00:56:05.639468 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7346 00:56:05.642651 [DutyScan_Calibration_Flow] ====Done====
7347 00:56:05.643072
7348 00:56:05.646092 [DutyScan_Calibration_Flow] k_type=2
7349 00:56:05.662405
7350 00:56:05.662831 ==DQ 0 ==
7351 00:56:05.666020 Final DQ duty delay cell = -4
7352 00:56:05.668950 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7353 00:56:05.672565 [-4] MIN Duty = 4813%(X100), DQS PI = 20
7354 00:56:05.675546 [-4] AVG Duty = 4891%(X100)
7355 00:56:05.675983
7356 00:56:05.676309 ==DQ 1 ==
7357 00:56:05.679302 Final DQ duty delay cell = 0
7358 00:56:05.682331 [0] MAX Duty = 5031%(X100), DQS PI = 30
7359 00:56:05.685525 [0] MIN Duty = 4844%(X100), DQS PI = 60
7360 00:56:05.689487 [0] AVG Duty = 4937%(X100)
7361 00:56:05.689921
7362 00:56:05.692549 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7363 00:56:05.692967
7364 00:56:05.695471 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7365 00:56:05.698935 [DutyScan_Calibration_Flow] ====Done====
7366 00:56:05.701754 nWR fixed to 30
7367 00:56:05.705186 [ModeRegInit_LP4] CH0 RK0
7368 00:56:05.705637 [ModeRegInit_LP4] CH0 RK1
7369 00:56:05.708349 [ModeRegInit_LP4] CH1 RK0
7370 00:56:05.711823 [ModeRegInit_LP4] CH1 RK1
7371 00:56:05.712258 match AC timing 5
7372 00:56:05.718524 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7373 00:56:05.721713 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7374 00:56:05.725221 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7375 00:56:05.732096 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7376 00:56:05.734763 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7377 00:56:05.738150 [MiockJmeterHQA]
7378 00:56:05.738578
7379 00:56:05.741437 [DramcMiockJmeter] u1RxGatingPI = 0
7380 00:56:05.741857 0 : 4363, 4138
7381 00:56:05.742193 4 : 4253, 4026
7382 00:56:05.744574 8 : 4253, 4027
7383 00:56:05.744994 12 : 4255, 4029
7384 00:56:05.748500 16 : 4253, 4026
7385 00:56:05.748922 20 : 4363, 4138
7386 00:56:05.751300 24 : 4363, 4137
7387 00:56:05.751723 28 : 4252, 4027
7388 00:56:05.752057 32 : 4253, 4027
7389 00:56:05.754847 36 : 4253, 4026
7390 00:56:05.755268 40 : 4250, 4027
7391 00:56:05.757831 44 : 4255, 4029
7392 00:56:05.758251 48 : 4360, 4138
7393 00:56:05.761070 52 : 4252, 4027
7394 00:56:05.761526 56 : 4250, 4027
7395 00:56:05.764673 60 : 4250, 4027
7396 00:56:05.765097 64 : 4252, 4029
7397 00:56:05.765467 68 : 4250, 4027
7398 00:56:05.768049 72 : 4360, 4138
7399 00:56:05.768471 76 : 4360, 4137
7400 00:56:05.771407 80 : 4250, 4027
7401 00:56:05.771830 84 : 4249, 4027
7402 00:56:05.774831 88 : 4250, 4026
7403 00:56:05.775446 92 : 4250, 4027
7404 00:56:05.777757 96 : 4252, 2793
7405 00:56:05.778384 100 : 4360, 0
7406 00:56:05.778965 104 : 4250, 0
7407 00:56:05.781190 108 : 4253, 0
7408 00:56:05.781836 112 : 4250, 0
7409 00:56:05.784042 116 : 4361, 0
7410 00:56:05.784496 120 : 4250, 0
7411 00:56:05.785098 124 : 4250, 0
7412 00:56:05.787806 128 : 4250, 0
7413 00:56:05.788249 132 : 4253, 0
7414 00:56:05.788593 136 : 4250, 0
7415 00:56:05.790899 140 : 4250, 0
7416 00:56:05.791330 144 : 4252, 0
7417 00:56:05.794413 148 : 4360, 0
7418 00:56:05.794856 152 : 4361, 0
7419 00:56:05.795194 156 : 4363, 0
7420 00:56:05.797292 160 : 4250, 0
7421 00:56:05.797719 164 : 4250, 0
7422 00:56:05.800943 168 : 4250, 0
7423 00:56:05.801404 172 : 4250, 0
7424 00:56:05.801748 176 : 4250, 0
7425 00:56:05.804458 180 : 4361, 0
7426 00:56:05.804885 184 : 4250, 0
7427 00:56:05.807206 188 : 4250, 0
7428 00:56:05.807632 192 : 4250, 0
7429 00:56:05.807968 196 : 4252, 0
7430 00:56:05.810830 200 : 4250, 0
7431 00:56:05.811261 204 : 4360, 0
7432 00:56:05.814415 208 : 4361, 0
7433 00:56:05.814859 212 : 4252, 0
7434 00:56:05.815247 216 : 4250, 0
7435 00:56:05.817536 220 : 4250, 417
7436 00:56:05.817964 224 : 4250, 3922
7437 00:56:05.820730 228 : 4252, 4029
7438 00:56:05.821186 232 : 4249, 4027
7439 00:56:05.824032 236 : 4250, 4026
7440 00:56:05.824457 240 : 4250, 4027
7441 00:56:05.827370 244 : 4360, 4138
7442 00:56:05.827796 248 : 4250, 4027
7443 00:56:05.830725 252 : 4250, 4026
7444 00:56:05.831152 256 : 4360, 4138
7445 00:56:05.831490 260 : 4250, 4027
7446 00:56:05.834039 264 : 4250, 4027
7447 00:56:05.834464 268 : 4363, 4140
7448 00:56:05.836987 272 : 4250, 4026
7449 00:56:05.837448 276 : 4250, 4027
7450 00:56:05.840551 280 : 4249, 4027
7451 00:56:05.840975 284 : 4252, 4029
7452 00:56:05.843677 288 : 4250, 4026
7453 00:56:05.844102 292 : 4250, 4027
7454 00:56:05.847432 296 : 4360, 4138
7455 00:56:05.847857 300 : 4250, 4027
7456 00:56:05.850440 304 : 4250, 4026
7457 00:56:05.850867 308 : 4361, 4137
7458 00:56:05.854073 312 : 4250, 4027
7459 00:56:05.854497 316 : 4249, 4027
7460 00:56:05.854834 320 : 4363, 4140
7461 00:56:05.857362 324 : 4250, 4026
7462 00:56:05.857792 328 : 4250, 4027
7463 00:56:05.860134 332 : 4250, 4009
7464 00:56:05.860612 336 : 4252, 1856
7465 00:56:05.861046
7466 00:56:05.863788 MIOCK jitter meter ch=0
7467 00:56:05.864281
7468 00:56:05.866613 1T = (336-100) = 236 dly cells
7469 00:56:05.873374 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7470 00:56:05.873814 ==
7471 00:56:05.876481 Dram Type= 6, Freq= 0, CH_0, rank 0
7472 00:56:05.880325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7473 00:56:05.880760 ==
7474 00:56:05.886515 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7475 00:56:05.890033 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7476 00:56:05.893533 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7477 00:56:05.899963 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7478 00:56:05.909061 [CA 0] Center 43 (13~74) winsize 62
7479 00:56:05.912684 [CA 1] Center 42 (12~73) winsize 62
7480 00:56:05.915569 [CA 2] Center 37 (8~67) winsize 60
7481 00:56:05.919114 [CA 3] Center 37 (7~67) winsize 61
7482 00:56:05.922217 [CA 4] Center 36 (6~66) winsize 61
7483 00:56:05.925448 [CA 5] Center 35 (5~66) winsize 62
7484 00:56:05.925869
7485 00:56:05.928956 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7486 00:56:05.929428
7487 00:56:05.935334 [CATrainingPosCal] consider 1 rank data
7488 00:56:05.935764 u2DelayCellTimex100 = 275/100 ps
7489 00:56:05.941442 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7490 00:56:05.945628 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7491 00:56:05.948114 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7492 00:56:05.951404 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7493 00:56:05.954913 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7494 00:56:05.958440 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7495 00:56:05.958524
7496 00:56:05.961536 CA PerBit enable=1, Macro0, CA PI delay=35
7497 00:56:05.961620
7498 00:56:05.964559 [CBTSetCACLKResult] CA Dly = 35
7499 00:56:05.967838 CS Dly: 10 (0~41)
7500 00:56:05.971584 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7501 00:56:05.975107 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7502 00:56:05.975191 ==
7503 00:56:05.978275 Dram Type= 6, Freq= 0, CH_0, rank 1
7504 00:56:05.984451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 00:56:05.984535 ==
7506 00:56:05.988105 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 00:56:05.994199 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 00:56:05.997526 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 00:56:06.003851 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 00:56:06.012475 [CA 0] Center 43 (13~74) winsize 62
7511 00:56:06.015367 [CA 1] Center 43 (13~73) winsize 61
7512 00:56:06.019023 [CA 2] Center 38 (9~68) winsize 60
7513 00:56:06.021932 [CA 3] Center 38 (9~68) winsize 60
7514 00:56:06.025207 [CA 4] Center 36 (6~67) winsize 62
7515 00:56:06.029135 [CA 5] Center 36 (6~66) winsize 61
7516 00:56:06.029248
7517 00:56:06.032178 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7518 00:56:06.032303
7519 00:56:06.035461 [CATrainingPosCal] consider 2 rank data
7520 00:56:06.039037 u2DelayCellTimex100 = 275/100 ps
7521 00:56:06.044997 CA0 delay=43 (13~74),Diff = 7 PI (24 cell)
7522 00:56:06.048559 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7523 00:56:06.051752 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7524 00:56:06.055199 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7525 00:56:06.058779 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7526 00:56:06.061993 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7527 00:56:06.062314
7528 00:56:06.065123 CA PerBit enable=1, Macro0, CA PI delay=36
7529 00:56:06.065459
7530 00:56:06.068739 [CBTSetCACLKResult] CA Dly = 36
7531 00:56:06.071623 CS Dly: 11 (0~43)
7532 00:56:06.075244 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 00:56:06.078374 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 00:56:06.078804
7535 00:56:06.081773 ----->DramcWriteLeveling(PI) begin...
7536 00:56:06.082211 ==
7537 00:56:06.085333 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 00:56:06.091616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 00:56:06.092071 ==
7540 00:56:06.094979 Write leveling (Byte 0): 32 => 32
7541 00:56:06.099052 Write leveling (Byte 1): 26 => 26
7542 00:56:06.099485 DramcWriteLeveling(PI) end<-----
7543 00:56:06.101496
7544 00:56:06.101922 ==
7545 00:56:06.104710 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 00:56:06.108489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 00:56:06.109037 ==
7548 00:56:06.111949 [Gating] SW mode calibration
7549 00:56:06.118363 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7550 00:56:06.121211 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7551 00:56:06.128007 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 00:56:06.131162 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 00:56:06.134797 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7554 00:56:06.141160 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7555 00:56:06.144351 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7556 00:56:06.150541 1 4 20 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
7557 00:56:06.154143 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 00:56:06.157210 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 00:56:06.163742 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 00:56:06.167241 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7561 00:56:06.170623 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
7562 00:56:06.177400 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
7563 00:56:06.180590 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7564 00:56:06.183898 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7565 00:56:06.190482 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 00:56:06.194237 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 00:56:06.197194 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 00:56:06.203647 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 00:56:06.206862 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7570 00:56:06.210001 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7571 00:56:06.216611 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7572 00:56:06.219834 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7573 00:56:06.222858 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 00:56:06.229536 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 00:56:06.232969 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 00:56:06.236479 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 00:56:06.242953 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 00:56:06.246399 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7579 00:56:06.249535 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7580 00:56:06.256193 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7581 00:56:06.259460 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7582 00:56:06.262767 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 00:56:06.269124 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 00:56:06.272714 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 00:56:06.276832 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 00:56:06.282285 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 00:56:06.285557 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 00:56:06.289417 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 00:56:06.295276 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 00:56:06.298573 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 00:56:06.302340 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 00:56:06.308600 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7593 00:56:06.311732 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 00:56:06.315292 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7595 00:56:06.321666 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 00:56:06.322099 Total UI for P1: 0, mck2ui 16
7597 00:56:06.328162 best dqsien dly found for B0: ( 1, 9, 8)
7598 00:56:06.332223 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7599 00:56:06.334978 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 00:56:06.338237 Total UI for P1: 0, mck2ui 16
7601 00:56:06.341687 best dqsien dly found for B1: ( 1, 9, 18)
7602 00:56:06.344789 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7603 00:56:06.348316 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7604 00:56:06.348745
7605 00:56:06.354968 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7606 00:56:06.358308 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7607 00:56:06.361597 [Gating] SW calibration Done
7608 00:56:06.362023 ==
7609 00:56:06.364906 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 00:56:06.368173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 00:56:06.368612 ==
7612 00:56:06.368973 RX Vref Scan: 0
7613 00:56:06.369320
7614 00:56:06.371305 RX Vref 0 -> 0, step: 1
7615 00:56:06.371752
7616 00:56:06.374575 RX Delay 0 -> 252, step: 8
7617 00:56:06.378112 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7618 00:56:06.381036 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7619 00:56:06.387810 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7620 00:56:06.390781 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7621 00:56:06.394128 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7622 00:56:06.397538 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7623 00:56:06.400869 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7624 00:56:06.407793 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7625 00:56:06.410395 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7626 00:56:06.414196 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7627 00:56:06.417710 iDelay=192, Bit 10, Center 123 (72 ~ 175) 104
7628 00:56:06.420695 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7629 00:56:06.426773 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7630 00:56:06.430225 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7631 00:56:06.433582 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7632 00:56:06.437045 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7633 00:56:06.437579 ==
7634 00:56:06.439972 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 00:56:06.447580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 00:56:06.448033 ==
7637 00:56:06.448383 DQS Delay:
7638 00:56:06.450410 DQS0 = 0, DQS1 = 0
7639 00:56:06.450819 DQM Delay:
7640 00:56:06.453437 DQM0 = 131, DQM1 = 125
7641 00:56:06.453886 DQ Delay:
7642 00:56:06.456764 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7643 00:56:06.460193 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7644 00:56:06.463463 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7645 00:56:06.466833 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7646 00:56:06.467246
7647 00:56:06.467594
7648 00:56:06.467898 ==
7649 00:56:06.470357 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 00:56:06.476580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 00:56:06.476995 ==
7652 00:56:06.477401
7653 00:56:06.477714
7654 00:56:06.478036 TX Vref Scan disable
7655 00:56:06.479902 == TX Byte 0 ==
7656 00:56:06.483136 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7657 00:56:06.489891 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7658 00:56:06.490345 == TX Byte 1 ==
7659 00:56:06.493699 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7660 00:56:06.500170 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7661 00:56:06.500679 ==
7662 00:56:06.502977 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 00:56:06.506366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 00:56:06.506895 ==
7665 00:56:06.520382
7666 00:56:06.523506 TX Vref early break, caculate TX vref
7667 00:56:06.527284 TX Vref=16, minBit 6, minWin=22, winSum=372
7668 00:56:06.530314 TX Vref=18, minBit 1, minWin=23, winSum=382
7669 00:56:06.533401 TX Vref=20, minBit 1, minWin=23, winSum=391
7670 00:56:06.536739 TX Vref=22, minBit 8, minWin=24, winSum=403
7671 00:56:06.540252 TX Vref=24, minBit 1, minWin=25, winSum=414
7672 00:56:06.546503 TX Vref=26, minBit 4, minWin=25, winSum=418
7673 00:56:06.549686 TX Vref=28, minBit 1, minWin=25, winSum=421
7674 00:56:06.552859 TX Vref=30, minBit 6, minWin=25, winSum=419
7675 00:56:06.556173 TX Vref=32, minBit 1, minWin=25, winSum=412
7676 00:56:06.559945 TX Vref=34, minBit 0, minWin=24, winSum=400
7677 00:56:06.566639 TX Vref=36, minBit 2, minWin=23, winSum=387
7678 00:56:06.569858 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
7679 00:56:06.569945
7680 00:56:06.572662 Final TX Range 0 Vref 28
7681 00:56:06.572748
7682 00:56:06.572849 ==
7683 00:56:06.575923 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 00:56:06.579216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 00:56:06.582582 ==
7686 00:56:06.582670
7687 00:56:06.582735
7688 00:56:06.582799 TX Vref Scan disable
7689 00:56:06.589656 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7690 00:56:06.589742 == TX Byte 0 ==
7691 00:56:06.592547 u2DelayCellOfst[0]=14 cells (4 PI)
7692 00:56:06.596060 u2DelayCellOfst[1]=17 cells (5 PI)
7693 00:56:06.599247 u2DelayCellOfst[2]=14 cells (4 PI)
7694 00:56:06.602478 u2DelayCellOfst[3]=14 cells (4 PI)
7695 00:56:06.605897 u2DelayCellOfst[4]=10 cells (3 PI)
7696 00:56:06.609536 u2DelayCellOfst[5]=0 cells (0 PI)
7697 00:56:06.612488 u2DelayCellOfst[6]=17 cells (5 PI)
7698 00:56:06.616508 u2DelayCellOfst[7]=17 cells (5 PI)
7699 00:56:06.619211 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7700 00:56:06.622600 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7701 00:56:06.625806 == TX Byte 1 ==
7702 00:56:06.629232 u2DelayCellOfst[8]=0 cells (0 PI)
7703 00:56:06.632482 u2DelayCellOfst[9]=0 cells (0 PI)
7704 00:56:06.635756 u2DelayCellOfst[10]=3 cells (1 PI)
7705 00:56:06.639322 u2DelayCellOfst[11]=0 cells (0 PI)
7706 00:56:06.642657 u2DelayCellOfst[12]=10 cells (3 PI)
7707 00:56:06.645565 u2DelayCellOfst[13]=10 cells (3 PI)
7708 00:56:06.645660 u2DelayCellOfst[14]=14 cells (4 PI)
7709 00:56:06.649277 u2DelayCellOfst[15]=10 cells (3 PI)
7710 00:56:06.655360 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7711 00:56:06.658893 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7712 00:56:06.662120 DramC Write-DBI on
7713 00:56:06.662214 ==
7714 00:56:06.665698 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 00:56:06.668761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 00:56:06.668857 ==
7717 00:56:06.668952
7718 00:56:06.669041
7719 00:56:06.671954 TX Vref Scan disable
7720 00:56:06.672048 == TX Byte 0 ==
7721 00:56:06.678581 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
7722 00:56:06.678668 == TX Byte 1 ==
7723 00:56:06.682438 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7724 00:56:06.685035 DramC Write-DBI off
7725 00:56:06.685121
7726 00:56:06.685221 [DATLAT]
7727 00:56:06.688453 Freq=1600, CH0 RK0
7728 00:56:06.688564
7729 00:56:06.688656 DATLAT Default: 0xf
7730 00:56:06.692248 0, 0xFFFF, sum = 0
7731 00:56:06.692330 1, 0xFFFF, sum = 0
7732 00:56:06.695246 2, 0xFFFF, sum = 0
7733 00:56:06.698430 3, 0xFFFF, sum = 0
7734 00:56:06.698512 4, 0xFFFF, sum = 0
7735 00:56:06.701933 5, 0xFFFF, sum = 0
7736 00:56:06.702018 6, 0xFFFF, sum = 0
7737 00:56:06.705105 7, 0xFFFF, sum = 0
7738 00:56:06.705189 8, 0xFFFF, sum = 0
7739 00:56:06.708115 9, 0xFFFF, sum = 0
7740 00:56:06.708199 10, 0xFFFF, sum = 0
7741 00:56:06.711459 11, 0xFFFF, sum = 0
7742 00:56:06.711543 12, 0xFFFF, sum = 0
7743 00:56:06.714928 13, 0xFFFF, sum = 0
7744 00:56:06.715014 14, 0x0, sum = 1
7745 00:56:06.718166 15, 0x0, sum = 2
7746 00:56:06.718251 16, 0x0, sum = 3
7747 00:56:06.721213 17, 0x0, sum = 4
7748 00:56:06.721347 best_step = 15
7749 00:56:06.721430
7750 00:56:06.721509 ==
7751 00:56:06.724848 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 00:56:06.731607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 00:56:06.731711 ==
7754 00:56:06.731816 RX Vref Scan: 1
7755 00:56:06.731919
7756 00:56:06.734766 Set Vref Range= 24 -> 127
7757 00:56:06.734886
7758 00:56:06.737889 RX Vref 24 -> 127, step: 1
7759 00:56:06.737999
7760 00:56:06.738084 RX Delay 11 -> 252, step: 4
7761 00:56:06.741222
7762 00:56:06.741350 Set Vref, RX VrefLevel [Byte0]: 24
7763 00:56:06.744435 [Byte1]: 24
7764 00:56:06.748811
7765 00:56:06.748977 Set Vref, RX VrefLevel [Byte0]: 25
7766 00:56:06.752152 [Byte1]: 25
7767 00:56:06.756418
7768 00:56:06.756579 Set Vref, RX VrefLevel [Byte0]: 26
7769 00:56:06.759629 [Byte1]: 26
7770 00:56:06.764254
7771 00:56:06.764414 Set Vref, RX VrefLevel [Byte0]: 27
7772 00:56:06.767715 [Byte1]: 27
7773 00:56:06.771711
7774 00:56:06.771840 Set Vref, RX VrefLevel [Byte0]: 28
7775 00:56:06.774650 [Byte1]: 28
7776 00:56:06.779678
7777 00:56:06.779794 Set Vref, RX VrefLevel [Byte0]: 29
7778 00:56:06.782374 [Byte1]: 29
7779 00:56:06.787411
7780 00:56:06.787510 Set Vref, RX VrefLevel [Byte0]: 30
7781 00:56:06.789969 [Byte1]: 30
7782 00:56:06.794435
7783 00:56:06.794516 Set Vref, RX VrefLevel [Byte0]: 31
7784 00:56:06.798038 [Byte1]: 31
7785 00:56:06.802157
7786 00:56:06.802238 Set Vref, RX VrefLevel [Byte0]: 32
7787 00:56:06.805450 [Byte1]: 32
7788 00:56:06.809633
7789 00:56:06.809714 Set Vref, RX VrefLevel [Byte0]: 33
7790 00:56:06.813074 [Byte1]: 33
7791 00:56:06.817382
7792 00:56:06.817463 Set Vref, RX VrefLevel [Byte0]: 34
7793 00:56:06.820785 [Byte1]: 34
7794 00:56:06.824758
7795 00:56:06.824839 Set Vref, RX VrefLevel [Byte0]: 35
7796 00:56:06.828191 [Byte1]: 35
7797 00:56:06.832824
7798 00:56:06.832932 Set Vref, RX VrefLevel [Byte0]: 36
7799 00:56:06.835637 [Byte1]: 36
7800 00:56:06.840153
7801 00:56:06.840233 Set Vref, RX VrefLevel [Byte0]: 37
7802 00:56:06.843801 [Byte1]: 37
7803 00:56:06.847641
7804 00:56:06.847722 Set Vref, RX VrefLevel [Byte0]: 38
7805 00:56:06.850927 [Byte1]: 38
7806 00:56:06.855331
7807 00:56:06.855442 Set Vref, RX VrefLevel [Byte0]: 39
7808 00:56:06.858547 [Byte1]: 39
7809 00:56:06.863105
7810 00:56:06.863185 Set Vref, RX VrefLevel [Byte0]: 40
7811 00:56:06.866529 [Byte1]: 40
7812 00:56:06.870758
7813 00:56:06.870838 Set Vref, RX VrefLevel [Byte0]: 41
7814 00:56:06.874025 [Byte1]: 41
7815 00:56:06.878252
7816 00:56:06.878338 Set Vref, RX VrefLevel [Byte0]: 42
7817 00:56:06.881618 [Byte1]: 42
7818 00:56:06.885722
7819 00:56:06.885814 Set Vref, RX VrefLevel [Byte0]: 43
7820 00:56:06.889574 [Byte1]: 43
7821 00:56:06.893489
7822 00:56:06.893598 Set Vref, RX VrefLevel [Byte0]: 44
7823 00:56:06.896755 [Byte1]: 44
7824 00:56:06.901222
7825 00:56:06.901360 Set Vref, RX VrefLevel [Byte0]: 45
7826 00:56:06.905145 [Byte1]: 45
7827 00:56:06.908761
7828 00:56:06.908930 Set Vref, RX VrefLevel [Byte0]: 46
7829 00:56:06.912392 [Byte1]: 46
7830 00:56:06.916152
7831 00:56:06.916376 Set Vref, RX VrefLevel [Byte0]: 47
7832 00:56:06.919802 [Byte1]: 47
7833 00:56:06.924500
7834 00:56:06.924734 Set Vref, RX VrefLevel [Byte0]: 48
7835 00:56:06.927158 [Byte1]: 48
7836 00:56:06.932129
7837 00:56:06.932501 Set Vref, RX VrefLevel [Byte0]: 49
7838 00:56:06.934968 [Byte1]: 49
7839 00:56:06.940025
7840 00:56:06.940436 Set Vref, RX VrefLevel [Byte0]: 50
7841 00:56:06.942512 [Byte1]: 50
7842 00:56:06.946999
7843 00:56:06.947409 Set Vref, RX VrefLevel [Byte0]: 51
7844 00:56:06.950572 [Byte1]: 51
7845 00:56:06.954540
7846 00:56:06.954929 Set Vref, RX VrefLevel [Byte0]: 52
7847 00:56:06.958334 [Byte1]: 52
7848 00:56:06.962482
7849 00:56:06.962896 Set Vref, RX VrefLevel [Byte0]: 53
7850 00:56:06.965781 [Byte1]: 53
7851 00:56:06.970577
7852 00:56:06.970985 Set Vref, RX VrefLevel [Byte0]: 54
7853 00:56:06.973309 [Byte1]: 54
7854 00:56:06.977477
7855 00:56:06.977887 Set Vref, RX VrefLevel [Byte0]: 55
7856 00:56:06.981159 [Byte1]: 55
7857 00:56:06.985069
7858 00:56:06.985522 Set Vref, RX VrefLevel [Byte0]: 56
7859 00:56:06.988330 [Byte1]: 56
7860 00:56:06.992965
7861 00:56:06.993414 Set Vref, RX VrefLevel [Byte0]: 57
7862 00:56:06.995843 [Byte1]: 57
7863 00:56:07.000171
7864 00:56:07.000581 Set Vref, RX VrefLevel [Byte0]: 58
7865 00:56:07.003881 [Byte1]: 58
7866 00:56:07.007805
7867 00:56:07.008235 Set Vref, RX VrefLevel [Byte0]: 59
7868 00:56:07.011260 [Byte1]: 59
7869 00:56:07.015430
7870 00:56:07.015868 Set Vref, RX VrefLevel [Byte0]: 60
7871 00:56:07.019471 [Byte1]: 60
7872 00:56:07.023419
7873 00:56:07.023828 Set Vref, RX VrefLevel [Byte0]: 61
7874 00:56:07.026370 [Byte1]: 61
7875 00:56:07.030494
7876 00:56:07.030964 Set Vref, RX VrefLevel [Byte0]: 62
7877 00:56:07.034030 [Byte1]: 62
7878 00:56:07.038463
7879 00:56:07.038688 Set Vref, RX VrefLevel [Byte0]: 63
7880 00:56:07.041677 [Byte1]: 63
7881 00:56:07.045826
7882 00:56:07.046006 Set Vref, RX VrefLevel [Byte0]: 64
7883 00:56:07.048867 [Byte1]: 64
7884 00:56:07.053522
7885 00:56:07.053656 Set Vref, RX VrefLevel [Byte0]: 65
7886 00:56:07.056776 [Byte1]: 65
7887 00:56:07.061029
7888 00:56:07.061178 Set Vref, RX VrefLevel [Byte0]: 66
7889 00:56:07.064186 [Byte1]: 66
7890 00:56:07.068835
7891 00:56:07.068925 Set Vref, RX VrefLevel [Byte0]: 67
7892 00:56:07.071844 [Byte1]: 67
7893 00:56:07.076365
7894 00:56:07.076455 Set Vref, RX VrefLevel [Byte0]: 68
7895 00:56:07.079776 [Byte1]: 68
7896 00:56:07.083848
7897 00:56:07.083938 Set Vref, RX VrefLevel [Byte0]: 69
7898 00:56:07.087034 [Byte1]: 69
7899 00:56:07.091502
7900 00:56:07.091592 Set Vref, RX VrefLevel [Byte0]: 70
7901 00:56:07.094811 [Byte1]: 70
7902 00:56:07.099212
7903 00:56:07.099309 Set Vref, RX VrefLevel [Byte0]: 71
7904 00:56:07.102138 [Byte1]: 71
7905 00:56:07.106775
7906 00:56:07.106929 Set Vref, RX VrefLevel [Byte0]: 72
7907 00:56:07.109858 [Byte1]: 72
7908 00:56:07.114335
7909 00:56:07.114505 Set Vref, RX VrefLevel [Byte0]: 73
7910 00:56:07.118264 [Byte1]: 73
7911 00:56:07.121839
7912 00:56:07.121999 Set Vref, RX VrefLevel [Byte0]: 74
7913 00:56:07.125275 [Byte1]: 74
7914 00:56:07.129458
7915 00:56:07.129645 Set Vref, RX VrefLevel [Byte0]: 75
7916 00:56:07.132910 [Byte1]: 75
7917 00:56:07.137182
7918 00:56:07.137481 Set Vref, RX VrefLevel [Byte0]: 76
7919 00:56:07.140627 [Byte1]: 76
7920 00:56:07.145235
7921 00:56:07.145612 Final RX Vref Byte 0 = 54 to rank0
7922 00:56:07.148434 Final RX Vref Byte 1 = 55 to rank0
7923 00:56:07.151614 Final RX Vref Byte 0 = 54 to rank1
7924 00:56:07.155280 Final RX Vref Byte 1 = 55 to rank1==
7925 00:56:07.158259 Dram Type= 6, Freq= 0, CH_0, rank 0
7926 00:56:07.164942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7927 00:56:07.165412 ==
7928 00:56:07.165752 DQS Delay:
7929 00:56:07.168001 DQS0 = 0, DQS1 = 0
7930 00:56:07.168414 DQM Delay:
7931 00:56:07.168740 DQM0 = 128, DQM1 = 125
7932 00:56:07.171822 DQ Delay:
7933 00:56:07.174634 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7934 00:56:07.178031 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
7935 00:56:07.181191 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
7936 00:56:07.184347 DQ12 =132, DQ13 =130, DQ14 =134, DQ15 =132
7937 00:56:07.184767
7938 00:56:07.185095
7939 00:56:07.185439
7940 00:56:07.188182 [DramC_TX_OE_Calibration] TA2
7941 00:56:07.191242 Original DQ_B0 (3 6) =30, OEN = 27
7942 00:56:07.194641 Original DQ_B1 (3 6) =30, OEN = 27
7943 00:56:07.197363 24, 0x0, End_B0=24 End_B1=24
7944 00:56:07.201041 25, 0x0, End_B0=25 End_B1=25
7945 00:56:07.201650 26, 0x0, End_B0=26 End_B1=26
7946 00:56:07.204264 27, 0x0, End_B0=27 End_B1=27
7947 00:56:07.207656 28, 0x0, End_B0=28 End_B1=28
7948 00:56:07.211344 29, 0x0, End_B0=29 End_B1=29
7949 00:56:07.211782 30, 0x0, End_B0=30 End_B1=30
7950 00:56:07.214215 31, 0x4141, End_B0=30 End_B1=30
7951 00:56:07.217295 Byte0 end_step=30 best_step=27
7952 00:56:07.220603 Byte1 end_step=30 best_step=27
7953 00:56:07.224265 Byte0 TX OE(2T, 0.5T) = (3, 3)
7954 00:56:07.227345 Byte1 TX OE(2T, 0.5T) = (3, 3)
7955 00:56:07.227760
7956 00:56:07.228092
7957 00:56:07.233643 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7958 00:56:07.236888 CH0 RK0: MR19=303, MR18=1A17
7959 00:56:07.243968 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
7960 00:56:07.244206
7961 00:56:07.246791 ----->DramcWriteLeveling(PI) begin...
7962 00:56:07.247025 ==
7963 00:56:07.250445 Dram Type= 6, Freq= 0, CH_0, rank 1
7964 00:56:07.253467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 00:56:07.253693 ==
7966 00:56:07.256993 Write leveling (Byte 0): 33 => 33
7967 00:56:07.260266 Write leveling (Byte 1): 29 => 29
7968 00:56:07.263488 DramcWriteLeveling(PI) end<-----
7969 00:56:07.263710
7970 00:56:07.263887 ==
7971 00:56:07.266765 Dram Type= 6, Freq= 0, CH_0, rank 1
7972 00:56:07.270205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 00:56:07.273506 ==
7974 00:56:07.273780 [Gating] SW mode calibration
7975 00:56:07.283382 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7976 00:56:07.286781 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7977 00:56:07.289763 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 00:56:07.296614 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7979 00:56:07.299907 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7980 00:56:07.303042 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7981 00:56:07.309515 1 4 16 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7982 00:56:07.312686 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7983 00:56:07.316126 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7984 00:56:07.323464 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 00:56:07.326153 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 00:56:07.329497 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 00:56:07.336163 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7988 00:56:07.339644 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7989 00:56:07.342475 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7990 00:56:07.349348 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
7991 00:56:07.352354 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 00:56:07.356089 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 00:56:07.362774 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 00:56:07.366465 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 00:56:07.369992 1 6 8 | B1->B0 | 2323 3e3e | 0 1 | (0 0) (0 0)
7996 00:56:07.375486 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7997 00:56:07.379005 1 6 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7998 00:56:07.382136 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7999 00:56:07.388517 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 00:56:07.391903 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 00:56:07.395742 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 00:56:07.401745 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8003 00:56:07.405229 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8004 00:56:07.408770 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8005 00:56:07.415057 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8006 00:56:07.418216 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8007 00:56:07.421920 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 00:56:07.428318 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 00:56:07.431782 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 00:56:07.438113 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 00:56:07.441842 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 00:56:07.444607 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 00:56:07.448091 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 00:56:07.454875 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 00:56:07.458301 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 00:56:07.461583 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 00:56:07.467894 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 00:56:07.471589 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 00:56:07.474949 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8020 00:56:07.481046 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8021 00:56:07.484550 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8022 00:56:07.487967 Total UI for P1: 0, mck2ui 16
8023 00:56:07.491275 best dqsien dly found for B0: ( 1, 9, 10)
8024 00:56:07.494518 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8025 00:56:07.501054 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 00:56:07.501510 Total UI for P1: 0, mck2ui 16
8027 00:56:07.507942 best dqsien dly found for B1: ( 1, 9, 18)
8028 00:56:07.510980 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8029 00:56:07.514233 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8030 00:56:07.514648
8031 00:56:07.517384 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8032 00:56:07.520579 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8033 00:56:07.524191 [Gating] SW calibration Done
8034 00:56:07.524644 ==
8035 00:56:07.527320 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 00:56:07.530622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 00:56:07.531039 ==
8038 00:56:07.534358 RX Vref Scan: 0
8039 00:56:07.534745
8040 00:56:07.537440 RX Vref 0 -> 0, step: 1
8041 00:56:07.537830
8042 00:56:07.538274 RX Delay 0 -> 252, step: 8
8043 00:56:07.544018 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8044 00:56:07.547756 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
8045 00:56:07.550629 iDelay=192, Bit 2, Center 131 (80 ~ 183) 104
8046 00:56:07.553899 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8047 00:56:07.557087 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8048 00:56:07.563985 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8049 00:56:07.567167 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8050 00:56:07.570577 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
8051 00:56:07.573768 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
8052 00:56:07.577182 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
8053 00:56:07.583566 iDelay=192, Bit 10, Center 127 (72 ~ 183) 112
8054 00:56:07.587004 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
8055 00:56:07.590625 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
8056 00:56:07.594118 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
8057 00:56:07.599938 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8058 00:56:07.603294 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
8059 00:56:07.603709 ==
8060 00:56:07.606363 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 00:56:07.609974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 00:56:07.610391 ==
8063 00:56:07.613048 DQS Delay:
8064 00:56:07.613573 DQS0 = 0, DQS1 = 0
8065 00:56:07.613907 DQM Delay:
8066 00:56:07.616352 DQM0 = 131, DQM1 = 125
8067 00:56:07.616802 DQ Delay:
8068 00:56:07.619953 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8069 00:56:07.623089 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8070 00:56:07.626755 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8071 00:56:07.632763 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8072 00:56:07.633322
8073 00:56:07.633672
8074 00:56:07.633975 ==
8075 00:56:07.635852 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 00:56:07.639498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 00:56:07.640020 ==
8078 00:56:07.640437
8079 00:56:07.640747
8080 00:56:07.642461 TX Vref Scan disable
8081 00:56:07.645745 == TX Byte 0 ==
8082 00:56:07.649350 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8083 00:56:07.652496 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8084 00:56:07.656119 == TX Byte 1 ==
8085 00:56:07.659152 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8086 00:56:07.662510 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8087 00:56:07.662940 ==
8088 00:56:07.665757 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 00:56:07.668865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 00:56:07.672031 ==
8091 00:56:07.684489
8092 00:56:07.688193 TX Vref early break, caculate TX vref
8093 00:56:07.691593 TX Vref=16, minBit 9, minWin=22, winSum=383
8094 00:56:07.694519 TX Vref=18, minBit 9, minWin=23, winSum=390
8095 00:56:07.697908 TX Vref=20, minBit 1, minWin=24, winSum=397
8096 00:56:07.701697 TX Vref=22, minBit 1, minWin=25, winSum=411
8097 00:56:07.704452 TX Vref=24, minBit 1, minWin=25, winSum=411
8098 00:56:07.710672 TX Vref=26, minBit 1, minWin=25, winSum=421
8099 00:56:07.714360 TX Vref=28, minBit 0, minWin=26, winSum=424
8100 00:56:07.717967 TX Vref=30, minBit 1, minWin=25, winSum=417
8101 00:56:07.720842 TX Vref=32, minBit 0, minWin=25, winSum=409
8102 00:56:07.724331 TX Vref=34, minBit 1, minWin=24, winSum=402
8103 00:56:07.727917 TX Vref=36, minBit 0, minWin=24, winSum=390
8104 00:56:07.733975 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8105 00:56:07.734523
8106 00:56:07.737303 Final TX Range 0 Vref 28
8107 00:56:07.738096
8108 00:56:07.738462 ==
8109 00:56:07.740508 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 00:56:07.744459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 00:56:07.744908 ==
8112 00:56:07.747516
8113 00:56:07.748020
8114 00:56:07.748356 TX Vref Scan disable
8115 00:56:07.754130 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8116 00:56:07.754606 == TX Byte 0 ==
8117 00:56:07.757515 u2DelayCellOfst[0]=10 cells (3 PI)
8118 00:56:07.760433 u2DelayCellOfst[1]=10 cells (3 PI)
8119 00:56:07.764317 u2DelayCellOfst[2]=7 cells (2 PI)
8120 00:56:07.767817 u2DelayCellOfst[3]=10 cells (3 PI)
8121 00:56:07.771183 u2DelayCellOfst[4]=3 cells (1 PI)
8122 00:56:07.774249 u2DelayCellOfst[5]=0 cells (0 PI)
8123 00:56:07.777526 u2DelayCellOfst[6]=14 cells (4 PI)
8124 00:56:07.780591 u2DelayCellOfst[7]=14 cells (4 PI)
8125 00:56:07.784026 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8126 00:56:07.787482 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8127 00:56:07.790191 == TX Byte 1 ==
8128 00:56:07.793874 u2DelayCellOfst[8]=0 cells (0 PI)
8129 00:56:07.796758 u2DelayCellOfst[9]=0 cells (0 PI)
8130 00:56:07.800273 u2DelayCellOfst[10]=3 cells (1 PI)
8131 00:56:07.804060 u2DelayCellOfst[11]=0 cells (0 PI)
8132 00:56:07.804505 u2DelayCellOfst[12]=10 cells (3 PI)
8133 00:56:07.807442 u2DelayCellOfst[13]=10 cells (3 PI)
8134 00:56:07.810341 u2DelayCellOfst[14]=14 cells (4 PI)
8135 00:56:07.813755 u2DelayCellOfst[15]=10 cells (3 PI)
8136 00:56:07.820032 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8137 00:56:07.823286 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8138 00:56:07.826601 DramC Write-DBI on
8139 00:56:07.827110 ==
8140 00:56:07.830059 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 00:56:07.833290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 00:56:07.833824 ==
8143 00:56:07.834163
8144 00:56:07.834488
8145 00:56:07.836404 TX Vref Scan disable
8146 00:56:07.836856 == TX Byte 0 ==
8147 00:56:07.843053 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8148 00:56:07.843548 == TX Byte 1 ==
8149 00:56:07.846331 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8150 00:56:07.849828 DramC Write-DBI off
8151 00:56:07.850373
8152 00:56:07.850740 [DATLAT]
8153 00:56:07.853363 Freq=1600, CH0 RK1
8154 00:56:07.853790
8155 00:56:07.854139 DATLAT Default: 0xf
8156 00:56:07.856819 0, 0xFFFF, sum = 0
8157 00:56:07.857247 1, 0xFFFF, sum = 0
8158 00:56:07.859577 2, 0xFFFF, sum = 0
8159 00:56:07.860003 3, 0xFFFF, sum = 0
8160 00:56:07.863009 4, 0xFFFF, sum = 0
8161 00:56:07.866358 5, 0xFFFF, sum = 0
8162 00:56:07.866787 6, 0xFFFF, sum = 0
8163 00:56:07.869678 7, 0xFFFF, sum = 0
8164 00:56:07.870132 8, 0xFFFF, sum = 0
8165 00:56:07.872528 9, 0xFFFF, sum = 0
8166 00:56:07.873034 10, 0xFFFF, sum = 0
8167 00:56:07.876127 11, 0xFFFF, sum = 0
8168 00:56:07.876604 12, 0xFFFF, sum = 0
8169 00:56:07.879245 13, 0xFFFF, sum = 0
8170 00:56:07.879736 14, 0x0, sum = 1
8171 00:56:07.882929 15, 0x0, sum = 2
8172 00:56:07.883508 16, 0x0, sum = 3
8173 00:56:07.885803 17, 0x0, sum = 4
8174 00:56:07.886260 best_step = 15
8175 00:56:07.886682
8176 00:56:07.887057 ==
8177 00:56:07.889833 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 00:56:07.892649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 00:56:07.896087 ==
8180 00:56:07.896545 RX Vref Scan: 0
8181 00:56:07.896939
8182 00:56:07.899044 RX Vref 0 -> 0, step: 1
8183 00:56:07.899480
8184 00:56:07.902771 RX Delay 11 -> 252, step: 4
8185 00:56:07.905770 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8186 00:56:07.909254 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8187 00:56:07.912186 iDelay=191, Bit 2, Center 126 (75 ~ 178) 104
8188 00:56:07.918886 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8189 00:56:07.921995 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8190 00:56:07.925349 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8191 00:56:07.928637 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8192 00:56:07.932333 iDelay=191, Bit 7, Center 136 (87 ~ 186) 100
8193 00:56:07.938608 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8194 00:56:07.941952 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8195 00:56:07.945033 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8196 00:56:07.948623 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8197 00:56:07.955503 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8198 00:56:07.958158 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8199 00:56:07.961704 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8200 00:56:07.965371 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8201 00:56:07.965786 ==
8202 00:56:07.968116 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 00:56:07.975040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 00:56:07.975459 ==
8205 00:56:07.975787 DQS Delay:
8206 00:56:07.976094 DQS0 = 0, DQS1 = 0
8207 00:56:07.977883 DQM Delay:
8208 00:56:07.978294 DQM0 = 129, DQM1 = 124
8209 00:56:07.981615 DQ Delay:
8210 00:56:07.984784 DQ0 =126, DQ1 =130, DQ2 =126, DQ3 =126
8211 00:56:07.987942 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
8212 00:56:07.991165 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8213 00:56:07.994603 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8214 00:56:07.995018
8215 00:56:07.995348
8216 00:56:07.995655
8217 00:56:07.998137 [DramC_TX_OE_Calibration] TA2
8218 00:56:08.000862 Original DQ_B0 (3 6) =30, OEN = 27
8219 00:56:08.004727 Original DQ_B1 (3 6) =30, OEN = 27
8220 00:56:08.007834 24, 0x0, End_B0=24 End_B1=24
8221 00:56:08.008337 25, 0x0, End_B0=25 End_B1=25
8222 00:56:08.011203 26, 0x0, End_B0=26 End_B1=26
8223 00:56:08.014327 27, 0x0, End_B0=27 End_B1=27
8224 00:56:08.017460 28, 0x0, End_B0=28 End_B1=28
8225 00:56:08.021417 29, 0x0, End_B0=29 End_B1=29
8226 00:56:08.021854 30, 0x0, End_B0=30 End_B1=30
8227 00:56:08.024048 31, 0x4141, End_B0=30 End_B1=30
8228 00:56:08.028227 Byte0 end_step=30 best_step=27
8229 00:56:08.030828 Byte1 end_step=30 best_step=27
8230 00:56:08.034309 Byte0 TX OE(2T, 0.5T) = (3, 3)
8231 00:56:08.037330 Byte1 TX OE(2T, 0.5T) = (3, 3)
8232 00:56:08.037778
8233 00:56:08.038113
8234 00:56:08.044186 [DQSOSCAuto] RK1, (LSB)MR18= 0x1514, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8235 00:56:08.047633 CH0 RK1: MR19=303, MR18=1514
8236 00:56:08.053772 CH0_RK1: MR19=0x303, MR18=0x1514, DQSOSC=399, MR23=63, INC=23, DEC=15
8237 00:56:08.057393 [RxdqsGatingPostProcess] freq 1600
8238 00:56:08.060526 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8239 00:56:08.063756 best DQS0 dly(2T, 0.5T) = (1, 1)
8240 00:56:08.067017 best DQS1 dly(2T, 0.5T) = (1, 1)
8241 00:56:08.070341 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8242 00:56:08.073695 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8243 00:56:08.077129 best DQS0 dly(2T, 0.5T) = (1, 1)
8244 00:56:08.080200 best DQS1 dly(2T, 0.5T) = (1, 1)
8245 00:56:08.083199 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8246 00:56:08.087214 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8247 00:56:08.090404 Pre-setting of DQS Precalculation
8248 00:56:08.093664 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8249 00:56:08.094150 ==
8250 00:56:08.097074 Dram Type= 6, Freq= 0, CH_1, rank 0
8251 00:56:08.103643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 00:56:08.104089 ==
8253 00:56:08.106617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8254 00:56:08.113139 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8255 00:56:08.116786 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8256 00:56:08.123364 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8257 00:56:08.131074 [CA 0] Center 42 (13~72) winsize 60
8258 00:56:08.134498 [CA 1] Center 42 (12~73) winsize 62
8259 00:56:08.137693 [CA 2] Center 39 (9~69) winsize 61
8260 00:56:08.141184 [CA 3] Center 38 (8~68) winsize 61
8261 00:56:08.144082 [CA 4] Center 38 (8~69) winsize 62
8262 00:56:08.147203 [CA 5] Center 37 (7~67) winsize 61
8263 00:56:08.147629
8264 00:56:08.150414 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8265 00:56:08.150833
8266 00:56:08.157670 [CATrainingPosCal] consider 1 rank data
8267 00:56:08.158089 u2DelayCellTimex100 = 275/100 ps
8268 00:56:08.163534 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8269 00:56:08.167241 CA1 delay=42 (12~73),Diff = 5 PI (17 cell)
8270 00:56:08.170268 CA2 delay=39 (9~69),Diff = 2 PI (7 cell)
8271 00:56:08.173713 CA3 delay=38 (8~68),Diff = 1 PI (3 cell)
8272 00:56:08.177204 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8273 00:56:08.180543 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8274 00:56:08.180995
8275 00:56:08.183507 CA PerBit enable=1, Macro0, CA PI delay=37
8276 00:56:08.183954
8277 00:56:08.187054 [CBTSetCACLKResult] CA Dly = 37
8278 00:56:08.190419 CS Dly: 8 (0~39)
8279 00:56:08.193592 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8280 00:56:08.197060 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8281 00:56:08.197555 ==
8282 00:56:08.199919 Dram Type= 6, Freq= 0, CH_1, rank 1
8283 00:56:08.207011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 00:56:08.207460 ==
8285 00:56:08.210168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8286 00:56:08.216251 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8287 00:56:08.219960 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8288 00:56:08.226237 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8289 00:56:08.234188 [CA 0] Center 42 (12~72) winsize 61
8290 00:56:08.237403 [CA 1] Center 43 (13~73) winsize 61
8291 00:56:08.240856 [CA 2] Center 38 (9~68) winsize 60
8292 00:56:08.243998 [CA 3] Center 37 (8~67) winsize 60
8293 00:56:08.247367 [CA 4] Center 37 (8~67) winsize 60
8294 00:56:08.250655 [CA 5] Center 37 (7~67) winsize 61
8295 00:56:08.251071
8296 00:56:08.253960 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8297 00:56:08.254377
8298 00:56:08.257221 [CATrainingPosCal] consider 2 rank data
8299 00:56:08.260313 u2DelayCellTimex100 = 275/100 ps
8300 00:56:08.267528 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8301 00:56:08.270123 CA1 delay=43 (13~73),Diff = 6 PI (21 cell)
8302 00:56:08.274068 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8303 00:56:08.276761 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8304 00:56:08.280170 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8305 00:56:08.283334 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8306 00:56:08.283750
8307 00:56:08.287192 CA PerBit enable=1, Macro0, CA PI delay=37
8308 00:56:08.287662
8309 00:56:08.290048 [CBTSetCACLKResult] CA Dly = 37
8310 00:56:08.293293 CS Dly: 10 (0~43)
8311 00:56:08.296739 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8312 00:56:08.299690 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8313 00:56:08.300107
8314 00:56:08.303155 ----->DramcWriteLeveling(PI) begin...
8315 00:56:08.303578 ==
8316 00:56:08.306561 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 00:56:08.313373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 00:56:08.313795 ==
8319 00:56:08.316713 Write leveling (Byte 0): 25 => 25
8320 00:56:08.320169 Write leveling (Byte 1): 25 => 25
8321 00:56:08.320591 DramcWriteLeveling(PI) end<-----
8322 00:56:08.323131
8323 00:56:08.323543 ==
8324 00:56:08.326436 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 00:56:08.329698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 00:56:08.330119 ==
8327 00:56:08.332989 [Gating] SW mode calibration
8328 00:56:08.339711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8329 00:56:08.342981 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8330 00:56:08.349291 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 00:56:08.353008 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 00:56:08.356238 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 00:56:08.362611 1 4 12 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
8334 00:56:08.366099 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 00:56:08.369217 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 00:56:08.376373 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 00:56:08.379266 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 00:56:08.382746 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 00:56:08.389056 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 00:56:08.392521 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8341 00:56:08.395710 1 5 12 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
8342 00:56:08.402470 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 00:56:08.405566 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 00:56:08.408734 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 00:56:08.415303 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 00:56:08.418568 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 00:56:08.421985 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 00:56:08.428568 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8349 00:56:08.431938 1 6 12 | B1->B0 | 2a2a 4545 | 1 0 | (0 0) (0 0)
8350 00:56:08.435114 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 00:56:08.441914 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 00:56:08.445073 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 00:56:08.448336 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 00:56:08.455403 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 00:56:08.458083 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 00:56:08.462116 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8357 00:56:08.468410 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8358 00:56:08.471414 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8359 00:56:08.474577 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 00:56:08.481763 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 00:56:08.484732 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 00:56:08.488029 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 00:56:08.494615 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 00:56:08.498079 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 00:56:08.501000 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 00:56:08.507640 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 00:56:08.511000 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 00:56:08.514127 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 00:56:08.521307 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 00:56:08.524098 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 00:56:08.527715 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 00:56:08.534441 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8373 00:56:08.537337 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8374 00:56:08.540457 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8375 00:56:08.543854 Total UI for P1: 0, mck2ui 16
8376 00:56:08.546901 best dqsien dly found for B0: ( 1, 9, 10)
8377 00:56:08.553820 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 00:56:08.556960 Total UI for P1: 0, mck2ui 16
8379 00:56:08.560522 best dqsien dly found for B1: ( 1, 9, 12)
8380 00:56:08.563806 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8381 00:56:08.567263 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8382 00:56:08.567676
8383 00:56:08.570488 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8384 00:56:08.573806 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8385 00:56:08.576822 [Gating] SW calibration Done
8386 00:56:08.577298 ==
8387 00:56:08.580208 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 00:56:08.583798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 00:56:08.584276 ==
8390 00:56:08.586721 RX Vref Scan: 0
8391 00:56:08.587132
8392 00:56:08.590339 RX Vref 0 -> 0, step: 1
8393 00:56:08.590798
8394 00:56:08.591153 RX Delay 0 -> 252, step: 8
8395 00:56:08.596640 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8396 00:56:08.599889 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8397 00:56:08.603281 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8398 00:56:08.606621 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8399 00:56:08.609886 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8400 00:56:08.616427 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8401 00:56:08.619849 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8402 00:56:08.623030 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8403 00:56:08.626562 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8404 00:56:08.629569 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8405 00:56:08.636034 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8406 00:56:08.639405 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8407 00:56:08.643091 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8408 00:56:08.646599 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8409 00:56:08.652672 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8410 00:56:08.656279 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8411 00:56:08.656728 ==
8412 00:56:08.659198 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 00:56:08.662771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 00:56:08.663221 ==
8415 00:56:08.666072 DQS Delay:
8416 00:56:08.666482 DQS0 = 0, DQS1 = 0
8417 00:56:08.666844 DQM Delay:
8418 00:56:08.669408 DQM0 = 134, DQM1 = 130
8419 00:56:08.669821 DQ Delay:
8420 00:56:08.672437 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8421 00:56:08.675383 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8422 00:56:08.682107 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8423 00:56:08.685440 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8424 00:56:08.685859
8425 00:56:08.686191
8426 00:56:08.686499 ==
8427 00:56:08.688745 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 00:56:08.692159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 00:56:08.692579 ==
8430 00:56:08.692959
8431 00:56:08.693308
8432 00:56:08.695688 TX Vref Scan disable
8433 00:56:08.698816 == TX Byte 0 ==
8434 00:56:08.702400 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8435 00:56:08.705500 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8436 00:56:08.708802 == TX Byte 1 ==
8437 00:56:08.712218 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8438 00:56:08.715596 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8439 00:56:08.716013 ==
8440 00:56:08.718860 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 00:56:08.721730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 00:56:08.725000 ==
8443 00:56:08.735990
8444 00:56:08.739567 TX Vref early break, caculate TX vref
8445 00:56:08.742613 TX Vref=16, minBit 9, minWin=21, winSum=372
8446 00:56:08.745747 TX Vref=18, minBit 9, minWin=22, winSum=377
8447 00:56:08.749186 TX Vref=20, minBit 8, minWin=23, winSum=387
8448 00:56:08.752119 TX Vref=22, minBit 8, minWin=23, winSum=401
8449 00:56:08.755810 TX Vref=24, minBit 3, minWin=25, winSum=410
8450 00:56:08.762769 TX Vref=26, minBit 8, minWin=24, winSum=413
8451 00:56:08.765707 TX Vref=28, minBit 5, minWin=25, winSum=420
8452 00:56:08.768503 TX Vref=30, minBit 0, minWin=25, winSum=417
8453 00:56:08.771965 TX Vref=32, minBit 0, minWin=24, winSum=405
8454 00:56:08.775160 TX Vref=34, minBit 11, minWin=22, winSum=393
8455 00:56:08.781693 [TxChooseVref] Worse bit 5, Min win 25, Win sum 420, Final Vref 28
8456 00:56:08.782172
8457 00:56:08.784971 Final TX Range 0 Vref 28
8458 00:56:08.785427
8459 00:56:08.785765 ==
8460 00:56:08.788334 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 00:56:08.791818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 00:56:08.792272 ==
8463 00:56:08.792699
8464 00:56:08.795362
8465 00:56:08.795779 TX Vref Scan disable
8466 00:56:08.801750 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8467 00:56:08.802168 == TX Byte 0 ==
8468 00:56:08.804886 u2DelayCellOfst[0]=14 cells (4 PI)
8469 00:56:08.807970 u2DelayCellOfst[1]=10 cells (3 PI)
8470 00:56:08.811458 u2DelayCellOfst[2]=0 cells (0 PI)
8471 00:56:08.814694 u2DelayCellOfst[3]=7 cells (2 PI)
8472 00:56:08.817964 u2DelayCellOfst[4]=10 cells (3 PI)
8473 00:56:08.821253 u2DelayCellOfst[5]=17 cells (5 PI)
8474 00:56:08.824639 u2DelayCellOfst[6]=14 cells (4 PI)
8475 00:56:08.827723 u2DelayCellOfst[7]=7 cells (2 PI)
8476 00:56:08.830921 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8477 00:56:08.834543 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8478 00:56:08.837371 == TX Byte 1 ==
8479 00:56:08.840515 u2DelayCellOfst[8]=0 cells (0 PI)
8480 00:56:08.843885 u2DelayCellOfst[9]=3 cells (1 PI)
8481 00:56:08.847199 u2DelayCellOfst[10]=10 cells (3 PI)
8482 00:56:08.851001 u2DelayCellOfst[11]=3 cells (1 PI)
8483 00:56:08.853706 u2DelayCellOfst[12]=14 cells (4 PI)
8484 00:56:08.857422 u2DelayCellOfst[13]=14 cells (4 PI)
8485 00:56:08.860483 u2DelayCellOfst[14]=17 cells (5 PI)
8486 00:56:08.864061 u2DelayCellOfst[15]=17 cells (5 PI)
8487 00:56:08.867126 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8488 00:56:08.870297 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8489 00:56:08.873441 DramC Write-DBI on
8490 00:56:08.873949 ==
8491 00:56:08.876956 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 00:56:08.880042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 00:56:08.880462 ==
8494 00:56:08.881094
8495 00:56:08.881725
8496 00:56:08.883558 TX Vref Scan disable
8497 00:56:08.883972 == TX Byte 0 ==
8498 00:56:08.889861 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8499 00:56:08.890361 == TX Byte 1 ==
8500 00:56:08.896717 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8501 00:56:08.897139 DramC Write-DBI off
8502 00:56:08.897534
8503 00:56:08.897850 [DATLAT]
8504 00:56:08.899910 Freq=1600, CH1 RK0
8505 00:56:08.900338
8506 00:56:08.903454 DATLAT Default: 0xf
8507 00:56:08.903869 0, 0xFFFF, sum = 0
8508 00:56:08.906343 1, 0xFFFF, sum = 0
8509 00:56:08.906764 2, 0xFFFF, sum = 0
8510 00:56:08.909841 3, 0xFFFF, sum = 0
8511 00:56:08.910262 4, 0xFFFF, sum = 0
8512 00:56:08.913229 5, 0xFFFF, sum = 0
8513 00:56:08.913697 6, 0xFFFF, sum = 0
8514 00:56:08.916064 7, 0xFFFF, sum = 0
8515 00:56:08.916491 8, 0xFFFF, sum = 0
8516 00:56:08.919708 9, 0xFFFF, sum = 0
8517 00:56:08.920132 10, 0xFFFF, sum = 0
8518 00:56:08.923316 11, 0xFFFF, sum = 0
8519 00:56:08.923753 12, 0xFFFF, sum = 0
8520 00:56:08.926631 13, 0xFFFF, sum = 0
8521 00:56:08.927056 14, 0x0, sum = 1
8522 00:56:08.929916 15, 0x0, sum = 2
8523 00:56:08.930343 16, 0x0, sum = 3
8524 00:56:08.933028 17, 0x0, sum = 4
8525 00:56:08.933567 best_step = 15
8526 00:56:08.933927
8527 00:56:08.934249 ==
8528 00:56:08.936389 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 00:56:08.942747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 00:56:08.943192 ==
8531 00:56:08.943529 RX Vref Scan: 1
8532 00:56:08.943840
8533 00:56:08.946330 Set Vref Range= 24 -> 127
8534 00:56:08.946858
8535 00:56:08.949678 RX Vref 24 -> 127, step: 1
8536 00:56:08.950096
8537 00:56:08.952398 RX Delay 19 -> 252, step: 4
8538 00:56:08.952810
8539 00:56:08.955803 Set Vref, RX VrefLevel [Byte0]: 24
8540 00:56:08.959228 [Byte1]: 24
8541 00:56:08.959783
8542 00:56:08.962241 Set Vref, RX VrefLevel [Byte0]: 25
8543 00:56:08.965447 [Byte1]: 25
8544 00:56:08.965870
8545 00:56:08.968652 Set Vref, RX VrefLevel [Byte0]: 26
8546 00:56:08.972024 [Byte1]: 26
8547 00:56:08.975753
8548 00:56:08.976168 Set Vref, RX VrefLevel [Byte0]: 27
8549 00:56:08.979125 [Byte1]: 27
8550 00:56:08.983200
8551 00:56:08.983613 Set Vref, RX VrefLevel [Byte0]: 28
8552 00:56:08.986189 [Byte1]: 28
8553 00:56:08.990686
8554 00:56:08.991128 Set Vref, RX VrefLevel [Byte0]: 29
8555 00:56:08.993856 [Byte1]: 29
8556 00:56:08.998082
8557 00:56:08.998545 Set Vref, RX VrefLevel [Byte0]: 30
8558 00:56:09.001353 [Byte1]: 30
8559 00:56:09.005767
8560 00:56:09.006182 Set Vref, RX VrefLevel [Byte0]: 31
8561 00:56:09.009001 [Byte1]: 31
8562 00:56:09.013478
8563 00:56:09.013909 Set Vref, RX VrefLevel [Byte0]: 32
8564 00:56:09.016923 [Byte1]: 32
8565 00:56:09.020982
8566 00:56:09.021446 Set Vref, RX VrefLevel [Byte0]: 33
8567 00:56:09.024277 [Byte1]: 33
8568 00:56:09.028512
8569 00:56:09.028925 Set Vref, RX VrefLevel [Byte0]: 34
8570 00:56:09.032040 [Byte1]: 34
8571 00:56:09.036376
8572 00:56:09.036793 Set Vref, RX VrefLevel [Byte0]: 35
8573 00:56:09.039214 [Byte1]: 35
8574 00:56:09.043783
8575 00:56:09.044199 Set Vref, RX VrefLevel [Byte0]: 36
8576 00:56:09.046782 [Byte1]: 36
8577 00:56:09.051264
8578 00:56:09.051857 Set Vref, RX VrefLevel [Byte0]: 37
8579 00:56:09.054542 [Byte1]: 37
8580 00:56:09.058569
8581 00:56:09.058984 Set Vref, RX VrefLevel [Byte0]: 38
8582 00:56:09.062238 [Byte1]: 38
8583 00:56:09.066456
8584 00:56:09.066881 Set Vref, RX VrefLevel [Byte0]: 39
8585 00:56:09.069575 [Byte1]: 39
8586 00:56:09.074099
8587 00:56:09.074512 Set Vref, RX VrefLevel [Byte0]: 40
8588 00:56:09.076916 [Byte1]: 40
8589 00:56:09.081361
8590 00:56:09.081777 Set Vref, RX VrefLevel [Byte0]: 41
8591 00:56:09.084649 [Byte1]: 41
8592 00:56:09.089597
8593 00:56:09.090011 Set Vref, RX VrefLevel [Byte0]: 42
8594 00:56:09.092602 [Byte1]: 42
8595 00:56:09.096716
8596 00:56:09.097146 Set Vref, RX VrefLevel [Byte0]: 43
8597 00:56:09.100246 [Byte1]: 43
8598 00:56:09.104006
8599 00:56:09.104470 Set Vref, RX VrefLevel [Byte0]: 44
8600 00:56:09.107929 [Byte1]: 44
8601 00:56:09.111772
8602 00:56:09.112184 Set Vref, RX VrefLevel [Byte0]: 45
8603 00:56:09.115117 [Byte1]: 45
8604 00:56:09.119187
8605 00:56:09.119599 Set Vref, RX VrefLevel [Byte0]: 46
8606 00:56:09.122430 [Byte1]: 46
8607 00:56:09.126743
8608 00:56:09.127156 Set Vref, RX VrefLevel [Byte0]: 47
8609 00:56:09.130082 [Byte1]: 47
8610 00:56:09.134359
8611 00:56:09.134772 Set Vref, RX VrefLevel [Byte0]: 48
8612 00:56:09.137905 [Byte1]: 48
8613 00:56:09.142580
8614 00:56:09.142994 Set Vref, RX VrefLevel [Byte0]: 49
8615 00:56:09.145497 [Byte1]: 49
8616 00:56:09.149751
8617 00:56:09.150166 Set Vref, RX VrefLevel [Byte0]: 50
8618 00:56:09.152995 [Byte1]: 50
8619 00:56:09.157583
8620 00:56:09.157994 Set Vref, RX VrefLevel [Byte0]: 51
8621 00:56:09.160386 [Byte1]: 51
8622 00:56:09.164893
8623 00:56:09.165337 Set Vref, RX VrefLevel [Byte0]: 52
8624 00:56:09.168350 [Byte1]: 52
8625 00:56:09.172472
8626 00:56:09.172887 Set Vref, RX VrefLevel [Byte0]: 53
8627 00:56:09.175471 [Byte1]: 53
8628 00:56:09.179905
8629 00:56:09.180320 Set Vref, RX VrefLevel [Byte0]: 54
8630 00:56:09.183231 [Byte1]: 54
8631 00:56:09.187922
8632 00:56:09.188334 Set Vref, RX VrefLevel [Byte0]: 55
8633 00:56:09.191185 [Byte1]: 55
8634 00:56:09.195064
8635 00:56:09.195483 Set Vref, RX VrefLevel [Byte0]: 56
8636 00:56:09.198175 [Byte1]: 56
8637 00:56:09.202972
8638 00:56:09.203385 Set Vref, RX VrefLevel [Byte0]: 57
8639 00:56:09.205950 [Byte1]: 57
8640 00:56:09.210361
8641 00:56:09.210770 Set Vref, RX VrefLevel [Byte0]: 58
8642 00:56:09.213472 [Byte1]: 58
8643 00:56:09.217857
8644 00:56:09.218272 Set Vref, RX VrefLevel [Byte0]: 59
8645 00:56:09.221562 [Byte1]: 59
8646 00:56:09.225521
8647 00:56:09.225938 Set Vref, RX VrefLevel [Byte0]: 60
8648 00:56:09.228769 [Byte1]: 60
8649 00:56:09.233335
8650 00:56:09.233750 Set Vref, RX VrefLevel [Byte0]: 61
8651 00:56:09.236282 [Byte1]: 61
8652 00:56:09.240811
8653 00:56:09.241327 Set Vref, RX VrefLevel [Byte0]: 62
8654 00:56:09.244098 [Byte1]: 62
8655 00:56:09.248201
8656 00:56:09.248617 Set Vref, RX VrefLevel [Byte0]: 63
8657 00:56:09.251676 [Byte1]: 63
8658 00:56:09.255861
8659 00:56:09.256277 Set Vref, RX VrefLevel [Byte0]: 64
8660 00:56:09.259418 [Byte1]: 64
8661 00:56:09.263157
8662 00:56:09.263568 Set Vref, RX VrefLevel [Byte0]: 65
8663 00:56:09.266379 [Byte1]: 65
8664 00:56:09.270844
8665 00:56:09.271273 Set Vref, RX VrefLevel [Byte0]: 66
8666 00:56:09.274301 [Byte1]: 66
8667 00:56:09.278920
8668 00:56:09.279336 Set Vref, RX VrefLevel [Byte0]: 67
8669 00:56:09.281568 [Byte1]: 67
8670 00:56:09.285773
8671 00:56:09.286188 Set Vref, RX VrefLevel [Byte0]: 68
8672 00:56:09.289587 [Byte1]: 68
8673 00:56:09.293678
8674 00:56:09.294130 Set Vref, RX VrefLevel [Byte0]: 69
8675 00:56:09.297250 [Byte1]: 69
8676 00:56:09.301229
8677 00:56:09.301691 Set Vref, RX VrefLevel [Byte0]: 70
8678 00:56:09.304262 [Byte1]: 70
8679 00:56:09.308447
8680 00:56:09.308866 Set Vref, RX VrefLevel [Byte0]: 71
8681 00:56:09.311871 [Byte1]: 71
8682 00:56:09.316197
8683 00:56:09.316610 Set Vref, RX VrefLevel [Byte0]: 72
8684 00:56:09.319576 [Byte1]: 72
8685 00:56:09.323898
8686 00:56:09.324327 Set Vref, RX VrefLevel [Byte0]: 73
8687 00:56:09.327254 [Byte1]: 73
8688 00:56:09.331910
8689 00:56:09.332321 Final RX Vref Byte 0 = 57 to rank0
8690 00:56:09.335038 Final RX Vref Byte 1 = 61 to rank0
8691 00:56:09.337817 Final RX Vref Byte 0 = 57 to rank1
8692 00:56:09.341060 Final RX Vref Byte 1 = 61 to rank1==
8693 00:56:09.344362 Dram Type= 6, Freq= 0, CH_1, rank 0
8694 00:56:09.350796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8695 00:56:09.351266 ==
8696 00:56:09.351716 DQS Delay:
8697 00:56:09.354463 DQS0 = 0, DQS1 = 0
8698 00:56:09.354856 DQM Delay:
8699 00:56:09.355283 DQM0 = 132, DQM1 = 128
8700 00:56:09.357743 DQ Delay:
8701 00:56:09.361237 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =132
8702 00:56:09.364068 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8703 00:56:09.368029 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8704 00:56:09.371122 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =136
8705 00:56:09.371578
8706 00:56:09.372021
8707 00:56:09.372452
8708 00:56:09.374402 [DramC_TX_OE_Calibration] TA2
8709 00:56:09.377630 Original DQ_B0 (3 6) =30, OEN = 27
8710 00:56:09.380429 Original DQ_B1 (3 6) =30, OEN = 27
8711 00:56:09.383752 24, 0x0, End_B0=24 End_B1=24
8712 00:56:09.387215 25, 0x0, End_B0=25 End_B1=25
8713 00:56:09.387640 26, 0x0, End_B0=26 End_B1=26
8714 00:56:09.390425 27, 0x0, End_B0=27 End_B1=27
8715 00:56:09.393909 28, 0x0, End_B0=28 End_B1=28
8716 00:56:09.397699 29, 0x0, End_B0=29 End_B1=29
8717 00:56:09.398123 30, 0x0, End_B0=30 End_B1=30
8718 00:56:09.400850 31, 0x4545, End_B0=30 End_B1=30
8719 00:56:09.404534 Byte0 end_step=30 best_step=27
8720 00:56:09.407523 Byte1 end_step=30 best_step=27
8721 00:56:09.410395 Byte0 TX OE(2T, 0.5T) = (3, 3)
8722 00:56:09.413740 Byte1 TX OE(2T, 0.5T) = (3, 3)
8723 00:56:09.414157
8724 00:56:09.414484
8725 00:56:09.420729 [DQSOSCAuto] RK0, (LSB)MR18= 0x111a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
8726 00:56:09.423642 CH1 RK0: MR19=303, MR18=111A
8727 00:56:09.430187 CH1_RK0: MR19=0x303, MR18=0x111A, DQSOSC=396, MR23=63, INC=23, DEC=15
8728 00:56:09.430609
8729 00:56:09.433468 ----->DramcWriteLeveling(PI) begin...
8730 00:56:09.433954 ==
8731 00:56:09.436813 Dram Type= 6, Freq= 0, CH_1, rank 1
8732 00:56:09.440347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 00:56:09.440767 ==
8734 00:56:09.443291 Write leveling (Byte 0): 25 => 25
8735 00:56:09.446543 Write leveling (Byte 1): 27 => 27
8736 00:56:09.450543 DramcWriteLeveling(PI) end<-----
8737 00:56:09.450961
8738 00:56:09.451286 ==
8739 00:56:09.453674 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 00:56:09.459960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 00:56:09.460382 ==
8742 00:56:09.460713 [Gating] SW mode calibration
8743 00:56:09.469908 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8744 00:56:09.473211 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8745 00:56:09.476540 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 00:56:09.483059 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8747 00:56:09.486362 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8748 00:56:09.489369 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8749 00:56:09.496237 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 00:56:09.499560 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 00:56:09.502820 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 00:56:09.509432 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 00:56:09.512347 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 00:56:09.516126 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8755 00:56:09.522706 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8756 00:56:09.525898 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8757 00:56:09.528929 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8758 00:56:09.535857 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 00:56:09.538782 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 00:56:09.545369 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 00:56:09.549382 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 00:56:09.551837 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
8763 00:56:09.558435 1 6 8 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8764 00:56:09.561801 1 6 12 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8765 00:56:09.565355 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 00:56:09.571837 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 00:56:09.575009 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 00:56:09.578300 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 00:56:09.584943 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 00:56:09.588291 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8771 00:56:09.591327 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8772 00:56:09.598227 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8773 00:56:09.601501 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8774 00:56:09.604290 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 00:56:09.611128 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 00:56:09.614420 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 00:56:09.617706 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 00:56:09.624655 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 00:56:09.627647 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 00:56:09.630965 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 00:56:09.637868 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 00:56:09.641296 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 00:56:09.644292 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 00:56:09.650900 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 00:56:09.654084 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8786 00:56:09.657289 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8787 00:56:09.663929 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8788 00:56:09.667200 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8789 00:56:09.670762 Total UI for P1: 0, mck2ui 16
8790 00:56:09.673916 best dqsien dly found for B0: ( 1, 9, 4)
8791 00:56:09.677236 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 00:56:09.680510 Total UI for P1: 0, mck2ui 16
8793 00:56:09.683619 best dqsien dly found for B1: ( 1, 9, 10)
8794 00:56:09.687284 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8795 00:56:09.690040 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8796 00:56:09.690490
8797 00:56:09.693425 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8798 00:56:09.700072 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8799 00:56:09.700583 [Gating] SW calibration Done
8800 00:56:09.703553 ==
8801 00:56:09.706815 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 00:56:09.709664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 00:56:09.710160 ==
8804 00:56:09.710663 RX Vref Scan: 0
8805 00:56:09.711210
8806 00:56:09.713081 RX Vref 0 -> 0, step: 1
8807 00:56:09.713687
8808 00:56:09.716614 RX Delay 0 -> 252, step: 8
8809 00:56:09.719605 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8810 00:56:09.722822 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8811 00:56:09.729766 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8812 00:56:09.733137 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8813 00:56:09.736361 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8814 00:56:09.739187 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8815 00:56:09.742583 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8816 00:56:09.749588 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8817 00:56:09.752724 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8818 00:56:09.755854 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8819 00:56:09.758889 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8820 00:56:09.763099 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8821 00:56:09.768969 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8822 00:56:09.772632 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8823 00:56:09.775998 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8824 00:56:09.778951 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8825 00:56:09.779373 ==
8826 00:56:09.782165 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 00:56:09.788814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 00:56:09.789237 ==
8829 00:56:09.789607 DQS Delay:
8830 00:56:09.791880 DQS0 = 0, DQS1 = 0
8831 00:56:09.792300 DQM Delay:
8832 00:56:09.795248 DQM0 = 133, DQM1 = 131
8833 00:56:09.795666 DQ Delay:
8834 00:56:09.798852 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8835 00:56:09.802111 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8836 00:56:09.805206 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8837 00:56:09.808362 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =139
8838 00:56:09.808780
8839 00:56:09.809109
8840 00:56:09.809471 ==
8841 00:56:09.811878 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 00:56:09.818235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 00:56:09.818684 ==
8844 00:56:09.819036
8845 00:56:09.819349
8846 00:56:09.819664 TX Vref Scan disable
8847 00:56:09.822140 == TX Byte 0 ==
8848 00:56:09.825103 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8849 00:56:09.831980 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8850 00:56:09.832422 == TX Byte 1 ==
8851 00:56:09.835056 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8852 00:56:09.841632 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8853 00:56:09.842091 ==
8854 00:56:09.845024 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 00:56:09.848764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 00:56:09.849209 ==
8857 00:56:09.861813
8858 00:56:09.865247 TX Vref early break, caculate TX vref
8859 00:56:09.868803 TX Vref=16, minBit 9, minWin=21, winSum=378
8860 00:56:09.871727 TX Vref=18, minBit 9, minWin=22, winSum=386
8861 00:56:09.874982 TX Vref=20, minBit 9, minWin=22, winSum=392
8862 00:56:09.878089 TX Vref=22, minBit 9, minWin=23, winSum=397
8863 00:56:09.881673 TX Vref=24, minBit 9, minWin=24, winSum=407
8864 00:56:09.888468 TX Vref=26, minBit 1, minWin=25, winSum=414
8865 00:56:09.891854 TX Vref=28, minBit 1, minWin=25, winSum=417
8866 00:56:09.894927 TX Vref=30, minBit 8, minWin=24, winSum=413
8867 00:56:09.898289 TX Vref=32, minBit 8, minWin=24, winSum=412
8868 00:56:09.901569 TX Vref=34, minBit 9, minWin=23, winSum=404
8869 00:56:09.908153 TX Vref=36, minBit 8, minWin=23, winSum=394
8870 00:56:09.911073 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 28
8871 00:56:09.911530
8872 00:56:09.914757 Final TX Range 0 Vref 28
8873 00:56:09.915286
8874 00:56:09.915664 ==
8875 00:56:09.918078 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 00:56:09.921347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 00:56:09.921905 ==
8878 00:56:09.924459
8879 00:56:09.924976
8880 00:56:09.925367 TX Vref Scan disable
8881 00:56:09.931173 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8882 00:56:09.931616 == TX Byte 0 ==
8883 00:56:09.934324 u2DelayCellOfst[0]=14 cells (4 PI)
8884 00:56:09.937589 u2DelayCellOfst[1]=10 cells (3 PI)
8885 00:56:09.941188 u2DelayCellOfst[2]=0 cells (0 PI)
8886 00:56:09.944655 u2DelayCellOfst[3]=3 cells (1 PI)
8887 00:56:09.948098 u2DelayCellOfst[4]=7 cells (2 PI)
8888 00:56:09.950871 u2DelayCellOfst[5]=14 cells (4 PI)
8889 00:56:09.954090 u2DelayCellOfst[6]=14 cells (4 PI)
8890 00:56:09.957515 u2DelayCellOfst[7]=3 cells (1 PI)
8891 00:56:09.960295 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8892 00:56:09.964083 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8893 00:56:09.967550 == TX Byte 1 ==
8894 00:56:09.970513 u2DelayCellOfst[8]=0 cells (0 PI)
8895 00:56:09.973914 u2DelayCellOfst[9]=3 cells (1 PI)
8896 00:56:09.977092 u2DelayCellOfst[10]=10 cells (3 PI)
8897 00:56:09.980421 u2DelayCellOfst[11]=3 cells (1 PI)
8898 00:56:09.983855 u2DelayCellOfst[12]=14 cells (4 PI)
8899 00:56:09.987728 u2DelayCellOfst[13]=14 cells (4 PI)
8900 00:56:09.990150 u2DelayCellOfst[14]=17 cells (5 PI)
8901 00:56:09.993572 u2DelayCellOfst[15]=17 cells (5 PI)
8902 00:56:09.996923 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8903 00:56:10.000351 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8904 00:56:10.003541 DramC Write-DBI on
8905 00:56:10.004007 ==
8906 00:56:10.006772 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 00:56:10.010201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 00:56:10.010650 ==
8909 00:56:10.011097
8910 00:56:10.011434
8911 00:56:10.013378 TX Vref Scan disable
8912 00:56:10.013832 == TX Byte 0 ==
8913 00:56:10.019638 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8914 00:56:10.020062 == TX Byte 1 ==
8915 00:56:10.026284 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8916 00:56:10.026706 DramC Write-DBI off
8917 00:56:10.027169
8918 00:56:10.027506 [DATLAT]
8919 00:56:10.029771 Freq=1600, CH1 RK1
8920 00:56:10.030197
8921 00:56:10.030643 DATLAT Default: 0xf
8922 00:56:10.033191 0, 0xFFFF, sum = 0
8923 00:56:10.036629 1, 0xFFFF, sum = 0
8924 00:56:10.037085 2, 0xFFFF, sum = 0
8925 00:56:10.040058 3, 0xFFFF, sum = 0
8926 00:56:10.040660 4, 0xFFFF, sum = 0
8927 00:56:10.043330 5, 0xFFFF, sum = 0
8928 00:56:10.043813 6, 0xFFFF, sum = 0
8929 00:56:10.046035 7, 0xFFFF, sum = 0
8930 00:56:10.046489 8, 0xFFFF, sum = 0
8931 00:56:10.049452 9, 0xFFFF, sum = 0
8932 00:56:10.049962 10, 0xFFFF, sum = 0
8933 00:56:10.052791 11, 0xFFFF, sum = 0
8934 00:56:10.053377 12, 0xFFFF, sum = 0
8935 00:56:10.056713 13, 0xFFFF, sum = 0
8936 00:56:10.057141 14, 0x0, sum = 1
8937 00:56:10.059532 15, 0x0, sum = 2
8938 00:56:10.059978 16, 0x0, sum = 3
8939 00:56:10.063057 17, 0x0, sum = 4
8940 00:56:10.063554 best_step = 15
8941 00:56:10.063916
8942 00:56:10.064294 ==
8943 00:56:10.066201 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 00:56:10.072387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 00:56:10.072813 ==
8946 00:56:10.073166 RX Vref Scan: 0
8947 00:56:10.073598
8948 00:56:10.075966 RX Vref 0 -> 0, step: 1
8949 00:56:10.076411
8950 00:56:10.079353 RX Delay 19 -> 252, step: 4
8951 00:56:10.082394 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8952 00:56:10.085718 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8953 00:56:10.089294 iDelay=195, Bit 2, Center 118 (63 ~ 174) 112
8954 00:56:10.095925 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8955 00:56:10.099193 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8956 00:56:10.102497 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8957 00:56:10.105341 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8958 00:56:10.108672 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8959 00:56:10.115381 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8960 00:56:10.118828 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8961 00:56:10.122215 iDelay=195, Bit 10, Center 132 (79 ~ 186) 108
8962 00:56:10.125182 iDelay=195, Bit 11, Center 122 (71 ~ 174) 104
8963 00:56:10.132059 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8964 00:56:10.135249 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8965 00:56:10.138577 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8966 00:56:10.141931 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8967 00:56:10.142364 ==
8968 00:56:10.144786 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 00:56:10.151564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 00:56:10.152082 ==
8971 00:56:10.152448 DQS Delay:
8972 00:56:10.155048 DQS0 = 0, DQS1 = 0
8973 00:56:10.155563 DQM Delay:
8974 00:56:10.155944 DQM0 = 130, DQM1 = 129
8975 00:56:10.158474 DQ Delay:
8976 00:56:10.161905 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
8977 00:56:10.165146 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
8978 00:56:10.167980 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8979 00:56:10.171420 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
8980 00:56:10.171958
8981 00:56:10.172372
8982 00:56:10.172700
8983 00:56:10.175129 [DramC_TX_OE_Calibration] TA2
8984 00:56:10.177928 Original DQ_B0 (3 6) =30, OEN = 27
8985 00:56:10.181160 Original DQ_B1 (3 6) =30, OEN = 27
8986 00:56:10.184671 24, 0x0, End_B0=24 End_B1=24
8987 00:56:10.187947 25, 0x0, End_B0=25 End_B1=25
8988 00:56:10.188413 26, 0x0, End_B0=26 End_B1=26
8989 00:56:10.191145 27, 0x0, End_B0=27 End_B1=27
8990 00:56:10.194856 28, 0x0, End_B0=28 End_B1=28
8991 00:56:10.197695 29, 0x0, End_B0=29 End_B1=29
8992 00:56:10.198187 30, 0x0, End_B0=30 End_B1=30
8993 00:56:10.200963 31, 0x4141, End_B0=30 End_B1=30
8994 00:56:10.204412 Byte0 end_step=30 best_step=27
8995 00:56:10.207402 Byte1 end_step=30 best_step=27
8996 00:56:10.211960 Byte0 TX OE(2T, 0.5T) = (3, 3)
8997 00:56:10.214503 Byte1 TX OE(2T, 0.5T) = (3, 3)
8998 00:56:10.215057
8999 00:56:10.215447
9000 00:56:10.220685 [DQSOSCAuto] RK1, (LSB)MR18= 0x1220, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
9001 00:56:10.224309 CH1 RK1: MR19=303, MR18=1220
9002 00:56:10.230666 CH1_RK1: MR19=0x303, MR18=0x1220, DQSOSC=393, MR23=63, INC=23, DEC=15
9003 00:56:10.233772 [RxdqsGatingPostProcess] freq 1600
9004 00:56:10.240490 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9005 00:56:10.240941 best DQS0 dly(2T, 0.5T) = (1, 1)
9006 00:56:10.244134 best DQS1 dly(2T, 0.5T) = (1, 1)
9007 00:56:10.247176 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9008 00:56:10.250586 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9009 00:56:10.253847 best DQS0 dly(2T, 0.5T) = (1, 1)
9010 00:56:10.257199 best DQS1 dly(2T, 0.5T) = (1, 1)
9011 00:56:10.260500 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9012 00:56:10.264299 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9013 00:56:10.266653 Pre-setting of DQS Precalculation
9014 00:56:10.270083 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9015 00:56:10.279952 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9016 00:56:10.286282 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9017 00:56:10.286734
9018 00:56:10.287068
9019 00:56:10.289865 [Calibration Summary] 3200 Mbps
9020 00:56:10.290318 CH 0, Rank 0
9021 00:56:10.293162 SW Impedance : PASS
9022 00:56:10.296414 DUTY Scan : NO K
9023 00:56:10.296831 ZQ Calibration : PASS
9024 00:56:10.299655 Jitter Meter : NO K
9025 00:56:10.302958 CBT Training : PASS
9026 00:56:10.303395 Write leveling : PASS
9027 00:56:10.306262 RX DQS gating : PASS
9028 00:56:10.306706 RX DQ/DQS(RDDQC) : PASS
9029 00:56:10.309861 TX DQ/DQS : PASS
9030 00:56:10.312720 RX DATLAT : PASS
9031 00:56:10.313167 RX DQ/DQS(Engine): PASS
9032 00:56:10.315998 TX OE : PASS
9033 00:56:10.316438 All Pass.
9034 00:56:10.316772
9035 00:56:10.319096 CH 0, Rank 1
9036 00:56:10.319515 SW Impedance : PASS
9037 00:56:10.322534 DUTY Scan : NO K
9038 00:56:10.325738 ZQ Calibration : PASS
9039 00:56:10.326160 Jitter Meter : NO K
9040 00:56:10.329290 CBT Training : PASS
9041 00:56:10.332372 Write leveling : PASS
9042 00:56:10.332810 RX DQS gating : PASS
9043 00:56:10.335669 RX DQ/DQS(RDDQC) : PASS
9044 00:56:10.338839 TX DQ/DQS : PASS
9045 00:56:10.339411 RX DATLAT : PASS
9046 00:56:10.342075 RX DQ/DQS(Engine): PASS
9047 00:56:10.345578 TX OE : PASS
9048 00:56:10.346012 All Pass.
9049 00:56:10.346446
9050 00:56:10.346862 CH 1, Rank 0
9051 00:56:10.348728 SW Impedance : PASS
9052 00:56:10.352116 DUTY Scan : NO K
9053 00:56:10.352550 ZQ Calibration : PASS
9054 00:56:10.355480 Jitter Meter : NO K
9055 00:56:10.358626 CBT Training : PASS
9056 00:56:10.359076 Write leveling : PASS
9057 00:56:10.362060 RX DQS gating : PASS
9058 00:56:10.365452 RX DQ/DQS(RDDQC) : PASS
9059 00:56:10.365887 TX DQ/DQS : PASS
9060 00:56:10.368826 RX DATLAT : PASS
9061 00:56:10.372114 RX DQ/DQS(Engine): PASS
9062 00:56:10.372550 TX OE : PASS
9063 00:56:10.375242 All Pass.
9064 00:56:10.375682
9065 00:56:10.376019 CH 1, Rank 1
9066 00:56:10.378902 SW Impedance : PASS
9067 00:56:10.379345 DUTY Scan : NO K
9068 00:56:10.381784 ZQ Calibration : PASS
9069 00:56:10.385540 Jitter Meter : NO K
9070 00:56:10.385983 CBT Training : PASS
9071 00:56:10.388479 Write leveling : PASS
9072 00:56:10.391413 RX DQS gating : PASS
9073 00:56:10.391853 RX DQ/DQS(RDDQC) : PASS
9074 00:56:10.395238 TX DQ/DQS : PASS
9075 00:56:10.397740 RX DATLAT : PASS
9076 00:56:10.398042 RX DQ/DQS(Engine): PASS
9077 00:56:10.401339 TX OE : PASS
9078 00:56:10.401638 All Pass.
9079 00:56:10.401817
9080 00:56:10.404638 DramC Write-DBI on
9081 00:56:10.407432 PER_BANK_REFRESH: Hybrid Mode
9082 00:56:10.407615 TX_TRACKING: ON
9083 00:56:10.417937 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9084 00:56:10.423960 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9085 00:56:10.430499 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9086 00:56:10.434622 [FAST_K] Save calibration result to emmc
9087 00:56:10.437275 sync common calibartion params.
9088 00:56:10.440601 sync cbt_mode0:1, 1:1
9089 00:56:10.443984 dram_init: ddr_geometry: 2
9090 00:56:10.444113 dram_init: ddr_geometry: 2
9091 00:56:10.446956 dram_init: ddr_geometry: 2
9092 00:56:10.450158 0:dram_rank_size:100000000
9093 00:56:10.453493 1:dram_rank_size:100000000
9094 00:56:10.457242 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9095 00:56:10.460398 DFS_SHUFFLE_HW_MODE: ON
9096 00:56:10.463892 dramc_set_vcore_voltage set vcore to 725000
9097 00:56:10.467402 Read voltage for 1600, 0
9098 00:56:10.467623 Vio18 = 0
9099 00:56:10.467832 Vcore = 725000
9100 00:56:10.470104 Vdram = 0
9101 00:56:10.470327 Vddq = 0
9102 00:56:10.470503 Vmddr = 0
9103 00:56:10.473558 switch to 3200 Mbps bootup
9104 00:56:10.477037 [DramcRunTimeConfig]
9105 00:56:10.477409 PHYPLL
9106 00:56:10.477695 DPM_CONTROL_AFTERK: ON
9107 00:56:10.480537 PER_BANK_REFRESH: ON
9108 00:56:10.484629 REFRESH_OVERHEAD_REDUCTION: ON
9109 00:56:10.487479 CMD_PICG_NEW_MODE: OFF
9110 00:56:10.487895 XRTWTW_NEW_MODE: ON
9111 00:56:10.490251 XRTRTR_NEW_MODE: ON
9112 00:56:10.490664 TX_TRACKING: ON
9113 00:56:10.493773 RDSEL_TRACKING: OFF
9114 00:56:10.494254 DQS Precalculation for DVFS: ON
9115 00:56:10.496592 RX_TRACKING: OFF
9116 00:56:10.497028 HW_GATING DBG: ON
9117 00:56:10.500357 ZQCS_ENABLE_LP4: ON
9118 00:56:10.503505 RX_PICG_NEW_MODE: ON
9119 00:56:10.504064 TX_PICG_NEW_MODE: ON
9120 00:56:10.506978 ENABLE_RX_DCM_DPHY: ON
9121 00:56:10.510099 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9122 00:56:10.513382 DUMMY_READ_FOR_TRACKING: OFF
9123 00:56:10.513849 !!! SPM_CONTROL_AFTERK: OFF
9124 00:56:10.516551 !!! SPM could not control APHY
9125 00:56:10.519728 IMPEDANCE_TRACKING: ON
9126 00:56:10.520223 TEMP_SENSOR: ON
9127 00:56:10.523085 HW_SAVE_FOR_SR: OFF
9128 00:56:10.526330 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9129 00:56:10.530017 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9130 00:56:10.530516 Read ODT Tracking: ON
9131 00:56:10.533121 Refresh Rate DeBounce: ON
9132 00:56:10.536340 DFS_NO_QUEUE_FLUSH: ON
9133 00:56:10.539798 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9134 00:56:10.540215 ENABLE_DFS_RUNTIME_MRW: OFF
9135 00:56:10.543025 DDR_RESERVE_NEW_MODE: ON
9136 00:56:10.546071 MR_CBT_SWITCH_FREQ: ON
9137 00:56:10.546528 =========================
9138 00:56:10.566413 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9139 00:56:10.569723 dram_init: ddr_geometry: 2
9140 00:56:10.588055 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9141 00:56:10.591337 dram_init: dram init end (result: 0)
9142 00:56:10.597913 DRAM-K: Full calibration passed in 24492 msecs
9143 00:56:10.601161 MRC: failed to locate region type 0.
9144 00:56:10.601626 DRAM rank0 size:0x100000000,
9145 00:56:10.604327 DRAM rank1 size=0x100000000
9146 00:56:10.614140 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9147 00:56:10.620573 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9148 00:56:10.630774 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9149 00:56:10.637443 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9150 00:56:10.637955 DRAM rank0 size:0x100000000,
9151 00:56:10.640709 DRAM rank1 size=0x100000000
9152 00:56:10.641224 CBMEM:
9153 00:56:10.643874 IMD: root @ 0xfffff000 254 entries.
9154 00:56:10.646920 IMD: root @ 0xffffec00 62 entries.
9155 00:56:10.653537 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9156 00:56:10.656765 WARNING: RO_VPD is uninitialized or empty.
9157 00:56:10.660204 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9158 00:56:10.668110 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9159 00:56:10.680666 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9160 00:56:10.692326 BS: romstage times (exec / console): total (unknown) / 24010 ms
9161 00:56:10.692745
9162 00:56:10.693074
9163 00:56:10.702246 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9164 00:56:10.705456 ARM64: Exception handlers installed.
9165 00:56:10.708932 ARM64: Testing exception
9166 00:56:10.711902 ARM64: Done test exception
9167 00:56:10.712298 Enumerating buses...
9168 00:56:10.715267 Show all devs... Before device enumeration.
9169 00:56:10.718344 Root Device: enabled 1
9170 00:56:10.722060 CPU_CLUSTER: 0: enabled 1
9171 00:56:10.722474 CPU: 00: enabled 1
9172 00:56:10.725104 Compare with tree...
9173 00:56:10.725663 Root Device: enabled 1
9174 00:56:10.728562 CPU_CLUSTER: 0: enabled 1
9175 00:56:10.731874 CPU: 00: enabled 1
9176 00:56:10.732306 Root Device scanning...
9177 00:56:10.735255 scan_static_bus for Root Device
9178 00:56:10.738046 CPU_CLUSTER: 0 enabled
9179 00:56:10.741711 scan_static_bus for Root Device done
9180 00:56:10.744691 scan_bus: bus Root Device finished in 8 msecs
9181 00:56:10.745329 done
9182 00:56:10.751672 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9183 00:56:10.754420 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9184 00:56:10.761113 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9185 00:56:10.768068 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9186 00:56:10.768549 Allocating resources...
9187 00:56:10.771399 Reading resources...
9188 00:56:10.774512 Root Device read_resources bus 0 link: 0
9189 00:56:10.777678 DRAM rank0 size:0x100000000,
9190 00:56:10.778257 DRAM rank1 size=0x100000000
9191 00:56:10.784519 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9192 00:56:10.785094 CPU: 00 missing read_resources
9193 00:56:10.790840 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9194 00:56:10.793980 Root Device read_resources bus 0 link: 0 done
9195 00:56:10.797320 Done reading resources.
9196 00:56:10.800734 Show resources in subtree (Root Device)...After reading.
9197 00:56:10.804187 Root Device child on link 0 CPU_CLUSTER: 0
9198 00:56:10.807690 CPU_CLUSTER: 0 child on link 0 CPU: 00
9199 00:56:10.817350 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9200 00:56:10.817826 CPU: 00
9201 00:56:10.824632 Root Device assign_resources, bus 0 link: 0
9202 00:56:10.827472 CPU_CLUSTER: 0 missing set_resources
9203 00:56:10.830702 Root Device assign_resources, bus 0 link: 0 done
9204 00:56:10.831277 Done setting resources.
9205 00:56:10.836915 Show resources in subtree (Root Device)...After assigning values.
9206 00:56:10.840170 Root Device child on link 0 CPU_CLUSTER: 0
9207 00:56:10.846752 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 00:56:10.853854 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 00:56:10.856951 CPU: 00
9210 00:56:10.857430 Done allocating resources.
9211 00:56:10.863811 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9212 00:56:10.864326 Enabling resources...
9213 00:56:10.866501 done.
9214 00:56:10.869820 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9215 00:56:10.873340 Initializing devices...
9216 00:56:10.873759 Root Device init
9217 00:56:10.876318 init hardware done!
9218 00:56:10.876849 0x00000018: ctrlr->caps
9219 00:56:10.879988 52.000 MHz: ctrlr->f_max
9220 00:56:10.883290 0.400 MHz: ctrlr->f_min
9221 00:56:10.886595 0x40ff8080: ctrlr->voltages
9222 00:56:10.887023 sclk: 390625
9223 00:56:10.887369 Bus Width = 1
9224 00:56:10.889895 sclk: 390625
9225 00:56:10.890337 Bus Width = 1
9226 00:56:10.892983 Early init status = 3
9227 00:56:10.896440 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9228 00:56:10.900732 in-header: 03 fc 00 00 01 00 00 00
9229 00:56:10.903928 in-data: 00
9230 00:56:10.907238 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9231 00:56:10.912947 in-header: 03 fd 00 00 00 00 00 00
9232 00:56:10.916193 in-data:
9233 00:56:10.919076 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9234 00:56:10.923727 in-header: 03 fc 00 00 01 00 00 00
9235 00:56:10.927347 in-data: 00
9236 00:56:10.930604 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9237 00:56:10.935987 in-header: 03 fd 00 00 00 00 00 00
9238 00:56:10.939007 in-data:
9239 00:56:10.942444 [SSUSB] Setting up USB HOST controller...
9240 00:56:10.945930 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9241 00:56:10.949245 [SSUSB] phy power-on done.
9242 00:56:10.952316 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9243 00:56:10.958983 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9244 00:56:10.962638 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9245 00:56:10.969027 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9246 00:56:10.975514 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9247 00:56:10.982128 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9248 00:56:10.989015 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9249 00:56:10.995299 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9250 00:56:10.998504 SPM: binary array size = 0x9dc
9251 00:56:11.002006 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9252 00:56:11.008428 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9253 00:56:11.015451 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9254 00:56:11.021583 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9255 00:56:11.024788 configure_display: Starting display init
9256 00:56:11.059129 anx7625_power_on_init: Init interface.
9257 00:56:11.062315 anx7625_disable_pd_protocol: Disabled PD feature.
9258 00:56:11.066178 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9259 00:56:11.093650 anx7625_start_dp_work: Secure OCM version=00
9260 00:56:11.097010 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9261 00:56:11.111596 sp_tx_get_edid_block: EDID Block = 1
9262 00:56:11.214083 Extracted contents:
9263 00:56:11.217460 header: 00 ff ff ff ff ff ff 00
9264 00:56:11.221121 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9265 00:56:11.224237 version: 01 04
9266 00:56:11.227316 basic params: 95 1f 11 78 0a
9267 00:56:11.230584 chroma info: 76 90 94 55 54 90 27 21 50 54
9268 00:56:11.233927 established: 00 00 00
9269 00:56:11.240823 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9270 00:56:11.244166 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9271 00:56:11.251262 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9272 00:56:11.257214 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9273 00:56:11.263947 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9274 00:56:11.266964 extensions: 00
9275 00:56:11.267442 checksum: fb
9276 00:56:11.267795
9277 00:56:11.270146 Manufacturer: IVO Model 57d Serial Number 0
9278 00:56:11.273643 Made week 0 of 2020
9279 00:56:11.276986 EDID version: 1.4
9280 00:56:11.277551 Digital display
9281 00:56:11.279990 6 bits per primary color channel
9282 00:56:11.280517 DisplayPort interface
9283 00:56:11.283908 Maximum image size: 31 cm x 17 cm
9284 00:56:11.286800 Gamma: 220%
9285 00:56:11.287186 Check DPMS levels
9286 00:56:11.290167 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9287 00:56:11.296703 First detailed timing is preferred timing
9288 00:56:11.297253 Established timings supported:
9289 00:56:11.300053 Standard timings supported:
9290 00:56:11.303171 Detailed timings
9291 00:56:11.306341 Hex of detail: 383680a07038204018303c0035ae10000019
9292 00:56:11.313360 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9293 00:56:11.316766 0780 0798 07c8 0820 hborder 0
9294 00:56:11.319940 0438 043b 0447 0458 vborder 0
9295 00:56:11.323106 -hsync -vsync
9296 00:56:11.323522 Did detailed timing
9297 00:56:11.329773 Hex of detail: 000000000000000000000000000000000000
9298 00:56:11.333010 Manufacturer-specified data, tag 0
9299 00:56:11.336123 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9300 00:56:11.339449 ASCII string: InfoVision
9301 00:56:11.342823 Hex of detail: 000000fe00523134304e574635205248200a
9302 00:56:11.346227 ASCII string: R140NWF5 RH
9303 00:56:11.346742 Checksum
9304 00:56:11.349070 Checksum: 0xfb (valid)
9305 00:56:11.352903 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9306 00:56:11.356178 DSI data_rate: 832800000 bps
9307 00:56:11.362258 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9308 00:56:11.366123 anx7625_parse_edid: pixelclock(138800).
9309 00:56:11.369213 hactive(1920), hsync(48), hfp(24), hbp(88)
9310 00:56:11.372302 vactive(1080), vsync(12), vfp(3), vbp(17)
9311 00:56:11.375549 anx7625_dsi_config: config dsi.
9312 00:56:11.382730 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9313 00:56:11.395987 anx7625_dsi_config: success to config DSI
9314 00:56:11.399260 anx7625_dp_start: MIPI phy setup OK.
9315 00:56:11.402901 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9316 00:56:11.406365 mtk_ddp_mode_set invalid vrefresh 60
9317 00:56:11.409150 main_disp_path_setup
9318 00:56:11.409822 ovl_layer_smi_id_en
9319 00:56:11.412510 ovl_layer_smi_id_en
9320 00:56:11.412892 ccorr_config
9321 00:56:11.413203 aal_config
9322 00:56:11.415990 gamma_config
9323 00:56:11.416494 postmask_config
9324 00:56:11.419045 dither_config
9325 00:56:11.422156 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9326 00:56:11.428851 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9327 00:56:11.432154 Root Device init finished in 555 msecs
9328 00:56:11.435576 CPU_CLUSTER: 0 init
9329 00:56:11.442347 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9330 00:56:11.449023 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9331 00:56:11.449565 APU_MBOX 0x190000b0 = 0x10001
9332 00:56:11.452360 APU_MBOX 0x190001b0 = 0x10001
9333 00:56:11.455858 APU_MBOX 0x190005b0 = 0x10001
9334 00:56:11.458581 APU_MBOX 0x190006b0 = 0x10001
9335 00:56:11.465375 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9336 00:56:11.475357 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9337 00:56:11.487748 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9338 00:56:11.494315 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9339 00:56:11.505895 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9340 00:56:11.514965 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9341 00:56:11.518379 CPU_CLUSTER: 0 init finished in 81 msecs
9342 00:56:11.521825 Devices initialized
9343 00:56:11.525339 Show all devs... After init.
9344 00:56:11.525759 Root Device: enabled 1
9345 00:56:11.528309 CPU_CLUSTER: 0: enabled 1
9346 00:56:11.532087 CPU: 00: enabled 1
9347 00:56:11.534721 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9348 00:56:11.538027 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9349 00:56:11.541249 ELOG: NV offset 0x57f000 size 0x1000
9350 00:56:11.548122 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9351 00:56:11.554617 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9352 00:56:11.558412 ELOG: Event(17) added with size 13 at 2024-06-16 00:56:10 UTC
9353 00:56:11.561252 out: cmd=0x121: 03 db 21 01 00 00 00 00
9354 00:56:11.565361 in-header: 03 a9 00 00 2c 00 00 00
9355 00:56:11.578484 in-data: 94 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9356 00:56:11.585329 ELOG: Event(A1) added with size 10 at 2024-06-16 00:56:10 UTC
9357 00:56:11.592235 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9358 00:56:11.598249 ELOG: Event(A0) added with size 9 at 2024-06-16 00:56:10 UTC
9359 00:56:11.601835 elog_add_boot_reason: Logged dev mode boot
9360 00:56:11.605117 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9361 00:56:11.608427 Finalize devices...
9362 00:56:11.608859 Devices finalized
9363 00:56:11.614871 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9364 00:56:11.618354 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9365 00:56:11.621321 in-header: 03 07 00 00 08 00 00 00
9366 00:56:11.624921 in-data: aa e4 47 04 13 02 00 00
9367 00:56:11.628157 Chrome EC: UHEPI supported
9368 00:56:11.634885 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9369 00:56:11.637812 in-header: 03 a9 00 00 08 00 00 00
9370 00:56:11.641186 in-data: 84 60 60 08 00 00 00 00
9371 00:56:11.647572 ELOG: Event(91) added with size 10 at 2024-06-16 00:56:10 UTC
9372 00:56:11.650882 Chrome EC: clear events_b mask to 0x0000000020004000
9373 00:56:11.657703 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9374 00:56:11.661599 in-header: 03 fd 00 00 00 00 00 00
9375 00:56:11.664850 in-data:
9376 00:56:11.668653 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9377 00:56:11.671280 Writing coreboot table at 0xffe64000
9378 00:56:11.674844 0. 000000000010a000-0000000000113fff: RAMSTAGE
9379 00:56:11.681487 1. 0000000040000000-00000000400fffff: RAM
9380 00:56:11.684538 2. 0000000040100000-000000004032afff: RAMSTAGE
9381 00:56:11.687651 3. 000000004032b000-00000000545fffff: RAM
9382 00:56:11.691164 4. 0000000054600000-000000005465ffff: BL31
9383 00:56:11.694684 5. 0000000054660000-00000000ffe63fff: RAM
9384 00:56:11.701059 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9385 00:56:11.704844 7. 0000000100000000-000000023fffffff: RAM
9386 00:56:11.708300 Passing 5 GPIOs to payload:
9387 00:56:11.711621 NAME | PORT | POLARITY | VALUE
9388 00:56:11.717766 EC in RW | 0x000000aa | low | undefined
9389 00:56:11.720711 EC interrupt | 0x00000005 | low | undefined
9390 00:56:11.723961 TPM interrupt | 0x000000ab | high | undefined
9391 00:56:11.731043 SD card detect | 0x00000011 | high | undefined
9392 00:56:11.733952 speaker enable | 0x00000093 | high | undefined
9393 00:56:11.737028 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9394 00:56:11.740712 in-header: 03 f9 00 00 02 00 00 00
9395 00:56:11.744310 in-data: 02 00
9396 00:56:11.747296 ADC[4]: Raw value=903694 ID=7
9397 00:56:11.747726 ADC[3]: Raw value=213916 ID=1
9398 00:56:11.750747 RAM Code: 0x71
9399 00:56:11.754001 ADC[6]: Raw value=74630 ID=0
9400 00:56:11.754423 ADC[5]: Raw value=213916 ID=1
9401 00:56:11.757222 SKU Code: 0x1
9402 00:56:11.763834 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7705
9403 00:56:11.764373 coreboot table: 964 bytes.
9404 00:56:11.767108 IMD ROOT 0. 0xfffff000 0x00001000
9405 00:56:11.770326 IMD SMALL 1. 0xffffe000 0x00001000
9406 00:56:11.773383 RO MCACHE 2. 0xffffc000 0x00001104
9407 00:56:11.776669 CONSOLE 3. 0xfff7c000 0x00080000
9408 00:56:11.780202 FMAP 4. 0xfff7b000 0x00000452
9409 00:56:11.783533 TIME STAMP 5. 0xfff7a000 0x00000910
9410 00:56:11.786604 VBOOT WORK 6. 0xfff66000 0x00014000
9411 00:56:11.790456 RAMOOPS 7. 0xffe66000 0x00100000
9412 00:56:11.793234 COREBOOT 8. 0xffe64000 0x00002000
9413 00:56:11.797145 IMD small region:
9414 00:56:11.799841 IMD ROOT 0. 0xffffec00 0x00000400
9415 00:56:11.803377 VPD 1. 0xffffeb80 0x0000006c
9416 00:56:11.806892 MMC STATUS 2. 0xffffeb60 0x00000004
9417 00:56:11.813374 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9418 00:56:11.819860 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9419 00:56:11.857775 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9420 00:56:11.861215 Checking segment from ROM address 0x40100000
9421 00:56:11.867949 Checking segment from ROM address 0x4010001c
9422 00:56:11.870968 Loading segment from ROM address 0x40100000
9423 00:56:11.871414 code (compression=0)
9424 00:56:11.880885 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9425 00:56:11.887612 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9426 00:56:11.891036 it's not compressed!
9427 00:56:11.894086 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9428 00:56:11.900812 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9429 00:56:11.918321 Loading segment from ROM address 0x4010001c
9430 00:56:11.918807 Entry Point 0x80000000
9431 00:56:11.921605 Loaded segments
9432 00:56:11.925089 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9433 00:56:11.931663 Jumping to boot code at 0x80000000(0xffe64000)
9434 00:56:11.937816 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9435 00:56:11.945015 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9436 00:56:11.952943 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9437 00:56:11.956277 Checking segment from ROM address 0x40100000
9438 00:56:11.959379 Checking segment from ROM address 0x4010001c
9439 00:56:11.965900 Loading segment from ROM address 0x40100000
9440 00:56:11.966485 code (compression=1)
9441 00:56:11.972594 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9442 00:56:11.982658 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9443 00:56:11.983191 using LZMA
9444 00:56:11.991522 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9445 00:56:11.997528 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9446 00:56:12.000920 Loading segment from ROM address 0x4010001c
9447 00:56:12.001461 Entry Point 0x54601000
9448 00:56:12.004520 Loaded segments
9449 00:56:12.007891 NOTICE: MT8192 bl31_setup
9450 00:56:12.014768 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9451 00:56:12.018628 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9452 00:56:12.021335 WARNING: region 0:
9453 00:56:12.024585 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 00:56:12.025017 WARNING: region 1:
9455 00:56:12.031040 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9456 00:56:12.034581 WARNING: region 2:
9457 00:56:12.037790 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9458 00:56:12.041155 WARNING: region 3:
9459 00:56:12.047605 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 00:56:12.048045 WARNING: region 4:
9461 00:56:12.054329 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 00:56:12.054753 WARNING: region 5:
9463 00:56:12.057670 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 00:56:12.061146 WARNING: region 6:
9465 00:56:12.064292 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 00:56:12.067357 WARNING: region 7:
9467 00:56:12.070578 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 00:56:12.077181 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9469 00:56:12.080473 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9470 00:56:12.087122 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9471 00:56:12.090616 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9472 00:56:12.094027 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9473 00:56:12.100363 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9474 00:56:12.103811 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9475 00:56:12.107302 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9476 00:56:12.113358 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9477 00:56:12.116825 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9478 00:56:12.123408 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9479 00:56:12.126869 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9480 00:56:12.130340 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9481 00:56:12.136553 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9482 00:56:12.139717 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9483 00:56:12.146953 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9484 00:56:12.149767 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9485 00:56:12.153057 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9486 00:56:12.159773 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9487 00:56:12.163137 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9488 00:56:12.169667 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9489 00:56:12.172962 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9490 00:56:12.176168 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9491 00:56:12.183214 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9492 00:56:12.186264 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9493 00:56:12.192627 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9494 00:56:12.196223 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9495 00:56:12.199570 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9496 00:56:12.205942 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9497 00:56:12.209106 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9498 00:56:12.215938 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9499 00:56:12.219195 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9500 00:56:12.222274 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9501 00:56:12.228873 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9502 00:56:12.232418 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9503 00:56:12.235811 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9504 00:56:12.238888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9505 00:56:12.245155 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9506 00:56:12.248864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9507 00:56:12.251900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9508 00:56:12.255584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9509 00:56:12.262217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9510 00:56:12.265030 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9511 00:56:12.268039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9512 00:56:12.271543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9513 00:56:12.278555 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9514 00:56:12.281722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9515 00:56:12.285086 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9516 00:56:12.291455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9517 00:56:12.294758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9518 00:56:12.301389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9519 00:56:12.304943 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9520 00:56:12.308070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9521 00:56:12.314622 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9522 00:56:12.317550 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9523 00:56:12.324423 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9524 00:56:12.327933 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9525 00:56:12.334313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9526 00:56:12.337643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9527 00:56:12.344371 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9528 00:56:12.347663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9529 00:56:12.354085 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9530 00:56:12.357360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9531 00:56:12.360782 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9532 00:56:12.366948 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9533 00:56:12.370699 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9534 00:56:12.376750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9535 00:56:12.380057 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9536 00:56:12.386887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9537 00:56:12.389966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9538 00:56:12.397184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9539 00:56:12.399759 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9540 00:56:12.403083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9541 00:56:12.410222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9542 00:56:12.413135 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9543 00:56:12.420015 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9544 00:56:12.423558 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9545 00:56:12.429838 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9546 00:56:12.433089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9547 00:56:12.439482 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9548 00:56:12.442943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9549 00:56:12.446527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9550 00:56:12.453001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9551 00:56:12.456230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9552 00:56:12.463033 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9553 00:56:12.466395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9554 00:56:12.472638 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9555 00:56:12.476107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9556 00:56:12.482483 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9557 00:56:12.485693 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9558 00:56:12.489246 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9559 00:56:12.495932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9560 00:56:12.499112 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9561 00:56:12.505871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9562 00:56:12.509174 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9563 00:56:12.515560 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9564 00:56:12.519350 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9565 00:56:12.522030 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9566 00:56:12.528455 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9567 00:56:12.532075 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9568 00:56:12.535230 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9569 00:56:12.538580 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9570 00:56:12.545843 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9571 00:56:12.548754 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9572 00:56:12.555351 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9573 00:56:12.558869 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9574 00:56:12.565583 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9575 00:56:12.568743 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9576 00:56:12.571574 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9577 00:56:12.578295 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9578 00:56:12.581390 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9579 00:56:12.588257 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9580 00:56:12.591169 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9581 00:56:12.594638 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9582 00:56:12.601186 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9583 00:56:12.604487 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9584 00:56:12.607917 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9585 00:56:12.614567 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9586 00:56:12.617828 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9587 00:56:12.620780 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9588 00:56:12.627730 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9589 00:56:12.630659 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9590 00:56:12.634264 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9591 00:56:12.637582 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9592 00:56:12.644112 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9593 00:56:12.647246 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9594 00:56:12.654119 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9595 00:56:12.657026 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9596 00:56:12.663675 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9597 00:56:12.667302 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9598 00:56:12.670363 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9599 00:56:12.676806 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9600 00:56:12.680034 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9601 00:56:12.687063 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9602 00:56:12.689886 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9603 00:56:12.693590 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9604 00:56:12.700080 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9605 00:56:12.703637 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9606 00:56:12.709777 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9607 00:56:12.712944 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9608 00:56:12.716777 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9609 00:56:12.723323 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9610 00:56:12.726451 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9611 00:56:12.733142 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9612 00:56:12.735903 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9613 00:56:12.739597 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9614 00:56:12.746170 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9615 00:56:12.749385 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9616 00:56:12.756129 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9617 00:56:12.759354 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9618 00:56:12.762579 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9619 00:56:12.768933 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9620 00:56:12.772779 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9621 00:56:12.779278 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9622 00:56:12.782674 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9623 00:56:12.786028 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9624 00:56:12.792637 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9625 00:56:12.795623 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9626 00:56:12.799030 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9627 00:56:12.805097 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9628 00:56:12.808635 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9629 00:56:12.815368 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9630 00:56:12.818858 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9631 00:56:12.825220 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9632 00:56:12.828483 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9633 00:56:12.831814 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9634 00:56:12.838341 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9635 00:56:12.841597 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9636 00:56:12.848697 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9637 00:56:12.851724 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9638 00:56:12.854821 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9639 00:56:12.861740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9640 00:56:12.865340 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9641 00:56:12.871783 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9642 00:56:12.874752 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9643 00:56:12.878240 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9644 00:56:12.884815 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9645 00:56:12.887885 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9646 00:56:12.894237 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9647 00:56:12.897735 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9648 00:56:12.900942 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9649 00:56:12.907724 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9650 00:56:12.910528 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9651 00:56:12.917347 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9652 00:56:12.920537 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9653 00:56:12.923796 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9654 00:56:12.930347 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9655 00:56:12.933852 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9656 00:56:12.940670 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9657 00:56:12.943595 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9658 00:56:12.950379 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9659 00:56:12.953860 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9660 00:56:12.957115 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9661 00:56:12.963209 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9662 00:56:12.966474 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9663 00:56:12.973558 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9664 00:56:12.976737 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9665 00:56:12.982996 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9666 00:56:12.986552 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9667 00:56:12.989670 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9668 00:56:12.996329 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9669 00:56:12.999943 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9670 00:56:13.006098 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9671 00:56:13.009685 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9672 00:56:13.016246 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9673 00:56:13.019547 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9674 00:56:13.022784 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9675 00:56:13.029682 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9676 00:56:13.033106 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9677 00:56:13.039345 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9678 00:56:13.042341 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9679 00:56:13.046165 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9680 00:56:13.052386 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9681 00:56:13.055876 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9682 00:56:13.062544 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9683 00:56:13.065590 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9684 00:56:13.072321 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9685 00:56:13.075652 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9686 00:56:13.082248 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9687 00:56:13.085339 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9688 00:56:13.088725 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9689 00:56:13.095606 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9690 00:56:13.098731 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9691 00:56:13.104956 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9692 00:56:13.108495 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9693 00:56:13.114881 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9694 00:56:13.118275 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9695 00:56:13.121921 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9696 00:56:13.127991 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9697 00:56:13.131836 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9698 00:56:13.135028 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9699 00:56:13.138122 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9700 00:56:13.144342 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9701 00:56:13.147934 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9702 00:56:13.151258 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9703 00:56:13.157773 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9704 00:56:13.161186 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9705 00:56:13.167537 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9706 00:56:13.170968 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9707 00:56:13.174309 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9708 00:56:13.180979 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9709 00:56:13.184461 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9710 00:56:13.187308 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9711 00:56:13.194549 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9712 00:56:13.197227 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9713 00:56:13.200394 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9714 00:56:13.206862 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9715 00:56:13.210338 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9716 00:56:13.217368 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9717 00:56:13.220157 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9718 00:56:13.223740 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9719 00:56:13.230281 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9720 00:56:13.233352 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9721 00:56:13.236655 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9722 00:56:13.243215 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9723 00:56:13.246662 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9724 00:56:13.252885 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9725 00:56:13.256605 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9726 00:56:13.259430 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9727 00:56:13.266377 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9728 00:56:13.269634 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9729 00:56:13.276297 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9730 00:56:13.279629 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9731 00:56:13.282558 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9732 00:56:13.289917 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9733 00:56:13.293301 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9734 00:56:13.296346 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9735 00:56:13.302955 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9736 00:56:13.305996 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9737 00:56:13.309336 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9738 00:56:13.312821 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9739 00:56:13.319312 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9740 00:56:13.322810 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9741 00:56:13.325695 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9742 00:56:13.329023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9743 00:56:13.336113 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9744 00:56:13.339333 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9745 00:56:13.342517 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9746 00:56:13.345511 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9747 00:56:13.352124 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9748 00:56:13.355293 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9749 00:56:13.359159 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9750 00:56:13.365782 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9751 00:56:13.368549 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9752 00:56:13.375420 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9753 00:56:13.378802 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9754 00:56:13.384852 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9755 00:56:13.388350 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9756 00:56:13.391685 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9757 00:56:13.398142 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9758 00:56:13.401970 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9759 00:56:13.407948 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9760 00:56:13.411845 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9761 00:56:13.417927 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9762 00:56:13.421451 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9763 00:56:13.424281 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9764 00:56:13.430762 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9765 00:56:13.434463 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9766 00:56:13.441106 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9767 00:56:13.444292 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9768 00:56:13.447469 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9769 00:56:13.454009 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9770 00:56:13.457540 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9771 00:56:13.463814 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9772 00:56:13.467498 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9773 00:56:13.470885 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9774 00:56:13.477505 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9775 00:56:13.480552 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9776 00:56:13.487136 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9777 00:56:13.489963 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9778 00:56:13.497016 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9779 00:56:13.500370 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9780 00:56:13.507084 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9781 00:56:13.510289 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9782 00:56:13.513735 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9783 00:56:13.519953 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9784 00:56:13.523351 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9785 00:56:13.529856 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9786 00:56:13.533721 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9787 00:56:13.536917 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9788 00:56:13.543286 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9789 00:56:13.546733 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9790 00:56:13.552872 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9791 00:56:13.556947 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9792 00:56:13.559694 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9793 00:56:13.566297 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9794 00:56:13.569527 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9795 00:56:13.576226 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9796 00:56:13.579553 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9797 00:56:13.582794 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9798 00:56:13.589712 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9799 00:56:13.592750 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9800 00:56:13.599791 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9801 00:56:13.602384 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9802 00:56:13.608919 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9803 00:56:13.612200 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9804 00:56:13.618763 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9805 00:56:13.622420 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9806 00:56:13.625338 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9807 00:56:13.632075 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9808 00:56:13.635402 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9809 00:56:13.641707 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9810 00:56:13.644858 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9811 00:56:13.651675 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9812 00:56:13.655072 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9813 00:56:13.658057 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9814 00:56:13.664687 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9815 00:56:13.668025 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9816 00:56:13.674691 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9817 00:56:13.677859 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9818 00:56:13.681120 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9819 00:56:13.688161 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9820 00:56:13.691069 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9821 00:56:13.697974 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9822 00:56:13.701329 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9823 00:56:13.707595 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9824 00:56:13.710773 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9825 00:56:13.713997 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9826 00:56:13.720545 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9827 00:56:13.724069 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9828 00:56:13.730526 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9829 00:56:13.734763 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9830 00:56:13.740623 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9831 00:56:13.744261 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9832 00:56:13.747120 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9833 00:56:13.754131 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9834 00:56:13.757170 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9835 00:56:13.764047 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9836 00:56:13.767044 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9837 00:56:13.773914 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9838 00:56:13.777028 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9839 00:56:13.783338 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9840 00:56:13.786824 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9841 00:56:13.793758 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9842 00:56:13.797087 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9843 00:56:13.800001 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9844 00:56:13.806966 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9845 00:56:13.809771 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9846 00:56:13.816827 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9847 00:56:13.820262 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9848 00:56:13.826458 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9849 00:56:13.830182 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9850 00:56:13.836363 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9851 00:56:13.839814 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9852 00:56:13.842948 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9853 00:56:13.849578 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9854 00:56:13.852961 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9855 00:56:13.859515 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9856 00:56:13.862959 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9857 00:56:13.869176 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9858 00:56:13.872616 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9859 00:56:13.879212 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9860 00:56:13.882304 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9861 00:56:13.885399 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9862 00:56:13.892693 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9863 00:56:13.895474 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9864 00:56:13.902068 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9865 00:56:13.905251 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9866 00:56:13.912244 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9867 00:56:13.915711 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9868 00:56:13.921811 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9869 00:56:13.925491 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9870 00:56:13.928512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9871 00:56:13.935234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9872 00:56:13.938170 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9873 00:56:13.945007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9874 00:56:13.948614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9875 00:56:13.954747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9876 00:56:13.958820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9877 00:56:13.964598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9878 00:56:13.967761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9879 00:56:13.974872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9880 00:56:13.978056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9881 00:56:13.984496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9882 00:56:13.987660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9883 00:56:13.994779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9884 00:56:13.997889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9885 00:56:14.004478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9886 00:56:14.007519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9887 00:56:14.014567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9888 00:56:14.017736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9889 00:56:14.023901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9890 00:56:14.027139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9891 00:56:14.034141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9892 00:56:14.037380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9893 00:56:14.043574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9894 00:56:14.047293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9895 00:56:14.053381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9896 00:56:14.057171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9897 00:56:14.063433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9898 00:56:14.066523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9899 00:56:14.073097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9900 00:56:14.076636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9901 00:56:14.082860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9902 00:56:14.087020 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9903 00:56:14.089551 INFO: [APUAPC] vio 0
9904 00:56:14.093454 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9905 00:56:14.099313 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9906 00:56:14.102631 INFO: [APUAPC] D0_APC_0: 0x400510
9907 00:56:14.103053 INFO: [APUAPC] D0_APC_1: 0x0
9908 00:56:14.106089 INFO: [APUAPC] D0_APC_2: 0x1540
9909 00:56:14.109711 INFO: [APUAPC] D0_APC_3: 0x0
9910 00:56:14.113197 INFO: [APUAPC] D1_APC_0: 0xffffffff
9911 00:56:14.116564 INFO: [APUAPC] D1_APC_1: 0xffffffff
9912 00:56:14.119174 INFO: [APUAPC] D1_APC_2: 0x3fffff
9913 00:56:14.122610 INFO: [APUAPC] D1_APC_3: 0x0
9914 00:56:14.125958 INFO: [APUAPC] D2_APC_0: 0xffffffff
9915 00:56:14.129314 INFO: [APUAPC] D2_APC_1: 0xffffffff
9916 00:56:14.132521 INFO: [APUAPC] D2_APC_2: 0x3fffff
9917 00:56:14.135977 INFO: [APUAPC] D2_APC_3: 0x0
9918 00:56:14.139711 INFO: [APUAPC] D3_APC_0: 0xffffffff
9919 00:56:14.142307 INFO: [APUAPC] D3_APC_1: 0xffffffff
9920 00:56:14.145717 INFO: [APUAPC] D3_APC_2: 0x3fffff
9921 00:56:14.148931 INFO: [APUAPC] D3_APC_3: 0x0
9922 00:56:14.152230 INFO: [APUAPC] D4_APC_0: 0xffffffff
9923 00:56:14.155388 INFO: [APUAPC] D4_APC_1: 0xffffffff
9924 00:56:14.158824 INFO: [APUAPC] D4_APC_2: 0x3fffff
9925 00:56:14.162205 INFO: [APUAPC] D4_APC_3: 0x0
9926 00:56:14.165727 INFO: [APUAPC] D5_APC_0: 0xffffffff
9927 00:56:14.168623 INFO: [APUAPC] D5_APC_1: 0xffffffff
9928 00:56:14.172136 INFO: [APUAPC] D5_APC_2: 0x3fffff
9929 00:56:14.175765 INFO: [APUAPC] D5_APC_3: 0x0
9930 00:56:14.178383 INFO: [APUAPC] D6_APC_0: 0xffffffff
9931 00:56:14.182001 INFO: [APUAPC] D6_APC_1: 0xffffffff
9932 00:56:14.185705 INFO: [APUAPC] D6_APC_2: 0x3fffff
9933 00:56:14.188442 INFO: [APUAPC] D6_APC_3: 0x0
9934 00:56:14.191950 INFO: [APUAPC] D7_APC_0: 0xffffffff
9935 00:56:14.195157 INFO: [APUAPC] D7_APC_1: 0xffffffff
9936 00:56:14.198343 INFO: [APUAPC] D7_APC_2: 0x3fffff
9937 00:56:14.201687 INFO: [APUAPC] D7_APC_3: 0x0
9938 00:56:14.204938 INFO: [APUAPC] D8_APC_0: 0xffffffff
9939 00:56:14.208270 INFO: [APUAPC] D8_APC_1: 0xffffffff
9940 00:56:14.211975 INFO: [APUAPC] D8_APC_2: 0x3fffff
9941 00:56:14.214918 INFO: [APUAPC] D8_APC_3: 0x0
9942 00:56:14.218048 INFO: [APUAPC] D9_APC_0: 0xffffffff
9943 00:56:14.221079 INFO: [APUAPC] D9_APC_1: 0xffffffff
9944 00:56:14.224525 INFO: [APUAPC] D9_APC_2: 0x3fffff
9945 00:56:14.227968 INFO: [APUAPC] D9_APC_3: 0x0
9946 00:56:14.231335 INFO: [APUAPC] D10_APC_0: 0xffffffff
9947 00:56:14.234521 INFO: [APUAPC] D10_APC_1: 0xffffffff
9948 00:56:14.237680 INFO: [APUAPC] D10_APC_2: 0x3fffff
9949 00:56:14.241042 INFO: [APUAPC] D10_APC_3: 0x0
9950 00:56:14.244323 INFO: [APUAPC] D11_APC_0: 0xffffffff
9951 00:56:14.247851 INFO: [APUAPC] D11_APC_1: 0xffffffff
9952 00:56:14.250902 INFO: [APUAPC] D11_APC_2: 0x3fffff
9953 00:56:14.254298 INFO: [APUAPC] D11_APC_3: 0x0
9954 00:56:14.257996 INFO: [APUAPC] D12_APC_0: 0xffffffff
9955 00:56:14.261284 INFO: [APUAPC] D12_APC_1: 0xffffffff
9956 00:56:14.264113 INFO: [APUAPC] D12_APC_2: 0x3fffff
9957 00:56:14.267757 INFO: [APUAPC] D12_APC_3: 0x0
9958 00:56:14.270646 INFO: [APUAPC] D13_APC_0: 0xffffffff
9959 00:56:14.274051 INFO: [APUAPC] D13_APC_1: 0xffffffff
9960 00:56:14.277698 INFO: [APUAPC] D13_APC_2: 0x3fffff
9961 00:56:14.280778 INFO: [APUAPC] D13_APC_3: 0x0
9962 00:56:14.283842 INFO: [APUAPC] D14_APC_0: 0xffffffff
9963 00:56:14.287202 INFO: [APUAPC] D14_APC_1: 0xffffffff
9964 00:56:14.290756 INFO: [APUAPC] D14_APC_2: 0x3fffff
9965 00:56:14.294176 INFO: [APUAPC] D14_APC_3: 0x0
9966 00:56:14.296928 INFO: [APUAPC] D15_APC_0: 0xffffffff
9967 00:56:14.300441 INFO: [APUAPC] D15_APC_1: 0xffffffff
9968 00:56:14.303732 INFO: [APUAPC] D15_APC_2: 0x3fffff
9969 00:56:14.307494 INFO: [APUAPC] D15_APC_3: 0x0
9970 00:56:14.310087 INFO: [APUAPC] APC_CON: 0x4
9971 00:56:14.313550 INFO: [NOCDAPC] D0_APC_0: 0x0
9972 00:56:14.317146 INFO: [NOCDAPC] D0_APC_1: 0x0
9973 00:56:14.320508 INFO: [NOCDAPC] D1_APC_0: 0x0
9974 00:56:14.323843 INFO: [NOCDAPC] D1_APC_1: 0xfff
9975 00:56:14.324268 INFO: [NOCDAPC] D2_APC_0: 0x0
9976 00:56:14.327087 INFO: [NOCDAPC] D2_APC_1: 0xfff
9977 00:56:14.329916 INFO: [NOCDAPC] D3_APC_0: 0x0
9978 00:56:14.333621 INFO: [NOCDAPC] D3_APC_1: 0xfff
9979 00:56:14.336925 INFO: [NOCDAPC] D4_APC_0: 0x0
9980 00:56:14.340081 INFO: [NOCDAPC] D4_APC_1: 0xfff
9981 00:56:14.343438 INFO: [NOCDAPC] D5_APC_0: 0x0
9982 00:56:14.346752 INFO: [NOCDAPC] D5_APC_1: 0xfff
9983 00:56:14.350027 INFO: [NOCDAPC] D6_APC_0: 0x0
9984 00:56:14.353521 INFO: [NOCDAPC] D6_APC_1: 0xfff
9985 00:56:14.357173 INFO: [NOCDAPC] D7_APC_0: 0x0
9986 00:56:14.359943 INFO: [NOCDAPC] D7_APC_1: 0xfff
9987 00:56:14.360366 INFO: [NOCDAPC] D8_APC_0: 0x0
9988 00:56:14.363395 INFO: [NOCDAPC] D8_APC_1: 0xfff
9989 00:56:14.366765 INFO: [NOCDAPC] D9_APC_0: 0x0
9990 00:56:14.369767 INFO: [NOCDAPC] D9_APC_1: 0xfff
9991 00:56:14.373211 INFO: [NOCDAPC] D10_APC_0: 0x0
9992 00:56:14.376518 INFO: [NOCDAPC] D10_APC_1: 0xfff
9993 00:56:14.379962 INFO: [NOCDAPC] D11_APC_0: 0x0
9994 00:56:14.382742 INFO: [NOCDAPC] D11_APC_1: 0xfff
9995 00:56:14.386196 INFO: [NOCDAPC] D12_APC_0: 0x0
9996 00:56:14.389335 INFO: [NOCDAPC] D12_APC_1: 0xfff
9997 00:56:14.393041 INFO: [NOCDAPC] D13_APC_0: 0x0
9998 00:56:14.395939 INFO: [NOCDAPC] D13_APC_1: 0xfff
9999 00:56:14.399543 INFO: [NOCDAPC] D14_APC_0: 0x0
10000 00:56:14.402496 INFO: [NOCDAPC] D14_APC_1: 0xfff
10001 00:56:14.406105 INFO: [NOCDAPC] D15_APC_0: 0x0
10002 00:56:14.409321 INFO: [NOCDAPC] D15_APC_1: 0xfff
10003 00:56:14.409742 INFO: [NOCDAPC] APC_CON: 0x4
10004 00:56:14.412859 INFO: [APUAPC] set_apusys_apc done
10005 00:56:14.415730 INFO: [DEVAPC] devapc_init done
10006 00:56:14.422884 INFO: GICv3 without legacy support detected.
10007 00:56:14.425665 INFO: ARM GICv3 driver initialized in EL3
10008 00:56:14.429017 INFO: Maximum SPI INTID supported: 639
10009 00:56:14.432208 INFO: BL31: Initializing runtime services
10010 00:56:14.438755 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10011 00:56:14.442399 INFO: SPM: enable CPC mode
10012 00:56:14.445418 INFO: mcdi ready for mcusys-off-idle and system suspend
10013 00:56:14.452359 INFO: BL31: Preparing for EL3 exit to normal world
10014 00:56:14.455132 INFO: Entry point address = 0x80000000
10015 00:56:14.455572 INFO: SPSR = 0x8
10016 00:56:14.463298
10017 00:56:14.463726
10018 00:56:14.464062
10019 00:56:14.465992 Starting depthcharge on Spherion...
10020 00:56:14.466445
10021 00:56:14.466779 Wipe memory regions:
10022 00:56:14.467102
10023 00:56:14.469343 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10024 00:56:14.469906 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10025 00:56:14.470331 Setting prompt string to ['asurada:']
10026 00:56:14.470738 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10027 00:56:14.471418 [0x00000040000000, 0x00000054600000)
10028 00:56:14.591359
10029 00:56:14.591852 [0x00000054660000, 0x00000080000000)
10030 00:56:14.851480
10031 00:56:14.851616 [0x000000821a7280, 0x000000ffe64000)
10032 00:56:15.595003
10033 00:56:15.595139 [0x00000100000000, 0x00000240000000)
10034 00:56:17.482675
10035 00:56:17.485872 Initializing XHCI USB controller at 0x11200000.
10036 00:56:18.523553
10037 00:56:18.526811 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10038 00:56:18.526904
10039 00:56:18.526971
10040 00:56:18.527255 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10042 00:56:18.627595 asurada: tftpboot 192.168.201.1 14368601/tftp-deploy-kt0gpwp2/kernel/image.itb 14368601/tftp-deploy-kt0gpwp2/kernel/cmdline
10043 00:56:18.627745 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10044 00:56:18.627830 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10045 00:56:18.632185 tftpboot 192.168.201.1 14368601/tftp-deploy-kt0gpwp2/kernel/image.itp-deploy-kt0gpwp2/kernel/cmdline
10046 00:56:18.632270
10047 00:56:18.632335 Waiting for link
10048 00:56:18.790497
10049 00:56:18.790631 R8152: Initializing
10050 00:56:18.790698
10051 00:56:18.793401 Version 6 (ocp_data = 5c30)
10052 00:56:18.793484
10053 00:56:18.796521 R8152: Done initializing
10054 00:56:18.796637
10055 00:56:18.796734 Adding net device
10056 00:56:20.702394
10057 00:56:20.702563 done.
10058 00:56:20.702663
10059 00:56:20.702756 MAC: 00:24:32:30:7c:7b
10060 00:56:20.702845
10061 00:56:20.705921 Sending DHCP discover... done.
10062 00:56:20.706022
10063 00:56:20.708770 Waiting for reply... done.
10064 00:56:20.708871
10065 00:56:20.712348 Sending DHCP request... done.
10066 00:56:20.712458
10067 00:56:20.717164 Waiting for reply... done.
10068 00:56:20.717308
10069 00:56:20.717407 My ip is 192.168.201.14
10070 00:56:20.717488
10071 00:56:20.720624 The DHCP server ip is 192.168.201.1
10072 00:56:20.720730
10073 00:56:20.727315 TFTP server IP predefined by user: 192.168.201.1
10074 00:56:20.727420
10075 00:56:20.733872 Bootfile predefined by user: 14368601/tftp-deploy-kt0gpwp2/kernel/image.itb
10076 00:56:20.733951
10077 00:56:20.737013 Sending tftp read request... done.
10078 00:56:20.737113
10079 00:56:20.740613 Waiting for the transfer...
10080 00:56:20.740717
10081 00:56:21.260684 00000000 ################################################################
10082 00:56:21.260851
10083 00:56:21.781157 00080000 ################################################################
10084 00:56:21.781361
10085 00:56:22.299335 00100000 ################################################################
10086 00:56:22.299479
10087 00:56:22.826610 00180000 ################################################################
10088 00:56:22.826783
10089 00:56:23.345757 00200000 ################################################################
10090 00:56:23.345896
10091 00:56:23.862561 00280000 ################################################################
10092 00:56:23.862732
10093 00:56:24.379142 00300000 ################################################################
10094 00:56:24.379272
10095 00:56:24.905483 00380000 ################################################################
10096 00:56:24.905624
10097 00:56:25.418248 00400000 ################################################################
10098 00:56:25.418384
10099 00:56:25.940418 00480000 ################################################################
10100 00:56:25.940554
10101 00:56:26.459199 00500000 ################################################################
10102 00:56:26.459356
10103 00:56:26.974287 00580000 ################################################################
10104 00:56:26.974477
10105 00:56:27.491888 00600000 ################################################################
10106 00:56:27.492060
10107 00:56:28.009616 00680000 ################################################################
10108 00:56:28.009753
10109 00:56:28.530488 00700000 ################################################################
10110 00:56:28.530623
10111 00:56:29.047695 00780000 ################################################################
10112 00:56:29.047827
10113 00:56:29.566871 00800000 ################################################################
10114 00:56:29.567009
10115 00:56:30.081274 00880000 ################################################################
10116 00:56:30.081408
10117 00:56:30.605008 00900000 ################################################################
10118 00:56:30.605182
10119 00:56:31.121992 00980000 ################################################################
10120 00:56:31.122135
10121 00:56:31.642488 00a00000 ################################################################
10122 00:56:31.642634
10123 00:56:32.163378 00a80000 ################################################################
10124 00:56:32.163508
10125 00:56:32.678487 00b00000 ################################################################
10126 00:56:32.678621
10127 00:56:33.202754 00b80000 ################################################################
10128 00:56:33.202888
10129 00:56:33.719273 00c00000 ################################################################
10130 00:56:33.719408
10131 00:56:34.236057 00c80000 ################################################################
10132 00:56:34.236186
10133 00:56:34.842924 00d00000 ################################################################
10134 00:56:34.843426
10135 00:56:35.488953 00d80000 ################################################################
10136 00:56:35.489590
10137 00:56:36.176137 00e00000 ################################################################
10138 00:56:36.176630
10139 00:56:36.797913 00e80000 ################################################################
10140 00:56:36.798528
10141 00:56:37.436658 00f00000 ################################################################
10142 00:56:37.437151
10143 00:56:38.116386 00f80000 ################################################################
10144 00:56:38.116876
10145 00:56:38.805131 01000000 ################################################################
10146 00:56:38.805676
10147 00:56:39.496088 01080000 ################################################################
10148 00:56:39.496610
10149 00:56:40.180245 01100000 ################################################################
10150 00:56:40.180760
10151 00:56:40.875785 01180000 ################################################################
10152 00:56:40.876328
10153 00:56:41.549607 01200000 ################################################################
10154 00:56:41.550166
10155 00:56:42.232664 01280000 ################################################################
10156 00:56:42.233175
10157 00:56:42.912399 01300000 ################################################################
10158 00:56:42.912945
10159 00:56:43.625063 01380000 ################################################################
10160 00:56:43.625633
10161 00:56:44.316399 01400000 ################################################################
10162 00:56:44.317047
10163 00:56:44.983058 01480000 ################################################################
10164 00:56:44.983559
10165 00:56:45.637457 01500000 ################################################################
10166 00:56:45.638128
10167 00:56:46.246879 01580000 ################################################################
10168 00:56:46.247020
10169 00:56:46.841995 01600000 ################################################################
10170 00:56:46.842139
10171 00:56:47.496150 01680000 ################################################################
10172 00:56:47.496288
10173 00:56:48.179897 01700000 ################################################################
10174 00:56:48.180523
10175 00:56:48.832530 01780000 ################################################################
10176 00:56:48.833246
10177 00:56:49.482961 01800000 ################################################################
10178 00:56:49.483455
10179 00:56:50.137595 01880000 ################################################################
10180 00:56:50.137734
10181 00:56:50.808885 01900000 ################################################################
10182 00:56:50.809053
10183 00:56:51.417961 01980000 ################################################################
10184 00:56:51.418127
10185 00:56:51.958276 01a00000 ################################################################
10186 00:56:51.958424
10187 00:56:52.497373 01a80000 ################################################################
10188 00:56:52.497504
10189 00:56:53.170324 01b00000 ################################################################
10190 00:56:53.170457
10191 00:56:53.845022 01b80000 ################################################################
10192 00:56:53.845162
10193 00:56:54.444941 01c00000 ################################################################
10194 00:56:54.445078
10195 00:56:55.020912 01c80000 ################################################################
10196 00:56:55.021082
10197 00:56:55.630966 01d00000 ################################################################
10198 00:56:55.631102
10199 00:56:56.262109 01d80000 ################################################################
10200 00:56:56.262483
10201 00:56:56.937842 01e00000 ################################################################
10202 00:56:56.938410
10203 00:56:57.594459 01e80000 ################################################################
10204 00:56:57.594953
10205 00:56:58.194124 01f00000 ################################################################
10206 00:56:58.194261
10207 00:56:58.751924 01f80000 ################################################################
10208 00:56:58.752080
10209 00:56:59.333114 02000000 ################################################################
10210 00:56:59.333387
10211 00:56:59.956012 02080000 ################################################################
10212 00:56:59.956523
10213 00:57:00.612779 02100000 ################################################################
10214 00:57:00.613318
10215 00:57:01.286069 02180000 ################################################################
10216 00:57:01.286574
10217 00:57:01.958696 02200000 ################################################################
10218 00:57:01.958858
10219 00:57:02.579407 02280000 ################################################################
10220 00:57:02.579950
10221 00:57:03.274814 02300000 ################################################################
10222 00:57:03.275004
10223 00:57:03.965154 02380000 ################################################################
10224 00:57:03.965746
10225 00:57:04.670548 02400000 ################################################################
10226 00:57:04.671144
10227 00:57:05.267374 02480000 ################################################################
10228 00:57:05.267544
10229 00:57:05.874589 02500000 ################################################################
10230 00:57:05.874739
10231 00:57:06.510948 02580000 ################################################################
10232 00:57:06.511096
10233 00:57:07.094401 02600000 ################################################################
10234 00:57:07.094549
10235 00:57:07.749903 02680000 ################################################################
10236 00:57:07.750420
10237 00:57:08.356252 02700000 ################################################################
10238 00:57:08.356396
10239 00:57:08.922494 02780000 ################################################################
10240 00:57:08.922639
10241 00:57:09.513503 02800000 ################################################################
10242 00:57:09.513654
10243 00:57:10.086295 02880000 ################################################################
10244 00:57:10.086445
10245 00:57:10.674142 02900000 ################################################################
10246 00:57:10.674315
10247 00:57:11.273220 02980000 ################################################################
10248 00:57:11.273781
10249 00:57:11.871257 02a00000 ################################################################
10250 00:57:11.871391
10251 00:57:12.522569 02a80000 ################################################################
10252 00:57:12.522717
10253 00:57:13.189350 02b00000 ################################################################
10254 00:57:13.189896
10255 00:57:13.759314 02b80000 ################################################################
10256 00:57:13.759462
10257 00:57:14.397842 02c00000 ################################################################
10258 00:57:14.398362
10259 00:57:15.046066 02c80000 ################################################################
10260 00:57:15.046389
10261 00:57:15.731572 02d00000 ################################################################
10262 00:57:15.732067
10263 00:57:16.425311 02d80000 ################################################################
10264 00:57:16.425810
10265 00:57:17.094135 02e00000 ################################################################
10266 00:57:17.094670
10267 00:57:17.766565 02e80000 ################################################################
10268 00:57:17.767143
10269 00:57:18.366352 02f00000 ################################################################
10270 00:57:18.366483
10271 00:57:18.985355 02f80000 ################################################################
10272 00:57:18.985847
10273 00:57:19.586179 03000000 ################################################################
10274 00:57:19.586318
10275 00:57:20.182549 03080000 ################################################################
10276 00:57:20.182788
10277 00:57:20.771294 03100000 ################################################################
10278 00:57:20.771429
10279 00:57:21.382252 03180000 ################################################################
10280 00:57:21.382386
10281 00:57:21.969534 03200000 ################################################################
10282 00:57:21.969672
10283 00:57:22.594468 03280000 ################################################################
10284 00:57:22.595153
10285 00:57:23.211709 03300000 ################################################################
10286 00:57:23.211848
10287 00:57:23.646925 03380000 ############################################### done.
10288 00:57:23.647060
10289 00:57:23.650377 The bootfile was 54386526 bytes long.
10290 00:57:23.650463
10291 00:57:23.653768 Sending tftp read request... done.
10292 00:57:23.653851
10293 00:57:23.653916 Waiting for the transfer...
10294 00:57:23.653977
10295 00:57:23.656858 00000000 # done.
10296 00:57:23.656941
10297 00:57:23.664021 Command line loaded dynamically from TFTP file: 14368601/tftp-deploy-kt0gpwp2/kernel/cmdline
10298 00:57:23.664117
10299 00:57:23.676760 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10300 00:57:23.676849
10301 00:57:23.680568 Loading FIT.
10302 00:57:23.680656
10303 00:57:23.683208 Image ramdisk-1 has 41212186 bytes.
10304 00:57:23.683302
10305 00:57:23.686990 Image fdt-1 has 47258 bytes.
10306 00:57:23.687083
10307 00:57:23.690053 Image kernel-1 has 13125045 bytes.
10308 00:57:23.690155
10309 00:57:23.697163 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10310 00:57:23.697295
10311 00:57:23.716801 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10312 00:57:23.716986
10313 00:57:23.720345 Choosing best match conf-1 for compat google,spherion-rev2.
10314 00:57:23.724769
10315 00:57:23.729102 Connected to device vid:did:rid of 1ae0:0028:00
10316 00:57:23.737913
10317 00:57:23.741580 tpm_get_response: command 0x17b, return code 0x0
10318 00:57:23.742001
10319 00:57:23.744359 ec_init: CrosEC protocol v3 supported (256, 248)
10320 00:57:23.748569
10321 00:57:23.751506 tpm_cleanup: add release locality here.
10322 00:57:23.752069
10323 00:57:23.752544 Shutting down all USB controllers.
10324 00:57:23.756238
10325 00:57:23.756760 Removing current net device
10326 00:57:23.757317
10327 00:57:23.761433 Exiting depthcharge with code 4 at timestamp: 98607365
10328 00:57:23.761856
10329 00:57:23.765174 LZMA decompressing kernel-1 to 0x821a6718
10330 00:57:23.765655
10331 00:57:23.768211 LZMA decompressing kernel-1 to 0x40000000
10332 00:57:25.384366
10333 00:57:25.384523 jumping to kernel
10334 00:57:25.385118 end: 2.2.4 bootloader-commands (duration 00:01:11) [common]
10335 00:57:25.385243 start: 2.2.5 auto-login-action (timeout 00:03:16) [common]
10336 00:57:25.385344 Setting prompt string to ['Linux version [0-9]']
10337 00:57:25.385429 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10338 00:57:25.385515 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10339 00:57:25.466288
10340 00:57:25.469534 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10341 00:57:25.473590 start: 2.2.5.1 login-action (timeout 00:03:16) [common]
10342 00:57:25.474259 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10343 00:57:25.474633 Setting prompt string to []
10344 00:57:25.475016 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10345 00:57:25.475386 Using line separator: #'\n'#
10346 00:57:25.475707 No login prompt set.
10347 00:57:25.476016 Parsing kernel messages
10348 00:57:25.476300 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10349 00:57:25.476808 [login-action] Waiting for messages, (timeout 00:03:16)
10350 00:57:25.477143 Waiting using forced prompt support (timeout 00:01:38)
10351 00:57:25.492655 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
10352 00:57:25.496114 [ 0.000000] random: crng init done
10353 00:57:25.502539 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10354 00:57:25.503116 [ 0.000000] efi: UEFI not found.
10355 00:57:25.512718 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10356 00:57:25.519399 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10357 00:57:25.529874 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10358 00:57:25.539549 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10359 00:57:25.545793 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10360 00:57:25.552182 [ 0.000000] printk: bootconsole [mtk8250] enabled
10361 00:57:25.559563 [ 0.000000] NUMA: No NUMA configuration found
10362 00:57:25.565894 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10363 00:57:25.569024 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10364 00:57:25.572126 [ 0.000000] Zone ranges:
10365 00:57:25.578807 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10366 00:57:25.582097 [ 0.000000] DMA32 empty
10367 00:57:25.588886 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10368 00:57:25.591959 [ 0.000000] Movable zone start for each node
10369 00:57:25.595203 [ 0.000000] Early memory node ranges
10370 00:57:25.602238 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10371 00:57:25.608792 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10372 00:57:25.615137 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10373 00:57:25.622325 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10374 00:57:25.625288 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10375 00:57:25.632243 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10376 00:57:25.690619 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10377 00:57:25.697749 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10378 00:57:25.703681 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10379 00:57:25.707276 [ 0.000000] psci: probing for conduit method from DT.
10380 00:57:25.713996 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10381 00:57:25.717225 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10382 00:57:25.724080 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10383 00:57:25.727116 [ 0.000000] psci: SMC Calling Convention v1.2
10384 00:57:25.734019 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10385 00:57:25.737519 [ 0.000000] Detected VIPT I-cache on CPU0
10386 00:57:25.743891 [ 0.000000] CPU features: detected: GIC system register CPU interface
10387 00:57:25.750705 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10388 00:57:25.757252 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10389 00:57:25.763604 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10390 00:57:25.770015 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10391 00:57:25.776976 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10392 00:57:25.783385 [ 0.000000] alternatives: applying boot alternatives
10393 00:57:25.786931 [ 0.000000] Fallback order for Node 0: 0
10394 00:57:25.796796 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10395 00:57:25.797340 [ 0.000000] Policy zone: Normal
10396 00:57:25.813059 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10397 00:57:25.823337 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10398 00:57:25.833968 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10399 00:57:25.843891 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10400 00:57:25.851175 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10401 00:57:25.854021 <6>[ 0.000000] software IO TLB: area num 8.
10402 00:57:25.910196 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10403 00:57:26.059546 <6>[ 0.000000] Memory: 7923812K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 428956K reserved, 32768K cma-reserved)
10404 00:57:26.066211 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10405 00:57:26.072409 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10406 00:57:26.075733 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10407 00:57:26.082467 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10408 00:57:26.088999 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10409 00:57:26.092402 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10410 00:57:26.102170 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10411 00:57:26.108847 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10412 00:57:26.112585 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10413 00:57:26.120312 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10414 00:57:26.123307 <6>[ 0.000000] GICv3: 608 SPIs implemented
10415 00:57:26.130431 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10416 00:57:26.133928 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10417 00:57:26.137135 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10418 00:57:26.147129 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10419 00:57:26.156494 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10420 00:57:26.169950 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10421 00:57:26.176239 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10422 00:57:26.185464 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10423 00:57:26.199127 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10424 00:57:26.206161 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10425 00:57:26.212652 <6>[ 0.009179] Console: colour dummy device 80x25
10426 00:57:26.222421 <6>[ 0.013937] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10427 00:57:26.225607 <6>[ 0.024379] pid_max: default: 32768 minimum: 301
10428 00:57:26.232185 <6>[ 0.029280] LSM: Security Framework initializing
10429 00:57:26.239244 <6>[ 0.034220] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10430 00:57:26.249323 <6>[ 0.042034] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10431 00:57:26.255508 <6>[ 0.051455] cblist_init_generic: Setting adjustable number of callback queues.
10432 00:57:26.262004 <6>[ 0.058944] cblist_init_generic: Setting shift to 3 and lim to 1.
10433 00:57:26.271958 <6>[ 0.065283] cblist_init_generic: Setting adjustable number of callback queues.
10434 00:57:26.275855 <6>[ 0.072709] cblist_init_generic: Setting shift to 3 and lim to 1.
10435 00:57:26.282365 <6>[ 0.079144] rcu: Hierarchical SRCU implementation.
10436 00:57:26.289323 <6>[ 0.084159] rcu: Max phase no-delay instances is 1000.
10437 00:57:26.295540 <6>[ 0.091220] EFI services will not be available.
10438 00:57:26.298449 <6>[ 0.096178] smp: Bringing up secondary CPUs ...
10439 00:57:26.306789 <6>[ 0.101231] Detected VIPT I-cache on CPU1
10440 00:57:26.313041 <6>[ 0.101301] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10441 00:57:26.319887 <6>[ 0.101332] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10442 00:57:26.323060 <6>[ 0.101672] Detected VIPT I-cache on CPU2
10443 00:57:26.329663 <6>[ 0.101724] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10444 00:57:26.339969 <6>[ 0.101742] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10445 00:57:26.343379 <6>[ 0.102005] Detected VIPT I-cache on CPU3
10446 00:57:26.350066 <6>[ 0.102053] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10447 00:57:26.356569 <6>[ 0.102068] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10448 00:57:26.360200 <6>[ 0.102373] CPU features: detected: Spectre-v4
10449 00:57:26.366685 <6>[ 0.102379] CPU features: detected: Spectre-BHB
10450 00:57:26.370100 <6>[ 0.102385] Detected PIPT I-cache on CPU4
10451 00:57:26.376516 <6>[ 0.102445] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10452 00:57:26.383511 <6>[ 0.102462] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10453 00:57:26.390051 <6>[ 0.102757] Detected PIPT I-cache on CPU5
10454 00:57:26.396816 <6>[ 0.102820] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10455 00:57:26.403427 <6>[ 0.102836] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10456 00:57:26.406334 <6>[ 0.103120] Detected PIPT I-cache on CPU6
10457 00:57:26.412727 <6>[ 0.103186] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10458 00:57:26.419451 <6>[ 0.103202] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10459 00:57:26.426087 <6>[ 0.103501] Detected PIPT I-cache on CPU7
10460 00:57:26.432622 <6>[ 0.103566] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10461 00:57:26.439610 <6>[ 0.103582] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10462 00:57:26.442818 <6>[ 0.103630] smp: Brought up 1 node, 8 CPUs
10463 00:57:26.449183 <6>[ 0.244970] SMP: Total of 8 processors activated.
10464 00:57:26.453324 <6>[ 0.249891] CPU features: detected: 32-bit EL0 Support
10465 00:57:26.463217 <6>[ 0.255288] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10466 00:57:26.469806 <6>[ 0.264088] CPU features: detected: Common not Private translations
10467 00:57:26.472964 <6>[ 0.270564] CPU features: detected: CRC32 instructions
10468 00:57:26.479437 <6>[ 0.275949] CPU features: detected: RCpc load-acquire (LDAPR)
10469 00:57:26.485814 <6>[ 0.281909] CPU features: detected: LSE atomic instructions
10470 00:57:26.492713 <6>[ 0.287691] CPU features: detected: Privileged Access Never
10471 00:57:26.496173 <6>[ 0.293470] CPU features: detected: RAS Extension Support
10472 00:57:26.506100 <6>[ 0.299079] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10473 00:57:26.509593 <6>[ 0.306301] CPU: All CPU(s) started at EL2
10474 00:57:26.515572 <6>[ 0.310645] alternatives: applying system-wide alternatives
10475 00:57:26.524527 <6>[ 0.321527] devtmpfs: initialized
10476 00:57:26.536338 <6>[ 0.330164] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10477 00:57:26.546478 <6>[ 0.340124] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10478 00:57:26.553305 <6>[ 0.348148] pinctrl core: initialized pinctrl subsystem
10479 00:57:26.556675 <6>[ 0.354824] DMI not present or invalid.
10480 00:57:26.562971 <6>[ 0.359232] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10481 00:57:26.572630 <6>[ 0.366077] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10482 00:57:26.579907 <6>[ 0.373667] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10483 00:57:26.589395 <6>[ 0.381884] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10484 00:57:26.592777 <6>[ 0.390126] audit: initializing netlink subsys (disabled)
10485 00:57:26.602668 <5>[ 0.395815] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10486 00:57:26.609160 <6>[ 0.396530] thermal_sys: Registered thermal governor 'step_wise'
10487 00:57:26.616372 <6>[ 0.403781] thermal_sys: Registered thermal governor 'power_allocator'
10488 00:57:26.619321 <6>[ 0.410035] cpuidle: using governor menu
10489 00:57:26.625946 <6>[ 0.420996] NET: Registered PF_QIPCRTR protocol family
10490 00:57:26.632636 <6>[ 0.426473] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10491 00:57:26.635929 <6>[ 0.433576] ASID allocator initialised with 32768 entries
10492 00:57:26.643435 <6>[ 0.440146] Serial: AMBA PL011 UART driver
10493 00:57:26.651820 <4>[ 0.448968] Trying to register duplicate clock ID: 134
10494 00:57:26.710077 <6>[ 0.510489] KASLR enabled
10495 00:57:26.724571 <6>[ 0.518162] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10496 00:57:26.731160 <6>[ 0.525177] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10497 00:57:26.737804 <6>[ 0.531667] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10498 00:57:26.744428 <6>[ 0.538671] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10499 00:57:26.750955 <6>[ 0.545158] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10500 00:57:26.757447 <6>[ 0.552166] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10501 00:57:26.764218 <6>[ 0.558652] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10502 00:57:26.770702 <6>[ 0.565654] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10503 00:57:26.774306 <6>[ 0.573167] ACPI: Interpreter disabled.
10504 00:57:26.782482 <6>[ 0.579588] iommu: Default domain type: Translated
10505 00:57:26.788889 <6>[ 0.584699] iommu: DMA domain TLB invalidation policy: strict mode
10506 00:57:26.792931 <5>[ 0.591359] SCSI subsystem initialized
10507 00:57:26.798953 <6>[ 0.595525] usbcore: registered new interface driver usbfs
10508 00:57:26.806016 <6>[ 0.601258] usbcore: registered new interface driver hub
10509 00:57:26.808625 <6>[ 0.606809] usbcore: registered new device driver usb
10510 00:57:26.816412 <6>[ 0.612901] pps_core: LinuxPPS API ver. 1 registered
10511 00:57:26.825617 <6>[ 0.618095] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10512 00:57:26.828797 <6>[ 0.627440] PTP clock support registered
10513 00:57:26.831903 <6>[ 0.631678] EDAC MC: Ver: 3.0.0
10514 00:57:26.839974 <6>[ 0.636816] FPGA manager framework
10515 00:57:26.846552 <6>[ 0.640501] Advanced Linux Sound Architecture Driver Initialized.
10516 00:57:26.849731 <6>[ 0.647275] vgaarb: loaded
10517 00:57:26.856124 <6>[ 0.650422] clocksource: Switched to clocksource arch_sys_counter
10518 00:57:26.859818 <5>[ 0.656859] VFS: Disk quotas dquot_6.6.0
10519 00:57:26.866713 <6>[ 0.661049] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10520 00:57:26.869139 <6>[ 0.668239] pnp: PnP ACPI: disabled
10521 00:57:26.878033 <6>[ 0.674925] NET: Registered PF_INET protocol family
10522 00:57:26.887734 <6>[ 0.680518] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10523 00:57:26.899335 <6>[ 0.692834] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10524 00:57:26.909063 <6>[ 0.701650] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10525 00:57:26.915749 <6>[ 0.709619] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10526 00:57:26.922648 <6>[ 0.718316] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10527 00:57:26.934795 <6>[ 0.728070] TCP: Hash tables configured (established 65536 bind 65536)
10528 00:57:26.941006 <6>[ 0.734937] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10529 00:57:26.947880 <6>[ 0.742136] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10530 00:57:26.954008 <6>[ 0.749838] NET: Registered PF_UNIX/PF_LOCAL protocol family
10531 00:57:26.960900 <6>[ 0.755989] RPC: Registered named UNIX socket transport module.
10532 00:57:26.964077 <6>[ 0.762145] RPC: Registered udp transport module.
10533 00:57:26.970552 <6>[ 0.767078] RPC: Registered tcp transport module.
10534 00:57:26.977098 <6>[ 0.772011] RPC: Registered tcp NFSv4.1 backchannel transport module.
10535 00:57:26.980232 <6>[ 0.778676] PCI: CLS 0 bytes, default 64
10536 00:57:26.984044 <6>[ 0.783084] Unpacking initramfs...
10537 00:57:26.993604 <6>[ 0.786811] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10538 00:57:27.000346 <6>[ 0.795438] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10539 00:57:27.007232 <6>[ 0.804277] kvm [1]: IPA Size Limit: 40 bits
10540 00:57:27.010488 <6>[ 0.808805] kvm [1]: GICv3: no GICV resource entry
10541 00:57:27.017457 <6>[ 0.813826] kvm [1]: disabling GICv2 emulation
10542 00:57:27.023551 <6>[ 0.818511] kvm [1]: GIC system register CPU interface enabled
10543 00:57:27.026928 <6>[ 0.824678] kvm [1]: vgic interrupt IRQ18
10544 00:57:27.033943 <6>[ 0.830594] kvm [1]: VHE mode initialized successfully
10545 00:57:27.040704 <5>[ 0.836975] Initialise system trusted keyrings
10546 00:57:27.046560 <6>[ 0.841779] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10547 00:57:27.055208 <6>[ 0.851656] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10548 00:57:27.061334 <5>[ 0.858048] NFS: Registering the id_resolver key type
10549 00:57:27.064851 <5>[ 0.863362] Key type id_resolver registered
10550 00:57:27.071277 <5>[ 0.867776] Key type id_legacy registered
10551 00:57:27.077783 <6>[ 0.872051] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10552 00:57:27.084712 <6>[ 0.878974] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10553 00:57:27.090846 <6>[ 0.886696] 9p: Installing v9fs 9p2000 file system support
10554 00:57:27.127969 <5>[ 0.924907] Key type asymmetric registered
10555 00:57:27.131072 <5>[ 0.929238] Asymmetric key parser 'x509' registered
10556 00:57:27.141190 <6>[ 0.934377] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10557 00:57:27.144120 <6>[ 0.941992] io scheduler mq-deadline registered
10558 00:57:27.147707 <6>[ 0.946771] io scheduler kyber registered
10559 00:57:27.166575 <6>[ 0.963682] EINJ: ACPI disabled.
10560 00:57:27.199197 <4>[ 0.989834] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10561 00:57:27.209216 <4>[ 1.000431] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10562 00:57:27.224172 <6>[ 1.021357] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10563 00:57:27.232340 <6>[ 1.029332] printk: console [ttyS0] disabled
10564 00:57:27.260391 <6>[ 1.053956] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10565 00:57:27.266669 <6>[ 1.063430] printk: console [ttyS0] enabled
10566 00:57:27.269841 <6>[ 1.063430] printk: console [ttyS0] enabled
10567 00:57:27.276573 <6>[ 1.072324] printk: bootconsole [mtk8250] disabled
10568 00:57:27.279646 <6>[ 1.072324] printk: bootconsole [mtk8250] disabled
10569 00:57:27.286821 <6>[ 1.083318] SuperH (H)SCI(F) driver initialized
10570 00:57:27.289676 <6>[ 1.088577] msm_serial: driver initialized
10571 00:57:27.303472 <6>[ 1.097465] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10572 00:57:27.313665 <6>[ 1.106008] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10573 00:57:27.320323 <6>[ 1.114550] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10574 00:57:27.330126 <6>[ 1.123177] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10575 00:57:27.339798 <6>[ 1.131884] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10576 00:57:27.347219 <6>[ 1.140603] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10577 00:57:27.357047 <6>[ 1.149143] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10578 00:57:27.363159 <6>[ 1.157938] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10579 00:57:27.373218 <6>[ 1.166481] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10580 00:57:27.384735 <6>[ 1.181868] loop: module loaded
10581 00:57:27.390982 <6>[ 1.187892] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10582 00:57:27.413630 <4>[ 1.211192] mtk-pmic-keys: Failed to locate of_node [id: -1]
10583 00:57:27.420465 <6>[ 1.217964] megasas: 07.719.03.00-rc1
10584 00:57:27.430678 <6>[ 1.227683] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10585 00:57:27.437223 <6>[ 1.233874] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10586 00:57:27.453678 <6>[ 1.250452] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10587 00:57:27.509458 <6>[ 1.299664] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10588 00:57:28.725187 <6>[ 2.521987] Freeing initrd memory: 40240K
10589 00:57:28.737074 <6>[ 2.533759] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10590 00:57:28.747520 <6>[ 2.544752] tun: Universal TUN/TAP device driver, 1.6
10591 00:57:28.750836 <6>[ 2.550828] thunder_xcv, ver 1.0
10592 00:57:28.753879 <6>[ 2.554323] thunder_bgx, ver 1.0
10593 00:57:28.757241 <6>[ 2.557824] nicpf, ver 1.0
10594 00:57:28.767806 <6>[ 2.561856] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10595 00:57:28.771021 <6>[ 2.569333] hns3: Copyright (c) 2017 Huawei Corporation.
10596 00:57:28.777770 <6>[ 2.574920] hclge is initializing
10597 00:57:28.780980 <6>[ 2.578503] e1000: Intel(R) PRO/1000 Network Driver
10598 00:57:28.788033 <6>[ 2.583633] e1000: Copyright (c) 1999-2006 Intel Corporation.
10599 00:57:28.790917 <6>[ 2.589649] e1000e: Intel(R) PRO/1000 Network Driver
10600 00:57:28.797396 <6>[ 2.594865] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10601 00:57:28.804005 <6>[ 2.601048] igb: Intel(R) Gigabit Ethernet Network Driver
10602 00:57:28.811123 <6>[ 2.606699] igb: Copyright (c) 2007-2014 Intel Corporation.
10603 00:57:28.817711 <6>[ 2.612535] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10604 00:57:28.824563 <6>[ 2.619052] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10605 00:57:28.827786 <6>[ 2.625513] sky2: driver version 1.30
10606 00:57:28.833749 <6>[ 2.630436] usbcore: registered new device driver r8152-cfgselector
10607 00:57:28.840342 <6>[ 2.636971] usbcore: registered new interface driver r8152
10608 00:57:28.846660 <6>[ 2.642782] VFIO - User Level meta-driver version: 0.3
10609 00:57:28.853616 <6>[ 2.651020] usbcore: registered new interface driver usb-storage
10610 00:57:28.860268 <6>[ 2.657466] usbcore: registered new device driver onboard-usb-hub
10611 00:57:28.869391 <6>[ 2.666599] mt6397-rtc mt6359-rtc: registered as rtc0
10612 00:57:28.879530 <6>[ 2.672064] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:57:28 UTC (1718499448)
10613 00:57:28.882658 <6>[ 2.681622] i2c_dev: i2c /dev entries driver
10614 00:57:28.896173 <4>[ 2.693498] cpu cpu0: supply cpu not found, using dummy regulator
10615 00:57:28.902889 <4>[ 2.699923] cpu cpu1: supply cpu not found, using dummy regulator
10616 00:57:28.909730 <4>[ 2.706342] cpu cpu2: supply cpu not found, using dummy regulator
10617 00:57:28.916883 <4>[ 2.712742] cpu cpu3: supply cpu not found, using dummy regulator
10618 00:57:28.922518 <4>[ 2.719139] cpu cpu4: supply cpu not found, using dummy regulator
10619 00:57:28.929202 <4>[ 2.725536] cpu cpu5: supply cpu not found, using dummy regulator
10620 00:57:28.936027 <4>[ 2.731932] cpu cpu6: supply cpu not found, using dummy regulator
10621 00:57:28.942306 <4>[ 2.738344] cpu cpu7: supply cpu not found, using dummy regulator
10622 00:57:28.962723 <6>[ 2.759939] cpu cpu0: EM: created perf domain
10623 00:57:28.965623 <6>[ 2.764850] cpu cpu4: EM: created perf domain
10624 00:57:28.973648 <6>[ 2.770444] sdhci: Secure Digital Host Controller Interface driver
10625 00:57:28.980316 <6>[ 2.776872] sdhci: Copyright(c) Pierre Ossman
10626 00:57:28.986469 <6>[ 2.781827] Synopsys Designware Multimedia Card Interface Driver
10627 00:57:28.993242 <6>[ 2.788467] sdhci-pltfm: SDHCI platform and OF driver helper
10628 00:57:28.996540 <6>[ 2.788522] mmc0: CQHCI version 5.10
10629 00:57:29.002825 <6>[ 2.799076] ledtrig-cpu: registered to indicate activity on CPUs
10630 00:57:29.009296 <6>[ 2.806089] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10631 00:57:29.016501 <6>[ 2.813139] usbcore: registered new interface driver usbhid
10632 00:57:29.019490 <6>[ 2.818960] usbhid: USB HID core driver
10633 00:57:29.029342 <6>[ 2.823171] spi_master spi0: will run message pump with realtime priority
10634 00:57:29.071200 <6>[ 2.862053] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10635 00:57:29.089598 <6>[ 2.877126] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10636 00:57:29.092748 <6>[ 2.887696] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10637 00:57:29.100735 <6>[ 2.897820] cros-ec-spi spi0.0: Chrome EC device registered
10638 00:57:29.107179 <6>[ 2.903840] mmc0: Command Queue Engine enabled
10639 00:57:29.114083 <6>[ 2.908571] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10640 00:57:29.117100 <6>[ 2.916250] mmcblk0: mmc0:0001 DA4128 116 GiB
10641 00:57:29.127326 <6>[ 2.924688] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10642 00:57:29.134892 <6>[ 2.932204] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10643 00:57:29.144916 <6>[ 2.937257] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10644 00:57:29.148983 <6>[ 2.938097] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10645 00:57:29.154788 <6>[ 2.948027] NET: Registered PF_PACKET protocol family
10646 00:57:29.161388 <6>[ 2.952616] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10647 00:57:29.164628 <6>[ 2.957368] 9pnet: Installing 9P2000 support
10648 00:57:29.171445 <5>[ 2.968368] Key type dns_resolver registered
10649 00:57:29.174562 <6>[ 2.973345] registered taskstats version 1
10650 00:57:29.181210 <5>[ 2.977718] Loading compiled-in X.509 certificates
10651 00:57:29.209104 <4>[ 2.999409] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 00:57:29.218673 <4>[ 3.010120] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 00:57:29.232849 <6>[ 3.030265] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10654 00:57:29.240107 <6>[ 3.037145] xhci-mtk 11200000.usb: xHCI Host Controller
10655 00:57:29.246233 <6>[ 3.042678] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10656 00:57:29.256749 <6>[ 3.050561] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10657 00:57:29.263582 <6>[ 3.059997] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10658 00:57:29.269706 <6>[ 3.066209] xhci-mtk 11200000.usb: xHCI Host Controller
10659 00:57:29.276509 <6>[ 3.071712] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10660 00:57:29.282924 <6>[ 3.079366] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10661 00:57:29.290434 <6>[ 3.087174] hub 1-0:1.0: USB hub found
10662 00:57:29.293230 <6>[ 3.091209] hub 1-0:1.0: 1 port detected
10663 00:57:29.302993 <6>[ 3.095478] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10664 00:57:29.306616 <6>[ 3.104206] hub 2-0:1.0: USB hub found
10665 00:57:29.309726 <6>[ 3.108245] hub 2-0:1.0: 1 port detected
10666 00:57:29.318098 <6>[ 3.115280] mtk-msdc 11f70000.mmc: Got CD GPIO
10667 00:57:29.336261 <6>[ 3.130017] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10668 00:57:29.346207 <6>[ 3.138414] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10669 00:57:29.352738 <6>[ 3.146755] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10670 00:57:29.362271 <6>[ 3.155093] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10671 00:57:29.369000 <6>[ 3.163432] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10672 00:57:29.379050 <6>[ 3.171769] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10673 00:57:29.386579 <6>[ 3.180108] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10674 00:57:29.395457 <6>[ 3.188446] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10675 00:57:29.402564 <6>[ 3.196784] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10676 00:57:29.411541 <6>[ 3.205122] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10677 00:57:29.418450 <6>[ 3.213460] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10678 00:57:29.428563 <6>[ 3.221804] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10679 00:57:29.434870 <6>[ 3.230143] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10680 00:57:29.444686 <6>[ 3.238480] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10681 00:57:29.451188 <6>[ 3.246824] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10682 00:57:29.458076 <6>[ 3.255517] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10683 00:57:29.465415 <6>[ 3.262643] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10684 00:57:29.472639 <6>[ 3.269445] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10685 00:57:29.481965 <6>[ 3.276213] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10686 00:57:29.489133 <6>[ 3.283187] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10687 00:57:29.495713 <6>[ 3.290041] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10688 00:57:29.505236 <6>[ 3.299174] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10689 00:57:29.515244 <6>[ 3.308295] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10690 00:57:29.524739 <6>[ 3.317591] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10691 00:57:29.535008 <6>[ 3.327058] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10692 00:57:29.544891 <6>[ 3.336525] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10693 00:57:29.551630 <6>[ 3.345645] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10694 00:57:29.561714 <6>[ 3.355112] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10695 00:57:29.571424 <6>[ 3.364231] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10696 00:57:29.581432 <6>[ 3.373530] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10697 00:57:29.590915 <6>[ 3.383691] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10698 00:57:29.601620 <6>[ 3.395652] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10699 00:57:29.724397 <6>[ 3.518716] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10700 00:57:29.879168 <6>[ 3.676564] hub 1-1:1.0: USB hub found
10701 00:57:29.882489 <6>[ 3.681095] hub 1-1:1.0: 4 ports detected
10702 00:57:29.894130 <6>[ 3.691642] hub 1-1:1.0: USB hub found
10703 00:57:29.897903 <6>[ 3.696013] hub 1-1:1.0: 4 ports detected
10704 00:57:30.004824 <6>[ 3.798949] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10705 00:57:30.029743 <6>[ 3.827231] hub 2-1:1.0: USB hub found
10706 00:57:30.033137 <6>[ 3.831681] hub 2-1:1.0: 3 ports detected
10707 00:57:30.044000 <6>[ 3.841278] hub 2-1:1.0: USB hub found
10708 00:57:30.047552 <6>[ 3.845715] hub 2-1:1.0: 3 ports detected
10709 00:57:30.221112 <6>[ 4.014737] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10710 00:57:30.353155 <6>[ 4.150530] hub 1-1.4:1.0: USB hub found
10711 00:57:30.356755 <6>[ 4.155191] hub 1-1.4:1.0: 2 ports detected
10712 00:57:30.369945 <6>[ 4.166750] hub 1-1.4:1.0: USB hub found
10713 00:57:30.372204 <6>[ 4.171375] hub 1-1.4:1.0: 2 ports detected
10714 00:57:30.432727 <6>[ 4.226953] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10715 00:57:30.541087 <6>[ 4.335363] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10716 00:57:30.577605 <4>[ 4.371881] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10717 00:57:30.587433 <4>[ 4.380992] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10718 00:57:30.626762 <6>[ 4.424387] r8152 2-1.3:1.0 eth0: v1.12.13
10719 00:57:30.668161 <6>[ 4.462584] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10720 00:57:30.861216 <6>[ 4.654737] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10721 00:57:32.204014 <6>[ 6.001480] r8152 2-1.3:1.0 eth0: carrier on
10722 00:57:34.808598 <5>[ 6.022538] Sending DHCP requests .., OK
10723 00:57:34.815346 <6>[ 8.610888] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10724 00:57:34.818722 <6>[ 8.619184] IP-Config: Complete:
10725 00:57:34.832049 <6>[ 8.622677] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10726 00:57:34.838849 <6>[ 8.633384] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10727 00:57:34.845443 <6>[ 8.641999] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10728 00:57:34.852131 <6>[ 8.642008] nameserver0=192.168.201.1
10729 00:57:34.854885 <6>[ 8.654163] clk: Disabling unused clocks
10730 00:57:34.858902 <6>[ 8.659712] ALSA device list:
10731 00:57:34.865429 <6>[ 8.663006] No soundcards found.
10732 00:57:34.872750 <6>[ 8.670802] Freeing unused kernel memory: 8512K
10733 00:57:34.876015 <6>[ 8.675792] Run /init as init process
10734 00:57:34.908620 <6>[ 8.706721] NET: Registered PF_INET6 protocol family
10735 00:57:34.915577 <6>[ 8.713488] Segment Routing with IPv6
10736 00:57:34.918729 <6>[ 8.717474] In-situ OAM (IOAM) with IPv6
10737 00:57:34.962997 <30>[ 8.734238] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10738 00:57:34.969581 <30>[ 8.767521] systemd[1]: Detected architecture arm64.
10739 00:57:34.970011
10740 00:57:34.976587 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10741 00:57:34.977010
10742 00:57:34.989220 <30>[ 8.786756] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10743 00:57:35.104270 <30>[ 8.898936] systemd[1]: Queued start job for default target graphical.target.
10744 00:57:35.150180 <30>[ 8.944648] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10745 00:57:35.157000 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10746 00:57:35.176262 <30>[ 8.970995] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10747 00:57:35.185938 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10748 00:57:35.206058 <30>[ 9.000178] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10749 00:57:35.215212 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10750 00:57:35.233247 <30>[ 9.028109] systemd[1]: Created slice user.slice - User and Session Slice.
10751 00:57:35.240156 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10752 00:57:35.264479 <30>[ 9.055357] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10753 00:57:35.273771 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10754 00:57:35.291495 <30>[ 9.082854] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10755 00:57:35.297919 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10756 00:57:35.326449 <30>[ 9.111235] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10757 00:57:35.336643 <30>[ 9.131143] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10758 00:57:35.342940 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10759 00:57:35.360632 <30>[ 9.155084] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10760 00:57:35.370795 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10761 00:57:35.388751 <30>[ 9.183224] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10762 00:57:35.398601 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10763 00:57:35.413400 <30>[ 9.211267] systemd[1]: Reached target paths.target - Path Units.
10764 00:57:35.423114 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10765 00:57:35.440235 <30>[ 9.234782] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10766 00:57:35.446581 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10767 00:57:35.461186 <30>[ 9.258785] systemd[1]: Reached target slices.target - Slice Units.
10768 00:57:35.471215 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10769 00:57:35.484987 <30>[ 9.283215] systemd[1]: Reached target swap.target - Swaps.
10770 00:57:35.492156 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10771 00:57:35.512620 <30>[ 9.307215] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10772 00:57:35.521947 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10773 00:57:35.541002 <30>[ 9.335190] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10774 00:57:35.550595 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10775 00:57:35.569997 <30>[ 9.364639] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10776 00:57:35.580148 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10777 00:57:35.596365 <30>[ 9.391354] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10778 00:57:35.606270 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10779 00:57:35.624968 <30>[ 9.419319] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10780 00:57:35.631515 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10781 00:57:35.648757 <30>[ 9.443388] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10782 00:57:35.658497 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10783 00:57:35.677311 <30>[ 9.472126] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10784 00:57:35.687370 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10785 00:57:35.705331 <30>[ 9.499820] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10786 00:57:35.714970 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10787 00:57:35.756037 <30>[ 9.550873] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10788 00:57:35.762905 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10789 00:57:35.782146 <30>[ 9.576707] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10790 00:57:35.788665 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10791 00:57:35.810836 <30>[ 9.605424] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10792 00:57:35.817781 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10793 00:57:35.842872 <30>[ 9.631214] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10794 00:57:35.856897 <30>[ 9.651213] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10795 00:57:35.865917 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10796 00:57:35.924597 <30>[ 9.719387] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10797 00:57:35.931236 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10798 00:57:35.957518 <30>[ 9.751981] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10799 00:57:35.967001 Startin<6>[ 9.761387] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10800 00:57:35.973392 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10801 00:57:35.997550 <30>[ 9.792070] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10802 00:57:36.004290 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10803 00:57:36.044696 <30>[ 9.839518] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10804 00:57:36.054751 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10805 00:57:36.078315 <30>[ 9.872341] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10806 00:57:36.084079 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10807 00:57:36.113304 <30>[ 9.907742] systemd[1]: Starting systemd-journald.service - Journal Service...
10808 00:57:36.119440 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10809 00:57:36.138602 <30>[ 9.933461] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10810 00:57:36.145139 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10811 00:57:36.171936 <30>[ 9.963314] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10812 00:57:36.178417 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10813 00:57:36.198894 <30>[ 9.993548] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10814 00:57:36.208664 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10815 00:57:36.232645 <30>[ 10.027166] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10816 00:57:36.242092 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10817 00:57:36.270432 <30>[ 10.065451] systemd[1]: Started systemd-journald.service - Journal Service.
10818 00:57:36.277099 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10819 00:57:36.298254 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10820 00:57:36.317079 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10821 00:57:36.336737 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10822 00:57:36.357690 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10823 00:57:36.378903 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10824 00:57:36.399037 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10825 00:57:36.422611 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10826 00:57:36.442941 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10827 00:57:36.462935 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10828 00:57:36.482517 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10829 00:57:36.505756 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10830 00:57:36.530073 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10831 00:57:36.549135 See 'systemctl status systemd-remount-fs.service' for details.
10832 00:57:36.569202 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10833 00:57:36.594526 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10834 00:57:36.652515 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10835 00:57:36.673034 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10836 00:57:36.693798 <46>[ 10.488775] systemd-journald[195]: Received client request to flush runtime journal.
10837 00:57:36.701214 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10838 00:57:36.723344 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10839 00:57:36.743920 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10840 00:57:36.769739 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10841 00:57:36.793718 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10842 00:57:36.817887 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10843 00:57:36.837958 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10844 00:57:36.857131 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10845 00:57:36.916872 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10846 00:57:36.939786 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10847 00:57:36.956246 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10848 00:57:36.972127 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10849 00:57:36.990835 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10850 00:57:37.017580 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10851 00:57:37.042950 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10852 00:57:37.063796 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10853 00:57:37.107499 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10854 00:57:37.293953 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10855 00:57:37.326868 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10856 00:57:37.349737 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10857 00:57:37.391032 <6>[ 11.186008] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10858 00:57:37.397631 <6>[ 11.190050] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10859 00:57:37.407805 <6>[ 11.193809] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10860 00:57:37.414291 <3>[ 11.202751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 00:57:37.424173 <6>[ 11.209810] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10862 00:57:37.427731 <6>[ 11.210529] remoteproc remoteproc0: scp is available
10863 00:57:37.434007 <6>[ 11.210622] remoteproc remoteproc0: powering up scp
10864 00:57:37.440624 <6>[ 11.210627] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10865 00:57:37.447164 <6>[ 11.210654] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10866 00:57:37.457053 <6>[ 11.217240] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10867 00:57:37.463759 <3>[ 11.217881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 00:57:37.473654 <3>[ 11.217889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 00:57:37.480224 <3>[ 11.217970] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 00:57:37.487483 <6>[ 11.220797] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10871 00:57:37.494804 <5>[ 11.221433] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10872 00:57:37.504277 <6>[ 11.221458] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10873 00:57:37.511154 <6>[ 11.221465] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10874 00:57:37.521674 <4>[ 11.221658] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10875 00:57:37.527742 <6>[ 11.222295] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10876 00:57:37.537652 <6>[ 11.222299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10877 00:57:37.544118 <6>[ 11.240021] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10878 00:57:37.554157 <4>[ 11.244501] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10879 00:57:37.557568 <4>[ 11.244501] Fallback method does not support PEC.
10880 00:57:37.568072 <3>[ 11.245677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 00:57:37.575113 <5>[ 11.249263] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10882 00:57:37.581825 <5>[ 11.249496] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10883 00:57:37.592027 <4>[ 11.249597] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10884 00:57:37.595552 <6>[ 11.249605] cfg80211: failed to load regulatory.db
10885 00:57:37.602388 <6>[ 11.253595] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10886 00:57:37.612241 <3>[ 11.259510] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10887 00:57:37.619052 <6>[ 11.267459] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10888 00:57:37.628556 <3>[ 11.275488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10889 00:57:37.635361 <3>[ 11.275493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10890 00:57:37.645326 <3>[ 11.277080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10891 00:57:37.652189 <6>[ 11.286439] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10892 00:57:37.661459 <3>[ 11.293107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10893 00:57:37.671516 <3>[ 11.307702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 00:57:37.678062 <3>[ 11.315430] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 00:57:37.681377 <6>[ 11.320942] mc: Linux media interface: v0.10
10896 00:57:37.691348 <4>[ 11.333328] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10897 00:57:37.698264 <6>[ 11.335800] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10898 00:57:37.705761 <3>[ 11.340421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10899 00:57:37.711006 <6>[ 11.347754] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10900 00:57:37.718475 <6>[ 11.347759] pci_bus 0000:00: root bus resource [bus 00-ff]
10901 00:57:37.725286 <6>[ 11.347767] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10902 00:57:37.735753 <6>[ 11.347769] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10903 00:57:37.742678 <6>[ 11.347797] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10904 00:57:37.749403 <6>[ 11.347810] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10905 00:57:37.752960 <6>[ 11.347881] pci 0000:00:00.0: supports D1 D2
10906 00:57:37.759673 <6>[ 11.347882] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10907 00:57:37.770141 <6>[ 11.348366] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10908 00:57:37.776185 <6>[ 11.348819] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10909 00:57:37.783027 <6>[ 11.348950] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10910 00:57:37.789234 <6>[ 11.348976] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10911 00:57:37.799259 <6>[ 11.348994] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10912 00:57:37.806122 <6>[ 11.349009] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10913 00:57:37.809473 <6>[ 11.349123] pci 0000:01:00.0: supports D1 D2
10914 00:57:37.815916 <6>[ 11.349128] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10915 00:57:37.822964 <4>[ 11.350964] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10916 00:57:37.832283 <3>[ 11.362030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 00:57:37.839135 <3>[ 11.362037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 00:57:37.848869 <3>[ 11.362042] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 00:57:37.855954 <3>[ 11.362048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 00:57:37.866383 <3>[ 11.362050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 00:57:37.873237 <3>[ 11.362084] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10922 00:57:37.880094 <6>[ 11.362477] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10923 00:57:37.886887 <6>[ 11.362507] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10924 00:57:37.896754 <6>[ 11.362511] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10925 00:57:37.903184 <6>[ 11.362519] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10926 00:57:37.910098 <6>[ 11.362532] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10927 00:57:37.920397 <6>[ 11.362545] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10928 00:57:37.924157 <6>[ 11.362557] pci 0000:00:00.0: PCI bridge to [bus 01]
10929 00:57:37.934073 <6>[ 11.362563] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10930 00:57:37.940554 <6>[ 11.362721] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10931 00:57:37.944014 <6>[ 11.363249] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10932 00:57:37.950437 <6>[ 11.363652] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10933 00:57:37.961661 <6>[ 11.364536] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10934 00:57:37.967620 <6>[ 11.367108] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10935 00:57:37.974431 <6>[ 11.370337] remoteproc remoteproc0: remote processor scp is now up
10936 00:57:37.985129 <6>[ 11.398887] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10937 00:57:37.991548 <3>[ 11.464655] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 00:57:38.001977 <6>[ 11.473769] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10939 00:57:38.011803 <3>[ 11.474046] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10940 00:57:38.018631 <6>[ 11.477555] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10941 00:57:38.029509 <3>[ 11.533255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 00:57:38.036034 <3>[ 11.534015] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10943 00:57:38.045763 <3>[ 11.557826] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 00:57:38.052728 <6>[ 11.557865] videodev: Linux video capture interface: v2.00
10945 00:57:38.056056 <6>[ 11.631603] Bluetooth: Core ver 2.22
10946 00:57:38.062567 <3>[ 11.656224] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 00:57:38.069814 <6>[ 11.659757] NET: Registered PF_BLUETOOTH protocol family
10948 00:57:38.075703 <6>[ 11.661594] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10949 00:57:38.088844 <6>[ 11.663223] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10950 00:57:38.095751 <6>[ 11.663481] usbcore: registered new interface driver uvcvideo
10951 00:57:38.102014 <6>[ 11.684565] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10952 00:57:38.109047 <3>[ 11.689234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 00:57:38.115189 <6>[ 11.690815] Bluetooth: HCI device and connection manager initialized
10954 00:57:38.121718 <6>[ 11.690833] Bluetooth: HCI socket layer initialized
10955 00:57:38.129016 <6>[ 11.690838] Bluetooth: L2CAP socket layer initialized
10956 00:57:38.131824 <6>[ 11.690853] Bluetooth: SCO socket layer initialized
10957 00:57:38.138187 <6>[ 11.711112] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10958 00:57:38.148229 <3>[ 11.711217] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 00:57:38.158056 <3>[ 11.731897] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 00:57:38.165197 <6>[ 11.736154] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10961 00:57:38.167881 <6>[ 11.755151] usbcore: registered new interface driver btusb
10962 00:57:38.177861 <4>[ 11.756096] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10963 00:57:38.185056 <3>[ 11.756102] Bluetooth: hci0: Failed to load firmware file (-2)
10964 00:57:38.190837 <3>[ 11.756104] Bluetooth: hci0: Failed to set up firmware (-2)
10965 00:57:38.200928 <4>[ 11.756107] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10966 00:57:38.207043 <6>[ 11.782613] mt7921e 0000:01:00.0: ASIC revision: 79610010
10967 00:57:38.217209 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10968 00:57:38.272784 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10969 00:57:38.292588 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10970 00:57:38.312010 <6>[ 12.106845] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10971 00:57:38.315099 <6>[ 12.106845]
10972 00:57:38.321412 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10973 00:57:38.341151 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10974 00:57:38.361228 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10975 00:57:38.409182 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10976 00:57:38.422536 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10977 00:57:38.441149 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10978 00:57:38.456719 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10979 00:57:38.471797 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10980 00:57:38.488056 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10981 00:57:38.505855 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10982 00:57:38.522527 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10983 00:57:38.540697 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10984 00:57:38.555969 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10985 00:57:38.575868 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10986 00:57:38.582072 <6>[ 12.376782] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10987 00:57:38.613564 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10988 00:57:38.638531 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10989 00:57:38.661078 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10990 00:57:38.680617 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10991 00:57:38.696539 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10992 00:57:38.739916 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10993 00:57:38.790520 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10994 00:57:38.809041 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10995 00:57:38.863307 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10996 00:57:38.882159 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10997 00:57:38.901098 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10998 00:57:38.921374 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10999 00:57:38.939142 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11000 00:57:39.001072 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11001 00:57:39.037446 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11002 00:57:39.081634
11003 00:57:39.084412 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11004 00:57:39.084838
11005 00:57:39.087374 debian-bookworm-arm64 login: root (automatic login)
11006 00:57:39.087887
11007 00:57:39.100968 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
11008 00:57:39.101497
11009 00:57:39.107941 The programs included with the Debian GNU/Linux system are free software;
11010 00:57:39.114686 the exact distribution terms for each program are described in the
11011 00:57:39.117559 individual files in /usr/share/doc/*/copyright.
11012 00:57:39.117972
11013 00:57:39.124617 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11014 00:57:39.128416 permitted by applicable law.
11015 00:57:39.130003 Matched prompt #10: / #
11017 00:57:39.131050 Setting prompt string to ['/ #']
11018 00:57:39.131483 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11020 00:57:39.132448 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11021 00:57:39.132878 start: 2.2.6 expect-shell-connection (timeout 00:03:02) [common]
11022 00:57:39.133325 Setting prompt string to ['/ #']
11023 00:57:39.133646 Forcing a shell prompt, looking for ['/ #']
11025 00:57:39.184395 / #
11026 00:57:39.184974 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11027 00:57:39.185378 Waiting using forced prompt support (timeout 00:02:30)
11028 00:57:39.190356
11029 00:57:39.191109 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11030 00:57:39.191581 start: 2.2.7 export-device-env (timeout 00:03:02) [common]
11031 00:57:39.192021 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11032 00:57:39.192586 end: 2.2 depthcharge-retry (duration 00:01:58) [common]
11033 00:57:39.193023 end: 2 depthcharge-action (duration 00:01:58) [common]
11034 00:57:39.193520 start: 3 lava-test-retry (timeout 00:07:39) [common]
11035 00:57:39.193957 start: 3.1 lava-test-shell (timeout 00:07:39) [common]
11036 00:57:39.194378 Using namespace: common
11038 00:57:39.295552 / # #
11039 00:57:39.296188 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11040 00:57:39.301580 #
11041 00:57:39.302294 Using /lava-14368601
11043 00:57:39.403426 / # export SHELL=/bin/sh
11044 00:57:39.409748 export SHELL=/bin/sh
11046 00:57:39.511267 / # . /lava-14368601/environment
11047 00:57:39.512027 <6>[ 13.242703] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11048 00:57:39.517909 . /lava-14368601/environment
11050 00:57:39.619829 / # /lava-14368601/bin/lava-test-runner /lava-14368601/0
11051 00:57:39.620473 Test shell timeout: 10s (minimum of the action and connection timeout)
11052 00:57:39.627037 /lava-14368601/bin/lava-test-runner /lava-14368601/0
11053 00:57:39.650256 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11054 00:57:39.656823 + cd /lava-14368601/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11055 00:57:39.657405 + cat uuid
11056 00:57:39.659845 + UUID=14368601_1.5.2.3.1
11057 00:57:39.660262 + set +x
11058 00:57:39.666876 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14368601_1.5.2.3.1>
11059 00:57:39.667720 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14368601_1.5.2.3.1
11060 00:57:39.668105 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14368601_1.5.2.3.1)
11061 00:57:39.668495 Skipping test definition patterns.
11062 00:57:39.670254 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11063 00:57:39.676731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11064 00:57:39.677359 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11066 00:57:39.686781 device: /dev/vide<4>[ 13.479636] use of bytesused == 0 is deprecated and will be removed in the future,
11067 00:57:39.687329 o2
11068 00:57:39.690021 <4>[ 13.488647] use the actual size instead.
11069 00:57:39.703922 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11070 00:57:39.714403 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11071 00:57:39.720574
11072 00:57:39.733289 Compliance test for mtk-vcodec-enc device /dev/video2:
11073 00:57:39.740009
11074 00:57:39.751210 Driver Info:
11075 00:57:39.761449 Driver name : mtk-vcodec-enc
11076 00:57:39.774352 Card type : MT8192 video encoder
11077 00:57:39.784690 Bus info : platform:17020000.vcodec
11078 00:57:39.792451 Driver version : 6.1.92
11079 00:57:39.804955 Capabilities : 0x84204000
11080 00:57:39.813463 Video Memory-to-Memory Multiplanar
11081 00:57:39.822857 Streaming
11082 00:57:39.833361 Extended Pix Format
11083 00:57:39.845241 Device Capabilities
11084 00:57:39.861750 Device Caps : 0x04204000
11085 00:57:39.873401 Video Memory-to-Memory Multiplanar
11086 00:57:39.885362 Streaming
11087 00:57:39.899309 Extended Pix Format
11088 00:57:39.912298 Detected Stateful Encoder
11089 00:57:39.923293
11090 00:57:39.938672 Required ioctls:
11091 00:57:39.954264 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11092 00:57:39.955012 test VIDIOC_QUERYCAP: OK
11093 00:57:39.955696 Received signal: <TESTSET> START Required-ioctls
11094 00:57:39.956260 Starting test_set Required-ioctls
11095 00:57:39.978833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11096 00:57:39.979581 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11098 00:57:39.981970 test invalid ioctls: OK
11099 00:57:40.002660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11100 00:57:40.003090
11101 00:57:40.003684 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11103 00:57:40.012562 Allow for multiple opens:
11104 00:57:40.020384 <LAVA_SIGNAL_TESTSET STOP>
11105 00:57:40.021162 Received signal: <TESTSET> STOP
11106 00:57:40.021586 Closing test_set Required-ioctls
11107 00:57:40.030056 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11108 00:57:40.030752 Received signal: <TESTSET> START Allow-for-multiple-opens
11109 00:57:40.031120 Starting test_set Allow-for-multiple-opens
11110 00:57:40.032498 test second /dev/video2 open: OK
11111 00:57:40.053837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11112 00:57:40.054518 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11114 00:57:40.057097 test VIDIOC_QUERYCAP: OK
11115 00:57:40.083907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11116 00:57:40.084689 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11118 00:57:40.086732 test VIDIOC_G/S_PRIORITY: OK
11119 00:57:40.107789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11120 00:57:40.108473 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11122 00:57:40.110936 test for unlimited opens: OK
11123 00:57:40.137379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11124 00:57:40.137813
11125 00:57:40.138399 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11127 00:57:40.147430 Debug ioctls:
11128 00:57:40.154851 <LAVA_SIGNAL_TESTSET STOP>
11129 00:57:40.155545 Received signal: <TESTSET> STOP
11130 00:57:40.155916 Closing test_set Allow-for-multiple-opens
11131 00:57:40.164614 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11132 00:57:40.165315 Received signal: <TESTSET> START Debug-ioctls
11133 00:57:40.165670 Starting test_set Debug-ioctls
11134 00:57:40.168247 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11135 00:57:40.188190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11136 00:57:40.189081 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11138 00:57:40.194430 test VIDIOC_LOG_STATUS: OK (Not Supported)
11139 00:57:40.211764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11140 00:57:40.212196
11141 00:57:40.212778 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11143 00:57:40.221450 Input ioctls:
11144 00:57:40.229021 <LAVA_SIGNAL_TESTSET STOP>
11145 00:57:40.229425 Received signal: <TESTSET> STOP
11146 00:57:40.229579 Closing test_set Debug-ioctls
11147 00:57:40.238277 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11148 00:57:40.238626 Received signal: <TESTSET> START Input-ioctls
11149 00:57:40.238756 Starting test_set Input-ioctls
11150 00:57:40.241738 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11151 00:57:40.266376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11152 00:57:40.266685 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11154 00:57:40.270170 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11155 00:57:40.287918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11156 00:57:40.288205 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11158 00:57:40.294717 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11159 00:57:40.313378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11160 00:57:40.313690 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11162 00:57:40.319928 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11163 00:57:40.339182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11164 00:57:40.339465 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11166 00:57:40.342495 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11167 00:57:40.365179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11168 00:57:40.365520 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11170 00:57:40.369196 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11171 00:57:40.389200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11172 00:57:40.389548 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11174 00:57:40.392457 Inputs: 0 Audio Inputs: 0 Tuners: 0
11175 00:57:40.400278
11176 00:57:40.420781 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11177 00:57:40.441774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11178 00:57:40.442091 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11180 00:57:40.447954 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11181 00:57:40.471307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11182 00:57:40.471614 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11184 00:57:40.476549 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11185 00:57:40.495156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11186 00:57:40.495437 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11188 00:57:40.502693 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11189 00:57:40.523924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11190 00:57:40.524202 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11192 00:57:40.532261 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11193 00:57:40.554053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11194 00:57:40.554157
11195 00:57:40.554396 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11197 00:57:40.573481 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11198 00:57:40.595584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11199 00:57:40.595876 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11201 00:57:40.602383 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11202 00:57:40.626113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11203 00:57:40.626401 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11205 00:57:40.629550 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11206 00:57:40.648551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11207 00:57:40.648828 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11209 00:57:40.651541 test VIDIOC_G/S_EDID: OK (Not Supported)
11210 00:57:40.672736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11211 00:57:40.672843
11212 00:57:40.673082 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11214 00:57:40.682659 Control ioctls:
11215 00:57:40.690028 <LAVA_SIGNAL_TESTSET STOP>
11216 00:57:40.690293 Received signal: <TESTSET> STOP
11217 00:57:40.690366 Closing test_set Input-ioctls
11218 00:57:40.699222 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11219 00:57:40.699479 Received signal: <TESTSET> START Control-ioctls
11220 00:57:40.699550 Starting test_set Control-ioctls
11221 00:57:40.702388 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11222 00:57:40.726277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11223 00:57:40.726408 test VIDIOC_QUERYCTRL: OK
11224 00:57:40.726650 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11226 00:57:40.748545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11227 00:57:40.748837 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11229 00:57:40.751275 test VIDIOC_G/S_CTRL: OK
11230 00:57:40.777753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11231 00:57:40.778090 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11233 00:57:40.781136 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11234 00:57:40.802415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11235 00:57:40.802714 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11237 00:57:40.808875 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11238 00:57:40.817919 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11239 00:57:40.843379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11240 00:57:40.843695 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11242 00:57:40.846089 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11243 00:57:40.867953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11244 00:57:40.868226 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11246 00:57:40.870968 Standard Controls: 16 Private Controls: 0
11247 00:57:40.879153
11248 00:57:40.892764 Format ioctls:
11249 00:57:40.899333 <LAVA_SIGNAL_TESTSET STOP>
11250 00:57:40.900324 Received signal: <TESTSET> STOP
11251 00:57:40.900710 Closing test_set Control-ioctls
11252 00:57:40.908757 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11253 00:57:40.909625 Received signal: <TESTSET> START Format-ioctls
11254 00:57:40.910145 Starting test_set Format-ioctls
11255 00:57:40.911905 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11256 00:57:40.937566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11257 00:57:40.938348 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11259 00:57:40.940635 test VIDIOC_G/S_PARM: OK
11260 00:57:40.963196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11261 00:57:40.964019 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11263 00:57:40.966743 test VIDIOC_G_FBUF: OK (Not Supported)
11264 00:57:40.988326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11265 00:57:40.989495 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11267 00:57:40.991692 test VIDIOC_G_FMT: OK
11268 00:57:41.013218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11269 00:57:41.014038 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11271 00:57:41.016184 test VIDIOC_TRY_FMT: OK
11272 00:57:41.037420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11273 00:57:41.037835 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11275 00:57:41.044542 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11276 00:57:41.052455 test VIDIOC_S_FMT: FAIL
11277 00:57:41.081055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11278 00:57:41.081402 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11280 00:57:41.084657 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11281 00:57:41.105496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11282 00:57:41.105879 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11284 00:57:41.109150 test Cropping: OK
11285 00:57:41.130072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11286 00:57:41.130584 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11288 00:57:41.132017 test Composing: OK (Not Supported)
11289 00:57:41.154207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11290 00:57:41.155020 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11292 00:57:41.157231 test Scaling: OK (Not Supported)
11293 00:57:41.179732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11294 00:57:41.180235
11295 00:57:41.180823 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11297 00:57:41.188184 Codec ioctls:
11298 00:57:41.195942 <LAVA_SIGNAL_TESTSET STOP>
11299 00:57:41.196620 Received signal: <TESTSET> STOP
11300 00:57:41.196967 Closing test_set Format-ioctls
11301 00:57:41.205388 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11302 00:57:41.206217 Received signal: <TESTSET> START Codec-ioctls
11303 00:57:41.206609 Starting test_set Codec-ioctls
11304 00:57:41.208867 test VIDIOC_(TRY_)ENCODER_CMD: OK
11305 00:57:41.230995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11306 00:57:41.231810 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11308 00:57:41.237876 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11309 00:57:41.256261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11310 00:57:41.257188 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11312 00:57:41.263129 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11313 00:57:41.280374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11314 00:57:41.280865
11315 00:57:41.281460 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11317 00:57:41.289482 Buffer ioctls:
11318 00:57:41.297714 <LAVA_SIGNAL_TESTSET STOP>
11319 00:57:41.298400 Received signal: <TESTSET> STOP
11320 00:57:41.298748 Closing test_set Codec-ioctls
11321 00:57:41.309375 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11322 00:57:41.310190 Received signal: <TESTSET> START Buffer-ioctls
11323 00:57:41.310651 Starting test_set Buffer-ioctls
11324 00:57:41.312174 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11325 00:57:41.336798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11326 00:57:41.337529 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11328 00:57:41.340255 test CREATE_BUFS maximum buffers: OK
11329 00:57:41.358226 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11331 00:57:41.361213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11332 00:57:41.361678 test VIDIOC_EXPBUF: OK
11333 00:57:41.381717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11334 00:57:41.382445 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11336 00:57:41.384468 test Requests: OK (Not Supported)
11337 00:57:41.405818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11338 00:57:41.406319
11339 00:57:41.406906 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11341 00:57:41.416122 Test input 0:
11342 00:57:41.430393
11343 00:57:41.440826 Streaming ioctls:
11344 00:57:41.448430 <LAVA_SIGNAL_TESTSET STOP>
11345 00:57:41.449254 Received signal: <TESTSET> STOP
11346 00:57:41.449678 Closing test_set Buffer-ioctls
11347 00:57:41.458800 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11348 00:57:41.459620 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11349 00:57:41.460017 Starting test_set Streaming-ioctls_Test-input-0
11350 00:57:41.461651 test read/write: OK (Not Supported)
11351 00:57:41.484225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11352 00:57:41.485068 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11354 00:57:41.490784 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11355 00:57:41.498472 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11356 00:57:41.511006 test blocking wait: FAIL
11357 00:57:41.536505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11358 00:57:41.537403 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11360 00:57:41.542545 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11361 00:57:41.548122 test MMAP (select): FAIL
11362 00:57:41.573702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11363 00:57:41.574540 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11365 00:57:41.580065 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11366 00:57:41.590664 test MMAP (epoll): FAIL
11367 00:57:41.615011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11368 00:57:41.615855 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11370 00:57:41.621742 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11371 00:57:41.628876 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11372 00:57:41.637750 test USERPTR (select): FAIL
11373 00:57:41.664416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11374 00:57:41.665191 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11376 00:57:41.671110 test DMABUF: Cannot test, specify --expbuf-device
11377 00:57:41.674264
11378 00:57:41.691296 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11379 00:57:41.698373 <LAVA_TEST_RUNNER EXIT>
11380 00:57:41.699154 ok: lava_test_shell seems to have completed
11381 00:57:41.699555 Marking unfinished test run as failed
11383 00:57:41.704103 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11384 00:57:41.704698 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11385 00:57:41.705133 end: 3 lava-test-retry (duration 00:00:03) [common]
11386 00:57:41.705630 start: 4 finalize (timeout 00:07:37) [common]
11387 00:57:41.706088 start: 4.1 power-off (timeout 00:00:30) [common]
11388 00:57:41.707030 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11389 00:57:41.960037 >> Command sent successfully.
11390 00:57:41.970407 Returned 0 in 0 seconds
11391 00:57:42.071740 end: 4.1 power-off (duration 00:00:00) [common]
11393 00:57:42.073318 start: 4.2 read-feedback (timeout 00:07:37) [common]
11394 00:57:42.074825 Listened to connection for namespace 'common' for up to 1s
11395 00:57:43.075322 Finalising connection for namespace 'common'
11396 00:57:43.075993 Disconnecting from shell: Finalise
11397 00:57:43.076396 / #
11398 00:57:43.177540 end: 4.2 read-feedback (duration 00:00:01) [common]
11399 00:57:43.178241 end: 4 finalize (duration 00:00:01) [common]
11400 00:57:43.178819 Cleaning after the job
11401 00:57:43.179352 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/ramdisk
11402 00:57:43.199194 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/kernel
11403 00:57:43.227979 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/dtb
11404 00:57:43.228270 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368601/tftp-deploy-kt0gpwp2/modules
11405 00:57:43.235670 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368601
11406 00:57:43.297623 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368601
11407 00:57:43.297797 Job finished correctly