Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 1
- Kernel Errors: 41
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 89
1 01:01:07.124356 lava-dispatcher, installed at version: 2024.03
2 01:01:07.124567 start: 0 validate
3 01:01:07.124677 Start time: 2024-06-16 01:01:07.124671+00:00 (UTC)
4 01:01:07.124808 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:01:07.124951 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:01:07.379572 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:01:07.380391 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:01:07.637388 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:01:07.638375 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 01:01:07.892379 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:01:07.893002 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:01:08.154242 validate duration: 1.03
14 01:01:08.155506 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:01:08.156049 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:01:08.156518 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:01:08.157293 Not decompressing ramdisk as can be used compressed.
18 01:01:08.157803 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 01:01:08.158288 saving as /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/ramdisk/rootfs.cpio.gz
20 01:01:08.158735 total size: 28105535 (26 MB)
21 01:01:08.163840 progress 0 % (0 MB)
22 01:01:08.190628 progress 5 % (1 MB)
23 01:01:08.202718 progress 10 % (2 MB)
24 01:01:08.211871 progress 15 % (4 MB)
25 01:01:08.219598 progress 20 % (5 MB)
26 01:01:08.226798 progress 25 % (6 MB)
27 01:01:08.233836 progress 30 % (8 MB)
28 01:01:08.240929 progress 35 % (9 MB)
29 01:01:08.247994 progress 40 % (10 MB)
30 01:01:08.254955 progress 45 % (12 MB)
31 01:01:08.262000 progress 50 % (13 MB)
32 01:01:08.268980 progress 55 % (14 MB)
33 01:01:08.276040 progress 60 % (16 MB)
34 01:01:08.283109 progress 65 % (17 MB)
35 01:01:08.290153 progress 70 % (18 MB)
36 01:01:08.297267 progress 75 % (20 MB)
37 01:01:08.304337 progress 80 % (21 MB)
38 01:01:08.311438 progress 85 % (22 MB)
39 01:01:08.318414 progress 90 % (24 MB)
40 01:01:08.325489 progress 95 % (25 MB)
41 01:01:08.332518 progress 100 % (26 MB)
42 01:01:08.332727 26 MB downloaded in 0.17 s (154.05 MB/s)
43 01:01:08.332875 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:01:08.333091 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:01:08.333171 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:01:08.333247 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:01:08.333384 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:01:08.333450 saving as /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/kernel/Image
50 01:01:08.333519 total size: 54813184 (52 MB)
51 01:01:08.333574 No compression specified
52 01:01:08.334593 progress 0 % (0 MB)
53 01:01:08.348425 progress 5 % (2 MB)
54 01:01:08.362596 progress 10 % (5 MB)
55 01:01:08.376047 progress 15 % (7 MB)
56 01:01:08.389822 progress 20 % (10 MB)
57 01:01:08.403773 progress 25 % (13 MB)
58 01:01:08.417354 progress 30 % (15 MB)
59 01:01:08.431318 progress 35 % (18 MB)
60 01:01:08.445089 progress 40 % (20 MB)
61 01:01:08.458858 progress 45 % (23 MB)
62 01:01:08.472726 progress 50 % (26 MB)
63 01:01:08.486723 progress 55 % (28 MB)
64 01:01:08.500467 progress 60 % (31 MB)
65 01:01:08.514350 progress 65 % (34 MB)
66 01:01:08.527919 progress 70 % (36 MB)
67 01:01:08.541679 progress 75 % (39 MB)
68 01:01:08.555438 progress 80 % (41 MB)
69 01:01:08.568951 progress 85 % (44 MB)
70 01:01:08.582781 progress 90 % (47 MB)
71 01:01:08.596492 progress 95 % (49 MB)
72 01:01:08.609944 progress 100 % (52 MB)
73 01:01:08.610160 52 MB downloaded in 0.28 s (188.96 MB/s)
74 01:01:08.610378 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:01:08.610582 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:01:08.610664 start: 1.3 download-retry (timeout 00:10:00) [common]
78 01:01:08.610740 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 01:01:08.610863 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
80 01:01:08.610924 saving as /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
81 01:01:08.610978 total size: 57695 (0 MB)
82 01:01:08.611030 No compression specified
83 01:01:08.612078 progress 56 % (0 MB)
84 01:01:08.612336 progress 100 % (0 MB)
85 01:01:08.612527 0 MB downloaded in 0.00 s (35.56 MB/s)
86 01:01:08.612639 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:01:08.612839 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:01:08.612915 start: 1.4 download-retry (timeout 00:10:00) [common]
90 01:01:08.612989 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 01:01:08.613088 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:01:08.613149 saving as /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/modules/modules.tar
93 01:01:08.613201 total size: 8617404 (8 MB)
94 01:01:08.613318 Using unxz to decompress xz
95 01:01:08.614711 progress 0 % (0 MB)
96 01:01:08.633507 progress 5 % (0 MB)
97 01:01:08.659689 progress 10 % (0 MB)
98 01:01:08.686630 progress 15 % (1 MB)
99 01:01:08.710354 progress 20 % (1 MB)
100 01:01:08.733774 progress 25 % (2 MB)
101 01:01:08.757252 progress 30 % (2 MB)
102 01:01:08.782963 progress 35 % (2 MB)
103 01:01:08.807180 progress 40 % (3 MB)
104 01:01:08.829473 progress 45 % (3 MB)
105 01:01:08.853744 progress 50 % (4 MB)
106 01:01:08.878314 progress 55 % (4 MB)
107 01:01:08.903024 progress 60 % (4 MB)
108 01:01:08.926593 progress 65 % (5 MB)
109 01:01:08.952233 progress 70 % (5 MB)
110 01:01:08.975422 progress 75 % (6 MB)
111 01:01:09.000843 progress 80 % (6 MB)
112 01:01:09.025434 progress 85 % (7 MB)
113 01:01:09.049928 progress 90 % (7 MB)
114 01:01:09.074380 progress 95 % (7 MB)
115 01:01:09.098770 progress 100 % (8 MB)
116 01:01:09.104454 8 MB downloaded in 0.49 s (16.73 MB/s)
117 01:01:09.104603 end: 1.4.1 http-download (duration 00:00:00) [common]
119 01:01:09.104811 end: 1.4 download-retry (duration 00:00:00) [common]
120 01:01:09.104888 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:01:09.104964 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:01:09.105041 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:01:09.105121 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:01:09.105280 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1
125 01:01:09.105396 makedir: /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin
126 01:01:09.105485 makedir: /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/tests
127 01:01:09.105572 makedir: /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/results
128 01:01:09.105659 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-add-keys
129 01:01:09.105792 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-add-sources
130 01:01:09.105912 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-background-process-start
131 01:01:09.106035 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-background-process-stop
132 01:01:09.106157 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-common-functions
133 01:01:09.106316 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-echo-ipv4
134 01:01:09.106427 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-install-packages
135 01:01:09.106536 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-installed-packages
136 01:01:09.106644 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-os-build
137 01:01:09.106752 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-probe-channel
138 01:01:09.106860 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-probe-ip
139 01:01:09.106968 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-target-ip
140 01:01:09.107076 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-target-mac
141 01:01:09.107183 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-target-storage
142 01:01:09.107295 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-test-case
143 01:01:09.107403 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-test-event
144 01:01:09.107540 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-test-feedback
145 01:01:09.107663 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-test-raise
146 01:01:09.107771 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-test-reference
147 01:01:09.107880 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-test-runner
148 01:01:09.108009 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-test-set
149 01:01:09.108137 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-test-shell
150 01:01:09.108248 Updating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-install-packages (oe)
151 01:01:09.108380 Updating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/bin/lava-installed-packages (oe)
152 01:01:09.108486 Creating /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/environment
153 01:01:09.108569 LAVA metadata
154 01:01:09.108632 - LAVA_JOB_ID=14368623
155 01:01:09.108687 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:01:09.108774 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:01:09.108833 skipped lava-vland-overlay
158 01:01:09.108898 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:01:09.108967 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:01:09.109019 skipped lava-multinode-overlay
161 01:01:09.109091 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:01:09.109166 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:01:09.109227 Loading test definitions
164 01:01:09.109301 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:01:09.109359 Using /lava-14368623 at stage 0
166 01:01:09.109642 uuid=14368623_1.5.2.3.1 testdef=None
167 01:01:09.109722 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:01:09.109796 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:01:09.110269 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:01:09.110467 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:01:09.110996 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:01:09.111203 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:01:09.112306 runner path: /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/0/tests/0_v4l2-compliance-uvc test_uuid 14368623_1.5.2.3.1
176 01:01:09.112476 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:01:09.112683 Creating lava-test-runner.conf files
179 01:01:09.112739 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368623/lava-overlay-lxrffsh1/lava-14368623/0 for stage 0
180 01:01:09.112821 - 0_v4l2-compliance-uvc
181 01:01:09.112908 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:01:09.112983 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:01:09.119015 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:01:09.119124 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:01:09.119203 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:01:09.119278 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:01:09.119352 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:01:09.988263 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 01:01:09.988395 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 01:01:09.988475 extracting modules file /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368623/extract-overlay-ramdisk-axkeiinw/ramdisk
191 01:01:10.214372 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:01:10.214498 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 01:01:10.214577 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368623/compress-overlay-6i4bqyp4/overlay-1.5.2.4.tar.gz to ramdisk
194 01:01:10.214637 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368623/compress-overlay-6i4bqyp4/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368623/extract-overlay-ramdisk-axkeiinw/ramdisk
195 01:01:10.220792 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:01:10.220886 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 01:01:10.220968 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:01:10.221044 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 01:01:10.221110 Building ramdisk /var/lib/lava/dispatcher/tmp/14368623/extract-overlay-ramdisk-axkeiinw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368623/extract-overlay-ramdisk-axkeiinw/ramdisk
200 01:01:10.930923 >> 275951 blocks
201 01:01:15.169251 rename /var/lib/lava/dispatcher/tmp/14368623/extract-overlay-ramdisk-axkeiinw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/ramdisk/ramdisk.cpio.gz
202 01:01:15.169411 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 01:01:15.169498 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 01:01:15.169575 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 01:01:15.169650 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/kernel/Image']
206 01:01:28.558646 Returned 0 in 13 seconds
207 01:01:28.659168 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/kernel/image.itb
208 01:01:29.362928 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:01:29.363059 output: Created: Sun Jun 16 02:01:29 2024
210 01:01:29.363123 output: Image 0 (kernel-1)
211 01:01:29.363181 output: Description:
212 01:01:29.363239 output: Created: Sun Jun 16 02:01:29 2024
213 01:01:29.363298 output: Type: Kernel Image
214 01:01:29.363355 output: Compression: lzma compressed
215 01:01:29.363414 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
216 01:01:29.363471 output: Architecture: AArch64
217 01:01:29.363527 output: OS: Linux
218 01:01:29.363584 output: Load Address: 0x00000000
219 01:01:29.363640 output: Entry Point: 0x00000000
220 01:01:29.363694 output: Hash algo: crc32
221 01:01:29.363748 output: Hash value: f6f06660
222 01:01:29.363798 output: Image 1 (fdt-1)
223 01:01:29.363846 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
224 01:01:29.363894 output: Created: Sun Jun 16 02:01:29 2024
225 01:01:29.363942 output: Type: Flat Device Tree
226 01:01:29.363988 output: Compression: uncompressed
227 01:01:29.364037 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
228 01:01:29.364084 output: Architecture: AArch64
229 01:01:29.364132 output: Hash algo: crc32
230 01:01:29.364178 output: Hash value: a9713552
231 01:01:29.364224 output: Image 2 (ramdisk-1)
232 01:01:29.364270 output: Description: unavailable
233 01:01:29.364317 output: Created: Sun Jun 16 02:01:29 2024
234 01:01:29.364364 output: Type: RAMDisk Image
235 01:01:29.364410 output: Compression: uncompressed
236 01:01:29.364457 output: Data Size: 41224565 Bytes = 40258.36 KiB = 39.31 MiB
237 01:01:29.364504 output: Architecture: AArch64
238 01:01:29.364550 output: OS: Linux
239 01:01:29.364595 output: Load Address: unavailable
240 01:01:29.364641 output: Entry Point: unavailable
241 01:01:29.364688 output: Hash algo: crc32
242 01:01:29.364734 output: Hash value: d216f75e
243 01:01:29.364814 output: Default Configuration: 'conf-1'
244 01:01:29.364866 output: Configuration 0 (conf-1)
245 01:01:29.364944 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
246 01:01:29.364992 output: Kernel: kernel-1
247 01:01:29.365072 output: Init Ramdisk: ramdisk-1
248 01:01:29.365119 output: FDT: fdt-1
249 01:01:29.365166 output: Loadables: kernel-1
250 01:01:29.365213 output:
251 01:01:29.365347 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 01:01:29.365428 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 01:01:29.365512 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 01:01:29.365592 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 01:01:29.365660 No LXC device requested
256 01:01:29.365730 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:01:29.365805 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 01:01:29.365873 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:01:29.365931 Checking files for TFTP limit of 4294967296 bytes.
260 01:01:29.366418 end: 1 tftp-deploy (duration 00:00:21) [common]
261 01:01:29.366517 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:01:29.366597 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:01:29.366704 substitutions:
264 01:01:29.366762 - {DTB}: 14368623/tftp-deploy-v7j96_eo/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
265 01:01:29.366821 - {INITRD}: 14368623/tftp-deploy-v7j96_eo/ramdisk/ramdisk.cpio.gz
266 01:01:29.366874 - {KERNEL}: 14368623/tftp-deploy-v7j96_eo/kernel/Image
267 01:01:29.366925 - {LAVA_MAC}: None
268 01:01:29.366976 - {PRESEED_CONFIG}: None
269 01:01:29.367026 - {PRESEED_LOCAL}: None
270 01:01:29.367076 - {RAMDISK}: 14368623/tftp-deploy-v7j96_eo/ramdisk/ramdisk.cpio.gz
271 01:01:29.367130 - {ROOT_PART}: None
272 01:01:29.367179 - {ROOT}: None
273 01:01:29.367228 - {SERVER_IP}: 192.168.201.1
274 01:01:29.367275 - {TEE}: None
275 01:01:29.367323 Parsed boot commands:
276 01:01:29.367370 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:01:29.367515 Parsed boot commands: tftpboot 192.168.201.1 14368623/tftp-deploy-v7j96_eo/kernel/image.itb 14368623/tftp-deploy-v7j96_eo/kernel/cmdline
278 01:01:29.367596 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:01:29.367671 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:01:29.367750 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:01:29.367830 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:01:29.367888 Not connected, no need to disconnect.
283 01:01:29.367954 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:01:29.368026 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:01:29.368083 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-5'
286 01:01:29.371381 Setting prompt string to ['lava-test: # ']
287 01:01:29.371690 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:01:29.371787 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:01:29.371879 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:01:29.371960 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:01:29.372152 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-5']
292 01:01:51.444740 Returned 0 in 22 seconds
293 01:01:51.545628 end: 2.2.2.1 pdu-reboot (duration 00:00:22) [common]
295 01:01:51.546935 end: 2.2.2 reset-device (duration 00:00:22) [common]
296 01:01:51.547400 start: 2.2.3 depthcharge-start (timeout 00:04:38) [common]
297 01:01:51.547821 Setting prompt string to 'Starting depthcharge on Juniper...'
298 01:01:51.548147 Changing prompt to 'Starting depthcharge on Juniper...'
299 01:01:51.548480 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
300 01:01:51.550128 [Enter `^Ec?' for help]
301 01:01:51.550556 [DL] 00000000 00000000 010701
302 01:01:51.550876
303 01:01:51.551080
304 01:01:51.551140 F0: 102B 0000
305 01:01:51.551199
306 01:01:51.551258 F3: 1006 0033 [0200]
307 01:01:51.551320
308 01:01:51.551375 F3: 4001 00E0 [0200]
309 01:01:51.551432
310 01:01:51.551485 F3: 0000 0000
311 01:01:51.551536
312 01:01:51.551587 V0: 0000 0000 [0001]
313 01:01:51.551637
314 01:01:51.551685 00: 1027 0002
315 01:01:51.551736
316 01:01:51.551784 01: 0000 0000
317 01:01:51.551837
318 01:01:51.551886 BP: 0C00 0251 [0000]
319 01:01:51.551936
320 01:01:51.551983 G0: 1182 0000
321 01:01:51.552030
322 01:01:51.552077 EC: 0004 0000 [0001]
323 01:01:51.552125
324 01:01:51.552172 S7: 0000 0000 [0000]
325 01:01:51.552220
326 01:01:51.552267 CC: 0000 0000 [0001]
327 01:01:51.552314
328 01:01:51.552362 T0: 0000 00DB [000F]
329 01:01:51.552410
330 01:01:51.552457 Jump to BL
331 01:01:51.552504
332 01:01:51.552552
333 01:01:51.552598
334 01:01:51.552646 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
335 01:01:51.552697 ARM64: Exception handlers installed.
336 01:01:51.552745 ARM64: Testing exception
337 01:01:51.552794 ARM64: Done test exception
338 01:01:51.552842 WDT: Last reset was cold boot
339 01:01:51.552894 SPI0(PAD0) initialized at 992727 Hz
340 01:01:51.552945 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
341 01:01:51.552993 Manufacturer: ef
342 01:01:51.553041 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
343 01:01:51.553090 Probing TPM: . done!
344 01:01:51.553138 TPM ready after 0 ms
345 01:01:51.553186 Connected to device vid:did:rid of 1ae0:0028:00
346 01:01:51.553234 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b81dc66
347 01:01:51.553282 Initialized TPM device CR50 revision 0
348 01:01:51.553331 tlcl_send_startup: Startup return code is 0
349 01:01:51.553378 TPM: setup succeeded
350 01:01:51.553426 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
351 01:01:51.553475 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
352 01:01:51.553524 in-header: 03 19 00 00 08 00 00 00
353 01:01:51.553572 in-data: a2 e0 47 00 13 00 00 00
354 01:01:51.553620 Chrome EC: UHEPI supported
355 01:01:51.553667 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
356 01:01:51.553715 in-header: 03 a1 00 00 08 00 00 00
357 01:01:51.553763 in-data: 84 60 60 10 00 00 00 00
358 01:01:51.553810 Phase 1
359 01:01:51.553858 FMAP: area GBB found @ 3f5000 (12032 bytes)
360 01:01:51.553906 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
361 01:01:51.553955 VB2:vb2_check_recovery() Recovery was requested manually
362 01:01:51.554003 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
363 01:01:51.554052 Recovery requested (1009000e)
364 01:01:51.554099 tlcl_extend: response is 0
365 01:01:51.554147 tlcl_extend: response is 0
366 01:01:51.554195
367 01:01:51.554280
368 01:01:51.554328 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
369 01:01:51.554377 ARM64: Exception handlers installed.
370 01:01:51.554425 ARM64: Testing exception
371 01:01:51.554472 ARM64: Done test exception
372 01:01:51.554520 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xaa70, sec=0x2019
373 01:01:51.554568 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
374 01:01:51.554616 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
375 01:01:51.554663 [RTC]rtc_get_frequency_meter,134: input=0xf, output=778
376 01:01:51.554711 [RTC]rtc_get_frequency_meter,134: input=0x17, output=959
377 01:01:51.554758 [RTC]rtc_get_frequency_meter,134: input=0x13, output=868
378 01:01:51.554805 [RTC]rtc_get_frequency_meter,134: input=0x11, output=824
379 01:01:51.554854 [RTC]rtc_get_frequency_meter,134: input=0x10, output=801
380 01:01:51.554902 [RTC]rtc_get_frequency_meter,134: input=0xf, output=778
381 01:01:51.554949 [RTC]rtc_get_frequency_meter,134: input=0x10, output=801
382 01:01:51.554997 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xaa70
383 01:01:51.555045 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
384 01:01:51.555092 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
385 01:01:51.555140 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
386 01:01:51.555188 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 01:01:51.555236 in-header: 03 19 00 00 08 00 00 00
388 01:01:51.555284 in-data: a2 e0 47 00 13 00 00 00
389 01:01:51.555332 Chrome EC: UHEPI supported
390 01:01:51.555380 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
391 01:01:51.555428 in-header: 03 a1 00 00 08 00 00 00
392 01:01:51.555476 in-data: 84 60 60 10 00 00 00 00
393 01:01:51.555524 Skip loading cached calibration data
394 01:01:51.555572 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
395 01:01:51.555620 in-header: 03 a1 00 00 08 00 00 00
396 01:01:51.555668 in-data: 84 60 60 10 00 00 00 00
397 01:01:51.555715 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
398 01:01:51.555764 in-header: 03 a1 00 00 08 00 00 00
399 01:01:51.555811 in-data: 84 60 60 10 00 00 00 00
400 01:01:51.555859 ADC[3]: Raw value=1040656 ID=8
401 01:01:51.555906 Manufacturer: ef
402 01:01:51.555954 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
403 01:01:51.556002 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
404 01:01:51.556050 CBFS @ 21000 size 3d4000
405 01:01:51.556098 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
406 01:01:51.556145 CBFS: Locating 'sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB'
407 01:01:51.556193 CBFS: Found @ offset 3c880 size 4b
408 01:01:51.556240 DRAM-K: Full Calibration
409 01:01:51.556291 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
410 01:01:51.556342 CBFS @ 21000 size 3d4000
411 01:01:51.556389 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
412 01:01:51.556436 CBFS: Locating 'fallback/dram'
413 01:01:51.556484 CBFS: Found @ offset 24b00 size 12268
414 01:01:51.556532 read SPI 0x45b44 0x1224c: 22773 us, 3263 KB/s, 26.104 Mbps
415 01:01:51.556581 ddr_geometry: 1, config: 0x0
416 01:01:51.556628 header.status = 0x0
417 01:01:51.556676 header.magic = 0x44524d4b (expected: 0x44524d4b)
418 01:01:51.556724 header.version = 0x5 (expected: 0x5)
419 01:01:51.556964 header.size = 0x8f0 (expected: 0x8f0)
420 01:01:51.557034 header.config = 0x0
421 01:01:51.557085 header.flags = 0x0
422 01:01:51.557133 header.checksum = 0x0
423 01:01:51.557182 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
424 01:01:51.557231 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
425 01:01:51.557279 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
426 01:01:51.557328 ddr_geometry:1
427 01:01:51.557376 [EMI] new MDL number = 1
428 01:01:51.557423 dram_cbt_mode_extern: 0
429 01:01:51.557471 dram_cbt_mode [RK0]: 0, [RK1]: 0
430 01:01:51.557519 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
431 01:01:51.557567
432 01:01:51.557614
433 01:01:51.557661 [Bianco] ETT version 0.0.0.1
434 01:01:51.557709 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
435 01:01:51.557757
436 01:01:51.557804 vSetVcoreByFreq with vcore:762500, freq=1600
437 01:01:51.557851
438 01:01:51.557898 [DramcInit]
439 01:01:51.557946 AutoRefreshCKEOff AutoREF OFF
440 01:01:51.557994 DDRPhyPLLSetting-CKEOFF
441 01:01:51.558042 DDRPhyPLLSetting-CKEON
442 01:01:51.558089
443 01:01:51.558137 Enable WDQS
444 01:01:51.558184 [ModeRegInit_LP4] CH0 RK0
445 01:01:51.558261 Write Rank0 MR13 =0x18
446 01:01:51.558322 Write Rank0 MR12 =0x5d
447 01:01:51.558369 Write Rank0 MR1 =0x56
448 01:01:51.558416 Write Rank0 MR2 =0x1a
449 01:01:51.558464 Write Rank0 MR11 =0x0
450 01:01:51.558512 Write Rank0 MR22 =0x38
451 01:01:51.558560 Write Rank0 MR14 =0x5d
452 01:01:51.558607 Write Rank0 MR3 =0x30
453 01:01:51.558655 Write Rank0 MR13 =0x58
454 01:01:51.558702 Write Rank0 MR12 =0x5d
455 01:01:51.558749 Write Rank0 MR1 =0x56
456 01:01:51.558797 Write Rank0 MR2 =0x2d
457 01:01:51.558844 Write Rank0 MR11 =0x23
458 01:01:51.558891 Write Rank0 MR22 =0x34
459 01:01:51.558938 Write Rank0 MR14 =0x10
460 01:01:51.558985 Write Rank0 MR3 =0x30
461 01:01:51.559033 Write Rank0 MR13 =0xd8
462 01:01:51.559079 [ModeRegInit_LP4] CH0 RK1
463 01:01:51.559127 Write Rank1 MR13 =0x18
464 01:01:51.559174 Write Rank1 MR12 =0x5d
465 01:01:51.559221 Write Rank1 MR1 =0x56
466 01:01:51.559269 Write Rank1 MR2 =0x1a
467 01:01:51.559315 Write Rank1 MR11 =0x0
468 01:01:51.559362 Write Rank1 MR22 =0x38
469 01:01:51.559409 Write Rank1 MR14 =0x5d
470 01:01:51.559456 Write Rank1 MR3 =0x30
471 01:01:51.559504 Write Rank1 MR13 =0x58
472 01:01:51.559551 Write Rank1 MR12 =0x5d
473 01:01:51.559598 Write Rank1 MR1 =0x56
474 01:01:51.559645 Write Rank1 MR2 =0x2d
475 01:01:51.559693 Write Rank1 MR11 =0x23
476 01:01:51.559740 Write Rank1 MR22 =0x34
477 01:01:51.559787 Write Rank1 MR14 =0x10
478 01:01:51.559834 Write Rank1 MR3 =0x30
479 01:01:51.559880 Write Rank1 MR13 =0xd8
480 01:01:51.559927 [ModeRegInit_LP4] CH1 RK0
481 01:01:51.559974 Write Rank0 MR13 =0x18
482 01:01:51.560021 Write Rank0 MR12 =0x5d
483 01:01:51.560068 Write Rank0 MR1 =0x56
484 01:01:51.560115 Write Rank0 MR2 =0x1a
485 01:01:51.560162 Write Rank0 MR11 =0x0
486 01:01:51.560209 Write Rank0 MR22 =0x38
487 01:01:51.560256 Write Rank0 MR14 =0x5d
488 01:01:51.560302 Write Rank0 MR3 =0x30
489 01:01:51.560349 Write Rank0 MR13 =0x58
490 01:01:51.560395 Write Rank0 MR12 =0x5d
491 01:01:51.560443 Write Rank0 MR1 =0x56
492 01:01:51.560491 Write Rank0 MR2 =0x2d
493 01:01:51.560538 Write Rank0 MR11 =0x23
494 01:01:51.560585 Write Rank0 MR22 =0x34
495 01:01:51.560632 Write Rank0 MR14 =0x10
496 01:01:51.560679 Write Rank0 MR3 =0x30
497 01:01:51.560726 Write Rank0 MR13 =0xd8
498 01:01:51.560773 [ModeRegInit_LP4] CH1 RK1
499 01:01:51.560819 Write Rank1 MR13 =0x18
500 01:01:51.560866 Write Rank1 MR12 =0x5d
501 01:01:51.560912 Write Rank1 MR1 =0x56
502 01:01:51.560960 Write Rank1 MR2 =0x1a
503 01:01:51.561007 Write Rank1 MR11 =0x0
504 01:01:51.561054 Write Rank1 MR22 =0x38
505 01:01:51.561101 Write Rank1 MR14 =0x5d
506 01:01:51.561148 Write Rank1 MR3 =0x30
507 01:01:51.561195 Write Rank1 MR13 =0x58
508 01:01:51.561241 Write Rank1 MR12 =0x5d
509 01:01:51.561287 Write Rank1 MR1 =0x56
510 01:01:51.561334 Write Rank1 MR2 =0x2d
511 01:01:51.561384 Write Rank1 MR11 =0x23
512 01:01:51.561432 Write Rank1 MR22 =0x34
513 01:01:51.561479 Write Rank1 MR14 =0x10
514 01:01:51.561526 Write Rank1 MR3 =0x30
515 01:01:51.561573 Write Rank1 MR13 =0xd8
516 01:01:51.561621 match AC timing 3
517 01:01:51.561668 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
518 01:01:51.561717 [MiockJmeterHQA]
519 01:01:51.561765 vSetVcoreByFreq with vcore:762500, freq=1600
520 01:01:51.561812
521 01:01:51.561859 MIOCK jitter meter ch=0
522 01:01:51.561907
523 01:01:51.561954 1T = (101-18) = 83 dly cells
524 01:01:51.562003 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 753/100 ps
525 01:01:51.562051 vSetVcoreByFreq with vcore:725000, freq=1200
526 01:01:51.562099
527 01:01:51.562146 MIOCK jitter meter ch=0
528 01:01:51.562192
529 01:01:51.562269 1T = (95-17) = 78 dly cells
530 01:01:51.562332 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
531 01:01:51.562380 vSetVcoreByFreq with vcore:725000, freq=800
532 01:01:51.562427
533 01:01:51.562474 MIOCK jitter meter ch=0
534 01:01:51.562522
535 01:01:51.562568 1T = (95-17) = 78 dly cells
536 01:01:51.562617 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps
537 01:01:51.562665 vSetVcoreByFreq with vcore:762500, freq=1600
538 01:01:51.562712 vSetVcoreByFreq with vcore:762500, freq=1600
539 01:01:51.562760
540 01:01:51.562807 K DRVP
541 01:01:51.562854 1. OCD DRVP=0 CALOUT=0
542 01:01:51.562903 1. OCD DRVP=1 CALOUT=0
543 01:01:51.562951 1. OCD DRVP=2 CALOUT=0
544 01:01:51.563000 1. OCD DRVP=3 CALOUT=0
545 01:01:51.563047 1. OCD DRVP=4 CALOUT=0
546 01:01:51.563095 1. OCD DRVP=5 CALOUT=0
547 01:01:51.563144 1. OCD DRVP=6 CALOUT=0
548 01:01:51.563193 1. OCD DRVP=7 CALOUT=0
549 01:01:51.563241 1. OCD DRVP=8 CALOUT=1
550 01:01:51.563289
551 01:01:51.563337 1. OCD DRVP calibration OK! DRVP=8
552 01:01:51.563386
553 01:01:51.563432
554 01:01:51.563479
555 01:01:51.563525 K ODTN
556 01:01:51.563573 3. OCD ODTN=0 ,CALOUT=1
557 01:01:51.563623 3. OCD ODTN=1 ,CALOUT=1
558 01:01:51.563672 3. OCD ODTN=2 ,CALOUT=1
559 01:01:51.563721 3. OCD ODTN=3 ,CALOUT=1
560 01:01:51.563769 3. OCD ODTN=4 ,CALOUT=1
561 01:01:51.563817 3. OCD ODTN=5 ,CALOUT=1
562 01:01:51.563865 3. OCD ODTN=6 ,CALOUT=1
563 01:01:51.563913 3. OCD ODTN=7 ,CALOUT=0
564 01:01:51.563961
565 01:01:51.564008 3. OCD ODTN calibration OK! ODTN=7
566 01:01:51.564056
567 01:01:51.564103 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
568 01:01:51.564150 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
569 01:01:51.564198 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
570 01:01:51.564245
571 01:01:51.564292 K DRVP
572 01:01:51.564339 1. OCD DRVP=0 CALOUT=0
573 01:01:51.564388 1. OCD DRVP=1 CALOUT=0
574 01:01:51.564436 1. OCD DRVP=2 CALOUT=0
575 01:01:51.564484 1. OCD DRVP=3 CALOUT=0
576 01:01:51.564532 1. OCD DRVP=4 CALOUT=0
577 01:01:51.564581 1. OCD DRVP=5 CALOUT=0
578 01:01:51.564629 1. OCD DRVP=6 CALOUT=0
579 01:01:51.564676 1. OCD DRVP=7 CALOUT=0
580 01:01:51.564724 1. OCD DRVP=8 CALOUT=0
581 01:01:51.564772 1. OCD DRVP=9 CALOUT=1
582 01:01:51.564820
583 01:01:51.565054 1. OCD DRVP calibration OK! DRVP=9
584 01:01:51.565116
585 01:01:51.565165
586 01:01:51.565213
587 01:01:51.565260 K ODTN
588 01:01:51.565307 3. OCD ODTN=0 ,CALOUT=1
589 01:01:51.565358 3. OCD ODTN=1 ,CALOUT=1
590 01:01:51.565406 3. OCD ODTN=2 ,CALOUT=1
591 01:01:51.565455 3. OCD ODTN=3 ,CALOUT=1
592 01:01:51.565503 3. OCD ODTN=4 ,CALOUT=1
593 01:01:51.565551 3. OCD ODTN=5 ,CALOUT=1
594 01:01:51.565599 3. OCD ODTN=6 ,CALOUT=1
595 01:01:51.565647 3. OCD ODTN=7 ,CALOUT=1
596 01:01:51.565696 3. OCD ODTN=8 ,CALOUT=1
597 01:01:51.565744 3. OCD ODTN=9 ,CALOUT=1
598 01:01:51.565792 3. OCD ODTN=10 ,CALOUT=1
599 01:01:51.565841 3. OCD ODTN=11 ,CALOUT=1
600 01:01:51.565889 3. OCD ODTN=12 ,CALOUT=1
601 01:01:51.565937 3. OCD ODTN=13 ,CALOUT=0
602 01:01:51.565985
603 01:01:51.566033 3. OCD ODTN calibration OK! ODTN=13
604 01:01:51.566082
605 01:01:51.566129 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=13
606 01:01:51.566177 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=13
607 01:01:51.566231 term_option=1, Reg: DRVP=9, DRVN=9, ODTN=13 (After Adjust)
608 01:01:51.566279
609 01:01:51.566327 [DramcInit]
610 01:01:51.566375 AutoRefreshCKEOff AutoREF OFF
611 01:01:51.566423 DDRPhyPLLSetting-CKEOFF
612 01:01:51.566470 DDRPhyPLLSetting-CKEON
613 01:01:51.566517
614 01:01:51.566570 Enable WDQS
615 01:01:51.566617 ==
616 01:01:51.566669 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
617 01:01:51.566718 fsp= 1, odt_onoff= 1, Byte mode= 0
618 01:01:51.566765 ==
619 01:01:51.566812 [Duty_Offset_Calibration]
620 01:01:51.566859
621 01:01:51.566906 ===========================
622 01:01:51.566954 B0:1 B1:0 CA:0
623 01:01:51.567001 ==
624 01:01:51.567049 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
625 01:01:51.567097 fsp= 1, odt_onoff= 1, Byte mode= 0
626 01:01:51.567144 ==
627 01:01:51.567192 [Duty_Offset_Calibration]
628 01:01:51.567238
629 01:01:51.567284 ===========================
630 01:01:51.567332 B0:1 B1:0 CA:-1
631 01:01:51.567380 [ModeRegInit_LP4] CH0 RK0
632 01:01:51.567427 Write Rank0 MR13 =0x18
633 01:01:51.567474 Write Rank0 MR12 =0x5d
634 01:01:51.567521 Write Rank0 MR1 =0x56
635 01:01:51.567568 Write Rank0 MR2 =0x1a
636 01:01:51.567615 Write Rank0 MR11 =0x0
637 01:01:51.567661 Write Rank0 MR22 =0x38
638 01:01:51.567708 Write Rank0 MR14 =0x5d
639 01:01:51.567756 Write Rank0 MR3 =0x30
640 01:01:51.567803 Write Rank0 MR13 =0x58
641 01:01:51.567850 Write Rank0 MR12 =0x5d
642 01:01:51.567897 Write Rank0 MR1 =0x56
643 01:01:51.567944 Write Rank0 MR2 =0x2d
644 01:01:51.567991 Write Rank0 MR11 =0x23
645 01:01:51.568038 Write Rank0 MR22 =0x34
646 01:01:51.568084 Write Rank0 MR14 =0x10
647 01:01:51.568131 Write Rank0 MR3 =0x30
648 01:01:51.568177 Write Rank0 MR13 =0xd8
649 01:01:51.568224 [ModeRegInit_LP4] CH0 RK1
650 01:01:51.568271 Write Rank1 MR13 =0x18
651 01:01:51.568318 Write Rank1 MR12 =0x5d
652 01:01:51.568365 Write Rank1 MR1 =0x56
653 01:01:51.568412 Write Rank1 MR2 =0x1a
654 01:01:51.568459 Write Rank1 MR11 =0x0
655 01:01:51.568505 Write Rank1 MR22 =0x38
656 01:01:51.568552 Write Rank1 MR14 =0x5d
657 01:01:51.568599 Write Rank1 MR3 =0x30
658 01:01:51.568646 Write Rank1 MR13 =0x58
659 01:01:51.568693 Write Rank1 MR12 =0x5d
660 01:01:51.568740 Write Rank1 MR1 =0x56
661 01:01:51.568787 Write Rank1 MR2 =0x2d
662 01:01:51.568835 Write Rank1 MR11 =0x23
663 01:01:51.568881 Write Rank1 MR22 =0x34
664 01:01:51.568928 Write Rank1 MR14 =0x10
665 01:01:51.568975 Write Rank1 MR3 =0x30
666 01:01:51.569023 Write Rank1 MR13 =0xd8
667 01:01:51.569070 [ModeRegInit_LP4] CH1 RK0
668 01:01:51.569117 Write Rank0 MR13 =0x18
669 01:01:51.569163 Write Rank0 MR12 =0x5d
670 01:01:51.569210 Write Rank0 MR1 =0x56
671 01:01:51.569257 Write Rank0 MR2 =0x1a
672 01:01:51.569304 Write Rank0 MR11 =0x0
673 01:01:51.569352 Write Rank0 MR22 =0x38
674 01:01:51.569399 Write Rank0 MR14 =0x5d
675 01:01:51.569447 Write Rank0 MR3 =0x30
676 01:01:51.569494 Write Rank0 MR13 =0x58
677 01:01:51.569541 Write Rank0 MR12 =0x5d
678 01:01:51.569589 Write Rank0 MR1 =0x56
679 01:01:51.569636 Write Rank0 MR2 =0x2d
680 01:01:51.569684 Write Rank0 MR11 =0x23
681 01:01:51.569738 Write Rank0 MR22 =0x34
682 01:01:51.569785 Write Rank0 MR14 =0x10
683 01:01:51.569832 Write Rank0 MR3 =0x30
684 01:01:51.569879 Write Rank0 MR13 =0xd8
685 01:01:51.569926 [ModeRegInit_LP4] CH1 RK1
686 01:01:51.569973 Write Rank1 MR13 =0x18
687 01:01:51.570020 Write Rank1 MR12 =0x5d
688 01:01:51.570067 Write Rank1 MR1 =0x56
689 01:01:51.570114 Write Rank1 MR2 =0x1a
690 01:01:51.570161 Write Rank1 MR11 =0x0
691 01:01:51.570207 Write Rank1 MR22 =0x38
692 01:01:51.570305 Write Rank1 MR14 =0x5d
693 01:01:51.570354 Write Rank1 MR3 =0x30
694 01:01:51.570401 Write Rank1 MR13 =0x58
695 01:01:51.570449 Write Rank1 MR12 =0x5d
696 01:01:51.570496 Write Rank1 MR1 =0x56
697 01:01:51.570544 Write Rank1 MR2 =0x2d
698 01:01:51.570591 Write Rank1 MR11 =0x23
699 01:01:51.570638 Write Rank1 MR22 =0x34
700 01:01:51.570684 Write Rank1 MR14 =0x10
701 01:01:51.570732 Write Rank1 MR3 =0x30
702 01:01:51.570780 Write Rank1 MR13 =0xd8
703 01:01:51.570828 match AC timing 3
704 01:01:51.570875 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
705 01:01:51.570925 DramC Write-DBI off
706 01:01:51.570972 DramC Read-DBI off
707 01:01:51.571019 Write Rank0 MR13 =0x59
708 01:01:51.571066 ==
709 01:01:51.571113 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
710 01:01:51.571161 fsp= 1, odt_onoff= 1, Byte mode= 0
711 01:01:51.571209 ==
712 01:01:51.571256 === u2Vref_new: 0x56 --> 0x2d
713 01:01:51.571303 === u2Vref_new: 0x58 --> 0x38
714 01:01:51.571351 === u2Vref_new: 0x5a --> 0x39
715 01:01:51.571399 === u2Vref_new: 0x5c --> 0x3c
716 01:01:51.571446 === u2Vref_new: 0x5e --> 0x3d
717 01:01:51.571493 === u2Vref_new: 0x60 --> 0xa0
718 01:01:51.571540 [CA 0] Center 33 (4~63) winsize 60
719 01:01:51.571588 [CA 1] Center 34 (6~63) winsize 58
720 01:01:51.571635 [CA 2] Center 27 (-1~55) winsize 57
721 01:01:51.571682 [CA 3] Center 23 (-4~51) winsize 56
722 01:01:51.571730 [CA 4] Center 23 (-4~51) winsize 56
723 01:01:51.571778 [CA 5] Center 28 (-1~58) winsize 60
724 01:01:51.571825
725 01:01:51.571873 [CATrainingPosCal] consider 1 rank data
726 01:01:51.571921 u2DelayCellTimex100 = 753/100 ps
727 01:01:51.571969 CA0 delay=33 (4~63),Diff = 10 PI (12 cell)
728 01:01:51.572016 CA1 delay=34 (6~63),Diff = 11 PI (14 cell)
729 01:01:51.572063 CA2 delay=27 (-1~55),Diff = 4 PI (5 cell)
730 01:01:51.572111 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
731 01:01:51.572158 CA4 delay=23 (-4~51),Diff = 0 PI (0 cell)
732 01:01:51.572206 CA5 delay=28 (-1~58),Diff = 5 PI (6 cell)
733 01:01:51.572253
734 01:01:51.572300 CA PerBit enable=1, Macro0, CA PI delay=23
735 01:01:51.572347 === u2Vref_new: 0x56 --> 0x2d
736 01:01:51.572395
737 01:01:51.572441 Vref(ca) range 1: 22
738 01:01:51.572488
739 01:01:51.572535 CS Dly= 10 (41-0-32)
740 01:01:51.572581 Write Rank0 MR13 =0xd8
741 01:01:51.572628 Write Rank0 MR13 =0xd8
742 01:01:51.572675 Write Rank0 MR12 =0x56
743 01:01:51.572723 Write Rank1 MR13 =0x59
744 01:01:51.572770 ==
745 01:01:51.572817 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
746 01:01:51.573069 fsp= 1, odt_onoff= 1, Byte mode= 0
747 01:01:51.573148 ==
748 01:01:51.573244 === u2Vref_new: 0x56 --> 0x2d
749 01:01:51.573331 === u2Vref_new: 0x58 --> 0x38
750 01:01:51.573407 === u2Vref_new: 0x5a --> 0x39
751 01:01:51.573483 === u2Vref_new: 0x5c --> 0x3c
752 01:01:51.573559 === u2Vref_new: 0x5e --> 0x3d
753 01:01:51.573635 === u2Vref_new: 0x60 --> 0xa0
754 01:01:51.573711 [CA 0] Center 33 (4~63) winsize 60
755 01:01:51.573787 [CA 1] Center 34 (5~63) winsize 59
756 01:01:51.573862 [CA 2] Center 28 (0~56) winsize 57
757 01:01:51.573938 [CA 3] Center 23 (-4~51) winsize 56
758 01:01:51.574014 [CA 4] Center 24 (-3~52) winsize 56
759 01:01:51.574090 [CA 5] Center 29 (1~58) winsize 58
760 01:01:51.574165
761 01:01:51.574249 [CATrainingPosCal] consider 2 rank data
762 01:01:51.574326 u2DelayCellTimex100 = 753/100 ps
763 01:01:51.574402 CA0 delay=33 (4~63),Diff = 10 PI (12 cell)
764 01:01:51.574478 CA1 delay=34 (6~63),Diff = 11 PI (14 cell)
765 01:01:51.574554 CA2 delay=27 (0~55),Diff = 4 PI (5 cell)
766 01:01:51.574630 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
767 01:01:51.574706 CA4 delay=24 (-3~51),Diff = 1 PI (1 cell)
768 01:01:51.574781 CA5 delay=29 (1~58),Diff = 6 PI (7 cell)
769 01:01:51.574856
770 01:01:51.574931 CA PerBit enable=1, Macro0, CA PI delay=23
771 01:01:51.575008 === u2Vref_new: 0x56 --> 0x2d
772 01:01:51.575083
773 01:01:51.575157 Vref(ca) range 1: 22
774 01:01:51.575232
775 01:01:51.575307 CS Dly= 7 (38-0-32)
776 01:01:51.575383 Write Rank1 MR13 =0xd8
777 01:01:51.575458 Write Rank1 MR13 =0xd8
778 01:01:51.575533 Write Rank1 MR12 =0x56
779 01:01:51.575609 [RankSwap] Rank num 2, (Multi 1), Rank 0
780 01:01:51.575685 Write Rank0 MR2 =0xad
781 01:01:51.575760 [Write Leveling]
782 01:01:51.575835 delay byte0 byte1 byte2 byte3
783 01:01:51.575910
784 01:01:51.575984 10 0 0
785 01:01:51.576062 11 0 0
786 01:01:51.576139 12 0 0
787 01:01:51.576216 13 0 0
788 01:01:51.576293 14 0 0
789 01:01:51.576370 15 0 0
790 01:01:51.576447 16 0 0
791 01:01:51.576524 17 0 0
792 01:01:51.576601 18 0 0
793 01:01:51.576677 19 0 0
794 01:01:51.576754 20 0 0
795 01:01:51.576831 21 0 0
796 01:01:51.576907 22 0 0
797 01:01:51.576984 23 0 0
798 01:01:51.577061 24 0 0
799 01:01:51.577138 25 0 0
800 01:01:51.577215 26 0 0
801 01:01:51.577292 27 0 0
802 01:01:51.577369 28 0 ff
803 01:01:51.577445 29 0 ff
804 01:01:51.577522 30 0 ff
805 01:01:51.577599 31 0 ff
806 01:01:51.577676 32 0 ff
807 01:01:51.577753 33 ff ff
808 01:01:51.577830 34 ff ff
809 01:01:51.577907 35 ff ff
810 01:01:51.577984 36 ff ff
811 01:01:51.578061 37 ff ff
812 01:01:51.578138 38 ff ff
813 01:01:51.578221 39 ff ff
814 01:01:51.578301 pass bytecount = 0xff (0xff: all bytes pass)
815 01:01:51.578376
816 01:01:51.578451 DQS0 dly: 33
817 01:01:51.578526 DQS1 dly: 28
818 01:01:51.578601 Write Rank0 MR2 =0x2d
819 01:01:51.578677 [RankSwap] Rank num 2, (Multi 1), Rank 0
820 01:01:51.578752 Write Rank0 MR1 =0xd6
821 01:01:51.578827 [Gating]
822 01:01:51.578901 ==
823 01:01:51.578977 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
824 01:01:51.579053 fsp= 1, odt_onoff= 1, Byte mode= 0
825 01:01:51.579128 ==
826 01:01:51.579204 3 1 0 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
827 01:01:51.579283 3 1 4 |3534 1c1b |(11 11)(11 11) |(0 0)(1 1)| 0
828 01:01:51.579362 3 1 8 |3534 3635 |(11 11)(11 11) |(0 0)(1 1)| 0
829 01:01:51.579440 3 1 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
830 01:01:51.579518 3 1 16 |3534 1110 |(11 11)(11 11) |(0 0)(0 1)| 0
831 01:01:51.579596 3 1 20 |3534 1515 |(11 11)(11 11) |(0 0)(0 1)| 0
832 01:01:51.579674 3 1 24 |3534 3433 |(11 11)(11 11) |(0 1)(0 1)| 0
833 01:01:51.579752 3 1 28 |3534 3434 |(11 11)(0 0) |(0 1)(0 1)| 0
834 01:01:51.579830 3 2 0 |b0a c0b |(11 11)(11 11) |(1 1)(1 1)| 0
835 01:01:51.579908 3 2 4 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
836 01:01:51.579986 3 2 8 |3d3d 1111 |(11 11)(11 11) |(1 1)(1 1)| 0
837 01:01:51.580063 3 2 12 |3d3d 3b3a |(11 11)(11 11) |(1 1)(1 1)| 0
838 01:01:51.580142 3 2 16 |3d3d 2525 |(11 11)(11 11) |(1 1)(1 1)| 0
839 01:01:51.580220 3 2 20 |3d3d 3c3c |(11 11)(11 11) |(1 1)(1 1)| 0
840 01:01:51.580297 3 2 24 |3d3d 3c3b |(11 11)(11 11) |(1 1)(1 1)| 0
841 01:01:51.580376 3 2 28 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
842 01:01:51.580454 3 3 0 |3d3d a0a |(11 11)(11 11) |(1 1)(1 1)| 0
843 01:01:51.580532 3 3 4 |3d3d 0 |(11 11)(11 11) |(1 1)(1 1)| 0
844 01:01:51.580610 3 3 8 |3332 504 |(11 11)(11 11) |(1 1)(1 1)| 0
845 01:01:51.580687 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
846 01:01:51.580765 [Byte 0] Lead/lag Transition tap number (1)
847 01:01:51.580841 [Byte 1] Lead/lag falling Transition (3, 3, 12)
848 01:01:51.580917 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
849 01:01:51.580995 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
850 01:01:51.581073 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
851 01:01:51.581150 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
852 01:01:51.581228 3 4 0 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
853 01:01:51.581306 3 4 4 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
854 01:01:51.581383 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
855 01:01:51.581461 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
856 01:01:51.581539 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
857 01:01:51.581617 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
858 01:01:51.581695 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
859 01:01:51.581773 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
860 01:01:51.581851 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
861 01:01:51.581929 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
862 01:01:51.582006 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
863 01:01:51.582084 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
864 01:01:51.582162 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
865 01:01:51.582240 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
866 01:01:51.582291 [Byte 0] Lead/lag falling Transition (3, 5, 20)
867 01:01:51.582339 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
868 01:01:51.582388 [Byte 1] Lead/lag falling Transition (3, 5, 24)
869 01:01:51.582437 3 5 28 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
870 01:01:51.582485 [Byte 0] Lead/lag Transition tap number (3)
871 01:01:51.582724 [Byte 1] Lead/lag Transition tap number (2)
872 01:01:51.582783 3 6 0 |606 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
873 01:01:51.582834 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
874 01:01:51.582883 [Byte 0]First pass (3, 6, 4)
875 01:01:51.582931 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
876 01:01:51.582979 [Byte 1]First pass (3, 6, 8)
877 01:01:51.583026 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
878 01:01:51.583079 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
879 01:01:51.583130 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
880 01:01:51.583178 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
881 01:01:51.583226 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
882 01:01:51.583275 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
883 01:01:51.583323 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
884 01:01:51.583371 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
885 01:01:51.583420 All bytes gating window > 1UI, Early break!
886 01:01:51.583468
887 01:01:51.583516 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 26)
888 01:01:51.583563
889 01:01:51.583610 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28)
890 01:01:51.583658
891 01:01:51.583704
892 01:01:51.583751
893 01:01:51.583797 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
894 01:01:51.583845
895 01:01:51.583893 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
896 01:01:51.583940
897 01:01:51.583987
898 01:01:51.584034 Write Rank0 MR1 =0x56
899 01:01:51.584081
900 01:01:51.584128 best RODT dly(2T, 0.5T) = (2, 2)
901 01:01:51.584174
902 01:01:51.584221 best RODT dly(2T, 0.5T) = (2, 2)
903 01:01:51.584268 ==
904 01:01:51.584315 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
905 01:01:51.584363 fsp= 1, odt_onoff= 1, Byte mode= 0
906 01:01:51.584411 ==
907 01:01:51.584458 Start DQ dly to find pass range UseTestEngine =0
908 01:01:51.584508 x-axis: bit #, y-axis: DQ dly (-127~63)
909 01:01:51.584559 RX Vref Scan = 0
910 01:01:51.584610 -26, [0] xxxxxxxx xxxxxxxx [MSB]
911 01:01:51.584660 -25, [0] xxxxxxxx xxxxxxxx [MSB]
912 01:01:51.584708 -24, [0] xxxxxxxx xxxxxxxx [MSB]
913 01:01:51.584756 -23, [0] xxxxxxxx xxxxxxxx [MSB]
914 01:01:51.584805 -22, [0] xxxxxxxx xxxxxxxx [MSB]
915 01:01:51.584853 -21, [0] xxxxxxxx xxxxxxxx [MSB]
916 01:01:51.584901 -20, [0] xxxxxxxx xxxxxxxx [MSB]
917 01:01:51.584949 -19, [0] xxxxxxxx xxxxxxxx [MSB]
918 01:01:51.584998 -18, [0] xxxxxxxx xxxxxxxx [MSB]
919 01:01:51.585046 -17, [0] xxxxxxxx xxxxxxxx [MSB]
920 01:01:51.585094 -16, [0] xxxxxxxx xxxxxxxx [MSB]
921 01:01:51.585142 -15, [0] xxxxxxxx xxxxxxxx [MSB]
922 01:01:51.585190 -14, [0] xxxxxxxx xxxxxxxx [MSB]
923 01:01:51.585238 -13, [0] xxxxxxxx xxxxxxxx [MSB]
924 01:01:51.585286 -12, [0] xxxxxxxx xxxxxxxx [MSB]
925 01:01:51.585335 -11, [0] xxxxxxxx xxxxxxxx [MSB]
926 01:01:51.585383 -10, [0] xxxxxxxx xxxxxxxx [MSB]
927 01:01:51.585431 -9, [0] xxxxxxxx xxxxxxxx [MSB]
928 01:01:51.585479 -8, [0] xxxxxxxx xxxxxxxx [MSB]
929 01:01:51.585528 -7, [0] xxxxxxxx xxxxxxxx [MSB]
930 01:01:51.585576 -6, [0] xxxxxxxx xxxxxxxx [MSB]
931 01:01:51.585624 -5, [0] xxxxxxxx xxxxxxxx [MSB]
932 01:01:51.585672 -4, [0] xxxxxxxx xxxxxxxx [MSB]
933 01:01:51.585720 -3, [0] xxxxxxxx xxxxxxxx [MSB]
934 01:01:51.585767 -2, [0] xxxoxxxx xxxxxxxx [MSB]
935 01:01:51.585815 -1, [0] xxxoxxxx xxxxxxxx [MSB]
936 01:01:51.585863 0, [0] xxxoxoox xxxxxoxx [MSB]
937 01:01:51.585911 1, [0] xxxoxooo xxxxxoxx [MSB]
938 01:01:51.585959 2, [0] xxxoxooo ooxxxoxx [MSB]
939 01:01:51.586008 3, [0] xxxoxooo ooxooooo [MSB]
940 01:01:51.586055 4, [0] xxxoxooo ooxooooo [MSB]
941 01:01:51.586103 5, [0] xxxoxooo ooxooooo [MSB]
942 01:01:51.586151 6, [0] xxxooooo oooooooo [MSB]
943 01:01:51.586199 7, [0] xooooooo oooooooo [MSB]
944 01:01:51.586256 8, [0] xooooooo oooooooo [MSB]
945 01:01:51.586306 30, [0] oooxoooo oooooooo [MSB]
946 01:01:51.586355 31, [0] oooxoooo oooooooo [MSB]
947 01:01:51.586407 32, [0] oooxoxxo oooooooo [MSB]
948 01:01:51.586457 33, [0] oooxoxxo ooooooxo [MSB]
949 01:01:51.586506 34, [0] oooxoxxo oooxooxo [MSB]
950 01:01:51.586554 35, [0] oooxoxxx xooxooxo [MSB]
951 01:01:51.586602 36, [0] oooxoxxx xooxoxxo [MSB]
952 01:01:51.586650 37, [0] oooxoxxx xooxxxxo [MSB]
953 01:01:51.586700 38, [0] oooxxxxx xxoxxxxx [MSB]
954 01:01:51.586748 39, [0] oxoxxxxx xxoxxxxx [MSB]
955 01:01:51.586796 40, [0] oxxxxxxx xxoxxxxx [MSB]
956 01:01:51.586845 41, [0] xxxxxxxx xxxxxxxx [MSB]
957 01:01:51.586893 iDelay=41, Bit 0, Center 24 (9 ~ 40) 32
958 01:01:51.586940 iDelay=41, Bit 1, Center 22 (7 ~ 38) 32
959 01:01:51.586988 iDelay=41, Bit 2, Center 23 (7 ~ 39) 33
960 01:01:51.587036 iDelay=41, Bit 3, Center 13 (-2 ~ 29) 32
961 01:01:51.587083 iDelay=41, Bit 4, Center 21 (6 ~ 37) 32
962 01:01:51.587130 iDelay=41, Bit 5, Center 15 (0 ~ 31) 32
963 01:01:51.587178 iDelay=41, Bit 6, Center 15 (0 ~ 31) 32
964 01:01:51.587225 iDelay=41, Bit 7, Center 17 (1 ~ 34) 34
965 01:01:51.587272 iDelay=41, Bit 8, Center 18 (2 ~ 34) 33
966 01:01:51.587319 iDelay=41, Bit 9, Center 19 (2 ~ 37) 36
967 01:01:51.587367 iDelay=41, Bit 10, Center 23 (6 ~ 40) 35
968 01:01:51.587414 iDelay=41, Bit 11, Center 18 (3 ~ 33) 31
969 01:01:51.587462 iDelay=41, Bit 12, Center 19 (3 ~ 36) 34
970 01:01:51.587509 iDelay=41, Bit 13, Center 17 (0 ~ 35) 36
971 01:01:51.587556 iDelay=41, Bit 14, Center 17 (3 ~ 32) 30
972 01:01:51.587603 iDelay=41, Bit 15, Center 20 (3 ~ 37) 35
973 01:01:51.587650 ==
974 01:01:51.587698 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
975 01:01:51.587745 fsp= 1, odt_onoff= 1, Byte mode= 0
976 01:01:51.587792 ==
977 01:01:51.587840 DQS Delay:
978 01:01:51.587887 DQS0 = 0, DQS1 = 0
979 01:01:51.587934 DQM Delay:
980 01:01:51.587981 DQM0 = 18, DQM1 = 18
981 01:01:51.588033 DQ Delay:
982 01:01:51.588087 DQ0 =24, DQ1 =22, DQ2 =23, DQ3 =13
983 01:01:51.588136 DQ4 =21, DQ5 =15, DQ6 =15, DQ7 =17
984 01:01:51.588185 DQ8 =18, DQ9 =19, DQ10 =23, DQ11 =18
985 01:01:51.588247 DQ12 =19, DQ13 =17, DQ14 =17, DQ15 =20
986 01:01:51.588308
987 01:01:51.588356
988 01:01:51.588403 DramC Write-DBI off
989 01:01:51.588451 ==
990 01:01:51.588498 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
991 01:01:51.588546 fsp= 1, odt_onoff= 1, Byte mode= 0
992 01:01:51.588593 ==
993 01:01:51.588641 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
994 01:01:51.588688
995 01:01:51.588736 Begin, DQ Scan Range 924~1180
996 01:01:51.588784
997 01:01:51.588830
998 01:01:51.588877 TX Vref Scan disable
999 01:01:51.588923 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1000 01:01:51.588972 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1001 01:01:51.589021 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1002 01:01:51.589273 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1003 01:01:51.589354 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1004 01:01:51.589453 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1005 01:01:51.589551 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1006 01:01:51.589650 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1007 01:01:51.589748 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1008 01:01:51.589849 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1009 01:01:51.589948 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1010 01:01:51.590038 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1011 01:01:51.590117 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1012 01:01:51.590196 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1013 01:01:51.590314 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1014 01:01:51.590394 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1015 01:01:51.590473 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1016 01:01:51.590551 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1017 01:01:51.590630 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1018 01:01:51.590708 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1019 01:01:51.590786 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1020 01:01:51.590863 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1021 01:01:51.590941 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1022 01:01:51.591021 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1023 01:01:51.591100 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1024 01:01:51.591179 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1025 01:01:51.591257 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1026 01:01:51.591335 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1027 01:01:51.591413 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1028 01:01:51.591491 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1029 01:01:51.591569 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1030 01:01:51.591647 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1031 01:01:51.591725 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1032 01:01:51.591803 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1033 01:01:51.591881 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1034 01:01:51.591959 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1035 01:01:51.592037 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1036 01:01:51.592114 961 |3 6 1|[0] xxxxxxxx oxxxxxxx [MSB]
1037 01:01:51.592193 962 |3 6 2|[0] xxxxxxxx oxxoxxxx [MSB]
1038 01:01:51.592271 963 |3 6 3|[0] xxxxxxxx ooxooxox [MSB]
1039 01:01:51.592349 964 |3 6 4|[0] xxxxxxxx ooxoooox [MSB]
1040 01:01:51.592426 965 |3 6 5|[0] xxxxxxxx ooxoooox [MSB]
1041 01:01:51.592504 966 |3 6 6|[0] xxxxxxxx ooxoooox [MSB]
1042 01:01:51.592582 967 |3 6 7|[0] xxxxxxxx ooxooooo [MSB]
1043 01:01:51.592659 968 |3 6 8|[0] xxxxxxxx oooooooo [MSB]
1044 01:01:51.592737 969 |3 6 9|[0] xxxxxxxx oooooooo [MSB]
1045 01:01:51.592814 970 |3 6 10|[0] xxxxxoxx oooooooo [MSB]
1046 01:01:51.592892 971 |3 6 11|[0] xxxoxoox oooooooo [MSB]
1047 01:01:51.592970 972 |3 6 12|[0] xxxoxooo oooooooo [MSB]
1048 01:01:51.593048 973 |3 6 13|[0] xxxoxooo oooooooo [MSB]
1049 01:01:51.593126 974 |3 6 14|[0] xxxooooo oooooooo [MSB]
1050 01:01:51.593204 975 |3 6 15|[0] xooooooo oooooooo [MSB]
1051 01:01:51.593337 988 |3 6 28|[0] oooooooo xooooxoo [MSB]
1052 01:01:51.593429 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1053 01:01:51.593507 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1054 01:01:51.593584 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1055 01:01:51.593662 992 |3 6 32|[0] oooxoooo xxxxxxxx [MSB]
1056 01:01:51.593740 993 |3 6 33|[0] oooxoxoo xxxxxxxx [MSB]
1057 01:01:51.593818 994 |3 6 34|[0] oooxoxxo xxxxxxxx [MSB]
1058 01:01:51.593896 995 |3 6 35|[0] oooxoxxo xxxxxxxx [MSB]
1059 01:01:51.593974 996 |3 6 36|[0] xxxxxxxx xxxxxxxx [MSB]
1060 01:01:51.594051 Byte0, DQ PI dly=983, DQM PI dly= 983
1061 01:01:51.594127 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
1062 01:01:51.594203
1063 01:01:51.594325 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
1064 01:01:51.594402
1065 01:01:51.594478 Byte1, DQ PI dly=976, DQM PI dly= 976
1066 01:01:51.594554 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
1067 01:01:51.594630
1068 01:01:51.594705 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
1069 01:01:51.594781
1070 01:01:51.594855 ==
1071 01:01:51.594931 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1072 01:01:51.595006 fsp= 1, odt_onoff= 1, Byte mode= 0
1073 01:01:51.595081 ==
1074 01:01:51.595157 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1075 01:01:51.595231
1076 01:01:51.595306 Begin, DQ Scan Range 952~1016
1077 01:01:51.595381 Write Rank0 MR14 =0x0
1078 01:01:51.595455
1079 01:01:51.595530 CH=0, VrefRange= 0, VrefLevel = 0
1080 01:01:51.595606 TX Bit0 (977~994) 18 985, Bit8 (964~983) 20 973,
1081 01:01:51.595685 TX Bit1 (977~992) 16 984, Bit9 (966~984) 19 975,
1082 01:01:51.595762 TX Bit2 (977~993) 17 985, Bit10 (969~989) 21 979,
1083 01:01:51.595840 TX Bit3 (970~988) 19 979, Bit11 (965~984) 20 974,
1084 01:01:51.595903 TX Bit4 (976~994) 19 985, Bit12 (967~985) 19 976,
1085 01:01:51.595953 TX Bit5 (974~989) 16 981, Bit13 (967~983) 17 975,
1086 01:01:51.596002 TX Bit6 (975~990) 16 982, Bit14 (967~983) 17 975,
1087 01:01:51.596050 TX Bit7 (975~992) 18 983, Bit15 (968~987) 20 977,
1088 01:01:51.596098
1089 01:01:51.596145 Write Rank0 MR14 =0x2
1090 01:01:51.596192
1091 01:01:51.596239 CH=0, VrefRange= 0, VrefLevel = 2
1092 01:01:51.596287 TX Bit0 (977~995) 19 986, Bit8 (964~983) 20 973,
1093 01:01:51.596336 TX Bit1 (977~993) 17 985, Bit9 (965~984) 20 974,
1094 01:01:51.596384 TX Bit2 (976~994) 19 985, Bit10 (969~989) 21 979,
1095 01:01:51.596432 TX Bit3 (970~989) 20 979, Bit11 (965~984) 20 974,
1096 01:01:51.596480 TX Bit4 (976~995) 20 985, Bit12 (966~986) 21 976,
1097 01:01:51.596562 TX Bit5 (973~990) 18 981, Bit13 (966~983) 18 974,
1098 01:01:51.596610 TX Bit6 (974~990) 17 982, Bit14 (966~984) 19 975,
1099 01:01:51.596658 TX Bit7 (974~992) 19 983, Bit15 (969~988) 20 978,
1100 01:01:51.596706
1101 01:01:51.596753 Write Rank0 MR14 =0x4
1102 01:01:51.596800
1103 01:01:51.596847 CH=0, VrefRange= 0, VrefLevel = 4
1104 01:01:51.596895 TX Bit0 (977~996) 20 986, Bit8 (964~984) 21 974,
1105 01:01:51.596942 TX Bit1 (977~993) 17 985, Bit9 (965~985) 21 975,
1106 01:01:51.596990 TX Bit2 (976~995) 20 985, Bit10 (969~989) 21 979,
1107 01:01:51.597038 TX Bit3 (969~990) 22 979, Bit11 (965~985) 21 975,
1108 01:01:51.597276 TX Bit4 (976~996) 21 986, Bit12 (966~987) 22 976,
1109 01:01:51.597335 TX Bit5 (973~990) 18 981, Bit13 (966~984) 19 975,
1110 01:01:51.597385 TX Bit6 (974~991) 18 982, Bit14 (966~984) 19 975,
1111 01:01:51.597433 TX Bit7 (974~992) 19 983, Bit15 (968~988) 21 978,
1112 01:01:51.597481
1113 01:01:51.597530 Write Rank0 MR14 =0x6
1114 01:01:51.597578
1115 01:01:51.597626 CH=0, VrefRange= 0, VrefLevel = 6
1116 01:01:51.597674 TX Bit0 (977~996) 20 986, Bit8 (963~984) 22 973,
1117 01:01:51.597723 TX Bit1 (977~994) 18 985, Bit9 (965~986) 22 975,
1118 01:01:51.597771 TX Bit2 (976~995) 20 985, Bit10 (969~990) 22 979,
1119 01:01:51.597819 TX Bit3 (969~990) 22 979, Bit11 (964~986) 23 975,
1120 01:01:51.597866 TX Bit4 (975~996) 22 985, Bit12 (965~988) 24 976,
1121 01:01:51.597938 TX Bit5 (972~990) 19 981, Bit13 (966~984) 19 975,
1122 01:01:51.598025 TX Bit6 (973~991) 19 982, Bit14 (965~985) 21 975,
1123 01:01:51.598104 TX Bit7 (974~993) 20 983, Bit15 (968~989) 22 978,
1124 01:01:51.598180
1125 01:01:51.598266 Write Rank0 MR14 =0x8
1126 01:01:51.598329
1127 01:01:51.598377 CH=0, VrefRange= 0, VrefLevel = 8
1128 01:01:51.598425 TX Bit0 (976~997) 22 986, Bit8 (963~985) 23 974,
1129 01:01:51.598473 TX Bit1 (976~995) 20 985, Bit9 (964~987) 24 975,
1130 01:01:51.598521 TX Bit2 (976~996) 21 986, Bit10 (968~990) 23 979,
1131 01:01:51.598570 TX Bit3 (969~990) 22 979, Bit11 (964~986) 23 975,
1132 01:01:51.598618 TX Bit4 (975~997) 23 986, Bit12 (965~988) 24 976,
1133 01:01:51.598665 TX Bit5 (972~991) 20 981, Bit13 (965~985) 21 975,
1134 01:01:51.598713 TX Bit6 (973~991) 19 982, Bit14 (965~985) 21 975,
1135 01:01:51.598762 TX Bit7 (974~993) 20 983, Bit15 (968~989) 22 978,
1136 01:01:51.598809
1137 01:01:51.598856 Write Rank0 MR14 =0xa
1138 01:01:51.598903
1139 01:01:51.598950 CH=0, VrefRange= 0, VrefLevel = 10
1140 01:01:51.598998 TX Bit0 (976~998) 23 987, Bit8 (963~986) 24 974,
1141 01:01:51.599047 TX Bit1 (976~996) 21 986, Bit9 (964~987) 24 975,
1142 01:01:51.599099 TX Bit2 (976~996) 21 986, Bit10 (969~990) 22 979,
1143 01:01:51.599152 TX Bit3 (969~991) 23 980, Bit11 (963~987) 25 975,
1144 01:01:51.599202 TX Bit4 (975~997) 23 986, Bit12 (964~988) 25 976,
1145 01:01:51.599250 TX Bit5 (971~991) 21 981, Bit13 (965~985) 21 975,
1146 01:01:51.599319 TX Bit6 (972~992) 21 982, Bit14 (965~986) 22 975,
1147 01:01:51.599369 TX Bit7 (973~994) 22 983, Bit15 (967~989) 23 978,
1148 01:01:51.599417
1149 01:01:51.599464 Write Rank0 MR14 =0xc
1150 01:01:51.599512
1151 01:01:51.599560 CH=0, VrefRange= 0, VrefLevel = 12
1152 01:01:51.599607 TX Bit0 (976~998) 23 987, Bit8 (962~986) 25 974,
1153 01:01:51.599655 TX Bit1 (976~996) 21 986, Bit9 (964~988) 25 976,
1154 01:01:51.599704 TX Bit2 (975~997) 23 986, Bit10 (968~990) 23 979,
1155 01:01:51.599752 TX Bit3 (968~991) 24 979, Bit11 (963~988) 26 975,
1156 01:01:51.599799 TX Bit4 (975~997) 23 986, Bit12 (964~988) 25 976,
1157 01:01:51.599847 TX Bit5 (971~991) 21 981, Bit13 (965~986) 22 975,
1158 01:01:51.599895 TX Bit6 (972~992) 21 982, Bit14 (964~987) 24 975,
1159 01:01:51.599943 TX Bit7 (973~995) 23 984, Bit15 (967~990) 24 978,
1160 01:01:51.599990
1161 01:01:51.600039 Write Rank0 MR14 =0xe
1162 01:01:51.600086
1163 01:01:51.600133 CH=0, VrefRange= 0, VrefLevel = 14
1164 01:01:51.600185 TX Bit0 (976~998) 23 987, Bit8 (962~987) 26 974,
1165 01:01:51.600235 TX Bit1 (976~996) 21 986, Bit9 (963~988) 26 975,
1166 01:01:51.600283 TX Bit2 (975~997) 23 986, Bit10 (968~991) 24 979,
1167 01:01:51.600330 TX Bit3 (968~991) 24 979, Bit11 (963~988) 26 975,
1168 01:01:51.600378 TX Bit4 (974~998) 25 986, Bit12 (964~989) 26 976,
1169 01:01:51.600426 TX Bit5 (970~992) 23 981, Bit13 (964~987) 24 975,
1170 01:01:51.600474 TX Bit6 (971~992) 22 981, Bit14 (964~988) 25 976,
1171 01:01:51.600522 TX Bit7 (972~995) 24 983, Bit15 (967~990) 24 978,
1172 01:01:51.600570
1173 01:01:51.600617 Write Rank0 MR14 =0x10
1174 01:01:51.600663
1175 01:01:51.600710 CH=0, VrefRange= 0, VrefLevel = 16
1176 01:01:51.600757 TX Bit0 (976~998) 23 987, Bit8 (962~988) 27 975,
1177 01:01:51.600806 TX Bit1 (975~997) 23 986, Bit9 (963~988) 26 975,
1178 01:01:51.600854 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1179 01:01:51.600902 TX Bit3 (968~991) 24 979, Bit11 (962~988) 27 975,
1180 01:01:51.600950 TX Bit4 (974~998) 25 986, Bit12 (963~989) 27 976,
1181 01:01:51.600997 TX Bit5 (970~992) 23 981, Bit13 (963~987) 25 975,
1182 01:01:51.601045 TX Bit6 (971~993) 23 982, Bit14 (963~988) 26 975,
1183 01:01:51.601092 TX Bit7 (972~996) 25 984, Bit15 (967~990) 24 978,
1184 01:01:51.601139
1185 01:01:51.601187 Write Rank0 MR14 =0x12
1186 01:01:51.601234
1187 01:01:51.601281 CH=0, VrefRange= 0, VrefLevel = 18
1188 01:01:51.601328 TX Bit0 (976~998) 23 987, Bit8 (962~988) 27 975,
1189 01:01:51.601376 TX Bit1 (975~997) 23 986, Bit9 (963~988) 26 975,
1190 01:01:51.601424 TX Bit2 (975~998) 24 986, Bit10 (968~991) 24 979,
1191 01:01:51.601472 TX Bit3 (968~991) 24 979, Bit11 (962~988) 27 975,
1192 01:01:51.601520 TX Bit4 (974~998) 25 986, Bit12 (963~989) 27 976,
1193 01:01:51.601567 TX Bit5 (970~992) 23 981, Bit13 (963~987) 25 975,
1194 01:01:51.601615 TX Bit6 (971~993) 23 982, Bit14 (963~988) 26 975,
1195 01:01:51.601663 TX Bit7 (972~996) 25 984, Bit15 (967~990) 24 978,
1196 01:01:51.601710
1197 01:01:51.601757 Write Rank0 MR14 =0x14
1198 01:01:51.601805
1199 01:01:51.601851 CH=0, VrefRange= 0, VrefLevel = 20
1200 01:01:51.601899 TX Bit0 (975~999) 25 987, Bit8 (961~988) 28 974,
1201 01:01:51.601946 TX Bit1 (975~997) 23 986, Bit9 (963~988) 26 975,
1202 01:01:51.601994 TX Bit2 (975~998) 24 986, Bit10 (967~991) 25 979,
1203 01:01:51.602041 TX Bit3 (967~992) 26 979, Bit11 (962~988) 27 975,
1204 01:01:51.602089 TX Bit4 (974~998) 25 986, Bit12 (963~989) 27 976,
1205 01:01:51.602137 TX Bit5 (970~993) 24 981, Bit13 (962~987) 26 974,
1206 01:01:51.602185 TX Bit6 (970~994) 25 982, Bit14 (962~989) 28 975,
1207 01:01:51.602277 TX Bit7 (971~996) 26 983, Bit15 (966~990) 25 978,
1208 01:01:51.602326
1209 01:01:51.602374 Write Rank0 MR14 =0x16
1210 01:01:51.602421
1211 01:01:51.602662 CH=0, VrefRange= 0, VrefLevel = 22
1212 01:01:51.602732 TX Bit0 (976~999) 24 987, Bit8 (961~987) 27 974,
1213 01:01:51.602829 TX Bit1 (975~998) 24 986, Bit9 (964~988) 25 976,
1214 01:01:51.602924 TX Bit2 (974~998) 25 986, Bit10 (967~991) 25 979,
1215 01:01:51.603020 TX Bit3 (967~992) 26 979, Bit11 (962~988) 27 975,
1216 01:01:51.603115 TX Bit4 (974~999) 26 986, Bit12 (963~989) 27 976,
1217 01:01:51.603211 TX Bit5 (969~993) 25 981, Bit13 (963~987) 25 975,
1218 01:01:51.603307 TX Bit6 (970~995) 26 982, Bit14 (963~989) 27 976,
1219 01:01:51.603402 TX Bit7 (971~996) 26 983, Bit15 (966~990) 25 978,
1220 01:01:51.603480
1221 01:01:51.603556 Write Rank0 MR14 =0x18
1222 01:01:51.603631
1223 01:01:51.603706 CH=0, VrefRange= 0, VrefLevel = 24
1224 01:01:51.603783 TX Bit0 (976~999) 24 987, Bit8 (961~987) 27 974,
1225 01:01:51.603859 TX Bit1 (975~998) 24 986, Bit9 (964~988) 25 976,
1226 01:01:51.603936 TX Bit2 (974~998) 25 986, Bit10 (967~991) 25 979,
1227 01:01:51.604013 TX Bit3 (967~992) 26 979, Bit11 (962~988) 27 975,
1228 01:01:51.604089 TX Bit4 (974~999) 26 986, Bit12 (963~989) 27 976,
1229 01:01:51.604166 TX Bit5 (969~993) 25 981, Bit13 (963~987) 25 975,
1230 01:01:51.604242 TX Bit6 (970~995) 26 982, Bit14 (963~989) 27 976,
1231 01:01:51.604319 TX Bit7 (971~996) 26 983, Bit15 (966~990) 25 978,
1232 01:01:51.604394
1233 01:01:51.604469 Write Rank0 MR14 =0x1a
1234 01:01:51.604544
1235 01:01:51.604619 CH=0, VrefRange= 0, VrefLevel = 26
1236 01:01:51.604695 TX Bit0 (976~999) 24 987, Bit8 (961~987) 27 974,
1237 01:01:51.604772 TX Bit1 (975~998) 24 986, Bit9 (964~988) 25 976,
1238 01:01:51.604849 TX Bit2 (974~998) 25 986, Bit10 (967~991) 25 979,
1239 01:01:51.604925 TX Bit3 (967~992) 26 979, Bit11 (962~988) 27 975,
1240 01:01:51.605001 TX Bit4 (974~999) 26 986, Bit12 (963~989) 27 976,
1241 01:01:51.605078 TX Bit5 (969~993) 25 981, Bit13 (963~987) 25 975,
1242 01:01:51.605154 TX Bit6 (970~995) 26 982, Bit14 (963~989) 27 976,
1243 01:01:51.605230 TX Bit7 (971~996) 26 983, Bit15 (966~990) 25 978,
1244 01:01:51.605305
1245 01:01:51.605381 Write Rank0 MR14 =0x1c
1246 01:01:51.605460
1247 01:01:51.605536 CH=0, VrefRange= 0, VrefLevel = 28
1248 01:01:51.605613 TX Bit0 (976~999) 24 987, Bit8 (961~987) 27 974,
1249 01:01:51.605689 TX Bit1 (975~998) 24 986, Bit9 (964~988) 25 976,
1250 01:01:51.605766 TX Bit2 (974~998) 25 986, Bit10 (967~991) 25 979,
1251 01:01:51.605843 TX Bit3 (967~992) 26 979, Bit11 (962~988) 27 975,
1252 01:01:51.605919 TX Bit4 (974~999) 26 986, Bit12 (963~989) 27 976,
1253 01:01:51.605996 TX Bit5 (969~993) 25 981, Bit13 (963~987) 25 975,
1254 01:01:51.606072 TX Bit6 (970~995) 26 982, Bit14 (963~989) 27 976,
1255 01:01:51.606149 TX Bit7 (971~996) 26 983, Bit15 (966~990) 25 978,
1256 01:01:51.606252
1257 01:01:51.606342
1258 01:01:51.606417 TX Vref found, early break! 378< 389
1259 01:01:51.606493 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
1260 01:01:51.606569 u1DelayCellOfst[0]=10 cells (8 PI)
1261 01:01:51.606646 u1DelayCellOfst[1]=9 cells (7 PI)
1262 01:01:51.606722 u1DelayCellOfst[2]=9 cells (7 PI)
1263 01:01:51.606798 u1DelayCellOfst[3]=0 cells (0 PI)
1264 01:01:51.606873 u1DelayCellOfst[4]=9 cells (7 PI)
1265 01:01:51.606949 u1DelayCellOfst[5]=2 cells (2 PI)
1266 01:01:51.607024 u1DelayCellOfst[6]=3 cells (3 PI)
1267 01:01:51.607100 u1DelayCellOfst[7]=5 cells (4 PI)
1268 01:01:51.607175 Byte0, DQ PI dly=979, DQM PI dly= 983
1269 01:01:51.607252 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1270 01:01:51.607327
1271 01:01:51.607403 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1272 01:01:51.607487
1273 01:01:51.607539 u1DelayCellOfst[8]=0 cells (0 PI)
1274 01:01:51.607588 u1DelayCellOfst[9]=2 cells (2 PI)
1275 01:01:51.607636 u1DelayCellOfst[10]=6 cells (5 PI)
1276 01:01:51.607684 u1DelayCellOfst[11]=1 cells (1 PI)
1277 01:01:51.607732 u1DelayCellOfst[12]=2 cells (2 PI)
1278 01:01:51.607780 u1DelayCellOfst[13]=1 cells (1 PI)
1279 01:01:51.607828 u1DelayCellOfst[14]=2 cells (2 PI)
1280 01:01:51.607875 u1DelayCellOfst[15]=5 cells (4 PI)
1281 01:01:51.607923 Byte1, DQ PI dly=974, DQM PI dly= 976
1282 01:01:51.607971 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 14)
1283 01:01:51.608019
1284 01:01:51.608066 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 14)
1285 01:01:51.608114
1286 01:01:51.608162 Write Rank0 MR14 =0x16
1287 01:01:51.608209
1288 01:01:51.608256 Final TX Range 0 Vref 22
1289 01:01:51.608304
1290 01:01:51.608351 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1291 01:01:51.608399
1292 01:01:51.608446 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1293 01:01:51.608494 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1294 01:01:51.608542 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1295 01:01:51.608590 Write Rank0 MR3 =0xb0
1296 01:01:51.608636 DramC Write-DBI on
1297 01:01:51.608683 ==
1298 01:01:51.608730 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1299 01:01:51.608778 fsp= 1, odt_onoff= 1, Byte mode= 0
1300 01:01:51.608825 ==
1301 01:01:51.608872 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1302 01:01:51.608919
1303 01:01:51.608966 Begin, DQ Scan Range 696~760
1304 01:01:51.609013
1305 01:01:51.609060
1306 01:01:51.609107 TX Vref Scan disable
1307 01:01:51.609156 696 |2 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1308 01:01:51.609206 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1309 01:01:51.609254 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1310 01:01:51.609302 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1311 01:01:51.609350 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1312 01:01:51.609398 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1313 01:01:51.609467 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1314 01:01:51.609548 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1315 01:01:51.609600 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1316 01:01:51.609649 705 |2 6 1|[0] xxxxxxxx oooooooo [MSB]
1317 01:01:51.609698 706 |2 6 2|[0] xxxxxxxx oooooooo [MSB]
1318 01:01:51.609747 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB]
1319 01:01:51.609795 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
1320 01:01:51.609844 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
1321 01:01:51.610088 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1322 01:01:51.610172 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1323 01:01:51.610283 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1324 01:01:51.610334 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1325 01:01:51.610383 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB]
1326 01:01:51.610432 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1327 01:01:51.610481 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1328 01:01:51.610529 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1329 01:01:51.610577 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1330 01:01:51.610625 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1331 01:01:51.610673 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1332 01:01:51.610722 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1333 01:01:51.610771 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1334 01:01:51.610831 743 |2 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1335 01:01:51.610881 Byte0, DQ PI dly=728, DQM PI dly= 728
1336 01:01:51.610929 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
1337 01:01:51.610976
1338 01:01:51.611023 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
1339 01:01:51.611070
1340 01:01:51.611117 Byte1, DQ PI dly=719, DQM PI dly= 719
1341 01:01:51.611164 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 15)
1342 01:01:51.611212
1343 01:01:51.611258 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 15)
1344 01:01:51.611304
1345 01:01:51.611352 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1346 01:01:51.611400 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1347 01:01:51.611448 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1348 01:01:51.611495 Write Rank0 MR3 =0x30
1349 01:01:51.611543 DramC Write-DBI off
1350 01:01:51.611590
1351 01:01:51.611635 [DATLAT]
1352 01:01:51.611682 Freq=1600, CH0 RK0, use_rxtx_scan=0
1353 01:01:51.611729
1354 01:01:51.611775 DATLAT Default: 0xf
1355 01:01:51.611822 7, 0xFFFF, sum=0
1356 01:01:51.611869 8, 0xFFFF, sum=0
1357 01:01:51.611916 9, 0xFFFF, sum=0
1358 01:01:51.611964 10, 0xFFFF, sum=0
1359 01:01:51.612012 11, 0xFFFF, sum=0
1360 01:01:51.612060 12, 0xFFFF, sum=0
1361 01:01:51.612107 13, 0xFFFF, sum=0
1362 01:01:51.612155 14, 0x0, sum=1
1363 01:01:51.612203 15, 0x0, sum=2
1364 01:01:51.612250 16, 0x0, sum=3
1365 01:01:51.612298 17, 0x0, sum=4
1366 01:01:51.612347 pattern=2 first_step=14 total pass=5 best_step=16
1367 01:01:51.612394 ==
1368 01:01:51.612441 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1369 01:01:51.612489 fsp= 1, odt_onoff= 1, Byte mode= 0
1370 01:01:51.612536 ==
1371 01:01:51.612583 Start DQ dly to find pass range UseTestEngine =1
1372 01:01:51.612630 x-axis: bit #, y-axis: DQ dly (-127~63)
1373 01:01:51.612678 RX Vref Scan = 1
1374 01:01:51.612725
1375 01:01:51.612772 RX Vref found, early break!
1376 01:01:51.612820
1377 01:01:51.612866 Final RX Vref 13, apply to both rank0 and 1
1378 01:01:51.612913 ==
1379 01:01:51.612961 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1380 01:01:51.613008 fsp= 1, odt_onoff= 1, Byte mode= 0
1381 01:01:51.613055 ==
1382 01:01:51.613102 DQS Delay:
1383 01:01:51.613149 DQS0 = 0, DQS1 = 0
1384 01:01:51.613201 DQM Delay:
1385 01:01:51.613249 DQM0 = 19, DQM1 = 18
1386 01:01:51.613297 DQ Delay:
1387 01:01:51.613344 DQ0 =24, DQ1 =23, DQ2 =23, DQ3 =13
1388 01:01:51.613391 DQ4 =22, DQ5 =15, DQ6 =17, DQ7 =18
1389 01:01:51.613438 DQ8 =17, DQ9 =19, DQ10 =22, DQ11 =17
1390 01:01:51.613485 DQ12 =19, DQ13 =16, DQ14 =17, DQ15 =19
1391 01:01:51.613532
1392 01:01:51.613578
1393 01:01:51.613624
1394 01:01:51.613670 [DramC_TX_OE_Calibration] TA2
1395 01:01:51.613717 Original DQ_B0 (3 6) =30, OEN = 27
1396 01:01:51.613765 Original DQ_B1 (3 6) =30, OEN = 27
1397 01:01:51.613812 23, 0x0, End_B0=23 End_B1=23
1398 01:01:51.613860 24, 0x0, End_B0=24 End_B1=24
1399 01:01:51.613908 25, 0x0, End_B0=25 End_B1=25
1400 01:01:51.613958 26, 0x0, End_B0=26 End_B1=26
1401 01:01:51.614021 27, 0x0, End_B0=27 End_B1=27
1402 01:01:51.614070 28, 0x0, End_B0=28 End_B1=28
1403 01:01:51.614119 29, 0x0, End_B0=29 End_B1=29
1404 01:01:51.614166 30, 0x0, End_B0=30 End_B1=30
1405 01:01:51.614221 31, 0xFFFF, End_B0=30 End_B1=30
1406 01:01:51.614304 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1407 01:01:51.614352 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1408 01:01:51.614399
1409 01:01:51.614448
1410 01:01:51.614495 Write Rank0 MR23 =0x3f
1411 01:01:51.614542 [DQSOSC]
1412 01:01:51.614589 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d, (MSB)MR19= 0x3, tDQSOscB0 = 340 ps tDQSOscB1 = 0 ps
1413 01:01:51.614637 CH0_RK0: MR19=0x3, MR18=0x9D, DQSOSC=340, MR23=63, INC=21, DEC=31
1414 01:01:51.614685 Write Rank0 MR23 =0x3f
1415 01:01:51.614733 [DQSOSC]
1416 01:01:51.614780 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d, (MSB)MR19= 0x3, tDQSOscB0 = 340 ps tDQSOscB1 = 0 ps
1417 01:01:51.614828 CH0 RK0: MR19=3, MR18=9D
1418 01:01:51.614875 [RankSwap] Rank num 2, (Multi 1), Rank 1
1419 01:01:51.614922 Write Rank0 MR2 =0xad
1420 01:01:51.614969 [Write Leveling]
1421 01:01:51.615016 delay byte0 byte1 byte2 byte3
1422 01:01:51.615062
1423 01:01:51.615109 10 0 0
1424 01:01:51.615157 11 0 0
1425 01:01:51.615205 12 0 0
1426 01:01:51.615254 13 0 0
1427 01:01:51.615302 14 0 0
1428 01:01:51.615350 15 0 0
1429 01:01:51.615399 16 0 0
1430 01:01:51.615446 17 0 0
1431 01:01:51.615494 18 0 0
1432 01:01:51.615542 19 0 0
1433 01:01:51.615589 20 0 0
1434 01:01:51.615636 21 0 0
1435 01:01:51.615683 22 0 0
1436 01:01:51.615730 23 0 0
1437 01:01:51.615778 24 0 0
1438 01:01:51.615825 25 0 0
1439 01:01:51.615872 26 0 0
1440 01:01:51.615919 27 0 0
1441 01:01:51.615966 28 0 0
1442 01:01:51.616012 29 0 0
1443 01:01:51.616060 30 0 ff
1444 01:01:51.616107 31 0 ff
1445 01:01:51.616155 32 0 ff
1446 01:01:51.616202 33 0 ff
1447 01:01:51.616249 34 ff ff
1448 01:01:51.616306 35 ff ff
1449 01:01:51.616356 36 ff ff
1450 01:01:51.616404 37 ff ff
1451 01:01:51.616452 38 ff ff
1452 01:01:51.616499 39 ff ff
1453 01:01:51.616546 40 ff ff
1454 01:01:51.616594 pass bytecount = 0xff (0xff: all bytes pass)
1455 01:01:51.616641
1456 01:01:51.616687 DQS0 dly: 34
1457 01:01:51.616735 DQS1 dly: 30
1458 01:01:51.616782 Write Rank0 MR2 =0x2d
1459 01:01:51.616837 [RankSwap] Rank num 2, (Multi 1), Rank 0
1460 01:01:51.616886 Write Rank1 MR1 =0xd6
1461 01:01:51.616933 [Gating]
1462 01:01:51.616979 ==
1463 01:01:51.617026 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1464 01:01:51.617074 fsp= 1, odt_onoff= 1, Byte mode= 0
1465 01:01:51.617120 ==
1466 01:01:51.617167 3 1 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1467 01:01:51.617216 3 1 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1468 01:01:51.617264 3 1 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1469 01:01:51.617313 3 1 12 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1470 01:01:51.617361 3 1 16 |3534 3535 |(11 11)(11 11) |(0 0)(0 1)| 0
1471 01:01:51.617600 3 1 20 |3534 2e2d |(11 11)(11 11) |(0 0)(0 1)| 0
1472 01:01:51.617670 3 1 24 |3534 2626 |(11 11)(11 11) |(0 0)(0 1)| 0
1473 01:01:51.617768 3 1 28 |3534 2828 |(11 11)(11 11) |(0 0)(1 0)| 0
1474 01:01:51.617865 3 2 0 |3534 1413 |(11 11)(11 11) |(0 1)(0 1)| 0
1475 01:01:51.617962 3 2 4 |3534 3434 |(11 11)(0 0) |(0 1)(0 1)| 0
1476 01:01:51.618059 3 2 8 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1477 01:01:51.618156 3 2 12 |3d3d 504 |(11 11)(11 11) |(1 1)(1 1)| 0
1478 01:01:51.618293 3 2 16 |3d3d 3c3c |(11 11)(11 11) |(1 1)(1 1)| 0
1479 01:01:51.618391 3 2 20 |3d3d 3d3d |(11 11)(0 0) |(1 1)(1 1)| 0
1480 01:01:51.618489 3 2 24 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
1481 01:01:51.618570 3 2 28 |3d3d 3d3d |(11 11)(0 0) |(1 1)(1 1)| 0
1482 01:01:51.618648 3 3 0 |3d3d 3c3b |(11 11)(11 11) |(1 1)(1 1)| 0
1483 01:01:51.618725 3 3 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1484 01:01:51.618802 3 3 8 |3d3d 3c3c |(11 11)(11 11) |(1 1)(1 1)| 0
1485 01:01:51.618879 3 3 12 |3d3d 1211 |(11 11)(11 11) |(1 1)(1 1)| 0
1486 01:01:51.618956 3 3 16 |1413 b0a |(11 11)(11 11) |(1 1)(1 1)| 0
1487 01:01:51.619034 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1488 01:01:51.619111 [Byte 0] Lead/lag Transition tap number (1)
1489 01:01:51.619187 [Byte 1] Lead/lag falling Transition (3, 3, 20)
1490 01:01:51.619262 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1491 01:01:51.619339 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1492 01:01:51.619416 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1493 01:01:51.619493 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1494 01:01:51.619571 3 4 8 |403 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1495 01:01:51.619648 3 4 12 |1211 201 |(11 11)(11 11) |(1 1)(1 1)| 0
1496 01:01:51.619726 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1497 01:01:51.619803 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1498 01:01:51.619881 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1499 01:01:51.619961 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1500 01:01:51.620039 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1501 01:01:51.620116 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1502 01:01:51.620193 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1503 01:01:51.620270 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1504 01:01:51.620352 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1505 01:01:51.620431 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1506 01:01:51.620508 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1507 01:01:51.620586 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1508 01:01:51.620663 [Byte 0] Lead/lag falling Transition (3, 5, 28)
1509 01:01:51.620739 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1510 01:01:51.620816 [Byte 1] Lead/lag falling Transition (3, 6, 0)
1511 01:01:51.620891 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1512 01:01:51.620969 3 6 8 |202 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1513 01:01:51.621047 [Byte 0] Lead/lag Transition tap number (4)
1514 01:01:51.621123 [Byte 1] Lead/lag Transition tap number (3)
1515 01:01:51.621198 3 6 12 |4646 3a3a |(10 10)(11 11) |(0 0)(0 0)| 0
1516 01:01:51.621275 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1517 01:01:51.621352 [Byte 0]First pass (3, 6, 16)
1518 01:01:51.621427 [Byte 1]First pass (3, 6, 16)
1519 01:01:51.621502 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1520 01:01:51.621579 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1521 01:01:51.621657 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1522 01:01:51.621734 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1523 01:01:51.621811 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1524 01:01:51.621888 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1525 01:01:51.621965 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1526 01:01:51.622042 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1527 01:01:51.622119 All bytes gating window > 1UI, Early break!
1528 01:01:51.622194
1529 01:01:51.622292 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 4)
1530 01:01:51.622341
1531 01:01:51.622388 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 6)
1532 01:01:51.622435
1533 01:01:51.622481
1534 01:01:51.622528
1535 01:01:51.622575 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1536 01:01:51.622624
1537 01:01:51.622671 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
1538 01:01:51.622717
1539 01:01:51.622763
1540 01:01:51.622809 Write Rank1 MR1 =0x56
1541 01:01:51.622857
1542 01:01:51.622903 best RODT dly(2T, 0.5T) = (2, 3)
1543 01:01:51.622950
1544 01:01:51.622996 best RODT dly(2T, 0.5T) = (2, 3)
1545 01:01:51.623043 ==
1546 01:01:51.623090 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1547 01:01:51.623138 fsp= 1, odt_onoff= 1, Byte mode= 0
1548 01:01:51.623185 ==
1549 01:01:51.623231 Start DQ dly to find pass range UseTestEngine =0
1550 01:01:51.623279 x-axis: bit #, y-axis: DQ dly (-127~63)
1551 01:01:51.623326 RX Vref Scan = 0
1552 01:01:51.623373 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1553 01:01:51.623422 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1554 01:01:51.623475 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1555 01:01:51.623523 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1556 01:01:51.623570 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1557 01:01:51.623617 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1558 01:01:51.623664 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1559 01:01:51.623713 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1560 01:01:51.623760 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1561 01:01:51.623808 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1562 01:01:51.623856 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1563 01:01:51.623903 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1564 01:01:51.623952 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1565 01:01:51.624000 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1566 01:01:51.624048 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1567 01:01:51.624096 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1568 01:01:51.624143 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1569 01:01:51.624191 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1570 01:01:51.624240 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1571 01:01:51.624288 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1572 01:01:51.624336 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1573 01:01:51.624384 -5, [0] xxxoxxxx xxxxxxxx [MSB]
1574 01:01:51.624433 -4, [0] xxxoxxxx xxxxxxxx [MSB]
1575 01:01:51.624480 -3, [0] xxxoxxxx xxxxxxxx [MSB]
1576 01:01:51.624527 -2, [0] xxxoxoxx xxxxxxxx [MSB]
1577 01:01:51.624575 -1, [0] xxxoxooo oxxxxxxx [MSB]
1578 01:01:51.624812 0, [0] xxxoxooo oxxoxxox [MSB]
1579 01:01:51.624875 1, [0] xxxoxooo ooxoooox [MSB]
1580 01:01:51.624926 2, [0] xxxoxooo ooxooooo [MSB]
1581 01:01:51.624975 3, [0] xxxoxooo ooxooooo [MSB]
1582 01:01:51.625023 4, [0] xxxoxooo ooxooooo [MSB]
1583 01:01:51.625072 5, [0] xooooooo oooooooo [MSB]
1584 01:01:51.625119 32, [0] oooxoooo oooooooo [MSB]
1585 01:01:51.625168 33, [0] oooxoooo oooooooo [MSB]
1586 01:01:51.625216 34, [0] oooxoxoo oooooooo [MSB]
1587 01:01:51.625264 35, [0] oooxoxoo oooxooxo [MSB]
1588 01:01:51.625312 36, [0] oooxoxxx xooxooxo [MSB]
1589 01:01:51.625360 37, [0] oooxoxxx xooxoxxo [MSB]
1590 01:01:51.625408 38, [0] oooxoxxx xxoxoxxo [MSB]
1591 01:01:51.625455 39, [0] oooxoxxx xxoxxxxo [MSB]
1592 01:01:51.625503 40, [0] oxoxxxxx xxoxxxxx [MSB]
1593 01:01:51.625550 41, [0] oxxxxxxx xxoxxxxx [MSB]
1594 01:01:51.625598 42, [0] xxxxxxxx xxoxxxxx [MSB]
1595 01:01:51.625645 43, [0] xxxxxxxx xxxxxxxx [MSB]
1596 01:01:51.625693 iDelay=43, Bit 0, Center 23 (6 ~ 41) 36
1597 01:01:51.625742 iDelay=43, Bit 1, Center 22 (5 ~ 39) 35
1598 01:01:51.625789 iDelay=43, Bit 2, Center 22 (5 ~ 40) 36
1599 01:01:51.625835 iDelay=43, Bit 3, Center 13 (-5 ~ 31) 37
1600 01:01:51.625883 iDelay=43, Bit 4, Center 22 (5 ~ 39) 35
1601 01:01:51.625931 iDelay=43, Bit 5, Center 15 (-2 ~ 33) 36
1602 01:01:51.625979 iDelay=43, Bit 6, Center 17 (-1 ~ 35) 37
1603 01:01:51.626026 iDelay=43, Bit 7, Center 17 (-1 ~ 35) 37
1604 01:01:51.626074 iDelay=43, Bit 8, Center 17 (-1 ~ 35) 37
1605 01:01:51.626121 iDelay=43, Bit 9, Center 19 (1 ~ 37) 37
1606 01:01:51.626167 iDelay=43, Bit 10, Center 23 (5 ~ 42) 38
1607 01:01:51.626222 iDelay=43, Bit 11, Center 17 (0 ~ 34) 35
1608 01:01:51.626306 iDelay=43, Bit 12, Center 19 (1 ~ 38) 38
1609 01:01:51.626353 iDelay=43, Bit 13, Center 18 (1 ~ 36) 36
1610 01:01:51.626401 iDelay=43, Bit 14, Center 17 (0 ~ 34) 35
1611 01:01:51.626448 iDelay=43, Bit 15, Center 20 (2 ~ 39) 38
1612 01:01:51.626495 ==
1613 01:01:51.626543 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1614 01:01:51.626591 fsp= 1, odt_onoff= 1, Byte mode= 0
1615 01:01:51.626639 ==
1616 01:01:51.626686 DQS Delay:
1617 01:01:51.626733 DQS0 = 0, DQS1 = 0
1618 01:01:51.626781 DQM Delay:
1619 01:01:51.626828 DQM0 = 18, DQM1 = 18
1620 01:01:51.626879 DQ Delay:
1621 01:01:51.626927 DQ0 =23, DQ1 =22, DQ2 =22, DQ3 =13
1622 01:01:51.626978 DQ4 =22, DQ5 =15, DQ6 =17, DQ7 =17
1623 01:01:51.627026 DQ8 =17, DQ9 =19, DQ10 =23, DQ11 =17
1624 01:01:51.627074 DQ12 =19, DQ13 =18, DQ14 =17, DQ15 =20
1625 01:01:51.627121
1626 01:01:51.627167
1627 01:01:51.627214 DramC Write-DBI off
1628 01:01:51.627261 ==
1629 01:01:51.627308 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1630 01:01:51.627356 fsp= 1, odt_onoff= 1, Byte mode= 0
1631 01:01:51.627403 ==
1632 01:01:51.627450 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1633 01:01:51.627497
1634 01:01:51.627544 Begin, DQ Scan Range 926~1182
1635 01:01:51.627591
1636 01:01:51.627638
1637 01:01:51.627684 TX Vref Scan disable
1638 01:01:51.627731 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1639 01:01:51.627781 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1640 01:01:51.627829 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1641 01:01:51.627878 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1642 01:01:51.627926 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1643 01:01:51.627974 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1644 01:01:51.628021 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1645 01:01:51.628069 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1646 01:01:51.628117 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1647 01:01:51.628165 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1648 01:01:51.628213 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1649 01:01:51.628262 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1650 01:01:51.628311 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1651 01:01:51.628359 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1652 01:01:51.628406 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1653 01:01:51.628454 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1654 01:01:51.628502 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1655 01:01:51.628550 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1656 01:01:51.628598 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1657 01:01:51.628646 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1658 01:01:51.628695 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1659 01:01:51.628742 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1660 01:01:51.628790 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1661 01:01:51.628838 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1662 01:01:51.628885 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1663 01:01:51.628933 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1664 01:01:51.628981 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1665 01:01:51.629028 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1666 01:01:51.629076 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1667 01:01:51.629125 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1668 01:01:51.629172 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1669 01:01:51.629219 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1670 01:01:51.629268 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1671 01:01:51.629315 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1672 01:01:51.629362 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1673 01:01:51.629411 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1674 01:01:51.629459 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1675 01:01:51.629506 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1676 01:01:51.629554 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1677 01:01:51.629602 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1678 01:01:51.629650 966 |3 6 6|[0] xxxxxxxx oxxxxxxx [MSB]
1679 01:01:51.629698 967 |3 6 7|[0] xxxxxxxx ooxooxox [MSB]
1680 01:01:51.629745 968 |3 6 8|[0] xxxxxxxx ooxooooo [MSB]
1681 01:01:51.629794 969 |3 6 9|[0] xxxxxxxx ooxooooo [MSB]
1682 01:01:51.629842 970 |3 6 10|[0] xxxxxxxx ooxooooo [MSB]
1683 01:01:51.629891 971 |3 6 11|[0] xxxxxxxx ooxooooo [MSB]
1684 01:01:51.629938 972 |3 6 12|[0] xxxoxoox oooooooo [MSB]
1685 01:01:51.629987 973 |3 6 13|[0] xxxoxoox oooooooo [MSB]
1686 01:01:51.630036 974 |3 6 14|[0] xxxoxoox oooooooo [MSB]
1687 01:01:51.630083 975 |3 6 15|[0] xxxoxoox oooooooo [MSB]
1688 01:01:51.630131 976 |3 6 16|[0] xooooooo oooooooo [MSB]
1689 01:01:51.630180 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1690 01:01:51.630235 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1691 01:01:51.630287 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1692 01:01:51.630337 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1693 01:01:51.630577 994 |3 6 34|[0] oooxoxoo xxxxxxxx [MSB]
1694 01:01:51.630634 995 |3 6 35|[0] oooxoxoo xxxxxxxx [MSB]
1695 01:01:51.630684 996 |3 6 36|[0] oooxoxxo xxxxxxxx [MSB]
1696 01:01:51.630733 997 |3 6 37|[0] xxoxxxxx xxxxxxxx [MSB]
1697 01:01:51.630782 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1698 01:01:51.630829 Byte0, DQ PI dly=984, DQM PI dly= 984
1699 01:01:51.630877 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
1700 01:01:51.630924
1701 01:01:51.630972 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
1702 01:01:51.631020
1703 01:01:51.631067 Byte1, DQ PI dly=978, DQM PI dly= 978
1704 01:01:51.631115 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1705 01:01:51.631162
1706 01:01:51.631209 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1707 01:01:51.631254
1708 01:01:51.631299 ==
1709 01:01:51.631347 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1710 01:01:51.631394 fsp= 1, odt_onoff= 1, Byte mode= 0
1711 01:01:51.631442 ==
1712 01:01:51.631489 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1713 01:01:51.631535
1714 01:01:51.631582 Begin, DQ Scan Range 954~1018
1715 01:01:51.631629 Write Rank1 MR14 =0x0
1716 01:01:51.631676
1717 01:01:51.631722 CH=0, VrefRange= 0, VrefLevel = 0
1718 01:01:51.631769 TX Bit0 (978~997) 20 987, Bit8 (968~986) 19 977,
1719 01:01:51.631819 TX Bit1 (977~995) 19 986, Bit9 (969~988) 20 978,
1720 01:01:51.631906 TX Bit2 (978~996) 19 987, Bit10 (974~991) 18 982,
1721 01:01:51.631954 TX Bit3 (973~989) 17 981, Bit11 (968~987) 20 977,
1722 01:01:51.632002 TX Bit4 (977~996) 20 986, Bit12 (971~988) 18 979,
1723 01:01:51.632050 TX Bit5 (975~990) 16 982, Bit13 (970~986) 17 978,
1724 01:01:51.632097 TX Bit6 (975~991) 17 983, Bit14 (969~987) 19 978,
1725 01:01:51.632144 TX Bit7 (977~992) 16 984, Bit15 (972~990) 19 981,
1726 01:01:51.632191
1727 01:01:51.632238 Write Rank1 MR14 =0x2
1728 01:01:51.632285
1729 01:01:51.632332 CH=0, VrefRange= 0, VrefLevel = 2
1730 01:01:51.632378 TX Bit0 (978~998) 21 988, Bit8 (967~987) 21 977,
1731 01:01:51.632426 TX Bit1 (977~995) 19 986, Bit9 (968~989) 22 978,
1732 01:01:51.632474 TX Bit2 (977~997) 21 987, Bit10 (974~991) 18 982,
1733 01:01:51.632521 TX Bit3 (973~990) 18 981, Bit11 (968~988) 21 978,
1734 01:01:51.632568 TX Bit4 (977~997) 21 987, Bit12 (969~989) 21 979,
1735 01:01:51.632615 TX Bit5 (975~990) 16 982, Bit13 (969~986) 18 977,
1736 01:01:51.632662 TX Bit6 (975~991) 17 983, Bit14 (969~988) 20 978,
1737 01:01:51.632709 TX Bit7 (977~992) 16 984, Bit15 (972~990) 19 981,
1738 01:01:51.632756
1739 01:01:51.632802 Write Rank1 MR14 =0x4
1740 01:01:51.632848
1741 01:01:51.632895 CH=0, VrefRange= 0, VrefLevel = 4
1742 01:01:51.632942 TX Bit0 (978~998) 21 988, Bit8 (967~987) 21 977,
1743 01:01:51.632988 TX Bit1 (977~996) 20 986, Bit9 (968~989) 22 978,
1744 01:01:51.633035 TX Bit2 (977~997) 21 987, Bit10 (974~991) 18 982,
1745 01:01:51.633083 TX Bit3 (973~990) 18 981, Bit11 (968~988) 21 978,
1746 01:01:51.633130 TX Bit4 (977~997) 21 987, Bit12 (969~989) 21 979,
1747 01:01:51.633177 TX Bit5 (974~990) 17 982, Bit13 (969~987) 19 978,
1748 01:01:51.633224 TX Bit6 (975~992) 18 983, Bit14 (969~989) 21 979,
1749 01:01:51.633271 TX Bit7 (977~993) 17 985, Bit15 (972~991) 20 981,
1750 01:01:51.633318
1751 01:01:51.633365 Write Rank1 MR14 =0x6
1752 01:01:51.633410
1753 01:01:51.633457 CH=0, VrefRange= 0, VrefLevel = 6
1754 01:01:51.633503 TX Bit0 (977~998) 22 987, Bit8 (967~988) 22 977,
1755 01:01:51.633550 TX Bit1 (977~996) 20 986, Bit9 (969~989) 21 979,
1756 01:01:51.633598 TX Bit2 (977~997) 21 987, Bit10 (973~991) 19 982,
1757 01:01:51.633649 TX Bit3 (973~990) 18 981, Bit11 (968~989) 22 978,
1758 01:01:51.633699 TX Bit4 (977~997) 21 987, Bit12 (968~989) 22 978,
1759 01:01:51.633748 TX Bit5 (974~991) 18 982, Bit13 (968~987) 20 977,
1760 01:01:51.633795 TX Bit6 (974~992) 19 983, Bit14 (968~989) 22 978,
1761 01:01:51.633842 TX Bit7 (977~994) 18 985, Bit15 (972~991) 20 981,
1762 01:01:51.633889
1763 01:01:51.633935 wait MRW command Rank1 MR14 =0x8 fired (1)
1764 01:01:51.633982 Write Rank1 MR14 =0x8
1765 01:01:51.634029
1766 01:01:51.634076 CH=0, VrefRange= 0, VrefLevel = 8
1767 01:01:51.634123 TX Bit0 (977~998) 22 987, Bit8 (967~989) 23 978,
1768 01:01:51.634170 TX Bit1 (977~997) 21 987, Bit9 (968~990) 23 979,
1769 01:01:51.634225 TX Bit2 (977~998) 22 987, Bit10 (974~992) 19 983,
1770 01:01:51.634275 TX Bit3 (972~990) 19 981, Bit11 (967~989) 23 978,
1771 01:01:51.634322 TX Bit4 (976~998) 23 987, Bit12 (969~990) 22 979,
1772 01:01:51.634370 TX Bit5 (973~991) 19 982, Bit13 (968~988) 21 978,
1773 01:01:51.634417 TX Bit6 (974~992) 19 983, Bit14 (968~989) 22 978,
1774 01:01:51.634464 TX Bit7 (976~994) 19 985, Bit15 (971~991) 21 981,
1775 01:01:51.634511
1776 01:01:51.634557 Write Rank1 MR14 =0xa
1777 01:01:51.634605
1778 01:01:51.634652 CH=0, VrefRange= 0, VrefLevel = 10
1779 01:01:51.634700 TX Bit0 (977~999) 23 988, Bit8 (967~989) 23 978,
1780 01:01:51.634747 TX Bit1 (977~997) 21 987, Bit9 (968~990) 23 979,
1781 01:01:51.634795 TX Bit2 (977~998) 22 987, Bit10 (973~992) 20 982,
1782 01:01:51.634842 TX Bit3 (971~991) 21 981, Bit11 (968~989) 22 978,
1783 01:01:51.634889 TX Bit4 (976~998) 23 987, Bit12 (968~990) 23 979,
1784 01:01:51.634937 TX Bit5 (973~992) 20 982, Bit13 (968~989) 22 978,
1785 01:01:51.634983 TX Bit6 (973~993) 21 983, Bit14 (968~990) 23 979,
1786 01:01:51.635030 TX Bit7 (976~995) 20 985, Bit15 (970~991) 22 980,
1787 01:01:51.635078
1788 01:01:51.635124 Write Rank1 MR14 =0xc
1789 01:01:51.635171
1790 01:01:51.635217 CH=0, VrefRange= 0, VrefLevel = 12
1791 01:01:51.635264 TX Bit0 (977~999) 23 988, Bit8 (966~989) 24 977,
1792 01:01:51.635311 TX Bit1 (977~998) 22 987, Bit9 (968~990) 23 979,
1793 01:01:51.635358 TX Bit2 (977~998) 22 987, Bit10 (973~992) 20 982,
1794 01:01:51.635405 TX Bit3 (971~991) 21 981, Bit11 (967~990) 24 978,
1795 01:01:51.635452 TX Bit4 (976~998) 23 987, Bit12 (968~990) 23 979,
1796 01:01:51.635500 TX Bit5 (972~992) 21 982, Bit13 (968~989) 22 978,
1797 01:01:51.635548 TX Bit6 (973~993) 21 983, Bit14 (968~990) 23 979,
1798 01:01:51.635595 TX Bit7 (976~995) 20 985, Bit15 (969~992) 24 980,
1799 01:01:51.635641
1800 01:01:51.635877 Write Rank1 MR14 =0xe
1801 01:01:51.635930
1802 01:01:51.635978 CH=0, VrefRange= 0, VrefLevel = 14
1803 01:01:51.636026 TX Bit0 (977~1000) 24 988, Bit8 (966~989) 24 977,
1804 01:01:51.636074 TX Bit1 (976~998) 23 987, Bit9 (967~990) 24 978,
1805 01:01:51.636122 TX Bit2 (976~998) 23 987, Bit10 (973~992) 20 982,
1806 01:01:51.636170 TX Bit3 (971~992) 22 981, Bit11 (967~990) 24 978,
1807 01:01:51.636217 TX Bit4 (976~999) 24 987, Bit12 (968~990) 23 979,
1808 01:01:51.636264 TX Bit5 (972~992) 21 982, Bit13 (968~989) 22 978,
1809 01:01:51.636311 TX Bit6 (973~994) 22 983, Bit14 (968~990) 23 979,
1810 01:01:51.636358 TX Bit7 (976~996) 21 986, Bit15 (969~992) 24 980,
1811 01:01:51.636405
1812 01:01:51.636452 Write Rank1 MR14 =0x10
1813 01:01:51.636499
1814 01:01:51.636545 CH=0, VrefRange= 0, VrefLevel = 16
1815 01:01:51.636593 TX Bit0 (976~1000) 25 988, Bit8 (966~990) 25 978,
1816 01:01:51.636640 TX Bit1 (976~998) 23 987, Bit9 (967~990) 24 978,
1817 01:01:51.636688 TX Bit2 (977~999) 23 988, Bit10 (972~993) 22 982,
1818 01:01:51.636735 TX Bit3 (970~992) 23 981, Bit11 (967~990) 24 978,
1819 01:01:51.636782 TX Bit4 (976~999) 24 987, Bit12 (968~990) 23 979,
1820 01:01:51.636829 TX Bit5 (971~993) 23 982, Bit13 (967~989) 23 978,
1821 01:01:51.636877 TX Bit6 (972~995) 24 983, Bit14 (967~990) 24 978,
1822 01:01:51.636924 TX Bit7 (976~997) 22 986, Bit15 (969~992) 24 980,
1823 01:01:51.636973
1824 01:01:51.637023 Write Rank1 MR14 =0x12
1825 01:01:51.637074
1826 01:01:51.637122 CH=0, VrefRange= 0, VrefLevel = 18
1827 01:01:51.637168 TX Bit0 (976~1000) 25 988, Bit8 (966~990) 25 978,
1828 01:01:51.637216 TX Bit1 (976~998) 23 987, Bit9 (967~990) 24 978,
1829 01:01:51.637263 TX Bit2 (976~999) 24 987, Bit10 (972~993) 22 982,
1830 01:01:51.637311 TX Bit3 (970~992) 23 981, Bit11 (967~990) 24 978,
1831 01:01:51.637358 TX Bit4 (976~999) 24 987, Bit12 (968~991) 24 979,
1832 01:01:51.637406 TX Bit5 (971~994) 24 982, Bit13 (967~990) 24 978,
1833 01:01:51.637453 TX Bit6 (972~995) 24 983, Bit14 (967~991) 25 979,
1834 01:01:51.637500 TX Bit7 (975~997) 23 986, Bit15 (968~992) 25 980,
1835 01:01:51.637547
1836 01:01:51.637593 Write Rank1 MR14 =0x14
1837 01:01:51.637640
1838 01:01:51.637687 CH=0, VrefRange= 0, VrefLevel = 20
1839 01:01:51.637749 TX Bit0 (976~1001) 26 988, Bit8 (966~990) 25 978,
1840 01:01:51.637798 TX Bit1 (976~999) 24 987, Bit9 (967~991) 25 979,
1841 01:01:51.637846 TX Bit2 (976~999) 24 987, Bit10 (972~994) 23 983,
1842 01:01:51.637894 TX Bit3 (969~993) 25 981, Bit11 (966~990) 25 978,
1843 01:01:51.637941 TX Bit4 (975~1000) 26 987, Bit12 (967~991) 25 979,
1844 01:01:51.637988 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1845 01:01:51.638035 TX Bit6 (971~996) 26 983, Bit14 (967~991) 25 979,
1846 01:01:51.638083 TX Bit7 (975~997) 23 986, Bit15 (969~993) 25 981,
1847 01:01:51.638129
1848 01:01:51.638176 Write Rank1 MR14 =0x16
1849 01:01:51.638232
1850 01:01:51.638281 CH=0, VrefRange= 0, VrefLevel = 22
1851 01:01:51.638328 TX Bit0 (976~1001) 26 988, Bit8 (966~990) 25 978,
1852 01:01:51.638376 TX Bit1 (976~999) 24 987, Bit9 (967~991) 25 979,
1853 01:01:51.638424 TX Bit2 (976~999) 24 987, Bit10 (972~994) 23 983,
1854 01:01:51.638474 TX Bit3 (969~993) 25 981, Bit11 (966~990) 25 978,
1855 01:01:51.638522 TX Bit4 (975~1000) 26 987, Bit12 (967~991) 25 979,
1856 01:01:51.638569 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1857 01:01:51.638617 TX Bit6 (971~996) 26 983, Bit14 (967~991) 25 979,
1858 01:01:51.638665 TX Bit7 (975~997) 23 986, Bit15 (969~993) 25 981,
1859 01:01:51.638712
1860 01:01:51.638759 Write Rank1 MR14 =0x18
1861 01:01:51.638805
1862 01:01:51.638852 CH=0, VrefRange= 0, VrefLevel = 24
1863 01:01:51.638899 TX Bit0 (976~1001) 26 988, Bit8 (966~990) 25 978,
1864 01:01:51.638948 TX Bit1 (976~999) 24 987, Bit9 (967~991) 25 979,
1865 01:01:51.638996 TX Bit2 (976~999) 24 987, Bit10 (972~994) 23 983,
1866 01:01:51.639043 TX Bit3 (969~993) 25 981, Bit11 (966~990) 25 978,
1867 01:01:51.639091 TX Bit4 (975~1000) 26 987, Bit12 (967~991) 25 979,
1868 01:01:51.639139 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1869 01:01:51.639186 TX Bit6 (971~996) 26 983, Bit14 (967~991) 25 979,
1870 01:01:51.639233 TX Bit7 (975~997) 23 986, Bit15 (969~993) 25 981,
1871 01:01:51.639280
1872 01:01:51.639327 Write Rank1 MR14 =0x1a
1873 01:01:51.639373
1874 01:01:51.639419 CH=0, VrefRange= 0, VrefLevel = 26
1875 01:01:51.639466 TX Bit0 (976~1001) 26 988, Bit8 (966~990) 25 978,
1876 01:01:51.639514 TX Bit1 (976~999) 24 987, Bit9 (967~991) 25 979,
1877 01:01:51.639562 TX Bit2 (976~999) 24 987, Bit10 (972~994) 23 983,
1878 01:01:51.639609 TX Bit3 (969~993) 25 981, Bit11 (966~990) 25 978,
1879 01:01:51.639656 TX Bit4 (975~1000) 26 987, Bit12 (967~991) 25 979,
1880 01:01:51.639703 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1881 01:01:51.639751 TX Bit6 (971~996) 26 983, Bit14 (967~991) 25 979,
1882 01:01:51.639798 TX Bit7 (975~997) 23 986, Bit15 (969~993) 25 981,
1883 01:01:51.639845
1884 01:01:51.639891 Write Rank1 MR14 =0x1c
1885 01:01:51.639938
1886 01:01:51.639984 CH=0, VrefRange= 0, VrefLevel = 28
1887 01:01:51.640031 TX Bit0 (976~1001) 26 988, Bit8 (966~990) 25 978,
1888 01:01:51.640078 TX Bit1 (976~999) 24 987, Bit9 (967~991) 25 979,
1889 01:01:51.640125 TX Bit2 (976~999) 24 987, Bit10 (972~994) 23 983,
1890 01:01:51.640173 TX Bit3 (969~993) 25 981, Bit11 (966~990) 25 978,
1891 01:01:51.640220 TX Bit4 (975~1000) 26 987, Bit12 (967~991) 25 979,
1892 01:01:51.640267 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1893 01:01:51.640315 TX Bit6 (971~996) 26 983, Bit14 (967~991) 25 979,
1894 01:01:51.640369 TX Bit7 (975~997) 23 986, Bit15 (969~993) 25 981,
1895 01:01:51.640417
1896 01:01:51.640466 Write Rank1 MR14 =0x1e
1897 01:01:51.640515
1898 01:01:51.640562 CH=0, VrefRange= 0, VrefLevel = 30
1899 01:01:51.640610 TX Bit0 (976~1001) 26 988, Bit8 (966~990) 25 978,
1900 01:01:51.640657 TX Bit1 (976~999) 24 987, Bit9 (967~991) 25 979,
1901 01:01:51.640893 TX Bit2 (976~999) 24 987, Bit10 (972~994) 23 983,
1902 01:01:51.640947 TX Bit3 (969~993) 25 981, Bit11 (966~990) 25 978,
1903 01:01:51.640996 TX Bit4 (975~1000) 26 987, Bit12 (967~991) 25 979,
1904 01:01:51.782649 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1905 01:01:51.783095 TX Bit6 (971~996) 26 983, Bit14 (967~991) 25 979,
1906 01:01:51.783418 TX Bit7 (975~997) 23 986, Bit15 (969~993) 25 981,
1907 01:01:51.783702
1908 01:01:51.784004
1909 01:01:51.784330 TX Vref found, early break! 375< 376
1910 01:01:51.784614 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
1911 01:01:51.784880 u1DelayCellOfst[0]=9 cells (7 PI)
1912 01:01:51.785131 u1DelayCellOfst[1]=7 cells (6 PI)
1913 01:01:51.785378 u1DelayCellOfst[2]=7 cells (6 PI)
1914 01:01:51.785624 u1DelayCellOfst[3]=0 cells (0 PI)
1915 01:01:51.785871 u1DelayCellOfst[4]=7 cells (6 PI)
1916 01:01:51.786118 u1DelayCellOfst[5]=1 cells (1 PI)
1917 01:01:51.786426 u1DelayCellOfst[6]=2 cells (2 PI)
1918 01:01:51.786700 u1DelayCellOfst[7]=6 cells (5 PI)
1919 01:01:51.786952 Byte0, DQ PI dly=981, DQM PI dly= 984
1920 01:01:51.787287 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1921 01:01:51.787638
1922 01:01:51.787898 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1923 01:01:51.788151
1924 01:01:51.788396 u1DelayCellOfst[8]=0 cells (0 PI)
1925 01:01:51.788647 u1DelayCellOfst[9]=1 cells (1 PI)
1926 01:01:51.788894 u1DelayCellOfst[10]=6 cells (5 PI)
1927 01:01:51.789144 u1DelayCellOfst[11]=0 cells (0 PI)
1928 01:01:51.789390 u1DelayCellOfst[12]=1 cells (1 PI)
1929 01:01:51.789637 u1DelayCellOfst[13]=0 cells (0 PI)
1930 01:01:51.789881 u1DelayCellOfst[14]=1 cells (1 PI)
1931 01:01:51.790123 u1DelayCellOfst[15]=3 cells (3 PI)
1932 01:01:51.790406 Byte1, DQ PI dly=978, DQM PI dly= 980
1933 01:01:51.790660 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1934 01:01:51.790906
1935 01:01:51.791151 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1936 01:01:51.791397
1937 01:01:51.791636 Write Rank1 MR14 =0x14
1938 01:01:51.791879
1939 01:01:51.792119 Final TX Range 0 Vref 20
1940 01:01:51.792363
1941 01:01:51.792604 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1942 01:01:51.792848
1943 01:01:51.793087 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1944 01:01:51.793334 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1945 01:01:51.793580 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1946 01:01:51.793825 Write Rank1 MR3 =0xb0
1947 01:01:51.794072 DramC Write-DBI on
1948 01:01:51.794351 ==
1949 01:01:51.794603 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1950 01:01:51.794853 fsp= 1, odt_onoff= 1, Byte mode= 0
1951 01:01:51.795104 ==
1952 01:01:51.795349 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1953 01:01:51.795596
1954 01:01:51.795840 Begin, DQ Scan Range 700~764
1955 01:01:51.796086
1956 01:01:51.796326
1957 01:01:51.796567 TX Vref Scan disable
1958 01:01:51.796813 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1959 01:01:51.797065 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1960 01:01:51.797312 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1961 01:01:51.797562 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1962 01:01:51.797847 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1963 01:01:51.798380 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1964 01:01:51.798669 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1965 01:01:51.798925 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1966 01:01:51.799209 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1967 01:01:51.799476 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1968 01:01:51.799725 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1969 01:01:51.799974 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1970 01:01:51.800219 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1971 01:01:51.800465 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1972 01:01:51.800715 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1973 01:01:51.800963 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1974 01:01:51.801211 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1975 01:01:51.801462 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1976 01:01:51.801712 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1977 01:01:51.801962 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1978 01:01:51.802229 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1979 01:01:51.802503 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1980 01:01:51.802754 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1981 01:01:51.803003 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1982 01:01:51.803253 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1983 01:01:51.803501 743 |2 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1984 01:01:51.803748 Byte0, DQ PI dly=729, DQM PI dly= 729
1985 01:01:51.804004 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 25)
1986 01:01:51.804181
1987 01:01:51.804354 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 25)
1988 01:01:51.804528
1989 01:01:51.804701 Byte1, DQ PI dly=722, DQM PI dly= 722
1990 01:01:51.804873 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 18)
1991 01:01:51.805044
1992 01:01:51.805215 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 18)
1993 01:01:51.805389
1994 01:01:51.805562 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1995 01:01:51.805737 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1996 01:01:51.805912 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1997 01:01:51.806087 Write Rank1 MR3 =0x30
1998 01:01:51.806283 DramC Write-DBI off
1999 01:01:51.806458
2000 01:01:51.806626 [DATLAT]
2001 01:01:51.806796 Freq=1600, CH0 RK1, use_rxtx_scan=0
2002 01:01:51.806972
2003 01:01:51.807146 DATLAT Default: 0x10
2004 01:01:51.807318 7, 0xFFFF, sum=0
2005 01:01:51.807492 8, 0xFFFF, sum=0
2006 01:01:51.807666 9, 0xFFFF, sum=0
2007 01:01:51.807843 10, 0xFFFF, sum=0
2008 01:01:51.808018 11, 0xFFFF, sum=0
2009 01:01:51.808194 12, 0xFFFF, sum=0
2010 01:01:51.808370 13, 0xFFFF, sum=0
2011 01:01:51.808548 14, 0x0, sum=1
2012 01:01:51.808723 15, 0x0, sum=2
2013 01:01:51.808897 16, 0x0, sum=3
2014 01:01:51.809067 17, 0x0, sum=4
2015 01:01:51.809201 pattern=2 first_step=14 total pass=5 best_step=16
2016 01:01:51.809331 ==
2017 01:01:51.809465 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2018 01:01:51.809602 fsp= 1, odt_onoff= 1, Byte mode= 0
2019 01:01:51.809742 ==
2020 01:01:51.809873 Start DQ dly to find pass range UseTestEngine =1
2021 01:01:51.810006 x-axis: bit #, y-axis: DQ dly (-127~63)
2022 01:01:51.810139 RX Vref Scan = 0
2023 01:01:51.810379 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2024 01:01:51.810563 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2025 01:01:51.811013 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2026 01:01:51.811206 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2027 01:01:51.811351 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2028 01:01:51.811489 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2029 01:01:51.811642 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2030 01:01:51.811853 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2031 01:01:51.812048 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2032 01:01:51.812185 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2033 01:01:51.812321 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2034 01:01:51.812455 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2035 01:01:51.812591 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2036 01:01:51.812725 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2037 01:01:51.812860 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2038 01:01:51.812996 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2039 01:01:51.813184 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2040 01:01:51.813327 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2041 01:01:51.813461 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2042 01:01:51.813596 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2043 01:01:51.813730 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2044 01:01:51.813864 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2045 01:01:51.814014 -4, [0] xxxoxxxx xxxxxxxx [MSB]
2046 01:01:51.814125 -3, [0] xxxoxxxx xxxxxxxx [MSB]
2047 01:01:51.814261 -2, [0] xxxoxxxx xxxxxxxx [MSB]
2048 01:01:51.814388 -1, [0] xxxoxoxx xxxxxxxx [MSB]
2049 01:01:51.814498 0, [0] xxxoxoxx oxxoxxxx [MSB]
2050 01:01:51.814609 1, [0] xxxoxoxx oxxoxxox [MSB]
2051 01:01:51.814719 2, [0] xxxoxoox oxxoxoox [MSB]
2052 01:01:51.814827 3, [0] xxxoxooo ooxooooo [MSB]
2053 01:01:51.814935 4, [0] xxxoxooo ooxooooo [MSB]
2054 01:01:51.815043 5, [0] xoxoxooo ooxooooo [MSB]
2055 01:01:51.815151 6, [0] xoxoxooo oooooooo [MSB]
2056 01:01:51.815259 32, [0] oooxoooo oooooooo [MSB]
2057 01:01:51.815369 33, [0] oooxoooo oooooooo [MSB]
2058 01:01:51.815476 34, [0] oooxoxoo oooooxoo [MSB]
2059 01:01:51.815584 35, [0] oooxoxxx oooxoxxo [MSB]
2060 01:01:51.815693 36, [0] oooxoxxx xxoxoxxo [MSB]
2061 01:01:51.815799 37, [0] oooxoxxx xxoxxxxo [MSB]
2062 01:01:51.815906 38, [0] oooxoxxx xxoxxxxx [MSB]
2063 01:01:51.816014 39, [0] oooxoxxx xxoxxxxx [MSB]
2064 01:01:51.816121 40, [0] ooxxoxxx xxxxxxxx [MSB]
2065 01:01:51.816229 41, [0] oxxxxxxx xxxxxxxx [MSB]
2066 01:01:51.816338 42, [0] xxxxxxxx xxxxxxxx [MSB]
2067 01:01:51.816447 iDelay=42, Bit 0, Center 24 (7 ~ 41) 35
2068 01:01:51.816553 iDelay=42, Bit 1, Center 22 (5 ~ 40) 36
2069 01:01:51.816684 iDelay=42, Bit 2, Center 23 (7 ~ 39) 33
2070 01:01:51.816794 iDelay=42, Bit 3, Center 13 (-4 ~ 31) 36
2071 01:01:51.816901 iDelay=42, Bit 4, Center 23 (7 ~ 40) 34
2072 01:01:51.817006 iDelay=42, Bit 5, Center 16 (-1 ~ 33) 35
2073 01:01:51.817112 iDelay=42, Bit 6, Center 18 (2 ~ 34) 33
2074 01:01:51.817217 iDelay=42, Bit 7, Center 18 (3 ~ 34) 32
2075 01:01:51.817322 iDelay=42, Bit 8, Center 17 (0 ~ 35) 36
2076 01:01:51.817428 iDelay=42, Bit 9, Center 19 (3 ~ 35) 33
2077 01:01:51.817533 iDelay=42, Bit 10, Center 22 (6 ~ 39) 34
2078 01:01:51.817639 iDelay=42, Bit 11, Center 17 (0 ~ 34) 35
2079 01:01:51.817745 iDelay=42, Bit 12, Center 19 (3 ~ 36) 34
2080 01:01:51.817851 iDelay=42, Bit 13, Center 17 (2 ~ 33) 32
2081 01:01:51.817957 iDelay=42, Bit 14, Center 17 (1 ~ 34) 34
2082 01:01:51.818062 iDelay=42, Bit 15, Center 20 (3 ~ 37) 35
2083 01:01:51.818167 ==
2084 01:01:51.818294 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2085 01:01:51.818402 fsp= 1, odt_onoff= 1, Byte mode= 0
2086 01:01:51.818508 ==
2087 01:01:51.818616 DQS Delay:
2088 01:01:51.818721 DQS0 = 0, DQS1 = 0
2089 01:01:51.818827 DQM Delay:
2090 01:01:51.818932 DQM0 = 19, DQM1 = 18
2091 01:01:51.819039 DQ Delay:
2092 01:01:51.819127 DQ0 =24, DQ1 =22, DQ2 =23, DQ3 =13
2093 01:01:51.819216 DQ4 =23, DQ5 =16, DQ6 =18, DQ7 =18
2094 01:01:51.819303 DQ8 =17, DQ9 =19, DQ10 =22, DQ11 =17
2095 01:01:51.819390 DQ12 =19, DQ13 =17, DQ14 =17, DQ15 =20
2096 01:01:51.819479
2097 01:01:51.819567
2098 01:01:51.819655
2099 01:01:51.819742 [DramC_TX_OE_Calibration] TA2
2100 01:01:51.819831 Original DQ_B0 (3 6) =30, OEN = 27
2101 01:01:51.819922 Original DQ_B1 (3 6) =30, OEN = 27
2102 01:01:51.820012 23, 0x0, End_B0=23 End_B1=23
2103 01:01:51.820103 24, 0x0, End_B0=24 End_B1=24
2104 01:01:51.820193 25, 0x0, End_B0=25 End_B1=25
2105 01:01:51.820283 26, 0x0, End_B0=26 End_B1=26
2106 01:01:51.820373 27, 0x0, End_B0=27 End_B1=27
2107 01:01:51.820464 28, 0x0, End_B0=28 End_B1=28
2108 01:01:51.820555 29, 0x0, End_B0=29 End_B1=29
2109 01:01:51.820678 30, 0x0, End_B0=30 End_B1=30
2110 01:01:51.820772 31, 0xFFFF, End_B0=30 End_B1=30
2111 01:01:51.820863 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2112 01:01:51.820954 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2113 01:01:51.821044
2114 01:01:51.821133
2115 01:01:51.821220 Write Rank1 MR23 =0x3f
2116 01:01:51.821309 [DQSOSC]
2117 01:01:51.821397 [DQSOSCAuto] RK1, (LSB)MR18= 0x8f, (MSB)MR19= 0x3, tDQSOscB0 = 345 ps tDQSOscB1 = 0 ps
2118 01:01:51.821488 CH0_RK1: MR19=0x3, MR18=0x8F, DQSOSC=345, MR23=63, INC=20, DEC=31
2119 01:01:51.821577 Write Rank1 MR23 =0x3f
2120 01:01:51.821664 [DQSOSC]
2121 01:01:51.821753 [DQSOSCAuto] RK1, (LSB)MR18= 0x8d, (MSB)MR19= 0x3, tDQSOscB0 = 346 ps tDQSOscB1 = 0 ps
2122 01:01:51.821843 CH0 RK1: MR19=3, MR18=8D
2123 01:01:51.821931 [RxdqsGatingPostProcess] freq 1600
2124 01:01:51.822020 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2125 01:01:51.822108 Rank: 0
2126 01:01:51.822196 best DQS0 dly(2T, 0.5T) = (2, 5)
2127 01:01:51.822300 best DQS1 dly(2T, 0.5T) = (2, 5)
2128 01:01:51.822389 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2129 01:01:51.822479 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2130 01:01:51.822567 Rank: 1
2131 01:01:51.822656 best DQS0 dly(2T, 0.5T) = (2, 6)
2132 01:01:51.822744 best DQS1 dly(2T, 0.5T) = (2, 6)
2133 01:01:51.822833 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2134 01:01:51.822921 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2135 01:01:51.823009 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2136 01:01:51.823098 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2137 01:01:51.823187 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2138 01:01:51.823275 Write Rank0 MR13 =0x59
2139 01:01:51.823364 ==
2140 01:01:51.823453 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2141 01:01:51.823543 fsp= 1, odt_onoff= 1, Byte mode= 0
2142 01:01:51.823631 ==
2143 01:01:51.823720 === u2Vref_new: 0x56 --> 0x3a
2144 01:01:51.823810 === u2Vref_new: 0x58 --> 0x58
2145 01:01:51.823899 === u2Vref_new: 0x5a --> 0x5a
2146 01:01:51.823997 === u2Vref_new: 0x5c --> 0x78
2147 01:01:51.824073 === u2Vref_new: 0x5e --> 0x7a
2148 01:01:51.824149 === u2Vref_new: 0x60 --> 0x90
2149 01:01:51.824434 [CA 0] Center 37 (11~63) winsize 53
2150 01:01:51.824521 [CA 1] Center 36 (9~63) winsize 55
2151 01:01:51.824599 [CA 2] Center 33 (4~63) winsize 60
2152 01:01:51.824677 [CA 3] Center 34 (5~63) winsize 59
2153 01:01:51.824752 [CA 4] Center 34 (6~63) winsize 58
2154 01:01:51.824829 [CA 5] Center 28 (-2~58) winsize 61
2155 01:01:51.824905
2156 01:01:51.824981 [CATrainingPosCal] consider 1 rank data
2157 01:01:51.825059 u2DelayCellTimex100 = 753/100 ps
2158 01:01:51.825135 CA0 delay=37 (11~63),Diff = 9 PI (11 cell)
2159 01:01:51.825211 CA1 delay=36 (9~63),Diff = 8 PI (10 cell)
2160 01:01:51.825287 CA2 delay=33 (4~63),Diff = 5 PI (6 cell)
2161 01:01:51.825362 CA3 delay=34 (5~63),Diff = 6 PI (7 cell)
2162 01:01:51.825438 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2163 01:01:51.825513 CA5 delay=28 (-2~58),Diff = 0 PI (0 cell)
2164 01:01:51.825589
2165 01:01:51.825665 CA PerBit enable=1, Macro0, CA PI delay=28
2166 01:01:51.825742 === u2Vref_new: 0x56 --> 0x3a
2167 01:01:51.825818
2168 01:01:51.825893 Vref(ca) range 1: 22
2169 01:01:51.825968
2170 01:01:51.826043 CS Dly= 12 (43-0-32)
2171 01:01:51.826120 Write Rank0 MR13 =0xd8
2172 01:01:51.826196 Write Rank0 MR13 =0xd8
2173 01:01:51.826286 Write Rank0 MR12 =0x56
2174 01:01:51.826362 Write Rank1 MR13 =0x59
2175 01:01:51.826437 ==
2176 01:01:51.826514 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2177 01:01:51.826592 fsp= 1, odt_onoff= 1, Byte mode= 0
2178 01:01:51.826669 ==
2179 01:01:51.826745 === u2Vref_new: 0x56 --> 0x3a
2180 01:01:51.826821 === u2Vref_new: 0x58 --> 0x58
2181 01:01:51.826899 === u2Vref_new: 0x5a --> 0x5a
2182 01:01:51.826975 === u2Vref_new: 0x5c --> 0x78
2183 01:01:51.827051 === u2Vref_new: 0x5e --> 0x7a
2184 01:01:51.827127 === u2Vref_new: 0x60 --> 0x90
2185 01:01:51.827204
2186 01:01:51.827281 CBT Vref found, early break!
2187 01:01:51.827358 [CA 0] Center 37 (12~63) winsize 52
2188 01:01:51.827435 [CA 1] Center 35 (7~63) winsize 57
2189 01:01:51.827511 [CA 2] Center 33 (4~63) winsize 60
2190 01:01:51.827587 [CA 3] Center 34 (5~63) winsize 59
2191 01:01:51.827663 [CA 4] Center 34 (6~63) winsize 58
2192 01:01:51.827738 [CA 5] Center 27 (-3~57) winsize 61
2193 01:01:51.827814
2194 01:01:51.827889 [CATrainingPosCal] consider 2 rank data
2195 01:01:51.827966 u2DelayCellTimex100 = 753/100 ps
2196 01:01:51.828042 CA0 delay=37 (12~63),Diff = 10 PI (12 cell)
2197 01:01:51.828119 CA1 delay=36 (9~63),Diff = 9 PI (11 cell)
2198 01:01:51.828196 CA2 delay=33 (4~63),Diff = 6 PI (7 cell)
2199 01:01:51.828273 CA3 delay=34 (5~63),Diff = 7 PI (9 cell)
2200 01:01:51.828349 CA4 delay=34 (6~63),Diff = 7 PI (9 cell)
2201 01:01:51.828425 CA5 delay=27 (-2~57),Diff = 0 PI (0 cell)
2202 01:01:51.828500
2203 01:01:51.828576 CA PerBit enable=1, Macro0, CA PI delay=27
2204 01:01:51.828652 === u2Vref_new: 0x56 --> 0x3a
2205 01:01:51.828729
2206 01:01:51.828804 Vref(ca) range 1: 22
2207 01:01:51.828880
2208 01:01:51.828955 CS Dly= 11 (42-0-32)
2209 01:01:51.829036 Write Rank1 MR13 =0xd8
2210 01:01:51.829103 Write Rank1 MR13 =0xd8
2211 01:01:51.829168 Write Rank1 MR12 =0x56
2212 01:01:51.829233 [RankSwap] Rank num 2, (Multi 1), Rank 0
2213 01:01:51.829299 Write Rank0 MR2 =0xad
2214 01:01:51.829365 [Write Leveling]
2215 01:01:51.829432 delay byte0 byte1 byte2 byte3
2216 01:01:51.829498
2217 01:01:51.829564 10 0 0
2218 01:01:51.829632 11 0 0
2219 01:01:51.829700 12 0 0
2220 01:01:51.829768 13 0 0
2221 01:01:51.829835 14 0 0
2222 01:01:51.829902 15 0 0
2223 01:01:51.829985 16 0 0
2224 01:01:51.830057 17 0 0
2225 01:01:51.830125 18 0 0
2226 01:01:51.830193 19 0 0
2227 01:01:51.830327 20 0 0
2228 01:01:51.831450 21 0 0
2229 01:01:51.831569 22 0 0
2230 01:01:51.834976 23 0 0
2231 01:01:51.835082 24 0 0
2232 01:01:51.838154 25 0 0
2233 01:01:51.838275 26 0 0
2234 01:01:51.838328 27 0 0
2235 01:01:51.841988 28 0 0
2236 01:01:51.842063 29 0 0
2237 01:01:51.844801 30 0 0
2238 01:01:51.844877 31 0 0
2239 01:01:51.844936 32 0 0
2240 01:01:51.848273 33 0 ff
2241 01:01:51.848349 34 0 ff
2242 01:01:51.851549 35 0 ff
2243 01:01:51.851626 36 ff ff
2244 01:01:51.854785 37 ff ff
2245 01:01:51.854861 38 ff ff
2246 01:01:51.858151 39 ff ff
2247 01:01:51.858249 40 ff ff
2248 01:01:51.858322 41 ff ff
2249 01:01:51.861901 42 ff ff
2250 01:01:51.865147 pass bytecount = 0xff (0xff: all bytes pass)
2251 01:01:51.865530
2252 01:01:51.868592 DQS0 dly: 36
2253 01:01:51.868973 DQS1 dly: 33
2254 01:01:51.869272 Write Rank0 MR2 =0x2d
2255 01:01:51.875571 [RankSwap] Rank num 2, (Multi 1), Rank 0
2256 01:01:51.876022 Write Rank0 MR1 =0xd6
2257 01:01:51.876324 [Gating]
2258 01:01:51.878857 ==
2259 01:01:51.882591 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2260 01:01:51.885784 fsp= 1, odt_onoff= 1, Byte mode= 0
2261 01:01:51.886279 ==
2262 01:01:51.889346 3 1 0 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2263 01:01:51.895742 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2264 01:01:51.898962 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2265 01:01:51.902313 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2266 01:01:51.905600 3 1 16 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2267 01:01:51.912508 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2268 01:01:51.915713 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2269 01:01:51.919252 3 1 28 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2270 01:01:51.925717 3 2 0 |403 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2271 01:01:51.929325 3 2 4 |3d3d 1413 |(11 11)(11 11) |(1 1)(0 0)| 0
2272 01:01:51.933068 3 2 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2273 01:01:51.939395 3 2 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2274 01:01:51.942298 3 2 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2275 01:01:51.945650 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2276 01:01:51.949088 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2277 01:01:51.956158 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2278 01:01:51.959202 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2279 01:01:51.962855 3 3 4 |c0c 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2280 01:01:51.969330 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2281 01:01:51.972710 [Byte 0] Lead/lag Transition tap number (1)
2282 01:01:51.976066 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2283 01:01:51.979459 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2284 01:01:51.985927 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2285 01:01:51.989507 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2286 01:01:51.992913 3 3 28 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2287 01:01:51.999441 3 4 0 |403 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2288 01:01:52.003260 3 4 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2289 01:01:52.006266 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2290 01:01:52.009586 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2291 01:01:52.016220 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2292 01:01:52.019559 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2293 01:01:52.023082 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2294 01:01:52.029892 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2295 01:01:52.033148 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2296 01:01:52.036490 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2297 01:01:52.043247 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2298 01:01:52.046584 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2299 01:01:52.050069 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2300 01:01:52.053401 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2301 01:01:52.060077 [Byte 0] Lead/lag falling Transition (3, 5, 20)
2302 01:01:52.063588 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2303 01:01:52.067059 [Byte 0] Lead/lag Transition tap number (2)
2304 01:01:52.069869 [Byte 1] Lead/lag falling Transition (3, 5, 24)
2305 01:01:52.076529 3 5 28 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2306 01:01:52.079931 [Byte 1] Lead/lag Transition tap number (2)
2307 01:01:52.083420 3 6 0 |202 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
2308 01:01:52.086348 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2309 01:01:52.089869 [Byte 0]First pass (3, 6, 4)
2310 01:01:52.093229 3 6 8 |4646 4646 |(0 0)(10 10) |(0 0)(0 0)| 0
2311 01:01:52.099943 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2312 01:01:52.100020 [Byte 1]First pass (3, 6, 12)
2313 01:01:52.106692 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2314 01:01:52.109886 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2315 01:01:52.113451 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2316 01:01:52.116547 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2317 01:01:52.120030 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2318 01:01:52.126623 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2319 01:01:52.130017 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2320 01:01:52.133339 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2321 01:01:52.136830 All bytes gating window > 1UI, Early break!
2322 01:01:52.136905
2323 01:01:52.139986 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 24)
2324 01:01:52.140067
2325 01:01:52.143342 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28)
2326 01:01:52.143422
2327 01:01:52.146688
2328 01:01:52.146774
2329 01:01:52.150163 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 24)
2330 01:01:52.150267
2331 01:01:52.153323 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
2332 01:01:52.153415
2333 01:01:52.153487
2334 01:01:52.156873 Write Rank0 MR1 =0x56
2335 01:01:52.156974
2336 01:01:52.160063 best RODT dly(2T, 0.5T) = (2, 2)
2337 01:01:52.160175
2338 01:01:52.160261 best RODT dly(2T, 0.5T) = (2, 2)
2339 01:01:52.163545 ==
2340 01:01:52.166718 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2341 01:01:52.170228 fsp= 1, odt_onoff= 1, Byte mode= 0
2342 01:01:52.170373 ==
2343 01:01:52.173404 Start DQ dly to find pass range UseTestEngine =0
2344 01:01:52.176905 x-axis: bit #, y-axis: DQ dly (-127~63)
2345 01:01:52.180340 RX Vref Scan = 0
2346 01:01:52.183565 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2347 01:01:52.187008 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2348 01:01:52.190259 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2349 01:01:52.190646 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2350 01:01:52.193862 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2351 01:01:52.197543 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2352 01:01:52.200716 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2353 01:01:52.203901 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2354 01:01:52.207293 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2355 01:01:52.210506 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2356 01:01:52.213935 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2357 01:01:52.214365 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2358 01:01:52.217348 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2359 01:01:52.220785 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2360 01:01:52.224352 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2361 01:01:52.227222 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2362 01:01:52.230675 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2363 01:01:52.233959 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2364 01:01:52.234389 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2365 01:01:52.237407 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2366 01:01:52.241028 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2367 01:01:52.244224 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2368 01:01:52.247494 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2369 01:01:52.250933 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2370 01:01:52.254194 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2371 01:01:52.254615 -1, [0] xxxxxxxx xxxxxxxo [MSB]
2372 01:01:52.257631 0, [0] xxxoxxxx xxxxxxxo [MSB]
2373 01:01:52.261039 1, [0] xxxoxxxx xxxxxxxo [MSB]
2374 01:01:52.264130 2, [0] xxxoxxxx xxxxxxxo [MSB]
2375 01:01:52.267822 3, [0] xxoooxxo oxoxxxxo [MSB]
2376 01:01:52.270925 4, [0] xxoooxxo oooxxoxo [MSB]
2377 01:01:52.271321 5, [0] xxoooxxo oooooooo [MSB]
2378 01:01:52.274312 6, [0] xxoooxxo oooooooo [MSB]
2379 01:01:52.277828 31, [0] oooxoooo oooooooo [MSB]
2380 01:01:52.281032 32, [0] ooxxoooo ooooooox [MSB]
2381 01:01:52.284609 33, [0] ooxxoooo oxooooox [MSB]
2382 01:01:52.287484 34, [0] ooxxoooo oxxxooox [MSB]
2383 01:01:52.287878 35, [0] ooxxoooo xxxxooxx [MSB]
2384 01:01:52.290878 36, [0] ooxxxoox xxxxoxxx [MSB]
2385 01:01:52.294412 37, [0] ooxxxoox xxxxoxxx [MSB]
2386 01:01:52.297731 38, [0] ooxxxoox xxxxxxxx [MSB]
2387 01:01:52.300909 39, [0] ooxxxoox xxxxxxxx [MSB]
2388 01:01:52.304493 40, [0] ooxxxoxx xxxxxxxx [MSB]
2389 01:01:52.307728 41, [0] xxxxxxxx xxxxxxxx [MSB]
2390 01:01:52.310774 iDelay=41, Bit 0, Center 23 (7 ~ 40) 34
2391 01:01:52.314140 iDelay=41, Bit 1, Center 23 (7 ~ 40) 34
2392 01:01:52.317532 iDelay=41, Bit 2, Center 17 (3 ~ 31) 29
2393 01:01:52.320890 iDelay=41, Bit 3, Center 15 (0 ~ 30) 31
2394 01:01:52.324023 iDelay=41, Bit 4, Center 19 (3 ~ 35) 33
2395 01:01:52.327526 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34
2396 01:01:52.330737 iDelay=41, Bit 6, Center 23 (7 ~ 39) 33
2397 01:01:52.334276 iDelay=41, Bit 7, Center 19 (3 ~ 35) 33
2398 01:01:52.337583 iDelay=41, Bit 8, Center 18 (3 ~ 34) 32
2399 01:01:52.340766 iDelay=41, Bit 9, Center 18 (4 ~ 32) 29
2400 01:01:52.344016 iDelay=41, Bit 10, Center 18 (3 ~ 33) 31
2401 01:01:52.347373 iDelay=41, Bit 11, Center 19 (5 ~ 33) 29
2402 01:01:52.350859 iDelay=41, Bit 12, Center 21 (5 ~ 37) 33
2403 01:01:52.357710 iDelay=41, Bit 13, Center 19 (4 ~ 35) 32
2404 01:01:52.360928 iDelay=41, Bit 14, Center 19 (5 ~ 34) 30
2405 01:01:52.364421 iDelay=41, Bit 15, Center 15 (-1 ~ 31) 33
2406 01:01:52.364814 ==
2407 01:01:52.367337 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2408 01:01:52.370650 fsp= 1, odt_onoff= 1, Byte mode= 0
2409 01:01:52.371049 ==
2410 01:01:52.373997 DQS Delay:
2411 01:01:52.374413 DQS0 = 0, DQS1 = 0
2412 01:01:52.377323 DQM Delay:
2413 01:01:52.377710 DQM0 = 20, DQM1 = 18
2414 01:01:52.378016 DQ Delay:
2415 01:01:52.380800 DQ0 =23, DQ1 =23, DQ2 =17, DQ3 =15
2416 01:01:52.384245 DQ4 =19, DQ5 =23, DQ6 =23, DQ7 =19
2417 01:01:52.387341 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =19
2418 01:01:52.390739 DQ12 =21, DQ13 =19, DQ14 =19, DQ15 =15
2419 01:01:52.391127
2420 01:01:52.391430
2421 01:01:52.394310 DramC Write-DBI off
2422 01:01:52.394698 ==
2423 01:01:52.397826 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2424 01:01:52.400890 fsp= 1, odt_onoff= 1, Byte mode= 0
2425 01:01:52.401323 ==
2426 01:01:52.407429 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2427 01:01:52.407822
2428 01:01:52.411072 Begin, DQ Scan Range 929~1185
2429 01:01:52.411475
2430 01:01:52.411780
2431 01:01:52.412064 TX Vref Scan disable
2432 01:01:52.414111 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2433 01:01:52.417932 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2434 01:01:52.420815 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2435 01:01:52.427510 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2436 01:01:52.430748 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2437 01:01:52.434327 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2438 01:01:52.437577 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2439 01:01:52.440947 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2440 01:01:52.444448 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2441 01:01:52.447492 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2442 01:01:52.450951 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2443 01:01:52.454271 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2444 01:01:52.457727 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2445 01:01:52.460982 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2446 01:01:52.464591 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2447 01:01:52.467792 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2448 01:01:52.471037 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2449 01:01:52.474550 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2450 01:01:52.477523 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2451 01:01:52.481106 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2452 01:01:52.487971 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2453 01:01:52.491023 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2454 01:01:52.494534 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2455 01:01:52.497935 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2456 01:01:52.501548 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2457 01:01:52.504992 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2458 01:01:52.508075 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2459 01:01:52.511371 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2460 01:01:52.514792 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2461 01:01:52.517864 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2462 01:01:52.521277 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2463 01:01:52.524768 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2464 01:01:52.528373 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2465 01:01:52.531278 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2466 01:01:52.534725 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2467 01:01:52.538056 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2468 01:01:52.541416 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2469 01:01:52.544894 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2470 01:01:52.547936 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2471 01:01:52.551528 968 |3 6 8|[0] xxxxxxxx xxxxxxxo [MSB]
2472 01:01:52.554997 969 |3 6 9|[0] xxxxxxxx xxxxxxxo [MSB]
2473 01:01:52.557960 970 |3 6 10|[0] xxxxxxxx oooxxxxo [MSB]
2474 01:01:52.561571 971 |3 6 11|[0] xxxoxxxx ooooxxoo [MSB]
2475 01:01:52.568112 972 |3 6 12|[0] xxxoxxxx oooooooo [MSB]
2476 01:01:52.571527 973 |3 6 13|[0] xxxoxxxx oooooooo [MSB]
2477 01:01:52.574905 974 |3 6 14|[0] xxooxxxx oooooooo [MSB]
2478 01:01:52.578230 975 |3 6 15|[0] xxoooxxo oooooooo [MSB]
2479 01:01:52.581882 976 |3 6 16|[0] xooooooo oooooooo [MSB]
2480 01:01:52.588008 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2481 01:01:52.591539 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2482 01:01:52.594733 994 |3 6 34|[0] ooxxoooo xxxxxxxx [MSB]
2483 01:01:52.598315 995 |3 6 35|[0] ooxxoooo xxxxxxxx [MSB]
2484 01:01:52.601576 996 |3 6 36|[0] ooxxoooo xxxxxxxx [MSB]
2485 01:01:52.604866 997 |3 6 37|[0] ooxxooox xxxxxxxx [MSB]
2486 01:01:52.608363 998 |3 6 38|[0] oxxxxoox xxxxxxxx [MSB]
2487 01:01:52.611597 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
2488 01:01:52.615089 Byte0, DQ PI dly=984, DQM PI dly= 984
2489 01:01:52.618527 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
2490 01:01:52.618960
2491 01:01:52.624883 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
2492 01:01:52.625327
2493 01:01:52.628308 Byte1, DQ PI dly=980, DQM PI dly= 980
2494 01:01:52.631569 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2495 01:01:52.632001
2496 01:01:52.635011 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2497 01:01:52.635445
2498 01:01:52.635778 ==
2499 01:01:52.641733 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2500 01:01:52.645216 fsp= 1, odt_onoff= 1, Byte mode= 0
2501 01:01:52.645677 ==
2502 01:01:52.648525 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2503 01:01:52.648988
2504 01:01:52.651878 Begin, DQ Scan Range 956~1020
2505 01:01:52.655058 Write Rank0 MR14 =0x0
2506 01:01:52.661881
2507 01:01:52.662406 CH=1, VrefRange= 0, VrefLevel = 0
2508 01:01:52.668646 TX Bit0 (978~997) 20 987, Bit8 (971~990) 20 980,
2509 01:01:52.672142 TX Bit1 (977~994) 18 985, Bit9 (971~989) 19 980,
2510 01:01:52.678689 TX Bit2 (976~990) 15 983, Bit10 (974~989) 16 981,
2511 01:01:52.682142 TX Bit3 (974~989) 16 981, Bit11 (975~991) 17 983,
2512 01:01:52.685661 TX Bit4 (977~991) 15 984, Bit12 (975~992) 18 983,
2513 01:01:52.692360 TX Bit5 (978~997) 20 987, Bit13 (975~991) 17 983,
2514 01:01:52.695465 TX Bit6 (978~997) 20 987, Bit14 (975~990) 16 982,
2515 01:01:52.698886 TX Bit7 (977~991) 15 984, Bit15 (970~987) 18 978,
2516 01:01:52.699319
2517 01:01:52.701986 Write Rank0 MR14 =0x2
2518 01:01:52.710312
2519 01:01:52.710744 CH=1, VrefRange= 0, VrefLevel = 2
2520 01:01:52.716837 TX Bit0 (978~997) 20 987, Bit8 (971~991) 21 981,
2521 01:01:52.720435 TX Bit1 (977~995) 19 986, Bit9 (971~990) 20 980,
2522 01:01:52.727194 TX Bit2 (976~990) 15 983, Bit10 (973~990) 18 981,
2523 01:01:52.730166 TX Bit3 (974~990) 17 982, Bit11 (974~991) 18 982,
2524 01:01:52.733531 TX Bit4 (976~992) 17 984, Bit12 (974~992) 19 983,
2525 01:01:52.740203 TX Bit5 (977~997) 21 987, Bit13 (975~991) 17 983,
2526 01:01:52.743578 TX Bit6 (978~997) 20 987, Bit14 (974~990) 17 982,
2527 01:01:52.746840 TX Bit7 (977~991) 15 984, Bit15 (970~987) 18 978,
2528 01:01:52.747235
2529 01:01:52.750302 Write Rank0 MR14 =0x4
2530 01:01:52.758617
2531 01:01:52.759002 CH=1, VrefRange= 0, VrefLevel = 4
2532 01:01:52.765211 TX Bit0 (978~997) 20 987, Bit8 (970~991) 22 980,
2533 01:01:52.768598 TX Bit1 (977~995) 19 986, Bit9 (971~990) 20 980,
2534 01:01:52.775340 TX Bit2 (976~991) 16 983, Bit10 (972~991) 20 981,
2535 01:01:52.778703 TX Bit3 (974~990) 17 982, Bit11 (974~992) 19 983,
2536 01:01:52.782111 TX Bit4 (976~993) 18 984, Bit12 (974~992) 19 983,
2537 01:01:52.788876 TX Bit5 (977~997) 21 987, Bit13 (975~991) 17 983,
2538 01:01:52.792054 TX Bit6 (978~997) 20 987, Bit14 (974~991) 18 982,
2539 01:01:52.795459 TX Bit7 (977~992) 16 984, Bit15 (969~988) 20 978,
2540 01:01:52.795895
2541 01:01:52.798618 Write Rank0 MR14 =0x6
2542 01:01:52.807250
2543 01:01:52.807675 CH=1, VrefRange= 0, VrefLevel = 6
2544 01:01:52.813791 TX Bit0 (977~997) 21 987, Bit8 (970~991) 22 980,
2545 01:01:52.817206 TX Bit1 (977~996) 20 986, Bit9 (970~991) 22 980,
2546 01:01:52.823742 TX Bit2 (976~991) 16 983, Bit10 (972~991) 20 981,
2547 01:01:52.827308 TX Bit3 (973~990) 18 981, Bit11 (973~991) 19 982,
2548 01:01:52.830449 TX Bit4 (976~993) 18 984, Bit12 (973~992) 20 982,
2549 01:01:52.837087 TX Bit5 (977~997) 21 987, Bit13 (975~992) 18 983,
2550 01:01:52.840474 TX Bit6 (977~997) 21 987, Bit14 (973~991) 19 982,
2551 01:01:52.843907 TX Bit7 (976~992) 17 984, Bit15 (969~989) 21 979,
2552 01:01:52.844297
2553 01:01:52.847198 Write Rank0 MR14 =0x8
2554 01:01:52.855784
2555 01:01:52.856234 CH=1, VrefRange= 0, VrefLevel = 8
2556 01:01:52.862393 TX Bit0 (978~998) 21 988, Bit8 (970~991) 22 980,
2557 01:01:52.865595 TX Bit1 (977~996) 20 986, Bit9 (970~991) 22 980,
2558 01:01:52.872234 TX Bit2 (975~991) 17 983, Bit10 (971~992) 22 981,
2559 01:01:52.875986 TX Bit3 (973~991) 19 982, Bit11 (973~992) 20 982,
2560 01:01:52.878988 TX Bit4 (976~994) 19 985, Bit12 (973~993) 21 983,
2561 01:01:52.885874 TX Bit5 (977~997) 21 987, Bit13 (974~992) 19 983,
2562 01:01:52.889531 TX Bit6 (977~997) 21 987, Bit14 (972~992) 21 982,
2563 01:01:52.892593 TX Bit7 (976~993) 18 984, Bit15 (969~989) 21 979,
2564 01:01:52.893106
2565 01:01:52.895764 Write Rank0 MR14 =0xa
2566 01:01:52.904352
2567 01:01:52.907568 CH=1, VrefRange= 0, VrefLevel = 10
2568 01:01:52.911363 TX Bit0 (977~998) 22 987, Bit8 (970~992) 23 981,
2569 01:01:52.914273 TX Bit1 (976~997) 22 986, Bit9 (970~991) 22 980,
2570 01:01:52.921137 TX Bit2 (975~992) 18 983, Bit10 (971~992) 22 981,
2571 01:01:52.924333 TX Bit3 (973~991) 19 982, Bit11 (972~992) 21 982,
2572 01:01:52.927651 TX Bit4 (975~995) 21 985, Bit12 (973~993) 21 983,
2573 01:01:52.934371 TX Bit5 (977~998) 22 987, Bit13 (973~992) 20 982,
2574 01:01:52.937583 TX Bit6 (977~998) 22 987, Bit14 (972~992) 21 982,
2575 01:01:52.940990 TX Bit7 (976~994) 19 985, Bit15 (969~990) 22 979,
2576 01:01:52.941547
2577 01:01:52.944102 Write Rank0 MR14 =0xc
2578 01:01:52.952948
2579 01:01:52.956098 CH=1, VrefRange= 0, VrefLevel = 12
2580 01:01:52.959735 TX Bit0 (977~998) 22 987, Bit8 (970~992) 23 981,
2581 01:01:52.963130 TX Bit1 (976~997) 22 986, Bit9 (970~991) 22 980,
2582 01:01:52.969715 TX Bit2 (975~992) 18 983, Bit10 (971~992) 22 981,
2583 01:01:52.973096 TX Bit3 (972~992) 21 982, Bit11 (972~993) 22 982,
2584 01:01:52.976662 TX Bit4 (975~996) 22 985, Bit12 (972~993) 22 982,
2585 01:01:52.983222 TX Bit5 (977~998) 22 987, Bit13 (973~992) 20 982,
2586 01:01:52.986277 TX Bit6 (977~998) 22 987, Bit14 (972~992) 21 982,
2587 01:01:52.989791 TX Bit7 (976~994) 19 985, Bit15 (969~991) 23 980,
2588 01:01:52.990260
2589 01:01:52.993074 Write Rank0 MR14 =0xe
2590 01:01:53.001469
2591 01:01:53.004894 CH=1, VrefRange= 0, VrefLevel = 14
2592 01:01:53.008199 TX Bit0 (977~998) 22 987, Bit8 (970~992) 23 981,
2593 01:01:53.011795 TX Bit1 (976~997) 22 986, Bit9 (970~992) 23 981,
2594 01:01:53.018087 TX Bit2 (974~993) 20 983, Bit10 (970~992) 23 981,
2595 01:01:53.022043 TX Bit3 (972~992) 21 982, Bit11 (971~993) 23 982,
2596 01:01:53.024885 TX Bit4 (975~996) 22 985, Bit12 (972~994) 23 983,
2597 01:01:53.031634 TX Bit5 (977~998) 22 987, Bit13 (972~993) 22 982,
2598 01:01:53.034806 TX Bit6 (977~998) 22 987, Bit14 (971~992) 22 981,
2599 01:01:53.038294 TX Bit7 (976~995) 20 985, Bit15 (968~991) 24 979,
2600 01:01:53.038730
2601 01:01:53.041589 Write Rank0 MR14 =0x10
2602 01:01:53.050376
2603 01:01:53.053819 CH=1, VrefRange= 0, VrefLevel = 16
2604 01:01:53.057577 TX Bit0 (977~999) 23 988, Bit8 (969~992) 24 980,
2605 01:01:53.060573 TX Bit1 (976~997) 22 986, Bit9 (970~992) 23 981,
2606 01:01:53.067229 TX Bit2 (974~993) 20 983, Bit10 (970~992) 23 981,
2607 01:01:53.070691 TX Bit3 (971~993) 23 982, Bit11 (971~993) 23 982,
2608 01:01:53.073995 TX Bit4 (975~996) 22 985, Bit12 (972~994) 23 983,
2609 01:01:53.080605 TX Bit5 (976~998) 23 987, Bit13 (972~993) 22 982,
2610 01:01:53.084069 TX Bit6 (977~999) 23 988, Bit14 (971~992) 22 981,
2611 01:01:53.087257 TX Bit7 (976~996) 21 986, Bit15 (968~991) 24 979,
2612 01:01:53.087693
2613 01:01:53.090514 Write Rank0 MR14 =0x12
2614 01:01:53.099370
2615 01:01:53.099882 CH=1, VrefRange= 0, VrefLevel = 18
2616 01:01:53.106085 TX Bit0 (976~999) 24 987, Bit8 (969~993) 25 981,
2617 01:01:53.109442 TX Bit1 (976~998) 23 987, Bit9 (970~992) 23 981,
2618 01:01:53.115981 TX Bit2 (974~994) 21 984, Bit10 (970~993) 24 981,
2619 01:01:53.119358 TX Bit3 (971~993) 23 982, Bit11 (971~994) 24 982,
2620 01:01:53.122706 TX Bit4 (975~997) 23 986, Bit12 (971~994) 24 982,
2621 01:01:53.129523 TX Bit5 (976~999) 24 987, Bit13 (971~993) 23 982,
2622 01:01:53.132820 TX Bit6 (977~999) 23 988, Bit14 (971~993) 23 982,
2623 01:01:53.136297 TX Bit7 (975~996) 22 985, Bit15 (968~992) 25 980,
2624 01:01:53.136694
2625 01:01:53.139444 Write Rank0 MR14 =0x14
2626 01:01:53.148116
2627 01:01:53.151696 CH=1, VrefRange= 0, VrefLevel = 20
2628 01:01:53.154801 TX Bit0 (976~999) 24 987, Bit8 (969~993) 25 981,
2629 01:01:53.158263 TX Bit1 (976~998) 23 987, Bit9 (969~992) 24 980,
2630 01:01:53.164769 TX Bit2 (973~995) 23 984, Bit10 (970~993) 24 981,
2631 01:01:53.168432 TX Bit3 (970~994) 25 982, Bit11 (970~994) 25 982,
2632 01:01:53.171562 TX Bit4 (974~997) 24 985, Bit12 (971~995) 25 983,
2633 01:01:53.178318 TX Bit5 (976~999) 24 987, Bit13 (971~994) 24 982,
2634 01:01:53.181618 TX Bit6 (976~999) 24 987, Bit14 (970~993) 24 981,
2635 01:01:53.185120 TX Bit7 (975~997) 23 986, Bit15 (968~992) 25 980,
2636 01:01:53.185590
2637 01:01:53.188298 Write Rank0 MR14 =0x16
2638 01:01:53.196985
2639 01:01:53.200463 CH=1, VrefRange= 0, VrefLevel = 22
2640 01:01:53.203678 TX Bit0 (976~999) 24 987, Bit8 (969~992) 24 980,
2641 01:01:53.206981 TX Bit1 (976~998) 23 987, Bit9 (969~992) 24 980,
2642 01:01:53.213789 TX Bit2 (973~995) 23 984, Bit10 (969~993) 25 981,
2643 01:01:53.217184 TX Bit3 (970~994) 25 982, Bit11 (970~994) 25 982,
2644 01:01:53.220585 TX Bit4 (974~997) 24 985, Bit12 (971~995) 25 983,
2645 01:01:53.227200 TX Bit5 (976~999) 24 987, Bit13 (971~994) 24 982,
2646 01:01:53.230832 TX Bit6 (976~999) 24 987, Bit14 (970~993) 24 981,
2647 01:01:53.234277 TX Bit7 (974~997) 24 985, Bit15 (968~992) 25 980,
2648 01:01:53.234716
2649 01:01:53.237288 Write Rank0 MR14 =0x18
2650 01:01:53.246181
2651 01:01:53.249310 CH=1, VrefRange= 0, VrefLevel = 24
2652 01:01:53.252624 TX Bit0 (976~999) 24 987, Bit8 (969~992) 24 980,
2653 01:01:53.256588 TX Bit1 (976~998) 23 987, Bit9 (969~992) 24 980,
2654 01:01:53.262830 TX Bit2 (973~995) 23 984, Bit10 (969~993) 25 981,
2655 01:01:53.266139 TX Bit3 (970~994) 25 982, Bit11 (970~994) 25 982,
2656 01:01:53.269672 TX Bit4 (974~997) 24 985, Bit12 (971~995) 25 983,
2657 01:01:53.276523 TX Bit5 (976~999) 24 987, Bit13 (971~994) 24 982,
2658 01:01:53.280149 TX Bit6 (976~999) 24 987, Bit14 (970~993) 24 981,
2659 01:01:53.282973 TX Bit7 (974~997) 24 985, Bit15 (968~992) 25 980,
2660 01:01:53.283403
2661 01:01:53.286656 Write Rank0 MR14 =0x1a
2662 01:01:53.295271
2663 01:01:53.295748 CH=1, VrefRange= 0, VrefLevel = 26
2664 01:01:53.302060 TX Bit0 (976~999) 24 987, Bit8 (969~992) 24 980,
2665 01:01:53.305491 TX Bit1 (976~998) 23 987, Bit9 (969~992) 24 980,
2666 01:01:53.312051 TX Bit2 (973~995) 23 984, Bit10 (969~993) 25 981,
2667 01:01:53.315722 TX Bit3 (970~994) 25 982, Bit11 (970~994) 25 982,
2668 01:01:53.318824 TX Bit4 (974~997) 24 985, Bit12 (971~995) 25 983,
2669 01:01:53.325704 TX Bit5 (976~999) 24 987, Bit13 (971~994) 24 982,
2670 01:01:53.328732 TX Bit6 (976~999) 24 987, Bit14 (970~993) 24 981,
2671 01:01:53.332214 TX Bit7 (974~997) 24 985, Bit15 (968~992) 25 980,
2672 01:01:53.332648
2673 01:01:53.335264 Write Rank0 MR14 =0x1c
2674 01:01:53.344438
2675 01:01:53.347418 CH=1, VrefRange= 0, VrefLevel = 28
2676 01:01:53.350924 TX Bit0 (976~999) 24 987, Bit8 (969~992) 24 980,
2677 01:01:53.354321 TX Bit1 (976~998) 23 987, Bit9 (969~992) 24 980,
2678 01:01:53.360936 TX Bit2 (973~995) 23 984, Bit10 (969~993) 25 981,
2679 01:01:53.364698 TX Bit3 (970~994) 25 982, Bit11 (970~994) 25 982,
2680 01:01:53.367706 TX Bit4 (974~997) 24 985, Bit12 (971~995) 25 983,
2681 01:01:53.374270 TX Bit5 (976~999) 24 987, Bit13 (971~994) 24 982,
2682 01:01:53.377856 TX Bit6 (976~999) 24 987, Bit14 (970~993) 24 981,
2683 01:01:53.381345 TX Bit7 (974~997) 24 985, Bit15 (968~992) 25 980,
2684 01:01:53.381794
2685 01:01:53.384419 Write Rank0 MR14 =0x1e
2686 01:01:53.393151
2687 01:01:53.396488 CH=1, VrefRange= 0, VrefLevel = 30
2688 01:01:53.399786 TX Bit0 (976~999) 24 987, Bit8 (969~992) 24 980,
2689 01:01:53.403437 TX Bit1 (976~998) 23 987, Bit9 (969~992) 24 980,
2690 01:01:53.409626 TX Bit2 (973~995) 23 984, Bit10 (969~993) 25 981,
2691 01:01:53.413314 TX Bit3 (970~994) 25 982, Bit11 (970~994) 25 982,
2692 01:01:53.416352 TX Bit4 (974~997) 24 985, Bit12 (971~995) 25 983,
2693 01:01:53.423111 TX Bit5 (976~999) 24 987, Bit13 (971~994) 24 982,
2694 01:01:53.426314 TX Bit6 (976~999) 24 987, Bit14 (970~993) 24 981,
2695 01:01:53.429833 TX Bit7 (974~997) 24 985, Bit15 (968~992) 25 980,
2696 01:01:53.430312
2697 01:01:53.430746
2698 01:01:53.433595 TX Vref found, early break! 365< 367
2699 01:01:53.439906 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
2700 01:01:53.443197 u1DelayCellOfst[0]=6 cells (5 PI)
2701 01:01:53.446535 u1DelayCellOfst[1]=6 cells (5 PI)
2702 01:01:53.450135 u1DelayCellOfst[2]=2 cells (2 PI)
2703 01:01:53.450553 u1DelayCellOfst[3]=0 cells (0 PI)
2704 01:01:53.453302 u1DelayCellOfst[4]=3 cells (3 PI)
2705 01:01:53.456904 u1DelayCellOfst[5]=6 cells (5 PI)
2706 01:01:53.460321 u1DelayCellOfst[6]=6 cells (5 PI)
2707 01:01:53.463496 u1DelayCellOfst[7]=3 cells (3 PI)
2708 01:01:53.466675 Byte0, DQ PI dly=982, DQM PI dly= 984
2709 01:01:53.469795 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
2710 01:01:53.470187
2711 01:01:53.477067 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
2712 01:01:53.477536
2713 01:01:53.480280 u1DelayCellOfst[8]=0 cells (0 PI)
2714 01:01:53.483391 u1DelayCellOfst[9]=0 cells (0 PI)
2715 01:01:53.486835 u1DelayCellOfst[10]=1 cells (1 PI)
2716 01:01:53.487301 u1DelayCellOfst[11]=2 cells (2 PI)
2717 01:01:53.489976 u1DelayCellOfst[12]=3 cells (3 PI)
2718 01:01:53.493445 u1DelayCellOfst[13]=2 cells (2 PI)
2719 01:01:53.497096 u1DelayCellOfst[14]=1 cells (1 PI)
2720 01:01:53.500017 u1DelayCellOfst[15]=0 cells (0 PI)
2721 01:01:53.503635 Byte1, DQ PI dly=980, DQM PI dly= 981
2722 01:01:53.506751 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2723 01:01:53.507189
2724 01:01:53.513364 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2725 01:01:53.513798
2726 01:01:53.514131 Write Rank0 MR14 =0x16
2727 01:01:53.514607
2728 01:01:53.516874 Final TX Range 0 Vref 22
2729 01:01:53.517387
2730 01:01:53.524012 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2731 01:01:53.524524
2732 01:01:53.530302 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2733 01:01:53.537136 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2734 01:01:53.543716 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2735 01:01:53.546943 Write Rank0 MR3 =0xb0
2736 01:01:53.547371 DramC Write-DBI on
2737 01:01:53.550262 ==
2738 01:01:53.553635 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2739 01:01:53.557136 fsp= 1, odt_onoff= 1, Byte mode= 0
2740 01:01:53.557565 ==
2741 01:01:53.560509 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2742 01:01:53.560938
2743 01:01:53.563703 Begin, DQ Scan Range 701~765
2744 01:01:53.564281
2745 01:01:53.564667
2746 01:01:53.567402 TX Vref Scan disable
2747 01:01:53.570502 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2748 01:01:53.573924 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2749 01:01:53.577187 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2750 01:01:53.580424 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2751 01:01:53.583873 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2752 01:01:53.587017 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2753 01:01:53.590357 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2754 01:01:53.593830 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2755 01:01:53.596885 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2756 01:01:53.600484 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2757 01:01:53.603878 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2758 01:01:53.607225 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2759 01:01:53.610520 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2760 01:01:53.613985 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2761 01:01:53.617276 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2762 01:01:53.620492 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2763 01:01:53.623756 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2764 01:01:53.633542 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2765 01:01:53.636729 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2766 01:01:53.640164 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2767 01:01:53.643775 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2768 01:01:53.646805 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2769 01:01:53.650299 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2770 01:01:53.653842 743 |2 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
2771 01:01:53.657266 Byte0, DQ PI dly=730, DQM PI dly= 730
2772 01:01:53.660352 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
2773 01:01:53.660863
2774 01:01:53.666893 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
2775 01:01:53.667329
2776 01:01:53.670346 Byte1, DQ PI dly=724, DQM PI dly= 724
2777 01:01:53.673452 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
2778 01:01:53.673886
2779 01:01:53.677151 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
2780 01:01:53.677583
2781 01:01:53.683684 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2782 01:01:53.690404 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2783 01:01:53.696952 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2784 01:01:53.700307 Write Rank0 MR3 =0x30
2785 01:01:53.703574 DramC Write-DBI off
2786 01:01:53.704049
2787 01:01:53.704389 [DATLAT]
2788 01:01:53.706684 Freq=1600, CH1 RK0, use_rxtx_scan=0
2789 01:01:53.707221
2790 01:01:53.707565 DATLAT Default: 0xf
2791 01:01:53.710331 7, 0xFFFF, sum=0
2792 01:01:53.710767 8, 0xFFFF, sum=0
2793 01:01:53.713649 9, 0xFFFF, sum=0
2794 01:01:53.714095 10, 0xFFFF, sum=0
2795 01:01:53.717521 11, 0xFFFF, sum=0
2796 01:01:53.718063 12, 0xFFFF, sum=0
2797 01:01:53.720434 13, 0xFFFF, sum=0
2798 01:01:53.720868 14, 0x0, sum=1
2799 01:01:53.723962 15, 0x0, sum=2
2800 01:01:53.724481 16, 0x0, sum=3
2801 01:01:53.724831 17, 0x0, sum=4
2802 01:01:53.730527 pattern=2 first_step=14 total pass=5 best_step=16
2803 01:01:53.731106 ==
2804 01:01:53.733660 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2805 01:01:53.737256 fsp= 1, odt_onoff= 1, Byte mode= 0
2806 01:01:53.737688 ==
2807 01:01:53.743819 Start DQ dly to find pass range UseTestEngine =1
2808 01:01:53.747053 x-axis: bit #, y-axis: DQ dly (-127~63)
2809 01:01:53.747486 RX Vref Scan = 1
2810 01:01:53.869675
2811 01:01:53.869810 RX Vref found, early break!
2812 01:01:53.869885
2813 01:01:53.876344 Final RX Vref 13, apply to both rank0 and 1
2814 01:01:53.876447 ==
2815 01:01:53.879675 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2816 01:01:53.883204 fsp= 1, odt_onoff= 1, Byte mode= 0
2817 01:01:53.883317 ==
2818 01:01:53.883405 DQS Delay:
2819 01:01:53.886704 DQS0 = 0, DQS1 = 0
2820 01:01:53.886897 DQM Delay:
2821 01:01:53.890160 DQM0 = 20, DQM1 = 18
2822 01:01:53.890396 DQ Delay:
2823 01:01:53.893282 DQ0 =23, DQ1 =23, DQ2 =17, DQ3 =14
2824 01:01:53.896914 DQ4 =19, DQ5 =24, DQ6 =24, DQ7 =19
2825 01:01:53.900208 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =19
2826 01:01:53.903561 DQ12 =21, DQ13 =19, DQ14 =20, DQ15 =15
2827 01:01:53.903800
2828 01:01:53.903973
2829 01:01:53.904140
2830 01:01:53.906595 [DramC_TX_OE_Calibration] TA2
2831 01:01:53.910168 Original DQ_B0 (3 6) =30, OEN = 27
2832 01:01:53.913667 Original DQ_B1 (3 6) =30, OEN = 27
2833 01:01:53.916909 23, 0x0, End_B0=23 End_B1=23
2834 01:01:53.917270 24, 0x0, End_B0=24 End_B1=24
2835 01:01:53.920356 25, 0x0, End_B0=25 End_B1=25
2836 01:01:53.923527 26, 0x0, End_B0=26 End_B1=26
2837 01:01:53.926877 27, 0x0, End_B0=27 End_B1=27
2838 01:01:53.927315 28, 0x0, End_B0=28 End_B1=28
2839 01:01:53.930481 29, 0x0, End_B0=29 End_B1=29
2840 01:01:53.933587 30, 0x0, End_B0=30 End_B1=30
2841 01:01:53.936839 31, 0xFFFF, End_B0=30 End_B1=30
2842 01:01:53.940223 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2843 01:01:53.946819 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2844 01:01:53.947291
2845 01:01:53.947649
2846 01:01:53.949791 Write Rank0 MR23 =0x3f
2847 01:01:53.950347 [DQSOSC]
2848 01:01:53.956740 [DQSOSCAuto] RK0, (LSB)MR18= 0xa4, (MSB)MR19= 0x3, tDQSOscB0 = 337 ps tDQSOscB1 = 0 ps
2849 01:01:53.963416 CH1_RK0: MR19=0x3, MR18=0xA4, DQSOSC=337, MR23=63, INC=21, DEC=32
2850 01:01:53.966719 Write Rank0 MR23 =0x3f
2851 01:01:53.967103 [DQSOSC]
2852 01:01:53.973422 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0, (MSB)MR19= 0x3, tDQSOscB0 = 339 ps tDQSOscB1 = 0 ps
2853 01:01:53.977024 CH1 RK0: MR19=3, MR18=A0
2854 01:01:53.980235 [RankSwap] Rank num 2, (Multi 1), Rank 1
2855 01:01:53.983860 Write Rank0 MR2 =0xad
2856 01:01:53.984244 [Write Leveling]
2857 01:01:53.986740 delay byte0 byte1 byte2 byte3
2858 01:01:53.987126
2859 01:01:53.987428 10 0 0
2860 01:01:53.990273 11 0 0
2861 01:01:53.990669 12 0 0
2862 01:01:53.993387 13 0 0
2863 01:01:53.993780 14 0 0
2864 01:01:53.997139 15 0 0
2865 01:01:53.997567 16 0 0
2866 01:01:53.997904 17 0 0
2867 01:01:53.999778 18 0 0
2868 01:01:53.999854 19 0 0
2869 01:01:54.002961 20 0 0
2870 01:01:54.003037 21 0 0
2871 01:01:54.003097 22 0 0
2872 01:01:54.006391 23 0 0
2873 01:01:54.006476 24 0 0
2874 01:01:54.009921 25 0 0
2875 01:01:54.009998 26 0 0
2876 01:01:54.010058 27 0 0
2877 01:01:54.013103 28 0 0
2878 01:01:54.013179 29 0 0
2879 01:01:54.016718 30 0 0
2880 01:01:54.016794 31 0 0
2881 01:01:54.019780 32 0 ff
2882 01:01:54.019861 33 0 ff
2883 01:01:54.019924 34 0 ff
2884 01:01:54.023543 35 0 ff
2885 01:01:54.023717 36 ff ff
2886 01:01:54.026667 37 ff ff
2887 01:01:54.026799 38 ff ff
2888 01:01:54.029963 39 ff ff
2889 01:01:54.030087 40 ff ff
2890 01:01:54.033359 41 ff ff
2891 01:01:54.033495 42 ff ff
2892 01:01:54.036592 pass bytecount = 0xff (0xff: all bytes pass)
2893 01:01:54.036762
2894 01:01:54.039897 DQS0 dly: 36
2895 01:01:54.040054 DQS1 dly: 32
2896 01:01:54.043080 Write Rank0 MR2 =0x2d
2897 01:01:54.046397 [RankSwap] Rank num 2, (Multi 1), Rank 0
2898 01:01:54.046549 Write Rank1 MR1 =0xd6
2899 01:01:54.049910 [Gating]
2900 01:01:54.050049 ==
2901 01:01:54.053214 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2902 01:01:54.056790 fsp= 1, odt_onoff= 1, Byte mode= 0
2903 01:01:54.056950 ==
2904 01:01:54.063469 3 1 0 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2905 01:01:54.066754 3 1 4 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2906 01:01:54.070249 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2907 01:01:54.073577 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2908 01:01:54.080678 3 1 16 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2909 01:01:54.083735 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 0)(1 0)| 0
2910 01:01:54.087038 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2911 01:01:54.093775 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2912 01:01:54.097435 3 2 0 |201 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2913 01:01:54.100714 3 2 4 |3d3d 201 |(11 11)(11 11) |(1 1)(0 0)| 0
2914 01:01:54.103891 3 2 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2915 01:01:54.110760 3 2 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2916 01:01:54.114034 3 2 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2917 01:01:54.117464 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2918 01:01:54.123851 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2919 01:01:54.127420 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2920 01:01:54.130742 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2921 01:01:54.137362 3 3 4 |e0e 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2922 01:01:54.140551 3 3 8 |706 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2923 01:01:54.144077 [Byte 0] Lead/lag Transition tap number (1)
2924 01:01:54.147485 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2925 01:01:54.154313 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2926 01:01:54.157195 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2927 01:01:54.160670 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2928 01:01:54.167306 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2929 01:01:54.170828 3 4 0 |303 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2930 01:01:54.173975 3 4 4 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2931 01:01:54.177511 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2932 01:01:54.184179 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2933 01:01:54.187584 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2934 01:01:54.190726 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2935 01:01:54.197320 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2936 01:01:54.200688 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2937 01:01:54.204051 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2938 01:01:54.210915 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2939 01:01:54.214137 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2940 01:01:54.217500 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2941 01:01:54.220881 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2942 01:01:54.227545 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2943 01:01:54.230819 [Byte 0] Lead/lag falling Transition (3, 5, 20)
2944 01:01:54.234269 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2945 01:01:54.240925 3 5 28 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2946 01:01:54.244612 [Byte 0] Lead/lag Transition tap number (3)
2947 01:01:54.247958 [Byte 1] Lead/lag falling Transition (3, 5, 28)
2948 01:01:54.251066 3 6 0 |808 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2949 01:01:54.257808 [Byte 1] Lead/lag Transition tap number (2)
2950 01:01:54.261265 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2951 01:01:54.264409 [Byte 0]First pass (3, 6, 4)
2952 01:01:54.267613 3 6 8 |4646 4646 |(0 0)(10 10) |(0 0)(0 0)| 0
2953 01:01:54.271408 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2954 01:01:54.274498 [Byte 1]First pass (3, 6, 12)
2955 01:01:54.277671 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2956 01:01:54.281189 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2957 01:01:54.284377 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2958 01:01:54.291292 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2959 01:01:54.294824 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2960 01:01:54.298252 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2961 01:01:54.301405 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2962 01:01:54.304859 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2963 01:01:54.311375 All bytes gating window > 1UI, Early break!
2964 01:01:54.311811
2965 01:01:54.314503 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 26)
2966 01:01:54.314936
2967 01:01:54.317929 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 0)
2968 01:01:54.318397
2969 01:01:54.318737
2970 01:01:54.319043
2971 01:01:54.321187 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
2972 01:01:54.321618
2973 01:01:54.324651 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 0)
2974 01:01:54.325080
2975 01:01:54.325412
2976 01:01:54.327853 Write Rank1 MR1 =0x56
2977 01:01:54.328238
2978 01:01:54.331188 best RODT dly(2T, 0.5T) = (2, 2)
2979 01:01:54.331631
2980 01:01:54.334582 best RODT dly(2T, 0.5T) = (2, 3)
2981 01:01:54.335009 ==
2982 01:01:54.338493 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2983 01:01:54.341502 fsp= 1, odt_onoff= 1, Byte mode= 0
2984 01:01:54.341954 ==
2985 01:01:54.347932 Start DQ dly to find pass range UseTestEngine =0
2986 01:01:54.351413 x-axis: bit #, y-axis: DQ dly (-127~63)
2987 01:01:54.351859 RX Vref Scan = 0
2988 01:01:54.354815 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2989 01:01:54.358001 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2990 01:01:54.361709 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2991 01:01:54.364706 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2992 01:01:54.368216 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2993 01:01:54.368746 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2994 01:01:54.371472 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2995 01:01:54.374890 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2996 01:01:54.378334 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2997 01:01:54.381762 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2998 01:01:54.385135 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2999 01:01:54.388778 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3000 01:01:54.391764 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3001 01:01:54.392296 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3002 01:01:54.395064 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3003 01:01:54.398424 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3004 01:01:54.401957 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3005 01:01:54.404926 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3006 01:01:54.408361 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3007 01:01:54.411849 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3008 01:01:54.412284 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3009 01:01:54.414999 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3010 01:01:54.418482 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3011 01:01:54.422007 -3, [0] xxxoxxxx xxxxxxxx [MSB]
3012 01:01:54.425323 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3013 01:01:54.428501 -1, [0] xxooxxxx xxxxxxxo [MSB]
3014 01:01:54.428930 0, [0] xxooxxxx xxoxxxxo [MSB]
3015 01:01:54.432011 1, [0] xxooxxxo oooxxxxo [MSB]
3016 01:01:54.435286 2, [0] xxooxxxo oooxxxxo [MSB]
3017 01:01:54.438520 3, [0] xxoooxxo ooooxooo [MSB]
3018 01:01:54.441743 4, [0] xxoooxxo ooooxooo [MSB]
3019 01:01:54.445146 5, [0] xxoooxxo oooooooo [MSB]
3020 01:01:54.445551 6, [0] xooooxoo oooooooo [MSB]
3021 01:01:54.448465 33, [0] oooxoooo oooooooo [MSB]
3022 01:01:54.451864 34, [0] oooxoooo ooooooox [MSB]
3023 01:01:54.455206 35, [0] ooxxoooo ooooooox [MSB]
3024 01:01:54.458495 36, [0] ooxxoooo oxooooox [MSB]
3025 01:01:54.461763 37, [0] ooxxoooo xxxxooox [MSB]
3026 01:01:54.465048 38, [0] ooxxoooo xxxxooox [MSB]
3027 01:01:54.465575 39, [0] ooxxxoox xxxxooxx [MSB]
3028 01:01:54.468466 40, [0] ooxxxoox xxxxoxxx [MSB]
3029 01:01:54.472084 41, [0] ooxxxoox xxxxxxxx [MSB]
3030 01:01:54.475521 42, [0] ooxxxxox xxxxxxxx [MSB]
3031 01:01:54.479197 43, [0] oxxxxxxx xxxxxxxx [MSB]
3032 01:01:54.481947 44, [0] xxxxxxxx xxxxxxxx [MSB]
3033 01:01:54.485618 iDelay=44, Bit 0, Center 25 (7 ~ 43) 37
3034 01:01:54.488880 iDelay=44, Bit 1, Center 24 (6 ~ 42) 37
3035 01:01:54.492063 iDelay=44, Bit 2, Center 16 (-1 ~ 34) 36
3036 01:01:54.495143 iDelay=44, Bit 3, Center 14 (-3 ~ 32) 36
3037 01:01:54.498630 iDelay=44, Bit 4, Center 20 (3 ~ 38) 36
3038 01:01:54.501703 iDelay=44, Bit 5, Center 24 (7 ~ 41) 35
3039 01:01:54.505130 iDelay=44, Bit 6, Center 24 (6 ~ 42) 37
3040 01:01:54.508487 iDelay=44, Bit 7, Center 19 (1 ~ 38) 38
3041 01:01:54.512024 iDelay=44, Bit 8, Center 18 (1 ~ 36) 36
3042 01:01:54.515436 iDelay=44, Bit 9, Center 18 (1 ~ 35) 35
3043 01:01:54.518813 iDelay=44, Bit 10, Center 18 (0 ~ 36) 37
3044 01:01:54.522485 iDelay=44, Bit 11, Center 19 (3 ~ 36) 34
3045 01:01:54.529205 iDelay=44, Bit 12, Center 22 (5 ~ 40) 36
3046 01:01:54.532040 iDelay=44, Bit 13, Center 21 (3 ~ 39) 37
3047 01:01:54.535694 iDelay=44, Bit 14, Center 20 (3 ~ 38) 36
3048 01:01:54.538812 iDelay=44, Bit 15, Center 15 (-2 ~ 33) 36
3049 01:01:54.539200 ==
3050 01:01:54.542163 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3051 01:01:54.545783 fsp= 1, odt_onoff= 1, Byte mode= 0
3052 01:01:54.546173 ==
3053 01:01:54.549011 DQS Delay:
3054 01:01:54.549398 DQS0 = 0, DQS1 = 0
3055 01:01:54.552139 DQM Delay:
3056 01:01:54.552528 DQM0 = 20, DQM1 = 18
3057 01:01:54.552836 DQ Delay:
3058 01:01:54.555442 DQ0 =25, DQ1 =24, DQ2 =16, DQ3 =14
3059 01:01:54.558658 DQ4 =20, DQ5 =24, DQ6 =24, DQ7 =19
3060 01:01:54.561969 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =19
3061 01:01:54.565500 DQ12 =22, DQ13 =21, DQ14 =20, DQ15 =15
3062 01:01:54.565883
3063 01:01:54.566182
3064 01:01:54.569299 DramC Write-DBI off
3065 01:01:54.569768 ==
3066 01:01:54.575794 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3067 01:01:54.576314 fsp= 1, odt_onoff= 1, Byte mode= 0
3068 01:01:54.578949 ==
3069 01:01:54.582279 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3070 01:01:54.582876
3071 01:01:54.585885 Begin, DQ Scan Range 928~1184
3072 01:01:54.586409
3073 01:01:54.586753
3074 01:01:54.587062 TX Vref Scan disable
3075 01:01:54.589045 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3076 01:01:54.592553 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3077 01:01:54.599178 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3078 01:01:54.602306 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3079 01:01:54.605573 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3080 01:01:54.609261 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3081 01:01:54.612274 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3082 01:01:54.616121 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3083 01:01:54.619063 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3084 01:01:54.622641 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3085 01:01:54.625687 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3086 01:01:54.628904 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3087 01:01:54.632491 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3088 01:01:54.635567 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3089 01:01:54.639373 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3090 01:01:54.642389 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3091 01:01:54.645760 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3092 01:01:54.649045 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3093 01:01:54.652337 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3094 01:01:54.655836 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3095 01:01:54.662662 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3096 01:01:54.665769 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3097 01:01:54.669142 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3098 01:01:54.672460 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3099 01:01:54.675919 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3100 01:01:54.679260 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3101 01:01:54.682799 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3102 01:01:54.686307 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3103 01:01:54.689520 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3104 01:01:54.692795 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3105 01:01:54.696128 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3106 01:01:54.699342 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3107 01:01:54.702676 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3108 01:01:54.705944 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3109 01:01:54.709386 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3110 01:01:54.712548 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3111 01:01:54.715999 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3112 01:01:54.719570 965 |3 6 5|[0] xxxxxxxx xxxxxxxo [MSB]
3113 01:01:54.722563 966 |3 6 6|[0] xxxxxxxx xxxxxxxo [MSB]
3114 01:01:54.726087 967 |3 6 7|[0] xxxxxxxx xxxxxxxo [MSB]
3115 01:01:54.729564 968 |3 6 8|[0] xxxxxxxx xxxxxxxo [MSB]
3116 01:01:54.732825 969 |3 6 9|[0] xxxxxxxx oooxxxxo [MSB]
3117 01:01:54.739388 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB]
3118 01:01:54.742800 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
3119 01:01:54.745971 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
3120 01:01:54.749357 973 |3 6 13|[0] xxooxxxx oooooooo [MSB]
3121 01:01:54.752764 974 |3 6 14|[0] xxoooxxx oooooooo [MSB]
3122 01:01:54.756181 975 |3 6 15|[0] xooooxxo oooooooo [MSB]
3123 01:01:54.763071 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3124 01:01:54.766616 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3125 01:01:54.769809 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3126 01:01:54.772872 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3127 01:01:54.776243 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
3128 01:01:54.779712 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
3129 01:01:54.783078 997 |3 6 37|[0] ooxxoooo xxxxxxxx [MSB]
3130 01:01:54.786365 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
3131 01:01:54.789697 Byte0, DQ PI dly=984, DQM PI dly= 984
3132 01:01:54.792797 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
3133 01:01:54.793308
3134 01:01:54.799799 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
3135 01:01:54.800191
3136 01:01:54.802989 Byte1, DQ PI dly=978, DQM PI dly= 978
3137 01:01:54.806937 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
3138 01:01:54.807408
3139 01:01:54.809678 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
3140 01:01:54.810150
3141 01:01:54.810513 ==
3142 01:01:54.816481 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3143 01:01:54.819740 fsp= 1, odt_onoff= 1, Byte mode= 0
3144 01:01:54.820133 ==
3145 01:01:54.823112 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3146 01:01:54.823501
3147 01:01:54.826518 Begin, DQ Scan Range 954~1018
3148 01:01:54.829706 Write Rank1 MR14 =0x0
3149 01:01:54.837699
3150 01:01:54.838099 CH=1, VrefRange= 0, VrefLevel = 0
3151 01:01:54.844018 TX Bit0 (977~998) 22 987, Bit8 (970~988) 19 979,
3152 01:01:54.847311 TX Bit1 (977~997) 21 987, Bit9 (970~987) 18 978,
3153 01:01:54.854037 TX Bit2 (975~991) 17 983, Bit10 (970~986) 17 978,
3154 01:01:54.857277 TX Bit3 (974~990) 17 982, Bit11 (971~990) 20 980,
3155 01:01:54.860759 TX Bit4 (976~993) 18 984, Bit12 (972~991) 20 981,
3156 01:01:54.867401 TX Bit5 (977~997) 21 987, Bit13 (972~988) 17 980,
3157 01:01:54.870764 TX Bit6 (977~997) 21 987, Bit14 (971~988) 18 979,
3158 01:01:54.874255 TX Bit7 (976~994) 19 985, Bit15 (968~985) 18 976,
3159 01:01:54.874650
3160 01:01:54.877528 Write Rank1 MR14 =0x2
3161 01:01:54.886922
3162 01:01:54.887402 CH=1, VrefRange= 0, VrefLevel = 2
3163 01:01:54.893043 TX Bit0 (977~998) 22 987, Bit8 (970~988) 19 979,
3164 01:01:54.896489 TX Bit1 (977~997) 21 987, Bit9 (970~987) 18 978,
3165 01:01:54.903020 TX Bit2 (974~991) 18 982, Bit10 (971~987) 17 979,
3166 01:01:54.906687 TX Bit3 (974~991) 18 982, Bit11 (971~990) 20 980,
3167 01:01:54.909644 TX Bit4 (976~994) 19 985, Bit12 (972~991) 20 981,
3168 01:01:54.916539 TX Bit5 (977~997) 21 987, Bit13 (971~988) 18 979,
3169 01:01:54.919878 TX Bit6 (977~998) 22 987, Bit14 (971~989) 19 980,
3170 01:01:54.923447 TX Bit7 (976~994) 19 985, Bit15 (968~986) 19 977,
3171 01:01:54.923837
3172 01:01:54.926146 Write Rank1 MR14 =0x4
3173 01:01:54.935223
3174 01:01:54.935303 CH=1, VrefRange= 0, VrefLevel = 4
3175 01:01:54.942117 TX Bit0 (977~998) 22 987, Bit8 (970~989) 20 979,
3176 01:01:54.945644 TX Bit1 (976~997) 22 986, Bit9 (970~989) 20 979,
3177 01:01:54.952060 TX Bit2 (974~992) 19 983, Bit10 (970~988) 19 979,
3178 01:01:54.955530 TX Bit3 (974~991) 18 982, Bit11 (971~990) 20 980,
3179 01:01:54.958758 TX Bit4 (976~994) 19 985, Bit12 (972~991) 20 981,
3180 01:01:54.965813 TX Bit5 (977~998) 22 987, Bit13 (971~989) 19 980,
3181 01:01:54.969177 TX Bit6 (977~998) 22 987, Bit14 (971~990) 20 980,
3182 01:01:54.972192 TX Bit7 (976~995) 20 985, Bit15 (968~987) 20 977,
3183 01:01:54.972593
3184 01:01:54.975470 Write Rank1 MR14 =0x6
3185 01:01:54.984180
3186 01:01:54.984294 CH=1, VrefRange= 0, VrefLevel = 6
3187 01:01:54.990451 TX Bit0 (977~998) 22 987, Bit8 (969~990) 22 979,
3188 01:01:54.993655 TX Bit1 (976~997) 22 986, Bit9 (970~989) 20 979,
3189 01:01:55.000595 TX Bit2 (974~992) 19 983, Bit10 (970~988) 19 979,
3190 01:01:55.004022 TX Bit3 (972~991) 20 981, Bit11 (971~991) 21 981,
3191 01:01:55.007411 TX Bit4 (975~995) 21 985, Bit12 (971~992) 22 981,
3192 01:01:55.013873 TX Bit5 (977~998) 22 987, Bit13 (971~990) 20 980,
3193 01:01:55.017196 TX Bit6 (977~998) 22 987, Bit14 (970~990) 21 980,
3194 01:01:55.020673 TX Bit7 (976~996) 21 986, Bit15 (967~987) 21 977,
3195 01:01:55.020750
3196 01:01:55.023967 Write Rank1 MR14 =0x8
3197 01:01:55.033322
3198 01:01:55.033417 CH=1, VrefRange= 0, VrefLevel = 8
3199 01:01:55.039679 TX Bit0 (977~999) 23 988, Bit8 (969~990) 22 979,
3200 01:01:55.043462 TX Bit1 (976~997) 22 986, Bit9 (969~990) 22 979,
3201 01:01:55.049721 TX Bit2 (973~993) 21 983, Bit10 (970~989) 20 979,
3202 01:01:55.053174 TX Bit3 (972~992) 21 982, Bit11 (970~991) 22 980,
3203 01:01:55.056722 TX Bit4 (975~996) 22 985, Bit12 (971~992) 22 981,
3204 01:01:55.063214 TX Bit5 (977~998) 22 987, Bit13 (971~990) 20 980,
3205 01:01:55.066846 TX Bit6 (977~998) 22 987, Bit14 (970~990) 21 980,
3206 01:01:55.069997 TX Bit7 (976~996) 21 986, Bit15 (967~988) 22 977,
3207 01:01:55.070247
3208 01:01:55.073377 Write Rank1 MR14 =0xa
3209 01:01:55.082621
3210 01:01:55.085919 CH=1, VrefRange= 0, VrefLevel = 10
3211 01:01:55.089210 TX Bit0 (977~999) 23 988, Bit8 (969~991) 23 980,
3212 01:01:55.092436 TX Bit1 (976~997) 22 986, Bit9 (969~990) 22 979,
3213 01:01:55.099351 TX Bit2 (972~993) 22 982, Bit10 (970~990) 21 980,
3214 01:01:55.102614 TX Bit3 (972~993) 22 982, Bit11 (970~992) 23 981,
3215 01:01:55.106078 TX Bit4 (975~996) 22 985, Bit12 (970~992) 23 981,
3216 01:01:55.112274 TX Bit5 (976~998) 23 987, Bit13 (971~991) 21 981,
3217 01:01:55.115734 TX Bit6 (977~998) 22 987, Bit14 (970~991) 22 980,
3218 01:01:55.119415 TX Bit7 (976~997) 22 986, Bit15 (967~988) 22 977,
3219 01:01:55.119942
3220 01:01:55.122400 Write Rank1 MR14 =0xc
3221 01:01:55.131707
3222 01:01:55.135028 CH=1, VrefRange= 0, VrefLevel = 12
3223 01:01:55.138725 TX Bit0 (976~999) 24 987, Bit8 (969~991) 23 980,
3224 01:01:55.141963 TX Bit1 (976~998) 23 987, Bit9 (969~991) 23 980,
3225 01:01:55.148500 TX Bit2 (972~994) 23 983, Bit10 (970~990) 21 980,
3226 01:01:55.151783 TX Bit3 (971~993) 23 982, Bit11 (970~992) 23 981,
3227 01:01:55.155148 TX Bit4 (975~997) 23 986, Bit12 (970~992) 23 981,
3228 01:01:55.162164 TX Bit5 (976~998) 23 987, Bit13 (970~991) 22 980,
3229 01:01:55.165257 TX Bit6 (976~999) 24 987, Bit14 (970~991) 22 980,
3230 01:01:55.168367 TX Bit7 (975~997) 23 986, Bit15 (966~989) 24 977,
3231 01:01:55.168895
3232 01:01:55.171546 Write Rank1 MR14 =0xe
3233 01:01:55.181326
3234 01:01:55.184305 CH=1, VrefRange= 0, VrefLevel = 14
3235 01:01:55.187545 TX Bit0 (976~999) 24 987, Bit8 (969~991) 23 980,
3236 01:01:55.190827 TX Bit1 (976~998) 23 987, Bit9 (969~991) 23 980,
3237 01:01:55.197584 TX Bit2 (972~995) 24 983, Bit10 (969~991) 23 980,
3238 01:01:55.200950 TX Bit3 (971~994) 24 982, Bit11 (970~992) 23 981,
3239 01:01:55.204234 TX Bit4 (974~997) 24 985, Bit12 (971~992) 22 981,
3240 01:01:55.210827 TX Bit5 (976~999) 24 987, Bit13 (970~991) 22 980,
3241 01:01:55.214271 TX Bit6 (976~999) 24 987, Bit14 (970~991) 22 980,
3242 01:01:55.217718 TX Bit7 (975~997) 23 986, Bit15 (966~990) 25 978,
3243 01:01:55.218153
3244 01:01:55.220862 Write Rank1 MR14 =0x10
3245 01:01:55.230087
3246 01:01:55.233302 CH=1, VrefRange= 0, VrefLevel = 16
3247 01:01:55.236705 TX Bit0 (976~999) 24 987, Bit8 (968~991) 24 979,
3248 01:01:55.240298 TX Bit1 (975~998) 24 986, Bit9 (968~991) 24 979,
3249 01:01:55.246959 TX Bit2 (971~996) 26 983, Bit10 (969~991) 23 980,
3250 01:01:55.250332 TX Bit3 (970~994) 25 982, Bit11 (970~992) 23 981,
3251 01:01:55.253456 TX Bit4 (974~997) 24 985, Bit12 (970~992) 23 981,
3252 01:01:55.260294 TX Bit5 (976~999) 24 987, Bit13 (970~991) 22 980,
3253 01:01:55.263592 TX Bit6 (976~999) 24 987, Bit14 (969~991) 23 980,
3254 01:01:55.267061 TX Bit7 (974~997) 24 985, Bit15 (966~990) 25 978,
3255 01:01:55.267455
3256 01:01:55.270193 Write Rank1 MR14 =0x12
3257 01:01:55.279398
3258 01:01:55.282812 CH=1, VrefRange= 0, VrefLevel = 18
3259 01:01:55.285931 TX Bit0 (976~1000) 25 988, Bit8 (968~991) 24 979,
3260 01:01:55.289104 TX Bit1 (975~998) 24 986, Bit9 (968~991) 24 979,
3261 01:01:55.295915 TX Bit2 (971~996) 26 983, Bit10 (968~991) 24 979,
3262 01:01:55.299243 TX Bit3 (970~995) 26 982, Bit11 (969~993) 25 981,
3263 01:01:55.302569 TX Bit4 (973~997) 25 985, Bit12 (970~993) 24 981,
3264 01:01:55.309489 TX Bit5 (976~999) 24 987, Bit13 (969~992) 24 980,
3265 01:01:55.312663 TX Bit6 (976~1000) 25 988, Bit14 (969~992) 24 980,
3266 01:01:55.315772 TX Bit7 (974~997) 24 985, Bit15 (966~990) 25 978,
3267 01:01:55.319160
3268 01:01:55.319235 Write Rank1 MR14 =0x14
3269 01:01:55.328715
3270 01:01:55.328791 CH=1, VrefRange= 0, VrefLevel = 20
3271 01:01:55.335461 TX Bit0 (976~1000) 25 988, Bit8 (968~991) 24 979,
3272 01:01:55.338968 TX Bit1 (975~998) 24 986, Bit9 (968~991) 24 979,
3273 01:01:55.345839 TX Bit2 (971~996) 26 983, Bit10 (968~991) 24 979,
3274 01:01:55.349040 TX Bit3 (970~995) 26 982, Bit11 (969~993) 25 981,
3275 01:01:55.352262 TX Bit4 (973~997) 25 985, Bit12 (970~993) 24 981,
3276 01:01:55.358969 TX Bit5 (976~999) 24 987, Bit13 (969~992) 24 980,
3277 01:01:55.362191 TX Bit6 (976~1000) 25 988, Bit14 (969~992) 24 980,
3278 01:01:55.365599 TX Bit7 (974~997) 24 985, Bit15 (966~990) 25 978,
3279 01:01:55.365677
3280 01:01:55.369181 Write Rank1 MR14 =0x16
3281 01:01:55.378681
3282 01:01:55.381816 CH=1, VrefRange= 0, VrefLevel = 22
3283 01:01:55.385265 TX Bit0 (976~1000) 25 988, Bit8 (968~991) 24 979,
3284 01:01:55.388583 TX Bit1 (975~998) 24 986, Bit9 (968~991) 24 979,
3285 01:01:55.395280 TX Bit2 (971~996) 26 983, Bit10 (968~991) 24 979,
3286 01:01:55.398922 TX Bit3 (970~995) 26 982, Bit11 (969~993) 25 981,
3287 01:01:55.402150 TX Bit4 (973~997) 25 985, Bit12 (970~993) 24 981,
3288 01:01:55.408606 TX Bit5 (976~999) 24 987, Bit13 (969~992) 24 980,
3289 01:01:55.412061 TX Bit6 (976~1000) 25 988, Bit14 (969~992) 24 980,
3290 01:01:55.415381 TX Bit7 (974~997) 24 985, Bit15 (966~990) 25 978,
3291 01:01:55.415459
3292 01:01:55.418771 Write Rank1 MR14 =0x18
3293 01:01:55.428398
3294 01:01:55.431603 CH=1, VrefRange= 0, VrefLevel = 24
3295 01:01:55.435081 TX Bit0 (975~1001) 27 988, Bit8 (968~992) 25 980,
3296 01:01:55.438438 TX Bit1 (975~999) 25 987, Bit9 (968~992) 25 980,
3297 01:01:55.444932 TX Bit2 (970~997) 28 983, Bit10 (968~992) 25 980,
3298 01:01:55.448353 TX Bit3 (970~996) 27 983, Bit11 (969~992) 24 980,
3299 01:01:55.451596 TX Bit4 (972~998) 27 985, Bit12 (969~992) 24 980,
3300 01:01:55.458338 TX Bit5 (975~1000) 26 987, Bit13 (969~992) 24 980,
3301 01:01:55.461642 TX Bit6 (976~1001) 26 988, Bit14 (969~992) 24 980,
3302 01:01:55.465353 TX Bit7 (972~998) 27 985, Bit15 (965~991) 27 978,
3303 01:01:55.468343
3304 01:01:55.468416 Write Rank1 MR14 =0x1a
3305 01:01:55.478092
3306 01:01:55.481307 CH=1, VrefRange= 0, VrefLevel = 26
3307 01:01:55.484861 TX Bit0 (975~1001) 27 988, Bit8 (968~992) 25 980,
3308 01:01:55.488193 TX Bit1 (975~999) 25 987, Bit9 (968~992) 25 980,
3309 01:01:55.494876 TX Bit2 (970~997) 28 983, Bit10 (968~992) 25 980,
3310 01:01:55.498080 TX Bit3 (970~996) 27 983, Bit11 (969~992) 24 980,
3311 01:01:55.501234 TX Bit4 (972~998) 27 985, Bit12 (969~992) 24 980,
3312 01:01:55.508096 TX Bit5 (975~1000) 26 987, Bit13 (969~992) 24 980,
3313 01:01:55.511420 TX Bit6 (976~1001) 26 988, Bit14 (969~992) 24 980,
3314 01:01:55.514782 TX Bit7 (972~998) 27 985, Bit15 (965~991) 27 978,
3315 01:01:55.517954
3316 01:01:55.518031 Write Rank1 MR14 =0x1c
3317 01:01:55.527739
3318 01:01:55.531096 CH=1, VrefRange= 0, VrefLevel = 28
3319 01:01:55.534596 TX Bit0 (975~1001) 27 988, Bit8 (968~992) 25 980,
3320 01:01:55.537708 TX Bit1 (975~999) 25 987, Bit9 (968~992) 25 980,
3321 01:01:55.544847 TX Bit2 (970~997) 28 983, Bit10 (968~992) 25 980,
3322 01:01:55.548041 TX Bit3 (970~996) 27 983, Bit11 (969~992) 24 980,
3323 01:01:55.550999 TX Bit4 (972~998) 27 985, Bit12 (969~992) 24 980,
3324 01:01:55.557793 TX Bit5 (975~1000) 26 987, Bit13 (969~992) 24 980,
3325 01:01:55.561069 TX Bit6 (976~1001) 26 988, Bit14 (969~992) 24 980,
3326 01:01:55.564522 TX Bit7 (972~998) 27 985, Bit15 (965~991) 27 978,
3327 01:01:55.564598
3328 01:01:55.567933 Write Rank1 MR14 =0x1e
3329 01:01:55.577370
3330 01:01:55.580849 CH=1, VrefRange= 0, VrefLevel = 30
3331 01:01:55.584252 TX Bit0 (975~1001) 27 988, Bit8 (968~992) 25 980,
3332 01:01:55.587315 TX Bit1 (975~999) 25 987, Bit9 (968~992) 25 980,
3333 01:01:55.594175 TX Bit2 (970~997) 28 983, Bit10 (968~992) 25 980,
3334 01:01:55.597469 TX Bit3 (970~996) 27 983, Bit11 (969~992) 24 980,
3335 01:01:55.600939 TX Bit4 (972~998) 27 985, Bit12 (969~992) 24 980,
3336 01:01:55.607833 TX Bit5 (975~1000) 26 987, Bit13 (969~992) 24 980,
3337 01:01:55.610867 TX Bit6 (976~1001) 26 988, Bit14 (969~992) 24 980,
3338 01:01:55.614142 TX Bit7 (972~998) 27 985, Bit15 (965~991) 27 978,
3339 01:01:55.617432
3340 01:01:55.617507
3341 01:01:55.620881 TX Vref found, early break! 386< 390
3342 01:01:55.624115 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =753/100 ps
3343 01:01:55.627509 u1DelayCellOfst[0]=6 cells (5 PI)
3344 01:01:55.631067 u1DelayCellOfst[1]=5 cells (4 PI)
3345 01:01:55.634242 u1DelayCellOfst[2]=0 cells (0 PI)
3346 01:01:55.637457 u1DelayCellOfst[3]=0 cells (0 PI)
3347 01:01:55.640879 u1DelayCellOfst[4]=2 cells (2 PI)
3348 01:01:55.640954 u1DelayCellOfst[5]=5 cells (4 PI)
3349 01:01:55.644474 u1DelayCellOfst[6]=6 cells (5 PI)
3350 01:01:55.647659 u1DelayCellOfst[7]=2 cells (2 PI)
3351 01:01:55.650968 Byte0, DQ PI dly=983, DQM PI dly= 985
3352 01:01:55.657484 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
3353 01:01:55.657560
3354 01:01:55.660874 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
3355 01:01:55.660950
3356 01:01:55.664096 u1DelayCellOfst[8]=2 cells (2 PI)
3357 01:01:55.667650 u1DelayCellOfst[9]=2 cells (2 PI)
3358 01:01:55.670741 u1DelayCellOfst[10]=2 cells (2 PI)
3359 01:01:55.674711 u1DelayCellOfst[11]=2 cells (2 PI)
3360 01:01:55.677428 u1DelayCellOfst[12]=2 cells (2 PI)
3361 01:01:55.677504 u1DelayCellOfst[13]=2 cells (2 PI)
3362 01:01:55.680793 u1DelayCellOfst[14]=2 cells (2 PI)
3363 01:01:55.684301 u1DelayCellOfst[15]=0 cells (0 PI)
3364 01:01:55.687518 Byte1, DQ PI dly=978, DQM PI dly= 979
3365 01:01:55.694180 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
3366 01:01:55.694298
3367 01:01:55.697427 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
3368 01:01:55.697527
3369 01:01:55.701076 Write Rank1 MR14 =0x18
3370 01:01:55.701150
3371 01:01:55.701209 Final TX Range 0 Vref 24
3372 01:01:55.701263
3373 01:01:55.707754 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3374 01:01:55.707830
3375 01:01:55.714356 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3376 01:01:55.720986 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3377 01:01:55.728046 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3378 01:01:55.731088 Write Rank1 MR3 =0xb0
3379 01:01:55.734546 DramC Write-DBI on
3380 01:01:55.734622 ==
3381 01:01:55.737857 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3382 01:01:55.741163 fsp= 1, odt_onoff= 1, Byte mode= 0
3383 01:01:55.741239 ==
3384 01:01:55.744525 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3385 01:01:55.744602
3386 01:01:55.747961 Begin, DQ Scan Range 699~763
3387 01:01:55.748047
3388 01:01:55.748106
3389 01:01:55.751165 TX Vref Scan disable
3390 01:01:55.754426 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3391 01:01:55.757948 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3392 01:01:55.761156 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3393 01:01:55.764470 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3394 01:01:55.767975 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3395 01:01:55.771300 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3396 01:01:55.774548 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3397 01:01:55.778193 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3398 01:01:55.781415 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3399 01:01:55.784729 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB]
3400 01:01:55.787904 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
3401 01:01:55.791368 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
3402 01:01:55.794522 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3403 01:01:55.798106 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3404 01:01:55.804855 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3405 01:01:55.808114 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3406 01:01:55.811376 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3407 01:01:55.818359 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3408 01:01:55.821623 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3409 01:01:55.824986 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3410 01:01:55.828317 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3411 01:01:55.831763 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3412 01:01:55.834883 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3413 01:01:55.838359 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3414 01:01:55.841840 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3415 01:01:55.844955 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
3416 01:01:55.848230 Byte0, DQ PI dly=729, DQM PI dly= 729
3417 01:01:55.851827 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 25)
3418 01:01:55.851905
3419 01:01:55.858222 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 25)
3420 01:01:55.858302
3421 01:01:55.861544 Byte1, DQ PI dly=721, DQM PI dly= 721
3422 01:01:55.865391 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17)
3423 01:01:55.865469
3424 01:01:55.868256 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17)
3425 01:01:55.868334
3426 01:01:55.874950 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3427 01:01:55.881575 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3428 01:01:55.891576 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3429 01:01:55.891654 Write Rank1 MR3 =0x30
3430 01:01:55.894905 DramC Write-DBI off
3431 01:01:55.894984
3432 01:01:55.895060 [DATLAT]
3433 01:01:55.898390 Freq=1600, CH1 RK1, use_rxtx_scan=0
3434 01:01:55.898468
3435 01:01:55.901907 DATLAT Default: 0x10
3436 01:01:55.901985 7, 0xFFFF, sum=0
3437 01:01:55.904982 8, 0xFFFF, sum=0
3438 01:01:55.905060 9, 0xFFFF, sum=0
3439 01:01:55.905139 10, 0xFFFF, sum=0
3440 01:01:55.908388 11, 0xFFFF, sum=0
3441 01:01:55.908466 12, 0xFFFF, sum=0
3442 01:01:55.911590 13, 0xFFFF, sum=0
3443 01:01:55.911668 14, 0x0, sum=1
3444 01:01:55.914767 15, 0x0, sum=2
3445 01:01:55.914846 16, 0x0, sum=3
3446 01:01:55.918349 17, 0x0, sum=4
3447 01:01:55.921611 pattern=2 first_step=14 total pass=5 best_step=16
3448 01:01:55.921688 ==
3449 01:01:55.928152 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3450 01:01:55.928248 fsp= 1, odt_onoff= 1, Byte mode= 0
3451 01:01:55.931448 ==
3452 01:01:55.935256 Start DQ dly to find pass range UseTestEngine =1
3453 01:01:55.938168 x-axis: bit #, y-axis: DQ dly (-127~63)
3454 01:01:55.938278 RX Vref Scan = 0
3455 01:01:55.941974 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3456 01:01:55.945105 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3457 01:01:55.948249 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3458 01:01:55.951582 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3459 01:01:55.954760 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3460 01:01:55.958084 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3461 01:01:55.961322 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3462 01:01:55.961401 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3463 01:01:55.964678 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3464 01:01:55.968161 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3465 01:01:55.971259 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3466 01:01:55.974822 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3467 01:01:55.978122 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3468 01:01:55.981492 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3469 01:01:55.984712 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3470 01:01:55.984790 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3471 01:01:55.988100 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3472 01:01:55.991445 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3473 01:01:55.994770 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3474 01:01:55.998504 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3475 01:01:56.001677 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3476 01:01:56.004829 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3477 01:01:56.004909 -4, [0] xxxoxxxx xxxxxxxx [MSB]
3478 01:01:56.008086 -3, [0] xxxoxxxx xxxxxxxx [MSB]
3479 01:01:56.011596 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3480 01:01:56.014864 -1, [0] xxooxxxx xxxxxxxo [MSB]
3481 01:01:56.018542 0, [0] xxooxxxx oxxxxxxo [MSB]
3482 01:01:56.021769 1, [0] xxooxxxx oooxxxxo [MSB]
3483 01:01:56.021848 2, [0] xxooxxxx ooooxxxo [MSB]
3484 01:01:56.024846 3, [0] xxoooxxo ooooxxoo [MSB]
3485 01:01:56.028244 4, [0] xxoooxxo ooooxooo [MSB]
3486 01:01:56.031624 5, [0] xxoooxxo oooooooo [MSB]
3487 01:01:56.034941 6, [0] xooooxxo oooooooo [MSB]
3488 01:01:56.038118 7, [0] xooooooo oooooooo [MSB]
3489 01:01:56.041713 33, [0] oooxoooo ooooooox [MSB]
3490 01:01:56.044988 34, [0] oooxoooo ooooooox [MSB]
3491 01:01:56.048607 35, [0] oooxoooo ooooooox [MSB]
3492 01:01:56.051612 36, [0] ooxxoooo ooxoooox [MSB]
3493 01:01:56.051688 37, [0] ooxxxooo xxxxooxx [MSB]
3494 01:01:56.054900 38, [0] ooxxxoox xxxxooxx [MSB]
3495 01:01:56.058317 39, [0] ooxxxoox xxxxoxxx [MSB]
3496 01:01:56.061593 40, [0] ooxxxoox xxxxxxxx [MSB]
3497 01:01:56.065052 41, [0] ooxxxxox xxxxxxxx [MSB]
3498 01:01:56.068846 42, [0] xxxxxxxx xxxxxxxx [MSB]
3499 01:01:56.071632 iDelay=42, Bit 0, Center 24 (8 ~ 41) 34
3500 01:01:56.075280 iDelay=42, Bit 1, Center 23 (6 ~ 41) 36
3501 01:01:56.078517 iDelay=42, Bit 2, Center 17 (-1 ~ 35) 37
3502 01:01:56.081973 iDelay=42, Bit 3, Center 14 (-4 ~ 32) 37
3503 01:01:56.085184 iDelay=42, Bit 4, Center 19 (3 ~ 36) 34
3504 01:01:56.088440 iDelay=42, Bit 5, Center 23 (7 ~ 40) 34
3505 01:01:56.091748 iDelay=42, Bit 6, Center 24 (7 ~ 41) 35
3506 01:01:56.095325 iDelay=42, Bit 7, Center 20 (3 ~ 37) 35
3507 01:01:56.098296 iDelay=42, Bit 8, Center 18 (0 ~ 36) 37
3508 01:01:56.101735 iDelay=42, Bit 9, Center 18 (1 ~ 36) 36
3509 01:01:56.105060 iDelay=42, Bit 10, Center 18 (1 ~ 35) 35
3510 01:01:56.111856 iDelay=42, Bit 11, Center 19 (2 ~ 36) 35
3511 01:01:56.115192 iDelay=42, Bit 12, Center 22 (5 ~ 39) 35
3512 01:01:56.118420 iDelay=42, Bit 13, Center 21 (4 ~ 38) 35
3513 01:01:56.121758 iDelay=42, Bit 14, Center 19 (3 ~ 36) 34
3514 01:01:56.125271 iDelay=42, Bit 15, Center 15 (-2 ~ 32) 35
3515 01:01:56.125347 ==
3516 01:01:56.128435 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3517 01:01:56.132036 fsp= 1, odt_onoff= 1, Byte mode= 0
3518 01:01:56.132112 ==
3519 01:01:56.135164 DQS Delay:
3520 01:01:56.135239 DQS0 = 0, DQS1 = 0
3521 01:01:56.138582 DQM Delay:
3522 01:01:56.138657 DQM0 = 20, DQM1 = 18
3523 01:01:56.138717 DQ Delay:
3524 01:01:56.141965 DQ0 =24, DQ1 =23, DQ2 =17, DQ3 =14
3525 01:01:56.145458 DQ4 =19, DQ5 =23, DQ6 =24, DQ7 =20
3526 01:01:56.149018 DQ8 =18, DQ9 =18, DQ10 =18, DQ11 =19
3527 01:01:56.152069 DQ12 =22, DQ13 =21, DQ14 =19, DQ15 =15
3528 01:01:56.152167
3529 01:01:56.152252
3530 01:01:56.152332
3531 01:01:56.155436 [DramC_TX_OE_Calibration] TA2
3532 01:01:56.158579 Original DQ_B0 (3 6) =30, OEN = 27
3533 01:01:56.162017 Original DQ_B1 (3 6) =30, OEN = 27
3534 01:01:56.165310 23, 0x0, End_B0=23 End_B1=23
3535 01:01:56.168667 24, 0x0, End_B0=24 End_B1=24
3536 01:01:56.168744 25, 0x0, End_B0=25 End_B1=25
3537 01:01:56.171895 26, 0x0, End_B0=26 End_B1=26
3538 01:01:56.175287 27, 0x0, End_B0=27 End_B1=27
3539 01:01:56.178748 28, 0x0, End_B0=28 End_B1=28
3540 01:01:56.182115 29, 0x0, End_B0=29 End_B1=29
3541 01:01:56.182192 30, 0x0, End_B0=30 End_B1=30
3542 01:01:56.185527 31, 0xFFFF, End_B0=30 End_B1=30
3543 01:01:56.192295 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3544 01:01:56.195347 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3545 01:01:56.198687
3546 01:01:56.198762
3547 01:01:56.198821 Write Rank1 MR23 =0x3f
3548 01:01:56.198876 [DQSOSC]
3549 01:01:56.208501 [DQSOSCAuto] RK1, (LSB)MR18= 0xa5, (MSB)MR19= 0x3, tDQSOscB0 = 337 ps tDQSOscB1 = 0 ps
3550 01:01:56.215434 CH1_RK1: MR19=0x3, MR18=0xA5, DQSOSC=337, MR23=63, INC=21, DEC=32
3551 01:01:56.215511 Write Rank1 MR23 =0x3f
3552 01:01:56.215570 [DQSOSC]
3553 01:01:56.225206 [DQSOSCAuto] RK1, (LSB)MR18= 0xa7, (MSB)MR19= 0x3, tDQSOscB0 = 336 ps tDQSOscB1 = 0 ps
3554 01:01:56.225283 CH1 RK1: MR19=3, MR18=A7
3555 01:01:56.229060 [RxdqsGatingPostProcess] freq 1600
3556 01:01:56.235366 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3557 01:01:56.235442 Rank: 0
3558 01:01:56.238913 best DQS0 dly(2T, 0.5T) = (2, 5)
3559 01:01:56.242097 best DQS1 dly(2T, 0.5T) = (2, 5)
3560 01:01:56.245461 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3561 01:01:56.248808 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
3562 01:01:56.248884 Rank: 1
3563 01:01:56.252226 best DQS0 dly(2T, 0.5T) = (2, 5)
3564 01:01:56.255619 best DQS1 dly(2T, 0.5T) = (2, 6)
3565 01:01:56.258828 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3566 01:01:56.262333 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3567 01:01:56.265508 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3568 01:01:56.268983 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3569 01:01:56.275541 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3570 01:01:56.275617
3571 01:01:56.275677
3572 01:01:56.278882 [Calibration Summary] Freqency 1600
3573 01:01:56.278959 CH 0, Rank 0
3574 01:01:56.279018 All Pass.
3575 01:01:56.279073
3576 01:01:56.282791 CH 0, Rank 1
3577 01:01:56.282866 All Pass.
3578 01:01:56.282925
3579 01:01:56.282979 CH 1, Rank 0
3580 01:01:56.285678 All Pass.
3581 01:01:56.285753
3582 01:01:56.285812 CH 1, Rank 1
3583 01:01:56.285866 All Pass.
3584 01:01:56.285918
3585 01:01:56.292195 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3586 01:01:56.298927 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3587 01:01:56.308885 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3588 01:01:56.308984 Write Rank0 MR3 =0xb0
3589 01:01:56.315760 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3590 01:01:56.322378 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3591 01:01:56.329466 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3592 01:01:56.332395 Write Rank1 MR3 =0xb0
3593 01:01:56.339159 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3594 01:01:56.345740 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3595 01:01:56.352334 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3596 01:01:56.355891 Write Rank0 MR3 =0xb0
3597 01:01:56.362116 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3598 01:01:56.368971 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3599 01:01:56.375585 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3600 01:01:56.375660 Write Rank1 MR3 =0xb0
3601 01:01:56.378746 DramC Write-DBI on
3602 01:01:56.382410 [GetDramInforAfterCalByMRR] Vendor 1.
3603 01:01:56.385485 [GetDramInforAfterCalByMRR] Revision 7.
3604 01:01:56.385560 MR8 12
3605 01:01:56.392171 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3606 01:01:56.392248 MR8 12
3607 01:01:56.395703 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3608 01:01:56.395778 MR8 12
3609 01:01:56.402392 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3610 01:01:56.402468 MR8 12
3611 01:01:56.409126 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3612 01:01:56.415962 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3613 01:01:56.419093 Write Rank0 MR13 =0xd0
3614 01:01:56.419168 Write Rank1 MR13 =0xd0
3615 01:01:56.422198 Write Rank0 MR13 =0xd0
3616 01:01:56.425925 Write Rank1 MR13 =0xd0
3617 01:01:56.429332 Save calibration result to emmc
3618 01:01:56.429407
3619 01:01:56.429466
3620 01:01:56.432718 [DramcModeReg_Check] Freq_1600, FSP_1
3621 01:01:56.432794 FSP_1, CH_0, RK0
3622 01:01:56.435771 Write Rank0 MR13 =0xd8
3623 01:01:56.439424 MR12 = 0x56 (global = 0x56) match
3624 01:01:56.442656 MR14 = 0x16 (global = 0x16) match
3625 01:01:56.442731 FSP_1, CH_0, RK1
3626 01:01:56.445957 Write Rank1 MR13 =0xd8
3627 01:01:56.449158 MR12 = 0x56 (global = 0x56) match
3628 01:01:56.452757 MR14 = 0x14 (global = 0x14) match
3629 01:01:56.452857 FSP_1, CH_1, RK0
3630 01:01:56.456094 Write Rank0 MR13 =0xd8
3631 01:01:56.459244 MR12 = 0x56 (global = 0x56) match
3632 01:01:56.462760 MR14 = 0x16 (global = 0x16) match
3633 01:01:56.462838 FSP_1, CH_1, RK1
3634 01:01:56.466301 Write Rank1 MR13 =0xd8
3635 01:01:56.469200 MR12 = 0x56 (global = 0x56) match
3636 01:01:56.472848 MR14 = 0x18 (global = 0x18) match
3637 01:01:56.472926
3638 01:01:56.475980 [MEM_TEST] 02: After DFS, before run time config
3639 01:01:56.486482 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3640 01:01:56.486560
3641 01:01:56.486637 [TA2_TEST]
3642 01:01:56.486709 === TA2 HW
3643 01:01:56.489751 TA2 PAT: XTALK
3644 01:01:56.493219 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3645 01:01:56.500041 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3646 01:01:56.503275 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3647 01:01:56.506536 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3648 01:01:56.506614
3649 01:01:56.509910
3650 01:01:56.509987 Settings after calibration
3651 01:01:56.510080
3652 01:01:56.513295 [DramcRunTimeConfig]
3653 01:01:56.516562 TransferPLLToSPMControl - MODE SW PHYPLL
3654 01:01:56.516675 TX_TRACKING: ON
3655 01:01:56.520214 RX_TRACKING: ON
3656 01:01:56.520289 HW_GATING: ON
3657 01:01:56.523299 HW_GATING DBG: OFF
3658 01:01:56.523374 ddr_geometry:1
3659 01:01:56.526943 ddr_geometry:1
3660 01:01:56.527018 ddr_geometry:1
3661 01:01:56.527076 ddr_geometry:1
3662 01:01:56.530072 ddr_geometry:1
3663 01:01:56.530170 ddr_geometry:1
3664 01:01:56.533318 ddr_geometry:1
3665 01:01:56.533393 ddr_geometry:1
3666 01:01:56.536542 High Freq DUMMY_READ_FOR_TRACKING: ON
3667 01:01:56.540336 ZQCS_ENABLE_LP4: OFF
3668 01:01:56.543204 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3669 01:01:56.546544 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3670 01:01:56.546619 SPM_CONTROL_AFTERK: ON
3671 01:01:56.549763 IMPEDANCE_TRACKING: ON
3672 01:01:56.549838 TEMP_SENSOR: ON
3673 01:01:56.553291 PER_BANK_REFRESH: ON
3674 01:01:56.553366 HW_SAVE_FOR_SR: ON
3675 01:01:56.556593 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3676 01:01:56.559791 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3677 01:01:56.563095 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3678 01:01:56.566645 Read ODT Tracking: ON
3679 01:01:56.570026 =========================
3680 01:01:56.570101
3681 01:01:56.570158 [TA2_TEST]
3682 01:01:56.570219 === TA2 HW
3683 01:01:56.576836 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3684 01:01:56.580145 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3685 01:01:56.586911 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3686 01:01:56.590069 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3687 01:01:56.590167
3688 01:01:56.593209 [MEM_TEST] 03: After run time config
3689 01:01:56.604600 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3690 01:01:56.607612 [complex_mem_test] start addr:0x40024000, len:131072
3691 01:01:56.812246 1st complex R/W mem test pass
3692 01:01:56.819380 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3693 01:01:56.822178 sync preloader write leveling
3694 01:01:56.825617 sync preloader cbt_mr12
3695 01:01:56.828806 sync preloader cbt_clk_dly
3696 01:01:56.829310 sync preloader cbt_cmd_dly
3697 01:01:56.832889 sync preloader cbt_cs
3698 01:01:56.835884 sync preloader cbt_ca_perbit_delay
3699 01:01:56.836272 sync preloader clk_delay
3700 01:01:56.839230 sync preloader dqs_delay
3701 01:01:56.842435 sync preloader u1Gating2T_Save
3702 01:01:56.845816 sync preloader u1Gating05T_Save
3703 01:01:56.849187 sync preloader u1Gatingfine_tune_Save
3704 01:01:56.852536 sync preloader u1Gatingucpass_count_Save
3705 01:01:56.855954 sync preloader u1TxWindowPerbitVref_Save
3706 01:01:56.859071 sync preloader u1TxCenter_min_Save
3707 01:01:56.862650 sync preloader u1TxCenter_max_Save
3708 01:01:56.865784 sync preloader u1Txwin_center_Save
3709 01:01:56.869004 sync preloader u1Txfirst_pass_Save
3710 01:01:56.869390 sync preloader u1Txlast_pass_Save
3711 01:01:56.872480 sync preloader u1RxDatlat_Save
3712 01:01:56.875910 sync preloader u1RxWinPerbitVref_Save
3713 01:01:56.882356 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3714 01:01:56.886037 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3715 01:01:56.889245 sync preloader delay_cell_unit
3716 01:01:56.895942 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3717 01:01:56.896336 sync preloader write leveling
3718 01:01:56.899096 sync preloader cbt_mr12
3719 01:01:56.902450 sync preloader cbt_clk_dly
3720 01:01:56.905963 sync preloader cbt_cmd_dly
3721 01:01:56.906396 sync preloader cbt_cs
3722 01:01:56.909101 sync preloader cbt_ca_perbit_delay
3723 01:01:56.912446 sync preloader clk_delay
3724 01:01:56.912829 sync preloader dqs_delay
3725 01:01:56.915923 sync preloader u1Gating2T_Save
3726 01:01:56.919338 sync preloader u1Gating05T_Save
3727 01:01:56.922688 sync preloader u1Gatingfine_tune_Save
3728 01:01:56.925869 sync preloader u1Gatingucpass_count_Save
3729 01:01:56.929406 sync preloader u1TxWindowPerbitVref_Save
3730 01:01:56.932629 sync preloader u1TxCenter_min_Save
3731 01:01:56.936083 sync preloader u1TxCenter_max_Save
3732 01:01:56.939627 sync preloader u1Txwin_center_Save
3733 01:01:56.942537 sync preloader u1Txfirst_pass_Save
3734 01:01:56.945826 sync preloader u1Txlast_pass_Save
3735 01:01:56.949341 sync preloader u1RxDatlat_Save
3736 01:01:56.952742 sync preloader u1RxWinPerbitVref_Save
3737 01:01:56.955792 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3738 01:01:56.959100 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3739 01:01:56.962483 sync preloader delay_cell_unit
3740 01:01:56.969036 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
3741 01:01:56.972868 sync preloader write leveling
3742 01:01:56.976136 sync preloader cbt_mr12
3743 01:01:56.976524 sync preloader cbt_clk_dly
3744 01:01:56.979074 sync preloader cbt_cmd_dly
3745 01:01:56.982472 sync preloader cbt_cs
3746 01:01:56.985828 sync preloader cbt_ca_perbit_delay
3747 01:01:56.986257 sync preloader clk_delay
3748 01:01:56.989108 sync preloader dqs_delay
3749 01:01:56.992554 sync preloader u1Gating2T_Save
3750 01:01:56.996098 sync preloader u1Gating05T_Save
3751 01:01:56.999080 sync preloader u1Gatingfine_tune_Save
3752 01:01:57.002706 sync preloader u1Gatingucpass_count_Save
3753 01:01:57.006130 sync preloader u1TxWindowPerbitVref_Save
3754 01:01:57.009577 sync preloader u1TxCenter_min_Save
3755 01:01:57.012551 sync preloader u1TxCenter_max_Save
3756 01:01:57.015545 sync preloader u1Txwin_center_Save
3757 01:01:57.015621 sync preloader u1Txfirst_pass_Save
3758 01:01:57.019043 sync preloader u1Txlast_pass_Save
3759 01:01:57.022222 sync preloader u1RxDatlat_Save
3760 01:01:57.025956 sync preloader u1RxWinPerbitVref_Save
3761 01:01:57.028871 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3762 01:01:57.035761 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3763 01:01:57.035836 sync preloader delay_cell_unit
3764 01:01:57.042576 just_for_test_dump_coreboot_params dump all params
3765 01:01:57.042663 dump source = 0x0
3766 01:01:57.045670 dump params frequency:1600
3767 01:01:57.049316 dump params rank number:2
3768 01:01:57.049410
3769 01:01:57.049481 dump params write leveling
3770 01:01:57.052638 write leveling[0][0][0] = 0x21
3771 01:01:57.055879 write leveling[0][0][1] = 0x1c
3772 01:01:57.059282 write leveling[0][1][0] = 0x22
3773 01:01:57.062527 write leveling[0][1][1] = 0x1e
3774 01:01:57.065994 write leveling[1][0][0] = 0x24
3775 01:01:57.066133 write leveling[1][0][1] = 0x21
3776 01:01:57.069621 write leveling[1][1][0] = 0x24
3777 01:01:57.072547 write leveling[1][1][1] = 0x20
3778 01:01:57.076116 dump params cbt_cs
3779 01:01:57.076300 cbt_cs[0][0] = 0x8
3780 01:01:57.079489 cbt_cs[0][1] = 0x8
3781 01:01:57.079677 cbt_cs[1][0] = 0xb
3782 01:01:57.082601 cbt_cs[1][1] = 0xb
3783 01:01:57.082821 dump params cbt_mr12
3784 01:01:57.086288 cbt_mr12[0][0] = 0x16
3785 01:01:57.086591 cbt_mr12[0][1] = 0x16
3786 01:01:57.089613 cbt_mr12[1][0] = 0x16
3787 01:01:57.093358 cbt_mr12[1][1] = 0x16
3788 01:01:57.093794 dump params tx window
3789 01:01:57.096567 tx_center_min[0][0][0] = 979
3790 01:01:57.100026 tx_center_max[0][0][0] = 987
3791 01:01:57.103126 tx_center_min[0][0][1] = 974
3792 01:01:57.103519 tx_center_max[0][0][1] = 979
3793 01:01:57.106501 tx_center_min[0][1][0] = 981
3794 01:01:57.109906 tx_center_max[0][1][0] = 988
3795 01:01:57.113007 tx_center_min[0][1][1] = 978
3796 01:01:57.113433 tx_center_max[0][1][1] = 983
3797 01:01:57.116356 tx_center_min[1][0][0] = 982
3798 01:01:57.119736 tx_center_max[1][0][0] = 987
3799 01:01:57.123125 tx_center_min[1][0][1] = 980
3800 01:01:57.126525 tx_center_max[1][0][1] = 983
3801 01:01:57.126956 tx_center_min[1][1][0] = 983
3802 01:01:57.129655 tx_center_max[1][1][0] = 988
3803 01:01:57.133030 tx_center_min[1][1][1] = 978
3804 01:01:57.136353 tx_center_max[1][1][1] = 980
3805 01:01:57.136746 dump params tx window
3806 01:01:57.140016 tx_win_center[0][0][0] = 987
3807 01:01:57.143082 tx_first_pass[0][0][0] = 976
3808 01:01:57.146403 tx_last_pass[0][0][0] = 999
3809 01:01:57.146879 tx_win_center[0][0][1] = 986
3810 01:01:57.150063 tx_first_pass[0][0][1] = 975
3811 01:01:57.153196 tx_last_pass[0][0][1] = 998
3812 01:01:57.156325 tx_win_center[0][0][2] = 986
3813 01:01:57.159646 tx_first_pass[0][0][2] = 974
3814 01:01:57.160037 tx_last_pass[0][0][2] = 998
3815 01:01:57.162812 tx_win_center[0][0][3] = 979
3816 01:01:57.166434 tx_first_pass[0][0][3] = 967
3817 01:01:57.169665 tx_last_pass[0][0][3] = 992
3818 01:01:57.170054 tx_win_center[0][0][4] = 986
3819 01:01:57.173080 tx_first_pass[0][0][4] = 974
3820 01:01:57.176509 tx_last_pass[0][0][4] = 999
3821 01:01:57.180095 tx_win_center[0][0][5] = 981
3822 01:01:57.183155 tx_first_pass[0][0][5] = 969
3823 01:01:57.183548 tx_last_pass[0][0][5] = 993
3824 01:01:57.186437 tx_win_center[0][0][6] = 982
3825 01:01:57.189845 tx_first_pass[0][0][6] = 970
3826 01:01:57.193641 tx_last_pass[0][0][6] = 995
3827 01:01:57.194030 tx_win_center[0][0][7] = 983
3828 01:01:57.196436 tx_first_pass[0][0][7] = 971
3829 01:01:57.199931 tx_last_pass[0][0][7] = 996
3830 01:01:57.203246 tx_win_center[0][0][8] = 974
3831 01:01:57.206536 tx_first_pass[0][0][8] = 961
3832 01:01:57.206925 tx_last_pass[0][0][8] = 987
3833 01:01:57.210129 tx_win_center[0][0][9] = 976
3834 01:01:57.213144 tx_first_pass[0][0][9] = 964
3835 01:01:57.216341 tx_last_pass[0][0][9] = 988
3836 01:01:57.216728 tx_win_center[0][0][10] = 979
3837 01:01:57.219860 tx_first_pass[0][0][10] = 967
3838 01:01:57.223056 tx_last_pass[0][0][10] = 991
3839 01:01:57.226433 tx_win_center[0][0][11] = 975
3840 01:01:57.229568 tx_first_pass[0][0][11] = 962
3841 01:01:57.229969 tx_last_pass[0][0][11] = 988
3842 01:01:57.233170 tx_win_center[0][0][12] = 976
3843 01:01:57.236201 tx_first_pass[0][0][12] = 963
3844 01:01:57.239856 tx_last_pass[0][0][12] = 989
3845 01:01:57.243295 tx_win_center[0][0][13] = 975
3846 01:01:57.243711 tx_first_pass[0][0][13] = 963
3847 01:01:57.246431 tx_last_pass[0][0][13] = 987
3848 01:01:57.249836 tx_win_center[0][0][14] = 976
3849 01:01:57.253161 tx_first_pass[0][0][14] = 963
3850 01:01:57.256176 tx_last_pass[0][0][14] = 989
3851 01:01:57.256254 tx_win_center[0][0][15] = 978
3852 01:01:57.259588 tx_first_pass[0][0][15] = 966
3853 01:01:57.262977 tx_last_pass[0][0][15] = 990
3854 01:01:57.266153 tx_win_center[0][1][0] = 988
3855 01:01:57.269428 tx_first_pass[0][1][0] = 976
3856 01:01:57.269506 tx_last_pass[0][1][0] = 1001
3857 01:01:57.272706 tx_win_center[0][1][1] = 987
3858 01:01:57.275997 tx_first_pass[0][1][1] = 976
3859 01:01:57.279332 tx_last_pass[0][1][1] = 999
3860 01:01:57.279409 tx_win_center[0][1][2] = 987
3861 01:01:57.282668 tx_first_pass[0][1][2] = 976
3862 01:01:57.286470 tx_last_pass[0][1][2] = 999
3863 01:01:57.289496 tx_win_center[0][1][3] = 981
3864 01:01:57.292989 tx_first_pass[0][1][3] = 969
3865 01:01:57.293068 tx_last_pass[0][1][3] = 993
3866 01:01:57.296191 tx_win_center[0][1][4] = 987
3867 01:01:57.299365 tx_first_pass[0][1][4] = 975
3868 01:01:57.302794 tx_last_pass[0][1][4] = 1000
3869 01:01:57.302872 tx_win_center[0][1][5] = 982
3870 01:01:57.306020 tx_first_pass[0][1][5] = 970
3871 01:01:57.309544 tx_last_pass[0][1][5] = 994
3872 01:01:57.312796 tx_win_center[0][1][6] = 983
3873 01:01:57.316168 tx_first_pass[0][1][6] = 971
3874 01:01:57.316245 tx_last_pass[0][1][6] = 996
3875 01:01:57.319903 tx_win_center[0][1][7] = 986
3876 01:01:57.323027 tx_first_pass[0][1][7] = 975
3877 01:01:57.326476 tx_last_pass[0][1][7] = 997
3878 01:01:57.326553 tx_win_center[0][1][8] = 978
3879 01:01:57.329452 tx_first_pass[0][1][8] = 966
3880 01:01:57.333420 tx_last_pass[0][1][8] = 990
3881 01:01:57.336169 tx_win_center[0][1][9] = 979
3882 01:01:57.339770 tx_first_pass[0][1][9] = 967
3883 01:01:57.339848 tx_last_pass[0][1][9] = 991
3884 01:01:57.343163 tx_win_center[0][1][10] = 983
3885 01:01:57.346527 tx_first_pass[0][1][10] = 972
3886 01:01:57.349941 tx_last_pass[0][1][10] = 994
3887 01:01:57.350019 tx_win_center[0][1][11] = 978
3888 01:01:57.353285 tx_first_pass[0][1][11] = 966
3889 01:01:57.356392 tx_last_pass[0][1][11] = 990
3890 01:01:57.359710 tx_win_center[0][1][12] = 979
3891 01:01:57.362969 tx_first_pass[0][1][12] = 967
3892 01:01:57.363047 tx_last_pass[0][1][12] = 991
3893 01:01:57.366744 tx_win_center[0][1][13] = 978
3894 01:01:57.369925 tx_first_pass[0][1][13] = 967
3895 01:01:57.373301 tx_last_pass[0][1][13] = 990
3896 01:01:57.376235 tx_win_center[0][1][14] = 979
3897 01:01:57.376310 tx_first_pass[0][1][14] = 967
3898 01:01:57.380036 tx_last_pass[0][1][14] = 991
3899 01:01:57.383171 tx_win_center[0][1][15] = 981
3900 01:01:57.386473 tx_first_pass[0][1][15] = 969
3901 01:01:57.389835 tx_last_pass[0][1][15] = 993
3902 01:01:57.389911 tx_win_center[1][0][0] = 987
3903 01:01:57.393184 tx_first_pass[1][0][0] = 976
3904 01:01:57.396419 tx_last_pass[1][0][0] = 999
3905 01:01:57.399717 tx_win_center[1][0][1] = 987
3906 01:01:57.403304 tx_first_pass[1][0][1] = 976
3907 01:01:57.403380 tx_last_pass[1][0][1] = 998
3908 01:01:57.406342 tx_win_center[1][0][2] = 984
3909 01:01:57.409699 tx_first_pass[1][0][2] = 973
3910 01:01:57.413106 tx_last_pass[1][0][2] = 995
3911 01:01:57.413182 tx_win_center[1][0][3] = 982
3912 01:01:57.416268 tx_first_pass[1][0][3] = 970
3913 01:01:57.419844 tx_last_pass[1][0][3] = 994
3914 01:01:57.423108 tx_win_center[1][0][4] = 985
3915 01:01:57.426409 tx_first_pass[1][0][4] = 974
3916 01:01:57.426484 tx_last_pass[1][0][4] = 997
3917 01:01:57.429590 tx_win_center[1][0][5] = 987
3918 01:01:57.432968 tx_first_pass[1][0][5] = 976
3919 01:01:57.436297 tx_last_pass[1][0][5] = 999
3920 01:01:57.436372 tx_win_center[1][0][6] = 987
3921 01:01:57.439612 tx_first_pass[1][0][6] = 976
3922 01:01:57.443411 tx_last_pass[1][0][6] = 999
3923 01:01:57.446331 tx_win_center[1][0][7] = 985
3924 01:01:57.446407 tx_first_pass[1][0][7] = 974
3925 01:01:57.449611 tx_last_pass[1][0][7] = 997
3926 01:01:57.453397 tx_win_center[1][0][8] = 980
3927 01:01:57.456835 tx_first_pass[1][0][8] = 969
3928 01:01:57.459765 tx_last_pass[1][0][8] = 992
3929 01:01:57.459840 tx_win_center[1][0][9] = 980
3930 01:01:57.463059 tx_first_pass[1][0][9] = 969
3931 01:01:57.466487 tx_last_pass[1][0][9] = 992
3932 01:01:57.469945 tx_win_center[1][0][10] = 981
3933 01:01:57.472917 tx_first_pass[1][0][10] = 969
3934 01:01:57.472993 tx_last_pass[1][0][10] = 993
3935 01:01:57.476706 tx_win_center[1][0][11] = 982
3936 01:01:57.479820 tx_first_pass[1][0][11] = 970
3937 01:01:57.483418 tx_last_pass[1][0][11] = 994
3938 01:01:57.483493 tx_win_center[1][0][12] = 983
3939 01:01:57.486612 tx_first_pass[1][0][12] = 971
3940 01:01:57.490019 tx_last_pass[1][0][12] = 995
3941 01:01:57.493286 tx_win_center[1][0][13] = 982
3942 01:01:57.496614 tx_first_pass[1][0][13] = 971
3943 01:01:57.496690 tx_last_pass[1][0][13] = 994
3944 01:01:57.499843 tx_win_center[1][0][14] = 981
3945 01:01:57.503263 tx_first_pass[1][0][14] = 970
3946 01:01:57.506487 tx_last_pass[1][0][14] = 993
3947 01:01:57.509862 tx_win_center[1][0][15] = 980
3948 01:01:57.509937 tx_first_pass[1][0][15] = 968
3949 01:01:57.513335 tx_last_pass[1][0][15] = 992
3950 01:01:57.516518 tx_win_center[1][1][0] = 988
3951 01:01:57.520051 tx_first_pass[1][1][0] = 975
3952 01:01:57.523458 tx_last_pass[1][1][0] = 1001
3953 01:01:57.523534 tx_win_center[1][1][1] = 987
3954 01:01:57.527139 tx_first_pass[1][1][1] = 975
3955 01:01:57.530526 tx_last_pass[1][1][1] = 999
3956 01:01:57.534108 tx_win_center[1][1][2] = 983
3957 01:01:57.534654 tx_first_pass[1][1][2] = 970
3958 01:01:57.537215 tx_last_pass[1][1][2] = 997
3959 01:01:57.540472 tx_win_center[1][1][3] = 983
3960 01:01:57.543682 tx_first_pass[1][1][3] = 970
3961 01:01:57.547166 tx_last_pass[1][1][3] = 996
3962 01:01:57.547596 tx_win_center[1][1][4] = 985
3963 01:01:57.550314 tx_first_pass[1][1][4] = 972
3964 01:01:57.554083 tx_last_pass[1][1][4] = 998
3965 01:01:57.557096 tx_win_center[1][1][5] = 987
3966 01:01:57.557530 tx_first_pass[1][1][5] = 975
3967 01:01:57.560787 tx_last_pass[1][1][5] = 1000
3968 01:01:57.564210 tx_win_center[1][1][6] = 988
3969 01:01:57.567417 tx_first_pass[1][1][6] = 976
3970 01:01:57.570869 tx_last_pass[1][1][6] = 1001
3971 01:01:57.571301 tx_win_center[1][1][7] = 985
3972 01:01:57.574209 tx_first_pass[1][1][7] = 972
3973 01:01:57.577633 tx_last_pass[1][1][7] = 998
3974 01:01:57.580753 tx_win_center[1][1][8] = 980
3975 01:01:57.581265 tx_first_pass[1][1][8] = 968
3976 01:01:57.584446 tx_last_pass[1][1][8] = 992
3977 01:01:57.587738 tx_win_center[1][1][9] = 980
3978 01:01:57.590824 tx_first_pass[1][1][9] = 968
3979 01:01:57.594361 tx_last_pass[1][1][9] = 992
3980 01:01:57.594874 tx_win_center[1][1][10] = 980
3981 01:01:57.597583 tx_first_pass[1][1][10] = 968
3982 01:01:57.600591 tx_last_pass[1][1][10] = 992
3983 01:01:57.604233 tx_win_center[1][1][11] = 980
3984 01:01:57.607456 tx_first_pass[1][1][11] = 969
3985 01:01:57.607894 tx_last_pass[1][1][11] = 992
3986 01:01:57.611025 tx_win_center[1][1][12] = 980
3987 01:01:57.614055 tx_first_pass[1][1][12] = 969
3988 01:01:57.617420 tx_last_pass[1][1][12] = 992
3989 01:01:57.620647 tx_win_center[1][1][13] = 980
3990 01:01:57.621102 tx_first_pass[1][1][13] = 969
3991 01:01:57.624207 tx_last_pass[1][1][13] = 992
3992 01:01:57.627401 tx_win_center[1][1][14] = 980
3993 01:01:57.630773 tx_first_pass[1][1][14] = 969
3994 01:01:57.633956 tx_last_pass[1][1][14] = 992
3995 01:01:57.634441 tx_win_center[1][1][15] = 978
3996 01:01:57.637325 tx_first_pass[1][1][15] = 965
3997 01:01:57.640577 tx_last_pass[1][1][15] = 991
3998 01:01:57.644465 dump params rx window
3999 01:01:57.644899 rx_firspass[0][0][0] = 8
4000 01:01:57.647332 rx_lastpass[0][0][0] = 40
4001 01:01:57.650909 rx_firspass[0][0][1] = 7
4002 01:01:57.651370 rx_lastpass[0][0][1] = 39
4003 01:01:57.654530 rx_firspass[0][0][2] = 9
4004 01:01:57.657254 rx_lastpass[0][0][2] = 38
4005 01:01:57.657685 rx_firspass[0][0][3] = -4
4006 01:01:57.660842 rx_lastpass[0][0][3] = 28
4007 01:01:57.663985 rx_firspass[0][0][4] = 6
4008 01:01:57.667369 rx_lastpass[0][0][4] = 38
4009 01:01:57.667801 rx_firspass[0][0][5] = 0
4010 01:01:57.670784 rx_lastpass[0][0][5] = 30
4011 01:01:57.674368 rx_firspass[0][0][6] = 1
4012 01:01:57.674875 rx_lastpass[0][0][6] = 32
4013 01:01:57.677671 rx_firspass[0][0][7] = 4
4014 01:01:57.680777 rx_lastpass[0][0][7] = 32
4015 01:01:57.681206 rx_firspass[0][0][8] = 0
4016 01:01:57.684516 rx_lastpass[0][0][8] = 34
4017 01:01:57.688067 rx_firspass[0][0][9] = 4
4018 01:01:57.688574 rx_lastpass[0][0][9] = 34
4019 01:01:57.691233 rx_firspass[0][0][10] = 7
4020 01:01:57.694299 rx_lastpass[0][0][10] = 37
4021 01:01:57.697557 rx_firspass[0][0][11] = 1
4022 01:01:57.698056 rx_lastpass[0][0][11] = 34
4023 01:01:57.701407 rx_firspass[0][0][12] = 2
4024 01:01:57.704638 rx_lastpass[0][0][12] = 36
4025 01:01:57.705142 rx_firspass[0][0][13] = 2
4026 01:01:57.707549 rx_lastpass[0][0][13] = 30
4027 01:01:57.711102 rx_firspass[0][0][14] = 0
4028 01:01:57.714663 rx_lastpass[0][0][14] = 35
4029 01:01:57.715093 rx_firspass[0][0][15] = 3
4030 01:01:57.717738 rx_lastpass[0][0][15] = 36
4031 01:01:57.720805 rx_firspass[0][1][0] = 7
4032 01:01:57.724589 rx_lastpass[0][1][0] = 41
4033 01:01:57.725103 rx_firspass[0][1][1] = 5
4034 01:01:57.727972 rx_lastpass[0][1][1] = 40
4035 01:01:57.731178 rx_firspass[0][1][2] = 7
4036 01:01:57.731632 rx_lastpass[0][1][2] = 39
4037 01:01:57.734474 rx_firspass[0][1][3] = -4
4038 01:01:57.737814 rx_lastpass[0][1][3] = 31
4039 01:01:57.738355 rx_firspass[0][1][4] = 7
4040 01:01:57.740972 rx_lastpass[0][1][4] = 40
4041 01:01:57.744511 rx_firspass[0][1][5] = -1
4042 01:01:57.747885 rx_lastpass[0][1][5] = 33
4043 01:01:57.748535 rx_firspass[0][1][6] = 2
4044 01:01:57.750929 rx_lastpass[0][1][6] = 34
4045 01:01:57.754504 rx_firspass[0][1][7] = 3
4046 01:01:57.754935 rx_lastpass[0][1][7] = 34
4047 01:01:57.757730 rx_firspass[0][1][8] = 0
4048 01:01:57.760963 rx_lastpass[0][1][8] = 35
4049 01:01:57.761450 rx_firspass[0][1][9] = 3
4050 01:01:57.764575 rx_lastpass[0][1][9] = 35
4051 01:01:57.767871 rx_firspass[0][1][10] = 6
4052 01:01:57.771185 rx_lastpass[0][1][10] = 39
4053 01:01:57.771616 rx_firspass[0][1][11] = 0
4054 01:01:57.774420 rx_lastpass[0][1][11] = 34
4055 01:01:57.777761 rx_firspass[0][1][12] = 3
4056 01:01:57.778446 rx_lastpass[0][1][12] = 36
4057 01:01:57.781125 rx_firspass[0][1][13] = 2
4058 01:01:57.784764 rx_lastpass[0][1][13] = 33
4059 01:01:57.787956 rx_firspass[0][1][14] = 1
4060 01:01:57.788494 rx_lastpass[0][1][14] = 34
4061 01:01:57.791052 rx_firspass[0][1][15] = 3
4062 01:01:57.794004 rx_lastpass[0][1][15] = 37
4063 01:01:57.794080 rx_firspass[1][0][0] = 7
4064 01:01:57.797402 rx_lastpass[1][0][0] = 39
4065 01:01:57.800788 rx_firspass[1][0][1] = 6
4066 01:01:57.804385 rx_lastpass[1][0][1] = 39
4067 01:01:57.804461 rx_firspass[1][0][2] = 0
4068 01:01:57.807827 rx_lastpass[1][0][2] = 34
4069 01:01:57.811247 rx_firspass[1][0][3] = -3
4070 01:01:57.811634 rx_lastpass[1][0][3] = 32
4071 01:01:57.814837 rx_firspass[1][0][4] = 3
4072 01:01:57.817958 rx_lastpass[1][0][4] = 34
4073 01:01:57.818407 rx_firspass[1][0][5] = 9
4074 01:01:57.821191 rx_lastpass[1][0][5] = 40
4075 01:01:57.824442 rx_firspass[1][0][6] = 9
4076 01:01:57.827820 rx_lastpass[1][0][6] = 40
4077 01:01:57.828210 rx_firspass[1][0][7] = 4
4078 01:01:57.831090 rx_lastpass[1][0][7] = 35
4079 01:01:57.834485 rx_firspass[1][0][8] = 0
4080 01:01:57.834873 rx_lastpass[1][0][8] = 35
4081 01:01:57.837635 rx_firspass[1][0][9] = 1
4082 01:01:57.841246 rx_lastpass[1][0][9] = 35
4083 01:01:57.841700 rx_firspass[1][0][10] = 2
4084 01:01:57.844579 rx_lastpass[1][0][10] = 33
4085 01:01:57.848010 rx_firspass[1][0][11] = 1
4086 01:01:57.851161 rx_lastpass[1][0][11] = 36
4087 01:01:57.851554 rx_firspass[1][0][12] = 3
4088 01:01:57.854754 rx_lastpass[1][0][12] = 37
4089 01:01:57.857791 rx_firspass[1][0][13] = 3
4090 01:01:57.858195 rx_lastpass[1][0][13] = 35
4091 01:01:57.861422 rx_firspass[1][0][14] = 3
4092 01:01:57.864933 rx_lastpass[1][0][14] = 35
4093 01:01:57.868393 rx_firspass[1][0][15] = -2
4094 01:01:57.868862 rx_lastpass[1][0][15] = 30
4095 01:01:57.871297 rx_firspass[1][1][0] = 8
4096 01:01:57.874721 rx_lastpass[1][1][0] = 41
4097 01:01:57.875133 rx_firspass[1][1][1] = 6
4098 01:01:57.878015 rx_lastpass[1][1][1] = 41
4099 01:01:57.881194 rx_firspass[1][1][2] = -1
4100 01:01:57.884611 rx_lastpass[1][1][2] = 35
4101 01:01:57.885142 rx_firspass[1][1][3] = -4
4102 01:01:57.887959 rx_lastpass[1][1][3] = 32
4103 01:01:57.891656 rx_firspass[1][1][4] = 3
4104 01:01:57.892126 rx_lastpass[1][1][4] = 36
4105 01:01:57.894764 rx_firspass[1][1][5] = 7
4106 01:01:57.898450 rx_lastpass[1][1][5] = 40
4107 01:01:57.898919 rx_firspass[1][1][6] = 7
4108 01:01:57.901540 rx_lastpass[1][1][6] = 41
4109 01:01:57.905075 rx_firspass[1][1][7] = 3
4110 01:01:57.908091 rx_lastpass[1][1][7] = 37
4111 01:01:57.908478 rx_firspass[1][1][8] = 0
4112 01:01:57.911529 rx_lastpass[1][1][8] = 36
4113 01:01:57.915019 rx_firspass[1][1][9] = 1
4114 01:01:57.915494 rx_lastpass[1][1][9] = 36
4115 01:01:57.918079 rx_firspass[1][1][10] = 1
4116 01:01:57.921802 rx_lastpass[1][1][10] = 35
4117 01:01:57.925010 rx_firspass[1][1][11] = 2
4118 01:01:57.925398 rx_lastpass[1][1][11] = 36
4119 01:01:57.928038 rx_firspass[1][1][12] = 5
4120 01:01:57.931485 rx_lastpass[1][1][12] = 39
4121 01:01:57.931875 rx_firspass[1][1][13] = 4
4122 01:01:57.934725 rx_lastpass[1][1][13] = 38
4123 01:01:57.938196 rx_firspass[1][1][14] = 3
4124 01:01:57.941848 rx_lastpass[1][1][14] = 36
4125 01:01:57.942414 rx_firspass[1][1][15] = -2
4126 01:01:57.944942 rx_lastpass[1][1][15] = 32
4127 01:01:57.948406 dump params clk_delay
4128 01:01:57.948911 clk_delay[0] = 0
4129 01:01:57.951434 clk_delay[1] = 0
4130 01:01:57.951875 dump params dqs_delay
4131 01:01:57.954909 dqs_delay[0][0] = -1
4132 01:01:57.955337 dqs_delay[0][1] = 0
4133 01:01:57.958261 dqs_delay[1][0] = 0
4134 01:01:57.958696 dqs_delay[1][1] = 0
4135 01:01:57.961863 dump params delay_cell_unit = 753
4136 01:01:57.965092 dump source = 0x0
4137 01:01:57.965602 dump params frequency:1200
4138 01:01:57.968417 dump params rank number:2
4139 01:01:57.968847
4140 01:01:57.971463 dump params write leveling
4141 01:01:57.974917 write leveling[0][0][0] = 0x0
4142 01:01:57.978129 write leveling[0][0][1] = 0x0
4143 01:01:57.978607 write leveling[0][1][0] = 0x0
4144 01:01:57.981574 write leveling[0][1][1] = 0x0
4145 01:01:57.985090 write leveling[1][0][0] = 0x0
4146 01:01:57.988833 write leveling[1][0][1] = 0x0
4147 01:01:57.991897 write leveling[1][1][0] = 0x0
4148 01:01:57.992411 write leveling[1][1][1] = 0x0
4149 01:01:57.995338 dump params cbt_cs
4150 01:01:57.995840 cbt_cs[0][0] = 0x0
4151 01:01:57.998403 cbt_cs[0][1] = 0x0
4152 01:01:57.998832 cbt_cs[1][0] = 0x0
4153 01:01:58.001714 cbt_cs[1][1] = 0x0
4154 01:01:58.004978 dump params cbt_mr12
4155 01:01:58.005460 cbt_mr12[0][0] = 0x0
4156 01:01:58.008193 cbt_mr12[0][1] = 0x0
4157 01:01:58.008712 cbt_mr12[1][0] = 0x0
4158 01:01:58.011638 cbt_mr12[1][1] = 0x0
4159 01:01:58.012067 dump params tx window
4160 01:01:58.015546 tx_center_min[0][0][0] = 0
4161 01:01:58.018822 tx_center_max[0][0][0] = 0
4162 01:01:58.021803 tx_center_min[0][0][1] = 0
4163 01:01:58.022440 tx_center_max[0][0][1] = 0
4164 01:01:58.025244 tx_center_min[0][1][0] = 0
4165 01:01:58.028778 tx_center_max[0][1][0] = 0
4166 01:01:58.029234 tx_center_min[0][1][1] = 0
4167 01:01:58.031817 tx_center_max[0][1][1] = 0
4168 01:01:58.035291 tx_center_min[1][0][0] = 0
4169 01:01:58.038400 tx_center_max[1][0][0] = 0
4170 01:01:58.039036 tx_center_min[1][0][1] = 0
4171 01:01:58.041958 tx_center_max[1][0][1] = 0
4172 01:01:58.045281 tx_center_min[1][1][0] = 0
4173 01:01:58.048402 tx_center_max[1][1][0] = 0
4174 01:01:58.048833 tx_center_min[1][1][1] = 0
4175 01:01:58.051961 tx_center_max[1][1][1] = 0
4176 01:01:58.055304 dump params tx window
4177 01:01:58.055926 tx_win_center[0][0][0] = 0
4178 01:01:58.058555 tx_first_pass[0][0][0] = 0
4179 01:01:58.061713 tx_last_pass[0][0][0] = 0
4180 01:01:58.065036 tx_win_center[0][0][1] = 0
4181 01:01:58.065425 tx_first_pass[0][0][1] = 0
4182 01:01:58.068533 tx_last_pass[0][0][1] = 0
4183 01:01:58.071781 tx_win_center[0][0][2] = 0
4184 01:01:58.075158 tx_first_pass[0][0][2] = 0
4185 01:01:58.075548 tx_last_pass[0][0][2] = 0
4186 01:01:58.078555 tx_win_center[0][0][3] = 0
4187 01:01:58.081825 tx_first_pass[0][0][3] = 0
4188 01:01:58.082238 tx_last_pass[0][0][3] = 0
4189 01:01:58.085050 tx_win_center[0][0][4] = 0
4190 01:01:58.088729 tx_first_pass[0][0][4] = 0
4191 01:01:58.092059 tx_last_pass[0][0][4] = 0
4192 01:01:58.092538 tx_win_center[0][0][5] = 0
4193 01:01:58.095205 tx_first_pass[0][0][5] = 0
4194 01:01:58.098845 tx_last_pass[0][0][5] = 0
4195 01:01:58.099325 tx_win_center[0][0][6] = 0
4196 01:01:58.102062 tx_first_pass[0][0][6] = 0
4197 01:01:58.105272 tx_last_pass[0][0][6] = 0
4198 01:01:58.108628 tx_win_center[0][0][7] = 0
4199 01:01:58.109033 tx_first_pass[0][0][7] = 0
4200 01:01:58.111890 tx_last_pass[0][0][7] = 0
4201 01:01:58.115243 tx_win_center[0][0][8] = 0
4202 01:01:58.118518 tx_first_pass[0][0][8] = 0
4203 01:01:58.118914 tx_last_pass[0][0][8] = 0
4204 01:01:58.121935 tx_win_center[0][0][9] = 0
4205 01:01:58.125193 tx_first_pass[0][0][9] = 0
4206 01:01:58.125592 tx_last_pass[0][0][9] = 0
4207 01:01:58.128567 tx_win_center[0][0][10] = 0
4208 01:01:58.132094 tx_first_pass[0][0][10] = 0
4209 01:01:58.135152 tx_last_pass[0][0][10] = 0
4210 01:01:58.135624 tx_win_center[0][0][11] = 0
4211 01:01:58.138531 tx_first_pass[0][0][11] = 0
4212 01:01:58.142050 tx_last_pass[0][0][11] = 0
4213 01:01:58.145325 tx_win_center[0][0][12] = 0
4214 01:01:58.145795 tx_first_pass[0][0][12] = 0
4215 01:01:58.148650 tx_last_pass[0][0][12] = 0
4216 01:01:58.151844 tx_win_center[0][0][13] = 0
4217 01:01:58.155305 tx_first_pass[0][0][13] = 0
4218 01:01:58.155695 tx_last_pass[0][0][13] = 0
4219 01:01:58.158551 tx_win_center[0][0][14] = 0
4220 01:01:58.161718 tx_first_pass[0][0][14] = 0
4221 01:01:58.165419 tx_last_pass[0][0][14] = 0
4222 01:01:58.165630 tx_win_center[0][0][15] = 0
4223 01:01:58.168476 tx_first_pass[0][0][15] = 0
4224 01:01:58.171715 tx_last_pass[0][0][15] = 0
4225 01:01:58.175214 tx_win_center[0][1][0] = 0
4226 01:01:58.175381 tx_first_pass[0][1][0] = 0
4227 01:01:58.178396 tx_last_pass[0][1][0] = 0
4228 01:01:58.181924 tx_win_center[0][1][1] = 0
4229 01:01:58.182091 tx_first_pass[0][1][1] = 0
4230 01:01:58.185341 tx_last_pass[0][1][1] = 0
4231 01:01:58.188547 tx_win_center[0][1][2] = 0
4232 01:01:58.192139 tx_first_pass[0][1][2] = 0
4233 01:01:58.192314 tx_last_pass[0][1][2] = 0
4234 01:01:58.195733 tx_win_center[0][1][3] = 0
4235 01:01:58.198863 tx_first_pass[0][1][3] = 0
4236 01:01:58.199024 tx_last_pass[0][1][3] = 0
4237 01:01:58.202156 tx_win_center[0][1][4] = 0
4238 01:01:58.205525 tx_first_pass[0][1][4] = 0
4239 01:01:58.208934 tx_last_pass[0][1][4] = 0
4240 01:01:58.209155 tx_win_center[0][1][5] = 0
4241 01:01:58.212186 tx_first_pass[0][1][5] = 0
4242 01:01:58.215645 tx_last_pass[0][1][5] = 0
4243 01:01:58.215805 tx_win_center[0][1][6] = 0
4244 01:01:58.218915 tx_first_pass[0][1][6] = 0
4245 01:01:58.222112 tx_last_pass[0][1][6] = 0
4246 01:01:58.225392 tx_win_center[0][1][7] = 0
4247 01:01:58.225559 tx_first_pass[0][1][7] = 0
4248 01:01:58.228671 tx_last_pass[0][1][7] = 0
4249 01:01:58.232079 tx_win_center[0][1][8] = 0
4250 01:01:58.235454 tx_first_pass[0][1][8] = 0
4251 01:01:58.235623 tx_last_pass[0][1][8] = 0
4252 01:01:58.238870 tx_win_center[0][1][9] = 0
4253 01:01:58.242178 tx_first_pass[0][1][9] = 0
4254 01:01:58.242437 tx_last_pass[0][1][9] = 0
4255 01:01:58.245639 tx_win_center[0][1][10] = 0
4256 01:01:58.249034 tx_first_pass[0][1][10] = 0
4257 01:01:58.252883 tx_last_pass[0][1][10] = 0
4258 01:01:58.253290 tx_win_center[0][1][11] = 0
4259 01:01:58.255823 tx_first_pass[0][1][11] = 0
4260 01:01:58.259233 tx_last_pass[0][1][11] = 0
4261 01:01:58.262703 tx_win_center[0][1][12] = 0
4262 01:01:58.263089 tx_first_pass[0][1][12] = 0
4263 01:01:58.265688 tx_last_pass[0][1][12] = 0
4264 01:01:58.269019 tx_win_center[0][1][13] = 0
4265 01:01:58.272312 tx_first_pass[0][1][13] = 0
4266 01:01:58.272868 tx_last_pass[0][1][13] = 0
4267 01:01:58.275801 tx_win_center[0][1][14] = 0
4268 01:01:58.279062 tx_first_pass[0][1][14] = 0
4269 01:01:58.282509 tx_last_pass[0][1][14] = 0
4270 01:01:58.282893 tx_win_center[0][1][15] = 0
4271 01:01:58.285926 tx_first_pass[0][1][15] = 0
4272 01:01:58.289347 tx_last_pass[0][1][15] = 0
4273 01:01:58.292402 tx_win_center[1][0][0] = 0
4274 01:01:58.292788 tx_first_pass[1][0][0] = 0
4275 01:01:58.296061 tx_last_pass[1][0][0] = 0
4276 01:01:58.299283 tx_win_center[1][0][1] = 0
4277 01:01:58.302524 tx_first_pass[1][0][1] = 0
4278 01:01:58.302913 tx_last_pass[1][0][1] = 0
4279 01:01:58.305916 tx_win_center[1][0][2] = 0
4280 01:01:58.309362 tx_first_pass[1][0][2] = 0
4281 01:01:58.309764 tx_last_pass[1][0][2] = 0
4282 01:01:58.312618 tx_win_center[1][0][3] = 0
4283 01:01:58.315980 tx_first_pass[1][0][3] = 0
4284 01:01:58.319522 tx_last_pass[1][0][3] = 0
4285 01:01:58.319910 tx_win_center[1][0][4] = 0
4286 01:01:58.322689 tx_first_pass[1][0][4] = 0
4287 01:01:58.325805 tx_last_pass[1][0][4] = 0
4288 01:01:58.326188 tx_win_center[1][0][5] = 0
4289 01:01:58.329583 tx_first_pass[1][0][5] = 0
4290 01:01:58.332579 tx_last_pass[1][0][5] = 0
4291 01:01:58.335954 tx_win_center[1][0][6] = 0
4292 01:01:58.336340 tx_first_pass[1][0][6] = 0
4293 01:01:58.339483 tx_last_pass[1][0][6] = 0
4294 01:01:58.342722 tx_win_center[1][0][7] = 0
4295 01:01:58.346127 tx_first_pass[1][0][7] = 0
4296 01:01:58.346535 tx_last_pass[1][0][7] = 0
4297 01:01:58.349353 tx_win_center[1][0][8] = 0
4298 01:01:58.352648 tx_first_pass[1][0][8] = 0
4299 01:01:58.353034 tx_last_pass[1][0][8] = 0
4300 01:01:58.356006 tx_win_center[1][0][9] = 0
4301 01:01:58.359251 tx_first_pass[1][0][9] = 0
4302 01:01:58.362503 tx_last_pass[1][0][9] = 0
4303 01:01:58.362881 tx_win_center[1][0][10] = 0
4304 01:01:58.366168 tx_first_pass[1][0][10] = 0
4305 01:01:58.369270 tx_last_pass[1][0][10] = 0
4306 01:01:58.372749 tx_win_center[1][0][11] = 0
4307 01:01:58.373131 tx_first_pass[1][0][11] = 0
4308 01:01:58.376136 tx_last_pass[1][0][11] = 0
4309 01:01:58.379593 tx_win_center[1][0][12] = 0
4310 01:01:58.382880 tx_first_pass[1][0][12] = 0
4311 01:01:58.383266 tx_last_pass[1][0][12] = 0
4312 01:01:58.386151 tx_win_center[1][0][13] = 0
4313 01:01:58.389462 tx_first_pass[1][0][13] = 0
4314 01:01:58.392899 tx_last_pass[1][0][13] = 0
4315 01:01:58.393279 tx_win_center[1][0][14] = 0
4316 01:01:58.396070 tx_first_pass[1][0][14] = 0
4317 01:01:58.399497 tx_last_pass[1][0][14] = 0
4318 01:01:58.402944 tx_win_center[1][0][15] = 0
4319 01:01:58.403326 tx_first_pass[1][0][15] = 0
4320 01:01:58.406174 tx_last_pass[1][0][15] = 0
4321 01:01:58.409284 tx_win_center[1][1][0] = 0
4322 01:01:58.412752 tx_first_pass[1][1][0] = 0
4323 01:01:58.413263 tx_last_pass[1][1][0] = 0
4324 01:01:58.416174 tx_win_center[1][1][1] = 0
4325 01:01:58.419291 tx_first_pass[1][1][1] = 0
4326 01:01:58.419692 tx_last_pass[1][1][1] = 0
4327 01:01:58.422799 tx_win_center[1][1][2] = 0
4328 01:01:58.426729 tx_first_pass[1][1][2] = 0
4329 01:01:58.429341 tx_last_pass[1][1][2] = 0
4330 01:01:58.429733 tx_win_center[1][1][3] = 0
4331 01:01:58.432645 tx_first_pass[1][1][3] = 0
4332 01:01:58.436227 tx_last_pass[1][1][3] = 0
4333 01:01:58.436692 tx_win_center[1][1][4] = 0
4334 01:01:58.439423 tx_first_pass[1][1][4] = 0
4335 01:01:58.442803 tx_last_pass[1][1][4] = 0
4336 01:01:58.446090 tx_win_center[1][1][5] = 0
4337 01:01:58.446653 tx_first_pass[1][1][5] = 0
4338 01:01:58.449442 tx_last_pass[1][1][5] = 0
4339 01:01:58.453152 tx_win_center[1][1][6] = 0
4340 01:01:58.453549 tx_first_pass[1][1][6] = 0
4341 01:01:58.456405 tx_last_pass[1][1][6] = 0
4342 01:01:58.459670 tx_win_center[1][1][7] = 0
4343 01:01:58.462933 tx_first_pass[1][1][7] = 0
4344 01:01:58.463370 tx_last_pass[1][1][7] = 0
4345 01:01:58.466328 tx_win_center[1][1][8] = 0
4346 01:01:58.469706 tx_first_pass[1][1][8] = 0
4347 01:01:58.470377 tx_last_pass[1][1][8] = 0
4348 01:01:58.473090 tx_win_center[1][1][9] = 0
4349 01:01:58.476201 tx_first_pass[1][1][9] = 0
4350 01:01:58.479589 tx_last_pass[1][1][9] = 0
4351 01:01:58.479972 tx_win_center[1][1][10] = 0
4352 01:01:58.483196 tx_first_pass[1][1][10] = 0
4353 01:01:58.486350 tx_last_pass[1][1][10] = 0
4354 01:01:58.489506 tx_win_center[1][1][11] = 0
4355 01:01:58.489888 tx_first_pass[1][1][11] = 0
4356 01:01:58.492995 tx_last_pass[1][1][11] = 0
4357 01:01:58.496208 tx_win_center[1][1][12] = 0
4358 01:01:58.499711 tx_first_pass[1][1][12] = 0
4359 01:01:58.500094 tx_last_pass[1][1][12] = 0
4360 01:01:58.503045 tx_win_center[1][1][13] = 0
4361 01:01:58.506610 tx_first_pass[1][1][13] = 0
4362 01:01:58.509669 tx_last_pass[1][1][13] = 0
4363 01:01:58.510053 tx_win_center[1][1][14] = 0
4364 01:01:58.513074 tx_first_pass[1][1][14] = 0
4365 01:01:58.516467 tx_last_pass[1][1][14] = 0
4366 01:01:58.519879 tx_win_center[1][1][15] = 0
4367 01:01:58.520263 tx_first_pass[1][1][15] = 0
4368 01:01:58.523161 tx_last_pass[1][1][15] = 0
4369 01:01:58.526575 dump params rx window
4370 01:01:58.527010 rx_firspass[0][0][0] = 0
4371 01:01:58.529750 rx_lastpass[0][0][0] = 0
4372 01:01:58.533169 rx_firspass[0][0][1] = 0
4373 01:01:58.533554 rx_lastpass[0][0][1] = 0
4374 01:01:58.536934 rx_firspass[0][0][2] = 0
4375 01:01:58.539935 rx_lastpass[0][0][2] = 0
4376 01:01:58.540434 rx_firspass[0][0][3] = 0
4377 01:01:58.543411 rx_lastpass[0][0][3] = 0
4378 01:01:58.546481 rx_firspass[0][0][4] = 0
4379 01:01:58.550064 rx_lastpass[0][0][4] = 0
4380 01:01:58.550529 rx_firspass[0][0][5] = 0
4381 01:01:58.553268 rx_lastpass[0][0][5] = 0
4382 01:01:58.556628 rx_firspass[0][0][6] = 0
4383 01:01:58.557017 rx_lastpass[0][0][6] = 0
4384 01:01:58.559761 rx_firspass[0][0][7] = 0
4385 01:01:58.563104 rx_lastpass[0][0][7] = 0
4386 01:01:58.563538 rx_firspass[0][0][8] = 0
4387 01:01:58.566748 rx_lastpass[0][0][8] = 0
4388 01:01:58.569987 rx_firspass[0][0][9] = 0
4389 01:01:58.570477 rx_lastpass[0][0][9] = 0
4390 01:01:58.573439 rx_firspass[0][0][10] = 0
4391 01:01:58.576910 rx_lastpass[0][0][10] = 0
4392 01:01:58.579838 rx_firspass[0][0][11] = 0
4393 01:01:58.580240 rx_lastpass[0][0][11] = 0
4394 01:01:58.583127 rx_firspass[0][0][12] = 0
4395 01:01:58.586636 rx_lastpass[0][0][12] = 0
4396 01:01:58.587115 rx_firspass[0][0][13] = 0
4397 01:01:58.590289 rx_lastpass[0][0][13] = 0
4398 01:01:58.593537 rx_firspass[0][0][14] = 0
4399 01:01:58.594023 rx_lastpass[0][0][14] = 0
4400 01:01:58.596880 rx_firspass[0][0][15] = 0
4401 01:01:58.599978 rx_lastpass[0][0][15] = 0
4402 01:01:58.603159 rx_firspass[0][1][0] = 0
4403 01:01:58.603545 rx_lastpass[0][1][0] = 0
4404 01:01:58.606975 rx_firspass[0][1][1] = 0
4405 01:01:58.610142 rx_lastpass[0][1][1] = 0
4406 01:01:58.610569 rx_firspass[0][1][2] = 0
4407 01:01:58.613349 rx_lastpass[0][1][2] = 0
4408 01:01:58.616542 rx_firspass[0][1][3] = 0
4409 01:01:58.616941 rx_lastpass[0][1][3] = 0
4410 01:01:58.620064 rx_firspass[0][1][4] = 0
4411 01:01:58.623401 rx_lastpass[0][1][4] = 0
4412 01:01:58.623786 rx_firspass[0][1][5] = 0
4413 01:01:58.626652 rx_lastpass[0][1][5] = 0
4414 01:01:58.629941 rx_firspass[0][1][6] = 0
4415 01:01:58.630359 rx_lastpass[0][1][6] = 0
4416 01:01:58.633983 rx_firspass[0][1][7] = 0
4417 01:01:58.636639 rx_lastpass[0][1][7] = 0
4418 01:01:58.637151 rx_firspass[0][1][8] = 0
4419 01:01:58.640209 rx_lastpass[0][1][8] = 0
4420 01:01:58.643603 rx_firspass[0][1][9] = 0
4421 01:01:58.647246 rx_lastpass[0][1][9] = 0
4422 01:01:58.647676 rx_firspass[0][1][10] = 0
4423 01:01:58.650149 rx_lastpass[0][1][10] = 0
4424 01:01:58.653468 rx_firspass[0][1][11] = 0
4425 01:01:58.653901 rx_lastpass[0][1][11] = 0
4426 01:01:58.657046 rx_firspass[0][1][12] = 0
4427 01:01:58.660617 rx_lastpass[0][1][12] = 0
4428 01:01:58.661046 rx_firspass[0][1][13] = 0
4429 01:01:58.663712 rx_lastpass[0][1][13] = 0
4430 01:01:58.667096 rx_firspass[0][1][14] = 0
4431 01:01:58.670674 rx_lastpass[0][1][14] = 0
4432 01:01:58.671186 rx_firspass[0][1][15] = 0
4433 01:01:58.674150 rx_lastpass[0][1][15] = 0
4434 01:01:58.677214 rx_firspass[1][0][0] = 0
4435 01:01:58.677878 rx_lastpass[1][0][0] = 0
4436 01:01:58.680790 rx_firspass[1][0][1] = 0
4437 01:01:58.683956 rx_lastpass[1][0][1] = 0
4438 01:01:58.684468 rx_firspass[1][0][2] = 0
4439 01:01:58.687321 rx_lastpass[1][0][2] = 0
4440 01:01:58.690644 rx_firspass[1][0][3] = 0
4441 01:01:58.691156 rx_lastpass[1][0][3] = 0
4442 01:01:58.694048 rx_firspass[1][0][4] = 0
4443 01:01:58.697420 rx_lastpass[1][0][4] = 0
4444 01:01:58.697928 rx_firspass[1][0][5] = 0
4445 01:01:58.700823 rx_lastpass[1][0][5] = 0
4446 01:01:58.704173 rx_firspass[1][0][6] = 0
4447 01:01:58.707719 rx_lastpass[1][0][6] = 0
4448 01:01:58.708280 rx_firspass[1][0][7] = 0
4449 01:01:58.710567 rx_lastpass[1][0][7] = 0
4450 01:01:58.713779 rx_firspass[1][0][8] = 0
4451 01:01:58.714200 rx_lastpass[1][0][8] = 0
4452 01:01:58.717423 rx_firspass[1][0][9] = 0
4453 01:01:58.720654 rx_lastpass[1][0][9] = 0
4454 01:01:58.721241 rx_firspass[1][0][10] = 0
4455 01:01:58.723830 rx_lastpass[1][0][10] = 0
4456 01:01:58.727308 rx_firspass[1][0][11] = 0
4457 01:01:58.727745 rx_lastpass[1][0][11] = 0
4458 01:01:58.730759 rx_firspass[1][0][12] = 0
4459 01:01:58.734052 rx_lastpass[1][0][12] = 0
4460 01:01:58.737207 rx_firspass[1][0][13] = 0
4461 01:01:58.737641 rx_lastpass[1][0][13] = 0
4462 01:01:58.740635 rx_firspass[1][0][14] = 0
4463 01:01:58.744127 rx_lastpass[1][0][14] = 0
4464 01:01:58.744556 rx_firspass[1][0][15] = 0
4465 01:01:58.747336 rx_lastpass[1][0][15] = 0
4466 01:01:58.750890 rx_firspass[1][1][0] = 0
4467 01:01:58.751283 rx_lastpass[1][1][0] = 0
4468 01:01:58.754037 rx_firspass[1][1][1] = 0
4469 01:01:58.757543 rx_lastpass[1][1][1] = 0
4470 01:01:58.760618 rx_firspass[1][1][2] = 0
4471 01:01:58.761014 rx_lastpass[1][1][2] = 0
4472 01:01:58.764163 rx_firspass[1][1][3] = 0
4473 01:01:58.767937 rx_lastpass[1][1][3] = 0
4474 01:01:58.768410 rx_firspass[1][1][4] = 0
4475 01:01:58.770942 rx_lastpass[1][1][4] = 0
4476 01:01:58.774524 rx_firspass[1][1][5] = 0
4477 01:01:58.774913 rx_lastpass[1][1][5] = 0
4478 01:01:58.778076 rx_firspass[1][1][6] = 0
4479 01:01:58.780849 rx_lastpass[1][1][6] = 0
4480 01:01:58.781237 rx_firspass[1][1][7] = 0
4481 01:01:58.784427 rx_lastpass[1][1][7] = 0
4482 01:01:58.787956 rx_firspass[1][1][8] = 0
4483 01:01:58.788431 rx_lastpass[1][1][8] = 0
4484 01:01:58.791349 rx_firspass[1][1][9] = 0
4485 01:01:58.794363 rx_lastpass[1][1][9] = 0
4486 01:01:58.794835 rx_firspass[1][1][10] = 0
4487 01:01:58.797993 rx_lastpass[1][1][10] = 0
4488 01:01:58.801198 rx_firspass[1][1][11] = 0
4489 01:01:58.804477 rx_lastpass[1][1][11] = 0
4490 01:01:58.804954 rx_firspass[1][1][12] = 0
4491 01:01:58.807813 rx_lastpass[1][1][12] = 0
4492 01:01:58.811574 rx_firspass[1][1][13] = 0
4493 01:01:58.812053 rx_lastpass[1][1][13] = 0
4494 01:01:58.814405 rx_firspass[1][1][14] = 0
4495 01:01:58.818252 rx_lastpass[1][1][14] = 0
4496 01:01:58.821082 rx_firspass[1][1][15] = 0
4497 01:01:58.821512 rx_lastpass[1][1][15] = 0
4498 01:01:58.824321 dump params clk_delay
4499 01:01:58.824750 clk_delay[0] = 0
4500 01:01:58.827738 clk_delay[1] = 0
4501 01:01:58.828168 dump params dqs_delay
4502 01:01:58.831439 dqs_delay[0][0] = 0
4503 01:01:58.831955 dqs_delay[0][1] = 0
4504 01:01:58.834592 dqs_delay[1][0] = 0
4505 01:01:58.837952 dqs_delay[1][1] = 0
4506 01:01:58.838523 dump params delay_cell_unit = 753
4507 01:01:58.841471 dump source = 0x0
4508 01:01:58.844734 dump params frequency:800
4509 01:01:58.845246 dump params rank number:2
4510 01:01:58.845583
4511 01:01:58.847973 dump params write leveling
4512 01:01:58.851326 write leveling[0][0][0] = 0x0
4513 01:01:58.854570 write leveling[0][0][1] = 0x0
4514 01:01:58.857805 write leveling[0][1][0] = 0x0
4515 01:01:58.858256 write leveling[0][1][1] = 0x0
4516 01:01:58.861239 write leveling[1][0][0] = 0x0
4517 01:01:58.864517 write leveling[1][0][1] = 0x0
4518 01:01:58.868111 write leveling[1][1][0] = 0x0
4519 01:01:58.871078 write leveling[1][1][1] = 0x0
4520 01:01:58.871505 dump params cbt_cs
4521 01:01:58.874734 cbt_cs[0][0] = 0x0
4522 01:01:58.875160 cbt_cs[0][1] = 0x0
4523 01:01:58.878020 cbt_cs[1][0] = 0x0
4524 01:01:58.878461 cbt_cs[1][1] = 0x0
4525 01:01:58.881451 dump params cbt_mr12
4526 01:01:58.881839 cbt_mr12[0][0] = 0x0
4527 01:01:58.884580 cbt_mr12[0][1] = 0x0
4528 01:01:58.884969 cbt_mr12[1][0] = 0x0
4529 01:01:58.888139 cbt_mr12[1][1] = 0x0
4530 01:01:58.891326 dump params tx window
4531 01:01:58.891717 tx_center_min[0][0][0] = 0
4532 01:01:58.894590 tx_center_max[0][0][0] = 0
4533 01:01:58.898076 tx_center_min[0][0][1] = 0
4534 01:01:58.898512 tx_center_max[0][0][1] = 0
4535 01:01:58.901294 tx_center_min[0][1][0] = 0
4536 01:01:58.904646 tx_center_max[0][1][0] = 0
4537 01:01:58.908060 tx_center_min[0][1][1] = 0
4538 01:01:58.908455 tx_center_max[0][1][1] = 0
4539 01:01:58.911319 tx_center_min[1][0][0] = 0
4540 01:01:58.914805 tx_center_max[1][0][0] = 0
4541 01:01:58.917967 tx_center_min[1][0][1] = 0
4542 01:01:58.918389 tx_center_max[1][0][1] = 0
4543 01:01:58.921618 tx_center_min[1][1][0] = 0
4544 01:01:58.924416 tx_center_max[1][1][0] = 0
4545 01:01:58.928395 tx_center_min[1][1][1] = 0
4546 01:01:58.928829 tx_center_max[1][1][1] = 0
4547 01:01:58.931319 dump params tx window
4548 01:01:58.934662 tx_win_center[0][0][0] = 0
4549 01:01:58.935053 tx_first_pass[0][0][0] = 0
4550 01:01:58.937918 tx_last_pass[0][0][0] = 0
4551 01:01:58.941516 tx_win_center[0][0][1] = 0
4552 01:01:58.944374 tx_first_pass[0][0][1] = 0
4553 01:01:58.944767 tx_last_pass[0][0][1] = 0
4554 01:01:58.947905 tx_win_center[0][0][2] = 0
4555 01:01:58.951262 tx_first_pass[0][0][2] = 0
4556 01:01:58.951653 tx_last_pass[0][0][2] = 0
4557 01:01:58.954465 tx_win_center[0][0][3] = 0
4558 01:01:58.958112 tx_first_pass[0][0][3] = 0
4559 01:01:58.961402 tx_last_pass[0][0][3] = 0
4560 01:01:58.961791 tx_win_center[0][0][4] = 0
4561 01:01:58.964781 tx_first_pass[0][0][4] = 0
4562 01:01:58.968237 tx_last_pass[0][0][4] = 0
4563 01:01:58.968630 tx_win_center[0][0][5] = 0
4564 01:01:58.971274 tx_first_pass[0][0][5] = 0
4565 01:01:58.974670 tx_last_pass[0][0][5] = 0
4566 01:01:58.978011 tx_win_center[0][0][6] = 0
4567 01:01:58.978422 tx_first_pass[0][0][6] = 0
4568 01:01:58.981304 tx_last_pass[0][0][6] = 0
4569 01:01:58.984884 tx_win_center[0][0][7] = 0
4570 01:01:58.988147 tx_first_pass[0][0][7] = 0
4571 01:01:58.988550 tx_last_pass[0][0][7] = 0
4572 01:01:58.991452 tx_win_center[0][0][8] = 0
4573 01:01:58.994727 tx_first_pass[0][0][8] = 0
4574 01:01:58.995122 tx_last_pass[0][0][8] = 0
4575 01:01:58.998173 tx_win_center[0][0][9] = 0
4576 01:01:59.001278 tx_first_pass[0][0][9] = 0
4577 01:01:59.004718 tx_last_pass[0][0][9] = 0
4578 01:01:59.005108 tx_win_center[0][0][10] = 0
4579 01:01:59.008138 tx_first_pass[0][0][10] = 0
4580 01:01:59.011327 tx_last_pass[0][0][10] = 0
4581 01:01:59.014607 tx_win_center[0][0][11] = 0
4582 01:01:59.015007 tx_first_pass[0][0][11] = 0
4583 01:01:59.018023 tx_last_pass[0][0][11] = 0
4584 01:01:59.021421 tx_win_center[0][0][12] = 0
4585 01:01:59.024567 tx_first_pass[0][0][12] = 0
4586 01:01:59.024963 tx_last_pass[0][0][12] = 0
4587 01:01:59.027912 tx_win_center[0][0][13] = 0
4588 01:01:59.031437 tx_first_pass[0][0][13] = 0
4589 01:01:59.034286 tx_last_pass[0][0][13] = 0
4590 01:01:59.034680 tx_win_center[0][0][14] = 0
4591 01:01:59.037659 tx_first_pass[0][0][14] = 0
4592 01:01:59.041029 tx_last_pass[0][0][14] = 0
4593 01:01:59.044409 tx_win_center[0][0][15] = 0
4594 01:01:59.044801 tx_first_pass[0][0][15] = 0
4595 01:01:59.047921 tx_last_pass[0][0][15] = 0
4596 01:01:59.051249 tx_win_center[0][1][0] = 0
4597 01:01:59.054503 tx_first_pass[0][1][0] = 0
4598 01:01:59.054902 tx_last_pass[0][1][0] = 0
4599 01:01:59.057653 tx_win_center[0][1][1] = 0
4600 01:01:59.060869 tx_first_pass[0][1][1] = 0
4601 01:01:59.061264 tx_last_pass[0][1][1] = 0
4602 01:01:59.064248 tx_win_center[0][1][2] = 0
4603 01:01:59.067514 tx_first_pass[0][1][2] = 0
4604 01:01:59.070863 tx_last_pass[0][1][2] = 0
4605 01:01:59.071259 tx_win_center[0][1][3] = 0
4606 01:01:59.074105 tx_first_pass[0][1][3] = 0
4607 01:01:59.077448 tx_last_pass[0][1][3] = 0
4608 01:01:59.080767 tx_win_center[0][1][4] = 0
4609 01:01:59.081159 tx_first_pass[0][1][4] = 0
4610 01:01:59.084287 tx_last_pass[0][1][4] = 0
4611 01:01:59.087662 tx_win_center[0][1][5] = 0
4612 01:01:59.090839 tx_first_pass[0][1][5] = 0
4613 01:01:59.091237 tx_last_pass[0][1][5] = 0
4614 01:01:59.094208 tx_win_center[0][1][6] = 0
4615 01:01:59.097740 tx_first_pass[0][1][6] = 0
4616 01:01:59.098131 tx_last_pass[0][1][6] = 0
4617 01:01:59.100962 tx_win_center[0][1][7] = 0
4618 01:01:59.104482 tx_first_pass[0][1][7] = 0
4619 01:01:59.108224 tx_last_pass[0][1][7] = 0
4620 01:01:59.108616 tx_win_center[0][1][8] = 0
4621 01:01:59.111323 tx_first_pass[0][1][8] = 0
4622 01:01:59.114435 tx_last_pass[0][1][8] = 0
4623 01:01:59.114870 tx_win_center[0][1][9] = 0
4624 01:01:59.117899 tx_first_pass[0][1][9] = 0
4625 01:01:59.121192 tx_last_pass[0][1][9] = 0
4626 01:01:59.124558 tx_win_center[0][1][10] = 0
4627 01:01:59.124951 tx_first_pass[0][1][10] = 0
4628 01:01:59.127876 tx_last_pass[0][1][10] = 0
4629 01:01:59.130995 tx_win_center[0][1][11] = 0
4630 01:01:59.134371 tx_first_pass[0][1][11] = 0
4631 01:01:59.134770 tx_last_pass[0][1][11] = 0
4632 01:01:59.137797 tx_win_center[0][1][12] = 0
4633 01:01:59.141043 tx_first_pass[0][1][12] = 0
4634 01:01:59.144314 tx_last_pass[0][1][12] = 0
4635 01:01:59.144712 tx_win_center[0][1][13] = 0
4636 01:01:59.147712 tx_first_pass[0][1][13] = 0
4637 01:01:59.151036 tx_last_pass[0][1][13] = 0
4638 01:01:59.154493 tx_win_center[0][1][14] = 0
4639 01:01:59.154890 tx_first_pass[0][1][14] = 0
4640 01:01:59.157860 tx_last_pass[0][1][14] = 0
4641 01:01:59.161261 tx_win_center[0][1][15] = 0
4642 01:01:59.164331 tx_first_pass[0][1][15] = 0
4643 01:01:59.164720 tx_last_pass[0][1][15] = 0
4644 01:01:59.167784 tx_win_center[1][0][0] = 0
4645 01:01:59.171143 tx_first_pass[1][0][0] = 0
4646 01:01:59.174490 tx_last_pass[1][0][0] = 0
4647 01:01:59.174880 tx_win_center[1][0][1] = 0
4648 01:01:59.177786 tx_first_pass[1][0][1] = 0
4649 01:01:59.181070 tx_last_pass[1][0][1] = 0
4650 01:01:59.181682 tx_win_center[1][0][2] = 0
4651 01:01:59.184623 tx_first_pass[1][0][2] = 0
4652 01:01:59.187795 tx_last_pass[1][0][2] = 0
4653 01:01:59.191164 tx_win_center[1][0][3] = 0
4654 01:01:59.191558 tx_first_pass[1][0][3] = 0
4655 01:01:59.194339 tx_last_pass[1][0][3] = 0
4656 01:01:59.197872 tx_win_center[1][0][4] = 0
4657 01:01:59.198458 tx_first_pass[1][0][4] = 0
4658 01:01:59.201128 tx_last_pass[1][0][4] = 0
4659 01:01:59.204704 tx_win_center[1][0][5] = 0
4660 01:01:59.207888 tx_first_pass[1][0][5] = 0
4661 01:01:59.208281 tx_last_pass[1][0][5] = 0
4662 01:01:59.211022 tx_win_center[1][0][6] = 0
4663 01:01:59.214789 tx_first_pass[1][0][6] = 0
4664 01:01:59.215250 tx_last_pass[1][0][6] = 0
4665 01:01:59.218108 tx_win_center[1][0][7] = 0
4666 01:01:59.221447 tx_first_pass[1][0][7] = 0
4667 01:01:59.224903 tx_last_pass[1][0][7] = 0
4668 01:01:59.225297 tx_win_center[1][0][8] = 0
4669 01:01:59.227804 tx_first_pass[1][0][8] = 0
4670 01:01:59.231299 tx_last_pass[1][0][8] = 0
4671 01:01:59.234649 tx_win_center[1][0][9] = 0
4672 01:01:59.235039 tx_first_pass[1][0][9] = 0
4673 01:01:59.237870 tx_last_pass[1][0][9] = 0
4674 01:01:59.241254 tx_win_center[1][0][10] = 0
4675 01:01:59.241645 tx_first_pass[1][0][10] = 0
4676 01:01:59.244640 tx_last_pass[1][0][10] = 0
4677 01:01:59.248422 tx_win_center[1][0][11] = 0
4678 01:01:59.251475 tx_first_pass[1][0][11] = 0
4679 01:01:59.251869 tx_last_pass[1][0][11] = 0
4680 01:01:59.254926 tx_win_center[1][0][12] = 0
4681 01:01:59.257992 tx_first_pass[1][0][12] = 0
4682 01:01:59.261510 tx_last_pass[1][0][12] = 0
4683 01:01:59.261901 tx_win_center[1][0][13] = 0
4684 01:01:59.264740 tx_first_pass[1][0][13] = 0
4685 01:01:59.268139 tx_last_pass[1][0][13] = 0
4686 01:01:59.271341 tx_win_center[1][0][14] = 0
4687 01:01:59.271735 tx_first_pass[1][0][14] = 0
4688 01:01:59.274660 tx_last_pass[1][0][14] = 0
4689 01:01:59.278061 tx_win_center[1][0][15] = 0
4690 01:01:59.281310 tx_first_pass[1][0][15] = 0
4691 01:01:59.281706 tx_last_pass[1][0][15] = 0
4692 01:01:59.284782 tx_win_center[1][1][0] = 0
4693 01:01:59.288355 tx_first_pass[1][1][0] = 0
4694 01:01:59.291688 tx_last_pass[1][1][0] = 0
4695 01:01:59.292209 tx_win_center[1][1][1] = 0
4696 01:01:59.295077 tx_first_pass[1][1][1] = 0
4697 01:01:59.298395 tx_last_pass[1][1][1] = 0
4698 01:01:59.301371 tx_win_center[1][1][2] = 0
4699 01:01:59.301804 tx_first_pass[1][1][2] = 0
4700 01:01:59.304853 tx_last_pass[1][1][2] = 0
4701 01:01:59.308144 tx_win_center[1][1][3] = 0
4702 01:01:59.308577 tx_first_pass[1][1][3] = 0
4703 01:01:59.311536 tx_last_pass[1][1][3] = 0
4704 01:01:59.315526 tx_win_center[1][1][4] = 0
4705 01:01:59.318471 tx_first_pass[1][1][4] = 0
4706 01:01:59.318987 tx_last_pass[1][1][4] = 0
4707 01:01:59.321767 tx_win_center[1][1][5] = 0
4708 01:01:59.325275 tx_first_pass[1][1][5] = 0
4709 01:01:59.325797 tx_last_pass[1][1][5] = 0
4710 01:01:59.328103 tx_win_center[1][1][6] = 0
4711 01:01:59.331872 tx_first_pass[1][1][6] = 0
4712 01:01:59.334953 tx_last_pass[1][1][6] = 0
4713 01:01:59.335391 tx_win_center[1][1][7] = 0
4714 01:01:59.338208 tx_first_pass[1][1][7] = 0
4715 01:01:59.341535 tx_last_pass[1][1][7] = 0
4716 01:01:59.344847 tx_win_center[1][1][8] = 0
4717 01:01:59.345283 tx_first_pass[1][1][8] = 0
4718 01:01:59.348089 tx_last_pass[1][1][8] = 0
4719 01:01:59.351743 tx_win_center[1][1][9] = 0
4720 01:01:59.352180 tx_first_pass[1][1][9] = 0
4721 01:01:59.355090 tx_last_pass[1][1][9] = 0
4722 01:01:59.358161 tx_win_center[1][1][10] = 0
4723 01:01:59.361499 tx_first_pass[1][1][10] = 0
4724 01:01:59.361933 tx_last_pass[1][1][10] = 0
4725 01:01:59.365222 tx_win_center[1][1][11] = 0
4726 01:01:59.368345 tx_first_pass[1][1][11] = 0
4727 01:01:59.371793 tx_last_pass[1][1][11] = 0
4728 01:01:59.372312 tx_win_center[1][1][12] = 0
4729 01:01:59.375009 tx_first_pass[1][1][12] = 0
4730 01:01:59.378685 tx_last_pass[1][1][12] = 0
4731 01:01:59.381736 tx_win_center[1][1][13] = 0
4732 01:01:59.382171 tx_first_pass[1][1][13] = 0
4733 01:01:59.385279 tx_last_pass[1][1][13] = 0
4734 01:01:59.388716 tx_win_center[1][1][14] = 0
4735 01:01:59.391934 tx_first_pass[1][1][14] = 0
4736 01:01:59.392448 tx_last_pass[1][1][14] = 0
4737 01:01:59.394974 tx_win_center[1][1][15] = 0
4738 01:01:59.398636 tx_first_pass[1][1][15] = 0
4739 01:01:59.401724 tx_last_pass[1][1][15] = 0
4740 01:01:59.402156 dump params rx window
4741 01:01:59.405247 rx_firspass[0][0][0] = 0
4742 01:01:59.408341 rx_lastpass[0][0][0] = 0
4743 01:01:59.408874 rx_firspass[0][0][1] = 0
4744 01:01:59.412067 rx_lastpass[0][0][1] = 0
4745 01:01:59.415555 rx_firspass[0][0][2] = 0
4746 01:01:59.416073 rx_lastpass[0][0][2] = 0
4747 01:01:59.418623 rx_firspass[0][0][3] = 0
4748 01:01:59.422071 rx_lastpass[0][0][3] = 0
4749 01:01:59.422533 rx_firspass[0][0][4] = 0
4750 01:01:59.425334 rx_lastpass[0][0][4] = 0
4751 01:01:59.428347 rx_firspass[0][0][5] = 0
4752 01:01:59.428777 rx_lastpass[0][0][5] = 0
4753 01:01:59.431955 rx_firspass[0][0][6] = 0
4754 01:01:59.434949 rx_lastpass[0][0][6] = 0
4755 01:01:59.435379 rx_firspass[0][0][7] = 0
4756 01:01:59.438521 rx_lastpass[0][0][7] = 0
4757 01:01:59.442099 rx_firspass[0][0][8] = 0
4758 01:01:59.442568 rx_lastpass[0][0][8] = 0
4759 01:01:59.445180 rx_firspass[0][0][9] = 0
4760 01:01:59.448624 rx_lastpass[0][0][9] = 0
4761 01:01:59.451763 rx_firspass[0][0][10] = 0
4762 01:01:59.452189 rx_lastpass[0][0][10] = 0
4763 01:01:59.455066 rx_firspass[0][0][11] = 0
4764 01:01:59.458703 rx_lastpass[0][0][11] = 0
4765 01:01:59.459151 rx_firspass[0][0][12] = 0
4766 01:01:59.461771 rx_lastpass[0][0][12] = 0
4767 01:01:59.465096 rx_firspass[0][0][13] = 0
4768 01:01:59.468122 rx_lastpass[0][0][13] = 0
4769 01:01:59.468512 rx_firspass[0][0][14] = 0
4770 01:01:59.471580 rx_lastpass[0][0][14] = 0
4771 01:01:59.475264 rx_firspass[0][0][15] = 0
4772 01:01:59.475656 rx_lastpass[0][0][15] = 0
4773 01:01:59.478253 rx_firspass[0][1][0] = 0
4774 01:01:59.481533 rx_lastpass[0][1][0] = 0
4775 01:01:59.481923 rx_firspass[0][1][1] = 0
4776 01:01:59.485050 rx_lastpass[0][1][1] = 0
4777 01:01:59.488402 rx_firspass[0][1][2] = 0
4778 01:01:59.491548 rx_lastpass[0][1][2] = 0
4779 01:01:59.491932 rx_firspass[0][1][3] = 0
4780 01:01:59.494953 rx_lastpass[0][1][3] = 0
4781 01:01:59.498304 rx_firspass[0][1][4] = 0
4782 01:01:59.498693 rx_lastpass[0][1][4] = 0
4783 01:01:59.501664 rx_firspass[0][1][5] = 0
4784 01:01:59.505175 rx_lastpass[0][1][5] = 0
4785 01:01:59.505568 rx_firspass[0][1][6] = 0
4786 01:01:59.508266 rx_lastpass[0][1][6] = 0
4787 01:01:59.511767 rx_firspass[0][1][7] = 0
4788 01:01:59.512154 rx_lastpass[0][1][7] = 0
4789 01:01:59.515095 rx_firspass[0][1][8] = 0
4790 01:01:59.518530 rx_lastpass[0][1][8] = 0
4791 01:01:59.518919 rx_firspass[0][1][9] = 0
4792 01:01:59.521738 rx_lastpass[0][1][9] = 0
4793 01:01:59.524991 rx_firspass[0][1][10] = 0
4794 01:01:59.528489 rx_lastpass[0][1][10] = 0
4795 01:01:59.528879 rx_firspass[0][1][11] = 0
4796 01:01:59.531650 rx_lastpass[0][1][11] = 0
4797 01:01:59.534995 rx_firspass[0][1][12] = 0
4798 01:01:59.535385 rx_lastpass[0][1][12] = 0
4799 01:01:59.538592 rx_firspass[0][1][13] = 0
4800 01:01:59.542047 rx_lastpass[0][1][13] = 0
4801 01:01:59.542508 rx_firspass[0][1][14] = 0
4802 01:01:59.545092 rx_lastpass[0][1][14] = 0
4803 01:01:59.548589 rx_firspass[0][1][15] = 0
4804 01:01:59.551988 rx_lastpass[0][1][15] = 0
4805 01:01:59.552378 rx_firspass[1][0][0] = 0
4806 01:01:59.555204 rx_lastpass[1][0][0] = 0
4807 01:01:59.558714 rx_firspass[1][0][1] = 0
4808 01:01:59.559156 rx_lastpass[1][0][1] = 0
4809 01:01:59.561781 rx_firspass[1][0][2] = 0
4810 01:01:59.565714 rx_lastpass[1][0][2] = 0
4811 01:01:59.566189 rx_firspass[1][0][3] = 0
4812 01:01:59.568596 rx_lastpass[1][0][3] = 0
4813 01:01:59.572090 rx_firspass[1][0][4] = 0
4814 01:01:59.572475 rx_lastpass[1][0][4] = 0
4815 01:01:59.575273 rx_firspass[1][0][5] = 0
4816 01:01:59.578510 rx_lastpass[1][0][5] = 0
4817 01:01:59.578902 rx_firspass[1][0][6] = 0
4818 01:01:59.581971 rx_lastpass[1][0][6] = 0
4819 01:01:59.585377 rx_firspass[1][0][7] = 0
4820 01:01:59.588406 rx_lastpass[1][0][7] = 0
4821 01:01:59.588796 rx_firspass[1][0][8] = 0
4822 01:01:59.591953 rx_lastpass[1][0][8] = 0
4823 01:01:59.595243 rx_firspass[1][0][9] = 0
4824 01:01:59.595626 rx_lastpass[1][0][9] = 0
4825 01:01:59.598735 rx_firspass[1][0][10] = 0
4826 01:01:59.601970 rx_lastpass[1][0][10] = 0
4827 01:01:59.602399 rx_firspass[1][0][11] = 0
4828 01:01:59.605276 rx_lastpass[1][0][11] = 0
4829 01:01:59.608349 rx_firspass[1][0][12] = 0
4830 01:01:59.611959 rx_lastpass[1][0][12] = 0
4831 01:01:59.612350 rx_firspass[1][0][13] = 0
4832 01:01:59.615332 rx_lastpass[1][0][13] = 0
4833 01:01:59.619178 rx_firspass[1][0][14] = 0
4834 01:01:59.619656 rx_lastpass[1][0][14] = 0
4835 01:01:59.622561 rx_firspass[1][0][15] = 0
4836 01:01:59.625289 rx_lastpass[1][0][15] = 0
4837 01:01:59.625724 rx_firspass[1][1][0] = 0
4838 01:01:59.628427 rx_lastpass[1][1][0] = 0
4839 01:01:59.631871 rx_firspass[1][1][1] = 0
4840 01:01:59.635026 rx_lastpass[1][1][1] = 0
4841 01:01:59.635413 rx_firspass[1][1][2] = 0
4842 01:01:59.638736 rx_lastpass[1][1][2] = 0
4843 01:01:59.641909 rx_firspass[1][1][3] = 0
4844 01:01:59.642333 rx_lastpass[1][1][3] = 0
4845 01:01:59.645321 rx_firspass[1][1][4] = 0
4846 01:01:59.648753 rx_lastpass[1][1][4] = 0
4847 01:01:59.649225 rx_firspass[1][1][5] = 0
4848 01:01:59.651865 rx_lastpass[1][1][5] = 0
4849 01:01:59.655115 rx_firspass[1][1][6] = 0
4850 01:01:59.655500 rx_lastpass[1][1][6] = 0
4851 01:01:59.658690 rx_firspass[1][1][7] = 0
4852 01:01:59.661906 rx_lastpass[1][1][7] = 0
4853 01:01:59.662344 rx_firspass[1][1][8] = 0
4854 01:01:59.665082 rx_lastpass[1][1][8] = 0
4855 01:01:59.668710 rx_firspass[1][1][9] = 0
4856 01:01:59.671782 rx_lastpass[1][1][9] = 0
4857 01:01:59.672170 rx_firspass[1][1][10] = 0
4858 01:01:59.675105 rx_lastpass[1][1][10] = 0
4859 01:01:59.678377 rx_firspass[1][1][11] = 0
4860 01:01:59.678765 rx_lastpass[1][1][11] = 0
4861 01:01:59.681937 rx_firspass[1][1][12] = 0
4862 01:01:59.685370 rx_lastpass[1][1][12] = 0
4863 01:01:59.685756 rx_firspass[1][1][13] = 0
4864 01:01:59.688504 rx_lastpass[1][1][13] = 0
4865 01:01:59.692235 rx_firspass[1][1][14] = 0
4866 01:01:59.695419 rx_lastpass[1][1][14] = 0
4867 01:01:59.695892 rx_firspass[1][1][15] = 0
4868 01:01:59.698516 rx_lastpass[1][1][15] = 0
4869 01:01:59.702133 dump params clk_delay
4870 01:01:59.702564 clk_delay[0] = 0
4871 01:01:59.705457 clk_delay[1] = 0
4872 01:01:59.705929 dump params dqs_delay
4873 01:01:59.708752 dqs_delay[0][0] = 0
4874 01:01:59.709137 dqs_delay[0][1] = 0
4875 01:01:59.711834 dqs_delay[1][0] = 0
4876 01:01:59.712222 dqs_delay[1][1] = 0
4877 01:01:59.715209 dump params delay_cell_unit = 753
4878 01:01:59.718161 mt_set_emi_preloader end
4879 01:01:59.721748 [mt_mem_init] dram size: 0x100000000, rank number: 2
4880 01:01:59.728123 [complex_mem_test] start addr:0x40000000, len:20480
4881 01:01:59.764737 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
4882 01:01:59.770943 [complex_mem_test] start addr:0x80000000, len:20480
4883 01:01:59.806861 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
4884 01:01:59.813579 [complex_mem_test] start addr:0xc0000000, len:20480
4885 01:01:59.849160 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
4886 01:01:59.855267 [complex_mem_test] start addr:0x56000000, len:8192
4887 01:01:59.872059 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
4888 01:01:59.872491 ddr_geometry:1
4889 01:01:59.878863 [complex_mem_test] start addr:0x80000000, len:8192
4890 01:01:59.895671 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
4891 01:01:59.899270 dram_init: dram init end (result: 0)
4892 01:01:59.905978 Successfully loaded DRAM blobs and ran DRAM calibration
4893 01:01:59.915787 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
4894 01:01:59.916227 CBMEM:
4895 01:01:59.919224 IMD: root @ 00000000fffff000 254 entries.
4896 01:01:59.922744 IMD: root @ 00000000ffffec00 62 entries.
4897 01:01:59.929296 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
4898 01:01:59.936126 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
4899 01:01:59.939394 in-header: 03 a1 00 00 08 00 00 00
4900 01:01:59.942916 in-data: 84 60 60 10 00 00 00 00
4901 01:01:59.946159 Chrome EC: clear events_b mask to 0x0000000020004000
4902 01:01:59.953193 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
4903 01:01:59.956655 in-header: 03 fd 00 00 00 00 00 00
4904 01:01:59.957085 in-data:
4905 01:01:59.963411 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
4906 01:01:59.963845 CBFS @ 21000 size 3d4000
4907 01:01:59.970007 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
4908 01:01:59.973485 CBFS: Locating 'fallback/ramstage'
4909 01:01:59.976630 CBFS: Found @ offset 10d40 size d563
4910 01:01:59.997580 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
4911 01:02:00.009704 Accumulated console time in romstage 12619 ms
4912 01:02:00.010096
4913 01:02:00.010449
4914 01:02:00.019932 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
4915 01:02:00.023193 ARM64: Exception handlers installed.
4916 01:02:00.023624 ARM64: Testing exception
4917 01:02:00.026901 ARM64: Done test exception
4918 01:02:00.029963 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
4919 01:02:00.033373 Manufacturer: ef
4920 01:02:00.036441 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
4921 01:02:00.039957 WARNING: RO_VPD is uninitialized or empty.
4922 01:02:00.046798 FMAP: area RW_VPD found @ 550000 (16384 bytes)
4923 01:02:00.050176 FMAP: area RW_VPD found @ 550000 (16384 bytes)
4924 01:02:00.059714 read SPI 0x550600 0x3a00: 4533 us, 3275 KB/s, 26.200 Mbps
4925 01:02:00.062712 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
4926 01:02:00.069610 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
4927 01:02:00.070115 Enumerating buses...
4928 01:02:00.076516 Show all devs... Before device enumeration.
4929 01:02:00.077035 Root Device: enabled 1
4930 01:02:00.079822 CPU_CLUSTER: 0: enabled 1
4931 01:02:00.080339 CPU: 00: enabled 1
4932 01:02:00.082920 Compare with tree...
4933 01:02:00.086279 Root Device: enabled 1
4934 01:02:00.086708 CPU_CLUSTER: 0: enabled 1
4935 01:02:00.089770 CPU: 00: enabled 1
4936 01:02:00.090195 Root Device scanning...
4937 01:02:00.092987 root_dev_scan_bus for Root Device
4938 01:02:00.096760 CPU_CLUSTER: 0 enabled
4939 01:02:00.099711 root_dev_scan_bus for Root Device done
4940 01:02:00.103281 scan_bus: scanning of bus Root Device took 10689 usecs
4941 01:02:00.107004 done
4942 01:02:00.109889 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
4943 01:02:00.112986 Allocating resources...
4944 01:02:00.113414 Reading resources...
4945 01:02:00.116614 Root Device read_resources bus 0 link: 0
4946 01:02:00.120002 CPU_CLUSTER: 0 read_resources bus 0 link: 0
4947 01:02:00.123200 CPU: 00 missing read_resources
4948 01:02:00.129896 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
4949 01:02:00.133091 Root Device read_resources bus 0 link: 0 done
4950 01:02:00.133525 Done reading resources.
4951 01:02:00.139895 Show resources in subtree (Root Device)...After reading.
4952 01:02:00.143227 Root Device child on link 0 CPU_CLUSTER: 0
4953 01:02:00.146518 CPU_CLUSTER: 0 child on link 0 CPU: 00
4954 01:02:00.156639 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
4955 01:02:00.157139 CPU: 00
4956 01:02:00.159896 Setting resources...
4957 01:02:00.163370 Root Device assign_resources, bus 0 link: 0
4958 01:02:00.166374 CPU_CLUSTER: 0 missing set_resources
4959 01:02:00.169926 Root Device assign_resources, bus 0 link: 0
4960 01:02:00.173103 Done setting resources.
4961 01:02:00.176515 Show resources in subtree (Root Device)...After assigning values.
4962 01:02:00.183285 Root Device child on link 0 CPU_CLUSTER: 0
4963 01:02:00.186746 CPU_CLUSTER: 0 child on link 0 CPU: 00
4964 01:02:00.193339 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
4965 01:02:00.196787 CPU: 00
4966 01:02:00.197186 Done allocating resources.
4967 01:02:00.203351 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
4968 01:02:00.203743 Enabling resources...
4969 01:02:00.204051 done.
4970 01:02:00.210134 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
4971 01:02:00.210571 Initializing devices...
4972 01:02:00.213500 Root Device init ...
4973 01:02:00.216707 mainboard_init: Starting display init.
4974 01:02:00.219984 ADC[4]: Raw value=77032 ID=0
4975 01:02:00.242273 anx7625_power_on_init: Init interface.
4976 01:02:00.245479 anx7625_disable_pd_protocol: Disabled PD feature.
4977 01:02:00.252010 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
4978 01:02:00.309122 anx7625_start_dp_work: Secure OCM version=00
4979 01:02:00.312727 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
4980 01:02:00.329990 sp_tx_get_edid_block: EDID Block = 1
4981 01:02:00.447110 Extracted contents:
4982 01:02:00.450471 header: 00 ff ff ff ff ff ff 00
4983 01:02:00.453527 serial number: 06 af 5c 14 00 00 00 00 00 1a
4984 01:02:00.456975 version: 01 04
4985 01:02:00.460493 basic params: 95 1a 0e 78 02
4986 01:02:00.463828 chroma info: 99 85 95 55 56 92 28 22 50 54
4987 01:02:00.467158 established: 00 00 00
4988 01:02:00.473853 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
4989 01:02:00.477045 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
4990 01:02:00.483642 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
4991 01:02:00.490325 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
4992 01:02:00.497076 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
4993 01:02:00.500611 extensions: 00
4994 01:02:00.501125 checksum: ae
4995 01:02:00.501465
4996 01:02:00.503980 Manufacturer: AUO Model 145c Serial Number 0
4997 01:02:00.506785 Made week 0 of 2016
4998 01:02:00.507240 EDID version: 1.4
4999 01:02:00.510282 Digital display
5000 01:02:00.513416 6 bits per primary color channel
5001 01:02:00.513860 DisplayPort interface
5002 01:02:00.517430 Maximum image size: 26 cm x 14 cm
5003 01:02:00.520244 Gamma: 220%
5004 01:02:00.520760 Check DPMS levels
5005 01:02:00.523905 Supported color formats: RGB 4:4:4
5006 01:02:00.527009 First detailed timing is preferred timing
5007 01:02:00.530394 Established timings supported:
5008 01:02:00.533687 Standard timings supported:
5009 01:02:00.534388 Detailed timings
5010 01:02:00.536660 Hex of detail: ce1d56ea50001a3030204600009010000018
5011 01:02:00.543488 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5012 01:02:00.547057 0556 0586 05a6 0640 hborder 0
5013 01:02:00.550291 0300 0304 030a 031a vborder 0
5014 01:02:00.553716 -hsync -vsync
5015 01:02:00.556862 Did detailed timing
5016 01:02:00.560165 Hex of detail: 0000000f0000000000000000000000000020
5017 01:02:00.563724 Manufacturer-specified data, tag 15
5018 01:02:00.566744 Hex of detail: 000000fe0041554f0a202020202020202020
5019 01:02:00.570309 ASCII string: AUO
5020 01:02:00.573749 Hex of detail: 000000fe004231313658414230312e34200a
5021 01:02:00.577156 ASCII string: B116XAB01.4
5022 01:02:00.577670 Checksum
5023 01:02:00.580066 Checksum: 0xae (valid)
5024 01:02:00.583562 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5025 01:02:00.587007 DSI data_rate: 457800000 bps
5026 01:02:00.594110 anx7625_parse_edid: set default k value to 0x3d for panel
5027 01:02:00.597351 anx7625_parse_edid: pixelclock(76300).
5028 01:02:00.600829 hactive(1366), hsync(32), hfp(48), hbp(154)
5029 01:02:00.604124 vactive(768), vsync(6), vfp(4), vbp(16)
5030 01:02:00.607221 anx7625_dsi_config: config dsi.
5031 01:02:00.615153 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5032 01:02:00.636068 anx7625_dsi_config: success to config DSI
5033 01:02:00.639687 anx7625_dp_start: MIPI phy setup OK.
5034 01:02:00.642594 [SSUSB] Setting up USB HOST controller...
5035 01:02:00.645928 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5036 01:02:00.649310 [SSUSB] phy power-on done.
5037 01:02:00.653152 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5038 01:02:00.656513 in-header: 03 fc 01 00 00 00 00 00
5039 01:02:00.656947 in-data:
5040 01:02:00.663448 handle_proto3_response: EC response with error code: 1
5041 01:02:00.663917 SPM: pcm index = 1
5042 01:02:00.666714 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5043 01:02:00.669921 CBFS @ 21000 size 3d4000
5044 01:02:00.676643 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5045 01:02:00.680166 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5046 01:02:00.683743 CBFS: Found @ offset 1e7c0 size 1026
5047 01:02:00.689910 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5048 01:02:00.693020 SPM: binary array size = 2988
5049 01:02:00.696871 SPM: version = pcm_allinone_v1.17.2_20180829
5050 01:02:00.699944 SPM binary loaded in 32 msecs
5051 01:02:00.707166 spm_kick_im_to_fetch: ptr = 000000004021eec2
5052 01:02:00.710677 spm_kick_im_to_fetch: len = 2988
5053 01:02:00.711068 SPM: spm_kick_pcm_to_run
5054 01:02:00.713935 SPM: spm_kick_pcm_to_run done
5055 01:02:00.717288 SPM: spm_init done in 52 msecs
5056 01:02:00.721215 Root Device init finished in 505265 usecs
5057 01:02:00.723925 CPU_CLUSTER: 0 init ...
5058 01:02:00.730804 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5059 01:02:00.737355 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5060 01:02:00.741150 CBFS @ 21000 size 3d4000
5061 01:02:00.744118 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5062 01:02:00.747298 CBFS: Locating 'sspm.bin'
5063 01:02:00.750611 CBFS: Found @ offset 208c0 size 41cb
5064 01:02:00.760421 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5065 01:02:00.768187 CPU_CLUSTER: 0 init finished in 42797 usecs
5066 01:02:00.768577 Devices initialized
5067 01:02:00.771915 Show all devs... After init.
5068 01:02:00.774992 Root Device: enabled 1
5069 01:02:00.775388 CPU_CLUSTER: 0: enabled 1
5070 01:02:00.778494 CPU: 00: enabled 1
5071 01:02:00.781632 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5072 01:02:00.785078 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5073 01:02:00.788302 ELOG: NV offset 0x558000 size 0x1000
5074 01:02:00.795774 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5075 01:02:00.802573 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5076 01:02:00.805634 ELOG: Event(17) added with size 13 at 2024-06-16 01:02:00 UTC
5077 01:02:00.808962 out: cmd=0x121: 03 db 21 01 00 00 00 00
5078 01:02:00.812663 in-header: 03 22 00 00 2c 00 00 00
5079 01:02:00.825889 in-data: aa 48 00 00 00 00 00 00 02 10 00 00 06 80 00 00 88 a8 01 00 06 80 00 00 9a b0 02 00 06 80 00 00 2a 0e 01 00 06 80 00 00 e0 fc 01 00
5080 01:02:00.829047 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5081 01:02:00.832531 in-header: 03 19 00 00 08 00 00 00
5082 01:02:00.835724 in-data: a2 e0 47 00 13 00 00 00
5083 01:02:00.839253 Chrome EC: UHEPI supported
5084 01:02:00.845906 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5085 01:02:00.849479 in-header: 03 e1 00 00 08 00 00 00
5086 01:02:00.852256 in-data: 84 20 60 10 00 00 00 00
5087 01:02:00.855931 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5088 01:02:00.862468 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5089 01:02:00.865904 in-header: 03 e1 00 00 08 00 00 00
5090 01:02:00.869643 in-data: 84 20 60 10 00 00 00 00
5091 01:02:00.876173 ELOG: Event(A1) added with size 10 at 2024-06-16 01:02:00 UTC
5092 01:02:00.883106 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5093 01:02:00.886434 ELOG: Event(A0) added with size 9 at 2024-06-16 01:02:00 UTC
5094 01:02:00.889580 elog_add_boot_reason: Logged dev mode boot
5095 01:02:00.892561 Finalize devices...
5096 01:02:00.893094 Devices finalized
5097 01:02:00.899808 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5098 01:02:00.902826 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5099 01:02:00.909699 ELOG: Event(91) added with size 10 at 2024-06-16 01:02:00 UTC
5100 01:02:00.912692 Writing coreboot table at 0xffeda000
5101 01:02:00.916020 0. 0000000000114000-000000000011efff: RAMSTAGE
5102 01:02:00.922701 1. 0000000040000000-000000004023cfff: RAMSTAGE
5103 01:02:00.926203 2. 000000004023d000-00000000545fffff: RAM
5104 01:02:00.929775 3. 0000000054600000-000000005465ffff: BL31
5105 01:02:00.932667 4. 0000000054660000-00000000ffed9fff: RAM
5106 01:02:00.939494 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5107 01:02:00.942543 6. 0000000100000000-000000013fffffff: RAM
5108 01:02:00.942965 Passing 5 GPIOs to payload:
5109 01:02:00.949895 NAME | PORT | POLARITY | VALUE
5110 01:02:00.953099 write protect | 0x00000096 | low | high
5111 01:02:00.959632 EC in RW | 0x000000b1 | high | undefined
5112 01:02:00.962799 EC interrupt | 0x00000097 | low | undefined
5113 01:02:00.966414 TPM interrupt | 0x00000099 | high | undefined
5114 01:02:00.972809 speaker enable | 0x000000af | high | undefined
5115 01:02:00.976107 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5116 01:02:00.979524 in-header: 03 f7 00 00 02 00 00 00
5117 01:02:00.979970 in-data: 04 00
5118 01:02:00.982792 Board ID: 4
5119 01:02:00.983223 ADC[3]: Raw value=1040656 ID=8
5120 01:02:00.986273 RAM code: 8
5121 01:02:00.986707 SKU ID: 16
5122 01:02:00.989509 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5123 01:02:00.993189 CBFS @ 21000 size 3d4000
5124 01:02:00.999795 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5125 01:02:01.003052 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 5a2
5126 01:02:01.006536 coreboot table: 940 bytes.
5127 01:02:01.009893 IMD ROOT 0. 00000000fffff000 00001000
5128 01:02:01.013058 IMD SMALL 1. 00000000ffffe000 00001000
5129 01:02:01.016419 CONSOLE 2. 00000000fffde000 00020000
5130 01:02:01.023131 FMAP 3. 00000000fffdd000 0000047c
5131 01:02:01.026199 TIME STAMP 4. 00000000fffdc000 00000910
5132 01:02:01.029571 RAMOOPS 5. 00000000ffedc000 00100000
5133 01:02:01.032945 COREBOOT 6. 00000000ffeda000 00002000
5134 01:02:01.033283 IMD small region:
5135 01:02:01.036473 IMD ROOT 0. 00000000ffffec00 00000400
5136 01:02:01.043161 VBOOT WORK 1. 00000000ffffeb00 00000100
5137 01:02:01.046274 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5138 01:02:01.049629 VPD 3. 00000000ffffea60 0000006c
5139 01:02:01.052683 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5140 01:02:01.059165 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5141 01:02:01.062799 in-header: 03 e1 00 00 08 00 00 00
5142 01:02:01.065832 in-data: 84 20 60 10 00 00 00 00
5143 01:02:01.072552 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5144 01:02:01.072944 CBFS @ 21000 size 3d4000
5145 01:02:01.079510 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5146 01:02:01.082709 CBFS: Locating 'fallback/payload'
5147 01:02:01.089943 CBFS: Found @ offset dc040 size 439a0
5148 01:02:01.177419 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5149 01:02:01.180716 Checking segment from ROM address 0x0000000040003a00
5150 01:02:01.187647 Checking segment from ROM address 0x0000000040003a1c
5151 01:02:01.191060 Loading segment from ROM address 0x0000000040003a00
5152 01:02:01.194254 code (compression=0)
5153 01:02:01.201243 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5154 01:02:01.211429 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5155 01:02:01.211771 it's not compressed!
5156 01:02:01.218551 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5157 01:02:01.225026 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5158 01:02:01.232272 Loading segment from ROM address 0x0000000040003a1c
5159 01:02:01.235199 Entry Point 0x0000000080000000
5160 01:02:01.235601 Loaded segments
5161 01:02:01.241921 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5162 01:02:01.245384 Jumping to boot code at 0000000080000000(00000000ffeda000)
5163 01:02:01.255150 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5164 01:02:01.258383 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5165 01:02:01.261888 CBFS @ 21000 size 3d4000
5166 01:02:01.268534 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5167 01:02:01.271812 CBFS: Locating 'fallback/bl31'
5168 01:02:01.275130 CBFS: Found @ offset 36dc0 size 5820
5169 01:02:01.286094 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5170 01:02:01.289214 Checking segment from ROM address 0x0000000040003a00
5171 01:02:01.295999 Checking segment from ROM address 0x0000000040003a1c
5172 01:02:01.299395 Loading segment from ROM address 0x0000000040003a00
5173 01:02:01.302740 code (compression=1)
5174 01:02:01.309352 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5175 01:02:01.319174 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5176 01:02:01.319563 using LZMA
5177 01:02:01.328030 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5178 01:02:01.334830 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5179 01:02:01.337963 Loading segment from ROM address 0x0000000040003a1c
5180 01:02:01.341336 Entry Point 0x0000000054601000
5181 01:02:01.341734 Loaded segments
5182 01:02:01.344616 NOTICE: MT8183 bl31_setup
5183 01:02:01.351714 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5184 01:02:01.354928 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5185 01:02:01.358175 INFO: [DEVAPC] dump DEVAPC registers:
5186 01:02:01.368125 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5187 01:02:01.374812 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5188 01:02:01.385096 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5189 01:02:01.391686 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5190 01:02:01.401668 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5191 01:02:01.408324 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5192 01:02:01.415115 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5193 01:02:01.425107 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5194 01:02:01.431737 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5195 01:02:01.441739 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5196 01:02:01.448518 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5197 01:02:01.458519 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5198 01:02:01.465188 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5199 01:02:01.471692 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5200 01:02:01.481797 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5201 01:02:01.488689 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5202 01:02:01.495304 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5203 01:02:01.502059 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5204 01:02:01.508608 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5205 01:02:01.515262 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5206 01:02:01.525125 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5207 01:02:01.532108 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5208 01:02:01.535196 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5209 01:02:01.538606 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5210 01:02:01.542309 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5211 01:02:01.545406 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5212 01:02:01.548995 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5213 01:02:01.555454 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5214 01:02:01.558673 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5215 01:02:01.562181 WARNING: region 0:
5216 01:02:01.565294 WARNING: apc:0x168, sa:0x0, ea:0xfff
5217 01:02:01.565652 WARNING: region 1:
5218 01:02:01.568884 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5219 01:02:01.572107 WARNING: region 2:
5220 01:02:01.575569 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5221 01:02:01.575960 WARNING: region 3:
5222 01:02:01.582155 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5223 01:02:01.582633 WARNING: region 4:
5224 01:02:01.585377 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5225 01:02:01.589121 WARNING: region 5:
5226 01:02:01.592106 WARNING: apc:0x0, sa:0x0, ea:0x0
5227 01:02:01.592492 WARNING: region 6:
5228 01:02:01.595450 WARNING: apc:0x0, sa:0x0, ea:0x0
5229 01:02:01.599175 WARNING: region 7:
5230 01:02:01.599557 WARNING: apc:0x0, sa:0x0, ea:0x0
5231 01:02:01.608938 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5232 01:02:01.612141 INFO: SPM: enable SPMC mode
5233 01:02:01.612524 NOTICE: spm_boot_init() start
5234 01:02:01.615494 NOTICE: spm_boot_init() end
5235 01:02:01.618776 INFO: BL31: Initializing runtime services
5236 01:02:01.625445 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5237 01:02:01.628840 INFO: BL31: Preparing for EL3 exit to normal world
5238 01:02:01.635664 INFO: Entry point address = 0x80000000
5239 01:02:01.636051 INFO: SPSR = 0x8
5240 01:02:01.658157
5241 01:02:01.658631
5242 01:02:01.659054
5243 01:02:01.660648 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
5244 01:02:01.661239 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
5245 01:02:01.661730 Setting prompt string to ['jacuzzi:']
5246 01:02:01.662194 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:28)
5247 01:02:01.663242 Starting depthcharge on Juniper...
5248 01:02:01.663687
5249 01:02:01.664775 vboot_handoff: creating legacy vboot_handoff structure
5250 01:02:01.665103
5251 01:02:01.668287 ec_init(0): CrosEC protocol v3 supported (544, 544)
5252 01:02:01.668717
5253 01:02:01.672087 Wipe memory regions:
5254 01:02:01.672595
5255 01:02:01.674787 [0x00000040000000, 0x00000054600000)
5256 01:02:01.717501
5257 01:02:01.717942 [0x00000054660000, 0x00000080000000)
5258 01:02:01.808688
5259 01:02:01.808782 [0x000000811994a0, 0x000000ffeda000)
5260 01:02:02.069114
5261 01:02:02.069620 [0x00000100000000, 0x00000140000000)
5262 01:02:02.202028
5263 01:02:02.205511 Initializing XHCI USB controller at 0x11200000.
5264 01:02:02.228506
5265 01:02:02.231788 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5266 01:02:02.232298
5267 01:02:02.232635
5268 01:02:02.233393 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5270 01:02:02.334651 jacuzzi: tftpboot 192.168.201.1 14368623/tftp-deploy-v7j96_eo/kernel/image.itb 14368623/tftp-deploy-v7j96_eo/kernel/cmdline
5271 01:02:02.335358 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5272 01:02:02.335772 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:27)
5273 01:02:02.340262 tftpboot 192.168.201.1 14368623/tftp-deploy-v7j96_eo/kernel/image.ittp-deploy-v7j96_eo/kernel/cmdline
5274 01:02:02.340696
5275 01:02:02.341032 Waiting for link
5276 01:02:02.888222
5277 01:02:02.888356 R8152: Initializing
5278 01:02:02.888414
5279 01:02:02.891419 Version 9 (ocp_data = 6010)
5280 01:02:02.891493
5281 01:02:02.894866 R8152: Done initializing
5282 01:02:02.894944
5283 01:02:02.895005 Adding net device
5284 01:02:03.074188
5285 01:02:03.074757 R8152: Initializing
5286 01:02:03.075091
5287 01:02:03.077402 Version 9 (ocp_data = 6010)
5288 01:02:03.077824
5289 01:02:03.081124 R8152: Done initializing
5290 01:02:03.081631
5291 01:02:03.083920 net_add_device: Attemp to include the same device
5292 01:02:03.470327
5293 01:02:03.470726 done.
5294 01:02:03.471064
5295 01:02:03.471384 MAC: 00:e0:4c:68:03:2b
5296 01:02:03.471644
5297 01:02:03.473431 Sending DHCP discover... done.
5298 01:02:03.473779
5299 01:02:03.476829 Waiting for reply... done.
5300 01:02:03.477211
5301 01:02:03.480146 Sending DHCP request... done.
5302 01:02:03.480528
5303 01:02:03.484239 Waiting for reply... done.
5304 01:02:03.484617
5305 01:02:03.484908 My ip is 192.168.201.17
5306 01:02:03.485183
5307 01:02:03.487102 The DHCP server ip is 192.168.201.1
5308 01:02:03.487486
5309 01:02:03.493965 TFTP server IP predefined by user: 192.168.201.1
5310 01:02:03.494418
5311 01:02:03.500520 Bootfile predefined by user: 14368623/tftp-deploy-v7j96_eo/kernel/image.itb
5312 01:02:03.500906
5313 01:02:03.501200 Sending tftp read request... done.
5314 01:02:03.503588
5315 01:02:03.510312 Waiting for the transfer...
5316 01:02:03.510781
5317 01:02:03.797588 00000000 ################################################################
5318 01:02:03.797723
5319 01:02:04.059420 00080000 ################################################################
5320 01:02:04.059564
5321 01:02:04.345363 00100000 ################################################################
5322 01:02:04.345500
5323 01:02:04.662158 00180000 ################################################################
5324 01:02:04.662321
5325 01:02:05.007084 00200000 ################################################################
5326 01:02:05.007214
5327 01:02:05.348441 00280000 ################################################################
5328 01:02:05.348569
5329 01:02:05.647822 00300000 ################################################################
5330 01:02:05.647979
5331 01:02:05.951600 00380000 ################################################################
5332 01:02:05.951736
5333 01:02:06.241695 00400000 ################################################################
5334 01:02:06.241822
5335 01:02:06.500858 00480000 ################################################################
5336 01:02:06.500985
5337 01:02:06.799561 00500000 ################################################################
5338 01:02:06.799685
5339 01:02:07.079389 00580000 ################################################################
5340 01:02:07.079515
5341 01:02:07.370192 00600000 ################################################################
5342 01:02:07.370339
5343 01:02:07.659328 00680000 ################################################################
5344 01:02:07.659821
5345 01:02:08.070386 00700000 ################################################################
5346 01:02:08.070895
5347 01:02:08.471003 00780000 ################################################################
5348 01:02:08.471487
5349 01:02:08.912093 00800000 ################################################################
5350 01:02:08.912542
5351 01:02:09.229271 00880000 ################################################################
5352 01:02:09.229400
5353 01:02:09.531747 00900000 ################################################################
5354 01:02:09.531876
5355 01:02:09.791793 00980000 ################################################################
5356 01:02:09.791922
5357 01:02:10.046686 00a00000 ################################################################
5358 01:02:10.046805
5359 01:02:10.301328 00a80000 ################################################################
5360 01:02:10.301450
5361 01:02:10.555102 00b00000 ################################################################
5362 01:02:10.555219
5363 01:02:10.828477 00b80000 ################################################################
5364 01:02:10.828599
5365 01:02:11.102558 00c00000 ################################################################
5366 01:02:11.102680
5367 01:02:11.396445 00c80000 ################################################################
5368 01:02:11.396564
5369 01:02:11.772467 00d00000 ################################################################
5370 01:02:11.772928
5371 01:02:12.175431 00d80000 ################################################################
5372 01:02:12.175928
5373 01:02:12.571869 00e00000 ################################################################
5374 01:02:12.572440
5375 01:02:12.972764 00e80000 ################################################################
5376 01:02:12.973227
5377 01:02:13.347727 00f00000 ################################################################
5378 01:02:13.348305
5379 01:02:13.730193 00f80000 ################################################################
5380 01:02:13.730691
5381 01:02:14.152507 01000000 ################################################################
5382 01:02:14.152968
5383 01:02:14.542337 01080000 ################################################################
5384 01:02:14.542804
5385 01:02:14.873565 01100000 ################################################################
5386 01:02:14.873689
5387 01:02:15.159902 01180000 ################################################################
5388 01:02:15.160054
5389 01:02:15.459899 01200000 ################################################################
5390 01:02:15.460019
5391 01:02:15.763395 01280000 ################################################################
5392 01:02:15.763520
5393 01:02:16.066470 01300000 ################################################################
5394 01:02:16.066593
5395 01:02:16.344699 01380000 ################################################################
5396 01:02:16.344819
5397 01:02:16.619178 01400000 ################################################################
5398 01:02:16.619304
5399 01:02:16.885834 01480000 ################################################################
5400 01:02:16.885957
5401 01:02:17.152337 01500000 ################################################################
5402 01:02:17.152460
5403 01:02:17.415321 01580000 ################################################################
5404 01:02:17.415446
5405 01:02:17.709641 01600000 ################################################################
5406 01:02:17.709767
5407 01:02:18.004632 01680000 ################################################################
5408 01:02:18.004756
5409 01:02:18.303154 01700000 ################################################################
5410 01:02:18.303278
5411 01:02:18.602131 01780000 ################################################################
5412 01:02:18.602294
5413 01:02:18.901987 01800000 ################################################################
5414 01:02:18.902110
5415 01:02:19.201144 01880000 ################################################################
5416 01:02:19.201263
5417 01:02:19.498893 01900000 ################################################################
5418 01:02:19.499018
5419 01:02:19.784828 01980000 ################################################################
5420 01:02:19.784946
5421 01:02:20.047272 01a00000 ################################################################
5422 01:02:20.047389
5423 01:02:20.343975 01a80000 ################################################################
5424 01:02:20.344093
5425 01:02:20.623800 01b00000 ################################################################
5426 01:02:20.623928
5427 01:02:20.918748 01b80000 ################################################################
5428 01:02:20.918869
5429 01:02:21.223352 01c00000 ################################################################
5430 01:02:21.223473
5431 01:02:21.528066 01c80000 ################################################################
5432 01:02:21.528185
5433 01:02:21.786257 01d00000 ################################################################
5434 01:02:21.786381
5435 01:02:22.077890 01d80000 ################################################################
5436 01:02:22.078008
5437 01:02:22.378030 01e00000 ################################################################
5438 01:02:22.378151
5439 01:02:22.676049 01e80000 ################################################################
5440 01:02:22.676169
5441 01:02:22.945908 01f00000 ################################################################
5442 01:02:22.946055
5443 01:02:23.201141 01f80000 ################################################################
5444 01:02:23.201258
5445 01:02:23.456183 02000000 ################################################################
5446 01:02:23.456320
5447 01:02:23.729862 02080000 ################################################################
5448 01:02:23.730000
5449 01:02:24.027865 02100000 ################################################################
5450 01:02:24.027992
5451 01:02:24.315626 02180000 ################################################################
5452 01:02:24.315751
5453 01:02:24.576487 02200000 ################################################################
5454 01:02:24.576604
5455 01:02:24.851895 02280000 ################################################################
5456 01:02:24.852014
5457 01:02:25.119743 02300000 ################################################################
5458 01:02:25.119860
5459 01:02:25.410154 02380000 ################################################################
5460 01:02:25.410321
5461 01:02:25.680799 02400000 ################################################################
5462 01:02:25.680925
5463 01:02:25.962761 02480000 ################################################################
5464 01:02:25.962882
5465 01:02:26.262629 02500000 ################################################################
5466 01:02:26.262748
5467 01:02:26.537646 02580000 ################################################################
5468 01:02:26.537770
5469 01:02:26.792008 02600000 ################################################################
5470 01:02:26.792124
5471 01:02:27.057129 02680000 ################################################################
5472 01:02:27.057252
5473 01:02:27.318848 02700000 ################################################################
5474 01:02:27.318963
5475 01:02:27.615530 02780000 ################################################################
5476 01:02:27.615653
5477 01:02:27.899868 02800000 ################################################################
5478 01:02:27.899994
5479 01:02:28.199235 02880000 ################################################################
5480 01:02:28.199361
5481 01:02:28.496942 02900000 ################################################################
5482 01:02:28.497059
5483 01:02:28.794295 02980000 ################################################################
5484 01:02:28.794419
5485 01:02:29.079739 02a00000 ################################################################
5486 01:02:29.079860
5487 01:02:29.379028 02a80000 ################################################################
5488 01:02:29.379171
5489 01:02:29.677457 02b00000 ################################################################
5490 01:02:29.677578
5491 01:02:29.973975 02b80000 ################################################################
5492 01:02:29.974130
5493 01:02:30.226726 02c00000 ################################################################
5494 01:02:30.226848
5495 01:02:30.481477 02c80000 ################################################################
5496 01:02:30.481596
5497 01:02:30.736648 02d00000 ################################################################
5498 01:02:30.736767
5499 01:02:31.021646 02d80000 ################################################################
5500 01:02:31.021764
5501 01:02:31.314773 02e00000 ################################################################
5502 01:02:31.314896
5503 01:02:31.588415 02e80000 ################################################################
5504 01:02:31.588541
5505 01:02:31.868803 02f00000 ################################################################
5506 01:02:31.868920
5507 01:02:32.169245 02f80000 ################################################################
5508 01:02:32.169364
5509 01:02:32.468573 03000000 ################################################################
5510 01:02:32.468700
5511 01:02:32.765005 03080000 ################################################################
5512 01:02:32.765128
5513 01:02:33.063710 03100000 ################################################################
5514 01:02:33.063833
5515 01:02:33.368208 03180000 ################################################################
5516 01:02:33.368328
5517 01:02:33.655111 03200000 ################################################################
5518 01:02:33.655236
5519 01:02:33.927458 03280000 ################################################################
5520 01:02:33.927579
5521 01:02:34.203564 03300000 ################################################################
5522 01:02:34.203687
5523 01:02:34.437492 03380000 ################################################## done.
5524 01:02:34.437611
5525 01:02:34.440670 The bootfile was 54409350 bytes long.
5526 01:02:34.440817
5527 01:02:34.443898 Sending tftp read request... done.
5528 01:02:34.443997
5529 01:02:34.444068 Waiting for the transfer...
5530 01:02:34.444131
5531 01:02:34.447514 00000000 # done.
5532 01:02:34.447602
5533 01:02:34.454287 Command line loaded dynamically from TFTP file: 14368623/tftp-deploy-v7j96_eo/kernel/cmdline
5534 01:02:34.454451
5535 01:02:34.470953 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5536 01:02:34.471170
5537 01:02:34.474054 Loading FIT.
5538 01:02:34.474278
5539 01:02:34.477647 Image ramdisk-1 has 41224565 bytes.
5540 01:02:34.477803
5541 01:02:34.477925 Image fdt-1 has 57695 bytes.
5542 01:02:34.478086
5543 01:02:34.480690 Image kernel-1 has 13125045 bytes.
5544 01:02:34.480929
5545 01:02:34.491011 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5546 01:02:34.491344
5547 01:02:34.504796 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5548 01:02:34.505313
5549 01:02:34.507923 Choosing best match conf-1 for compat google,juniper-sku16.
5550 01:02:34.512998
5551 01:02:34.517474 Connected to device vid:did:rid of 1ae0:0028:00
5552 01:02:34.524534
5553 01:02:34.527570 tpm_get_response: command 0x17b, return code 0x0
5554 01:02:34.528002
5555 01:02:34.531280 tpm_cleanup: add release locality here.
5556 01:02:34.531703
5557 01:02:34.534901 Shutting down all USB controllers.
5558 01:02:34.535401
5559 01:02:34.538206 Removing current net device
5560 01:02:34.538764
5561 01:02:34.541136 Exiting depthcharge with code 4 at timestamp: 49043770
5562 01:02:34.541562
5563 01:02:34.545057 LZMA decompressing kernel-1 to 0x80193568
5564 01:02:34.545560
5565 01:02:34.547894 LZMA decompressing kernel-1 to 0x40000000
5566 01:02:36.414927
5567 01:02:36.415433 jumping to kernel
5568 01:02:36.417532 end: 2.2.4 bootloader-commands (duration 00:00:35) [common]
5569 01:02:36.418018 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
5570 01:02:36.418427 Setting prompt string to ['Linux version [0-9]']
5571 01:02:36.418793 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5572 01:02:36.419143 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5573 01:02:36.490508
5574 01:02:36.493691 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5575 01:02:36.497328 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
5576 01:02:36.497897 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5577 01:02:36.498327 Setting prompt string to []
5578 01:02:36.498731 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5579 01:02:36.499093 Using line separator: #'\n'#
5580 01:02:36.499394 No login prompt set.
5581 01:02:36.499792 Parsing kernel messages
5582 01:02:36.500113 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5583 01:02:36.500641 [login-action] Waiting for messages, (timeout 00:03:53)
5584 01:02:36.500990 Waiting using forced prompt support (timeout 00:01:56)
5585 01:02:36.516779 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
5586 01:02:36.520653 [ 0.000000] random: crng init done
5587 01:02:36.526930 [ 0.000000] Machine model: Google juniper sku16 board
5588 01:02:36.530589 [ 0.000000] efi: UEFI not found.
5589 01:02:36.537126 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5590 01:02:36.544338 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5591 01:02:36.553816 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5592 01:02:36.557135 [ 0.000000] printk: bootconsole [mtk8250] enabled
5593 01:02:36.565647 [ 0.000000] NUMA: No NUMA configuration found
5594 01:02:36.571778 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5595 01:02:36.578700 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5596 01:02:36.579208 [ 0.000000] Zone ranges:
5597 01:02:36.585589 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5598 01:02:36.588574 [ 0.000000] DMA32 empty
5599 01:02:36.595154 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5600 01:02:36.598431 [ 0.000000] Movable zone start for each node
5601 01:02:36.602605 [ 0.000000] Early memory node ranges
5602 01:02:36.608527 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5603 01:02:36.615445 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5604 01:02:36.622081 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5605 01:02:36.629109 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5606 01:02:36.632177 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5607 01:02:36.642017 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5608 01:02:36.657782 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5609 01:02:36.664373 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5610 01:02:36.671024 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5611 01:02:36.674340 [ 0.000000] psci: probing for conduit method from DT.
5612 01:02:36.680867 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5613 01:02:36.684176 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5614 01:02:36.691114 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5615 01:02:36.694415 [ 0.000000] psci: SMC Calling Convention v1.1
5616 01:02:36.701050 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5617 01:02:36.704230 [ 0.000000] Detected VIPT I-cache on CPU0
5618 01:02:36.710815 [ 0.000000] CPU features: detected: GIC system register CPU interface
5619 01:02:36.717813 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5620 01:02:36.724479 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5621 01:02:36.727605 [ 0.000000] CPU features: detected: ARM erratum 845719
5622 01:02:36.734766 [ 0.000000] alternatives: applying boot alternatives
5623 01:02:36.737917 [ 0.000000] Fallback order for Node 0: 0
5624 01:02:36.744346 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5625 01:02:36.747817 [ 0.000000] Policy zone: Normal
5626 01:02:36.767883 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5627 01:02:36.777329 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5628 01:02:36.788199 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5629 01:02:36.794432 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5630 01:02:36.801015 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5631 01:02:36.807525 <6>[ 0.000000] software IO TLB: area num 8.
5632 01:02:36.832322 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5633 01:02:36.890310 <6>[ 0.000000] Memory: 3874816K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 283648K reserved, 32768K cma-reserved)
5634 01:02:36.897069 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5635 01:02:36.903321 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5636 01:02:36.906769 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5637 01:02:36.913167 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5638 01:02:36.920046 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5639 01:02:36.923445 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5640 01:02:36.933779 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5641 01:02:36.940332 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5642 01:02:36.943409 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5643 01:02:36.955452 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5644 01:02:36.962243 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5645 01:02:36.965510 <6>[ 0.000000] GICv3: 640 SPIs implemented
5646 01:02:36.968973 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5647 01:02:36.975471 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5648 01:02:36.979038 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5649 01:02:36.985402 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5650 01:02:36.995678 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5651 01:02:37.008380 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5652 01:02:37.015158 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5653 01:02:37.027038 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5654 01:02:37.040701 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5655 01:02:37.047416 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5656 01:02:37.054461 <6>[ 0.009479] Console: colour dummy device 80x25
5657 01:02:37.057044 <6>[ 0.014518] printk: console [tty1] enabled
5658 01:02:37.067144 <6>[ 0.018902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5659 01:02:37.074071 <6>[ 0.029367] pid_max: default: 32768 minimum: 301
5660 01:02:37.077615 <6>[ 0.034248] LSM: Security Framework initializing
5661 01:02:37.087167 <6>[ 0.039164] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5662 01:02:37.093906 <6>[ 0.046788] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5663 01:02:37.100904 <4>[ 0.055665] cacheinfo: Unable to detect cache hierarchy for CPU 0
5664 01:02:37.110449 <6>[ 0.062292] cblist_init_generic: Setting adjustable number of callback queues.
5665 01:02:37.113709 <6>[ 0.069737] cblist_init_generic: Setting shift to 3 and lim to 1.
5666 01:02:37.124146 <6>[ 0.076090] cblist_init_generic: Setting adjustable number of callback queues.
5667 01:02:37.130540 <6>[ 0.083534] cblist_init_generic: Setting shift to 3 and lim to 1.
5668 01:02:37.133898 <6>[ 0.089933] rcu: Hierarchical SRCU implementation.
5669 01:02:37.140666 <6>[ 0.094958] rcu: Max phase no-delay instances is 1000.
5670 01:02:37.147330 <6>[ 0.102894] EFI services will not be available.
5671 01:02:37.150672 <6>[ 0.107839] smp: Bringing up secondary CPUs ...
5672 01:02:37.161162 <6>[ 0.113133] Detected VIPT I-cache on CPU1
5673 01:02:37.167595 <4>[ 0.113181] cacheinfo: Unable to detect cache hierarchy for CPU 1
5674 01:02:37.174555 <6>[ 0.113190] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5675 01:02:37.181339 <6>[ 0.113222] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5676 01:02:37.184722 <6>[ 0.113703] Detected VIPT I-cache on CPU2
5677 01:02:37.191283 <4>[ 0.113736] cacheinfo: Unable to detect cache hierarchy for CPU 2
5678 01:02:37.197444 <6>[ 0.113741] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5679 01:02:37.204357 <6>[ 0.113752] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5680 01:02:37.207646 <6>[ 0.114198] Detected VIPT I-cache on CPU3
5681 01:02:37.214126 <4>[ 0.114228] cacheinfo: Unable to detect cache hierarchy for CPU 3
5682 01:02:37.221254 <6>[ 0.114233] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5683 01:02:37.227383 <6>[ 0.114244] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5684 01:02:37.234148 <6>[ 0.114819] CPU features: detected: Spectre-v2
5685 01:02:37.237808 <6>[ 0.114828] CPU features: detected: Spectre-BHB
5686 01:02:37.244454 <6>[ 0.114833] CPU features: detected: ARM erratum 858921
5687 01:02:37.247400 <6>[ 0.114838] Detected VIPT I-cache on CPU4
5688 01:02:37.254325 <4>[ 0.114886] cacheinfo: Unable to detect cache hierarchy for CPU 4
5689 01:02:37.260736 <6>[ 0.114894] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5690 01:02:37.267661 <6>[ 0.114902] arch_timer: Enabling local workaround for ARM erratum 858921
5691 01:02:37.274943 <6>[ 0.114912] arch_timer: CPU4: Trapping CNTVCT access
5692 01:02:37.280899 <6>[ 0.114920] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5693 01:02:37.284439 <6>[ 0.115406] Detected VIPT I-cache on CPU5
5694 01:02:37.291042 <4>[ 0.115446] cacheinfo: Unable to detect cache hierarchy for CPU 5
5695 01:02:37.297998 <6>[ 0.115452] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5696 01:02:37.304865 <6>[ 0.115458] arch_timer: Enabling local workaround for ARM erratum 858921
5697 01:02:37.311045 <6>[ 0.115465] arch_timer: CPU5: Trapping CNTVCT access
5698 01:02:37.317889 <6>[ 0.115470] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5699 01:02:37.320954 <6>[ 0.115906] Detected VIPT I-cache on CPU6
5700 01:02:37.327659 <4>[ 0.115950] cacheinfo: Unable to detect cache hierarchy for CPU 6
5701 01:02:37.334366 <6>[ 0.115956] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5702 01:02:37.341040 <6>[ 0.115963] arch_timer: Enabling local workaround for ARM erratum 858921
5703 01:02:37.347644 <6>[ 0.115970] arch_timer: CPU6: Trapping CNTVCT access
5704 01:02:37.354073 <6>[ 0.115975] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5705 01:02:37.357355 <6>[ 0.116506] Detected VIPT I-cache on CPU7
5706 01:02:37.364430 <4>[ 0.116550] cacheinfo: Unable to detect cache hierarchy for CPU 7
5707 01:02:37.370658 <6>[ 0.116556] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5708 01:02:37.377319 <6>[ 0.116563] arch_timer: Enabling local workaround for ARM erratum 858921
5709 01:02:37.384024 <6>[ 0.116570] arch_timer: CPU7: Trapping CNTVCT access
5710 01:02:37.390816 <6>[ 0.116575] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5711 01:02:37.394102 <6>[ 0.116626] smp: Brought up 1 node, 8 CPUs
5712 01:02:37.400915 <6>[ 0.355493] SMP: Total of 8 processors activated.
5713 01:02:37.404333 <6>[ 0.360429] CPU features: detected: 32-bit EL0 Support
5714 01:02:37.410640 <6>[ 0.365800] CPU features: detected: 32-bit EL1 Support
5715 01:02:37.417640 <6>[ 0.371166] CPU features: detected: CRC32 instructions
5716 01:02:37.420606 <6>[ 0.376592] CPU: All CPU(s) started at EL2
5717 01:02:37.427400 <6>[ 0.380930] alternatives: applying system-wide alternatives
5718 01:02:37.430534 <6>[ 0.388913] devtmpfs: initialized
5719 01:02:37.445618 <6>[ 0.397853] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5720 01:02:37.455677 <6>[ 0.407801] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5721 01:02:37.458892 <6>[ 0.415532] pinctrl core: initialized pinctrl subsystem
5722 01:02:37.467325 <6>[ 0.422655] DMI not present or invalid.
5723 01:02:37.473945 <6>[ 0.427026] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5724 01:02:37.480310 <6>[ 0.433922] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5725 01:02:37.490054 <6>[ 0.441447] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5726 01:02:37.496945 <6>[ 0.449697] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5727 01:02:37.503675 <6>[ 0.457873] audit: initializing netlink subsys (disabled)
5728 01:02:37.510343 <5>[ 0.463577] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5729 01:02:37.517223 <6>[ 0.464563] thermal_sys: Registered thermal governor 'step_wise'
5730 01:02:37.523486 <6>[ 0.471543] thermal_sys: Registered thermal governor 'power_allocator'
5731 01:02:37.527016 <6>[ 0.477840] cpuidle: using governor menu
5732 01:02:37.533753 <6>[ 0.488802] NET: Registered PF_QIPCRTR protocol family
5733 01:02:37.540588 <6>[ 0.494284] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5734 01:02:37.546832 <6>[ 0.501379] ASID allocator initialised with 32768 entries
5735 01:02:37.553653 <6>[ 0.508155] Serial: AMBA PL011 UART driver
5736 01:02:37.563393 <4>[ 0.518573] Trying to register duplicate clock ID: 113
5737 01:02:37.623036 <6>[ 0.575237] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5738 01:02:37.637400 <6>[ 0.589595] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5739 01:02:37.640661 <6>[ 0.599344] KASLR enabled
5740 01:02:37.655129 <6>[ 0.607349] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5741 01:02:37.661946 <6>[ 0.614350] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5742 01:02:37.668541 <6>[ 0.620827] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5743 01:02:37.675188 <6>[ 0.627817] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5744 01:02:37.682041 <6>[ 0.634291] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5745 01:02:37.688798 <6>[ 0.641280] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5746 01:02:37.695464 <6>[ 0.647755] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5747 01:02:37.702093 <6>[ 0.654744] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5748 01:02:37.705473 <6>[ 0.662315] ACPI: Interpreter disabled.
5749 01:02:37.714582 <6>[ 0.670308] iommu: Default domain type: Translated
5750 01:02:37.721583 <6>[ 0.675414] iommu: DMA domain TLB invalidation policy: strict mode
5751 01:02:37.725018 <5>[ 0.682046] SCSI subsystem initialized
5752 01:02:37.731786 <6>[ 0.686459] usbcore: registered new interface driver usbfs
5753 01:02:37.738325 <6>[ 0.692187] usbcore: registered new interface driver hub
5754 01:02:37.741497 <6>[ 0.697728] usbcore: registered new device driver usb
5755 01:02:37.748587 <6>[ 0.704039] pps_core: LinuxPPS API ver. 1 registered
5756 01:02:37.758499 <6>[ 0.709225] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5757 01:02:37.761952 <6>[ 0.718548] PTP clock support registered
5758 01:02:37.765295 <6>[ 0.722800] EDAC MC: Ver: 3.0.0
5759 01:02:37.772859 <6>[ 0.728438] FPGA manager framework
5760 01:02:37.776117 <6>[ 0.732121] Advanced Linux Sound Architecture Driver Initialized.
5761 01:02:37.780117 <6>[ 0.738876] vgaarb: loaded
5762 01:02:37.786977 <6>[ 0.741995] clocksource: Switched to clocksource arch_sys_counter
5763 01:02:37.793596 <5>[ 0.748427] VFS: Disk quotas dquot_6.6.0
5764 01:02:37.800062 <6>[ 0.752602] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5765 01:02:37.803494 <6>[ 0.759777] pnp: PnP ACPI: disabled
5766 01:02:37.811076 <6>[ 0.766672] NET: Registered PF_INET protocol family
5767 01:02:37.817659 <6>[ 0.771899] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5768 01:02:37.829706 <6>[ 0.781808] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5769 01:02:37.836471 <6>[ 0.790562] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5770 01:02:37.846473 <6>[ 0.798512] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5771 01:02:37.853516 <6>[ 0.806744] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5772 01:02:37.859879 <6>[ 0.814837] TCP: Hash tables configured (established 32768 bind 32768)
5773 01:02:37.866588 <6>[ 0.821665] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5774 01:02:37.876836 <6>[ 0.828637] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5775 01:02:37.883216 <6>[ 0.836117] NET: Registered PF_UNIX/PF_LOCAL protocol family
5776 01:02:37.886647 <6>[ 0.842212] RPC: Registered named UNIX socket transport module.
5777 01:02:37.893134 <6>[ 0.848355] RPC: Registered udp transport module.
5778 01:02:37.896357 <6>[ 0.853280] RPC: Registered tcp transport module.
5779 01:02:37.903261 <6>[ 0.858203] RPC: Registered tcp NFSv4.1 backchannel transport module.
5780 01:02:37.909917 <6>[ 0.864855] PCI: CLS 0 bytes, default 64
5781 01:02:37.913201 <6>[ 0.869138] Unpacking initramfs...
5782 01:02:37.934268 <6>[ 0.886328] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5783 01:02:37.944350 <6>[ 0.895076] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5784 01:02:37.947722 <6>[ 0.903993] kvm [1]: IPA Size Limit: 40 bits
5785 01:02:37.955182 <6>[ 0.910346] kvm [1]: vgic-v2@c420000
5786 01:02:37.958087 <6>[ 0.914179] kvm [1]: GIC system register CPU interface enabled
5787 01:02:37.965156 <6>[ 0.920367] kvm [1]: vgic interrupt IRQ18
5788 01:02:37.968335 <6>[ 0.924755] kvm [1]: Hyp mode initialized successfully
5789 01:02:37.975548 <5>[ 0.931142] Initialise system trusted keyrings
5790 01:02:37.982018 <6>[ 0.936004] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5791 01:02:37.990953 <6>[ 0.946009] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5792 01:02:37.997180 <5>[ 0.952435] NFS: Registering the id_resolver key type
5793 01:02:38.001031 <5>[ 0.957743] Key type id_resolver registered
5794 01:02:38.007202 <5>[ 0.962158] Key type id_legacy registered
5795 01:02:38.014264 <6>[ 0.966469] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
5796 01:02:38.020304 <6>[ 0.973390] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
5797 01:02:38.027494 <6>[ 0.981136] 9p: Installing v9fs 9p2000 file system support
5798 01:02:38.054030 <5>[ 1.009544] Key type asymmetric registered
5799 01:02:38.057353 <5>[ 1.013889] Asymmetric key parser 'x509' registered
5800 01:02:38.067481 <6>[ 1.019048] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
5801 01:02:38.070656 <6>[ 1.026665] io scheduler mq-deadline registered
5802 01:02:38.074360 <6>[ 1.031422] io scheduler kyber registered
5803 01:02:38.096665 <6>[ 1.052220] EINJ: ACPI disabled.
5804 01:02:38.103252 <4>[ 1.055965] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
5805 01:02:38.141520 <6>[ 1.096739] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
5806 01:02:38.149938 <6>[ 1.105191] printk: console [ttyS0] disabled
5807 01:02:38.177616 <6>[ 1.129844] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
5808 01:02:38.184332 <6>[ 1.139330] printk: console [ttyS0] enabled
5809 01:02:38.187597 <6>[ 1.139330] printk: console [ttyS0] enabled
5810 01:02:38.194693 <6>[ 1.148247] printk: bootconsole [mtk8250] disabled
5811 01:02:38.197597 <6>[ 1.148247] printk: bootconsole [mtk8250] disabled
5812 01:02:38.208007 <3>[ 1.158785] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
5813 01:02:38.214045 <3>[ 1.167170] mt6577-uart 11003000.serial: Error applying setting, reverse things back
5814 01:02:38.243558 <6>[ 1.195586] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
5815 01:02:38.250055 <6>[ 1.205238] serial serial0: tty port ttyS1 registered
5816 01:02:38.256891 <6>[ 1.211810] SuperH (H)SCI(F) driver initialized
5817 01:02:38.259825 <6>[ 1.217301] msm_serial: driver initialized
5818 01:02:38.275423 <6>[ 1.227648] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
5819 01:02:38.285161 <6>[ 1.236242] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
5820 01:02:38.292077 <6>[ 1.244816] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
5821 01:02:38.301873 <6>[ 1.253386] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
5822 01:02:38.308359 <6>[ 1.262043] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
5823 01:02:38.318580 <6>[ 1.270711] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
5824 01:02:38.328462 <6>[ 1.279451] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
5825 01:02:38.335225 <6>[ 1.288188] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
5826 01:02:38.345119 <6>[ 1.296754] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
5827 01:02:38.355115 <6>[ 1.305547] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
5828 01:02:38.362682 <4>[ 1.317937] cacheinfo: Unable to detect cache hierarchy for CPU 0
5829 01:02:38.372231 <6>[ 1.327312] loop: module loaded
5830 01:02:38.383500 <6>[ 1.339233] vsim1: Bringing 1800000uV into 2700000-2700000uV
5831 01:02:38.401471 <6>[ 1.357173] megasas: 07.719.03.00-rc1
5832 01:02:38.410696 <6>[ 1.365903] spi-nor spi1.0: w25q64dw (8192 Kbytes)
5833 01:02:38.417980 <6>[ 1.373370] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
5834 01:02:38.434866 <6>[ 1.390091] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
5835 01:02:38.491095 <6>[ 1.440217] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b8
5836 01:02:39.230654 <6>[ 2.186192] Freeing initrd memory: 40256K
5837 01:02:39.245597 <4>[ 2.198083] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
5838 01:02:39.252700 <4>[ 2.207310] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1
5839 01:02:39.259131 <4>[ 2.214008] Hardware name: Google juniper sku16 board (DT)
5840 01:02:39.262449 <4>[ 2.219747] Call trace:
5841 01:02:39.265898 <4>[ 2.222447] dump_backtrace.part.0+0xe0/0xf0
5842 01:02:39.269193 <4>[ 2.226985] show_stack+0x18/0x30
5843 01:02:39.272627 <4>[ 2.230557] dump_stack_lvl+0x68/0x84
5844 01:02:39.275901 <4>[ 2.234478] dump_stack+0x18/0x34
5845 01:02:39.282692 <4>[ 2.238047] sysfs_warn_dup+0x64/0x80
5846 01:02:39.285994 <4>[ 2.241969] sysfs_do_create_link_sd+0xf0/0x100
5847 01:02:39.289609 <4>[ 2.246756] sysfs_create_link+0x20/0x40
5848 01:02:39.293104 <4>[ 2.250936] bus_add_device+0x68/0x10c
5849 01:02:39.299853 <4>[ 2.254942] device_add+0x340/0x7ac
5850 01:02:39.302935 <4>[ 2.258685] of_device_add+0x44/0x60
5851 01:02:39.306347 <4>[ 2.262519] of_platform_device_create_pdata+0x90/0x120
5852 01:02:39.313064 <4>[ 2.268000] of_platform_bus_create+0x170/0x370
5853 01:02:39.316141 <4>[ 2.272787] of_platform_populate+0x50/0xfc
5854 01:02:39.322846 <4>[ 2.277226] parse_mtd_partitions+0x1dc/0x510
5855 01:02:39.326290 <4>[ 2.281840] mtd_device_parse_register+0xf8/0x2e0
5856 01:02:39.329646 <4>[ 2.286798] spi_nor_probe+0x21c/0x2f0
5857 01:02:39.333425 <4>[ 2.290804] spi_mem_probe+0x6c/0xb0
5858 01:02:39.336281 <4>[ 2.294636] spi_probe+0x84/0xe4
5859 01:02:39.343265 <4>[ 2.298118] really_probe+0xbc/0x2e0
5860 01:02:39.346259 <4>[ 2.301948] __driver_probe_device+0x78/0x11c
5861 01:02:39.349938 <4>[ 2.306560] driver_probe_device+0xd8/0x160
5862 01:02:39.356241 <4>[ 2.310998] __device_attach_driver+0xb8/0x134
5863 01:02:39.359844 <4>[ 2.315697] bus_for_each_drv+0x78/0xd0
5864 01:02:39.362943 <4>[ 2.319787] __device_attach+0xa8/0x1c0
5865 01:02:39.366562 <4>[ 2.323877] device_initial_probe+0x14/0x20
5866 01:02:39.373248 <4>[ 2.328315] bus_probe_device+0x9c/0xa4
5867 01:02:39.376520 <4>[ 2.332405] device_add+0x3ac/0x7ac
5868 01:02:39.379643 <4>[ 2.336147] __spi_add_device+0x78/0x120
5869 01:02:39.383214 <4>[ 2.340326] spi_add_device+0x40/0x7c
5870 01:02:39.389956 <4>[ 2.344243] spi_register_controller+0x610/0xad0
5871 01:02:39.393136 <4>[ 2.349116] devm_spi_register_controller+0x4c/0xa4
5872 01:02:39.396693 <4>[ 2.354249] mtk_spi_probe+0x3f8/0x650
5873 01:02:39.403479 <4>[ 2.358253] platform_probe+0x68/0xe0
5874 01:02:39.406575 <4>[ 2.362171] really_probe+0xbc/0x2e0
5875 01:02:39.409857 <4>[ 2.366001] __driver_probe_device+0x78/0x11c
5876 01:02:39.412931 <4>[ 2.370612] driver_probe_device+0xd8/0x160
5877 01:02:39.419598 <4>[ 2.375050] __driver_attach+0x94/0x19c
5878 01:02:39.423220 <4>[ 2.379140] bus_for_each_dev+0x70/0xd0
5879 01:02:39.426242 <4>[ 2.383230] driver_attach+0x24/0x30
5880 01:02:39.429967 <4>[ 2.387060] bus_add_driver+0x154/0x20c
5881 01:02:39.436517 <4>[ 2.391150] driver_register+0x78/0x130
5882 01:02:39.439859 <4>[ 2.395241] __platform_driver_register+0x28/0x34
5883 01:02:39.443047 <4>[ 2.400201] mtk_spi_driver_init+0x1c/0x28
5884 01:02:39.449776 <4>[ 2.404555] do_one_initcall+0x50/0x1d0
5885 01:02:39.453215 <4>[ 2.408644] kernel_init_freeable+0x21c/0x288
5886 01:02:39.456527 <4>[ 2.413258] kernel_init+0x24/0x12c
5887 01:02:39.459505 <4>[ 2.417003] ret_from_fork+0x10/0x20
5888 01:02:39.470352 <6>[ 2.425914] tun: Universal TUN/TAP device driver, 1.6
5889 01:02:39.473546 <6>[ 2.432215] thunder_xcv, ver 1.0
5890 01:02:39.480133 <6>[ 2.435735] thunder_bgx, ver 1.0
5891 01:02:39.480624 <6>[ 2.439241] nicpf, ver 1.0
5892 01:02:39.491491 <6>[ 2.443618] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
5893 01:02:39.494819 <6>[ 2.451107] hns3: Copyright (c) 2017 Huawei Corporation.
5894 01:02:39.501653 <6>[ 2.456706] hclge is initializing
5895 01:02:39.504960 <6>[ 2.460290] e1000: Intel(R) PRO/1000 Network Driver
5896 01:02:39.511562 <6>[ 2.465425] e1000: Copyright (c) 1999-2006 Intel Corporation.
5897 01:02:39.515145 <6>[ 2.471447] e1000e: Intel(R) PRO/1000 Network Driver
5898 01:02:39.521650 <6>[ 2.476668] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
5899 01:02:39.528109 <6>[ 2.482861] igb: Intel(R) Gigabit Ethernet Network Driver
5900 01:02:39.534699 <6>[ 2.488516] igb: Copyright (c) 2007-2014 Intel Corporation.
5901 01:02:39.541606 <6>[ 2.494358] igbvf: Intel(R) Gigabit Virtual Function Network Driver
5902 01:02:39.548160 <6>[ 2.500881] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
5903 01:02:39.551442 <6>[ 2.507434] sky2: driver version 1.30
5904 01:02:39.558319 <6>[ 2.512687] usbcore: registered new device driver r8152-cfgselector
5905 01:02:39.565053 <6>[ 2.519229] usbcore: registered new interface driver r8152
5906 01:02:39.571177 <6>[ 2.525054] VFIO - User Level meta-driver version: 0.3
5907 01:02:39.578120 <6>[ 2.532852] mtu3 11201000.usb: uwk - reg:0x420, version:101
5908 01:02:39.584505 <4>[ 2.538726] mtu3 11201000.usb: supply vbus not found, using dummy regulator
5909 01:02:39.591639 <6>[ 2.546008] mtu3 11201000.usb: dr_mode: 1, drd: auto
5910 01:02:39.597937 <6>[ 2.551235] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
5911 01:02:39.601472 <6>[ 2.557429] mtu3 11201000.usb: usb3-drd: 0
5912 01:02:39.608022 <6>[ 2.562993] mtu3 11201000.usb: xHCI platform device register success...
5913 01:02:39.619365 <4>[ 2.571670] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
5914 01:02:39.625925 <6>[ 2.579610] xhci-mtk 11200000.usb: xHCI Host Controller
5915 01:02:39.632940 <6>[ 2.585114] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
5916 01:02:39.639210 <6>[ 2.592833] xhci-mtk 11200000.usb: USB3 root hub has no ports
5917 01:02:39.649371 <6>[ 2.598840] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
5918 01:02:39.652719 <6>[ 2.608264] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
5919 01:02:39.659247 <6>[ 2.614340] xhci-mtk 11200000.usb: xHCI Host Controller
5920 01:02:39.666143 <6>[ 2.619829] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
5921 01:02:39.672576 <6>[ 2.627486] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
5922 01:02:39.679044 <6>[ 2.634302] hub 1-0:1.0: USB hub found
5923 01:02:39.682350 <6>[ 2.638331] hub 1-0:1.0: 1 port detected
5924 01:02:39.692662 <6>[ 2.643657] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
5925 01:02:39.695693 <6>[ 2.652285] hub 2-0:1.0: USB hub found
5926 01:02:39.702404 <3>[ 2.656340] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
5927 01:02:39.709209 <6>[ 2.664237] usbcore: registered new interface driver usb-storage
5928 01:02:39.715602 <6>[ 2.670848] usbcore: registered new device driver onboard-usb-hub
5929 01:02:39.729995 <4>[ 2.682093] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
5930 01:02:39.739009 <6>[ 2.694349] mt6397-rtc mt6358-rtc: registered as rtc0
5931 01:02:39.748922 <6>[ 2.699827] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-16T01:02:39 UTC (1718499759)
5932 01:02:39.752301 <6>[ 2.709712] i2c_dev: i2c /dev entries driver
5933 01:02:39.764012 <6>[ 2.716127] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5934 01:02:39.773834 <6>[ 2.724446] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5935 01:02:39.777446 <6>[ 2.733350] i2c 4-0058: Fixed dependency cycle(s) with /panel
5936 01:02:39.787316 <6>[ 2.739380] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
5937 01:02:39.794362 <3>[ 2.746849] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
5938 01:02:39.811029 <6>[ 2.766746] cpu cpu0: EM: created perf domain
5939 01:02:39.821521 <6>[ 2.772228] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
5940 01:02:39.828362 <6>[ 2.783512] cpu cpu4: EM: created perf domain
5941 01:02:39.835058 <6>[ 2.790655] sdhci: Secure Digital Host Controller Interface driver
5942 01:02:39.842175 <6>[ 2.797110] sdhci: Copyright(c) Pierre Ossman
5943 01:02:39.848455 <6>[ 2.802511] Synopsys Designware Multimedia Card Interface Driver
5944 01:02:39.854967 <6>[ 2.802990] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
5945 01:02:39.858574 <6>[ 2.809584] sdhci-pltfm: SDHCI platform and OF driver helper
5946 01:02:39.866816 <6>[ 2.822340] ledtrig-cpu: registered to indicate activity on CPUs
5947 01:02:39.874630 <6>[ 2.830086] usbcore: registered new interface driver usbhid
5948 01:02:39.878189 <6>[ 2.835924] usbhid: USB HID core driver
5949 01:02:39.888973 <6>[ 2.840240] spi_master spi2: will run message pump with realtime priority
5950 01:02:39.892487 <4>[ 2.840485] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
5951 01:02:39.903080 <4>[ 2.854602] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
5952 01:02:39.913314 <6>[ 2.859734] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
5953 01:02:39.932202 <6>[ 2.877714] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
5954 01:02:39.938709 <4>[ 2.888227] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
5955 01:02:39.945677 <6>[ 2.898839] cros-ec-spi spi2.0: Chrome EC device registered
5956 01:02:39.952281 <4>[ 2.905641] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
5957 01:02:39.965604 <4>[ 2.917291] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
5958 01:02:39.971653 <4>[ 2.926111] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
5959 01:02:39.983548 <6>[ 2.935935] mmc1: new ultra high speed SDR104 SDIO card at address 0001
5960 01:02:39.990688 <6>[ 2.945876] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14
5961 01:02:39.997267 <6>[ 2.952282] mmc0: new HS400 MMC card at address 0001
5962 01:02:40.003764 <6>[ 2.958491] mmcblk0: mmc0:0001 TB2932 29.2 GiB
5963 01:02:40.012063 <6>[ 2.967463] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
5964 01:02:40.021490 <6>[ 2.976995] mmcblk0boot0: mmc0:0001 TB2932 4.00 MiB
5965 01:02:40.031559 <6>[ 2.981971] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
5966 01:02:40.034714 <6>[ 2.983483] mmcblk0boot1: mmc0:0001 TB2932 4.00 MiB
5967 01:02:40.047942 <6>[ 2.994798] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
5968 01:02:40.051724 <6>[ 2.997189] mmcblk0rpmb: mmc0:0001 TB2932 4.00 MiB, chardev (507:0)
5969 01:02:40.064995 <6>[ 3.006376] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
5970 01:02:40.074675 <6>[ 3.006718] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
5971 01:02:40.081535 <6>[ 3.008826] NET: Registered PF_PACKET protocol family
5972 01:02:40.084809 <6>[ 3.041070] 9pnet: Installing 9P2000 support
5973 01:02:40.088164 <5>[ 3.045658] Key type dns_resolver registered
5974 01:02:40.095317 <6>[ 3.050750] registered taskstats version 1
5975 01:02:40.098755 <5>[ 3.055123] Loading compiled-in X.509 certificates
5976 01:02:40.105140 <6>[ 3.058016] usb 1-1: new high-speed USB device number 2 using xhci-mtk
5977 01:02:40.139692 <3>[ 3.091817] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
5978 01:02:40.166309 <6>[ 3.114926] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
5979 01:02:40.176649 <6>[ 3.128634] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
5980 01:02:40.186524 <6>[ 3.137359] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
5981 01:02:40.193196 <6>[ 3.145916] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
5982 01:02:40.203244 <6>[ 3.154521] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
5983 01:02:40.210073 <6>[ 3.163069] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
5984 01:02:40.219783 <6>[ 3.171664] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
5985 01:02:40.229537 <6>[ 3.180202] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
5986 01:02:40.236940 <6>[ 3.189717] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
5987 01:02:40.243201 <6>[ 3.197235] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
5988 01:02:40.249737 <6>[ 3.204538] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
5989 01:02:40.259561 <6>[ 3.211769] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
5990 01:02:40.262646 <6>[ 3.217701] hub 1-1:1.0: USB hub found
5991 01:02:40.269522 <6>[ 3.219216] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
5992 01:02:40.273073 <6>[ 3.223036] hub 1-1:1.0: 3 ports detected
5993 01:02:40.279405 <6>[ 3.230795] panfrost 13040000.gpu: clock rate = 511999970
5994 01:02:40.289541 <6>[ 3.239117] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
5995 01:02:40.296159 <6>[ 3.249488] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
5996 01:02:40.306071 <6>[ 3.257518] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
5997 01:02:40.319139 <6>[ 3.265951] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
5998 01:02:40.325756 <6>[ 3.278035] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
5999 01:02:40.337314 <6>[ 3.289547] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6000 01:02:40.347307 <6>[ 3.298882] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6001 01:02:40.357491 <6>[ 3.308040] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6002 01:02:40.367070 <6>[ 3.317173] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6003 01:02:40.374089 <6>[ 3.326300] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6004 01:02:40.384002 <6>[ 3.335601] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6005 01:02:40.394115 <6>[ 3.344902] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6006 01:02:40.403978 <6>[ 3.354375] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6007 01:02:40.413698 <6>[ 3.363848] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6008 01:02:40.420393 <6>[ 3.372977] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6009 01:02:40.493743 <6>[ 3.445551] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6010 01:02:40.503834 <6>[ 3.454428] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6011 01:02:40.513940 <6>[ 3.466208] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6012 01:02:40.570149 <6>[ 3.522134] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
6013 01:02:40.671738 <6>[ 3.627064] hub 1-1.1:1.0: USB hub found
6014 01:02:40.674751 <6>[ 3.631337] hub 1-1.1:1.0: 4 ports detected
6015 01:02:41.196740 <6>[ 4.136374] Console: switching to colour frame buffer device 170x48
6016 01:02:41.206794 <6>[ 4.158816] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6017 01:02:41.226575 <6>[ 4.175243] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6018 01:02:41.244459 <6>[ 4.193249] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6019 01:02:41.251006 <6>[ 4.205434] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6020 01:02:41.261797 <6>[ 4.213578] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6021 01:02:41.271643 <6>[ 4.219742] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6022 01:02:41.290001 <6>[ 4.238991] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6023 01:02:41.296737 <6>[ 4.246140] usb 1-1.2: new high-speed USB device number 4 using xhci-mtk
6024 01:02:41.482098 <6>[ 4.434210] r8152-cfgselector 1-1.2: reset high-speed USB device number 4 using xhci-mtk
6025 01:02:41.593776 <4>[ 4.545754] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6026 01:02:41.603627 <4>[ 4.555012] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6027 01:02:41.643208 <6>[ 4.598753] r8152 1-1.2:1.0 eth0: v1.12.13
6028 01:02:41.664591 <6>[ 4.613243] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6029 01:02:41.670923 <6>[ 4.624370] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
6030 01:02:41.858075 <6>[ 4.810031] usb 1-1.3: new high-speed USB device number 6 using xhci-mtk
6031 01:02:41.994297 <6>[ 4.942882] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6032 01:02:42.046386 <6>[ 4.998554] r8152-cfgselector 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
6033 01:02:42.171055 <4>[ 5.123316] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6034 01:02:42.183828 <4>[ 5.135984] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6035 01:02:42.244519 <6>[ 5.200216] r8152 1-1.1.1:1.0 eth1: v1.12.13
6036 01:02:42.271592 <6>[ 5.220641] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6037 01:02:43.267556 <6>[ 6.223013] r8152 1-1.2:1.0 eth0: carrier on
6038 01:02:45.322463 <5>[ 6.246072] Sending DHCP requests .., OK
6039 01:02:45.334867 <6>[ 8.287151] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.17
6040 01:02:45.345063 <6>[ 8.300430] IP-Config: Complete:
6041 01:02:45.360044 <6>[ 8.308789] device=eth0, hwaddr=00:e0:4c:68:03:2b, ipaddr=192.168.201.17, mask=255.255.255.0, gw=192.168.201.1
6042 01:02:45.372851 <6>[ 8.324535] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-5, domain=lava-rack, nis-domain=(none)
6043 01:02:45.385652 <6>[ 8.337801] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6044 01:02:45.393247 <6>[ 8.337809] nameserver0=192.168.201.1
6045 01:02:45.425750 <6>[ 8.381219] clk: Disabling unused clocks
6046 01:02:45.432365 <6>[ 8.391235] ALSA device list:
6047 01:02:45.441113 <6>[ 8.396369] No soundcards found.
6048 01:02:45.449085 <6>[ 8.404252] Freeing unused kernel memory: 8512K
6049 01:02:45.455635 <6>[ 8.411104] Run /init as init process
6050 01:02:45.490065 <6>[ 8.445362] NET: Registered PF_INET6 protocol family
6051 01:02:45.499841 <6>[ 8.455336] Segment Routing with IPv6
6052 01:02:45.503155 <6>[ 8.460409] In-situ OAM (IOAM) with IPv6
6053 01:02:45.550298 <30>[ 8.479006] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6054 01:02:45.559292 <30>[ 8.514462] systemd[1]: Detected architecture arm64.
6055 01:02:45.563719
6056 01:02:45.567199 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6057 01:02:45.567630
6058 01:02:45.586948 <30>[ 8.542411] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6059 01:02:45.733531 <30>[ 8.685885] systemd[1]: Queued start job for default target graphical.target.
6060 01:02:45.760488 <30>[ 8.712235] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6061 01:02:45.766897 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6062 01:02:45.786636 <30>[ 8.739027] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6063 01:02:45.796836 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6064 01:02:45.815157 <30>[ 8.767435] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6065 01:02:45.827235 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6066 01:02:45.846856 <30>[ 8.799010] systemd[1]: Created slice user.slice - User and Session Slice.
6067 01:02:45.857255 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6068 01:02:45.877482 <30>[ 8.826540] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6069 01:02:45.890481 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6070 01:02:45.909689 <30>[ 8.858421] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6071 01:02:45.922257 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6072 01:02:45.948243 <30>[ 8.890284] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6073 01:02:45.966907 <30>[ 8.918925] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6074 01:02:45.974180 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6075 01:02:45.993995 <30>[ 8.946203] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6076 01:02:46.007513 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6077 01:02:46.026152 <30>[ 8.978257] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6078 01:02:46.041017 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6079 01:02:46.054923 <30>[ 9.010295] systemd[1]: Reached target paths.target - Path Units.
6080 01:02:46.069560 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6081 01:02:46.086376 <30>[ 9.038215] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6082 01:02:46.098765 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6083 01:02:46.114907 <30>[ 9.070168] systemd[1]: Reached target slices.target - Slice Units.
6084 01:02:46.129987 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6085 01:02:46.143086 <30>[ 9.098211] systemd[1]: Reached target swap.target - Swaps.
6086 01:02:46.154130 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6087 01:02:46.174528 <30>[ 9.126255] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6088 01:02:46.187787 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6089 01:02:46.206605 <30>[ 9.158591] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6090 01:02:46.220524 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6091 01:02:46.239892 <30>[ 9.191967] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6092 01:02:46.253420 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6093 01:02:46.270731 <30>[ 9.222938] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6094 01:02:46.285224 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6095 01:02:46.302808 <30>[ 9.254849] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6096 01:02:46.315398 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6097 01:02:46.335068 <30>[ 9.287002] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6098 01:02:46.348931 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6099 01:02:46.366755 <30>[ 9.318930] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6100 01:02:46.380086 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6101 01:02:46.398600 <30>[ 9.350652] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6102 01:02:46.411534 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6103 01:02:46.458362 <30>[ 9.410420] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6104 01:02:46.470026 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6105 01:02:46.491767 <30>[ 9.444042] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6106 01:02:46.502748 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6107 01:02:46.522689 <30>[ 9.474924] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6108 01:02:46.534781 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6109 01:02:46.561389 <30>[ 9.506714] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6110 01:02:46.603036 <30>[ 9.554680] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6111 01:02:46.615675 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6112 01:02:46.640143 <30>[ 9.592189] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6113 01:02:46.654065 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6114 01:02:46.675558 <30>[ 9.627926] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6115 01:02:46.690901 Starting [0;1;39mmodprobe@dm_mod.s…[<6>[ 9.643470] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6116 01:02:46.694109 0m - Load Kernel Module dm_mod...
6117 01:02:46.739042 <30>[ 9.691010] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6118 01:02:46.752508 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6119 01:02:46.779669 <30>[ 9.731920] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6120 01:02:46.794001 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6121 01:02:46.839474 <30>[ 9.791378] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6122 01:02:46.850869 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6123 01:02:46.884860 <30>[ 9.836889] systemd[1]: Starting systemd-journald.service - Journal Service...
6124 01:02:46.895535 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6125 01:02:46.913933 <30>[ 9.865767] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6126 01:02:46.923654 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6127 01:02:46.949983 <30>[ 9.898615] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6128 01:02:46.961342 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6129 01:02:46.982552 <30>[ 9.934768] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6130 01:02:46.995407 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6131 01:02:47.021115 <30>[ 9.973182] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6132 01:02:47.032184 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6133 01:02:47.053539 <30>[ 10.005800] systemd[1]: Started systemd-journald.service - Journal Service.
6134 01:02:47.063373 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6135 01:02:47.084278 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6136 01:02:47.103078 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6137 01:02:47.118801 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6138 01:02:47.139461 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6139 01:02:47.159258 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6140 01:02:47.183001 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6141 01:02:47.207091 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6142 01:02:47.227334 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6143 01:02:47.251245 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6144 01:02:47.274813 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6145 01:02:47.295143 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6146 01:02:47.315632 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
6147 01:02:47.322321 See 'systemctl status systemd-remount-fs.service' for details.
6148 01:02:47.347866 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6149 01:02:47.406970 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6150 01:02:47.437385 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6151 01:02:47.449913 <46>[ 10.401923] systemd-journald[202]: Received client request to flush runtime journal.
6152 01:02:47.467937 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6153 01:02:47.493751 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6154 01:02:47.551183 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6155 01:02:47.576685 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6156 01:02:47.596009 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6157 01:02:47.616485 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6158 01:02:47.636071 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6159 01:02:47.656124 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6160 01:02:47.675744 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6161 01:02:47.723611 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6162 01:02:47.749436 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6163 01:02:47.771158 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6164 01:02:47.791339 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6165 01:02:47.835272 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6166 01:02:47.859794 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6167 01:02:47.896936 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6168 01:02:47.936713 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6169 01:02:47.957095 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6170 01:02:47.978258 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager <6>[ 10.931327] r8152 1-1.1.1:1.0 enx88541f0f7aca: renamed from eth1
6171 01:02:47.981730 for Device Events and Files.
6172 01:02:48.016138 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6173 01:02:48.034900 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6174 01:02:48.065499 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6175 01:02:48.144668 <3>[ 11.100030] thermal_sys: Failed to find 'trips' node
6176 01:02:48.154772 <3>[ 11.106029] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6177 01:02:48.165028 <3>[ 11.106457] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6178 01:02:48.168114 <3>[ 11.107769] mtk-scp 10500000.scp: invalid resource
6179 01:02:48.174858 <6>[ 11.107819] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6180 01:02:48.181380 <6>[ 11.108827] remoteproc remoteproc0: scp is available
6181 01:02:48.187843 <4>[ 11.108957] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6182 01:02:48.194282 <6>[ 11.108965] remoteproc remoteproc0: powering up scp
6183 01:02:48.205178 <4>[ 11.108991] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6184 01:02:48.211921 <3>[ 11.108995] remoteproc remoteproc0: request_firmware failed: -2
6185 01:02:48.223244 <6>[ 11.114303] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6186 01:02:48.233177 <3>[ 11.116115] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6187 01:02:48.243800 <4>[ 11.116124] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6188 01:02:48.246877 <3>[ 11.117463] thermal_sys: Failed to find 'trips' node
6189 01:02:48.256892 <3>[ 11.117466] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6190 01:02:48.266975 <3>[ 11.117472] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6191 01:02:48.273536 <4>[ 11.117475] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6192 01:02:48.288606 <6>[ 11.120212] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6193 01:02:48.295039 <3>[ 11.123879] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6194 01:02:48.305042 <3>[ 11.131365] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6195 01:02:48.315269 <6>[ 11.132248] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6196 01:02:48.324908 <4>[ 11.134430] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6197 01:02:48.338353 <3>[ 11.136630] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6198 01:02:48.348559 <6>[ 11.138333] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6199 01:02:48.360017 <3>[ 11.141392] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6200 01:02:48.373136 <6>[ 11.142356] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6201 01:02:48.379710 <3>[ 11.149816] elan_i2c 2-0015: Error applying setting, reverse things back
6202 01:02:48.386433 <4>[ 11.199674] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6203 01:02:48.396732 <3>[ 11.203379] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6204 01:02:48.406600 <4>[ 11.244682] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6205 01:02:48.410048 <6>[ 11.265418] mc: Linux media interface: v0.10
6206 01:02:48.419781 <3>[ 11.311379] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6207 01:02:48.438245 <3>[ 11.389970] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6208 01:02:48.447800 <3>[ 11.399453] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6209 01:02:48.457958 <3>[ 11.408835] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6210 01:02:48.467754 <3>[ 11.414377] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6211 01:02:48.477896 <3>[ 11.417441] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6212 01:02:48.488022 <6>[ 11.431432] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input6
6213 01:02:48.494408 <6>[ 11.443484] videodev: Linux video capture interface: v2.00
6214 01:02:48.506509 <3>[ 11.458665] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6215 01:02:48.513456 <6>[ 11.462925] cs_system_cfg: CoreSight Configuration manager initialised
6216 01:02:48.537642 <3>[ 11.486277] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6217 01:02:48.552714 <6>[ 11.504502] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6218 01:02:48.559194 <3>[ 11.506401] debugfs: File 'Playback' in directory 'dapm' already present!
6219 01:02:48.574169 <3>[ 11.526318] debugfs: File 'Capture' in directory 'dapm' already present!
6220 01:02:48.590940 <6>[ 11.539686] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input7
6221 01:02:48.597734 <6>[ 11.544517] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6222 01:02:48.618470 <6>[ 11.570262] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6223 01:02:48.629662 <6>[ 11.581548] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6224 01:02:48.640316 <6>[ 11.589330] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6225 01:02:48.651067 <6>[ 11.589471] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6226 01:02:48.663518 <6>[ 11.615324] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6227 01:02:48.670807 <6>[ 11.626130] Bluetooth: Core ver 2.22
6228 01:02:48.677749 <6>[ 11.633010] NET: Registered PF_BLUETOOTH protocol family
6229 01:02:48.687541 <6>[ 11.633291] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6230 01:02:48.693983 <6>[ 11.638609] Bluetooth: HCI device and connection manager initialized
6231 01:02:48.708006 <6>[ 11.663567] Bluetooth: HCI socket layer initialized
6232 01:02:48.715635 <6>[ 11.670757] Bluetooth: L2CAP socket layer initialized
6233 01:02:48.722253 <6>[ 11.670916] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6234 01:02:48.728429 <6>[ 11.676445] Bluetooth: SCO socket layer initialized
6235 01:02:48.773395 <5>[ 11.725392] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6236 01:02:48.798683 <5>[ 11.750534] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6237 01:02:48.810886 <5>[ 11.762847] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6238 01:02:48.824030 <4>[ 11.775536] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6239 01:02:48.832146 <6>[ 11.787531] cfg80211: failed to load regulatory.db
6240 01:02:48.997310 <4>[ 11.949245] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6241 01:02:49.003701 <4>[ 11.949245] Fallback method does not support PEC.
6242 01:02:49.019792 <6>[ 11.974022] Bluetooth: HCI UART driver ver 2.3
6243 01:02:49.026410 <3>[ 11.975418] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6244 01:02:49.033005 <6>[ 11.979836] Bluetooth: HCI UART protocol H4 registered
6245 01:02:49.044649 <3>[ 11.993987] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6246 01:02:49.058542 <6>[ 12.011050] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6247 01:02:49.082887 <6>[ 12.038162] Bluetooth: HCI UART protocol LL registered
6248 01:02:49.092926 <6>[ 12.048386] Bluetooth: HCI UART protocol Three-wire (H5) registered
6249 01:02:49.183041 <6>[ 12.134556] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6250 01:02:49.189622 <6>[ 12.134749] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6251 01:02:49.241042 <6>[ 12.196581] Bluetooth: HCI UART protocol Broadcom registered
6252 01:02:49.265606 <6>[ 12.217435] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6253 01:02:49.277383 <6>[ 12.232545] Bluetooth: HCI UART protocol QCA registered
6254 01:02:49.290883 <6>[ 12.242931] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6255 01:02:49.306689 <6>[ 12.255557] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6256 01:02:49.326817 <6>[ 12.271738] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6257 01:02:49.333777 <6>[ 12.278900] Bluetooth: hci0: setting up ROME/QCA6390
6258 01:02:49.340643 <6>[ 12.295968] Bluetooth: HCI UART protocol Marvell registered
6259 01:02:49.395013 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6260 01:02:49.401762 <3>[ 12.353589] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6261 01:02:49.417341 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m <3>[ 12.369620] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6262 01:02:49.420547 - System Time Set.
6263 01:02:49.427496 <3>[ 12.380054] power_supply sbs-12-000b: driver failed to report `capacity_level' property: -6
6264 01:02:49.445103 <3>[ 12.396525] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6265 01:02:49.461092 Startin<6>[ 12.413084] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6266 01:02:49.471363 g [0;1;39msystemd-backlight…e<6>[ 12.422315] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6267 01:02:49.481390 ss of backlight:<3>[ 12.428307] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6268 01:02:49.481824 backlight_lcd0...
6269 01:02:49.500433 <3>[ 12.452028] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6270 01:02:49.511344 <6>[ 12.459366] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6271 01:02:49.521325 <3>[ 12.466403] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6272 01:02:49.525203 <6>[ 12.472404] usbcore: registered new interface driver uvcvideo
6273 01:02:49.536565 <3>[ 12.486440] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6274 01:02:49.548007 <3>[ 12.501815] Bluetooth: hci0: Frame reassembly failed (-84)
6275 01:02:49.557064 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6276 01:02:49.579344 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6277 01:02:49.627857 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6278 01:02:49.671091 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6279 01:02:49.687173 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6280 01:02:49.705531 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6281 01:02:49.721290 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6282 01:02:49.737832 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6283 01:02:49.756656 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6284 01:02:49.771893 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6285 01:02:49.788130 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6286 01:02:49.810587 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m -<6>[ 12.764269] Bluetooth: hci0: QCA Product ID :0x00000008
6287 01:02:49.811102 Socket Units.
6288 01:02:49.817944 <6>[ 12.773095] Bluetooth: hci0: QCA SOC Version :0x00000044
6289 01:02:49.826297 <6>[ 12.781421] Bluetooth: hci0: QCA ROM Version :0x00000302
6290 01:02:49.834922 <6>[ 12.789890] Bluetooth: hci0: QCA Patch Version:0x00000111
6291 01:02:49.842786 <6>[ 12.798325] Bluetooth: hci0: QCA controller version 0x00440302
6292 01:02:49.855220 <6>[ 12.807156] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6293 01:02:49.861820 <6>[ 12.807513] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6294 01:02:49.871828 <4>[ 12.814042] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6295 01:02:49.886958 <3>[ 12.838974] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6296 01:02:49.893708 <3>[ 12.849022] Bluetooth: hci0: QCA Failed to download patch (-2)
6297 01:02:49.904993 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6298 01:02:49.924696 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6299 01:02:49.940076 <4>[ 12.895299] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6300 01:02:49.963078 <4>[ 12.914949] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6301 01:02:49.979116 Starting [0;1;39mdbus.<4>[ 12.929800] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6302 01:02:49.982268 service[0m - D-Bus System Message Bus...
6303 01:02:49.988561 <4>[ 12.942718] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6304 01:02:50.027810 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6305 01:02:50.054821 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6306 01:02:50.073699 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6307 01:02:50.102244 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6308 01:02:50.147159 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6309 01:02:50.186082 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6310 01:02:50.205668 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6311 01:02:50.248754 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6312 01:02:50.268857 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6313 01:02:50.287883 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6314 01:02:50.309563 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6315 01:02:50.327083 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6316 01:02:50.362420 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6317 01:02:50.392996 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6318 01:02:50.463533
6319 01:02:50.466859 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6320 01:02:50.467289
6321 01:02:50.470114 debian-bookworm-arm64 login: root (automatic login)
6322 01:02:50.470649
6323 01:02:50.494969 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
6324 01:02:50.495487
6325 01:02:50.501375 The programs included with the Debian GNU/Linux system are free software;
6326 01:02:50.507657 the exact distribution terms for each program are described in the
6327 01:02:50.511059 individual files in /usr/share/doc/*/copyright.
6328 01:02:50.511572
6329 01:02:50.517956 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6330 01:02:50.521404 permitted by applicable law.
6331 01:02:50.522915 Matched prompt #10: / #
6333 01:02:50.523911 Setting prompt string to ['/ #']
6334 01:02:50.524360 end: 2.2.5.1 login-action (duration 00:00:14) [common]
6336 01:02:50.525358 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
6337 01:02:50.525791 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
6338 01:02:50.526159 Setting prompt string to ['/ #']
6339 01:02:50.526496 Forcing a shell prompt, looking for ['/ #']
6341 01:02:50.577271 / #
6342 01:02:50.577940 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6343 01:02:50.578344 Waiting using forced prompt support (timeout 00:02:30)
6344 01:02:50.584241
6345 01:02:50.585162 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6346 01:02:50.585667 start: 2.2.7 export-device-env (timeout 00:03:39) [common]
6347 01:02:50.586130 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6348 01:02:50.586652 end: 2.2 depthcharge-retry (duration 00:01:21) [common]
6349 01:02:50.587093 end: 2 depthcharge-action (duration 00:01:21) [common]
6350 01:02:50.587544 start: 3 lava-test-retry (timeout 00:08:18) [common]
6351 01:02:50.588006 start: 3.1 lava-test-shell (timeout 00:08:18) [common]
6352 01:02:50.588367 Using namespace: common
6354 01:02:50.689449 / # #
6355 01:02:50.690101 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6356 01:02:50.695800 #
6357 01:02:50.696599 Using /lava-14368623
6359 01:02:50.797677 / # export SHELL=/bin/sh
6360 01:02:50.803846 export SHELL=/bin/sh
6362 01:02:50.905419 / # . /lava-14368623/environment
6363 01:02:50.911939 . /lava-14368623/environment
6365 01:02:51.013531 / # /lava-14368623/bin/lava-test-runner /lava-14368623/0
6366 01:02:51.014186 Test shell timeout: 10s (minimum of the action and connection timeout)
6367 01:02:51.020433 /lava-14368623/bin/lava-test-runner /lava-14368623/0
6368 01:02:51.050788 + export TESTRUN_ID=0_v4l2-compliance-uvc
6369 01:02:51.053868 + cd /lava-14368623/0/tests/0_v4l2-compliance-uvc
6370 01:02:51.054419 + cat uuid
6371 01:02:51.057403 + UUID=14368623_1.5.2.3.1
6372 01:02:51.057915 + set +x
6373 01:02:51.063774 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14368623_1.5.2.3.1>
6374 01:02:51.064581 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14368623_1.5.2.3.1
6375 01:02:51.064960 Starting test lava.0_v4l2-compliance-uvc (14368623_1.5.2.3.1)
6376 01:02:51.065373 Skipping test definition patterns.
6377 01:02:51.067037 + /usr/bin/v4l2-parser.sh -d uvcvideo
6378 01:02:51.073742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
6379 01:02:51.074289 device: /dev/video2
6380 01:02:51.074887 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
6382 01:02:57.898618 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
6383 01:02:57.913409 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
6384 01:02:57.924428
6385 01:02:57.942035 Compliance test for uvcvideo device /dev/video2:
6386 01:02:57.953083
6387 01:02:57.965610 Driver Info:
6388 01:02:57.981494 Driver name : uvcvideo
6389 01:02:57.997817 Card type : HD WebCam: HD WebCam
6390 01:02:58.013752 Bus info : usb-11200000.usb-1.3
6391 01:02:58.024307 Driver version : 6.1.92
6392 01:02:58.037520 Capabilities : 0x84a00001
6393 01:02:58.056258 Metadata Capture
6394 01:02:58.069385 Streaming
6395 01:02:58.085214 Extended Pix Format
6396 01:02:58.099348 Device Capabilities
6397 01:02:58.113912 Device Caps : 0x04200001
6398 01:02:58.132409 Streaming
6399 01:02:58.147999 Extended Pix Format
6400 01:02:58.160945 Media Driver Info:
6401 01:02:58.176348 Driver name : uvcvideo
6402 01:02:58.192339 Model : HD WebCam: HD WebCam
6403 01:02:58.203459 Serial :
6404 01:02:58.222365 Bus info : usb-11200000.usb-1.3
6405 01:02:58.233099 Media version : 6.1.92
6406 01:02:58.251663 Hardware revision: 0x00003269 (12905)
6407 01:02:58.261845 Driver version : 6.1.92
6408 01:02:58.275783 Interface Info:
6409 01:02:58.291443 <LAVA_SIGNAL_TESTSET START Interface-Info>
6410 01:02:58.291878 ID : 0x03000002
6411 01:02:58.292688 Received signal: <TESTSET> START Interface-Info
6412 01:02:58.293317 Starting test_set Interface-Info
6413 01:02:58.305174 Type : V4L Video
6414 01:02:58.321132 Entity Info:
6415 01:02:58.329974 <LAVA_SIGNAL_TESTSET STOP>
6416 01:02:58.331066 Received signal: <TESTSET> STOP
6417 01:02:58.331580 Closing test_set Interface-Info
6418 01:02:58.341051 <LAVA_SIGNAL_TESTSET START Entity-Info>
6419 01:02:58.341824 Received signal: <TESTSET> START Entity-Info
6420 01:02:58.342198 Starting test_set Entity-Info
6421 01:02:58.343850 ID : 0x00000001 (1)
6422 01:02:58.360745 Name : HD WebCam: HD WebCam
6423 01:02:58.374663 Function : V4L2 I/O
6424 01:02:58.389214 Flags : default
6425 01:02:58.402868 Pad 0x01000007 : 0: Sink
6426 01:02:58.426298 Link 0x02000013: from remote pad 0x100000a of entity 'Extension 4' (Video Pixel Formatter): Data, Enabled, Immutable
6427 01:02:58.426800
6428 01:02:58.443646 Required ioctls:
6429 01:02:58.452997 <LAVA_SIGNAL_TESTSET STOP>
6430 01:02:58.453767 Received signal: <TESTSET> STOP
6431 01:02:58.454116 Closing test_set Entity-Info
6432 01:02:58.464738 <LAVA_SIGNAL_TESTSET START Required-ioctls>
6433 01:02:58.465515 Received signal: <TESTSET> START Required-ioctls
6434 01:02:58.465890 Starting test_set Required-ioctls
6435 01:02:58.468272 test MC information (see 'Media Driver Info' above): OK
6436 01:02:58.502604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
6437 01:02:58.503394 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
6439 01:02:58.505752 test VIDIOC_QUERYCAP: OK
6440 01:02:58.530046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
6441 01:02:58.531052 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
6443 01:02:58.533476 test invalid ioctls: OK
6444 01:02:58.561512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
6445 01:02:58.562055
6446 01:02:58.562923 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
6448 01:02:58.578045 Allow for multiple opens:
6449 01:02:58.588345 <LAVA_SIGNAL_TESTSET STOP>
6450 01:02:58.589107 Received signal: <TESTSET> STOP
6451 01:02:58.589453 Closing test_set Required-ioctls
6452 01:02:58.599127 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
6453 01:02:58.599891 Received signal: <TESTSET> START Allow-for-multiple-opens
6454 01:02:58.600246 Starting test_set Allow-for-multiple-opens
6455 01:02:58.602508 test second /dev/video2 open: OK
6456 01:02:58.627854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
6457 01:02:58.628634 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
6459 01:02:58.630509 test VIDIOC_QUERYCAP: OK
6460 01:02:58.659149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
6461 01:02:58.659928 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
6463 01:02:58.662396 test VIDIOC_G/S_PRIORITY: OK
6464 01:02:58.691054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
6465 01:02:58.691819 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
6467 01:02:58.694434 test for unlimited opens: OK
6468 01:02:58.724272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
6469 01:02:58.724793
6470 01:02:58.725468 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
6472 01:02:58.746109 Debug ioctls:
6473 01:02:58.754667 <LAVA_SIGNAL_TESTSET STOP>
6474 01:02:58.755505 Received signal: <TESTSET> STOP
6475 01:02:58.755869 Closing test_set Allow-for-multiple-opens
6476 01:02:58.765713 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
6477 01:02:58.766542 Received signal: <TESTSET> START Debug-ioctls
6478 01:02:58.766911 Starting test_set Debug-ioctls
6479 01:02:58.769252 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
6480 01:02:58.794563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
6481 01:02:58.795307 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
6483 01:02:58.801448 test VIDIOC_LOG_STATUS: OK (Not Supported)
6484 01:02:58.823799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
6485 01:02:58.824312
6486 01:02:58.824897 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
6488 01:02:58.839193 Input ioctls:
6489 01:02:58.846745 <LAVA_SIGNAL_TESTSET STOP>
6490 01:02:58.847505 Received signal: <TESTSET> STOP
6491 01:02:58.847852 Closing test_set Debug-ioctls
6492 01:02:58.856974 <LAVA_SIGNAL_TESTSET START Input-ioctls>
6493 01:02:58.857738 Received signal: <TESTSET> START Input-ioctls
6494 01:02:58.858089 Starting test_set Input-ioctls
6495 01:02:58.860050 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
6496 01:02:58.889372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
6497 01:02:58.890135 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
6499 01:02:58.892700 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
6500 01:02:58.917776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
6501 01:02:58.918553 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
6503 01:02:58.924322 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
6504 01:02:58.948987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
6505 01:02:58.949758 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
6507 01:02:58.955188 test VIDIOC_ENUMAUDIO: OK (Not Supported)
6508 01:02:58.976424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
6509 01:02:58.977194 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
6511 01:02:58.979449 test VIDIOC_G/S/ENUMINPUT: OK
6512 01:02:59.008284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
6513 01:02:59.009053 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
6515 01:02:59.011657 test VIDIOC_G/S_AUDIO: OK (Not Supported)
6516 01:02:59.037131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
6517 01:02:59.037895 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
6519 01:02:59.040325 Inputs: 1 Audio Inputs: 0 Tuners: 0
6520 01:02:59.052280
6521 01:02:59.075017 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
6522 01:02:59.100757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
6523 01:02:59.101520 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
6525 01:02:59.107098 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
6526 01:02:59.132758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
6527 01:02:59.133514 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
6529 01:02:59.139109 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
6530 01:02:59.161347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
6531 01:02:59.162086 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
6533 01:02:59.166896 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
6534 01:02:59.192785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
6535 01:02:59.193532 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
6537 01:02:59.199147 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
6538 01:02:59.222722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
6539 01:02:59.223486 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
6541 01:02:59.226818
6542 01:02:59.248235 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
6543 01:02:59.275710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
6544 01:02:59.276474 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
6546 01:02:59.282162 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
6547 01:02:59.311115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
6548 01:02:59.311878 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
6550 01:02:59.314134 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
6551 01:02:59.340083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
6552 01:02:59.340840 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
6554 01:02:59.346476 test VIDIOC_G/S_EDID: OK (Not Supported)
6555 01:02:59.369184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
6556 01:02:59.369696
6557 01:02:59.370313 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
6559 01:02:59.383689 Control ioctls (Input 0):
6560 01:02:59.393397 <LAVA_SIGNAL_TESTSET STOP>
6561 01:02:59.394175 Received signal: <TESTSET> STOP
6562 01:02:59.394558 Closing test_set Input-ioctls
6563 01:02:59.405207 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
6564 01:02:59.405963 Received signal: <TESTSET> START Control-ioctls-Input-0
6565 01:02:59.406349 Starting test_set Control-ioctls-Input-0
6566 01:02:59.408456 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
6567 01:02:59.437673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
6568 01:02:59.438195 test VIDIOC_QUERYCTRL: OK
6569 01:02:59.438820 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
6571 01:02:59.461832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
6572 01:02:59.462626 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
6574 01:02:59.464995 test VIDIOC_G/S_CTRL: OK
6575 01:02:59.490137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
6576 01:02:59.490924 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
6578 01:02:59.493234 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
6579 01:02:59.524637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
6580 01:02:59.525395 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
6582 01:02:59.530750 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
6583 01:02:59.558275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
6584 01:02:59.559011 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
6586 01:02:59.561805 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
6587 01:02:59.587253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
6588 01:02:59.587986 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
6590 01:02:59.590550 Standard Controls: 15 Private Controls: 0
6591 01:02:59.604260
6592 01:02:59.618687 Format ioctls (Input 0):
6593 01:02:59.629135 <LAVA_SIGNAL_TESTSET STOP>
6594 01:02:59.629889 Received signal: <TESTSET> STOP
6595 01:02:59.630272 Closing test_set Control-ioctls-Input-0
6596 01:02:59.640321 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
6597 01:02:59.641076 Received signal: <TESTSET> START Format-ioctls-Input-0
6598 01:02:59.641426 Starting test_set Format-ioctls-Input-0
6599 01:02:59.643508 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
6600 01:02:59.675137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
6601 01:02:59.675902 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
6603 01:02:59.678119 test VIDIOC_G/S_PARM: OK
6604 01:02:59.700769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
6605 01:02:59.701582 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
6607 01:02:59.703981 test VIDIOC_G_FBUF: OK (Not Supported)
6608 01:02:59.730603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
6609 01:02:59.731362 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
6611 01:02:59.733968 test VIDIOC_G_FMT: OK
6612 01:02:59.761972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
6613 01:02:59.762770 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
6615 01:02:59.764632 test VIDIOC_TRY_FMT: OK
6616 01:02:59.795020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
6617 01:02:59.795776 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
6619 01:02:59.801977 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
6620 01:02:59.809783 test VIDIOC_S_FMT: OK
6621 01:02:59.840711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
6622 01:02:59.841468 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
6624 01:02:59.843894 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
6625 01:02:59.879492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
6626 01:02:59.880244 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
6628 01:02:59.882454 test Cropping: OK (Not Supported)
6629 01:02:59.907779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
6630 01:02:59.908537 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
6632 01:02:59.910596 test Composing: OK (Not Supported)
6633 01:02:59.938079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
6634 01:02:59.938891 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
6636 01:02:59.941454 test Scaling: OK (Not Supported)
6637 01:02:59.970769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
6638 01:02:59.971264
6639 01:02:59.971835 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
6641 01:02:59.987632 Codec ioctls (Input 0):
6642 01:02:59.998229 <LAVA_SIGNAL_TESTSET STOP>
6643 01:02:59.998982 Received signal: <TESTSET> STOP
6644 01:02:59.999323 Closing test_set Format-ioctls-Input-0
6645 01:03:00.008072 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
6646 01:03:00.008828 Received signal: <TESTSET> START Codec-ioctls-Input-0
6647 01:03:00.009177 Starting test_set Codec-ioctls-Input-0
6648 01:03:00.011141 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
6649 01:03:00.040734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
6650 01:03:00.041492 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
6652 01:03:00.047029 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
6653 01:03:00.072631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
6654 01:03:00.073389 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
6656 01:03:00.078734 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
6657 01:03:00.105877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
6658 01:03:00.106438
6659 01:03:00.107022 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
6661 01:03:00.122954 Buffer ioctls (Input 0):
6662 01:03:00.132702 <LAVA_SIGNAL_TESTSET STOP>
6663 01:03:00.133463 Received signal: <TESTSET> STOP
6664 01:03:00.133807 Closing test_set Codec-ioctls-Input-0
6665 01:03:00.142422 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
6666 01:03:00.143218 Received signal: <TESTSET> START Buffer-ioctls-Input-0
6667 01:03:00.143589 Starting test_set Buffer-ioctls-Input-0
6668 01:03:00.145184 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
6669 01:03:00.176797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
6670 01:03:00.177562 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
6672 01:03:00.179839 test CREATE_BUFS maximum buffers: OK
6673 01:03:00.203802 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
6675 01:03:00.206844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
6676 01:03:00.207354 test VIDIOC_EXPBUF: OK
6677 01:03:00.235330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
6678 01:03:00.236094 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
6680 01:03:00.238621 test Requests: OK (Not Supported)
6681 01:03:00.266452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
6682 01:03:00.266967
6683 01:03:00.267545 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
6685 01:03:00.281459 Test input 0:
6686 01:03:00.293997
6687 01:03:00.309459 Streaming ioctls:
6688 01:03:00.319491 <LAVA_SIGNAL_TESTSET STOP>
6689 01:03:00.320246 Received signal: <TESTSET> STOP
6690 01:03:00.320587 Closing test_set Buffer-ioctls-Input-0
6691 01:03:00.330207 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
6692 01:03:00.330995 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
6693 01:03:00.331356 Starting test_set Streaming-ioctls_Test-input-0
6694 01:03:00.333565 test read/write: OK (Not Supported)
6695 01:03:00.362403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
6696 01:03:00.363152 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
6698 01:03:00.365490 test blocking wait: OK
6699 01:03:00.390573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
6700 01:03:00.391330 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
6702 01:03:00.396988 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
6703 01:03:00.404530 test MMAP (no poll): FAIL
6704 01:03:00.433807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
6705 01:03:00.434609 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
6707 01:03:00.440221 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
6708 01:03:00.448534 test MMAP (select): FAIL
6709 01:03:00.480291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
6710 01:03:00.481048 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
6712 01:03:00.486794 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
6713 01:03:00.493562 test MMAP (epoll): FAIL
6714 01:03:00.523262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
6715 01:03:00.523776
6716 01:03:00.524356 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
6718 01:03:00.760596
6719 01:03:00.773651 test USERPTR (no poll): OK
6720 01:03:00.805092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
6721 01:03:00.805607
6722 01:03:00.806191 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
6724 01:03:01.049928
6725 01:03:01.059938 test USERPTR (select): OK
6726 01:03:01.092004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
6727 01:03:01.092748 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
6729 01:03:01.098138 test DMABUF: Cannot test, specify --expbuf-device
6730 01:03:01.107345
6731 01:03:01.126973 Total for uvcvideo device /dev/video2: 54, Succeeded: 51, Failed: 3, Warnings: 1
6732 01:03:01.132232 <LAVA_TEST_RUNNER EXIT>
6733 01:03:01.132602 ok: lava_test_shell seems to have completed
6734 01:03:01.132735 Marking unfinished test run as failed
6736 01:03:01.134173 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
6737 01:03:01.134401 end: 3.1 lava-test-shell (duration 00:00:11) [common]
6738 01:03:01.134543 end: 3 lava-test-retry (duration 00:00:11) [common]
6739 01:03:01.134690 start: 4 finalize (timeout 00:08:07) [common]
6740 01:03:01.134836 start: 4.1 power-off (timeout 00:00:30) [common]
6741 01:03:01.135083 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-5', '--port=1', '--command=off']
6742 01:03:01.371718 >> Command sent successfully.
6743 01:03:01.386347 Returned 0 in 0 seconds
6744 01:03:01.487762 end: 4.1 power-off (duration 00:00:00) [common]
6746 01:03:01.489162 start: 4.2 read-feedback (timeout 00:08:07) [common]
6747 01:03:01.490359 Listened to connection for namespace 'common' for up to 1s
6748 01:03:02.490523 Finalising connection for namespace 'common'
6749 01:03:02.491170 Disconnecting from shell: Finalise
6750 01:03:02.491570 / #
6751 01:03:02.592513 end: 4.2 read-feedback (duration 00:00:01) [common]
6752 01:03:02.593204 end: 4 finalize (duration 00:00:01) [common]
6753 01:03:02.593809 Cleaning after the job
6754 01:03:02.594361 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/ramdisk
6755 01:03:02.615326 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/kernel
6756 01:03:02.646638 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/dtb
6757 01:03:02.646932 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368623/tftp-deploy-v7j96_eo/modules
6758 01:03:02.654336 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368623
6759 01:03:02.713784 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368623
6760 01:03:02.713945 Job finished correctly