Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 44
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 88
1 01:01:45.374964 lava-dispatcher, installed at version: 2024.03
2 01:01:45.375185 start: 0 validate
3 01:01:45.375300 Start time: 2024-06-16 01:01:45.375294+00:00 (UTC)
4 01:01:45.375435 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:01:45.375576 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:01:45.627781 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:01:45.627946 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:01:45.877674 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:01:45.878568 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 01:01:46.131834 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:01:46.132423 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:01:46.384358 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:01:46.384496 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:01:46.636498 validate duration: 1.26
16 01:01:46.636838 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:01:46.636979 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:01:46.637120 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:01:46.637342 Not decompressing ramdisk as can be used compressed.
20 01:01:46.637472 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:01:46.637593 saving as /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/ramdisk/initrd.cpio.gz
22 01:01:46.637691 total size: 5628169 (5 MB)
23 01:01:46.639068 progress 0 % (0 MB)
24 01:01:46.641565 progress 5 % (0 MB)
25 01:01:46.644037 progress 10 % (0 MB)
26 01:01:46.646357 progress 15 % (0 MB)
27 01:01:46.648774 progress 20 % (1 MB)
28 01:01:46.651074 progress 25 % (1 MB)
29 01:01:46.653441 progress 30 % (1 MB)
30 01:01:46.655971 progress 35 % (1 MB)
31 01:01:46.658138 progress 40 % (2 MB)
32 01:01:46.660642 progress 45 % (2 MB)
33 01:01:46.662795 progress 50 % (2 MB)
34 01:01:46.665124 progress 55 % (2 MB)
35 01:01:46.667668 progress 60 % (3 MB)
36 01:01:46.669762 progress 65 % (3 MB)
37 01:01:46.672175 progress 70 % (3 MB)
38 01:01:46.674323 progress 75 % (4 MB)
39 01:01:46.676661 progress 80 % (4 MB)
40 01:01:46.678570 progress 85 % (4 MB)
41 01:01:46.680122 progress 90 % (4 MB)
42 01:01:46.681679 progress 95 % (5 MB)
43 01:01:46.683106 progress 100 % (5 MB)
44 01:01:46.683332 5 MB downloaded in 0.05 s (117.63 MB/s)
45 01:01:46.683487 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:01:46.683722 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:01:46.683803 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:01:46.683878 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:01:46.684018 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:01:46.684089 saving as /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/kernel/Image
52 01:01:46.684144 total size: 54813184 (52 MB)
53 01:01:46.684199 No compression specified
54 01:01:46.685235 progress 0 % (0 MB)
55 01:01:46.699395 progress 5 % (2 MB)
56 01:01:46.713491 progress 10 % (5 MB)
57 01:01:46.727823 progress 15 % (7 MB)
58 01:01:46.741692 progress 20 % (10 MB)
59 01:01:46.755806 progress 25 % (13 MB)
60 01:01:46.769573 progress 30 % (15 MB)
61 01:01:46.783723 progress 35 % (18 MB)
62 01:01:46.797881 progress 40 % (20 MB)
63 01:01:46.811889 progress 45 % (23 MB)
64 01:01:46.826150 progress 50 % (26 MB)
65 01:01:46.840638 progress 55 % (28 MB)
66 01:01:46.854595 progress 60 % (31 MB)
67 01:01:46.869324 progress 65 % (34 MB)
68 01:01:46.883215 progress 70 % (36 MB)
69 01:01:46.897204 progress 75 % (39 MB)
70 01:01:46.911122 progress 80 % (41 MB)
71 01:01:46.924905 progress 85 % (44 MB)
72 01:01:46.938856 progress 90 % (47 MB)
73 01:01:46.952818 progress 95 % (49 MB)
74 01:01:46.966465 progress 100 % (52 MB)
75 01:01:46.966738 52 MB downloaded in 0.28 s (184.98 MB/s)
76 01:01:46.966890 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:01:46.967120 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:01:46.967204 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:01:46.967282 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:01:46.967411 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 01:01:46.967479 saving as /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 01:01:46.967549 total size: 57695 (0 MB)
84 01:01:46.967607 No compression specified
85 01:01:46.968761 progress 56 % (0 MB)
86 01:01:46.969026 progress 100 % (0 MB)
87 01:01:46.969241 0 MB downloaded in 0.00 s (32.58 MB/s)
88 01:01:46.969356 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:01:46.969559 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:01:46.969655 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:01:46.969733 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:01:46.969839 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:01:46.969900 saving as /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/nfsrootfs/full.rootfs.tar
95 01:01:46.969952 total size: 120894716 (115 MB)
96 01:01:46.970047 Using unxz to decompress xz
97 01:01:46.971266 progress 0 % (0 MB)
98 01:01:47.312310 progress 5 % (5 MB)
99 01:01:47.658815 progress 10 % (11 MB)
100 01:01:48.000273 progress 15 % (17 MB)
101 01:01:48.336296 progress 20 % (23 MB)
102 01:01:48.645454 progress 25 % (28 MB)
103 01:01:48.996295 progress 30 % (34 MB)
104 01:01:49.323067 progress 35 % (40 MB)
105 01:01:49.500814 progress 40 % (46 MB)
106 01:01:49.688630 progress 45 % (51 MB)
107 01:01:50.004154 progress 50 % (57 MB)
108 01:01:50.380774 progress 55 % (63 MB)
109 01:01:50.738314 progress 60 % (69 MB)
110 01:01:51.092932 progress 65 % (74 MB)
111 01:01:51.450756 progress 70 % (80 MB)
112 01:01:51.821351 progress 75 % (86 MB)
113 01:01:52.164622 progress 80 % (92 MB)
114 01:01:52.506709 progress 85 % (98 MB)
115 01:01:52.847483 progress 90 % (103 MB)
116 01:01:53.178892 progress 95 % (109 MB)
117 01:01:53.552262 progress 100 % (115 MB)
118 01:01:53.557589 115 MB downloaded in 6.59 s (17.50 MB/s)
119 01:01:53.557750 end: 1.4.1 http-download (duration 00:00:07) [common]
121 01:01:53.557977 end: 1.4 download-retry (duration 00:00:07) [common]
122 01:01:53.558089 start: 1.5 download-retry (timeout 00:09:53) [common]
123 01:01:53.558165 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 01:01:53.558288 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:01:53.558350 saving as /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/modules/modules.tar
126 01:01:53.558404 total size: 8617404 (8 MB)
127 01:01:53.558459 Using unxz to decompress xz
128 01:01:53.559978 progress 0 % (0 MB)
129 01:01:53.579584 progress 5 % (0 MB)
130 01:01:53.606182 progress 10 % (0 MB)
131 01:01:53.633904 progress 15 % (1 MB)
132 01:01:53.658476 progress 20 % (1 MB)
133 01:01:53.682973 progress 25 % (2 MB)
134 01:01:53.706905 progress 30 % (2 MB)
135 01:01:53.733371 progress 35 % (2 MB)
136 01:01:53.758474 progress 40 % (3 MB)
137 01:01:53.782483 progress 45 % (3 MB)
138 01:01:53.806647 progress 50 % (4 MB)
139 01:01:53.831350 progress 55 % (4 MB)
140 01:01:53.856375 progress 60 % (4 MB)
141 01:01:53.882585 progress 65 % (5 MB)
142 01:01:53.910320 progress 70 % (5 MB)
143 01:01:53.934538 progress 75 % (6 MB)
144 01:01:53.960899 progress 80 % (6 MB)
145 01:01:53.986148 progress 85 % (7 MB)
146 01:01:54.011713 progress 90 % (7 MB)
147 01:01:54.037656 progress 95 % (7 MB)
148 01:01:54.063329 progress 100 % (8 MB)
149 01:01:54.069438 8 MB downloaded in 0.51 s (16.08 MB/s)
150 01:01:54.069628 end: 1.5.1 http-download (duration 00:00:01) [common]
152 01:01:54.070046 end: 1.5 download-retry (duration 00:00:01) [common]
153 01:01:54.070131 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 01:01:54.070209 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 01:01:57.560409 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14368634/extract-nfsrootfs-pm0qfktj
156 01:01:57.560584 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 01:01:57.560676 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 01:01:57.560838 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp
159 01:01:57.560955 makedir: /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin
160 01:01:57.561044 makedir: /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/tests
161 01:01:57.561131 makedir: /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/results
162 01:01:57.561212 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-add-keys
163 01:01:57.561335 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-add-sources
164 01:01:57.561469 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-background-process-start
165 01:01:57.561598 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-background-process-stop
166 01:01:57.561754 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-common-functions
167 01:01:57.561910 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-echo-ipv4
168 01:01:57.562086 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-install-packages
169 01:01:57.562198 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-installed-packages
170 01:01:57.562307 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-os-build
171 01:01:57.562415 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-probe-channel
172 01:01:57.562524 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-probe-ip
173 01:01:57.562635 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-target-ip
174 01:01:57.562744 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-target-mac
175 01:01:57.562852 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-target-storage
176 01:01:57.562965 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-test-case
177 01:01:57.563073 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-test-event
178 01:01:57.563188 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-test-feedback
179 01:01:57.563298 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-test-raise
180 01:01:57.563408 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-test-reference
181 01:01:57.563518 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-test-runner
182 01:01:57.563627 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-test-set
183 01:01:57.563735 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-test-shell
184 01:01:57.563846 Updating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-add-keys (debian)
185 01:01:57.563979 Updating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-add-sources (debian)
186 01:01:57.564108 Updating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-install-packages (debian)
187 01:01:57.564233 Updating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-installed-packages (debian)
188 01:01:57.564357 Updating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/bin/lava-os-build (debian)
189 01:01:57.564466 Creating /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/environment
190 01:01:57.564553 LAVA metadata
191 01:01:57.564636 - LAVA_JOB_ID=14368634
192 01:01:57.564705 - LAVA_DISPATCHER_IP=192.168.201.1
193 01:01:57.564795 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 01:01:57.564851 skipped lava-vland-overlay
195 01:01:57.564916 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 01:01:57.564985 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 01:01:57.565040 skipped lava-multinode-overlay
198 01:01:57.565103 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 01:01:57.565170 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 01:01:57.565230 Loading test definitions
201 01:01:57.565302 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 01:01:57.565359 Using /lava-14368634 at stage 0
203 01:01:57.565622 uuid=14368634_1.6.2.3.1 testdef=None
204 01:01:57.565700 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 01:01:57.565773 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 01:01:57.566200 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 01:01:57.566393 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 01:01:57.566887 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 01:01:57.567098 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 01:01:57.567577 runner path: /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/0/tests/0_timesync-off test_uuid 14368634_1.6.2.3.1
213 01:01:57.567717 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 01:01:57.567917 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 01:01:57.567981 Using /lava-14368634 at stage 0
217 01:01:57.568065 Fetching tests from https://github.com/kernelci/test-definitions.git
218 01:01:57.568139 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/0/tests/1_kselftest-arm64'
219 01:01:59.877288 Running '/usr/bin/git checkout kernelci.org
220 01:02:00.025670 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 01:02:00.026075 uuid=14368634_1.6.2.3.5 testdef=None
222 01:02:00.026174 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 01:02:00.026366 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 01:02:00.026992 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 01:02:00.027194 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 01:02:00.028064 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 01:02:00.028274 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 01:02:00.029121 runner path: /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/0/tests/1_kselftest-arm64 test_uuid 14368634_1.6.2.3.5
232 01:02:00.029212 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 01:02:00.029336 BRANCH='cip-gitlab'
234 01:02:00.029415 SKIPFILE='/dev/null'
235 01:02:00.029497 SKIP_INSTALL='True'
236 01:02:00.029573 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 01:02:00.029651 TST_CASENAME=''
238 01:02:00.029726 TST_CMDFILES='arm64'
239 01:02:00.029894 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 01:02:00.030162 Creating lava-test-runner.conf files
242 01:02:00.030218 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368634/lava-overlay-6g6gu9jp/lava-14368634/0 for stage 0
243 01:02:00.030300 - 0_timesync-off
244 01:02:00.030360 - 1_kselftest-arm64
245 01:02:00.030447 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 01:02:00.030523 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 01:02:07.115120 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 01:02:07.115258 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 01:02:07.115343 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 01:02:07.115425 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 01:02:07.115504 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 01:02:07.273851 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 01:02:07.274032 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 01:02:07.274130 extracting modules file /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368634/extract-nfsrootfs-pm0qfktj
255 01:02:07.490692 extracting modules file /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368634/extract-overlay-ramdisk-mb1mvkua/ramdisk
256 01:02:07.717767 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 01:02:07.717914 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 01:02:07.717997 [common] Applying overlay to NFS
259 01:02:07.718059 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368634/compress-overlay-6597c2x1/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368634/extract-nfsrootfs-pm0qfktj
260 01:02:08.563038 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 01:02:08.563182 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 01:02:08.563266 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 01:02:08.563354 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 01:02:08.563424 Building ramdisk /var/lib/lava/dispatcher/tmp/14368634/extract-overlay-ramdisk-mb1mvkua/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368634/extract-overlay-ramdisk-mb1mvkua/ramdisk
265 01:02:08.886669 >> 130405 blocks
266 01:02:10.977015 rename /var/lib/lava/dispatcher/tmp/14368634/extract-overlay-ramdisk-mb1mvkua/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/ramdisk/ramdisk.cpio.gz
267 01:02:10.977193 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 01:02:10.977283 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 01:02:10.977362 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 01:02:10.977442 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/kernel/Image']
271 01:02:24.785418 Returned 0 in 13 seconds
272 01:02:24.886176 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/kernel/image.itb
273 01:02:25.312319 output: FIT description: Kernel Image image with one or more FDT blobs
274 01:02:25.312443 output: Created: Sun Jun 16 02:02:25 2024
275 01:02:25.312513 output: Image 0 (kernel-1)
276 01:02:25.312572 output: Description:
277 01:02:25.312629 output: Created: Sun Jun 16 02:02:25 2024
278 01:02:25.312684 output: Type: Kernel Image
279 01:02:25.312737 output: Compression: lzma compressed
280 01:02:25.312793 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
281 01:02:25.312844 output: Architecture: AArch64
282 01:02:25.312934 output: OS: Linux
283 01:02:25.313012 output: Load Address: 0x00000000
284 01:02:25.313063 output: Entry Point: 0x00000000
285 01:02:25.313112 output: Hash algo: crc32
286 01:02:25.313162 output: Hash value: f6f06660
287 01:02:25.313213 output: Image 1 (fdt-1)
288 01:02:25.313261 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 01:02:25.313310 output: Created: Sun Jun 16 02:02:25 2024
290 01:02:25.313358 output: Type: Flat Device Tree
291 01:02:25.313426 output: Compression: uncompressed
292 01:02:25.313483 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 01:02:25.313537 output: Architecture: AArch64
294 01:02:25.313612 output: Hash algo: crc32
295 01:02:25.313667 output: Hash value: a9713552
296 01:02:25.313722 output: Image 2 (ramdisk-1)
297 01:02:25.313776 output: Description: unavailable
298 01:02:25.313826 output: Created: Sun Jun 16 02:02:25 2024
299 01:02:25.313875 output: Type: RAMDisk Image
300 01:02:25.313927 output: Compression: uncompressed
301 01:02:25.313978 output: Data Size: 18737688 Bytes = 18298.52 KiB = 17.87 MiB
302 01:02:25.314091 output: Architecture: AArch64
303 01:02:25.314146 output: OS: Linux
304 01:02:25.314194 output: Load Address: unavailable
305 01:02:25.314243 output: Entry Point: unavailable
306 01:02:25.314291 output: Hash algo: crc32
307 01:02:25.314339 output: Hash value: c4bb8ba0
308 01:02:25.314386 output: Default Configuration: 'conf-1'
309 01:02:25.314435 output: Configuration 0 (conf-1)
310 01:02:25.314483 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 01:02:25.314531 output: Kernel: kernel-1
312 01:02:25.314578 output: Init Ramdisk: ramdisk-1
313 01:02:25.314626 output: FDT: fdt-1
314 01:02:25.314673 output: Loadables: kernel-1
315 01:02:25.314749 output:
316 01:02:25.314910 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 01:02:25.315000 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 01:02:25.315090 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 01:02:25.315171 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 01:02:25.315236 No LXC device requested
321 01:02:25.315304 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 01:02:25.315381 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 01:02:25.315452 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 01:02:25.315514 Checking files for TFTP limit of 4294967296 bytes.
325 01:02:25.315990 end: 1 tftp-deploy (duration 00:00:39) [common]
326 01:02:25.316086 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 01:02:25.316169 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 01:02:25.316279 substitutions:
329 01:02:25.316340 - {DTB}: 14368634/tftp-deploy-3qp76dav/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 01:02:25.316400 - {INITRD}: 14368634/tftp-deploy-3qp76dav/ramdisk/ramdisk.cpio.gz
331 01:02:25.316454 - {KERNEL}: 14368634/tftp-deploy-3qp76dav/kernel/Image
332 01:02:25.316506 - {LAVA_MAC}: None
333 01:02:25.316557 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14368634/extract-nfsrootfs-pm0qfktj
334 01:02:25.316608 - {NFS_SERVER_IP}: 192.168.201.1
335 01:02:25.316657 - {PRESEED_CONFIG}: None
336 01:02:25.316714 - {PRESEED_LOCAL}: None
337 01:02:25.316765 - {RAMDISK}: 14368634/tftp-deploy-3qp76dav/ramdisk/ramdisk.cpio.gz
338 01:02:25.316815 - {ROOT_PART}: None
339 01:02:25.316864 - {ROOT}: None
340 01:02:25.316913 - {SERVER_IP}: 192.168.201.1
341 01:02:25.316961 - {TEE}: None
342 01:02:25.317011 Parsed boot commands:
343 01:02:25.317059 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 01:02:25.317210 Parsed boot commands: tftpboot 192.168.201.1 14368634/tftp-deploy-3qp76dav/kernel/image.itb 14368634/tftp-deploy-3qp76dav/kernel/cmdline
345 01:02:25.317299 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 01:02:25.317378 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 01:02:25.317458 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 01:02:25.317536 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 01:02:25.317598 Not connected, no need to disconnect.
350 01:02:25.317665 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 01:02:25.317739 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 01:02:25.317799 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-1'
353 01:02:25.321275 Setting prompt string to ['lava-test: # ']
354 01:02:25.321613 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 01:02:25.321719 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 01:02:25.321816 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 01:02:25.321918 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 01:02:25.322117 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-1']
359 01:02:46.960753 Returned 0 in 21 seconds
360 01:02:47.061276 end: 2.2.2.1 pdu-reboot (duration 00:00:22) [common]
362 01:02:47.061648 end: 2.2.2 reset-device (duration 00:00:22) [common]
363 01:02:47.061773 start: 2.2.3 depthcharge-start (timeout 00:04:38) [common]
364 01:02:47.061887 Setting prompt string to 'Starting depthcharge on Juniper...'
365 01:02:47.061977 Changing prompt to 'Starting depthcharge on Juniper...'
366 01:02:47.062063 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
367 01:02:47.062432 [Enter `^Ec?' for help]
368 01:02:47.062503 [DL] 00000000 00000000 010701
369 01:02:47.062571
370 01:02:47.062644
371 01:02:47.062698 F0: 102B 0000
372 01:02:47.062753
373 01:02:47.062806 F3: 1006 0033 [0200]
374 01:02:47.062867
375 01:02:47.062925 F3: 4001 00E0 [0200]
376 01:02:47.062978
377 01:02:47.063033 F3: 0000 0000
378 01:02:47.063086
379 01:02:47.063142 V0: 0000 0000 [0001]
380 01:02:47.063231
381 01:02:47.063314 00: 1027 0002
382 01:02:47.063411
383 01:02:47.063500 01: 0000 0000
384 01:02:47.063586
385 01:02:47.063667 BP: 0C00 0251 [0000]
386 01:02:47.063749
387 01:02:47.063827 G0: 1182 0000
388 01:02:47.063910
389 01:02:47.064006 EC: 0004 0000 [0001]
390 01:02:47.064085
391 01:02:47.064163 S7: 0000 0000 [0000]
392 01:02:47.064243
393 01:02:47.064321 CC: 0000 0000 [0001]
394 01:02:47.064402
395 01:02:47.064490 T0: 0000 00DB [000F]
396 01:02:47.064569
397 01:02:47.064646 Jump to BL
398 01:02:47.064724
399 01:02:47.064802
400 01:02:47.064879
401 01:02:47.064960 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
402 01:02:47.065043 ARM64: Exception handlers installed.
403 01:02:47.065122 ARM64: Testing exception
404 01:02:47.065200 ARM64: Done test exception
405 01:02:47.065253 WDT: Last reset was cold boot
406 01:02:47.065303 SPI0(PAD0) initialized at 992727 Hz
407 01:02:47.065353 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
408 01:02:47.065403 Manufacturer: ef
409 01:02:47.065456 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
410 01:02:47.065507 Probing TPM: . done!
411 01:02:47.065556 TPM ready after 0 ms
412 01:02:47.065606 Connected to device vid:did:rid of 1ae0:0028:00
413 01:02:47.065656 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
414 01:02:47.065719 Initialized TPM device CR50 revision 0
415 01:02:47.065799 tlcl_send_startup: Startup return code is 0
416 01:02:47.065878 TPM: setup succeeded
417 01:02:47.065961 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
418 01:02:47.066029 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
419 01:02:47.066081 in-header: 03 19 00 00 08 00 00 00
420 01:02:47.066154 in-data: a2 e0 47 00 13 00 00 00
421 01:02:47.066214 Chrome EC: UHEPI supported
422 01:02:47.066265 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
423 01:02:47.066316 in-header: 03 a1 00 00 08 00 00 00
424 01:02:47.066367 in-data: 84 60 60 10 00 00 00 00
425 01:02:47.066417 Phase 1
426 01:02:47.066498 FMAP: area GBB found @ 3f5000 (12032 bytes)
427 01:02:47.066590 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
428 01:02:47.066674 VB2:vb2_check_recovery() Recovery was requested manually
429 01:02:47.066755 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
430 01:02:47.066834 Recovery requested (1009000e)
431 01:02:47.066902 tlcl_extend: response is 0
432 01:02:47.066957 tlcl_extend: response is 0
433 01:02:47.067007
434 01:02:47.067056
435 01:02:47.067105 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
436 01:02:47.067158 ARM64: Exception handlers installed.
437 01:02:47.067209 ARM64: Testing exception
438 01:02:47.067258 ARM64: Done test exception
439 01:02:47.067308 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x826a, sec=0x2000
440 01:02:47.067386 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
441 01:02:47.067469 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
442 01:02:47.067548 [RTC]rtc_get_frequency_meter,134: input=0xf, output=876
443 01:02:47.067627 [RTC]rtc_get_frequency_meter,134: input=0x7, output=742
444 01:02:47.067708 [RTC]rtc_get_frequency_meter,134: input=0xb, output=809
445 01:02:47.067786 [RTC]rtc_get_frequency_meter,134: input=0x9, output=776
446 01:02:47.067865 [RTC]rtc_get_frequency_meter,134: input=0xa, output=792
447 01:02:47.067946 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x826a
448 01:02:47.068024 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
449 01:02:47.068103 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
450 01:02:47.068185 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
451 01:02:47.068263 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
452 01:02:47.068342 in-header: 03 19 00 00 08 00 00 00
453 01:02:47.068422 in-data: a2 e0 47 00 13 00 00 00
454 01:02:47.068500 Chrome EC: UHEPI supported
455 01:02:47.068579 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
456 01:02:47.068660 in-header: 03 a1 00 00 08 00 00 00
457 01:02:47.068739 in-data: 84 60 60 10 00 00 00 00
458 01:02:47.068817 Skip loading cached calibration data
459 01:02:47.068899 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
460 01:02:47.068978 in-header: 03 a1 00 00 08 00 00 00
461 01:02:47.069056 in-data: 84 60 60 10 00 00 00 00
462 01:02:47.069131 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
463 01:02:47.069183 in-header: 03 a1 00 00 08 00 00 00
464 01:02:47.069233 in-data: 84 60 60 10 00 00 00 00
465 01:02:47.069283 ADC[3]: Raw value=216781 ID=1
466 01:02:47.069332 Manufacturer: ef
467 01:02:47.069411 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
468 01:02:47.069491 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
469 01:02:47.069569 CBFS @ 21000 size 3d4000
470 01:02:47.069663 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
471 01:02:47.069740 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
472 01:02:47.069817 CBFS: Found @ offset 3c700 size 44
473 01:02:47.069895 DRAM-K: Full Calibration
474 01:02:47.069971 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
475 01:02:47.070087 CBFS @ 21000 size 3d4000
476 01:02:47.070140 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
477 01:02:47.070205 CBFS: Locating 'fallback/dram'
478 01:02:47.070263 CBFS: Found @ offset 24b00 size 12268
479 01:02:47.070312 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
480 01:02:47.070390 ddr_geometry: 1, config: 0x0
481 01:02:47.070466 header.status = 0x0
482 01:02:47.070603 header.magic = 0x44524d4b (expected: 0x44524d4b)
483 01:02:47.070717 header.version = 0x5 (expected: 0x5)
484 01:02:47.070808 header.size = 0x8f0 (expected: 0x8f0)
485 01:02:47.070888 header.config = 0x0
486 01:02:47.070964 header.flags = 0x0
487 01:02:47.071040 header.checksum = 0x0
488 01:02:47.071315 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
489 01:02:47.071404 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
490 01:02:47.071484 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
491 01:02:47.071562 ddr_geometry:1
492 01:02:47.071670 [EMI] new MDL number = 1
493 01:02:47.071748 dram_cbt_mode_extern: 0
494 01:02:47.071826 dram_cbt_mode [RK0]: 0, [RK1]: 0
495 01:02:47.071903 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
496 01:02:47.071978
497 01:02:47.072055
498 01:02:47.072132 [Bianco] ETT version 0.0.0.1
499 01:02:47.072210 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
500 01:02:47.072287
501 01:02:47.072338 vSetVcoreByFreq with vcore:762500, freq=1600
502 01:02:47.072388
503 01:02:47.072437 [DramcInit]
504 01:02:47.072485 AutoRefreshCKEOff AutoREF OFF
505 01:02:47.072536 DDRPhyPLLSetting-CKEOFF
506 01:02:47.072586 DDRPhyPLLSetting-CKEON
507 01:02:47.072635
508 01:02:47.072718 Enable WDQS
509 01:02:47.072806 [ModeRegInit_LP4] CH0 RK0
510 01:02:47.072958 Write Rank0 MR13 =0x18
511 01:02:47.073062 Write Rank0 MR12 =0x5d
512 01:02:47.073128 Write Rank0 MR1 =0x56
513 01:02:47.073179 Write Rank0 MR2 =0x1a
514 01:02:47.073239 Write Rank0 MR11 =0x0
515 01:02:47.073324 Write Rank0 MR22 =0x38
516 01:02:47.073401 Write Rank0 MR14 =0x5d
517 01:02:47.073487 Write Rank0 MR3 =0x30
518 01:02:47.073571 Write Rank0 MR13 =0x58
519 01:02:47.073648 Write Rank0 MR12 =0x5d
520 01:02:47.073726 Write Rank0 MR1 =0x56
521 01:02:47.073803 Write Rank0 MR2 =0x2d
522 01:02:47.073891 Write Rank0 MR11 =0x23
523 01:02:47.073968 Write Rank0 MR22 =0x34
524 01:02:47.074062 Write Rank0 MR14 =0x10
525 01:02:47.074111 Write Rank0 MR3 =0x30
526 01:02:47.074164 Write Rank0 MR13 =0xd8
527 01:02:47.074214 [ModeRegInit_LP4] CH0 RK1
528 01:02:47.074264 Write Rank1 MR13 =0x18
529 01:02:47.074312 Write Rank1 MR12 =0x5d
530 01:02:47.074361 Write Rank1 MR1 =0x56
531 01:02:47.074413 Write Rank1 MR2 =0x1a
532 01:02:47.074461 Write Rank1 MR11 =0x0
533 01:02:47.074510 Write Rank1 MR22 =0x38
534 01:02:47.074559 Write Rank1 MR14 =0x5d
535 01:02:47.074607 Write Rank1 MR3 =0x30
536 01:02:47.074696 Write Rank1 MR13 =0x58
537 01:02:47.074775 Write Rank1 MR12 =0x5d
538 01:02:47.074851 Write Rank1 MR1 =0x56
539 01:02:47.074958 Write Rank1 MR2 =0x2d
540 01:02:47.075034 Write Rank1 MR11 =0x23
541 01:02:47.075111 Write Rank1 MR22 =0x34
542 01:02:47.075189 Write Rank1 MR14 =0x10
543 01:02:47.075265 Write Rank1 MR3 =0x30
544 01:02:47.075352 Write Rank1 MR13 =0xd8
545 01:02:47.075442 [ModeRegInit_LP4] CH1 RK0
546 01:02:47.075521 Write Rank0 MR13 =0x18
547 01:02:47.075598 Write Rank0 MR12 =0x5d
548 01:02:47.075676 Write Rank0 MR1 =0x56
549 01:02:47.075753 Write Rank0 MR2 =0x1a
550 01:02:47.075829 Write Rank0 MR11 =0x0
551 01:02:47.075907 Write Rank0 MR22 =0x38
552 01:02:47.075982 Write Rank0 MR14 =0x5d
553 01:02:47.076058 Write Rank0 MR3 =0x30
554 01:02:47.076135 Write Rank0 MR13 =0x58
555 01:02:47.076211 Write Rank0 MR12 =0x5d
556 01:02:47.076287 Write Rank0 MR1 =0x56
557 01:02:47.076365 Write Rank0 MR2 =0x2d
558 01:02:47.076440 Write Rank0 MR11 =0x23
559 01:02:47.076516 Write Rank0 MR22 =0x34
560 01:02:47.076593 Write Rank0 MR14 =0x10
561 01:02:47.076672 Write Rank0 MR3 =0x30
562 01:02:47.076749 Write Rank0 MR13 =0xd8
563 01:02:47.076840 [ModeRegInit_LP4] CH1 RK1
564 01:02:47.076917 Write Rank1 MR13 =0x18
565 01:02:47.076993 Write Rank1 MR12 =0x5d
566 01:02:47.077067 Write Rank1 MR1 =0x56
567 01:02:47.077116 Write Rank1 MR2 =0x1a
568 01:02:47.077179 Write Rank1 MR11 =0x0
569 01:02:47.077342 Write Rank1 MR22 =0x38
570 01:02:47.077433 Write Rank1 MR14 =0x5d
571 01:02:47.077519 Write Rank1 MR3 =0x30
572 01:02:47.077597 Write Rank1 MR13 =0x58
573 01:02:47.077672 Write Rank1 MR12 =0x5d
574 01:02:47.077749 Write Rank1 MR1 =0x56
575 01:02:47.077826 Write Rank1 MR2 =0x2d
576 01:02:47.077902 Write Rank1 MR11 =0x23
577 01:02:47.077978 Write Rank1 MR22 =0x34
578 01:02:47.078069 Write Rank1 MR14 =0x10
579 01:02:47.078118 Write Rank1 MR3 =0x30
580 01:02:47.078166 Write Rank1 MR13 =0xd8
581 01:02:47.078215 match AC timing 3
582 01:02:47.078268 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
583 01:02:47.078320 [MiockJmeterHQA]
584 01:02:47.078369 vSetVcoreByFreq with vcore:762500, freq=1600
585 01:02:47.078418
586 01:02:47.078467 MIOCK jitter meter ch=0
587 01:02:47.078519
588 01:02:47.078567 1T = (89-15) = 74 dly cells
589 01:02:47.078620 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 844/100 ps
590 01:02:47.078670 vSetVcoreByFreq with vcore:725000, freq=1200
591 01:02:47.078718
592 01:02:47.078770 MIOCK jitter meter ch=0
593 01:02:47.078818
594 01:02:47.078865 1T = (84-13) = 71 dly cells
595 01:02:47.078915 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 880/100 ps
596 01:02:47.078965 vSetVcoreByFreq with vcore:725000, freq=800
597 01:02:47.079017
598 01:02:47.079066 MIOCK jitter meter ch=0
599 01:02:47.079129
600 01:02:47.079220 1T = (84-13) = 71 dly cells
601 01:02:47.079290 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 880/100 ps
602 01:02:47.079367 vSetVcoreByFreq with vcore:762500, freq=1600
603 01:02:47.079459 vSetVcoreByFreq with vcore:762500, freq=1600
604 01:02:47.079539
605 01:02:47.079615 K DRVP
606 01:02:47.079692 1. OCD DRVP=0 CALOUT=0
607 01:02:47.079772 1. OCD DRVP=1 CALOUT=0
608 01:02:47.079851 1. OCD DRVP=2 CALOUT=0
609 01:02:47.079930 1. OCD DRVP=3 CALOUT=0
610 01:02:47.080010 1. OCD DRVP=4 CALOUT=0
611 01:02:47.080089 1. OCD DRVP=5 CALOUT=0
612 01:02:47.080167 1. OCD DRVP=6 CALOUT=0
613 01:02:47.080248 1. OCD DRVP=7 CALOUT=0
614 01:02:47.080326 1. OCD DRVP=8 CALOUT=0
615 01:02:47.080404 1. OCD DRVP=9 CALOUT=1
616 01:02:47.080484
617 01:02:47.080561 1. OCD DRVP calibration OK! DRVP=9
618 01:02:47.080639
619 01:02:47.080717
620 01:02:47.080792
621 01:02:47.080881 K ODTN
622 01:02:47.080971 3. OCD ODTN=0 ,CALOUT=1
623 01:02:47.081053 3. OCD ODTN=1 ,CALOUT=1
624 01:02:47.081132 3. OCD ODTN=2 ,CALOUT=1
625 01:02:47.081204 3. OCD ODTN=3 ,CALOUT=1
626 01:02:47.081295 3. OCD ODTN=4 ,CALOUT=1
627 01:02:47.081386 3. OCD ODTN=5 ,CALOUT=1
628 01:02:47.081472 3. OCD ODTN=6 ,CALOUT=1
629 01:02:47.081624 3. OCD ODTN=7 ,CALOUT=1
630 01:02:47.081733 3. OCD ODTN=8 ,CALOUT=0
631 01:02:47.081823
632 01:02:47.081903 3. OCD ODTN calibration OK! ODTN=8
633 01:02:47.082007
634 01:02:47.082101 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=8
635 01:02:47.082179 term_option=0, Reg: DRVP=9, DRVN=8, ODTN=15
636 01:02:47.082257 term_option=0, Reg: DRVP=9, DRVN=8, ODTN=15 (After Adjust)
637 01:02:47.082333
638 01:02:47.082383 K DRVP
639 01:02:47.082433 1. OCD DRVP=0 CALOUT=0
640 01:02:47.082483 1. OCD DRVP=1 CALOUT=0
641 01:02:47.082533 1. OCD DRVP=2 CALOUT=0
642 01:02:47.082586 1. OCD DRVP=3 CALOUT=0
643 01:02:47.082636 1. OCD DRVP=4 CALOUT=0
644 01:02:47.082685 1. OCD DRVP=5 CALOUT=0
645 01:02:47.082735 1. OCD DRVP=6 CALOUT=0
646 01:02:47.082784 1. OCD DRVP=7 CALOUT=0
647 01:02:47.082836 1. OCD DRVP=8 CALOUT=0
648 01:02:47.082886 1. OCD DRVP=9 CALOUT=0
649 01:02:47.082935 1. OCD DRVP=10 CALOUT=1
650 01:02:47.082984
651 01:02:47.083036 1. OCD DRVP calibration OK! DRVP=10
652 01:02:47.083115
653 01:02:47.083190
654 01:02:47.083265
655 01:02:47.083342 K ODTN
656 01:02:47.083417 3. OCD ODTN=0 ,CALOUT=1
657 01:02:47.083688 3. OCD ODTN=1 ,CALOUT=1
658 01:02:47.083775 3. OCD ODTN=2 ,CALOUT=1
659 01:02:47.083855 3. OCD ODTN=3 ,CALOUT=1
660 01:02:47.083933 3. OCD ODTN=4 ,CALOUT=1
661 01:02:47.084014 3. OCD ODTN=5 ,CALOUT=1
662 01:02:47.084092 3. OCD ODTN=6 ,CALOUT=1
663 01:02:47.084179 3. OCD ODTN=7 ,CALOUT=1
664 01:02:47.084262 3. OCD ODTN=8 ,CALOUT=1
665 01:02:47.084341 3. OCD ODTN=9 ,CALOUT=1
666 01:02:47.084419 3. OCD ODTN=10 ,CALOUT=1
667 01:02:47.084500 3. OCD ODTN=11 ,CALOUT=1
668 01:02:47.084580 3. OCD ODTN=12 ,CALOUT=1
669 01:02:47.084658 3. OCD ODTN=13 ,CALOUT=1
670 01:02:47.084738 3. OCD ODTN=14 ,CALOUT=1
671 01:02:47.084817 3. OCD ODTN=15 ,CALOUT=0
672 01:02:47.084895
673 01:02:47.084973 3. OCD ODTN calibration OK! ODTN=15
674 01:02:47.085052
675 01:02:47.085129 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=15
676 01:02:47.085206 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15
677 01:02:47.085261 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15 (After Adjust)
678 01:02:47.085311
679 01:02:47.085359 [DramcInit]
680 01:02:47.085408 AutoRefreshCKEOff AutoREF OFF
681 01:02:47.085457 DDRPhyPLLSetting-CKEOFF
682 01:02:47.085535 DDRPhyPLLSetting-CKEON
683 01:02:47.085610
684 01:02:47.085686 Enable WDQS
685 01:02:47.085775 ==
686 01:02:47.085859 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
687 01:02:47.085936 fsp= 1, odt_onoff= 1, Byte mode= 0
688 01:02:47.086048 ==
689 01:02:47.086099 [Duty_Offset_Calibration]
690 01:02:47.086149
691 01:02:47.086200 ===========================
692 01:02:47.086251 B0:0 B1:0 CA:2
693 01:02:47.086298 ==
694 01:02:47.086347 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
695 01:02:47.086396 fsp= 1, odt_onoff= 1, Byte mode= 0
696 01:02:47.086448 ==
697 01:02:47.086497 [Duty_Offset_Calibration]
698 01:02:47.086545
699 01:02:47.086593 ===========================
700 01:02:47.086641 B0:0 B1:1 CA:1
701 01:02:47.086692 [ModeRegInit_LP4] CH0 RK0
702 01:02:47.086742 Write Rank0 MR13 =0x18
703 01:02:47.086790 Write Rank0 MR12 =0x5d
704 01:02:47.086838 Write Rank0 MR1 =0x56
705 01:02:47.086887 Write Rank0 MR2 =0x1a
706 01:02:47.086937 Write Rank0 MR11 =0x0
707 01:02:47.087002 Write Rank0 MR22 =0x38
708 01:02:47.087051 Write Rank0 MR14 =0x5d
709 01:02:47.087129 Write Rank0 MR3 =0x30
710 01:02:47.087182 Write Rank0 MR13 =0x58
711 01:02:47.087232 Write Rank0 MR12 =0x5d
712 01:02:47.087281 Write Rank0 MR1 =0x56
713 01:02:47.087330 Write Rank0 MR2 =0x2d
714 01:02:47.087385 Write Rank0 MR11 =0x23
715 01:02:47.087486 Write Rank0 MR22 =0x34
716 01:02:47.087563 Write Rank0 MR14 =0x10
717 01:02:47.087639 Write Rank0 MR3 =0x30
718 01:02:47.087717 Write Rank0 MR13 =0xd8
719 01:02:47.087792 [ModeRegInit_LP4] CH0 RK1
720 01:02:47.087868 Write Rank1 MR13 =0x18
721 01:02:47.087946 Write Rank1 MR12 =0x5d
722 01:02:47.088021 Write Rank1 MR1 =0x56
723 01:02:47.088097 Write Rank1 MR2 =0x1a
724 01:02:47.088174 Write Rank1 MR11 =0x0
725 01:02:47.088258 Write Rank1 MR22 =0x38
726 01:02:47.088420 Write Rank1 MR14 =0x5d
727 01:02:47.088513 Write Rank1 MR3 =0x30
728 01:02:47.088597 Write Rank1 MR13 =0x58
729 01:02:47.088688 Write Rank1 MR12 =0x5d
730 01:02:47.088766 Write Rank1 MR1 =0x56
731 01:02:47.088856 Write Rank1 MR2 =0x2d
732 01:02:47.088934 Write Rank1 MR11 =0x23
733 01:02:47.089013 Write Rank1 MR22 =0x34
734 01:02:47.089079 Write Rank1 MR14 =0x10
735 01:02:47.089129 Write Rank1 MR3 =0x30
736 01:02:47.089178 Write Rank1 MR13 =0xd8
737 01:02:47.089227 [ModeRegInit_LP4] CH1 RK0
738 01:02:47.089276 Write Rank0 MR13 =0x18
739 01:02:47.089327 Write Rank0 MR12 =0x5d
740 01:02:47.089376 Write Rank0 MR1 =0x56
741 01:02:47.089424 Write Rank0 MR2 =0x1a
742 01:02:47.089472 Write Rank0 MR11 =0x0
743 01:02:47.089524 Write Rank0 MR22 =0x38
744 01:02:47.089605 Write Rank0 MR14 =0x5d
745 01:02:47.089691 Write Rank0 MR3 =0x30
746 01:02:47.089768 Write Rank0 MR13 =0x58
747 01:02:47.089845 Write Rank0 MR12 =0x5d
748 01:02:47.089920 Write Rank0 MR1 =0x56
749 01:02:47.090018 Write Rank0 MR2 =0x2d
750 01:02:47.090086 Write Rank0 MR11 =0x23
751 01:02:47.090136 Write Rank0 MR22 =0x34
752 01:02:47.090184 Write Rank0 MR14 =0x10
753 01:02:47.090236 Write Rank0 MR3 =0x30
754 01:02:47.090326 Write Rank0 MR13 =0xd8
755 01:02:47.090403 [ModeRegInit_LP4] CH1 RK1
756 01:02:47.090508 Write Rank1 MR13 =0x18
757 01:02:47.090615 Write Rank1 MR12 =0x5d
758 01:02:47.090701 Write Rank1 MR1 =0x56
759 01:02:47.090782 Write Rank1 MR2 =0x1a
760 01:02:47.090858 Write Rank1 MR11 =0x0
761 01:02:47.090934 Write Rank1 MR22 =0x38
762 01:02:47.091011 Write Rank1 MR14 =0x5d
763 01:02:47.091086 Write Rank1 MR3 =0x30
764 01:02:47.091163 Write Rank1 MR13 =0x58
765 01:02:47.091324 Write Rank1 MR12 =0x5d
766 01:02:47.091424 Write Rank1 MR1 =0x56
767 01:02:47.091513 Write Rank1 MR2 =0x2d
768 01:02:47.091590 Write Rank1 MR11 =0x23
769 01:02:47.091666 Write Rank1 MR22 =0x34
770 01:02:47.091744 Write Rank1 MR14 =0x10
771 01:02:47.091819 Write Rank1 MR3 =0x30
772 01:02:47.091896 Write Rank1 MR13 =0xd8
773 01:02:47.091974 match AC timing 3
774 01:02:47.092052 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
775 01:02:47.092129 DramC Write-DBI off
776 01:02:47.092209 DramC Read-DBI off
777 01:02:47.092295 Write Rank0 MR13 =0x59
778 01:02:47.092461 ==
779 01:02:47.092559 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
780 01:02:47.092641 fsp= 1, odt_onoff= 1, Byte mode= 0
781 01:02:47.092719 ==
782 01:02:47.092796 === u2Vref_new: 0x56 --> 0x2d
783 01:02:47.092873 === u2Vref_new: 0x58 --> 0x38
784 01:02:47.092951 === u2Vref_new: 0x5a --> 0x39
785 01:02:47.093028 === u2Vref_new: 0x5c --> 0x3c
786 01:02:47.093114 === u2Vref_new: 0x5e --> 0x3d
787 01:02:47.093170 === u2Vref_new: 0x60 --> 0xa0
788 01:02:47.093220 [CA 0] Center 34 (6~63) winsize 58
789 01:02:47.093269 [CA 1] Center 36 (9~63) winsize 55
790 01:02:47.093317 [CA 2] Center 30 (2~59) winsize 58
791 01:02:47.093370 [CA 3] Center 26 (-2~54) winsize 57
792 01:02:47.093447 [CA 4] Center 26 (-2~54) winsize 57
793 01:02:47.093523 [CA 5] Center 31 (2~61) winsize 60
794 01:02:47.093598
795 01:02:47.093677 [CATrainingPosCal] consider 1 rank data
796 01:02:47.093754 u2DelayCellTimex100 = 844/100 ps
797 01:02:47.093831 CA0 delay=34 (6~63),Diff = 8 PI (9 cell)
798 01:02:47.093925 CA1 delay=36 (9~63),Diff = 10 PI (11 cell)
799 01:02:47.094022 CA2 delay=30 (2~59),Diff = 4 PI (4 cell)
800 01:02:47.094087 CA3 delay=26 (-2~54),Diff = 0 PI (0 cell)
801 01:02:47.094142 CA4 delay=26 (-2~54),Diff = 0 PI (0 cell)
802 01:02:47.094191 CA5 delay=31 (2~61),Diff = 5 PI (5 cell)
803 01:02:47.094240
804 01:02:47.094289 CA PerBit enable=1, Macro0, CA PI delay=26
805 01:02:47.094338 === u2Vref_new: 0x60 --> 0xa0
806 01:02:47.094390
807 01:02:47.094439 Vref(ca) range 1: 32
808 01:02:47.094541
809 01:02:47.094634 CS Dly= 10 (41-0-32)
810 01:02:47.094710 Write Rank0 MR13 =0xd8
811 01:02:47.094786 Write Rank0 MR13 =0xd8
812 01:02:47.094864 Write Rank0 MR12 =0x60
813 01:02:47.094940 Write Rank1 MR13 =0x59
814 01:02:47.095017 ==
815 01:02:47.095115 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
816 01:02:47.095481 fsp= 1, odt_onoff= 1, Byte mode= 0
817 01:02:47.095571 ==
818 01:02:47.095654 === u2Vref_new: 0x56 --> 0x2d
819 01:02:47.095734 === u2Vref_new: 0x58 --> 0x38
820 01:02:47.095812 === u2Vref_new: 0x5a --> 0x39
821 01:02:47.095892 === u2Vref_new: 0x5c --> 0x3c
822 01:02:47.095970 === u2Vref_new: 0x5e --> 0x3d
823 01:02:47.096047 === u2Vref_new: 0x60 --> 0xa0
824 01:02:47.096126 [CA 0] Center 36 (9~63) winsize 55
825 01:02:47.096202 [CA 1] Center 36 (9~63) winsize 55
826 01:02:47.096279 [CA 2] Center 32 (3~61) winsize 59
827 01:02:47.096357 [CA 3] Center 26 (-2~54) winsize 57
828 01:02:47.096436 [CA 4] Center 25 (-2~53) winsize 56
829 01:02:47.096512 [CA 5] Center 30 (1~60) winsize 60
830 01:02:47.096589
831 01:02:47.096666 [CATrainingPosCal] consider 2 rank data
832 01:02:47.096742 u2DelayCellTimex100 = 844/100 ps
833 01:02:47.096818 CA0 delay=36 (9~63),Diff = 11 PI (12 cell)
834 01:02:47.096898 CA1 delay=36 (9~63),Diff = 11 PI (12 cell)
835 01:02:47.096976 CA2 delay=31 (3~59),Diff = 6 PI (6 cell)
836 01:02:47.097054 CA3 delay=26 (-2~54),Diff = 1 PI (1 cell)
837 01:02:47.097131 CA4 delay=25 (-2~53),Diff = 0 PI (0 cell)
838 01:02:47.097182 CA5 delay=31 (2~60),Diff = 6 PI (6 cell)
839 01:02:47.097231
840 01:02:47.097280 CA PerBit enable=1, Macro0, CA PI delay=25
841 01:02:47.097344 === u2Vref_new: 0x5c --> 0x3c
842 01:02:47.097427
843 01:02:47.097511 Vref(ca) range 1: 28
844 01:02:47.097590
845 01:02:47.097665 CS Dly= 6 (37-0-32)
846 01:02:47.097741 Write Rank1 MR13 =0xd8
847 01:02:47.097819 Write Rank1 MR13 =0xd8
848 01:02:47.097896 Write Rank1 MR12 =0x5c
849 01:02:47.097973 [RankSwap] Rank num 2, (Multi 1), Rank 0
850 01:02:47.098071 Write Rank0 MR2 =0xad
851 01:02:47.098122 [Write Leveling]
852 01:02:47.098171 delay byte0 byte1 byte2 byte3
853 01:02:47.098220
854 01:02:47.098269 10 0 0
855 01:02:47.098348 11 0 0
856 01:02:47.098415 12 0 0
857 01:02:47.098493 13 0 0
858 01:02:47.098573 14 0 0
859 01:02:47.098651 15 0 0
860 01:02:47.098729 16 0 0
861 01:02:47.098806 17 0 0
862 01:02:47.098892 18 0 0
863 01:02:47.098971 19 0 0
864 01:02:47.099051 20 0 0
865 01:02:47.099168 21 0 0
866 01:02:47.099247 22 0 0
867 01:02:47.099327 23 0 0
868 01:02:47.099406 24 0 ff
869 01:02:47.099485 25 0 ff
870 01:02:47.099565 26 0 ff
871 01:02:47.099643 27 0 ff
872 01:02:47.099721 28 0 ff
873 01:02:47.099801 29 0 ff
874 01:02:47.099881 30 0 ff
875 01:02:47.099959 31 0 ff
876 01:02:47.100040 32 ff ff
877 01:02:47.100119 33 ff ff
878 01:02:47.100197 34 ff ff
879 01:02:47.100278 35 ff ff
880 01:02:47.100368 36 ff ff
881 01:02:47.100448 37 ff ff
882 01:02:47.100529 38 ff ff
883 01:02:47.100609 pass bytecount = 0xff (0xff: all bytes pass)
884 01:02:47.100685
885 01:02:47.100763 DQS0 dly: 32
886 01:02:47.100831 DQS1 dly: 24
887 01:02:47.100881 Write Rank0 MR2 =0x2d
888 01:02:47.100952 [RankSwap] Rank num 2, (Multi 1), Rank 0
889 01:02:47.101007 Write Rank0 MR1 =0xd6
890 01:02:47.101056 [Gating]
891 01:02:47.101105 ==
892 01:02:47.101153 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
893 01:02:47.101202 fsp= 1, odt_onoff= 1, Byte mode= 0
894 01:02:47.101265 ==
895 01:02:47.101344 3 1 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
896 01:02:47.101424 3 1 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
897 01:02:47.101505 3 1 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
898 01:02:47.101596 3 1 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
899 01:02:47.101677 3 1 16 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
900 01:02:47.101758 3 1 20 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
901 01:02:47.101842 3 1 24 |3534 3535 |(11 11)(11 11) |(0 0)(0 0)| 0
902 01:02:47.101922 3 1 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
903 01:02:47.102025 3 2 0 |3534 2a2a |(11 11)(11 11) |(0 0)(1 1)| 0
904 01:02:47.102092 [Byte 1] Lead/lag Transition tap number (1)
905 01:02:47.102142 3 2 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
906 01:02:47.102192 3 2 8 |3534 3535 |(11 11)(11 11) |(0 1)(0 0)| 0
907 01:02:47.102246 3 2 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
908 01:02:47.102299 3 2 16 |201 403 |(11 11)(11 11) |(1 1)(1 1)| 0
909 01:02:47.102350 3 2 20 |3d3d 3c3b |(11 11)(11 11) |(1 1)(1 1)| 0
910 01:02:47.102400 3 2 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
911 01:02:47.102450 3 2 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
912 01:02:47.102521 3 3 0 |3d3d 3c3b |(11 11)(11 11) |(1 1)(1 1)| 0
913 01:02:47.102600 3 3 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
914 01:02:47.102691 [Byte 1] Lead/lag Transition tap number (1)
915 01:02:47.102814 3 3 8 |3d3d 2120 |(11 11)(11 11) |(1 1)(0 0)| 0
916 01:02:47.102894 3 3 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
917 01:02:47.102975 3 3 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
918 01:02:47.103054 3 3 20 |3534 202 |(11 11)(11 11) |(1 1)(1 1)| 0
919 01:02:47.103134 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
920 01:02:47.103214 [Byte 0] Lead/lag Transition tap number (1)
921 01:02:47.103294 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
922 01:02:47.103373 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
923 01:02:47.103453 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
924 01:02:47.103533 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
925 01:02:47.103612 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
926 01:02:47.103690 3 4 16 |403 bbef |(11 11)(11 11) |(1 1)(1 1)| 0
927 01:02:47.103772 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 01:02:47.103851 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 01:02:47.103930 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 01:02:47.104011 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 01:02:47.104090 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 01:02:47.104179 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 01:02:47.104263 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 01:02:47.104343 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
935 01:02:47.104422 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
936 01:02:47.104502 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
937 01:02:47.104581 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
938 01:02:47.104660 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
939 01:02:47.104742 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
940 01:02:47.105025 [Byte 0] Lead/lag falling Transition (3, 6, 4)
941 01:02:47.105110 [Byte 1] Lead/lag falling Transition (3, 6, 4)
942 01:02:47.105220 3 6 8 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
943 01:02:47.105301 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
944 01:02:47.105380 [Byte 0] Lead/lag Transition tap number (3)
945 01:02:47.105459 [Byte 1] Lead/lag Transition tap number (3)
946 01:02:47.105539 3 6 16 |605 202 |(11 11)(11 11) |(0 0)(0 0)| 0
947 01:02:47.105621 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 01:02:47.105701 [Byte 0]First pass (3, 6, 20)
949 01:02:47.105779 [Byte 1]First pass (3, 6, 20)
950 01:02:47.105857 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 01:02:47.105936 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 01:02:47.106092 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 01:02:47.106181 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
954 01:02:47.106261 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
955 01:02:47.106339 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
956 01:02:47.106421 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
957 01:02:47.106500 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
958 01:02:47.106578 All bytes gating window > 1UI, Early break!
959 01:02:47.106656
960 01:02:47.106732 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 10)
961 01:02:47.106809
962 01:02:47.106887 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 10)
963 01:02:47.106964
964 01:02:47.107039
965 01:02:47.107114
966 01:02:47.107191 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
967 01:02:47.107278
968 01:02:47.107357 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
969 01:02:47.107432
970 01:02:47.107509
971 01:02:47.107586 Write Rank0 MR1 =0x56
972 01:02:47.107674
973 01:02:47.107759 best RODT dly(2T, 0.5T) = (2, 3)
974 01:02:47.107843
975 01:02:47.107978 best RODT dly(2T, 0.5T) = (2, 3)
976 01:02:47.108108 ==
977 01:02:47.108200 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
978 01:02:47.108285 fsp= 1, odt_onoff= 1, Byte mode= 0
979 01:02:47.108368 ==
980 01:02:47.108447 Start DQ dly to find pass range UseTestEngine =0
981 01:02:47.108524 x-axis: bit #, y-axis: DQ dly (-127~63)
982 01:02:47.108603 RX Vref Scan = 0
983 01:02:47.108679 -26, [0] xxxxxxxx xxxxxxxx [MSB]
984 01:02:47.108761 -25, [0] xxxxxxxx xxxxxxxx [MSB]
985 01:02:47.108839 -24, [0] xxxxxxxx xxxxxxxx [MSB]
986 01:02:47.108919 -23, [0] xxxxxxxx xxxxxxxx [MSB]
987 01:02:47.108997 -22, [0] xxxxxxxx xxxxxxxx [MSB]
988 01:02:47.109074 -21, [0] xxxxxxxx xxxxxxxx [MSB]
989 01:02:47.109151 -20, [0] xxxxxxxx xxxxxxxx [MSB]
990 01:02:47.109204 -19, [0] xxxxxxxx xxxxxxxx [MSB]
991 01:02:47.109253 -18, [0] xxxxxxxx xxxxxxxx [MSB]
992 01:02:47.109302 -17, [0] xxxxxxxx xxxxxxxx [MSB]
993 01:02:47.109351 -16, [0] xxxxxxxx xxxxxxxx [MSB]
994 01:02:47.109400 -15, [0] xxxxxxxx xxxxxxxx [MSB]
995 01:02:47.109455 -14, [0] xxxxxxxx xxxxxxxx [MSB]
996 01:02:47.109534 -13, [0] xxxxxxxx xxxxxxxx [MSB]
997 01:02:47.109612 -12, [0] xxxxxxxx xxxxxxxx [MSB]
998 01:02:47.109690 -11, [0] xxxxxxxx xxxxxxxx [MSB]
999 01:02:47.109769 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1000 01:02:47.109847 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1001 01:02:47.109925 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1002 01:02:47.110044 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1003 01:02:47.110099 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1004 01:02:47.110149 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1005 01:02:47.110199 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1006 01:02:47.110273 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1007 01:02:47.110356 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1008 01:02:47.110435 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1009 01:02:47.110513 0, [0] xxxxxxxx xxxxxxxx [MSB]
1010 01:02:47.110592 1, [0] xxxxxxxx oxxxxxxx [MSB]
1011 01:02:47.110684 2, [0] xxxxxxxx oxxxxxxx [MSB]
1012 01:02:47.110763 3, [0] xxxoxxxx oxxoxxxx [MSB]
1013 01:02:47.110841 4, [0] xxxoxoxx ooxoxoxx [MSB]
1014 01:02:47.110921 5, [0] xxxoxoxx ooxoxoox [MSB]
1015 01:02:47.110999 6, [0] xxxoxoxx ooxoooox [MSB]
1016 01:02:47.111077 7, [0] xxxoxooo ooxooooo [MSB]
1017 01:02:47.111156 8, [0] xoxoxooo ooxooooo [MSB]
1018 01:02:47.111237 9, [0] ooxooooo ooxooooo [MSB]
1019 01:02:47.111327 10, [0] oooooooo ooxooooo [MSB]
1020 01:02:47.111406 30, [0] oooooooo oooooooo [MSB]
1021 01:02:47.111485 31, [0] oooooooo oooooooo [MSB]
1022 01:02:47.111568 32, [0] oooxoooo oooooooo [MSB]
1023 01:02:47.111647 33, [0] oooxoooo xooooooo [MSB]
1024 01:02:47.111726 34, [0] oooxoooo xooooooo [MSB]
1025 01:02:47.111804 35, [0] oooxoxoo xooxoooo [MSB]
1026 01:02:47.111884 36, [0] oooxoxxo xxoxxooo [MSB]
1027 01:02:47.111962 37, [0] oooxoxxo xxoxxoxo [MSB]
1028 01:02:47.112040 38, [0] oooxoxxo xxoxxxxo [MSB]
1029 01:02:47.112123 39, [0] oxoxoxxx xxoxxxxo [MSB]
1030 01:02:47.112189 40, [0] xxoxxxxx xxoxxxxo [MSB]
1031 01:02:47.112241 41, [0] xxoxxxxx xxoxxxxx [MSB]
1032 01:02:47.112291 42, [0] xxxxxxxx xxxxxxxx [MSB]
1033 01:02:47.112341 iDelay=42, Bit 0, Center 24 (9 ~ 39) 31
1034 01:02:47.112390 iDelay=42, Bit 1, Center 23 (8 ~ 38) 31
1035 01:02:47.112442 iDelay=42, Bit 2, Center 25 (10 ~ 41) 32
1036 01:02:47.112519 iDelay=42, Bit 3, Center 17 (3 ~ 31) 29
1037 01:02:47.112609 iDelay=42, Bit 4, Center 24 (9 ~ 39) 31
1038 01:02:47.112692 iDelay=42, Bit 5, Center 19 (4 ~ 34) 31
1039 01:02:47.112769 iDelay=42, Bit 6, Center 21 (7 ~ 35) 29
1040 01:02:47.112851 iDelay=42, Bit 7, Center 22 (7 ~ 38) 32
1041 01:02:47.112932 iDelay=42, Bit 8, Center 16 (1 ~ 32) 32
1042 01:02:47.113026 iDelay=42, Bit 9, Center 19 (4 ~ 35) 32
1043 01:02:47.113105 iDelay=42, Bit 10, Center 26 (11 ~ 41) 31
1044 01:02:47.113186 iDelay=42, Bit 11, Center 18 (3 ~ 34) 32
1045 01:02:47.113263 iDelay=42, Bit 12, Center 20 (6 ~ 35) 30
1046 01:02:47.113341 iDelay=42, Bit 13, Center 20 (4 ~ 37) 34
1047 01:02:47.113422 iDelay=42, Bit 14, Center 20 (5 ~ 36) 32
1048 01:02:47.113505 iDelay=42, Bit 15, Center 23 (7 ~ 40) 34
1049 01:02:47.113582 ==
1050 01:02:47.113672 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1051 01:02:47.113751 fsp= 1, odt_onoff= 1, Byte mode= 0
1052 01:02:47.113828 ==
1053 01:02:47.113914 DQS Delay:
1054 01:02:47.114011 DQS0 = 0, DQS1 = 0
1055 01:02:47.114080 DQM Delay:
1056 01:02:47.114130 DQM0 = 21, DQM1 = 20
1057 01:02:47.114209 DQ Delay:
1058 01:02:47.114260 DQ0 =24, DQ1 =23, DQ2 =25, DQ3 =17
1059 01:02:47.114311 DQ4 =24, DQ5 =19, DQ6 =21, DQ7 =22
1060 01:02:47.114363 DQ8 =16, DQ9 =19, DQ10 =26, DQ11 =18
1061 01:02:47.114412 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =23
1062 01:02:47.114460
1063 01:02:47.114508
1064 01:02:47.114555 DramC Write-DBI off
1065 01:02:47.114608 ==
1066 01:02:47.114657 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1067 01:02:47.114912 fsp= 1, odt_onoff= 1, Byte mode= 0
1068 01:02:47.114969 ==
1069 01:02:47.115019 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1070 01:02:47.115071
1071 01:02:47.115148 Begin, DQ Scan Range 920~1176
1072 01:02:47.115223
1073 01:02:47.115301
1074 01:02:47.115417 TX Vref Scan disable
1075 01:02:47.115495 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1076 01:02:47.115577 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1077 01:02:47.115656 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1078 01:02:47.115735 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1079 01:02:47.115816 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1080 01:02:47.115895 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1081 01:02:47.115974 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1082 01:02:47.116053 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1083 01:02:47.116134 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1084 01:02:47.116213 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1085 01:02:47.116292 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1086 01:02:47.116370 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1087 01:02:47.116453 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1088 01:02:47.116532 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1089 01:02:47.116611 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1090 01:02:47.116720 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1091 01:02:47.116815 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1092 01:02:47.116894 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1093 01:02:47.116975 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1094 01:02:47.117062 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1095 01:02:47.117115 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1096 01:02:47.117165 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1097 01:02:47.117215 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1098 01:02:47.117271 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1099 01:02:47.117351 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1100 01:02:47.117430 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1101 01:02:47.117510 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1102 01:02:47.117592 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1103 01:02:47.117672 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1104 01:02:47.117759 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1105 01:02:47.117855 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1106 01:02:47.117952 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1107 01:02:47.118040 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1108 01:02:47.118093 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1109 01:02:47.118166 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1110 01:02:47.118246 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1111 01:02:47.118386 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1112 01:02:47.118516 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1113 01:02:47.118614 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1114 01:02:47.118697 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1115 01:02:47.118785 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1116 01:02:47.118865 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1117 01:02:47.118945 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1118 01:02:47.119026 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1119 01:02:47.119108 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1120 01:02:47.119188 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1121 01:02:47.119267 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1122 01:02:47.119348 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1123 01:02:47.119427 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1124 01:02:47.119506 969 |3 6 9|[0] xxxxxxxx oxxoooxx [MSB]
1125 01:02:47.119587 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1126 01:02:47.119666 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1127 01:02:47.119745 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1128 01:02:47.119824 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1129 01:02:47.119905 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1130 01:02:47.119984 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1131 01:02:47.120049 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1132 01:02:47.120110 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1133 01:02:47.120193 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1134 01:02:47.120274 979 |3 6 19|[0] xoxoooox oooooooo [MSB]
1135 01:02:47.120355 980 |3 6 20|[0] xooooooo oooooooo [MSB]
1136 01:02:47.120436 989 |3 6 29|[0] oooooooo xooxoooo [MSB]
1137 01:02:47.120518 990 |3 6 30|[0] oooooooo xooxoxoo [MSB]
1138 01:02:47.120599 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1139 01:02:47.120680 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1140 01:02:47.120759 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1141 01:02:47.120839 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1142 01:02:47.120918 995 |3 6 35|[0] oooxoxoo xxxxxxxx [MSB]
1143 01:02:47.121003 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1144 01:02:47.121088 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1145 01:02:47.121167 998 |3 6 38|[0] oooxoxxo xxxxxxxx [MSB]
1146 01:02:47.121246 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1147 01:02:47.121326 Byte0, DQ PI dly=987, DQM PI dly= 987
1148 01:02:47.121404 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
1149 01:02:47.121480
1150 01:02:47.121556 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
1151 01:02:47.121635
1152 01:02:47.121711 Byte1, DQ PI dly=980, DQM PI dly= 980
1153 01:02:47.121788 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1154 01:02:47.121866
1155 01:02:47.121942 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1156 01:02:47.122019
1157 01:02:47.122072 ==
1158 01:02:47.122122 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1159 01:02:47.122171 fsp= 1, odt_onoff= 1, Byte mode= 0
1160 01:02:47.122219 ==
1161 01:02:47.122267 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1162 01:02:47.122318
1163 01:02:47.122368 Begin, DQ Scan Range 956~1020
1164 01:02:47.122416 Write Rank0 MR14 =0x0
1165 01:02:47.122464
1166 01:02:47.122512 CH=0, VrefRange= 0, VrefLevel = 0
1167 01:02:47.122564 TX Bit0 (983~993) 11 988, Bit8 (970~982) 13 976,
1168 01:02:47.122614 TX Bit1 (981~994) 14 987, Bit9 (973~986) 14 979,
1169 01:02:47.122663 TX Bit2 (983~994) 12 988, Bit10 (978~988) 11 983,
1170 01:02:47.122712 TX Bit3 (978~990) 13 984, Bit11 (972~983) 12 977,
1171 01:02:47.122761 TX Bit4 (981~994) 14 987, Bit12 (973~986) 14 979,
1172 01:02:47.122813 TX Bit5 (980~989) 10 984, Bit13 (973~985) 13 979,
1173 01:02:47.122862 TX Bit6 (980~992) 13 986, Bit14 (974~988) 15 981,
1174 01:02:47.122911 TX Bit7 (981~994) 14 987, Bit15 (978~989) 12 983,
1175 01:02:47.122959
1176 01:02:47.123006 Write Rank0 MR14 =0x2
1177 01:02:47.123062
1178 01:02:47.123335 CH=0, VrefRange= 0, VrefLevel = 2
1179 01:02:47.123417 TX Bit0 (983~994) 12 988, Bit8 (970~983) 14 976,
1180 01:02:47.123495 TX Bit1 (982~995) 14 988, Bit9 (972~986) 15 979,
1181 01:02:47.123591 TX Bit2 (983~995) 13 989, Bit10 (978~989) 12 983,
1182 01:02:47.123714 TX Bit3 (978~991) 14 984, Bit11 (971~984) 14 977,
1183 01:02:47.123791 TX Bit4 (981~994) 14 987, Bit12 (972~986) 15 979,
1184 01:02:47.123870 TX Bit5 (980~991) 12 985, Bit13 (973~985) 13 979,
1185 01:02:47.123948 TX Bit6 (980~993) 14 986, Bit14 (974~988) 15 981,
1186 01:02:47.124026 TX Bit7 (980~995) 16 987, Bit15 (978~990) 13 984,
1187 01:02:47.124102
1188 01:02:47.124179 Write Rank0 MR14 =0x4
1189 01:02:47.124254
1190 01:02:47.124330 CH=0, VrefRange= 0, VrefLevel = 4
1191 01:02:47.124409 TX Bit0 (983~994) 12 988, Bit8 (969~984) 16 976,
1192 01:02:47.124487 TX Bit1 (981~996) 16 988, Bit9 (972~988) 17 980,
1193 01:02:47.124564 TX Bit2 (983~996) 14 989, Bit10 (977~989) 13 983,
1194 01:02:47.124641 TX Bit3 (978~992) 15 985, Bit11 (971~985) 15 978,
1195 01:02:47.124719 TX Bit4 (980~995) 16 987, Bit12 (971~987) 17 979,
1196 01:02:47.124796 TX Bit5 (980~991) 12 985, Bit13 (972~986) 15 979,
1197 01:02:47.124874 TX Bit6 (980~993) 14 986, Bit14 (973~988) 16 980,
1198 01:02:47.124952 TX Bit7 (980~995) 16 987, Bit15 (977~991) 15 984,
1199 01:02:47.125033
1200 01:02:47.125151 Write Rank0 MR14 =0x6
1201 01:02:47.125212
1202 01:02:47.125262 CH=0, VrefRange= 0, VrefLevel = 6
1203 01:02:47.125311 TX Bit0 (983~995) 13 989, Bit8 (969~985) 17 977,
1204 01:02:47.125361 TX Bit1 (981~996) 16 988, Bit9 (972~988) 17 980,
1205 01:02:47.125410 TX Bit2 (982~996) 15 989, Bit10 (977~990) 14 983,
1206 01:02:47.125487 TX Bit3 (978~992) 15 985, Bit11 (971~986) 16 978,
1207 01:02:47.125565 TX Bit4 (980~996) 17 988, Bit12 (972~987) 16 979,
1208 01:02:47.125642 TX Bit5 (980~992) 13 986, Bit13 (972~987) 16 979,
1209 01:02:47.125721 TX Bit6 (980~993) 14 986, Bit14 (973~989) 17 981,
1210 01:02:47.125798 TX Bit7 (980~996) 17 988, Bit15 (977~991) 15 984,
1211 01:02:47.125874
1212 01:02:47.125952 Write Rank0 MR14 =0x8
1213 01:02:47.126054
1214 01:02:47.126105 CH=0, VrefRange= 0, VrefLevel = 8
1215 01:02:47.126154 TX Bit0 (981~996) 16 988, Bit8 (969~985) 17 977,
1216 01:02:47.126206 TX Bit1 (980~997) 18 988, Bit9 (971~988) 18 979,
1217 01:02:47.126256 TX Bit2 (982~997) 16 989, Bit10 (977~991) 15 984,
1218 01:02:47.126305 TX Bit3 (978~992) 15 985, Bit11 (970~986) 17 978,
1219 01:02:47.126354 TX Bit4 (980~996) 17 988, Bit12 (971~988) 18 979,
1220 01:02:47.126403 TX Bit5 (980~992) 13 986, Bit13 (971~988) 18 979,
1221 01:02:47.126451 TX Bit6 (979~994) 16 986, Bit14 (973~989) 17 981,
1222 01:02:47.126505 TX Bit7 (980~997) 18 988, Bit15 (976~991) 16 983,
1223 01:02:47.126554
1224 01:02:47.126603 Write Rank0 MR14 =0xa
1225 01:02:47.126650
1226 01:02:47.126698 CH=0, VrefRange= 0, VrefLevel = 10
1227 01:02:47.126748 TX Bit0 (982~997) 16 989, Bit8 (969~986) 18 977,
1228 01:02:47.126801 TX Bit1 (980~997) 18 988, Bit9 (971~989) 19 980,
1229 01:02:47.126850 TX Bit2 (981~998) 18 989, Bit10 (976~991) 16 983,
1230 01:02:47.126901 TX Bit3 (977~993) 17 985, Bit11 (969~987) 19 978,
1231 01:02:47.126950 TX Bit4 (980~997) 18 988, Bit12 (970~988) 19 979,
1232 01:02:47.126999 TX Bit5 (979~993) 15 986, Bit13 (971~988) 18 979,
1233 01:02:47.127133 TX Bit6 (979~994) 16 986, Bit14 (972~990) 19 981,
1234 01:02:47.127292 TX Bit7 (980~997) 18 988, Bit15 (975~992) 18 983,
1235 01:02:47.127387
1236 01:02:47.127473 Write Rank0 MR14 =0xc
1237 01:02:47.127552
1238 01:02:47.127631 CH=0, VrefRange= 0, VrefLevel = 12
1239 01:02:47.127711 TX Bit0 (982~997) 16 989, Bit8 (968~987) 20 977,
1240 01:02:47.127790 TX Bit1 (980~999) 20 989, Bit9 (971~989) 19 980,
1241 01:02:47.127868 TX Bit2 (981~999) 19 990, Bit10 (975~992) 18 983,
1242 01:02:47.127946 TX Bit3 (977~993) 17 985, Bit11 (969~987) 19 978,
1243 01:02:47.128023 TX Bit4 (980~998) 19 989, Bit12 (970~989) 20 979,
1244 01:02:47.128102 TX Bit5 (979~993) 15 986, Bit13 (970~989) 20 979,
1245 01:02:47.128180 TX Bit6 (979~995) 17 987, Bit14 (971~990) 20 980,
1246 01:02:47.128257 TX Bit7 (980~998) 19 989, Bit15 (976~992) 17 984,
1247 01:02:47.128334
1248 01:02:47.128410 Write Rank0 MR14 =0xe
1249 01:02:47.128485
1250 01:02:47.128562 CH=0, VrefRange= 0, VrefLevel = 14
1251 01:02:47.128640 TX Bit0 (981~998) 18 989, Bit8 (968~987) 20 977,
1252 01:02:47.128717 TX Bit1 (979~999) 21 989, Bit9 (970~989) 20 979,
1253 01:02:47.128795 TX Bit2 (980~1000) 21 990, Bit10 (975~992) 18 983,
1254 01:02:47.128873 TX Bit3 (977~993) 17 985, Bit11 (969~988) 20 978,
1255 01:02:47.128951 TX Bit4 (979~998) 20 988, Bit12 (969~989) 21 979,
1256 01:02:47.129035 TX Bit5 (979~994) 16 986, Bit13 (970~989) 20 979,
1257 01:02:47.129127 TX Bit6 (979~996) 18 987, Bit14 (972~991) 20 981,
1258 01:02:47.129177 TX Bit7 (979~998) 20 988, Bit15 (975~993) 19 984,
1259 01:02:47.129226
1260 01:02:47.129278 Write Rank0 MR14 =0x10
1261 01:02:47.129354
1262 01:02:47.129430 CH=0, VrefRange= 0, VrefLevel = 16
1263 01:02:47.129516 TX Bit0 (980~999) 20 989, Bit8 (968~988) 21 978,
1264 01:02:47.129597 TX Bit1 (980~1000) 21 990, Bit9 (969~990) 22 979,
1265 01:02:47.129688 TX Bit2 (980~1000) 21 990, Bit10 (975~994) 20 984,
1266 01:02:47.129769 TX Bit3 (977~994) 18 985, Bit11 (968~988) 21 978,
1267 01:02:47.129847 TX Bit4 (979~1000) 22 989, Bit12 (969~990) 22 979,
1268 01:02:47.129925 TX Bit5 (979~994) 16 986, Bit13 (969~989) 21 979,
1269 01:02:47.130036 TX Bit6 (979~996) 18 987, Bit14 (971~991) 21 981,
1270 01:02:47.130122 TX Bit7 (979~999) 21 989, Bit15 (974~994) 21 984,
1271 01:02:47.130201
1272 01:02:47.130278 Write Rank0 MR14 =0x12
1273 01:02:47.130355
1274 01:02:47.130431 CH=0, VrefRange= 0, VrefLevel = 18
1275 01:02:47.130514 TX Bit0 (980~999) 20 989, Bit8 (968~988) 21 978,
1276 01:02:47.130604 TX Bit1 (980~1000) 21 990, Bit9 (969~990) 22 979,
1277 01:02:47.130683 TX Bit2 (980~1001) 22 990, Bit10 (974~994) 21 984,
1278 01:02:47.130957 TX Bit3 (976~994) 19 985, Bit11 (968~989) 22 978,
1279 01:02:47.131099 TX Bit4 (979~1000) 22 989, Bit12 (969~990) 22 979,
1280 01:02:47.131210 TX Bit5 (979~995) 17 987, Bit13 (969~990) 22 979,
1281 01:02:47.131295 TX Bit6 (979~996) 18 987, Bit14 (971~992) 22 981,
1282 01:02:47.131371 TX Bit7 (979~1000) 22 989, Bit15 (974~995) 22 984,
1283 01:02:47.131422
1284 01:02:47.131493 Write Rank0 MR14 =0x14
1285 01:02:47.131569
1286 01:02:47.131645 CH=0, VrefRange= 0, VrefLevel = 20
1287 01:02:47.131722 TX Bit0 (980~1000) 21 990, Bit8 (967~989) 23 978,
1288 01:02:47.131793 TX Bit1 (979~1001) 23 990, Bit9 (969~991) 23 980,
1289 01:02:47.131846 TX Bit2 (980~1001) 22 990, Bit10 (974~995) 22 984,
1290 01:02:47.131897 TX Bit3 (976~994) 19 985, Bit11 (968~989) 22 978,
1291 01:02:47.131947 TX Bit4 (979~1001) 23 990, Bit12 (969~990) 22 979,
1292 01:02:47.131996 TX Bit5 (978~995) 18 986, Bit13 (969~990) 22 979,
1293 01:02:47.132045 TX Bit6 (978~998) 21 988, Bit14 (970~992) 23 981,
1294 01:02:47.132097 TX Bit7 (979~1001) 23 990, Bit15 (974~995) 22 984,
1295 01:02:47.132146
1296 01:02:47.132194 Write Rank0 MR14 =0x16
1297 01:02:47.132248
1298 01:02:47.132372 CH=0, VrefRange= 0, VrefLevel = 22
1299 01:02:47.132500 TX Bit0 (980~1001) 22 990, Bit8 (967~989) 23 978,
1300 01:02:47.132580 TX Bit1 (979~1001) 23 990, Bit9 (968~991) 24 979,
1301 01:02:47.132658 TX Bit2 (980~1002) 23 991, Bit10 (974~995) 22 984,
1302 01:02:47.132735 TX Bit3 (976~995) 20 985, Bit11 (968~989) 22 978,
1303 01:02:47.132809 TX Bit4 (979~1001) 23 990, Bit12 (968~991) 24 979,
1304 01:02:47.132860 TX Bit5 (978~996) 19 987, Bit13 (968~991) 24 979,
1305 01:02:47.132910 TX Bit6 (978~998) 21 988, Bit14 (969~992) 24 980,
1306 01:02:47.132959 TX Bit7 (979~1001) 23 990, Bit15 (975~995) 21 985,
1307 01:02:47.133008
1308 01:02:47.133064 Write Rank0 MR14 =0x18
1309 01:02:47.133127
1310 01:02:47.133203 CH=0, VrefRange= 0, VrefLevel = 24
1311 01:02:47.133280 TX Bit0 (980~1002) 23 991, Bit8 (967~989) 23 978,
1312 01:02:47.133359 TX Bit1 (979~1002) 24 990, Bit9 (968~991) 24 979,
1313 01:02:47.133437 TX Bit2 (980~1003) 24 991, Bit10 (973~995) 23 984,
1314 01:02:47.133514 TX Bit3 (976~995) 20 985, Bit11 (968~990) 23 979,
1315 01:02:47.133591 TX Bit4 (979~1002) 24 990, Bit12 (968~991) 24 979,
1316 01:02:47.133670 TX Bit5 (978~996) 19 987, Bit13 (968~991) 24 979,
1317 01:02:47.133748 TX Bit6 (978~999) 22 988, Bit14 (969~993) 25 981,
1318 01:02:47.133826 TX Bit7 (979~1002) 24 990, Bit15 (974~996) 23 985,
1319 01:02:47.133901
1320 01:02:47.134004 Write Rank0 MR14 =0x1a
1321 01:02:47.134077
1322 01:02:47.134126 CH=0, VrefRange= 0, VrefLevel = 26
1323 01:02:47.134175 TX Bit0 (979~1002) 24 990, Bit8 (967~990) 24 978,
1324 01:02:47.134224 TX Bit1 (979~1002) 24 990, Bit9 (968~991) 24 979,
1325 01:02:47.134273 TX Bit2 (979~1003) 25 991, Bit10 (973~996) 24 984,
1326 01:02:47.134326 TX Bit3 (975~995) 21 985, Bit11 (967~990) 24 978,
1327 01:02:47.134380 TX Bit4 (979~1002) 24 990, Bit12 (968~992) 25 980,
1328 01:02:47.134458 TX Bit5 (978~997) 20 987, Bit13 (968~991) 24 979,
1329 01:02:47.134535 TX Bit6 (978~999) 22 988, Bit14 (969~994) 26 981,
1330 01:02:47.134612 TX Bit7 (979~1002) 24 990, Bit15 (974~996) 23 985,
1331 01:02:47.134674
1332 01:02:47.134723 Write Rank0 MR14 =0x1c
1333 01:02:47.134772
1334 01:02:47.134819 CH=0, VrefRange= 0, VrefLevel = 28
1335 01:02:47.134868 TX Bit0 (979~1003) 25 991, Bit8 (966~990) 25 978,
1336 01:02:47.134917 TX Bit1 (979~1003) 25 991, Bit9 (968~991) 24 979,
1337 01:02:47.134967 TX Bit2 (979~1004) 26 991, Bit10 (973~996) 24 984,
1338 01:02:47.135027 TX Bit3 (975~996) 22 985, Bit11 (967~990) 24 978,
1339 01:02:47.135079 TX Bit4 (978~1003) 26 990, Bit12 (968~992) 25 980,
1340 01:02:47.135128 TX Bit5 (978~998) 21 988, Bit13 (968~992) 25 980,
1341 01:02:47.135178 TX Bit6 (978~999) 22 988, Bit14 (969~994) 26 981,
1342 01:02:47.135232 TX Bit7 (979~1003) 25 991, Bit15 (973~996) 24 984,
1343 01:02:47.135283
1344 01:02:47.135337 Write Rank0 MR14 =0x1e
1345 01:02:47.135386
1346 01:02:47.135434 CH=0, VrefRange= 0, VrefLevel = 30
1347 01:02:47.135482 TX Bit0 (979~1003) 25 991, Bit8 (966~989) 24 977,
1348 01:02:47.135532 TX Bit1 (979~1003) 25 991, Bit9 (968~991) 24 979,
1349 01:02:47.135588 TX Bit2 (980~1004) 25 992, Bit10 (973~996) 24 984,
1350 01:02:47.135668 TX Bit3 (974~996) 23 985, Bit11 (967~990) 24 978,
1351 01:02:47.135745 TX Bit4 (979~1003) 25 991, Bit12 (968~992) 25 980,
1352 01:02:47.135903 TX Bit5 (978~999) 22 988, Bit13 (968~992) 25 980,
1353 01:02:47.136009 TX Bit6 (978~1000) 23 989, Bit14 (968~993) 26 980,
1354 01:02:47.136098 TX Bit7 (979~1003) 25 991, Bit15 (972~996) 25 984,
1355 01:02:47.136179
1356 01:02:47.136255 Write Rank0 MR14 =0x20
1357 01:02:47.136331
1358 01:02:47.136409 CH=0, VrefRange= 0, VrefLevel = 32
1359 01:02:47.136486 TX Bit0 (979~1004) 26 991, Bit8 (967~989) 23 978,
1360 01:02:47.136564 TX Bit1 (979~1003) 25 991, Bit9 (968~990) 23 979,
1361 01:02:47.136640 TX Bit2 (979~1005) 27 992, Bit10 (973~996) 24 984,
1362 01:02:47.136737 TX Bit3 (974~996) 23 985, Bit11 (967~990) 24 978,
1363 01:02:47.136828 TX Bit4 (979~1003) 25 991, Bit12 (968~992) 25 980,
1364 01:02:47.136904 TX Bit5 (977~999) 23 988, Bit13 (968~992) 25 980,
1365 01:02:47.136983 TX Bit6 (978~1000) 23 989, Bit14 (968~992) 25 980,
1366 01:02:47.137049 TX Bit7 (979~1002) 24 990, Bit15 (973~996) 24 984,
1367 01:02:47.137098
1368 01:02:47.137146 Write Rank0 MR14 =0x22
1369 01:02:47.137197
1370 01:02:47.137264 CH=0, VrefRange= 0, VrefLevel = 34
1371 01:02:47.137341 TX Bit0 (979~1004) 26 991, Bit8 (967~989) 23 978,
1372 01:02:47.137420 TX Bit1 (979~1003) 25 991, Bit9 (968~990) 23 979,
1373 01:02:47.137497 TX Bit2 (979~1005) 27 992, Bit10 (973~996) 24 984,
1374 01:02:47.137574 TX Bit3 (974~996) 23 985, Bit11 (967~990) 24 978,
1375 01:02:47.137653 TX Bit4 (979~1003) 25 991, Bit12 (968~992) 25 980,
1376 01:02:47.137731 TX Bit5 (977~999) 23 988, Bit13 (968~992) 25 980,
1377 01:02:47.138040 TX Bit6 (978~1000) 23 989, Bit14 (968~992) 25 980,
1378 01:02:47.138100 TX Bit7 (979~1002) 24 990, Bit15 (973~996) 24 984,
1379 01:02:47.138151
1380 01:02:47.138204 Write Rank0 MR14 =0x24
1381 01:02:47.138257
1382 01:02:47.138305 CH=0, VrefRange= 0, VrefLevel = 36
1383 01:02:47.138354 TX Bit0 (979~1004) 26 991, Bit8 (967~989) 23 978,
1384 01:02:47.138406 TX Bit1 (979~1003) 25 991, Bit9 (968~990) 23 979,
1385 01:02:47.138486 TX Bit2 (979~1005) 27 992, Bit10 (973~996) 24 984,
1386 01:02:47.138563 TX Bit3 (974~996) 23 985, Bit11 (967~990) 24 978,
1387 01:02:47.138642 TX Bit4 (979~1003) 25 991, Bit12 (968~992) 25 980,
1388 01:02:47.138721 TX Bit5 (977~999) 23 988, Bit13 (968~992) 25 980,
1389 01:02:47.138798 TX Bit6 (978~1000) 23 989, Bit14 (968~992) 25 980,
1390 01:02:47.138877 TX Bit7 (979~1002) 24 990, Bit15 (973~996) 24 984,
1391 01:02:47.138953
1392 01:02:47.139028 Write Rank0 MR14 =0x26
1393 01:02:47.139107
1394 01:02:47.139184 CH=0, VrefRange= 0, VrefLevel = 38
1395 01:02:47.139261 TX Bit0 (979~1004) 26 991, Bit8 (967~989) 23 978,
1396 01:02:47.139338 TX Bit1 (979~1003) 25 991, Bit9 (968~990) 23 979,
1397 01:02:47.139417 TX Bit2 (979~1005) 27 992, Bit10 (973~996) 24 984,
1398 01:02:47.139494 TX Bit3 (974~996) 23 985, Bit11 (967~990) 24 978,
1399 01:02:47.139571 TX Bit4 (979~1003) 25 991, Bit12 (968~992) 25 980,
1400 01:02:47.139648 TX Bit5 (977~999) 23 988, Bit13 (968~992) 25 980,
1401 01:02:47.139726 TX Bit6 (978~1000) 23 989, Bit14 (968~992) 25 980,
1402 01:02:47.139805 TX Bit7 (979~1002) 24 990, Bit15 (973~996) 24 984,
1403 01:02:47.139880
1404 01:02:47.139954
1405 01:02:47.140031 TX Vref found, early break! 368< 369
1406 01:02:47.140108 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =844/100 ps
1407 01:02:47.140184 u1DelayCellOfst[0]=6 cells (6 PI)
1408 01:02:47.140259 u1DelayCellOfst[1]=6 cells (6 PI)
1409 01:02:47.140338 u1DelayCellOfst[2]=8 cells (7 PI)
1410 01:02:47.140414 u1DelayCellOfst[3]=0 cells (0 PI)
1411 01:02:47.140489 u1DelayCellOfst[4]=6 cells (6 PI)
1412 01:02:47.140566 u1DelayCellOfst[5]=3 cells (3 PI)
1413 01:02:47.140641 u1DelayCellOfst[6]=4 cells (4 PI)
1414 01:02:47.140717 u1DelayCellOfst[7]=5 cells (5 PI)
1415 01:02:47.140792 Byte0, DQ PI dly=985, DQM PI dly= 988
1416 01:02:47.140869 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
1417 01:02:47.140946
1418 01:02:47.141025 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
1419 01:02:47.141179
1420 01:02:47.141321 u1DelayCellOfst[8]=0 cells (0 PI)
1421 01:02:47.141456 u1DelayCellOfst[9]=1 cells (1 PI)
1422 01:02:47.141591 u1DelayCellOfst[10]=6 cells (6 PI)
1423 01:02:47.141669 u1DelayCellOfst[11]=0 cells (0 PI)
1424 01:02:47.141762 u1DelayCellOfst[12]=2 cells (2 PI)
1425 01:02:47.141853 u1DelayCellOfst[13]=2 cells (2 PI)
1426 01:02:47.141929 u1DelayCellOfst[14]=2 cells (2 PI)
1427 01:02:47.142040 u1DelayCellOfst[15]=6 cells (6 PI)
1428 01:02:47.142095 Byte1, DQ PI dly=978, DQM PI dly= 981
1429 01:02:47.142145 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1430 01:02:47.142196
1431 01:02:47.142245 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1432 01:02:47.142293
1433 01:02:47.142340 Write Rank0 MR14 =0x20
1434 01:02:47.142390
1435 01:02:47.142437 Final TX Range 0 Vref 32
1436 01:02:47.142486
1437 01:02:47.142535 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1438 01:02:47.142584
1439 01:02:47.142631 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1440 01:02:47.142687 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1441 01:02:47.142768 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1442 01:02:47.142849 Write Rank0 MR3 =0xb0
1443 01:02:47.142932 DramC Write-DBI on
1444 01:02:47.143009 ==
1445 01:02:47.143085 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1446 01:02:47.143164 fsp= 1, odt_onoff= 1, Byte mode= 0
1447 01:02:47.143239 ==
1448 01:02:47.143317 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1449 01:02:47.143392
1450 01:02:47.143468 Begin, DQ Scan Range 701~765
1451 01:02:47.143546
1452 01:02:47.143621
1453 01:02:47.143696 TX Vref Scan disable
1454 01:02:47.143771 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1455 01:02:47.143852 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1456 01:02:47.143931 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1457 01:02:47.144009 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1458 01:02:47.144089 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1459 01:02:47.144169 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1460 01:02:47.144248 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1461 01:02:47.144326 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1462 01:02:47.144406 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1463 01:02:47.144485 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1464 01:02:47.144564 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1465 01:02:47.144642 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1466 01:02:47.144722 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1467 01:02:47.144802 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1468 01:02:47.144881 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1469 01:02:47.144959 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1470 01:02:47.145039 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1471 01:02:47.145117 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1472 01:02:47.145196 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1473 01:02:47.145274 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
1474 01:02:47.145331 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
1475 01:02:47.145409 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1476 01:02:47.145487 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1477 01:02:47.145571 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1478 01:02:47.145652 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1479 01:02:47.145768 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1480 01:02:47.145849 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1481 01:02:47.145928 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1482 01:02:47.146051 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1483 01:02:47.146122 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1484 01:02:47.146172 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
1485 01:02:47.146221 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
1486 01:02:47.146270 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
1487 01:02:47.146319 749 |2 6 45|[0] xxxxxxxx xxxxxxxx [MSB]
1488 01:02:47.146370 Byte0, DQ PI dly=735, DQM PI dly= 735
1489 01:02:47.146614 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 31)
1490 01:02:47.146673
1491 01:02:47.146723 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 31)
1492 01:02:47.146772
1493 01:02:47.146820 Byte1, DQ PI dly=724, DQM PI dly= 724
1494 01:02:47.146869 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
1495 01:02:47.146939
1496 01:02:47.147014 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
1497 01:02:47.147092
1498 01:02:47.147169 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1499 01:02:47.147247 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1500 01:02:47.147327 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1501 01:02:47.147403 Write Rank0 MR3 =0x30
1502 01:02:47.147478 DramC Write-DBI off
1503 01:02:47.147563
1504 01:02:47.147644 [DATLAT]
1505 01:02:47.147720 Freq=1600, CH0 RK0, use_rxtx_scan=0
1506 01:02:47.147808
1507 01:02:47.147890 DATLAT Default: 0xf
1508 01:02:47.147979 7, 0xFFFF, sum=0
1509 01:02:47.148058 8, 0xFFFF, sum=0
1510 01:02:47.148138 9, 0xFFFF, sum=0
1511 01:02:47.148217 10, 0xFFFF, sum=0
1512 01:02:47.148295 11, 0xFFFF, sum=0
1513 01:02:47.148375 12, 0xFFFF, sum=0
1514 01:02:47.148455 13, 0xFFFF, sum=0
1515 01:02:47.148532 14, 0x0, sum=1
1516 01:02:47.148610 15, 0x0, sum=2
1517 01:02:47.148689 16, 0x0, sum=3
1518 01:02:47.148769 17, 0x0, sum=4
1519 01:02:47.148856 pattern=2 first_step=14 total pass=5 best_step=16
1520 01:02:47.148975 ==
1521 01:02:47.149053 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1522 01:02:47.149124 fsp= 1, odt_onoff= 1, Byte mode= 0
1523 01:02:47.149178 ==
1524 01:02:47.149227 Start DQ dly to find pass range UseTestEngine =1
1525 01:02:47.149356 x-axis: bit #, y-axis: DQ dly (-127~63)
1526 01:02:47.149488 RX Vref Scan = 1
1527 01:02:47.149578
1528 01:02:47.149665 RX Vref found, early break!
1529 01:02:47.149751
1530 01:02:47.149836 Final RX Vref 12, apply to both rank0 and 1
1531 01:02:47.149913 ==
1532 01:02:47.150026 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1533 01:02:47.150107 fsp= 1, odt_onoff= 1, Byte mode= 0
1534 01:02:47.150186 ==
1535 01:02:47.150262 DQS Delay:
1536 01:02:47.150340 DQS0 = 0, DQS1 = 0
1537 01:02:47.150416 DQM Delay:
1538 01:02:47.150491 DQM0 = 21, DQM1 = 20
1539 01:02:47.150568 DQ Delay:
1540 01:02:47.150644 DQ0 =23, DQ1 =22, DQ2 =24, DQ3 =17
1541 01:02:47.150726 DQ4 =23, DQ5 =19, DQ6 =20, DQ7 =23
1542 01:02:47.150808 DQ8 =17, DQ9 =18, DQ10 =25, DQ11 =18
1543 01:02:47.150887 DQ12 =20, DQ13 =19, DQ14 =21, DQ15 =23
1544 01:02:47.150964
1545 01:02:47.151039
1546 01:02:47.151113
1547 01:02:47.151190 [DramC_TX_OE_Calibration] TA2
1548 01:02:47.151266 Original DQ_B0 (3 6) =30, OEN = 27
1549 01:02:47.151343 Original DQ_B1 (3 6) =30, OEN = 27
1550 01:02:47.151419 23, 0x0, End_B0=23 End_B1=23
1551 01:02:47.151500 24, 0x0, End_B0=24 End_B1=24
1552 01:02:47.151578 25, 0x0, End_B0=25 End_B1=25
1553 01:02:47.151656 26, 0x0, End_B0=26 End_B1=26
1554 01:02:47.151735 27, 0x0, End_B0=27 End_B1=27
1555 01:02:47.151815 28, 0x0, End_B0=28 End_B1=28
1556 01:02:47.151907 29, 0x0, End_B0=29 End_B1=29
1557 01:02:47.151986 30, 0x0, End_B0=30 End_B1=30
1558 01:02:47.152067 31, 0xFFFF, End_B0=30 End_B1=30
1559 01:02:47.152148 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1560 01:02:47.152225 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1561 01:02:47.152300
1562 01:02:47.152375
1563 01:02:47.152451 Write Rank0 MR23 =0x3f
1564 01:02:47.152526 [DQSOSC]
1565 01:02:47.152604 [DQSOSCAuto] RK0, (LSB)MR18= 0xcccc, (MSB)MR19= 0x202, tDQSOscB0 = 439 ps tDQSOscB1 = 439 ps
1566 01:02:47.152686 CH0_RK0: MR19=0x202, MR18=0xCCCC, DQSOSC=439, MR23=63, INC=12, DEC=19
1567 01:02:47.152763 Write Rank0 MR23 =0x3f
1568 01:02:47.152838 [DQSOSC]
1569 01:02:47.152917 [DQSOSCAuto] RK0, (LSB)MR18= 0xcccc, (MSB)MR19= 0x202, tDQSOscB0 = 439 ps tDQSOscB1 = 439 ps
1570 01:02:47.153005 CH0 RK0: MR19=202, MR18=CCCC
1571 01:02:47.153082 [RankSwap] Rank num 2, (Multi 1), Rank 1
1572 01:02:47.153158 Write Rank0 MR2 =0xad
1573 01:02:47.153218 [Write Leveling]
1574 01:02:47.153281 delay byte0 byte1 byte2 byte3
1575 01:02:47.153356
1576 01:02:47.153432 10 0 0
1577 01:02:47.153520 11 0 0
1578 01:02:47.153600 12 0 0
1579 01:02:47.153690 13 0 0
1580 01:02:47.153771 14 0 0
1581 01:02:47.153863 15 0 0
1582 01:02:47.153947 16 0 0
1583 01:02:47.154072 17 0 0
1584 01:02:47.154150 18 0 0
1585 01:02:47.154231 19 0 0
1586 01:02:47.154287 20 0 0
1587 01:02:47.154356 21 0 0
1588 01:02:47.154434 22 0 ff
1589 01:02:47.154512 23 0 ff
1590 01:02:47.154591 24 0 ff
1591 01:02:47.154684 25 0 ff
1592 01:02:47.154763 26 0 ff
1593 01:02:47.154842 27 0 ff
1594 01:02:47.154920 28 0 ff
1595 01:02:47.154997 29 0 ff
1596 01:02:47.155077 30 ff ff
1597 01:02:47.155159 31 ff ff
1598 01:02:47.155239 32 ff ff
1599 01:02:47.155317 33 ff ff
1600 01:02:47.155395 34 ff ff
1601 01:02:47.155472 35 ff ff
1602 01:02:47.155551 36 ff ff
1603 01:02:47.155631 pass bytecount = 0xff (0xff: all bytes pass)
1604 01:02:47.155720
1605 01:02:47.155797 DQS0 dly: 30
1606 01:02:47.155875 DQS1 dly: 22
1607 01:02:47.155950 Write Rank0 MR2 =0x2d
1608 01:02:47.156027 [RankSwap] Rank num 2, (Multi 1), Rank 0
1609 01:02:47.156102 Write Rank1 MR1 =0xd6
1610 01:02:47.156180 [Gating]
1611 01:02:47.156255 ==
1612 01:02:47.156332 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1613 01:02:47.156410 fsp= 1, odt_onoff= 1, Byte mode= 0
1614 01:02:47.156486 ==
1615 01:02:47.156563 3 1 0 |3534 1414 |(11 11)(11 11) |(0 0)(1 1)| 0
1616 01:02:47.156642 3 1 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1617 01:02:47.156722 3 1 8 |3534 3535 |(11 11)(0 0) |(0 0)(0 0)| 0
1618 01:02:47.156802 3 1 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1619 01:02:47.156881 3 1 16 |3534 3332 |(11 11)(11 11) |(1 1)(1 1)| 0
1620 01:02:47.156960 3 1 20 |3534 3535 |(11 11)(0 0) |(0 0)(1 1)| 0
1621 01:02:47.157041 3 1 24 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1622 01:02:47.157119 [Byte 1] Lead/lag Transition tap number (1)
1623 01:02:47.157195 3 1 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1624 01:02:47.157274 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1625 01:02:47.157356 3 2 4 |3534 3534 |(11 11)(11 11) |(0 0)(1 0)| 0
1626 01:02:47.157435 3 2 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
1627 01:02:47.157520 3 2 12 |3534 3434 |(11 11)(11 11) |(0 1)(0 1)| 0
1628 01:02:47.157608 3 2 16 |1413 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1629 01:02:47.157695 3 2 20 |3d3d 403 |(11 11)(11 11) |(1 1)(0 0)| 0
1630 01:02:47.157775 3 2 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1631 01:02:47.157853 3 2 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1632 01:02:47.157935 3 3 0 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
1633 01:02:47.158252 3 3 4 |3d3d 3c3c |(11 11)(10 10) |(1 1)(0 0)| 0
1634 01:02:47.158336 3 3 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1635 01:02:47.158461 3 3 12 |3d3d 3d3d |(11 11)(0 0) |(1 1)(0 0)| 0
1636 01:02:47.158545 3 3 16 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
1637 01:02:47.158624 3 3 20 |202 2726 |(11 11)(11 11) |(1 1)(1 1)| 0
1638 01:02:47.158703 3 3 24 |3534 3231 |(11 11)(11 11) |(1 1)(1 1)| 0
1639 01:02:47.158784 [Byte 0] Lead/lag Transition tap number (1)
1640 01:02:47.158861 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1641 01:02:47.158913 [Byte 1] Lead/lag Transition tap number (1)
1642 01:02:47.158962 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1643 01:02:47.159011 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1644 01:02:47.159064 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1645 01:02:47.159132 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1646 01:02:47.159211 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1647 01:02:47.159289 3 4 20 |403 1a19 |(11 11)(11 11) |(1 1)(0 1)| 0
1648 01:02:47.159370 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1649 01:02:47.159462 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1650 01:02:47.159542 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1651 01:02:47.159623 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1652 01:02:47.159704 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1653 01:02:47.159783 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1654 01:02:47.159861 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1655 01:02:47.159941 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1656 01:02:47.160019 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1657 01:02:47.160097 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1658 01:02:47.160185 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1659 01:02:47.160270 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1660 01:02:47.160349 [Byte 0] Lead/lag falling Transition (3, 6, 4)
1661 01:02:47.160425 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1662 01:02:47.160506 [Byte 1] Lead/lag falling Transition (3, 6, 8)
1663 01:02:47.160596 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1664 01:02:47.160676 3 6 16 |3e3d 3e3d |(11 11)(11 11) |(1 0)(1 0)| 0
1665 01:02:47.160755 [Byte 0] Lead/lag Transition tap number (4)
1666 01:02:47.160833 [Byte 1] Lead/lag Transition tap number (3)
1667 01:02:47.160909 3 6 20 |e0e 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
1668 01:02:47.160987 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1669 01:02:47.161063 [Byte 0]First pass (3, 6, 24)
1670 01:02:47.161115 [Byte 1]First pass (3, 6, 24)
1671 01:02:47.161164 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1672 01:02:47.161213 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1673 01:02:47.161262 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1674 01:02:47.161318 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1675 01:02:47.161410 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1676 01:02:47.161489 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1677 01:02:47.161568 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1678 01:02:47.161648 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1679 01:02:47.161726 All bytes gating window > 1UI, Early break!
1680 01:02:47.161801
1681 01:02:47.161877 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
1682 01:02:47.161955
1683 01:02:47.162057 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 14)
1684 01:02:47.162106
1685 01:02:47.162157
1686 01:02:47.162205
1687 01:02:47.162252 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
1688 01:02:47.162300
1689 01:02:47.162348 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
1690 01:02:47.162428
1691 01:02:47.162482
1692 01:02:47.162530 Write Rank1 MR1 =0x56
1693 01:02:47.162578
1694 01:02:47.162625 best RODT dly(2T, 0.5T) = (2, 3)
1695 01:02:47.162702
1696 01:02:47.162779 best RODT dly(2T, 0.5T) = (2, 3)
1697 01:02:47.162864 ==
1698 01:02:47.163022 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1699 01:02:47.163117 fsp= 1, odt_onoff= 1, Byte mode= 0
1700 01:02:47.163207 ==
1701 01:02:47.163286 Start DQ dly to find pass range UseTestEngine =0
1702 01:02:47.163377 x-axis: bit #, y-axis: DQ dly (-127~63)
1703 01:02:47.163457 RX Vref Scan = 0
1704 01:02:47.163533 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1705 01:02:47.163611 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1706 01:02:47.163690 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1707 01:02:47.163770 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1708 01:02:47.163860 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1709 01:02:47.163944 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1710 01:02:47.164024 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1711 01:02:47.164103 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1712 01:02:47.164186 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1713 01:02:47.164265 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1714 01:02:47.164353 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1715 01:02:47.164434 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1716 01:02:47.164513 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1717 01:02:47.164592 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1718 01:02:47.164670 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1719 01:02:47.164750 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1720 01:02:47.164828 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1721 01:02:47.164907 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1722 01:02:47.164985 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1723 01:02:47.165065 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1724 01:02:47.165121 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1725 01:02:47.165199 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1726 01:02:47.165276 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1727 01:02:47.165357 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1728 01:02:47.165435 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1729 01:02:47.165524 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1730 01:02:47.165607 0, [0] xxxxxxxx xxxxxxxx [MSB]
1731 01:02:47.165686 1, [0] xxxoxxxx oxxxxxxx [MSB]
1732 01:02:47.165764 2, [0] xxxoxxxx oxxxxxxx [MSB]
1733 01:02:47.165841 3, [0] xxxoxoxx oxxoxxxx [MSB]
1734 01:02:47.165921 4, [0] xxxoxoxx oxxoxxxx [MSB]
1735 01:02:47.166017 5, [0] xxxoxooo ooxooxxx [MSB]
1736 01:02:47.166109 6, [0] xxxoxooo ooxooxxx [MSB]
1737 01:02:47.166161 7, [0] xoxooooo ooxoooox [MSB]
1738 01:02:47.166238 8, [0] xoxooooo ooxoooox [MSB]
1739 01:02:47.166316 9, [0] oooooooo ooxooooo [MSB]
1740 01:02:47.166393 10, [0] oooooooo ooxooooo [MSB]
1741 01:02:47.166471 32, [0] oooooooo oooooooo [MSB]
1742 01:02:47.166550 33, [0] oooxoooo xooooooo [MSB]
1743 01:02:47.166628 34, [0] oooxoooo xooooooo [MSB]
1744 01:02:47.166705 35, [0] oooxoooo xooxoooo [MSB]
1745 01:02:47.166979 36, [0] oooxooxo xxoxxooo [MSB]
1746 01:02:47.167040 37, [0] oooxoxxo xxoxxxoo [MSB]
1747 01:02:47.167099 38, [0] oooxoxxo xxoxxxxo [MSB]
1748 01:02:47.167178 39, [0] oooxoxxx xxoxxxxo [MSB]
1749 01:02:47.167266 40, [0] oxoxxxxx xxoxxxxx [MSB]
1750 01:02:47.167384 41, [0] xxxxxxxx xxoxxxxx [MSB]
1751 01:02:47.167464 42, [0] xxxxxxxx xxoxxxxx [MSB]
1752 01:02:47.167554 43, [0] xxxxxxxx xxxxxxxx [MSB]
1753 01:02:47.167648 iDelay=43, Bit 0, Center 24 (9 ~ 40) 32
1754 01:02:47.167727 iDelay=43, Bit 1, Center 23 (7 ~ 39) 33
1755 01:02:47.167803 iDelay=43, Bit 2, Center 24 (9 ~ 40) 32
1756 01:02:47.167880 iDelay=43, Bit 3, Center 16 (1 ~ 32) 32
1757 01:02:47.167957 iDelay=43, Bit 4, Center 23 (7 ~ 39) 33
1758 01:02:47.168032 iDelay=43, Bit 5, Center 19 (3 ~ 36) 34
1759 01:02:47.168109 iDelay=43, Bit 6, Center 20 (5 ~ 35) 31
1760 01:02:47.168187 iDelay=43, Bit 7, Center 21 (5 ~ 38) 34
1761 01:02:47.168264 iDelay=43, Bit 8, Center 16 (1 ~ 32) 32
1762 01:02:47.168340 iDelay=43, Bit 9, Center 20 (5 ~ 35) 31
1763 01:02:47.168417 iDelay=43, Bit 10, Center 26 (11 ~ 42) 32
1764 01:02:47.168494 iDelay=43, Bit 11, Center 18 (3 ~ 34) 32
1765 01:02:47.168575 iDelay=43, Bit 12, Center 20 (5 ~ 35) 31
1766 01:02:47.168682 iDelay=43, Bit 13, Center 21 (7 ~ 36) 30
1767 01:02:47.168760 iDelay=43, Bit 14, Center 22 (7 ~ 37) 31
1768 01:02:47.168837 iDelay=43, Bit 15, Center 24 (9 ~ 39) 31
1769 01:02:47.168911 ==
1770 01:02:47.169048 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1771 01:02:47.169154 fsp= 1, odt_onoff= 1, Byte mode= 0
1772 01:02:47.169222 ==
1773 01:02:47.169272 DQS Delay:
1774 01:02:47.169320 DQS0 = 0, DQS1 = 0
1775 01:02:47.169368 DQM Delay:
1776 01:02:47.169416 DQM0 = 21, DQM1 = 20
1777 01:02:47.169472 DQ Delay:
1778 01:02:47.169548 DQ0 =24, DQ1 =23, DQ2 =24, DQ3 =16
1779 01:02:47.169624 DQ4 =23, DQ5 =19, DQ6 =20, DQ7 =21
1780 01:02:47.169700 DQ8 =16, DQ9 =20, DQ10 =26, DQ11 =18
1781 01:02:47.169778 DQ12 =20, DQ13 =21, DQ14 =22, DQ15 =24
1782 01:02:47.169853
1783 01:02:47.169928
1784 01:02:47.170036 DramC Write-DBI off
1785 01:02:47.170090 ==
1786 01:02:47.170138 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1787 01:02:47.170188 fsp= 1, odt_onoff= 1, Byte mode= 0
1788 01:02:47.170236 ==
1789 01:02:47.170284 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1790 01:02:47.170337
1791 01:02:47.170385 Begin, DQ Scan Range 918~1174
1792 01:02:47.170433
1793 01:02:47.170480
1794 01:02:47.170528 TX Vref Scan disable
1795 01:02:47.170576 918 |3 4 22|[0] xxxxxxxx xxxxxxxx [MSB]
1796 01:02:47.170628 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
1797 01:02:47.170678 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1798 01:02:47.170727 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1799 01:02:47.170775 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1800 01:02:47.170823 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1801 01:02:47.170875 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1802 01:02:47.170925 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1803 01:02:47.170974 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1804 01:02:47.171023 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1805 01:02:47.171071 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1806 01:02:47.171120 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1807 01:02:47.171171 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1808 01:02:47.171222 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1809 01:02:47.171271 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1810 01:02:47.171320 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1811 01:02:47.171369 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1812 01:02:47.171418 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1813 01:02:47.171471 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1814 01:02:47.171550 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1815 01:02:47.171629 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1816 01:02:47.171708 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1817 01:02:47.171787 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1818 01:02:47.171865 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1819 01:02:47.171943 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1820 01:02:47.172024 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1821 01:02:47.172103 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1822 01:02:47.172181 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1823 01:02:47.172261 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1824 01:02:47.172340 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1825 01:02:47.172417 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1826 01:02:47.172497 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1827 01:02:47.172575 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1828 01:02:47.172654 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1829 01:02:47.172734 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1830 01:02:47.172813 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1831 01:02:47.172891 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1832 01:02:47.172971 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1833 01:02:47.173049 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1834 01:02:47.173127 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1835 01:02:47.173207 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1836 01:02:47.173285 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1837 01:02:47.173363 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1838 01:02:47.173441 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1839 01:02:47.173521 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1840 01:02:47.173600 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1841 01:02:47.173677 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1842 01:02:47.173755 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1843 01:02:47.173836 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1844 01:02:47.173915 967 |3 6 7|[0] xxxxxxxx oxxoxxxx [MSB]
1845 01:02:47.174020 968 |3 6 8|[0] xxxxxxxx ooxooxxx [MSB]
1846 01:02:47.174109 969 |3 6 9|[0] xxxxxxxx ooxoooxx [MSB]
1847 01:02:47.174160 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1848 01:02:47.174210 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1849 01:02:47.174260 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1850 01:02:47.174311 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
1851 01:02:47.174393 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
1852 01:02:47.174472 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1853 01:02:47.174550 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1854 01:02:47.174628 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1855 01:02:47.174709 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1856 01:02:47.174788 979 |3 6 19|[0] xxooooox oooooooo [MSB]
1857 01:02:47.174869 986 |3 6 26|[0] oooooooo xooxoooo [MSB]
1858 01:02:47.174950 987 |3 6 27|[0] oooooooo xooxoooo [MSB]
1859 01:02:47.175225 988 |3 6 28|[0] oooooooo xooxoooo [MSB]
1860 01:02:47.175313 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1861 01:02:47.175394 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1862 01:02:47.175473 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1863 01:02:47.175553 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1864 01:02:47.175635 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1865 01:02:47.175715 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1866 01:02:47.175794 995 |3 6 35|[0] oooxoxxo xxxxxxxx [MSB]
1867 01:02:47.175875 996 |3 6 36|[0] xxxxxxxx xxxxxxxx [MSB]
1868 01:02:47.175955 Byte0, DQ PI dly=986, DQM PI dly= 986
1869 01:02:47.176032 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
1870 01:02:47.176109
1871 01:02:47.176161 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
1872 01:02:47.176210
1873 01:02:47.176257 Byte1, DQ PI dly=978, DQM PI dly= 978
1874 01:02:47.176336 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1875 01:02:47.176412
1876 01:02:47.176489 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1877 01:02:47.176566
1878 01:02:47.176642 ==
1879 01:02:47.176719 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1880 01:02:47.176799 fsp= 1, odt_onoff= 1, Byte mode= 0
1881 01:02:47.176877 ==
1882 01:02:47.176953 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1883 01:02:47.177025
1884 01:02:47.177078 Begin, DQ Scan Range 954~1018
1885 01:02:47.177127 Write Rank1 MR14 =0x0
1886 01:02:47.177190
1887 01:02:47.177248 CH=0, VrefRange= 0, VrefLevel = 0
1888 01:02:47.177297 TX Bit0 (982~994) 13 988, Bit8 (968~981) 14 974,
1889 01:02:47.177369 TX Bit1 (981~992) 12 986, Bit9 (971~983) 13 977,
1890 01:02:47.177448 TX Bit2 (981~993) 13 987, Bit10 (976~989) 14 982,
1891 01:02:47.177525 TX Bit3 (978~986) 9 982, Bit11 (970~981) 12 975,
1892 01:02:47.177605 TX Bit4 (980~993) 14 986, Bit12 (972~983) 12 977,
1893 01:02:47.177684 TX Bit5 (979~991) 13 985, Bit13 (973~983) 11 978,
1894 01:02:47.177772 TX Bit6 (979~991) 13 985, Bit14 (973~985) 13 979,
1895 01:02:47.177850 TX Bit7 (981~992) 12 986, Bit15 (976~988) 13 982,
1896 01:02:47.177928
1897 01:02:47.178037 Write Rank1 MR14 =0x2
1898 01:02:47.178088
1899 01:02:47.178136 CH=0, VrefRange= 0, VrefLevel = 2
1900 01:02:47.178188 TX Bit0 (981~994) 14 987, Bit8 (969~982) 14 975,
1901 01:02:47.178237 TX Bit1 (980~993) 14 986, Bit9 (971~983) 13 977,
1902 01:02:47.178285 TX Bit2 (981~994) 14 987, Bit10 (975~989) 15 982,
1903 01:02:47.178335 TX Bit3 (978~987) 10 982, Bit11 (970~981) 12 975,
1904 01:02:47.178384 TX Bit4 (980~993) 14 986, Bit12 (972~983) 12 977,
1905 01:02:47.178432 TX Bit5 (979~992) 14 985, Bit13 (972~984) 13 978,
1906 01:02:47.178511 TX Bit6 (979~992) 14 985, Bit14 (973~985) 13 979,
1907 01:02:47.178588 TX Bit7 (980~993) 14 986, Bit15 (975~989) 15 982,
1908 01:02:47.178663
1909 01:02:47.178740 Write Rank1 MR14 =0x4
1910 01:02:47.178815
1911 01:02:47.178890 CH=0, VrefRange= 0, VrefLevel = 4
1912 01:02:47.178966 TX Bit0 (981~995) 15 988, Bit8 (968~982) 15 975,
1913 01:02:47.179045 TX Bit1 (980~994) 15 987, Bit9 (970~984) 15 977,
1914 01:02:47.179123 TX Bit2 (980~994) 15 987, Bit10 (975~989) 15 982,
1915 01:02:47.179200 TX Bit3 (977~988) 12 982, Bit11 (969~981) 13 975,
1916 01:02:47.179277 TX Bit4 (979~993) 15 986, Bit12 (971~984) 14 977,
1917 01:02:47.179355 TX Bit5 (978~992) 15 985, Bit13 (972~984) 13 978,
1918 01:02:47.179432 TX Bit6 (978~992) 15 985, Bit14 (971~986) 16 978,
1919 01:02:47.179509 TX Bit7 (980~993) 14 986, Bit15 (976~989) 14 982,
1920 01:02:47.179584
1921 01:02:47.179662 Write Rank1 MR14 =0x6
1922 01:02:47.179737
1923 01:02:47.179813 CH=0, VrefRange= 0, VrefLevel = 6
1924 01:02:47.179901 TX Bit0 (980~996) 17 988, Bit8 (968~982) 15 975,
1925 01:02:47.179982 TX Bit1 (980~994) 15 987, Bit9 (969~985) 17 977,
1926 01:02:47.180058 TX Bit2 (980~995) 16 987, Bit10 (975~990) 16 982,
1927 01:02:47.180137 TX Bit3 (977~989) 13 983, Bit11 (968~982) 15 975,
1928 01:02:47.180216 TX Bit4 (979~994) 16 986, Bit12 (971~984) 14 977,
1929 01:02:47.180293 TX Bit5 (978~992) 15 985, Bit13 (971~985) 15 978,
1930 01:02:47.180370 TX Bit6 (979~992) 14 985, Bit14 (971~987) 17 979,
1931 01:02:47.180449 TX Bit7 (980~994) 15 987, Bit15 (974~989) 16 981,
1932 01:02:47.180524
1933 01:02:47.180599 Write Rank1 MR14 =0x8
1934 01:02:47.180676
1935 01:02:47.180753 CH=0, VrefRange= 0, VrefLevel = 8
1936 01:02:47.180830 TX Bit0 (980~996) 17 988, Bit8 (967~983) 17 975,
1937 01:02:47.180910 TX Bit1 (980~995) 16 987, Bit9 (969~985) 17 977,
1938 01:02:47.180999 TX Bit2 (980~995) 16 987, Bit10 (974~990) 17 982,
1939 01:02:47.181077 TX Bit3 (977~990) 14 983, Bit11 (968~983) 16 975,
1940 01:02:47.181154 TX Bit4 (979~994) 16 986, Bit12 (971~985) 15 978,
1941 01:02:47.181231 TX Bit5 (978~992) 15 985, Bit13 (971~985) 15 978,
1942 01:02:47.181291 TX Bit6 (978~993) 16 985, Bit14 (971~988) 18 979,
1943 01:02:47.181358 TX Bit7 (979~994) 16 986, Bit15 (974~990) 17 982,
1944 01:02:47.181434
1945 01:02:47.181510 Write Rank1 MR14 =0xa
1946 01:02:47.181597
1947 01:02:47.181674 CH=0, VrefRange= 0, VrefLevel = 10
1948 01:02:47.181752 TX Bit0 (980~997) 18 988, Bit8 (967~983) 17 975,
1949 01:02:47.181830 TX Bit1 (980~995) 16 987, Bit9 (969~986) 18 977,
1950 01:02:47.181907 TX Bit2 (980~996) 17 988, Bit10 (974~990) 17 982,
1951 01:02:47.182009 TX Bit3 (976~991) 16 983, Bit11 (968~983) 16 975,
1952 01:02:47.182112 TX Bit4 (979~995) 17 987, Bit12 (969~985) 17 977,
1953 01:02:47.182190 TX Bit5 (978~993) 16 985, Bit13 (971~986) 16 978,
1954 01:02:47.182270 TX Bit6 (978~993) 16 985, Bit14 (971~988) 18 979,
1955 01:02:47.182348 TX Bit7 (979~994) 16 986, Bit15 (974~990) 17 982,
1956 01:02:47.182424
1957 01:02:47.182499 Write Rank1 MR14 =0xc
1958 01:02:47.182576
1959 01:02:47.182651 CH=0, VrefRange= 0, VrefLevel = 12
1960 01:02:47.182727 TX Bit0 (980~997) 18 988, Bit8 (967~984) 18 975,
1961 01:02:47.182805 TX Bit1 (980~996) 17 988, Bit9 (969~987) 19 978,
1962 01:02:47.182885 TX Bit2 (980~997) 18 988, Bit10 (974~990) 17 982,
1963 01:02:47.182962 TX Bit3 (976~991) 16 983, Bit11 (967~984) 18 975,
1964 01:02:47.183038 TX Bit4 (979~995) 17 987, Bit12 (970~986) 17 978,
1965 01:02:47.183319 TX Bit5 (977~993) 17 985, Bit13 (970~986) 17 978,
1966 01:02:47.183403 TX Bit6 (978~994) 17 986, Bit14 (971~989) 19 980,
1967 01:02:47.183481 TX Bit7 (979~995) 17 987, Bit15 (973~990) 18 981,
1968 01:02:47.183556
1969 01:02:47.183634 Write Rank1 MR14 =0xe
1970 01:02:47.183709
1971 01:02:47.183785 CH=0, VrefRange= 0, VrefLevel = 14
1972 01:02:47.183863 TX Bit0 (980~999) 20 989, Bit8 (967~984) 18 975,
1973 01:02:47.183942 TX Bit1 (979~997) 19 988, Bit9 (968~988) 21 978,
1974 01:02:47.184018 TX Bit2 (980~998) 19 989, Bit10 (973~991) 19 982,
1975 01:02:47.326152 TX Bit3 (976~992) 17 984, Bit11 (967~984) 18 975,
1976 01:02:47.326281 TX Bit4 (979~996) 18 987, Bit12 (969~988) 20 978,
1977 01:02:47.326371 TX Bit5 (977~994) 18 985, Bit13 (969~988) 20 978,
1978 01:02:47.326455 TX Bit6 (978~994) 17 986, Bit14 (970~989) 20 979,
1979 01:02:47.326538 TX Bit7 (979~996) 18 987, Bit15 (973~991) 19 982,
1980 01:02:47.326618
1981 01:02:47.326695 Write Rank1 MR14 =0x10
1982 01:02:47.326760
1983 01:02:47.326814 CH=0, VrefRange= 0, VrefLevel = 16
1984 01:02:47.326864 TX Bit0 (980~999) 20 989, Bit8 (967~985) 19 976,
1985 01:02:47.326914 TX Bit1 (979~997) 19 988, Bit9 (968~988) 21 978,
1986 01:02:47.326964 TX Bit2 (979~999) 21 989, Bit10 (973~992) 20 982,
1987 01:02:47.327042 TX Bit3 (975~992) 18 983, Bit11 (967~985) 19 976,
1988 01:02:47.327120 TX Bit4 (979~997) 19 988, Bit12 (969~988) 20 978,
1989 01:02:47.327197 TX Bit5 (977~994) 18 985, Bit13 (969~988) 20 978,
1990 01:02:47.327276 TX Bit6 (978~994) 17 986, Bit14 (970~989) 20 979,
1991 01:02:47.327355 TX Bit7 (979~996) 18 987, Bit15 (973~991) 19 982,
1992 01:02:47.327431
1993 01:02:47.327508 Write Rank1 MR14 =0x12
1994 01:02:47.327582
1995 01:02:47.327655 CH=0, VrefRange= 0, VrefLevel = 18
1996 01:02:47.327708 TX Bit0 (979~1000) 22 989, Bit8 (967~985) 19 976,
1997 01:02:47.327761 TX Bit1 (979~998) 20 988, Bit9 (968~988) 21 978,
1998 01:02:47.327810 TX Bit2 (979~999) 21 989, Bit10 (973~992) 20 982,
1999 01:02:47.327859 TX Bit3 (974~992) 19 983, Bit11 (967~985) 19 976,
2000 01:02:47.327907 TX Bit4 (978~998) 21 988, Bit12 (968~988) 21 978,
2001 01:02:47.327958 TX Bit5 (977~995) 19 986, Bit13 (968~988) 21 978,
2002 01:02:47.328007 TX Bit6 (977~995) 19 986, Bit14 (968~990) 23 979,
2003 01:02:47.328054 TX Bit7 (979~997) 19 988, Bit15 (973~992) 20 982,
2004 01:02:47.328102
2005 01:02:47.328149 Write Rank1 MR14 =0x14
2006 01:02:47.328198
2007 01:02:47.328246 CH=0, VrefRange= 0, VrefLevel = 20
2008 01:02:47.328323 TX Bit0 (979~1001) 23 990, Bit8 (966~986) 21 976,
2009 01:02:47.328399 TX Bit1 (979~999) 21 989, Bit9 (967~989) 23 978,
2010 01:02:47.328478 TX Bit2 (980~1000) 21 990, Bit10 (973~993) 21 983,
2011 01:02:47.328556 TX Bit3 (974~993) 20 983, Bit11 (967~985) 19 976,
2012 01:02:47.328634 TX Bit4 (978~998) 21 988, Bit12 (968~989) 22 978,
2013 01:02:47.328713 TX Bit5 (977~995) 19 986, Bit13 (968~989) 22 978,
2014 01:02:47.328792 TX Bit6 (977~996) 20 986, Bit14 (969~990) 22 979,
2015 01:02:47.328869 TX Bit7 (979~998) 20 988, Bit15 (972~992) 21 982,
2016 01:02:47.328946
2017 01:02:47.329022 Write Rank1 MR14 =0x16
2018 01:02:47.329097
2019 01:02:47.329173 CH=0, VrefRange= 0, VrefLevel = 22
2020 01:02:47.329252 TX Bit0 (979~1001) 23 990, Bit8 (966~987) 22 976,
2021 01:02:47.329329 TX Bit1 (979~999) 21 989, Bit9 (967~989) 23 978,
2022 01:02:47.329405 TX Bit2 (979~1000) 22 989, Bit10 (973~993) 21 983,
2023 01:02:47.329483 TX Bit3 (973~993) 21 983, Bit11 (966~986) 21 976,
2024 01:02:47.329560 TX Bit4 (978~999) 22 988, Bit12 (968~989) 22 978,
2025 01:02:47.329637 TX Bit5 (976~996) 21 986, Bit13 (968~989) 22 978,
2026 01:02:47.329715 TX Bit6 (977~996) 20 986, Bit14 (968~991) 24 979,
2027 01:02:47.329793 TX Bit7 (978~999) 22 988, Bit15 (972~993) 22 982,
2028 01:02:47.329868
2029 01:02:47.329945 Write Rank1 MR14 =0x18
2030 01:02:47.330070
2031 01:02:47.330149 CH=0, VrefRange= 0, VrefLevel = 24
2032 01:02:47.330228 TX Bit0 (979~1002) 24 990, Bit8 (966~987) 22 976,
2033 01:02:47.330306 TX Bit1 (979~1000) 22 989, Bit9 (967~989) 23 978,
2034 01:02:47.330383 TX Bit2 (979~1001) 23 990, Bit10 (973~994) 22 983,
2035 01:02:47.330443 TX Bit3 (973~994) 22 983, Bit11 (966~987) 22 976,
2036 01:02:47.330493 TX Bit4 (978~999) 22 988, Bit12 (968~989) 22 978,
2037 01:02:47.330542 TX Bit5 (976~996) 21 986, Bit13 (968~989) 22 978,
2038 01:02:47.330590 TX Bit6 (977~997) 21 987, Bit14 (968~991) 24 979,
2039 01:02:47.330660 TX Bit7 (978~999) 22 988, Bit15 (972~993) 22 982,
2040 01:02:47.330737
2041 01:02:47.330813 Write Rank1 MR14 =0x1a
2042 01:02:47.330890
2043 01:02:47.330971 CH=0, VrefRange= 0, VrefLevel = 26
2044 01:02:47.331049 TX Bit0 (979~1002) 24 990, Bit8 (966~988) 23 977,
2045 01:02:47.331133 TX Bit1 (978~1000) 23 989, Bit9 (967~989) 23 978,
2046 01:02:47.331212 TX Bit2 (979~1001) 23 990, Bit10 (972~993) 22 982,
2047 01:02:47.331300 TX Bit3 (972~994) 23 983, Bit11 (966~988) 23 977,
2048 01:02:47.331355 TX Bit4 (978~1000) 23 989, Bit12 (967~989) 23 978,
2049 01:02:47.331406 TX Bit5 (976~997) 22 986, Bit13 (968~990) 23 979,
2050 01:02:47.331455 TX Bit6 (977~998) 22 987, Bit14 (968~991) 24 979,
2051 01:02:47.331504 TX Bit7 (978~1000) 23 989, Bit15 (972~993) 22 982,
2052 01:02:47.331553
2053 01:02:47.331610 Write Rank1 MR14 =0x1c
2054 01:02:47.331663
2055 01:02:47.331711 CH=0, VrefRange= 0, VrefLevel = 28
2056 01:02:47.331760 TX Bit0 (979~1003) 25 991, Bit8 (965~989) 25 977,
2057 01:02:47.331809 TX Bit1 (978~1001) 24 989, Bit9 (967~989) 23 978,
2058 01:02:47.331863 TX Bit2 (979~1002) 24 990, Bit10 (972~995) 24 983,
2059 01:02:47.331912 TX Bit3 (972~994) 23 983, Bit11 (966~988) 23 977,
2060 01:02:47.331974 TX Bit4 (978~1001) 24 989, Bit12 (967~989) 23 978,
2061 01:02:47.332025 TX Bit5 (976~998) 23 987, Bit13 (967~989) 23 978,
2062 01:02:47.332077 TX Bit6 (977~998) 22 987, Bit14 (968~991) 24 979,
2063 01:02:47.332156 TX Bit7 (978~1000) 23 989, Bit15 (971~994) 24 982,
2064 01:02:47.332233
2065 01:02:47.332308 Write Rank1 MR14 =0x1e
2066 01:02:47.332385
2067 01:02:47.332665 CH=0, VrefRange= 0, VrefLevel = 30
2068 01:02:47.332747 TX Bit0 (979~1003) 25 991, Bit8 (966~988) 23 977,
2069 01:02:47.332827 TX Bit1 (978~1001) 24 989, Bit9 (967~989) 23 978,
2070 01:02:47.332908 TX Bit2 (979~1002) 24 990, Bit10 (972~994) 23 983,
2071 01:02:47.332988 TX Bit3 (972~995) 24 983, Bit11 (966~989) 24 977,
2072 01:02:47.333095 TX Bit4 (978~1001) 24 989, Bit12 (967~990) 24 978,
2073 01:02:47.333176 TX Bit5 (976~997) 22 986, Bit13 (967~989) 23 978,
2074 01:02:47.333254 TX Bit6 (977~999) 23 988, Bit14 (968~991) 24 979,
2075 01:02:47.333366 TX Bit7 (978~1001) 24 989, Bit15 (970~994) 25 982,
2076 01:02:47.333493
2077 01:02:47.333569 Write Rank1 MR14 =0x20
2078 01:02:47.333644
2079 01:02:47.333722 CH=0, VrefRange= 0, VrefLevel = 32
2080 01:02:47.333800 TX Bit0 (979~1003) 25 991, Bit8 (966~988) 23 977,
2081 01:02:47.333881 TX Bit1 (978~1001) 24 989, Bit9 (967~989) 23 978,
2082 01:02:47.333990 TX Bit2 (979~1002) 24 990, Bit10 (972~994) 23 983,
2083 01:02:47.334083 TX Bit3 (972~995) 24 983, Bit11 (966~989) 24 977,
2084 01:02:47.334161 TX Bit4 (978~1001) 24 989, Bit12 (967~990) 24 978,
2085 01:02:47.334238 TX Bit5 (976~997) 22 986, Bit13 (967~989) 23 978,
2086 01:02:47.334317 TX Bit6 (977~999) 23 988, Bit14 (968~991) 24 979,
2087 01:02:47.334396 TX Bit7 (978~1001) 24 989, Bit15 (970~994) 25 982,
2088 01:02:47.334477
2089 01:02:47.334588 wait MRW command Rank1 MR14 =0x22 fired (1)
2090 01:02:47.334664 Write Rank1 MR14 =0x22
2091 01:02:47.334740
2092 01:02:47.334815 CH=0, VrefRange= 0, VrefLevel = 34
2093 01:02:47.334893 TX Bit0 (979~1003) 25 991, Bit8 (966~988) 23 977,
2094 01:02:47.334972 TX Bit1 (978~1001) 24 989, Bit9 (967~989) 23 978,
2095 01:02:47.335051 TX Bit2 (979~1002) 24 990, Bit10 (972~994) 23 983,
2096 01:02:47.335128 TX Bit3 (972~995) 24 983, Bit11 (966~989) 24 977,
2097 01:02:47.335207 TX Bit4 (978~1001) 24 989, Bit12 (967~990) 24 978,
2098 01:02:47.335285 TX Bit5 (976~997) 22 986, Bit13 (967~989) 23 978,
2099 01:02:47.335362 TX Bit6 (977~999) 23 988, Bit14 (968~991) 24 979,
2100 01:02:47.335439 TX Bit7 (978~1001) 24 989, Bit15 (970~994) 25 982,
2101 01:02:47.335518
2102 01:02:47.335595 Write Rank1 MR14 =0x24
2103 01:02:47.335670
2104 01:02:47.335783 CH=0, VrefRange= 0, VrefLevel = 36
2105 01:02:47.335860 TX Bit0 (979~1003) 25 991, Bit8 (966~988) 23 977,
2106 01:02:47.335937 TX Bit1 (978~1001) 24 989, Bit9 (967~989) 23 978,
2107 01:02:47.336014 TX Bit2 (979~1002) 24 990, Bit10 (972~994) 23 983,
2108 01:02:47.336093 TX Bit3 (972~995) 24 983, Bit11 (966~989) 24 977,
2109 01:02:47.336173 TX Bit4 (978~1001) 24 989, Bit12 (967~990) 24 978,
2110 01:02:47.336251 TX Bit5 (976~997) 22 986, Bit13 (967~989) 23 978,
2111 01:02:47.336328 TX Bit6 (977~999) 23 988, Bit14 (968~991) 24 979,
2112 01:02:47.336407 TX Bit7 (978~1001) 24 989, Bit15 (970~994) 25 982,
2113 01:02:47.336484
2114 01:02:47.336559
2115 01:02:47.336635 TX Vref found, early break! 353< 360
2116 01:02:47.336715 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =844/100 ps
2117 01:02:47.336794 u1DelayCellOfst[0]=9 cells (8 PI)
2118 01:02:47.336870 u1DelayCellOfst[1]=6 cells (6 PI)
2119 01:02:47.336946 u1DelayCellOfst[2]=8 cells (7 PI)
2120 01:02:47.337004 u1DelayCellOfst[3]=0 cells (0 PI)
2121 01:02:47.337053 u1DelayCellOfst[4]=6 cells (6 PI)
2122 01:02:47.337102 u1DelayCellOfst[5]=3 cells (3 PI)
2123 01:02:47.337151 u1DelayCellOfst[6]=5 cells (5 PI)
2124 01:02:47.337199 u1DelayCellOfst[7]=6 cells (6 PI)
2125 01:02:47.337253 Byte0, DQ PI dly=983, DQM PI dly= 987
2126 01:02:47.337347 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
2127 01:02:47.337468
2128 01:02:47.337593 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
2129 01:02:47.337671
2130 01:02:47.337748 u1DelayCellOfst[8]=0 cells (0 PI)
2131 01:02:47.337826 u1DelayCellOfst[9]=1 cells (1 PI)
2132 01:02:47.337921 u1DelayCellOfst[10]=6 cells (6 PI)
2133 01:02:47.338002 u1DelayCellOfst[11]=0 cells (0 PI)
2134 01:02:47.338067 u1DelayCellOfst[12]=1 cells (1 PI)
2135 01:02:47.338118 u1DelayCellOfst[13]=1 cells (1 PI)
2136 01:02:47.338168 u1DelayCellOfst[14]=2 cells (2 PI)
2137 01:02:47.338217 u1DelayCellOfst[15]=5 cells (5 PI)
2138 01:02:47.338265 Byte1, DQ PI dly=977, DQM PI dly= 980
2139 01:02:47.338315 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
2140 01:02:47.338364
2141 01:02:47.338414 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
2142 01:02:47.338464
2143 01:02:47.338515 Write Rank1 MR14 =0x1e
2144 01:02:47.338564
2145 01:02:47.338612 Final TX Range 0 Vref 30
2146 01:02:47.338660
2147 01:02:47.338710 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2148 01:02:47.338761
2149 01:02:47.338809 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2150 01:02:47.338858 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2151 01:02:47.338907 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2152 01:02:47.338956 Write Rank1 MR3 =0xb0
2153 01:02:47.339009 DramC Write-DBI on
2154 01:02:47.339060 ==
2155 01:02:47.339109 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2156 01:02:47.339171 fsp= 1, odt_onoff= 1, Byte mode= 0
2157 01:02:47.339235 ==
2158 01:02:47.339284 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2159 01:02:47.339333
2160 01:02:47.339380 Begin, DQ Scan Range 700~764
2161 01:02:47.339428
2162 01:02:47.339476
2163 01:02:47.339525 TX Vref Scan disable
2164 01:02:47.339575 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2165 01:02:47.339628 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2166 01:02:47.339678 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2167 01:02:47.339726 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2168 01:02:47.339776 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2169 01:02:47.339828 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2170 01:02:47.339877 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2171 01:02:47.339927 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2172 01:02:47.339975 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2173 01:02:47.340024 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2174 01:02:47.340075 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2175 01:02:47.340126 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2176 01:02:47.340177 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2177 01:02:47.340416 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2178 01:02:47.340472 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2179 01:02:47.340523 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2180 01:02:47.340574 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2181 01:02:47.340626 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2182 01:02:47.340677 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2183 01:02:47.340730 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2184 01:02:47.340779 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2185 01:02:47.340829 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2186 01:02:47.340879 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
2187 01:02:47.340932 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2188 01:02:47.340983 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2189 01:02:47.341032 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2190 01:02:47.341081 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2191 01:02:47.341130 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2192 01:02:47.341179 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2193 01:02:47.341234 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2194 01:02:47.341288 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2195 01:02:47.341364 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2196 01:02:47.341434 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2197 01:02:47.341483 746 |2 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
2198 01:02:47.341538 Byte0, DQ PI dly=733, DQM PI dly= 733
2199 01:02:47.341587 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 29)
2200 01:02:47.341636
2201 01:02:47.341684 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 29)
2202 01:02:47.341732
2203 01:02:47.341780 Byte1, DQ PI dly=723, DQM PI dly= 723
2204 01:02:47.341852 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2205 01:02:47.341930
2206 01:02:47.342031 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2207 01:02:47.342083
2208 01:02:47.342134 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2209 01:02:47.342185 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2210 01:02:47.342233 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2211 01:02:47.342283 Write Rank1 MR3 =0x30
2212 01:02:47.342331 DramC Write-DBI off
2213 01:02:47.342379
2214 01:02:47.342430 [DATLAT]
2215 01:02:47.342481 Freq=1600, CH0 RK1, use_rxtx_scan=0
2216 01:02:47.342531
2217 01:02:47.342579 DATLAT Default: 0x10
2218 01:02:47.342627 7, 0xFFFF, sum=0
2219 01:02:47.342676 8, 0xFFFF, sum=0
2220 01:02:47.342727 9, 0xFFFF, sum=0
2221 01:02:47.342777 10, 0xFFFF, sum=0
2222 01:02:47.342826 11, 0xFFFF, sum=0
2223 01:02:47.342875 12, 0xFFFF, sum=0
2224 01:02:47.342923 13, 0xFFFF, sum=0
2225 01:02:47.342972 14, 0x0, sum=1
2226 01:02:47.343023 15, 0x0, sum=2
2227 01:02:47.343073 16, 0x0, sum=3
2228 01:02:47.343125 17, 0x0, sum=4
2229 01:02:47.343174 pattern=2 first_step=14 total pass=5 best_step=16
2230 01:02:47.343222 ==
2231 01:02:47.343270 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2232 01:02:47.343318 fsp= 1, odt_onoff= 1, Byte mode= 0
2233 01:02:47.343370 ==
2234 01:02:47.343418 Start DQ dly to find pass range UseTestEngine =1
2235 01:02:47.343471 x-axis: bit #, y-axis: DQ dly (-127~63)
2236 01:02:47.343535 RX Vref Scan = 0
2237 01:02:47.343617 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2238 01:02:47.343674 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2239 01:02:47.343726 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2240 01:02:47.343776 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2241 01:02:47.343825 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2242 01:02:47.343874 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2243 01:02:47.343926 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2244 01:02:47.343976 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2245 01:02:47.344025 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2246 01:02:47.344075 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2247 01:02:47.344124 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2248 01:02:47.344173 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2249 01:02:47.344225 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2250 01:02:47.344277 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2251 01:02:47.344326 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2252 01:02:47.344375 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2253 01:02:47.344425 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2254 01:02:47.344474 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2255 01:02:47.344523 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2256 01:02:47.344574 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2257 01:02:47.344623 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2258 01:02:47.344671 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2259 01:02:47.344720 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2260 01:02:47.344768 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2261 01:02:47.344817 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2262 01:02:47.344870 -1, [0] xxxxxxxx xxxxxxxx [MSB]
2263 01:02:47.344924 0, [0] xxxxxxxx xxxxxxxx [MSB]
2264 01:02:47.344975 1, [0] xxxoxxxx oxxxxxxx [MSB]
2265 01:02:47.345025 2, [0] xxxoxxxx oxxxxxxx [MSB]
2266 01:02:47.345073 3, [0] xxxoxxxx oxxoxxxx [MSB]
2267 01:02:47.345122 4, [0] xxxoxoxx oxxoxxxx [MSB]
2268 01:02:47.345175 5, [0] xxxoxoox ooxooxxx [MSB]
2269 01:02:47.345224 6, [0] xxxoxooo ooxooxxx [MSB]
2270 01:02:47.345274 7, [0] xoxoxooo ooxoooox [MSB]
2271 01:02:47.345323 8, [0] xoxoxooo ooxoooox [MSB]
2272 01:02:47.345373 9, [0] oooooooo ooxooooo [MSB]
2273 01:02:47.345424 10, [0] oooooooo ooxooooo [MSB]
2274 01:02:47.345476 33, [0] oooxoooo xooxoooo [MSB]
2275 01:02:47.345526 34, [0] oooxoooo xooxoooo [MSB]
2276 01:02:47.345575 35, [0] oooxoxoo xxoxoxoo [MSB]
2277 01:02:47.345625 36, [0] oooxoxxo xxoxxxoo [MSB]
2278 01:02:47.345676 37, [0] oooxoxxo xxoxxxoo [MSB]
2279 01:02:47.345727 38, [0] oooxxxxx xxoxxxxo [MSB]
2280 01:02:47.345775 39, [0] oooxxxxx xxoxxxxx [MSB]
2281 01:02:47.345824 40, [0] xxxxxxxx xxoxxxxx [MSB]
2282 01:02:47.345873 41, [0] xxxxxxxx xxoxxxxx [MSB]
2283 01:02:47.345922 42, [0] xxxxxxxx xxxxxxxx [MSB]
2284 01:02:47.345975 iDelay=42, Bit 0, Center 24 (9 ~ 39) 31
2285 01:02:47.346068 iDelay=42, Bit 1, Center 23 (7 ~ 39) 33
2286 01:02:47.346116 iDelay=42, Bit 2, Center 24 (9 ~ 39) 31
2287 01:02:47.346164 iDelay=42, Bit 3, Center 16 (1 ~ 32) 32
2288 01:02:47.346212 iDelay=42, Bit 4, Center 23 (9 ~ 37) 29
2289 01:02:47.346263 iDelay=42, Bit 5, Center 19 (4 ~ 34) 31
2290 01:02:47.346312 iDelay=42, Bit 6, Center 20 (5 ~ 35) 31
2291 01:02:47.346361 iDelay=42, Bit 7, Center 21 (6 ~ 37) 32
2292 01:02:47.346409 iDelay=42, Bit 8, Center 16 (1 ~ 32) 32
2293 01:02:47.346457 iDelay=42, Bit 9, Center 19 (5 ~ 34) 30
2294 01:02:47.346504 iDelay=42, Bit 10, Center 26 (11 ~ 41) 31
2295 01:02:47.346556 iDelay=42, Bit 11, Center 17 (3 ~ 32) 30
2296 01:02:47.346604 iDelay=42, Bit 12, Center 20 (5 ~ 35) 31
2297 01:02:47.346655 iDelay=42, Bit 13, Center 20 (7 ~ 34) 28
2298 01:02:47.346893 iDelay=42, Bit 14, Center 22 (7 ~ 37) 31
2299 01:02:47.346949 iDelay=42, Bit 15, Center 23 (9 ~ 38) 30
2300 01:02:47.346999 ==
2301 01:02:47.347047 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2302 01:02:47.347096 fsp= 1, odt_onoff= 1, Byte mode= 0
2303 01:02:47.347147 ==
2304 01:02:47.347196 DQS Delay:
2305 01:02:47.347247 DQS0 = 0, DQS1 = 0
2306 01:02:47.347295 DQM Delay:
2307 01:02:47.347343 DQM0 = 21, DQM1 = 20
2308 01:02:47.347391 DQ Delay:
2309 01:02:47.347441 DQ0 =24, DQ1 =23, DQ2 =24, DQ3 =16
2310 01:02:47.347490 DQ4 =23, DQ5 =19, DQ6 =20, DQ7 =21
2311 01:02:47.347539 DQ8 =16, DQ9 =19, DQ10 =26, DQ11 =17
2312 01:02:47.347587 DQ12 =20, DQ13 =20, DQ14 =22, DQ15 =23
2313 01:02:47.347636
2314 01:02:47.347683
2315 01:02:47.347732
2316 01:02:47.347781 [DramC_TX_OE_Calibration] TA2
2317 01:02:47.347831 Original DQ_B0 (3 6) =30, OEN = 27
2318 01:02:47.347880 Original DQ_B1 (3 6) =30, OEN = 27
2319 01:02:47.347928 23, 0x0, End_B0=23 End_B1=23
2320 01:02:47.347978 24, 0x0, End_B0=24 End_B1=24
2321 01:02:47.348031 25, 0x0, End_B0=25 End_B1=25
2322 01:02:47.348081 26, 0x0, End_B0=26 End_B1=26
2323 01:02:47.348130 27, 0x0, End_B0=27 End_B1=27
2324 01:02:47.348179 28, 0x0, End_B0=28 End_B1=28
2325 01:02:47.348228 29, 0x0, End_B0=29 End_B1=29
2326 01:02:47.348277 30, 0x0, End_B0=30 End_B1=30
2327 01:02:47.348329 31, 0xFFFF, End_B0=30 End_B1=30
2328 01:02:47.348382 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2329 01:02:47.348431 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2330 01:02:47.348479
2331 01:02:47.348527
2332 01:02:47.348574 Write Rank1 MR23 =0x3f
2333 01:02:47.348626 [DQSOSC]
2334 01:02:47.348675 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0x202, tDQSOscB0 = 454 ps tDQSOscB1 = 454 ps
2335 01:02:47.348724 CH0_RK1: MR19=0x202, MR18=0xB5B5, DQSOSC=454, MR23=63, INC=11, DEC=17
2336 01:02:47.348773 Write Rank1 MR23 =0x3f
2337 01:02:47.348821 [DQSOSC]
2338 01:02:47.348868 [DQSOSCAuto] RK1, (LSB)MR18= 0xb7b7, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
2339 01:02:47.348922 CH0 RK1: MR19=202, MR18=B7B7
2340 01:02:47.348974 [RxdqsGatingPostProcess] freq 1600
2341 01:02:47.349023 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2342 01:02:47.349071 Rank: 0
2343 01:02:47.349119 best DQS0 dly(2T, 0.5T) = (2, 6)
2344 01:02:47.349167 best DQS1 dly(2T, 0.5T) = (2, 6)
2345 01:02:47.349220 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2346 01:02:47.349269 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2347 01:02:47.349319 Rank: 1
2348 01:02:47.349367 best DQS0 dly(2T, 0.5T) = (2, 6)
2349 01:02:47.349415 best DQS1 dly(2T, 0.5T) = (2, 6)
2350 01:02:47.349463 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2351 01:02:47.349515 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2352 01:02:47.349567 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2353 01:02:47.349617 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2354 01:02:47.349666 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2355 01:02:47.349714 Write Rank0 MR13 =0x59
2356 01:02:47.349765 ==
2357 01:02:47.349843 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2358 01:02:47.349919 fsp= 1, odt_onoff= 1, Byte mode= 0
2359 01:02:47.349999 ==
2360 01:02:47.350084 === u2Vref_new: 0x56 --> 0x3a
2361 01:02:47.350134 === u2Vref_new: 0x58 --> 0x58
2362 01:02:47.350185 === u2Vref_new: 0x5a --> 0x5a
2363 01:02:47.350233 === u2Vref_new: 0x5c --> 0x78
2364 01:02:47.350281 === u2Vref_new: 0x5e --> 0x7a
2365 01:02:47.350328 === u2Vref_new: 0x60 --> 0x90
2366 01:02:47.350378 [CA 0] Center 38 (14~63) winsize 50
2367 01:02:47.350427 [CA 1] Center 37 (12~63) winsize 52
2368 01:02:47.350475 [CA 2] Center 35 (7~63) winsize 57
2369 01:02:47.350522 [CA 3] Center 35 (7~63) winsize 57
2370 01:02:47.350570 [CA 4] Center 33 (4~63) winsize 60
2371 01:02:47.350617 [CA 5] Center 28 (-1~57) winsize 59
2372 01:02:47.350668
2373 01:02:47.350718 [CATrainingPosCal] consider 1 rank data
2374 01:02:47.350766 u2DelayCellTimex100 = 844/100 ps
2375 01:02:47.350814 CA0 delay=38 (14~63),Diff = 10 PI (11 cell)
2376 01:02:47.350861 CA1 delay=37 (12~63),Diff = 9 PI (10 cell)
2377 01:02:47.350909 CA2 delay=35 (7~63),Diff = 7 PI (8 cell)
2378 01:02:47.350959 CA3 delay=35 (7~63),Diff = 7 PI (8 cell)
2379 01:02:47.351007 CA4 delay=33 (4~63),Diff = 5 PI (5 cell)
2380 01:02:47.351055 CA5 delay=28 (-1~57),Diff = 0 PI (0 cell)
2381 01:02:47.351102
2382 01:02:47.351150 CA PerBit enable=1, Macro0, CA PI delay=28
2383 01:02:47.351198 === u2Vref_new: 0x5a --> 0x5a
2384 01:02:47.351249
2385 01:02:47.351299 Vref(ca) range 1: 26
2386 01:02:47.351346
2387 01:02:47.351392 CS Dly= 10 (41-0-32)
2388 01:02:47.351440 Write Rank0 MR13 =0xd8
2389 01:02:47.351488 Write Rank0 MR13 =0xd8
2390 01:02:47.351539 Write Rank0 MR12 =0x5a
2391 01:02:47.351587 Write Rank1 MR13 =0x59
2392 01:02:47.351634 ==
2393 01:02:47.351682 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2394 01:02:47.351730 fsp= 1, odt_onoff= 1, Byte mode= 0
2395 01:02:47.351777 ==
2396 01:02:47.351829 === u2Vref_new: 0x56 --> 0x3a
2397 01:02:47.351879 === u2Vref_new: 0x58 --> 0x58
2398 01:02:47.351928 === u2Vref_new: 0x5a --> 0x5a
2399 01:02:47.351976 === u2Vref_new: 0x5c --> 0x78
2400 01:02:47.352023 === u2Vref_new: 0x5e --> 0x7a
2401 01:02:47.352070 === u2Vref_new: 0x60 --> 0x90
2402 01:02:47.352123 [CA 0] Center 36 (10~63) winsize 54
2403 01:02:47.352173 [CA 1] Center 36 (10~63) winsize 54
2404 01:02:47.352221 [CA 2] Center 34 (5~63) winsize 59
2405 01:02:47.352268 [CA 3] Center 34 (6~63) winsize 58
2406 01:02:47.352315 [CA 4] Center 34 (6~63) winsize 58
2407 01:02:47.352363 [CA 5] Center 27 (-1~56) winsize 58
2408 01:02:47.352413
2409 01:02:47.352462 [CATrainingPosCal] consider 2 rank data
2410 01:02:47.352539 u2DelayCellTimex100 = 844/100 ps
2411 01:02:47.352615 CA0 delay=38 (14~63),Diff = 11 PI (12 cell)
2412 01:02:47.352723 CA1 delay=37 (12~63),Diff = 10 PI (11 cell)
2413 01:02:47.352799 CA2 delay=35 (7~63),Diff = 8 PI (9 cell)
2414 01:02:47.352874 CA3 delay=35 (7~63),Diff = 8 PI (9 cell)
2415 01:02:47.352950 CA4 delay=34 (6~63),Diff = 7 PI (8 cell)
2416 01:02:47.353027 CA5 delay=27 (-1~56),Diff = 0 PI (0 cell)
2417 01:02:47.353104
2418 01:02:47.353180 CA PerBit enable=1, Macro0, CA PI delay=27
2419 01:02:47.353255 === u2Vref_new: 0x60 --> 0x90
2420 01:02:47.353331
2421 01:02:47.353406 Vref(ca) range 1: 32
2422 01:02:47.353480
2423 01:02:47.353555 CS Dly= 10 (41-0-32)
2424 01:02:47.353631 Write Rank1 MR13 =0xd8
2425 01:02:47.353709 Write Rank1 MR13 =0xd8
2426 01:02:47.353784 Write Rank1 MR12 =0x60
2427 01:02:47.353859 [RankSwap] Rank num 2, (Multi 1), Rank 0
2428 01:02:47.353936 Write Rank0 MR2 =0xad
2429 01:02:47.354047 [Write Leveling]
2430 01:02:47.354123 delay byte0 byte1 byte2 byte3
2431 01:02:47.354198
2432 01:02:47.354276 10 0 0
2433 01:02:47.354354 11 0 0
2434 01:02:47.354659 12 0 0
2435 01:02:47.354771 13 0 0
2436 01:02:47.354852 14 0 0
2437 01:02:47.354930 15 0 0
2438 01:02:47.355008 16 0 0
2439 01:02:47.355127 17 0 0
2440 01:02:47.355210 18 0 0
2441 01:02:47.355291 19 0 0
2442 01:02:47.355371 20 0 0
2443 01:02:47.355451 21 0 0
2444 01:02:47.355529 22 0 0
2445 01:02:47.355607 23 0 0
2446 01:02:47.355692 24 0 0
2447 01:02:47.355770 25 0 0
2448 01:02:47.355860 26 0 0
2449 01:02:47.355940 27 0 0
2450 01:02:47.357923 28 0 0
2451 01:02:47.358035 29 0 0
2452 01:02:47.358100 30 0 0
2453 01:02:47.361568 31 0 ff
2454 01:02:47.361669 32 0 ff
2455 01:02:47.364579 33 0 ff
2456 01:02:47.364670 34 0 ff
2457 01:02:47.367956 35 ff ff
2458 01:02:47.368024 36 ff ff
2459 01:02:47.371359 37 ff ff
2460 01:02:47.371423 38 ff ff
2461 01:02:47.371481 39 ff ff
2462 01:02:47.374724 40 ff ff
2463 01:02:47.374816 41 ff ff
2464 01:02:47.381357 pass bytecount = 0xff (0xff: all bytes pass)
2465 01:02:47.381428
2466 01:02:47.381483 DQS0 dly: 35
2467 01:02:47.381534 DQS1 dly: 31
2468 01:02:47.384627 Write Rank0 MR2 =0x2d
2469 01:02:47.388097 [RankSwap] Rank num 2, (Multi 1), Rank 0
2470 01:02:47.391295 Write Rank0 MR1 =0xd6
2471 01:02:47.391362 [Gating]
2472 01:02:47.391419 ==
2473 01:02:47.398099 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2474 01:02:47.398171 fsp= 1, odt_onoff= 1, Byte mode= 0
2475 01:02:47.401179 ==
2476 01:02:47.404645 3 1 0 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
2477 01:02:47.408163 3 1 4 |3534 2423 |(11 11)(11 11) |(0 0)(1 1)| 0
2478 01:02:47.411268 3 1 8 |3534 2f2e |(11 11)(11 11) |(0 0)(0 0)| 0
2479 01:02:47.418491 3 1 12 |3534 3231 |(11 11)(11 11) |(1 1)(1 1)| 0
2480 01:02:47.421484 3 1 16 |3534 3332 |(11 11)(11 11) |(1 1)(1 1)| 0
2481 01:02:47.424429 3 1 20 |3534 3332 |(11 11)(11 11) |(1 1)(0 0)| 0
2482 01:02:47.431344 3 1 24 |3534 1717 |(11 11)(11 11) |(1 1)(1 0)| 0
2483 01:02:47.434614 3 1 28 |3534 3131 |(11 11)(11 11) |(0 1)(1 1)| 0
2484 01:02:47.437626 3 2 0 |3534 3231 |(11 11)(11 11) |(0 1)(1 1)| 0
2485 01:02:47.444444 [Byte 1] Lead/lag falling Transition (3, 2, 0)
2486 01:02:47.447628 3 2 4 |3534 2f2e |(11 11)(11 11) |(0 1)(0 1)| 0
2487 01:02:47.451093 3 2 8 |3534 3030 |(11 11)(11 11) |(0 1)(0 1)| 0
2488 01:02:47.454338 3 2 12 |3534 202 |(11 11)(11 11) |(0 1)(0 1)| 0
2489 01:02:47.460844 3 2 16 |3534 1d1d |(11 11)(11 11) |(0 1)(0 1)| 0
2490 01:02:47.464158 3 2 20 |201 1918 |(11 11)(11 11) |(1 1)(1 1)| 0
2491 01:02:47.467468 [Byte 1] Lead/lag falling Transition (3, 2, 20)
2492 01:02:47.474426 3 2 24 |3d3d 706 |(11 11)(11 11) |(1 1)(1 0)| 0
2493 01:02:47.477807 3 2 28 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2494 01:02:47.481330 3 3 0 |3d3d 1312 |(11 11)(1 1) |(1 1)(1 1)| 0
2495 01:02:47.487390 3 3 4 |3d3d 3b3a |(11 11)(11 11) |(1 1)(1 1)| 0
2496 01:02:47.491030 3 3 8 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
2497 01:02:47.494518 [Byte 1] Lead/lag Transition tap number (1)
2498 01:02:47.497463 3 3 12 |3d3d 3938 |(11 11)(11 11) |(1 1)(0 0)| 0
2499 01:02:47.504293 3 3 16 |3d3d 706 |(11 11)(11 11) |(1 1)(1 1)| 0
2500 01:02:47.507571 3 3 20 |3d3d 808 |(11 11)(11 11) |(1 1)(1 1)| 0
2501 01:02:47.510527 3 3 24 |908 1414 |(11 11)(11 11) |(1 1)(1 1)| 0
2502 01:02:47.513971 3 3 28 |1110 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2503 01:02:47.520953 [Byte 0] Lead/lag falling Transition (3, 3, 28)
2504 01:02:47.524357 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2505 01:02:47.527508 [Byte 1] Lead/lag falling Transition (3, 4, 0)
2506 01:02:47.534216 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2507 01:02:47.537735 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2508 01:02:47.540757 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2509 01:02:47.547406 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2510 01:02:47.550618 3 4 20 |808 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2511 01:02:47.553655 3 4 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2512 01:02:47.560685 3 4 28 |3d3d b0a |(11 11)(11 11) |(1 1)(1 1)| 0
2513 01:02:47.563991 3 5 0 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2514 01:02:47.567049 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2515 01:02:47.570478 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2516 01:02:47.577215 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2517 01:02:47.580544 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2518 01:02:47.583722 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2519 01:02:47.590499 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2520 01:02:47.593718 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2521 01:02:47.597055 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2522 01:02:47.603686 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2523 01:02:47.606884 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2524 01:02:47.610163 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2525 01:02:47.613496 [Byte 0] Lead/lag falling Transition (3, 6, 12)
2526 01:02:47.620235 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2527 01:02:47.623444 [Byte 0] Lead/lag Transition tap number (2)
2528 01:02:47.626837 3 6 20 |605 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2529 01:02:47.633452 [Byte 1] Lead/lag falling Transition (3, 6, 20)
2530 01:02:47.637042 3 6 24 |1414 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2531 01:02:47.640268 [Byte 1] Lead/lag Transition tap number (2)
2532 01:02:47.643704 3 6 28 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2533 01:02:47.646531 [Byte 0]First pass (3, 6, 28)
2534 01:02:47.650275 3 7 0 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2535 01:02:47.653411 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2536 01:02:47.656559 [Byte 1]First pass (3, 7, 4)
2537 01:02:47.660238 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2538 01:02:47.666487 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2539 01:02:47.670210 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2540 01:02:47.673150 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2541 01:02:47.676897 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2542 01:02:47.683692 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2543 01:02:47.686338 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2544 01:02:47.689704 4 0 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2545 01:02:47.693300 All bytes gating window > 1UI, Early break!
2546 01:02:47.693397
2547 01:02:47.696771 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 16)
2548 01:02:47.696870
2549 01:02:47.699950 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 24)
2550 01:02:47.700055
2551 01:02:47.702994
2552 01:02:47.703062
2553 01:02:47.706318 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 16)
2554 01:02:47.706406
2555 01:02:47.709873 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 24)
2556 01:02:47.709958
2557 01:02:47.710073
2558 01:02:47.713698 Write Rank0 MR1 =0x56
2559 01:02:47.713802
2560 01:02:47.716684 best RODT dly(2T, 0.5T) = (2, 3)
2561 01:02:47.716774
2562 01:02:47.719963 best RODT dly(2T, 0.5T) = (2, 3)
2563 01:02:47.720039 ==
2564 01:02:47.722893 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2565 01:02:47.726300 fsp= 1, odt_onoff= 1, Byte mode= 0
2566 01:02:47.726376 ==
2567 01:02:47.729740 Start DQ dly to find pass range UseTestEngine =0
2568 01:02:47.736221 x-axis: bit #, y-axis: DQ dly (-127~63)
2569 01:02:47.736296 RX Vref Scan = 0
2570 01:02:47.739629 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2571 01:02:47.743031 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2572 01:02:47.746487 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2573 01:02:47.749479 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2574 01:02:47.749619 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2575 01:02:47.752746 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2576 01:02:47.756105 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2577 01:02:47.759606 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2578 01:02:47.762686 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2579 01:02:47.765988 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2580 01:02:47.769709 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2581 01:02:47.772905 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2582 01:02:47.772976 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2583 01:02:47.776172 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2584 01:02:47.779708 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2585 01:02:47.783042 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2586 01:02:47.786434 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2587 01:02:47.789404 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2588 01:02:47.792609 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2589 01:02:47.796433 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2590 01:02:47.796510 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2591 01:02:47.799641 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2592 01:02:47.803053 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2593 01:02:47.805836 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2594 01:02:47.809305 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2595 01:02:47.812884 -1, [0] xxxxxxxx xxxxxxxx [MSB]
2596 01:02:47.816193 0, [0] xxxxxxxx xxxxxxxo [MSB]
2597 01:02:47.816296 1, [0] xxxxxxxx xxxxxxxo [MSB]
2598 01:02:47.819405 2, [0] xxxxxxxx xxxxxxxo [MSB]
2599 01:02:47.822799 3, [0] xxxoxxxx ooxxxxxo [MSB]
2600 01:02:47.825924 4, [0] xxxoxxxx ooxxxxxo [MSB]
2601 01:02:47.829846 5, [0] xxxoxxxx ooxxxxxo [MSB]
2602 01:02:47.829946 6, [0] xoooxxxo oooxxxxo [MSB]
2603 01:02:47.833000 7, [0] xooooxxo oooxoxoo [MSB]
2604 01:02:47.835924 31, [0] oooooooo ooooooox [MSB]
2605 01:02:47.839269 32, [0] oooooooo ooooooox [MSB]
2606 01:02:47.843178 33, [0] oooooooo ooooooox [MSB]
2607 01:02:47.845938 34, [0] oooooooo oxooooox [MSB]
2608 01:02:47.849416 35, [0] ooxxoooo xxooooox [MSB]
2609 01:02:47.849486 36, [0] ooxxoooo xxooooox [MSB]
2610 01:02:47.852769 37, [0] ooxxxooo xxxoooox [MSB]
2611 01:02:47.856328 38, [0] ooxxxooo xxxxoxxx [MSB]
2612 01:02:47.859237 39, [0] oxxxxoox xxxxxxxx [MSB]
2613 01:02:47.862499 40, [0] oxxxxxox xxxxxxxx [MSB]
2614 01:02:47.866192 41, [0] xxxxxxxx xxxxxxxx [MSB]
2615 01:02:47.869016 iDelay=41, Bit 0, Center 24 (8 ~ 40) 33
2616 01:02:47.872424 iDelay=41, Bit 1, Center 22 (6 ~ 38) 33
2617 01:02:47.876048 iDelay=41, Bit 2, Center 20 (6 ~ 34) 29
2618 01:02:47.879429 iDelay=41, Bit 3, Center 18 (3 ~ 34) 32
2619 01:02:47.882740 iDelay=41, Bit 4, Center 21 (7 ~ 36) 30
2620 01:02:47.885730 iDelay=41, Bit 5, Center 23 (8 ~ 39) 32
2621 01:02:47.889500 iDelay=41, Bit 6, Center 24 (8 ~ 40) 33
2622 01:02:47.892758 iDelay=41, Bit 7, Center 22 (6 ~ 38) 33
2623 01:02:47.896118 iDelay=41, Bit 8, Center 18 (3 ~ 34) 32
2624 01:02:47.898998 iDelay=41, Bit 9, Center 18 (3 ~ 33) 31
2625 01:02:47.902490 iDelay=41, Bit 10, Center 21 (6 ~ 36) 31
2626 01:02:47.909245 iDelay=41, Bit 11, Center 22 (8 ~ 37) 30
2627 01:02:47.912338 iDelay=41, Bit 12, Center 22 (7 ~ 38) 32
2628 01:02:47.916238 iDelay=41, Bit 13, Center 22 (8 ~ 37) 30
2629 01:02:47.919370 iDelay=41, Bit 14, Center 22 (7 ~ 37) 31
2630 01:02:47.922562 iDelay=41, Bit 15, Center 15 (0 ~ 30) 31
2631 01:02:47.922651 ==
2632 01:02:47.926254 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2633 01:02:47.929253 fsp= 1, odt_onoff= 1, Byte mode= 0
2634 01:02:47.929321 ==
2635 01:02:47.932869 DQS Delay:
2636 01:02:47.932945 DQS0 = 0, DQS1 = 0
2637 01:02:47.935957 DQM Delay:
2638 01:02:47.936025 DQM0 = 21, DQM1 = 20
2639 01:02:47.936081 DQ Delay:
2640 01:02:47.938913 DQ0 =24, DQ1 =22, DQ2 =20, DQ3 =18
2641 01:02:47.942505 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =22
2642 01:02:47.946533 DQ8 =18, DQ9 =18, DQ10 =21, DQ11 =22
2643 01:02:47.949178 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =15
2644 01:02:47.949271
2645 01:02:47.949329
2646 01:02:47.952474 DramC Write-DBI off
2647 01:02:47.952564 ==
2648 01:02:47.958909 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2649 01:02:47.962495 fsp= 1, odt_onoff= 1, Byte mode= 0
2650 01:02:47.962562 ==
2651 01:02:47.966097 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2652 01:02:47.966162
2653 01:02:47.968738 Begin, DQ Scan Range 927~1183
2654 01:02:47.968825
2655 01:02:47.968912
2656 01:02:47.972491 TX Vref Scan disable
2657 01:02:47.975389 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2658 01:02:47.979311 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2659 01:02:47.981935 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2660 01:02:47.985709 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2661 01:02:47.988720 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2662 01:02:47.992241 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2663 01:02:47.995642 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2664 01:02:47.998709 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2665 01:02:48.002292 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2666 01:02:48.005376 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2667 01:02:48.008925 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2668 01:02:48.012120 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2669 01:02:48.015368 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2670 01:02:48.018831 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2671 01:02:48.022224 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2672 01:02:48.028994 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2673 01:02:48.031906 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2674 01:02:48.035217 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2675 01:02:48.038434 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2676 01:02:48.041833 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2677 01:02:48.045360 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2678 01:02:48.048466 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2679 01:02:48.051767 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2680 01:02:48.054873 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2681 01:02:48.058567 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2682 01:02:48.061937 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2683 01:02:48.065269 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2684 01:02:48.068354 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2685 01:02:48.071705 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2686 01:02:48.078193 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2687 01:02:48.081491 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2688 01:02:48.085119 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2689 01:02:48.088476 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2690 01:02:48.091653 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2691 01:02:48.094653 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2692 01:02:48.098406 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2693 01:02:48.101815 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2694 01:02:48.104843 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2695 01:02:48.107903 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2696 01:02:48.111446 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2697 01:02:48.114738 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2698 01:02:48.118061 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2699 01:02:48.121255 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2700 01:02:48.124620 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2701 01:02:48.127999 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2702 01:02:48.131326 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2703 01:02:48.134702 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2704 01:02:48.137896 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
2705 01:02:48.141515 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
2706 01:02:48.147868 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
2707 01:02:48.151384 977 |3 6 17|[0] xxxxxxxx ooxxxxxo [MSB]
2708 01:02:48.154751 978 |3 6 18|[0] xxxxxxxx ooxxxxxo [MSB]
2709 01:02:48.158052 979 |3 6 19|[0] xxxxxxxx ooxxxxoo [MSB]
2710 01:02:48.161354 980 |3 6 20|[0] xxxxxxxx oooxoxoo [MSB]
2711 01:02:48.165005 981 |3 6 21|[0] xxxxxxxx oooooxoo [MSB]
2712 01:02:48.167793 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
2713 01:02:48.171279 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
2714 01:02:48.174863 984 |3 6 24|[0] xxxxxxxx oooooooo [MSB]
2715 01:02:48.177738 993 |3 6 33|[0] oooooooo ooooooox [MSB]
2716 01:02:48.184598 994 |3 6 34|[0] oooooooo ooooooox [MSB]
2717 01:02:48.187870 995 |3 6 35|[0] oooooooo ooooooox [MSB]
2718 01:02:48.191180 996 |3 6 36|[0] oooooooo xxxxxoxx [MSB]
2719 01:02:48.194640 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2720 01:02:48.197848 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2721 01:02:48.201070 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
2722 01:02:48.204396 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB]
2723 01:02:48.208062 1001 |3 6 41|[0] oooooooo xxxxxxxx [MSB]
2724 01:02:48.211162 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
2725 01:02:48.214054 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
2726 01:02:48.217677 1004 |3 6 44|[0] oooxoooo xxxxxxxx [MSB]
2727 01:02:48.220964 1005 |3 6 45|[0] oooxoooo xxxxxxxx [MSB]
2728 01:02:48.227514 1006 |3 6 46|[0] ooxxoooo xxxxxxxx [MSB]
2729 01:02:48.230862 1007 |3 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
2730 01:02:48.234265 Byte0, DQ PI dly=994, DQM PI dly= 994
2731 01:02:48.237190 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 34)
2732 01:02:48.237258
2733 01:02:48.240797 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 34)
2734 01:02:48.240884
2735 01:02:48.243985 Byte1, DQ PI dly=986, DQM PI dly= 986
2736 01:02:48.251103 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
2737 01:02:48.251197
2738 01:02:48.254150 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
2739 01:02:48.254214
2740 01:02:48.254268 ==
2741 01:02:48.260418 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2742 01:02:48.263785 fsp= 1, odt_onoff= 1, Byte mode= 0
2743 01:02:48.263872 ==
2744 01:02:48.267155 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2745 01:02:48.267247
2746 01:02:48.270650 Begin, DQ Scan Range 962~1026
2747 01:02:48.270749 Write Rank0 MR14 =0x0
2748 01:02:48.280440
2749 01:02:48.280573 CH=1, VrefRange= 0, VrefLevel = 0
2750 01:02:48.286680 TX Bit0 (987~1002) 16 994, Bit8 (980~992) 13 986,
2751 01:02:48.290092 TX Bit1 (986~1000) 15 993, Bit9 (980~991) 12 985,
2752 01:02:48.296924 TX Bit2 (985~1000) 16 992, Bit10 (983~993) 11 988,
2753 01:02:48.300119 TX Bit3 (982~995) 14 988, Bit11 (983~994) 12 988,
2754 01:02:48.303451 TX Bit4 (985~1001) 17 993, Bit12 (984~994) 11 989,
2755 01:02:48.309847 TX Bit5 (988~1001) 14 994, Bit13 (985~993) 9 989,
2756 01:02:48.313440 TX Bit6 (986~1001) 16 993, Bit14 (983~994) 12 988,
2757 01:02:48.320021 TX Bit7 (985~1001) 17 993, Bit15 (977~987) 11 982,
2758 01:02:48.320114
2759 01:02:48.320197 Write Rank0 MR14 =0x2
2760 01:02:48.329190
2761 01:02:48.329256 CH=1, VrefRange= 0, VrefLevel = 2
2762 01:02:48.335586 TX Bit0 (986~1003) 18 994, Bit8 (979~992) 14 985,
2763 01:02:48.338662 TX Bit1 (985~1001) 17 993, Bit9 (980~992) 13 986,
2764 01:02:48.345208 TX Bit2 (984~1001) 18 992, Bit10 (983~994) 12 988,
2765 01:02:48.349109 TX Bit3 (982~996) 15 989, Bit11 (983~996) 14 989,
2766 01:02:48.352341 TX Bit4 (985~1002) 18 993, Bit12 (983~995) 13 989,
2767 01:02:48.358818 TX Bit5 (987~1002) 16 994, Bit13 (984~993) 10 988,
2768 01:02:48.362100 TX Bit6 (986~1002) 17 994, Bit14 (983~995) 13 989,
2769 01:02:48.368670 TX Bit7 (985~1002) 18 993, Bit15 (975~988) 14 981,
2770 01:02:48.368741
2771 01:02:48.368799 Write Rank0 MR14 =0x4
2772 01:02:48.378591
2773 01:02:48.378673 CH=1, VrefRange= 0, VrefLevel = 4
2774 01:02:48.384872 TX Bit0 (986~1004) 19 995, Bit8 (978~993) 16 985,
2775 01:02:48.388215 TX Bit1 (985~1001) 17 993, Bit9 (978~992) 15 985,
2776 01:02:48.394552 TX Bit2 (984~1001) 18 992, Bit10 (983~995) 13 989,
2777 01:02:48.398486 TX Bit3 (982~997) 16 989, Bit11 (983~997) 15 990,
2778 01:02:48.401802 TX Bit4 (985~1003) 19 994, Bit12 (983~995) 13 989,
2779 01:02:48.408245 TX Bit5 (986~1003) 18 994, Bit13 (984~994) 11 989,
2780 01:02:48.411384 TX Bit6 (986~1003) 18 994, Bit14 (982~995) 14 988,
2781 01:02:48.418240 TX Bit7 (985~1002) 18 993, Bit15 (976~989) 14 982,
2782 01:02:48.418315
2783 01:02:48.418390 Write Rank0 MR14 =0x6
2784 01:02:48.427377
2785 01:02:48.427452 CH=1, VrefRange= 0, VrefLevel = 6
2786 01:02:48.434403 TX Bit0 (986~1005) 20 995, Bit8 (978~993) 16 985,
2787 01:02:48.437442 TX Bit1 (985~1002) 18 993, Bit9 (978~993) 16 985,
2788 01:02:48.444025 TX Bit2 (984~1002) 19 993, Bit10 (982~996) 15 989,
2789 01:02:48.447801 TX Bit3 (981~998) 18 989, Bit11 (982~998) 17 990,
2790 01:02:48.451018 TX Bit4 (985~1004) 20 994, Bit12 (983~996) 14 989,
2791 01:02:48.457644 TX Bit5 (986~1004) 19 995, Bit13 (984~995) 12 989,
2792 01:02:48.461556 TX Bit6 (985~1004) 20 994, Bit14 (982~996) 15 989,
2793 01:02:48.467575 TX Bit7 (985~1004) 20 994, Bit15 (976~990) 15 983,
2794 01:02:48.467652
2795 01:02:48.467711 Write Rank0 MR14 =0x8
2796 01:02:48.477020
2797 01:02:48.477095 CH=1, VrefRange= 0, VrefLevel = 8
2798 01:02:48.483770 TX Bit0 (986~1006) 21 996, Bit8 (977~994) 18 985,
2799 01:02:48.487190 TX Bit1 (985~1003) 19 994, Bit9 (978~993) 16 985,
2800 01:02:48.493911 TX Bit2 (983~1003) 21 993, Bit10 (982~997) 16 989,
2801 01:02:48.497314 TX Bit3 (980~999) 20 989, Bit11 (982~998) 17 990,
2802 01:02:48.500471 TX Bit4 (984~1004) 21 994, Bit12 (983~998) 16 990,
2803 01:02:48.507058 TX Bit5 (986~1004) 19 995, Bit13 (983~996) 14 989,
2804 01:02:48.510449 TX Bit6 (985~1004) 20 994, Bit14 (981~997) 17 989,
2805 01:02:48.516879 TX Bit7 (984~1004) 21 994, Bit15 (974~991) 18 982,
2806 01:02:48.516955
2807 01:02:48.517013 Write Rank0 MR14 =0xa
2808 01:02:48.526261
2809 01:02:48.529665 CH=1, VrefRange= 0, VrefLevel = 10
2810 01:02:48.533654 TX Bit0 (986~1006) 21 996, Bit8 (977~994) 18 985,
2811 01:02:48.536362 TX Bit1 (984~1003) 20 993, Bit9 (977~994) 18 985,
2812 01:02:48.543568 TX Bit2 (983~1003) 21 993, Bit10 (981~997) 17 989,
2813 01:02:48.546706 TX Bit3 (980~1000) 21 990, Bit11 (982~998) 17 990,
2814 01:02:48.549725 TX Bit4 (984~1005) 22 994, Bit12 (981~998) 18 989,
2815 01:02:48.556270 TX Bit5 (986~1005) 20 995, Bit13 (983~997) 15 990,
2816 01:02:48.559721 TX Bit6 (985~1005) 21 995, Bit14 (981~997) 17 989,
2817 01:02:48.566579 TX Bit7 (984~1005) 22 994, Bit15 (975~991) 17 983,
2818 01:02:48.566670
2819 01:02:48.566745 Write Rank0 MR14 =0xc
2820 01:02:48.576657
2821 01:02:48.580448 CH=1, VrefRange= 0, VrefLevel = 12
2822 01:02:48.583537 TX Bit0 (985~1006) 22 995, Bit8 (977~995) 19 986,
2823 01:02:48.586433 TX Bit1 (984~1004) 21 994, Bit9 (977~994) 18 985,
2824 01:02:48.592833 TX Bit2 (983~1004) 22 993, Bit10 (980~998) 19 989,
2825 01:02:48.595883 TX Bit3 (980~1000) 21 990, Bit11 (982~999) 18 990,
2826 01:02:48.599550 TX Bit4 (984~1006) 23 995, Bit12 (982~998) 17 990,
2827 01:02:48.605999 TX Bit5 (986~1006) 21 996, Bit13 (983~998) 16 990,
2828 01:02:48.609717 TX Bit6 (985~1006) 22 995, Bit14 (981~998) 18 989,
2829 01:02:48.615948 TX Bit7 (984~1006) 23 995, Bit15 (973~992) 20 982,
2830 01:02:48.616042
2831 01:02:48.616132 Write Rank0 MR14 =0xe
2832 01:02:48.625714
2833 01:02:48.625783 CH=1, VrefRange= 0, VrefLevel = 14
2834 01:02:48.632397 TX Bit0 (985~1006) 22 995, Bit8 (977~995) 19 986,
2835 01:02:48.635579 TX Bit1 (984~1005) 22 994, Bit9 (976~994) 19 985,
2836 01:02:48.642448 TX Bit2 (983~1005) 23 994, Bit10 (980~998) 19 989,
2837 01:02:48.645512 TX Bit3 (980~1000) 21 990, Bit11 (981~999) 19 990,
2838 01:02:48.652170 TX Bit4 (984~1006) 23 995, Bit12 (981~999) 19 990,
2839 01:02:48.655614 TX Bit5 (985~1006) 22 995, Bit13 (983~998) 16 990,
2840 01:02:48.659074 TX Bit6 (984~1006) 23 995, Bit14 (980~998) 19 989,
2841 01:02:48.665112 TX Bit7 (984~1006) 23 995, Bit15 (973~992) 20 982,
2842 01:02:48.665207
2843 01:02:48.665289 Write Rank0 MR14 =0x10
2844 01:02:48.675673
2845 01:02:48.679101 CH=1, VrefRange= 0, VrefLevel = 16
2846 01:02:48.682550 TX Bit0 (985~1007) 23 996, Bit8 (976~996) 21 986,
2847 01:02:48.685908 TX Bit1 (984~1006) 23 995, Bit9 (976~996) 21 986,
2848 01:02:48.692549 TX Bit2 (982~1005) 24 993, Bit10 (979~999) 21 989,
2849 01:02:48.695231 TX Bit3 (979~1001) 23 990, Bit11 (980~999) 20 989,
2850 01:02:48.702238 TX Bit4 (983~1006) 24 994, Bit12 (980~999) 20 989,
2851 01:02:48.706419 TX Bit5 (985~1006) 22 995, Bit13 (982~998) 17 990,
2852 01:02:48.708658 TX Bit6 (984~1006) 23 995, Bit14 (979~999) 21 989,
2853 01:02:48.715334 TX Bit7 (983~1006) 24 994, Bit15 (972~992) 21 982,
2854 01:02:48.715410
2855 01:02:48.715467 Write Rank0 MR14 =0x12
2856 01:02:48.725747
2857 01:02:48.729038 CH=1, VrefRange= 0, VrefLevel = 18
2858 01:02:48.732418 TX Bit0 (985~1007) 23 996, Bit8 (976~997) 22 986,
2859 01:02:48.735500 TX Bit1 (983~1006) 24 994, Bit9 (976~996) 21 986,
2860 01:02:48.742691 TX Bit2 (982~1006) 25 994, Bit10 (979~999) 21 989,
2861 01:02:48.745802 TX Bit3 (979~1002) 24 990, Bit11 (980~1000) 21 990,
2862 01:02:48.749137 TX Bit4 (983~1006) 24 994, Bit12 (980~999) 20 989,
2863 01:02:48.755597 TX Bit5 (985~1006) 22 995, Bit13 (981~999) 19 990,
2864 01:02:48.758973 TX Bit6 (984~1006) 23 995, Bit14 (979~999) 21 989,
2865 01:02:48.765707 TX Bit7 (983~1006) 24 994, Bit15 (973~993) 21 983,
2866 01:02:48.765783
2867 01:02:48.765841 Write Rank0 MR14 =0x14
2868 01:02:48.775538
2869 01:02:48.778974 CH=1, VrefRange= 0, VrefLevel = 20
2870 01:02:48.782090 TX Bit0 (984~1007) 24 995, Bit8 (976~997) 22 986,
2871 01:02:48.785378 TX Bit1 (983~1006) 24 994, Bit9 (975~996) 22 985,
2872 01:02:48.792098 TX Bit2 (982~1006) 25 994, Bit10 (979~999) 21 989,
2873 01:02:48.795406 TX Bit3 (979~1002) 24 990, Bit11 (980~1000) 21 990,
2874 01:02:48.802245 TX Bit4 (983~1006) 24 994, Bit12 (979~1000) 22 989,
2875 01:02:48.805506 TX Bit5 (985~1007) 23 996, Bit13 (981~999) 19 990,
2876 01:02:48.808721 TX Bit6 (984~1007) 24 995, Bit14 (978~999) 22 988,
2877 01:02:48.815405 TX Bit7 (983~1006) 24 994, Bit15 (972~993) 22 982,
2878 01:02:48.815481
2879 01:02:48.815540 Write Rank0 MR14 =0x16
2880 01:02:48.825804
2881 01:02:48.829148 CH=1, VrefRange= 0, VrefLevel = 22
2882 01:02:48.832281 TX Bit0 (984~1007) 24 995, Bit8 (975~998) 24 986,
2883 01:02:48.835899 TX Bit1 (983~1006) 24 994, Bit9 (975~998) 24 986,
2884 01:02:48.842294 TX Bit2 (981~1006) 26 993, Bit10 (978~1000) 23 989,
2885 01:02:48.845707 TX Bit3 (978~1003) 26 990, Bit11 (980~1000) 21 990,
2886 01:02:48.852584 TX Bit4 (983~1007) 25 995, Bit12 (979~1000) 22 989,
2887 01:02:48.855270 TX Bit5 (985~1007) 23 996, Bit13 (981~1000) 20 990,
2888 01:02:48.858697 TX Bit6 (984~1007) 24 995, Bit14 (978~1000) 23 989,
2889 01:02:48.865318 TX Bit7 (983~1007) 25 995, Bit15 (971~993) 23 982,
2890 01:02:48.865394
2891 01:02:48.868563 Write Rank0 MR14 =0x18
2892 01:02:48.876061
2893 01:02:48.879388 CH=1, VrefRange= 0, VrefLevel = 24
2894 01:02:48.882620 TX Bit0 (984~1007) 24 995, Bit8 (974~998) 25 986,
2895 01:02:48.886094 TX Bit1 (983~1006) 24 994, Bit9 (975~998) 24 986,
2896 01:02:48.892706 TX Bit2 (981~1006) 26 993, Bit10 (978~1000) 23 989,
2897 01:02:48.895965 TX Bit3 (978~1003) 26 990, Bit11 (979~1001) 23 990,
2898 01:02:48.902872 TX Bit4 (982~1007) 26 994, Bit12 (979~1000) 22 989,
2899 01:02:48.906211 TX Bit5 (985~1007) 23 996, Bit13 (980~1000) 21 990,
2900 01:02:48.909157 TX Bit6 (983~1007) 25 995, Bit14 (978~1000) 23 989,
2901 01:02:48.916005 TX Bit7 (982~1007) 26 994, Bit15 (972~995) 24 983,
2902 01:02:48.916074
2903 01:02:48.916131 Write Rank0 MR14 =0x1a
2904 01:02:48.925979
2905 01:02:48.929773 CH=1, VrefRange= 0, VrefLevel = 26
2906 01:02:48.932926 TX Bit0 (984~1007) 24 995, Bit8 (974~999) 26 986,
2907 01:02:48.935875 TX Bit1 (982~1007) 26 994, Bit9 (974~998) 25 986,
2908 01:02:48.943132 TX Bit2 (981~1006) 26 993, Bit10 (978~1000) 23 989,
2909 01:02:48.946381 TX Bit3 (978~1004) 27 991, Bit11 (979~1001) 23 990,
2910 01:02:48.952428 TX Bit4 (982~1007) 26 994, Bit12 (979~1000) 22 989,
2911 01:02:48.955927 TX Bit5 (984~1007) 24 995, Bit13 (980~1000) 21 990,
2912 01:02:48.959251 TX Bit6 (983~1007) 25 995, Bit14 (978~1000) 23 989,
2913 01:02:48.965702 TX Bit7 (982~1007) 26 994, Bit15 (971~995) 25 983,
2914 01:02:48.965771
2915 01:02:48.969083 Write Rank0 MR14 =0x1c
2916 01:02:48.976984
2917 01:02:48.980336 CH=1, VrefRange= 0, VrefLevel = 28
2918 01:02:48.983651 TX Bit0 (984~1008) 25 996, Bit8 (974~999) 26 986,
2919 01:02:48.986541 TX Bit1 (982~1007) 26 994, Bit9 (974~998) 25 986,
2920 01:02:48.993751 TX Bit2 (980~1007) 28 993, Bit10 (978~1000) 23 989,
2921 01:02:48.996638 TX Bit3 (978~1005) 28 991, Bit11 (978~1001) 24 989,
2922 01:02:49.003435 TX Bit4 (982~1007) 26 994, Bit12 (978~1001) 24 989,
2923 01:02:49.006879 TX Bit5 (984~1007) 24 995, Bit13 (979~1000) 22 989,
2924 01:02:49.010169 TX Bit6 (983~1008) 26 995, Bit14 (977~1001) 25 989,
2925 01:02:49.016951 TX Bit7 (982~1007) 26 994, Bit15 (970~996) 27 983,
2926 01:02:49.017025
2927 01:02:49.017079 Write Rank0 MR14 =0x1e
2928 01:02:49.027374
2929 01:02:49.030522 CH=1, VrefRange= 0, VrefLevel = 30
2930 01:02:49.033813 TX Bit0 (984~1008) 25 996, Bit8 (974~999) 26 986,
2931 01:02:49.037182 TX Bit1 (982~1007) 26 994, Bit9 (974~998) 25 986,
2932 01:02:49.043991 TX Bit2 (981~1007) 27 994, Bit10 (977~1001) 25 989,
2933 01:02:49.047255 TX Bit3 (978~1005) 28 991, Bit11 (978~1001) 24 989,
2934 01:02:49.053911 TX Bit4 (982~1007) 26 994, Bit12 (978~1000) 23 989,
2935 01:02:49.057167 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
2936 01:02:49.060289 TX Bit6 (982~1008) 27 995, Bit14 (977~1000) 24 988,
2937 01:02:49.067055 TX Bit7 (981~1007) 27 994, Bit15 (970~996) 27 983,
2938 01:02:49.067123
2939 01:02:49.067178 Write Rank0 MR14 =0x20
2940 01:02:49.077508
2941 01:02:49.081000 CH=1, VrefRange= 0, VrefLevel = 32
2942 01:02:49.084510 TX Bit0 (984~1008) 25 996, Bit8 (974~999) 26 986,
2943 01:02:49.087906 TX Bit1 (982~1007) 26 994, Bit9 (974~998) 25 986,
2944 01:02:49.094338 TX Bit2 (981~1007) 27 994, Bit10 (977~1001) 25 989,
2945 01:02:49.097922 TX Bit3 (978~1005) 28 991, Bit11 (978~1001) 24 989,
2946 01:02:49.104607 TX Bit4 (982~1007) 26 994, Bit12 (978~1000) 23 989,
2947 01:02:49.107912 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
2948 01:02:49.111084 TX Bit6 (982~1008) 27 995, Bit14 (977~1000) 24 988,
2949 01:02:49.117779 TX Bit7 (981~1007) 27 994, Bit15 (970~996) 27 983,
2950 01:02:49.117843
2951 01:02:49.117925 Write Rank0 MR14 =0x22
2952 01:02:49.128402
2953 01:02:49.131792 CH=1, VrefRange= 0, VrefLevel = 34
2954 01:02:49.135235 TX Bit0 (984~1008) 25 996, Bit8 (974~999) 26 986,
2955 01:02:49.138253 TX Bit1 (982~1007) 26 994, Bit9 (974~998) 25 986,
2956 01:02:49.145298 TX Bit2 (981~1007) 27 994, Bit10 (977~1001) 25 989,
2957 01:02:49.148612 TX Bit3 (978~1005) 28 991, Bit11 (978~1001) 24 989,
2958 01:02:49.151846 TX Bit4 (982~1007) 26 994, Bit12 (978~1000) 23 989,
2959 01:02:49.158497 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
2960 01:02:49.161687 TX Bit6 (982~1008) 27 995, Bit14 (977~1000) 24 988,
2961 01:02:49.168192 TX Bit7 (981~1007) 27 994, Bit15 (970~996) 27 983,
2962 01:02:49.168280
2963 01:02:49.168361 Write Rank0 MR14 =0x24
2964 01:02:49.178556
2965 01:02:49.182265 CH=1, VrefRange= 0, VrefLevel = 36
2966 01:02:49.185186 TX Bit0 (984~1008) 25 996, Bit8 (974~999) 26 986,
2967 01:02:49.188674 TX Bit1 (982~1007) 26 994, Bit9 (974~998) 25 986,
2968 01:02:49.195199 TX Bit2 (981~1007) 27 994, Bit10 (977~1001) 25 989,
2969 01:02:49.198546 TX Bit3 (978~1005) 28 991, Bit11 (978~1001) 24 989,
2970 01:02:49.205378 TX Bit4 (982~1007) 26 994, Bit12 (978~1000) 23 989,
2971 01:02:49.208457 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
2972 01:02:49.211695 TX Bit6 (982~1008) 27 995, Bit14 (977~1000) 24 988,
2973 01:02:49.218610 TX Bit7 (981~1007) 27 994, Bit15 (970~996) 27 983,
2974 01:02:49.218673
2975 01:02:49.218727
2976 01:02:49.222193 TX Vref found, early break! 383< 388
2977 01:02:49.225647 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =844/100 ps
2978 01:02:49.228438 u1DelayCellOfst[0]=5 cells (5 PI)
2979 01:02:49.231827 u1DelayCellOfst[1]=3 cells (3 PI)
2980 01:02:49.235316 u1DelayCellOfst[2]=3 cells (3 PI)
2981 01:02:49.238762 u1DelayCellOfst[3]=0 cells (0 PI)
2982 01:02:49.241705 u1DelayCellOfst[4]=3 cells (3 PI)
2983 01:02:49.245363 u1DelayCellOfst[5]=4 cells (4 PI)
2984 01:02:49.248207 u1DelayCellOfst[6]=4 cells (4 PI)
2985 01:02:49.252053 u1DelayCellOfst[7]=3 cells (3 PI)
2986 01:02:49.256171 Byte0, DQ PI dly=991, DQM PI dly= 993
2987 01:02:49.258315 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 31)
2988 01:02:49.258379
2989 01:02:49.261727 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 31)
2990 01:02:49.261797
2991 01:02:49.265785 u1DelayCellOfst[8]=3 cells (3 PI)
2992 01:02:49.268538 u1DelayCellOfst[9]=3 cells (3 PI)
2993 01:02:49.271782 u1DelayCellOfst[10]=6 cells (6 PI)
2994 01:02:49.274937 u1DelayCellOfst[11]=6 cells (6 PI)
2995 01:02:49.278272 u1DelayCellOfst[12]=6 cells (6 PI)
2996 01:02:49.281454 u1DelayCellOfst[13]=8 cells (7 PI)
2997 01:02:49.285117 u1DelayCellOfst[14]=5 cells (5 PI)
2998 01:02:49.288237 u1DelayCellOfst[15]=0 cells (0 PI)
2999 01:02:49.291621 Byte1, DQ PI dly=983, DQM PI dly= 986
3000 01:02:49.294650 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
3001 01:02:49.294726
3002 01:02:49.298302 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
3003 01:02:49.298392
3004 01:02:49.302183 Write Rank0 MR14 =0x1e
3005 01:02:49.302276
3006 01:02:49.304634 Final TX Range 0 Vref 30
3007 01:02:49.304696
3008 01:02:49.311207 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3009 01:02:49.311301
3010 01:02:49.317903 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3011 01:02:49.324614 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3012 01:02:49.331545 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3013 01:02:49.334542 Write Rank0 MR3 =0xb0
3014 01:02:49.334612 DramC Write-DBI on
3015 01:02:49.334668 ==
3016 01:02:49.341221 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3017 01:02:49.344305 fsp= 1, odt_onoff= 1, Byte mode= 0
3018 01:02:49.344374 ==
3019 01:02:49.347729 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3020 01:02:49.347815
3021 01:02:49.351167 Begin, DQ Scan Range 706~770
3022 01:02:49.351231
3023 01:02:49.351287
3024 01:02:49.354184 TX Vref Scan disable
3025 01:02:49.357600 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3026 01:02:49.360913 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3027 01:02:49.364550 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3028 01:02:49.367623 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3029 01:02:49.370763 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3030 01:02:49.374586 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3031 01:02:49.377894 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3032 01:02:49.381220 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3033 01:02:49.384402 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3034 01:02:49.388218 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3035 01:02:49.390819 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3036 01:02:49.394403 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3037 01:02:49.397782 718 |2 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
3038 01:02:49.400752 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3039 01:02:49.404570 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3040 01:02:49.407692 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3041 01:02:49.411217 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3042 01:02:49.417614 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3043 01:02:49.420910 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3044 01:02:49.424420 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3045 01:02:49.427550 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
3046 01:02:49.430884 727 |2 6 23|[0] xxxxxxxx oooooooo [MSB]
3047 01:02:49.437427 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3048 01:02:49.441179 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3049 01:02:49.444587 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3050 01:02:49.447614 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3051 01:02:49.451558 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3052 01:02:49.454519 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3053 01:02:49.457442 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3054 01:02:49.461615 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3055 01:02:49.464216 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
3056 01:02:49.467503 753 |2 6 49|[0] xxxxxxxx xxxxxxxx [MSB]
3057 01:02:49.470722 Byte0, DQ PI dly=740, DQM PI dly= 740
3058 01:02:49.474162 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 36)
3059 01:02:49.477898
3060 01:02:49.481120 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 36)
3061 01:02:49.481216
3062 01:02:49.484406 Byte1, DQ PI dly=731, DQM PI dly= 731
3063 01:02:49.487691 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
3064 01:02:49.487778
3065 01:02:49.494042 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
3066 01:02:49.494110
3067 01:02:49.497427 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3068 01:02:49.507361 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3069 01:02:49.514171 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3070 01:02:49.514244 Write Rank0 MR3 =0x30
3071 01:02:49.517801 DramC Write-DBI off
3072 01:02:49.517895
3073 01:02:49.517978 [DATLAT]
3074 01:02:49.520998 Freq=1600, CH1 RK0, use_rxtx_scan=0
3075 01:02:49.521089
3076 01:02:49.524256 DATLAT Default: 0xf
3077 01:02:49.524342 7, 0xFFFF, sum=0
3078 01:02:49.527844 8, 0xFFFF, sum=0
3079 01:02:49.528025 9, 0xFFFF, sum=0
3080 01:02:49.530714 10, 0xFFFF, sum=0
3081 01:02:49.530783 11, 0xFFFF, sum=0
3082 01:02:49.533827 12, 0xFFFF, sum=0
3083 01:02:49.533959 13, 0xFFFF, sum=0
3084 01:02:49.537476 14, 0x0, sum=1
3085 01:02:49.537567 15, 0x0, sum=2
3086 01:02:49.537651 16, 0x0, sum=3
3087 01:02:49.540523 17, 0x0, sum=4
3088 01:02:49.544157 pattern=2 first_step=14 total pass=5 best_step=16
3089 01:02:49.544251 ==
3090 01:02:49.550663 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3091 01:02:49.553888 fsp= 1, odt_onoff= 1, Byte mode= 0
3092 01:02:49.553978 ==
3093 01:02:49.557216 Start DQ dly to find pass range UseTestEngine =1
3094 01:02:49.560299 x-axis: bit #, y-axis: DQ dly (-127~63)
3095 01:02:49.563758 RX Vref Scan = 1
3096 01:02:49.677295
3097 01:02:49.677424 RX Vref found, early break!
3098 01:02:49.677510
3099 01:02:49.683887 Final RX Vref 12, apply to both rank0 and 1
3100 01:02:49.683959 ==
3101 01:02:49.687531 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3102 01:02:49.690556 fsp= 1, odt_onoff= 1, Byte mode= 0
3103 01:02:49.690623 ==
3104 01:02:49.690679 DQS Delay:
3105 01:02:49.694246 DQS0 = 0, DQS1 = 0
3106 01:02:49.694308 DQM Delay:
3107 01:02:49.697571 DQM0 = 21, DQM1 = 19
3108 01:02:49.697658 DQ Delay:
3109 01:02:49.700767 DQ0 =23, DQ1 =21, DQ2 =20, DQ3 =19
3110 01:02:49.703969 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =22
3111 01:02:49.706882 DQ8 =18, DQ9 =16, DQ10 =21, DQ11 =22
3112 01:02:49.710901 DQ12 =22, DQ13 =22, DQ14 =21, DQ15 =15
3113 01:02:49.710966
3114 01:02:49.711022
3115 01:02:49.711074
3116 01:02:49.713924 [DramC_TX_OE_Calibration] TA2
3117 01:02:49.717267 Original DQ_B0 (3 6) =30, OEN = 27
3118 01:02:49.720785 Original DQ_B1 (3 6) =30, OEN = 27
3119 01:02:49.723611 23, 0x0, End_B0=23 End_B1=23
3120 01:02:49.723678 24, 0x0, End_B0=24 End_B1=24
3121 01:02:49.727390 25, 0x0, End_B0=25 End_B1=25
3122 01:02:49.730689 26, 0x0, End_B0=26 End_B1=26
3123 01:02:49.733712 27, 0x0, End_B0=27 End_B1=27
3124 01:02:49.737105 28, 0x0, End_B0=28 End_B1=28
3125 01:02:49.737176 29, 0x0, End_B0=29 End_B1=29
3126 01:02:49.740968 30, 0x0, End_B0=30 End_B1=30
3127 01:02:49.743501 31, 0xFFFF, End_B0=30 End_B1=30
3128 01:02:49.750315 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3129 01:02:49.753650 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3130 01:02:49.753729
3131 01:02:49.753809
3132 01:02:49.756889 Write Rank0 MR23 =0x3f
3133 01:02:49.756967 [DQSOSC]
3134 01:02:49.766826 [DQSOSCAuto] RK0, (LSB)MR18= 0xbebe, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3135 01:02:49.773654 CH1_RK0: MR19=0x202, MR18=0xBEBE, DQSOSC=448, MR23=63, INC=12, DEC=18
3136 01:02:49.773733 Write Rank0 MR23 =0x3f
3137 01:02:49.773812 [DQSOSC]
3138 01:02:49.783878 [DQSOSCAuto] RK0, (LSB)MR18= 0xbcbc, (MSB)MR19= 0x202, tDQSOscB0 = 450 ps tDQSOscB1 = 450 ps
3139 01:02:49.787170 CH1 RK0: MR19=202, MR18=BCBC
3140 01:02:49.790243 [RankSwap] Rank num 2, (Multi 1), Rank 1
3141 01:02:49.790321 Write Rank0 MR2 =0xad
3142 01:02:49.793712 [Write Leveling]
3143 01:02:49.797150 delay byte0 byte1 byte2 byte3
3144 01:02:49.797227
3145 01:02:49.797306 10 0 0
3146 01:02:49.800157 11 0 0
3147 01:02:49.800235 12 0 0
3148 01:02:49.800313 13 0 0
3149 01:02:49.803645 14 0 0
3150 01:02:49.803724 15 0 0
3151 01:02:49.807227 16 0 0
3152 01:02:49.807307 17 0 0
3153 01:02:49.807385 18 0 0
3154 01:02:49.810277 19 0 0
3155 01:02:49.810356 20 0 0
3156 01:02:49.813608 21 0 0
3157 01:02:49.813687 22 0 0
3158 01:02:49.816576 23 0 0
3159 01:02:49.816655 24 0 0
3160 01:02:49.816734 25 0 0
3161 01:02:49.819967 26 0 0
3162 01:02:49.820046 27 0 0
3163 01:02:49.823334 28 0 0
3164 01:02:49.823413 29 0 0
3165 01:02:49.826533 30 0 0
3166 01:02:49.826613 31 0 0
3167 01:02:49.826692 32 0 ff
3168 01:02:49.829732 33 0 ff
3169 01:02:49.829811 34 0 ff
3170 01:02:49.833545 35 0 ff
3171 01:02:49.833624 36 0 ff
3172 01:02:49.836449 37 ff ff
3173 01:02:49.836528 38 0 ff
3174 01:02:49.839780 39 ff ff
3175 01:02:49.839859 40 ff ff
3176 01:02:49.839937 41 ff ff
3177 01:02:49.843147 42 ff ff
3178 01:02:49.843226 43 ff ff
3179 01:02:49.846811 44 ff ff
3180 01:02:49.846890 45 ff ff
3181 01:02:49.852927 pass bytecount = 0xff (0xff: all bytes pass)
3182 01:02:49.853005
3183 01:02:49.853083 DQS0 dly: 39
3184 01:02:49.853155 DQS1 dly: 32
3185 01:02:49.856205 Write Rank0 MR2 =0x2d
3186 01:02:49.859542 [RankSwap] Rank num 2, (Multi 1), Rank 0
3187 01:02:49.862814 Write Rank1 MR1 =0xd6
3188 01:02:49.862892 [Gating]
3189 01:02:49.862968 ==
3190 01:02:49.866603 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3191 01:02:49.869588 fsp= 1, odt_onoff= 1, Byte mode= 0
3192 01:02:49.873085 ==
3193 01:02:49.876528 3 1 0 |3534 3434 |(11 11)(10 10) |(0 0)(0 0)| 0
3194 01:02:49.879941 3 1 4 |3534 302f |(11 11)(11 11) |(1 1)(1 1)| 0
3195 01:02:49.882685 3 1 8 |3534 808 |(11 11)(1 1) |(1 1)(0 0)| 0
3196 01:02:49.889616 3 1 12 |3534 3232 |(11 11)(11 11) |(1 1)(0 0)| 0
3197 01:02:49.892918 3 1 16 |3534 d0c |(11 11)(11 11) |(1 1)(1 1)| 0
3198 01:02:49.896415 3 1 20 |3534 808 |(11 11)(11 11) |(0 1)(1 0)| 0
3199 01:02:49.902699 3 1 24 |3534 302f |(11 11)(11 11) |(0 1)(0 1)| 0
3200 01:02:49.906138 3 1 28 |3534 3232 |(11 11)(10 10) |(0 1)(1 1)| 0
3201 01:02:49.909521 3 2 0 |3534 201 |(11 11)(11 11) |(0 1)(0 1)| 0
3202 01:02:49.913150 3 2 4 |3534 3231 |(11 11)(11 11) |(0 1)(0 1)| 0
3203 01:02:49.919248 3 2 8 |3534 2d2d |(11 11)(11 11) |(0 1)(0 1)| 0
3204 01:02:49.922532 3 2 12 |201 1918 |(11 11)(11 11) |(1 1)(0 1)| 0
3205 01:02:49.925686 3 2 16 |3d3d 201f |(11 11)(1 11) |(1 1)(0 1)| 0
3206 01:02:49.932315 3 2 20 |3d3d 605 |(11 11)(11 11) |(1 1)(1 1)| 0
3207 01:02:49.935739 3 2 24 |3d3d 606 |(11 11)(11 11) |(1 1)(1 1)| 0
3208 01:02:49.939620 3 2 28 |3d3d 1b1a |(11 11)(11 11) |(1 1)(1 1)| 0
3209 01:02:49.943084 [Byte 1] Lead/lag Transition tap number (1)
3210 01:02:49.948987 3 3 0 |3d3d 403 |(11 11)(11 11) |(1 1)(0 0)| 0
3211 01:02:49.952380 3 3 4 |3d3d 3737 |(11 11)(11 11) |(1 1)(1 1)| 0
3212 01:02:49.955553 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3213 01:02:49.962772 3 3 12 |3d3d 3837 |(11 11)(11 11) |(1 1)(1 1)| 0
3214 01:02:49.965853 3 3 16 |0 3635 |(11 11)(11 11) |(1 1)(1 1)| 0
3215 01:02:49.968996 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3216 01:02:49.975561 [Byte 0] Lead/lag falling Transition (3, 3, 20)
3217 01:02:49.978999 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3218 01:02:49.982305 [Byte 1] Lead/lag falling Transition (3, 3, 24)
3219 01:02:49.986015 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3220 01:02:49.992220 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3221 01:02:49.995739 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3222 01:02:49.998758 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3223 01:02:50.005580 3 4 12 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3224 01:02:50.008926 3 4 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3225 01:02:50.012116 3 4 20 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3226 01:02:50.018946 3 4 24 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3227 01:02:50.022237 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3228 01:02:50.025571 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3229 01:02:50.028969 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3230 01:02:50.035488 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3231 01:02:50.038692 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3232 01:02:50.042145 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3233 01:02:50.048605 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3234 01:02:50.052261 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3235 01:02:50.055572 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3236 01:02:50.062201 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3237 01:02:50.066014 [Byte 0] Lead/lag falling Transition (3, 6, 0)
3238 01:02:50.068883 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3239 01:02:50.072176 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3240 01:02:50.079352 [Byte 0] Lead/lag Transition tap number (3)
3241 01:02:50.082176 [Byte 1] Lead/lag falling Transition (3, 6, 8)
3242 01:02:50.085554 3 6 12 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3243 01:02:50.092516 3 6 16 |2828 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3244 01:02:50.095507 [Byte 1] Lead/lag Transition tap number (3)
3245 01:02:50.098778 3 6 20 |4646 3d3d |(0 0)(11 11) |(0 0)(0 0)| 0
3246 01:02:50.102083 [Byte 0]First pass (3, 6, 20)
3247 01:02:50.105364 3 6 24 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
3248 01:02:50.108830 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3249 01:02:50.111837 [Byte 1]First pass (3, 6, 28)
3250 01:02:50.115759 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3251 01:02:50.118747 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3252 01:02:50.125868 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3253 01:02:50.128789 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3254 01:02:50.132065 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3255 01:02:50.135267 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3256 01:02:50.141669 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3257 01:02:50.145129 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3258 01:02:50.148466 All bytes gating window > 1UI, Early break!
3259 01:02:50.148536
3260 01:02:50.151628 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
3261 01:02:50.151691
3262 01:02:50.155239 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 14)
3263 01:02:50.155301
3264 01:02:50.155353
3265 01:02:50.155404
3266 01:02:50.158478 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
3267 01:02:50.162067
3268 01:02:50.165546 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
3269 01:02:50.165632
3270 01:02:50.165711
3271 01:02:50.165792 Write Rank1 MR1 =0x56
3272 01:02:50.165870
3273 01:02:50.168422 best RODT dly(2T, 0.5T) = (2, 3)
3274 01:02:50.168506
3275 01:02:50.171849 best RODT dly(2T, 0.5T) = (2, 3)
3276 01:02:50.171914 ==
3277 01:02:50.178144 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3278 01:02:50.181844 fsp= 1, odt_onoff= 1, Byte mode= 0
3279 01:02:50.181933 ==
3280 01:02:50.185167 Start DQ dly to find pass range UseTestEngine =0
3281 01:02:50.187988 x-axis: bit #, y-axis: DQ dly (-127~63)
3282 01:02:50.191495 RX Vref Scan = 0
3283 01:02:50.194698 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3284 01:02:50.198109 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3285 01:02:50.198199 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3286 01:02:50.201383 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3287 01:02:50.204901 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3288 01:02:50.208150 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3289 01:02:50.211151 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3290 01:02:50.214968 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3291 01:02:50.217993 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3292 01:02:50.221517 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3293 01:02:50.221586 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3294 01:02:50.224885 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3295 01:02:50.227844 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3296 01:02:50.231114 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3297 01:02:50.234711 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3298 01:02:50.237856 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3299 01:02:50.241082 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3300 01:02:50.244694 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3301 01:02:50.244775 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3302 01:02:50.248203 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3303 01:02:50.251041 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3304 01:02:50.254405 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3305 01:02:50.257849 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3306 01:02:50.261246 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3307 01:02:50.264546 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3308 01:02:50.267988 -1, [0] xxxxxxxx xxxxxxxx [MSB]
3309 01:02:50.268067 0, [0] xxxxxxxx xxxxxxxx [MSB]
3310 01:02:50.271066 1, [0] xxxoxxxx xoxxxxxo [MSB]
3311 01:02:50.274387 2, [0] xxxoxxxx ooxxxxxo [MSB]
3312 01:02:50.277697 3, [0] xxxoxxxx ooxxxxxo [MSB]
3313 01:02:50.281144 4, [0] xxooxxxx ooxxxxxo [MSB]
3314 01:02:50.281224 5, [0] xxooxxxx oooxoxxo [MSB]
3315 01:02:50.284092 6, [0] xooooxxo oooooooo [MSB]
3316 01:02:50.287691 7, [0] xooooxxo oooooooo [MSB]
3317 01:02:50.291472 8, [0] xooooooo oooooooo [MSB]
3318 01:02:50.294471 31, [0] oooooooo ooooooox [MSB]
3319 01:02:50.297769 32, [0] oooooooo ooooooox [MSB]
3320 01:02:50.301075 33, [0] oooooooo ooooooox [MSB]
3321 01:02:50.301155 34, [0] oooooooo oxooooox [MSB]
3322 01:02:50.303856 35, [0] oooooooo xxooooox [MSB]
3323 01:02:50.307771 36, [0] ooxxoooo xxooooox [MSB]
3324 01:02:50.310837 37, [0] ooxxoooo xxooooox [MSB]
3325 01:02:50.313772 38, [0] ooxxxooo xxxoooox [MSB]
3326 01:02:50.317555 39, [0] ooxxxoox xxxxxxxx [MSB]
3327 01:02:50.320514 40, [0] oxxxxoox xxxxxxxx [MSB]
3328 01:02:50.320594 41, [0] xxxxxxox xxxxxxxx [MSB]
3329 01:02:50.324388 42, [0] xxxxxxxx xxxxxxxx [MSB]
3330 01:02:50.327379 iDelay=42, Bit 0, Center 24 (9 ~ 40) 32
3331 01:02:50.330869 iDelay=42, Bit 1, Center 22 (6 ~ 39) 34
3332 01:02:50.337583 iDelay=42, Bit 2, Center 19 (4 ~ 35) 32
3333 01:02:50.340466 iDelay=42, Bit 3, Center 18 (1 ~ 35) 35
3334 01:02:50.344171 iDelay=42, Bit 4, Center 21 (6 ~ 37) 32
3335 01:02:50.347509 iDelay=42, Bit 5, Center 24 (8 ~ 40) 33
3336 01:02:50.350690 iDelay=42, Bit 6, Center 24 (8 ~ 41) 34
3337 01:02:50.354099 iDelay=42, Bit 7, Center 22 (6 ~ 38) 33
3338 01:02:50.357389 iDelay=42, Bit 8, Center 18 (2 ~ 34) 33
3339 01:02:50.360803 iDelay=42, Bit 9, Center 17 (1 ~ 33) 33
3340 01:02:50.364235 iDelay=42, Bit 10, Center 21 (5 ~ 37) 33
3341 01:02:50.367597 iDelay=42, Bit 11, Center 22 (6 ~ 38) 33
3342 01:02:50.370725 iDelay=42, Bit 12, Center 21 (5 ~ 38) 34
3343 01:02:50.373868 iDelay=42, Bit 13, Center 22 (6 ~ 38) 33
3344 01:02:50.377688 iDelay=42, Bit 14, Center 22 (6 ~ 38) 33
3345 01:02:50.380326 iDelay=42, Bit 15, Center 15 (1 ~ 30) 30
3346 01:02:50.383860 ==
3347 01:02:50.386941 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3348 01:02:50.390867 fsp= 1, odt_onoff= 1, Byte mode= 0
3349 01:02:50.390959 ==
3350 01:02:50.391042 DQS Delay:
3351 01:02:50.394086 DQS0 = 0, DQS1 = 0
3352 01:02:50.394157 DQM Delay:
3353 01:02:50.397080 DQM0 = 21, DQM1 = 19
3354 01:02:50.397162 DQ Delay:
3355 01:02:50.400526 DQ0 =24, DQ1 =22, DQ2 =19, DQ3 =18
3356 01:02:50.403981 DQ4 =21, DQ5 =24, DQ6 =24, DQ7 =22
3357 01:02:50.407286 DQ8 =18, DQ9 =17, DQ10 =21, DQ11 =22
3358 01:02:50.410620 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =15
3359 01:02:50.410680
3360 01:02:50.410732
3361 01:02:50.413951 DramC Write-DBI off
3362 01:02:50.414070 ==
3363 01:02:50.417644 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3364 01:02:50.420316 fsp= 1, odt_onoff= 1, Byte mode= 0
3365 01:02:50.420398 ==
3366 01:02:50.423914 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3367 01:02:50.427465
3368 01:02:50.427554 Begin, DQ Scan Range 928~1184
3369 01:02:50.427640
3370 01:02:50.427717
3371 01:02:50.430562 TX Vref Scan disable
3372 01:02:50.433689 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3373 01:02:50.437072 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3374 01:02:50.440204 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3375 01:02:50.443590 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3376 01:02:50.447152 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3377 01:02:50.450630 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3378 01:02:50.457186 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3379 01:02:50.460258 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3380 01:02:50.463720 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3381 01:02:50.466805 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3382 01:02:50.470083 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3383 01:02:50.473952 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3384 01:02:50.477507 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3385 01:02:50.480012 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3386 01:02:50.483784 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3387 01:02:50.486898 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3388 01:02:50.490160 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3389 01:02:50.493217 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3390 01:02:50.496762 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3391 01:02:50.499920 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3392 01:02:50.503243 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3393 01:02:50.510106 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3394 01:02:50.513350 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3395 01:02:50.516801 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3396 01:02:50.519904 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3397 01:02:50.523303 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3398 01:02:50.526509 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3399 01:02:50.530221 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3400 01:02:50.533265 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3401 01:02:50.536932 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3402 01:02:50.540533 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3403 01:02:50.542963 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3404 01:02:50.546364 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3405 01:02:50.549798 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3406 01:02:50.553231 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3407 01:02:50.556876 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3408 01:02:50.559756 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3409 01:02:50.562861 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3410 01:02:50.566252 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3411 01:02:50.569505 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3412 01:02:50.576631 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3413 01:02:50.579762 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3414 01:02:50.582744 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3415 01:02:50.586343 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3416 01:02:50.589268 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3417 01:02:50.592757 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3418 01:02:50.596285 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
3419 01:02:50.599167 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
3420 01:02:50.602433 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
3421 01:02:50.605779 977 |3 6 17|[0] xxxxxxxx ooxxxxxo [MSB]
3422 01:02:50.609518 978 |3 6 18|[0] xxxxxxxx ooxxxxxo [MSB]
3423 01:02:50.612665 979 |3 6 19|[0] xxxxxxxx oooxxxxo [MSB]
3424 01:02:50.615999 980 |3 6 20|[0] xxxxxxxx ooooxxoo [MSB]
3425 01:02:50.619112 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
3426 01:02:50.622546 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
3427 01:02:50.625967 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
3428 01:02:50.632586 984 |3 6 24|[0] xxxxxxxx oooooooo [MSB]
3429 01:02:50.636048 994 |3 6 34|[0] oooooooo ooooooox [MSB]
3430 01:02:50.638899 995 |3 6 35|[0] oooooooo oxooooox [MSB]
3431 01:02:50.642156 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3432 01:02:50.646118 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3433 01:02:50.649077 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
3434 01:02:50.652098 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
3435 01:02:50.659220 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB]
3436 01:02:50.662247 1001 |3 6 41|[0] oooooooo xxxxxxxx [MSB]
3437 01:02:50.665784 1002 |3 6 42|[0] oooooooo xxxxxxxx [MSB]
3438 01:02:50.668793 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
3439 01:02:50.672361 1004 |3 6 44|[0] oooxoooo xxxxxxxx [MSB]
3440 01:02:50.675359 1005 |3 6 45|[0] oooxoooo xxxxxxxx [MSB]
3441 01:02:50.678588 1006 |3 6 46|[0] oooxoooo xxxxxxxx [MSB]
3442 01:02:50.682061 1007 |3 6 47|[0] xxxxoxxx xxxxxxxx [MSB]
3443 01:02:50.685329 1008 |3 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
3444 01:02:50.688715 Byte0, DQ PI dly=994, DQM PI dly= 994
3445 01:02:50.695341 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 34)
3446 01:02:50.695435
3447 01:02:50.698819 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 34)
3448 01:02:50.698986
3449 01:02:50.702113 Byte1, DQ PI dly=986, DQM PI dly= 986
3450 01:02:50.705066 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
3451 01:02:50.705160
3452 01:02:50.711880 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
3453 01:02:50.711975
3454 01:02:50.712058 ==
3455 01:02:50.714829 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3456 01:02:50.718546 fsp= 1, odt_onoff= 1, Byte mode= 0
3457 01:02:50.718616 ==
3458 01:02:50.724788 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3459 01:02:50.724875
3460 01:02:50.728381 Begin, DQ Scan Range 962~1026
3461 01:02:50.728468 Write Rank1 MR14 =0x0
3462 01:02:50.736782
3463 01:02:50.736872 CH=1, VrefRange= 0, VrefLevel = 0
3464 01:02:50.743364 TX Bit0 (989~1001) 13 995, Bit8 (980~991) 12 985,
3465 01:02:50.746655 TX Bit1 (987~1000) 14 993, Bit9 (980~990) 11 985,
3466 01:02:50.753610 TX Bit2 (984~1000) 17 992, Bit10 (982~993) 12 987,
3467 01:02:50.756552 TX Bit3 (983~996) 14 989, Bit11 (983~995) 13 989,
3468 01:02:50.760717 TX Bit4 (986~1002) 17 994, Bit12 (983~994) 12 988,
3469 01:02:50.766710 TX Bit5 (988~1000) 13 994, Bit13 (984~993) 10 988,
3470 01:02:50.770114 TX Bit6 (986~1001) 16 993, Bit14 (983~994) 12 988,
3471 01:02:50.776944 TX Bit7 (986~1001) 16 993, Bit15 (976~987) 12 981,
3472 01:02:50.777039
3473 01:02:50.777124 Write Rank1 MR14 =0x2
3474 01:02:50.786045
3475 01:02:50.786118 CH=1, VrefRange= 0, VrefLevel = 2
3476 01:02:50.792792 TX Bit0 (988~1002) 15 995, Bit8 (979~992) 14 985,
3477 01:02:50.795931 TX Bit1 (986~1001) 16 993, Bit9 (980~991) 12 985,
3478 01:02:50.802826 TX Bit2 (984~1000) 17 992, Bit10 (983~994) 12 988,
3479 01:02:50.806139 TX Bit3 (982~997) 16 989, Bit11 (983~996) 14 989,
3480 01:02:50.809014 TX Bit4 (986~1003) 18 994, Bit12 (983~994) 12 988,
3481 01:02:50.816413 TX Bit5 (987~1001) 15 994, Bit13 (984~994) 11 989,
3482 01:02:50.818995 TX Bit6 (986~1001) 16 993, Bit14 (983~994) 12 988,
3483 01:02:50.826050 TX Bit7 (986~1001) 16 993, Bit15 (975~989) 15 982,
3484 01:02:50.826122
3485 01:02:50.826179 Write Rank1 MR14 =0x4
3486 01:02:50.835358
3487 01:02:50.835426 CH=1, VrefRange= 0, VrefLevel = 4
3488 01:02:50.841825 TX Bit0 (987~1003) 17 995, Bit8 (978~992) 15 985,
3489 01:02:50.845452 TX Bit1 (986~1001) 16 993, Bit9 (979~992) 14 985,
3490 01:02:50.851472 TX Bit2 (984~1001) 18 992, Bit10 (982~995) 14 988,
3491 01:02:50.855002 TX Bit3 (982~998) 17 990, Bit11 (982~997) 16 989,
3492 01:02:50.858463 TX Bit4 (985~1004) 20 994, Bit12 (983~995) 13 989,
3493 01:02:50.864917 TX Bit5 (987~1002) 16 994, Bit13 (984~995) 12 989,
3494 01:02:50.868068 TX Bit6 (986~1002) 17 994, Bit14 (982~995) 14 988,
3495 01:02:50.874913 TX Bit7 (986~1002) 17 994, Bit15 (975~990) 16 982,
3496 01:02:50.874993
3497 01:02:50.875070 Write Rank1 MR14 =0x6
3498 01:02:50.884704
3499 01:02:50.884783 CH=1, VrefRange= 0, VrefLevel = 6
3500 01:02:50.891288 TX Bit0 (987~1004) 18 995, Bit8 (978~992) 15 985,
3501 01:02:50.894687 TX Bit1 (985~1002) 18 993, Bit9 (978~992) 15 985,
3502 01:02:50.901358 TX Bit2 (983~1001) 19 992, Bit10 (981~996) 16 988,
3503 01:02:50.904860 TX Bit3 (981~999) 19 990, Bit11 (982~998) 17 990,
3504 01:02:50.908145 TX Bit4 (985~1005) 21 995, Bit12 (983~996) 14 989,
3505 01:02:50.914498 TX Bit5 (986~1003) 18 994, Bit13 (983~996) 14 989,
3506 01:02:50.917781 TX Bit6 (985~1003) 19 994, Bit14 (982~996) 15 989,
3507 01:02:50.924242 TX Bit7 (985~1003) 19 994, Bit15 (975~991) 17 983,
3508 01:02:50.924320
3509 01:02:50.924398 Write Rank1 MR14 =0x8
3510 01:02:50.934305
3511 01:02:50.934390 CH=1, VrefRange= 0, VrefLevel = 8
3512 01:02:50.940560 TX Bit0 (987~1005) 19 996, Bit8 (977~993) 17 985,
3513 01:02:50.944027 TX Bit1 (986~1003) 18 994, Bit9 (978~992) 15 985,
3514 01:02:50.951016 TX Bit2 (984~1003) 20 993, Bit10 (981~997) 17 989,
3515 01:02:50.953676 TX Bit3 (981~1000) 20 990, Bit11 (982~998) 17 990,
3516 01:02:50.957408 TX Bit4 (985~1005) 21 995, Bit12 (982~997) 16 989,
3517 01:02:50.963660 TX Bit5 (986~1004) 19 995, Bit13 (983~996) 14 989,
3518 01:02:50.967238 TX Bit6 (985~1004) 20 994, Bit14 (982~997) 16 989,
3519 01:02:50.973681 TX Bit7 (985~1004) 20 994, Bit15 (975~991) 17 983,
3520 01:02:50.973760
3521 01:02:50.973851 Write Rank1 MR14 =0xa
3522 01:02:50.983708
3523 01:02:50.986906 CH=1, VrefRange= 0, VrefLevel = 10
3524 01:02:50.990549 TX Bit0 (986~1006) 21 996, Bit8 (977~993) 17 985,
3525 01:02:50.993504 TX Bit1 (985~1004) 20 994, Bit9 (978~992) 15 985,
3526 01:02:50.999958 TX Bit2 (983~1003) 21 993, Bit10 (981~997) 17 989,
3527 01:02:51.003255 TX Bit3 (981~1000) 20 990, Bit11 (982~999) 18 990,
3528 01:02:51.006638 TX Bit4 (985~1006) 22 995, Bit12 (982~998) 17 990,
3529 01:02:51.013378 TX Bit5 (986~1005) 20 995, Bit13 (983~998) 16 990,
3530 01:02:51.016509 TX Bit6 (985~1005) 21 995, Bit14 (981~997) 17 989,
3531 01:02:51.023392 TX Bit7 (985~1005) 21 995, Bit15 (974~992) 19 983,
3532 01:02:51.023472
3533 01:02:51.023548 Write Rank1 MR14 =0xc
3534 01:02:51.033096
3535 01:02:51.037082 CH=1, VrefRange= 0, VrefLevel = 12
3536 01:02:51.039898 TX Bit0 (986~1006) 21 996, Bit8 (977~994) 18 985,
3537 01:02:51.043068 TX Bit1 (985~1005) 21 995, Bit9 (977~993) 17 985,
3538 01:02:51.050426 TX Bit2 (983~1004) 22 993, Bit10 (980~997) 18 988,
3539 01:02:51.053434 TX Bit3 (980~1001) 22 990, Bit11 (981~999) 19 990,
3540 01:02:51.056650 TX Bit4 (985~1006) 22 995, Bit12 (982~998) 17 990,
3541 01:02:51.063379 TX Bit5 (986~1006) 21 996, Bit13 (982~998) 17 990,
3542 01:02:51.066776 TX Bit6 (985~1006) 22 995, Bit14 (981~998) 18 989,
3543 01:02:51.072924 TX Bit7 (985~1006) 22 995, Bit15 (973~992) 20 982,
3544 01:02:51.073001
3545 01:02:51.073060 Write Rank1 MR14 =0xe
3546 01:02:51.082742
3547 01:02:51.086410 CH=1, VrefRange= 0, VrefLevel = 14
3548 01:02:51.089415 TX Bit0 (986~1006) 21 996, Bit8 (976~994) 19 985,
3549 01:02:51.092953 TX Bit1 (985~1005) 21 995, Bit9 (977~993) 17 985,
3550 01:02:51.099591 TX Bit2 (983~1005) 23 994, Bit10 (980~998) 19 989,
3551 01:02:51.102901 TX Bit3 (980~1001) 22 990, Bit11 (981~1000) 20 990,
3552 01:02:51.105962 TX Bit4 (984~1006) 23 995, Bit12 (981~999) 19 990,
3553 01:02:51.113129 TX Bit5 (985~1006) 22 995, Bit13 (982~999) 18 990,
3554 01:02:51.116136 TX Bit6 (985~1006) 22 995, Bit14 (980~998) 19 989,
3555 01:02:51.122787 TX Bit7 (985~1006) 22 995, Bit15 (973~993) 21 983,
3556 01:02:51.122862
3557 01:02:51.122921 Write Rank1 MR14 =0x10
3558 01:02:51.133237
3559 01:02:51.136288 CH=1, VrefRange= 0, VrefLevel = 16
3560 01:02:51.139606 TX Bit0 (986~1006) 21 996, Bit8 (976~995) 20 985,
3561 01:02:51.143143 TX Bit1 (984~1006) 23 995, Bit9 (977~994) 18 985,
3562 01:02:51.149857 TX Bit2 (982~1006) 25 994, Bit10 (979~999) 21 989,
3563 01:02:51.153160 TX Bit3 (979~1002) 24 990, Bit11 (980~1000) 21 990,
3564 01:02:51.156642 TX Bit4 (984~1007) 24 995, Bit12 (981~999) 19 990,
3565 01:02:51.163183 TX Bit5 (985~1006) 22 995, Bit13 (982~999) 18 990,
3566 01:02:51.166618 TX Bit6 (984~1006) 23 995, Bit14 (980~999) 20 989,
3567 01:02:51.173122 TX Bit7 (984~1006) 23 995, Bit15 (973~993) 21 983,
3568 01:02:51.173201
3569 01:02:51.173278 Write Rank1 MR14 =0x12
3570 01:02:51.182884
3571 01:02:51.186224 CH=1, VrefRange= 0, VrefLevel = 18
3572 01:02:51.189925 TX Bit0 (986~1007) 22 996, Bit8 (976~995) 20 985,
3573 01:02:51.193220 TX Bit1 (984~1006) 23 995, Bit9 (976~994) 19 985,
3574 01:02:51.199723 TX Bit2 (981~1006) 26 993, Bit10 (979~999) 21 989,
3575 01:02:51.202978 TX Bit3 (979~1002) 24 990, Bit11 (980~1000) 21 990,
3576 01:02:51.209486 TX Bit4 (984~1007) 24 995, Bit12 (980~999) 20 989,
3577 01:02:51.212582 TX Bit5 (984~1007) 24 995, Bit13 (982~1000) 19 991,
3578 01:02:51.215921 TX Bit6 (984~1007) 24 995, Bit14 (980~999) 20 989,
3579 01:02:51.222591 TX Bit7 (984~1006) 23 995, Bit15 (972~994) 23 983,
3580 01:02:51.222672
3581 01:02:51.222748 Write Rank1 MR14 =0x14
3582 01:02:51.233072
3583 01:02:51.236704 CH=1, VrefRange= 0, VrefLevel = 20
3584 01:02:51.239758 TX Bit0 (985~1007) 23 996, Bit8 (976~996) 21 986,
3585 01:02:51.243596 TX Bit1 (984~1006) 23 995, Bit9 (976~995) 20 985,
3586 01:02:51.249726 TX Bit2 (981~1006) 26 993, Bit10 (979~999) 21 989,
3587 01:02:51.253177 TX Bit3 (979~1003) 25 991, Bit11 (979~1000) 22 989,
3588 01:02:51.256746 TX Bit4 (983~1007) 25 995, Bit12 (980~1000) 21 990,
3589 01:02:51.263299 TX Bit5 (984~1007) 24 995, Bit13 (981~1000) 20 990,
3590 01:02:51.266504 TX Bit6 (984~1007) 24 995, Bit14 (979~999) 21 989,
3591 01:02:51.273429 TX Bit7 (984~1006) 23 995, Bit15 (971~994) 24 982,
3592 01:02:51.273509
3593 01:02:51.273586 Write Rank1 MR14 =0x16
3594 01:02:51.283600
3595 01:02:51.286948 CH=1, VrefRange= 0, VrefLevel = 22
3596 01:02:51.290251 TX Bit0 (985~1007) 23 996, Bit8 (975~997) 23 986,
3597 01:02:51.293460 TX Bit1 (984~1007) 24 995, Bit9 (976~996) 21 986,
3598 01:02:51.299939 TX Bit2 (981~1006) 26 993, Bit10 (978~999) 22 988,
3599 01:02:51.303668 TX Bit3 (979~1004) 26 991, Bit11 (979~1001) 23 990,
3600 01:02:51.306724 TX Bit4 (983~1007) 25 995, Bit12 (980~1000) 21 990,
3601 01:02:51.313438 TX Bit5 (984~1007) 24 995, Bit13 (981~1000) 20 990,
3602 01:02:51.316653 TX Bit6 (983~1007) 25 995, Bit14 (979~999) 21 989,
3603 01:02:51.323260 TX Bit7 (984~1007) 24 995, Bit15 (971~994) 24 982,
3604 01:02:51.323338
3605 01:02:51.323415 Write Rank1 MR14 =0x18
3606 01:02:51.333890
3607 01:02:51.336760 CH=1, VrefRange= 0, VrefLevel = 24
3608 01:02:51.340893 TX Bit0 (985~1007) 23 996, Bit8 (974~998) 25 986,
3609 01:02:51.343730 TX Bit1 (984~1007) 24 995, Bit9 (975~996) 22 985,
3610 01:02:51.350375 TX Bit2 (981~1006) 26 993, Bit10 (977~1000) 24 988,
3611 01:02:51.353550 TX Bit3 (979~1005) 27 992, Bit11 (978~1001) 24 989,
3612 01:02:51.360513 TX Bit4 (983~1007) 25 995, Bit12 (979~1000) 22 989,
3613 01:02:51.363918 TX Bit5 (984~1007) 24 995, Bit13 (981~1001) 21 991,
3614 01:02:51.367265 TX Bit6 (983~1007) 25 995, Bit14 (978~1000) 23 989,
3615 01:02:51.373354 TX Bit7 (984~1007) 24 995, Bit15 (971~995) 25 983,
3616 01:02:51.373431
3617 01:02:51.373489 Write Rank1 MR14 =0x1a
3618 01:02:51.384396
3619 01:02:51.387384 CH=1, VrefRange= 0, VrefLevel = 26
3620 01:02:51.390618 TX Bit0 (984~1007) 24 995, Bit8 (974~998) 25 986,
3621 01:02:51.393908 TX Bit1 (983~1007) 25 995, Bit9 (975~997) 23 986,
3622 01:02:51.400693 TX Bit2 (980~1007) 28 993, Bit10 (977~1000) 24 988,
3623 01:02:51.404257 TX Bit3 (979~1005) 27 992, Bit11 (979~1001) 23 990,
3624 01:02:51.410523 TX Bit4 (983~1008) 26 995, Bit12 (979~1000) 22 989,
3625 01:02:51.413698 TX Bit5 (984~1007) 24 995, Bit13 (980~1001) 22 990,
3626 01:02:51.417149 TX Bit6 (983~1007) 25 995, Bit14 (978~1000) 23 989,
3627 01:02:51.423865 TX Bit7 (983~1007) 25 995, Bit15 (971~995) 25 983,
3628 01:02:51.423941
3629 01:02:51.427289 Write Rank1 MR14 =0x1c
3630 01:02:51.434414
3631 01:02:51.437971 CH=1, VrefRange= 0, VrefLevel = 28
3632 01:02:51.441225 TX Bit0 (984~1008) 25 996, Bit8 (974~999) 26 986,
3633 01:02:51.444772 TX Bit1 (983~1007) 25 995, Bit9 (975~998) 24 986,
3634 01:02:51.451322 TX Bit2 (980~1007) 28 993, Bit10 (977~1000) 24 988,
3635 01:02:51.454476 TX Bit3 (978~1005) 28 991, Bit11 (977~1001) 25 989,
3636 01:02:51.461159 TX Bit4 (983~1008) 26 995, Bit12 (979~1001) 23 990,
3637 01:02:51.464472 TX Bit5 (984~1008) 25 996, Bit13 (979~1001) 23 990,
3638 01:02:51.467965 TX Bit6 (983~1008) 26 995, Bit14 (978~1000) 23 989,
3639 01:02:51.474259 TX Bit7 (983~1007) 25 995, Bit15 (970~995) 26 982,
3640 01:02:51.474357
3641 01:02:51.477711 Write Rank1 MR14 =0x1e
3642 01:02:51.485424
3643 01:02:51.488413 CH=1, VrefRange= 0, VrefLevel = 30
3644 01:02:51.492226 TX Bit0 (985~1008) 24 996, Bit8 (974~998) 25 986,
3645 01:02:51.495495 TX Bit1 (983~1007) 25 995, Bit9 (974~998) 25 986,
3646 01:02:51.501976 TX Bit2 (980~1007) 28 993, Bit10 (976~1001) 26 988,
3647 01:02:51.505290 TX Bit3 (978~1005) 28 991, Bit11 (978~1001) 24 989,
3648 01:02:51.511683 TX Bit4 (983~1008) 26 995, Bit12 (978~1001) 24 989,
3649 01:02:51.514852 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
3650 01:02:51.518406 TX Bit6 (982~1008) 27 995, Bit14 (977~1000) 24 988,
3651 01:02:51.525019 TX Bit7 (983~1007) 25 995, Bit15 (970~995) 26 982,
3652 01:02:51.525097
3653 01:02:51.525174 Write Rank1 MR14 =0x20
3654 01:02:51.536141
3655 01:02:51.539087 CH=1, VrefRange= 0, VrefLevel = 32
3656 01:02:51.542203 TX Bit0 (985~1008) 24 996, Bit8 (974~998) 25 986,
3657 01:02:51.545671 TX Bit1 (983~1007) 25 995, Bit9 (974~998) 25 986,
3658 01:02:51.552600 TX Bit2 (980~1007) 28 993, Bit10 (976~1001) 26 988,
3659 01:02:51.555743 TX Bit3 (978~1005) 28 991, Bit11 (978~1001) 24 989,
3660 01:02:51.562306 TX Bit4 (983~1008) 26 995, Bit12 (978~1001) 24 989,
3661 01:02:51.565598 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
3662 01:02:51.569058 TX Bit6 (982~1008) 27 995, Bit14 (977~1000) 24 988,
3663 01:02:51.575392 TX Bit7 (983~1007) 25 995, Bit15 (970~995) 26 982,
3664 01:02:51.575471
3665 01:02:51.575547 Write Rank1 MR14 =0x22
3666 01:02:51.586762
3667 01:02:51.589753 CH=1, VrefRange= 0, VrefLevel = 34
3668 01:02:51.593385 TX Bit0 (985~1008) 24 996, Bit8 (974~998) 25 986,
3669 01:02:51.596531 TX Bit1 (983~1007) 25 995, Bit9 (974~998) 25 986,
3670 01:02:51.603319 TX Bit2 (980~1007) 28 993, Bit10 (976~1001) 26 988,
3671 01:02:51.606246 TX Bit3 (978~1005) 28 991, Bit11 (978~1001) 24 989,
3672 01:02:51.612891 TX Bit4 (983~1008) 26 995, Bit12 (978~1001) 24 989,
3673 01:02:51.616082 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
3674 01:02:51.619328 TX Bit6 (982~1008) 27 995, Bit14 (977~1000) 24 988,
3675 01:02:51.626111 TX Bit7 (983~1007) 25 995, Bit15 (970~995) 26 982,
3676 01:02:51.626190
3677 01:02:51.629581 Write Rank1 MR14 =0x24
3678 01:02:51.637079
3679 01:02:51.640652 CH=1, VrefRange= 0, VrefLevel = 36
3680 01:02:51.643945 TX Bit0 (985~1008) 24 996, Bit8 (974~998) 25 986,
3681 01:02:51.647217 TX Bit1 (983~1007) 25 995, Bit9 (974~998) 25 986,
3682 01:02:51.653405 TX Bit2 (980~1007) 28 993, Bit10 (976~1001) 26 988,
3683 01:02:51.657080 TX Bit3 (978~1005) 28 991, Bit11 (978~1001) 24 989,
3684 01:02:51.663580 TX Bit4 (983~1008) 26 995, Bit12 (978~1001) 24 989,
3685 01:02:51.666692 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
3686 01:02:51.670661 TX Bit6 (982~1008) 27 995, Bit14 (977~1000) 24 988,
3687 01:02:51.676798 TX Bit7 (983~1007) 25 995, Bit15 (970~995) 26 982,
3688 01:02:51.676890
3689 01:02:51.676967 Write Rank1 MR14 =0x26
3690 01:02:51.687400
3691 01:02:51.691054 CH=1, VrefRange= 0, VrefLevel = 38
3692 01:02:51.694641 TX Bit0 (985~1008) 24 996, Bit8 (974~998) 25 986,
3693 01:02:51.697435 TX Bit1 (983~1007) 25 995, Bit9 (974~998) 25 986,
3694 01:02:51.703944 TX Bit2 (980~1007) 28 993, Bit10 (976~1001) 26 988,
3695 01:02:51.707663 TX Bit3 (978~1005) 28 991, Bit11 (978~1001) 24 989,
3696 01:02:51.714014 TX Bit4 (983~1008) 26 995, Bit12 (978~1001) 24 989,
3697 01:02:51.717190 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
3698 01:02:51.720595 TX Bit6 (982~1008) 27 995, Bit14 (977~1000) 24 988,
3699 01:02:51.727815 TX Bit7 (983~1007) 25 995, Bit15 (970~995) 26 982,
3700 01:02:51.727898
3701 01:02:51.727975
3702 01:02:51.730708 TX Vref found, early break! 374< 385
3703 01:02:51.734029 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =844/100 ps
3704 01:02:51.737555 u1DelayCellOfst[0]=5 cells (5 PI)
3705 01:02:51.740492 u1DelayCellOfst[1]=4 cells (4 PI)
3706 01:02:51.744598 u1DelayCellOfst[2]=2 cells (2 PI)
3707 01:02:51.747186 u1DelayCellOfst[3]=0 cells (0 PI)
3708 01:02:51.750600 u1DelayCellOfst[4]=4 cells (4 PI)
3709 01:02:51.753757 u1DelayCellOfst[5]=4 cells (4 PI)
3710 01:02:51.757108 u1DelayCellOfst[6]=4 cells (4 PI)
3711 01:02:51.760319 u1DelayCellOfst[7]=4 cells (4 PI)
3712 01:02:51.764255 Byte0, DQ PI dly=991, DQM PI dly= 993
3713 01:02:51.767264 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 31)
3714 01:02:51.767345
3715 01:02:51.770827 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 31)
3716 01:02:51.770906
3717 01:02:51.773901 u1DelayCellOfst[8]=4 cells (4 PI)
3718 01:02:51.777199 u1DelayCellOfst[9]=4 cells (4 PI)
3719 01:02:51.780983 u1DelayCellOfst[10]=6 cells (6 PI)
3720 01:02:51.783693 u1DelayCellOfst[11]=8 cells (7 PI)
3721 01:02:51.787388 u1DelayCellOfst[12]=8 cells (7 PI)
3722 01:02:51.790473 u1DelayCellOfst[13]=9 cells (8 PI)
3723 01:02:51.793603 u1DelayCellOfst[14]=6 cells (6 PI)
3724 01:02:51.797028 u1DelayCellOfst[15]=0 cells (0 PI)
3725 01:02:51.800438 Byte1, DQ PI dly=982, DQM PI dly= 986
3726 01:02:51.804084 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
3727 01:02:51.804168
3728 01:02:51.807213 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
3729 01:02:51.807291
3730 01:02:51.810430 Write Rank1 MR14 =0x1e
3731 01:02:51.810508
3732 01:02:51.813621 Final TX Range 0 Vref 30
3733 01:02:51.813699
3734 01:02:51.820280 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3735 01:02:51.820358
3736 01:02:51.826835 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3737 01:02:51.833296 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3738 01:02:51.840155 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3739 01:02:51.843445 Write Rank1 MR3 =0xb0
3740 01:02:51.843523 DramC Write-DBI on
3741 01:02:51.843599 ==
3742 01:02:51.849917 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3743 01:02:51.853434 fsp= 1, odt_onoff= 1, Byte mode= 0
3744 01:02:51.853513 ==
3745 01:02:51.856736 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3746 01:02:51.856813
3747 01:02:51.860098 Begin, DQ Scan Range 706~770
3748 01:02:51.860175
3749 01:02:51.860254
3750 01:02:51.863574 TX Vref Scan disable
3751 01:02:51.866570 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3752 01:02:51.869941 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3753 01:02:51.873004 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3754 01:02:51.876619 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3755 01:02:51.879649 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3756 01:02:51.883544 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3757 01:02:51.886665 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3758 01:02:51.889909 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3759 01:02:51.893447 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3760 01:02:51.896211 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3761 01:02:51.899819 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3762 01:02:51.902927 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3763 01:02:51.906494 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3764 01:02:51.909715 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3765 01:02:51.913005 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3766 01:02:51.916125 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3767 01:02:51.923336 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3768 01:02:51.926795 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3769 01:02:51.929443 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3770 01:02:51.932798 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3771 01:02:51.936214 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
3772 01:02:51.939384 727 |2 6 23|[0] xxxxxxxx oooooooo [MSB]
3773 01:02:51.946700 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3774 01:02:51.950101 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3775 01:02:51.953302 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3776 01:02:51.956765 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3777 01:02:51.959955 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3778 01:02:51.963304 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3779 01:02:51.966551 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3780 01:02:51.969758 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3781 01:02:51.973102 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
3782 01:02:51.976589 753 |2 6 49|[0] oooooooo xxxxxxxx [MSB]
3783 01:02:51.979902 754 |2 6 50|[0] xxxxxxxx xxxxxxxx [MSB]
3784 01:02:51.983228 Byte0, DQ PI dly=740, DQM PI dly= 740
3785 01:02:51.989998 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 36)
3786 01:02:51.990109
3787 01:02:51.993021 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 36)
3788 01:02:51.993101
3789 01:02:51.996205 Byte1, DQ PI dly=730, DQM PI dly= 730
3790 01:02:51.999547 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
3791 01:02:51.999626
3792 01:02:52.006252 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
3793 01:02:52.006331
3794 01:02:52.013193 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3795 01:02:52.019908 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3796 01:02:52.026038 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3797 01:02:52.026118 Write Rank1 MR3 =0x30
3798 01:02:52.029588 DramC Write-DBI off
3799 01:02:52.029687
3800 01:02:52.029781 [DATLAT]
3801 01:02:52.032756 Freq=1600, CH1 RK1, use_rxtx_scan=0
3802 01:02:52.032834
3803 01:02:52.036511 DATLAT Default: 0x10
3804 01:02:52.036589 7, 0xFFFF, sum=0
3805 01:02:52.039294 8, 0xFFFF, sum=0
3806 01:02:52.039370 9, 0xFFFF, sum=0
3807 01:02:52.042660 10, 0xFFFF, sum=0
3808 01:02:52.042740 11, 0xFFFF, sum=0
3809 01:02:52.046127 12, 0xFFFF, sum=0
3810 01:02:52.046247 13, 0xFFFF, sum=0
3811 01:02:52.049469 14, 0x0, sum=1
3812 01:02:52.049548 15, 0x0, sum=2
3813 01:02:52.049625 16, 0x0, sum=3
3814 01:02:52.053166 17, 0x0, sum=4
3815 01:02:52.055992 pattern=2 first_step=14 total pass=5 best_step=16
3816 01:02:52.056071 ==
3817 01:02:52.062617 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3818 01:02:52.065888 fsp= 1, odt_onoff= 1, Byte mode= 0
3819 01:02:52.065966 ==
3820 01:02:52.069631 Start DQ dly to find pass range UseTestEngine =1
3821 01:02:52.072570 x-axis: bit #, y-axis: DQ dly (-127~63)
3822 01:02:52.076304 RX Vref Scan = 0
3823 01:02:52.079511 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3824 01:02:52.079594 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3825 01:02:52.082880 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3826 01:02:52.086282 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3827 01:02:52.089168 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3828 01:02:52.092778 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3829 01:02:52.095778 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3830 01:02:52.099705 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3831 01:02:52.102533 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3832 01:02:52.102613 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3833 01:02:52.106339 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3834 01:02:52.109194 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3835 01:02:52.112951 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3836 01:02:52.116143 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3837 01:02:52.119349 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3838 01:02:52.122924 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3839 01:02:52.125967 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3840 01:02:52.126085 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3841 01:02:52.129594 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3842 01:02:52.132816 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3843 01:02:52.135939 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3844 01:02:52.139150 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3845 01:02:52.142349 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3846 01:02:52.145614 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3847 01:02:52.145693 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3848 01:02:52.149410 -1, [0] xxxxxxxx xxxxxxxx [MSB]
3849 01:02:52.153058 0, [0] xxxxxxxx xxxxxxxo [MSB]
3850 01:02:52.156153 1, [0] xxxxxxxx xoxxxxxo [MSB]
3851 01:02:52.159336 2, [0] xxxxxxxx xoxxxxxo [MSB]
3852 01:02:52.162609 3, [0] xxxoxxxx ooxxxxxo [MSB]
3853 01:02:52.162712 4, [0] xxooxxxx ooxxxxxo [MSB]
3854 01:02:52.166407 5, [0] xxooxxxx ooxxxxxo [MSB]
3855 01:02:52.169603 6, [0] xooooxxx ooxxoxxo [MSB]
3856 01:02:52.172953 7, [0] oooooxxx oooooooo [MSB]
3857 01:02:52.175930 8, [0] ooooooxo oooooooo [MSB]
3858 01:02:52.179259 31, [0] oooooooo ooooooox [MSB]
3859 01:02:52.182491 32, [0] oooooooo ooooooox [MSB]
3860 01:02:52.186089 33, [0] oooooooo oxooooox [MSB]
3861 01:02:52.189033 34, [0] oooooooo xxooooox [MSB]
3862 01:02:52.192420 35, [0] oooxoooo xxooooox [MSB]
3863 01:02:52.192500 36, [0] ooxxoooo xxooooox [MSB]
3864 01:02:52.196086 37, [0] ooxxoooo xxxoxoxx [MSB]
3865 01:02:52.199021 38, [0] ooxxxoox xxxoxxxx [MSB]
3866 01:02:52.202726 39, [0] oxxxxoox xxxxxxxx [MSB]
3867 01:02:52.205971 40, [0] xxxxxxox xxxxxxxx [MSB]
3868 01:02:52.209137 41, [0] xxxxxxxx xxxxxxxx [MSB]
3869 01:02:52.212818 iDelay=41, Bit 0, Center 23 (7 ~ 39) 33
3870 01:02:52.216036 iDelay=41, Bit 1, Center 22 (6 ~ 38) 33
3871 01:02:52.219486 iDelay=41, Bit 2, Center 19 (4 ~ 35) 32
3872 01:02:52.222665 iDelay=41, Bit 3, Center 18 (3 ~ 34) 32
3873 01:02:52.225976 iDelay=41, Bit 4, Center 21 (6 ~ 37) 32
3874 01:02:52.229201 iDelay=41, Bit 5, Center 23 (8 ~ 39) 32
3875 01:02:52.232410 iDelay=41, Bit 6, Center 24 (9 ~ 40) 32
3876 01:02:52.236065 iDelay=41, Bit 7, Center 22 (8 ~ 37) 30
3877 01:02:52.239593 iDelay=41, Bit 8, Center 18 (3 ~ 33) 31
3878 01:02:52.242797 iDelay=41, Bit 9, Center 16 (1 ~ 32) 32
3879 01:02:52.245961 iDelay=41, Bit 10, Center 21 (7 ~ 36) 30
3880 01:02:52.249193 iDelay=41, Bit 11, Center 22 (7 ~ 38) 32
3881 01:02:52.256613 iDelay=41, Bit 12, Center 21 (6 ~ 36) 31
3882 01:02:52.259154 iDelay=41, Bit 13, Center 22 (7 ~ 37) 31
3883 01:02:52.262621 iDelay=41, Bit 14, Center 21 (7 ~ 36) 30
3884 01:02:52.265992 iDelay=41, Bit 15, Center 15 (0 ~ 30) 31
3885 01:02:52.266085 ==
3886 01:02:52.269069 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3887 01:02:52.272665 fsp= 1, odt_onoff= 1, Byte mode= 0
3888 01:02:52.272743 ==
3889 01:02:52.275890 DQS Delay:
3890 01:02:52.275968 DQS0 = 0, DQS1 = 0
3891 01:02:52.278993 DQM Delay:
3892 01:02:52.279071 DQM0 = 21, DQM1 = 19
3893 01:02:52.279148 DQ Delay:
3894 01:02:52.282618 DQ0 =23, DQ1 =22, DQ2 =19, DQ3 =18
3895 01:02:52.285898 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =22
3896 01:02:52.289167 DQ8 =18, DQ9 =16, DQ10 =21, DQ11 =22
3897 01:02:52.292451 DQ12 =21, DQ13 =22, DQ14 =21, DQ15 =15
3898 01:02:52.292529
3899 01:02:52.292605
3900 01:02:52.295634
3901 01:02:52.295712 [DramC_TX_OE_Calibration] TA2
3902 01:02:52.299046 Original DQ_B0 (3 6) =30, OEN = 27
3903 01:02:52.302154 Original DQ_B1 (3 6) =30, OEN = 27
3904 01:02:52.305409 23, 0x0, End_B0=23 End_B1=23
3905 01:02:52.309283 24, 0x0, End_B0=24 End_B1=24
3906 01:02:52.312058 25, 0x0, End_B0=25 End_B1=25
3907 01:02:52.312137 26, 0x0, End_B0=26 End_B1=26
3908 01:02:52.316007 27, 0x0, End_B0=27 End_B1=27
3909 01:02:52.319185 28, 0x0, End_B0=28 End_B1=28
3910 01:02:52.322366 29, 0x0, End_B0=29 End_B1=29
3911 01:02:52.322495 30, 0x0, End_B0=30 End_B1=30
3912 01:02:52.325880 31, 0xFFFF, End_B0=30 End_B1=30
3913 01:02:52.332165 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3914 01:02:52.338920 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3915 01:02:52.338998
3916 01:02:52.339074
3917 01:02:52.339146 Write Rank1 MR23 =0x3f
3918 01:02:52.342020 [DQSOSC]
3919 01:02:52.348768 [DQSOSCAuto] RK1, (LSB)MR18= 0xd7d7, (MSB)MR19= 0x202, tDQSOscB0 = 433 ps tDQSOscB1 = 433 ps
3920 01:02:52.355791 CH1_RK1: MR19=0x202, MR18=0xD7D7, DQSOSC=433, MR23=63, INC=13, DEC=19
3921 01:02:52.355871 Write Rank1 MR23 =0x3f
3922 01:02:52.358608 [DQSOSC]
3923 01:02:52.365515 [DQSOSCAuto] RK1, (LSB)MR18= 0xd6d6, (MSB)MR19= 0x202, tDQSOscB0 = 433 ps tDQSOscB1 = 433 ps
3924 01:02:52.368602 CH1 RK1: MR19=202, MR18=D6D6
3925 01:02:52.372237 [RxdqsGatingPostProcess] freq 1600
3926 01:02:52.378365 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3927 01:02:52.378444 Rank: 0
3928 01:02:52.382008 best DQS0 dly(2T, 0.5T) = (2, 6)
3929 01:02:52.385344 best DQS1 dly(2T, 0.5T) = (2, 6)
3930 01:02:52.388715 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3931 01:02:52.391793 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3932 01:02:52.391871 Rank: 1
3933 01:02:52.395342 best DQS0 dly(2T, 0.5T) = (2, 6)
3934 01:02:52.398507 best DQS1 dly(2T, 0.5T) = (2, 6)
3935 01:02:52.401663 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3936 01:02:52.401741 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3937 01:02:52.408685 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3938 01:02:52.411515 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3939 01:02:52.414959 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3940 01:02:52.415039
3941 01:02:52.415116
3942 01:02:52.418372 [Calibration Summary] Freqency 1600
3943 01:02:52.421455 CH 0, Rank 0
3944 01:02:52.421530 All Pass.
3945 01:02:52.421644
3946 01:02:52.421702 CH 0, Rank 1
3947 01:02:52.424968 All Pass.
3948 01:02:52.425043
3949 01:02:52.425101 CH 1, Rank 0
3950 01:02:52.425155 All Pass.
3951 01:02:52.428232
3952 01:02:52.428328 CH 1, Rank 1
3953 01:02:52.428389 All Pass.
3954 01:02:52.428443
3955 01:02:52.435120 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3956 01:02:52.441693 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3957 01:02:52.448035 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3958 01:02:52.452037 Write Rank0 MR3 =0xb0
3959 01:02:52.458247 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3960 01:02:52.465193 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3961 01:02:52.471927 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3962 01:02:52.474454 Write Rank1 MR3 =0xb0
3963 01:02:52.481529 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3964 01:02:52.487958 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3965 01:02:52.494314 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3966 01:02:52.497749 Write Rank0 MR3 =0xb0
3967 01:02:52.504262 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3968 01:02:52.510888 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3969 01:02:52.517753 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3970 01:02:52.517830 Write Rank1 MR3 =0xb0
3971 01:02:52.521005 DramC Write-DBI on
3972 01:02:52.524240 [GetDramInforAfterCalByMRR] Vendor 6.
3973 01:02:52.527296 [GetDramInforAfterCalByMRR] Revision 505.
3974 01:02:52.527373 MR8 1111
3975 01:02:52.533790 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3976 01:02:52.533886 MR8 1111
3977 01:02:52.540516 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3978 01:02:52.540592 MR8 1111
3979 01:02:52.543659 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3980 01:02:52.547222 MR8 1111
3981 01:02:52.550936 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3982 01:02:52.560644 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3983 01:02:52.560717 Write Rank0 MR13 =0xd0
3984 01:02:52.564003 Write Rank1 MR13 =0xd0
3985 01:02:52.567126 Write Rank0 MR13 =0xd0
3986 01:02:52.567191 Write Rank1 MR13 =0xd0
3987 01:02:52.570206 Save calibration result to emmc
3988 01:02:52.570272
3989 01:02:52.570332
3990 01:02:52.573989 [DramcModeReg_Check] Freq_1600, FSP_1
3991 01:02:52.577244 FSP_1, CH_0, RK0
3992 01:02:52.577306 Write Rank0 MR13 =0xd8
3993 01:02:52.580584 MR12 = 0x60 (global = 0x60) match
3994 01:02:52.583522 MR14 = 0x20 (global = 0x20) match
3995 01:02:52.587107 FSP_1, CH_0, RK1
3996 01:02:52.587200 Write Rank1 MR13 =0xd8
3997 01:02:52.590033 MR12 = 0x5c (global = 0x5c) match
3998 01:02:52.593899 MR14 = 0x1e (global = 0x1e) match
3999 01:02:52.596998 FSP_1, CH_1, RK0
4000 01:02:52.597061 Write Rank0 MR13 =0xd8
4001 01:02:52.600048 MR12 = 0x5a (global = 0x5a) match
4002 01:02:52.603420 MR14 = 0x1e (global = 0x1e) match
4003 01:02:52.607051 FSP_1, CH_1, RK1
4004 01:02:52.607113 Write Rank1 MR13 =0xd8
4005 01:02:52.610423 MR12 = 0x60 (global = 0x60) match
4006 01:02:52.613524 MR14 = 0x1e (global = 0x1e) match
4007 01:02:52.613589
4008 01:02:52.619935 [MEM_TEST] 02: After DFS, before run time config
4009 01:02:52.626545 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4010 01:02:52.626615
4011 01:02:52.630279 [TA2_TEST]
4012 01:02:52.630349 === TA2 HW
4013 01:02:52.633160 TA2 PAT: XTALK
4014 01:02:52.636522 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
4015 01:02:52.639814 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
4016 01:02:52.646313 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
4017 01:02:52.649960 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
4018 01:02:52.650103
4019 01:02:52.650162
4020 01:02:52.652912 Settings after calibration
4021 01:02:52.652988
4022 01:02:52.656237 [DramcRunTimeConfig]
4023 01:02:52.659816 TransferPLLToSPMControl - MODE SW PHYPLL
4024 01:02:52.659893 TX_TRACKING: ON
4025 01:02:52.663024 RX_TRACKING: ON
4026 01:02:52.663100 HW_GATING: ON
4027 01:02:52.666524 HW_GATING DBG: OFF
4028 01:02:52.666600 ddr_geometry:1
4029 01:02:52.669558 ddr_geometry:1
4030 01:02:52.669633 ddr_geometry:1
4031 01:02:52.669694 ddr_geometry:1
4032 01:02:52.672837 ddr_geometry:1
4033 01:02:52.672912 ddr_geometry:1
4034 01:02:52.676152 ddr_geometry:1
4035 01:02:52.676228 ddr_geometry:1
4036 01:02:52.679795 High Freq DUMMY_READ_FOR_TRACKING: ON
4037 01:02:52.682807 ZQCS_ENABLE_LP4: OFF
4038 01:02:52.686208 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
4039 01:02:52.689571 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
4040 01:02:52.689648 SPM_CONTROL_AFTERK: ON
4041 01:02:52.692898 IMPEDANCE_TRACKING: ON
4042 01:02:52.692974 TEMP_SENSOR: ON
4043 01:02:52.696086 PER_BANK_REFRESH: ON
4044 01:02:52.696162 HW_SAVE_FOR_SR: ON
4045 01:02:52.699323 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4046 01:02:52.702950 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
4047 01:02:52.706412 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
4048 01:02:52.709577 Read ODT Tracking: ON
4049 01:02:52.712896 =========================
4050 01:02:52.712971
4051 01:02:52.713067 [TA2_TEST]
4052 01:02:52.713121 === TA2 HW
4053 01:02:52.719896 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
4054 01:02:52.722533 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
4055 01:02:52.729690 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
4056 01:02:52.733043 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
4057 01:02:52.733118
4058 01:02:52.736167 [MEM_TEST] 03: After run time config
4059 01:02:52.747494 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4060 01:02:52.750824 [complex_mem_test] start addr:0x40024000, len:131072
4061 01:02:52.955158 1st complex R/W mem test pass
4062 01:02:52.962161 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
4063 01:02:52.965039 sync preloader write leveling
4064 01:02:52.968490 sync preloader cbt_mr12
4065 01:02:52.971841 sync preloader cbt_clk_dly
4066 01:02:52.971916 sync preloader cbt_cmd_dly
4067 01:02:52.974935 sync preloader cbt_cs
4068 01:02:52.978546 sync preloader cbt_ca_perbit_delay
4069 01:02:52.978648 sync preloader clk_delay
4070 01:02:52.981704 sync preloader dqs_delay
4071 01:02:52.984994 sync preloader u1Gating2T_Save
4072 01:02:52.988558 sync preloader u1Gating05T_Save
4073 01:02:52.991630 sync preloader u1Gatingfine_tune_Save
4074 01:02:52.995159 sync preloader u1Gatingucpass_count_Save
4075 01:02:52.998268 sync preloader u1TxWindowPerbitVref_Save
4076 01:02:53.001634 sync preloader u1TxCenter_min_Save
4077 01:02:53.004949 sync preloader u1TxCenter_max_Save
4078 01:02:53.008191 sync preloader u1Txwin_center_Save
4079 01:02:53.011951 sync preloader u1Txfirst_pass_Save
4080 01:02:53.014763 sync preloader u1Txlast_pass_Save
4081 01:02:53.014839 sync preloader u1RxDatlat_Save
4082 01:02:53.021664 sync preloader u1RxWinPerbitVref_Save
4083 01:02:53.025108 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4084 01:02:53.028469 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4085 01:02:53.031541 sync preloader delay_cell_unit
4086 01:02:53.038000 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4087 01:02:53.041309 sync preloader write leveling
4088 01:02:53.041385 sync preloader cbt_mr12
4089 01:02:53.045077 sync preloader cbt_clk_dly
4090 01:02:53.047922 sync preloader cbt_cmd_dly
4091 01:02:53.047994 sync preloader cbt_cs
4092 01:02:53.051517 sync preloader cbt_ca_perbit_delay
4093 01:02:53.055004 sync preloader clk_delay
4094 01:02:53.057926 sync preloader dqs_delay
4095 01:02:53.061323 sync preloader u1Gating2T_Save
4096 01:02:53.061422 sync preloader u1Gating05T_Save
4097 01:02:53.064853 sync preloader u1Gatingfine_tune_Save
4098 01:02:53.067704 sync preloader u1Gatingucpass_count_Save
4099 01:02:53.074523 sync preloader u1TxWindowPerbitVref_Save
4100 01:02:53.074599 sync preloader u1TxCenter_min_Save
4101 01:02:53.077926 sync preloader u1TxCenter_max_Save
4102 01:02:53.081094 sync preloader u1Txwin_center_Save
4103 01:02:53.084932 sync preloader u1Txfirst_pass_Save
4104 01:02:53.087763 sync preloader u1Txlast_pass_Save
4105 01:02:53.091315 sync preloader u1RxDatlat_Save
4106 01:02:53.094723 sync preloader u1RxWinPerbitVref_Save
4107 01:02:53.097859 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4108 01:02:53.104343 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4109 01:02:53.104457 sync preloader delay_cell_unit
4110 01:02:53.111078 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4111 01:02:53.114526 sync preloader write leveling
4112 01:02:53.117546 sync preloader cbt_mr12
4113 01:02:53.121523 sync preloader cbt_clk_dly
4114 01:02:53.121599 sync preloader cbt_cmd_dly
4115 01:02:53.124631 sync preloader cbt_cs
4116 01:02:53.127690 sync preloader cbt_ca_perbit_delay
4117 01:02:53.130922 sync preloader clk_delay
4118 01:02:53.131021 sync preloader dqs_delay
4119 01:02:53.134292 sync preloader u1Gating2T_Save
4120 01:02:53.137796 sync preloader u1Gating05T_Save
4121 01:02:53.140928 sync preloader u1Gatingfine_tune_Save
4122 01:02:53.144040 sync preloader u1Gatingucpass_count_Save
4123 01:02:53.147730 sync preloader u1TxWindowPerbitVref_Save
4124 01:02:53.151239 sync preloader u1TxCenter_min_Save
4125 01:02:53.154424 sync preloader u1TxCenter_max_Save
4126 01:02:53.157852 sync preloader u1Txwin_center_Save
4127 01:02:53.160778 sync preloader u1Txfirst_pass_Save
4128 01:02:53.164459 sync preloader u1Txlast_pass_Save
4129 01:02:53.167360 sync preloader u1RxDatlat_Save
4130 01:02:53.170963 sync preloader u1RxWinPerbitVref_Save
4131 01:02:53.174537 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4132 01:02:53.177627 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4133 01:02:53.180988 sync preloader delay_cell_unit
4134 01:02:53.184656 just_for_test_dump_coreboot_params dump all params
4135 01:02:53.187701 dump source = 0x0
4136 01:02:53.187780 dump params frequency:1600
4137 01:02:53.190850 dump params rank number:2
4138 01:02:53.190927
4139 01:02:53.194151 dump params write leveling
4140 01:02:53.197128 write leveling[0][0][0] = 0x20
4141 01:02:53.201252 write leveling[0][0][1] = 0x18
4142 01:02:53.201329 write leveling[0][1][0] = 0x1e
4143 01:02:53.203866 write leveling[0][1][1] = 0x16
4144 01:02:53.207202 write leveling[1][0][0] = 0x23
4145 01:02:53.210595 write leveling[1][0][1] = 0x1f
4146 01:02:53.214134 write leveling[1][1][0] = 0x27
4147 01:02:53.217333 write leveling[1][1][1] = 0x20
4148 01:02:53.217432 dump params cbt_cs
4149 01:02:53.220426 cbt_cs[0][0] = 0x8
4150 01:02:53.220528 cbt_cs[0][1] = 0x8
4151 01:02:53.223735 cbt_cs[1][0] = 0xa
4152 01:02:53.223811 cbt_cs[1][1] = 0xa
4153 01:02:53.227262 dump params cbt_mr12
4154 01:02:53.227338 cbt_mr12[0][0] = 0x20
4155 01:02:53.230716 cbt_mr12[0][1] = 0x1c
4156 01:02:53.234039 cbt_mr12[1][0] = 0x1a
4157 01:02:53.234128 cbt_mr12[1][1] = 0x20
4158 01:02:53.236963 dump params tx window
4159 01:02:53.241059 tx_center_min[0][0][0] = 985
4160 01:02:53.241135 tx_center_max[0][0][0] = 992
4161 01:02:53.243706 tx_center_min[0][0][1] = 978
4162 01:02:53.247069 tx_center_max[0][0][1] = 984
4163 01:02:53.250399 tx_center_min[0][1][0] = 983
4164 01:02:53.253711 tx_center_max[0][1][0] = 991
4165 01:02:53.253810 tx_center_min[0][1][1] = 977
4166 01:02:53.257373 tx_center_max[0][1][1] = 983
4167 01:02:53.260630 tx_center_min[1][0][0] = 991
4168 01:02:53.263855 tx_center_max[1][0][0] = 996
4169 01:02:53.263955 tx_center_min[1][0][1] = 983
4170 01:02:53.267381 tx_center_max[1][0][1] = 990
4171 01:02:53.270782 tx_center_min[1][1][0] = 991
4172 01:02:53.273569 tx_center_max[1][1][0] = 996
4173 01:02:53.276882 tx_center_min[1][1][1] = 982
4174 01:02:53.276958 tx_center_max[1][1][1] = 990
4175 01:02:53.280824 dump params tx window
4176 01:02:53.283442 tx_win_center[0][0][0] = 991
4177 01:02:53.286754 tx_first_pass[0][0][0] = 979
4178 01:02:53.286830 tx_last_pass[0][0][0] = 1004
4179 01:02:53.290366 tx_win_center[0][0][1] = 991
4180 01:02:53.293744 tx_first_pass[0][0][1] = 979
4181 01:02:53.297289 tx_last_pass[0][0][1] = 1003
4182 01:02:53.300206 tx_win_center[0][0][2] = 992
4183 01:02:53.300274 tx_first_pass[0][0][2] = 979
4184 01:02:53.303442 tx_last_pass[0][0][2] = 1005
4185 01:02:53.306759 tx_win_center[0][0][3] = 985
4186 01:02:53.310168 tx_first_pass[0][0][3] = 974
4187 01:02:53.310258 tx_last_pass[0][0][3] = 996
4188 01:02:53.313612 tx_win_center[0][0][4] = 991
4189 01:02:53.317241 tx_first_pass[0][0][4] = 979
4190 01:02:53.320389 tx_last_pass[0][0][4] = 1003
4191 01:02:53.323711 tx_win_center[0][0][5] = 988
4192 01:02:53.323790 tx_first_pass[0][0][5] = 977
4193 01:02:53.326733 tx_last_pass[0][0][5] = 999
4194 01:02:53.329941 tx_win_center[0][0][6] = 989
4195 01:02:53.333497 tx_first_pass[0][0][6] = 978
4196 01:02:53.333604 tx_last_pass[0][0][6] = 1000
4197 01:02:53.337579 tx_win_center[0][0][7] = 990
4198 01:02:53.340326 tx_first_pass[0][0][7] = 979
4199 01:02:53.343355 tx_last_pass[0][0][7] = 1002
4200 01:02:53.346607 tx_win_center[0][0][8] = 978
4201 01:02:53.346748 tx_first_pass[0][0][8] = 967
4202 01:02:53.349854 tx_last_pass[0][0][8] = 989
4203 01:02:53.353470 tx_win_center[0][0][9] = 979
4204 01:02:53.356846 tx_first_pass[0][0][9] = 968
4205 01:02:53.360276 tx_last_pass[0][0][9] = 990
4206 01:02:53.360346 tx_win_center[0][0][10] = 984
4207 01:02:53.363645 tx_first_pass[0][0][10] = 973
4208 01:02:53.366607 tx_last_pass[0][0][10] = 996
4209 01:02:53.369947 tx_win_center[0][0][11] = 978
4210 01:02:53.373734 tx_first_pass[0][0][11] = 967
4211 01:02:53.373803 tx_last_pass[0][0][11] = 990
4212 01:02:53.376464 tx_win_center[0][0][12] = 980
4213 01:02:53.379965 tx_first_pass[0][0][12] = 968
4214 01:02:53.383184 tx_last_pass[0][0][12] = 992
4215 01:02:53.386818 tx_win_center[0][0][13] = 980
4216 01:02:53.386886 tx_first_pass[0][0][13] = 968
4217 01:02:53.390202 tx_last_pass[0][0][13] = 992
4218 01:02:53.393514 tx_win_center[0][0][14] = 980
4219 01:02:53.397039 tx_first_pass[0][0][14] = 968
4220 01:02:53.399922 tx_last_pass[0][0][14] = 992
4221 01:02:53.399997 tx_win_center[0][0][15] = 984
4222 01:02:53.403723 tx_first_pass[0][0][15] = 973
4223 01:02:53.406704 tx_last_pass[0][0][15] = 996
4224 01:02:53.410172 tx_win_center[0][1][0] = 991
4225 01:02:53.413176 tx_first_pass[0][1][0] = 979
4226 01:02:53.413253 tx_last_pass[0][1][0] = 1003
4227 01:02:53.416822 tx_win_center[0][1][1] = 989
4228 01:02:53.419945 tx_first_pass[0][1][1] = 978
4229 01:02:53.423322 tx_last_pass[0][1][1] = 1001
4230 01:02:53.426578 tx_win_center[0][1][2] = 990
4231 01:02:53.426654 tx_first_pass[0][1][2] = 979
4232 01:02:53.430427 tx_last_pass[0][1][2] = 1002
4233 01:02:53.433095 tx_win_center[0][1][3] = 983
4234 01:02:53.436236 tx_first_pass[0][1][3] = 972
4235 01:02:53.436332 tx_last_pass[0][1][3] = 995
4236 01:02:53.440142 tx_win_center[0][1][4] = 989
4237 01:02:53.443218 tx_first_pass[0][1][4] = 978
4238 01:02:53.446577 tx_last_pass[0][1][4] = 1001
4239 01:02:53.450068 tx_win_center[0][1][5] = 986
4240 01:02:53.450144 tx_first_pass[0][1][5] = 976
4241 01:02:53.453036 tx_last_pass[0][1][5] = 997
4242 01:02:53.456301 tx_win_center[0][1][6] = 988
4243 01:02:53.459605 tx_first_pass[0][1][6] = 977
4244 01:02:53.459700 tx_last_pass[0][1][6] = 999
4245 01:02:53.462907 tx_win_center[0][1][7] = 989
4246 01:02:53.466253 tx_first_pass[0][1][7] = 978
4247 01:02:53.469689 tx_last_pass[0][1][7] = 1001
4248 01:02:53.472946 tx_win_center[0][1][8] = 977
4249 01:02:53.473012 tx_first_pass[0][1][8] = 966
4250 01:02:53.476198 tx_last_pass[0][1][8] = 988
4251 01:02:53.479535 tx_win_center[0][1][9] = 978
4252 01:02:53.483371 tx_first_pass[0][1][9] = 967
4253 01:02:53.483462 tx_last_pass[0][1][9] = 989
4254 01:02:53.486771 tx_win_center[0][1][10] = 983
4255 01:02:53.489478 tx_first_pass[0][1][10] = 972
4256 01:02:53.493604 tx_last_pass[0][1][10] = 994
4257 01:02:53.496541 tx_win_center[0][1][11] = 977
4258 01:02:53.499628 tx_first_pass[0][1][11] = 966
4259 01:02:53.499704 tx_last_pass[0][1][11] = 989
4260 01:02:53.502722 tx_win_center[0][1][12] = 978
4261 01:02:53.506156 tx_first_pass[0][1][12] = 967
4262 01:02:53.509724 tx_last_pass[0][1][12] = 990
4263 01:02:53.513130 tx_win_center[0][1][13] = 978
4264 01:02:53.513200 tx_first_pass[0][1][13] = 967
4265 01:02:53.516206 tx_last_pass[0][1][13] = 989
4266 01:02:53.519181 tx_win_center[0][1][14] = 979
4267 01:02:53.522854 tx_first_pass[0][1][14] = 968
4268 01:02:53.526231 tx_last_pass[0][1][14] = 991
4269 01:02:53.526306 tx_win_center[0][1][15] = 982
4270 01:02:53.529764 tx_first_pass[0][1][15] = 970
4271 01:02:53.532636 tx_last_pass[0][1][15] = 994
4272 01:02:53.536147 tx_win_center[1][0][0] = 996
4273 01:02:53.539527 tx_first_pass[1][0][0] = 984
4274 01:02:53.539618 tx_last_pass[1][0][0] = 1008
4275 01:02:53.542749 tx_win_center[1][0][1] = 994
4276 01:02:53.546443 tx_first_pass[1][0][1] = 982
4277 01:02:53.549504 tx_last_pass[1][0][1] = 1007
4278 01:02:53.549596 tx_win_center[1][0][2] = 994
4279 01:02:53.552796 tx_first_pass[1][0][2] = 981
4280 01:02:53.556112 tx_last_pass[1][0][2] = 1007
4281 01:02:53.559309 tx_win_center[1][0][3] = 991
4282 01:02:53.562795 tx_first_pass[1][0][3] = 978
4283 01:02:53.562872 tx_last_pass[1][0][3] = 1005
4284 01:02:53.566249 tx_win_center[1][0][4] = 994
4285 01:02:53.569686 tx_first_pass[1][0][4] = 982
4286 01:02:53.572653 tx_last_pass[1][0][4] = 1007
4287 01:02:53.572731 tx_win_center[1][0][5] = 995
4288 01:02:53.576289 tx_first_pass[1][0][5] = 983
4289 01:02:53.579726 tx_last_pass[1][0][5] = 1008
4290 01:02:53.583021 tx_win_center[1][0][6] = 995
4291 01:02:53.586010 tx_first_pass[1][0][6] = 982
4292 01:02:53.586102 tx_last_pass[1][0][6] = 1008
4293 01:02:53.589711 tx_win_center[1][0][7] = 994
4294 01:02:53.592819 tx_first_pass[1][0][7] = 981
4295 01:02:53.595847 tx_last_pass[1][0][7] = 1007
4296 01:02:53.599526 tx_win_center[1][0][8] = 986
4297 01:02:53.599617 tx_first_pass[1][0][8] = 974
4298 01:02:53.602866 tx_last_pass[1][0][8] = 999
4299 01:02:53.605871 tx_win_center[1][0][9] = 986
4300 01:02:53.609605 tx_first_pass[1][0][9] = 974
4301 01:02:53.609695 tx_last_pass[1][0][9] = 998
4302 01:02:53.613033 tx_win_center[1][0][10] = 989
4303 01:02:53.615922 tx_first_pass[1][0][10] = 977
4304 01:02:53.619162 tx_last_pass[1][0][10] = 1001
4305 01:02:53.622544 tx_win_center[1][0][11] = 989
4306 01:02:53.625769 tx_first_pass[1][0][11] = 978
4307 01:02:53.625841 tx_last_pass[1][0][11] = 1001
4308 01:02:53.629404 tx_win_center[1][0][12] = 989
4309 01:02:53.632773 tx_first_pass[1][0][12] = 978
4310 01:02:53.635825 tx_last_pass[1][0][12] = 1000
4311 01:02:53.638925 tx_win_center[1][0][13] = 990
4312 01:02:53.639000 tx_first_pass[1][0][13] = 979
4313 01:02:53.642567 tx_last_pass[1][0][13] = 1001
4314 01:02:53.645830 tx_win_center[1][0][14] = 988
4315 01:02:53.648774 tx_first_pass[1][0][14] = 977
4316 01:02:53.652213 tx_last_pass[1][0][14] = 1000
4317 01:02:53.655442 tx_win_center[1][0][15] = 983
4318 01:02:53.655511 tx_first_pass[1][0][15] = 970
4319 01:02:53.658873 tx_last_pass[1][0][15] = 996
4320 01:02:53.662409 tx_win_center[1][1][0] = 996
4321 01:02:53.665697 tx_first_pass[1][1][0] = 985
4322 01:02:53.665771 tx_last_pass[1][1][0] = 1008
4323 01:02:53.669046 tx_win_center[1][1][1] = 995
4324 01:02:53.672055 tx_first_pass[1][1][1] = 983
4325 01:02:53.675578 tx_last_pass[1][1][1] = 1007
4326 01:02:53.678928 tx_win_center[1][1][2] = 993
4327 01:02:53.678998 tx_first_pass[1][1][2] = 980
4328 01:02:53.682129 tx_last_pass[1][1][2] = 1007
4329 01:02:53.685310 tx_win_center[1][1][3] = 991
4330 01:02:53.688731 tx_first_pass[1][1][3] = 978
4331 01:02:53.691822 tx_last_pass[1][1][3] = 1005
4332 01:02:53.691916 tx_win_center[1][1][4] = 995
4333 01:02:53.695941 tx_first_pass[1][1][4] = 983
4334 01:02:53.698965 tx_last_pass[1][1][4] = 1008
4335 01:02:53.701977 tx_win_center[1][1][5] = 995
4336 01:02:53.705505 tx_first_pass[1][1][5] = 983
4337 01:02:53.705595 tx_last_pass[1][1][5] = 1008
4338 01:02:53.708543 tx_win_center[1][1][6] = 995
4339 01:02:53.711644 tx_first_pass[1][1][6] = 982
4340 01:02:53.715404 tx_last_pass[1][1][6] = 1008
4341 01:02:53.715475 tx_win_center[1][1][7] = 995
4342 01:02:53.718523 tx_first_pass[1][1][7] = 983
4343 01:02:53.721997 tx_last_pass[1][1][7] = 1007
4344 01:02:53.725125 tx_win_center[1][1][8] = 986
4345 01:02:53.728442 tx_first_pass[1][1][8] = 974
4346 01:02:53.728508 tx_last_pass[1][1][8] = 998
4347 01:02:53.731932 tx_win_center[1][1][9] = 986
4348 01:02:53.734903 tx_first_pass[1][1][9] = 974
4349 01:02:53.738381 tx_last_pass[1][1][9] = 998
4350 01:02:53.742167 tx_win_center[1][1][10] = 988
4351 01:02:53.742239 tx_first_pass[1][1][10] = 976
4352 01:02:53.745156 tx_last_pass[1][1][10] = 1001
4353 01:02:53.748466 tx_win_center[1][1][11] = 989
4354 01:02:53.751666 tx_first_pass[1][1][11] = 978
4355 01:02:53.754898 tx_last_pass[1][1][11] = 1001
4356 01:02:53.754965 tx_win_center[1][1][12] = 989
4357 01:02:53.758363 tx_first_pass[1][1][12] = 978
4358 01:02:53.761634 tx_last_pass[1][1][12] = 1001
4359 01:02:53.765240 tx_win_center[1][1][13] = 990
4360 01:02:53.768453 tx_first_pass[1][1][13] = 979
4361 01:02:53.768520 tx_last_pass[1][1][13] = 1001
4362 01:02:53.772097 tx_win_center[1][1][14] = 988
4363 01:02:53.775343 tx_first_pass[1][1][14] = 977
4364 01:02:53.778321 tx_last_pass[1][1][14] = 1000
4365 01:02:53.782218 tx_win_center[1][1][15] = 982
4366 01:02:53.784926 tx_first_pass[1][1][15] = 970
4367 01:02:53.785001 tx_last_pass[1][1][15] = 995
4368 01:02:53.788681 dump params rx window
4369 01:02:53.791821 rx_firspass[0][0][0] = 9
4370 01:02:53.791897 rx_lastpass[0][0][0] = 37
4371 01:02:53.795082 rx_firspass[0][0][1] = 9
4372 01:02:53.798579 rx_lastpass[0][0][1] = 36
4373 01:02:53.798655 rx_firspass[0][0][2] = 11
4374 01:02:53.802138 rx_lastpass[0][0][2] = 37
4375 01:02:53.804908 rx_firspass[0][0][3] = 3
4376 01:02:53.808146 rx_lastpass[0][0][3] = 32
4377 01:02:53.808222 rx_firspass[0][0][4] = 10
4378 01:02:53.811496 rx_lastpass[0][0][4] = 36
4379 01:02:53.815007 rx_firspass[0][0][5] = 6
4380 01:02:53.815081 rx_lastpass[0][0][5] = 32
4381 01:02:53.818316 rx_firspass[0][0][6] = 7
4382 01:02:53.821952 rx_lastpass[0][0][6] = 35
4383 01:02:53.822064 rx_firspass[0][0][7] = 11
4384 01:02:53.825231 rx_lastpass[0][0][7] = 35
4385 01:02:53.828482 rx_firspass[0][0][8] = 3
4386 01:02:53.831368 rx_lastpass[0][0][8] = 31
4387 01:02:53.831443 rx_firspass[0][0][9] = 6
4388 01:02:53.834818 rx_lastpass[0][0][9] = 32
4389 01:02:53.838161 rx_firspass[0][0][10] = 11
4390 01:02:53.838236 rx_lastpass[0][0][10] = 39
4391 01:02:53.841875 rx_firspass[0][0][11] = 4
4392 01:02:53.845015 rx_lastpass[0][0][11] = 31
4393 01:02:53.848529 rx_firspass[0][0][12] = 6
4394 01:02:53.848604 rx_lastpass[0][0][12] = 34
4395 01:02:53.851389 rx_firspass[0][0][13] = 7
4396 01:02:53.854996 rx_lastpass[0][0][13] = 32
4397 01:02:53.858073 rx_firspass[0][0][14] = 7
4398 01:02:53.858149 rx_lastpass[0][0][14] = 35
4399 01:02:53.861563 rx_firspass[0][0][15] = 10
4400 01:02:53.864570 rx_lastpass[0][0][15] = 36
4401 01:02:53.864662 rx_firspass[0][1][0] = 9
4402 01:02:53.868097 rx_lastpass[0][1][0] = 39
4403 01:02:53.871154 rx_firspass[0][1][1] = 7
4404 01:02:53.874534 rx_lastpass[0][1][1] = 39
4405 01:02:53.874610 rx_firspass[0][1][2] = 9
4406 01:02:53.877922 rx_lastpass[0][1][2] = 39
4407 01:02:53.881498 rx_firspass[0][1][3] = 1
4408 01:02:53.881573 rx_lastpass[0][1][3] = 32
4409 01:02:53.884689 rx_firspass[0][1][4] = 9
4410 01:02:53.888121 rx_lastpass[0][1][4] = 37
4411 01:02:53.888196 rx_firspass[0][1][5] = 4
4412 01:02:53.891175 rx_lastpass[0][1][5] = 34
4413 01:02:53.894485 rx_firspass[0][1][6] = 5
4414 01:02:53.898247 rx_lastpass[0][1][6] = 35
4415 01:02:53.898322 rx_firspass[0][1][7] = 6
4416 01:02:53.901361 rx_lastpass[0][1][7] = 37
4417 01:02:53.904926 rx_firspass[0][1][8] = 1
4418 01:02:53.905001 rx_lastpass[0][1][8] = 32
4419 01:02:53.908074 rx_firspass[0][1][9] = 5
4420 01:02:53.911519 rx_lastpass[0][1][9] = 34
4421 01:02:53.914454 rx_firspass[0][1][10] = 11
4422 01:02:53.914529 rx_lastpass[0][1][10] = 41
4423 01:02:53.918223 rx_firspass[0][1][11] = 3
4424 01:02:53.921032 rx_lastpass[0][1][11] = 32
4425 01:02:53.921108 rx_firspass[0][1][12] = 5
4426 01:02:53.924233 rx_lastpass[0][1][12] = 35
4427 01:02:53.928174 rx_firspass[0][1][13] = 7
4428 01:02:53.931191 rx_lastpass[0][1][13] = 34
4429 01:02:53.931257 rx_firspass[0][1][14] = 7
4430 01:02:53.934460 rx_lastpass[0][1][14] = 37
4431 01:02:53.937821 rx_firspass[0][1][15] = 9
4432 01:02:53.940921 rx_lastpass[0][1][15] = 38
4433 01:02:53.940996 rx_firspass[1][0][0] = 8
4434 01:02:53.944498 rx_lastpass[1][0][0] = 37
4435 01:02:53.948006 rx_firspass[1][0][1] = 7
4436 01:02:53.948074 rx_lastpass[1][0][1] = 35
4437 01:02:53.950923 rx_firspass[1][0][2] = 5
4438 01:02:53.954173 rx_lastpass[1][0][2] = 35
4439 01:02:53.954238 rx_firspass[1][0][3] = 5
4440 01:02:53.957638 rx_lastpass[1][0][3] = 32
4441 01:02:53.960907 rx_firspass[1][0][4] = 7
4442 01:02:53.963995 rx_lastpass[1][0][4] = 36
4443 01:02:53.964060 rx_firspass[1][0][5] = 9
4444 01:02:53.968138 rx_lastpass[1][0][5] = 38
4445 01:02:53.971187 rx_firspass[1][0][6] = 11
4446 01:02:53.971254 rx_lastpass[1][0][6] = 37
4447 01:02:53.974071 rx_firspass[1][0][7] = 9
4448 01:02:53.977779 rx_lastpass[1][0][7] = 36
4449 01:02:53.977845 rx_firspass[1][0][8] = 5
4450 01:02:53.981069 rx_lastpass[1][0][8] = 32
4451 01:02:53.984384 rx_firspass[1][0][9] = 3
4452 01:02:53.987911 rx_lastpass[1][0][9] = 31
4453 01:02:53.987979 rx_firspass[1][0][10] = 6
4454 01:02:53.990773 rx_lastpass[1][0][10] = 36
4455 01:02:53.994014 rx_firspass[1][0][11] = 7
4456 01:02:53.994096 rx_lastpass[1][0][11] = 36
4457 01:02:53.997815 rx_firspass[1][0][12] = 9
4458 01:02:54.000825 rx_lastpass[1][0][12] = 35
4459 01:02:54.003903 rx_firspass[1][0][13] = 8
4460 01:02:54.003972 rx_lastpass[1][0][13] = 36
4461 01:02:54.007720 rx_firspass[1][0][14] = 8
4462 01:02:54.010962 rx_lastpass[1][0][14] = 34
4463 01:02:54.014294 rx_firspass[1][0][15] = 2
4464 01:02:54.014360 rx_lastpass[1][0][15] = 28
4465 01:02:54.017599 rx_firspass[1][1][0] = 7
4466 01:02:54.020544 rx_lastpass[1][1][0] = 39
4467 01:02:54.020611 rx_firspass[1][1][1] = 6
4468 01:02:54.023998 rx_lastpass[1][1][1] = 38
4469 01:02:54.028102 rx_firspass[1][1][2] = 4
4470 01:02:54.030951 rx_lastpass[1][1][2] = 35
4471 01:02:54.031015 rx_firspass[1][1][3] = 3
4472 01:02:54.034224 rx_lastpass[1][1][3] = 34
4473 01:02:54.037279 rx_firspass[1][1][4] = 6
4474 01:02:54.037362 rx_lastpass[1][1][4] = 37
4475 01:02:54.040445 rx_firspass[1][1][5] = 8
4476 01:02:54.043574 rx_lastpass[1][1][5] = 39
4477 01:02:54.043649 rx_firspass[1][1][6] = 9
4478 01:02:54.047292 rx_lastpass[1][1][6] = 40
4479 01:02:54.050601 rx_firspass[1][1][7] = 8
4480 01:02:54.053855 rx_lastpass[1][1][7] = 37
4481 01:02:54.053947 rx_firspass[1][1][8] = 3
4482 01:02:54.056952 rx_lastpass[1][1][8] = 33
4483 01:02:54.060512 rx_firspass[1][1][9] = 1
4484 01:02:54.060588 rx_lastpass[1][1][9] = 32
4485 01:02:54.063715 rx_firspass[1][1][10] = 7
4486 01:02:54.067143 rx_lastpass[1][1][10] = 36
4487 01:02:54.067219 rx_firspass[1][1][11] = 7
4488 01:02:54.070854 rx_lastpass[1][1][11] = 38
4489 01:02:54.074169 rx_firspass[1][1][12] = 6
4490 01:02:54.076842 rx_lastpass[1][1][12] = 36
4491 01:02:54.076933 rx_firspass[1][1][13] = 7
4492 01:02:54.080527 rx_lastpass[1][1][13] = 37
4493 01:02:54.083776 rx_firspass[1][1][14] = 7
4494 01:02:54.087083 rx_lastpass[1][1][14] = 36
4495 01:02:54.087158 rx_firspass[1][1][15] = 0
4496 01:02:54.090786 rx_lastpass[1][1][15] = 30
4497 01:02:54.093787 dump params clk_delay
4498 01:02:54.093863 clk_delay[0] = 0
4499 01:02:54.097261 clk_delay[1] = 0
4500 01:02:54.097336 dump params dqs_delay
4501 01:02:54.100284 dqs_delay[0][0] = 0
4502 01:02:54.100362 dqs_delay[0][1] = 0
4503 01:02:54.104106 dqs_delay[1][0] = 0
4504 01:02:54.104181 dqs_delay[1][1] = 0
4505 01:02:54.106889 dump params delay_cell_unit = 844
4506 01:02:54.110629 dump source = 0x0
4507 01:02:54.110704 dump params frequency:1200
4508 01:02:54.113759 dump params rank number:2
4509 01:02:54.113834
4510 01:02:54.117240 dump params write leveling
4511 01:02:54.120135 write leveling[0][0][0] = 0x0
4512 01:02:54.123513 write leveling[0][0][1] = 0x0
4513 01:02:54.123589 write leveling[0][1][0] = 0x0
4514 01:02:54.126828 write leveling[0][1][1] = 0x0
4515 01:02:54.130126 write leveling[1][0][0] = 0x0
4516 01:02:54.133852 write leveling[1][0][1] = 0x0
4517 01:02:54.136809 write leveling[1][1][0] = 0x0
4518 01:02:54.136885 write leveling[1][1][1] = 0x0
4519 01:02:54.140439 dump params cbt_cs
4520 01:02:54.140515 cbt_cs[0][0] = 0x0
4521 01:02:54.143441 cbt_cs[0][1] = 0x0
4522 01:02:54.146554 cbt_cs[1][0] = 0x0
4523 01:02:54.146628 cbt_cs[1][1] = 0x0
4524 01:02:54.150268 dump params cbt_mr12
4525 01:02:54.150343 cbt_mr12[0][0] = 0x0
4526 01:02:54.153315 cbt_mr12[0][1] = 0x0
4527 01:02:54.153391 cbt_mr12[1][0] = 0x0
4528 01:02:54.156942 cbt_mr12[1][1] = 0x0
4529 01:02:54.157017 dump params tx window
4530 01:02:54.160103 tx_center_min[0][0][0] = 0
4531 01:02:54.163126 tx_center_max[0][0][0] = 0
4532 01:02:54.166841 tx_center_min[0][0][1] = 0
4533 01:02:54.166917 tx_center_max[0][0][1] = 0
4534 01:02:54.170028 tx_center_min[0][1][0] = 0
4535 01:02:54.173527 tx_center_max[0][1][0] = 0
4536 01:02:54.176932 tx_center_min[0][1][1] = 0
4537 01:02:54.177015 tx_center_max[0][1][1] = 0
4538 01:02:54.179853 tx_center_min[1][0][0] = 0
4539 01:02:54.183141 tx_center_max[1][0][0] = 0
4540 01:02:54.186328 tx_center_min[1][0][1] = 0
4541 01:02:54.186403 tx_center_max[1][0][1] = 0
4542 01:02:54.189678 tx_center_min[1][1][0] = 0
4543 01:02:54.193460 tx_center_max[1][1][0] = 0
4544 01:02:54.196493 tx_center_min[1][1][1] = 0
4545 01:02:54.196566 tx_center_max[1][1][1] = 0
4546 01:02:54.199822 dump params tx window
4547 01:02:54.203074 tx_win_center[0][0][0] = 0
4548 01:02:54.203141 tx_first_pass[0][0][0] = 0
4549 01:02:54.206442 tx_last_pass[0][0][0] = 0
4550 01:02:54.209714 tx_win_center[0][0][1] = 0
4551 01:02:54.212810 tx_first_pass[0][0][1] = 0
4552 01:02:54.212876 tx_last_pass[0][0][1] = 0
4553 01:02:54.216275 tx_win_center[0][0][2] = 0
4554 01:02:54.219612 tx_first_pass[0][0][2] = 0
4555 01:02:54.223252 tx_last_pass[0][0][2] = 0
4556 01:02:54.223345 tx_win_center[0][0][3] = 0
4557 01:02:54.225996 tx_first_pass[0][0][3] = 0
4558 01:02:54.229627 tx_last_pass[0][0][3] = 0
4559 01:02:54.229781 tx_win_center[0][0][4] = 0
4560 01:02:54.232657 tx_first_pass[0][0][4] = 0
4561 01:02:54.236654 tx_last_pass[0][0][4] = 0
4562 01:02:54.239425 tx_win_center[0][0][5] = 0
4563 01:02:54.239530 tx_first_pass[0][0][5] = 0
4564 01:02:54.243348 tx_last_pass[0][0][5] = 0
4565 01:02:54.246588 tx_win_center[0][0][6] = 0
4566 01:02:54.246655 tx_first_pass[0][0][6] = 0
4567 01:02:54.249809 tx_last_pass[0][0][6] = 0
4568 01:02:54.253090 tx_win_center[0][0][7] = 0
4569 01:02:54.256149 tx_first_pass[0][0][7] = 0
4570 01:02:54.256219 tx_last_pass[0][0][7] = 0
4571 01:02:54.259736 tx_win_center[0][0][8] = 0
4572 01:02:54.263143 tx_first_pass[0][0][8] = 0
4573 01:02:54.266440 tx_last_pass[0][0][8] = 0
4574 01:02:54.266515 tx_win_center[0][0][9] = 0
4575 01:02:54.269611 tx_first_pass[0][0][9] = 0
4576 01:02:54.272764 tx_last_pass[0][0][9] = 0
4577 01:02:54.272840 tx_win_center[0][0][10] = 0
4578 01:02:54.276550 tx_first_pass[0][0][10] = 0
4579 01:02:54.279877 tx_last_pass[0][0][10] = 0
4580 01:02:54.282719 tx_win_center[0][0][11] = 0
4581 01:02:54.286097 tx_first_pass[0][0][11] = 0
4582 01:02:54.286173 tx_last_pass[0][0][11] = 0
4583 01:02:54.289325 tx_win_center[0][0][12] = 0
4584 01:02:54.293103 tx_first_pass[0][0][12] = 0
4585 01:02:54.293178 tx_last_pass[0][0][12] = 0
4586 01:02:54.296319 tx_win_center[0][0][13] = 0
4587 01:02:54.299304 tx_first_pass[0][0][13] = 0
4588 01:02:54.303114 tx_last_pass[0][0][13] = 0
4589 01:02:54.306663 tx_win_center[0][0][14] = 0
4590 01:02:54.306739 tx_first_pass[0][0][14] = 0
4591 01:02:54.309438 tx_last_pass[0][0][14] = 0
4592 01:02:54.313203 tx_win_center[0][0][15] = 0
4593 01:02:54.316415 tx_first_pass[0][0][15] = 0
4594 01:02:54.316492 tx_last_pass[0][0][15] = 0
4595 01:02:54.319315 tx_win_center[0][1][0] = 0
4596 01:02:54.322973 tx_first_pass[0][1][0] = 0
4597 01:02:54.323048 tx_last_pass[0][1][0] = 0
4598 01:02:54.326008 tx_win_center[0][1][1] = 0
4599 01:02:54.329425 tx_first_pass[0][1][1] = 0
4600 01:02:54.332759 tx_last_pass[0][1][1] = 0
4601 01:02:54.332825 tx_win_center[0][1][2] = 0
4602 01:02:54.335938 tx_first_pass[0][1][2] = 0
4603 01:02:54.339483 tx_last_pass[0][1][2] = 0
4604 01:02:54.342452 tx_win_center[0][1][3] = 0
4605 01:02:54.342521 tx_first_pass[0][1][3] = 0
4606 01:02:54.346185 tx_last_pass[0][1][3] = 0
4607 01:02:54.349340 tx_win_center[0][1][4] = 0
4608 01:02:54.349409 tx_first_pass[0][1][4] = 0
4609 01:02:54.352467 tx_last_pass[0][1][4] = 0
4610 01:02:54.355834 tx_win_center[0][1][5] = 0
4611 01:02:54.359399 tx_first_pass[0][1][5] = 0
4612 01:02:54.359465 tx_last_pass[0][1][5] = 0
4613 01:02:54.362784 tx_win_center[0][1][6] = 0
4614 01:02:54.365929 tx_first_pass[0][1][6] = 0
4615 01:02:54.369110 tx_last_pass[0][1][6] = 0
4616 01:02:54.369193 tx_win_center[0][1][7] = 0
4617 01:02:54.372521 tx_first_pass[0][1][7] = 0
4618 01:02:54.375749 tx_last_pass[0][1][7] = 0
4619 01:02:54.375824 tx_win_center[0][1][8] = 0
4620 01:02:54.379364 tx_first_pass[0][1][8] = 0
4621 01:02:54.382591 tx_last_pass[0][1][8] = 0
4622 01:02:54.386115 tx_win_center[0][1][9] = 0
4623 01:02:54.386192 tx_first_pass[0][1][9] = 0
4624 01:02:54.389016 tx_last_pass[0][1][9] = 0
4625 01:02:54.392574 tx_win_center[0][1][10] = 0
4626 01:02:54.395815 tx_first_pass[0][1][10] = 0
4627 01:02:54.395884 tx_last_pass[0][1][10] = 0
4628 01:02:54.398854 tx_win_center[0][1][11] = 0
4629 01:02:54.402630 tx_first_pass[0][1][11] = 0
4630 01:02:54.405723 tx_last_pass[0][1][11] = 0
4631 01:02:54.405788 tx_win_center[0][1][12] = 0
4632 01:02:54.409147 tx_first_pass[0][1][12] = 0
4633 01:02:54.412276 tx_last_pass[0][1][12] = 0
4634 01:02:54.415534 tx_win_center[0][1][13] = 0
4635 01:02:54.415604 tx_first_pass[0][1][13] = 0
4636 01:02:54.418952 tx_last_pass[0][1][13] = 0
4637 01:02:54.422098 tx_win_center[0][1][14] = 0
4638 01:02:54.425476 tx_first_pass[0][1][14] = 0
4639 01:02:54.425540 tx_last_pass[0][1][14] = 0
4640 01:02:54.428823 tx_win_center[0][1][15] = 0
4641 01:02:54.431990 tx_first_pass[0][1][15] = 0
4642 01:02:54.435704 tx_last_pass[0][1][15] = 0
4643 01:02:54.435783 tx_win_center[1][0][0] = 0
4644 01:02:54.438749 tx_first_pass[1][0][0] = 0
4645 01:02:54.441657 tx_last_pass[1][0][0] = 0
4646 01:02:54.445082 tx_win_center[1][0][1] = 0
4647 01:02:54.445148 tx_first_pass[1][0][1] = 0
4648 01:02:54.448635 tx_last_pass[1][0][1] = 0
4649 01:02:54.451807 tx_win_center[1][0][2] = 0
4650 01:02:54.455174 tx_first_pass[1][0][2] = 0
4651 01:02:54.455250 tx_last_pass[1][0][2] = 0
4652 01:02:54.458663 tx_win_center[1][0][3] = 0
4653 01:02:54.462197 tx_first_pass[1][0][3] = 0
4654 01:02:54.462273 tx_last_pass[1][0][3] = 0
4655 01:02:54.465106 tx_win_center[1][0][4] = 0
4656 01:02:54.468603 tx_first_pass[1][0][4] = 0
4657 01:02:54.472243 tx_last_pass[1][0][4] = 0
4658 01:02:54.472312 tx_win_center[1][0][5] = 0
4659 01:02:54.475311 tx_first_pass[1][0][5] = 0
4660 01:02:54.478267 tx_last_pass[1][0][5] = 0
4661 01:02:54.481826 tx_win_center[1][0][6] = 0
4662 01:02:54.481936 tx_first_pass[1][0][6] = 0
4663 01:02:54.485149 tx_last_pass[1][0][6] = 0
4664 01:02:54.488770 tx_win_center[1][0][7] = 0
4665 01:02:54.488862 tx_first_pass[1][0][7] = 0
4666 01:02:54.491818 tx_last_pass[1][0][7] = 0
4667 01:02:54.495139 tx_win_center[1][0][8] = 0
4668 01:02:54.498312 tx_first_pass[1][0][8] = 0
4669 01:02:54.498377 tx_last_pass[1][0][8] = 0
4670 01:02:54.501891 tx_win_center[1][0][9] = 0
4671 01:02:54.505009 tx_first_pass[1][0][9] = 0
4672 01:02:54.508357 tx_last_pass[1][0][9] = 0
4673 01:02:54.508454 tx_win_center[1][0][10] = 0
4674 01:02:54.511508 tx_first_pass[1][0][10] = 0
4675 01:02:54.515199 tx_last_pass[1][0][10] = 0
4676 01:02:54.518175 tx_win_center[1][0][11] = 0
4677 01:02:54.518237 tx_first_pass[1][0][11] = 0
4678 01:02:54.521295 tx_last_pass[1][0][11] = 0
4679 01:02:54.524623 tx_win_center[1][0][12] = 0
4680 01:02:54.528039 tx_first_pass[1][0][12] = 0
4681 01:02:54.528114 tx_last_pass[1][0][12] = 0
4682 01:02:54.531755 tx_win_center[1][0][13] = 0
4683 01:02:54.534698 tx_first_pass[1][0][13] = 0
4684 01:02:54.538280 tx_last_pass[1][0][13] = 0
4685 01:02:54.538356 tx_win_center[1][0][14] = 0
4686 01:02:54.540973 tx_first_pass[1][0][14] = 0
4687 01:02:54.544366 tx_last_pass[1][0][14] = 0
4688 01:02:54.547707 tx_win_center[1][0][15] = 0
4689 01:02:54.547778 tx_first_pass[1][0][15] = 0
4690 01:02:54.551364 tx_last_pass[1][0][15] = 0
4691 01:02:54.554351 tx_win_center[1][1][0] = 0
4692 01:02:54.557837 tx_first_pass[1][1][0] = 0
4693 01:02:54.557906 tx_last_pass[1][1][0] = 0
4694 01:02:54.561237 tx_win_center[1][1][1] = 0
4695 01:02:54.564295 tx_first_pass[1][1][1] = 0
4696 01:02:54.567975 tx_last_pass[1][1][1] = 0
4697 01:02:54.568052 tx_win_center[1][1][2] = 0
4698 01:02:54.570729 tx_first_pass[1][1][2] = 0
4699 01:02:54.574075 tx_last_pass[1][1][2] = 0
4700 01:02:54.574152 tx_win_center[1][1][3] = 0
4701 01:02:54.577795 tx_first_pass[1][1][3] = 0
4702 01:02:54.580863 tx_last_pass[1][1][3] = 0
4703 01:02:54.584283 tx_win_center[1][1][4] = 0
4704 01:02:54.584378 tx_first_pass[1][1][4] = 0
4705 01:02:54.588085 tx_last_pass[1][1][4] = 0
4706 01:02:54.591105 tx_win_center[1][1][5] = 0
4707 01:02:54.594119 tx_first_pass[1][1][5] = 0
4708 01:02:54.594196 tx_last_pass[1][1][5] = 0
4709 01:02:54.597419 tx_win_center[1][1][6] = 0
4710 01:02:54.600750 tx_first_pass[1][1][6] = 0
4711 01:02:54.600827 tx_last_pass[1][1][6] = 0
4712 01:02:54.603975 tx_win_center[1][1][7] = 0
4713 01:02:54.607737 tx_first_pass[1][1][7] = 0
4714 01:02:54.610571 tx_last_pass[1][1][7] = 0
4715 01:02:54.610648 tx_win_center[1][1][8] = 0
4716 01:02:54.614346 tx_first_pass[1][1][8] = 0
4717 01:02:54.617448 tx_last_pass[1][1][8] = 0
4718 01:02:54.620752 tx_win_center[1][1][9] = 0
4719 01:02:54.620824 tx_first_pass[1][1][9] = 0
4720 01:02:54.624036 tx_last_pass[1][1][9] = 0
4721 01:02:54.627673 tx_win_center[1][1][10] = 0
4722 01:02:54.630915 tx_first_pass[1][1][10] = 0
4723 01:02:54.630982 tx_last_pass[1][1][10] = 0
4724 01:02:54.634143 tx_win_center[1][1][11] = 0
4725 01:02:54.637628 tx_first_pass[1][1][11] = 0
4726 01:02:54.641078 tx_last_pass[1][1][11] = 0
4727 01:02:54.641144 tx_win_center[1][1][12] = 0
4728 01:02:54.644336 tx_first_pass[1][1][12] = 0
4729 01:02:54.647670 tx_last_pass[1][1][12] = 0
4730 01:02:54.650500 tx_win_center[1][1][13] = 0
4731 01:02:54.650565 tx_first_pass[1][1][13] = 0
4732 01:02:54.653904 tx_last_pass[1][1][13] = 0
4733 01:02:54.657295 tx_win_center[1][1][14] = 0
4734 01:02:54.660549 tx_first_pass[1][1][14] = 0
4735 01:02:54.660648 tx_last_pass[1][1][14] = 0
4736 01:02:54.664382 tx_win_center[1][1][15] = 0
4737 01:02:54.667459 tx_first_pass[1][1][15] = 0
4738 01:02:54.667535 tx_last_pass[1][1][15] = 0
4739 01:02:54.670859 dump params rx window
4740 01:02:54.673881 rx_firspass[0][0][0] = 0
4741 01:02:54.673986 rx_lastpass[0][0][0] = 0
4742 01:02:54.677226 rx_firspass[0][0][1] = 0
4743 01:02:54.680836 rx_lastpass[0][0][1] = 0
4744 01:02:54.680913 rx_firspass[0][0][2] = 0
4745 01:02:54.684784 rx_lastpass[0][0][2] = 0
4746 01:02:54.687207 rx_firspass[0][0][3] = 0
4747 01:02:54.691209 rx_lastpass[0][0][3] = 0
4748 01:02:54.691287 rx_firspass[0][0][4] = 0
4749 01:02:54.693877 rx_lastpass[0][0][4] = 0
4750 01:02:54.697355 rx_firspass[0][0][5] = 0
4751 01:02:54.697430 rx_lastpass[0][0][5] = 0
4752 01:02:54.700693 rx_firspass[0][0][6] = 0
4753 01:02:54.704265 rx_lastpass[0][0][6] = 0
4754 01:02:54.704344 rx_firspass[0][0][7] = 0
4755 01:02:54.707345 rx_lastpass[0][0][7] = 0
4756 01:02:54.710571 rx_firspass[0][0][8] = 0
4757 01:02:54.710645 rx_lastpass[0][0][8] = 0
4758 01:02:54.713739 rx_firspass[0][0][9] = 0
4759 01:02:54.717383 rx_lastpass[0][0][9] = 0
4760 01:02:54.720392 rx_firspass[0][0][10] = 0
4761 01:02:54.720468 rx_lastpass[0][0][10] = 0
4762 01:02:54.723896 rx_firspass[0][0][11] = 0
4763 01:02:54.727138 rx_lastpass[0][0][11] = 0
4764 01:02:54.727234 rx_firspass[0][0][12] = 0
4765 01:02:54.730410 rx_lastpass[0][0][12] = 0
4766 01:02:54.733462 rx_firspass[0][0][13] = 0
4767 01:02:54.736765 rx_lastpass[0][0][13] = 0
4768 01:02:54.736841 rx_firspass[0][0][14] = 0
4769 01:02:54.740182 rx_lastpass[0][0][14] = 0
4770 01:02:54.743513 rx_firspass[0][0][15] = 0
4771 01:02:54.743588 rx_lastpass[0][0][15] = 0
4772 01:02:54.747042 rx_firspass[0][1][0] = 0
4773 01:02:54.750313 rx_lastpass[0][1][0] = 0
4774 01:02:54.750389 rx_firspass[0][1][1] = 0
4775 01:02:54.753474 rx_lastpass[0][1][1] = 0
4776 01:02:54.757422 rx_firspass[0][1][2] = 0
4777 01:02:54.760165 rx_lastpass[0][1][2] = 0
4778 01:02:54.760241 rx_firspass[0][1][3] = 0
4779 01:02:54.763408 rx_lastpass[0][1][3] = 0
4780 01:02:54.767017 rx_firspass[0][1][4] = 0
4781 01:02:54.767092 rx_lastpass[0][1][4] = 0
4782 01:02:54.770191 rx_firspass[0][1][5] = 0
4783 01:02:54.773518 rx_lastpass[0][1][5] = 0
4784 01:02:54.773594 rx_firspass[0][1][6] = 0
4785 01:02:54.776733 rx_lastpass[0][1][6] = 0
4786 01:02:54.780219 rx_firspass[0][1][7] = 0
4787 01:02:54.780295 rx_lastpass[0][1][7] = 0
4788 01:02:54.783930 rx_firspass[0][1][8] = 0
4789 01:02:54.787082 rx_lastpass[0][1][8] = 0
4790 01:02:54.787163 rx_firspass[0][1][9] = 0
4791 01:02:54.789904 rx_lastpass[0][1][9] = 0
4792 01:02:54.793644 rx_firspass[0][1][10] = 0
4793 01:02:54.796656 rx_lastpass[0][1][10] = 0
4794 01:02:54.796723 rx_firspass[0][1][11] = 0
4795 01:02:54.800232 rx_lastpass[0][1][11] = 0
4796 01:02:54.803396 rx_firspass[0][1][12] = 0
4797 01:02:54.803461 rx_lastpass[0][1][12] = 0
4798 01:02:54.806688 rx_firspass[0][1][13] = 0
4799 01:02:54.810214 rx_lastpass[0][1][13] = 0
4800 01:02:54.813354 rx_firspass[0][1][14] = 0
4801 01:02:54.813417 rx_lastpass[0][1][14] = 0
4802 01:02:54.816842 rx_firspass[0][1][15] = 0
4803 01:02:54.820274 rx_lastpass[0][1][15] = 0
4804 01:02:54.820338 rx_firspass[1][0][0] = 0
4805 01:02:54.823368 rx_lastpass[1][0][0] = 0
4806 01:02:54.826271 rx_firspass[1][0][1] = 0
4807 01:02:54.830031 rx_lastpass[1][0][1] = 0
4808 01:02:54.830110 rx_firspass[1][0][2] = 0
4809 01:02:54.833257 rx_lastpass[1][0][2] = 0
4810 01:02:54.836433 rx_firspass[1][0][3] = 0
4811 01:02:54.836497 rx_lastpass[1][0][3] = 0
4812 01:02:54.839577 rx_firspass[1][0][4] = 0
4813 01:02:54.842976 rx_lastpass[1][0][4] = 0
4814 01:02:54.843055 rx_firspass[1][0][5] = 0
4815 01:02:54.846440 rx_lastpass[1][0][5] = 0
4816 01:02:54.849601 rx_firspass[1][0][6] = 0
4817 01:02:54.849670 rx_lastpass[1][0][6] = 0
4818 01:02:54.852989 rx_firspass[1][0][7] = 0
4819 01:02:54.856125 rx_lastpass[1][0][7] = 0
4820 01:02:54.856190 rx_firspass[1][0][8] = 0
4821 01:02:54.859549 rx_lastpass[1][0][8] = 0
4822 01:02:54.863177 rx_firspass[1][0][9] = 0
4823 01:02:54.866406 rx_lastpass[1][0][9] = 0
4824 01:02:54.866482 rx_firspass[1][0][10] = 0
4825 01:02:54.869593 rx_lastpass[1][0][10] = 0
4826 01:02:54.872917 rx_firspass[1][0][11] = 0
4827 01:02:54.872992 rx_lastpass[1][0][11] = 0
4828 01:02:54.876798 rx_firspass[1][0][12] = 0
4829 01:02:54.879958 rx_lastpass[1][0][12] = 0
4830 01:02:54.883017 rx_firspass[1][0][13] = 0
4831 01:02:54.883094 rx_lastpass[1][0][13] = 0
4832 01:02:54.886179 rx_firspass[1][0][14] = 0
4833 01:02:54.890012 rx_lastpass[1][0][14] = 0
4834 01:02:54.890102 rx_firspass[1][0][15] = 0
4835 01:02:54.892917 rx_lastpass[1][0][15] = 0
4836 01:02:54.896983 rx_firspass[1][1][0] = 0
4837 01:02:54.897058 rx_lastpass[1][1][0] = 0
4838 01:02:54.900046 rx_firspass[1][1][1] = 0
4839 01:02:54.903247 rx_lastpass[1][1][1] = 0
4840 01:02:54.906544 rx_firspass[1][1][2] = 0
4841 01:02:54.906622 rx_lastpass[1][1][2] = 0
4842 01:02:54.909581 rx_firspass[1][1][3] = 0
4843 01:02:54.913200 rx_lastpass[1][1][3] = 0
4844 01:02:54.913276 rx_firspass[1][1][4] = 0
4845 01:02:54.916403 rx_lastpass[1][1][4] = 0
4846 01:02:54.919469 rx_firspass[1][1][5] = 0
4847 01:02:54.919544 rx_lastpass[1][1][5] = 0
4848 01:02:54.922913 rx_firspass[1][1][6] = 0
4849 01:02:54.926847 rx_lastpass[1][1][6] = 0
4850 01:02:54.926915 rx_firspass[1][1][7] = 0
4851 01:02:54.929595 rx_lastpass[1][1][7] = 0
4852 01:02:54.933126 rx_firspass[1][1][8] = 0
4853 01:02:54.933195 rx_lastpass[1][1][8] = 0
4854 01:02:54.936127 rx_firspass[1][1][9] = 0
4855 01:02:54.939711 rx_lastpass[1][1][9] = 0
4856 01:02:54.943054 rx_firspass[1][1][10] = 0
4857 01:02:54.943125 rx_lastpass[1][1][10] = 0
4858 01:02:54.946503 rx_firspass[1][1][11] = 0
4859 01:02:54.949387 rx_lastpass[1][1][11] = 0
4860 01:02:54.949463 rx_firspass[1][1][12] = 0
4861 01:02:54.952654 rx_lastpass[1][1][12] = 0
4862 01:02:54.955889 rx_firspass[1][1][13] = 0
4863 01:02:54.959756 rx_lastpass[1][1][13] = 0
4864 01:02:54.959831 rx_firspass[1][1][14] = 0
4865 01:02:54.962638 rx_lastpass[1][1][14] = 0
4866 01:02:54.965933 rx_firspass[1][1][15] = 0
4867 01:02:54.966046 rx_lastpass[1][1][15] = 0
4868 01:02:54.969168 dump params clk_delay
4869 01:02:54.969243 clk_delay[0] = 0
4870 01:02:54.972851 clk_delay[1] = 0
4871 01:02:54.976045 dump params dqs_delay
4872 01:02:54.976153 dqs_delay[0][0] = 0
4873 01:02:54.979251 dqs_delay[0][1] = 0
4874 01:02:54.979326 dqs_delay[1][0] = 0
4875 01:02:54.982817 dqs_delay[1][1] = 0
4876 01:02:54.985846 dump params delay_cell_unit = 844
4877 01:02:54.985921 dump source = 0x0
4878 01:02:54.989261 dump params frequency:800
4879 01:02:54.992463 dump params rank number:2
4880 01:02:54.992539
4881 01:02:54.992598 dump params write leveling
4882 01:02:54.996291 write leveling[0][0][0] = 0x0
4883 01:02:54.999244 write leveling[0][0][1] = 0x0
4884 01:02:55.002712 write leveling[0][1][0] = 0x0
4885 01:02:55.006275 write leveling[0][1][1] = 0x0
4886 01:02:55.006352 write leveling[1][0][0] = 0x0
4887 01:02:55.009357 write leveling[1][0][1] = 0x0
4888 01:02:55.012595 write leveling[1][1][0] = 0x0
4889 01:02:55.015847 write leveling[1][1][1] = 0x0
4890 01:02:55.015937 dump params cbt_cs
4891 01:02:55.019294 cbt_cs[0][0] = 0x0
4892 01:02:55.019370 cbt_cs[0][1] = 0x0
4893 01:02:55.022376 cbt_cs[1][0] = 0x0
4894 01:02:55.022452 cbt_cs[1][1] = 0x0
4895 01:02:55.025880 dump params cbt_mr12
4896 01:02:55.025957 cbt_mr12[0][0] = 0x0
4897 01:02:55.029429 cbt_mr12[0][1] = 0x0
4898 01:02:55.032929 cbt_mr12[1][0] = 0x0
4899 01:02:55.033005 cbt_mr12[1][1] = 0x0
4900 01:02:55.035768 dump params tx window
4901 01:02:55.035844 tx_center_min[0][0][0] = 0
4902 01:02:55.038954 tx_center_max[0][0][0] = 0
4903 01:02:55.043103 tx_center_min[0][0][1] = 0
4904 01:02:55.045864 tx_center_max[0][0][1] = 0
4905 01:02:55.045939 tx_center_min[0][1][0] = 0
4906 01:02:55.049103 tx_center_max[0][1][0] = 0
4907 01:02:55.052484 tx_center_min[0][1][1] = 0
4908 01:02:55.055692 tx_center_max[0][1][1] = 0
4909 01:02:55.055768 tx_center_min[1][0][0] = 0
4910 01:02:55.059503 tx_center_max[1][0][0] = 0
4911 01:02:55.062526 tx_center_min[1][0][1] = 0
4912 01:02:55.065584 tx_center_max[1][0][1] = 0
4913 01:02:55.065673 tx_center_min[1][1][0] = 0
4914 01:02:55.068923 tx_center_max[1][1][0] = 0
4915 01:02:55.072259 tx_center_min[1][1][1] = 0
4916 01:02:55.075962 tx_center_max[1][1][1] = 0
4917 01:02:55.076037 dump params tx window
4918 01:02:55.078969 tx_win_center[0][0][0] = 0
4919 01:02:55.082492 tx_first_pass[0][0][0] = 0
4920 01:02:55.082569 tx_last_pass[0][0][0] = 0
4921 01:02:55.086219 tx_win_center[0][0][1] = 0
4922 01:02:55.089369 tx_first_pass[0][0][1] = 0
4923 01:02:55.092467 tx_last_pass[0][0][1] = 0
4924 01:02:55.092543 tx_win_center[0][0][2] = 0
4925 01:02:55.095860 tx_first_pass[0][0][2] = 0
4926 01:02:55.099229 tx_last_pass[0][0][2] = 0
4927 01:02:55.099305 tx_win_center[0][0][3] = 0
4928 01:02:55.102181 tx_first_pass[0][0][3] = 0
4929 01:02:55.105554 tx_last_pass[0][0][3] = 0
4930 01:02:55.108939 tx_win_center[0][0][4] = 0
4931 01:02:55.109047 tx_first_pass[0][0][4] = 0
4932 01:02:55.112162 tx_last_pass[0][0][4] = 0
4933 01:02:55.115543 tx_win_center[0][0][5] = 0
4934 01:02:55.119034 tx_first_pass[0][0][5] = 0
4935 01:02:55.119109 tx_last_pass[0][0][5] = 0
4936 01:02:55.121926 tx_win_center[0][0][6] = 0
4937 01:02:55.125637 tx_first_pass[0][0][6] = 0
4938 01:02:55.125712 tx_last_pass[0][0][6] = 0
4939 01:02:55.128655 tx_win_center[0][0][7] = 0
4940 01:02:55.132057 tx_first_pass[0][0][7] = 0
4941 01:02:55.135402 tx_last_pass[0][0][7] = 0
4942 01:02:55.135478 tx_win_center[0][0][8] = 0
4943 01:02:55.138761 tx_first_pass[0][0][8] = 0
4944 01:02:55.142355 tx_last_pass[0][0][8] = 0
4945 01:02:55.145563 tx_win_center[0][0][9] = 0
4946 01:02:55.145638 tx_first_pass[0][0][9] = 0
4947 01:02:55.149173 tx_last_pass[0][0][9] = 0
4948 01:02:55.152792 tx_win_center[0][0][10] = 0
4949 01:02:55.155885 tx_first_pass[0][0][10] = 0
4950 01:02:55.155960 tx_last_pass[0][0][10] = 0
4951 01:02:55.158777 tx_win_center[0][0][11] = 0
4952 01:02:55.162177 tx_first_pass[0][0][11] = 0
4953 01:02:55.165227 tx_last_pass[0][0][11] = 0
4954 01:02:55.165303 tx_win_center[0][0][12] = 0
4955 01:02:55.168427 tx_first_pass[0][0][12] = 0
4956 01:02:55.172494 tx_last_pass[0][0][12] = 0
4957 01:02:55.175350 tx_win_center[0][0][13] = 0
4958 01:02:55.175425 tx_first_pass[0][0][13] = 0
4959 01:02:55.179415 tx_last_pass[0][0][13] = 0
4960 01:02:55.181964 tx_win_center[0][0][14] = 0
4961 01:02:55.185147 tx_first_pass[0][0][14] = 0
4962 01:02:55.185222 tx_last_pass[0][0][14] = 0
4963 01:02:55.188315 tx_win_center[0][0][15] = 0
4964 01:02:55.192154 tx_first_pass[0][0][15] = 0
4965 01:02:55.195403 tx_last_pass[0][0][15] = 0
4966 01:02:55.195493 tx_win_center[0][1][0] = 0
4967 01:02:55.198652 tx_first_pass[0][1][0] = 0
4968 01:02:55.201741 tx_last_pass[0][1][0] = 0
4969 01:02:55.201832 tx_win_center[0][1][1] = 0
4970 01:02:55.205016 tx_first_pass[0][1][1] = 0
4971 01:02:55.208597 tx_last_pass[0][1][1] = 0
4972 01:02:55.212125 tx_win_center[0][1][2] = 0
4973 01:02:55.212194 tx_first_pass[0][1][2] = 0
4974 01:02:55.215319 tx_last_pass[0][1][2] = 0
4975 01:02:55.218377 tx_win_center[0][1][3] = 0
4976 01:02:55.221686 tx_first_pass[0][1][3] = 0
4977 01:02:55.221787 tx_last_pass[0][1][3] = 0
4978 01:02:55.225283 tx_win_center[0][1][4] = 0
4979 01:02:55.228587 tx_first_pass[0][1][4] = 0
4980 01:02:55.228686 tx_last_pass[0][1][4] = 0
4981 01:02:55.231655 tx_win_center[0][1][5] = 0
4982 01:02:55.234859 tx_first_pass[0][1][5] = 0
4983 01:02:55.238018 tx_last_pass[0][1][5] = 0
4984 01:02:55.238095 tx_win_center[0][1][6] = 0
4985 01:02:55.241442 tx_first_pass[0][1][6] = 0
4986 01:02:55.244880 tx_last_pass[0][1][6] = 0
4987 01:02:55.248157 tx_win_center[0][1][7] = 0
4988 01:02:55.248234 tx_first_pass[0][1][7] = 0
4989 01:02:55.251525 tx_last_pass[0][1][7] = 0
4990 01:02:55.256204 tx_win_center[0][1][8] = 0
4991 01:02:55.257832 tx_first_pass[0][1][8] = 0
4992 01:02:55.257935 tx_last_pass[0][1][8] = 0
4993 01:02:55.261302 tx_win_center[0][1][9] = 0
4994 01:02:55.264589 tx_first_pass[0][1][9] = 0
4995 01:02:55.264665 tx_last_pass[0][1][9] = 0
4996 01:02:55.267636 tx_win_center[0][1][10] = 0
4997 01:02:55.271049 tx_first_pass[0][1][10] = 0
4998 01:02:55.274630 tx_last_pass[0][1][10] = 0
4999 01:02:55.274706 tx_win_center[0][1][11] = 0
5000 01:02:55.277938 tx_first_pass[0][1][11] = 0
5001 01:02:55.281037 tx_last_pass[0][1][11] = 0
5002 01:02:55.284657 tx_win_center[0][1][12] = 0
5003 01:02:55.284732 tx_first_pass[0][1][12] = 0
5004 01:02:55.288158 tx_last_pass[0][1][12] = 0
5005 01:02:55.291485 tx_win_center[0][1][13] = 0
5006 01:02:55.294350 tx_first_pass[0][1][13] = 0
5007 01:02:55.294425 tx_last_pass[0][1][13] = 0
5008 01:02:55.298344 tx_win_center[0][1][14] = 0
5009 01:02:55.301433 tx_first_pass[0][1][14] = 0
5010 01:02:55.304152 tx_last_pass[0][1][14] = 0
5011 01:02:55.308020 tx_win_center[0][1][15] = 0
5012 01:02:55.308097 tx_first_pass[0][1][15] = 0
5013 01:02:55.310934 tx_last_pass[0][1][15] = 0
5014 01:02:55.314263 tx_win_center[1][0][0] = 0
5015 01:02:55.317931 tx_first_pass[1][0][0] = 0
5016 01:02:55.318039 tx_last_pass[1][0][0] = 0
5017 01:02:55.320752 tx_win_center[1][0][1] = 0
5018 01:02:55.324589 tx_first_pass[1][0][1] = 0
5019 01:02:55.324665 tx_last_pass[1][0][1] = 0
5020 01:02:55.327697 tx_win_center[1][0][2] = 0
5021 01:02:55.330618 tx_first_pass[1][0][2] = 0
5022 01:02:55.334474 tx_last_pass[1][0][2] = 0
5023 01:02:55.334549 tx_win_center[1][0][3] = 0
5024 01:02:55.337602 tx_first_pass[1][0][3] = 0
5025 01:02:55.340536 tx_last_pass[1][0][3] = 0
5026 01:02:55.343857 tx_win_center[1][0][4] = 0
5027 01:02:55.343951 tx_first_pass[1][0][4] = 0
5028 01:02:55.347536 tx_last_pass[1][0][4] = 0
5029 01:02:55.350884 tx_win_center[1][0][5] = 0
5030 01:02:55.350960 tx_first_pass[1][0][5] = 0
5031 01:02:55.353862 tx_last_pass[1][0][5] = 0
5032 01:02:55.357233 tx_win_center[1][0][6] = 0
5033 01:02:55.361432 tx_first_pass[1][0][6] = 0
5034 01:02:55.361508 tx_last_pass[1][0][6] = 0
5035 01:02:55.363666 tx_win_center[1][0][7] = 0
5036 01:02:55.367087 tx_first_pass[1][0][7] = 0
5037 01:02:55.370687 tx_last_pass[1][0][7] = 0
5038 01:02:55.370764 tx_win_center[1][0][8] = 0
5039 01:02:55.374269 tx_first_pass[1][0][8] = 0
5040 01:02:55.377463 tx_last_pass[1][0][8] = 0
5041 01:02:55.377562 tx_win_center[1][0][9] = 0
5042 01:02:55.380236 tx_first_pass[1][0][9] = 0
5043 01:02:55.383575 tx_last_pass[1][0][9] = 0
5044 01:02:55.387051 tx_win_center[1][0][10] = 0
5045 01:02:55.387149 tx_first_pass[1][0][10] = 0
5046 01:02:55.390652 tx_last_pass[1][0][10] = 0
5047 01:02:55.393685 tx_win_center[1][0][11] = 0
5048 01:02:55.397119 tx_first_pass[1][0][11] = 0
5049 01:02:55.397214 tx_last_pass[1][0][11] = 0
5050 01:02:55.400570 tx_win_center[1][0][12] = 0
5051 01:02:55.403523 tx_first_pass[1][0][12] = 0
5052 01:02:55.406875 tx_last_pass[1][0][12] = 0
5053 01:02:55.406944 tx_win_center[1][0][13] = 0
5054 01:02:55.410199 tx_first_pass[1][0][13] = 0
5055 01:02:55.413792 tx_last_pass[1][0][13] = 0
5056 01:02:55.416917 tx_win_center[1][0][14] = 0
5057 01:02:55.417016 tx_first_pass[1][0][14] = 0
5058 01:02:55.420066 tx_last_pass[1][0][14] = 0
5059 01:02:55.424000 tx_win_center[1][0][15] = 0
5060 01:02:55.427102 tx_first_pass[1][0][15] = 0
5061 01:02:55.427178 tx_last_pass[1][0][15] = 0
5062 01:02:55.430161 tx_win_center[1][1][0] = 0
5063 01:02:55.433866 tx_first_pass[1][1][0] = 0
5064 01:02:55.437252 tx_last_pass[1][1][0] = 0
5065 01:02:55.437327 tx_win_center[1][1][1] = 0
5066 01:02:55.440839 tx_first_pass[1][1][1] = 0
5067 01:02:55.443760 tx_last_pass[1][1][1] = 0
5068 01:02:55.443829 tx_win_center[1][1][2] = 0
5069 01:02:55.446968 tx_first_pass[1][1][2] = 0
5070 01:02:55.450089 tx_last_pass[1][1][2] = 0
5071 01:02:55.454156 tx_win_center[1][1][3] = 0
5072 01:02:55.454224 tx_first_pass[1][1][3] = 0
5073 01:02:55.456876 tx_last_pass[1][1][3] = 0
5074 01:02:55.460403 tx_win_center[1][1][4] = 0
5075 01:02:55.464052 tx_first_pass[1][1][4] = 0
5076 01:02:55.464161 tx_last_pass[1][1][4] = 0
5077 01:02:55.467035 tx_win_center[1][1][5] = 0
5078 01:02:55.470104 tx_first_pass[1][1][5] = 0
5079 01:02:55.470171 tx_last_pass[1][1][5] = 0
5080 01:02:55.473756 tx_win_center[1][1][6] = 0
5081 01:02:55.477170 tx_first_pass[1][1][6] = 0
5082 01:02:55.480301 tx_last_pass[1][1][6] = 0
5083 01:02:55.480376 tx_win_center[1][1][7] = 0
5084 01:02:55.483417 tx_first_pass[1][1][7] = 0
5085 01:02:55.486594 tx_last_pass[1][1][7] = 0
5086 01:02:55.490110 tx_win_center[1][1][8] = 0
5087 01:02:55.490185 tx_first_pass[1][1][8] = 0
5088 01:02:55.493820 tx_last_pass[1][1][8] = 0
5089 01:02:55.496771 tx_win_center[1][1][9] = 0
5090 01:02:55.496846 tx_first_pass[1][1][9] = 0
5091 01:02:55.500041 tx_last_pass[1][1][9] = 0
5092 01:02:55.503552 tx_win_center[1][1][10] = 0
5093 01:02:55.506658 tx_first_pass[1][1][10] = 0
5094 01:02:55.506734 tx_last_pass[1][1][10] = 0
5095 01:02:55.510195 tx_win_center[1][1][11] = 0
5096 01:02:55.513756 tx_first_pass[1][1][11] = 0
5097 01:02:55.517024 tx_last_pass[1][1][11] = 0
5098 01:02:55.517102 tx_win_center[1][1][12] = 0
5099 01:02:55.520295 tx_first_pass[1][1][12] = 0
5100 01:02:55.523674 tx_last_pass[1][1][12] = 0
5101 01:02:55.526705 tx_win_center[1][1][13] = 0
5102 01:02:55.526780 tx_first_pass[1][1][13] = 0
5103 01:02:55.530107 tx_last_pass[1][1][13] = 0
5104 01:02:55.533546 tx_win_center[1][1][14] = 0
5105 01:02:55.537355 tx_first_pass[1][1][14] = 0
5106 01:02:55.537431 tx_last_pass[1][1][14] = 0
5107 01:02:55.540243 tx_win_center[1][1][15] = 0
5108 01:02:55.543575 tx_first_pass[1][1][15] = 0
5109 01:02:55.546678 tx_last_pass[1][1][15] = 0
5110 01:02:55.546754 dump params rx window
5111 01:02:55.550542 rx_firspass[0][0][0] = 0
5112 01:02:55.553776 rx_lastpass[0][0][0] = 0
5113 01:02:55.553852 rx_firspass[0][0][1] = 0
5114 01:02:55.556759 rx_lastpass[0][0][1] = 0
5115 01:02:55.560386 rx_firspass[0][0][2] = 0
5116 01:02:55.560463 rx_lastpass[0][0][2] = 0
5117 01:02:55.563475 rx_firspass[0][0][3] = 0
5118 01:02:55.566986 rx_lastpass[0][0][3] = 0
5119 01:02:55.567063 rx_firspass[0][0][4] = 0
5120 01:02:55.569861 rx_lastpass[0][0][4] = 0
5121 01:02:55.573499 rx_firspass[0][0][5] = 0
5122 01:02:55.576731 rx_lastpass[0][0][5] = 0
5123 01:02:55.576806 rx_firspass[0][0][6] = 0
5124 01:02:55.580036 rx_lastpass[0][0][6] = 0
5125 01:02:55.583227 rx_firspass[0][0][7] = 0
5126 01:02:55.583303 rx_lastpass[0][0][7] = 0
5127 01:02:55.586584 rx_firspass[0][0][8] = 0
5128 01:02:55.590084 rx_lastpass[0][0][8] = 0
5129 01:02:55.590182 rx_firspass[0][0][9] = 0
5130 01:02:55.593445 rx_lastpass[0][0][9] = 0
5131 01:02:55.596585 rx_firspass[0][0][10] = 0
5132 01:02:55.596654 rx_lastpass[0][0][10] = 0
5133 01:02:55.599818 rx_firspass[0][0][11] = 0
5134 01:02:55.603183 rx_lastpass[0][0][11] = 0
5135 01:02:55.606352 rx_firspass[0][0][12] = 0
5136 01:02:55.606421 rx_lastpass[0][0][12] = 0
5137 01:02:55.610066 rx_firspass[0][0][13] = 0
5138 01:02:55.613140 rx_lastpass[0][0][13] = 0
5139 01:02:55.613202 rx_firspass[0][0][14] = 0
5140 01:02:55.616657 rx_lastpass[0][0][14] = 0
5141 01:02:55.619595 rx_firspass[0][0][15] = 0
5142 01:02:55.622872 rx_lastpass[0][0][15] = 0
5143 01:02:55.622947 rx_firspass[0][1][0] = 0
5144 01:02:55.626436 rx_lastpass[0][1][0] = 0
5145 01:02:55.629969 rx_firspass[0][1][1] = 0
5146 01:02:55.630079 rx_lastpass[0][1][1] = 0
5147 01:02:55.633094 rx_firspass[0][1][2] = 0
5148 01:02:55.636417 rx_lastpass[0][1][2] = 0
5149 01:02:55.636568 rx_firspass[0][1][3] = 0
5150 01:02:55.640043 rx_lastpass[0][1][3] = 0
5151 01:02:55.643222 rx_firspass[0][1][4] = 0
5152 01:02:55.643299 rx_lastpass[0][1][4] = 0
5153 01:02:55.646743 rx_firspass[0][1][5] = 0
5154 01:02:55.649677 rx_lastpass[0][1][5] = 0
5155 01:02:55.649778 rx_firspass[0][1][6] = 0
5156 01:02:55.653560 rx_lastpass[0][1][6] = 0
5157 01:02:55.656394 rx_firspass[0][1][7] = 0
5158 01:02:55.659994 rx_lastpass[0][1][7] = 0
5159 01:02:55.660079 rx_firspass[0][1][8] = 0
5160 01:02:55.663193 rx_lastpass[0][1][8] = 0
5161 01:02:55.666506 rx_firspass[0][1][9] = 0
5162 01:02:55.666582 rx_lastpass[0][1][9] = 0
5163 01:02:55.669867 rx_firspass[0][1][10] = 0
5164 01:02:55.672832 rx_lastpass[0][1][10] = 0
5165 01:02:55.672925 rx_firspass[0][1][11] = 0
5166 01:02:55.676244 rx_lastpass[0][1][11] = 0
5167 01:02:55.679465 rx_firspass[0][1][12] = 0
5168 01:02:55.683688 rx_lastpass[0][1][12] = 0
5169 01:02:55.683805 rx_firspass[0][1][13] = 0
5170 01:02:55.686552 rx_lastpass[0][1][13] = 0
5171 01:02:55.689944 rx_firspass[0][1][14] = 0
5172 01:02:55.690058 rx_lastpass[0][1][14] = 0
5173 01:02:55.693492 rx_firspass[0][1][15] = 0
5174 01:02:55.696517 rx_lastpass[0][1][15] = 0
5175 01:02:55.699574 rx_firspass[1][0][0] = 0
5176 01:02:55.699650 rx_lastpass[1][0][0] = 0
5177 01:02:55.703398 rx_firspass[1][0][1] = 0
5178 01:02:55.706722 rx_lastpass[1][0][1] = 0
5179 01:02:55.706798 rx_firspass[1][0][2] = 0
5180 01:02:55.709785 rx_lastpass[1][0][2] = 0
5181 01:02:55.713037 rx_firspass[1][0][3] = 0
5182 01:02:55.713120 rx_lastpass[1][0][3] = 0
5183 01:02:55.716065 rx_firspass[1][0][4] = 0
5184 01:02:55.719461 rx_lastpass[1][0][4] = 0
5185 01:02:55.719562 rx_firspass[1][0][5] = 0
5186 01:02:55.723545 rx_lastpass[1][0][5] = 0
5187 01:02:55.726330 rx_firspass[1][0][6] = 0
5188 01:02:55.726406 rx_lastpass[1][0][6] = 0
5189 01:02:55.729751 rx_firspass[1][0][7] = 0
5190 01:02:55.733161 rx_lastpass[1][0][7] = 0
5191 01:02:55.736094 rx_firspass[1][0][8] = 0
5192 01:02:55.736170 rx_lastpass[1][0][8] = 0
5193 01:02:55.739687 rx_firspass[1][0][9] = 0
5194 01:02:55.742646 rx_lastpass[1][0][9] = 0
5195 01:02:55.742722 rx_firspass[1][0][10] = 0
5196 01:02:55.746483 rx_lastpass[1][0][10] = 0
5197 01:02:55.749399 rx_firspass[1][0][11] = 0
5198 01:02:55.749484 rx_lastpass[1][0][11] = 0
5199 01:02:55.753159 rx_firspass[1][0][12] = 0
5200 01:02:55.756425 rx_lastpass[1][0][12] = 0
5201 01:02:55.759515 rx_firspass[1][0][13] = 0
5202 01:02:55.759591 rx_lastpass[1][0][13] = 0
5203 01:02:55.763079 rx_firspass[1][0][14] = 0
5204 01:02:55.765879 rx_lastpass[1][0][14] = 0
5205 01:02:55.765955 rx_firspass[1][0][15] = 0
5206 01:02:55.769595 rx_lastpass[1][0][15] = 0
5207 01:02:55.772672 rx_firspass[1][1][0] = 0
5208 01:02:55.776156 rx_lastpass[1][1][0] = 0
5209 01:02:55.776246 rx_firspass[1][1][1] = 0
5210 01:02:55.779333 rx_lastpass[1][1][1] = 0
5211 01:02:55.782930 rx_firspass[1][1][2] = 0
5212 01:02:55.783006 rx_lastpass[1][1][2] = 0
5213 01:02:55.785859 rx_firspass[1][1][3] = 0
5214 01:02:55.789057 rx_lastpass[1][1][3] = 0
5215 01:02:55.789170 rx_firspass[1][1][4] = 0
5216 01:02:55.793298 rx_lastpass[1][1][4] = 0
5217 01:02:55.795918 rx_firspass[1][1][5] = 0
5218 01:02:55.795995 rx_lastpass[1][1][5] = 0
5219 01:02:55.799229 rx_firspass[1][1][6] = 0
5220 01:02:55.802855 rx_lastpass[1][1][6] = 0
5221 01:02:55.805893 rx_firspass[1][1][7] = 0
5222 01:02:55.806037 rx_lastpass[1][1][7] = 0
5223 01:02:55.808994 rx_firspass[1][1][8] = 0
5224 01:02:55.812889 rx_lastpass[1][1][8] = 0
5225 01:02:55.812966 rx_firspass[1][1][9] = 0
5226 01:02:55.815959 rx_lastpass[1][1][9] = 0
5227 01:02:55.819020 rx_firspass[1][1][10] = 0
5228 01:02:55.819096 rx_lastpass[1][1][10] = 0
5229 01:02:55.822154 rx_firspass[1][1][11] = 0
5230 01:02:55.825642 rx_lastpass[1][1][11] = 0
5231 01:02:55.825719 rx_firspass[1][1][12] = 0
5232 01:02:55.829369 rx_lastpass[1][1][12] = 0
5233 01:02:55.832706 rx_firspass[1][1][13] = 0
5234 01:02:55.835874 rx_lastpass[1][1][13] = 0
5235 01:02:55.835951 rx_firspass[1][1][14] = 0
5236 01:02:55.838902 rx_lastpass[1][1][14] = 0
5237 01:02:55.842286 rx_firspass[1][1][15] = 0
5238 01:02:55.842363 rx_lastpass[1][1][15] = 0
5239 01:02:55.845751 dump params clk_delay
5240 01:02:55.849096 clk_delay[0] = 0
5241 01:02:55.849165 clk_delay[1] = 0
5242 01:02:55.852231 dump params dqs_delay
5243 01:02:55.852329 dqs_delay[0][0] = 0
5244 01:02:55.855966 dqs_delay[0][1] = 0
5245 01:02:55.856034 dqs_delay[1][0] = 0
5246 01:02:55.859195 dqs_delay[1][1] = 0
5247 01:02:55.862018 dump params delay_cell_unit = 844
5248 01:02:55.862126 mt_set_emi_preloader end
5249 01:02:55.869124 [mt_mem_init] dram size: 0x100000000, rank number: 2
5250 01:02:55.872236 [complex_mem_test] start addr:0x40000000, len:20480
5251 01:02:55.910312 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5252 01:02:55.916163 [complex_mem_test] start addr:0x80000000, len:20480
5253 01:02:55.952099 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5254 01:02:55.958813 [complex_mem_test] start addr:0xc0000000, len:20480
5255 01:02:55.994586 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5256 01:02:56.001160 [complex_mem_test] start addr:0x56000000, len:8192
5257 01:02:56.017733 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5258 01:02:56.020937 ddr_geometry:1
5259 01:02:56.024240 [complex_mem_test] start addr:0x80000000, len:8192
5260 01:02:56.041582 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5261 01:02:56.044793 dram_init: dram init end (result: 0)
5262 01:02:56.051329 Successfully loaded DRAM blobs and ran DRAM calibration
5263 01:02:56.061853 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5264 01:02:56.061950 CBMEM:
5265 01:02:56.064727 IMD: root @ 00000000fffff000 254 entries.
5266 01:02:56.068018 IMD: root @ 00000000ffffec00 62 entries.
5267 01:02:56.074789 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5268 01:02:56.081481 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5269 01:02:56.084896 in-header: 03 a1 00 00 08 00 00 00
5270 01:02:56.087753 in-data: 84 60 60 10 00 00 00 00
5271 01:02:56.091298 Chrome EC: clear events_b mask to 0x0000000020004000
5272 01:02:56.098952 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5273 01:02:56.102056 in-header: 03 fd 00 00 00 00 00 00
5274 01:02:56.102156 in-data:
5275 01:02:56.108398 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5276 01:02:56.108489 CBFS @ 21000 size 3d4000
5277 01:02:56.115588 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5278 01:02:56.118253 CBFS: Locating 'fallback/ramstage'
5279 01:02:56.121541 CBFS: Found @ offset 10d40 size d563
5280 01:02:56.143205 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5281 01:02:56.155714 Accumulated console time in romstage 13718 ms
5282 01:02:56.155790
5283 01:02:56.155848
5284 01:02:56.165555 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5285 01:02:56.168798 ARM64: Exception handlers installed.
5286 01:02:56.168874 ARM64: Testing exception
5287 01:02:56.172332 ARM64: Done test exception
5288 01:02:56.175483 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5289 01:02:56.178847 Manufacturer: ef
5290 01:02:56.182189 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5291 01:02:56.188943 WARNING: RO_VPD is uninitialized or empty.
5292 01:02:56.191925 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5293 01:02:56.194992 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5294 01:02:56.205101 read SPI 0x550600 0x3a00: 4533 us, 3275 KB/s, 26.200 Mbps
5295 01:02:56.208465 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5296 01:02:56.215451 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5297 01:02:56.215528 Enumerating buses...
5298 01:02:56.222117 Show all devs... Before device enumeration.
5299 01:02:56.222192 Root Device: enabled 1
5300 01:02:56.225022 CPU_CLUSTER: 0: enabled 1
5301 01:02:56.225098 CPU: 00: enabled 1
5302 01:02:56.228394 Compare with tree...
5303 01:02:56.232205 Root Device: enabled 1
5304 01:02:56.232281 CPU_CLUSTER: 0: enabled 1
5305 01:02:56.235064 CPU: 00: enabled 1
5306 01:02:56.238157 Root Device scanning...
5307 01:02:56.238233 root_dev_scan_bus for Root Device
5308 01:02:56.241565 CPU_CLUSTER: 0 enabled
5309 01:02:56.245037 root_dev_scan_bus for Root Device done
5310 01:02:56.251736 scan_bus: scanning of bus Root Device took 10689 usecs
5311 01:02:56.251812 done
5312 01:02:56.255266 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5313 01:02:56.258525 Allocating resources...
5314 01:02:56.258626 Reading resources...
5315 01:02:56.262378 Root Device read_resources bus 0 link: 0
5316 01:02:56.268106 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5317 01:02:56.271594 CPU: 00 missing read_resources
5318 01:02:56.274952 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5319 01:02:56.278241 Root Device read_resources bus 0 link: 0 done
5320 01:02:56.281748 Done reading resources.
5321 01:02:56.284574 Show resources in subtree (Root Device)...After reading.
5322 01:02:56.287847 Root Device child on link 0 CPU_CLUSTER: 0
5323 01:02:56.291138 CPU_CLUSTER: 0 child on link 0 CPU: 00
5324 01:02:56.301585 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5325 01:02:56.301662 CPU: 00
5326 01:02:56.304818 Setting resources...
5327 01:02:56.307956 Root Device assign_resources, bus 0 link: 0
5328 01:02:56.311113 CPU_CLUSTER: 0 missing set_resources
5329 01:02:56.314925 Root Device assign_resources, bus 0 link: 0
5330 01:02:56.318157 Done setting resources.
5331 01:02:56.324703 Show resources in subtree (Root Device)...After assigning values.
5332 01:02:56.328006 Root Device child on link 0 CPU_CLUSTER: 0
5333 01:02:56.331299 CPU_CLUSTER: 0 child on link 0 CPU: 00
5334 01:02:56.340961 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5335 01:02:56.341062 CPU: 00
5336 01:02:56.344225 Done allocating resources.
5337 01:02:56.347553 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5338 01:02:56.351331 Enabling resources...
5339 01:02:56.351412 done.
5340 01:02:56.354196 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5341 01:02:56.358145 Initializing devices...
5342 01:02:56.358217 Root Device init ...
5343 01:02:56.364354 mainboard_init: Starting display init.
5344 01:02:56.364470 ADC[4]: Raw value=75944 ID=0
5345 01:02:56.388233 anx7625_power_on_init: Init interface.
5346 01:02:56.391229 anx7625_disable_pd_protocol: Disabled PD feature.
5347 01:02:56.397857 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5348 01:02:56.455064 anx7625_start_dp_work: Secure OCM version=00
5349 01:02:56.458132 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5350 01:02:56.475650 sp_tx_get_edid_block: EDID Block = 1
5351 01:02:56.592823 Extracted contents:
5352 01:02:56.596431 header: 00 ff ff ff ff ff ff 00
5353 01:02:56.599121 serial number: 06 af 5c 14 00 00 00 00 00 1a
5354 01:02:56.602544 version: 01 04
5355 01:02:56.605896 basic params: 95 1a 0e 78 02
5356 01:02:56.609045 chroma info: 99 85 95 55 56 92 28 22 50 54
5357 01:02:56.612418 established: 00 00 00
5358 01:02:56.619290 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5359 01:02:56.622559 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5360 01:02:56.629207 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5361 01:02:56.635912 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5362 01:02:56.642260 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5363 01:02:56.645234 extensions: 00
5364 01:02:56.645326 checksum: ae
5365 01:02:56.645421
5366 01:02:56.648647 Manufacturer: AUO Model 145c Serial Number 0
5367 01:02:56.652290 Made week 0 of 2016
5368 01:02:56.652378 EDID version: 1.4
5369 01:02:56.656031 Digital display
5370 01:02:56.659000 6 bits per primary color channel
5371 01:02:56.659068 DisplayPort interface
5372 01:02:56.662106 Maximum image size: 26 cm x 14 cm
5373 01:02:56.665358 Gamma: 220%
5374 01:02:56.665425 Check DPMS levels
5375 01:02:56.668783 Supported color formats: RGB 4:4:4
5376 01:02:56.672093 First detailed timing is preferred timing
5377 01:02:56.675650 Established timings supported:
5378 01:02:56.678984 Standard timings supported:
5379 01:02:56.679077 Detailed timings
5380 01:02:56.685589 Hex of detail: ce1d56ea50001a3030204600009010000018
5381 01:02:56.689248 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5382 01:02:56.692007 0556 0586 05a6 0640 hborder 0
5383 01:02:56.695509 0300 0304 030a 031a vborder 0
5384 01:02:56.699021 -hsync -vsync
5385 01:02:56.702011 Did detailed timing
5386 01:02:56.705534 Hex of detail: 0000000f0000000000000000000000000020
5387 01:02:56.709043 Manufacturer-specified data, tag 15
5388 01:02:56.712001 Hex of detail: 000000fe0041554f0a202020202020202020
5389 01:02:56.715485 ASCII string: AUO
5390 01:02:56.719066 Hex of detail: 000000fe004231313658414230312e34200a
5391 01:02:56.722328 ASCII string: B116XAB01.4
5392 01:02:56.722397 Checksum
5393 01:02:56.725292 Checksum: 0xae (valid)
5394 01:02:56.732049 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5395 01:02:56.732148 DSI data_rate: 457800000 bps
5396 01:02:56.739847 anx7625_parse_edid: set default k value to 0x3d for panel
5397 01:02:56.743454 anx7625_parse_edid: pixelclock(76300).
5398 01:02:56.746091 hactive(1366), hsync(32), hfp(48), hbp(154)
5399 01:02:56.749419 vactive(768), vsync(6), vfp(4), vbp(16)
5400 01:02:56.752880 anx7625_dsi_config: config dsi.
5401 01:02:56.761041 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5402 01:02:56.781851 anx7625_dsi_config: success to config DSI
5403 01:02:56.785264 anx7625_dp_start: MIPI phy setup OK.
5404 01:02:56.789026 [SSUSB] Setting up USB HOST controller...
5405 01:02:56.792240 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5406 01:02:56.792331 [SSUSB] phy power-on done.
5407 01:02:56.799068 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5408 01:02:56.802190 in-header: 03 fc 01 00 00 00 00 00
5409 01:02:56.802277 in-data:
5410 01:02:56.805431 handle_proto3_response: EC response with error code: 1
5411 01:02:56.809208 SPM: pcm index = 1
5412 01:02:56.812532 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5413 01:02:56.815620 CBFS @ 21000 size 3d4000
5414 01:02:56.822073 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5415 01:02:56.825410 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5416 01:02:56.828921 CBFS: Found @ offset 1e7c0 size 1026
5417 01:02:56.835484 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5418 01:02:56.838800 SPM: binary array size = 2988
5419 01:02:56.841885 SPM: version = pcm_allinone_v1.17.2_20180829
5420 01:02:56.845146 SPM binary loaded in 32 msecs
5421 01:02:56.852994 spm_kick_im_to_fetch: ptr = 000000004021eec2
5422 01:02:56.856701 spm_kick_im_to_fetch: len = 2988
5423 01:02:56.856798 SPM: spm_kick_pcm_to_run
5424 01:02:56.859471 SPM: spm_kick_pcm_to_run done
5425 01:02:56.862753 SPM: spm_init done in 52 msecs
5426 01:02:56.866124 Root Device init finished in 505265 usecs
5427 01:02:56.869503 CPU_CLUSTER: 0 init ...
5428 01:02:56.879480 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5429 01:02:56.882563 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5430 01:02:56.885873 CBFS @ 21000 size 3d4000
5431 01:02:56.889164 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5432 01:02:56.892537 CBFS: Locating 'sspm.bin'
5433 01:02:56.896056 CBFS: Found @ offset 208c0 size 41cb
5434 01:02:56.906146 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5435 01:02:56.914092 CPU_CLUSTER: 0 init finished in 42804 usecs
5436 01:02:56.914165 Devices initialized
5437 01:02:56.917659 Show all devs... After init.
5438 01:02:56.920627 Root Device: enabled 1
5439 01:02:56.920743 CPU_CLUSTER: 0: enabled 1
5440 01:02:56.923848 CPU: 00: enabled 1
5441 01:02:56.927346 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5442 01:02:56.930364 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5443 01:02:56.933704 ELOG: NV offset 0x558000 size 0x1000
5444 01:02:56.941585 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5445 01:02:56.948342 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5446 01:02:56.951594 ELOG: Event(17) added with size 13 at 2024-06-16 01:02:57 UTC
5447 01:02:56.958220 out: cmd=0x121: 03 db 21 01 00 00 00 00
5448 01:02:56.961422 in-header: 03 c2 00 00 2c 00 00 00
5449 01:02:56.971531 in-data: 90 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 48 2b 01 00 06 80 00 00 4a 21 02 00 06 80 00 00 da 34 02 00 06 80 00 00 a7 6f 03 00
5450 01:02:56.974748 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5451 01:02:56.978106 in-header: 03 19 00 00 08 00 00 00
5452 01:02:56.981479 in-data: a2 e0 47 00 13 00 00 00
5453 01:02:56.984868 Chrome EC: UHEPI supported
5454 01:02:56.991142 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5455 01:02:56.994342 in-header: 03 e1 00 00 08 00 00 00
5456 01:02:56.997631 in-data: 84 20 60 10 00 00 00 00
5457 01:02:57.001162 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5458 01:02:57.007719 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5459 01:02:57.011018 in-header: 03 e1 00 00 08 00 00 00
5460 01:02:57.014427 in-data: 84 20 60 10 00 00 00 00
5461 01:02:57.020836 ELOG: Event(A1) added with size 10 at 2024-06-16 01:02:57 UTC
5462 01:02:57.027617 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5463 01:02:57.034325 ELOG: Event(A0) added with size 9 at 2024-06-16 01:02:57 UTC
5464 01:02:57.037634 elog_add_boot_reason: Logged dev mode boot
5465 01:02:57.037742 Finalize devices...
5466 01:02:57.040900 Devices finalized
5467 01:02:57.044216 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5468 01:02:57.051055 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5469 01:02:57.054293 ELOG: Event(91) added with size 10 at 2024-06-16 01:02:57 UTC
5470 01:02:57.057672 Writing coreboot table at 0xffeda000
5471 01:02:57.063964 0. 0000000000114000-000000000011efff: RAMSTAGE
5472 01:02:57.067213 1. 0000000040000000-000000004023cfff: RAMSTAGE
5473 01:02:57.071154 2. 000000004023d000-00000000545fffff: RAM
5474 01:02:57.074130 3. 0000000054600000-000000005465ffff: BL31
5475 01:02:57.077475 4. 0000000054660000-00000000ffed9fff: RAM
5476 01:02:57.084338 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5477 01:02:57.087524 6. 0000000100000000-000000013fffffff: RAM
5478 01:02:57.090706 Passing 5 GPIOs to payload:
5479 01:02:57.094172 NAME | PORT | POLARITY | VALUE
5480 01:02:57.100673 write protect | 0x00000096 | low | low
5481 01:02:57.104067 EC in RW | 0x000000b1 | high | undefined
5482 01:02:57.107311 EC interrupt | 0x00000097 | low | undefined
5483 01:02:57.114009 TPM interrupt | 0x00000099 | high | undefined
5484 01:02:57.117292 speaker enable | 0x000000af | high | undefined
5485 01:02:57.120711 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5486 01:02:57.124145 in-header: 03 f7 00 00 02 00 00 00
5487 01:02:57.127511 in-data: 04 00
5488 01:02:57.127578 Board ID: 4
5489 01:02:57.130660 ADC[3]: Raw value=216068 ID=1
5490 01:02:57.130749 RAM code: 1
5491 01:02:57.130830 SKU ID: 16
5492 01:02:57.137030 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5493 01:02:57.137121 CBFS @ 21000 size 3d4000
5494 01:02:57.143962 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5495 01:02:57.150710 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum ccd0
5496 01:02:57.153852 coreboot table: 940 bytes.
5497 01:02:57.157032 IMD ROOT 0. 00000000fffff000 00001000
5498 01:02:57.160241 IMD SMALL 1. 00000000ffffe000 00001000
5499 01:02:57.163588 CONSOLE 2. 00000000fffde000 00020000
5500 01:02:57.166821 FMAP 3. 00000000fffdd000 0000047c
5501 01:02:57.170296 TIME STAMP 4. 00000000fffdc000 00000910
5502 01:02:57.173468 RAMOOPS 5. 00000000ffedc000 00100000
5503 01:02:57.177293 COREBOOT 6. 00000000ffeda000 00002000
5504 01:02:57.180774 IMD small region:
5505 01:02:57.183526 IMD ROOT 0. 00000000ffffec00 00000400
5506 01:02:57.187047 VBOOT WORK 1. 00000000ffffeb00 00000100
5507 01:02:57.190222 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5508 01:02:57.193630 VPD 3. 00000000ffffea60 0000006c
5509 01:02:57.200418 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5510 01:02:57.207360 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5511 01:02:57.210396 in-header: 03 e1 00 00 08 00 00 00
5512 01:02:57.213469 in-data: 84 20 60 10 00 00 00 00
5513 01:02:57.217206 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5514 01:02:57.220492 CBFS @ 21000 size 3d4000
5515 01:02:57.223955 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5516 01:02:57.226719 CBFS: Locating 'fallback/payload'
5517 01:02:57.235596 CBFS: Found @ offset dc040 size 439a0
5518 01:02:57.323546 read SPI 0xfd078 0x439a0: 84380 us, 3281 KB/s, 26.248 Mbps
5519 01:02:57.326754 Checking segment from ROM address 0x0000000040003a00
5520 01:02:57.333677 Checking segment from ROM address 0x0000000040003a1c
5521 01:02:57.336720 Loading segment from ROM address 0x0000000040003a00
5522 01:02:57.340436 code (compression=0)
5523 01:02:57.350090 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5524 01:02:57.356753 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5525 01:02:57.359863 it's not compressed!
5526 01:02:57.363309 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5527 01:02:57.369925 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5528 01:02:57.377814 Loading segment from ROM address 0x0000000040003a1c
5529 01:02:57.381178 Entry Point 0x0000000080000000
5530 01:02:57.381253 Loaded segments
5531 01:02:57.388008 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5532 01:02:57.391390 Jumping to boot code at 0000000080000000(00000000ffeda000)
5533 01:02:57.401454 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5534 01:02:57.404525 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5535 01:02:57.407774 CBFS @ 21000 size 3d4000
5536 01:02:57.414341 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5537 01:02:57.417852 CBFS: Locating 'fallback/bl31'
5538 01:02:57.421125 CBFS: Found @ offset 36dc0 size 5820
5539 01:02:57.431999 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5540 01:02:57.435192 Checking segment from ROM address 0x0000000040003a00
5541 01:02:57.441717 Checking segment from ROM address 0x0000000040003a1c
5542 01:02:57.445020 Loading segment from ROM address 0x0000000040003a00
5543 01:02:57.448357 code (compression=1)
5544 01:02:57.455140 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5545 01:02:57.464935 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5546 01:02:57.465010 using LZMA
5547 01:02:57.473505 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5548 01:02:57.480168 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5549 01:02:57.483980 Loading segment from ROM address 0x0000000040003a1c
5550 01:02:57.487208 Entry Point 0x0000000054601000
5551 01:02:57.487301 Loaded segments
5552 01:02:57.490720 NOTICE: MT8183 bl31_setup
5553 01:02:57.497673 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5554 01:02:57.500851 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5555 01:02:57.504216 INFO: [DEVAPC] dump DEVAPC registers:
5556 01:02:57.514309 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5557 01:02:57.521293 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5558 01:02:57.530877 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5559 01:02:57.537152 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5560 01:02:57.546946 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5561 01:02:57.553974 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5562 01:02:57.563560 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5563 01:02:57.570192 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5564 01:02:57.580206 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5565 01:02:57.586543 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5566 01:02:57.596468 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5567 01:02:57.603215 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5568 01:02:57.610158 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5569 01:02:57.619778 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5570 01:02:57.626240 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5571 01:02:57.632898 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5572 01:02:57.639554 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5573 01:02:57.649558 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5574 01:02:57.656092 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5575 01:02:57.662970 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5576 01:02:57.669489 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5577 01:02:57.676007 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5578 01:02:57.679455 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5579 01:02:57.682659 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5580 01:02:57.686338 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5581 01:02:57.689851 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5582 01:02:57.692708 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5583 01:02:57.699240 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5584 01:02:57.706066 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5585 01:02:57.706137 WARNING: region 0:
5586 01:02:57.709292 WARNING: apc:0x168, sa:0x0, ea:0xfff
5587 01:02:57.712348 WARNING: region 1:
5588 01:02:57.716078 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5589 01:02:57.716151 WARNING: region 2:
5590 01:02:57.722573 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5591 01:02:57.722645 WARNING: region 3:
5592 01:02:57.726106 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5593 01:02:57.729379 WARNING: region 4:
5594 01:02:57.732424 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5595 01:02:57.732489 WARNING: region 5:
5596 01:02:57.735638 WARNING: apc:0x0, sa:0x0, ea:0x0
5597 01:02:57.738820 WARNING: region 6:
5598 01:02:57.742531 WARNING: apc:0x0, sa:0x0, ea:0x0
5599 01:02:57.742604 WARNING: region 7:
5600 01:02:57.745942 WARNING: apc:0x0, sa:0x0, ea:0x0
5601 01:02:57.752350 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5602 01:02:57.755397 INFO: SPM: enable SPMC mode
5603 01:02:57.758912 NOTICE: spm_boot_init() start
5604 01:02:57.762106 NOTICE: spm_boot_init() end
5605 01:02:57.765364 INFO: BL31: Initializing runtime services
5606 01:02:57.772180 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5607 01:02:57.775880 INFO: BL31: Preparing for EL3 exit to normal world
5608 01:02:57.779040 INFO: Entry point address = 0x80000000
5609 01:02:57.782163 INFO: SPSR = 0x8
5610 01:02:57.804229
5611 01:02:57.804331
5612 01:02:57.804419
5613 01:02:57.804898 end: 2.2.3 depthcharge-start (duration 00:00:11) [common]
5614 01:02:57.805026 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
5615 01:02:57.805130 Setting prompt string to ['jacuzzi:']
5616 01:02:57.805232 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:28)
5617 01:02:57.807411 Starting depthcharge on Juniper...
5618 01:02:57.807510
5619 01:02:57.810835 vboot_handoff: creating legacy vboot_handoff structure
5620 01:02:57.810935
5621 01:02:57.814041 ec_init(0): CrosEC protocol v3 supported (544, 544)
5622 01:02:57.814144
5623 01:02:57.817441 Wipe memory regions:
5624 01:02:57.817522
5625 01:02:57.820466 [0x00000040000000, 0x00000054600000)
5626 01:02:57.863171
5627 01:02:57.863258 [0x00000054660000, 0x00000080000000)
5628 01:02:57.955075
5629 01:02:57.955200 [0x000000811994a0, 0x000000ffeda000)
5630 01:02:58.215127
5631 01:02:58.215245 [0x00000100000000, 0x00000140000000)
5632 01:02:58.348059
5633 01:02:58.351161 Initializing XHCI USB controller at 0x11200000.
5634 01:02:58.373845
5635 01:02:58.377182 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5636 01:02:58.377258
5637 01:02:58.377319
5638 01:02:58.377593 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5640 01:02:58.477935 jacuzzi: tftpboot 192.168.201.1 14368634/tftp-deploy-3qp76dav/kernel/image.itb 14368634/tftp-deploy-3qp76dav/kernel/cmdline
5641 01:02:58.478160 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5642 01:02:58.478243 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:27)
5643 01:02:58.482124 tftpboot 192.168.201.1 14368634/tftp-deploy-3qp76dav/kernel/image.itbtp-deploy-3qp76dav/kernel/cmdline
5644 01:02:58.482201
5645 01:02:58.482265 Waiting for link
5646 01:02:58.887659
5647 01:02:58.887794 R8152: Initializing
5648 01:02:58.887854
5649 01:02:58.890978 Version 9 (ocp_data = 6010)
5650 01:02:58.891054
5651 01:02:58.894297 R8152: Done initializing
5652 01:02:58.894376
5653 01:02:58.894432 Adding net device
5654 01:02:59.279965
5655 01:02:59.280079 done.
5656 01:02:59.280139
5657 01:02:59.280193 MAC: 00:e0:4c:72:3d:67
5658 01:02:59.280245
5659 01:02:59.283778 Sending DHCP discover... done.
5660 01:02:59.283855
5661 01:02:59.286708 Waiting for reply... done.
5662 01:02:59.286784
5663 01:02:59.289849 Sending DHCP request... done.
5664 01:02:59.289948
5665 01:02:59.293767 Waiting for reply... done.
5666 01:02:59.293865
5667 01:02:59.293957 My ip is 192.168.201.13
5668 01:02:59.294060
5669 01:02:59.296851 The DHCP server ip is 192.168.201.1
5670 01:02:59.296927
5671 01:02:59.303697 TFTP server IP predefined by user: 192.168.201.1
5672 01:02:59.303773
5673 01:02:59.310041 Bootfile predefined by user: 14368634/tftp-deploy-3qp76dav/kernel/image.itb
5674 01:02:59.310118
5675 01:02:59.310176 Sending tftp read request... done.
5676 01:02:59.313527
5677 01:02:59.317332 Waiting for the transfer...
5678 01:02:59.317410
5679 01:02:59.570593 00000000 ################################################################
5680 01:02:59.570712
5681 01:02:59.833772 00080000 ################################################################
5682 01:02:59.833894
5683 01:03:00.095253 00100000 ################################################################
5684 01:03:00.095369
5685 01:03:00.348591 00180000 ################################################################
5686 01:03:00.348735
5687 01:03:00.599917 00200000 ################################################################
5688 01:03:00.600031
5689 01:03:00.862640 00280000 ################################################################
5690 01:03:00.862786
5691 01:03:01.128701 00300000 ################################################################
5692 01:03:01.128840
5693 01:03:01.381404 00380000 ################################################################
5694 01:03:01.381548
5695 01:03:01.647826 00400000 ################################################################
5696 01:03:01.647961
5697 01:03:01.917359 00480000 ################################################################
5698 01:03:01.917499
5699 01:03:02.180818 00500000 ################################################################
5700 01:03:02.180940
5701 01:03:02.463933 00580000 ################################################################
5702 01:03:02.464073
5703 01:03:02.720510 00600000 ################################################################
5704 01:03:02.720662
5705 01:03:02.967920 00680000 ################################################################
5706 01:03:02.968045
5707 01:03:03.217434 00700000 ################################################################
5708 01:03:03.217566
5709 01:03:03.470163 00780000 ################################################################
5710 01:03:03.470275
5711 01:03:03.723006 00800000 ################################################################
5712 01:03:03.723118
5713 01:03:03.984801 00880000 ################################################################
5714 01:03:03.984930
5715 01:03:04.258433 00900000 ################################################################
5716 01:03:04.258553
5717 01:03:04.510191 00980000 ################################################################
5718 01:03:04.510345
5719 01:03:04.791515 00a00000 ################################################################
5720 01:03:04.791638
5721 01:03:05.075023 00a80000 ################################################################
5722 01:03:05.075147
5723 01:03:05.354493 00b00000 ################################################################
5724 01:03:05.354634
5725 01:03:05.609340 00b80000 ################################################################
5726 01:03:05.609463
5727 01:03:05.875783 00c00000 ################################################################
5728 01:03:05.875908
5729 01:03:06.129701 00c80000 ################################################################
5730 01:03:06.129844
5731 01:03:06.386266 00d00000 ################################################################
5732 01:03:06.386390
5733 01:03:06.641311 00d80000 ################################################################
5734 01:03:06.641448
5735 01:03:06.893389 00e00000 ################################################################
5736 01:03:06.893537
5737 01:03:07.141899 00e80000 ################################################################
5738 01:03:07.142056
5739 01:03:07.391764 00f00000 ################################################################
5740 01:03:07.391888
5741 01:03:07.641794 00f80000 ################################################################
5742 01:03:07.641915
5743 01:03:07.891750 01000000 ################################################################
5744 01:03:07.891891
5745 01:03:08.142071 01080000 ################################################################
5746 01:03:08.142192
5747 01:03:08.392950 01100000 ################################################################
5748 01:03:08.393097
5749 01:03:08.643009 01180000 ################################################################
5750 01:03:08.643149
5751 01:03:08.893329 01200000 ################################################################
5752 01:03:08.893454
5753 01:03:09.142788 01280000 ################################################################
5754 01:03:09.142907
5755 01:03:09.398422 01300000 ################################################################
5756 01:03:09.398551
5757 01:03:09.648832 01380000 ################################################################
5758 01:03:09.648971
5759 01:03:09.901826 01400000 ################################################################
5760 01:03:09.901943
5761 01:03:10.152912 01480000 ################################################################
5762 01:03:10.153024
5763 01:03:10.403279 01500000 ################################################################
5764 01:03:10.403399
5765 01:03:10.651814 01580000 ################################################################
5766 01:03:10.651931
5767 01:03:10.903673 01600000 ################################################################
5768 01:03:10.903787
5769 01:03:11.154827 01680000 ################################################################
5770 01:03:11.154972
5771 01:03:11.407486 01700000 ################################################################
5772 01:03:11.407715
5773 01:03:11.673456 01780000 ################################################################
5774 01:03:11.673580
5775 01:03:11.930937 01800000 ################################################################
5776 01:03:11.931056
5777 01:03:12.189526 01880000 ################################################################
5778 01:03:12.189667
5779 01:03:12.454113 01900000 ################################################################
5780 01:03:12.454234
5781 01:03:12.704149 01980000 ################################################################
5782 01:03:12.704269
5783 01:03:12.957619 01a00000 ################################################################
5784 01:03:12.957759
5785 01:03:13.208397 01a80000 ################################################################
5786 01:03:13.208533
5787 01:03:13.459479 01b00000 ################################################################
5788 01:03:13.459600
5789 01:03:13.708979 01b80000 ################################################################
5790 01:03:13.709140
5791 01:03:13.967075 01c00000 ################################################################
5792 01:03:13.967213
5793 01:03:14.215729 01c80000 ################################################################
5794 01:03:14.215874
5795 01:03:14.466011 01d00000 ################################################################
5796 01:03:14.466145
5797 01:03:14.731756 01d80000 ################################################################
5798 01:03:14.731907
5799 01:03:14.957274 01e00000 ######################################################### done.
5800 01:03:14.957409
5801 01:03:14.960746 The bootfile was 31922470 bytes long.
5802 01:03:14.960841
5803 01:03:14.960927 Sending tftp read request... done.
5804 01:03:14.963619
5805 01:03:14.963685 Waiting for the transfer...
5806 01:03:14.963741
5807 01:03:14.967168 00000000 # done.
5808 01:03:14.967247
5809 01:03:14.973810 Command line loaded dynamically from TFTP file: 14368634/tftp-deploy-3qp76dav/kernel/cmdline
5810 01:03:14.973905
5811 01:03:15.000425 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368634/extract-nfsrootfs-pm0qfktj,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5812 01:03:15.000529
5813 01:03:15.000614 Loading FIT.
5814 01:03:15.000698
5815 01:03:15.003558 Image ramdisk-1 has 18737688 bytes.
5816 01:03:15.003630
5817 01:03:15.006867 Image fdt-1 has 57695 bytes.
5818 01:03:15.006933
5819 01:03:15.010205 Image kernel-1 has 13125045 bytes.
5820 01:03:15.010291
5821 01:03:15.020361 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5822 01:03:15.020452
5823 01:03:15.030153 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5824 01:03:15.030223
5825 01:03:15.036953 Choosing best match conf-1 for compat google,juniper-sku16.
5826 01:03:15.040218
5827 01:03:15.045213 Connected to device vid:did:rid of 1ae0:0028:00
5828 01:03:15.053140
5829 01:03:15.056170 tpm_get_response: command 0x17b, return code 0x0
5830 01:03:15.056258
5831 01:03:15.059768 tpm_cleanup: add release locality here.
5832 01:03:15.059857
5833 01:03:15.063202 Shutting down all USB controllers.
5834 01:03:15.063288
5835 01:03:15.066965 Removing current net device
5836 01:03:15.067032
5837 01:03:15.069559 Exiting depthcharge with code 4 at timestamp: 34595700
5838 01:03:15.069644
5839 01:03:15.073902 LZMA decompressing kernel-1 to 0x80193568
5840 01:03:15.073999
5841 01:03:15.079794 LZMA decompressing kernel-1 to 0x40000000
5842 01:03:16.944017
5843 01:03:16.944152 jumping to kernel
5844 01:03:16.944978 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
5845 01:03:16.945073 start: 2.2.5 auto-login-action (timeout 00:04:08) [common]
5846 01:03:16.945153 Setting prompt string to ['Linux version [0-9]']
5847 01:03:16.945225 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5848 01:03:16.945292 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5849 01:03:17.019755
5850 01:03:17.022693 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5851 01:03:17.026110 start: 2.2.5.1 login-action (timeout 00:04:08) [common]
5852 01:03:17.026230 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5853 01:03:17.026323 Setting prompt string to []
5854 01:03:17.026420 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5855 01:03:17.026515 Using line separator: #'\n'#
5856 01:03:17.026595 No login prompt set.
5857 01:03:17.026677 Parsing kernel messages
5858 01:03:17.026728 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5859 01:03:17.026825 [login-action] Waiting for messages, (timeout 00:04:08)
5860 01:03:17.026885 Waiting using forced prompt support (timeout 00:02:04)
5861 01:03:17.046082 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
5862 01:03:17.049165 [ 0.000000] random: crng init done
5863 01:03:17.055927 [ 0.000000] Machine model: Google juniper sku16 board
5864 01:03:17.059464 [ 0.000000] efi: UEFI not found.
5865 01:03:17.066838 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5866 01:03:17.072729 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5867 01:03:17.082600 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5868 01:03:17.086190 [ 0.000000] printk: bootconsole [mtk8250] enabled
5869 01:03:17.094236 [ 0.000000] NUMA: No NUMA configuration found
5870 01:03:17.100881 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5871 01:03:17.107735 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5872 01:03:17.107830 [ 0.000000] Zone ranges:
5873 01:03:17.114243 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5874 01:03:17.117613 [ 0.000000] DMA32 empty
5875 01:03:17.124155 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5876 01:03:17.127640 [ 0.000000] Movable zone start for each node
5877 01:03:17.131270 [ 0.000000] Early memory node ranges
5878 01:03:17.137374 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5879 01:03:17.144198 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5880 01:03:17.150994 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5881 01:03:17.157452 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5882 01:03:17.164246 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5883 01:03:17.170992 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5884 01:03:17.186836 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5885 01:03:17.193325 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5886 01:03:17.200017 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5887 01:03:17.203541 [ 0.000000] psci: probing for conduit method from DT.
5888 01:03:17.209748 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5889 01:03:17.213574 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5890 01:03:17.219919 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5891 01:03:17.223062 [ 0.000000] psci: SMC Calling Convention v1.1
5892 01:03:17.229798 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5893 01:03:17.233131 [ 0.000000] Detected VIPT I-cache on CPU0
5894 01:03:17.240068 [ 0.000000] CPU features: detected: GIC system register CPU interface
5895 01:03:17.246461 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5896 01:03:17.252999 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5897 01:03:17.259750 [ 0.000000] CPU features: detected: ARM erratum 845719
5898 01:03:17.263220 [ 0.000000] alternatives: applying boot alternatives
5899 01:03:17.266193 [ 0.000000] Fallback order for Node 0: 0
5900 01:03:17.273150 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5901 01:03:17.276717 [ 0.000000] Policy zone: Normal
5902 01:03:17.302997 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14368634/extract-nfsrootfs-pm0qfktj,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5903 01:03:17.316095 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5904 01:03:17.326247 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5905 01:03:17.333118 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5906 01:03:17.339210 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5907 01:03:17.343223 <6>[ 0.000000] software IO TLB: area num 8.
5908 01:03:17.369984 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5909 01:03:17.428171 <6>[ 0.000000] Memory: 3896772K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 261692K reserved, 32768K cma-reserved)
5910 01:03:17.434640 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5911 01:03:17.441170 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5912 01:03:17.444669 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5913 01:03:17.451009 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5914 01:03:17.458038 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5915 01:03:17.461498 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5916 01:03:17.471512 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5917 01:03:17.477735 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5918 01:03:17.484167 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5919 01:03:17.494616 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5920 01:03:17.497562 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5921 01:03:17.501229 <6>[ 0.000000] GICv3: 640 SPIs implemented
5922 01:03:17.507512 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5923 01:03:17.510824 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5924 01:03:17.517579 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5925 01:03:17.523957 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5926 01:03:17.534215 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5927 01:03:17.547562 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5928 01:03:17.554451 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5929 01:03:17.565139 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5930 01:03:17.578356 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5931 01:03:17.585323 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5932 01:03:17.592026 <6>[ 0.009467] Console: colour dummy device 80x25
5933 01:03:17.595294 <6>[ 0.014509] printk: console [tty1] enabled
5934 01:03:17.605257 <6>[ 0.018895] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5935 01:03:17.611758 <6>[ 0.029360] pid_max: default: 32768 minimum: 301
5936 01:03:17.615047 <6>[ 0.034240] LSM: Security Framework initializing
5937 01:03:17.624835 <6>[ 0.039157] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5938 01:03:17.631821 <6>[ 0.046779] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5939 01:03:17.638615 <4>[ 0.055647] cacheinfo: Unable to detect cache hierarchy for CPU 0
5940 01:03:17.649068 <6>[ 0.062272] cblist_init_generic: Setting adjustable number of callback queues.
5941 01:03:17.655290 <6>[ 0.069717] cblist_init_generic: Setting shift to 3 and lim to 1.
5942 01:03:17.661913 <6>[ 0.076069] cblist_init_generic: Setting adjustable number of callback queues.
5943 01:03:17.668527 <6>[ 0.083514] cblist_init_generic: Setting shift to 3 and lim to 1.
5944 01:03:17.671641 <6>[ 0.089913] rcu: Hierarchical SRCU implementation.
5945 01:03:17.678869 <6>[ 0.094938] rcu: Max phase no-delay instances is 1000.
5946 01:03:17.685180 <6>[ 0.102858] EFI services will not be available.
5947 01:03:17.688536 <6>[ 0.107804] smp: Bringing up secondary CPUs ...
5948 01:03:17.699186 <6>[ 0.113052] Detected VIPT I-cache on CPU1
5949 01:03:17.705662 <4>[ 0.113098] cacheinfo: Unable to detect cache hierarchy for CPU 1
5950 01:03:17.712538 <6>[ 0.113108] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5951 01:03:17.719128 <6>[ 0.113141] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5952 01:03:17.722482 <6>[ 0.113621] Detected VIPT I-cache on CPU2
5953 01:03:17.729585 <4>[ 0.113654] cacheinfo: Unable to detect cache hierarchy for CPU 2
5954 01:03:17.736006 <6>[ 0.113659] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5955 01:03:17.742830 <6>[ 0.113671] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5956 01:03:17.745849 <6>[ 0.114116] Detected VIPT I-cache on CPU3
5957 01:03:17.752615 <4>[ 0.114147] cacheinfo: Unable to detect cache hierarchy for CPU 3
5958 01:03:17.759523 <6>[ 0.114152] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5959 01:03:17.765639 <6>[ 0.114163] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5960 01:03:17.773048 <6>[ 0.114737] CPU features: detected: Spectre-v2
5961 01:03:17.775735 <6>[ 0.114747] CPU features: detected: Spectre-BHB
5962 01:03:17.782377 <6>[ 0.114751] CPU features: detected: ARM erratum 858921
5963 01:03:17.785643 <6>[ 0.114756] Detected VIPT I-cache on CPU4
5964 01:03:17.792424 <4>[ 0.114805] cacheinfo: Unable to detect cache hierarchy for CPU 4
5965 01:03:17.799406 <6>[ 0.114813] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5966 01:03:17.805755 <6>[ 0.114821] arch_timer: Enabling local workaround for ARM erratum 858921
5967 01:03:17.812227 <6>[ 0.114832] arch_timer: CPU4: Trapping CNTVCT access
5968 01:03:17.818953 <6>[ 0.114839] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5969 01:03:17.822366 <6>[ 0.115324] Detected VIPT I-cache on CPU5
5970 01:03:17.829186 <4>[ 0.115365] cacheinfo: Unable to detect cache hierarchy for CPU 5
5971 01:03:17.835397 <6>[ 0.115371] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5972 01:03:17.842094 <6>[ 0.115378] arch_timer: Enabling local workaround for ARM erratum 858921
5973 01:03:17.848637 <6>[ 0.115384] arch_timer: CPU5: Trapping CNTVCT access
5974 01:03:17.855709 <6>[ 0.115389] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5975 01:03:17.858740 <6>[ 0.115823] Detected VIPT I-cache on CPU6
5976 01:03:17.865329 <4>[ 0.115870] cacheinfo: Unable to detect cache hierarchy for CPU 6
5977 01:03:17.872272 <6>[ 0.115876] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5978 01:03:17.878642 <6>[ 0.115883] arch_timer: Enabling local workaround for ARM erratum 858921
5979 01:03:17.885465 <6>[ 0.115889] arch_timer: CPU6: Trapping CNTVCT access
5980 01:03:17.892114 <6>[ 0.115894] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5981 01:03:17.895255 <6>[ 0.116424] Detected VIPT I-cache on CPU7
5982 01:03:17.901715 <4>[ 0.116467] cacheinfo: Unable to detect cache hierarchy for CPU 7
5983 01:03:17.908168 <6>[ 0.116473] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5984 01:03:17.917929 <6>[ 0.116480] arch_timer: Enabling local workaround for ARM erratum 858921
5985 01:03:17.921788 <6>[ 0.116487] arch_timer: CPU7: Trapping CNTVCT access
5986 01:03:17.928176 <6>[ 0.116492] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5987 01:03:17.931310 <6>[ 0.116540] smp: Brought up 1 node, 8 CPUs
5988 01:03:17.938238 <6>[ 0.355437] SMP: Total of 8 processors activated.
5989 01:03:17.944462 <6>[ 0.360371] CPU features: detected: 32-bit EL0 Support
5990 01:03:17.947794 <6>[ 0.365750] CPU features: detected: 32-bit EL1 Support
5991 01:03:17.954893 <6>[ 0.371117] CPU features: detected: CRC32 instructions
5992 01:03:17.957895 <6>[ 0.376542] CPU: All CPU(s) started at EL2
5993 01:03:17.964437 <6>[ 0.380881] alternatives: applying system-wide alternatives
5994 01:03:17.971231 <6>[ 0.388902] devtmpfs: initialized
5995 01:03:17.984184 <6>[ 0.397866] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5996 01:03:17.993810 <6>[ 0.407814] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5997 01:03:17.997084 <6>[ 0.415542] pinctrl core: initialized pinctrl subsystem
5998 01:03:18.005168 <6>[ 0.422658] DMI not present or invalid.
5999 01:03:18.011523 <6>[ 0.427025] NET: Registered PF_NETLINK/PF_ROUTE protocol family
6000 01:03:18.018716 <6>[ 0.433931] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
6001 01:03:18.028594 <6>[ 0.441460] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
6002 01:03:18.034952 <6>[ 0.449712] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
6003 01:03:18.041469 <6>[ 0.457890] audit: initializing netlink subsys (disabled)
6004 01:03:18.048006 <5>[ 0.463593] audit: type=2000 audit(0.328:1): state=initialized audit_enabled=0 res=1
6005 01:03:18.054907 <6>[ 0.464566] thermal_sys: Registered thermal governor 'step_wise'
6006 01:03:18.061663 <6>[ 0.471559] thermal_sys: Registered thermal governor 'power_allocator'
6007 01:03:18.064915 <6>[ 0.477856] cpuidle: using governor menu
6008 01:03:18.071798 <6>[ 0.488817] NET: Registered PF_QIPCRTR protocol family
6009 01:03:18.077908 <6>[ 0.494311] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
6010 01:03:18.085121 <6>[ 0.501407] ASID allocator initialised with 32768 entries
6011 01:03:18.091306 <6>[ 0.508176] Serial: AMBA PL011 UART driver
6012 01:03:18.100804 <4>[ 0.518582] Trying to register duplicate clock ID: 113
6013 01:03:18.161141 <6>[ 0.574835] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6014 01:03:18.175090 <6>[ 0.589178] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6015 01:03:18.178292 <6>[ 0.598930] KASLR enabled
6016 01:03:18.192521 <6>[ 0.606930] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
6017 01:03:18.199514 <6>[ 0.613933] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
6018 01:03:18.206413 <6>[ 0.620411] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
6019 01:03:18.212958 <6>[ 0.627401] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
6020 01:03:18.219591 <6>[ 0.633876] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
6021 01:03:18.225710 <6>[ 0.640866] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
6022 01:03:18.232886 <6>[ 0.647339] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
6023 01:03:18.239179 <6>[ 0.654328] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
6024 01:03:18.242409 <6>[ 0.661899] ACPI: Interpreter disabled.
6025 01:03:18.252755 <6>[ 0.669897] iommu: Default domain type: Translated
6026 01:03:18.259506 <6>[ 0.675003] iommu: DMA domain TLB invalidation policy: strict mode
6027 01:03:18.262547 <5>[ 0.681633] SCSI subsystem initialized
6028 01:03:18.269322 <6>[ 0.686049] usbcore: registered new interface driver usbfs
6029 01:03:18.275595 <6>[ 0.691776] usbcore: registered new interface driver hub
6030 01:03:18.279396 <6>[ 0.697318] usbcore: registered new device driver usb
6031 01:03:18.286233 <6>[ 0.703621] pps_core: LinuxPPS API ver. 1 registered
6032 01:03:18.295855 <6>[ 0.708806] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
6033 01:03:18.299211 <6>[ 0.718130] PTP clock support registered
6034 01:03:18.302977 <6>[ 0.722384] EDAC MC: Ver: 3.0.0
6035 01:03:18.310312 <6>[ 0.728020] FPGA manager framework
6036 01:03:18.317124 <6>[ 0.731703] Advanced Linux Sound Architecture Driver Initialized.
6037 01:03:18.320365 <6>[ 0.738455] vgaarb: loaded
6038 01:03:18.326792 <6>[ 0.741581] clocksource: Switched to clocksource arch_sys_counter
6039 01:03:18.330751 <5>[ 0.748010] VFS: Disk quotas dquot_6.6.0
6040 01:03:18.336833 <6>[ 0.752185] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
6041 01:03:18.339991 <6>[ 0.759359] pnp: PnP ACPI: disabled
6042 01:03:18.348663 <6>[ 0.766220] NET: Registered PF_INET protocol family
6043 01:03:18.355339 <6>[ 0.771443] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6044 01:03:18.367377 <6>[ 0.781346] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6045 01:03:18.377202 <6>[ 0.790098] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6046 01:03:18.383479 <6>[ 0.798049] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6047 01:03:18.390123 <6>[ 0.806283] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6048 01:03:18.400370 <6>[ 0.814377] TCP: Hash tables configured (established 32768 bind 32768)
6049 01:03:18.406968 <6>[ 0.821201] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6050 01:03:18.413449 <6>[ 0.828171] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6051 01:03:18.420276 <6>[ 0.835648] NET: Registered PF_UNIX/PF_LOCAL protocol family
6052 01:03:18.427104 <6>[ 0.841770] RPC: Registered named UNIX socket transport module.
6053 01:03:18.430282 <6>[ 0.847914] RPC: Registered udp transport module.
6054 01:03:18.436707 <6>[ 0.852839] RPC: Registered tcp transport module.
6055 01:03:18.443595 <6>[ 0.857761] RPC: Registered tcp NFSv4.1 backchannel transport module.
6056 01:03:18.446800 <6>[ 0.864413] PCI: CLS 0 bytes, default 64
6057 01:03:18.450226 <6>[ 0.868697] Unpacking initramfs...
6058 01:03:18.475815 <6>[ 0.889735] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6059 01:03:18.485273 <6>[ 0.898490] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6060 01:03:18.488440 <6>[ 0.907402] kvm [1]: IPA Size Limit: 40 bits
6061 01:03:18.496205 <6>[ 0.913754] kvm [1]: vgic-v2@c420000
6062 01:03:18.499841 <6>[ 0.917580] kvm [1]: GIC system register CPU interface enabled
6063 01:03:18.506118 <6>[ 0.923769] kvm [1]: vgic interrupt IRQ18
6064 01:03:18.509803 <6>[ 0.928147] kvm [1]: Hyp mode initialized successfully
6065 01:03:18.517111 <5>[ 0.934518] Initialise system trusted keyrings
6066 01:03:18.523816 <6>[ 0.939370] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6067 01:03:18.531909 <6>[ 0.949347] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6068 01:03:18.538443 <5>[ 0.955796] NFS: Registering the id_resolver key type
6069 01:03:18.542085 <5>[ 0.961104] Key type id_resolver registered
6070 01:03:18.548509 <5>[ 0.965517] Key type id_legacy registered
6071 01:03:18.554891 <6>[ 0.969825] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6072 01:03:18.561544 <6>[ 0.976745] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6073 01:03:18.568206 <6>[ 0.984507] 9p: Installing v9fs 9p2000 file system support
6074 01:03:18.595324 <5>[ 1.012970] Key type asymmetric registered
6075 01:03:18.598663 <5>[ 1.017319] Asymmetric key parser 'x509' registered
6076 01:03:18.608763 <6>[ 1.022478] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6077 01:03:18.612389 <6>[ 1.030094] io scheduler mq-deadline registered
6078 01:03:18.615461 <6>[ 1.034850] io scheduler kyber registered
6079 01:03:18.638114 <6>[ 1.055658] EINJ: ACPI disabled.
6080 01:03:18.644886 <4>[ 1.059425] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6081 01:03:18.682969 <6>[ 1.100309] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6082 01:03:18.691223 <6>[ 1.108793] printk: console [ttyS0] disabled
6083 01:03:18.719520 <6>[ 1.133443] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6084 01:03:18.726527 <6>[ 1.142917] printk: console [ttyS0] enabled
6085 01:03:18.729555 <6>[ 1.142917] printk: console [ttyS0] enabled
6086 01:03:18.736209 <6>[ 1.151838] printk: bootconsole [mtk8250] disabled
6087 01:03:18.739434 <6>[ 1.151838] printk: bootconsole [mtk8250] disabled
6088 01:03:18.749412 <3>[ 1.162381] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6089 01:03:18.755755 <3>[ 1.170764] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6090 01:03:18.785210 <6>[ 1.199186] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6091 01:03:18.791542 <6>[ 1.208843] serial serial0: tty port ttyS1 registered
6092 01:03:18.798134 <6>[ 1.215385] SuperH (H)SCI(F) driver initialized
6093 01:03:18.801350 <6>[ 1.220891] msm_serial: driver initialized
6094 01:03:18.817890 <6>[ 1.231247] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6095 01:03:18.826898 <6>[ 1.239848] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6096 01:03:18.833891 <6>[ 1.248419] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6097 01:03:18.843375 <6>[ 1.256988] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6098 01:03:18.849883 <6>[ 1.265644] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6099 01:03:18.860066 <6>[ 1.274307] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6100 01:03:18.870280 <6>[ 1.283043] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6101 01:03:18.877023 <6>[ 1.291782] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6102 01:03:18.886745 <6>[ 1.300351] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6103 01:03:18.896545 <6>[ 1.309155] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6104 01:03:18.904290 <4>[ 1.321520] cacheinfo: Unable to detect cache hierarchy for CPU 0
6105 01:03:18.913887 <6>[ 1.330967] loop: module loaded
6106 01:03:18.925741 <6>[ 1.342898] vsim1: Bringing 1800000uV into 2700000-2700000uV
6107 01:03:18.943425 <6>[ 1.360933] megasas: 07.719.03.00-rc1
6108 01:03:18.952085 <6>[ 1.369749] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6109 01:03:18.959599 <6>[ 1.376959] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6110 01:03:18.976666 <6>[ 1.393728] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6111 01:03:19.033435 <6>[ 1.443818] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6112 01:03:19.071361 <6>[ 1.489007] Freeing initrd memory: 18296K
6113 01:03:19.084906 <4>[ 1.498998] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6114 01:03:19.091445 <4>[ 1.508237] CPU: 6 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1
6115 01:03:19.098185 <4>[ 1.514936] Hardware name: Google juniper sku16 board (DT)
6116 01:03:19.101294 <4>[ 1.520675] Call trace:
6117 01:03:19.104778 <4>[ 1.523375] dump_backtrace.part.0+0xe0/0xf0
6118 01:03:19.107911 <4>[ 1.527912] show_stack+0x18/0x30
6119 01:03:19.111776 <4>[ 1.531484] dump_stack_lvl+0x68/0x84
6120 01:03:19.117783 <4>[ 1.535404] dump_stack+0x18/0x34
6121 01:03:19.121520 <4>[ 1.538974] sysfs_warn_dup+0x64/0x80
6122 01:03:19.124460 <4>[ 1.542895] sysfs_do_create_link_sd+0xf0/0x100
6123 01:03:19.128917 <4>[ 1.547683] sysfs_create_link+0x20/0x40
6124 01:03:19.132017 <4>[ 1.551862] bus_add_device+0x68/0x10c
6125 01:03:19.135745 <4>[ 1.555868] device_add+0x340/0x7ac
6126 01:03:19.142417 <4>[ 1.559611] of_device_add+0x44/0x60
6127 01:03:19.145525 <4>[ 1.563445] of_platform_device_create_pdata+0x90/0x120
6128 01:03:19.151992 <4>[ 1.568926] of_platform_bus_create+0x170/0x370
6129 01:03:19.155807 <4>[ 1.573713] of_platform_populate+0x50/0xfc
6130 01:03:19.158974 <4>[ 1.578152] parse_mtd_partitions+0x1dc/0x510
6131 01:03:19.165326 <4>[ 1.582765] mtd_device_parse_register+0xf8/0x2e0
6132 01:03:19.168651 <4>[ 1.587723] spi_nor_probe+0x21c/0x2f0
6133 01:03:19.172376 <4>[ 1.591729] spi_mem_probe+0x6c/0xb0
6134 01:03:19.175537 <4>[ 1.595562] spi_probe+0x84/0xe4
6135 01:03:19.182164 <4>[ 1.599044] really_probe+0xbc/0x2e0
6136 01:03:19.185318 <4>[ 1.602874] __driver_probe_device+0x78/0x11c
6137 01:03:19.188416 <4>[ 1.607485] driver_probe_device+0xd8/0x160
6138 01:03:19.194973 <4>[ 1.611923] __device_attach_driver+0xb8/0x134
6139 01:03:19.198783 <4>[ 1.616622] bus_for_each_drv+0x78/0xd0
6140 01:03:19.201776 <4>[ 1.620712] __device_attach+0xa8/0x1c0
6141 01:03:19.208651 <4>[ 1.624802] device_initial_probe+0x14/0x20
6142 01:03:19.211484 <4>[ 1.629241] bus_probe_device+0x9c/0xa4
6143 01:03:19.214721 <4>[ 1.633331] device_add+0x3ac/0x7ac
6144 01:03:19.218136 <4>[ 1.637073] __spi_add_device+0x78/0x120
6145 01:03:19.221722 <4>[ 1.641251] spi_add_device+0x40/0x7c
6146 01:03:19.228393 <4>[ 1.645168] spi_register_controller+0x610/0xad0
6147 01:03:19.231739 <4>[ 1.650041] devm_spi_register_controller+0x4c/0xa4
6148 01:03:19.235035 <4>[ 1.655174] mtk_spi_probe+0x3f8/0x650
6149 01:03:19.241538 <4>[ 1.659179] platform_probe+0x68/0xe0
6150 01:03:19.244922 <4>[ 1.663097] really_probe+0xbc/0x2e0
6151 01:03:19.248163 <4>[ 1.666927] __driver_probe_device+0x78/0x11c
6152 01:03:19.254899 <4>[ 1.671538] driver_probe_device+0xd8/0x160
6153 01:03:19.258319 <4>[ 1.675976] __driver_attach+0x94/0x19c
6154 01:03:19.261552 <4>[ 1.680066] bus_for_each_dev+0x70/0xd0
6155 01:03:19.264943 <4>[ 1.684156] driver_attach+0x24/0x30
6156 01:03:19.268327 <4>[ 1.687986] bus_add_driver+0x154/0x20c
6157 01:03:19.274747 <4>[ 1.692076] driver_register+0x78/0x130
6158 01:03:19.278402 <4>[ 1.696167] __platform_driver_register+0x28/0x34
6159 01:03:19.281722 <4>[ 1.701127] mtk_spi_driver_init+0x1c/0x28
6160 01:03:19.288452 <4>[ 1.705481] do_one_initcall+0x50/0x1d0
6161 01:03:19.291552 <4>[ 1.709571] kernel_init_freeable+0x21c/0x288
6162 01:03:19.294506 <4>[ 1.714184] kernel_init+0x24/0x12c
6163 01:03:19.298170 <4>[ 1.717930] ret_from_fork+0x10/0x20
6164 01:03:19.309071 <6>[ 1.726697] tun: Universal TUN/TAP device driver, 1.6
6165 01:03:19.312320 <6>[ 1.732976] thunder_xcv, ver 1.0
6166 01:03:19.316074 <6>[ 1.736493] thunder_bgx, ver 1.0
6167 01:03:19.319077 <6>[ 1.740058] nicpf, ver 1.0
6168 01:03:19.330290 <6>[ 1.744430] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6169 01:03:19.333433 <6>[ 1.751914] hns3: Copyright (c) 2017 Huawei Corporation.
6170 01:03:19.337214 <6>[ 1.757513] hclge is initializing
6171 01:03:19.343681 <6>[ 1.761096] e1000: Intel(R) PRO/1000 Network Driver
6172 01:03:19.350218 <6>[ 1.766232] e1000: Copyright (c) 1999-2006 Intel Corporation.
6173 01:03:19.353153 <6>[ 1.772257] e1000e: Intel(R) PRO/1000 Network Driver
6174 01:03:19.360236 <6>[ 1.777478] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6175 01:03:19.366732 <6>[ 1.783670] igb: Intel(R) Gigabit Ethernet Network Driver
6176 01:03:19.373214 <6>[ 1.789327] igb: Copyright (c) 2007-2014 Intel Corporation.
6177 01:03:19.379850 <6>[ 1.795172] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6178 01:03:19.386467 <6>[ 1.801698] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6179 01:03:19.390198 <6>[ 1.808256] sky2: driver version 1.30
6180 01:03:19.396495 <6>[ 1.813516] usbcore: registered new device driver r8152-cfgselector
6181 01:03:19.403627 <6>[ 1.820064] usbcore: registered new interface driver r8152
6182 01:03:19.410155 <6>[ 1.825896] VFIO - User Level meta-driver version: 0.3
6183 01:03:19.416645 <6>[ 1.833720] mtu3 11201000.usb: uwk - reg:0x420, version:101
6184 01:03:19.422982 <4>[ 1.839588] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6185 01:03:19.430154 <6>[ 1.846874] mtu3 11201000.usb: dr_mode: 1, drd: auto
6186 01:03:19.436637 <6>[ 1.852100] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6187 01:03:19.439818 <6>[ 1.858276] mtu3 11201000.usb: usb3-drd: 0
6188 01:03:19.449718 <6>[ 1.863824] mtu3 11201000.usb: xHCI platform device register success...
6189 01:03:19.456352 <4>[ 1.872449] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6190 01:03:19.463080 <6>[ 1.880374] xhci-mtk 11200000.usb: xHCI Host Controller
6191 01:03:19.470058 <6>[ 1.885875] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6192 01:03:19.476310 <6>[ 1.893599] xhci-mtk 11200000.usb: USB3 root hub has no ports
6193 01:03:19.486187 <6>[ 1.899606] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6194 01:03:19.493242 <6>[ 1.909028] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6195 01:03:19.499782 <6>[ 1.915111] xhci-mtk 11200000.usb: xHCI Host Controller
6196 01:03:19.506701 <6>[ 1.920599] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6197 01:03:19.512996 <6>[ 1.928256] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6198 01:03:19.516306 <6>[ 1.935079] hub 1-0:1.0: USB hub found
6199 01:03:19.519955 <6>[ 1.939108] hub 1-0:1.0: 1 port detected
6200 01:03:19.530521 <6>[ 1.944439] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6201 01:03:19.533973 <6>[ 1.953054] hub 2-0:1.0: USB hub found
6202 01:03:19.540286 <3>[ 1.957088] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6203 01:03:19.547492 <6>[ 1.964966] usbcore: registered new interface driver usb-storage
6204 01:03:19.554060 <6>[ 1.971575] usbcore: registered new device driver onboard-usb-hub
6205 01:03:19.567363 <4>[ 1.981677] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6206 01:03:19.576758 <6>[ 1.993899] mt6397-rtc mt6358-rtc: registered as rtc0
6207 01:03:19.586317 <6>[ 1.999374] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-16T01:03:19 UTC (1718499799)
6208 01:03:19.589537 <6>[ 2.009253] i2c_dev: i2c /dev entries driver
6209 01:03:19.601361 <6>[ 2.015632] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6210 01:03:19.611459 <6>[ 2.023951] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6211 01:03:19.614727 <6>[ 2.032856] i2c 4-0058: Fixed dependency cycle(s) with /panel
6212 01:03:19.624909 <6>[ 2.038887] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6213 01:03:19.631309 <3>[ 2.046355] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
6214 01:03:19.648826 <6>[ 2.066186] cpu cpu0: EM: created perf domain
6215 01:03:19.658858 <6>[ 2.071667] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6216 01:03:19.665474 <6>[ 2.082954] cpu cpu4: EM: created perf domain
6217 01:03:19.672562 <6>[ 2.090129] sdhci: Secure Digital Host Controller Interface driver
6218 01:03:19.679737 <6>[ 2.096575] sdhci: Copyright(c) Pierre Ossman
6219 01:03:19.686220 <6>[ 2.101987] Synopsys Designware Multimedia Card Interface Driver
6220 01:03:19.692788 <6>[ 2.102511] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6221 01:03:19.696136 <6>[ 2.109058] sdhci-pltfm: SDHCI platform and OF driver helper
6222 01:03:19.704599 <6>[ 2.121869] ledtrig-cpu: registered to indicate activity on CPUs
6223 01:03:19.712451 <6>[ 2.129594] usbcore: registered new interface driver usbhid
6224 01:03:19.715601 <6>[ 2.135429] usbhid: USB HID core driver
6225 01:03:19.726161 <6>[ 2.139748] spi_master spi2: will run message pump with realtime priority
6226 01:03:19.729805 <4>[ 2.139893] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6227 01:03:19.740418 <4>[ 2.154095] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6228 01:03:19.750404 <6>[ 2.158761] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6229 01:03:19.770057 <6>[ 2.177364] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6230 01:03:19.776572 <6>[ 2.192125] cros-ec-spi spi2.0: Chrome EC device registered
6231 01:03:19.783325 <4>[ 2.198970] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6232 01:03:19.801172 <4>[ 2.215269] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6233 01:03:19.812875 <4>[ 2.227243] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6234 01:03:19.820020 <4>[ 2.236076] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6235 01:03:19.832191 <6>[ 2.246281] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6236 01:03:19.861868 <6>[ 2.278737] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x12c14
6237 01:03:19.869584 <6>[ 2.287017] mmc0: new HS400 MMC card at address 0001
6238 01:03:19.876450 <6>[ 2.293220] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6239 01:03:19.883176 <6>[ 2.295732] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6240 01:03:19.889483 <6>[ 2.304153] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6241 01:03:19.899920 <6>[ 2.310153] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6242 01:03:19.912936 <6>[ 2.314247] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6243 01:03:19.919660 <6>[ 2.315840] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6244 01:03:19.922937 <6>[ 2.317145] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6245 01:03:19.929461 <6>[ 2.318163] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6246 01:03:19.935964 <6>[ 2.324781] NET: Registered PF_PACKET protocol family
6247 01:03:19.946418 <6>[ 2.336015] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6248 01:03:19.949616 <6>[ 2.340868] 9pnet: Installing 9P2000 support
6249 01:03:19.956329 <6>[ 2.365595] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6250 01:03:19.959536 <5>[ 2.367816] Key type dns_resolver registered
6251 01:03:19.966724 <6>[ 2.384056] registered taskstats version 1
6252 01:03:19.969725 <5>[ 2.388429] Loading compiled-in X.509 certificates
6253 01:03:20.013285 <3>[ 2.427583] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6254 01:03:20.042307 <6>[ 2.452993] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6255 01:03:20.052440 <6>[ 2.466443] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6256 01:03:20.062227 <6>[ 2.475004] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6257 01:03:20.068830 <6>[ 2.483528] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6258 01:03:20.079073 <6>[ 2.492054] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6259 01:03:20.085340 <6>[ 2.500575] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6260 01:03:20.095481 <6>[ 2.509094] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6261 01:03:20.105646 <6>[ 2.517615] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6262 01:03:20.108503 <6>[ 2.520541] hub 1-1:1.0: USB hub found
6263 01:03:20.115159 <6>[ 2.526838] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6264 01:03:20.118970 <6>[ 2.530537] hub 1-1:1.0: 3 ports detected
6265 01:03:20.124959 <6>[ 2.537659] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6266 01:03:20.131285 <6>[ 2.548282] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6267 01:03:20.141251 <6>[ 2.555619] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6268 01:03:20.148277 <6>[ 2.563102] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6269 01:03:20.154922 <6>[ 2.571406] panfrost 13040000.gpu: clock rate = 511999970
6270 01:03:20.164985 <6>[ 2.577101] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6271 01:03:20.174324 <6>[ 2.587501] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6272 01:03:20.180924 <6>[ 2.595533] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6273 01:03:20.194606 <6>[ 2.603965] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6274 01:03:20.200759 <6>[ 2.616045] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6275 01:03:20.213685 <6>[ 2.628107] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6276 01:03:20.223791 <6>[ 2.637410] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6277 01:03:20.234230 <6>[ 2.646580] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6278 01:03:20.243885 <6>[ 2.655710] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6279 01:03:20.250370 <6>[ 2.664841] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6280 01:03:20.260488 <6>[ 2.674143] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6281 01:03:20.270281 <6>[ 2.683443] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6282 01:03:20.280111 <6>[ 2.692916] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6283 01:03:20.290229 <6>[ 2.702394] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6284 01:03:20.299953 <6>[ 2.711521] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6285 01:03:20.371773 <6>[ 2.785435] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6286 01:03:20.381048 <6>[ 2.794358] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6287 01:03:20.391239 <6>[ 2.805590] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6288 01:03:20.415180 <6>[ 2.829586] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6289 01:03:21.098197 <6>[ 3.021985] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6290 01:03:21.108286 <4>[ 3.134224] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6291 01:03:21.114918 <4>[ 3.134243] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6292 01:03:21.121560 <6>[ 3.171333] r8152 1-1.2:1.0 eth0: v1.12.13
6293 01:03:21.128358 <6>[ 3.249609] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6294 01:03:21.134530 <6>[ 3.495782] Console: switching to colour frame buffer device 170x48
6295 01:03:21.141019 <6>[ 3.556437] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6296 01:03:21.163143 <6>[ 3.573761] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6297 01:03:21.180055 <6>[ 3.590843] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6298 01:03:21.189905 <6>[ 3.603583] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6299 01:03:21.197088 <6>[ 3.611893] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6300 01:03:21.209749 <6>[ 3.618898] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6301 01:03:21.227104 <6>[ 3.638035] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6302 01:03:22.355907 <6>[ 4.773461] r8152 1-1.2:1.0 eth0: carrier on
6303 01:03:25.312196 <5>[ 4.801614] Sending DHCP requests .., OK
6304 01:03:25.318825 <6>[ 7.733987] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6305 01:03:25.322502 <6>[ 7.742430] IP-Config: Complete:
6306 01:03:25.335465 <6>[ 7.746001] device=eth0, hwaddr=00:e0:4c:72:3d:67, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6307 01:03:25.345218 <6>[ 7.756901] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-1, domain=lava-rack, nis-domain=(none)
6308 01:03:25.356990 <6>[ 7.771182] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6309 01:03:25.366143 <6>[ 7.771193] nameserver0=192.168.201.1
6310 01:03:25.373859 <6>[ 7.791039] clk: Disabling unused clocks
6311 01:03:25.378144 <6>[ 7.798973] ALSA device list:
6312 01:03:25.387825 <6>[ 7.805012] No soundcards found.
6313 01:03:25.396616 <6>[ 7.814055] Freeing unused kernel memory: 8512K
6314 01:03:25.403678 <6>[ 7.821192] Run /init as init process
6315 01:03:25.415480 Loading, please wait...
6316 01:03:25.451520 Starting systemd-udevd version 252.22-1~deb12u1
6317 01:03:25.785062 <6>[ 8.198973] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6318 01:03:25.798965 <4>[ 8.213096] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6319 01:03:25.813951 <6>[ 8.224911] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6320 01:03:25.823873 <3>[ 8.235970] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6321 01:03:25.830484 <4>[ 8.236016] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6322 01:03:25.837228 <3>[ 8.236145] mtk-scp 10500000.scp: invalid resource
6323 01:03:25.846891 <6>[ 8.236212] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6324 01:03:25.857546 <6>[ 8.237381] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6325 01:03:25.870159 <3>[ 8.237772] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6326 01:03:25.873806 <6>[ 8.239511] remoteproc remoteproc0: scp is available
6327 01:03:25.883555 <4>[ 8.239871] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6328 01:03:25.886820 <6>[ 8.239879] remoteproc remoteproc0: powering up scp
6329 01:03:25.896866 <4>[ 8.239894] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6330 01:03:25.904037 <3>[ 8.239898] remoteproc remoteproc0: request_firmware failed: -2
6331 01:03:25.910266 <3>[ 8.246042] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6332 01:03:25.920378 <4>[ 8.261094] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6333 01:03:25.930529 <3>[ 8.268137] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6334 01:03:25.940520 <3>[ 8.279073] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6335 01:03:25.947541 <3>[ 8.291476] elan_i2c 2-0015: Error applying setting, reverse things back
6336 01:03:25.954755 <3>[ 8.296716] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6337 01:03:25.961151 <6>[ 8.298249] mc: Linux media interface: v0.10
6338 01:03:25.967766 <6>[ 8.335155] cs_system_cfg: CoreSight Configuration manager initialised
6339 01:03:25.974687 <6>[ 8.335155] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6340 01:03:25.984700 <3>[ 8.341937] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6341 01:03:25.994803 <5>[ 8.348006] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6342 01:03:26.001598 <6>[ 8.353432] videodev: Linux video capture interface: v2.00
6343 01:03:26.008434 <3>[ 8.361526] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6344 01:03:26.014814 <5>[ 8.367352] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6345 01:03:26.024856 <5>[ 8.367830] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6346 01:03:26.034726 <4>[ 8.367905] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6347 01:03:26.037876 <6>[ 8.367915] cfg80211: failed to load regulatory.db
6348 01:03:26.048085 <6>[ 8.422224] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6349 01:03:26.057786 <3>[ 8.422627] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6350 01:03:26.064535 <6>[ 8.439286] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6351 01:03:26.074486 <3>[ 8.447019] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6352 01:03:26.077740 <6>[ 8.447753] Bluetooth: Core ver 2.22
6353 01:03:26.081063 <6>[ 8.447814] NET: Registered PF_BLUETOOTH protocol family
6354 01:03:26.088034 <6>[ 8.447817] Bluetooth: HCI device and connection manager initialized
6355 01:03:26.094720 <6>[ 8.447833] Bluetooth: HCI socket layer initialized
6356 01:03:26.101543 <6>[ 8.447839] Bluetooth: L2CAP socket layer initialized
6357 01:03:26.107984 <6>[ 8.447849] Bluetooth: SCO socket layer initialized
6358 01:03:26.114726 <6>[ 8.456089] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6359 01:03:26.124374 <3>[ 8.460945] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6360 01:03:26.134723 <3>[ 8.460957] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6361 01:03:26.141158 <3>[ 8.460998] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6362 01:03:26.154517 <3>[ 8.461215] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6363 01:03:26.161016 <6>[ 8.470840] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6364 01:03:26.167824 <3>[ 8.479519] debugfs: File 'Playback' in directory 'dapm' already present!
6365 01:03:26.178681 <6>[ 8.480041] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6366 01:03:26.185471 <6>[ 8.480087] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6367 01:03:26.195158 Begin: Loading essential drivers<6>[ 8.480528] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6368 01:03:26.198699 ... done.
6369 01:03:26.208557 Begin: Running /scri<6>[ 8.480737] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6370 01:03:26.208633 pts/init-premount ... done.
6371 01:03:26.218366 Beg<6>[ 8.487582] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6372 01:03:26.228988 in: Mounting root file system ..<6>[ 8.487627] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6373 01:03:26.239002 . Begin: Running /scripts/nfs-to<3>[ 8.495408] debugfs: File 'Capture' in directory 'dapm' already present!
6374 01:03:26.239105 p ... done.
6375 01:03:26.248204 Begin: Running /scr<6>[ 8.504742] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6376 01:03:26.255305 ipts/nfs-premount ... Waiting up<6>[ 8.504924] Bluetooth: HCI UART driver ver 2.3
6377 01:03:26.264732 to 60 secs for any ethernet to <6>[ 8.504928] Bluetooth: HCI UART protocol H4 registered
6378 01:03:26.264810 become available
6379 01:03:26.271439 Device /sys/cl<6>[ 8.504964] Bluetooth: HCI UART protocol LL registered
6380 01:03:26.274845 ass/net/eth0 found
6381 01:03:26.274921 done.
6382 01:03:26.281593 Begin<6>[ 8.504977] Bluetooth: HCI UART protocol Three-wire (H5) registered
6383 01:03:26.291482 : Waiting up to 180 secs for any<6>[ 8.505343] Bluetooth: HCI UART protocol Broadcom registered
6384 01:03:26.297854 network device to become availa<6>[ 8.505372] Bluetooth: HCI UART protocol QCA registered
6385 01:03:26.297933 ble ... done.
6386 01:03:26.304787 <6>[ 8.505387] Bluetooth: HCI UART protocol Marvell registered
6387 01:03:26.311416 <6>[ 8.506338] Bluetooth: hci0: setting up ROME/QCA6390
6388 01:03:26.325407 <6>[ 8.506567] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6389 01:03:26.328706 <6>[ 8.506813] usbcore: registered new interface driver uvcvideo
6390 01:03:26.344764 <6>[ 8.506823] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6391 01:03:26.352869 <3>[ 8.508190] thermal_sys: Failed to find 'trips' node
6392 01:03:26.363551 <3>[ 8.508195] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6393 01:03:26.373412 <3>[ 8.508203] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6394 01:03:26.383705 <4>[ 8.508206] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6395 01:03:26.386863 <3>[ 8.509414] thermal_sys: Failed to find 'trips' node
6396 01:03:26.398429 <3>[ 8.509419] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6397 01:03:26.408578 IP-Config: eth0 hardware address<3>[ 8.509426] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6398 01:03:26.418496 00:e0:4c:72:3d:67 mtu 1500 DHCP<4>[ 8.509428] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6399 01:03:26.418575
6400 01:03:26.428229 IP-Config: eth<6>[ 8.517249] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6401 01:03:26.441501 0 complete (dhcp<6>[ 8.544230] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6402 01:03:26.448103 from 192.168.20<6>[ 8.547112] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6403 01:03:26.451607 1.1):
6404 01:03:26.458204 address:<6>[ 8.555535] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6405 01:03:26.468246 192.168.201.13 <6>[ 8.564100] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6406 01:03:26.481200 broadcast: 192<6>[ 8.576195] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6407 01:03:26.491107 .168.201.255 ne<4>[ 8.723470] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6408 01:03:26.497554 <4>[ 8.723470] Fallback method does not support PEC.
6409 01:03:26.504018 tmask: 255.255.2<3>[ 8.737030] Bluetooth: hci0: Frame reassembly failed (-84)
6410 01:03:26.504098 55.0
6411 01:03:26.511836 gatewa<3>[ 8.798120] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6412 01:03:26.521922 y: 192.168.201.1<6>[ 8.921881] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6413 01:03:26.534913 dns0 : 192.168.201.1 <3>[ 8.934222] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6414 01:03:26.534998 dns1 : 0.0.0.0
6415 01:03:26.541730 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-1
6416 01:03:26.548149 domain : lava-rack
6417 01:03:26.551747 rootserver: 192.168.201.1 rootpath:
6418 01:03:26.555198 filename :
6419 01:03:26.555276 done.
6420 01:03:26.557955 Begin: Running /scripts/nfs-bottom ... done.
6421 01:03:26.561157 Begin: Running /scripts/init-bottom ... done.
6422 01:03:26.616881 <6>[ 9.034439] Bluetooth: hci0: QCA Product ID :0x00000008
6423 01:03:26.626138 <6>[ 9.043738] Bluetooth: hci0: QCA SOC Version :0x00000044
6424 01:03:26.634818 <6>[ 9.052233] Bluetooth: hci0: QCA ROM Version :0x00000302
6425 01:03:26.643613 <6>[ 9.060452] Bluetooth: hci0: QCA Patch Version:0x00000111
6426 01:03:26.651205 <6>[ 9.068332] Bluetooth: hci0: QCA controller version 0x00440302
6427 01:03:26.662273 <6>[ 9.076480] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6428 01:03:26.672378 <4>[ 9.085191] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6429 01:03:26.682760 <3>[ 9.096814] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6430 01:03:26.689588 <3>[ 9.106959] Bluetooth: hci0: QCA Failed to download patch (-2)
6431 01:03:26.871849 <6>[ 9.286050] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6432 01:03:26.955223 <4>[ 9.368856] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6433 01:03:26.973934 <4>[ 9.388190] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6434 01:03:26.990394 <4>[ 9.404345] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6435 01:03:27.000212 <4>[ 9.417347] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6436 01:03:27.917025 <6>[ 10.334560] NET: Registered PF_INET6 protocol family
6437 01:03:27.929118 <6>[ 10.346500] Segment Routing with IPv6
6438 01:03:27.937643 <6>[ 10.354822] In-situ OAM (IOAM) with IPv6
6439 01:03:28.120206 <30>[ 10.511308] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6440 01:03:28.141840 <30>[ 10.558803] systemd[1]: Detected architecture arm64.
6441 01:03:28.152742
6442 01:03:28.156175 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6443 01:03:28.156254
6444 01:03:28.181698 <30>[ 10.599160] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6445 01:03:29.161966 <30>[ 11.576128] systemd[1]: Queued start job for default target graphical.target.
6446 01:03:29.200734 <30>[ 11.614952] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6447 01:03:29.213164 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6448 01:03:29.233901 <30>[ 11.647999] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6449 01:03:29.247721 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6450 01:03:29.266634 <30>[ 11.680134] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6451 01:03:29.280125 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6452 01:03:29.297333 <30>[ 11.711209] systemd[1]: Created slice user.slice - User and Session Slice.
6453 01:03:29.309370 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6454 01:03:29.331341 <30>[ 11.742181] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6455 01:03:29.344674 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6456 01:03:29.367816 <30>[ 11.778003] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6457 01:03:29.379664 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6458 01:03:29.405824 <30>[ 11.809956] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6459 01:03:29.426779 <30>[ 11.840112] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6460 01:03:29.434806 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6461 01:03:29.455967 <30>[ 11.869920] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6462 01:03:29.468823 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6463 01:03:29.488056 <30>[ 11.901832] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6464 01:03:29.502075 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6465 01:03:29.516702 <30>[ 11.933874] systemd[1]: Reached target paths.target - Path Units.
6466 01:03:29.531282 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6467 01:03:29.547657 <30>[ 11.961765] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6468 01:03:29.560038 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6469 01:03:29.572367 <30>[ 11.989745] systemd[1]: Reached target slices.target - Slice Units.
6470 01:03:29.587046 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6471 01:03:29.600860 <30>[ 12.017782] systemd[1]: Reached target swap.target - Swaps.
6472 01:03:29.611452 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6473 01:03:29.631834 <30>[ 12.045836] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6474 01:03:29.645347 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6475 01:03:29.664155 <30>[ 12.078238] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6476 01:03:29.678249 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6477 01:03:29.698832 <30>[ 12.112965] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6478 01:03:29.711074 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6479 01:03:29.729637 <30>[ 12.143694] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6480 01:03:29.743554 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6481 01:03:29.760528 <30>[ 12.174663] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6482 01:03:29.773089 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6483 01:03:29.793820 <30>[ 12.207515] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6484 01:03:29.807290 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6485 01:03:29.826956 <30>[ 12.240706] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6486 01:03:29.839994 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6487 01:03:29.856487 <30>[ 12.270346] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6488 01:03:29.869489 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6489 01:03:29.908818 <30>[ 12.322748] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6490 01:03:29.920149 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6491 01:03:29.932496 <30>[ 12.346395] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6492 01:03:29.944731 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6493 01:03:29.970046 <30>[ 12.383613] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6494 01:03:29.983010 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6495 01:03:30.007227 <30>[ 12.414646] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6496 01:03:30.057838 <30>[ 12.472011] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6497 01:03:30.072981 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6498 01:03:30.098363 <30>[ 12.512182] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6499 01:03:30.112878 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6500 01:03:30.148531 <30>[ 12.562498] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6501 01:03:30.160184 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6502 01:03:30.185822 <30>[ 12.599602] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6503 01:03:30.200969 Startin<6>[ 12.612721] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6504 01:03:30.204361 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6505 01:03:30.249153 <30>[ 12.663150] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6506 01:03:30.264269 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6507 01:03:30.284455 <30>[ 12.698503] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6508 01:03:30.296549 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6509 01:03:30.324917 <6>[ 12.742133] fuse: init (API version 7.37)
6510 01:03:30.352920 <30>[ 12.766747] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6511 01:03:30.364938 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6512 01:03:30.395446 <30>[ 12.809441] systemd[1]: Starting systemd-journald.service - Journal Service...
6513 01:03:30.408789 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6514 01:03:30.468470 <30>[ 12.882459] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6515 01:03:30.479788 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6516 01:03:30.503674 <30>[ 12.914489] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6517 01:03:30.516280 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6518 01:03:30.568367 <30>[ 12.982245] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6519 01:03:30.581531 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6520 01:03:30.606182 <30>[ 13.020199] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6521 01:03:30.618012 Startin<3>[ 13.031630] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6522 01:03:30.624130 g [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6523 01:03:30.636312 <3>[ 13.049553] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6524 01:03:30.649139 <30>[ 13.062995] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6525 01:03:30.663375 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - H<3>[ 13.077693] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6526 01:03:30.666531 uge Pages File System.
6527 01:03:30.680620 <3>[ 13.094476] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6528 01:03:30.691080 <30>[ 13.103568] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6529 01:03:30.705852 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSI<3>[ 13.120169] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6530 01:03:30.709021 X Message Queue File System.
6531 01:03:30.722920 <3>[ 13.136588] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6532 01:03:30.730702 <30>[ 13.146211] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6533 01:03:30.740464 <3>[ 13.153175] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6534 01:03:30.752769 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6535 01:03:30.759681 <3>[ 13.174070] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6536 01:03:30.771708 <30>[ 13.184939] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6537 01:03:30.786011 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6538 01:03:30.805112 <30>[ 13.218809] systemd[1]: Started systemd-journald.service - Journal Service.
6539 01:03:30.814906 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6540 01:03:30.837706 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6541 01:03:30.863593 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6542 01:03:30.882850 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6543 01:03:30.902561 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6544 01:03:30.922674 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6545 01:03:30.943037 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6546 01:03:30.961528 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6547 01:03:30.981481 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6548 01:03:31.001505 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6549 01:03:31.022845 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6550 01:03:31.064615 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6551 01:03:31.090120 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6552 01:03:31.111677 <4>[ 13.518984] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6553 01:03:31.122900 <3>[ 13.536741] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6554 01:03:31.130252 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6555 01:03:31.150668 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6556 01:03:31.180721 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Ke<46>[ 13.592723] systemd-journald[322]: Received client request to flush runtime journal.
6557 01:03:31.184550 rnel Variables...
6558 01:03:31.208950 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6559 01:03:31.238792 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6560 01:03:31.261453 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6561 01:03:31.281782 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6562 01:03:31.306007 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6563 01:03:31.326398 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6564 01:03:32.305015 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6565 01:03:32.357533 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6566 01:03:32.661720 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6567 01:03:32.774324 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6568 01:03:32.793530 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6569 01:03:32.812461 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6570 01:03:32.857338 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6571 01:03:32.884165 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6572 01:03:33.149770 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6573 01:03:33.212434 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6574 01:03:33.254440 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6575 01:03:33.456146 <4>[ 15.872839] power_supply_show_property: 4 callbacks suppressed
6576 01:03:33.467259 <3>[ 15.872849] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6577 01:03:33.473804 <3>[ 15.884756] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6578 01:03:33.497641 <3>[ 15.910545] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6579 01:03:33.504255 <3>[ 15.911002] power_supply sbs-12-000b: driver failed to report `capacity_level' property: -6
6580 01:03:33.525788 <3>[ 15.939202] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6581 01:03:33.543307 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/system<3>[ 15.955712] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6582 01:03:33.543432 d-backlight.
6583 01:03:33.558071 <3>[ 15.971230] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6584 01:03:33.575773 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Sup<3>[ 15.987654] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6585 01:03:33.576139 port.
6586 01:03:33.590379 <3>[ 16.003339] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6587 01:03:33.604758 <3>[ 16.017995] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6588 01:03:33.632995 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6589 01:03:33.650944 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6590 01:03:33.694972 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6591 01:03:33.783111 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6592 01:03:33.805039 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6593 01:03:33.824925 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6594 01:03:33.922519 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6595 01:03:33.947426 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6596 01:03:33.969924 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6597 01:03:34.017638 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6598 01:03:34.043149 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6599 01:03:34.069700 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6600 01:03:34.090557 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6601 01:03:34.110981 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6602 01:03:34.133903 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6603 01:03:34.157655 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6604 01:03:34.177165 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6605 01:03:34.197456 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6606 01:03:34.222591 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6607 01:03:34.244618 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6608 01:03:34.266164 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6609 01:03:34.286765 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6610 01:03:34.305329 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6611 01:03:34.322984 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6612 01:03:34.343550 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6613 01:03:34.360307 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6614 01:03:34.376455 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6615 01:03:34.395325 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6616 01:03:34.412606 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6617 01:03:34.429546 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6618 01:03:34.473536 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6619 01:03:34.495440 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6620 01:03:34.531007 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6621 01:03:34.641306 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6622 01:03:34.669971 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6623 01:03:34.691457 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6624 01:03:34.709484 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6625 01:03:34.874751 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6626 01:03:34.905416 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6627 01:03:34.977903 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6628 01:03:34.997262 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6629 01:03:35.014596 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6630 01:03:35.054308 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6631 01:03:35.078116 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6632 01:03:35.099910 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6633 01:03:35.118272 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6634 01:03:35.162826 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6635 01:03:35.220915 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6636 01:03:35.312271
6637 01:03:35.315756 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6638 01:03:35.316143
6639 01:03:35.318999 debian-bookworm-arm64 login: root (automatic login)
6640 01:03:35.319404
6641 01:03:35.624476 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
6642 01:03:35.624933
6643 01:03:35.631092 The programs included with the Debian GNU/Linux system are free software;
6644 01:03:35.637748 the exact distribution terms for each program are described in the
6645 01:03:35.640778 individual files in /usr/share/doc/*/copyright.
6646 01:03:35.641190
6647 01:03:35.647908 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6648 01:03:35.651142 permitted by applicable law.
6649 01:03:36.811925 Matched prompt #10: / #
6651 01:03:36.812958 Setting prompt string to ['/ #']
6652 01:03:36.813373 end: 2.2.5.1 login-action (duration 00:00:20) [common]
6654 01:03:36.814313 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
6655 01:03:36.814714 start: 2.2.6 expect-shell-connection (timeout 00:03:49) [common]
6656 01:03:36.815042 Setting prompt string to ['/ #']
6657 01:03:36.815321 Forcing a shell prompt, looking for ['/ #']
6659 01:03:36.866075 / #
6660 01:03:36.866737 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6661 01:03:36.867163 Waiting using forced prompt support (timeout 00:02:30)
6662 01:03:36.872669
6663 01:03:36.873724 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6664 01:03:36.874258 start: 2.2.7 export-device-env (timeout 00:03:48) [common]
6666 01:03:36.975522 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368634/extract-nfsrootfs-pm0qfktj'
6667 01:03:36.982142 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14368634/extract-nfsrootfs-pm0qfktj'
6669 01:03:37.083714 / # export NFS_SERVER_IP='192.168.201.1'
6670 01:03:37.090170 export NFS_SERVER_IP='192.168.201.1'
6671 01:03:37.091054 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6672 01:03:37.091546 end: 2.2 depthcharge-retry (duration 00:01:12) [common]
6673 01:03:37.092022 end: 2 depthcharge-action (duration 00:01:12) [common]
6674 01:03:37.092467 start: 3 lava-test-retry (timeout 00:08:10) [common]
6675 01:03:37.092904 start: 3.1 lava-test-shell (timeout 00:08:10) [common]
6676 01:03:37.093278 Using namespace: common
6678 01:03:37.194374 / # #
6679 01:03:37.195117 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6680 01:03:37.200808 #
6681 01:03:37.201620 Using /lava-14368634
6683 01:03:37.302812 / # export SHELL=/bin/bash
6684 01:03:37.309074 export SHELL=/bin/bash
6686 01:03:37.410662 / # . /lava-14368634/environment
6687 01:03:37.417186 . /lava-14368634/environment
6689 01:03:37.523904 / # /lava-14368634/bin/lava-test-runner /lava-14368634/0
6690 01:03:37.524610 Test shell timeout: 10s (minimum of the action and connection timeout)
6691 01:03:37.530330 /lava-14368634/bin/lava-test-runner /lava-14368634/0
6692 01:03:37.805892 + export TESTRUN_ID=0_timesync-off
6693 01:03:37.809114 + TESTRUN_ID=0_timesync-off
6694 01:03:37.812561 + cd /lava-14368634/0/tests/0_timesync-off
6695 01:03:37.815735 ++ cat uuid
6696 01:03:37.820562 + UUID=14368634_1.6.2.3.1
6697 01:03:37.820921 + set +x
6698 01:03:37.827122 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14368634_1.6.2.3.1>
6699 01:03:37.827799 Received signal: <STARTRUN> 0_timesync-off 14368634_1.6.2.3.1
6700 01:03:37.828169 Starting test lava.0_timesync-off (14368634_1.6.2.3.1)
6701 01:03:37.828600 Skipping test definition patterns.
6702 01:03:37.830177 + systemctl stop systemd-timesyncd
6703 01:03:37.890465 + set +x
6704 01:03:37.893937 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14368634_1.6.2.3.1>
6705 01:03:37.894630 Received signal: <ENDRUN> 0_timesync-off 14368634_1.6.2.3.1
6706 01:03:37.895016 Ending use of test pattern.
6707 01:03:37.895304 Ending test lava.0_timesync-off (14368634_1.6.2.3.1), duration 0.07
6709 01:03:37.981059 + export TESTRUN_ID=1_kselftest-arm64
6710 01:03:37.981543 + TESTRUN_ID=1_kselftest-arm64
6711 01:03:37.988109 + cd /lava-14368634/0/tests/1_kselftest-arm64
6712 01:03:37.988502 ++ cat uuid
6713 01:03:37.993052 + UUID=14368634_1.6.2.3.5
6714 01:03:37.993435 + set +x
6715 01:03:38.000156 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14368634_1.6.2.3.5>
6716 01:03:38.000793 Received signal: <STARTRUN> 1_kselftest-arm64 14368634_1.6.2.3.5
6717 01:03:38.001128 Starting test lava.1_kselftest-arm64 (14368634_1.6.2.3.5)
6718 01:03:38.001490 Skipping test definition patterns.
6719 01:03:38.003549 + cd ./automated/linux/kselftest/
6720 01:03:38.032746 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
6721 01:03:38.081184 INFO: install_deps skipped
6722 01:03:38.581255 --2024-06-16 01:03:38-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
6723 01:03:38.812616 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6724 01:03:38.937483 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6725 01:03:39.061552 HTTP request sent, awaiting response... 200 OK
6726 01:03:39.065041 Length: 1647948 (1.6M) [application/octet-stream]
6727 01:03:39.068341 Saving to: 'kselftest_armhf.tar.gz'
6728 01:03:39.068730
6729 01:03:39.069034
6730 01:03:39.311876 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6731 01:03:39.559522 kselftest_armhf.tar 2%[ ] 44.98K 181KB/s
6732 01:03:39.856602 kselftest_armhf.tar 13%[=> ] 213.25K 429KB/s
6733 01:03:39.983804 kselftest_armhf.tar 51%[=========> ] 824.13K 1.01MB/s
6734 01:03:39.990542 kselftest_armhf.tar 100%[===================>] 1.57M 1.71MB/s in 0.9s
6735 01:03:39.990940
6736 01:03:40.134947 2024-06-16 01:03:39 (1.71 MB/s) - 'kselftest_armhf.tar.gz' saved [1647948/1647948]
6737 01:03:40.135060
6738 01:03:44.719554 skiplist:
6739 01:03:44.722945 ========================================
6740 01:03:44.726390 ========================================
6741 01:03:44.777150 arm64:tags_test
6742 01:03:44.780493 arm64:run_tags_test.sh
6743 01:03:44.780907 arm64:fake_sigreturn_bad_magic
6744 01:03:44.783825 arm64:fake_sigreturn_bad_size
6745 01:03:44.787047 arm64:fake_sigreturn_bad_size_for_magic0
6746 01:03:44.790259 arm64:fake_sigreturn_duplicated_fpsimd
6747 01:03:44.793534 arm64:fake_sigreturn_misaligned_sp
6748 01:03:44.796850 arm64:fake_sigreturn_missing_fpsimd
6749 01:03:44.800177 arm64:fake_sigreturn_sme_change_vl
6750 01:03:44.803520 arm64:fake_sigreturn_sve_change_vl
6751 01:03:44.806781 arm64:mangle_pstate_invalid_compat_toggle
6752 01:03:44.810394 arm64:mangle_pstate_invalid_daif_bits
6753 01:03:44.813552 arm64:mangle_pstate_invalid_mode_el1h
6754 01:03:44.816813 arm64:mangle_pstate_invalid_mode_el1t
6755 01:03:44.819903 arm64:mangle_pstate_invalid_mode_el2h
6756 01:03:44.826558 arm64:mangle_pstate_invalid_mode_el2t
6757 01:03:44.829739 arm64:mangle_pstate_invalid_mode_el3h
6758 01:03:44.833117 arm64:mangle_pstate_invalid_mode_el3t
6759 01:03:44.833542 arm64:sme_trap_no_sm
6760 01:03:44.836576 arm64:sme_trap_non_streaming
6761 01:03:44.837109 arm64:sme_trap_za
6762 01:03:44.839749 arm64:sme_vl
6763 01:03:44.840271 arm64:ssve_regs
6764 01:03:44.843392 arm64:sve_regs
6765 01:03:44.843823 arm64:sve_vl
6766 01:03:44.846587 arm64:za_no_regs
6767 01:03:44.847001 arm64:za_regs
6768 01:03:44.847304 arm64:pac
6769 01:03:44.849952 arm64:fp-stress
6770 01:03:44.850364 arm64:sve-ptrace
6771 01:03:44.853092 arm64:sve-probe-vls
6772 01:03:44.853483 arm64:vec-syscfg
6773 01:03:44.856454 arm64:za-fork
6774 01:03:44.856863 arm64:za-ptrace
6775 01:03:44.860065 arm64:check_buffer_fill
6776 01:03:44.860459 arm64:check_child_memory
6777 01:03:44.863036 arm64:check_gcr_el1_cswitch
6778 01:03:44.866387 arm64:check_ksm_options
6779 01:03:44.866779 arm64:check_mmap_options
6780 01:03:44.869852 arm64:check_prctl
6781 01:03:44.872726 arm64:check_tags_inclusion
6782 01:03:44.873141 arm64:check_user_mem
6783 01:03:44.876245 arm64:btitest
6784 01:03:44.876723 arm64:nobtitest
6785 01:03:44.877065 arm64:hwcap
6786 01:03:44.879584 arm64:ptrace
6787 01:03:44.880092 arm64:syscall-abi
6788 01:03:44.882786 arm64:tpidr2
6789 01:03:44.886632 ============== Tests to run ===============
6790 01:03:44.887135 arm64:tags_test
6791 01:03:44.889618 arm64:run_tags_test.sh
6792 01:03:44.892891 arm64:fake_sigreturn_bad_magic
6793 01:03:44.895706 arm64:fake_sigreturn_bad_size
6794 01:03:44.899852 arm64:fake_sigreturn_bad_size_for_magic0
6795 01:03:44.902314 arm64:fake_sigreturn_duplicated_fpsimd
6796 01:03:44.906208 arm64:fake_sigreturn_misaligned_sp
6797 01:03:44.909071 arm64:fake_sigreturn_missing_fpsimd
6798 01:03:44.912403 arm64:fake_sigreturn_sme_change_vl
6799 01:03:44.915667 arm64:fake_sigreturn_sve_change_vl
6800 01:03:44.919260 arm64:mangle_pstate_invalid_compat_toggle
6801 01:03:44.922423 arm64:mangle_pstate_invalid_daif_bits
6802 01:03:44.925708 arm64:mangle_pstate_invalid_mode_el1h
6803 01:03:44.928921 arm64:mangle_pstate_invalid_mode_el1t
6804 01:03:44.932407 arm64:mangle_pstate_invalid_mode_el2h
6805 01:03:44.935798 arm64:mangle_pstate_invalid_mode_el2t
6806 01:03:44.938899 arm64:mangle_pstate_invalid_mode_el3h
6807 01:03:44.942332 arm64:mangle_pstate_invalid_mode_el3t
6808 01:03:44.942726 arm64:sme_trap_no_sm
6809 01:03:44.945425 arm64:sme_trap_non_streaming
6810 01:03:44.948979 arm64:sme_trap_za
6811 01:03:44.949455 arm64:sme_vl
6812 01:03:44.952253 arm64:ssve_regs
6813 01:03:44.952646 arm64:sve_regs
6814 01:03:44.952956 arm64:sve_vl
6815 01:03:44.955430 arm64:za_no_regs
6816 01:03:44.955825 arm64:za_regs
6817 01:03:44.958519 arm64:pac
6818 01:03:44.958913 arm64:fp-stress
6819 01:03:44.959219 arm64:sve-ptrace
6820 01:03:44.962210 arm64:sve-probe-vls
6821 01:03:44.962606 arm64:vec-syscfg
6822 01:03:44.965781 arm64:za-fork
6823 01:03:44.966332 arm64:za-ptrace
6824 01:03:44.968672 arm64:check_buffer_fill
6825 01:03:44.972122 arm64:check_child_memory
6826 01:03:44.972516 arm64:check_gcr_el1_cswitch
6827 01:03:44.975521 arm64:check_ksm_options
6828 01:03:44.978526 arm64:check_mmap_options
6829 01:03:44.978920 arm64:check_prctl
6830 01:03:44.982035 arm64:check_tags_inclusion
6831 01:03:44.985309 arm64:check_user_mem
6832 01:03:44.985702 arm64:btitest
6833 01:03:44.986051 arm64:nobtitest
6834 01:03:44.988519 arm64:hwcap
6835 01:03:44.988910 arm64:ptrace
6836 01:03:44.992018 arm64:syscall-abi
6837 01:03:44.992509 arm64:tpidr2
6838 01:03:44.995108 ===========End Tests to run ===============
6839 01:03:44.998361 shardfile-arm64 pass
6840 01:03:45.275735 <12>[ 27.692385] kselftest: Running tests in arm64
6841 01:03:45.286189 TAP version 13
6842 01:03:45.302009 1..48
6843 01:03:45.322325 # selftests: arm64: tags_test
6844 01:03:45.804433 ok 1 selftests: arm64: tags_test
6845 01:03:45.825164 # selftests: arm64: run_tags_test.sh
6846 01:03:45.910742 # --------------------
6847 01:03:45.914065 # running tags test
6848 01:03:45.914581 # --------------------
6849 01:03:45.917599 # [PASS]
6850 01:03:45.920227 ok 2 selftests: arm64: run_tags_test.sh
6851 01:03:45.936383 # selftests: arm64: fake_sigreturn_bad_magic
6852 01:03:46.021786 # Registered handlers for all signals.
6853 01:03:46.022382 # Detected MINSTKSIGSZ:4720
6854 01:03:46.024379 # Testcase initialized.
6855 01:03:46.028057 # uc context validated.
6856 01:03:46.031001 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6857 01:03:46.034234 # Handled SIG_COPYCTX
6858 01:03:46.034666 # Available space:3568
6859 01:03:46.040816 # Using badly built context - ERR: BAD MAGIC !
6860 01:03:46.047698 # SIG_OK -- SP:0xFFFFE60C4D10 si_addr@:0xffffe60c4d10 si_code:2 token@:0xffffe60c3ab0 offset:-4704
6861 01:03:46.050757 # ==>> completed. PASS(1)
6862 01:03:46.057810 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
6863 01:03:46.064073 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE60C3AB0
6864 01:03:46.070867 ok 3 selftests: arm64: fake_sigreturn_bad_magic
6865 01:03:46.074289 # selftests: arm64: fake_sigreturn_bad_size
6866 01:03:46.139732 # Registered handlers for all signals.
6867 01:03:46.140166 # Detected MINSTKSIGSZ:4720
6868 01:03:46.143149 # Testcase initialized.
6869 01:03:46.146291 # uc context validated.
6870 01:03:46.149784 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6871 01:03:46.152988 # Handled SIG_COPYCTX
6872 01:03:46.153385 # Available space:3568
6873 01:03:46.155899 # uc context validated.
6874 01:03:46.163278 # Using badly built context - ERR: Bad size for esr_context
6875 01:03:46.169206 # SIG_OK -- SP:0xFFFFF84EE220 si_addr@:0xfffff84ee220 si_code:2 token@:0xfffff84ecfc0 offset:-4704
6876 01:03:46.172762 # ==>> completed. PASS(1)
6877 01:03:46.179385 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
6878 01:03:46.186097 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF84ECFC0
6879 01:03:46.189198 ok 4 selftests: arm64: fake_sigreturn_bad_size
6880 01:03:46.195879 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
6881 01:03:46.245680 # Registered handlers for all signals.
6882 01:03:46.246183 # Detected MINSTKSIGSZ:4720
6883 01:03:46.249262 # Testcase initialized.
6884 01:03:46.252809 # uc context validated.
6885 01:03:46.255745 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6886 01:03:46.258704 # Handled SIG_COPYCTX
6887 01:03:46.258787 # Available space:3568
6888 01:03:46.265077 # Using badly built context - ERR: Bad size for terminator
6889 01:03:46.275348 # SIG_OK -- SP:0xFFFFE6382C30 si_addr@:0xffffe6382c30 si_code:2 token@:0xffffe63819d0 offset:-4704
6890 01:03:46.275801 # ==>> completed. PASS(1)
6891 01:03:46.285245 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
6892 01:03:46.292187 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE63819D0
6893 01:03:46.295461 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
6894 01:03:46.302510 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
6895 01:03:46.350730 # Registered handlers for all signals.
6896 01:03:46.351281 # Detected MINSTKSIGSZ:4720
6897 01:03:46.353804 # Testcase initialized.
6898 01:03:46.357310 # uc context validated.
6899 01:03:46.360643 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6900 01:03:46.363696 # Handled SIG_COPYCTX
6901 01:03:46.364151 # Available space:3568
6902 01:03:46.370043 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
6903 01:03:46.379725 # SIG_OK -- SP:0xFFFFFD0F6F90 si_addr@:0xfffffd0f6f90 si_code:2 token@:0xfffffd0f5d30 offset:-4704
6904 01:03:46.380157 # ==>> completed. PASS(1)
6905 01:03:46.390292 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
6906 01:03:46.396867 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFD0F5D30
6907 01:03:46.400154 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
6908 01:03:46.403364 # selftests: arm64: fake_sigreturn_misaligned_sp
6909 01:03:46.453649 # Registered handlers for all signals.
6910 01:03:46.454199 # Detected MINSTKSIGSZ:4720
6911 01:03:46.457630 # Testcase initialized.
6912 01:03:46.460266 # uc context validated.
6913 01:03:46.464201 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6914 01:03:46.467013 # Handled SIG_COPYCTX
6915 01:03:46.473795 # SIG_OK -- SP:0xFFFFC8957FE3 si_addr@:0xffffc8957fe3 si_code:2 token@:0xffffc8957fe3 offset:0
6916 01:03:46.477083 # ==>> completed. PASS(1)
6917 01:03:46.484120 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
6918 01:03:46.489872 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC8957FE3
6919 01:03:46.497208 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
6920 01:03:46.499840 # selftests: arm64: fake_sigreturn_missing_fpsimd
6921 01:03:46.571606 # Registered handlers for all signals.
6922 01:03:46.572200 # Detected MINSTKSIGSZ:4720
6923 01:03:46.574394 # Testcase initialized.
6924 01:03:46.577899 # uc context validated.
6925 01:03:46.581184 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6926 01:03:46.584712 # Handled SIG_COPYCTX
6927 01:03:46.588206 # Mangling template header. Spare space:4096
6928 01:03:46.591376 # Using badly built context - ERR: Missing FPSIMD
6929 01:03:46.601126 # SIG_OK -- SP:0xFFFFDD9A3D30 si_addr@:0xffffdd9a3d30 si_code:2 token@:0xffffdd9a2ad0 offset:-4704
6930 01:03:46.604510 # ==>> completed. PASS(1)
6931 01:03:46.611697 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
6932 01:03:46.617590 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDD9A2AD0
6933 01:03:46.620814 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
6934 01:03:46.627289 # selftests: arm64: fake_sigreturn_sme_change_vl
6935 01:03:46.674814 # Registered handlers for all signals.
6936 01:03:46.675343 # Detected MINSTKSIGSZ:4720
6937 01:03:46.677968 # ==>> completed. SKIP.
6938 01:03:46.684645 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
6939 01:03:46.687997 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
6940 01:03:46.702090 # selftests: arm64: fake_sigreturn_sve_change_vl
6941 01:03:46.771721 # Registered handlers for all signals.
6942 01:03:46.772289 # Detected MINSTKSIGSZ:4720
6943 01:03:46.775239 # ==>> completed. SKIP.
6944 01:03:46.778475 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
6945 01:03:46.785283 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
6946 01:03:46.792905 # selftests: arm64: mangle_pstate_invalid_compat_toggle
6947 01:03:46.866941 # Registered handlers for all signals.
6948 01:03:46.867421 # Detected MINSTKSIGSZ:4720
6949 01:03:46.870557 # Testcase initialized.
6950 01:03:46.873940 # uc context validated.
6951 01:03:46.874365 # Handled SIG_TRIG
6952 01:03:46.883616 # SIG_OK -- SP:0xFFFFF942FE80 si_addr@:0xfffff942fe80 si_code:2 token@:(nil) offset:-281474863660672
6953 01:03:46.887134 # ==>> completed. PASS(1)
6954 01:03:46.893731 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
6955 01:03:46.900390 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
6956 01:03:46.903420 # selftests: arm64: mangle_pstate_invalid_daif_bits
6957 01:03:46.968632 # Registered handlers for all signals.
6958 01:03:46.969151 # Detected MINSTKSIGSZ:4720
6959 01:03:46.971510 # Testcase initialized.
6960 01:03:46.974933 # uc context validated.
6961 01:03:46.975463 # Handled SIG_TRIG
6962 01:03:46.985183 # SIG_OK -- SP:0xFFFFCA3295E0 si_addr@:0xffffca3295e0 si_code:2 token@:(nil) offset:-281474074056160
6963 01:03:46.988255 # ==>> completed. PASS(1)
6964 01:03:46.994815 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
6965 01:03:46.998232 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
6966 01:03:47.004824 # selftests: arm64: mangle_pstate_invalid_mode_el1h
6967 01:03:47.065934 # Registered handlers for all signals.
6968 01:03:47.066571 # Detected MINSTKSIGSZ:4720
6969 01:03:47.069626 # Testcase initialized.
6970 01:03:47.072786 # uc context validated.
6971 01:03:47.073171 # Handled SIG_TRIG
6972 01:03:47.082337 # SIG_OK -- SP:0xFFFFDA1ABA50 si_addr@:0xffffda1aba50 si_code:2 token@:(nil) offset:-281474340928080
6973 01:03:47.085934 # ==>> completed. PASS(1)
6974 01:03:47.092742 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
6975 01:03:47.095733 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
6976 01:03:47.101885 # selftests: arm64: mangle_pstate_invalid_mode_el1t
6977 01:03:47.158347 # Registered handlers for all signals.
6978 01:03:47.159001 # Detected MINSTKSIGSZ:4720
6979 01:03:47.161844 # Testcase initialized.
6980 01:03:47.165157 # uc context validated.
6981 01:03:47.165567 # Handled SIG_TRIG
6982 01:03:47.174969 # SIG_OK -- SP:0xFFFFC1896410 si_addr@:0xffffc1896410 si_code:2 token@:(nil) offset:-281473928750096
6983 01:03:47.178503 # ==>> completed. PASS(1)
6984 01:03:47.185085 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
6985 01:03:47.188016 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
6986 01:03:47.194862 # selftests: arm64: mangle_pstate_invalid_mode_el2h
6987 01:03:47.249433 # Registered handlers for all signals.
6988 01:03:47.249840 # Detected MINSTKSIGSZ:4720
6989 01:03:47.252322 # Testcase initialized.
6990 01:03:47.255763 # uc context validated.
6991 01:03:47.256162 # Handled SIG_TRIG
6992 01:03:47.265859 # SIG_OK -- SP:0xFFFFFD7ADDA0 si_addr@:0xfffffd7adda0 si_code:2 token@:(nil) offset:-281474934431136
6993 01:03:47.268933 # ==>> completed. PASS(1)
6994 01:03:47.275190 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
6995 01:03:47.278610 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
6996 01:03:47.285158 # selftests: arm64: mangle_pstate_invalid_mode_el2t
6997 01:03:47.356785 # Registered handlers for all signals.
6998 01:03:47.357207 # Detected MINSTKSIGSZ:4720
6999 01:03:47.360342 # Testcase initialized.
7000 01:03:47.363591 # uc context validated.
7001 01:03:47.363963 # Handled SIG_TRIG
7002 01:03:47.373351 # SIG_OK -- SP:0xFFFFE4957C10 si_addr@:0xffffe4957c10 si_code:2 token@:(nil) offset:-281474516745232
7003 01:03:47.376712 # ==>> completed. PASS(1)
7004 01:03:47.383395 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
7005 01:03:47.386795 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
7006 01:03:47.393185 # selftests: arm64: mangle_pstate_invalid_mode_el3h
7007 01:03:47.454799 # Registered handlers for all signals.
7008 01:03:47.455267 # Detected MINSTKSIGSZ:4720
7009 01:03:47.458207 # Testcase initialized.
7010 01:03:47.462020 # uc context validated.
7011 01:03:47.462416 # Handled SIG_TRIG
7012 01:03:47.471787 # SIG_OK -- SP:0xFFFFC3540AD0 si_addr@:0xffffc3540ad0 si_code:2 token@:(nil) offset:-281473958808272
7013 01:03:47.475324 # ==>> completed. PASS(1)
7014 01:03:47.481592 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
7015 01:03:47.484906 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
7016 01:03:47.491319 # selftests: arm64: mangle_pstate_invalid_mode_el3t
7017 01:03:47.544327 # Registered handlers for all signals.
7018 01:03:47.544763 # Detected MINSTKSIGSZ:4720
7019 01:03:47.547597 # Testcase initialized.
7020 01:03:47.550925 # uc context validated.
7021 01:03:47.551314 # Handled SIG_TRIG
7022 01:03:47.561142 # SIG_OK -- SP:0xFFFFF3C4CBC0 si_addr@:0xfffff3c4cbc0 si_code:2 token@:(nil) offset:-281474771504064
7023 01:03:47.564382 # ==>> completed. PASS(1)
7024 01:03:47.570737 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
7025 01:03:47.574363 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
7026 01:03:47.577574 # selftests: arm64: sme_trap_no_sm
7027 01:03:47.650087 # Registered handlers for all signals.
7028 01:03:47.650545 # Detected MINSTKSIGSZ:4720
7029 01:03:47.653626 # ==>> completed. SKIP.
7030 01:03:47.663454 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
7031 01:03:47.666563 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
7032 01:03:47.673745 # selftests: arm64: sme_trap_non_streaming
7033 01:03:47.743873 # Registered handlers for all signals.
7034 01:03:47.744329 # Detected MINSTKSIGSZ:4720
7035 01:03:47.747454 # ==>> completed. SKIP.
7036 01:03:47.757074 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
7037 01:03:47.763683 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
7038 01:03:47.767113 # selftests: arm64: sme_trap_za
7039 01:03:47.828523 # Registered handlers for all signals.
7040 01:03:47.828984 # Detected MINSTKSIGSZ:4720
7041 01:03:47.831672 # Testcase initialized.
7042 01:03:47.842211 # SIG_OK -- SP:0xFFFFFED1BE80 si_addr@:0xaaaabb1e2510 si_code:1 token@:(nil) offset:-187650260477200
7043 01:03:47.842647 # ==>> completed. PASS(1)
7044 01:03:47.851837 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
7045 01:03:47.852230 ok 21 selftests: arm64: sme_trap_za
7046 01:03:47.855605 # selftests: arm64: sme_vl
7047 01:03:47.931153 # Registered handlers for all signals.
7048 01:03:47.931588 # Detected MINSTKSIGSZ:4720
7049 01:03:47.934801 # ==>> completed. SKIP.
7050 01:03:47.941000 # # SME VL :: Check that we get the right SME VL reported
7051 01:03:47.944341 ok 22 selftests: arm64: sme_vl # SKIP
7052 01:03:47.949004 # selftests: arm64: ssve_regs
7053 01:03:48.038547 # Registered handlers for all signals.
7054 01:03:48.039023 # Detected MINSTKSIGSZ:4720
7055 01:03:48.042016 # ==>> completed. SKIP.
7056 01:03:48.048359 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
7057 01:03:48.051375 ok 23 selftests: arm64: ssve_regs # SKIP
7058 01:03:48.060386 # selftests: arm64: sve_regs
7059 01:03:48.132108 # Registered handlers for all signals.
7060 01:03:48.132546 # Detected MINSTKSIGSZ:4720
7061 01:03:48.136399 # ==>> completed. SKIP.
7062 01:03:48.142128 # # SVE registers :: Check that we get the right SVE registers reported
7063 01:03:48.145311 ok 24 selftests: arm64: sve_regs # SKIP
7064 01:03:48.152342 # selftests: arm64: sve_vl
7065 01:03:48.241287 # Registered handlers for all signals.
7066 01:03:48.241810 # Detected MINSTKSIGSZ:4720
7067 01:03:48.244617 # ==>> completed. SKIP.
7068 01:03:48.250516 # # SVE VL :: Check that we get the right SVE VL reported
7069 01:03:48.253494 ok 25 selftests: arm64: sve_vl # SKIP
7070 01:03:48.259223 # selftests: arm64: za_no_regs
7071 01:03:48.333788 # Registered handlers for all signals.
7072 01:03:48.334326 # Detected MINSTKSIGSZ:4720
7073 01:03:48.337198 # ==>> completed. SKIP.
7074 01:03:48.344125 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
7075 01:03:48.346928 ok 26 selftests: arm64: za_no_regs # SKIP
7076 01:03:48.353074 # selftests: arm64: za_regs
7077 01:03:48.429937 # Registered handlers for all signals.
7078 01:03:48.430466 # Detected MINSTKSIGSZ:4720
7079 01:03:48.433238 # ==>> completed. SKIP.
7080 01:03:48.439617 # # ZA register :: Check that we get the right ZA registers reported
7081 01:03:48.443123 ok 27 selftests: arm64: za_regs # SKIP
7082 01:03:48.450206 # selftests: arm64: pac
7083 01:03:48.525563 # TAP version 13
7084 01:03:48.526067 # 1..7
7085 01:03:48.528347 # # Starting 7 tests from 1 test cases.
7086 01:03:48.531496 # # RUN global.corrupt_pac ...
7087 01:03:48.534903 # # SKIP PAUTH not enabled
7088 01:03:48.538528 # # OK global.corrupt_pac
7089 01:03:48.542027 # ok 1 # SKIP PAUTH not enabled
7090 01:03:48.548216 # # RUN global.pac_instructions_not_nop ...
7091 01:03:48.551621 # # SKIP PAUTH not enabled
7092 01:03:48.554967 # # OK global.pac_instructions_not_nop
7093 01:03:48.558258 # ok 2 # SKIP PAUTH not enabled
7094 01:03:48.564664 # # RUN global.pac_instructions_not_nop_generic ...
7095 01:03:48.568162 # # SKIP Generic PAUTH not enabled
7096 01:03:48.571835 # # OK global.pac_instructions_not_nop_generic
7097 01:03:48.574653 # ok 3 # SKIP Generic PAUTH not enabled
7098 01:03:48.581163 # # RUN global.single_thread_different_keys ...
7099 01:03:48.584795 # # SKIP PAUTH not enabled
7100 01:03:48.590895 # # OK global.single_thread_different_keys
7101 01:03:48.591305 # ok 4 # SKIP PAUTH not enabled
7102 01:03:48.598137 # # RUN global.exec_changed_keys ...
7103 01:03:48.601110 # # SKIP PAUTH not enabled
7104 01:03:48.604946 # # OK global.exec_changed_keys
7105 01:03:48.607793 # ok 5 # SKIP PAUTH not enabled
7106 01:03:48.611075 # # RUN global.context_switch_keep_keys ...
7107 01:03:48.614099 # # SKIP PAUTH not enabled
7108 01:03:48.620939 # # OK global.context_switch_keep_keys
7109 01:03:48.621346 # ok 6 # SKIP PAUTH not enabled
7110 01:03:48.627881 # # RUN global.context_switch_keep_keys_generic ...
7111 01:03:48.631134 # # SKIP Generic PAUTH not enabled
7112 01:03:48.637636 # # OK global.context_switch_keep_keys_generic
7113 01:03:48.640902 # ok 7 # SKIP Generic PAUTH not enabled
7114 01:03:48.644645 # # PASSED: 7 / 7 tests passed.
7115 01:03:48.647669 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
7116 01:03:48.650905 ok 28 selftests: arm64: pac
7117 01:03:48.654056 # selftests: arm64: fp-stress
7118 01:03:55.574243 <6>[ 37.993857] vaux18: disabling
7119 01:03:55.578028 <6>[ 37.997229] vio28: disabling
7120 01:03:58.614305 # TAP version 13
7121 01:03:58.614814 # 1..16
7122 01:03:58.617625 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
7123 01:03:58.621589 # # Will run for 10s
7124 01:03:58.622147 # # Started FPSIMD-0-0
7125 01:03:58.624443 # # Started FPSIMD-0-1
7126 01:03:58.627241 # # Started FPSIMD-1-0
7127 01:03:58.627673 # # Started FPSIMD-1-1
7128 01:03:58.630480 # # Started FPSIMD-2-0
7129 01:03:58.634062 # # Started FPSIMD-2-1
7130 01:03:58.634475 # # Started FPSIMD-3-0
7131 01:03:58.637630 # # Started FPSIMD-3-1
7132 01:03:58.638067 # # Started FPSIMD-4-0
7133 01:03:58.640585 # # Started FPSIMD-4-1
7134 01:03:58.644101 # # Started FPSIMD-5-0
7135 01:03:58.644626 # # Started FPSIMD-5-1
7136 01:03:58.647488 # # Started FPSIMD-6-0
7137 01:03:58.650873 # # Started FPSIMD-6-1
7138 01:03:58.651277 # # Started FPSIMD-7-0
7139 01:03:58.653947 # # Started FPSIMD-7-1
7140 01:03:58.657045 # # FPSIMD-0-1: Vector length: 128 bits
7141 01:03:58.660557 # # FPSIMD-0-1: PID: 1191
7142 01:03:58.663585 # # FPSIMD-2-0: Vector length: 128 bits
7143 01:03:58.664105 # # FPSIMD-2-0: PID: 1194
7144 01:03:58.670226 # # FPSIMD-3-0: Vector length: 128 bits
7145 01:03:58.670798 # # FPSIMD-3-0: PID: 1196
7146 01:03:58.673710 # # FPSIMD-1-1: Vector length: 128 bits
7147 01:03:58.676788 # # FPSIMD-1-1: PID: 1193
7148 01:03:58.680418 # # FPSIMD-1-0: Vector length: 128 bits
7149 01:03:58.683506 # # FPSIMD-1-0: PID: 1192
7150 01:03:58.686745 # # FPSIMD-2-1: Vector length: 128 bits
7151 01:03:58.690958 # # FPSIMD-2-1: PID: 1195
7152 01:03:58.693349 # # FPSIMD-5-0: Vector length: 128 bits
7153 01:03:58.693736 # # FPSIMD-5-0: PID: 1200
7154 01:03:58.700480 # # FPSIMD-0-0: Vector length: 128 bits
7155 01:03:58.700993 # # FPSIMD-0-0: PID: 1190
7156 01:03:58.703810 # # FPSIMD-4-0: Vector length: 128 bits
7157 01:03:58.707229 # # FPSIMD-4-0: PID: 1198
7158 01:03:58.710126 # # FPSIMD-7-1: Vector length: 128 bits
7159 01:03:58.713289 # # FPSIMD-7-1: PID: 1205
7160 01:03:58.716689 # # FPSIMD-4-1: Vector length: 128 bits
7161 01:03:58.719864 # # FPSIMD-4-1: PID: 1199
7162 01:03:58.723728 # # FPSIMD-7-0: Vector length: 128 bits
7163 01:03:58.724120 # # FPSIMD-7-0: PID: 1204
7164 01:03:58.726988 # # FPSIMD-5-1: Vector length: 128 bits
7165 01:03:58.730660 # # FPSIMD-5-1: PID: 1201
7166 01:03:58.733565 # # FPSIMD-3-1: Vector length: 128 bits
7167 01:03:58.737154 # # FPSIMD-3-1: PID: 1197
7168 01:03:58.739970 # # FPSIMD-6-0: Vector length: 128 bits
7169 01:03:58.742949 # # FPSIMD-6-0: PID: 1202
7170 01:03:58.746226 # # FPSIMD-6-1: Vector length: 128 bits
7171 01:03:58.749629 # # FPSIMD-6-1: PID: 1203
7172 01:03:58.750157 # # Finishing up...
7173 01:03:58.756639 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=742791, signals=10
7174 01:03:58.762634 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=800578, signals=10
7175 01:03:58.772814 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=799942, signals=10
7176 01:03:58.779482 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=831300, signals=10
7177 01:03:58.786522 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=738063, signals=10
7178 01:03:58.793244 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=833219, signals=10
7179 01:03:58.799822 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=763596, signals=10
7180 01:03:58.803424 # ok 1 FPSIMD-0-0
7181 01:03:58.803900 # ok 2 FPSIMD-0-1
7182 01:03:58.806112 # ok 3 FPSIMD-1-0
7183 01:03:58.806499 # ok 4 FPSIMD-1-1
7184 01:03:58.809763 # ok 5 FPSIMD-2-0
7185 01:03:58.810309 # ok 6 FPSIMD-2-1
7186 01:03:58.813137 # ok 7 FPSIMD-3-0
7187 01:03:58.813606 # ok 8 FPSIMD-3-1
7188 01:03:58.816110 # ok 9 FPSIMD-4-0
7189 01:03:58.816497 # ok 10 FPSIMD-4-1
7190 01:03:58.819540 # ok 11 FPSIMD-5-0
7191 01:03:58.819941 # ok 12 FPSIMD-5-1
7192 01:03:58.822736 # ok 13 FPSIMD-6-0
7193 01:03:58.823121 # ok 14 FPSIMD-6-1
7194 01:03:58.826608 # ok 15 FPSIMD-7-0
7195 01:03:58.827172 # ok 16 FPSIMD-7-1
7196 01:03:58.832808 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=704958, signals=9
7197 01:03:58.843021 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=771832, signals=10
7198 01:03:58.849647 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=838262, signals=10
7199 01:03:58.856073 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=728830, signals=10
7200 01:03:58.862415 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=848616, signals=10
7201 01:03:58.868899 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=712592, signals=10
7202 01:03:58.875783 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=956924, signals=10
7203 01:03:58.886193 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=789323, signals=9
7204 01:03:58.892454 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=755581, signals=10
7205 01:03:58.895807 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
7206 01:03:58.899268 ok 29 selftests: arm64: fp-stress
7207 01:03:58.902024 # selftests: arm64: sve-ptrace
7208 01:03:58.905762 # TAP version 13
7209 01:03:58.906291 # 1..4104
7210 01:03:58.908783 # ok 2 # SKIP SVE not available
7211 01:03:58.912561 # # Planned tests != run tests (4104 != 1)
7212 01:03:58.915536 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7213 01:03:58.922089 ok 30 selftests: arm64: sve-ptrace # SKIP
7214 01:03:58.925690 # selftests: arm64: sve-probe-vls
7215 01:03:58.926128 # TAP version 13
7216 01:03:58.926448 # 1..2
7217 01:03:58.928872 # ok 2 # SKIP SVE not available
7218 01:03:58.931857 # # Planned tests != run tests (2 != 1)
7219 01:03:58.938684 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7220 01:03:58.942013 ok 31 selftests: arm64: sve-probe-vls # SKIP
7221 01:03:58.945947 # selftests: arm64: vec-syscfg
7222 01:03:58.946382 # TAP version 13
7223 01:03:58.946694 # 1..20
7224 01:03:58.949012 # ok 1 # SKIP SVE not supported
7225 01:03:58.952141 # ok 2 # SKIP SVE not supported
7226 01:03:58.955941 # ok 3 # SKIP SVE not supported
7227 01:03:58.958424 # ok 4 # SKIP SVE not supported
7228 01:03:58.962178 # ok 5 # SKIP SVE not supported
7229 01:03:58.965267 # ok 6 # SKIP SVE not supported
7230 01:03:58.965662 # ok 7 # SKIP SVE not supported
7231 01:03:58.968859 # ok 8 # SKIP SVE not supported
7232 01:03:58.971766 # ok 9 # SKIP SVE not supported
7233 01:03:58.974996 # ok 10 # SKIP SVE not supported
7234 01:03:58.978212 # ok 11 # SKIP SME not supported
7235 01:03:58.981702 # ok 12 # SKIP SME not supported
7236 01:03:58.985127 # ok 13 # SKIP SME not supported
7237 01:03:58.988375 # ok 14 # SKIP SME not supported
7238 01:03:58.991614 # ok 15 # SKIP SME not supported
7239 01:03:58.995006 # ok 16 # SKIP SME not supported
7240 01:03:58.995537 # ok 17 # SKIP SME not supported
7241 01:03:58.997852 # ok 18 # SKIP SME not supported
7242 01:03:59.001778 # ok 19 # SKIP SME not supported
7243 01:03:59.004683 # ok 20 # SKIP SME not supported
7244 01:03:59.011352 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
7245 01:03:59.014986 ok 32 selftests: arm64: vec-syscfg
7246 01:03:59.015385 # selftests: arm64: za-fork
7247 01:03:59.018345 # TAP version 13
7248 01:03:59.018777 # 1..1
7249 01:03:59.019116 # # PID: 1282
7250 01:03:59.021555 # # SME support not present
7251 01:03:59.024643 # ok 0 skipped
7252 01:03:59.028027 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7253 01:03:59.031237 ok 33 selftests: arm64: za-fork
7254 01:03:59.034416 # selftests: arm64: za-ptrace
7255 01:03:59.110147 # TAP version 13
7256 01:03:59.110614 # 1..1
7257 01:03:59.113367 # ok 2 # SKIP SME not available
7258 01:03:59.120502 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7259 01:03:59.123293 ok 34 selftests: arm64: za-ptrace # SKIP
7260 01:03:59.135278 # selftests: arm64: check_buffer_fill
7261 01:03:59.216293 # # SKIP: MTE features unavailable
7262 01:03:59.224739 ok 35 selftests: arm64: check_buffer_fill # SKIP
7263 01:03:59.242118 # selftests: arm64: check_child_memory
7264 01:03:59.321291 # # SKIP: MTE features unavailable
7265 01:03:59.329458 ok 36 selftests: arm64: check_child_memory # SKIP
7266 01:03:59.349527 # selftests: arm64: check_gcr_el1_cswitch
7267 01:03:59.419466 # # SKIP: MTE features unavailable
7268 01:03:59.428089 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
7269 01:03:59.445523 # selftests: arm64: check_ksm_options
7270 01:03:59.522133 # # SKIP: MTE features unavailable
7271 01:03:59.530368 ok 38 selftests: arm64: check_ksm_options # SKIP
7272 01:03:59.547579 # selftests: arm64: check_mmap_options
7273 01:03:59.629737 # # SKIP: MTE features unavailable
7274 01:03:59.639774 ok 39 selftests: arm64: check_mmap_options # SKIP
7275 01:03:59.653853 # selftests: arm64: check_prctl
7276 01:03:59.725528 # TAP version 13
7277 01:03:59.726085 # 1..5
7278 01:03:59.728959 # ok 1 check_basic_read
7279 01:03:59.729485 # ok 2 NONE
7280 01:03:59.732807 # ok 3 # SKIP SYNC
7281 01:03:59.733353 # ok 4 # SKIP ASYNC
7282 01:03:59.735775 # ok 5 # SKIP SYNC+ASYNC
7283 01:03:59.738737 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
7284 01:03:59.742350 ok 40 selftests: arm64: check_prctl
7285 01:03:59.751160 # selftests: arm64: check_tags_inclusion
7286 01:03:59.827574 # # SKIP: MTE features unavailable
7287 01:03:59.837621 ok 41 selftests: arm64: check_tags_inclusion # SKIP
7288 01:03:59.851465 # selftests: arm64: check_user_mem
7289 01:03:59.943720 # # SKIP: MTE features unavailable
7290 01:03:59.953003 ok 42 selftests: arm64: check_user_mem # SKIP
7291 01:03:59.968621 # selftests: arm64: btitest
7292 01:04:00.047293 # TAP version 13
7293 01:04:00.047806 # 1..18
7294 01:04:00.050448 # # HWCAP_PACA not present
7295 01:04:00.053653 # # HWCAP2_BTI not present
7296 01:04:00.054152 # # Test binary built for BTI
7297 01:04:00.060141 # ok 1 nohint_func/call_using_br_x0 # SKIP
7298 01:04:00.063301 # ok 1 nohint_func/call_using_br_x16 # SKIP
7299 01:04:00.066619 # ok 1 nohint_func/call_using_blr # SKIP
7300 01:04:00.069824 # ok 1 bti_none_func/call_using_br_x0 # SKIP
7301 01:04:00.073462 # ok 1 bti_none_func/call_using_br_x16 # SKIP
7302 01:04:00.079851 # ok 1 bti_none_func/call_using_blr # SKIP
7303 01:04:00.082580 # ok 1 bti_c_func/call_using_br_x0 # SKIP
7304 01:04:00.086212 # ok 1 bti_c_func/call_using_br_x16 # SKIP
7305 01:04:00.089818 # ok 1 bti_c_func/call_using_blr # SKIP
7306 01:04:00.093476 # ok 1 bti_j_func/call_using_br_x0 # SKIP
7307 01:04:00.096471 # ok 1 bti_j_func/call_using_br_x16 # SKIP
7308 01:04:00.099920 # ok 1 bti_j_func/call_using_blr # SKIP
7309 01:04:00.103250 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
7310 01:04:00.110153 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
7311 01:04:00.113486 # ok 1 bti_jc_func/call_using_blr # SKIP
7312 01:04:00.116756 # ok 1 paciasp_func/call_using_br_x0 # SKIP
7313 01:04:00.119740 # ok 1 paciasp_func/call_using_br_x16 # SKIP
7314 01:04:00.123167 # ok 1 paciasp_func/call_using_blr # SKIP
7315 01:04:00.129800 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
7316 01:04:00.133418 # # WARNING - EXPECTED TEST COUNT WRONG
7317 01:04:00.136744 ok 43 selftests: arm64: btitest
7318 01:04:00.137180 # selftests: arm64: nobtitest
7319 01:04:00.152746 # TAP version 13
7320 01:04:00.153307 # 1..18
7321 01:04:00.155779 # # HWCAP_PACA not present
7322 01:04:00.159223 # # HWCAP2_BTI not present
7323 01:04:00.162295 # # Test binary not built for BTI
7324 01:04:00.165810 # ok 1 nohint_func/call_using_br_x0 # SKIP
7325 01:04:00.168797 # ok 1 nohint_func/call_using_br_x16 # SKIP
7326 01:04:00.172065 # ok 1 nohint_func/call_using_blr # SKIP
7327 01:04:00.176145 # ok 1 bti_none_func/call_using_br_x0 # SKIP
7328 01:04:00.182037 # ok 1 bti_none_func/call_using_br_x16 # SKIP
7329 01:04:00.185298 # ok 1 bti_none_func/call_using_blr # SKIP
7330 01:04:00.188569 # ok 1 bti_c_func/call_using_br_x0 # SKIP
7331 01:04:00.192226 # ok 1 bti_c_func/call_using_br_x16 # SKIP
7332 01:04:00.195759 # ok 1 bti_c_func/call_using_blr # SKIP
7333 01:04:00.198525 # ok 1 bti_j_func/call_using_br_x0 # SKIP
7334 01:04:00.201673 # ok 1 bti_j_func/call_using_br_x16 # SKIP
7335 01:04:00.205510 # ok 1 bti_j_func/call_using_blr # SKIP
7336 01:04:00.212411 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
7337 01:04:00.215758 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
7338 01:04:00.218768 # ok 1 bti_jc_func/call_using_blr # SKIP
7339 01:04:00.222387 # ok 1 paciasp_func/call_using_br_x0 # SKIP
7340 01:04:00.225307 # ok 1 paciasp_func/call_using_br_x16 # SKIP
7341 01:04:00.228368 # ok 1 paciasp_func/call_using_blr # SKIP
7342 01:04:00.235378 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
7343 01:04:00.238554 # # WARNING - EXPECTED TEST COUNT WRONG
7344 01:04:00.241957 ok 44 selftests: arm64: nobtitest
7345 01:04:00.245250 # selftests: arm64: hwcap
7346 01:04:00.262646 # TAP version 13
7347 01:04:00.263161 # 1..28
7348 01:04:00.265630 # ok 1 cpuinfo_match_RNG
7349 01:04:00.269359 # # SIGILL reported for RNG
7350 01:04:00.269870 # ok 2 # SKIP sigill_RNG
7351 01:04:00.271935 # ok 3 cpuinfo_match_SME
7352 01:04:00.275965 # ok 4 sigill_SME
7353 01:04:00.276499 # ok 5 cpuinfo_match_SVE
7354 01:04:00.278979 # ok 6 sigill_SVE
7355 01:04:00.279407 # ok 7 cpuinfo_match_SVE 2
7356 01:04:00.282729 # # SIGILL reported for SVE 2
7357 01:04:00.285851 # ok 8 # SKIP sigill_SVE 2
7358 01:04:00.288804 # ok 9 cpuinfo_match_SVE AES
7359 01:04:00.292065 # # SIGILL reported for SVE AES
7360 01:04:00.295424 # ok 10 # SKIP sigill_SVE AES
7361 01:04:00.295843 # ok 11 cpuinfo_match_SVE2 PMULL
7362 01:04:00.298562 # # SIGILL reported for SVE2 PMULL
7363 01:04:00.302067 # ok 12 # SKIP sigill_SVE2 PMULL
7364 01:04:00.305477 # ok 13 cpuinfo_match_SVE2 BITPERM
7365 01:04:00.308207 # # SIGILL reported for SVE2 BITPERM
7366 01:04:00.311670 # ok 14 # SKIP sigill_SVE2 BITPERM
7367 01:04:00.315444 # ok 15 cpuinfo_match_SVE2 SHA3
7368 01:04:00.318438 # # SIGILL reported for SVE2 SHA3
7369 01:04:00.321885 # ok 16 # SKIP sigill_SVE2 SHA3
7370 01:04:00.325410 # ok 17 cpuinfo_match_SVE2 SM4
7371 01:04:00.328402 # # SIGILL reported for SVE2 SM4
7372 01:04:00.328787 # ok 18 # SKIP sigill_SVE2 SM4
7373 01:04:00.331982 # ok 19 cpuinfo_match_SVE2 I8MM
7374 01:04:00.334991 # # SIGILL reported for SVE2 I8MM
7375 01:04:00.338270 # ok 20 # SKIP sigill_SVE2 I8MM
7376 01:04:00.341632 # ok 21 cpuinfo_match_SVE2 F32MM
7377 01:04:00.345345 # # SIGILL reported for SVE2 F32MM
7378 01:04:00.348192 # ok 22 # SKIP sigill_SVE2 F32MM
7379 01:04:00.351762 # ok 23 cpuinfo_match_SVE2 F64MM
7380 01:04:00.355100 # # SIGILL reported for SVE2 F64MM
7381 01:04:00.358316 # ok 24 # SKIP sigill_SVE2 F64MM
7382 01:04:00.358712 # ok 25 cpuinfo_match_SVE2 BF16
7383 01:04:00.361703 # # SIGILL reported for SVE2 BF16
7384 01:04:00.364964 # ok 26 # SKIP sigill_SVE2 BF16
7385 01:04:00.368040 # ok 27 cpuinfo_match_SVE2 EBF16
7386 01:04:00.371369 # ok 28 # SKIP sigill_SVE2 EBF16
7387 01:04:00.378275 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
7388 01:04:00.378721 ok 45 selftests: arm64: hwcap
7389 01:04:00.381626 # selftests: arm64: ptrace
7390 01:04:00.384692 # TAP version 13
7391 01:04:00.385189 # 1..7
7392 01:04:00.388132 # # Parent is 1525, child is 1526
7393 01:04:00.388523 # ok 1 read_tpidr_one
7394 01:04:00.391461 # ok 2 write_tpidr_one
7395 01:04:00.394843 # ok 3 verify_tpidr_one
7396 01:04:00.395230 # ok 4 count_tpidrs
7397 01:04:00.398230 # ok 5 tpidr2_write
7398 01:04:00.398615 # ok 6 tpidr2_read
7399 01:04:00.401223 # ok 7 write_tpidr_only
7400 01:04:00.404458 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
7401 01:04:00.407966 ok 46 selftests: arm64: ptrace
7402 01:04:00.411433 # selftests: arm64: syscall-abi
7403 01:04:00.459541 # TAP version 13
7404 01:04:00.460007 # 1..2
7405 01:04:00.463235 # ok 1 getpid() FPSIMD
7406 01:04:00.466309 # ok 2 sched_yield() FPSIMD
7407 01:04:00.469432 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
7408 01:04:00.472627 ok 47 selftests: arm64: syscall-abi
7409 01:04:00.481282 # selftests: arm64: tpidr2
7410 01:04:00.571780 # TAP version 13
7411 01:04:00.572284 # 1..5
7412 01:04:00.574474 # # PID: 1562
7413 01:04:00.574933 # # SME support not present
7414 01:04:00.577861 # ok 0 skipped, TPIDR2 not supported
7415 01:04:00.581047 # ok 1 skipped, TPIDR2 not supported
7416 01:04:00.584666 # ok 2 skipped, TPIDR2 not supported
7417 01:04:00.588605 # ok 3 skipped, TPIDR2 not supported
7418 01:04:00.591459 # ok 4 skipped, TPIDR2 not supported
7419 01:04:00.597686 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
7420 01:04:00.601162 ok 48 selftests: arm64: tpidr2
7421 01:04:02.288819 arm64_tags_test pass
7422 01:04:02.291927 arm64_run_tags_test_sh pass
7423 01:04:02.295137 arm64_fake_sigreturn_bad_magic pass
7424 01:04:02.298949 arm64_fake_sigreturn_bad_size pass
7425 01:04:02.302164 arm64_fake_sigreturn_bad_size_for_magic0 pass
7426 01:04:02.305509 arm64_fake_sigreturn_duplicated_fpsimd pass
7427 01:04:02.308764 arm64_fake_sigreturn_misaligned_sp pass
7428 01:04:02.312313 arm64_fake_sigreturn_missing_fpsimd pass
7429 01:04:02.315653 arm64_fake_sigreturn_sme_change_vl skip
7430 01:04:02.322415 arm64_fake_sigreturn_sve_change_vl skip
7431 01:04:02.325752 arm64_mangle_pstate_invalid_compat_toggle pass
7432 01:04:02.328634 arm64_mangle_pstate_invalid_daif_bits pass
7433 01:04:02.331808 arm64_mangle_pstate_invalid_mode_el1h pass
7434 01:04:02.339038 arm64_mangle_pstate_invalid_mode_el1t pass
7435 01:04:02.342106 arm64_mangle_pstate_invalid_mode_el2h pass
7436 01:04:02.345267 arm64_mangle_pstate_invalid_mode_el2t pass
7437 01:04:02.348810 arm64_mangle_pstate_invalid_mode_el3h pass
7438 01:04:02.351991 arm64_mangle_pstate_invalid_mode_el3t pass
7439 01:04:02.355309 arm64_sme_trap_no_sm skip
7440 01:04:02.358355 arm64_sme_trap_non_streaming skip
7441 01:04:02.362469 arm64_sme_trap_za pass
7442 01:04:02.362976 arm64_sme_vl skip
7443 01:04:02.364933 arm64_ssve_regs skip
7444 01:04:02.365357 arm64_sve_regs skip
7445 01:04:02.368956 arm64_sve_vl skip
7446 01:04:02.371522 arm64_za_no_regs skip
7447 01:04:02.371946 arm64_za_regs skip
7448 01:04:02.375238 arm64_pac_PAUTH_not_enabled skip
7449 01:04:02.378767 arm64_pac_PAUTH_not_enabled_dup2 skip
7450 01:04:02.381882 arm64_pac_Generic_PAUTH_not_enabled skip
7451 01:04:02.384843 arm64_pac_PAUTH_not_enabled_dup3 skip
7452 01:04:02.388515 arm64_pac_PAUTH_not_enabled_dup4 skip
7453 01:04:02.391670 arm64_pac_PAUTH_not_enabled_dup5 skip
7454 01:04:02.398208 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
7455 01:04:02.398675 arm64_pac pass
7456 01:04:02.401663 arm64_fp-stress_FPSIMD-0-0 pass
7457 01:04:02.405262 arm64_fp-stress_FPSIMD-0-1 pass
7458 01:04:02.408614 arm64_fp-stress_FPSIMD-1-0 pass
7459 01:04:02.411782 arm64_fp-stress_FPSIMD-1-1 pass
7460 01:04:02.414962 arm64_fp-stress_FPSIMD-2-0 pass
7461 01:04:02.415348 arm64_fp-stress_FPSIMD-2-1 pass
7462 01:04:02.418272 arm64_fp-stress_FPSIMD-3-0 pass
7463 01:04:02.421883 arm64_fp-stress_FPSIMD-3-1 pass
7464 01:04:02.425487 arm64_fp-stress_FPSIMD-4-0 pass
7465 01:04:02.428263 arm64_fp-stress_FPSIMD-4-1 pass
7466 01:04:02.431592 arm64_fp-stress_FPSIMD-5-0 pass
7467 01:04:02.434759 arm64_fp-stress_FPSIMD-5-1 pass
7468 01:04:02.438109 arm64_fp-stress_FPSIMD-6-0 pass
7469 01:04:02.441038 arm64_fp-stress_FPSIMD-6-1 pass
7470 01:04:02.445043 arm64_fp-stress_FPSIMD-7-0 pass
7471 01:04:02.445535 arm64_fp-stress_FPSIMD-7-1 pass
7472 01:04:02.448109 arm64_fp-stress pass
7473 01:04:02.451407 arm64_sve-ptrace_SVE_not_available skip
7474 01:04:02.454700 arm64_sve-ptrace skip
7475 01:04:02.458078 arm64_sve-probe-vls_SVE_not_available skip
7476 01:04:02.461595 arm64_sve-probe-vls skip
7477 01:04:02.464670 arm64_vec-syscfg_SVE_not_supported skip
7478 01:04:02.467784 arm64_vec-syscfg_SVE_not_supported_dup2 skip
7479 01:04:02.470963 arm64_vec-syscfg_SVE_not_supported_dup3 skip
7480 01:04:02.474602 arm64_vec-syscfg_SVE_not_supported_dup4 skip
7481 01:04:02.478127 arm64_vec-syscfg_SVE_not_supported_dup5 skip
7482 01:04:02.485023 arm64_vec-syscfg_SVE_not_supported_dup6 skip
7483 01:04:02.487756 arm64_vec-syscfg_SVE_not_supported_dup7 skip
7484 01:04:02.491137 arm64_vec-syscfg_SVE_not_supported_dup8 skip
7485 01:04:02.494582 arm64_vec-syscfg_SVE_not_supported_dup9 skip
7486 01:04:02.501319 arm64_vec-syscfg_SVE_not_supported_dup10 skip
7487 01:04:02.503990 arm64_vec-syscfg_SME_not_supported skip
7488 01:04:02.507634 arm64_vec-syscfg_SME_not_supported_dup2 skip
7489 01:04:02.510951 arm64_vec-syscfg_SME_not_supported_dup3 skip
7490 01:04:02.514083 arm64_vec-syscfg_SME_not_supported_dup4 skip
7491 01:04:02.517398 arm64_vec-syscfg_SME_not_supported_dup5 skip
7492 01:04:02.524315 arm64_vec-syscfg_SME_not_supported_dup6 skip
7493 01:04:02.526914 arm64_vec-syscfg_SME_not_supported_dup7 skip
7494 01:04:02.530466 arm64_vec-syscfg_SME_not_supported_dup8 skip
7495 01:04:02.533938 arm64_vec-syscfg_SME_not_supported_dup9 skip
7496 01:04:02.540550 arm64_vec-syscfg_SME_not_supported_dup10 skip
7497 01:04:02.541009 arm64_vec-syscfg pass
7498 01:04:02.544137 arm64_za-fork_skipped pass
7499 01:04:02.544607 arm64_za-fork pass
7500 01:04:02.546784 arm64_za-ptrace_SME_not_available skip
7501 01:04:02.550742 arm64_za-ptrace skip
7502 01:04:02.553584 arm64_check_buffer_fill skip
7503 01:04:02.557094 arm64_check_child_memory skip
7504 01:04:02.560525 arm64_check_gcr_el1_cswitch skip
7505 01:04:02.563607 arm64_check_ksm_options skip
7506 01:04:02.566835 arm64_check_mmap_options skip
7507 01:04:02.569889 arm64_check_prctl_check_basic_read pass
7508 01:04:02.573620 arm64_check_prctl_NONE pass
7509 01:04:02.574042 arm64_check_prctl_SYNC skip
7510 01:04:02.576987 arm64_check_prctl_ASYNC skip
7511 01:04:02.580317 arm64_check_prctl_SYNC_ASYNC skip
7512 01:04:02.583391 arm64_check_prctl pass
7513 01:04:02.586741 arm64_check_tags_inclusion skip
7514 01:04:02.589674 arm64_check_user_mem skip
7515 01:04:02.593437 arm64_btitest_nohint_func_call_using_br_x0 skip
7516 01:04:02.596775 arm64_btitest_nohint_func_call_using_br_x16 skip
7517 01:04:02.603104 arm64_btitest_nohint_func_call_using_blr skip
7518 01:04:02.607138 arm64_btitest_bti_none_func_call_using_br_x0 skip
7519 01:04:02.614030 arm64_btitest_bti_none_func_call_using_br_x16 skip
7520 01:04:02.617138 arm64_btitest_bti_none_func_call_using_blr skip
7521 01:04:02.620370 arm64_btitest_bti_c_func_call_using_br_x0 skip
7522 01:04:02.626654 arm64_btitest_bti_c_func_call_using_br_x16 skip
7523 01:04:02.630399 arm64_btitest_bti_c_func_call_using_blr skip
7524 01:04:02.633070 arm64_btitest_bti_j_func_call_using_br_x0 skip
7525 01:04:02.640160 arm64_btitest_bti_j_func_call_using_br_x16 skip
7526 01:04:02.643522 arm64_btitest_bti_j_func_call_using_blr skip
7527 01:04:02.646502 arm64_btitest_bti_jc_func_call_using_br_x0 skip
7528 01:04:02.652979 arm64_btitest_bti_jc_func_call_using_br_x16 skip
7529 01:04:02.656529 arm64_btitest_bti_jc_func_call_using_blr skip
7530 01:04:02.659879 arm64_btitest_paciasp_func_call_using_br_x0 skip
7531 01:04:02.666545 arm64_btitest_paciasp_func_call_using_br_x16 skip
7532 01:04:02.669715 arm64_btitest_paciasp_func_call_using_blr skip
7533 01:04:02.670133 arm64_btitest pass
7534 01:04:02.676400 arm64_nobtitest_nohint_func_call_using_br_x0 skip
7535 01:04:02.679772 arm64_nobtitest_nohint_func_call_using_br_x16 skip
7536 01:04:02.682989 arm64_nobtitest_nohint_func_call_using_blr skip
7537 01:04:02.689675 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
7538 01:04:02.693121 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
7539 01:04:02.699673 arm64_nobtitest_bti_none_func_call_using_blr skip
7540 01:04:02.703122 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
7541 01:04:02.706071 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
7542 01:04:02.712750 arm64_nobtitest_bti_c_func_call_using_blr skip
7543 01:04:02.715906 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
7544 01:04:02.719330 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
7545 01:04:02.722558 arm64_nobtitest_bti_j_func_call_using_blr skip
7546 01:04:02.729511 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
7547 01:04:02.732604 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
7548 01:04:02.736310 arm64_nobtitest_bti_jc_func_call_using_blr skip
7549 01:04:02.742575 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
7550 01:04:02.745854 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
7551 01:04:02.749195 arm64_nobtitest_paciasp_func_call_using_blr skip
7552 01:04:02.752322 arm64_nobtitest pass
7553 01:04:02.755629 arm64_hwcap_cpuinfo_match_RNG pass
7554 01:04:02.758830 arm64_hwcap_sigill_RNG skip
7555 01:04:02.762438 arm64_hwcap_cpuinfo_match_SME pass
7556 01:04:02.762827 arm64_hwcap_sigill_SME pass
7557 01:04:02.765830 arm64_hwcap_cpuinfo_match_SVE pass
7558 01:04:02.768784 arm64_hwcap_sigill_SVE pass
7559 01:04:02.772597 arm64_hwcap_cpuinfo_match_SVE_2 pass
7560 01:04:02.775271 arm64_hwcap_sigill_SVE_2 skip
7561 01:04:02.778549 arm64_hwcap_cpuinfo_match_SVE_AES pass
7562 01:04:02.782231 arm64_hwcap_sigill_SVE_AES skip
7563 01:04:02.785505 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
7564 01:04:02.788566 arm64_hwcap_sigill_SVE2_PMULL skip
7565 01:04:02.791970 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
7566 01:04:02.795289 arm64_hwcap_sigill_SVE2_BITPERM skip
7567 01:04:02.799050 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
7568 01:04:02.801936 arm64_hwcap_sigill_SVE2_SHA3 skip
7569 01:04:02.805121 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
7570 01:04:02.808162 arm64_hwcap_sigill_SVE2_SM4 skip
7571 01:04:02.812262 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
7572 01:04:02.815407 arm64_hwcap_sigill_SVE2_I8MM skip
7573 01:04:02.818525 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
7574 01:04:02.821807 arm64_hwcap_sigill_SVE2_F32MM skip
7575 01:04:02.825541 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
7576 01:04:02.828729 arm64_hwcap_sigill_SVE2_F64MM skip
7577 01:04:02.835320 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
7578 01:04:02.838480 arm64_hwcap_sigill_SVE2_BF16 skip
7579 01:04:02.841640 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
7580 01:04:02.845273 arm64_hwcap_sigill_SVE2_EBF16 skip
7581 01:04:02.845658 arm64_hwcap pass
7582 01:04:02.848337 arm64_ptrace_read_tpidr_one pass
7583 01:04:02.852124 arm64_ptrace_write_tpidr_one pass
7584 01:04:02.855013 arm64_ptrace_verify_tpidr_one pass
7585 01:04:02.858517 arm64_ptrace_count_tpidrs pass
7586 01:04:02.861555 arm64_ptrace_tpidr2_write pass
7587 01:04:02.862071 arm64_ptrace_tpidr2_read pass
7588 01:04:02.864984 arm64_ptrace_write_tpidr_only pass
7589 01:04:02.868627 arm64_ptrace pass
7590 01:04:02.871680 arm64_syscall-abi_getpid_FPSIMD pass
7591 01:04:02.875103 arm64_syscall-abi_sched_yield_FPSIMD pass
7592 01:04:02.877794 arm64_syscall-abi pass
7593 01:04:02.881126 arm64_tpidr2_skipped_TPIDR2_not_supported pass
7594 01:04:02.884407 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
7595 01:04:02.891015 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
7596 01:04:02.894704 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
7597 01:04:02.897732 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
7598 01:04:02.900912 arm64_tpidr2 pass
7599 01:04:02.904383 + ../../utils/send-to-lava.sh ./output/result.txt
7600 01:04:02.910962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
7601 01:04:02.911230 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
7603 01:04:02.917526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
7604 01:04:02.917770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
7606 01:04:02.921532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
7608 01:04:02.924352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
7609 01:04:02.930795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
7610 01:04:02.931037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
7612 01:04:02.937626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
7613 01:04:02.937894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
7615 01:04:02.978375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
7616 01:04:02.978645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
7618 01:04:03.026285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
7619 01:04:03.026574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
7621 01:04:03.070440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
7622 01:04:03.070700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
7624 01:04:03.111772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
7625 01:04:03.112020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
7627 01:04:03.158909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
7628 01:04:03.159566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
7630 01:04:03.210869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
7631 01:04:03.211500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
7633 01:04:03.266012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
7634 01:04:03.266646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
7636 01:04:03.318502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
7637 01:04:03.319129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
7639 01:04:03.370649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
7640 01:04:03.371416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
7642 01:04:03.423288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
7643 01:04:03.423907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
7645 01:04:03.473361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
7646 01:04:03.474031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
7648 01:04:03.527676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
7649 01:04:03.528373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
7651 01:04:03.582841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
7652 01:04:03.583576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
7654 01:04:03.641331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
7655 01:04:03.642110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
7657 01:04:03.698123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
7658 01:04:03.698845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
7660 01:04:03.757348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
7662 01:04:03.759968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
7663 01:04:03.809043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
7664 01:04:03.809698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
7666 01:04:03.857634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
7667 01:04:03.857886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
7669 01:04:03.901182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
7670 01:04:03.901461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
7672 01:04:03.937615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
7673 01:04:03.937894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
7675 01:04:03.981807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
7676 01:04:03.982084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
7678 01:04:04.020124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
7679 01:04:04.020399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
7681 01:04:04.063103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
7682 01:04:04.063398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
7684 01:04:04.111603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
7686 01:04:04.114493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
7687 01:04:04.162189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
7688 01:04:04.162905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
7690 01:04:04.214445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
7691 01:04:04.215202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
7693 01:04:04.262352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
7694 01:04:04.263111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
7696 01:04:04.314864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
7697 01:04:04.315520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
7699 01:04:04.369587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
7700 01:04:04.370295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
7702 01:04:04.420025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
7703 01:04:04.420797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
7705 01:04:04.466093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
7706 01:04:04.466746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
7708 01:04:04.516040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
7709 01:04:04.516691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
7711 01:04:04.570880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
7712 01:04:04.571597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
7714 01:04:04.628865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
7715 01:04:04.629584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
7717 01:04:04.686693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
7718 01:04:04.687399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
7720 01:04:04.740149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
7721 01:04:04.740771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
7723 01:04:04.795083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
7724 01:04:04.795806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
7726 01:04:04.847598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
7727 01:04:04.848354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
7729 01:04:04.894720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
7730 01:04:04.895381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
7732 01:04:04.943064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
7733 01:04:04.943766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
7735 01:04:04.998753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
7736 01:04:04.999412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
7738 01:04:05.052276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
7739 01:04:05.053005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
7741 01:04:05.110754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
7742 01:04:05.111519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
7744 01:04:05.167749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
7745 01:04:05.168418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
7747 01:04:05.226721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
7748 01:04:05.227372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
7750 01:04:05.275208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
7751 01:04:05.275863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
7753 01:04:05.325723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
7754 01:04:05.326387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
7756 01:04:05.375190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
7757 01:04:05.375821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
7759 01:04:05.427504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
7760 01:04:05.428160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
7762 01:04:05.478913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
7763 01:04:05.479552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
7765 01:04:05.541380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
7766 01:04:05.542063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
7768 01:04:05.595066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
7769 01:04:05.595760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
7771 01:04:05.661321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
7772 01:04:05.661970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
7774 01:04:05.715550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
7775 01:04:05.716263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
7777 01:04:05.775543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
7778 01:04:05.776278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
7780 01:04:05.828972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
7781 01:04:05.829632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
7783 01:04:05.888363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
7784 01:04:05.889017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
7786 01:04:05.942770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
7787 01:04:05.943034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
7789 01:04:05.992439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
7790 01:04:05.993090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
7792 01:04:06.053829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
7793 01:04:06.054598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
7795 01:04:06.107665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
7796 01:04:06.108395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
7798 01:04:06.156666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
7799 01:04:06.157533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
7801 01:04:06.202876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
7802 01:04:06.203517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
7804 01:04:06.251488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
7805 01:04:06.252202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
7807 01:04:06.305895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
7808 01:04:06.306651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
7810 01:04:06.356659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
7811 01:04:06.357390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
7813 01:04:06.408117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
7814 01:04:06.408849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
7816 01:04:06.453846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
7817 01:04:06.454522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
7819 01:04:06.508212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
7820 01:04:06.508856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
7822 01:04:06.557894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
7823 01:04:06.558185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
7825 01:04:06.609711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
7826 01:04:06.610395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
7828 01:04:06.661071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
7829 01:04:06.661723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
7831 01:04:06.709761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
7832 01:04:06.710447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
7834 01:04:06.760437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
7835 01:04:06.761080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
7837 01:04:06.817778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
7838 01:04:06.818465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
7840 01:04:06.874513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
7841 01:04:06.875190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
7843 01:04:06.920433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
7844 01:04:06.920824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
7846 01:04:06.971192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
7847 01:04:06.971862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
7849 01:04:07.020413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
7850 01:04:07.021051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
7852 01:04:07.073504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
7854 01:04:07.076370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
7855 01:04:07.127015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
7856 01:04:07.127652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
7858 01:04:07.181000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
7859 01:04:07.181652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
7861 01:04:07.233944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
7862 01:04:07.234611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
7864 01:04:07.282412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
7865 01:04:07.283050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
7867 01:04:07.332308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
7868 01:04:07.332948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
7870 01:04:07.380703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
7871 01:04:07.381413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
7873 01:04:07.430091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
7875 01:04:07.432733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
7876 01:04:07.488133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
7877 01:04:07.488782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
7879 01:04:07.539201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
7880 01:04:07.539853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
7882 01:04:07.593353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
7883 01:04:07.594027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
7885 01:04:07.652302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
7886 01:04:07.653026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
7888 01:04:07.711527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
7889 01:04:07.712178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
7891 01:04:07.774100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
7892 01:04:07.774746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
7894 01:04:07.820848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
7895 01:04:07.821105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
7897 01:04:07.864433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
7898 01:04:07.865058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
7900 01:04:07.912079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
7901 01:04:07.912724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
7903 01:04:07.961293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
7904 01:04:07.961919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
7906 01:04:08.012151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
7907 01:04:08.012947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
7909 01:04:08.061634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
7910 01:04:08.062262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
7912 01:04:08.108470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
7913 01:04:08.108745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
7915 01:04:08.156332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
7916 01:04:08.156594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
7918 01:04:08.203419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
7919 01:04:08.203939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
7921 01:04:08.254133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
7922 01:04:08.254765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
7924 01:04:08.308180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
7925 01:04:08.308810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
7927 01:04:08.355917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
7928 01:04:08.356544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
7930 01:04:08.405423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
7931 01:04:08.406195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
7933 01:04:08.454280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
7934 01:04:08.454525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
7936 01:04:08.500697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
7937 01:04:08.501048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
7939 01:04:08.543382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
7940 01:04:08.544030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
7942 01:04:08.600545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
7943 01:04:08.601183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
7945 01:04:08.651868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
7946 01:04:08.652498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
7948 01:04:08.700790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
7949 01:04:08.701099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
7951 01:04:08.746486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
7952 01:04:08.747117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
7954 01:04:08.799886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
7955 01:04:08.800518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
7957 01:04:08.857740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
7958 01:04:08.858470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
7960 01:04:08.913275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
7961 01:04:08.913899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
7963 01:04:08.968617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
7964 01:04:08.969302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
7966 01:04:09.025385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
7967 01:04:09.026158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
7969 01:04:09.081471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
7970 01:04:09.082159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
7972 01:04:09.133773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
7973 01:04:09.134459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
7975 01:04:09.179292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
7976 01:04:09.180135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
7978 01:04:09.226619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
7979 01:04:09.227269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
7981 01:04:09.272572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
7982 01:04:09.273211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
7984 01:04:09.318839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
7985 01:04:09.319484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
7987 01:04:09.366662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
7988 01:04:09.367295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
7990 01:04:09.416803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
7991 01:04:09.417436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
7993 01:04:09.465807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
7994 01:04:09.466496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
7996 01:04:09.517460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
7997 01:04:09.518093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
7999 01:04:09.572898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
8000 01:04:09.573527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
8002 01:04:09.625767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
8003 01:04:09.626499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
8005 01:04:09.685727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
8006 01:04:09.686517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
8008 01:04:09.732736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
8009 01:04:09.733404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
8011 01:04:09.785741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
8012 01:04:09.786553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
8014 01:04:09.825035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
8015 01:04:09.825302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
8017 01:04:09.869549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
8018 01:04:09.869799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
8020 01:04:09.906300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
8021 01:04:09.906630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
8023 01:04:09.947532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
8024 01:04:09.947810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
8026 01:04:09.980365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
8027 01:04:09.980634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
8029 01:04:10.025288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
8030 01:04:10.025563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
8032 01:04:10.063811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
8033 01:04:10.064100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
8035 01:04:10.104546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
8036 01:04:10.105167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
8038 01:04:10.150915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
8039 01:04:10.151176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
8041 01:04:10.195713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
8042 01:04:10.196213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
8044 01:04:10.236844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
8046 01:04:10.240181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
8047 01:04:10.291905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
8048 01:04:10.292601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
8050 01:04:10.346285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
8052 01:04:10.349410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
8053 01:04:10.400234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
8054 01:04:10.400940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
8056 01:04:10.450536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
8058 01:04:10.453286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
8059 01:04:10.504580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
8060 01:04:10.505298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
8062 01:04:10.552095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
8063 01:04:10.552728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
8065 01:04:10.599583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
8066 01:04:10.600345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
8068 01:04:10.653119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
8069 01:04:10.653879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
8071 01:04:10.703935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
8072 01:04:10.704621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
8074 01:04:10.754523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
8076 01:04:10.757465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
8077 01:04:10.810715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
8078 01:04:10.811351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
8080 01:04:10.860608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
8081 01:04:10.860852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
8083 01:04:10.905934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
8084 01:04:10.906236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
8086 01:04:10.955087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
8088 01:04:10.958016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
8089 01:04:11.008332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
8091 01:04:11.011079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
8092 01:04:11.053322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
8093 01:04:11.053644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
8095 01:04:11.096226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
8096 01:04:11.096478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
8098 01:04:11.141708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
8099 01:04:11.142033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
8101 01:04:11.185585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
8102 01:04:11.185868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
8104 01:04:11.232148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
8105 01:04:11.232573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
8107 01:04:11.278461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
8108 01:04:11.278789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
8110 01:04:11.324434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
8111 01:04:11.324678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
8113 01:04:11.368035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
8114 01:04:11.368343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
8116 01:04:11.410391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
8117 01:04:11.410653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
8119 01:04:11.456882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
8120 01:04:11.457375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
8122 01:04:11.500999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
8123 01:04:11.501443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
8125 01:04:11.552987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
8126 01:04:11.553616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
8128 01:04:11.602144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
8129 01:04:11.602784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
8131 01:04:11.655145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
8132 01:04:11.655794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
8134 01:04:11.708036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
8135 01:04:11.708487 + set +x
8136 01:04:11.709029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
8138 01:04:11.714340 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14368634_1.6.2.3.5>
8139 01:04:11.714962 Received signal: <ENDRUN> 1_kselftest-arm64 14368634_1.6.2.3.5
8140 01:04:11.715304 Ending use of test pattern.
8141 01:04:11.715655 Ending test lava.1_kselftest-arm64 (14368634_1.6.2.3.5), duration 33.71
8143 01:04:11.717849 <LAVA_TEST_RUNNER EXIT>
8144 01:04:11.718535 ok: lava_test_shell seems to have completed
8145 01:04:11.723194 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
8146 01:04:11.724132 end: 3.1 lava-test-shell (duration 00:00:35) [common]
8147 01:04:11.724608 end: 3 lava-test-retry (duration 00:00:35) [common]
8148 01:04:11.725029 start: 4 finalize (timeout 00:07:35) [common]
8149 01:04:11.725440 start: 4.1 power-off (timeout 00:00:30) [common]
8150 01:04:11.726151 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-1', '--port=1', '--command=off']
8151 01:04:12.824923 >> Command sent successfully.
8152 01:04:12.838544 Returned 0 in 1 seconds
8153 01:04:12.939740 end: 4.1 power-off (duration 00:00:01) [common]
8155 01:04:12.941067 start: 4.2 read-feedback (timeout 00:07:34) [common]
8156 01:04:12.942179 Listened to connection for namespace 'common' for up to 1s
8157 01:04:13.942294 Finalising connection for namespace 'common'
8158 01:04:13.942966 Disconnecting from shell: Finalise
8159 01:04:13.943398 / #
8160 01:04:14.044428 end: 4.2 read-feedback (duration 00:00:01) [common]
8161 01:04:14.045089 end: 4 finalize (duration 00:00:02) [common]
8162 01:04:14.045688 Cleaning after the job
8163 01:04:14.046257 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/ramdisk
8164 01:04:14.056457 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/kernel
8165 01:04:14.089709 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/dtb
8166 01:04:14.090036 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/nfsrootfs
8167 01:04:14.160260 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368634/tftp-deploy-3qp76dav/modules
8168 01:04:14.166055 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368634
8169 01:04:14.710590 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368634
8170 01:04:14.710764 Job finished correctly