Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 00:54:53.256445 lava-dispatcher, installed at version: 2024.03
2 00:54:53.256683 start: 0 validate
3 00:54:53.256799 Start time: 2024-06-16 00:54:53.256792+00:00 (UTC)
4 00:54:53.256928 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:54:53.257064 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 00:54:53.506645 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:54:53.506836 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:55:10.013362 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:55:10.013539 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:55:10.262664 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:55:10.262864 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-24-g0315de64ea248%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:55:14.011591 validate duration: 20.75
14 00:55:14.011928 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:55:14.012070 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:55:14.012185 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:55:14.012373 Not decompressing ramdisk as can be used compressed.
18 00:55:14.012498 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 00:55:14.012590 saving as /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/ramdisk/rootfs.cpio.gz
20 00:55:14.012689 total size: 28105535 (26 MB)
21 00:55:14.261920 progress 0 % (0 MB)
22 00:55:14.269941 progress 5 % (1 MB)
23 00:55:14.277800 progress 10 % (2 MB)
24 00:55:14.285880 progress 15 % (4 MB)
25 00:55:14.293852 progress 20 % (5 MB)
26 00:55:14.301957 progress 25 % (6 MB)
27 00:55:14.310039 progress 30 % (8 MB)
28 00:55:14.318197 progress 35 % (9 MB)
29 00:55:14.325773 progress 40 % (10 MB)
30 00:55:14.333416 progress 45 % (12 MB)
31 00:55:14.341545 progress 50 % (13 MB)
32 00:55:14.349474 progress 55 % (14 MB)
33 00:55:14.357512 progress 60 % (16 MB)
34 00:55:14.365606 progress 65 % (17 MB)
35 00:55:14.373745 progress 70 % (18 MB)
36 00:55:14.381609 progress 75 % (20 MB)
37 00:55:14.389701 progress 80 % (21 MB)
38 00:55:14.397820 progress 85 % (22 MB)
39 00:55:14.405571 progress 90 % (24 MB)
40 00:55:14.413886 progress 95 % (25 MB)
41 00:55:14.422461 progress 100 % (26 MB)
42 00:55:14.422783 26 MB downloaded in 0.41 s (65.36 MB/s)
43 00:55:14.423031 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:55:14.423440 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:55:14.423548 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:55:14.423689 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:55:14.423907 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:55:14.424010 saving as /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/kernel/Image
50 00:55:14.424089 total size: 54813184 (52 MB)
51 00:55:14.424192 No compression specified
52 00:55:14.425716 progress 0 % (0 MB)
53 00:55:14.442355 progress 5 % (2 MB)
54 00:55:14.458932 progress 10 % (5 MB)
55 00:55:14.473875 progress 15 % (7 MB)
56 00:55:14.489074 progress 20 % (10 MB)
57 00:55:14.504897 progress 25 % (13 MB)
58 00:55:14.520794 progress 30 % (15 MB)
59 00:55:14.536544 progress 35 % (18 MB)
60 00:55:14.551923 progress 40 % (20 MB)
61 00:55:14.567503 progress 45 % (23 MB)
62 00:55:14.583646 progress 50 % (26 MB)
63 00:55:14.599110 progress 55 % (28 MB)
64 00:55:14.614468 progress 60 % (31 MB)
65 00:55:14.630243 progress 65 % (34 MB)
66 00:55:14.645657 progress 70 % (36 MB)
67 00:55:14.661505 progress 75 % (39 MB)
68 00:55:14.676324 progress 80 % (41 MB)
69 00:55:14.691572 progress 85 % (44 MB)
70 00:55:14.706866 progress 90 % (47 MB)
71 00:55:14.722548 progress 95 % (49 MB)
72 00:55:14.738084 progress 100 % (52 MB)
73 00:55:14.738355 52 MB downloaded in 0.31 s (166.34 MB/s)
74 00:55:14.738562 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:55:14.738835 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:55:14.738923 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:55:14.739013 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:55:14.739149 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:55:14.739220 saving as /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/dtb/mt8192-asurada-spherion-r0.dtb
81 00:55:14.739274 total size: 47258 (0 MB)
82 00:55:14.739328 No compression specified
83 00:55:14.740382 progress 69 % (0 MB)
84 00:55:14.740649 progress 100 % (0 MB)
85 00:55:14.740879 0 MB downloaded in 0.00 s (28.15 MB/s)
86 00:55:14.741011 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:55:14.741234 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:55:14.741316 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:55:14.741398 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:55:14.741505 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-24-g0315de64ea248/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:55:14.741589 saving as /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/modules/modules.tar
93 00:55:14.741644 total size: 8617404 (8 MB)
94 00:55:14.741698 Using unxz to decompress xz
95 00:55:14.743266 progress 0 % (0 MB)
96 00:55:14.764515 progress 5 % (0 MB)
97 00:55:14.794736 progress 10 % (0 MB)
98 00:55:14.825515 progress 15 % (1 MB)
99 00:55:14.852799 progress 20 % (1 MB)
100 00:55:14.881345 progress 25 % (2 MB)
101 00:55:14.909983 progress 30 % (2 MB)
102 00:55:14.938719 progress 35 % (2 MB)
103 00:55:14.966023 progress 40 % (3 MB)
104 00:55:14.992211 progress 45 % (3 MB)
105 00:55:15.020017 progress 50 % (4 MB)
106 00:55:15.048544 progress 55 % (4 MB)
107 00:55:15.076249 progress 60 % (4 MB)
108 00:55:15.103512 progress 65 % (5 MB)
109 00:55:15.133307 progress 70 % (5 MB)
110 00:55:15.159639 progress 75 % (6 MB)
111 00:55:15.189593 progress 80 % (6 MB)
112 00:55:15.215601 progress 85 % (7 MB)
113 00:55:15.243134 progress 90 % (7 MB)
114 00:55:15.271211 progress 95 % (7 MB)
115 00:55:15.298490 progress 100 % (8 MB)
116 00:55:15.304932 8 MB downloaded in 0.56 s (14.59 MB/s)
117 00:55:15.305214 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:55:15.305656 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:55:15.305807 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:55:15.305951 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:55:15.306085 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:55:15.306224 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:55:15.306454 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp
125 00:55:15.306642 makedir: /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin
126 00:55:15.306798 makedir: /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/tests
127 00:55:15.306955 makedir: /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/results
128 00:55:15.307100 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-add-keys
129 00:55:15.307307 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-add-sources
130 00:55:15.307512 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-background-process-start
131 00:55:15.307710 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-background-process-stop
132 00:55:15.307914 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-common-functions
133 00:55:15.308107 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-echo-ipv4
134 00:55:15.308305 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-install-packages
135 00:55:15.308501 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-installed-packages
136 00:55:15.308690 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-os-build
137 00:55:15.308882 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-probe-channel
138 00:55:15.309078 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-probe-ip
139 00:55:15.309281 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-target-ip
140 00:55:15.309473 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-target-mac
141 00:55:15.309675 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-target-storage
142 00:55:15.309870 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-test-case
143 00:55:15.310064 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-test-event
144 00:55:15.310257 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-test-feedback
145 00:55:15.310455 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-test-raise
146 00:55:15.310663 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-test-reference
147 00:55:15.310855 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-test-runner
148 00:55:15.311044 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-test-set
149 00:55:15.311243 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-test-shell
150 00:55:15.311438 Updating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-install-packages (oe)
151 00:55:15.311674 Updating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/bin/lava-installed-packages (oe)
152 00:55:15.311863 Creating /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/environment
153 00:55:15.312016 LAVA metadata
154 00:55:15.312141 - LAVA_JOB_ID=14368569
155 00:55:15.312253 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:55:15.312421 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:55:15.312541 skipped lava-vland-overlay
158 00:55:15.312675 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:55:15.312810 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:55:15.312929 skipped lava-multinode-overlay
161 00:55:15.313062 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:55:15.313196 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:55:15.313319 Loading test definitions
164 00:55:15.313468 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:55:15.313588 Using /lava-14368569 at stage 0
166 00:55:15.314108 uuid=14368569_1.5.2.3.1 testdef=None
167 00:55:15.314248 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:55:15.314393 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:55:15.315171 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:55:15.315579 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:55:15.316603 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:55:15.317028 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:55:15.318042 runner path: /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/0/tests/0_v4l2-compliance-uvc test_uuid 14368569_1.5.2.3.1
176 00:55:15.318269 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:55:15.318667 Creating lava-test-runner.conf files
179 00:55:15.318776 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14368569/lava-overlay-vlw95qvp/lava-14368569/0 for stage 0
180 00:55:15.318917 - 0_v4l2-compliance-uvc
181 00:55:15.319076 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:55:15.319217 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:55:15.329431 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:55:15.329640 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:55:15.329791 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:55:15.329943 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:55:15.330094 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:55:16.251928 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:55:16.252116 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 00:55:16.252228 extracting modules file /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14368569/extract-overlay-ramdisk-771z_h7d/ramdisk
191 00:55:16.530982 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:55:16.531128 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 00:55:16.531206 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368569/compress-overlay-s9mpdogc/overlay-1.5.2.4.tar.gz to ramdisk
194 00:55:16.531275 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14368569/compress-overlay-s9mpdogc/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14368569/extract-overlay-ramdisk-771z_h7d/ramdisk
195 00:55:16.538643 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:55:16.538761 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 00:55:16.538843 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:55:16.538933 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 00:55:16.539003 Building ramdisk /var/lib/lava/dispatcher/tmp/14368569/extract-overlay-ramdisk-771z_h7d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14368569/extract-overlay-ramdisk-771z_h7d/ramdisk
200 00:55:17.237670 >> 275951 blocks
201 00:55:21.761807 rename /var/lib/lava/dispatcher/tmp/14368569/extract-overlay-ramdisk-771z_h7d/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/ramdisk/ramdisk.cpio.gz
202 00:55:21.762030 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 00:55:21.762160 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 00:55:21.762277 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 00:55:21.762391 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/kernel/Image']
206 00:55:37.233421 Returned 0 in 15 seconds
207 00:55:37.333956 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/kernel/image.itb
208 00:55:38.022199 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:55:38.022366 output: Created: Sun Jun 16 01:55:37 2024
210 00:55:38.022466 output: Image 0 (kernel-1)
211 00:55:38.022556 output: Description:
212 00:55:38.022643 output: Created: Sun Jun 16 01:55:37 2024
213 00:55:38.022735 output: Type: Kernel Image
214 00:55:38.022824 output: Compression: lzma compressed
215 00:55:38.022922 output: Data Size: 13125045 Bytes = 12817.43 KiB = 12.52 MiB
216 00:55:38.023008 output: Architecture: AArch64
217 00:55:38.023098 output: OS: Linux
218 00:55:38.023195 output: Load Address: 0x00000000
219 00:55:38.023285 output: Entry Point: 0x00000000
220 00:55:38.023382 output: Hash algo: crc32
221 00:55:38.023506 output: Hash value: f6f06660
222 00:55:38.023614 output: Image 1 (fdt-1)
223 00:55:38.023698 output: Description: mt8192-asurada-spherion-r0
224 00:55:38.023783 output: Created: Sun Jun 16 01:55:37 2024
225 00:55:38.023873 output: Type: Flat Device Tree
226 00:55:38.023956 output: Compression: uncompressed
227 00:55:38.024037 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:55:38.024124 output: Architecture: AArch64
229 00:55:38.024202 output: Hash algo: crc32
230 00:55:38.024279 output: Hash value: 0f8e4d2e
231 00:55:38.024365 output: Image 2 (ramdisk-1)
232 00:55:38.024443 output: Description: unavailable
233 00:55:38.024522 output: Created: Sun Jun 16 01:55:37 2024
234 00:55:38.024610 output: Type: RAMDisk Image
235 00:55:38.024691 output: Compression: uncompressed
236 00:55:38.024771 output: Data Size: 41210746 Bytes = 40244.87 KiB = 39.30 MiB
237 00:55:38.024857 output: Architecture: AArch64
238 00:55:38.024935 output: OS: Linux
239 00:55:38.025013 output: Load Address: unavailable
240 00:55:38.025097 output: Entry Point: unavailable
241 00:55:38.025175 output: Hash algo: crc32
242 00:55:38.025252 output: Hash value: 02be0aa1
243 00:55:38.025335 output: Default Configuration: 'conf-1'
244 00:55:38.025414 output: Configuration 0 (conf-1)
245 00:55:38.025498 output: Description: mt8192-asurada-spherion-r0
246 00:55:38.025587 output: Kernel: kernel-1
247 00:55:38.025668 output: Init Ramdisk: ramdisk-1
248 00:55:38.025753 output: FDT: fdt-1
249 00:55:38.025834 output: Loadables: kernel-1
250 00:55:38.025912 output:
251 00:55:38.026109 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 00:55:38.026239 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 00:55:38.026369 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 00:55:38.026498 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 00:55:38.026601 No LXC device requested
256 00:55:38.026722 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:55:38.026845 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 00:55:38.026965 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:55:38.027060 Checking files for TFTP limit of 4294967296 bytes.
260 00:55:38.027729 end: 1 tftp-deploy (duration 00:00:24) [common]
261 00:55:38.027873 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:55:38.027991 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:55:38.028148 substitutions:
264 00:55:38.028243 - {DTB}: 14368569/tftp-deploy-07bfviip/dtb/mt8192-asurada-spherion-r0.dtb
265 00:55:38.028344 - {INITRD}: 14368569/tftp-deploy-07bfviip/ramdisk/ramdisk.cpio.gz
266 00:55:38.028433 - {KERNEL}: 14368569/tftp-deploy-07bfviip/kernel/Image
267 00:55:38.028515 - {LAVA_MAC}: None
268 00:55:38.028602 - {PRESEED_CONFIG}: None
269 00:55:38.028687 - {PRESEED_LOCAL}: None
270 00:55:38.028770 - {RAMDISK}: 14368569/tftp-deploy-07bfviip/ramdisk/ramdisk.cpio.gz
271 00:55:38.028869 - {ROOT_PART}: None
272 00:55:38.028953 - {ROOT}: None
273 00:55:38.029035 - {SERVER_IP}: 192.168.201.1
274 00:55:38.029124 - {TEE}: None
275 00:55:38.029206 Parsed boot commands:
276 00:55:38.029291 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:55:38.029538 Parsed boot commands: tftpboot 192.168.201.1 14368569/tftp-deploy-07bfviip/kernel/image.itb 14368569/tftp-deploy-07bfviip/kernel/cmdline
278 00:55:38.029674 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:55:38.029805 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:55:38.029931 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:55:38.030058 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:55:38.030154 Not connected, no need to disconnect.
283 00:55:38.030269 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:55:38.030386 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:55:38.030488 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 00:55:38.034632 Setting prompt string to ['lava-test: # ']
287 00:55:38.035049 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:55:38.035209 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:55:38.035349 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:55:38.035481 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:55:38.035756 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 00:55:47.167324 >> Command sent successfully.
293 00:55:47.170527 Returned 0 in 9 seconds
294 00:55:47.270870 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 00:55:47.271155 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 00:55:47.271254 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 00:55:47.271342 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:55:47.271401 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:55:47.271462 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:55:47.271883 [Enter `^Ec?' for help]
302 00:55:48.779362
303 00:55:48.779500
304 00:55:48.779589 F0: 102B 0000
305 00:55:48.779676
306 00:55:48.779757 F3: 1001 0000 [0200]
307 00:55:48.783486
308 00:55:48.783597 F3: 1001 0000
309 00:55:48.783695
310 00:55:48.783788 F7: 102D 0000
311 00:55:48.783878
312 00:55:48.787012 F1: 0000 0000
313 00:55:48.787127
314 00:55:48.787229 V0: 0000 0000 [0001]
315 00:55:48.787292
316 00:55:48.787347 00: 0007 8000
317 00:55:48.787403
318 00:55:48.790493 01: 0000 0000
319 00:55:48.790599
320 00:55:48.790662 BP: 0C00 0209 [0000]
321 00:55:48.790737
322 00:55:48.794594 G0: 1182 0000
323 00:55:48.794674
324 00:55:48.794733 EC: 0000 0021 [4000]
325 00:55:48.794788
326 00:55:48.797933 S7: 0000 0000 [0000]
327 00:55:48.798021
328 00:55:48.798083 CC: 0000 0000 [0001]
329 00:55:48.798138
330 00:55:48.801251 T0: 0000 0040 [010F]
331 00:55:48.801333
332 00:55:48.801392 Jump to BL
333 00:55:48.801484
334 00:55:48.826945
335 00:55:48.827106
336 00:55:48.834139 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 00:55:48.838295 ARM64: Exception handlers installed.
338 00:55:48.842006 ARM64: Testing exception
339 00:55:48.842181 ARM64: Done test exception
340 00:55:48.849277 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 00:55:48.859967 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 00:55:48.866834 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 00:55:48.877073 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 00:55:48.883900 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 00:55:48.894130 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 00:55:48.904483 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 00:55:48.910553 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 00:55:48.929228 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 00:55:48.932679 WDT: Last reset was cold boot
350 00:55:48.936161 SPI1(PAD0) initialized at 2873684 Hz
351 00:55:48.939328 SPI5(PAD0) initialized at 992727 Hz
352 00:55:48.942512 VBOOT: Loading verstage.
353 00:55:48.949172 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 00:55:48.952551 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 00:55:48.955817 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 00:55:48.959001 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 00:55:48.966498 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 00:55:48.973431 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 00:55:48.984408 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 00:55:48.984539
361 00:55:48.984626
362 00:55:48.994342 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 00:55:48.997794 ARM64: Exception handlers installed.
364 00:55:49.001193 ARM64: Testing exception
365 00:55:49.001271 ARM64: Done test exception
366 00:55:49.007933 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 00:55:49.011250 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 00:55:49.025245 Probing TPM: . done!
369 00:55:49.025328 TPM ready after 0 ms
370 00:55:49.032029 Connected to device vid:did:rid of 1ae0:0028:00
371 00:55:49.041955 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 00:55:49.079406 Initialized TPM device CR50 revision 0
373 00:55:49.090630 tlcl_send_startup: Startup return code is 0
374 00:55:49.090716 TPM: setup succeeded
375 00:55:49.102119 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 00:55:49.111072 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 00:55:49.121182 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 00:55:49.130087 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 00:55:49.133356 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 00:55:49.136737 in-header: 03 07 00 00 08 00 00 00
381 00:55:49.139985 in-data: aa e4 47 04 13 02 00 00
382 00:55:49.143183 Chrome EC: UHEPI supported
383 00:55:49.149876 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 00:55:49.153950 in-header: 03 a9 00 00 08 00 00 00
385 00:55:49.156631 in-data: 84 60 60 08 00 00 00 00
386 00:55:49.156706 Phase 1
387 00:55:49.159989 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 00:55:49.166733 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 00:55:49.173746 VB2:vb2_check_recovery() Recovery was requested manually
390 00:55:49.177259 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 00:55:49.180068 Recovery requested (1009000e)
392 00:55:49.188730 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 00:55:49.193952 tlcl_extend: response is 0
394 00:55:49.202059 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 00:55:49.207472 tlcl_extend: response is 0
396 00:55:49.214004 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 00:55:49.236018 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 00:55:49.242043 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 00:55:49.242131
400 00:55:49.242189
401 00:55:49.252802 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 00:55:49.256185 ARM64: Exception handlers installed.
403 00:55:49.256261 ARM64: Testing exception
404 00:55:49.259523 ARM64: Done test exception
405 00:55:49.280359 pmic_efuse_setting: Set efuses in 11 msecs
406 00:55:49.284122 pmwrap_interface_init: Select PMIF_VLD_RDY
407 00:55:49.290636 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 00:55:49.294260 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 00:55:49.301004 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 00:55:49.303916 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 00:55:49.307148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 00:55:49.313919 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 00:55:49.317346 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 00:55:49.324168 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 00:55:49.327548 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 00:55:49.333920 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 00:55:49.337435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 00:55:49.340613 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 00:55:49.347332 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 00:55:49.354009 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 00:55:49.357291 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 00:55:49.363990 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 00:55:49.370954 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 00:55:49.374287 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 00:55:49.381275 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 00:55:49.387437 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 00:55:49.390754 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 00:55:49.397539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 00:55:49.404687 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 00:55:49.407782 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 00:55:49.414402 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 00:55:49.421312 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 00:55:49.424464 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 00:55:49.430834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 00:55:49.434331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 00:55:49.437502 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 00:55:49.444493 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 00:55:49.447712 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 00:55:49.454203 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 00:55:49.458040 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 00:55:49.464827 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 00:55:49.468080 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 00:55:49.474853 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 00:55:49.478223 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 00:55:49.484990 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 00:55:49.488378 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 00:55:49.491754 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 00:55:49.498258 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 00:55:49.501705 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 00:55:49.505085 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 00:55:49.511717 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 00:55:49.515248 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 00:55:49.518460 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 00:55:49.521774 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 00:55:49.528533 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 00:55:49.532025 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 00:55:49.535276 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 00:55:49.541872 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 00:55:49.552072 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 00:55:49.555595 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 00:55:49.565250 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 00:55:49.572150 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 00:55:49.578430 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 00:55:49.581868 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:55:49.585205 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 00:55:49.593431 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x25
467 00:55:49.600239 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 00:55:49.603480 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 00:55:49.606846 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 00:55:49.617789 [RTC]rtc_get_frequency_meter,154: input=15, output=760
471 00:55:49.627315 [RTC]rtc_get_frequency_meter,154: input=23, output=943
472 00:55:49.636768 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 00:55:49.646353 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 00:55:49.655805 [RTC]rtc_get_frequency_meter,154: input=16, output=780
475 00:55:49.665431 [RTC]rtc_get_frequency_meter,154: input=16, output=783
476 00:55:49.675017 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 00:55:49.677867 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 00:55:49.685190 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 00:55:49.689002 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 00:55:49.691901 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 00:55:49.698821 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 00:55:49.701920 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 00:55:49.705254 ADC[4]: Raw value=906203 ID=7
484 00:55:49.705369 ADC[3]: Raw value=213441 ID=1
485 00:55:49.708584 RAM Code: 0x71
486 00:55:49.712022 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 00:55:49.718592 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 00:55:49.725487 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 00:55:49.732247 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 00:55:49.735573 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 00:55:49.738962 in-header: 03 07 00 00 08 00 00 00
492 00:55:49.742310 in-data: aa e4 47 04 13 02 00 00
493 00:55:49.745719 Chrome EC: UHEPI supported
494 00:55:49.752627 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 00:55:49.755986 in-header: 03 a9 00 00 08 00 00 00
496 00:55:49.759196 in-data: 84 60 60 08 00 00 00 00
497 00:55:49.762253 MRC: failed to locate region type 0.
498 00:55:49.768868 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 00:55:49.772422 DRAM-K: Running full calibration
500 00:55:49.778693 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 00:55:49.778787 header.status = 0x0
502 00:55:49.782060 header.version = 0x6 (expected: 0x6)
503 00:55:49.785479 header.size = 0xd00 (expected: 0xd00)
504 00:55:49.788946 header.flags = 0x0
505 00:55:49.795648 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 00:55:49.811367 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 00:55:49.818048 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 00:55:49.821737 dram_init: ddr_geometry: 2
509 00:55:49.821825 [EMI] MDL number = 2
510 00:55:49.824898 [EMI] Get MDL freq = 0
511 00:55:49.828018 dram_init: ddr_type: 0
512 00:55:49.828096 is_discrete_lpddr4: 1
513 00:55:49.831446 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 00:55:49.831523
515 00:55:49.831582
516 00:55:49.835079 [Bian_co] ETT version 0.0.0.1
517 00:55:49.841298 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 00:55:49.841409
519 00:55:49.844784 dramc_set_vcore_voltage set vcore to 650000
520 00:55:49.848106 Read voltage for 800, 4
521 00:55:49.848184 Vio18 = 0
522 00:55:49.848243 Vcore = 650000
523 00:55:49.848298 Vdram = 0
524 00:55:49.851414 Vddq = 0
525 00:55:49.851493 Vmddr = 0
526 00:55:49.854808 dram_init: config_dvfs: 1
527 00:55:49.858180 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 00:55:49.864984 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 00:55:49.868305 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 00:55:49.871697 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 00:55:49.874917 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 00:55:49.877989 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 00:55:49.881436 MEM_TYPE=3, freq_sel=18
534 00:55:49.885141 sv_algorithm_assistance_LP4_1600
535 00:55:49.888732 ============ PULL DRAM RESETB DOWN ============
536 00:55:49.892322 ========== PULL DRAM RESETB DOWN end =========
537 00:55:49.896454 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 00:55:49.899745 ===================================
539 00:55:49.903178 LPDDR4 DRAM CONFIGURATION
540 00:55:49.907249 ===================================
541 00:55:49.907333 EX_ROW_EN[0] = 0x0
542 00:55:49.911279 EX_ROW_EN[1] = 0x0
543 00:55:49.911360 LP4Y_EN = 0x0
544 00:55:49.914649 WORK_FSP = 0x0
545 00:55:49.914727 WL = 0x2
546 00:55:49.918722 RL = 0x2
547 00:55:49.918803 BL = 0x2
548 00:55:49.922110 RPST = 0x0
549 00:55:49.922190 RD_PRE = 0x0
550 00:55:49.925397 WR_PRE = 0x1
551 00:55:49.925497 WR_PST = 0x0
552 00:55:49.928636 DBI_WR = 0x0
553 00:55:49.928714 DBI_RD = 0x0
554 00:55:49.932469 OTF = 0x1
555 00:55:49.935150 ===================================
556 00:55:49.938915 ===================================
557 00:55:49.938996 ANA top config
558 00:55:49.941945 ===================================
559 00:55:49.945331 DLL_ASYNC_EN = 0
560 00:55:49.948790 ALL_SLAVE_EN = 1
561 00:55:49.948870 NEW_RANK_MODE = 1
562 00:55:49.951918 DLL_IDLE_MODE = 1
563 00:55:49.955153 LP45_APHY_COMB_EN = 1
564 00:55:49.958886 TX_ODT_DIS = 1
565 00:55:49.962061 NEW_8X_MODE = 1
566 00:55:49.965535 ===================================
567 00:55:49.965656 ===================================
568 00:55:49.968777 data_rate = 1600
569 00:55:49.972078 CKR = 1
570 00:55:49.975556 DQ_P2S_RATIO = 8
571 00:55:49.979017 ===================================
572 00:55:49.982264 CA_P2S_RATIO = 8
573 00:55:49.985557 DQ_CA_OPEN = 0
574 00:55:49.985639 DQ_SEMI_OPEN = 0
575 00:55:49.988835 CA_SEMI_OPEN = 0
576 00:55:49.992071 CA_FULL_RATE = 0
577 00:55:49.995753 DQ_CKDIV4_EN = 1
578 00:55:49.999002 CA_CKDIV4_EN = 1
579 00:55:50.002104 CA_PREDIV_EN = 0
580 00:55:50.002181 PH8_DLY = 0
581 00:55:50.005389 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 00:55:50.008730 DQ_AAMCK_DIV = 4
583 00:55:50.012867 CA_AAMCK_DIV = 4
584 00:55:50.015518 CA_ADMCK_DIV = 4
585 00:55:50.018969 DQ_TRACK_CA_EN = 0
586 00:55:50.019046 CA_PICK = 800
587 00:55:50.022437 CA_MCKIO = 800
588 00:55:50.025720 MCKIO_SEMI = 0
589 00:55:50.028857 PLL_FREQ = 3068
590 00:55:50.032159 DQ_UI_PI_RATIO = 32
591 00:55:50.035487 CA_UI_PI_RATIO = 0
592 00:55:50.039291 ===================================
593 00:55:50.042643 ===================================
594 00:55:50.042726 memory_type:LPDDR4
595 00:55:50.045479 GP_NUM : 10
596 00:55:50.048897 SRAM_EN : 1
597 00:55:50.048976 MD32_EN : 0
598 00:55:50.052312 ===================================
599 00:55:50.055608 [ANA_INIT] >>>>>>>>>>>>>>
600 00:55:50.059040 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 00:55:50.062326 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 00:55:50.065620 ===================================
603 00:55:50.068754 data_rate = 1600,PCW = 0X7600
604 00:55:50.072083 ===================================
605 00:55:50.075834 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 00:55:50.079044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:55:50.085804 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 00:55:50.089138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 00:55:50.092343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:55:50.095522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 00:55:50.098999 [ANA_INIT] flow start
612 00:55:50.102018 [ANA_INIT] PLL >>>>>>>>
613 00:55:50.102097 [ANA_INIT] PLL <<<<<<<<
614 00:55:50.105723 [ANA_INIT] MIDPI >>>>>>>>
615 00:55:50.108990 [ANA_INIT] MIDPI <<<<<<<<
616 00:55:50.112580 [ANA_INIT] DLL >>>>>>>>
617 00:55:50.112658 [ANA_INIT] flow end
618 00:55:50.115816 ============ LP4 DIFF to SE enter ============
619 00:55:50.122506 ============ LP4 DIFF to SE exit ============
620 00:55:50.122587 [ANA_INIT] <<<<<<<<<<<<<
621 00:55:50.125997 [Flow] Enable top DCM control >>>>>
622 00:55:50.128642 [Flow] Enable top DCM control <<<<<
623 00:55:50.132037 Enable DLL master slave shuffle
624 00:55:50.138867 ==============================================================
625 00:55:50.138946 Gating Mode config
626 00:55:50.145505 ==============================================================
627 00:55:50.145603 Config description:
628 00:55:50.156091 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 00:55:50.162504 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 00:55:50.169268 SELPH_MODE 0: By rank 1: By Phase
631 00:55:50.172734 ==============================================================
632 00:55:50.176157 GAT_TRACK_EN = 1
633 00:55:50.179474 RX_GATING_MODE = 2
634 00:55:50.182685 RX_GATING_TRACK_MODE = 2
635 00:55:50.186082 SELPH_MODE = 1
636 00:55:50.189475 PICG_EARLY_EN = 1
637 00:55:50.192852 VALID_LAT_VALUE = 1
638 00:55:50.196031 ==============================================================
639 00:55:50.199314 Enter into Gating configuration >>>>
640 00:55:50.202466 Exit from Gating configuration <<<<
641 00:55:50.206110 Enter into DVFS_PRE_config >>>>>
642 00:55:50.219446 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 00:55:50.222881 Exit from DVFS_PRE_config <<<<<
644 00:55:50.226248 Enter into PICG configuration >>>>
645 00:55:50.226325 Exit from PICG configuration <<<<
646 00:55:50.229383 [RX_INPUT] configuration >>>>>
647 00:55:50.233031 [RX_INPUT] configuration <<<<<
648 00:55:50.239462 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 00:55:50.243057 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 00:55:50.249665 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 00:55:50.256552 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 00:55:50.263273 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 00:55:50.269909 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 00:55:50.273298 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 00:55:50.276673 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 00:55:50.280056 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 00:55:50.286899 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 00:55:50.289659 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 00:55:50.293143 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 00:55:50.296700 ===================================
661 00:55:50.300093 LPDDR4 DRAM CONFIGURATION
662 00:55:50.303332 ===================================
663 00:55:50.303411 EX_ROW_EN[0] = 0x0
664 00:55:50.306825 EX_ROW_EN[1] = 0x0
665 00:55:50.306915 LP4Y_EN = 0x0
666 00:55:50.310100 WORK_FSP = 0x0
667 00:55:50.313500 WL = 0x2
668 00:55:50.313650 RL = 0x2
669 00:55:50.316820 BL = 0x2
670 00:55:50.316893 RPST = 0x0
671 00:55:50.320166 RD_PRE = 0x0
672 00:55:50.320243 WR_PRE = 0x1
673 00:55:50.323342 WR_PST = 0x0
674 00:55:50.323418 DBI_WR = 0x0
675 00:55:50.326626 DBI_RD = 0x0
676 00:55:50.326708 OTF = 0x1
677 00:55:50.329976 ===================================
678 00:55:50.333235 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 00:55:50.336974 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 00:55:50.343642 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 00:55:50.347025 ===================================
682 00:55:50.350245 LPDDR4 DRAM CONFIGURATION
683 00:55:50.353516 ===================================
684 00:55:50.353615 EX_ROW_EN[0] = 0x10
685 00:55:50.356809 EX_ROW_EN[1] = 0x0
686 00:55:50.356891 LP4Y_EN = 0x0
687 00:55:50.360500 WORK_FSP = 0x0
688 00:55:50.360581 WL = 0x2
689 00:55:50.363394 RL = 0x2
690 00:55:50.363475 BL = 0x2
691 00:55:50.366941 RPST = 0x0
692 00:55:50.367025 RD_PRE = 0x0
693 00:55:50.370302 WR_PRE = 0x1
694 00:55:50.370378 WR_PST = 0x0
695 00:55:50.373314 DBI_WR = 0x0
696 00:55:50.373395 DBI_RD = 0x0
697 00:55:50.376662 OTF = 0x1
698 00:55:50.380276 ===================================
699 00:55:50.386924 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 00:55:50.390503 nWR fixed to 40
701 00:55:50.393959 [ModeRegInit_LP4] CH0 RK0
702 00:55:50.394048 [ModeRegInit_LP4] CH0 RK1
703 00:55:50.396725 [ModeRegInit_LP4] CH1 RK0
704 00:55:50.400111 [ModeRegInit_LP4] CH1 RK1
705 00:55:50.400213 match AC timing 13
706 00:55:50.406878 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 00:55:50.410321 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 00:55:50.413788 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 00:55:50.420043 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 00:55:50.423495 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 00:55:50.423577 [EMI DOE] emi_dcm 0
712 00:55:50.430026 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 00:55:50.430114 ==
714 00:55:50.433959 Dram Type= 6, Freq= 0, CH_0, rank 0
715 00:55:50.437297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 00:55:50.437387 ==
717 00:55:50.443560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 00:55:50.447019 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 00:55:50.457772 [CA 0] Center 36 (6~67) winsize 62
720 00:55:50.460533 [CA 1] Center 36 (6~67) winsize 62
721 00:55:50.463903 [CA 2] Center 34 (4~65) winsize 62
722 00:55:50.468073 [CA 3] Center 33 (3~64) winsize 62
723 00:55:50.470778 [CA 4] Center 33 (3~63) winsize 61
724 00:55:50.474821 [CA 5] Center 32 (3~62) winsize 60
725 00:55:50.475029
726 00:55:50.478853 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 00:55:50.479012
728 00:55:50.481848 [CATrainingPosCal] consider 1 rank data
729 00:55:50.485491 u2DelayCellTimex100 = 270/100 ps
730 00:55:50.488994 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 00:55:50.491804 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 00:55:50.495611 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 00:55:50.498433 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 00:55:50.502343 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
735 00:55:50.505135 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 00:55:50.505267
737 00:55:50.512446 CA PerBit enable=1, Macro0, CA PI delay=32
738 00:55:50.512591
739 00:55:50.512680 [CBTSetCACLKResult] CA Dly = 32
740 00:55:50.515732 CS Dly: 5 (0~36)
741 00:55:50.515842 ==
742 00:55:50.519144 Dram Type= 6, Freq= 0, CH_0, rank 1
743 00:55:50.522608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 00:55:50.522733 ==
745 00:55:50.528747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 00:55:50.535628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 00:55:50.543910 [CA 0] Center 36 (6~67) winsize 62
748 00:55:50.546690 [CA 1] Center 36 (6~67) winsize 62
749 00:55:50.550129 [CA 2] Center 33 (3~64) winsize 62
750 00:55:50.553581 [CA 3] Center 33 (3~64) winsize 62
751 00:55:50.556916 [CA 4] Center 33 (3~63) winsize 61
752 00:55:50.560272 [CA 5] Center 32 (2~63) winsize 62
753 00:55:50.560356
754 00:55:50.563599 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 00:55:50.563679
756 00:55:50.567245 [CATrainingPosCal] consider 2 rank data
757 00:55:50.570242 u2DelayCellTimex100 = 270/100 ps
758 00:55:50.573645 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 00:55:50.577018 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 00:55:50.583740 CA2 delay=34 (4~64),Diff = 2 PI (14 cell)
761 00:55:50.587051 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 00:55:50.590511 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 00:55:50.593898 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 00:55:50.594002
765 00:55:50.597259 CA PerBit enable=1, Macro0, CA PI delay=32
766 00:55:50.597349
767 00:55:50.600444 [CBTSetCACLKResult] CA Dly = 32
768 00:55:50.600526 CS Dly: 5 (0~36)
769 00:55:50.600587
770 00:55:50.604084 ----->DramcWriteLeveling(PI) begin...
771 00:55:50.604167 ==
772 00:55:50.607181 Dram Type= 6, Freq= 0, CH_0, rank 0
773 00:55:50.614103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 00:55:50.614199 ==
775 00:55:50.617455 Write leveling (Byte 0): 31 => 31
776 00:55:50.620630 Write leveling (Byte 1): 31 => 31
777 00:55:50.620711 DramcWriteLeveling(PI) end<-----
778 00:55:50.623600
779 00:55:50.623679 ==
780 00:55:50.627237 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:55:50.630343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 00:55:50.630436 ==
783 00:55:50.633637 [Gating] SW mode calibration
784 00:55:50.640331 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 00:55:50.643702 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 00:55:50.650732 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 00:55:50.653748 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 00:55:50.657167 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 00:55:50.663923 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 00:55:50.667415 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:55:50.670844 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:55:50.674060 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:55:50.680819 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:55:50.684440 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:55:50.687604 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:55:50.694231 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:55:50.697515 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:55:50.701003 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:55:50.707567 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:55:50.710901 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:55:50.714657 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:55:50.721244 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:55:50.724158 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 00:55:50.727462 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 00:55:50.734473 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:55:50.737652 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:55:50.741108 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:55:50.744465 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:55:50.751377 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:55:50.754797 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:55:50.758039 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 00:55:50.764502 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
813 00:55:50.767909 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 00:55:50.771496 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:55:50.777759 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:55:50.781130 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:55:50.784357 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:55:50.791301 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 00:55:50.794604 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 00:55:50.798220 0 10 8 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (1 0)
821 00:55:50.804878 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:55:50.807892 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:55:50.811777 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:55:50.815166 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:55:50.821879 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:55:50.824682 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:55:50.828160 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
828 00:55:50.834574 0 11 8 | B1->B0 | 2e2e 3f3f | 0 1 | (0 0) (1 1)
829 00:55:50.838627 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 00:55:50.841201 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:55:50.848107 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:55:50.851251 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:55:50.854874 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:55:50.861729 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:55:50.864482 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 00:55:50.867826 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 00:55:50.874827 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:55:50.878343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:55:50.881739 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:55:50.887831 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:55:50.891232 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:55:50.894741 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:55:50.901650 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:55:50.904504 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:55:50.907806 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:55:50.914853 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:55:50.918008 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:55:50.921396 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:55:50.924798 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:55:50.931543 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:55:50.934584 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 00:55:50.938272 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 00:55:50.941491 Total UI for P1: 0, mck2ui 16
854 00:55:50.944702 best dqsien dly found for B0: ( 0, 14, 4)
855 00:55:50.951380 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 00:55:50.954759 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 00:55:50.958096 Total UI for P1: 0, mck2ui 16
858 00:55:50.961366 best dqsien dly found for B1: ( 0, 14, 10)
859 00:55:50.964979 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
860 00:55:50.968210 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 00:55:50.968280
862 00:55:50.971637 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
863 00:55:50.974507 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 00:55:50.978148 [Gating] SW calibration Done
865 00:55:50.978228 ==
866 00:55:50.981589 Dram Type= 6, Freq= 0, CH_0, rank 0
867 00:55:50.985200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 00:55:50.987963 ==
869 00:55:50.988043 RX Vref Scan: 0
870 00:55:50.988122
871 00:55:50.991369 RX Vref 0 -> 0, step: 1
872 00:55:50.991448
873 00:55:50.994881 RX Delay -130 -> 252, step: 16
874 00:55:50.998305 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
875 00:55:51.001645 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
876 00:55:51.005054 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
877 00:55:51.008487 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
878 00:55:51.011880 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
879 00:55:51.018614 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
880 00:55:51.021411 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
881 00:55:51.024820 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
882 00:55:51.028155 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
883 00:55:51.032012 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
884 00:55:51.038315 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
885 00:55:51.042026 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
886 00:55:51.045023 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
887 00:55:51.048562 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
888 00:55:51.051528 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
889 00:55:51.058521 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
890 00:55:51.058600 ==
891 00:55:51.061485 Dram Type= 6, Freq= 0, CH_0, rank 0
892 00:55:51.064987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 00:55:51.065120 ==
894 00:55:51.065195 DQS Delay:
895 00:55:51.068474 DQS0 = 0, DQS1 = 0
896 00:55:51.068572 DQM Delay:
897 00:55:51.071944 DQM0 = 90, DQM1 = 81
898 00:55:51.072041 DQ Delay:
899 00:55:51.075347 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
900 00:55:51.078021 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
901 00:55:51.081624 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
902 00:55:51.084718 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
903 00:55:51.084840
904 00:55:51.084901
905 00:55:51.084955 ==
906 00:55:51.088508 Dram Type= 6, Freq= 0, CH_0, rank 0
907 00:55:51.091834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 00:55:51.091927 ==
909 00:55:51.095194
910 00:55:51.095277
911 00:55:51.095348 TX Vref Scan disable
912 00:55:51.098432 == TX Byte 0 ==
913 00:55:51.101992 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
914 00:55:51.104664 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
915 00:55:51.108115 == TX Byte 1 ==
916 00:55:51.111737 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
917 00:55:51.115203 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
918 00:55:51.115282 ==
919 00:55:51.118574 Dram Type= 6, Freq= 0, CH_0, rank 0
920 00:55:51.125207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 00:55:51.125292 ==
922 00:55:51.137078 TX Vref=22, minBit 7, minWin=27, winSum=447
923 00:55:51.139905 TX Vref=24, minBit 11, minWin=27, winSum=450
924 00:55:51.143743 TX Vref=26, minBit 0, minWin=28, winSum=456
925 00:55:51.146928 TX Vref=28, minBit 9, minWin=27, winSum=457
926 00:55:51.150215 TX Vref=30, minBit 8, minWin=28, winSum=456
927 00:55:51.153578 TX Vref=32, minBit 0, minWin=28, winSum=455
928 00:55:51.160210 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 26
929 00:55:51.160307
930 00:55:51.163480 Final TX Range 1 Vref 26
931 00:55:51.163573
932 00:55:51.163655 ==
933 00:55:51.167046 Dram Type= 6, Freq= 0, CH_0, rank 0
934 00:55:51.170533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 00:55:51.170631 ==
936 00:55:51.170713
937 00:55:51.170791
938 00:55:51.173537 TX Vref Scan disable
939 00:55:51.177113 == TX Byte 0 ==
940 00:55:51.180123 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
941 00:55:51.183893 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
942 00:55:51.187390 == TX Byte 1 ==
943 00:55:51.190615 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
944 00:55:51.193791 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
945 00:55:51.193957
946 00:55:51.196834 [DATLAT]
947 00:55:51.196952 Freq=800, CH0 RK0
948 00:55:51.197045
949 00:55:51.200624 DATLAT Default: 0xa
950 00:55:51.200700 0, 0xFFFF, sum = 0
951 00:55:51.203656 1, 0xFFFF, sum = 0
952 00:55:51.203748 2, 0xFFFF, sum = 0
953 00:55:51.207507 3, 0xFFFF, sum = 0
954 00:55:51.207589 4, 0xFFFF, sum = 0
955 00:55:51.210554 5, 0xFFFF, sum = 0
956 00:55:51.210659 6, 0xFFFF, sum = 0
957 00:55:51.214075 7, 0xFFFF, sum = 0
958 00:55:51.214182 8, 0xFFFF, sum = 0
959 00:55:51.217607 9, 0x0, sum = 1
960 00:55:51.217714 10, 0x0, sum = 2
961 00:55:51.220278 11, 0x0, sum = 3
962 00:55:51.220384 12, 0x0, sum = 4
963 00:55:51.223570 best_step = 10
964 00:55:51.223675
965 00:55:51.223763 ==
966 00:55:51.227082 Dram Type= 6, Freq= 0, CH_0, rank 0
967 00:55:51.230501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 00:55:51.230604 ==
969 00:55:51.230690 RX Vref Scan: 1
970 00:55:51.234084
971 00:55:51.234178 Set Vref Range= 32 -> 127
972 00:55:51.234253
973 00:55:51.237439 RX Vref 32 -> 127, step: 1
974 00:55:51.237532
975 00:55:51.241054 RX Delay -95 -> 252, step: 8
976 00:55:51.241144
977 00:55:51.244471 Set Vref, RX VrefLevel [Byte0]: 32
978 00:55:51.247107 [Byte1]: 32
979 00:55:51.247202
980 00:55:51.250484 Set Vref, RX VrefLevel [Byte0]: 33
981 00:55:51.253954 [Byte1]: 33
982 00:55:51.254051
983 00:55:51.257286 Set Vref, RX VrefLevel [Byte0]: 34
984 00:55:51.260617 [Byte1]: 34
985 00:55:51.264834
986 00:55:51.264912 Set Vref, RX VrefLevel [Byte0]: 35
987 00:55:51.268192 [Byte1]: 35
988 00:55:51.272273
989 00:55:51.272350 Set Vref, RX VrefLevel [Byte0]: 36
990 00:55:51.275598 [Byte1]: 36
991 00:55:51.280013
992 00:55:51.280094 Set Vref, RX VrefLevel [Byte0]: 37
993 00:55:51.283289 [Byte1]: 37
994 00:55:51.287214
995 00:55:51.287291 Set Vref, RX VrefLevel [Byte0]: 38
996 00:55:51.291016 [Byte1]: 38
997 00:55:51.294876
998 00:55:51.294956 Set Vref, RX VrefLevel [Byte0]: 39
999 00:55:51.298347 [Byte1]: 39
1000 00:55:51.302913
1001 00:55:51.302991 Set Vref, RX VrefLevel [Byte0]: 40
1002 00:55:51.306156 [Byte1]: 40
1003 00:55:51.310197
1004 00:55:51.310277 Set Vref, RX VrefLevel [Byte0]: 41
1005 00:55:51.313250 [Byte1]: 41
1006 00:55:51.317759
1007 00:55:51.317863 Set Vref, RX VrefLevel [Byte0]: 42
1008 00:55:51.321211 [Byte1]: 42
1009 00:55:51.325250
1010 00:55:51.325330 Set Vref, RX VrefLevel [Byte0]: 43
1011 00:55:51.328573 [Byte1]: 43
1012 00:55:51.333492
1013 00:55:51.333594 Set Vref, RX VrefLevel [Byte0]: 44
1014 00:55:51.336181 [Byte1]: 44
1015 00:55:51.341038
1016 00:55:51.341117 Set Vref, RX VrefLevel [Byte0]: 45
1017 00:55:51.343844 [Byte1]: 45
1018 00:55:51.348070
1019 00:55:51.348152 Set Vref, RX VrefLevel [Byte0]: 46
1020 00:55:51.351573 [Byte1]: 46
1021 00:55:51.355615
1022 00:55:51.355697 Set Vref, RX VrefLevel [Byte0]: 47
1023 00:55:51.358888 [Byte1]: 47
1024 00:55:51.363651
1025 00:55:51.363758 Set Vref, RX VrefLevel [Byte0]: 48
1026 00:55:51.366954 [Byte1]: 48
1027 00:55:51.371079
1028 00:55:51.371184 Set Vref, RX VrefLevel [Byte0]: 49
1029 00:55:51.374569 [Byte1]: 49
1030 00:55:51.378842
1031 00:55:51.378947 Set Vref, RX VrefLevel [Byte0]: 50
1032 00:55:51.382262 [Byte1]: 50
1033 00:55:51.386097
1034 00:55:51.386199 Set Vref, RX VrefLevel [Byte0]: 51
1035 00:55:51.389509 [Byte1]: 51
1036 00:55:51.394106
1037 00:55:51.394212 Set Vref, RX VrefLevel [Byte0]: 52
1038 00:55:51.397440 [Byte1]: 52
1039 00:55:51.401154
1040 00:55:51.401230 Set Vref, RX VrefLevel [Byte0]: 53
1041 00:55:51.404630 [Byte1]: 53
1042 00:55:51.409364
1043 00:55:51.409437 Set Vref, RX VrefLevel [Byte0]: 54
1044 00:55:51.412474 [Byte1]: 54
1045 00:55:51.416767
1046 00:55:51.416868 Set Vref, RX VrefLevel [Byte0]: 55
1047 00:55:51.420110 [Byte1]: 55
1048 00:55:51.424212
1049 00:55:51.424320 Set Vref, RX VrefLevel [Byte0]: 56
1050 00:55:51.427294 [Byte1]: 56
1051 00:55:51.431955
1052 00:55:51.432056 Set Vref, RX VrefLevel [Byte0]: 57
1053 00:55:51.435300 [Byte1]: 57
1054 00:55:51.439627
1055 00:55:51.439731 Set Vref, RX VrefLevel [Byte0]: 58
1056 00:55:51.443020 [Byte1]: 58
1057 00:55:51.447203
1058 00:55:51.447289 Set Vref, RX VrefLevel [Byte0]: 59
1059 00:55:51.450196 [Byte1]: 59
1060 00:55:51.454521
1061 00:55:51.454594 Set Vref, RX VrefLevel [Byte0]: 60
1062 00:55:51.457998 [Byte1]: 60
1063 00:55:51.462125
1064 00:55:51.462199 Set Vref, RX VrefLevel [Byte0]: 61
1065 00:55:51.465496 [Byte1]: 61
1066 00:55:51.469537
1067 00:55:51.469618 Set Vref, RX VrefLevel [Byte0]: 62
1068 00:55:51.473005 [Byte1]: 62
1069 00:55:51.477633
1070 00:55:51.477730 Set Vref, RX VrefLevel [Byte0]: 63
1071 00:55:51.480478 [Byte1]: 63
1072 00:55:51.485293
1073 00:55:51.485367 Set Vref, RX VrefLevel [Byte0]: 64
1074 00:55:51.488713 [Byte1]: 64
1075 00:55:51.492662
1076 00:55:51.492765 Set Vref, RX VrefLevel [Byte0]: 65
1077 00:55:51.495868 [Byte1]: 65
1078 00:55:51.500168
1079 00:55:51.500269 Set Vref, RX VrefLevel [Byte0]: 66
1080 00:55:51.503626 [Byte1]: 66
1081 00:55:51.507624
1082 00:55:51.507728 Set Vref, RX VrefLevel [Byte0]: 67
1083 00:55:51.511215 [Byte1]: 67
1084 00:55:51.515609
1085 00:55:51.515691 Set Vref, RX VrefLevel [Byte0]: 68
1086 00:55:51.518936 [Byte1]: 68
1087 00:55:51.522828
1088 00:55:51.522932 Set Vref, RX VrefLevel [Byte0]: 69
1089 00:55:51.526399 [Byte1]: 69
1090 00:55:51.530441
1091 00:55:51.530545 Set Vref, RX VrefLevel [Byte0]: 70
1092 00:55:51.534169 [Byte1]: 70
1093 00:55:51.538711
1094 00:55:51.538815 Set Vref, RX VrefLevel [Byte0]: 71
1095 00:55:51.541220 [Byte1]: 71
1096 00:55:51.545980
1097 00:55:51.546088 Set Vref, RX VrefLevel [Byte0]: 72
1098 00:55:51.549434 [Byte1]: 72
1099 00:55:51.553511
1100 00:55:51.553623 Set Vref, RX VrefLevel [Byte0]: 73
1101 00:55:51.556955 [Byte1]: 73
1102 00:55:51.561147
1103 00:55:51.561251 Set Vref, RX VrefLevel [Byte0]: 74
1104 00:55:51.564576 [Byte1]: 74
1105 00:55:51.568814
1106 00:55:51.568918 Set Vref, RX VrefLevel [Byte0]: 75
1107 00:55:51.572175 [Byte1]: 75
1108 00:55:51.575958
1109 00:55:51.576063 Set Vref, RX VrefLevel [Byte0]: 76
1110 00:55:51.579235 [Byte1]: 76
1111 00:55:51.583956
1112 00:55:51.584064 Final RX Vref Byte 0 = 52 to rank0
1113 00:55:51.586982 Final RX Vref Byte 1 = 56 to rank0
1114 00:55:51.590391 Final RX Vref Byte 0 = 52 to rank1
1115 00:55:51.593801 Final RX Vref Byte 1 = 56 to rank1==
1116 00:55:51.597361 Dram Type= 6, Freq= 0, CH_0, rank 0
1117 00:55:51.604169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1118 00:55:51.604276 ==
1119 00:55:51.604364 DQS Delay:
1120 00:55:51.604449 DQS0 = 0, DQS1 = 0
1121 00:55:51.607559 DQM Delay:
1122 00:55:51.607660 DQM0 = 91, DQM1 = 85
1123 00:55:51.610698 DQ Delay:
1124 00:55:51.610797 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1125 00:55:51.613801 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1126 00:55:51.616946 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
1127 00:55:51.620675 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1128 00:55:51.623854
1129 00:55:51.623956
1130 00:55:51.630729 [DQSOSCAuto] RK0, (LSB)MR18= 0x5247, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
1131 00:55:51.634105 CH0 RK0: MR19=606, MR18=5247
1132 00:55:51.640814 CH0_RK0: MR19=0x606, MR18=0x5247, DQSOSC=389, MR23=63, INC=97, DEC=65
1133 00:55:51.640959
1134 00:55:51.643855 ----->DramcWriteLeveling(PI) begin...
1135 00:55:51.643960 ==
1136 00:55:51.647737 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 00:55:51.650894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 00:55:51.650999 ==
1139 00:55:51.654148 Write leveling (Byte 0): 34 => 34
1140 00:55:51.657290 Write leveling (Byte 1): 30 => 30
1141 00:55:51.660525 DramcWriteLeveling(PI) end<-----
1142 00:55:51.660624
1143 00:55:51.660711 ==
1144 00:55:51.664058 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 00:55:51.667397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 00:55:51.667499 ==
1147 00:55:51.670941 [Gating] SW mode calibration
1148 00:55:51.677152 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1149 00:55:51.683729 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1150 00:55:51.687775 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 00:55:51.691214 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 00:55:51.734865 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1153 00:55:51.735175 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 00:55:51.735279 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 00:55:51.735381 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 00:55:51.735470 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:55:51.735556 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:55:51.735655 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:55:51.735740 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:55:51.735824 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:55:51.735908 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:55:51.750653 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:55:51.750974 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:55:51.754048 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:55:51.757092 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:55:51.757193 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:55:51.760110 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1168 00:55:51.767164 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1169 00:55:51.770381 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:55:51.773864 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:55:51.780641 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:55:51.783429 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:55:51.786932 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:55:51.793404 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:55:51.797213 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:55:51.800489 0 9 8 | B1->B0 | 2f2f 2d2d | 1 1 | (0 0) (0 0)
1177 00:55:51.807317 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 00:55:51.810165 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 00:55:51.813590 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 00:55:51.820527 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 00:55:51.823949 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 00:55:51.827310 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 00:55:51.834135 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1184 00:55:51.836923 0 10 8 | B1->B0 | 2828 2828 | 1 0 | (1 1) (0 0)
1185 00:55:51.840862 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 00:55:51.843908 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 00:55:51.850538 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:55:51.854188 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:55:51.857173 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:55:51.864047 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:55:51.867136 0 11 4 | B1->B0 | 2626 2727 | 1 0 | (0 0) (0 0)
1192 00:55:51.870897 0 11 8 | B1->B0 | 4040 3737 | 1 0 | (0 0) (0 0)
1193 00:55:51.877717 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 00:55:51.881080 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 00:55:51.883778 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 00:55:51.890606 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 00:55:51.894113 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 00:55:51.897381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 00:55:51.904059 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:55:51.907445 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1201 00:55:51.910601 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 00:55:51.917489 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 00:55:51.920990 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:55:51.923848 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:55:51.927258 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:55:51.933987 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:55:51.937489 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:55:51.940984 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:55:51.947287 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:55:51.950840 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:55:51.954064 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:55:51.960794 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:55:51.964016 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:55:51.967433 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:55:51.974297 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1216 00:55:51.977177 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1217 00:55:51.980711 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 00:55:51.984333 Total UI for P1: 0, mck2ui 16
1219 00:55:51.987318 best dqsien dly found for B0: ( 0, 14, 6)
1220 00:55:51.990797 Total UI for P1: 0, mck2ui 16
1221 00:55:51.994013 best dqsien dly found for B1: ( 0, 14, 8)
1222 00:55:51.997672 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1223 00:55:52.000951 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1224 00:55:52.001090
1225 00:55:52.004220 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1226 00:55:52.011165 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1227 00:55:52.011273 [Gating] SW calibration Done
1228 00:55:52.011359 ==
1229 00:55:52.014445 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 00:55:52.020656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 00:55:52.020764 ==
1232 00:55:52.020853 RX Vref Scan: 0
1233 00:55:52.020939
1234 00:55:52.024073 RX Vref 0 -> 0, step: 1
1235 00:55:52.024174
1236 00:55:52.027514 RX Delay -130 -> 252, step: 16
1237 00:55:52.031013 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1238 00:55:52.033841 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1239 00:55:52.037176 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1240 00:55:52.044201 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1241 00:55:52.047616 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1242 00:55:52.050475 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1243 00:55:52.054167 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1244 00:55:52.057532 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1245 00:55:52.060799 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1246 00:55:52.067654 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1247 00:55:52.070936 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1248 00:55:52.074042 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1249 00:55:52.077453 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1250 00:55:52.083941 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1251 00:55:52.087649 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1252 00:55:52.090732 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1253 00:55:52.090814 ==
1254 00:55:52.093805 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 00:55:52.097479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 00:55:52.097589 ==
1257 00:55:52.100502 DQS Delay:
1258 00:55:52.100580 DQS0 = 0, DQS1 = 0
1259 00:55:52.100641 DQM Delay:
1260 00:55:52.103840 DQM0 = 89, DQM1 = 82
1261 00:55:52.103941 DQ Delay:
1262 00:55:52.107454 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1263 00:55:52.110985 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1264 00:55:52.114412 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1265 00:55:52.117609 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1266 00:55:52.117714
1267 00:55:52.117812
1268 00:55:52.117904 ==
1269 00:55:52.120958 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 00:55:52.127968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 00:55:52.128094 ==
1272 00:55:52.128170
1273 00:55:52.128224
1274 00:55:52.128276 TX Vref Scan disable
1275 00:55:52.131305 == TX Byte 0 ==
1276 00:55:52.134791 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1277 00:55:52.137517 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1278 00:55:52.140986 == TX Byte 1 ==
1279 00:55:52.144433 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1280 00:55:52.151174 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1281 00:55:52.151258 ==
1282 00:55:52.154487 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 00:55:52.157874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 00:55:52.157952 ==
1285 00:55:52.171040 TX Vref=22, minBit 10, minWin=27, winSum=448
1286 00:55:52.173828 TX Vref=24, minBit 1, minWin=28, winSum=452
1287 00:55:52.177158 TX Vref=26, minBit 11, minWin=27, winSum=456
1288 00:55:52.180559 TX Vref=28, minBit 7, minWin=28, winSum=460
1289 00:55:52.183845 TX Vref=30, minBit 8, minWin=27, winSum=458
1290 00:55:52.190423 TX Vref=32, minBit 1, minWin=28, winSum=456
1291 00:55:52.193899 [TxChooseVref] Worse bit 7, Min win 28, Win sum 460, Final Vref 28
1292 00:55:52.194003
1293 00:55:52.197240 Final TX Range 1 Vref 28
1294 00:55:52.197319
1295 00:55:52.197377 ==
1296 00:55:52.200634 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 00:55:52.203822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 00:55:52.203901 ==
1299 00:55:52.203960
1300 00:55:52.207201
1301 00:55:52.207277 TX Vref Scan disable
1302 00:55:52.210374 == TX Byte 0 ==
1303 00:55:52.213922 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1304 00:55:52.217403 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1305 00:55:52.220788 == TX Byte 1 ==
1306 00:55:52.224062 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1307 00:55:52.227897 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1308 00:55:52.230990
1309 00:55:52.231067 [DATLAT]
1310 00:55:52.231126 Freq=800, CH0 RK1
1311 00:55:52.231182
1312 00:55:52.233891 DATLAT Default: 0xa
1313 00:55:52.233979 0, 0xFFFF, sum = 0
1314 00:55:52.237391 1, 0xFFFF, sum = 0
1315 00:55:52.237470 2, 0xFFFF, sum = 0
1316 00:55:52.240748 3, 0xFFFF, sum = 0
1317 00:55:52.240828 4, 0xFFFF, sum = 0
1318 00:55:52.244169 5, 0xFFFF, sum = 0
1319 00:55:52.244283 6, 0xFFFF, sum = 0
1320 00:55:52.247725 7, 0xFFFF, sum = 0
1321 00:55:52.247798 8, 0xFFFF, sum = 0
1322 00:55:52.251276 9, 0x0, sum = 1
1323 00:55:52.251357 10, 0x0, sum = 2
1324 00:55:52.253903 11, 0x0, sum = 3
1325 00:55:52.253986 12, 0x0, sum = 4
1326 00:55:52.257431 best_step = 10
1327 00:55:52.257509
1328 00:55:52.257581 ==
1329 00:55:52.260795 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 00:55:52.264308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 00:55:52.264389 ==
1332 00:55:52.267671 RX Vref Scan: 0
1333 00:55:52.267744
1334 00:55:52.267802 RX Vref 0 -> 0, step: 1
1335 00:55:52.267857
1336 00:55:52.270792 RX Delay -79 -> 252, step: 8
1337 00:55:52.277846 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1338 00:55:52.281260 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1339 00:55:52.284212 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1340 00:55:52.287634 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1341 00:55:52.291114 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1342 00:55:52.297326 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1343 00:55:52.301139 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1344 00:55:52.304466 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1345 00:55:52.307728 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1346 00:55:52.311044 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1347 00:55:52.317535 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1348 00:55:52.320921 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1349 00:55:52.324246 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1350 00:55:52.327883 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1351 00:55:52.331373 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1352 00:55:52.337482 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1353 00:55:52.337591 ==
1354 00:55:52.340783 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 00:55:52.344097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 00:55:52.344186 ==
1357 00:55:52.344275 DQS Delay:
1358 00:55:52.347482 DQS0 = 0, DQS1 = 0
1359 00:55:52.347552 DQM Delay:
1360 00:55:52.350797 DQM0 = 92, DQM1 = 82
1361 00:55:52.350900 DQ Delay:
1362 00:55:52.354257 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1363 00:55:52.357535 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1364 00:55:52.360978 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1365 00:55:52.364556 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =92
1366 00:55:52.364635
1367 00:55:52.364695
1368 00:55:52.371112 [DQSOSCAuto] RK1, (LSB)MR18= 0x4919, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
1369 00:55:52.374598 CH0 RK1: MR19=606, MR18=4919
1370 00:55:52.381427 CH0_RK1: MR19=0x606, MR18=0x4919, DQSOSC=391, MR23=63, INC=96, DEC=64
1371 00:55:52.384288 [RxdqsGatingPostProcess] freq 800
1372 00:55:52.387711 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 00:55:52.391178 Pre-setting of DQS Precalculation
1374 00:55:52.398149 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 00:55:52.398237 ==
1376 00:55:52.401369 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 00:55:52.404890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 00:55:52.404969 ==
1379 00:55:52.411304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 00:55:52.417756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 00:55:52.425482 [CA 0] Center 36 (6~67) winsize 62
1382 00:55:52.429493 [CA 1] Center 36 (6~67) winsize 62
1383 00:55:52.432303 [CA 2] Center 35 (5~66) winsize 62
1384 00:55:52.435712 [CA 3] Center 34 (4~65) winsize 62
1385 00:55:52.439154 [CA 4] Center 34 (4~65) winsize 62
1386 00:55:52.442458 [CA 5] Center 34 (4~64) winsize 61
1387 00:55:52.442554
1388 00:55:52.445854 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1389 00:55:52.445932
1390 00:55:52.449124 [CATrainingPosCal] consider 1 rank data
1391 00:55:52.452620 u2DelayCellTimex100 = 270/100 ps
1392 00:55:52.455791 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 00:55:52.459106 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1394 00:55:52.465819 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1395 00:55:52.469174 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 00:55:52.472548 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 00:55:52.475533 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 00:55:52.475610
1399 00:55:52.479267 CA PerBit enable=1, Macro0, CA PI delay=34
1400 00:55:52.479344
1401 00:55:52.482494 [CBTSetCACLKResult] CA Dly = 34
1402 00:55:52.482583 CS Dly: 6 (0~37)
1403 00:55:52.482642 ==
1404 00:55:52.486068 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 00:55:52.492521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 00:55:52.492600 ==
1407 00:55:52.495878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 00:55:52.502559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 00:55:52.512118 [CA 0] Center 36 (6~67) winsize 62
1410 00:55:52.515438 [CA 1] Center 37 (6~68) winsize 63
1411 00:55:52.518831 [CA 2] Center 35 (4~66) winsize 63
1412 00:55:52.522111 [CA 3] Center 34 (4~65) winsize 62
1413 00:55:52.525457 [CA 4] Center 35 (4~66) winsize 63
1414 00:55:52.528697 [CA 5] Center 34 (4~65) winsize 62
1415 00:55:52.528777
1416 00:55:52.532246 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1417 00:55:52.532323
1418 00:55:52.535169 [CATrainingPosCal] consider 2 rank data
1419 00:55:52.538626 u2DelayCellTimex100 = 270/100 ps
1420 00:55:52.541999 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 00:55:52.545495 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1422 00:55:52.552132 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1423 00:55:52.555150 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 00:55:52.558537 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 00:55:52.561738 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 00:55:52.561847
1427 00:55:52.564976 CA PerBit enable=1, Macro0, CA PI delay=34
1428 00:55:52.565052
1429 00:55:52.568338 [CBTSetCACLKResult] CA Dly = 34
1430 00:55:52.568418 CS Dly: 6 (0~38)
1431 00:55:52.568478
1432 00:55:52.571700 ----->DramcWriteLeveling(PI) begin...
1433 00:55:52.571778 ==
1434 00:55:52.575221 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 00:55:52.581956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 00:55:52.582038 ==
1437 00:55:52.585208 Write leveling (Byte 0): 27 => 27
1438 00:55:52.588634 Write leveling (Byte 1): 26 => 26
1439 00:55:52.588711 DramcWriteLeveling(PI) end<-----
1440 00:55:52.592027
1441 00:55:52.592104 ==
1442 00:55:52.595133 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 00:55:52.598916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 00:55:52.598994 ==
1445 00:55:52.602194 [Gating] SW mode calibration
1446 00:55:52.608787 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 00:55:52.612232 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 00:55:52.618733 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 00:55:52.622043 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1450 00:55:52.625398 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 00:55:52.631952 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 00:55:52.635346 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 00:55:52.638794 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 00:55:52.645195 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 00:55:52.648749 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:55:52.652530 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:55:52.658525 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:55:52.662168 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:55:52.665260 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:55:52.668513 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:55:52.675585 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:55:52.678957 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:55:52.682514 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:55:52.688507 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:55:52.691808 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 00:55:52.695255 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1467 00:55:52.701984 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 00:55:52.705334 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:55:52.708584 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:55:52.715154 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:55:52.718946 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:55:52.722389 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:55:52.729128 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
1474 00:55:52.732165 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1475 00:55:52.735480 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 00:55:52.742120 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 00:55:52.745403 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 00:55:52.748874 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 00:55:52.755299 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 00:55:52.758756 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1481 00:55:52.762239 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (0 1)
1482 00:55:52.765455 0 10 8 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
1483 00:55:52.771874 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 00:55:52.775656 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 00:55:52.778701 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:55:52.785787 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:55:52.789196 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:55:52.792464 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1489 00:55:52.799149 0 11 4 | B1->B0 | 2e2e 3434 | 0 0 | (0 0) (1 1)
1490 00:55:52.802512 0 11 8 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
1491 00:55:52.805893 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 00:55:52.812492 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 00:55:52.815864 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 00:55:52.819209 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 00:55:52.825451 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:55:52.828855 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:55:52.832392 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 00:55:52.835604 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 00:55:52.842229 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 00:55:52.845613 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 00:55:52.848939 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 00:55:52.855791 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:55:52.859317 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:55:52.862513 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:55:52.869363 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:55:52.872375 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:55:52.875553 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:55:52.882851 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:55:52.885946 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:55:52.888977 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:55:52.895959 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:55:52.899276 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1513 00:55:52.902678 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1514 00:55:52.906065 Total UI for P1: 0, mck2ui 16
1515 00:55:52.909418 best dqsien dly found for B1: ( 0, 14, 0)
1516 00:55:52.912727 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1517 00:55:52.919203 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 00:55:52.922675 Total UI for P1: 0, mck2ui 16
1519 00:55:52.926101 best dqsien dly found for B0: ( 0, 14, 6)
1520 00:55:52.929478 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1521 00:55:52.932730 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1522 00:55:52.932827
1523 00:55:52.936274 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 00:55:52.939593 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1525 00:55:52.942895 [Gating] SW calibration Done
1526 00:55:52.942991 ==
1527 00:55:52.946246 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 00:55:52.949116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 00:55:52.949228 ==
1530 00:55:52.952729 RX Vref Scan: 0
1531 00:55:52.952806
1532 00:55:52.952865 RX Vref 0 -> 0, step: 1
1533 00:55:52.952919
1534 00:55:52.955831 RX Delay -130 -> 252, step: 16
1535 00:55:52.962543 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1536 00:55:52.965836 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1537 00:55:52.969511 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1538 00:55:52.972560 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1539 00:55:52.975637 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1540 00:55:52.979478 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1541 00:55:52.985752 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1542 00:55:52.989479 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1543 00:55:52.992530 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1544 00:55:52.995704 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1545 00:55:52.999407 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1546 00:55:53.005807 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1547 00:55:53.009189 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1548 00:55:53.012551 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1549 00:55:53.016052 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1550 00:55:53.019390 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1551 00:55:53.022710 ==
1552 00:55:53.026117 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 00:55:53.029484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 00:55:53.029618 ==
1555 00:55:53.029680 DQS Delay:
1556 00:55:53.032884 DQS0 = 0, DQS1 = 0
1557 00:55:53.032960 DQM Delay:
1558 00:55:53.036273 DQM0 = 93, DQM1 = 91
1559 00:55:53.036350 DQ Delay:
1560 00:55:53.039733 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1561 00:55:53.043103 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1562 00:55:53.046209 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1563 00:55:53.049559 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1564 00:55:53.049670
1565 00:55:53.049731
1566 00:55:53.049786 ==
1567 00:55:53.053035 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 00:55:53.056411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 00:55:53.056489 ==
1570 00:55:53.056548
1571 00:55:53.056603
1572 00:55:53.059808 TX Vref Scan disable
1573 00:55:53.063222 == TX Byte 0 ==
1574 00:55:53.066592 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1575 00:55:53.069517 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1576 00:55:53.072927 == TX Byte 1 ==
1577 00:55:53.076586 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1578 00:55:53.079703 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1579 00:55:53.079782 ==
1580 00:55:53.083355 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 00:55:53.086268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 00:55:53.086346 ==
1583 00:55:53.100863 TX Vref=22, minBit 3, minWin=26, winSum=434
1584 00:55:53.104009 TX Vref=24, minBit 0, minWin=27, winSum=444
1585 00:55:53.107157 TX Vref=26, minBit 3, minWin=26, winSum=443
1586 00:55:53.110922 TX Vref=28, minBit 0, minWin=27, winSum=446
1587 00:55:53.114064 TX Vref=30, minBit 0, minWin=27, winSum=447
1588 00:55:53.120754 TX Vref=32, minBit 0, minWin=27, winSum=448
1589 00:55:53.124311 [TxChooseVref] Worse bit 0, Min win 27, Win sum 448, Final Vref 32
1590 00:55:53.124391
1591 00:55:53.127173 Final TX Range 1 Vref 32
1592 00:55:53.127249
1593 00:55:53.127315 ==
1594 00:55:53.130827 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 00:55:53.134172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 00:55:53.134249 ==
1597 00:55:53.137553
1598 00:55:53.137647
1599 00:55:53.137707 TX Vref Scan disable
1600 00:55:53.141008 == TX Byte 0 ==
1601 00:55:53.144425 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1602 00:55:53.150940 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1603 00:55:53.151025 == TX Byte 1 ==
1604 00:55:53.154254 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1605 00:55:53.157624 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1606 00:55:53.161008
1607 00:55:53.161085 [DATLAT]
1608 00:55:53.161146 Freq=800, CH1 RK0
1609 00:55:53.161215
1610 00:55:53.164383 DATLAT Default: 0xa
1611 00:55:53.164460 0, 0xFFFF, sum = 0
1612 00:55:53.167779 1, 0xFFFF, sum = 0
1613 00:55:53.167856 2, 0xFFFF, sum = 0
1614 00:55:53.171155 3, 0xFFFF, sum = 0
1615 00:55:53.171233 4, 0xFFFF, sum = 0
1616 00:55:53.174256 5, 0xFFFF, sum = 0
1617 00:55:53.174336 6, 0xFFFF, sum = 0
1618 00:55:53.177734 7, 0xFFFF, sum = 0
1619 00:55:53.177837 8, 0xFFFF, sum = 0
1620 00:55:53.180977 9, 0x0, sum = 1
1621 00:55:53.181055 10, 0x0, sum = 2
1622 00:55:53.184060 11, 0x0, sum = 3
1623 00:55:53.184140 12, 0x0, sum = 4
1624 00:55:53.187539 best_step = 10
1625 00:55:53.187617
1626 00:55:53.187676 ==
1627 00:55:53.190939 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 00:55:53.194282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 00:55:53.194360 ==
1630 00:55:53.197518 RX Vref Scan: 1
1631 00:55:53.197663
1632 00:55:53.197749 Set Vref Range= 32 -> 127
1633 00:55:53.197835
1634 00:55:53.201225 RX Vref 32 -> 127, step: 1
1635 00:55:53.201301
1636 00:55:53.204331 RX Delay -63 -> 252, step: 8
1637 00:55:53.204431
1638 00:55:53.207932 Set Vref, RX VrefLevel [Byte0]: 32
1639 00:55:53.211359 [Byte1]: 32
1640 00:55:53.211437
1641 00:55:53.214285 Set Vref, RX VrefLevel [Byte0]: 33
1642 00:55:53.217972 [Byte1]: 33
1643 00:55:53.218074
1644 00:55:53.221109 Set Vref, RX VrefLevel [Byte0]: 34
1645 00:55:53.224599 [Byte1]: 34
1646 00:55:53.228551
1647 00:55:53.228656 Set Vref, RX VrefLevel [Byte0]: 35
1648 00:55:53.231585 [Byte1]: 35
1649 00:55:53.235586
1650 00:55:53.235686 Set Vref, RX VrefLevel [Byte0]: 36
1651 00:55:53.238970 [Byte1]: 36
1652 00:55:53.243533
1653 00:55:53.243652 Set Vref, RX VrefLevel [Byte0]: 37
1654 00:55:53.246883 [Byte1]: 37
1655 00:55:53.250763
1656 00:55:53.250843 Set Vref, RX VrefLevel [Byte0]: 38
1657 00:55:53.253938 [Byte1]: 38
1658 00:55:53.258530
1659 00:55:53.258609 Set Vref, RX VrefLevel [Byte0]: 39
1660 00:55:53.261892 [Byte1]: 39
1661 00:55:53.265830
1662 00:55:53.265909 Set Vref, RX VrefLevel [Byte0]: 40
1663 00:55:53.269318 [Byte1]: 40
1664 00:55:53.273476
1665 00:55:53.273596 Set Vref, RX VrefLevel [Byte0]: 41
1666 00:55:53.276724 [Byte1]: 41
1667 00:55:53.280825
1668 00:55:53.280903 Set Vref, RX VrefLevel [Byte0]: 42
1669 00:55:53.284206 [Byte1]: 42
1670 00:55:53.288792
1671 00:55:53.288893 Set Vref, RX VrefLevel [Byte0]: 43
1672 00:55:53.292086 [Byte1]: 43
1673 00:55:53.295956
1674 00:55:53.296033 Set Vref, RX VrefLevel [Byte0]: 44
1675 00:55:53.299368 [Byte1]: 44
1676 00:55:53.303460
1677 00:55:53.303561 Set Vref, RX VrefLevel [Byte0]: 45
1678 00:55:53.306726 [Byte1]: 45
1679 00:55:53.311124
1680 00:55:53.311204 Set Vref, RX VrefLevel [Byte0]: 46
1681 00:55:53.314055 [Byte1]: 46
1682 00:55:53.318628
1683 00:55:53.318711 Set Vref, RX VrefLevel [Byte0]: 47
1684 00:55:53.321828 [Byte1]: 47
1685 00:55:53.326193
1686 00:55:53.326275 Set Vref, RX VrefLevel [Byte0]: 48
1687 00:55:53.329348 [Byte1]: 48
1688 00:55:53.333562
1689 00:55:53.333652 Set Vref, RX VrefLevel [Byte0]: 49
1690 00:55:53.336730 [Byte1]: 49
1691 00:55:53.340944
1692 00:55:53.341015 Set Vref, RX VrefLevel [Byte0]: 50
1693 00:55:53.344037 [Byte1]: 50
1694 00:55:53.348384
1695 00:55:53.348485 Set Vref, RX VrefLevel [Byte0]: 51
1696 00:55:53.351280 [Byte1]: 51
1697 00:55:53.355683
1698 00:55:53.355796 Set Vref, RX VrefLevel [Byte0]: 52
1699 00:55:53.358978 [Byte1]: 52
1700 00:55:53.363618
1701 00:55:53.363722 Set Vref, RX VrefLevel [Byte0]: 53
1702 00:55:53.366780 [Byte1]: 53
1703 00:55:53.370602
1704 00:55:53.370693 Set Vref, RX VrefLevel [Byte0]: 54
1705 00:55:53.374114 [Byte1]: 54
1706 00:55:53.378543
1707 00:55:53.378630 Set Vref, RX VrefLevel [Byte0]: 55
1708 00:55:53.381810 [Byte1]: 55
1709 00:55:53.385759
1710 00:55:53.385837 Set Vref, RX VrefLevel [Byte0]: 56
1711 00:55:53.389071 [Byte1]: 56
1712 00:55:53.393584
1713 00:55:53.393675 Set Vref, RX VrefLevel [Byte0]: 57
1714 00:55:53.396854 [Byte1]: 57
1715 00:55:53.400788
1716 00:55:53.400867 Set Vref, RX VrefLevel [Byte0]: 58
1717 00:55:53.404155 [Byte1]: 58
1718 00:55:53.408289
1719 00:55:53.408367 Set Vref, RX VrefLevel [Byte0]: 59
1720 00:55:53.411664 [Byte1]: 59
1721 00:55:53.415576
1722 00:55:53.415659 Set Vref, RX VrefLevel [Byte0]: 60
1723 00:55:53.418965 [Byte1]: 60
1724 00:55:53.423640
1725 00:55:53.423737 Set Vref, RX VrefLevel [Byte0]: 61
1726 00:55:53.426859 [Byte1]: 61
1727 00:55:53.430779
1728 00:55:53.430861 Set Vref, RX VrefLevel [Byte0]: 62
1729 00:55:53.434106 [Byte1]: 62
1730 00:55:53.438502
1731 00:55:53.438584 Set Vref, RX VrefLevel [Byte0]: 63
1732 00:55:53.441775 [Byte1]: 63
1733 00:55:53.445492
1734 00:55:53.445608 Set Vref, RX VrefLevel [Byte0]: 64
1735 00:55:53.449224 [Byte1]: 64
1736 00:55:53.453175
1737 00:55:53.453251 Set Vref, RX VrefLevel [Byte0]: 65
1738 00:55:53.456652 [Byte1]: 65
1739 00:55:53.460521
1740 00:55:53.460596 Set Vref, RX VrefLevel [Byte0]: 66
1741 00:55:53.463743 [Byte1]: 66
1742 00:55:53.468098
1743 00:55:53.468220 Set Vref, RX VrefLevel [Byte0]: 67
1744 00:55:53.471905 [Byte1]: 67
1745 00:55:53.475618
1746 00:55:53.475695 Set Vref, RX VrefLevel [Byte0]: 68
1747 00:55:53.479070 [Byte1]: 68
1748 00:55:53.483194
1749 00:55:53.483278 Set Vref, RX VrefLevel [Byte0]: 69
1750 00:55:53.486636 [Byte1]: 69
1751 00:55:53.490656
1752 00:55:53.490739 Set Vref, RX VrefLevel [Byte0]: 70
1753 00:55:53.494431 [Byte1]: 70
1754 00:55:53.498566
1755 00:55:53.498649 Set Vref, RX VrefLevel [Byte0]: 71
1756 00:55:53.501682 [Byte1]: 71
1757 00:55:53.505593
1758 00:55:53.505687 Final RX Vref Byte 0 = 58 to rank0
1759 00:55:53.508956 Final RX Vref Byte 1 = 57 to rank0
1760 00:55:53.512310 Final RX Vref Byte 0 = 58 to rank1
1761 00:55:53.515705 Final RX Vref Byte 1 = 57 to rank1==
1762 00:55:53.518957 Dram Type= 6, Freq= 0, CH_1, rank 0
1763 00:55:53.522368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1764 00:55:53.525681 ==
1765 00:55:53.525763 DQS Delay:
1766 00:55:53.525854 DQS0 = 0, DQS1 = 0
1767 00:55:53.529151 DQM Delay:
1768 00:55:53.529229 DQM0 = 95, DQM1 = 90
1769 00:55:53.532540 DQ Delay:
1770 00:55:53.535810 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1771 00:55:53.539213 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1772 00:55:53.542382 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1773 00:55:53.545684 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1774 00:55:53.545764
1775 00:55:53.545842
1776 00:55:53.552498 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1777 00:55:53.555739 CH1 RK0: MR19=606, MR18=2E4A
1778 00:55:53.562776 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1779 00:55:53.562857
1780 00:55:53.566111 ----->DramcWriteLeveling(PI) begin...
1781 00:55:53.566192 ==
1782 00:55:53.568769 Dram Type= 6, Freq= 0, CH_1, rank 1
1783 00:55:53.572613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 00:55:53.572693 ==
1785 00:55:53.575700 Write leveling (Byte 0): 24 => 24
1786 00:55:53.579029 Write leveling (Byte 1): 30 => 30
1787 00:55:53.582268 DramcWriteLeveling(PI) end<-----
1788 00:55:53.582347
1789 00:55:53.582425 ==
1790 00:55:53.586230 Dram Type= 6, Freq= 0, CH_1, rank 1
1791 00:55:53.589466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 00:55:53.589589 ==
1793 00:55:53.592797 [Gating] SW mode calibration
1794 00:55:53.599217 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1795 00:55:53.606096 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1796 00:55:53.609279 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1797 00:55:53.612806 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1798 00:55:53.619390 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 00:55:53.622745 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 00:55:53.625945 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 00:55:53.632898 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 00:55:53.636198 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 00:55:53.639151 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 00:55:53.646212 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 00:55:53.649499 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 00:55:53.652918 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 00:55:53.659084 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 00:55:53.662346 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 00:55:53.665674 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 00:55:53.669431 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 00:55:53.675643 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:55:53.679429 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:55:53.682553 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1814 00:55:53.689497 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:55:53.692755 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:55:53.695969 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:55:53.702851 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:55:53.706282 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:55:53.709444 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:55:53.716190 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:55:53.719339 0 9 4 | B1->B0 | 2727 2323 | 1 1 | (1 1) (1 1)
1822 00:55:53.722852 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 00:55:53.729324 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 00:55:53.732884 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 00:55:53.735804 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 00:55:53.742492 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 00:55:53.745812 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 00:55:53.749178 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1829 00:55:53.752528 0 10 4 | B1->B0 | 2929 3131 | 0 1 | (0 0) (1 0)
1830 00:55:53.759257 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1831 00:55:53.762662 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:55:53.766036 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:55:53.772813 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:55:53.776105 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:55:53.779276 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:55:53.786137 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1837 00:55:53.789340 0 11 4 | B1->B0 | 3333 2e2e | 0 1 | (1 1) (0 0)
1838 00:55:53.792953 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1839 00:55:53.799481 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 00:55:53.802586 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 00:55:53.805844 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 00:55:53.812772 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 00:55:53.816119 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 00:55:53.819326 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1845 00:55:53.825878 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1846 00:55:53.829890 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 00:55:53.832573 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 00:55:53.836433 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 00:55:53.842790 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 00:55:53.846193 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 00:55:53.849568 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 00:55:53.856431 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 00:55:53.859504 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 00:55:53.862888 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 00:55:53.869538 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 00:55:53.872931 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 00:55:53.876310 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 00:55:53.882553 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 00:55:53.885864 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:55:53.889791 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 00:55:53.896392 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1862 00:55:53.899664 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 00:55:53.903085 Total UI for P1: 0, mck2ui 16
1864 00:55:53.906443 best dqsien dly found for B0: ( 0, 14, 4)
1865 00:55:53.909490 Total UI for P1: 0, mck2ui 16
1866 00:55:53.912968 best dqsien dly found for B1: ( 0, 14, 4)
1867 00:55:53.916360 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1868 00:55:53.919707 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1869 00:55:53.919783
1870 00:55:53.923132 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1871 00:55:53.926303 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1872 00:55:53.929672 [Gating] SW calibration Done
1873 00:55:53.929748 ==
1874 00:55:53.933052 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 00:55:53.936309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 00:55:53.936385 ==
1877 00:55:53.939745 RX Vref Scan: 0
1878 00:55:53.939820
1879 00:55:53.939878 RX Vref 0 -> 0, step: 1
1880 00:55:53.943019
1881 00:55:53.943095 RX Delay -130 -> 252, step: 16
1882 00:55:53.949902 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1883 00:55:53.952800 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1884 00:55:53.956672 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1885 00:55:53.959749 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1886 00:55:53.963386 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1887 00:55:53.966555 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1888 00:55:53.973466 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1889 00:55:53.976424 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1890 00:55:53.979996 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1891 00:55:53.983325 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1892 00:55:53.986733 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1893 00:55:53.993527 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1894 00:55:53.996609 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1895 00:55:54.000029 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1896 00:55:54.003386 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1897 00:55:54.009759 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1898 00:55:54.009851 ==
1899 00:55:54.013405 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 00:55:54.016471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 00:55:54.016597 ==
1902 00:55:54.016660 DQS Delay:
1903 00:55:54.019662 DQS0 = 0, DQS1 = 0
1904 00:55:54.019739 DQM Delay:
1905 00:55:54.023181 DQM0 = 93, DQM1 = 90
1906 00:55:54.023259 DQ Delay:
1907 00:55:54.026708 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1908 00:55:54.029821 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1909 00:55:54.032784 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1910 00:55:54.036702 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1911 00:55:54.036781
1912 00:55:54.036840
1913 00:55:54.036894 ==
1914 00:55:54.039976 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 00:55:54.043246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 00:55:54.043347 ==
1917 00:55:54.043432
1918 00:55:54.046728
1919 00:55:54.046829 TX Vref Scan disable
1920 00:55:54.050079 == TX Byte 0 ==
1921 00:55:54.053479 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1922 00:55:54.056816 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1923 00:55:54.060096 == TX Byte 1 ==
1924 00:55:54.063442 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1925 00:55:54.066690 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1926 00:55:54.066769 ==
1927 00:55:54.069937 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 00:55:54.076675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 00:55:54.076756 ==
1930 00:55:54.088316 TX Vref=22, minBit 1, minWin=26, winSum=435
1931 00:55:54.091719 TX Vref=24, minBit 1, minWin=26, winSum=440
1932 00:55:54.095030 TX Vref=26, minBit 0, minWin=27, winSum=444
1933 00:55:54.098416 TX Vref=28, minBit 3, minWin=26, winSum=445
1934 00:55:54.102205 TX Vref=30, minBit 4, minWin=26, winSum=446
1935 00:55:54.105514 TX Vref=32, minBit 4, minWin=26, winSum=442
1936 00:55:54.112148 [TxChooseVref] Worse bit 0, Min win 27, Win sum 444, Final Vref 26
1937 00:55:54.112242
1938 00:55:54.115535 Final TX Range 1 Vref 26
1939 00:55:54.115614
1940 00:55:54.115674 ==
1941 00:55:54.118440 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 00:55:54.122262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 00:55:54.122340 ==
1944 00:55:54.122400
1945 00:55:54.122455
1946 00:55:54.125342 TX Vref Scan disable
1947 00:55:54.128673 == TX Byte 0 ==
1948 00:55:54.131751 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1949 00:55:54.135276 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1950 00:55:54.138211 == TX Byte 1 ==
1951 00:55:54.142079 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1952 00:55:54.145067 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1953 00:55:54.148738
1954 00:55:54.148888 [DATLAT]
1955 00:55:54.149018 Freq=800, CH1 RK1
1956 00:55:54.149143
1957 00:55:54.151933 DATLAT Default: 0xa
1958 00:55:54.152070 0, 0xFFFF, sum = 0
1959 00:55:54.155230 1, 0xFFFF, sum = 0
1960 00:55:54.155375 2, 0xFFFF, sum = 0
1961 00:55:54.158684 3, 0xFFFF, sum = 0
1962 00:55:54.158766 4, 0xFFFF, sum = 0
1963 00:55:54.161917 5, 0xFFFF, sum = 0
1964 00:55:54.162025 6, 0xFFFF, sum = 0
1965 00:55:54.165358 7, 0xFFFF, sum = 0
1966 00:55:54.165436 8, 0xFFFF, sum = 0
1967 00:55:54.168749 9, 0x0, sum = 1
1968 00:55:54.168828 10, 0x0, sum = 2
1969 00:55:54.172060 11, 0x0, sum = 3
1970 00:55:54.172140 12, 0x0, sum = 4
1971 00:55:54.175254 best_step = 10
1972 00:55:54.175334
1973 00:55:54.175394 ==
1974 00:55:54.178620 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 00:55:54.181781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 00:55:54.181860 ==
1977 00:55:54.185284 RX Vref Scan: 0
1978 00:55:54.185364
1979 00:55:54.185449 RX Vref 0 -> 0, step: 1
1980 00:55:54.185533
1981 00:55:54.188607 RX Delay -63 -> 252, step: 8
1982 00:55:54.195332 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1983 00:55:54.199136 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1984 00:55:54.202053 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1985 00:55:54.205458 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1986 00:55:54.208738 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1987 00:55:54.212062 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1988 00:55:54.218757 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1989 00:55:54.222111 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1990 00:55:54.225493 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1991 00:55:54.228732 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1992 00:55:54.231954 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1993 00:55:54.238603 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1994 00:55:54.242343 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1995 00:55:54.245614 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1996 00:55:54.248874 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1997 00:55:54.252112 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1998 00:55:54.252192 ==
1999 00:55:54.255509 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 00:55:54.262028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 00:55:54.262109 ==
2002 00:55:54.262170 DQS Delay:
2003 00:55:54.265463 DQS0 = 0, DQS1 = 0
2004 00:55:54.265565 DQM Delay:
2005 00:55:54.265700 DQM0 = 97, DQM1 = 91
2006 00:55:54.268725 DQ Delay:
2007 00:55:54.272206 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2008 00:55:54.275468 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2009 00:55:54.278762 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2010 00:55:54.282101 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2011 00:55:54.282199
2012 00:55:54.282284
2013 00:55:54.288764 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2014 00:55:54.292061 CH1 RK1: MR19=606, MR18=4A13
2015 00:55:54.298850 CH1_RK1: MR19=0x606, MR18=0x4A13, DQSOSC=391, MR23=63, INC=96, DEC=64
2016 00:55:54.302329 [RxdqsGatingPostProcess] freq 800
2017 00:55:54.305484 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2018 00:55:54.309064 Pre-setting of DQS Precalculation
2019 00:55:54.315538 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2020 00:55:54.322110 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2021 00:55:54.328943 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2022 00:55:54.329038
2023 00:55:54.329113
2024 00:55:54.332354 [Calibration Summary] 1600 Mbps
2025 00:55:54.332439 CH 0, Rank 0
2026 00:55:54.335669 SW Impedance : PASS
2027 00:55:54.338993 DUTY Scan : NO K
2028 00:55:54.339077 ZQ Calibration : PASS
2029 00:55:54.342406 Jitter Meter : NO K
2030 00:55:54.345595 CBT Training : PASS
2031 00:55:54.345710 Write leveling : PASS
2032 00:55:54.348749 RX DQS gating : PASS
2033 00:55:54.348867 RX DQ/DQS(RDDQC) : PASS
2034 00:55:54.352528 TX DQ/DQS : PASS
2035 00:55:54.355780 RX DATLAT : PASS
2036 00:55:54.355861 RX DQ/DQS(Engine): PASS
2037 00:55:54.358979 TX OE : NO K
2038 00:55:54.359067 All Pass.
2039 00:55:54.359128
2040 00:55:54.362404 CH 0, Rank 1
2041 00:55:54.362499 SW Impedance : PASS
2042 00:55:54.365726 DUTY Scan : NO K
2043 00:55:54.369054 ZQ Calibration : PASS
2044 00:55:54.369139 Jitter Meter : NO K
2045 00:55:54.372592 CBT Training : PASS
2046 00:55:54.375644 Write leveling : PASS
2047 00:55:54.375736 RX DQS gating : PASS
2048 00:55:54.379183 RX DQ/DQS(RDDQC) : PASS
2049 00:55:54.382176 TX DQ/DQS : PASS
2050 00:55:54.382304 RX DATLAT : PASS
2051 00:55:54.386005 RX DQ/DQS(Engine): PASS
2052 00:55:54.389202 TX OE : NO K
2053 00:55:54.389356 All Pass.
2054 00:55:54.389443
2055 00:55:54.389530 CH 1, Rank 0
2056 00:55:54.392694 SW Impedance : PASS
2057 00:55:54.396121 DUTY Scan : NO K
2058 00:55:54.396315 ZQ Calibration : PASS
2059 00:55:54.398935 Jitter Meter : NO K
2060 00:55:54.399085 CBT Training : PASS
2061 00:55:54.402342 Write leveling : PASS
2062 00:55:54.405823 RX DQS gating : PASS
2063 00:55:54.405929 RX DQ/DQS(RDDQC) : PASS
2064 00:55:54.409300 TX DQ/DQS : PASS
2065 00:55:54.412741 RX DATLAT : PASS
2066 00:55:54.412819 RX DQ/DQS(Engine): PASS
2067 00:55:54.416264 TX OE : NO K
2068 00:55:54.416342 All Pass.
2069 00:55:54.416402
2070 00:55:54.419493 CH 1, Rank 1
2071 00:55:54.419571 SW Impedance : PASS
2072 00:55:54.422675 DUTY Scan : NO K
2073 00:55:54.426157 ZQ Calibration : PASS
2074 00:55:54.426234 Jitter Meter : NO K
2075 00:55:54.429306 CBT Training : PASS
2076 00:55:54.429383 Write leveling : PASS
2077 00:55:54.432841 RX DQS gating : PASS
2078 00:55:54.436266 RX DQ/DQS(RDDQC) : PASS
2079 00:55:54.436385 TX DQ/DQS : PASS
2080 00:55:54.439408 RX DATLAT : PASS
2081 00:55:54.442806 RX DQ/DQS(Engine): PASS
2082 00:55:54.442912 TX OE : NO K
2083 00:55:54.445926 All Pass.
2084 00:55:54.445995
2085 00:55:54.446054 DramC Write-DBI off
2086 00:55:54.449380 PER_BANK_REFRESH: Hybrid Mode
2087 00:55:54.452689 TX_TRACKING: ON
2088 00:55:54.455861 [GetDramInforAfterCalByMRR] Vendor 6.
2089 00:55:54.459133 [GetDramInforAfterCalByMRR] Revision 606.
2090 00:55:54.462888 [GetDramInforAfterCalByMRR] Revision 2 0.
2091 00:55:54.462969 MR0 0x3b3b
2092 00:55:54.463027 MR8 0x5151
2093 00:55:54.468859 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2094 00:55:54.468936
2095 00:55:54.468997 MR0 0x3b3b
2096 00:55:54.469052 MR8 0x5151
2097 00:55:54.472215 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 00:55:54.472283
2099 00:55:54.482407 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2100 00:55:54.485682 [FAST_K] Save calibration result to emmc
2101 00:55:54.489469 [FAST_K] Save calibration result to emmc
2102 00:55:54.492503 dram_init: config_dvfs: 1
2103 00:55:54.495930 dramc_set_vcore_voltage set vcore to 662500
2104 00:55:54.498841 Read voltage for 1200, 2
2105 00:55:54.498933 Vio18 = 0
2106 00:55:54.498999 Vcore = 662500
2107 00:55:54.502282 Vdram = 0
2108 00:55:54.502351 Vddq = 0
2109 00:55:54.502408 Vmddr = 0
2110 00:55:54.509113 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2111 00:55:54.512510 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2112 00:55:54.515948 MEM_TYPE=3, freq_sel=15
2113 00:55:54.519434 sv_algorithm_assistance_LP4_1600
2114 00:55:54.522980 ============ PULL DRAM RESETB DOWN ============
2115 00:55:54.525683 ========== PULL DRAM RESETB DOWN end =========
2116 00:55:54.532551 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 00:55:54.536038 ===================================
2118 00:55:54.536131 LPDDR4 DRAM CONFIGURATION
2119 00:55:54.539315 ===================================
2120 00:55:54.542653 EX_ROW_EN[0] = 0x0
2121 00:55:54.545681 EX_ROW_EN[1] = 0x0
2122 00:55:54.545759 LP4Y_EN = 0x0
2123 00:55:54.549448 WORK_FSP = 0x0
2124 00:55:54.549559 WL = 0x4
2125 00:55:54.552813 RL = 0x4
2126 00:55:54.552881 BL = 0x2
2127 00:55:54.556106 RPST = 0x0
2128 00:55:54.556190 RD_PRE = 0x0
2129 00:55:54.559257 WR_PRE = 0x1
2130 00:55:54.559337 WR_PST = 0x0
2131 00:55:54.562765 DBI_WR = 0x0
2132 00:55:54.562868 DBI_RD = 0x0
2133 00:55:54.565934 OTF = 0x1
2134 00:55:54.569491 ===================================
2135 00:55:54.572899 ===================================
2136 00:55:54.572972 ANA top config
2137 00:55:54.575826 ===================================
2138 00:55:54.579063 DLL_ASYNC_EN = 0
2139 00:55:54.582539 ALL_SLAVE_EN = 0
2140 00:55:54.582644 NEW_RANK_MODE = 1
2141 00:55:54.585828 DLL_IDLE_MODE = 1
2142 00:55:54.589344 LP45_APHY_COMB_EN = 1
2143 00:55:54.592832 TX_ODT_DIS = 1
2144 00:55:54.596185 NEW_8X_MODE = 1
2145 00:55:54.599539 ===================================
2146 00:55:54.602847 ===================================
2147 00:55:54.602922 data_rate = 2400
2148 00:55:54.606149 CKR = 1
2149 00:55:54.609108 DQ_P2S_RATIO = 8
2150 00:55:54.612639 ===================================
2151 00:55:54.615951 CA_P2S_RATIO = 8
2152 00:55:54.619399 DQ_CA_OPEN = 0
2153 00:55:54.622797 DQ_SEMI_OPEN = 0
2154 00:55:54.622873 CA_SEMI_OPEN = 0
2155 00:55:54.626281 CA_FULL_RATE = 0
2156 00:55:54.629028 DQ_CKDIV4_EN = 0
2157 00:55:54.632344 CA_CKDIV4_EN = 0
2158 00:55:54.635712 CA_PREDIV_EN = 0
2159 00:55:54.639188 PH8_DLY = 17
2160 00:55:54.639265 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2161 00:55:54.642624 DQ_AAMCK_DIV = 4
2162 00:55:54.646273 CA_AAMCK_DIV = 4
2163 00:55:54.649118 CA_ADMCK_DIV = 4
2164 00:55:54.652738 DQ_TRACK_CA_EN = 0
2165 00:55:54.656355 CA_PICK = 1200
2166 00:55:54.656434 CA_MCKIO = 1200
2167 00:55:54.659118 MCKIO_SEMI = 0
2168 00:55:54.662594 PLL_FREQ = 2366
2169 00:55:54.666297 DQ_UI_PI_RATIO = 32
2170 00:55:54.669462 CA_UI_PI_RATIO = 0
2171 00:55:54.672438 ===================================
2172 00:55:54.676130 ===================================
2173 00:55:54.679888 memory_type:LPDDR4
2174 00:55:54.680000 GP_NUM : 10
2175 00:55:54.682711 SRAM_EN : 1
2176 00:55:54.682864 MD32_EN : 0
2177 00:55:54.686143 ===================================
2178 00:55:54.689670 [ANA_INIT] >>>>>>>>>>>>>>
2179 00:55:54.692843 <<<<<< [CONFIGURE PHASE]: ANA_TX
2180 00:55:54.696223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2181 00:55:54.699508 ===================================
2182 00:55:54.702742 data_rate = 2400,PCW = 0X5b00
2183 00:55:54.705947 ===================================
2184 00:55:54.709323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2185 00:55:54.712986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 00:55:54.720007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 00:55:54.722954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2188 00:55:54.726449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2189 00:55:54.732866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2190 00:55:54.732960 [ANA_INIT] flow start
2191 00:55:54.736142 [ANA_INIT] PLL >>>>>>>>
2192 00:55:54.736232 [ANA_INIT] PLL <<<<<<<<
2193 00:55:54.739607 [ANA_INIT] MIDPI >>>>>>>>
2194 00:55:54.743011 [ANA_INIT] MIDPI <<<<<<<<
2195 00:55:54.746353 [ANA_INIT] DLL >>>>>>>>
2196 00:55:54.746414 [ANA_INIT] DLL <<<<<<<<
2197 00:55:54.749909 [ANA_INIT] flow end
2198 00:55:54.752669 ============ LP4 DIFF to SE enter ============
2199 00:55:54.756214 ============ LP4 DIFF to SE exit ============
2200 00:55:54.759674 [ANA_INIT] <<<<<<<<<<<<<
2201 00:55:54.763038 [Flow] Enable top DCM control >>>>>
2202 00:55:54.766503 [Flow] Enable top DCM control <<<<<
2203 00:55:54.769979 Enable DLL master slave shuffle
2204 00:55:54.775946 ==============================================================
2205 00:55:54.776023 Gating Mode config
2206 00:55:54.782698 ==============================================================
2207 00:55:54.782764 Config description:
2208 00:55:54.793280 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2209 00:55:54.799653 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2210 00:55:54.806645 SELPH_MODE 0: By rank 1: By Phase
2211 00:55:54.809405 ==============================================================
2212 00:55:54.812775 GAT_TRACK_EN = 1
2213 00:55:54.815913 RX_GATING_MODE = 2
2214 00:55:54.819619 RX_GATING_TRACK_MODE = 2
2215 00:55:54.823219 SELPH_MODE = 1
2216 00:55:54.826496 PICG_EARLY_EN = 1
2217 00:55:54.829535 VALID_LAT_VALUE = 1
2218 00:55:54.832935 ==============================================================
2219 00:55:54.836216 Enter into Gating configuration >>>>
2220 00:55:54.839587 Exit from Gating configuration <<<<
2221 00:55:54.842669 Enter into DVFS_PRE_config >>>>>
2222 00:55:54.856065 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2223 00:55:54.859605 Exit from DVFS_PRE_config <<<<<
2224 00:55:54.859677 Enter into PICG configuration >>>>
2225 00:55:54.862984 Exit from PICG configuration <<<<
2226 00:55:54.866319 [RX_INPUT] configuration >>>>>
2227 00:55:54.869811 [RX_INPUT] configuration <<<<<
2228 00:55:54.876548 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2229 00:55:54.880105 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2230 00:55:54.886186 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 00:55:54.892946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 00:55:54.899628 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 00:55:54.906542 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 00:55:54.910014 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2235 00:55:54.913255 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2236 00:55:54.916336 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2237 00:55:54.923218 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2238 00:55:54.926647 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2239 00:55:54.930120 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2240 00:55:54.933442 ===================================
2241 00:55:54.936669 LPDDR4 DRAM CONFIGURATION
2242 00:55:54.939838 ===================================
2243 00:55:54.939915 EX_ROW_EN[0] = 0x0
2244 00:55:54.943523 EX_ROW_EN[1] = 0x0
2245 00:55:54.943600 LP4Y_EN = 0x0
2246 00:55:54.946639 WORK_FSP = 0x0
2247 00:55:54.946718 WL = 0x4
2248 00:55:54.949896 RL = 0x4
2249 00:55:54.953137 BL = 0x2
2250 00:55:54.953214 RPST = 0x0
2251 00:55:54.956953 RD_PRE = 0x0
2252 00:55:54.957027 WR_PRE = 0x1
2253 00:55:54.960056 WR_PST = 0x0
2254 00:55:54.960121 DBI_WR = 0x0
2255 00:55:54.963602 DBI_RD = 0x0
2256 00:55:54.963669 OTF = 0x1
2257 00:55:54.966465 ===================================
2258 00:55:54.970024 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2259 00:55:54.973354 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2260 00:55:54.980242 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 00:55:54.983627 ===================================
2262 00:55:54.987168 LPDDR4 DRAM CONFIGURATION
2263 00:55:54.989808 ===================================
2264 00:55:54.989873 EX_ROW_EN[0] = 0x10
2265 00:55:54.993253 EX_ROW_EN[1] = 0x0
2266 00:55:54.993315 LP4Y_EN = 0x0
2267 00:55:54.996619 WORK_FSP = 0x0
2268 00:55:54.996679 WL = 0x4
2269 00:55:55.000131 RL = 0x4
2270 00:55:55.000193 BL = 0x2
2271 00:55:55.003494 RPST = 0x0
2272 00:55:55.003569 RD_PRE = 0x0
2273 00:55:55.006580 WR_PRE = 0x1
2274 00:55:55.006655 WR_PST = 0x0
2275 00:55:55.009816 DBI_WR = 0x0
2276 00:55:55.009891 DBI_RD = 0x0
2277 00:55:55.013730 OTF = 0x1
2278 00:55:55.017063 ===================================
2279 00:55:55.023662 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2280 00:55:55.023737 ==
2281 00:55:55.027052 Dram Type= 6, Freq= 0, CH_0, rank 0
2282 00:55:55.029884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2283 00:55:55.029960 ==
2284 00:55:55.034002 [Duty_Offset_Calibration]
2285 00:55:55.034100 B0:2 B1:1 CA:1
2286 00:55:55.034183
2287 00:55:55.036694 [DutyScan_Calibration_Flow] k_type=0
2288 00:55:55.047106
2289 00:55:55.047180 ==CLK 0==
2290 00:55:55.050361 Final CLK duty delay cell = 0
2291 00:55:55.053738 [0] MAX Duty = 5218%(X100), DQS PI = 24
2292 00:55:55.056986 [0] MIN Duty = 4844%(X100), DQS PI = 48
2293 00:55:55.057053 [0] AVG Duty = 5031%(X100)
2294 00:55:55.060327
2295 00:55:55.063726 CH0 CLK Duty spec in!! Max-Min= 374%
2296 00:55:55.067172 [DutyScan_Calibration_Flow] ====Done====
2297 00:55:55.067237
2298 00:55:55.070556 [DutyScan_Calibration_Flow] k_type=1
2299 00:55:55.086195
2300 00:55:55.086275 ==DQS 0 ==
2301 00:55:55.089314 Final DQS duty delay cell = -4
2302 00:55:55.092305 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2303 00:55:55.095610 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2304 00:55:55.099268 [-4] AVG Duty = 4937%(X100)
2305 00:55:55.099343
2306 00:55:55.099400 ==DQS 1 ==
2307 00:55:55.102685 Final DQS duty delay cell = 0
2308 00:55:55.106127 [0] MAX Duty = 5156%(X100), DQS PI = 14
2309 00:55:55.109474 [0] MIN Duty = 5000%(X100), DQS PI = 32
2310 00:55:55.112780 [0] AVG Duty = 5078%(X100)
2311 00:55:55.112855
2312 00:55:55.116077 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2313 00:55:55.116151
2314 00:55:55.119207 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2315 00:55:55.122540 [DutyScan_Calibration_Flow] ====Done====
2316 00:55:55.122615
2317 00:55:55.125841 [DutyScan_Calibration_Flow] k_type=3
2318 00:55:55.142722
2319 00:55:55.142797 ==DQM 0 ==
2320 00:55:55.146131 Final DQM duty delay cell = 0
2321 00:55:55.149404 [0] MAX Duty = 5156%(X100), DQS PI = 30
2322 00:55:55.152668 [0] MIN Duty = 4906%(X100), DQS PI = 50
2323 00:55:55.152743 [0] AVG Duty = 5031%(X100)
2324 00:55:55.155768
2325 00:55:55.155842 ==DQM 1 ==
2326 00:55:55.159531 Final DQM duty delay cell = 0
2327 00:55:55.162707 [0] MAX Duty = 5093%(X100), DQS PI = 0
2328 00:55:55.166078 [0] MIN Duty = 5031%(X100), DQS PI = 14
2329 00:55:55.166153 [0] AVG Duty = 5062%(X100)
2330 00:55:55.169319
2331 00:55:55.172827 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2332 00:55:55.172900
2333 00:55:55.175601 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2334 00:55:55.179374 [DutyScan_Calibration_Flow] ====Done====
2335 00:55:55.179448
2336 00:55:55.182159 [DutyScan_Calibration_Flow] k_type=2
2337 00:55:55.199526
2338 00:55:55.199621 ==DQ 0 ==
2339 00:55:55.202868 Final DQ duty delay cell = 0
2340 00:55:55.206026 [0] MAX Duty = 5031%(X100), DQS PI = 26
2341 00:55:55.209128 [0] MIN Duty = 4875%(X100), DQS PI = 0
2342 00:55:55.209202 [0] AVG Duty = 4953%(X100)
2343 00:55:55.209259
2344 00:55:55.212293 ==DQ 1 ==
2345 00:55:55.215732 Final DQ duty delay cell = 0
2346 00:55:55.219165 [0] MAX Duty = 5093%(X100), DQS PI = 24
2347 00:55:55.222549 [0] MIN Duty = 4938%(X100), DQS PI = 36
2348 00:55:55.222623 [0] AVG Duty = 5015%(X100)
2349 00:55:55.222689
2350 00:55:55.225944 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2351 00:55:55.226017
2352 00:55:55.229118 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2353 00:55:55.236055 [DutyScan_Calibration_Flow] ====Done====
2354 00:55:55.236150 ==
2355 00:55:55.239507 Dram Type= 6, Freq= 0, CH_1, rank 0
2356 00:55:55.243042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 00:55:55.243116 ==
2358 00:55:55.246395 [Duty_Offset_Calibration]
2359 00:55:55.246476 B0:1 B1:0 CA:0
2360 00:55:55.246534
2361 00:55:55.249250 [DutyScan_Calibration_Flow] k_type=0
2362 00:55:55.258090
2363 00:55:55.258163 ==CLK 0==
2364 00:55:55.262149 Final CLK duty delay cell = -4
2365 00:55:55.264889 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2366 00:55:55.268678 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2367 00:55:55.271896 [-4] AVG Duty = 4937%(X100)
2368 00:55:55.271970
2369 00:55:55.275225 CH1 CLK Duty spec in!! Max-Min= 125%
2370 00:55:55.278558 [DutyScan_Calibration_Flow] ====Done====
2371 00:55:55.278628
2372 00:55:55.281809 [DutyScan_Calibration_Flow] k_type=1
2373 00:55:55.298086
2374 00:55:55.298161 ==DQS 0 ==
2375 00:55:55.301490 Final DQS duty delay cell = 0
2376 00:55:55.304813 [0] MAX Duty = 5062%(X100), DQS PI = 22
2377 00:55:55.307974 [0] MIN Duty = 4844%(X100), DQS PI = 0
2378 00:55:55.308050 [0] AVG Duty = 4953%(X100)
2379 00:55:55.311657
2380 00:55:55.311761 ==DQS 1 ==
2381 00:55:55.314889 Final DQS duty delay cell = 0
2382 00:55:55.318141 [0] MAX Duty = 5218%(X100), DQS PI = 18
2383 00:55:55.321275 [0] MIN Duty = 4969%(X100), DQS PI = 8
2384 00:55:55.321357 [0] AVG Duty = 5093%(X100)
2385 00:55:55.321416
2386 00:55:55.328570 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2387 00:55:55.328646
2388 00:55:55.331974 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2389 00:55:55.334697 [DutyScan_Calibration_Flow] ====Done====
2390 00:55:55.334767
2391 00:55:55.338055 [DutyScan_Calibration_Flow] k_type=3
2392 00:55:55.355034
2393 00:55:55.355107 ==DQM 0 ==
2394 00:55:55.358401 Final DQM duty delay cell = 0
2395 00:55:55.361105 [0] MAX Duty = 5156%(X100), DQS PI = 8
2396 00:55:55.364974 [0] MIN Duty = 5000%(X100), DQS PI = 0
2397 00:55:55.365041 [0] AVG Duty = 5078%(X100)
2398 00:55:55.365100
2399 00:55:55.367620 ==DQM 1 ==
2400 00:55:55.371065 Final DQM duty delay cell = 0
2401 00:55:55.375061 [0] MAX Duty = 5031%(X100), DQS PI = 26
2402 00:55:55.378284 [0] MIN Duty = 4875%(X100), DQS PI = 36
2403 00:55:55.378350 [0] AVG Duty = 4953%(X100)
2404 00:55:55.381483
2405 00:55:55.384928 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2406 00:55:55.384994
2407 00:55:55.388141 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2408 00:55:55.391536 [DutyScan_Calibration_Flow] ====Done====
2409 00:55:55.391601
2410 00:55:55.394335 [DutyScan_Calibration_Flow] k_type=2
2411 00:55:55.410775
2412 00:55:55.410844 ==DQ 0 ==
2413 00:55:55.414038 Final DQ duty delay cell = -4
2414 00:55:55.417220 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2415 00:55:55.420391 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2416 00:55:55.423650 [-4] AVG Duty = 4984%(X100)
2417 00:55:55.423738
2418 00:55:55.423818 ==DQ 1 ==
2419 00:55:55.427064 Final DQ duty delay cell = 0
2420 00:55:55.430416 [0] MAX Duty = 5125%(X100), DQS PI = 20
2421 00:55:55.433727 [0] MIN Duty = 4938%(X100), DQS PI = 34
2422 00:55:55.433802 [0] AVG Duty = 5031%(X100)
2423 00:55:55.433860
2424 00:55:55.440627 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2425 00:55:55.440702
2426 00:55:55.444211 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2427 00:55:55.447147 [DutyScan_Calibration_Flow] ====Done====
2428 00:55:55.450637 nWR fixed to 30
2429 00:55:55.450710 [ModeRegInit_LP4] CH0 RK0
2430 00:55:55.453816 [ModeRegInit_LP4] CH0 RK1
2431 00:55:55.457230 [ModeRegInit_LP4] CH1 RK0
2432 00:55:55.460563 [ModeRegInit_LP4] CH1 RK1
2433 00:55:55.460630 match AC timing 7
2434 00:55:55.463949 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2435 00:55:55.470612 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2436 00:55:55.473935 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2437 00:55:55.477296 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2438 00:55:55.483841 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2439 00:55:55.483908 ==
2440 00:55:55.487005 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 00:55:55.490472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 00:55:55.490537 ==
2443 00:55:55.497180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2444 00:55:55.503976 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2445 00:55:55.510704 [CA 0] Center 39 (8~70) winsize 63
2446 00:55:55.514035 [CA 1] Center 39 (8~70) winsize 63
2447 00:55:55.517368 [CA 2] Center 35 (5~66) winsize 62
2448 00:55:55.520840 [CA 3] Center 34 (4~65) winsize 62
2449 00:55:55.524160 [CA 4] Center 33 (3~64) winsize 62
2450 00:55:55.527349 [CA 5] Center 32 (3~62) winsize 60
2451 00:55:55.527424
2452 00:55:55.530600 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2453 00:55:55.530675
2454 00:55:55.533876 [CATrainingPosCal] consider 1 rank data
2455 00:55:55.537266 u2DelayCellTimex100 = 270/100 ps
2456 00:55:55.540657 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2457 00:55:55.544036 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2458 00:55:55.550763 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2459 00:55:55.553956 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2460 00:55:55.557727 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2461 00:55:55.560843 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2462 00:55:55.560912
2463 00:55:55.563834 CA PerBit enable=1, Macro0, CA PI delay=32
2464 00:55:55.563902
2465 00:55:55.567386 [CBTSetCACLKResult] CA Dly = 32
2466 00:55:55.567480 CS Dly: 6 (0~37)
2467 00:55:55.567569 ==
2468 00:55:55.570839 Dram Type= 6, Freq= 0, CH_0, rank 1
2469 00:55:55.577459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 00:55:55.577559 ==
2471 00:55:55.580780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 00:55:55.587365 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2473 00:55:55.596614 [CA 0] Center 38 (8~69) winsize 62
2474 00:55:55.599974 [CA 1] Center 38 (8~69) winsize 62
2475 00:55:55.603236 [CA 2] Center 35 (4~66) winsize 63
2476 00:55:55.606638 [CA 3] Center 34 (4~65) winsize 62
2477 00:55:55.609505 [CA 4] Center 33 (3~64) winsize 62
2478 00:55:55.612941 [CA 5] Center 32 (2~62) winsize 61
2479 00:55:55.613007
2480 00:55:55.616359 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2481 00:55:55.616423
2482 00:55:55.619817 [CATrainingPosCal] consider 2 rank data
2483 00:55:55.623348 u2DelayCellTimex100 = 270/100 ps
2484 00:55:55.626798 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2485 00:55:55.630085 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2486 00:55:55.636550 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2487 00:55:55.640019 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2488 00:55:55.643425 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2489 00:55:55.646586 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2490 00:55:55.646709
2491 00:55:55.649926 CA PerBit enable=1, Macro0, CA PI delay=32
2492 00:55:55.650068
2493 00:55:55.653201 [CBTSetCACLKResult] CA Dly = 32
2494 00:55:55.653355 CS Dly: 6 (0~38)
2495 00:55:55.653457
2496 00:55:55.656588 ----->DramcWriteLeveling(PI) begin...
2497 00:55:55.656699 ==
2498 00:55:55.659930 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 00:55:55.667058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 00:55:55.667177 ==
2501 00:55:55.669745 Write leveling (Byte 0): 32 => 32
2502 00:55:55.673043 Write leveling (Byte 1): 28 => 28
2503 00:55:55.673178 DramcWriteLeveling(PI) end<-----
2504 00:55:55.676384
2505 00:55:55.676507 ==
2506 00:55:55.680280 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 00:55:55.683277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 00:55:55.683380 ==
2509 00:55:55.686781 [Gating] SW mode calibration
2510 00:55:55.693284 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2511 00:55:55.696783 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2512 00:55:55.703428 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2513 00:55:55.706394 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2514 00:55:55.710104 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 00:55:55.716739 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 00:55:55.720143 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 00:55:55.723524 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 00:55:55.729687 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2519 00:55:55.733175 0 15 28 | B1->B0 | 3333 2323 | 1 0 | (1 1) (1 0)
2520 00:55:55.736696 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2521 00:55:55.743193 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 00:55:55.746657 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 00:55:55.750027 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 00:55:55.753572 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 00:55:55.760051 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 00:55:55.763374 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2527 00:55:55.766793 1 0 28 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
2528 00:55:55.773666 1 1 0 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
2529 00:55:55.776601 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 00:55:55.779840 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 00:55:55.786670 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 00:55:55.790176 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 00:55:55.793462 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 00:55:55.800335 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 00:55:55.803798 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2536 00:55:55.807145 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2537 00:55:55.813798 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 00:55:55.816706 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 00:55:55.820145 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 00:55:55.826826 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 00:55:55.830045 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 00:55:55.833376 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 00:55:55.836790 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 00:55:55.843491 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 00:55:55.847149 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 00:55:55.850475 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 00:55:55.857206 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 00:55:55.860646 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 00:55:55.864015 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 00:55:55.870721 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:55:55.873467 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2552 00:55:55.876913 Total UI for P1: 0, mck2ui 16
2553 00:55:55.881108 best dqsien dly found for B0: ( 1, 3, 26)
2554 00:55:55.883823 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2555 00:55:55.890611 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 00:55:55.890744 Total UI for P1: 0, mck2ui 16
2557 00:55:55.894049 best dqsien dly found for B1: ( 1, 3, 30)
2558 00:55:55.900777 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2559 00:55:55.904161 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2560 00:55:55.904307
2561 00:55:55.907597 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2562 00:55:55.910944 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2563 00:55:55.913765 [Gating] SW calibration Done
2564 00:55:55.913910 ==
2565 00:55:55.917113 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 00:55:55.920461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 00:55:55.920567 ==
2568 00:55:55.920653 RX Vref Scan: 0
2569 00:55:55.923922
2570 00:55:55.924019 RX Vref 0 -> 0, step: 1
2571 00:55:55.924111
2572 00:55:55.927217 RX Delay -40 -> 252, step: 8
2573 00:55:55.930560 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2574 00:55:55.934115 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2575 00:55:55.940854 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2576 00:55:55.944052 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2577 00:55:55.947308 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2578 00:55:55.950424 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2579 00:55:55.954005 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2580 00:55:55.960478 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2581 00:55:55.964175 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2582 00:55:55.967556 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2583 00:55:55.970472 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2584 00:55:55.974043 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2585 00:55:55.980975 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2586 00:55:55.983868 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2587 00:55:55.987591 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2588 00:55:55.990710 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2589 00:55:55.990813 ==
2590 00:55:55.994017 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 00:55:55.997894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 00:55:56.000573 ==
2593 00:55:56.000727 DQS Delay:
2594 00:55:56.000885 DQS0 = 0, DQS1 = 0
2595 00:55:56.004129 DQM Delay:
2596 00:55:56.004282 DQM0 = 121, DQM1 = 113
2597 00:55:56.007561 DQ Delay:
2598 00:55:56.010979 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2599 00:55:56.014489 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2600 00:55:56.017793 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2601 00:55:56.021033 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2602 00:55:56.021150
2603 00:55:56.021240
2604 00:55:56.021321 ==
2605 00:55:56.024284 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 00:55:56.027888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 00:55:56.027964 ==
2608 00:55:56.028034
2609 00:55:56.028130
2610 00:55:56.030633 TX Vref Scan disable
2611 00:55:56.034012 == TX Byte 0 ==
2612 00:55:56.037449 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2613 00:55:56.040813 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2614 00:55:56.044337 == TX Byte 1 ==
2615 00:55:56.047816 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2616 00:55:56.051171 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2617 00:55:56.051249 ==
2618 00:55:56.054018 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 00:55:56.057470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 00:55:56.060880 ==
2621 00:55:56.071195 TX Vref=22, minBit 0, minWin=25, winSum=407
2622 00:55:56.074770 TX Vref=24, minBit 0, minWin=25, winSum=413
2623 00:55:56.078032 TX Vref=26, minBit 1, minWin=25, winSum=421
2624 00:55:56.081215 TX Vref=28, minBit 1, minWin=26, winSum=423
2625 00:55:56.084655 TX Vref=30, minBit 0, minWin=26, winSum=428
2626 00:55:56.087845 TX Vref=32, minBit 0, minWin=26, winSum=424
2627 00:55:56.094942 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
2628 00:55:56.095055
2629 00:55:56.098218 Final TX Range 1 Vref 30
2630 00:55:56.098311
2631 00:55:56.098394 ==
2632 00:55:56.101458 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 00:55:56.104558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 00:55:56.104652 ==
2635 00:55:56.104735
2636 00:55:56.104817
2637 00:55:56.108170 TX Vref Scan disable
2638 00:55:56.111454 == TX Byte 0 ==
2639 00:55:56.114774 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2640 00:55:56.117922 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2641 00:55:56.121578 == TX Byte 1 ==
2642 00:55:56.124549 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2643 00:55:56.128229 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2644 00:55:56.128326
2645 00:55:56.131310 [DATLAT]
2646 00:55:56.131378 Freq=1200, CH0 RK0
2647 00:55:56.131435
2648 00:55:56.134646 DATLAT Default: 0xd
2649 00:55:56.134714 0, 0xFFFF, sum = 0
2650 00:55:56.137993 1, 0xFFFF, sum = 0
2651 00:55:56.138089 2, 0xFFFF, sum = 0
2652 00:55:56.141441 3, 0xFFFF, sum = 0
2653 00:55:56.141508 4, 0xFFFF, sum = 0
2654 00:55:56.144695 5, 0xFFFF, sum = 0
2655 00:55:56.144760 6, 0xFFFF, sum = 0
2656 00:55:56.148182 7, 0xFFFF, sum = 0
2657 00:55:56.148248 8, 0xFFFF, sum = 0
2658 00:55:56.151877 9, 0xFFFF, sum = 0
2659 00:55:56.151942 10, 0xFFFF, sum = 0
2660 00:55:56.154483 11, 0xFFFF, sum = 0
2661 00:55:56.154549 12, 0x0, sum = 1
2662 00:55:56.157990 13, 0x0, sum = 2
2663 00:55:56.158057 14, 0x0, sum = 3
2664 00:55:56.161316 15, 0x0, sum = 4
2665 00:55:56.161406 best_step = 13
2666 00:55:56.161485
2667 00:55:56.161611 ==
2668 00:55:56.164870 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 00:55:56.171358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 00:55:56.171445 ==
2671 00:55:56.171506 RX Vref Scan: 1
2672 00:55:56.171561
2673 00:55:56.174754 Set Vref Range= 32 -> 127
2674 00:55:56.174833
2675 00:55:56.178245 RX Vref 32 -> 127, step: 1
2676 00:55:56.178324
2677 00:55:56.181695 RX Delay -13 -> 252, step: 4
2678 00:55:56.181776
2679 00:55:56.181836 Set Vref, RX VrefLevel [Byte0]: 32
2680 00:55:56.184981 [Byte1]: 32
2681 00:55:56.189590
2682 00:55:56.189682 Set Vref, RX VrefLevel [Byte0]: 33
2683 00:55:56.193001 [Byte1]: 33
2684 00:55:56.197665
2685 00:55:56.197749 Set Vref, RX VrefLevel [Byte0]: 34
2686 00:55:56.200836 [Byte1]: 34
2687 00:55:56.205544
2688 00:55:56.205653 Set Vref, RX VrefLevel [Byte0]: 35
2689 00:55:56.208459 [Byte1]: 35
2690 00:55:56.213200
2691 00:55:56.213277 Set Vref, RX VrefLevel [Byte0]: 36
2692 00:55:56.216669 [Byte1]: 36
2693 00:55:56.221275
2694 00:55:56.221352 Set Vref, RX VrefLevel [Byte0]: 37
2695 00:55:56.224171 [Byte1]: 37
2696 00:55:56.229218
2697 00:55:56.229295 Set Vref, RX VrefLevel [Byte0]: 38
2698 00:55:56.232325 [Byte1]: 38
2699 00:55:56.236872
2700 00:55:56.236961 Set Vref, RX VrefLevel [Byte0]: 39
2701 00:55:56.240178 [Byte1]: 39
2702 00:55:56.244591
2703 00:55:56.244710 Set Vref, RX VrefLevel [Byte0]: 40
2704 00:55:56.247882 [Byte1]: 40
2705 00:55:56.252616
2706 00:55:56.252730 Set Vref, RX VrefLevel [Byte0]: 41
2707 00:55:56.255981 [Byte1]: 41
2708 00:55:56.260740
2709 00:55:56.260887 Set Vref, RX VrefLevel [Byte0]: 42
2710 00:55:56.266894 [Byte1]: 42
2711 00:55:56.267055
2712 00:55:56.270430 Set Vref, RX VrefLevel [Byte0]: 43
2713 00:55:56.273928 [Byte1]: 43
2714 00:55:56.274116
2715 00:55:56.277187 Set Vref, RX VrefLevel [Byte0]: 44
2716 00:55:56.280536 [Byte1]: 44
2717 00:55:56.284775
2718 00:55:56.285106 Set Vref, RX VrefLevel [Byte0]: 45
2719 00:55:56.287650 [Byte1]: 45
2720 00:55:56.292175
2721 00:55:56.292584 Set Vref, RX VrefLevel [Byte0]: 46
2722 00:55:56.295464 [Byte1]: 46
2723 00:55:56.299928
2724 00:55:56.300259 Set Vref, RX VrefLevel [Byte0]: 47
2725 00:55:56.303312 [Byte1]: 47
2726 00:55:56.308048
2727 00:55:56.308391 Set Vref, RX VrefLevel [Byte0]: 48
2728 00:55:56.311378 [Byte1]: 48
2729 00:55:56.316293
2730 00:55:56.316624 Set Vref, RX VrefLevel [Byte0]: 49
2731 00:55:56.319081 [Byte1]: 49
2732 00:55:56.323721
2733 00:55:56.324056 Set Vref, RX VrefLevel [Byte0]: 50
2734 00:55:56.327268 [Byte1]: 50
2735 00:55:56.331888
2736 00:55:56.332126 Set Vref, RX VrefLevel [Byte0]: 51
2737 00:55:56.334748 [Byte1]: 51
2738 00:55:56.339404
2739 00:55:56.339643 Set Vref, RX VrefLevel [Byte0]: 52
2740 00:55:56.342764 [Byte1]: 52
2741 00:55:56.347221
2742 00:55:56.347459 Set Vref, RX VrefLevel [Byte0]: 53
2743 00:55:56.350674 [Byte1]: 53
2744 00:55:56.355576
2745 00:55:56.355816 Set Vref, RX VrefLevel [Byte0]: 54
2746 00:55:56.358904 [Byte1]: 54
2747 00:55:56.391395
2748 00:55:56.391576 Set Vref, RX VrefLevel [Byte0]: 55
2749 00:55:56.391698 [Byte1]: 55
2750 00:55:56.391811
2751 00:55:56.391918 Set Vref, RX VrefLevel [Byte0]: 56
2752 00:55:56.392023 [Byte1]: 56
2753 00:55:56.392125
2754 00:55:56.392226 Set Vref, RX VrefLevel [Byte0]: 57
2755 00:55:56.392326 [Byte1]: 57
2756 00:55:56.392425
2757 00:55:56.392524 Set Vref, RX VrefLevel [Byte0]: 58
2758 00:55:56.392625 [Byte1]: 58
2759 00:55:56.394750
2760 00:55:56.394880 Set Vref, RX VrefLevel [Byte0]: 59
2761 00:55:56.397984 [Byte1]: 59
2762 00:55:56.402722
2763 00:55:56.402835 Set Vref, RX VrefLevel [Byte0]: 60
2764 00:55:56.405841 [Byte1]: 60
2765 00:55:56.410275
2766 00:55:56.410364 Set Vref, RX VrefLevel [Byte0]: 61
2767 00:55:56.413842 [Byte1]: 61
2768 00:55:56.418557
2769 00:55:56.418641 Set Vref, RX VrefLevel [Byte0]: 62
2770 00:55:56.421312 [Byte1]: 62
2771 00:55:56.426088
2772 00:55:56.426164 Set Vref, RX VrefLevel [Byte0]: 63
2773 00:55:56.429312 [Byte1]: 63
2774 00:55:56.434204
2775 00:55:56.434280 Set Vref, RX VrefLevel [Byte0]: 64
2776 00:55:56.437706 [Byte1]: 64
2777 00:55:56.441856
2778 00:55:56.441932 Set Vref, RX VrefLevel [Byte0]: 65
2779 00:55:56.445175 [Byte1]: 65
2780 00:55:56.449851
2781 00:55:56.449927 Set Vref, RX VrefLevel [Byte0]: 66
2782 00:55:56.453297 [Byte1]: 66
2783 00:55:56.458050
2784 00:55:56.458125 Set Vref, RX VrefLevel [Byte0]: 67
2785 00:55:56.460805 [Byte1]: 67
2786 00:55:56.465678
2787 00:55:56.465764 Set Vref, RX VrefLevel [Byte0]: 68
2788 00:55:56.468926 [Byte1]: 68
2789 00:55:56.473757
2790 00:55:56.473852 Set Vref, RX VrefLevel [Byte0]: 69
2791 00:55:56.476709 [Byte1]: 69
2792 00:55:56.481517
2793 00:55:56.481710 Final RX Vref Byte 0 = 55 to rank0
2794 00:55:56.484999 Final RX Vref Byte 1 = 46 to rank0
2795 00:55:56.488252 Final RX Vref Byte 0 = 55 to rank1
2796 00:55:56.491686 Final RX Vref Byte 1 = 46 to rank1==
2797 00:55:56.494998 Dram Type= 6, Freq= 0, CH_0, rank 0
2798 00:55:56.501773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2799 00:55:56.501996 ==
2800 00:55:56.502144 DQS Delay:
2801 00:55:56.502282 DQS0 = 0, DQS1 = 0
2802 00:55:56.504877 DQM Delay:
2803 00:55:56.505100 DQM0 = 120, DQM1 = 110
2804 00:55:56.508420 DQ Delay:
2805 00:55:56.511376 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =120
2806 00:55:56.515045 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2807 00:55:56.518673 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =104
2808 00:55:56.521584 DQ12 =116, DQ13 =116, DQ14 =122, DQ15 =120
2809 00:55:56.521921
2810 00:55:56.522179
2811 00:55:56.528407 [DQSOSCAuto] RK0, (LSB)MR18= 0x150e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2812 00:55:56.532037 CH0 RK0: MR19=404, MR18=150E
2813 00:55:56.538597 CH0_RK0: MR19=0x404, MR18=0x150E, DQSOSC=401, MR23=63, INC=40, DEC=27
2814 00:55:56.538959
2815 00:55:56.541917 ----->DramcWriteLeveling(PI) begin...
2816 00:55:56.542354 ==
2817 00:55:56.545132 Dram Type= 6, Freq= 0, CH_0, rank 1
2818 00:55:56.548525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2819 00:55:56.548883 ==
2820 00:55:56.551867 Write leveling (Byte 0): 33 => 33
2821 00:55:56.555188 Write leveling (Byte 1): 29 => 29
2822 00:55:56.558594 DramcWriteLeveling(PI) end<-----
2823 00:55:56.558947
2824 00:55:56.559249 ==
2825 00:55:56.562159 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 00:55:56.568470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 00:55:56.568825 ==
2828 00:55:56.569120 [Gating] SW mode calibration
2829 00:55:56.578790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2830 00:55:56.581652 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2831 00:55:56.585062 0 15 0 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (0 0)
2832 00:55:56.591841 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 00:55:56.595183 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 00:55:56.598606 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 00:55:56.605362 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 00:55:56.608912 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 00:55:56.612205 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
2838 00:55:56.618791 0 15 28 | B1->B0 | 3030 2f2f | 1 1 | (0 1) (0 1)
2839 00:55:56.622293 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 00:55:56.625544 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 00:55:56.631786 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 00:55:56.635257 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 00:55:56.638424 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 00:55:56.642427 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 00:55:56.648887 1 0 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
2846 00:55:56.651842 1 0 28 | B1->B0 | 3a3a 3737 | 0 0 | (0 0) (0 0)
2847 00:55:56.655730 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 00:55:56.662094 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 00:55:56.665054 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 00:55:56.668603 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 00:55:56.675577 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 00:55:56.679031 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 00:55:56.682393 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 00:55:56.688637 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2855 00:55:56.692106 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2856 00:55:56.695667 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 00:55:56.702481 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 00:55:56.705329 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 00:55:56.708724 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 00:55:56.715505 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 00:55:56.718894 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 00:55:56.722278 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 00:55:56.725602 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 00:55:56.732341 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 00:55:56.735873 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 00:55:56.739193 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 00:55:56.745635 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 00:55:56.749045 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 00:55:56.752499 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 00:55:56.759291 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2871 00:55:56.762002 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 00:55:56.766036 Total UI for P1: 0, mck2ui 16
2873 00:55:56.769171 best dqsien dly found for B0: ( 1, 3, 28)
2874 00:55:56.772435 Total UI for P1: 0, mck2ui 16
2875 00:55:56.775617 best dqsien dly found for B1: ( 1, 3, 28)
2876 00:55:56.779554 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2877 00:55:56.782633 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2878 00:55:56.782989
2879 00:55:56.785894 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2880 00:55:56.789493 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2881 00:55:56.792294 [Gating] SW calibration Done
2882 00:55:56.792649 ==
2883 00:55:56.795857 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 00:55:56.799234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 00:55:56.799595 ==
2886 00:55:56.802708 RX Vref Scan: 0
2887 00:55:56.803063
2888 00:55:56.805408 RX Vref 0 -> 0, step: 1
2889 00:55:56.805790
2890 00:55:56.806065 RX Delay -40 -> 252, step: 8
2891 00:55:56.812276 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2892 00:55:56.815585 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2893 00:55:56.818996 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2894 00:55:56.822575 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2895 00:55:56.825389 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2896 00:55:56.832063 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2897 00:55:56.835373 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2898 00:55:56.838840 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2899 00:55:56.842250 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2900 00:55:56.845627 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2901 00:55:56.852095 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2902 00:55:56.855359 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2903 00:55:56.858847 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2904 00:55:56.862313 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2905 00:55:56.868484 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2906 00:55:56.871931 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2907 00:55:56.872287 ==
2908 00:55:56.875302 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 00:55:56.878898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 00:55:56.879254 ==
2911 00:55:56.879531 DQS Delay:
2912 00:55:56.882294 DQS0 = 0, DQS1 = 0
2913 00:55:56.882648 DQM Delay:
2914 00:55:56.885784 DQM0 = 121, DQM1 = 112
2915 00:55:56.886138 DQ Delay:
2916 00:55:56.888481 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2917 00:55:56.892091 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2918 00:55:56.895298 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2919 00:55:56.898826 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2920 00:55:56.899165
2921 00:55:56.902152
2922 00:55:56.902453 ==
2923 00:55:56.905387 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 00:55:56.909126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 00:55:56.909446 ==
2926 00:55:56.909756
2927 00:55:56.910004
2928 00:55:56.911973 TX Vref Scan disable
2929 00:55:56.912283 == TX Byte 0 ==
2930 00:55:56.919132 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2931 00:55:56.921968 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2932 00:55:56.922323 == TX Byte 1 ==
2933 00:55:56.928793 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2934 00:55:56.932236 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2935 00:55:56.932594 ==
2936 00:55:56.935063 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 00:55:56.938446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 00:55:56.938805 ==
2939 00:55:56.951319 TX Vref=22, minBit 1, minWin=25, winSum=411
2940 00:55:56.954561 TX Vref=24, minBit 3, minWin=25, winSum=416
2941 00:55:56.957912 TX Vref=26, minBit 1, minWin=25, winSum=420
2942 00:55:56.960962 TX Vref=28, minBit 1, minWin=26, winSum=425
2943 00:55:56.964257 TX Vref=30, minBit 1, minWin=26, winSum=426
2944 00:55:56.971209 TX Vref=32, minBit 0, minWin=26, winSum=423
2945 00:55:56.974678 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 30
2946 00:55:56.975035
2947 00:55:56.977918 Final TX Range 1 Vref 30
2948 00:55:56.978273
2949 00:55:56.978549 ==
2950 00:55:56.980760 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 00:55:56.984125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 00:55:56.984596 ==
2953 00:55:56.987462
2954 00:55:56.987959
2955 00:55:56.988251 TX Vref Scan disable
2956 00:55:56.990893 == TX Byte 0 ==
2957 00:55:56.994319 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2958 00:55:56.997750 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2959 00:55:57.001231 == TX Byte 1 ==
2960 00:55:57.004622 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2961 00:55:57.007486 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2962 00:55:57.010910
2963 00:55:57.011383 [DATLAT]
2964 00:55:57.011701 Freq=1200, CH0 RK1
2965 00:55:57.012132
2966 00:55:57.014277 DATLAT Default: 0xd
2967 00:55:57.014649 0, 0xFFFF, sum = 0
2968 00:55:57.018005 1, 0xFFFF, sum = 0
2969 00:55:57.018340 2, 0xFFFF, sum = 0
2970 00:55:57.020675 3, 0xFFFF, sum = 0
2971 00:55:57.020890 4, 0xFFFF, sum = 0
2972 00:55:57.023950 5, 0xFFFF, sum = 0
2973 00:55:57.027842 6, 0xFFFF, sum = 0
2974 00:55:57.028179 7, 0xFFFF, sum = 0
2975 00:55:57.031127 8, 0xFFFF, sum = 0
2976 00:55:57.031336 9, 0xFFFF, sum = 0
2977 00:55:57.034214 10, 0xFFFF, sum = 0
2978 00:55:57.034383 11, 0xFFFF, sum = 0
2979 00:55:57.037304 12, 0x0, sum = 1
2980 00:55:57.037471 13, 0x0, sum = 2
2981 00:55:57.040705 14, 0x0, sum = 3
2982 00:55:57.040824 15, 0x0, sum = 4
2983 00:55:57.040906 best_step = 13
2984 00:55:57.044228
2985 00:55:57.044340 ==
2986 00:55:57.047076 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 00:55:57.050640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 00:55:57.050727 ==
2989 00:55:57.050792 RX Vref Scan: 0
2990 00:55:57.050852
2991 00:55:57.053853 RX Vref 0 -> 0, step: 1
2992 00:55:57.053936
2993 00:55:57.057047 RX Delay -13 -> 252, step: 4
2994 00:55:57.060381 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
2995 00:55:57.067571 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2996 00:55:57.070788 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2997 00:55:57.074309 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2998 00:55:57.077121 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
2999 00:55:57.080602 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3000 00:55:57.087616 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3001 00:55:57.090779 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3002 00:55:57.094151 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3003 00:55:57.097765 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3004 00:55:57.100987 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3005 00:55:57.104299 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3006 00:55:57.110794 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3007 00:55:57.114347 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3008 00:55:57.117749 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3009 00:55:57.120493 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3010 00:55:57.120653 ==
3011 00:55:57.123880 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 00:55:57.130813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 00:55:57.131035 ==
3014 00:55:57.131206 DQS Delay:
3015 00:55:57.134191 DQS0 = 0, DQS1 = 0
3016 00:55:57.134459 DQM Delay:
3017 00:55:57.137062 DQM0 = 121, DQM1 = 109
3018 00:55:57.137308 DQ Delay:
3019 00:55:57.140595 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3020 00:55:57.144050 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3021 00:55:57.147369 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3022 00:55:57.150732 DQ12 =114, DQ13 =116, DQ14 =118, DQ15 =118
3023 00:55:57.151247
3024 00:55:57.151676
3025 00:55:57.160669 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 402 ps
3026 00:55:57.161102 CH0 RK1: MR19=403, MR18=13F3
3027 00:55:57.167200 CH0_RK1: MR19=0x403, MR18=0x13F3, DQSOSC=402, MR23=63, INC=40, DEC=27
3028 00:55:57.170540 [RxdqsGatingPostProcess] freq 1200
3029 00:55:57.177434 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3030 00:55:57.180504 best DQS0 dly(2T, 0.5T) = (0, 11)
3031 00:55:57.183951 best DQS1 dly(2T, 0.5T) = (0, 11)
3032 00:55:57.187118 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3033 00:55:57.190392 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3034 00:55:57.193418 best DQS0 dly(2T, 0.5T) = (0, 11)
3035 00:55:57.197268 best DQS1 dly(2T, 0.5T) = (0, 11)
3036 00:55:57.200586 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3037 00:55:57.203991 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3038 00:55:57.204392 Pre-setting of DQS Precalculation
3039 00:55:57.210322 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3040 00:55:57.210728 ==
3041 00:55:57.213831 Dram Type= 6, Freq= 0, CH_1, rank 0
3042 00:55:57.217286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 00:55:57.217715 ==
3044 00:55:57.223595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3045 00:55:57.230293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3046 00:55:57.237942 [CA 0] Center 37 (7~68) winsize 62
3047 00:55:57.240905 [CA 1] Center 37 (7~68) winsize 62
3048 00:55:57.244158 [CA 2] Center 35 (5~65) winsize 61
3049 00:55:57.247532 [CA 3] Center 34 (4~65) winsize 62
3050 00:55:57.250906 [CA 4] Center 34 (4~64) winsize 61
3051 00:55:57.254326 [CA 5] Center 33 (3~63) winsize 61
3052 00:55:57.254732
3053 00:55:57.257652 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3054 00:55:57.258043
3055 00:55:57.261167 [CATrainingPosCal] consider 1 rank data
3056 00:55:57.264125 u2DelayCellTimex100 = 270/100 ps
3057 00:55:57.267493 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3058 00:55:57.274001 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3059 00:55:57.277691 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3060 00:55:57.280595 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3061 00:55:57.283960 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3062 00:55:57.287239 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3063 00:55:57.287632
3064 00:55:57.290920 CA PerBit enable=1, Macro0, CA PI delay=33
3065 00:55:57.291310
3066 00:55:57.293708 [CBTSetCACLKResult] CA Dly = 33
3067 00:55:57.294172 CS Dly: 6 (0~37)
3068 00:55:57.297093 ==
3069 00:55:57.300570 Dram Type= 6, Freq= 0, CH_1, rank 1
3070 00:55:57.303926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 00:55:57.304385 ==
3072 00:55:57.307282 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 00:55:57.314003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3074 00:55:57.323331 [CA 0] Center 37 (7~68) winsize 62
3075 00:55:57.326533 [CA 1] Center 37 (7~68) winsize 62
3076 00:55:57.329873 [CA 2] Center 35 (5~65) winsize 61
3077 00:55:57.333306 [CA 3] Center 34 (4~65) winsize 62
3078 00:55:57.336693 [CA 4] Center 34 (4~65) winsize 62
3079 00:55:57.340065 [CA 5] Center 34 (4~64) winsize 61
3080 00:55:57.340502
3081 00:55:57.343600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3082 00:55:57.343989
3083 00:55:57.346208 [CATrainingPosCal] consider 2 rank data
3084 00:55:57.349579 u2DelayCellTimex100 = 270/100 ps
3085 00:55:57.353002 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 00:55:57.356381 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 00:55:57.363200 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3088 00:55:57.366654 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3089 00:55:57.370014 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 00:55:57.373523 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3091 00:55:57.373953
3092 00:55:57.376806 CA PerBit enable=1, Macro0, CA PI delay=33
3093 00:55:57.377194
3094 00:55:57.380050 [CBTSetCACLKResult] CA Dly = 33
3095 00:55:57.380446 CS Dly: 8 (0~41)
3096 00:55:57.380809
3097 00:55:57.383341 ----->DramcWriteLeveling(PI) begin...
3098 00:55:57.386606 ==
3099 00:55:57.390046 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 00:55:57.393525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 00:55:57.394024 ==
3102 00:55:57.396391 Write leveling (Byte 0): 26 => 26
3103 00:55:57.399656 Write leveling (Byte 1): 28 => 28
3104 00:55:57.403030 DramcWriteLeveling(PI) end<-----
3105 00:55:57.403423
3106 00:55:57.403723 ==
3107 00:55:57.406488 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 00:55:57.409801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 00:55:57.410199 ==
3110 00:55:57.413143 [Gating] SW mode calibration
3111 00:55:57.419857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3112 00:55:57.426406 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3113 00:55:57.429518 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 00:55:57.433003 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 00:55:57.439910 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 00:55:57.442682 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 00:55:57.446295 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 00:55:57.449513 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 00:55:57.456402 0 15 24 | B1->B0 | 3333 2828 | 1 0 | (1 0) (0 1)
3120 00:55:57.459693 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3121 00:55:57.462886 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 00:55:57.469460 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 00:55:57.472864 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 00:55:57.476324 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 00:55:57.482893 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 00:55:57.486201 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3127 00:55:57.489815 1 0 24 | B1->B0 | 3636 4444 | 0 0 | (0 0) (1 1)
3128 00:55:57.496302 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 00:55:57.499932 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 00:55:57.503246 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 00:55:57.509442 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 00:55:57.512879 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 00:55:57.516192 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 00:55:57.522672 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 00:55:57.526106 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3136 00:55:57.529684 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3137 00:55:57.533079 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 00:55:57.539335 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 00:55:57.542632 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 00:55:57.546047 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 00:55:57.552808 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 00:55:57.556030 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 00:55:57.559171 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 00:55:57.566140 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 00:55:57.569200 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 00:55:57.572785 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 00:55:57.579522 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 00:55:57.582940 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 00:55:57.586117 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 00:55:57.592146 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3151 00:55:57.596048 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3152 00:55:57.599266 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3153 00:55:57.605919 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 00:55:57.606291 Total UI for P1: 0, mck2ui 16
3155 00:55:57.612881 best dqsien dly found for B0: ( 1, 3, 24)
3156 00:55:57.613285 Total UI for P1: 0, mck2ui 16
3157 00:55:57.618910 best dqsien dly found for B1: ( 1, 3, 26)
3158 00:55:57.622436 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3159 00:55:57.625862 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3160 00:55:57.626249
3161 00:55:57.629137 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3162 00:55:57.632560 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3163 00:55:57.635969 [Gating] SW calibration Done
3164 00:55:57.636356 ==
3165 00:55:57.642058 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 00:55:57.642847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 00:55:57.643199 ==
3168 00:55:57.646149 RX Vref Scan: 0
3169 00:55:57.646548
3170 00:55:57.646855 RX Vref 0 -> 0, step: 1
3171 00:55:57.647148
3172 00:55:57.649622 RX Delay -40 -> 252, step: 8
3173 00:55:57.652456 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3174 00:55:57.659286 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3175 00:55:57.662497 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3176 00:55:57.665713 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3177 00:55:57.668961 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3178 00:55:57.672261 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3179 00:55:57.679216 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3180 00:55:57.682632 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3181 00:55:57.685715 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3182 00:55:57.689119 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3183 00:55:57.692344 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3184 00:55:57.698856 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3185 00:55:57.702256 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3186 00:55:57.705766 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3187 00:55:57.708622 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3188 00:55:57.712033 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3189 00:55:57.715450 ==
3190 00:55:57.715528 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 00:55:57.722030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 00:55:57.722107 ==
3193 00:55:57.722167 DQS Delay:
3194 00:55:57.725462 DQS0 = 0, DQS1 = 0
3195 00:55:57.725574 DQM Delay:
3196 00:55:57.729060 DQM0 = 119, DQM1 = 116
3197 00:55:57.729136 DQ Delay:
3198 00:55:57.732240 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3199 00:55:57.735554 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3200 00:55:57.739116 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3201 00:55:57.741854 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3202 00:55:57.741957
3203 00:55:57.742026
3204 00:55:57.742088 ==
3205 00:55:57.745350 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 00:55:57.752015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 00:55:57.752118 ==
3208 00:55:57.752197
3209 00:55:57.752270
3210 00:55:57.752340 TX Vref Scan disable
3211 00:55:57.755515 == TX Byte 0 ==
3212 00:55:57.759070 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3213 00:55:57.762453 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3214 00:55:57.766080 == TX Byte 1 ==
3215 00:55:57.768647 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3216 00:55:57.772057 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3217 00:55:57.775505 ==
3218 00:55:57.778735 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 00:55:57.782242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 00:55:57.782503 ==
3221 00:55:57.793233 TX Vref=22, minBit 11, minWin=24, winSum=411
3222 00:55:57.797164 TX Vref=24, minBit 11, minWin=25, winSum=419
3223 00:55:57.800489 TX Vref=26, minBit 9, minWin=25, winSum=425
3224 00:55:57.803221 TX Vref=28, minBit 1, minWin=26, winSum=426
3225 00:55:57.806819 TX Vref=30, minBit 1, minWin=26, winSum=431
3226 00:55:57.813503 TX Vref=32, minBit 2, minWin=26, winSum=434
3227 00:55:57.816970 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 32
3228 00:55:57.817363
3229 00:55:57.820427 Final TX Range 1 Vref 32
3230 00:55:57.820816
3231 00:55:57.821118 ==
3232 00:55:57.823218 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 00:55:57.826542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 00:55:57.829917 ==
3235 00:55:57.830312
3236 00:55:57.830781
3237 00:55:57.831080 TX Vref Scan disable
3238 00:55:57.833189 == TX Byte 0 ==
3239 00:55:57.836837 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3240 00:55:57.843335 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3241 00:55:57.843804 == TX Byte 1 ==
3242 00:55:57.846710 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3243 00:55:57.853277 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3244 00:55:57.853881
3245 00:55:57.854315 [DATLAT]
3246 00:55:57.854613 Freq=1200, CH1 RK0
3247 00:55:57.854982
3248 00:55:57.856408 DATLAT Default: 0xd
3249 00:55:57.856836 0, 0xFFFF, sum = 0
3250 00:55:57.859902 1, 0xFFFF, sum = 0
3251 00:55:57.860295 2, 0xFFFF, sum = 0
3252 00:55:57.863525 3, 0xFFFF, sum = 0
3253 00:55:57.866461 4, 0xFFFF, sum = 0
3254 00:55:57.866875 5, 0xFFFF, sum = 0
3255 00:55:57.870277 6, 0xFFFF, sum = 0
3256 00:55:57.870668 7, 0xFFFF, sum = 0
3257 00:55:57.873606 8, 0xFFFF, sum = 0
3258 00:55:57.874001 9, 0xFFFF, sum = 0
3259 00:55:57.876499 10, 0xFFFF, sum = 0
3260 00:55:57.877047 11, 0xFFFF, sum = 0
3261 00:55:57.879888 12, 0x0, sum = 1
3262 00:55:57.880279 13, 0x0, sum = 2
3263 00:55:57.883301 14, 0x0, sum = 3
3264 00:55:57.883723 15, 0x0, sum = 4
3265 00:55:57.884140 best_step = 13
3266 00:55:57.886978
3267 00:55:57.887398 ==
3268 00:55:57.890424 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 00:55:57.893146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 00:55:57.893627 ==
3271 00:55:57.893975 RX Vref Scan: 1
3272 00:55:57.894296
3273 00:55:57.896500 Set Vref Range= 32 -> 127
3274 00:55:57.896932
3275 00:55:57.900411 RX Vref 32 -> 127, step: 1
3276 00:55:57.900952
3277 00:55:57.903646 RX Delay -5 -> 252, step: 4
3278 00:55:57.904043
3279 00:55:57.907256 Set Vref, RX VrefLevel [Byte0]: 32
3280 00:55:57.909922 [Byte1]: 32
3281 00:55:57.910306
3282 00:55:57.913387 Set Vref, RX VrefLevel [Byte0]: 33
3283 00:55:57.916769 [Byte1]: 33
3284 00:55:57.917166
3285 00:55:57.920312 Set Vref, RX VrefLevel [Byte0]: 34
3286 00:55:57.923116 [Byte1]: 34
3287 00:55:57.927257
3288 00:55:57.927699 Set Vref, RX VrefLevel [Byte0]: 35
3289 00:55:57.930610 [Byte1]: 35
3290 00:55:57.935638
3291 00:55:57.936080 Set Vref, RX VrefLevel [Byte0]: 36
3292 00:55:57.938404 [Byte1]: 36
3293 00:55:57.943202
3294 00:55:57.943593 Set Vref, RX VrefLevel [Byte0]: 37
3295 00:55:57.946660 [Byte1]: 37
3296 00:55:57.950738
3297 00:55:57.951133 Set Vref, RX VrefLevel [Byte0]: 38
3298 00:55:57.954187 [Byte1]: 38
3299 00:55:57.959236
3300 00:55:57.959643 Set Vref, RX VrefLevel [Byte0]: 39
3301 00:55:57.962422 [Byte1]: 39
3302 00:55:57.966866
3303 00:55:57.967256 Set Vref, RX VrefLevel [Byte0]: 40
3304 00:55:57.969828 [Byte1]: 40
3305 00:55:57.974319
3306 00:55:57.974705 Set Vref, RX VrefLevel [Byte0]: 41
3307 00:55:57.977743 [Byte1]: 41
3308 00:55:57.982561
3309 00:55:57.982947 Set Vref, RX VrefLevel [Byte0]: 42
3310 00:55:57.985537 [Byte1]: 42
3311 00:55:57.990329
3312 00:55:57.990724 Set Vref, RX VrefLevel [Byte0]: 43
3313 00:55:57.993757 [Byte1]: 43
3314 00:55:57.997766
3315 00:55:57.998064 Set Vref, RX VrefLevel [Byte0]: 44
3316 00:55:58.001395 [Byte1]: 44
3317 00:55:58.005975
3318 00:55:58.006250 Set Vref, RX VrefLevel [Byte0]: 45
3319 00:55:58.009484 [Byte1]: 45
3320 00:55:58.013881
3321 00:55:58.014159 Set Vref, RX VrefLevel [Byte0]: 46
3322 00:55:58.016971 [Byte1]: 46
3323 00:55:58.021826
3324 00:55:58.022101 Set Vref, RX VrefLevel [Byte0]: 47
3325 00:55:58.025176 [Byte1]: 47
3326 00:55:58.029302
3327 00:55:58.029602 Set Vref, RX VrefLevel [Byte0]: 48
3328 00:55:58.032802 [Byte1]: 48
3329 00:55:58.037295
3330 00:55:58.037669 Set Vref, RX VrefLevel [Byte0]: 49
3331 00:55:58.040800 [Byte1]: 49
3332 00:55:58.045000
3333 00:55:58.045370 Set Vref, RX VrefLevel [Byte0]: 50
3334 00:55:58.048542 [Byte1]: 50
3335 00:55:58.053347
3336 00:55:58.053923 Set Vref, RX VrefLevel [Byte0]: 51
3337 00:55:58.056467 [Byte1]: 51
3338 00:55:58.061045
3339 00:55:58.061505 Set Vref, RX VrefLevel [Byte0]: 52
3340 00:55:58.063817 [Byte1]: 52
3341 00:55:58.068578
3342 00:55:58.069037 Set Vref, RX VrefLevel [Byte0]: 53
3343 00:55:58.072229 [Byte1]: 53
3344 00:55:58.076433
3345 00:55:58.079916 Set Vref, RX VrefLevel [Byte0]: 54
3346 00:55:58.083078 [Byte1]: 54
3347 00:55:58.083478
3348 00:55:58.086646 Set Vref, RX VrefLevel [Byte0]: 55
3349 00:55:58.090039 [Byte1]: 55
3350 00:55:58.090386
3351 00:55:58.093239 Set Vref, RX VrefLevel [Byte0]: 56
3352 00:55:58.096538 [Byte1]: 56
3353 00:55:58.100382
3354 00:55:58.100729 Set Vref, RX VrefLevel [Byte0]: 57
3355 00:55:58.103194 [Byte1]: 57
3356 00:55:58.108493
3357 00:55:58.108865 Set Vref, RX VrefLevel [Byte0]: 58
3358 00:55:58.111703 [Byte1]: 58
3359 00:55:58.115945
3360 00:55:58.116409 Set Vref, RX VrefLevel [Byte0]: 59
3361 00:55:58.118965 [Byte1]: 59
3362 00:55:58.123899
3363 00:55:58.124242 Set Vref, RX VrefLevel [Byte0]: 60
3364 00:55:58.126979 [Byte1]: 60
3365 00:55:58.131205
3366 00:55:58.131698 Set Vref, RX VrefLevel [Byte0]: 61
3367 00:55:58.134583 [Byte1]: 61
3368 00:55:58.139279
3369 00:55:58.139625 Set Vref, RX VrefLevel [Byte0]: 62
3370 00:55:58.142649 [Byte1]: 62
3371 00:55:58.147028
3372 00:55:58.147421 Set Vref, RX VrefLevel [Byte0]: 63
3373 00:55:58.150887 [Byte1]: 63
3374 00:55:58.154963
3375 00:55:58.155332 Set Vref, RX VrefLevel [Byte0]: 64
3376 00:55:58.158466 [Byte1]: 64
3377 00:55:58.163368
3378 00:55:58.163723 Set Vref, RX VrefLevel [Byte0]: 65
3379 00:55:58.166025 [Byte1]: 65
3380 00:55:58.170861
3381 00:55:58.171212 Set Vref, RX VrefLevel [Byte0]: 66
3382 00:55:58.174307 [Byte1]: 66
3383 00:55:58.178467
3384 00:55:58.178816 Set Vref, RX VrefLevel [Byte0]: 67
3385 00:55:58.181953 [Byte1]: 67
3386 00:55:58.186791
3387 00:55:58.187207 Set Vref, RX VrefLevel [Byte0]: 68
3388 00:55:58.190119 [Byte1]: 68
3389 00:55:58.194246
3390 00:55:58.194779 Set Vref, RX VrefLevel [Byte0]: 69
3391 00:55:58.197509 [Byte1]: 69
3392 00:55:58.202370
3393 00:55:58.202740 Set Vref, RX VrefLevel [Byte0]: 70
3394 00:55:58.205640 [Byte1]: 70
3395 00:55:58.209973
3396 00:55:58.210373 Set Vref, RX VrefLevel [Byte0]: 71
3397 00:55:58.213368 [Byte1]: 71
3398 00:55:58.218242
3399 00:55:58.218621 Final RX Vref Byte 0 = 51 to rank0
3400 00:55:58.221058 Final RX Vref Byte 1 = 52 to rank0
3401 00:55:58.224568 Final RX Vref Byte 0 = 51 to rank1
3402 00:55:58.228178 Final RX Vref Byte 1 = 52 to rank1==
3403 00:55:58.231455 Dram Type= 6, Freq= 0, CH_1, rank 0
3404 00:55:58.237729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 00:55:58.238154 ==
3406 00:55:58.238443 DQS Delay:
3407 00:55:58.238755 DQS0 = 0, DQS1 = 0
3408 00:55:58.241039 DQM Delay:
3409 00:55:58.241443 DQM0 = 119, DQM1 = 116
3410 00:55:58.244386 DQ Delay:
3411 00:55:58.248077 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =114
3412 00:55:58.250970 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3413 00:55:58.254629 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =110
3414 00:55:58.257839 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3415 00:55:58.258193
3416 00:55:58.258557
3417 00:55:58.264990 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3418 00:55:58.268030 CH1 RK0: MR19=404, MR18=417
3419 00:55:58.274670 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3420 00:55:58.275026
3421 00:55:58.277906 ----->DramcWriteLeveling(PI) begin...
3422 00:55:58.278429 ==
3423 00:55:58.281238 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 00:55:58.284821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 00:55:58.285193 ==
3426 00:55:58.287640 Write leveling (Byte 0): 27 => 27
3427 00:55:58.291025 Write leveling (Byte 1): 27 => 27
3428 00:55:58.294940 DramcWriteLeveling(PI) end<-----
3429 00:55:58.295307
3430 00:55:58.295671 ==
3431 00:55:58.297739 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 00:55:58.304700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 00:55:58.305072 ==
3434 00:55:58.305440 [Gating] SW mode calibration
3435 00:55:58.314832 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3436 00:55:58.317857 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3437 00:55:58.321187 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 00:55:58.327938 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 00:55:58.330716 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 00:55:58.334327 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 00:55:58.341240 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 00:55:58.344820 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3443 00:55:58.347635 0 15 24 | B1->B0 | 2a2a 3333 | 0 1 | (0 1) (1 1)
3444 00:55:58.354538 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3445 00:55:58.357893 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 00:55:58.361341 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 00:55:58.367510 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 00:55:58.370874 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 00:55:58.374112 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 00:55:58.380498 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3451 00:55:58.384070 1 0 24 | B1->B0 | 4545 2929 | 0 0 | (0 0) (0 0)
3452 00:55:58.387760 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 00:55:58.393985 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 00:55:58.397130 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 00:55:58.400342 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 00:55:58.407394 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 00:55:58.410598 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 00:55:58.413940 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 00:55:58.420477 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3460 00:55:58.423617 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3461 00:55:58.426813 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 00:55:58.433897 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 00:55:58.437283 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 00:55:58.440143 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 00:55:58.447076 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 00:55:58.450544 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 00:55:58.453964 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 00:55:58.460222 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 00:55:58.463458 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 00:55:58.467112 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 00:55:58.470591 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 00:55:58.477313 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 00:55:58.480115 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 00:55:58.483396 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3475 00:55:58.490102 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3476 00:55:58.493489 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3477 00:55:58.496997 Total UI for P1: 0, mck2ui 16
3478 00:55:58.500407 best dqsien dly found for B1: ( 1, 3, 22)
3479 00:55:58.503886 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 00:55:58.507051 Total UI for P1: 0, mck2ui 16
3481 00:55:58.510375 best dqsien dly found for B0: ( 1, 3, 26)
3482 00:55:58.513670 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3483 00:55:58.516926 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3484 00:55:58.520351
3485 00:55:58.523676 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3486 00:55:58.526842 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3487 00:55:58.529788 [Gating] SW calibration Done
3488 00:55:58.530123 ==
3489 00:55:58.533273 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 00:55:58.536618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 00:55:58.536947 ==
3492 00:55:58.537208 RX Vref Scan: 0
3493 00:55:58.539735
3494 00:55:58.540030 RX Vref 0 -> 0, step: 1
3495 00:55:58.540295
3496 00:55:58.543135 RX Delay -40 -> 252, step: 8
3497 00:55:58.546994 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3498 00:55:58.549984 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3499 00:55:58.556343 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3500 00:55:58.560108 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3501 00:55:58.562875 iDelay=200, Bit 4, Center 115 (56 ~ 175) 120
3502 00:55:58.566431 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3503 00:55:58.569878 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3504 00:55:58.576737 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3505 00:55:58.580190 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3506 00:55:58.583062 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3507 00:55:58.586409 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3508 00:55:58.589882 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3509 00:55:58.596681 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3510 00:55:58.600214 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3511 00:55:58.603551 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3512 00:55:58.606424 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3513 00:55:58.606780 ==
3514 00:55:58.609893 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 00:55:58.616391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 00:55:58.616786 ==
3517 00:55:58.617065 DQS Delay:
3518 00:55:58.617327 DQS0 = 0, DQS1 = 0
3519 00:55:58.619724 DQM Delay:
3520 00:55:58.620074 DQM0 = 120, DQM1 = 118
3521 00:55:58.623530 DQ Delay:
3522 00:55:58.626801 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3523 00:55:58.630316 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3524 00:55:58.633026 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3525 00:55:58.636599 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3526 00:55:58.637013
3527 00:55:58.637292
3528 00:55:58.637575 ==
3529 00:55:58.640149 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 00:55:58.642893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 00:55:58.646188 ==
3532 00:55:58.646543
3533 00:55:58.646817
3534 00:55:58.647070 TX Vref Scan disable
3535 00:55:58.649626 == TX Byte 0 ==
3536 00:55:58.652961 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3537 00:55:58.656273 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3538 00:55:58.659567 == TX Byte 1 ==
3539 00:55:58.662812 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3540 00:55:58.666505 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3541 00:55:58.666887 ==
3542 00:55:58.669381 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 00:55:58.676166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 00:55:58.676529 ==
3545 00:55:58.686853 TX Vref=22, minBit 9, minWin=25, winSum=419
3546 00:55:58.690297 TX Vref=24, minBit 0, minWin=26, winSum=426
3547 00:55:58.693249 TX Vref=26, minBit 0, minWin=26, winSum=425
3548 00:55:58.697170 TX Vref=28, minBit 10, minWin=25, winSum=428
3549 00:55:58.699976 TX Vref=30, minBit 10, minWin=25, winSum=432
3550 00:55:58.707487 TX Vref=32, minBit 9, minWin=26, winSum=432
3551 00:55:58.710468 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 32
3552 00:55:58.710837
3553 00:55:58.714004 Final TX Range 1 Vref 32
3554 00:55:58.714375
3555 00:55:58.714655 ==
3556 00:55:58.717269 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 00:55:58.720595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 00:55:58.720999 ==
3559 00:55:58.721409
3560 00:55:58.723908
3561 00:55:58.724392 TX Vref Scan disable
3562 00:55:58.727244 == TX Byte 0 ==
3563 00:55:58.730391 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3564 00:55:58.733758 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3565 00:55:58.737130 == TX Byte 1 ==
3566 00:55:58.740522 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3567 00:55:58.743344 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3568 00:55:58.743525
3569 00:55:58.746636 [DATLAT]
3570 00:55:58.746787 Freq=1200, CH1 RK1
3571 00:55:58.746894
3572 00:55:58.749936 DATLAT Default: 0xd
3573 00:55:58.750065 0, 0xFFFF, sum = 0
3574 00:55:58.753844 1, 0xFFFF, sum = 0
3575 00:55:58.753982 2, 0xFFFF, sum = 0
3576 00:55:58.756575 3, 0xFFFF, sum = 0
3577 00:55:58.756689 4, 0xFFFF, sum = 0
3578 00:55:58.759844 5, 0xFFFF, sum = 0
3579 00:55:58.759988 6, 0xFFFF, sum = 0
3580 00:55:58.763365 7, 0xFFFF, sum = 0
3581 00:55:58.763457 8, 0xFFFF, sum = 0
3582 00:55:58.766866 9, 0xFFFF, sum = 0
3583 00:55:58.770313 10, 0xFFFF, sum = 0
3584 00:55:58.770391 11, 0xFFFF, sum = 0
3585 00:55:58.773673 12, 0x0, sum = 1
3586 00:55:58.773751 13, 0x0, sum = 2
3587 00:55:58.776576 14, 0x0, sum = 3
3588 00:55:58.776653 15, 0x0, sum = 4
3589 00:55:58.776713 best_step = 13
3590 00:55:58.776767
3591 00:55:58.780059 ==
3592 00:55:58.783403 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 00:55:58.786903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 00:55:58.786980 ==
3595 00:55:58.787039 RX Vref Scan: 0
3596 00:55:58.787094
3597 00:55:58.790435 RX Vref 0 -> 0, step: 1
3598 00:55:58.790510
3599 00:55:58.793104 RX Delay -5 -> 252, step: 4
3600 00:55:58.796932 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3601 00:55:58.800050 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3602 00:55:58.806902 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3603 00:55:58.810274 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3604 00:55:58.813147 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3605 00:55:58.816782 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3606 00:55:58.819928 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3607 00:55:58.826630 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3608 00:55:58.830060 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3609 00:55:58.833501 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3610 00:55:58.837236 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3611 00:55:58.840232 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3612 00:55:58.847302 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3613 00:55:58.850095 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3614 00:55:58.853635 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3615 00:55:58.856883 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3616 00:55:58.857270 ==
3617 00:55:58.860310 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 00:55:58.867173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 00:55:58.867645 ==
3620 00:55:58.868011 DQS Delay:
3621 00:55:58.870603 DQS0 = 0, DQS1 = 0
3622 00:55:58.871003 DQM Delay:
3623 00:55:58.871306 DQM0 = 120, DQM1 = 118
3624 00:55:58.873504 DQ Delay:
3625 00:55:58.876943 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3626 00:55:58.880545 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3627 00:55:58.883947 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3628 00:55:58.887243 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3629 00:55:58.887677
3630 00:55:58.887987
3631 00:55:58.896949 [DQSOSCAuto] RK1, (LSB)MR18= 0x14f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3632 00:55:58.897427 CH1 RK1: MR19=403, MR18=14F0
3633 00:55:58.904030 CH1_RK1: MR19=0x403, MR18=0x14F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3634 00:55:58.906638 [RxdqsGatingPostProcess] freq 1200
3635 00:55:58.913649 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3636 00:55:58.917079 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 00:55:58.920534 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 00:55:58.923297 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 00:55:58.926857 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 00:55:58.927268 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 00:55:58.930034 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 00:55:58.933872 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 00:55:58.936969 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 00:55:58.939861 Pre-setting of DQS Precalculation
3645 00:55:58.946708 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3646 00:55:58.953417 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3647 00:55:58.960015 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3648 00:55:58.960582
3649 00:55:58.960895
3650 00:55:58.963228 [Calibration Summary] 2400 Mbps
3651 00:55:58.963618 CH 0, Rank 0
3652 00:55:58.966391 SW Impedance : PASS
3653 00:55:58.969863 DUTY Scan : NO K
3654 00:55:58.970252 ZQ Calibration : PASS
3655 00:55:58.973176 Jitter Meter : NO K
3656 00:55:58.976557 CBT Training : PASS
3657 00:55:58.976951 Write leveling : PASS
3658 00:55:58.979914 RX DQS gating : PASS
3659 00:55:58.983174 RX DQ/DQS(RDDQC) : PASS
3660 00:55:58.983562 TX DQ/DQS : PASS
3661 00:55:58.986562 RX DATLAT : PASS
3662 00:55:58.989776 RX DQ/DQS(Engine): PASS
3663 00:55:58.990166 TX OE : NO K
3664 00:55:58.993130 All Pass.
3665 00:55:58.993512
3666 00:55:58.993867 CH 0, Rank 1
3667 00:55:58.996538 SW Impedance : PASS
3668 00:55:58.996922 DUTY Scan : NO K
3669 00:55:59.000004 ZQ Calibration : PASS
3670 00:55:59.003712 Jitter Meter : NO K
3671 00:55:59.004189 CBT Training : PASS
3672 00:55:59.006316 Write leveling : PASS
3673 00:55:59.009647 RX DQS gating : PASS
3674 00:55:59.010036 RX DQ/DQS(RDDQC) : PASS
3675 00:55:59.013060 TX DQ/DQS : PASS
3676 00:55:59.013461 RX DATLAT : PASS
3677 00:55:59.016493 RX DQ/DQS(Engine): PASS
3678 00:55:59.020114 TX OE : NO K
3679 00:55:59.020501 All Pass.
3680 00:55:59.020806
3681 00:55:59.021084 CH 1, Rank 0
3682 00:55:59.023580 SW Impedance : PASS
3683 00:55:59.026387 DUTY Scan : NO K
3684 00:55:59.026774 ZQ Calibration : PASS
3685 00:55:59.029876 Jitter Meter : NO K
3686 00:55:59.033238 CBT Training : PASS
3687 00:55:59.033656 Write leveling : PASS
3688 00:55:59.036843 RX DQS gating : PASS
3689 00:55:59.040045 RX DQ/DQS(RDDQC) : PASS
3690 00:55:59.040437 TX DQ/DQS : PASS
3691 00:55:59.043381 RX DATLAT : PASS
3692 00:55:59.046648 RX DQ/DQS(Engine): PASS
3693 00:55:59.047046 TX OE : NO K
3694 00:55:59.047396 All Pass.
3695 00:55:59.050233
3696 00:55:59.050673 CH 1, Rank 1
3697 00:55:59.053001 SW Impedance : PASS
3698 00:55:59.053460 DUTY Scan : NO K
3699 00:55:59.056947 ZQ Calibration : PASS
3700 00:55:59.057346 Jitter Meter : NO K
3701 00:55:59.060148 CBT Training : PASS
3702 00:55:59.062942 Write leveling : PASS
3703 00:55:59.063429 RX DQS gating : PASS
3704 00:55:59.066379 RX DQ/DQS(RDDQC) : PASS
3705 00:55:59.069919 TX DQ/DQS : PASS
3706 00:55:59.070307 RX DATLAT : PASS
3707 00:55:59.073402 RX DQ/DQS(Engine): PASS
3708 00:55:59.076544 TX OE : NO K
3709 00:55:59.076936 All Pass.
3710 00:55:59.077232
3711 00:55:59.079690 DramC Write-DBI off
3712 00:55:59.080075 PER_BANK_REFRESH: Hybrid Mode
3713 00:55:59.082980 TX_TRACKING: ON
3714 00:55:59.089641 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3715 00:55:59.096497 [FAST_K] Save calibration result to emmc
3716 00:55:59.099433 dramc_set_vcore_voltage set vcore to 650000
3717 00:55:59.100082 Read voltage for 600, 5
3718 00:55:59.102739 Vio18 = 0
3719 00:55:59.103257 Vcore = 650000
3720 00:55:59.103911 Vdram = 0
3721 00:55:59.106367 Vddq = 0
3722 00:55:59.106752 Vmddr = 0
3723 00:55:59.109584 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3724 00:55:59.116001 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3725 00:55:59.119801 MEM_TYPE=3, freq_sel=19
3726 00:55:59.122741 sv_algorithm_assistance_LP4_1600
3727 00:55:59.125905 ============ PULL DRAM RESETB DOWN ============
3728 00:55:59.129464 ========== PULL DRAM RESETB DOWN end =========
3729 00:55:59.136424 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3730 00:55:59.139975 ===================================
3731 00:55:59.140361 LPDDR4 DRAM CONFIGURATION
3732 00:55:59.143185 ===================================
3733 00:55:59.145993 EX_ROW_EN[0] = 0x0
3734 00:55:59.146380 EX_ROW_EN[1] = 0x0
3735 00:55:59.150061 LP4Y_EN = 0x0
3736 00:55:59.150449 WORK_FSP = 0x0
3737 00:55:59.152637 WL = 0x2
3738 00:55:59.153021 RL = 0x2
3739 00:55:59.156040 BL = 0x2
3740 00:55:59.156428 RPST = 0x0
3741 00:55:59.159567 RD_PRE = 0x0
3742 00:55:59.162921 WR_PRE = 0x1
3743 00:55:59.163308 WR_PST = 0x0
3744 00:55:59.166413 DBI_WR = 0x0
3745 00:55:59.166799 DBI_RD = 0x0
3746 00:55:59.169589 OTF = 0x1
3747 00:55:59.173032 ===================================
3748 00:55:59.176434 ===================================
3749 00:55:59.176823 ANA top config
3750 00:55:59.179934 ===================================
3751 00:55:59.183107 DLL_ASYNC_EN = 0
3752 00:55:59.183567 ALL_SLAVE_EN = 1
3753 00:55:59.186569 NEW_RANK_MODE = 1
3754 00:55:59.189981 DLL_IDLE_MODE = 1
3755 00:55:59.192641 LP45_APHY_COMB_EN = 1
3756 00:55:59.195935 TX_ODT_DIS = 1
3757 00:55:59.196346 NEW_8X_MODE = 1
3758 00:55:59.199235 ===================================
3759 00:55:59.202796 ===================================
3760 00:55:59.205718 data_rate = 1200
3761 00:55:59.209203 CKR = 1
3762 00:55:59.212606 DQ_P2S_RATIO = 8
3763 00:55:59.215936 ===================================
3764 00:55:59.219316 CA_P2S_RATIO = 8
3765 00:55:59.222320 DQ_CA_OPEN = 0
3766 00:55:59.222707 DQ_SEMI_OPEN = 0
3767 00:55:59.226036 CA_SEMI_OPEN = 0
3768 00:55:59.228971 CA_FULL_RATE = 0
3769 00:55:59.232309 DQ_CKDIV4_EN = 1
3770 00:55:59.235571 CA_CKDIV4_EN = 1
3771 00:55:59.239383 CA_PREDIV_EN = 0
3772 00:55:59.239956 PH8_DLY = 0
3773 00:55:59.242154 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3774 00:55:59.245915 DQ_AAMCK_DIV = 4
3775 00:55:59.249328 CA_AAMCK_DIV = 4
3776 00:55:59.252153 CA_ADMCK_DIV = 4
3777 00:55:59.255676 DQ_TRACK_CA_EN = 0
3778 00:55:59.256074 CA_PICK = 600
3779 00:55:59.259212 CA_MCKIO = 600
3780 00:55:59.262003 MCKIO_SEMI = 0
3781 00:55:59.265337 PLL_FREQ = 2288
3782 00:55:59.268672 DQ_UI_PI_RATIO = 32
3783 00:55:59.272124 CA_UI_PI_RATIO = 0
3784 00:55:59.275429 ===================================
3785 00:55:59.278828 ===================================
3786 00:55:59.282325 memory_type:LPDDR4
3787 00:55:59.282715 GP_NUM : 10
3788 00:55:59.285907 SRAM_EN : 1
3789 00:55:59.286296 MD32_EN : 0
3790 00:55:59.289097 ===================================
3791 00:55:59.292544 [ANA_INIT] >>>>>>>>>>>>>>
3792 00:55:59.295355 <<<<<< [CONFIGURE PHASE]: ANA_TX
3793 00:55:59.298737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3794 00:55:59.302082 ===================================
3795 00:55:59.305524 data_rate = 1200,PCW = 0X5800
3796 00:55:59.309029 ===================================
3797 00:55:59.312432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3798 00:55:59.315155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 00:55:59.321883 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 00:55:59.325390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3801 00:55:59.328915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3802 00:55:59.335668 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3803 00:55:59.336058 [ANA_INIT] flow start
3804 00:55:59.338749 [ANA_INIT] PLL >>>>>>>>
3805 00:55:59.338824 [ANA_INIT] PLL <<<<<<<<
3806 00:55:59.341506 [ANA_INIT] MIDPI >>>>>>>>
3807 00:55:59.345398 [ANA_INIT] MIDPI <<<<<<<<
3808 00:55:59.348555 [ANA_INIT] DLL >>>>>>>>
3809 00:55:59.348622 [ANA_INIT] flow end
3810 00:55:59.351498 ============ LP4 DIFF to SE enter ============
3811 00:55:59.358218 ============ LP4 DIFF to SE exit ============
3812 00:55:59.358314 [ANA_INIT] <<<<<<<<<<<<<
3813 00:55:59.361901 [Flow] Enable top DCM control >>>>>
3814 00:55:59.365193 [Flow] Enable top DCM control <<<<<
3815 00:55:59.368228 Enable DLL master slave shuffle
3816 00:55:59.374699 ==============================================================
3817 00:55:59.374771 Gating Mode config
3818 00:55:59.381371 ==============================================================
3819 00:55:59.385022 Config description:
3820 00:55:59.394969 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3821 00:55:59.401875 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3822 00:55:59.405053 SELPH_MODE 0: By rank 1: By Phase
3823 00:55:59.411348 ==============================================================
3824 00:55:59.414901 GAT_TRACK_EN = 1
3825 00:55:59.414976 RX_GATING_MODE = 2
3826 00:55:59.418346 RX_GATING_TRACK_MODE = 2
3827 00:55:59.421142 SELPH_MODE = 1
3828 00:55:59.425071 PICG_EARLY_EN = 1
3829 00:55:59.427863 VALID_LAT_VALUE = 1
3830 00:55:59.434729 ==============================================================
3831 00:55:59.438107 Enter into Gating configuration >>>>
3832 00:55:59.441553 Exit from Gating configuration <<<<
3833 00:55:59.445046 Enter into DVFS_PRE_config >>>>>
3834 00:55:59.454593 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3835 00:55:59.457945 Exit from DVFS_PRE_config <<<<<
3836 00:55:59.461236 Enter into PICG configuration >>>>
3837 00:55:59.464533 Exit from PICG configuration <<<<
3838 00:55:59.468045 [RX_INPUT] configuration >>>>>
3839 00:55:59.470864 [RX_INPUT] configuration <<<<<
3840 00:55:59.474400 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3841 00:55:59.481260 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3842 00:55:59.487362 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 00:55:59.494265 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 00:55:59.497651 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 00:55:59.503985 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 00:55:59.507823 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3847 00:55:59.513940 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3848 00:55:59.517455 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3849 00:55:59.520818 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3850 00:55:59.524069 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3851 00:55:59.530653 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 00:55:59.533771 ===================================
3853 00:55:59.533840 LPDDR4 DRAM CONFIGURATION
3854 00:55:59.537186 ===================================
3855 00:55:59.540512 EX_ROW_EN[0] = 0x0
3856 00:55:59.544041 EX_ROW_EN[1] = 0x0
3857 00:55:59.544131 LP4Y_EN = 0x0
3858 00:55:59.547496 WORK_FSP = 0x0
3859 00:55:59.547567 WL = 0x2
3860 00:55:59.550399 RL = 0x2
3861 00:55:59.550472 BL = 0x2
3862 00:55:59.553723 RPST = 0x0
3863 00:55:59.553791 RD_PRE = 0x0
3864 00:55:59.557034 WR_PRE = 0x1
3865 00:55:59.557101 WR_PST = 0x0
3866 00:55:59.560436 DBI_WR = 0x0
3867 00:55:59.560503 DBI_RD = 0x0
3868 00:55:59.563979 OTF = 0x1
3869 00:55:59.567228 ===================================
3870 00:55:59.570635 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3871 00:55:59.573558 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3872 00:55:59.580627 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 00:55:59.583466 ===================================
3874 00:55:59.583535 LPDDR4 DRAM CONFIGURATION
3875 00:55:59.586983 ===================================
3876 00:55:59.590178 EX_ROW_EN[0] = 0x10
3877 00:55:59.593705 EX_ROW_EN[1] = 0x0
3878 00:55:59.593774 LP4Y_EN = 0x0
3879 00:55:59.597079 WORK_FSP = 0x0
3880 00:55:59.597160 WL = 0x2
3881 00:55:59.600546 RL = 0x2
3882 00:55:59.600622 BL = 0x2
3883 00:55:59.603302 RPST = 0x0
3884 00:55:59.603373 RD_PRE = 0x0
3885 00:55:59.606846 WR_PRE = 0x1
3886 00:55:59.606915 WR_PST = 0x0
3887 00:55:59.610239 DBI_WR = 0x0
3888 00:55:59.610305 DBI_RD = 0x0
3889 00:55:59.613662 OTF = 0x1
3890 00:55:59.616967 ===================================
3891 00:55:59.623361 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3892 00:55:59.626845 nWR fixed to 30
3893 00:55:59.630201 [ModeRegInit_LP4] CH0 RK0
3894 00:55:59.630285 [ModeRegInit_LP4] CH0 RK1
3895 00:55:59.633356 [ModeRegInit_LP4] CH1 RK0
3896 00:55:59.636681 [ModeRegInit_LP4] CH1 RK1
3897 00:55:59.636747 match AC timing 17
3898 00:55:59.643041 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3899 00:55:59.646732 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3900 00:55:59.650210 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3901 00:55:59.656733 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3902 00:55:59.659543 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3903 00:55:59.659619 ==
3904 00:55:59.663246 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 00:55:59.666437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3906 00:55:59.666508 ==
3907 00:55:59.673380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3908 00:55:59.680021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3909 00:55:59.683467 [CA 0] Center 35 (5~66) winsize 62
3910 00:55:59.686385 [CA 1] Center 35 (5~66) winsize 62
3911 00:55:59.689799 [CA 2] Center 33 (3~64) winsize 62
3912 00:55:59.693196 [CA 3] Center 33 (2~64) winsize 63
3913 00:55:59.696545 [CA 4] Center 33 (2~64) winsize 63
3914 00:55:59.699972 [CA 5] Center 32 (2~63) winsize 62
3915 00:55:59.700042
3916 00:55:59.703297 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3917 00:55:59.703364
3918 00:55:59.706862 [CATrainingPosCal] consider 1 rank data
3919 00:55:59.709689 u2DelayCellTimex100 = 270/100 ps
3920 00:55:59.713195 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3921 00:55:59.716705 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3922 00:55:59.720048 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3923 00:55:59.723370 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3924 00:55:59.726801 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3925 00:55:59.730247 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3926 00:55:59.730319
3927 00:55:59.733223 CA PerBit enable=1, Macro0, CA PI delay=32
3928 00:55:59.736520
3929 00:55:59.736587 [CBTSetCACLKResult] CA Dly = 32
3930 00:55:59.740035 CS Dly: 4 (0~35)
3931 00:55:59.740103 ==
3932 00:55:59.743467 Dram Type= 6, Freq= 0, CH_0, rank 1
3933 00:55:59.746268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 00:55:59.746341 ==
3935 00:55:59.753109 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 00:55:59.760002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3937 00:55:59.763371 [CA 0] Center 35 (5~66) winsize 62
3938 00:55:59.766520 [CA 1] Center 35 (5~66) winsize 62
3939 00:55:59.769793 [CA 2] Center 34 (3~65) winsize 63
3940 00:55:59.772877 [CA 3] Center 33 (2~64) winsize 63
3941 00:55:59.776161 [CA 4] Center 32 (2~63) winsize 62
3942 00:55:59.779847 [CA 5] Center 32 (2~63) winsize 62
3943 00:55:59.779921
3944 00:55:59.782880 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3945 00:55:59.782949
3946 00:55:59.786770 [CATrainingPosCal] consider 2 rank data
3947 00:55:59.789832 u2DelayCellTimex100 = 270/100 ps
3948 00:55:59.792854 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3949 00:55:59.796279 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3950 00:55:59.799791 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3951 00:55:59.802998 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3952 00:55:59.805879 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3953 00:55:59.809146 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3954 00:55:59.813000
3955 00:55:59.816409 CA PerBit enable=1, Macro0, CA PI delay=32
3956 00:55:59.816482
3957 00:55:59.819268 [CBTSetCACLKResult] CA Dly = 32
3958 00:55:59.819334 CS Dly: 4 (0~36)
3959 00:55:59.819389
3960 00:55:59.822831 ----->DramcWriteLeveling(PI) begin...
3961 00:55:59.822898 ==
3962 00:55:59.826180 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 00:55:59.829499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 00:55:59.832997 ==
3965 00:55:59.833064 Write leveling (Byte 0): 34 => 34
3966 00:55:59.836426 Write leveling (Byte 1): 32 => 32
3967 00:55:59.839129 DramcWriteLeveling(PI) end<-----
3968 00:55:59.839195
3969 00:55:59.839256 ==
3970 00:55:59.842342 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 00:55:59.849032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 00:55:59.849105 ==
3973 00:55:59.849162 [Gating] SW mode calibration
3974 00:55:59.859559 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 00:55:59.862841 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3976 00:55:59.866349 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 00:55:59.872439 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 00:55:59.875887 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 00:55:59.879204 0 9 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
3980 00:55:59.885969 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (0 1) (0 0)
3981 00:55:59.889289 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 00:55:59.892730 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 00:55:59.899431 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 00:55:59.902820 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 00:55:59.906003 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 00:55:59.912502 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3987 00:55:59.916072 0 10 12 | B1->B0 | 2323 3a39 | 0 1 | (0 0) (0 0)
3988 00:55:59.919192 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3989 00:55:59.925715 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 00:55:59.929275 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 00:55:59.932474 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 00:55:59.938907 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 00:55:59.942328 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 00:55:59.945658 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 00:55:59.952506 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 00:55:59.955968 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 00:55:59.958707 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 00:55:59.965718 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 00:55:59.969131 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 00:55:59.971952 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:55:59.978840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 00:55:59.982144 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:55:59.985628 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:55:59.992153 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 00:55:59.995434 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 00:55:59.998847 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 00:56:00.002293 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 00:56:00.008990 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:56:00.012408 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:56:00.015114 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:56:00.021997 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:56:00.025382 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4013 00:56:00.028661 Total UI for P1: 0, mck2ui 16
4014 00:56:00.031896 best dqsien dly found for B0: ( 0, 13, 14)
4015 00:56:00.035228 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 00:56:00.038699 Total UI for P1: 0, mck2ui 16
4017 00:56:00.041948 best dqsien dly found for B1: ( 0, 13, 16)
4018 00:56:00.045233 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4019 00:56:00.048918 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4020 00:56:00.051865
4021 00:56:00.055231 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4022 00:56:00.058555 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4023 00:56:00.061877 [Gating] SW calibration Done
4024 00:56:00.061969 ==
4025 00:56:00.065424 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 00:56:00.068742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 00:56:00.068824 ==
4028 00:56:00.068883 RX Vref Scan: 0
4029 00:56:00.068937
4030 00:56:00.072113 RX Vref 0 -> 0, step: 1
4031 00:56:00.072178
4032 00:56:00.074926 RX Delay -230 -> 252, step: 16
4033 00:56:00.078392 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4034 00:56:00.085152 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4035 00:56:00.088565 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4036 00:56:00.092030 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4037 00:56:00.095395 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4038 00:56:00.098545 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4039 00:56:00.101862 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4040 00:56:00.108772 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4041 00:56:00.112040 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4042 00:56:00.115429 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4043 00:56:00.118900 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4044 00:56:00.125166 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4045 00:56:00.128660 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4046 00:56:00.132109 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4047 00:56:00.135660 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4048 00:56:00.142015 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4049 00:56:00.142091 ==
4050 00:56:00.145403 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 00:56:00.148820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 00:56:00.148917 ==
4053 00:56:00.149001 DQS Delay:
4054 00:56:00.152129 DQS0 = 0, DQS1 = 0
4055 00:56:00.152191 DQM Delay:
4056 00:56:00.155379 DQM0 = 52, DQM1 = 49
4057 00:56:00.155484 DQ Delay:
4058 00:56:00.159095 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4059 00:56:00.162328 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4060 00:56:00.165417 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4061 00:56:00.168539 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4062 00:56:00.168615
4063 00:56:00.168673
4064 00:56:00.168727 ==
4065 00:56:00.172161 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 00:56:00.175173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 00:56:00.175286 ==
4068 00:56:00.175356
4069 00:56:00.178532
4070 00:56:00.178616 TX Vref Scan disable
4071 00:56:00.181731 == TX Byte 0 ==
4072 00:56:00.185461 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4073 00:56:00.188729 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4074 00:56:00.192029 == TX Byte 1 ==
4075 00:56:00.195192 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4076 00:56:00.198459 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4077 00:56:00.198530 ==
4078 00:56:00.202018 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 00:56:00.208464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 00:56:00.208534 ==
4081 00:56:00.208591
4082 00:56:00.208644
4083 00:56:00.208698 TX Vref Scan disable
4084 00:56:00.213211 == TX Byte 0 ==
4085 00:56:00.216560 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4086 00:56:00.219878 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4087 00:56:00.223259 == TX Byte 1 ==
4088 00:56:00.226628 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4089 00:56:00.232950 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4090 00:56:00.233018
4091 00:56:00.233073 [DATLAT]
4092 00:56:00.233127 Freq=600, CH0 RK0
4093 00:56:00.233178
4094 00:56:00.236509 DATLAT Default: 0x9
4095 00:56:00.236584 0, 0xFFFF, sum = 0
4096 00:56:00.239272 1, 0xFFFF, sum = 0
4097 00:56:00.239349 2, 0xFFFF, sum = 0
4098 00:56:00.242603 3, 0xFFFF, sum = 0
4099 00:56:00.246087 4, 0xFFFF, sum = 0
4100 00:56:00.246162 5, 0xFFFF, sum = 0
4101 00:56:00.249459 6, 0xFFFF, sum = 0
4102 00:56:00.249535 7, 0xFFFF, sum = 0
4103 00:56:00.252927 8, 0x0, sum = 1
4104 00:56:00.253003 9, 0x0, sum = 2
4105 00:56:00.253061 10, 0x0, sum = 3
4106 00:56:00.256516 11, 0x0, sum = 4
4107 00:56:00.256593 best_step = 9
4108 00:56:00.256650
4109 00:56:00.256703 ==
4110 00:56:00.259317 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 00:56:00.266038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 00:56:00.266116 ==
4113 00:56:00.266174 RX Vref Scan: 1
4114 00:56:00.266228
4115 00:56:00.269448 RX Vref 0 -> 0, step: 1
4116 00:56:00.269525
4117 00:56:00.272559 RX Delay -147 -> 252, step: 8
4118 00:56:00.272633
4119 00:56:00.275893 Set Vref, RX VrefLevel [Byte0]: 55
4120 00:56:00.279366 [Byte1]: 46
4121 00:56:00.279441
4122 00:56:00.282729 Final RX Vref Byte 0 = 55 to rank0
4123 00:56:00.286153 Final RX Vref Byte 1 = 46 to rank0
4124 00:56:00.289532 Final RX Vref Byte 0 = 55 to rank1
4125 00:56:00.292876 Final RX Vref Byte 1 = 46 to rank1==
4126 00:56:00.296115 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 00:56:00.299476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 00:56:00.299542 ==
4129 00:56:00.303175 DQS Delay:
4130 00:56:00.303240 DQS0 = 0, DQS1 = 0
4131 00:56:00.303295 DQM Delay:
4132 00:56:00.306260 DQM0 = 52, DQM1 = 46
4133 00:56:00.306321 DQ Delay:
4134 00:56:00.309804 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4135 00:56:00.312752 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4136 00:56:00.316143 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4137 00:56:00.319635 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4138 00:56:00.319702
4139 00:56:00.319758
4140 00:56:00.329564 [DQSOSCAuto] RK0, (LSB)MR18= 0x7568, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 387 ps
4141 00:56:00.329649 CH0 RK0: MR19=808, MR18=7568
4142 00:56:00.336130 CH0_RK0: MR19=0x808, MR18=0x7568, DQSOSC=387, MR23=63, INC=175, DEC=116
4143 00:56:00.336225
4144 00:56:00.339522 ----->DramcWriteLeveling(PI) begin...
4145 00:56:00.339700 ==
4146 00:56:00.342994 Dram Type= 6, Freq= 0, CH_0, rank 1
4147 00:56:00.349351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 00:56:00.349422 ==
4149 00:56:00.352951 Write leveling (Byte 0): 35 => 35
4150 00:56:00.356399 Write leveling (Byte 1): 32 => 32
4151 00:56:00.356459 DramcWriteLeveling(PI) end<-----
4152 00:56:00.359865
4153 00:56:00.359925 ==
4154 00:56:00.362592 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 00:56:00.366022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 00:56:00.366090 ==
4157 00:56:00.369527 [Gating] SW mode calibration
4158 00:56:00.376296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4159 00:56:00.379596 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4160 00:56:00.386095 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 00:56:00.389277 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 00:56:00.392754 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4163 00:56:00.399502 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4164 00:56:00.402924 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (1 0)
4165 00:56:00.406215 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 00:56:00.412482 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 00:56:00.415827 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 00:56:00.419140 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 00:56:00.425916 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 00:56:00.429360 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 00:56:00.432737 0 10 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4172 00:56:00.439405 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4173 00:56:00.442380 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 00:56:00.445646 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 00:56:00.452452 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 00:56:00.455904 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 00:56:00.458680 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 00:56:00.465499 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 00:56:00.468978 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4180 00:56:00.472329 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 00:56:00.479055 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 00:56:00.481796 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 00:56:00.485200 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 00:56:00.492418 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 00:56:00.495766 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 00:56:00.498630 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 00:56:00.505151 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 00:56:00.508444 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 00:56:00.512428 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 00:56:00.515630 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 00:56:00.522176 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 00:56:00.525530 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 00:56:00.528968 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 00:56:00.535113 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4195 00:56:00.538434 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4196 00:56:00.541914 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4197 00:56:00.545136 Total UI for P1: 0, mck2ui 16
4198 00:56:00.548492 best dqsien dly found for B1: ( 0, 13, 12)
4199 00:56:00.555357 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 00:56:00.555428 Total UI for P1: 0, mck2ui 16
4201 00:56:00.562188 best dqsien dly found for B0: ( 0, 13, 16)
4202 00:56:00.564961 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4203 00:56:00.568375 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4204 00:56:00.568467
4205 00:56:00.572137 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4206 00:56:00.575188 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4207 00:56:00.578759 [Gating] SW calibration Done
4208 00:56:00.578826 ==
4209 00:56:00.581656 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 00:56:00.585674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 00:56:00.585745 ==
4212 00:56:00.588455 RX Vref Scan: 0
4213 00:56:00.588520
4214 00:56:00.588574 RX Vref 0 -> 0, step: 1
4215 00:56:00.588635
4216 00:56:00.592087 RX Delay -230 -> 252, step: 16
4217 00:56:00.598472 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4218 00:56:00.601907 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4219 00:56:00.605210 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4220 00:56:00.608474 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4221 00:56:00.612258 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4222 00:56:00.618442 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4223 00:56:00.621686 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4224 00:56:00.624918 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4225 00:56:00.628208 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4226 00:56:00.635095 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4227 00:56:00.638349 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4228 00:56:00.641676 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4229 00:56:00.645104 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4230 00:56:00.648513 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4231 00:56:00.655484 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4232 00:56:00.658277 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4233 00:56:00.658344 ==
4234 00:56:00.661765 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 00:56:00.665074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 00:56:00.665169 ==
4237 00:56:00.668518 DQS Delay:
4238 00:56:00.668584 DQS0 = 0, DQS1 = 0
4239 00:56:00.671948 DQM Delay:
4240 00:56:00.672026 DQM0 = 49, DQM1 = 43
4241 00:56:00.672085 DQ Delay:
4242 00:56:00.675472 DQ0 =41, DQ1 =49, DQ2 =49, DQ3 =41
4243 00:56:00.678279 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4244 00:56:00.681657 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4245 00:56:00.684998 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4246 00:56:00.685070
4247 00:56:00.685126
4248 00:56:00.685177 ==
4249 00:56:00.688192 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 00:56:00.695004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 00:56:00.695073 ==
4252 00:56:00.695130
4253 00:56:00.695186
4254 00:56:00.695237 TX Vref Scan disable
4255 00:56:00.698977 == TX Byte 0 ==
4256 00:56:00.702499 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4257 00:56:00.706026 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4258 00:56:00.708815 == TX Byte 1 ==
4259 00:56:00.712434 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4260 00:56:00.715863 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4261 00:56:00.719163 ==
4262 00:56:00.722744 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 00:56:00.725859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 00:56:00.725931 ==
4265 00:56:00.725986
4266 00:56:00.726038
4267 00:56:00.729157 TX Vref Scan disable
4268 00:56:00.729244 == TX Byte 0 ==
4269 00:56:00.735705 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4270 00:56:00.739473 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4271 00:56:00.739567 == TX Byte 1 ==
4272 00:56:00.745900 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4273 00:56:00.748861 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4274 00:56:00.748956
4275 00:56:00.749045 [DATLAT]
4276 00:56:00.752274 Freq=600, CH0 RK1
4277 00:56:00.752361
4278 00:56:00.752419 DATLAT Default: 0x9
4279 00:56:00.755697 0, 0xFFFF, sum = 0
4280 00:56:00.755767 1, 0xFFFF, sum = 0
4281 00:56:00.759092 2, 0xFFFF, sum = 0
4282 00:56:00.759161 3, 0xFFFF, sum = 0
4283 00:56:00.762254 4, 0xFFFF, sum = 0
4284 00:56:00.762329 5, 0xFFFF, sum = 0
4285 00:56:00.765664 6, 0xFFFF, sum = 0
4286 00:56:00.769100 7, 0xFFFF, sum = 0
4287 00:56:00.769197 8, 0x0, sum = 1
4288 00:56:00.769293 9, 0x0, sum = 2
4289 00:56:00.772580 10, 0x0, sum = 3
4290 00:56:00.772678 11, 0x0, sum = 4
4291 00:56:00.776011 best_step = 9
4292 00:56:00.776101
4293 00:56:00.776182 ==
4294 00:56:00.778951 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 00:56:00.782351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 00:56:00.782416 ==
4297 00:56:00.785819 RX Vref Scan: 0
4298 00:56:00.785879
4299 00:56:00.785932 RX Vref 0 -> 0, step: 1
4300 00:56:00.785988
4301 00:56:00.789225 RX Delay -163 -> 252, step: 8
4302 00:56:00.796081 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4303 00:56:00.799564 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4304 00:56:00.802916 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4305 00:56:00.806133 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4306 00:56:00.809303 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4307 00:56:00.816080 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4308 00:56:00.819148 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4309 00:56:00.822425 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4310 00:56:00.825748 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4311 00:56:00.832654 iDelay=197, Bit 9, Center 32 (-107 ~ 172) 280
4312 00:56:00.836041 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4313 00:56:00.838907 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4314 00:56:00.842309 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4315 00:56:00.845771 iDelay=197, Bit 13, Center 52 (-83 ~ 188) 272
4316 00:56:00.852467 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4317 00:56:00.855535 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4318 00:56:00.855601 ==
4319 00:56:00.858954 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 00:56:00.862583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 00:56:00.862651 ==
4322 00:56:00.865528 DQS Delay:
4323 00:56:00.865655 DQS0 = 0, DQS1 = 0
4324 00:56:00.865727 DQM Delay:
4325 00:56:00.869126 DQM0 = 53, DQM1 = 46
4326 00:56:00.869197 DQ Delay:
4327 00:56:00.872521 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4328 00:56:00.875441 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4329 00:56:00.879017 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4330 00:56:00.882479 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4331 00:56:00.882554
4332 00:56:00.882610
4333 00:56:00.891924 [DQSOSCAuto] RK1, (LSB)MR18= 0x6628, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4334 00:56:00.892025 CH0 RK1: MR19=808, MR18=6628
4335 00:56:00.898801 CH0_RK1: MR19=0x808, MR18=0x6628, DQSOSC=390, MR23=63, INC=172, DEC=114
4336 00:56:00.902322 [RxdqsGatingPostProcess] freq 600
4337 00:56:00.908695 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4338 00:56:00.912215 Pre-setting of DQS Precalculation
4339 00:56:00.915622 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4340 00:56:00.915694 ==
4341 00:56:00.918832 Dram Type= 6, Freq= 0, CH_1, rank 0
4342 00:56:00.922054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 00:56:00.925285 ==
4344 00:56:00.929152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4345 00:56:00.935261 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4346 00:56:00.938855 [CA 0] Center 36 (5~67) winsize 63
4347 00:56:00.942059 [CA 1] Center 36 (6~67) winsize 62
4348 00:56:00.945459 [CA 2] Center 35 (4~66) winsize 63
4349 00:56:00.948960 [CA 3] Center 34 (4~65) winsize 62
4350 00:56:00.951781 [CA 4] Center 35 (4~66) winsize 63
4351 00:56:00.955143 [CA 5] Center 34 (3~65) winsize 63
4352 00:56:00.955208
4353 00:56:00.958593 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4354 00:56:00.958662
4355 00:56:00.961966 [CATrainingPosCal] consider 1 rank data
4356 00:56:00.965382 u2DelayCellTimex100 = 270/100 ps
4357 00:56:00.968817 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4358 00:56:00.972201 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4359 00:56:00.975458 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4360 00:56:00.981740 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4361 00:56:00.984874 CA4 delay=35 (4~66),Diff = 1 PI (9 cell)
4362 00:56:00.988535 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4363 00:56:00.988602
4364 00:56:00.992038 CA PerBit enable=1, Macro0, CA PI delay=34
4365 00:56:00.992106
4366 00:56:00.994953 [CBTSetCACLKResult] CA Dly = 34
4367 00:56:00.995018 CS Dly: 5 (0~36)
4368 00:56:00.995073 ==
4369 00:56:00.998396 Dram Type= 6, Freq= 0, CH_1, rank 1
4370 00:56:01.005101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 00:56:01.005196 ==
4372 00:56:01.008559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 00:56:01.015356 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4374 00:56:01.018665 [CA 0] Center 36 (5~67) winsize 63
4375 00:56:01.022196 [CA 1] Center 36 (6~67) winsize 62
4376 00:56:01.025003 [CA 2] Center 35 (4~66) winsize 63
4377 00:56:01.028236 [CA 3] Center 34 (4~65) winsize 62
4378 00:56:01.031606 [CA 4] Center 35 (4~66) winsize 63
4379 00:56:01.035048 [CA 5] Center 34 (4~65) winsize 62
4380 00:56:01.035118
4381 00:56:01.038515 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4382 00:56:01.038582
4383 00:56:01.041775 [CATrainingPosCal] consider 2 rank data
4384 00:56:01.045187 u2DelayCellTimex100 = 270/100 ps
4385 00:56:01.048481 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4386 00:56:01.051613 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4387 00:56:01.058663 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4388 00:56:01.062209 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 00:56:01.065012 CA4 delay=35 (4~66),Diff = 1 PI (9 cell)
4390 00:56:01.068958 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 00:56:01.069051
4392 00:56:01.071736 CA PerBit enable=1, Macro0, CA PI delay=34
4393 00:56:01.071802
4394 00:56:01.075070 [CBTSetCACLKResult] CA Dly = 34
4395 00:56:01.075134 CS Dly: 6 (0~38)
4396 00:56:01.075192
4397 00:56:01.078531 ----->DramcWriteLeveling(PI) begin...
4398 00:56:01.078600 ==
4399 00:56:01.081986 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 00:56:01.088749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 00:56:01.088841 ==
4402 00:56:01.091896 Write leveling (Byte 0): 29 => 29
4403 00:56:01.095474 Write leveling (Byte 1): 29 => 29
4404 00:56:01.095556 DramcWriteLeveling(PI) end<-----
4405 00:56:01.098790
4406 00:56:01.098859 ==
4407 00:56:01.101710 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 00:56:01.105058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 00:56:01.105124 ==
4410 00:56:01.108766 [Gating] SW mode calibration
4411 00:56:01.115180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4412 00:56:01.118480 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4413 00:56:01.124863 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 00:56:01.128343 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 00:56:01.131782 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 00:56:01.138340 0 9 12 | B1->B0 | 3030 2929 | 1 0 | (0 0) (0 0)
4417 00:56:01.141848 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 00:56:01.145261 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 00:56:01.151639 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 00:56:01.155011 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 00:56:01.158419 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 00:56:01.165386 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 00:56:01.168564 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4424 00:56:01.171685 0 10 12 | B1->B0 | 3535 4242 | 0 0 | (0 0) (0 0)
4425 00:56:01.178429 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4426 00:56:01.181851 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 00:56:01.184684 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 00:56:01.191606 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 00:56:01.194499 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 00:56:01.197954 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 00:56:01.204978 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 00:56:01.207948 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 00:56:01.211333 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 00:56:01.218288 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 00:56:01.221552 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 00:56:01.224735 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:56:01.231522 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:56:01.235062 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:56:01.238384 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 00:56:01.241721 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 00:56:01.248364 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 00:56:01.251118 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 00:56:01.254546 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 00:56:01.261639 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:56:01.264993 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 00:56:01.268167 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:56:01.274852 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4448 00:56:01.277998 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4449 00:56:01.281184 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 00:56:01.284873 Total UI for P1: 0, mck2ui 16
4451 00:56:01.288113 best dqsien dly found for B0: ( 0, 13, 10)
4452 00:56:01.291570 Total UI for P1: 0, mck2ui 16
4453 00:56:01.294982 best dqsien dly found for B1: ( 0, 13, 12)
4454 00:56:01.297812 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4455 00:56:01.301272 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4456 00:56:01.301338
4457 00:56:01.308174 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4458 00:56:01.310954 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4459 00:56:01.314833 [Gating] SW calibration Done
4460 00:56:01.314904 ==
4461 00:56:01.317997 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 00:56:01.321241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 00:56:01.321311 ==
4464 00:56:01.321370 RX Vref Scan: 0
4465 00:56:01.321424
4466 00:56:01.324722 RX Vref 0 -> 0, step: 1
4467 00:56:01.324787
4468 00:56:01.328176 RX Delay -230 -> 252, step: 16
4469 00:56:01.331444 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4470 00:56:01.334797 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4471 00:56:01.341367 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4472 00:56:01.344330 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4473 00:56:01.347857 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4474 00:56:01.350929 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4475 00:56:01.357658 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4476 00:56:01.360779 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4477 00:56:01.364189 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4478 00:56:01.367773 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4479 00:56:01.374395 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4480 00:56:01.377892 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4481 00:56:01.380756 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4482 00:56:01.384060 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4483 00:56:01.387411 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4484 00:56:01.394065 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4485 00:56:01.394158 ==
4486 00:56:01.397272 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 00:56:01.400635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 00:56:01.400705 ==
4489 00:56:01.400762 DQS Delay:
4490 00:56:01.404171 DQS0 = 0, DQS1 = 0
4491 00:56:01.404237 DQM Delay:
4492 00:56:01.407735 DQM0 = 50, DQM1 = 46
4493 00:56:01.407818 DQ Delay:
4494 00:56:01.410508 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4495 00:56:01.413890 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4496 00:56:01.417557 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4497 00:56:01.420939 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4498 00:56:01.421002
4499 00:56:01.421056
4500 00:56:01.421106 ==
4501 00:56:01.424130 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 00:56:01.427198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 00:56:01.430464 ==
4504 00:56:01.430527
4505 00:56:01.430578
4506 00:56:01.430628 TX Vref Scan disable
4507 00:56:01.433894 == TX Byte 0 ==
4508 00:56:01.437260 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4509 00:56:01.440588 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4510 00:56:01.444060 == TX Byte 1 ==
4511 00:56:01.447531 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4512 00:56:01.450891 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4513 00:56:01.454053 ==
4514 00:56:01.454181 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 00:56:01.461041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 00:56:01.461162 ==
4517 00:56:01.461225
4518 00:56:01.461280
4519 00:56:01.463614 TX Vref Scan disable
4520 00:56:01.463688 == TX Byte 0 ==
4521 00:56:01.470469 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4522 00:56:01.473556 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4523 00:56:01.473672 == TX Byte 1 ==
4524 00:56:01.480810 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4525 00:56:01.483656 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4526 00:56:01.483755
4527 00:56:01.483868 [DATLAT]
4528 00:56:01.487188 Freq=600, CH1 RK0
4529 00:56:01.487285
4530 00:56:01.487368 DATLAT Default: 0x9
4531 00:56:01.490552 0, 0xFFFF, sum = 0
4532 00:56:01.490625 1, 0xFFFF, sum = 0
4533 00:56:01.493912 2, 0xFFFF, sum = 0
4534 00:56:01.493989 3, 0xFFFF, sum = 0
4535 00:56:01.497239 4, 0xFFFF, sum = 0
4536 00:56:01.497340 5, 0xFFFF, sum = 0
4537 00:56:01.500669 6, 0xFFFF, sum = 0
4538 00:56:01.503501 7, 0xFFFF, sum = 0
4539 00:56:01.503568 8, 0x0, sum = 1
4540 00:56:01.503628 9, 0x0, sum = 2
4541 00:56:01.507436 10, 0x0, sum = 3
4542 00:56:01.507548 11, 0x0, sum = 4
4543 00:56:01.510710 best_step = 9
4544 00:56:01.510885
4545 00:56:01.511002 ==
4546 00:56:01.513367 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 00:56:01.516912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 00:56:01.516996 ==
4549 00:56:01.520427 RX Vref Scan: 1
4550 00:56:01.520507
4551 00:56:01.520597 RX Vref 0 -> 0, step: 1
4552 00:56:01.520652
4553 00:56:01.523969 RX Delay -163 -> 252, step: 8
4554 00:56:01.524090
4555 00:56:01.526643 Set Vref, RX VrefLevel [Byte0]: 51
4556 00:56:01.530130 [Byte1]: 52
4557 00:56:01.533995
4558 00:56:01.534113 Final RX Vref Byte 0 = 51 to rank0
4559 00:56:01.537069 Final RX Vref Byte 1 = 52 to rank0
4560 00:56:01.540354 Final RX Vref Byte 0 = 51 to rank1
4561 00:56:01.544451 Final RX Vref Byte 1 = 52 to rank1==
4562 00:56:01.547607 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 00:56:01.553859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 00:56:01.553999 ==
4565 00:56:01.554101 DQS Delay:
4566 00:56:01.554195 DQS0 = 0, DQS1 = 0
4567 00:56:01.557193 DQM Delay:
4568 00:56:01.557304 DQM0 = 48, DQM1 = 44
4569 00:56:01.560533 DQ Delay:
4570 00:56:01.563742 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4571 00:56:01.567539 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4572 00:56:01.567655 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4573 00:56:01.574181 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4574 00:56:01.574304
4575 00:56:01.574401
4576 00:56:01.580590 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4577 00:56:01.583630 CH1 RK0: MR19=808, MR18=4E73
4578 00:56:01.590251 CH1_RK0: MR19=0x808, MR18=0x4E73, DQSOSC=388, MR23=63, INC=174, DEC=116
4579 00:56:01.590379
4580 00:56:01.593636 ----->DramcWriteLeveling(PI) begin...
4581 00:56:01.593751 ==
4582 00:56:01.597009 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 00:56:01.600780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 00:56:01.600899 ==
4585 00:56:01.603616 Write leveling (Byte 0): 30 => 30
4586 00:56:01.607058 Write leveling (Byte 1): 30 => 30
4587 00:56:01.610492 DramcWriteLeveling(PI) end<-----
4588 00:56:01.610609
4589 00:56:01.610704 ==
4590 00:56:01.613962 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 00:56:01.617122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 00:56:01.617236 ==
4593 00:56:01.620446 [Gating] SW mode calibration
4594 00:56:01.626764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4595 00:56:01.633718 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4596 00:56:01.637136 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 00:56:01.643795 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 00:56:01.646993 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 00:56:01.650691 0 9 12 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 0)
4600 00:56:01.654011 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 00:56:01.660010 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 00:56:01.663439 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 00:56:01.666761 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 00:56:01.673638 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 00:56:01.676919 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 00:56:01.680172 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 00:56:01.687030 0 10 12 | B1->B0 | 3838 3737 | 1 0 | (0 0) (0 0)
4608 00:56:01.690411 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 00:56:01.693468 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 00:56:01.700003 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 00:56:01.703491 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 00:56:01.707009 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 00:56:01.713416 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 00:56:01.717006 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 00:56:01.719809 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 00:56:01.727023 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 00:56:01.729891 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 00:56:01.733275 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 00:56:01.740119 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 00:56:01.743618 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 00:56:01.746403 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 00:56:01.752947 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 00:56:01.756277 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 00:56:01.759668 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 00:56:01.766562 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 00:56:01.769950 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 00:56:01.772769 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 00:56:01.779521 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 00:56:01.782621 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 00:56:01.786070 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 00:56:01.793019 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 00:56:01.793114 Total UI for P1: 0, mck2ui 16
4633 00:56:01.796471 best dqsien dly found for B0: ( 0, 13, 10)
4634 00:56:01.799286 Total UI for P1: 0, mck2ui 16
4635 00:56:01.802797 best dqsien dly found for B1: ( 0, 13, 10)
4636 00:56:01.809555 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4637 00:56:01.812790 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4638 00:56:01.812867
4639 00:56:01.816181 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4640 00:56:01.819260 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4641 00:56:01.822793 [Gating] SW calibration Done
4642 00:56:01.822860 ==
4643 00:56:01.826326 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 00:56:01.829266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 00:56:01.829356 ==
4646 00:56:01.833200 RX Vref Scan: 0
4647 00:56:01.833266
4648 00:56:01.833325 RX Vref 0 -> 0, step: 1
4649 00:56:01.833382
4650 00:56:01.836518 RX Delay -230 -> 252, step: 16
4651 00:56:01.839251 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4652 00:56:01.846225 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4653 00:56:01.849695 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4654 00:56:01.852457 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4655 00:56:01.855827 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4656 00:56:01.862410 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4657 00:56:01.865699 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4658 00:56:01.869654 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4659 00:56:01.872844 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4660 00:56:01.876018 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4661 00:56:01.882528 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4662 00:56:01.886000 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4663 00:56:01.889120 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4664 00:56:01.892322 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4665 00:56:01.899090 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4666 00:56:01.902616 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4667 00:56:01.902692 ==
4668 00:56:01.906083 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 00:56:01.909493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 00:56:01.909620 ==
4671 00:56:01.912974 DQS Delay:
4672 00:56:01.913049 DQS0 = 0, DQS1 = 0
4673 00:56:01.913108 DQM Delay:
4674 00:56:01.916248 DQM0 = 51, DQM1 = 49
4675 00:56:01.916322 DQ Delay:
4676 00:56:01.919097 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4677 00:56:01.922534 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4678 00:56:01.925920 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4679 00:56:01.929238 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4680 00:56:01.929312
4681 00:56:01.929370
4682 00:56:01.929424 ==
4683 00:56:01.932465 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 00:56:01.939270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 00:56:01.939345 ==
4686 00:56:01.939404
4687 00:56:01.939457
4688 00:56:01.939508 TX Vref Scan disable
4689 00:56:01.942778 == TX Byte 0 ==
4690 00:56:01.945653 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4691 00:56:01.952409 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4692 00:56:01.952485 == TX Byte 1 ==
4693 00:56:01.955801 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4694 00:56:01.959284 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4695 00:56:01.962722 ==
4696 00:56:01.965955 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 00:56:01.969346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 00:56:01.969422 ==
4699 00:56:01.969480
4700 00:56:01.969533
4701 00:56:01.972649 TX Vref Scan disable
4702 00:56:01.972723 == TX Byte 0 ==
4703 00:56:01.979297 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4704 00:56:01.982584 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4705 00:56:01.982660 == TX Byte 1 ==
4706 00:56:01.989257 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4707 00:56:01.992730 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4708 00:56:01.992805
4709 00:56:01.992863 [DATLAT]
4710 00:56:01.996018 Freq=600, CH1 RK1
4711 00:56:01.996093
4712 00:56:01.996151 DATLAT Default: 0x9
4713 00:56:01.999179 0, 0xFFFF, sum = 0
4714 00:56:01.999255 1, 0xFFFF, sum = 0
4715 00:56:02.002489 2, 0xFFFF, sum = 0
4716 00:56:02.002566 3, 0xFFFF, sum = 0
4717 00:56:02.006056 4, 0xFFFF, sum = 0
4718 00:56:02.009337 5, 0xFFFF, sum = 0
4719 00:56:02.009414 6, 0xFFFF, sum = 0
4720 00:56:02.012726 7, 0xFFFF, sum = 0
4721 00:56:02.012802 8, 0x0, sum = 1
4722 00:56:02.012862 9, 0x0, sum = 2
4723 00:56:02.015576 10, 0x0, sum = 3
4724 00:56:02.015652 11, 0x0, sum = 4
4725 00:56:02.019642 best_step = 9
4726 00:56:02.019718
4727 00:56:02.019784 ==
4728 00:56:02.022279 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 00:56:02.025762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 00:56:02.025838 ==
4731 00:56:02.029266 RX Vref Scan: 0
4732 00:56:02.029340
4733 00:56:02.029398 RX Vref 0 -> 0, step: 1
4734 00:56:02.029452
4735 00:56:02.032788 RX Delay -163 -> 252, step: 8
4736 00:56:02.039644 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4737 00:56:02.043042 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4738 00:56:02.046307 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4739 00:56:02.049664 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4740 00:56:02.053100 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4741 00:56:02.059179 iDelay=205, Bit 5, Center 64 (-75 ~ 204) 280
4742 00:56:02.062371 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4743 00:56:02.066031 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4744 00:56:02.069557 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4745 00:56:02.075991 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4746 00:56:02.079311 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4747 00:56:02.082457 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4748 00:56:02.085654 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4749 00:56:02.088972 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4750 00:56:02.095720 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4751 00:56:02.098957 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4752 00:56:02.099026 ==
4753 00:56:02.102169 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 00:56:02.105991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 00:56:02.106063 ==
4756 00:56:02.109051 DQS Delay:
4757 00:56:02.109115 DQS0 = 0, DQS1 = 0
4758 00:56:02.109169 DQM Delay:
4759 00:56:02.112296 DQM0 = 50, DQM1 = 44
4760 00:56:02.112374 DQ Delay:
4761 00:56:02.115780 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4762 00:56:02.119202 DQ4 =48, DQ5 =64, DQ6 =60, DQ7 =48
4763 00:56:02.122546 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4764 00:56:02.125851 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4765 00:56:02.125927
4766 00:56:02.126002
4767 00:56:02.135536 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4768 00:56:02.139086 CH1 RK1: MR19=808, MR18=6D22
4769 00:56:02.141943 CH1_RK1: MR19=0x808, MR18=0x6D22, DQSOSC=389, MR23=63, INC=173, DEC=115
4770 00:56:02.145443 [RxdqsGatingPostProcess] freq 600
4771 00:56:02.152412 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4772 00:56:02.155736 Pre-setting of DQS Precalculation
4773 00:56:02.159198 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4774 00:56:02.168958 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4775 00:56:02.175648 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4776 00:56:02.175725
4777 00:56:02.175782
4778 00:56:02.178532 [Calibration Summary] 1200 Mbps
4779 00:56:02.178608 CH 0, Rank 0
4780 00:56:02.182076 SW Impedance : PASS
4781 00:56:02.182151 DUTY Scan : NO K
4782 00:56:02.185587 ZQ Calibration : PASS
4783 00:56:02.188529 Jitter Meter : NO K
4784 00:56:02.188655 CBT Training : PASS
4785 00:56:02.191851 Write leveling : PASS
4786 00:56:02.194953 RX DQS gating : PASS
4787 00:56:02.195057 RX DQ/DQS(RDDQC) : PASS
4788 00:56:02.198672 TX DQ/DQS : PASS
4789 00:56:02.201776 RX DATLAT : PASS
4790 00:56:02.201851 RX DQ/DQS(Engine): PASS
4791 00:56:02.205588 TX OE : NO K
4792 00:56:02.205727 All Pass.
4793 00:56:02.205804
4794 00:56:02.208740 CH 0, Rank 1
4795 00:56:02.208815 SW Impedance : PASS
4796 00:56:02.211804 DUTY Scan : NO K
4797 00:56:02.211894 ZQ Calibration : PASS
4798 00:56:02.215254 Jitter Meter : NO K
4799 00:56:02.218498 CBT Training : PASS
4800 00:56:02.218606 Write leveling : PASS
4801 00:56:02.221964 RX DQS gating : PASS
4802 00:56:02.224973 RX DQ/DQS(RDDQC) : PASS
4803 00:56:02.225048 TX DQ/DQS : PASS
4804 00:56:02.228778 RX DATLAT : PASS
4805 00:56:02.231598 RX DQ/DQS(Engine): PASS
4806 00:56:02.231674 TX OE : NO K
4807 00:56:02.234926 All Pass.
4808 00:56:02.235001
4809 00:56:02.235060 CH 1, Rank 0
4810 00:56:02.238621 SW Impedance : PASS
4811 00:56:02.238696 DUTY Scan : NO K
4812 00:56:02.241740 ZQ Calibration : PASS
4813 00:56:02.244857 Jitter Meter : NO K
4814 00:56:02.244933 CBT Training : PASS
4815 00:56:02.248451 Write leveling : PASS
4816 00:56:02.251795 RX DQS gating : PASS
4817 00:56:02.251870 RX DQ/DQS(RDDQC) : PASS
4818 00:56:02.255184 TX DQ/DQS : PASS
4819 00:56:02.255260 RX DATLAT : PASS
4820 00:56:02.258535 RX DQ/DQS(Engine): PASS
4821 00:56:02.261795 TX OE : NO K
4822 00:56:02.261897 All Pass.
4823 00:56:02.261982
4824 00:56:02.262040 CH 1, Rank 1
4825 00:56:02.265215 SW Impedance : PASS
4826 00:56:02.268071 DUTY Scan : NO K
4827 00:56:02.268146 ZQ Calibration : PASS
4828 00:56:02.271421 Jitter Meter : NO K
4829 00:56:02.274841 CBT Training : PASS
4830 00:56:02.274916 Write leveling : PASS
4831 00:56:02.278212 RX DQS gating : PASS
4832 00:56:02.281500 RX DQ/DQS(RDDQC) : PASS
4833 00:56:02.281639 TX DQ/DQS : PASS
4834 00:56:02.284994 RX DATLAT : PASS
4835 00:56:02.288579 RX DQ/DQS(Engine): PASS
4836 00:56:02.288653 TX OE : NO K
4837 00:56:02.291322 All Pass.
4838 00:56:02.291410
4839 00:56:02.291469 DramC Write-DBI off
4840 00:56:02.294887 PER_BANK_REFRESH: Hybrid Mode
4841 00:56:02.294962 TX_TRACKING: ON
4842 00:56:02.304602 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4843 00:56:02.307979 [FAST_K] Save calibration result to emmc
4844 00:56:02.311391 dramc_set_vcore_voltage set vcore to 662500
4845 00:56:02.314843 Read voltage for 933, 3
4846 00:56:02.314917 Vio18 = 0
4847 00:56:02.318165 Vcore = 662500
4848 00:56:02.318240 Vdram = 0
4849 00:56:02.318299 Vddq = 0
4850 00:56:02.318353 Vmddr = 0
4851 00:56:02.324527 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4852 00:56:02.331604 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4853 00:56:02.331680 MEM_TYPE=3, freq_sel=17
4854 00:56:02.334649 sv_algorithm_assistance_LP4_1600
4855 00:56:02.338143 ============ PULL DRAM RESETB DOWN ============
4856 00:56:02.344833 ========== PULL DRAM RESETB DOWN end =========
4857 00:56:02.347730 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4858 00:56:02.351104 ===================================
4859 00:56:02.354548 LPDDR4 DRAM CONFIGURATION
4860 00:56:02.357837 ===================================
4861 00:56:02.357912 EX_ROW_EN[0] = 0x0
4862 00:56:02.361361 EX_ROW_EN[1] = 0x0
4863 00:56:02.361461 LP4Y_EN = 0x0
4864 00:56:02.364569 WORK_FSP = 0x0
4865 00:56:02.367785 WL = 0x3
4866 00:56:02.367860 RL = 0x3
4867 00:56:02.371266 BL = 0x2
4868 00:56:02.371341 RPST = 0x0
4869 00:56:02.374756 RD_PRE = 0x0
4870 00:56:02.374831 WR_PRE = 0x1
4871 00:56:02.377780 WR_PST = 0x0
4872 00:56:02.377855 DBI_WR = 0x0
4873 00:56:02.380982 DBI_RD = 0x0
4874 00:56:02.381062 OTF = 0x1
4875 00:56:02.384930 ===================================
4876 00:56:02.387764 ===================================
4877 00:56:02.391275 ANA top config
4878 00:56:02.394770 ===================================
4879 00:56:02.394846 DLL_ASYNC_EN = 0
4880 00:56:02.397583 ALL_SLAVE_EN = 1
4881 00:56:02.401074 NEW_RANK_MODE = 1
4882 00:56:02.404594 DLL_IDLE_MODE = 1
4883 00:56:02.404713 LP45_APHY_COMB_EN = 1
4884 00:56:02.408158 TX_ODT_DIS = 1
4885 00:56:02.410932 NEW_8X_MODE = 1
4886 00:56:02.414442 ===================================
4887 00:56:02.417883 ===================================
4888 00:56:02.421467 data_rate = 1866
4889 00:56:02.424208 CKR = 1
4890 00:56:02.427430 DQ_P2S_RATIO = 8
4891 00:56:02.430777 ===================================
4892 00:56:02.430853 CA_P2S_RATIO = 8
4893 00:56:02.434207 DQ_CA_OPEN = 0
4894 00:56:02.437560 DQ_SEMI_OPEN = 0
4895 00:56:02.441010 CA_SEMI_OPEN = 0
4896 00:56:02.444419 CA_FULL_RATE = 0
4897 00:56:02.444495 DQ_CKDIV4_EN = 1
4898 00:56:02.447522 CA_CKDIV4_EN = 1
4899 00:56:02.450830 CA_PREDIV_EN = 0
4900 00:56:02.454279 PH8_DLY = 0
4901 00:56:02.457729 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4902 00:56:02.460965 DQ_AAMCK_DIV = 4
4903 00:56:02.461041 CA_AAMCK_DIV = 4
4904 00:56:02.464755 CA_ADMCK_DIV = 4
4905 00:56:02.468041 DQ_TRACK_CA_EN = 0
4906 00:56:02.471243 CA_PICK = 933
4907 00:56:02.474413 CA_MCKIO = 933
4908 00:56:02.478039 MCKIO_SEMI = 0
4909 00:56:02.481003 PLL_FREQ = 3732
4910 00:56:02.481079 DQ_UI_PI_RATIO = 32
4911 00:56:02.484471 CA_UI_PI_RATIO = 0
4912 00:56:02.488052 ===================================
4913 00:56:02.491149 ===================================
4914 00:56:02.494101 memory_type:LPDDR4
4915 00:56:02.497465 GP_NUM : 10
4916 00:56:02.497540 SRAM_EN : 1
4917 00:56:02.500987 MD32_EN : 0
4918 00:56:02.504325 ===================================
4919 00:56:02.507667 [ANA_INIT] >>>>>>>>>>>>>>
4920 00:56:02.507767 <<<<<< [CONFIGURE PHASE]: ANA_TX
4921 00:56:02.511083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4922 00:56:02.513958 ===================================
4923 00:56:02.517462 data_rate = 1866,PCW = 0X8f00
4924 00:56:02.520943 ===================================
4925 00:56:02.523743 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4926 00:56:02.530529 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 00:56:02.537433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 00:56:02.540831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4929 00:56:02.544233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4930 00:56:02.547728 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4931 00:56:02.550403 [ANA_INIT] flow start
4932 00:56:02.550478 [ANA_INIT] PLL >>>>>>>>
4933 00:56:02.553816 [ANA_INIT] PLL <<<<<<<<
4934 00:56:02.556989 [ANA_INIT] MIDPI >>>>>>>>
4935 00:56:02.560413 [ANA_INIT] MIDPI <<<<<<<<
4936 00:56:02.560487 [ANA_INIT] DLL >>>>>>>>
4937 00:56:02.563800 [ANA_INIT] flow end
4938 00:56:02.567256 ============ LP4 DIFF to SE enter ============
4939 00:56:02.570649 ============ LP4 DIFF to SE exit ============
4940 00:56:02.573894 [ANA_INIT] <<<<<<<<<<<<<
4941 00:56:02.577149 [Flow] Enable top DCM control >>>>>
4942 00:56:02.580446 [Flow] Enable top DCM control <<<<<
4943 00:56:02.584022 Enable DLL master slave shuffle
4944 00:56:02.587475 ==============================================================
4945 00:56:02.590728 Gating Mode config
4946 00:56:02.596955 ==============================================================
4947 00:56:02.597026 Config description:
4948 00:56:02.607154 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4949 00:56:02.614145 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4950 00:56:02.620624 SELPH_MODE 0: By rank 1: By Phase
4951 00:56:02.624107 ==============================================================
4952 00:56:02.627318 GAT_TRACK_EN = 1
4953 00:56:02.630743 RX_GATING_MODE = 2
4954 00:56:02.634193 RX_GATING_TRACK_MODE = 2
4955 00:56:02.636833 SELPH_MODE = 1
4956 00:56:02.640315 PICG_EARLY_EN = 1
4957 00:56:02.643773 VALID_LAT_VALUE = 1
4958 00:56:02.647300 ==============================================================
4959 00:56:02.650695 Enter into Gating configuration >>>>
4960 00:56:02.653488 Exit from Gating configuration <<<<
4961 00:56:02.656967 Enter into DVFS_PRE_config >>>>>
4962 00:56:02.669947 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4963 00:56:02.673731 Exit from DVFS_PRE_config <<<<<
4964 00:56:02.673807 Enter into PICG configuration >>>>
4965 00:56:02.676964 Exit from PICG configuration <<<<
4966 00:56:02.680429 [RX_INPUT] configuration >>>>>
4967 00:56:02.683593 [RX_INPUT] configuration <<<<<
4968 00:56:02.690493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4969 00:56:02.693993 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4970 00:56:02.700069 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 00:56:02.706826 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 00:56:02.713447 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 00:56:02.720230 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 00:56:02.723684 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4975 00:56:02.727066 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4976 00:56:02.730233 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4977 00:56:02.736631 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4978 00:56:02.740009 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4979 00:56:02.743277 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 00:56:02.746635 ===================================
4981 00:56:02.749865 LPDDR4 DRAM CONFIGURATION
4982 00:56:02.753384 ===================================
4983 00:56:02.756872 EX_ROW_EN[0] = 0x0
4984 00:56:02.756948 EX_ROW_EN[1] = 0x0
4985 00:56:02.759730 LP4Y_EN = 0x0
4986 00:56:02.759810 WORK_FSP = 0x0
4987 00:56:02.763265 WL = 0x3
4988 00:56:02.763388 RL = 0x3
4989 00:56:02.766838 BL = 0x2
4990 00:56:02.766913 RPST = 0x0
4991 00:56:02.770398 RD_PRE = 0x0
4992 00:56:02.770469 WR_PRE = 0x1
4993 00:56:02.773139 WR_PST = 0x0
4994 00:56:02.773209 DBI_WR = 0x0
4995 00:56:02.776446 DBI_RD = 0x0
4996 00:56:02.776512 OTF = 0x1
4997 00:56:02.779756 ===================================
4998 00:56:02.783494 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4999 00:56:02.789690 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5000 00:56:02.793172 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 00:56:02.796452 ===================================
5002 00:56:02.800213 LPDDR4 DRAM CONFIGURATION
5003 00:56:02.802982 ===================================
5004 00:56:02.803060 EX_ROW_EN[0] = 0x10
5005 00:56:02.806424 EX_ROW_EN[1] = 0x0
5006 00:56:02.809803 LP4Y_EN = 0x0
5007 00:56:02.809873 WORK_FSP = 0x0
5008 00:56:02.812993 WL = 0x3
5009 00:56:02.813061 RL = 0x3
5010 00:56:02.816880 BL = 0x2
5011 00:56:02.816963 RPST = 0x0
5012 00:56:02.820074 RD_PRE = 0x0
5013 00:56:02.820152 WR_PRE = 0x1
5014 00:56:02.823570 WR_PST = 0x0
5015 00:56:02.823674 DBI_WR = 0x0
5016 00:56:02.826945 DBI_RD = 0x0
5017 00:56:02.827036 OTF = 0x1
5018 00:56:02.829737 ===================================
5019 00:56:02.836510 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5020 00:56:02.840717 nWR fixed to 30
5021 00:56:02.844074 [ModeRegInit_LP4] CH0 RK0
5022 00:56:02.844157 [ModeRegInit_LP4] CH0 RK1
5023 00:56:02.847496 [ModeRegInit_LP4] CH1 RK0
5024 00:56:02.850608 [ModeRegInit_LP4] CH1 RK1
5025 00:56:02.850679 match AC timing 9
5026 00:56:02.856836 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5027 00:56:02.860385 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5028 00:56:02.863741 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5029 00:56:02.870285 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5030 00:56:02.873755 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5031 00:56:02.873843 ==
5032 00:56:02.877229 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 00:56:02.880097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5034 00:56:02.880188 ==
5035 00:56:02.886748 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5036 00:56:02.893356 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5037 00:56:02.896839 [CA 0] Center 37 (6~68) winsize 63
5038 00:56:02.900081 [CA 1] Center 37 (6~68) winsize 63
5039 00:56:02.903285 [CA 2] Center 34 (4~65) winsize 62
5040 00:56:02.906475 [CA 3] Center 34 (3~65) winsize 63
5041 00:56:02.909964 [CA 4] Center 33 (3~64) winsize 62
5042 00:56:02.913324 [CA 5] Center 32 (2~62) winsize 61
5043 00:56:02.913399
5044 00:56:02.916735 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5045 00:56:02.916812
5046 00:56:02.919866 [CATrainingPosCal] consider 1 rank data
5047 00:56:02.923256 u2DelayCellTimex100 = 270/100 ps
5048 00:56:02.926313 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5049 00:56:02.930041 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5050 00:56:02.933323 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5051 00:56:02.936818 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5052 00:56:02.943017 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5053 00:56:02.946452 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5054 00:56:02.946528
5055 00:56:02.949758 CA PerBit enable=1, Macro0, CA PI delay=32
5056 00:56:02.949833
5057 00:56:02.953280 [CBTSetCACLKResult] CA Dly = 32
5058 00:56:02.953356 CS Dly: 5 (0~36)
5059 00:56:02.953415 ==
5060 00:56:02.956619 Dram Type= 6, Freq= 0, CH_0, rank 1
5061 00:56:02.962693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 00:56:02.962770 ==
5063 00:56:02.966110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 00:56:02.973033 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 00:56:02.976164 [CA 0] Center 37 (6~68) winsize 63
5066 00:56:02.979356 [CA 1] Center 37 (7~68) winsize 62
5067 00:56:02.983126 [CA 2] Center 34 (4~65) winsize 62
5068 00:56:02.986185 [CA 3] Center 34 (3~65) winsize 63
5069 00:56:02.989647 [CA 4] Center 32 (2~63) winsize 62
5070 00:56:02.993143 [CA 5] Center 32 (2~62) winsize 61
5071 00:56:02.993219
5072 00:56:02.996498 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 00:56:02.996574
5074 00:56:02.999864 [CATrainingPosCal] consider 2 rank data
5075 00:56:03.003280 u2DelayCellTimex100 = 270/100 ps
5076 00:56:03.005970 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5077 00:56:03.009357 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5078 00:56:03.012854 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5079 00:56:03.019618 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5080 00:56:03.022794 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5081 00:56:03.026155 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5082 00:56:03.026226
5083 00:56:03.029295 CA PerBit enable=1, Macro0, CA PI delay=32
5084 00:56:03.029361
5085 00:56:03.032756 [CBTSetCACLKResult] CA Dly = 32
5086 00:56:03.032820 CS Dly: 5 (0~37)
5087 00:56:03.032876
5088 00:56:03.036174 ----->DramcWriteLeveling(PI) begin...
5089 00:56:03.036239 ==
5090 00:56:03.039506 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 00:56:03.046095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 00:56:03.046172 ==
5093 00:56:03.049187 Write leveling (Byte 0): 30 => 30
5094 00:56:03.052562 Write leveling (Byte 1): 27 => 27
5095 00:56:03.052638 DramcWriteLeveling(PI) end<-----
5096 00:56:03.052696
5097 00:56:03.056070 ==
5098 00:56:03.059552 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 00:56:03.063041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 00:56:03.063124 ==
5101 00:56:03.065862 [Gating] SW mode calibration
5102 00:56:03.072737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 00:56:03.076195 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5104 00:56:03.083004 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (1 1) (1 1)
5105 00:56:03.086293 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 00:56:03.089447 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 00:56:03.096155 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 00:56:03.099126 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 00:56:03.102896 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 00:56:03.109427 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5111 00:56:03.112635 0 14 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
5112 00:56:03.116165 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5113 00:56:03.123244 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 00:56:03.126011 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 00:56:03.129405 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 00:56:03.132848 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 00:56:03.139720 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 00:56:03.143119 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5119 00:56:03.146303 0 15 28 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (0 0)
5120 00:56:03.153183 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5121 00:56:03.156287 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 00:56:03.159247 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 00:56:03.166130 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 00:56:03.169676 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 00:56:03.172657 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 00:56:03.179461 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 00:56:03.182627 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5128 00:56:03.186092 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5129 00:56:03.192319 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 00:56:03.195798 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 00:56:03.199194 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 00:56:03.205937 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 00:56:03.209176 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 00:56:03.212956 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 00:56:03.219363 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 00:56:03.222873 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 00:56:03.226213 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 00:56:03.232423 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 00:56:03.235802 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 00:56:03.239152 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 00:56:03.246110 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 00:56:03.249518 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 00:56:03.252853 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5144 00:56:03.256201 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 00:56:03.259537 Total UI for P1: 0, mck2ui 16
5146 00:56:03.262970 best dqsien dly found for B0: ( 1, 2, 28)
5147 00:56:03.265672 Total UI for P1: 0, mck2ui 16
5148 00:56:03.269423 best dqsien dly found for B1: ( 1, 2, 28)
5149 00:56:03.272700 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5150 00:56:03.275979 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5151 00:56:03.279130
5152 00:56:03.282196 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5153 00:56:03.285895 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5154 00:56:03.288886 [Gating] SW calibration Done
5155 00:56:03.288966 ==
5156 00:56:03.292621 Dram Type= 6, Freq= 0, CH_0, rank 0
5157 00:56:03.295718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 00:56:03.295851 ==
5159 00:56:03.295939 RX Vref Scan: 0
5160 00:56:03.299043
5161 00:56:03.299139 RX Vref 0 -> 0, step: 1
5162 00:56:03.299214
5163 00:56:03.302371 RX Delay -80 -> 252, step: 8
5164 00:56:03.305768 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5165 00:56:03.309244 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5166 00:56:03.315463 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5167 00:56:03.318935 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5168 00:56:03.322399 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5169 00:56:03.325634 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5170 00:56:03.328935 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5171 00:56:03.332614 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5172 00:56:03.339059 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5173 00:56:03.342369 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5174 00:56:03.345331 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5175 00:56:03.348783 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5176 00:56:03.352156 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5177 00:56:03.358823 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5178 00:56:03.361882 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5179 00:56:03.365389 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5180 00:56:03.365490 ==
5181 00:56:03.368862 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 00:56:03.372253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 00:56:03.372332 ==
5184 00:56:03.375725 DQS Delay:
5185 00:56:03.375803 DQS0 = 0, DQS1 = 0
5186 00:56:03.378478 DQM Delay:
5187 00:56:03.378580 DQM0 = 104, DQM1 = 96
5188 00:56:03.378667 DQ Delay:
5189 00:56:03.381911 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5190 00:56:03.385354 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =115
5191 00:56:03.388737 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5192 00:56:03.395146 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5193 00:56:03.395255
5194 00:56:03.395347
5195 00:56:03.395430 ==
5196 00:56:03.398780 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 00:56:03.401759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 00:56:03.401856 ==
5199 00:56:03.401940
5200 00:56:03.402022
5201 00:56:03.405337 TX Vref Scan disable
5202 00:56:03.405427 == TX Byte 0 ==
5203 00:56:03.412199 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5204 00:56:03.415478 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5205 00:56:03.415548 == TX Byte 1 ==
5206 00:56:03.421771 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5207 00:56:03.425204 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5208 00:56:03.425268 ==
5209 00:56:03.428620 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 00:56:03.431465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 00:56:03.431532 ==
5212 00:56:03.431586
5213 00:56:03.431637
5214 00:56:03.434830 TX Vref Scan disable
5215 00:56:03.438226 == TX Byte 0 ==
5216 00:56:03.441733 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5217 00:56:03.445112 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5218 00:56:03.448295 == TX Byte 1 ==
5219 00:56:03.451950 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5220 00:56:03.454954 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5221 00:56:03.455023
5222 00:56:03.458637 [DATLAT]
5223 00:56:03.458704 Freq=933, CH0 RK0
5224 00:56:03.458758
5225 00:56:03.461675 DATLAT Default: 0xd
5226 00:56:03.461741 0, 0xFFFF, sum = 0
5227 00:56:03.464841 1, 0xFFFF, sum = 0
5228 00:56:03.464908 2, 0xFFFF, sum = 0
5229 00:56:03.468370 3, 0xFFFF, sum = 0
5230 00:56:03.468442 4, 0xFFFF, sum = 0
5231 00:56:03.471708 5, 0xFFFF, sum = 0
5232 00:56:03.471828 6, 0xFFFF, sum = 0
5233 00:56:03.475104 7, 0xFFFF, sum = 0
5234 00:56:03.475172 8, 0xFFFF, sum = 0
5235 00:56:03.478540 9, 0xFFFF, sum = 0
5236 00:56:03.478638 10, 0x0, sum = 1
5237 00:56:03.481901 11, 0x0, sum = 2
5238 00:56:03.481993 12, 0x0, sum = 3
5239 00:56:03.484695 13, 0x0, sum = 4
5240 00:56:03.484760 best_step = 11
5241 00:56:03.484844
5242 00:56:03.484923 ==
5243 00:56:03.488179 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 00:56:03.495028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 00:56:03.495104 ==
5246 00:56:03.495163 RX Vref Scan: 1
5247 00:56:03.495227
5248 00:56:03.498411 RX Vref 0 -> 0, step: 1
5249 00:56:03.498478
5250 00:56:03.501732 RX Delay -45 -> 252, step: 4
5251 00:56:03.501803
5252 00:56:03.505148 Set Vref, RX VrefLevel [Byte0]: 55
5253 00:56:03.508422 [Byte1]: 46
5254 00:56:03.508489
5255 00:56:03.511630 Final RX Vref Byte 0 = 55 to rank0
5256 00:56:03.514865 Final RX Vref Byte 1 = 46 to rank0
5257 00:56:03.518050 Final RX Vref Byte 0 = 55 to rank1
5258 00:56:03.521098 Final RX Vref Byte 1 = 46 to rank1==
5259 00:56:03.524430 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 00:56:03.527762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 00:56:03.527840 ==
5262 00:56:03.531430 DQS Delay:
5263 00:56:03.531505 DQS0 = 0, DQS1 = 0
5264 00:56:03.534858 DQM Delay:
5265 00:56:03.534934 DQM0 = 104, DQM1 = 94
5266 00:56:03.534993 DQ Delay:
5267 00:56:03.538431 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5268 00:56:03.541222 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5269 00:56:03.544501 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =90
5270 00:56:03.551513 DQ12 =98, DQ13 =98, DQ14 =106, DQ15 =100
5271 00:56:03.551578
5272 00:56:03.551632
5273 00:56:03.558098 [DQSOSCAuto] RK0, (LSB)MR18= 0x362d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 404 ps
5274 00:56:03.560886 CH0 RK0: MR19=505, MR18=362D
5275 00:56:03.567921 CH0_RK0: MR19=0x505, MR18=0x362D, DQSOSC=404, MR23=63, INC=66, DEC=44
5276 00:56:03.567989
5277 00:56:03.571244 ----->DramcWriteLeveling(PI) begin...
5278 00:56:03.571309 ==
5279 00:56:03.574271 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 00:56:03.578178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 00:56:03.578254 ==
5282 00:56:03.581280 Write leveling (Byte 0): 32 => 32
5283 00:56:03.584692 Write leveling (Byte 1): 27 => 27
5284 00:56:03.587633 DramcWriteLeveling(PI) end<-----
5285 00:56:03.587709
5286 00:56:03.587767 ==
5287 00:56:03.591296 Dram Type= 6, Freq= 0, CH_0, rank 1
5288 00:56:03.594450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 00:56:03.594518 ==
5290 00:56:03.597795 [Gating] SW mode calibration
5291 00:56:03.604554 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5292 00:56:03.611015 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5293 00:56:03.614349 0 14 0 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
5294 00:56:03.617603 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 00:56:03.624559 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 00:56:03.627698 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 00:56:03.631251 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 00:56:03.637806 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 00:56:03.641254 0 14 24 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
5300 00:56:03.644745 0 14 28 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (0 1)
5301 00:56:03.650820 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 00:56:03.654288 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 00:56:03.657739 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 00:56:03.664473 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 00:56:03.667211 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 00:56:03.670703 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 00:56:03.677534 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5308 00:56:03.680998 0 15 28 | B1->B0 | 3737 3535 | 0 0 | (1 1) (1 1)
5309 00:56:03.684310 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 00:56:03.690729 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 00:56:03.694189 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 00:56:03.697534 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 00:56:03.704005 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 00:56:03.707116 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 00:56:03.710685 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 00:56:03.717239 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5317 00:56:03.720939 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5318 00:56:03.724434 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 00:56:03.730676 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 00:56:03.734160 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 00:56:03.737067 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 00:56:03.740399 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 00:56:03.747259 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 00:56:03.750268 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 00:56:03.754073 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 00:56:03.760305 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 00:56:03.763729 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 00:56:03.770435 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 00:56:03.773829 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 00:56:03.776772 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 00:56:03.783481 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 00:56:03.787011 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5333 00:56:03.789806 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 00:56:03.793220 Total UI for P1: 0, mck2ui 16
5335 00:56:03.796752 best dqsien dly found for B0: ( 1, 2, 28)
5336 00:56:03.800152 Total UI for P1: 0, mck2ui 16
5337 00:56:03.803573 best dqsien dly found for B1: ( 1, 2, 28)
5338 00:56:03.807129 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5339 00:56:03.809913 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5340 00:56:03.809989
5341 00:56:03.813361 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5342 00:56:03.820017 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5343 00:56:03.820093 [Gating] SW calibration Done
5344 00:56:03.820152 ==
5345 00:56:03.823128 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 00:56:03.829750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 00:56:03.829827 ==
5348 00:56:03.829887 RX Vref Scan: 0
5349 00:56:03.829958
5350 00:56:03.833084 RX Vref 0 -> 0, step: 1
5351 00:56:03.833158
5352 00:56:03.837164 RX Delay -80 -> 252, step: 8
5353 00:56:03.839752 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5354 00:56:03.843350 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5355 00:56:03.846948 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5356 00:56:03.849490 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5357 00:56:03.856307 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5358 00:56:03.859892 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5359 00:56:03.863327 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5360 00:56:03.866477 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5361 00:56:03.869754 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5362 00:56:03.872731 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5363 00:56:03.879654 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5364 00:56:03.882739 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5365 00:56:03.886081 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5366 00:56:03.889569 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5367 00:56:03.892949 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5368 00:56:03.896499 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5369 00:56:03.899839 ==
5370 00:56:03.902661 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 00:56:03.906082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 00:56:03.906159 ==
5373 00:56:03.906218 DQS Delay:
5374 00:56:03.909573 DQS0 = 0, DQS1 = 0
5375 00:56:03.909663 DQM Delay:
5376 00:56:03.913039 DQM0 = 105, DQM1 = 94
5377 00:56:03.913115 DQ Delay:
5378 00:56:03.916411 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5379 00:56:03.919274 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5380 00:56:03.922740 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5381 00:56:03.926252 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5382 00:56:03.926328
5383 00:56:03.926388
5384 00:56:03.926442 ==
5385 00:56:03.929538 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 00:56:03.932746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 00:56:03.935989 ==
5388 00:56:03.936065
5389 00:56:03.936138
5390 00:56:03.936216 TX Vref Scan disable
5391 00:56:03.939219 == TX Byte 0 ==
5392 00:56:03.942629 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5393 00:56:03.946174 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5394 00:56:03.949503 == TX Byte 1 ==
5395 00:56:03.952577 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5396 00:56:03.955943 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5397 00:56:03.956019 ==
5398 00:56:03.959474 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 00:56:03.965712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 00:56:03.965788 ==
5401 00:56:03.965848
5402 00:56:03.965903
5403 00:56:03.969012 TX Vref Scan disable
5404 00:56:03.969122 == TX Byte 0 ==
5405 00:56:03.975833 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5406 00:56:03.979203 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5407 00:56:03.979279 == TX Byte 1 ==
5408 00:56:03.985674 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5409 00:56:03.989350 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5410 00:56:03.989425
5411 00:56:03.989483 [DATLAT]
5412 00:56:03.992788 Freq=933, CH0 RK1
5413 00:56:03.992864
5414 00:56:03.992921 DATLAT Default: 0xb
5415 00:56:03.995734 0, 0xFFFF, sum = 0
5416 00:56:03.995810 1, 0xFFFF, sum = 0
5417 00:56:03.998939 2, 0xFFFF, sum = 0
5418 00:56:03.999016 3, 0xFFFF, sum = 0
5419 00:56:04.002171 4, 0xFFFF, sum = 0
5420 00:56:04.002247 5, 0xFFFF, sum = 0
5421 00:56:04.005680 6, 0xFFFF, sum = 0
5422 00:56:04.005756 7, 0xFFFF, sum = 0
5423 00:56:04.009174 8, 0xFFFF, sum = 0
5424 00:56:04.012421 9, 0xFFFF, sum = 0
5425 00:56:04.012498 10, 0x0, sum = 1
5426 00:56:04.012558 11, 0x0, sum = 2
5427 00:56:04.015767 12, 0x0, sum = 3
5428 00:56:04.015844 13, 0x0, sum = 4
5429 00:56:04.019064 best_step = 11
5430 00:56:04.019141
5431 00:56:04.019198 ==
5432 00:56:04.022498 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 00:56:04.025844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 00:56:04.025921 ==
5435 00:56:04.028614 RX Vref Scan: 0
5436 00:56:04.028689
5437 00:56:04.028747 RX Vref 0 -> 0, step: 1
5438 00:56:04.028801
5439 00:56:04.032074 RX Delay -45 -> 252, step: 4
5440 00:56:04.039629 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5441 00:56:04.042759 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5442 00:56:04.046215 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5443 00:56:04.048982 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5444 00:56:04.052997 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5445 00:56:04.059462 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5446 00:56:04.062790 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5447 00:56:04.066099 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5448 00:56:04.068934 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5449 00:56:04.072348 iDelay=199, Bit 9, Center 84 (3 ~ 166) 164
5450 00:56:04.075795 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5451 00:56:04.082544 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5452 00:56:04.086035 iDelay=199, Bit 12, Center 98 (19 ~ 178) 160
5453 00:56:04.089527 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5454 00:56:04.092297 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5455 00:56:04.095733 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5456 00:56:04.099111 ==
5457 00:56:04.102419 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 00:56:04.105853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 00:56:04.105930 ==
5460 00:56:04.105989 DQS Delay:
5461 00:56:04.109039 DQS0 = 0, DQS1 = 0
5462 00:56:04.109114 DQM Delay:
5463 00:56:04.112760 DQM0 = 104, DQM1 = 93
5464 00:56:04.112835 DQ Delay:
5465 00:56:04.115544 DQ0 =100, DQ1 =106, DQ2 =102, DQ3 =102
5466 00:56:04.118827 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5467 00:56:04.122694 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =86
5468 00:56:04.125883 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102
5469 00:56:04.125961
5470 00:56:04.126020
5471 00:56:04.135572 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 407 ps
5472 00:56:04.135649 CH0 RK1: MR19=505, MR18=2F08
5473 00:56:04.142401 CH0_RK1: MR19=0x505, MR18=0x2F08, DQSOSC=407, MR23=63, INC=65, DEC=43
5474 00:56:04.145661 [RxdqsGatingPostProcess] freq 933
5475 00:56:04.152437 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5476 00:56:04.155626 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 00:56:04.159324 best DQS1 dly(2T, 0.5T) = (0, 10)
5478 00:56:04.162606 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 00:56:04.165536 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5480 00:56:04.165637 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 00:56:04.168700 best DQS1 dly(2T, 0.5T) = (0, 10)
5482 00:56:04.172674 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 00:56:04.175517 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5484 00:56:04.178938 Pre-setting of DQS Precalculation
5485 00:56:04.185655 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5486 00:56:04.185734 ==
5487 00:56:04.189108 Dram Type= 6, Freq= 0, CH_1, rank 0
5488 00:56:04.192538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 00:56:04.192615 ==
5490 00:56:04.198834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5491 00:56:04.205571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5492 00:56:04.209076 [CA 0] Center 36 (6~67) winsize 62
5493 00:56:04.212441 [CA 1] Center 37 (6~68) winsize 63
5494 00:56:04.215782 [CA 2] Center 34 (4~65) winsize 62
5495 00:56:04.218543 [CA 3] Center 34 (4~65) winsize 62
5496 00:56:04.221945 [CA 4] Center 34 (4~65) winsize 62
5497 00:56:04.222022 [CA 5] Center 33 (3~64) winsize 62
5498 00:56:04.225304
5499 00:56:04.228765 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5500 00:56:04.228841
5501 00:56:04.231988 [CATrainingPosCal] consider 1 rank data
5502 00:56:04.235338 u2DelayCellTimex100 = 270/100 ps
5503 00:56:04.238767 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5504 00:56:04.242124 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5505 00:56:04.245287 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5506 00:56:04.248570 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5507 00:56:04.251703 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5508 00:56:04.255327 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5509 00:56:04.255403
5510 00:56:04.258577 CA PerBit enable=1, Macro0, CA PI delay=33
5511 00:56:04.261861
5512 00:56:04.261936 [CBTSetCACLKResult] CA Dly = 33
5513 00:56:04.265186 CS Dly: 6 (0~37)
5514 00:56:04.265279 ==
5515 00:56:04.268503 Dram Type= 6, Freq= 0, CH_1, rank 1
5516 00:56:04.271627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 00:56:04.271705 ==
5518 00:56:04.278364 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 00:56:04.285032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5520 00:56:04.288564 [CA 0] Center 37 (6~68) winsize 63
5521 00:56:04.291604 [CA 1] Center 37 (7~68) winsize 62
5522 00:56:04.295058 [CA 2] Center 35 (4~66) winsize 63
5523 00:56:04.298468 [CA 3] Center 34 (4~65) winsize 62
5524 00:56:04.302073 [CA 4] Center 34 (4~65) winsize 62
5525 00:56:04.304826 [CA 5] Center 34 (4~64) winsize 61
5526 00:56:04.304902
5527 00:56:04.308144 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5528 00:56:04.308220
5529 00:56:04.311612 [CATrainingPosCal] consider 2 rank data
5530 00:56:04.315089 u2DelayCellTimex100 = 270/100 ps
5531 00:56:04.318354 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5532 00:56:04.321817 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5533 00:56:04.325176 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5534 00:56:04.328598 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5535 00:56:04.331873 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5536 00:56:04.335151 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5537 00:56:04.335228
5538 00:56:04.338414 CA PerBit enable=1, Macro0, CA PI delay=34
5539 00:56:04.341819
5540 00:56:04.341894 [CBTSetCACLKResult] CA Dly = 34
5541 00:56:04.345209 CS Dly: 7 (0~40)
5542 00:56:04.345284
5543 00:56:04.348016 ----->DramcWriteLeveling(PI) begin...
5544 00:56:04.348096 ==
5545 00:56:04.351482 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 00:56:04.355027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 00:56:04.355104 ==
5548 00:56:04.358601 Write leveling (Byte 0): 26 => 26
5549 00:56:04.362034 Write leveling (Byte 1): 26 => 26
5550 00:56:04.365431 DramcWriteLeveling(PI) end<-----
5551 00:56:04.365507
5552 00:56:04.365589 ==
5553 00:56:04.368108 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 00:56:04.371436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 00:56:04.371513 ==
5556 00:56:04.374762 [Gating] SW mode calibration
5557 00:56:04.381415 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5558 00:56:04.387968 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5559 00:56:04.391509 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 00:56:04.398159 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 00:56:04.401437 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 00:56:04.404524 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 00:56:04.411219 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 00:56:04.414705 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 00:56:04.418111 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 1)
5566 00:56:04.424958 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 1) (1 0)
5567 00:56:04.428376 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 00:56:04.431832 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 00:56:04.434699 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 00:56:04.441493 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 00:56:04.444810 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 00:56:04.447960 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 00:56:04.455025 0 15 24 | B1->B0 | 2828 3737 | 0 1 | (0 0) (0 0)
5574 00:56:04.458458 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 00:56:04.461757 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 00:56:04.468520 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 00:56:04.471800 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 00:56:04.475205 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 00:56:04.481534 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 00:56:04.485126 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 00:56:04.488388 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5582 00:56:04.494509 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 00:56:04.498290 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 00:56:04.501468 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 00:56:04.508030 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 00:56:04.511133 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 00:56:04.514385 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 00:56:04.521055 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 00:56:04.524604 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 00:56:04.527986 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 00:56:04.534920 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 00:56:04.538004 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 00:56:04.541403 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 00:56:04.547640 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 00:56:04.550998 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 00:56:04.554771 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 00:56:04.558154 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5598 00:56:04.564238 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5599 00:56:04.567709 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 00:56:04.571137 Total UI for P1: 0, mck2ui 16
5601 00:56:04.574547 best dqsien dly found for B0: ( 1, 2, 26)
5602 00:56:04.577364 Total UI for P1: 0, mck2ui 16
5603 00:56:04.580878 best dqsien dly found for B1: ( 1, 2, 26)
5604 00:56:04.584340 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5605 00:56:04.587848 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5606 00:56:04.587945
5607 00:56:04.591281 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5608 00:56:04.594609 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5609 00:56:04.598029 [Gating] SW calibration Done
5610 00:56:04.598097 ==
5611 00:56:04.600793 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 00:56:04.607844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 00:56:04.607914 ==
5614 00:56:04.607970 RX Vref Scan: 0
5615 00:56:04.608023
5616 00:56:04.611181 RX Vref 0 -> 0, step: 1
5617 00:56:04.611271
5618 00:56:04.614290 RX Delay -80 -> 252, step: 8
5619 00:56:04.617444 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5620 00:56:04.621193 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5621 00:56:04.624288 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5622 00:56:04.627385 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5623 00:56:04.631124 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5624 00:56:04.637429 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5625 00:56:04.640498 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5626 00:56:04.644180 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5627 00:56:04.647651 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5628 00:56:04.650668 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5629 00:56:04.657228 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5630 00:56:04.660484 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5631 00:56:04.663819 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5632 00:56:04.667112 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5633 00:56:04.670623 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5634 00:56:04.677530 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5635 00:56:04.677631 ==
5636 00:56:04.680944 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 00:56:04.683836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 00:56:04.683913 ==
5639 00:56:04.683972 DQS Delay:
5640 00:56:04.687403 DQS0 = 0, DQS1 = 0
5641 00:56:04.687478 DQM Delay:
5642 00:56:04.690727 DQM0 = 102, DQM1 = 98
5643 00:56:04.690803 DQ Delay:
5644 00:56:04.694227 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5645 00:56:04.696943 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5646 00:56:04.700426 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5647 00:56:04.703902 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5648 00:56:04.703978
5649 00:56:04.704037
5650 00:56:04.704091 ==
5651 00:56:04.707324 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 00:56:04.710930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 00:56:04.713736 ==
5654 00:56:04.713811
5655 00:56:04.713869
5656 00:56:04.713922 TX Vref Scan disable
5657 00:56:04.717167 == TX Byte 0 ==
5658 00:56:04.720649 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5659 00:56:04.724019 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5660 00:56:04.727104 == TX Byte 1 ==
5661 00:56:04.730392 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5662 00:56:04.733716 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5663 00:56:04.736915 ==
5664 00:56:04.740617 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 00:56:04.743802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 00:56:04.743878 ==
5667 00:56:04.743938
5668 00:56:04.743991
5669 00:56:04.747129 TX Vref Scan disable
5670 00:56:04.747205 == TX Byte 0 ==
5671 00:56:04.753773 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5672 00:56:04.756923 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5673 00:56:04.757002 == TX Byte 1 ==
5674 00:56:04.763980 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5675 00:56:04.766879 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5676 00:56:04.766965
5677 00:56:04.767025 [DATLAT]
5678 00:56:04.770571 Freq=933, CH1 RK0
5679 00:56:04.770661
5680 00:56:04.770721 DATLAT Default: 0xd
5681 00:56:04.773568 0, 0xFFFF, sum = 0
5682 00:56:04.773646 1, 0xFFFF, sum = 0
5683 00:56:04.777050 2, 0xFFFF, sum = 0
5684 00:56:04.777127 3, 0xFFFF, sum = 0
5685 00:56:04.780098 4, 0xFFFF, sum = 0
5686 00:56:04.780176 5, 0xFFFF, sum = 0
5687 00:56:04.783434 6, 0xFFFF, sum = 0
5688 00:56:04.783511 7, 0xFFFF, sum = 0
5689 00:56:04.786669 8, 0xFFFF, sum = 0
5690 00:56:04.790096 9, 0xFFFF, sum = 0
5691 00:56:04.790173 10, 0x0, sum = 1
5692 00:56:04.790233 11, 0x0, sum = 2
5693 00:56:04.793685 12, 0x0, sum = 3
5694 00:56:04.793762 13, 0x0, sum = 4
5695 00:56:04.797145 best_step = 11
5696 00:56:04.797221
5697 00:56:04.797279 ==
5698 00:56:04.800514 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 00:56:04.803866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 00:56:04.803942 ==
5701 00:56:04.807091 RX Vref Scan: 1
5702 00:56:04.807166
5703 00:56:04.807224 RX Vref 0 -> 0, step: 1
5704 00:56:04.807280
5705 00:56:04.809896 RX Delay -45 -> 252, step: 4
5706 00:56:04.809972
5707 00:56:04.813427 Set Vref, RX VrefLevel [Byte0]: 51
5708 00:56:04.816977 [Byte1]: 52
5709 00:56:04.821276
5710 00:56:04.821350 Final RX Vref Byte 0 = 51 to rank0
5711 00:56:04.823961 Final RX Vref Byte 1 = 52 to rank0
5712 00:56:04.827422 Final RX Vref Byte 0 = 51 to rank1
5713 00:56:04.830741 Final RX Vref Byte 1 = 52 to rank1==
5714 00:56:04.834097 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 00:56:04.840795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 00:56:04.840872 ==
5717 00:56:04.840931 DQS Delay:
5718 00:56:04.840985 DQS0 = 0, DQS1 = 0
5719 00:56:04.844196 DQM Delay:
5720 00:56:04.844272 DQM0 = 102, DQM1 = 98
5721 00:56:04.847523 DQ Delay:
5722 00:56:04.850757 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5723 00:56:04.853934 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5724 00:56:04.857746 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5725 00:56:04.860505 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5726 00:56:04.860580
5727 00:56:04.860639
5728 00:56:04.867424 [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5729 00:56:04.870590 CH1 RK0: MR19=505, MR18=1931
5730 00:56:04.877519 CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43
5731 00:56:04.877626
5732 00:56:04.880920 ----->DramcWriteLeveling(PI) begin...
5733 00:56:04.881025 ==
5734 00:56:04.884250 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 00:56:04.887287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 00:56:04.887379 ==
5737 00:56:04.890635 Write leveling (Byte 0): 26 => 26
5738 00:56:04.893756 Write leveling (Byte 1): 28 => 28
5739 00:56:04.897228 DramcWriteLeveling(PI) end<-----
5740 00:56:04.897312
5741 00:56:04.897368 ==
5742 00:56:04.900767 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 00:56:04.907117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 00:56:04.907184 ==
5745 00:56:04.907239 [Gating] SW mode calibration
5746 00:56:04.917014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5747 00:56:04.920480 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5748 00:56:04.923879 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 00:56:04.930088 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 00:56:04.933622 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 00:56:04.936987 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 00:56:04.943729 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 00:56:04.946938 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 00:56:04.950354 0 14 24 | B1->B0 | 2f2f 3333 | 0 1 | (0 0) (1 0)
5755 00:56:04.957150 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5756 00:56:04.960462 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 00:56:04.963707 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 00:56:04.970196 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 00:56:04.973601 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 00:56:04.976998 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 00:56:04.983484 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 00:56:04.986762 0 15 24 | B1->B0 | 3a3a 2d2d | 0 0 | (0 0) (0 0)
5763 00:56:04.990101 0 15 28 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
5764 00:56:04.997028 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 00:56:05.000308 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 00:56:05.003532 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 00:56:05.010520 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 00:56:05.013105 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 00:56:05.016412 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 00:56:05.023257 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5771 00:56:05.026665 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5772 00:56:05.030171 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 00:56:05.036322 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 00:56:05.039817 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 00:56:05.043146 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 00:56:05.046537 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 00:56:05.052860 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 00:56:05.056690 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 00:56:05.060120 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 00:56:05.066490 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 00:56:05.069934 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 00:56:05.073100 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 00:56:05.079436 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 00:56:05.082702 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 00:56:05.086163 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5786 00:56:05.092650 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5787 00:56:05.096270 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 00:56:05.099571 Total UI for P1: 0, mck2ui 16
5789 00:56:05.102980 best dqsien dly found for B0: ( 1, 2, 24)
5790 00:56:05.106524 Total UI for P1: 0, mck2ui 16
5791 00:56:05.109925 best dqsien dly found for B1: ( 1, 2, 26)
5792 00:56:05.113236 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5793 00:56:05.116346 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5794 00:56:05.116422
5795 00:56:05.119500 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5796 00:56:05.122829 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5797 00:56:05.126029 [Gating] SW calibration Done
5798 00:56:05.126105 ==
5799 00:56:05.129680 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 00:56:05.136079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 00:56:05.136155 ==
5802 00:56:05.136224 RX Vref Scan: 0
5803 00:56:05.136308
5804 00:56:05.139610 RX Vref 0 -> 0, step: 1
5805 00:56:05.139675
5806 00:56:05.143182 RX Delay -80 -> 252, step: 8
5807 00:56:05.145849 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5808 00:56:05.149674 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5809 00:56:05.152470 iDelay=208, Bit 2, Center 91 (8 ~ 175) 168
5810 00:56:05.155975 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5811 00:56:05.159384 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5812 00:56:05.166110 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5813 00:56:05.169515 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5814 00:56:05.173012 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5815 00:56:05.176319 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5816 00:56:05.179154 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5817 00:56:05.182456 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5818 00:56:05.189222 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5819 00:56:05.192603 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5820 00:56:05.196035 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5821 00:56:05.199281 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5822 00:56:05.202458 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5823 00:56:05.206009 ==
5824 00:56:05.206075 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 00:56:05.212689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 00:56:05.212759 ==
5827 00:56:05.212815 DQS Delay:
5828 00:56:05.216143 DQS0 = 0, DQS1 = 0
5829 00:56:05.216218 DQM Delay:
5830 00:56:05.219590 DQM0 = 102, DQM1 = 99
5831 00:56:05.219673 DQ Delay:
5832 00:56:05.222199 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5833 00:56:05.225695 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5834 00:56:05.229062 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5835 00:56:05.232510 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5836 00:56:05.232585
5837 00:56:05.232643
5838 00:56:05.232695 ==
5839 00:56:05.235568 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 00:56:05.239324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 00:56:05.239433 ==
5842 00:56:05.242823
5843 00:56:05.242898
5844 00:56:05.242955 TX Vref Scan disable
5845 00:56:05.246006 == TX Byte 0 ==
5846 00:56:05.249324 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5847 00:56:05.252479 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5848 00:56:05.255813 == TX Byte 1 ==
5849 00:56:05.259316 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5850 00:56:05.262114 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5851 00:56:05.262201 ==
5852 00:56:05.265535 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 00:56:05.272192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 00:56:05.272280 ==
5855 00:56:05.272339
5856 00:56:05.272392
5857 00:56:05.272443 TX Vref Scan disable
5858 00:56:05.276320 == TX Byte 0 ==
5859 00:56:05.279600 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5860 00:56:05.286365 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5861 00:56:05.286441 == TX Byte 1 ==
5862 00:56:05.289882 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5863 00:56:05.293052 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5864 00:56:05.296812
5865 00:56:05.296895 [DATLAT]
5866 00:56:05.296956 Freq=933, CH1 RK1
5867 00:56:05.297011
5868 00:56:05.300042 DATLAT Default: 0xb
5869 00:56:05.300163 0, 0xFFFF, sum = 0
5870 00:56:05.302895 1, 0xFFFF, sum = 0
5871 00:56:05.302995 2, 0xFFFF, sum = 0
5872 00:56:05.306273 3, 0xFFFF, sum = 0
5873 00:56:05.306343 4, 0xFFFF, sum = 0
5874 00:56:05.309741 5, 0xFFFF, sum = 0
5875 00:56:05.312790 6, 0xFFFF, sum = 0
5876 00:56:05.312887 7, 0xFFFF, sum = 0
5877 00:56:05.316386 8, 0xFFFF, sum = 0
5878 00:56:05.316477 9, 0xFFFF, sum = 0
5879 00:56:05.319673 10, 0x0, sum = 1
5880 00:56:05.319750 11, 0x0, sum = 2
5881 00:56:05.319811 12, 0x0, sum = 3
5882 00:56:05.323117 13, 0x0, sum = 4
5883 00:56:05.323194 best_step = 11
5884 00:56:05.323253
5885 00:56:05.326412 ==
5886 00:56:05.326491 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 00:56:05.333247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 00:56:05.333325 ==
5889 00:56:05.333386 RX Vref Scan: 0
5890 00:56:05.333440
5891 00:56:05.336030 RX Vref 0 -> 0, step: 1
5892 00:56:05.336105
5893 00:56:05.339389 RX Delay -45 -> 252, step: 4
5894 00:56:05.342733 iDelay=199, Bit 0, Center 108 (27 ~ 190) 164
5895 00:56:05.349462 iDelay=199, Bit 1, Center 100 (19 ~ 182) 164
5896 00:56:05.352758 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5897 00:56:05.356194 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5898 00:56:05.359825 iDelay=199, Bit 4, Center 98 (19 ~ 178) 160
5899 00:56:05.362845 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5900 00:56:05.369804 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5901 00:56:05.373118 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5902 00:56:05.375874 iDelay=199, Bit 8, Center 88 (3 ~ 174) 172
5903 00:56:05.379843 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5904 00:56:05.382544 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5905 00:56:05.385934 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5906 00:56:05.392772 iDelay=199, Bit 12, Center 110 (23 ~ 198) 176
5907 00:56:05.396116 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5908 00:56:05.399525 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5909 00:56:05.402759 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5910 00:56:05.402838 ==
5911 00:56:05.406137 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 00:56:05.412882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 00:56:05.412952 ==
5914 00:56:05.413024 DQS Delay:
5915 00:56:05.415685 DQS0 = 0, DQS1 = 0
5916 00:56:05.415784 DQM Delay:
5917 00:56:05.415868 DQM0 = 104, DQM1 = 99
5918 00:56:05.419072 DQ Delay:
5919 00:56:05.422826 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5920 00:56:05.425947 DQ4 =98, DQ5 =116, DQ6 =114, DQ7 =102
5921 00:56:05.429334 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =92
5922 00:56:05.432720 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5923 00:56:05.432796
5924 00:56:05.432855
5925 00:56:05.439471 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5926 00:56:05.443023 CH1 RK1: MR19=505, MR18=2E01
5927 00:56:05.449144 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5928 00:56:05.452487 [RxdqsGatingPostProcess] freq 933
5929 00:56:05.459299 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5930 00:56:05.462691 best DQS0 dly(2T, 0.5T) = (0, 10)
5931 00:56:05.466016 best DQS1 dly(2T, 0.5T) = (0, 10)
5932 00:56:05.468792 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5933 00:56:05.468860 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5934 00:56:05.472768 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 00:56:05.476057 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 00:56:05.479468 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 00:56:05.482688 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 00:56:05.485848 Pre-setting of DQS Precalculation
5939 00:56:05.492315 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5940 00:56:05.498986 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5941 00:56:05.505743 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5942 00:56:05.505816
5943 00:56:05.505873
5944 00:56:05.509080 [Calibration Summary] 1866 Mbps
5945 00:56:05.509145 CH 0, Rank 0
5946 00:56:05.512459 SW Impedance : PASS
5947 00:56:05.515930 DUTY Scan : NO K
5948 00:56:05.515996 ZQ Calibration : PASS
5949 00:56:05.518736 Jitter Meter : NO K
5950 00:56:05.522159 CBT Training : PASS
5951 00:56:05.522228 Write leveling : PASS
5952 00:56:05.525579 RX DQS gating : PASS
5953 00:56:05.525661 RX DQ/DQS(RDDQC) : PASS
5954 00:56:05.528921 TX DQ/DQS : PASS
5955 00:56:05.532132 RX DATLAT : PASS
5956 00:56:05.532209 RX DQ/DQS(Engine): PASS
5957 00:56:05.535392 TX OE : NO K
5958 00:56:05.535484 All Pass.
5959 00:56:05.535574
5960 00:56:05.539149 CH 0, Rank 1
5961 00:56:05.539218 SW Impedance : PASS
5962 00:56:05.542467 DUTY Scan : NO K
5963 00:56:05.546031 ZQ Calibration : PASS
5964 00:56:05.546106 Jitter Meter : NO K
5965 00:56:05.548652 CBT Training : PASS
5966 00:56:05.552164 Write leveling : PASS
5967 00:56:05.552239 RX DQS gating : PASS
5968 00:56:05.555470 RX DQ/DQS(RDDQC) : PASS
5969 00:56:05.558636 TX DQ/DQS : PASS
5970 00:56:05.558712 RX DATLAT : PASS
5971 00:56:05.561988 RX DQ/DQS(Engine): PASS
5972 00:56:05.565228 TX OE : NO K
5973 00:56:05.565304 All Pass.
5974 00:56:05.565362
5975 00:56:05.565415 CH 1, Rank 0
5976 00:56:05.568664 SW Impedance : PASS
5977 00:56:05.571970 DUTY Scan : NO K
5978 00:56:05.572045 ZQ Calibration : PASS
5979 00:56:05.575498 Jitter Meter : NO K
5980 00:56:05.578877 CBT Training : PASS
5981 00:56:05.578952 Write leveling : PASS
5982 00:56:05.582190 RX DQS gating : PASS
5983 00:56:05.582266 RX DQ/DQS(RDDQC) : PASS
5984 00:56:05.585576 TX DQ/DQS : PASS
5985 00:56:05.589143 RX DATLAT : PASS
5986 00:56:05.589234 RX DQ/DQS(Engine): PASS
5987 00:56:05.591863 TX OE : NO K
5988 00:56:05.591939 All Pass.
5989 00:56:05.592011
5990 00:56:05.595270 CH 1, Rank 1
5991 00:56:05.595353 SW Impedance : PASS
5992 00:56:05.598630 DUTY Scan : NO K
5993 00:56:05.602458 ZQ Calibration : PASS
5994 00:56:05.602533 Jitter Meter : NO K
5995 00:56:05.605688 CBT Training : PASS
5996 00:56:05.608722 Write leveling : PASS
5997 00:56:05.608797 RX DQS gating : PASS
5998 00:56:05.612462 RX DQ/DQS(RDDQC) : PASS
5999 00:56:05.615188 TX DQ/DQS : PASS
6000 00:56:05.615260 RX DATLAT : PASS
6001 00:56:05.618524 RX DQ/DQS(Engine): PASS
6002 00:56:05.622232 TX OE : NO K
6003 00:56:05.622302 All Pass.
6004 00:56:05.622364
6005 00:56:05.622424 DramC Write-DBI off
6006 00:56:05.625106 PER_BANK_REFRESH: Hybrid Mode
6007 00:56:05.628732 TX_TRACKING: ON
6008 00:56:05.635722 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6009 00:56:05.638450 [FAST_K] Save calibration result to emmc
6010 00:56:05.645692 dramc_set_vcore_voltage set vcore to 650000
6011 00:56:05.645771 Read voltage for 400, 6
6012 00:56:05.645830 Vio18 = 0
6013 00:56:05.648790 Vcore = 650000
6014 00:56:05.648863 Vdram = 0
6015 00:56:05.648923 Vddq = 0
6016 00:56:05.651831 Vmddr = 0
6017 00:56:05.655293 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6018 00:56:05.662035 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6019 00:56:05.662111 MEM_TYPE=3, freq_sel=20
6020 00:56:05.665317 sv_algorithm_assistance_LP4_800
6021 00:56:05.672293 ============ PULL DRAM RESETB DOWN ============
6022 00:56:05.675730 ========== PULL DRAM RESETB DOWN end =========
6023 00:56:05.678552 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6024 00:56:05.682017 ===================================
6025 00:56:05.685451 LPDDR4 DRAM CONFIGURATION
6026 00:56:05.688167 ===================================
6027 00:56:05.691658 EX_ROW_EN[0] = 0x0
6028 00:56:05.691733 EX_ROW_EN[1] = 0x0
6029 00:56:05.695018 LP4Y_EN = 0x0
6030 00:56:05.695093 WORK_FSP = 0x0
6031 00:56:05.698461 WL = 0x2
6032 00:56:05.698536 RL = 0x2
6033 00:56:05.701822 BL = 0x2
6034 00:56:05.701896 RPST = 0x0
6035 00:56:05.705289 RD_PRE = 0x0
6036 00:56:05.705365 WR_PRE = 0x1
6037 00:56:05.708853 WR_PST = 0x0
6038 00:56:05.708952 DBI_WR = 0x0
6039 00:56:05.711670 DBI_RD = 0x0
6040 00:56:05.711763 OTF = 0x1
6041 00:56:05.715133 ===================================
6042 00:56:05.718531 ===================================
6043 00:56:05.721842 ANA top config
6044 00:56:05.725321 ===================================
6045 00:56:05.728433 DLL_ASYNC_EN = 0
6046 00:56:05.728510 ALL_SLAVE_EN = 1
6047 00:56:05.732065 NEW_RANK_MODE = 1
6048 00:56:05.734820 DLL_IDLE_MODE = 1
6049 00:56:05.738455 LP45_APHY_COMB_EN = 1
6050 00:56:05.738531 TX_ODT_DIS = 1
6051 00:56:05.741522 NEW_8X_MODE = 1
6052 00:56:05.745026 ===================================
6053 00:56:05.747877 ===================================
6054 00:56:05.751305 data_rate = 800
6055 00:56:05.754643 CKR = 1
6056 00:56:05.758164 DQ_P2S_RATIO = 4
6057 00:56:05.761165 ===================================
6058 00:56:05.764994 CA_P2S_RATIO = 4
6059 00:56:05.765071 DQ_CA_OPEN = 0
6060 00:56:05.768071 DQ_SEMI_OPEN = 1
6061 00:56:05.771523 CA_SEMI_OPEN = 1
6062 00:56:05.774597 CA_FULL_RATE = 0
6063 00:56:05.777855 DQ_CKDIV4_EN = 0
6064 00:56:05.781136 CA_CKDIV4_EN = 1
6065 00:56:05.781212 CA_PREDIV_EN = 0
6066 00:56:05.784618 PH8_DLY = 0
6067 00:56:05.788043 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6068 00:56:05.791272 DQ_AAMCK_DIV = 0
6069 00:56:05.794849 CA_AAMCK_DIV = 0
6070 00:56:05.798329 CA_ADMCK_DIV = 4
6071 00:56:05.798405 DQ_TRACK_CA_EN = 0
6072 00:56:05.801048 CA_PICK = 800
6073 00:56:05.804344 CA_MCKIO = 400
6074 00:56:05.807701 MCKIO_SEMI = 400
6075 00:56:05.811198 PLL_FREQ = 3016
6076 00:56:05.814679 DQ_UI_PI_RATIO = 32
6077 00:56:05.818071 CA_UI_PI_RATIO = 32
6078 00:56:05.821439 ===================================
6079 00:56:05.825063 ===================================
6080 00:56:05.825138 memory_type:LPDDR4
6081 00:56:05.827790 GP_NUM : 10
6082 00:56:05.831225 SRAM_EN : 1
6083 00:56:05.831301 MD32_EN : 0
6084 00:56:05.834561 ===================================
6085 00:56:05.838095 [ANA_INIT] >>>>>>>>>>>>>>
6086 00:56:05.841448 <<<<<< [CONFIGURE PHASE]: ANA_TX
6087 00:56:05.844317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6088 00:56:05.847685 ===================================
6089 00:56:05.851632 data_rate = 800,PCW = 0X7400
6090 00:56:05.854253 ===================================
6091 00:56:05.857691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6092 00:56:05.861148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6093 00:56:05.874675 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 00:56:05.877698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6095 00:56:05.881143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6096 00:56:05.884596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6097 00:56:05.887614 [ANA_INIT] flow start
6098 00:56:05.887691 [ANA_INIT] PLL >>>>>>>>
6099 00:56:05.891176 [ANA_INIT] PLL <<<<<<<<
6100 00:56:05.894150 [ANA_INIT] MIDPI >>>>>>>>
6101 00:56:05.897514 [ANA_INIT] MIDPI <<<<<<<<
6102 00:56:05.897639 [ANA_INIT] DLL >>>>>>>>
6103 00:56:05.901213 [ANA_INIT] flow end
6104 00:56:05.904448 ============ LP4 DIFF to SE enter ============
6105 00:56:05.907439 ============ LP4 DIFF to SE exit ============
6106 00:56:05.911170 [ANA_INIT] <<<<<<<<<<<<<
6107 00:56:05.914340 [Flow] Enable top DCM control >>>>>
6108 00:56:05.917727 [Flow] Enable top DCM control <<<<<
6109 00:56:05.921128 Enable DLL master slave shuffle
6110 00:56:05.927439 ==============================================================
6111 00:56:05.927516 Gating Mode config
6112 00:56:05.934406 ==============================================================
6113 00:56:05.934483 Config description:
6114 00:56:05.944027 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6115 00:56:05.950947 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6116 00:56:05.957765 SELPH_MODE 0: By rank 1: By Phase
6117 00:56:05.960433 ==============================================================
6118 00:56:05.963884 GAT_TRACK_EN = 0
6119 00:56:05.967255 RX_GATING_MODE = 2
6120 00:56:05.970750 RX_GATING_TRACK_MODE = 2
6121 00:56:05.974272 SELPH_MODE = 1
6122 00:56:05.977656 PICG_EARLY_EN = 1
6123 00:56:05.980441 VALID_LAT_VALUE = 1
6124 00:56:05.983973 ==============================================================
6125 00:56:05.990887 Enter into Gating configuration >>>>
6126 00:56:05.990964 Exit from Gating configuration <<<<
6127 00:56:05.993636 Enter into DVFS_PRE_config >>>>>
6128 00:56:06.007568 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6129 00:56:06.010751 Exit from DVFS_PRE_config <<<<<
6130 00:56:06.013824 Enter into PICG configuration >>>>
6131 00:56:06.017440 Exit from PICG configuration <<<<
6132 00:56:06.017540 [RX_INPUT] configuration >>>>>
6133 00:56:06.020433 [RX_INPUT] configuration <<<<<
6134 00:56:06.026906 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6135 00:56:06.030503 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6136 00:56:06.037215 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 00:56:06.043812 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 00:56:06.050428 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 00:56:06.056766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 00:56:06.060135 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6141 00:56:06.063683 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6142 00:56:06.070400 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6143 00:56:06.073821 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6144 00:56:06.076686 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6145 00:56:06.080215 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6146 00:56:06.083676 ===================================
6147 00:56:06.087162 LPDDR4 DRAM CONFIGURATION
6148 00:56:06.090080 ===================================
6149 00:56:06.093484 EX_ROW_EN[0] = 0x0
6150 00:56:06.093607 EX_ROW_EN[1] = 0x0
6151 00:56:06.096746 LP4Y_EN = 0x0
6152 00:56:06.096837 WORK_FSP = 0x0
6153 00:56:06.100151 WL = 0x2
6154 00:56:06.100237 RL = 0x2
6155 00:56:06.103445 BL = 0x2
6156 00:56:06.103530 RPST = 0x0
6157 00:56:06.106992 RD_PRE = 0x0
6158 00:56:06.107054 WR_PRE = 0x1
6159 00:56:06.110467 WR_PST = 0x0
6160 00:56:06.110527 DBI_WR = 0x0
6161 00:56:06.113893 DBI_RD = 0x0
6162 00:56:06.113951 OTF = 0x1
6163 00:56:06.117215 ===================================
6164 00:56:06.123490 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6165 00:56:06.126980 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6166 00:56:06.130447 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6167 00:56:06.133727 ===================================
6168 00:56:06.137061 LPDDR4 DRAM CONFIGURATION
6169 00:56:06.140242 ===================================
6170 00:56:06.143300 EX_ROW_EN[0] = 0x10
6171 00:56:06.143371 EX_ROW_EN[1] = 0x0
6172 00:56:06.146941 LP4Y_EN = 0x0
6173 00:56:06.147012 WORK_FSP = 0x0
6174 00:56:06.149909 WL = 0x2
6175 00:56:06.149997 RL = 0x2
6176 00:56:06.152978 BL = 0x2
6177 00:56:06.153044 RPST = 0x0
6178 00:56:06.156533 RD_PRE = 0x0
6179 00:56:06.156597 WR_PRE = 0x1
6180 00:56:06.159953 WR_PST = 0x0
6181 00:56:06.160018 DBI_WR = 0x0
6182 00:56:06.163399 DBI_RD = 0x0
6183 00:56:06.163470 OTF = 0x1
6184 00:56:06.166976 ===================================
6185 00:56:06.173106 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6186 00:56:06.177700 nWR fixed to 30
6187 00:56:06.181312 [ModeRegInit_LP4] CH0 RK0
6188 00:56:06.181406 [ModeRegInit_LP4] CH0 RK1
6189 00:56:06.184690 [ModeRegInit_LP4] CH1 RK0
6190 00:56:06.187822 [ModeRegInit_LP4] CH1 RK1
6191 00:56:06.187912 match AC timing 19
6192 00:56:06.194929 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6193 00:56:06.198405 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6194 00:56:06.201104 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6195 00:56:06.208008 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6196 00:56:06.211572 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6197 00:56:06.211638 ==
6198 00:56:06.214909 Dram Type= 6, Freq= 0, CH_0, rank 0
6199 00:56:06.217825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6200 00:56:06.217887 ==
6201 00:56:06.224659 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6202 00:56:06.230998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6203 00:56:06.234477 [CA 0] Center 36 (8~64) winsize 57
6204 00:56:06.238003 [CA 1] Center 36 (8~64) winsize 57
6205 00:56:06.241438 [CA 2] Center 36 (8~64) winsize 57
6206 00:56:06.241525 [CA 3] Center 36 (8~64) winsize 57
6207 00:56:06.244911 [CA 4] Center 36 (8~64) winsize 57
6208 00:56:06.248095 [CA 5] Center 36 (8~64) winsize 57
6209 00:56:06.248180
6210 00:56:06.251353 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6211 00:56:06.254874
6212 00:56:06.257585 [CATrainingPosCal] consider 1 rank data
6213 00:56:06.257661 u2DelayCellTimex100 = 270/100 ps
6214 00:56:06.264522 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 00:56:06.267949 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 00:56:06.271247 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 00:56:06.274361 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 00:56:06.277853 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 00:56:06.281397 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 00:56:06.281486
6221 00:56:06.284676 CA PerBit enable=1, Macro0, CA PI delay=36
6222 00:56:06.284738
6223 00:56:06.287901 [CBTSetCACLKResult] CA Dly = 36
6224 00:56:06.291052 CS Dly: 1 (0~32)
6225 00:56:06.291143 ==
6226 00:56:06.294436 Dram Type= 6, Freq= 0, CH_0, rank 1
6227 00:56:06.297726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 00:56:06.297813 ==
6229 00:56:06.304516 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 00:56:06.307898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6231 00:56:06.311327 [CA 0] Center 36 (8~64) winsize 57
6232 00:56:06.314475 [CA 1] Center 36 (8~64) winsize 57
6233 00:56:06.317698 [CA 2] Center 36 (8~64) winsize 57
6234 00:56:06.321143 [CA 3] Center 36 (8~64) winsize 57
6235 00:56:06.324475 [CA 4] Center 36 (8~64) winsize 57
6236 00:56:06.327420 [CA 5] Center 36 (8~64) winsize 57
6237 00:56:06.327492
6238 00:56:06.330845 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6239 00:56:06.330914
6240 00:56:06.334297 [CATrainingPosCal] consider 2 rank data
6241 00:56:06.337816 u2DelayCellTimex100 = 270/100 ps
6242 00:56:06.341303 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 00:56:06.344090 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 00:56:06.347592 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 00:56:06.354304 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 00:56:06.357873 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 00:56:06.360513 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 00:56:06.360605
6249 00:56:06.363854 CA PerBit enable=1, Macro0, CA PI delay=36
6250 00:56:06.363923
6251 00:56:06.367168 [CBTSetCACLKResult] CA Dly = 36
6252 00:56:06.367305 CS Dly: 1 (0~32)
6253 00:56:06.367408
6254 00:56:06.370650 ----->DramcWriteLeveling(PI) begin...
6255 00:56:06.370723 ==
6256 00:56:06.374103 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 00:56:06.380587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 00:56:06.380684 ==
6259 00:56:06.383917 Write leveling (Byte 0): 40 => 8
6260 00:56:06.387332 Write leveling (Byte 1): 40 => 8
6261 00:56:06.387430 DramcWriteLeveling(PI) end<-----
6262 00:56:06.387526
6263 00:56:06.390803 ==
6264 00:56:06.394111 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 00:56:06.397401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 00:56:06.397500 ==
6267 00:56:06.400708 [Gating] SW mode calibration
6268 00:56:06.407002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6269 00:56:06.410394 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6270 00:56:06.417156 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 00:56:06.420623 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 00:56:06.423957 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 00:56:06.430853 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 00:56:06.433963 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 00:56:06.437219 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 00:56:06.443699 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 00:56:06.447043 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 00:56:06.450501 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 00:56:06.453866 Total UI for P1: 0, mck2ui 16
6280 00:56:06.457103 best dqsien dly found for B0: ( 0, 14, 24)
6281 00:56:06.460376 Total UI for P1: 0, mck2ui 16
6282 00:56:06.463806 best dqsien dly found for B1: ( 0, 14, 24)
6283 00:56:06.467180 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6284 00:56:06.470466 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6285 00:56:06.470560
6286 00:56:06.473737 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6287 00:56:06.480746 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 00:56:06.480824 [Gating] SW calibration Done
6289 00:56:06.480883 ==
6290 00:56:06.484118 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 00:56:06.490573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 00:56:06.490649 ==
6293 00:56:06.490708 RX Vref Scan: 0
6294 00:56:06.490763
6295 00:56:06.494164 RX Vref 0 -> 0, step: 1
6296 00:56:06.494239
6297 00:56:06.497500 RX Delay -410 -> 252, step: 16
6298 00:56:06.500915 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6299 00:56:06.504096 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6300 00:56:06.510469 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6301 00:56:06.513930 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6302 00:56:06.517467 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6303 00:56:06.520857 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6304 00:56:06.527073 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6305 00:56:06.530588 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6306 00:56:06.533940 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6307 00:56:06.537233 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6308 00:56:06.544041 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6309 00:56:06.547401 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6310 00:56:06.550859 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6311 00:56:06.554124 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6312 00:56:06.560628 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6313 00:56:06.563620 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6314 00:56:06.563714 ==
6315 00:56:06.567160 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 00:56:06.570304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 00:56:06.570402 ==
6318 00:56:06.573766 DQS Delay:
6319 00:56:06.573839 DQS0 = 27, DQS1 = 35
6320 00:56:06.573896 DQM Delay:
6321 00:56:06.577153 DQM0 = 12, DQM1 = 12
6322 00:56:06.577244 DQ Delay:
6323 00:56:06.580317 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6324 00:56:06.583616 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6325 00:56:06.587077 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6326 00:56:06.590457 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6327 00:56:06.590555
6328 00:56:06.590641
6329 00:56:06.590724 ==
6330 00:56:06.593630 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 00:56:06.596838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 00:56:06.596928 ==
6333 00:56:06.600147
6334 00:56:06.600244
6335 00:56:06.600326 TX Vref Scan disable
6336 00:56:06.603628 == TX Byte 0 ==
6337 00:56:06.607136 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 00:56:06.610540 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 00:56:06.613419 == TX Byte 1 ==
6340 00:56:06.617257 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 00:56:06.620416 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 00:56:06.620510 ==
6343 00:56:06.623884 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 00:56:06.627183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 00:56:06.630624 ==
6346 00:56:06.630716
6347 00:56:06.630780
6348 00:56:06.630834 TX Vref Scan disable
6349 00:56:06.633467 == TX Byte 0 ==
6350 00:56:06.637019 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 00:56:06.640319 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 00:56:06.643745 == TX Byte 1 ==
6353 00:56:06.647219 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 00:56:06.649947 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 00:56:06.650039
6356 00:56:06.653450 [DATLAT]
6357 00:56:06.653538 Freq=400, CH0 RK0
6358 00:56:06.653632
6359 00:56:06.656964 DATLAT Default: 0xf
6360 00:56:06.657064 0, 0xFFFF, sum = 0
6361 00:56:06.660437 1, 0xFFFF, sum = 0
6362 00:56:06.660525 2, 0xFFFF, sum = 0
6363 00:56:06.663191 3, 0xFFFF, sum = 0
6364 00:56:06.663279 4, 0xFFFF, sum = 0
6365 00:56:06.666741 5, 0xFFFF, sum = 0
6366 00:56:06.666808 6, 0xFFFF, sum = 0
6367 00:56:06.670140 7, 0xFFFF, sum = 0
6368 00:56:06.670243 8, 0xFFFF, sum = 0
6369 00:56:06.673459 9, 0xFFFF, sum = 0
6370 00:56:06.673601 10, 0xFFFF, sum = 0
6371 00:56:06.676805 11, 0xFFFF, sum = 0
6372 00:56:06.676903 12, 0xFFFF, sum = 0
6373 00:56:06.680212 13, 0x0, sum = 1
6374 00:56:06.680306 14, 0x0, sum = 2
6375 00:56:06.683681 15, 0x0, sum = 3
6376 00:56:06.683782 16, 0x0, sum = 4
6377 00:56:06.687088 best_step = 14
6378 00:56:06.687178
6379 00:56:06.687269 ==
6380 00:56:06.690427 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 00:56:06.693610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 00:56:06.693680 ==
6383 00:56:06.696769 RX Vref Scan: 1
6384 00:56:06.696838
6385 00:56:06.696894 RX Vref 0 -> 0, step: 1
6386 00:56:06.696961
6387 00:56:06.700281 RX Delay -311 -> 252, step: 8
6388 00:56:06.700347
6389 00:56:06.703230 Set Vref, RX VrefLevel [Byte0]: 55
6390 00:56:06.707008 [Byte1]: 46
6391 00:56:06.710808
6392 00:56:06.710876 Final RX Vref Byte 0 = 55 to rank0
6393 00:56:06.714544 Final RX Vref Byte 1 = 46 to rank0
6394 00:56:06.717434 Final RX Vref Byte 0 = 55 to rank1
6395 00:56:06.721071 Final RX Vref Byte 1 = 46 to rank1==
6396 00:56:06.724133 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 00:56:06.730939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 00:56:06.731029 ==
6399 00:56:06.731108 DQS Delay:
6400 00:56:06.734482 DQS0 = 24, DQS1 = 36
6401 00:56:06.734556 DQM Delay:
6402 00:56:06.734630 DQM0 = 8, DQM1 = 14
6403 00:56:06.737810 DQ Delay:
6404 00:56:06.741221 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6405 00:56:06.741303 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6406 00:56:06.744024 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6407 00:56:06.747861 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6408 00:56:06.747960
6409 00:56:06.748048
6410 00:56:06.757555 [DQSOSCAuto] RK0, (LSB)MR18= 0xd2be, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 383 ps
6411 00:56:06.761022 CH0 RK0: MR19=C0C, MR18=D2BE
6412 00:56:06.767232 CH0_RK0: MR19=0xC0C, MR18=0xD2BE, DQSOSC=383, MR23=63, INC=402, DEC=268
6413 00:56:06.767298 ==
6414 00:56:06.770625 Dram Type= 6, Freq= 0, CH_0, rank 1
6415 00:56:06.774068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 00:56:06.774138 ==
6417 00:56:06.777476 [Gating] SW mode calibration
6418 00:56:06.783695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6419 00:56:06.790413 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6420 00:56:06.793825 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 00:56:06.797261 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 00:56:06.803596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 00:56:06.807100 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 00:56:06.810574 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 00:56:06.813905 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 00:56:06.820627 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 00:56:06.823676 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 00:56:06.827394 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 00:56:06.830352 Total UI for P1: 0, mck2ui 16
6430 00:56:06.833919 best dqsien dly found for B0: ( 0, 14, 24)
6431 00:56:06.836903 Total UI for P1: 0, mck2ui 16
6432 00:56:06.840286 best dqsien dly found for B1: ( 0, 14, 24)
6433 00:56:06.843499 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6434 00:56:06.847150 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6435 00:56:06.850535
6436 00:56:06.853453 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6437 00:56:06.856902 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 00:56:06.860176 [Gating] SW calibration Done
6439 00:56:06.860272 ==
6440 00:56:06.863884 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 00:56:06.866946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 00:56:06.867026 ==
6443 00:56:06.867083 RX Vref Scan: 0
6444 00:56:06.870613
6445 00:56:06.870706 RX Vref 0 -> 0, step: 1
6446 00:56:06.870789
6447 00:56:06.873979 RX Delay -410 -> 252, step: 16
6448 00:56:06.877391 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6449 00:56:06.883642 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6450 00:56:06.886931 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6451 00:56:06.890410 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6452 00:56:06.893805 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6453 00:56:06.899996 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6454 00:56:06.903427 iDelay=230, Bit 6, Center -11 (-234 ~ 213) 448
6455 00:56:06.906942 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6456 00:56:06.910377 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6457 00:56:06.916623 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6458 00:56:06.920148 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6459 00:56:06.923784 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6460 00:56:06.926475 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6461 00:56:06.933392 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6462 00:56:06.936773 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6463 00:56:06.940127 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6464 00:56:06.940206 ==
6465 00:56:06.943706 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 00:56:06.950046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 00:56:06.950146 ==
6468 00:56:06.950230 DQS Delay:
6469 00:56:06.953384 DQS0 = 27, DQS1 = 35
6470 00:56:06.953473 DQM Delay:
6471 00:56:06.953569 DQM0 = 13, DQM1 = 13
6472 00:56:06.956776 DQ Delay:
6473 00:56:06.960124 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6474 00:56:06.960224 DQ4 =24, DQ5 =0, DQ6 =16, DQ7 =24
6475 00:56:06.963396 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6476 00:56:06.966612 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6477 00:56:06.966704
6478 00:56:06.966787
6479 00:56:06.969804 ==
6480 00:56:06.972809 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 00:56:06.976392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 00:56:06.976494 ==
6483 00:56:06.976580
6484 00:56:06.976663
6485 00:56:06.979768 TX Vref Scan disable
6486 00:56:06.979867 == TX Byte 0 ==
6487 00:56:06.982956 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6488 00:56:06.989802 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6489 00:56:06.989875 == TX Byte 1 ==
6490 00:56:06.992758 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6491 00:56:06.999819 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6492 00:56:06.999914 ==
6493 00:56:07.003104 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 00:56:07.006622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 00:56:07.006693 ==
6496 00:56:07.006750
6497 00:56:07.006804
6498 00:56:07.009731 TX Vref Scan disable
6499 00:56:07.009809 == TX Byte 0 ==
6500 00:56:07.012965 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6501 00:56:07.019922 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6502 00:56:07.019999 == TX Byte 1 ==
6503 00:56:07.022639 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6504 00:56:07.029852 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6505 00:56:07.029931
6506 00:56:07.030014 [DATLAT]
6507 00:56:07.030088 Freq=400, CH0 RK1
6508 00:56:07.030159
6509 00:56:07.033084 DATLAT Default: 0xe
6510 00:56:07.033154 0, 0xFFFF, sum = 0
6511 00:56:07.036423 1, 0xFFFF, sum = 0
6512 00:56:07.039927 2, 0xFFFF, sum = 0
6513 00:56:07.040008 3, 0xFFFF, sum = 0
6514 00:56:07.042852 4, 0xFFFF, sum = 0
6515 00:56:07.042938 5, 0xFFFF, sum = 0
6516 00:56:07.046239 6, 0xFFFF, sum = 0
6517 00:56:07.046326 7, 0xFFFF, sum = 0
6518 00:56:07.049765 8, 0xFFFF, sum = 0
6519 00:56:07.049857 9, 0xFFFF, sum = 0
6520 00:56:07.053194 10, 0xFFFF, sum = 0
6521 00:56:07.053268 11, 0xFFFF, sum = 0
6522 00:56:07.056047 12, 0xFFFF, sum = 0
6523 00:56:07.056121 13, 0x0, sum = 1
6524 00:56:07.059428 14, 0x0, sum = 2
6525 00:56:07.059498 15, 0x0, sum = 3
6526 00:56:07.062711 16, 0x0, sum = 4
6527 00:56:07.062778 best_step = 14
6528 00:56:07.062845
6529 00:56:07.062900 ==
6530 00:56:07.065990 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 00:56:07.069383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 00:56:07.069477 ==
6533 00:56:07.072789 RX Vref Scan: 0
6534 00:56:07.072866
6535 00:56:07.076255 RX Vref 0 -> 0, step: 1
6536 00:56:07.076331
6537 00:56:07.076391 RX Delay -311 -> 252, step: 8
6538 00:56:07.085090 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6539 00:56:07.088429 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6540 00:56:07.091928 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6541 00:56:07.098106 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6542 00:56:07.101341 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6543 00:56:07.104556 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6544 00:56:07.108291 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6545 00:56:07.111234 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6546 00:56:07.117886 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6547 00:56:07.121200 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6548 00:56:07.124909 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6549 00:56:07.131444 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6550 00:56:07.134817 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6551 00:56:07.137782 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6552 00:56:07.141263 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6553 00:56:07.148152 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6554 00:56:07.148235 ==
6555 00:56:07.151537 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 00:56:07.154966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 00:56:07.155044 ==
6558 00:56:07.155104 DQS Delay:
6559 00:56:07.157722 DQS0 = 24, DQS1 = 36
6560 00:56:07.157799 DQM Delay:
6561 00:56:07.161094 DQM0 = 8, DQM1 = 14
6562 00:56:07.161168 DQ Delay:
6563 00:56:07.164514 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6564 00:56:07.167880 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6565 00:56:07.171067 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6566 00:56:07.174458 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6567 00:56:07.174529
6568 00:56:07.174587
6569 00:56:07.181393 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6570 00:56:07.184776 CH0 RK1: MR19=C0C, MR18=BD5D
6571 00:56:07.191517 CH0_RK1: MR19=0xC0C, MR18=0xBD5D, DQSOSC=386, MR23=63, INC=396, DEC=264
6572 00:56:07.194929 [RxdqsGatingPostProcess] freq 400
6573 00:56:07.197786 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6574 00:56:07.201363 best DQS0 dly(2T, 0.5T) = (0, 10)
6575 00:56:07.204063 best DQS1 dly(2T, 0.5T) = (0, 10)
6576 00:56:07.207648 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6577 00:56:07.211104 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6578 00:56:07.214713 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 00:56:07.217474 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 00:56:07.220872 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 00:56:07.224749 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 00:56:07.227368 Pre-setting of DQS Precalculation
6583 00:56:07.231120 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6584 00:56:07.234257 ==
6585 00:56:07.237449 Dram Type= 6, Freq= 0, CH_1, rank 0
6586 00:56:07.240707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 00:56:07.240789 ==
6588 00:56:07.244200 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6589 00:56:07.250633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6590 00:56:07.254424 [CA 0] Center 36 (8~64) winsize 57
6591 00:56:07.257639 [CA 1] Center 36 (8~64) winsize 57
6592 00:56:07.260739 [CA 2] Center 36 (8~64) winsize 57
6593 00:56:07.263965 [CA 3] Center 36 (8~64) winsize 57
6594 00:56:07.267440 [CA 4] Center 36 (8~64) winsize 57
6595 00:56:07.270950 [CA 5] Center 36 (8~64) winsize 57
6596 00:56:07.271047
6597 00:56:07.274176 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6598 00:56:07.274249
6599 00:56:07.277468 [CATrainingPosCal] consider 1 rank data
6600 00:56:07.280751 u2DelayCellTimex100 = 270/100 ps
6601 00:56:07.284057 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 00:56:07.286902 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 00:56:07.290470 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 00:56:07.293982 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 00:56:07.300444 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 00:56:07.303991 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 00:56:07.304071
6608 00:56:07.306817 CA PerBit enable=1, Macro0, CA PI delay=36
6609 00:56:07.306908
6610 00:56:07.310106 [CBTSetCACLKResult] CA Dly = 36
6611 00:56:07.310174 CS Dly: 1 (0~32)
6612 00:56:07.310230 ==
6613 00:56:07.313728 Dram Type= 6, Freq= 0, CH_1, rank 1
6614 00:56:07.320560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 00:56:07.320630 ==
6616 00:56:07.324118 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 00:56:07.330793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6618 00:56:07.334235 [CA 0] Center 36 (8~64) winsize 57
6619 00:56:07.337473 [CA 1] Center 36 (8~64) winsize 57
6620 00:56:07.340737 [CA 2] Center 36 (8~64) winsize 57
6621 00:56:07.344078 [CA 3] Center 36 (8~64) winsize 57
6622 00:56:07.347114 [CA 4] Center 36 (8~64) winsize 57
6623 00:56:07.350743 [CA 5] Center 36 (8~64) winsize 57
6624 00:56:07.350811
6625 00:56:07.354036 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6626 00:56:07.354104
6627 00:56:07.357526 [CATrainingPosCal] consider 2 rank data
6628 00:56:07.360988 u2DelayCellTimex100 = 270/100 ps
6629 00:56:07.363732 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 00:56:07.367326 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 00:56:07.370511 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 00:56:07.373825 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 00:56:07.376984 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 00:56:07.380266 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 00:56:07.380360
6636 00:56:07.383812 CA PerBit enable=1, Macro0, CA PI delay=36
6637 00:56:07.386890
6638 00:56:07.386958 [CBTSetCACLKResult] CA Dly = 36
6639 00:56:07.390413 CS Dly: 1 (0~32)
6640 00:56:07.390481
6641 00:56:07.393836 ----->DramcWriteLeveling(PI) begin...
6642 00:56:07.393919 ==
6643 00:56:07.397087 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 00:56:07.400255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 00:56:07.400437 ==
6646 00:56:07.403742 Write leveling (Byte 0): 40 => 8
6647 00:56:07.406924 Write leveling (Byte 1): 40 => 8
6648 00:56:07.410253 DramcWriteLeveling(PI) end<-----
6649 00:56:07.410357
6650 00:56:07.410444 ==
6651 00:56:07.413610 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 00:56:07.417092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 00:56:07.417198 ==
6654 00:56:07.420459 [Gating] SW mode calibration
6655 00:56:07.426777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6656 00:56:07.433439 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6657 00:56:07.437163 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 00:56:07.443900 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 00:56:07.447347 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 00:56:07.450112 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 00:56:07.457035 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 00:56:07.460658 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 00:56:07.463762 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 00:56:07.470301 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 00:56:07.473874 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 00:56:07.477078 Total UI for P1: 0, mck2ui 16
6667 00:56:07.479844 best dqsien dly found for B0: ( 0, 14, 24)
6668 00:56:07.483402 Total UI for P1: 0, mck2ui 16
6669 00:56:07.486709 best dqsien dly found for B1: ( 0, 14, 24)
6670 00:56:07.490119 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6671 00:56:07.493424 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6672 00:56:07.493514
6673 00:56:07.496805 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6674 00:56:07.500253 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 00:56:07.503657 [Gating] SW calibration Done
6676 00:56:07.503723 ==
6677 00:56:07.506673 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 00:56:07.509969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 00:56:07.510042 ==
6680 00:56:07.513777 RX Vref Scan: 0
6681 00:56:07.513856
6682 00:56:07.516783 RX Vref 0 -> 0, step: 1
6683 00:56:07.516861
6684 00:56:07.516927 RX Delay -410 -> 252, step: 16
6685 00:56:07.523533 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6686 00:56:07.527034 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6687 00:56:07.530138 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6688 00:56:07.533627 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6689 00:56:07.540224 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6690 00:56:07.543013 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6691 00:56:07.546901 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6692 00:56:07.550333 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6693 00:56:07.556565 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6694 00:56:07.560131 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6695 00:56:07.563475 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6696 00:56:07.566683 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6697 00:56:07.573129 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6698 00:56:07.576222 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6699 00:56:07.580060 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6700 00:56:07.586658 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6701 00:56:07.586729 ==
6702 00:56:07.590045 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 00:56:07.592783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 00:56:07.592852 ==
6705 00:56:07.592909 DQS Delay:
6706 00:56:07.596751 DQS0 = 35, DQS1 = 35
6707 00:56:07.596818 DQM Delay:
6708 00:56:07.600066 DQM0 = 16, DQM1 = 13
6709 00:56:07.600134 DQ Delay:
6710 00:56:07.603286 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6711 00:56:07.606648 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6712 00:56:07.610060 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6713 00:56:07.613434 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6714 00:56:07.613507
6715 00:56:07.613600
6716 00:56:07.613664 ==
6717 00:56:07.616948 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 00:56:07.619761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 00:56:07.619828 ==
6720 00:56:07.619898
6721 00:56:07.619977
6722 00:56:07.623138 TX Vref Scan disable
6723 00:56:07.623208 == TX Byte 0 ==
6724 00:56:07.629694 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 00:56:07.633064 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 00:56:07.633133 == TX Byte 1 ==
6727 00:56:07.639797 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 00:56:07.643374 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 00:56:07.643480 ==
6730 00:56:07.646271 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 00:56:07.649754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 00:56:07.649820 ==
6733 00:56:07.649875
6734 00:56:07.649961
6735 00:56:07.653036 TX Vref Scan disable
6736 00:56:07.653107 == TX Byte 0 ==
6737 00:56:07.659605 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 00:56:07.663072 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 00:56:07.663139 == TX Byte 1 ==
6740 00:56:07.669903 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 00:56:07.673328 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 00:56:07.673394
6743 00:56:07.673449 [DATLAT]
6744 00:56:07.676758 Freq=400, CH1 RK0
6745 00:56:07.676839
6746 00:56:07.676937 DATLAT Default: 0xf
6747 00:56:07.679452 0, 0xFFFF, sum = 0
6748 00:56:07.679529 1, 0xFFFF, sum = 0
6749 00:56:07.683309 2, 0xFFFF, sum = 0
6750 00:56:07.683386 3, 0xFFFF, sum = 0
6751 00:56:07.686054 4, 0xFFFF, sum = 0
6752 00:56:07.686133 5, 0xFFFF, sum = 0
6753 00:56:07.689935 6, 0xFFFF, sum = 0
6754 00:56:07.690007 7, 0xFFFF, sum = 0
6755 00:56:07.693303 8, 0xFFFF, sum = 0
6756 00:56:07.693397 9, 0xFFFF, sum = 0
6757 00:56:07.696867 10, 0xFFFF, sum = 0
6758 00:56:07.699663 11, 0xFFFF, sum = 0
6759 00:56:07.699743 12, 0xFFFF, sum = 0
6760 00:56:07.703189 13, 0x0, sum = 1
6761 00:56:07.703285 14, 0x0, sum = 2
6762 00:56:07.706536 15, 0x0, sum = 3
6763 00:56:07.706614 16, 0x0, sum = 4
6764 00:56:07.706687 best_step = 14
6765 00:56:07.706760
6766 00:56:07.709798 ==
6767 00:56:07.713120 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 00:56:07.716447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 00:56:07.716515 ==
6770 00:56:07.716596 RX Vref Scan: 1
6771 00:56:07.716684
6772 00:56:07.719766 RX Vref 0 -> 0, step: 1
6773 00:56:07.719841
6774 00:56:07.723152 RX Delay -311 -> 252, step: 8
6775 00:56:07.723220
6776 00:56:07.726722 Set Vref, RX VrefLevel [Byte0]: 51
6777 00:56:07.729475 [Byte1]: 52
6778 00:56:07.732715
6779 00:56:07.732783 Final RX Vref Byte 0 = 51 to rank0
6780 00:56:07.736260 Final RX Vref Byte 1 = 52 to rank0
6781 00:56:07.739868 Final RX Vref Byte 0 = 51 to rank1
6782 00:56:07.743156 Final RX Vref Byte 1 = 52 to rank1==
6783 00:56:07.746703 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 00:56:07.752783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 00:56:07.752862 ==
6786 00:56:07.752953 DQS Delay:
6787 00:56:07.756133 DQS0 = 32, DQS1 = 32
6788 00:56:07.756202 DQM Delay:
6789 00:56:07.756284 DQM0 = 13, DQM1 = 10
6790 00:56:07.759367 DQ Delay:
6791 00:56:07.762925 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6792 00:56:07.762995 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6793 00:56:07.766445 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6794 00:56:07.769960 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6795 00:56:07.770052
6796 00:56:07.770150
6797 00:56:07.779788 [DQSOSCAuto] RK0, (LSB)MR18= 0x94cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6798 00:56:07.782770 CH1 RK0: MR19=C0C, MR18=94CC
6799 00:56:07.789987 CH1_RK0: MR19=0xC0C, MR18=0x94CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6800 00:56:07.790065 ==
6801 00:56:07.792715 Dram Type= 6, Freq= 0, CH_1, rank 1
6802 00:56:07.796667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 00:56:07.796736 ==
6804 00:56:07.799877 [Gating] SW mode calibration
6805 00:56:07.805994 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6806 00:56:07.809458 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6807 00:56:07.816175 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6808 00:56:07.819465 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 00:56:07.822872 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 00:56:07.829749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 00:56:07.832450 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 00:56:07.835731 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 00:56:07.842624 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 00:56:07.846119 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 00:56:07.849514 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 00:56:07.852414 Total UI for P1: 0, mck2ui 16
6817 00:56:07.855888 best dqsien dly found for B0: ( 0, 14, 24)
6818 00:56:07.859325 Total UI for P1: 0, mck2ui 16
6819 00:56:07.862857 best dqsien dly found for B1: ( 0, 14, 24)
6820 00:56:07.865675 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6821 00:56:07.868977 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6822 00:56:07.872447
6823 00:56:07.875656 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6824 00:56:07.879472 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 00:56:07.882626 [Gating] SW calibration Done
6826 00:56:07.882700 ==
6827 00:56:07.885726 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 00:56:07.888862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 00:56:07.888939 ==
6830 00:56:07.889033 RX Vref Scan: 0
6831 00:56:07.892297
6832 00:56:07.892384 RX Vref 0 -> 0, step: 1
6833 00:56:07.892480
6834 00:56:07.896008 RX Delay -410 -> 252, step: 16
6835 00:56:07.898910 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6836 00:56:07.905915 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6837 00:56:07.909036 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6838 00:56:07.912583 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6839 00:56:07.915636 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6840 00:56:07.922542 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6841 00:56:07.925630 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6842 00:56:07.929049 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6843 00:56:07.932223 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6844 00:56:07.939087 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6845 00:56:07.942506 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6846 00:56:07.945848 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6847 00:56:07.948744 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6848 00:56:07.955759 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6849 00:56:07.958795 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6850 00:56:07.962235 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6851 00:56:07.962348 ==
6852 00:56:07.965921 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 00:56:07.969094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 00:56:07.972545 ==
6855 00:56:07.972618 DQS Delay:
6856 00:56:07.972681 DQS0 = 35, DQS1 = 35
6857 00:56:07.975333 DQM Delay:
6858 00:56:07.975400 DQM0 = 17, DQM1 = 14
6859 00:56:07.978724 DQ Delay:
6860 00:56:07.982157 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6861 00:56:07.982252 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6862 00:56:07.985478 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6863 00:56:07.988844 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6864 00:56:07.988914
6865 00:56:07.988974
6866 00:56:07.992328 ==
6867 00:56:07.995779 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 00:56:07.998628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 00:56:07.998730 ==
6870 00:56:07.998823
6871 00:56:07.998909
6872 00:56:08.001978 TX Vref Scan disable
6873 00:56:08.002096 == TX Byte 0 ==
6874 00:56:08.005234 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6875 00:56:08.011837 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6876 00:56:08.011951 == TX Byte 1 ==
6877 00:56:08.015587 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6878 00:56:08.022386 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6879 00:56:08.022498 ==
6880 00:56:08.025674 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 00:56:08.028913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 00:56:08.029006 ==
6883 00:56:08.029091
6884 00:56:08.029171
6885 00:56:08.032024 TX Vref Scan disable
6886 00:56:08.032114 == TX Byte 0 ==
6887 00:56:08.035504 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6888 00:56:08.042181 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6889 00:56:08.042285 == TX Byte 1 ==
6890 00:56:08.045127 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6891 00:56:08.052141 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6892 00:56:08.052240
6893 00:56:08.052324 [DATLAT]
6894 00:56:08.052405 Freq=400, CH1 RK1
6895 00:56:08.052482
6896 00:56:08.055687 DATLAT Default: 0xe
6897 00:56:08.055756 0, 0xFFFF, sum = 0
6898 00:56:08.058411 1, 0xFFFF, sum = 0
6899 00:56:08.058479 2, 0xFFFF, sum = 0
6900 00:56:08.061962 3, 0xFFFF, sum = 0
6901 00:56:08.065154 4, 0xFFFF, sum = 0
6902 00:56:08.065249 5, 0xFFFF, sum = 0
6903 00:56:08.068353 6, 0xFFFF, sum = 0
6904 00:56:08.068453 7, 0xFFFF, sum = 0
6905 00:56:08.072030 8, 0xFFFF, sum = 0
6906 00:56:08.072125 9, 0xFFFF, sum = 0
6907 00:56:08.075660 10, 0xFFFF, sum = 0
6908 00:56:08.075760 11, 0xFFFF, sum = 0
6909 00:56:08.078455 12, 0xFFFF, sum = 0
6910 00:56:08.078524 13, 0x0, sum = 1
6911 00:56:08.082046 14, 0x0, sum = 2
6912 00:56:08.082117 15, 0x0, sum = 3
6913 00:56:08.085617 16, 0x0, sum = 4
6914 00:56:08.085688 best_step = 14
6915 00:56:08.085744
6916 00:56:08.085796 ==
6917 00:56:08.088907 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 00:56:08.091719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 00:56:08.091822 ==
6920 00:56:08.095257 RX Vref Scan: 0
6921 00:56:08.095358
6922 00:56:08.098918 RX Vref 0 -> 0, step: 1
6923 00:56:08.098988
6924 00:56:08.099045 RX Delay -311 -> 252, step: 8
6925 00:56:08.107298 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6926 00:56:08.110714 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6927 00:56:08.114237 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6928 00:56:08.117494 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6929 00:56:08.124015 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6930 00:56:08.127368 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6931 00:56:08.130897 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6932 00:56:08.134480 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6933 00:56:08.140795 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6934 00:56:08.144028 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6935 00:56:08.147238 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6936 00:56:08.150757 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6937 00:56:08.157465 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6938 00:56:08.160519 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6939 00:56:08.163989 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6940 00:56:08.167125 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6941 00:56:08.170348 ==
6942 00:56:08.174121 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 00:56:08.177195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 00:56:08.177308 ==
6945 00:56:08.177396 DQS Delay:
6946 00:56:08.180774 DQS0 = 28, DQS1 = 36
6947 00:56:08.180872 DQM Delay:
6948 00:56:08.183861 DQM0 = 10, DQM1 = 15
6949 00:56:08.183936 DQ Delay:
6950 00:56:08.187469 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6951 00:56:08.190799 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6952 00:56:08.193432 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6953 00:56:08.196829 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6954 00:56:08.196930
6955 00:56:08.197019
6956 00:56:08.203692 [DQSOSCAuto] RK1, (LSB)MR18= 0xca59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
6957 00:56:08.207124 CH1 RK1: MR19=C0C, MR18=CA59
6958 00:56:08.213360 CH1_RK1: MR19=0xC0C, MR18=0xCA59, DQSOSC=384, MR23=63, INC=400, DEC=267
6959 00:56:08.216859 [RxdqsGatingPostProcess] freq 400
6960 00:56:08.223275 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6961 00:56:08.223406 best DQS0 dly(2T, 0.5T) = (0, 10)
6962 00:56:08.226563 best DQS1 dly(2T, 0.5T) = (0, 10)
6963 00:56:08.229773 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6964 00:56:08.233720 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6965 00:56:08.236523 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 00:56:08.239876 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 00:56:08.243286 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 00:56:08.246807 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 00:56:08.250170 Pre-setting of DQS Precalculation
6970 00:56:08.256969 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6971 00:56:08.263184 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6972 00:56:08.269799 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6973 00:56:08.269869
6974 00:56:08.269928
6975 00:56:08.273425 [Calibration Summary] 800 Mbps
6976 00:56:08.273493 CH 0, Rank 0
6977 00:56:08.276760 SW Impedance : PASS
6978 00:56:08.276838 DUTY Scan : NO K
6979 00:56:08.280226 ZQ Calibration : PASS
6980 00:56:08.283700 Jitter Meter : NO K
6981 00:56:08.283770 CBT Training : PASS
6982 00:56:08.286421 Write leveling : PASS
6983 00:56:08.289756 RX DQS gating : PASS
6984 00:56:08.289830 RX DQ/DQS(RDDQC) : PASS
6985 00:56:08.293713 TX DQ/DQS : PASS
6986 00:56:08.296288 RX DATLAT : PASS
6987 00:56:08.296363 RX DQ/DQS(Engine): PASS
6988 00:56:08.300160 TX OE : NO K
6989 00:56:08.300228 All Pass.
6990 00:56:08.300283
6991 00:56:08.303169 CH 0, Rank 1
6992 00:56:08.303234 SW Impedance : PASS
6993 00:56:08.306811 DUTY Scan : NO K
6994 00:56:08.309636 ZQ Calibration : PASS
6995 00:56:08.309711 Jitter Meter : NO K
6996 00:56:08.313128 CBT Training : PASS
6997 00:56:08.316504 Write leveling : NO K
6998 00:56:08.316576 RX DQS gating : PASS
6999 00:56:08.319903 RX DQ/DQS(RDDQC) : PASS
7000 00:56:08.319970 TX DQ/DQS : PASS
7001 00:56:08.323296 RX DATLAT : PASS
7002 00:56:08.326530 RX DQ/DQS(Engine): PASS
7003 00:56:08.326606 TX OE : NO K
7004 00:56:08.330122 All Pass.
7005 00:56:08.330188
7006 00:56:08.330244 CH 1, Rank 0
7007 00:56:08.332826 SW Impedance : PASS
7008 00:56:08.332894 DUTY Scan : NO K
7009 00:56:08.336693 ZQ Calibration : PASS
7010 00:56:08.339961 Jitter Meter : NO K
7011 00:56:08.340029 CBT Training : PASS
7012 00:56:08.343201 Write leveling : PASS
7013 00:56:08.346258 RX DQS gating : PASS
7014 00:56:08.346333 RX DQ/DQS(RDDQC) : PASS
7015 00:56:08.349699 TX DQ/DQS : PASS
7016 00:56:08.353152 RX DATLAT : PASS
7017 00:56:08.353218 RX DQ/DQS(Engine): PASS
7018 00:56:08.356606 TX OE : NO K
7019 00:56:08.356674 All Pass.
7020 00:56:08.356735
7021 00:56:08.359931 CH 1, Rank 1
7022 00:56:08.359995 SW Impedance : PASS
7023 00:56:08.362832 DUTY Scan : NO K
7024 00:56:08.366153 ZQ Calibration : PASS
7025 00:56:08.366220 Jitter Meter : NO K
7026 00:56:08.369674 CBT Training : PASS
7027 00:56:08.369740 Write leveling : NO K
7028 00:56:08.373195 RX DQS gating : PASS
7029 00:56:08.376590 RX DQ/DQS(RDDQC) : PASS
7030 00:56:08.376667 TX DQ/DQS : PASS
7031 00:56:08.379774 RX DATLAT : PASS
7032 00:56:08.382847 RX DQ/DQS(Engine): PASS
7033 00:56:08.382912 TX OE : NO K
7034 00:56:08.386588 All Pass.
7035 00:56:08.386656
7036 00:56:08.386712 DramC Write-DBI off
7037 00:56:08.389870 PER_BANK_REFRESH: Hybrid Mode
7038 00:56:08.393366 TX_TRACKING: ON
7039 00:56:08.399381 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7040 00:56:08.402915 [FAST_K] Save calibration result to emmc
7041 00:56:08.406326 dramc_set_vcore_voltage set vcore to 725000
7042 00:56:08.409748 Read voltage for 1600, 0
7043 00:56:08.409816 Vio18 = 0
7044 00:56:08.413092 Vcore = 725000
7045 00:56:08.413186 Vdram = 0
7046 00:56:08.413271 Vddq = 0
7047 00:56:08.416373 Vmddr = 0
7048 00:56:08.419778 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7049 00:56:08.425958 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7050 00:56:08.426030 MEM_TYPE=3, freq_sel=13
7051 00:56:08.429648 sv_algorithm_assistance_LP4_3733
7052 00:56:08.436195 ============ PULL DRAM RESETB DOWN ============
7053 00:56:08.439744 ========== PULL DRAM RESETB DOWN end =========
7054 00:56:08.443036 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7055 00:56:08.446485 ===================================
7056 00:56:08.449218 LPDDR4 DRAM CONFIGURATION
7057 00:56:08.453116 ===================================
7058 00:56:08.453216 EX_ROW_EN[0] = 0x0
7059 00:56:08.456315 EX_ROW_EN[1] = 0x0
7060 00:56:08.459554 LP4Y_EN = 0x0
7061 00:56:08.459620 WORK_FSP = 0x1
7062 00:56:08.462953 WL = 0x5
7063 00:56:08.463021 RL = 0x5
7064 00:56:08.466330 BL = 0x2
7065 00:56:08.466398 RPST = 0x0
7066 00:56:08.469092 RD_PRE = 0x0
7067 00:56:08.469189 WR_PRE = 0x1
7068 00:56:08.472609 WR_PST = 0x1
7069 00:56:08.472704 DBI_WR = 0x0
7070 00:56:08.476019 DBI_RD = 0x0
7071 00:56:08.476100 OTF = 0x1
7072 00:56:08.479517 ===================================
7073 00:56:08.482950 ===================================
7074 00:56:08.486396 ANA top config
7075 00:56:08.489765 ===================================
7076 00:56:08.489837 DLL_ASYNC_EN = 0
7077 00:56:08.492942 ALL_SLAVE_EN = 0
7078 00:56:08.496093 NEW_RANK_MODE = 1
7079 00:56:08.499286 DLL_IDLE_MODE = 1
7080 00:56:08.502660 LP45_APHY_COMB_EN = 1
7081 00:56:08.502748 TX_ODT_DIS = 0
7082 00:56:08.506254 NEW_8X_MODE = 1
7083 00:56:08.509495 ===================================
7084 00:56:08.513004 ===================================
7085 00:56:08.515741 data_rate = 3200
7086 00:56:08.519192 CKR = 1
7087 00:56:08.522605 DQ_P2S_RATIO = 8
7088 00:56:08.526105 ===================================
7089 00:56:08.526211 CA_P2S_RATIO = 8
7090 00:56:08.529466 DQ_CA_OPEN = 0
7091 00:56:08.532227 DQ_SEMI_OPEN = 0
7092 00:56:08.535554 CA_SEMI_OPEN = 0
7093 00:56:08.538848 CA_FULL_RATE = 0
7094 00:56:08.542678 DQ_CKDIV4_EN = 0
7095 00:56:08.542747 CA_CKDIV4_EN = 0
7096 00:56:08.545805 CA_PREDIV_EN = 0
7097 00:56:08.548842 PH8_DLY = 12
7098 00:56:08.552401 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7099 00:56:08.555450 DQ_AAMCK_DIV = 4
7100 00:56:08.559297 CA_AAMCK_DIV = 4
7101 00:56:08.562552 CA_ADMCK_DIV = 4
7102 00:56:08.562651 DQ_TRACK_CA_EN = 0
7103 00:56:08.565982 CA_PICK = 1600
7104 00:56:08.568599 CA_MCKIO = 1600
7105 00:56:08.572521 MCKIO_SEMI = 0
7106 00:56:08.575255 PLL_FREQ = 3068
7107 00:56:08.578809 DQ_UI_PI_RATIO = 32
7108 00:56:08.582168 CA_UI_PI_RATIO = 0
7109 00:56:08.585799 ===================================
7110 00:56:08.589248 ===================================
7111 00:56:08.589344 memory_type:LPDDR4
7112 00:56:08.592033 GP_NUM : 10
7113 00:56:08.592122 SRAM_EN : 1
7114 00:56:08.595431 MD32_EN : 0
7115 00:56:08.598905 ===================================
7116 00:56:08.602502 [ANA_INIT] >>>>>>>>>>>>>>
7117 00:56:08.605736 <<<<<< [CONFIGURE PHASE]: ANA_TX
7118 00:56:08.609097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7119 00:56:08.612185 ===================================
7120 00:56:08.612259 data_rate = 3200,PCW = 0X7600
7121 00:56:08.615864 ===================================
7122 00:56:08.618870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7123 00:56:08.625698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7124 00:56:08.632604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 00:56:08.636031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7126 00:56:08.638936 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7127 00:56:08.642278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7128 00:56:08.645692 [ANA_INIT] flow start
7129 00:56:08.648967 [ANA_INIT] PLL >>>>>>>>
7130 00:56:08.649031 [ANA_INIT] PLL <<<<<<<<
7131 00:56:08.652348 [ANA_INIT] MIDPI >>>>>>>>
7132 00:56:08.655678 [ANA_INIT] MIDPI <<<<<<<<
7133 00:56:08.655745 [ANA_INIT] DLL >>>>>>>>
7134 00:56:08.659138 [ANA_INIT] DLL <<<<<<<<
7135 00:56:08.662143 [ANA_INIT] flow end
7136 00:56:08.665463 ============ LP4 DIFF to SE enter ============
7137 00:56:08.669037 ============ LP4 DIFF to SE exit ============
7138 00:56:08.672589 [ANA_INIT] <<<<<<<<<<<<<
7139 00:56:08.675443 [Flow] Enable top DCM control >>>>>
7140 00:56:08.678961 [Flow] Enable top DCM control <<<<<
7141 00:56:08.682129 Enable DLL master slave shuffle
7142 00:56:08.685807 ==============================================================
7143 00:56:08.689228 Gating Mode config
7144 00:56:08.695503 ==============================================================
7145 00:56:08.695573 Config description:
7146 00:56:08.705963 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7147 00:56:08.712141 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7148 00:56:08.715542 SELPH_MODE 0: By rank 1: By Phase
7149 00:56:08.722181 ==============================================================
7150 00:56:08.725487 GAT_TRACK_EN = 1
7151 00:56:08.728687 RX_GATING_MODE = 2
7152 00:56:08.731919 RX_GATING_TRACK_MODE = 2
7153 00:56:08.736015 SELPH_MODE = 1
7154 00:56:08.738848 PICG_EARLY_EN = 1
7155 00:56:08.741883 VALID_LAT_VALUE = 1
7156 00:56:08.745005 ==============================================================
7157 00:56:08.748401 Enter into Gating configuration >>>>
7158 00:56:08.751828 Exit from Gating configuration <<<<
7159 00:56:08.755139 Enter into DVFS_PRE_config >>>>>
7160 00:56:08.764855 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7161 00:56:08.768418 Exit from DVFS_PRE_config <<<<<
7162 00:56:08.771784 Enter into PICG configuration >>>>
7163 00:56:08.775190 Exit from PICG configuration <<<<
7164 00:56:08.778647 [RX_INPUT] configuration >>>>>
7165 00:56:08.781901 [RX_INPUT] configuration <<<<<
7166 00:56:08.788073 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7167 00:56:08.791525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7168 00:56:08.798053 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 00:56:08.804800 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 00:56:08.811764 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 00:56:08.818563 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 00:56:08.821414 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7173 00:56:08.824745 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7174 00:56:08.828169 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7175 00:56:08.834987 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7176 00:56:08.838463 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7177 00:56:08.841931 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7178 00:56:08.845258 ===================================
7179 00:56:08.848437 LPDDR4 DRAM CONFIGURATION
7180 00:56:08.851678 ===================================
7181 00:56:08.851768 EX_ROW_EN[0] = 0x0
7182 00:56:08.854742 EX_ROW_EN[1] = 0x0
7183 00:56:08.858248 LP4Y_EN = 0x0
7184 00:56:08.858313 WORK_FSP = 0x1
7185 00:56:08.861526 WL = 0x5
7186 00:56:08.861605 RL = 0x5
7187 00:56:08.864851 BL = 0x2
7188 00:56:08.864917 RPST = 0x0
7189 00:56:08.867943 RD_PRE = 0x0
7190 00:56:08.868012 WR_PRE = 0x1
7191 00:56:08.871465 WR_PST = 0x1
7192 00:56:08.871530 DBI_WR = 0x0
7193 00:56:08.874831 DBI_RD = 0x0
7194 00:56:08.874897 OTF = 0x1
7195 00:56:08.878250 ===================================
7196 00:56:08.881538 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7197 00:56:08.888512 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7198 00:56:08.891366 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7199 00:56:08.894640 ===================================
7200 00:56:08.898072 LPDDR4 DRAM CONFIGURATION
7201 00:56:08.901363 ===================================
7202 00:56:08.901426 EX_ROW_EN[0] = 0x10
7203 00:56:08.904604 EX_ROW_EN[1] = 0x0
7204 00:56:08.904670 LP4Y_EN = 0x0
7205 00:56:08.908460 WORK_FSP = 0x1
7206 00:56:08.908524 WL = 0x5
7207 00:56:08.911325 RL = 0x5
7208 00:56:08.911387 BL = 0x2
7209 00:56:08.914563 RPST = 0x0
7210 00:56:08.918288 RD_PRE = 0x0
7211 00:56:08.918356 WR_PRE = 0x1
7212 00:56:08.921257 WR_PST = 0x1
7213 00:56:08.921320 DBI_WR = 0x0
7214 00:56:08.925041 DBI_RD = 0x0
7215 00:56:08.925107 OTF = 0x1
7216 00:56:08.927789 ===================================
7217 00:56:08.934596 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7218 00:56:08.934673 ==
7219 00:56:08.938109 Dram Type= 6, Freq= 0, CH_0, rank 0
7220 00:56:08.941558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7221 00:56:08.941625 ==
7222 00:56:08.945008 [Duty_Offset_Calibration]
7223 00:56:08.945071 B0:2 B1:1 CA:1
7224 00:56:08.945123
7225 00:56:08.948480 [DutyScan_Calibration_Flow] k_type=0
7226 00:56:08.959336
7227 00:56:08.959403 ==CLK 0==
7228 00:56:08.962660 Final CLK duty delay cell = 0
7229 00:56:08.966025 [0] MAX Duty = 5156%(X100), DQS PI = 22
7230 00:56:08.969344 [0] MIN Duty = 4876%(X100), DQS PI = 48
7231 00:56:08.969407 [0] AVG Duty = 5016%(X100)
7232 00:56:08.972605
7233 00:56:08.976273 CH0 CLK Duty spec in!! Max-Min= 280%
7234 00:56:08.979286 [DutyScan_Calibration_Flow] ====Done====
7235 00:56:08.979355
7236 00:56:08.982768 [DutyScan_Calibration_Flow] k_type=1
7237 00:56:08.998553
7238 00:56:08.998624 ==DQS 0 ==
7239 00:56:09.002019 Final DQS duty delay cell = -4
7240 00:56:09.005324 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7241 00:56:09.008517 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7242 00:56:09.011935 [-4] AVG Duty = 4891%(X100)
7243 00:56:09.012037
7244 00:56:09.012124 ==DQS 1 ==
7245 00:56:09.015318 Final DQS duty delay cell = 0
7246 00:56:09.018899 [0] MAX Duty = 5187%(X100), DQS PI = 20
7247 00:56:09.022158 [0] MIN Duty = 5031%(X100), DQS PI = 52
7248 00:56:09.025537 [0] AVG Duty = 5109%(X100)
7249 00:56:09.025633
7250 00:56:09.028744 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7251 00:56:09.028819
7252 00:56:09.031877 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7253 00:56:09.034959 [DutyScan_Calibration_Flow] ====Done====
7254 00:56:09.035034
7255 00:56:09.038582 [DutyScan_Calibration_Flow] k_type=3
7256 00:56:09.055963
7257 00:56:09.056039 ==DQM 0 ==
7258 00:56:09.059398 Final DQM duty delay cell = 0
7259 00:56:09.062919 [0] MAX Duty = 5187%(X100), DQS PI = 34
7260 00:56:09.066278 [0] MIN Duty = 4876%(X100), DQS PI = 60
7261 00:56:09.066353 [0] AVG Duty = 5031%(X100)
7262 00:56:09.069620
7263 00:56:09.069695 ==DQM 1 ==
7264 00:56:09.072480 Final DQM duty delay cell = 0
7265 00:56:09.075870 [0] MAX Duty = 5187%(X100), DQS PI = 20
7266 00:56:09.079432 [0] MIN Duty = 5031%(X100), DQS PI = 48
7267 00:56:09.082918 [0] AVG Duty = 5109%(X100)
7268 00:56:09.082993
7269 00:56:09.086336 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7270 00:56:09.086412
7271 00:56:09.089107 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7272 00:56:09.092545 [DutyScan_Calibration_Flow] ====Done====
7273 00:56:09.092615
7274 00:56:09.096024 [DutyScan_Calibration_Flow] k_type=2
7275 00:56:09.113095
7276 00:56:09.113197 ==DQ 0 ==
7277 00:56:09.116451 Final DQ duty delay cell = 0
7278 00:56:09.119993 [0] MAX Duty = 5062%(X100), DQS PI = 28
7279 00:56:09.123079 [0] MIN Duty = 4907%(X100), DQS PI = 0
7280 00:56:09.123179 [0] AVG Duty = 4984%(X100)
7281 00:56:09.126818
7282 00:56:09.126910 ==DQ 1 ==
7283 00:56:09.130001 Final DQ duty delay cell = 0
7284 00:56:09.133222 [0] MAX Duty = 5125%(X100), DQS PI = 6
7285 00:56:09.136681 [0] MIN Duty = 4907%(X100), DQS PI = 34
7286 00:56:09.136771 [0] AVG Duty = 5016%(X100)
7287 00:56:09.136852
7288 00:56:09.139929 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7289 00:56:09.143067
7290 00:56:09.146191 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7291 00:56:09.149810 [DutyScan_Calibration_Flow] ====Done====
7292 00:56:09.149885 ==
7293 00:56:09.152825 Dram Type= 6, Freq= 0, CH_1, rank 0
7294 00:56:09.156191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 00:56:09.156321 ==
7296 00:56:09.159381 [Duty_Offset_Calibration]
7297 00:56:09.159456 B0:1 B1:0 CA:0
7298 00:56:09.159512
7299 00:56:09.162926 [DutyScan_Calibration_Flow] k_type=0
7300 00:56:09.172388
7301 00:56:09.172466 ==CLK 0==
7302 00:56:09.175831 Final CLK duty delay cell = -4
7303 00:56:09.179458 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7304 00:56:09.183025 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7305 00:56:09.185916 [-4] AVG Duty = 4906%(X100)
7306 00:56:09.185991
7307 00:56:09.189350 CH1 CLK Duty spec in!! Max-Min= 125%
7308 00:56:09.192196 [DutyScan_Calibration_Flow] ====Done====
7309 00:56:09.192291
7310 00:56:09.195637 [DutyScan_Calibration_Flow] k_type=1
7311 00:56:09.212860
7312 00:56:09.212995 ==DQS 0 ==
7313 00:56:09.216084 Final DQS duty delay cell = 0
7314 00:56:09.219212 [0] MAX Duty = 5094%(X100), DQS PI = 18
7315 00:56:09.222362 [0] MIN Duty = 4844%(X100), DQS PI = 42
7316 00:56:09.225505 [0] AVG Duty = 4969%(X100)
7317 00:56:09.225611
7318 00:56:09.225713 ==DQS 1 ==
7319 00:56:09.229159 Final DQS duty delay cell = 0
7320 00:56:09.232508 [0] MAX Duty = 5249%(X100), DQS PI = 16
7321 00:56:09.235930 [0] MIN Duty = 4938%(X100), DQS PI = 8
7322 00:56:09.235997 [0] AVG Duty = 5093%(X100)
7323 00:56:09.238876
7324 00:56:09.242562 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7325 00:56:09.242633
7326 00:56:09.245767 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7327 00:56:09.248852 [DutyScan_Calibration_Flow] ====Done====
7328 00:56:09.248924
7329 00:56:09.252562 [DutyScan_Calibration_Flow] k_type=3
7330 00:56:09.269077
7331 00:56:09.269162 ==DQM 0 ==
7332 00:56:09.272721 Final DQM duty delay cell = 0
7333 00:56:09.276033 [0] MAX Duty = 5187%(X100), DQS PI = 8
7334 00:56:09.279516 [0] MIN Duty = 4969%(X100), DQS PI = 48
7335 00:56:09.279586 [0] AVG Duty = 5078%(X100)
7336 00:56:09.282922
7337 00:56:09.282991 ==DQM 1 ==
7338 00:56:09.286452 Final DQM duty delay cell = 0
7339 00:56:09.289131 [0] MAX Duty = 5093%(X100), DQS PI = 16
7340 00:56:09.292577 [0] MIN Duty = 4907%(X100), DQS PI = 32
7341 00:56:09.295990 [0] AVG Duty = 5000%(X100)
7342 00:56:09.296064
7343 00:56:09.299538 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7344 00:56:09.299602
7345 00:56:09.302352 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7346 00:56:09.305809 [DutyScan_Calibration_Flow] ====Done====
7347 00:56:09.305875
7348 00:56:09.309224 [DutyScan_Calibration_Flow] k_type=2
7349 00:56:09.325521
7350 00:56:09.325609 ==DQ 0 ==
7351 00:56:09.328964 Final DQ duty delay cell = -4
7352 00:56:09.331868 [-4] MAX Duty = 5031%(X100), DQS PI = 8
7353 00:56:09.335281 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7354 00:56:09.338692 [-4] AVG Duty = 4937%(X100)
7355 00:56:09.338762
7356 00:56:09.338817 ==DQ 1 ==
7357 00:56:09.341898 Final DQ duty delay cell = 0
7358 00:56:09.345078 [0] MAX Duty = 5156%(X100), DQS PI = 18
7359 00:56:09.348818 [0] MIN Duty = 4938%(X100), DQS PI = 10
7360 00:56:09.351913 [0] AVG Duty = 5047%(X100)
7361 00:56:09.351985
7362 00:56:09.355016 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7363 00:56:09.355087
7364 00:56:09.358455 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7365 00:56:09.361717 [DutyScan_Calibration_Flow] ====Done====
7366 00:56:09.365512 nWR fixed to 30
7367 00:56:09.368504 [ModeRegInit_LP4] CH0 RK0
7368 00:56:09.368580 [ModeRegInit_LP4] CH0 RK1
7369 00:56:09.372009 [ModeRegInit_LP4] CH1 RK0
7370 00:56:09.375449 [ModeRegInit_LP4] CH1 RK1
7371 00:56:09.375513 match AC timing 5
7372 00:56:09.381840 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7373 00:56:09.385310 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7374 00:56:09.388719 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7375 00:56:09.395029 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7376 00:56:09.398463 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7377 00:56:09.398542 [MiockJmeterHQA]
7378 00:56:09.398600
7379 00:56:09.401840 [DramcMiockJmeter] u1RxGatingPI = 0
7380 00:56:09.405267 0 : 4253, 4026
7381 00:56:09.405343 4 : 4252, 4027
7382 00:56:09.408786 8 : 4252, 4027
7383 00:56:09.408862 12 : 4255, 4029
7384 00:56:09.408921 16 : 4366, 4140
7385 00:56:09.411524 20 : 4253, 4026
7386 00:56:09.411601 24 : 4252, 4027
7387 00:56:09.415053 28 : 4365, 4140
7388 00:56:09.415129 32 : 4363, 4137
7389 00:56:09.418616 36 : 4363, 4138
7390 00:56:09.418692 40 : 4253, 4026
7391 00:56:09.421456 44 : 4363, 4138
7392 00:56:09.421566 48 : 4252, 4027
7393 00:56:09.421642 52 : 4253, 4026
7394 00:56:09.425473 56 : 4254, 4029
7395 00:56:09.425594 60 : 4252, 4027
7396 00:56:09.428830 64 : 4250, 4027
7397 00:56:09.428905 68 : 4250, 4026
7398 00:56:09.431567 72 : 4250, 4026
7399 00:56:09.431643 76 : 4249, 4027
7400 00:56:09.431701 80 : 4363, 4140
7401 00:56:09.435141 84 : 4250, 4027
7402 00:56:09.435216 88 : 4252, 165
7403 00:56:09.438582 92 : 4250, 0
7404 00:56:09.438657 96 : 4254, 0
7405 00:56:09.438715 100 : 4249, 0
7406 00:56:09.441967 104 : 4252, 0
7407 00:56:09.442057 108 : 4250, 0
7408 00:56:09.445352 112 : 4365, 0
7409 00:56:09.445429 116 : 4361, 0
7410 00:56:09.445488 120 : 4360, 0
7411 00:56:09.448096 124 : 4250, 0
7412 00:56:09.448172 128 : 4249, 0
7413 00:56:09.451509 132 : 4250, 0
7414 00:56:09.451585 136 : 4253, 0
7415 00:56:09.451645 140 : 4250, 0
7416 00:56:09.454917 144 : 4249, 0
7417 00:56:09.454993 148 : 4250, 0
7418 00:56:09.458049 152 : 4249, 0
7419 00:56:09.458126 156 : 4250, 0
7420 00:56:09.458210 160 : 4250, 0
7421 00:56:09.461818 164 : 4360, 0
7422 00:56:09.461895 168 : 4363, 0
7423 00:56:09.461955 172 : 4250, 0
7424 00:56:09.465211 176 : 4250, 0
7425 00:56:09.465287 180 : 4252, 0
7426 00:56:09.468010 184 : 4250, 0
7427 00:56:09.468087 188 : 4250, 0
7428 00:56:09.468147 192 : 4254, 0
7429 00:56:09.471506 196 : 4255, 0
7430 00:56:09.471582 200 : 4250, 0
7431 00:56:09.474909 204 : 4360, 1374
7432 00:56:09.474986 208 : 4250, 4002
7433 00:56:09.478464 212 : 4250, 4027
7434 00:56:09.478568 216 : 4250, 4027
7435 00:56:09.478656 220 : 4249, 4027
7436 00:56:09.481928 224 : 4255, 4029
7437 00:56:09.482048 228 : 4363, 4137
7438 00:56:09.485209 232 : 4250, 4027
7439 00:56:09.485285 236 : 4249, 4027
7440 00:56:09.488372 240 : 4253, 4026
7441 00:56:09.488448 244 : 4250, 4026
7442 00:56:09.491398 248 : 4360, 4138
7443 00:56:09.491475 252 : 4250, 4027
7444 00:56:09.494960 256 : 4363, 4137
7445 00:56:09.495036 260 : 4250, 4026
7446 00:56:09.498571 264 : 4250, 4027
7447 00:56:09.498648 268 : 4249, 4027
7448 00:56:09.501481 272 : 4250, 4027
7449 00:56:09.501614 276 : 4250, 4027
7450 00:56:09.501675 280 : 4363, 4137
7451 00:56:09.504913 284 : 4250, 4027
7452 00:56:09.504990 288 : 4249, 4027
7453 00:56:09.508269 292 : 4250, 4026
7454 00:56:09.508346 296 : 4250, 4026
7455 00:56:09.511385 300 : 4360, 4138
7456 00:56:09.511462 304 : 4250, 4027
7457 00:56:09.514759 308 : 4360, 4065
7458 00:56:09.514836 312 : 4250, 1780
7459 00:56:09.514896
7460 00:56:09.518230 MIOCK jitter meter ch=0
7461 00:56:09.518307
7462 00:56:09.521180 1T = (312-88) = 224 dly cells
7463 00:56:09.528067 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7464 00:56:09.528167 ==
7465 00:56:09.531489 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 00:56:09.534959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7467 00:56:09.535032 ==
7468 00:56:09.541143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7469 00:56:09.544636 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7470 00:56:09.548096 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7471 00:56:09.554312 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7472 00:56:09.563105 [CA 0] Center 42 (12~73) winsize 62
7473 00:56:09.566360 [CA 1] Center 42 (12~73) winsize 62
7474 00:56:09.569471 [CA 2] Center 37 (8~67) winsize 60
7475 00:56:09.573028 [CA 3] Center 37 (7~67) winsize 61
7476 00:56:09.576642 [CA 4] Center 36 (6~66) winsize 61
7477 00:56:09.580072 [CA 5] Center 35 (6~64) winsize 59
7478 00:56:09.580147
7479 00:56:09.582882 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7480 00:56:09.582957
7481 00:56:09.586398 [CATrainingPosCal] consider 1 rank data
7482 00:56:09.589925 u2DelayCellTimex100 = 290/100 ps
7483 00:56:09.593369 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7484 00:56:09.599710 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7485 00:56:09.602996 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7486 00:56:09.606344 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7487 00:56:09.609737 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7488 00:56:09.612909 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7489 00:56:09.612985
7490 00:56:09.616101 CA PerBit enable=1, Macro0, CA PI delay=35
7491 00:56:09.616178
7492 00:56:09.619270 [CBTSetCACLKResult] CA Dly = 35
7493 00:56:09.622450 CS Dly: 9 (0~40)
7494 00:56:09.626062 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7495 00:56:09.629717 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7496 00:56:09.629802 ==
7497 00:56:09.632461 Dram Type= 6, Freq= 0, CH_0, rank 1
7498 00:56:09.635873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7499 00:56:09.639347 ==
7500 00:56:09.642978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7501 00:56:09.645854 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7502 00:56:09.652373 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7503 00:56:09.655674 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7504 00:56:09.666091 [CA 0] Center 43 (13~73) winsize 61
7505 00:56:09.669428 [CA 1] Center 42 (12~73) winsize 62
7506 00:56:09.672650 [CA 2] Center 38 (8~68) winsize 61
7507 00:56:09.676052 [CA 3] Center 38 (8~68) winsize 61
7508 00:56:09.679400 [CA 4] Center 36 (6~66) winsize 61
7509 00:56:09.682528 [CA 5] Center 35 (6~65) winsize 60
7510 00:56:09.682620
7511 00:56:09.686020 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7512 00:56:09.686111
7513 00:56:09.689599 [CATrainingPosCal] consider 2 rank data
7514 00:56:09.693047 u2DelayCellTimex100 = 290/100 ps
7515 00:56:09.695867 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7516 00:56:09.702786 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7517 00:56:09.705662 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7518 00:56:09.709120 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7519 00:56:09.712448 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7520 00:56:09.715708 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7521 00:56:09.715801
7522 00:56:09.719090 CA PerBit enable=1, Macro0, CA PI delay=35
7523 00:56:09.719181
7524 00:56:09.722342 [CBTSetCACLKResult] CA Dly = 35
7525 00:56:09.725852 CS Dly: 10 (0~42)
7526 00:56:09.729230 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7527 00:56:09.732591 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7528 00:56:09.732689
7529 00:56:09.736066 ----->DramcWriteLeveling(PI) begin...
7530 00:56:09.736167 ==
7531 00:56:09.739375 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 00:56:09.745814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 00:56:09.745887 ==
7534 00:56:09.749091 Write leveling (Byte 0): 35 => 35
7535 00:56:09.749185 Write leveling (Byte 1): 27 => 27
7536 00:56:09.752516 DramcWriteLeveling(PI) end<-----
7537 00:56:09.752605
7538 00:56:09.752696 ==
7539 00:56:09.755718 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 00:56:09.762073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 00:56:09.762169 ==
7542 00:56:09.765517 [Gating] SW mode calibration
7543 00:56:09.772143 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7544 00:56:09.775484 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7545 00:56:09.782344 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7546 00:56:09.785643 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7547 00:56:09.788940 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7548 00:56:09.795590 1 4 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7549 00:56:09.799086 1 4 16 | B1->B0 | 2424 3b3b | 0 1 | (0 0) (0 0)
7550 00:56:09.801910 1 4 20 | B1->B0 | 3232 3737 | 1 0 | (1 1) (1 1)
7551 00:56:09.808865 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7552 00:56:09.812336 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7553 00:56:09.815765 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7554 00:56:09.821924 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7555 00:56:09.825311 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
7556 00:56:09.828615 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7557 00:56:09.832057 1 5 16 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)
7558 00:56:09.838809 1 5 20 | B1->B0 | 2424 2a2a | 0 0 | (1 0) (0 0)
7559 00:56:09.842175 1 5 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (1 1)
7560 00:56:09.845540 1 5 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7561 00:56:09.852305 1 6 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7562 00:56:09.855492 1 6 4 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7563 00:56:09.858581 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7564 00:56:09.865423 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7565 00:56:09.868847 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7566 00:56:09.872041 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7567 00:56:09.878394 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7568 00:56:09.882154 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 00:56:09.885176 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 00:56:09.891698 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 00:56:09.895036 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 00:56:09.898928 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7573 00:56:09.905002 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7574 00:56:09.908474 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 00:56:09.911963 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 00:56:09.918899 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 00:56:09.921622 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 00:56:09.925442 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 00:56:09.932113 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 00:56:09.935288 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 00:56:09.938694 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 00:56:09.944812 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 00:56:09.948363 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 00:56:09.951844 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 00:56:09.958169 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 00:56:09.961553 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 00:56:09.964817 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7588 00:56:09.971496 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7589 00:56:09.974614 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7590 00:56:09.978457 Total UI for P1: 0, mck2ui 16
7591 00:56:09.981896 best dqsien dly found for B0: ( 1, 9, 10)
7592 00:56:09.984626 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7593 00:56:09.988148 Total UI for P1: 0, mck2ui 16
7594 00:56:09.991582 best dqsien dly found for B1: ( 1, 9, 18)
7595 00:56:09.994928 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7596 00:56:09.998002 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7597 00:56:09.998101
7598 00:56:10.001678 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7599 00:56:10.005026 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7600 00:56:10.008055 [Gating] SW calibration Done
7601 00:56:10.008122 ==
7602 00:56:10.011552 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 00:56:10.018105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 00:56:10.018200 ==
7605 00:56:10.018291 RX Vref Scan: 0
7606 00:56:10.018380
7607 00:56:10.021587 RX Vref 0 -> 0, step: 1
7608 00:56:10.021658
7609 00:56:10.025012 RX Delay 0 -> 252, step: 8
7610 00:56:10.028363 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7611 00:56:10.031641 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7612 00:56:10.035180 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7613 00:56:10.038540 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7614 00:56:10.044983 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7615 00:56:10.048083 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7616 00:56:10.051477 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7617 00:56:10.054826 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7618 00:56:10.058350 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7619 00:56:10.064619 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7620 00:56:10.068084 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7621 00:56:10.071470 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7622 00:56:10.074825 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7623 00:56:10.078175 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7624 00:56:10.084611 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7625 00:56:10.087770 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7626 00:56:10.087871 ==
7627 00:56:10.090991 Dram Type= 6, Freq= 0, CH_0, rank 0
7628 00:56:10.094754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7629 00:56:10.094855 ==
7630 00:56:10.098134 DQS Delay:
7631 00:56:10.098226 DQS0 = 0, DQS1 = 0
7632 00:56:10.098321 DQM Delay:
7633 00:56:10.101503 DQM0 = 137, DQM1 = 129
7634 00:56:10.101631 DQ Delay:
7635 00:56:10.104345 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7636 00:56:10.107700 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7637 00:56:10.111217 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7638 00:56:10.118031 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
7639 00:56:10.118123
7640 00:56:10.118205
7641 00:56:10.118283 ==
7642 00:56:10.121391 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 00:56:10.124344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 00:56:10.124436 ==
7645 00:56:10.124518
7646 00:56:10.124608
7647 00:56:10.127860 TX Vref Scan disable
7648 00:56:10.127947 == TX Byte 0 ==
7649 00:56:10.134324 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7650 00:56:10.137981 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7651 00:56:10.138073 == TX Byte 1 ==
7652 00:56:10.144657 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7653 00:56:10.147969 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7654 00:56:10.148059 ==
7655 00:56:10.151276 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 00:56:10.154527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 00:56:10.154613 ==
7658 00:56:10.167574
7659 00:56:10.171107 TX Vref early break, caculate TX vref
7660 00:56:10.174430 TX Vref=16, minBit 7, minWin=22, winSum=379
7661 00:56:10.177781 TX Vref=18, minBit 0, minWin=23, winSum=391
7662 00:56:10.181252 TX Vref=20, minBit 0, minWin=24, winSum=401
7663 00:56:10.184626 TX Vref=22, minBit 4, minWin=24, winSum=408
7664 00:56:10.187471 TX Vref=24, minBit 4, minWin=25, winSum=418
7665 00:56:10.193953 TX Vref=26, minBit 7, minWin=25, winSum=424
7666 00:56:10.197672 TX Vref=28, minBit 2, minWin=25, winSum=426
7667 00:56:10.200765 TX Vref=30, minBit 1, minWin=25, winSum=416
7668 00:56:10.204515 TX Vref=32, minBit 0, minWin=24, winSum=400
7669 00:56:10.211065 [TxChooseVref] Worse bit 2, Min win 25, Win sum 426, Final Vref 28
7670 00:56:10.211157
7671 00:56:10.214514 Final TX Range 0 Vref 28
7672 00:56:10.214606
7673 00:56:10.214690 ==
7674 00:56:10.217324 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 00:56:10.220746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 00:56:10.220834 ==
7677 00:56:10.220918
7678 00:56:10.220996
7679 00:56:10.224264 TX Vref Scan disable
7680 00:56:10.227717 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7681 00:56:10.231134 == TX Byte 0 ==
7682 00:56:10.233934 u2DelayCellOfst[0]=10 cells (3 PI)
7683 00:56:10.237260 u2DelayCellOfst[1]=13 cells (4 PI)
7684 00:56:10.240551 u2DelayCellOfst[2]=10 cells (3 PI)
7685 00:56:10.244154 u2DelayCellOfst[3]=10 cells (3 PI)
7686 00:56:10.247204 u2DelayCellOfst[4]=6 cells (2 PI)
7687 00:56:10.250819 u2DelayCellOfst[5]=0 cells (0 PI)
7688 00:56:10.250911 u2DelayCellOfst[6]=16 cells (5 PI)
7689 00:56:10.254391 u2DelayCellOfst[7]=16 cells (5 PI)
7690 00:56:10.260870 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7691 00:56:10.264376 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7692 00:56:10.264469 == TX Byte 1 ==
7693 00:56:10.267441 u2DelayCellOfst[8]=0 cells (0 PI)
7694 00:56:10.270453 u2DelayCellOfst[9]=3 cells (1 PI)
7695 00:56:10.273682 u2DelayCellOfst[10]=10 cells (3 PI)
7696 00:56:10.277115 u2DelayCellOfst[11]=3 cells (1 PI)
7697 00:56:10.280339 u2DelayCellOfst[12]=10 cells (3 PI)
7698 00:56:10.283890 u2DelayCellOfst[13]=10 cells (3 PI)
7699 00:56:10.287379 u2DelayCellOfst[14]=13 cells (4 PI)
7700 00:56:10.290799 u2DelayCellOfst[15]=10 cells (3 PI)
7701 00:56:10.293540 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7702 00:56:10.296953 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7703 00:56:10.300300 DramC Write-DBI on
7704 00:56:10.300392 ==
7705 00:56:10.303701 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 00:56:10.306893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 00:56:10.306987 ==
7708 00:56:10.307070
7709 00:56:10.310628
7710 00:56:10.310707 TX Vref Scan disable
7711 00:56:10.313947 == TX Byte 0 ==
7712 00:56:10.317210 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7713 00:56:10.320362 == TX Byte 1 ==
7714 00:56:10.323589 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7715 00:56:10.323684 DramC Write-DBI off
7716 00:56:10.327047
7717 00:56:10.327141 [DATLAT]
7718 00:56:10.327224 Freq=1600, CH0 RK0
7719 00:56:10.327304
7720 00:56:10.330378 DATLAT Default: 0xf
7721 00:56:10.330479 0, 0xFFFF, sum = 0
7722 00:56:10.334005 1, 0xFFFF, sum = 0
7723 00:56:10.334076 2, 0xFFFF, sum = 0
7724 00:56:10.336730 3, 0xFFFF, sum = 0
7725 00:56:10.336824 4, 0xFFFF, sum = 0
7726 00:56:10.340117 5, 0xFFFF, sum = 0
7727 00:56:10.343500 6, 0xFFFF, sum = 0
7728 00:56:10.343593 7, 0xFFFF, sum = 0
7729 00:56:10.347013 8, 0xFFFF, sum = 0
7730 00:56:10.347106 9, 0xFFFF, sum = 0
7731 00:56:10.350206 10, 0xFFFF, sum = 0
7732 00:56:10.350301 11, 0xFFFF, sum = 0
7733 00:56:10.353582 12, 0xFFFF, sum = 0
7734 00:56:10.353688 13, 0xFFFF, sum = 0
7735 00:56:10.356882 14, 0x0, sum = 1
7736 00:56:10.356980 15, 0x0, sum = 2
7737 00:56:10.360124 16, 0x0, sum = 3
7738 00:56:10.360218 17, 0x0, sum = 4
7739 00:56:10.363503 best_step = 15
7740 00:56:10.363594
7741 00:56:10.363674 ==
7742 00:56:10.366633 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 00:56:10.370280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 00:56:10.370354 ==
7745 00:56:10.370413 RX Vref Scan: 1
7746 00:56:10.373723
7747 00:56:10.373813 Set Vref Range= 24 -> 127
7748 00:56:10.373878
7749 00:56:10.376943 RX Vref 24 -> 127, step: 1
7750 00:56:10.377025
7751 00:56:10.380296 RX Delay 19 -> 252, step: 4
7752 00:56:10.380389
7753 00:56:10.383507 Set Vref, RX VrefLevel [Byte0]: 24
7754 00:56:10.386497 [Byte1]: 24
7755 00:56:10.386586
7756 00:56:10.390151 Set Vref, RX VrefLevel [Byte0]: 25
7757 00:56:10.393423 [Byte1]: 25
7758 00:56:10.393496
7759 00:56:10.396946 Set Vref, RX VrefLevel [Byte0]: 26
7760 00:56:10.399713 [Byte1]: 26
7761 00:56:10.403771
7762 00:56:10.403839 Set Vref, RX VrefLevel [Byte0]: 27
7763 00:56:10.407189 [Byte1]: 27
7764 00:56:10.411238
7765 00:56:10.411306 Set Vref, RX VrefLevel [Byte0]: 28
7766 00:56:10.414679 [Byte1]: 28
7767 00:56:10.418857
7768 00:56:10.418953 Set Vref, RX VrefLevel [Byte0]: 29
7769 00:56:10.422491 [Byte1]: 29
7770 00:56:10.426652
7771 00:56:10.426725 Set Vref, RX VrefLevel [Byte0]: 30
7772 00:56:10.429855 [Byte1]: 30
7773 00:56:10.434103
7774 00:56:10.434200 Set Vref, RX VrefLevel [Byte0]: 31
7775 00:56:10.437162 [Byte1]: 31
7776 00:56:10.441995
7777 00:56:10.442075 Set Vref, RX VrefLevel [Byte0]: 32
7778 00:56:10.445232 [Byte1]: 32
7779 00:56:10.449299
7780 00:56:10.449364 Set Vref, RX VrefLevel [Byte0]: 33
7781 00:56:10.452646 [Byte1]: 33
7782 00:56:10.456769
7783 00:56:10.456836 Set Vref, RX VrefLevel [Byte0]: 34
7784 00:56:10.460120 [Byte1]: 34
7785 00:56:10.464234
7786 00:56:10.464301 Set Vref, RX VrefLevel [Byte0]: 35
7787 00:56:10.467717 [Byte1]: 35
7788 00:56:10.471838
7789 00:56:10.471905 Set Vref, RX VrefLevel [Byte0]: 36
7790 00:56:10.475569 [Byte1]: 36
7791 00:56:10.479413
7792 00:56:10.479485 Set Vref, RX VrefLevel [Byte0]: 37
7793 00:56:10.482776 [Byte1]: 37
7794 00:56:10.486938
7795 00:56:10.487012 Set Vref, RX VrefLevel [Byte0]: 38
7796 00:56:10.490417 [Byte1]: 38
7797 00:56:10.494960
7798 00:56:10.495085 Set Vref, RX VrefLevel [Byte0]: 39
7799 00:56:10.498168 [Byte1]: 39
7800 00:56:10.502063
7801 00:56:10.502161 Set Vref, RX VrefLevel [Byte0]: 40
7802 00:56:10.505959 [Byte1]: 40
7803 00:56:10.510144
7804 00:56:10.510213 Set Vref, RX VrefLevel [Byte0]: 41
7805 00:56:10.512870 [Byte1]: 41
7806 00:56:10.517627
7807 00:56:10.517696 Set Vref, RX VrefLevel [Byte0]: 42
7808 00:56:10.521164 [Byte1]: 42
7809 00:56:10.525225
7810 00:56:10.525316 Set Vref, RX VrefLevel [Byte0]: 43
7811 00:56:10.528581 [Byte1]: 43
7812 00:56:10.532670
7813 00:56:10.532765 Set Vref, RX VrefLevel [Byte0]: 44
7814 00:56:10.536088 [Byte1]: 44
7815 00:56:10.540101
7816 00:56:10.540209 Set Vref, RX VrefLevel [Byte0]: 45
7817 00:56:10.543830 [Byte1]: 45
7818 00:56:10.547993
7819 00:56:10.548082 Set Vref, RX VrefLevel [Byte0]: 46
7820 00:56:10.551013 [Byte1]: 46
7821 00:56:10.555272
7822 00:56:10.555347 Set Vref, RX VrefLevel [Byte0]: 47
7823 00:56:10.558563 [Byte1]: 47
7824 00:56:10.562661
7825 00:56:10.562728 Set Vref, RX VrefLevel [Byte0]: 48
7826 00:56:10.565831 [Byte1]: 48
7827 00:56:10.570339
7828 00:56:10.570411 Set Vref, RX VrefLevel [Byte0]: 49
7829 00:56:10.573803 [Byte1]: 49
7830 00:56:10.577971
7831 00:56:10.578093 Set Vref, RX VrefLevel [Byte0]: 50
7832 00:56:10.581241 [Byte1]: 50
7833 00:56:10.585696
7834 00:56:10.585771 Set Vref, RX VrefLevel [Byte0]: 51
7835 00:56:10.588851 [Byte1]: 51
7836 00:56:10.593460
7837 00:56:10.593591 Set Vref, RX VrefLevel [Byte0]: 52
7838 00:56:10.596265 [Byte1]: 52
7839 00:56:10.600920
7840 00:56:10.601043 Set Vref, RX VrefLevel [Byte0]: 53
7841 00:56:10.604086 [Byte1]: 53
7842 00:56:10.608610
7843 00:56:10.608708 Set Vref, RX VrefLevel [Byte0]: 54
7844 00:56:10.611992 [Byte1]: 54
7845 00:56:10.615884
7846 00:56:10.615981 Set Vref, RX VrefLevel [Byte0]: 55
7847 00:56:10.619359 [Byte1]: 55
7848 00:56:10.623410
7849 00:56:10.623504 Set Vref, RX VrefLevel [Byte0]: 56
7850 00:56:10.626833 [Byte1]: 56
7851 00:56:10.631009
7852 00:56:10.631108 Set Vref, RX VrefLevel [Byte0]: 57
7853 00:56:10.634356 [Byte1]: 57
7854 00:56:10.638475
7855 00:56:10.638571 Set Vref, RX VrefLevel [Byte0]: 58
7856 00:56:10.641956 [Byte1]: 58
7857 00:56:10.646073
7858 00:56:10.646166 Set Vref, RX VrefLevel [Byte0]: 59
7859 00:56:10.649470 [Byte1]: 59
7860 00:56:10.653481
7861 00:56:10.653615 Set Vref, RX VrefLevel [Byte0]: 60
7862 00:56:10.657456 [Byte1]: 60
7863 00:56:10.661049
7864 00:56:10.661141 Set Vref, RX VrefLevel [Byte0]: 61
7865 00:56:10.664804 [Byte1]: 61
7866 00:56:10.668744
7867 00:56:10.668838 Set Vref, RX VrefLevel [Byte0]: 62
7868 00:56:10.671939 [Byte1]: 62
7869 00:56:10.676420
7870 00:56:10.676511 Set Vref, RX VrefLevel [Byte0]: 63
7871 00:56:10.679550 [Byte1]: 63
7872 00:56:10.684151
7873 00:56:10.684244 Set Vref, RX VrefLevel [Byte0]: 64
7874 00:56:10.687708 [Byte1]: 64
7875 00:56:10.691678
7876 00:56:10.691771 Set Vref, RX VrefLevel [Byte0]: 65
7877 00:56:10.694869 [Byte1]: 65
7878 00:56:10.699202
7879 00:56:10.699298 Set Vref, RX VrefLevel [Byte0]: 66
7880 00:56:10.702513 [Byte1]: 66
7881 00:56:10.706642
7882 00:56:10.706734 Set Vref, RX VrefLevel [Byte0]: 67
7883 00:56:10.709935 [Byte1]: 67
7884 00:56:10.714416
7885 00:56:10.714510 Set Vref, RX VrefLevel [Byte0]: 68
7886 00:56:10.717490 [Byte1]: 68
7887 00:56:10.721963
7888 00:56:10.722060 Set Vref, RX VrefLevel [Byte0]: 69
7889 00:56:10.725326 [Byte1]: 69
7890 00:56:10.729305
7891 00:56:10.729412 Set Vref, RX VrefLevel [Byte0]: 70
7892 00:56:10.732701 [Byte1]: 70
7893 00:56:10.736846
7894 00:56:10.736937 Set Vref, RX VrefLevel [Byte0]: 71
7895 00:56:10.740100 [Byte1]: 71
7896 00:56:10.744340
7897 00:56:10.744435 Set Vref, RX VrefLevel [Byte0]: 72
7898 00:56:10.747721 [Byte1]: 72
7899 00:56:10.752507
7900 00:56:10.752596 Set Vref, RX VrefLevel [Byte0]: 73
7901 00:56:10.755371 [Byte1]: 73
7902 00:56:10.759492
7903 00:56:10.759581 Set Vref, RX VrefLevel [Byte0]: 74
7904 00:56:10.762900 [Byte1]: 74
7905 00:56:10.767105
7906 00:56:10.767198 Set Vref, RX VrefLevel [Byte0]: 75
7907 00:56:10.770467 [Byte1]: 75
7908 00:56:10.774897
7909 00:56:10.774987 Final RX Vref Byte 0 = 55 to rank0
7910 00:56:10.778489 Final RX Vref Byte 1 = 59 to rank0
7911 00:56:10.781501 Final RX Vref Byte 0 = 55 to rank1
7912 00:56:10.784655 Final RX Vref Byte 1 = 59 to rank1==
7913 00:56:10.788046 Dram Type= 6, Freq= 0, CH_0, rank 0
7914 00:56:10.795016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7915 00:56:10.795114 ==
7916 00:56:10.795200 DQS Delay:
7917 00:56:10.795281 DQS0 = 0, DQS1 = 0
7918 00:56:10.797808 DQM Delay:
7919 00:56:10.797877 DQM0 = 134, DQM1 = 126
7920 00:56:10.801038 DQ Delay:
7921 00:56:10.804407 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7922 00:56:10.808236 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7923 00:56:10.811451 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7924 00:56:10.814910 DQ12 =130, DQ13 =130, DQ14 =138, DQ15 =134
7925 00:56:10.815004
7926 00:56:10.815090
7927 00:56:10.815175
7928 00:56:10.817696 [DramC_TX_OE_Calibration] TA2
7929 00:56:10.821084 Original DQ_B0 (3 6) =30, OEN = 27
7930 00:56:10.824397 Original DQ_B1 (3 6) =30, OEN = 27
7931 00:56:10.827602 24, 0x0, End_B0=24 End_B1=24
7932 00:56:10.827680 25, 0x0, End_B0=25 End_B1=25
7933 00:56:10.831521 26, 0x0, End_B0=26 End_B1=26
7934 00:56:10.834891 27, 0x0, End_B0=27 End_B1=27
7935 00:56:10.837726 28, 0x0, End_B0=28 End_B1=28
7936 00:56:10.841038 29, 0x0, End_B0=29 End_B1=29
7937 00:56:10.841108 30, 0x0, End_B0=30 End_B1=30
7938 00:56:10.844456 31, 0x4141, End_B0=30 End_B1=30
7939 00:56:10.848003 Byte0 end_step=30 best_step=27
7940 00:56:10.850846 Byte1 end_step=30 best_step=27
7941 00:56:10.854173 Byte0 TX OE(2T, 0.5T) = (3, 3)
7942 00:56:10.857747 Byte1 TX OE(2T, 0.5T) = (3, 3)
7943 00:56:10.857819
7944 00:56:10.857879
7945 00:56:10.864658 [DQSOSCAuto] RK0, (LSB)MR18= 0x2722, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7946 00:56:10.867347 CH0 RK0: MR19=303, MR18=2722
7947 00:56:10.874344 CH0_RK0: MR19=0x303, MR18=0x2722, DQSOSC=390, MR23=63, INC=24, DEC=16
7948 00:56:10.874421
7949 00:56:10.877621 ----->DramcWriteLeveling(PI) begin...
7950 00:56:10.877705 ==
7951 00:56:10.881098 Dram Type= 6, Freq= 0, CH_0, rank 1
7952 00:56:10.884122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 00:56:10.884215 ==
7954 00:56:10.887818 Write leveling (Byte 0): 34 => 34
7955 00:56:10.890854 Write leveling (Byte 1): 27 => 27
7956 00:56:10.893922 DramcWriteLeveling(PI) end<-----
7957 00:56:10.894027
7958 00:56:10.894145 ==
7959 00:56:10.897841 Dram Type= 6, Freq= 0, CH_0, rank 1
7960 00:56:10.901059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 00:56:10.901150 ==
7962 00:56:10.904313 [Gating] SW mode calibration
7963 00:56:10.910847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7964 00:56:10.917337 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7965 00:56:10.920913 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7966 00:56:10.924241 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 00:56:10.930745 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 00:56:10.934068 1 4 12 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7969 00:56:10.937313 1 4 16 | B1->B0 | 3232 3939 | 0 0 | (0 0) (1 1)
7970 00:56:10.944023 1 4 20 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
7971 00:56:10.947411 1 4 24 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
7972 00:56:10.950970 1 4 28 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1)
7973 00:56:10.957207 1 5 0 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7974 00:56:10.960595 1 5 4 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7975 00:56:10.964058 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 0)
7976 00:56:10.970912 1 5 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
7977 00:56:10.974240 1 5 16 | B1->B0 | 2d2d 2827 | 1 1 | (1 0) (1 0)
7978 00:56:10.977775 1 5 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7979 00:56:10.984169 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7980 00:56:10.987572 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7981 00:56:10.991012 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7982 00:56:10.996998 1 6 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7983 00:56:11.000371 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7984 00:56:11.004125 1 6 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7985 00:56:11.010628 1 6 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7986 00:56:11.013734 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7987 00:56:11.017016 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 00:56:11.023766 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 00:56:11.027084 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 00:56:11.030293 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 00:56:11.036969 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 00:56:11.040429 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7993 00:56:11.043754 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7994 00:56:11.050357 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 00:56:11.053499 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 00:56:11.056664 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 00:56:11.063397 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 00:56:11.066845 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 00:56:11.069660 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 00:56:11.076405 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 00:56:11.079827 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 00:56:11.083376 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 00:56:11.089461 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 00:56:11.092899 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 00:56:11.096390 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 00:56:11.102664 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 00:56:11.106076 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 00:56:11.109426 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8009 00:56:11.116223 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8010 00:56:11.119436 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 00:56:11.122699 Total UI for P1: 0, mck2ui 16
8012 00:56:11.125940 best dqsien dly found for B0: ( 1, 9, 14)
8013 00:56:11.129170 Total UI for P1: 0, mck2ui 16
8014 00:56:11.132720 best dqsien dly found for B1: ( 1, 9, 14)
8015 00:56:11.135546 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8016 00:56:11.139035 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8017 00:56:11.139111
8018 00:56:11.142497 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8019 00:56:11.145960 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8020 00:56:11.149120 [Gating] SW calibration Done
8021 00:56:11.149193 ==
8022 00:56:11.152127 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 00:56:11.155971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 00:56:11.158929 ==
8025 00:56:11.159011 RX Vref Scan: 0
8026 00:56:11.159085
8027 00:56:11.161984 RX Vref 0 -> 0, step: 1
8028 00:56:11.162058
8029 00:56:11.165558 RX Delay 0 -> 252, step: 8
8030 00:56:11.168937 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8031 00:56:11.172389 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8032 00:56:11.175494 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8033 00:56:11.178771 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8034 00:56:11.185701 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8035 00:56:11.189152 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8036 00:56:11.191941 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8037 00:56:11.195437 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
8038 00:56:11.198957 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8039 00:56:11.202446 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8040 00:56:11.209213 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8041 00:56:11.211879 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8042 00:56:11.215255 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8043 00:56:11.219083 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8044 00:56:11.225260 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8045 00:56:11.228520 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8046 00:56:11.228627 ==
8047 00:56:11.232476 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 00:56:11.235743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 00:56:11.235845 ==
8050 00:56:11.239018 DQS Delay:
8051 00:56:11.239117 DQS0 = 0, DQS1 = 0
8052 00:56:11.239204 DQM Delay:
8053 00:56:11.242439 DQM0 = 136, DQM1 = 128
8054 00:56:11.242532 DQ Delay:
8055 00:56:11.245253 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8056 00:56:11.248643 DQ4 =135, DQ5 =127, DQ6 =139, DQ7 =147
8057 00:56:11.252172 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8058 00:56:11.255485 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8059 00:56:11.258961
8060 00:56:11.259053
8061 00:56:11.259141 ==
8062 00:56:11.262224 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 00:56:11.265560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 00:56:11.265653 ==
8065 00:56:11.265743
8066 00:56:11.265830
8067 00:56:11.269186 TX Vref Scan disable
8068 00:56:11.269281 == TX Byte 0 ==
8069 00:56:11.275934 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8070 00:56:11.279131 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8071 00:56:11.279232 == TX Byte 1 ==
8072 00:56:11.285527 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8073 00:56:11.288887 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8074 00:56:11.288983 ==
8075 00:56:11.292430 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 00:56:11.295211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 00:56:11.295303 ==
8078 00:56:11.309818
8079 00:56:11.313281 TX Vref early break, caculate TX vref
8080 00:56:11.316810 TX Vref=16, minBit 1, minWin=22, winSum=388
8081 00:56:11.319593 TX Vref=18, minBit 1, minWin=24, winSum=399
8082 00:56:11.322963 TX Vref=20, minBit 1, minWin=24, winSum=407
8083 00:56:11.326194 TX Vref=22, minBit 1, minWin=24, winSum=416
8084 00:56:11.329479 TX Vref=24, minBit 2, minWin=25, winSum=424
8085 00:56:11.336739 TX Vref=26, minBit 1, minWin=25, winSum=430
8086 00:56:11.339905 TX Vref=28, minBit 7, minWin=25, winSum=426
8087 00:56:11.343320 TX Vref=30, minBit 0, minWin=25, winSum=417
8088 00:56:11.346597 TX Vref=32, minBit 1, minWin=24, winSum=408
8089 00:56:11.349730 TX Vref=34, minBit 1, minWin=24, winSum=401
8090 00:56:11.356461 [TxChooseVref] Worse bit 1, Min win 25, Win sum 430, Final Vref 26
8091 00:56:11.356536
8092 00:56:11.359866 Final TX Range 0 Vref 26
8093 00:56:11.359940
8094 00:56:11.360014 ==
8095 00:56:11.363356 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 00:56:11.366063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 00:56:11.366139 ==
8098 00:56:11.366214
8099 00:56:11.366283
8100 00:56:11.369445 TX Vref Scan disable
8101 00:56:11.376168 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8102 00:56:11.376243 == TX Byte 0 ==
8103 00:56:11.379707 u2DelayCellOfst[0]=13 cells (4 PI)
8104 00:56:11.383095 u2DelayCellOfst[1]=13 cells (4 PI)
8105 00:56:11.386511 u2DelayCellOfst[2]=10 cells (3 PI)
8106 00:56:11.389357 u2DelayCellOfst[3]=10 cells (3 PI)
8107 00:56:11.392741 u2DelayCellOfst[4]=6 cells (2 PI)
8108 00:56:11.396578 u2DelayCellOfst[5]=0 cells (0 PI)
8109 00:56:11.399777 u2DelayCellOfst[6]=13 cells (4 PI)
8110 00:56:11.399878 u2DelayCellOfst[7]=13 cells (4 PI)
8111 00:56:11.406337 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8112 00:56:11.409648 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8113 00:56:11.409724 == TX Byte 1 ==
8114 00:56:11.412668 u2DelayCellOfst[8]=0 cells (0 PI)
8115 00:56:11.416461 u2DelayCellOfst[9]=0 cells (0 PI)
8116 00:56:11.419355 u2DelayCellOfst[10]=6 cells (2 PI)
8117 00:56:11.422546 u2DelayCellOfst[11]=6 cells (2 PI)
8118 00:56:11.425842 u2DelayCellOfst[12]=10 cells (3 PI)
8119 00:56:11.429351 u2DelayCellOfst[13]=10 cells (3 PI)
8120 00:56:11.432863 u2DelayCellOfst[14]=13 cells (4 PI)
8121 00:56:11.436186 u2DelayCellOfst[15]=10 cells (3 PI)
8122 00:56:11.439450 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8123 00:56:11.446212 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8124 00:56:11.446287 DramC Write-DBI on
8125 00:56:11.446348 ==
8126 00:56:11.449842 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 00:56:11.453019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 00:56:11.453113 ==
8129 00:56:11.456147
8130 00:56:11.456248
8131 00:56:11.456332 TX Vref Scan disable
8132 00:56:11.459408 == TX Byte 0 ==
8133 00:56:11.462631 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8134 00:56:11.465803 == TX Byte 1 ==
8135 00:56:11.469819 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8136 00:56:11.469912 DramC Write-DBI off
8137 00:56:11.473144
8138 00:56:11.473231 [DATLAT]
8139 00:56:11.473351 Freq=1600, CH0 RK1
8140 00:56:11.473444
8141 00:56:11.476414 DATLAT Default: 0xf
8142 00:56:11.476515 0, 0xFFFF, sum = 0
8143 00:56:11.479788 1, 0xFFFF, sum = 0
8144 00:56:11.479884 2, 0xFFFF, sum = 0
8145 00:56:11.482647 3, 0xFFFF, sum = 0
8146 00:56:11.482738 4, 0xFFFF, sum = 0
8147 00:56:11.485966 5, 0xFFFF, sum = 0
8148 00:56:11.489519 6, 0xFFFF, sum = 0
8149 00:56:11.489635 7, 0xFFFF, sum = 0
8150 00:56:11.492926 8, 0xFFFF, sum = 0
8151 00:56:11.493016 9, 0xFFFF, sum = 0
8152 00:56:11.496244 10, 0xFFFF, sum = 0
8153 00:56:11.496342 11, 0xFFFF, sum = 0
8154 00:56:11.499581 12, 0xFFFF, sum = 0
8155 00:56:11.499674 13, 0xFFFF, sum = 0
8156 00:56:11.502827 14, 0x0, sum = 1
8157 00:56:11.502922 15, 0x0, sum = 2
8158 00:56:11.506085 16, 0x0, sum = 3
8159 00:56:11.506150 17, 0x0, sum = 4
8160 00:56:11.509499 best_step = 15
8161 00:56:11.509587
8162 00:56:11.509644 ==
8163 00:56:11.512372 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 00:56:11.515774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 00:56:11.515863 ==
8166 00:56:11.515947 RX Vref Scan: 0
8167 00:56:11.519190
8168 00:56:11.519281 RX Vref 0 -> 0, step: 1
8169 00:56:11.519367
8170 00:56:11.522639 RX Delay 19 -> 252, step: 4
8171 00:56:11.525911 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8172 00:56:11.532426 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8173 00:56:11.536136 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8174 00:56:11.539423 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8175 00:56:11.542239 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8176 00:56:11.545716 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8177 00:56:11.552547 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8178 00:56:11.555692 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8179 00:56:11.559321 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8180 00:56:11.562617 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8181 00:56:11.565808 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8182 00:56:11.572580 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8183 00:56:11.575716 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8184 00:56:11.578991 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8185 00:56:11.582015 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8186 00:56:11.585910 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8187 00:56:11.589365 ==
8188 00:56:11.589460 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 00:56:11.595571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 00:56:11.595668 ==
8191 00:56:11.595757 DQS Delay:
8192 00:56:11.598977 DQS0 = 0, DQS1 = 0
8193 00:56:11.599077 DQM Delay:
8194 00:56:11.602504 DQM0 = 134, DQM1 = 127
8195 00:56:11.602574 DQ Delay:
8196 00:56:11.605843 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8197 00:56:11.609172 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8198 00:56:11.612531 DQ8 =118, DQ9 =116, DQ10 =130, DQ11 =118
8199 00:56:11.615859 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8200 00:56:11.615948
8201 00:56:11.616032
8202 00:56:11.616112
8203 00:56:11.618667 [DramC_TX_OE_Calibration] TA2
8204 00:56:11.622131 Original DQ_B0 (3 6) =30, OEN = 27
8205 00:56:11.625629 Original DQ_B1 (3 6) =30, OEN = 27
8206 00:56:11.629125 24, 0x0, End_B0=24 End_B1=24
8207 00:56:11.632421 25, 0x0, End_B0=25 End_B1=25
8208 00:56:11.632523 26, 0x0, End_B0=26 End_B1=26
8209 00:56:11.635084 27, 0x0, End_B0=27 End_B1=27
8210 00:56:11.638513 28, 0x0, End_B0=28 End_B1=28
8211 00:56:11.642481 29, 0x0, End_B0=29 End_B1=29
8212 00:56:11.642656 30, 0x0, End_B0=30 End_B1=30
8213 00:56:11.645122 31, 0x4141, End_B0=30 End_B1=30
8214 00:56:11.648693 Byte0 end_step=30 best_step=27
8215 00:56:11.651986 Byte1 end_step=30 best_step=27
8216 00:56:11.655453 Byte0 TX OE(2T, 0.5T) = (3, 3)
8217 00:56:11.658873 Byte1 TX OE(2T, 0.5T) = (3, 3)
8218 00:56:11.658946
8219 00:56:11.659003
8220 00:56:11.665434 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8221 00:56:11.668743 CH0 RK1: MR19=303, MR18=2008
8222 00:56:11.675225 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8223 00:56:11.678418 [RxdqsGatingPostProcess] freq 1600
8224 00:56:11.681726 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8225 00:56:11.685045 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 00:56:11.688213 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 00:56:11.691925 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 00:56:11.695090 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 00:56:11.698514 best DQS0 dly(2T, 0.5T) = (1, 1)
8230 00:56:11.701916 best DQS1 dly(2T, 0.5T) = (1, 1)
8231 00:56:11.705300 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8232 00:56:11.708154 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8233 00:56:11.711608 Pre-setting of DQS Precalculation
8234 00:56:11.714940 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8235 00:56:11.715039 ==
8236 00:56:11.718333 Dram Type= 6, Freq= 0, CH_1, rank 0
8237 00:56:11.725117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 00:56:11.725216 ==
8239 00:56:11.728621 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8240 00:56:11.734734 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8241 00:56:11.738507 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8242 00:56:11.744753 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8243 00:56:11.752191 [CA 0] Center 42 (13~72) winsize 60
8244 00:56:11.755443 [CA 1] Center 42 (13~72) winsize 60
8245 00:56:11.759279 [CA 2] Center 38 (9~68) winsize 60
8246 00:56:11.762477 [CA 3] Center 38 (9~68) winsize 60
8247 00:56:11.765978 [CA 4] Center 38 (9~68) winsize 60
8248 00:56:11.769186 [CA 5] Center 37 (8~67) winsize 60
8249 00:56:11.769280
8250 00:56:11.772471 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8251 00:56:11.772566
8252 00:56:11.775712 [CATrainingPosCal] consider 1 rank data
8253 00:56:11.778984 u2DelayCellTimex100 = 290/100 ps
8254 00:56:11.782357 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8255 00:56:11.788788 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8256 00:56:11.792122 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8257 00:56:11.795579 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8258 00:56:11.798886 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8259 00:56:11.801899 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8260 00:56:11.801993
8261 00:56:11.805104 CA PerBit enable=1, Macro0, CA PI delay=37
8262 00:56:11.805204
8263 00:56:11.808483 [CBTSetCACLKResult] CA Dly = 37
8264 00:56:11.811964 CS Dly: 10 (0~41)
8265 00:56:11.815422 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8266 00:56:11.818996 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8267 00:56:11.819127 ==
8268 00:56:11.821704 Dram Type= 6, Freq= 0, CH_1, rank 1
8269 00:56:11.825504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 00:56:11.828710 ==
8271 00:56:11.832064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8272 00:56:11.835479 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8273 00:56:11.841748 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8274 00:56:11.847970 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8275 00:56:11.855481 [CA 0] Center 42 (12~72) winsize 61
8276 00:56:11.858914 [CA 1] Center 42 (13~72) winsize 60
8277 00:56:11.862309 [CA 2] Center 38 (9~68) winsize 60
8278 00:56:11.865664 [CA 3] Center 38 (9~68) winsize 60
8279 00:56:11.868884 [CA 4] Center 39 (9~69) winsize 61
8280 00:56:11.871954 [CA 5] Center 37 (8~67) winsize 60
8281 00:56:11.872032
8282 00:56:11.875761 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8283 00:56:11.875837
8284 00:56:11.878889 [CATrainingPosCal] consider 2 rank data
8285 00:56:11.882118 u2DelayCellTimex100 = 290/100 ps
8286 00:56:11.885649 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8287 00:56:11.892347 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8288 00:56:11.895510 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8289 00:56:11.898917 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8290 00:56:11.902323 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8291 00:56:11.905072 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8292 00:56:11.905144
8293 00:56:11.908385 CA PerBit enable=1, Macro0, CA PI delay=37
8294 00:56:11.908460
8295 00:56:11.911587 [CBTSetCACLKResult] CA Dly = 37
8296 00:56:11.915405 CS Dly: 12 (0~45)
8297 00:56:11.918467 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8298 00:56:11.921866 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8299 00:56:11.921963
8300 00:56:11.925449 ----->DramcWriteLeveling(PI) begin...
8301 00:56:11.925541 ==
8302 00:56:11.928799 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 00:56:11.935246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 00:56:11.935345 ==
8305 00:56:11.935432 Write leveling (Byte 0): 27 => 27
8306 00:56:11.938642 Write leveling (Byte 1): 28 => 28
8307 00:56:11.942140 DramcWriteLeveling(PI) end<-----
8308 00:56:11.942236
8309 00:56:11.942362 ==
8310 00:56:11.945428 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 00:56:11.952114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 00:56:11.952209 ==
8313 00:56:11.955576 [Gating] SW mode calibration
8314 00:56:11.961621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8315 00:56:11.965173 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8316 00:56:11.972062 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 00:56:11.974865 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 00:56:11.978238 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8319 00:56:11.984718 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8320 00:56:11.988602 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 00:56:11.991704 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 00:56:11.994961 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 00:56:12.001692 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 00:56:12.004864 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 00:56:12.008439 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 00:56:12.015472 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
8327 00:56:12.018586 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
8328 00:56:12.021847 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 00:56:12.028493 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 00:56:12.031544 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 00:56:12.034778 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 00:56:12.041860 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 00:56:12.044973 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 00:56:12.048369 1 6 8 | B1->B0 | 2d2d 3d3d | 0 0 | (1 1) (0 0)
8335 00:56:12.055051 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8336 00:56:12.057810 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 00:56:12.061212 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 00:56:12.068200 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 00:56:12.071670 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 00:56:12.074450 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 00:56:12.081444 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 00:56:12.084887 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8343 00:56:12.088089 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8344 00:56:12.094946 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 00:56:12.097660 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 00:56:12.100909 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 00:56:12.107911 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 00:56:12.110894 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 00:56:12.114213 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 00:56:12.120999 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 00:56:12.124222 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 00:56:12.127698 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 00:56:12.134559 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 00:56:12.137690 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 00:56:12.140683 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 00:56:12.147837 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 00:56:12.150955 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 00:56:12.153993 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8359 00:56:12.160813 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8360 00:56:12.163635 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 00:56:12.167462 Total UI for P1: 0, mck2ui 16
8362 00:56:12.170907 best dqsien dly found for B0: ( 1, 9, 10)
8363 00:56:12.173656 Total UI for P1: 0, mck2ui 16
8364 00:56:12.177222 best dqsien dly found for B1: ( 1, 9, 10)
8365 00:56:12.180706 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8366 00:56:12.184097 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8367 00:56:12.184168
8368 00:56:12.186883 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8369 00:56:12.190392 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8370 00:56:12.193710 [Gating] SW calibration Done
8371 00:56:12.193785 ==
8372 00:56:12.196985 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 00:56:12.200319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 00:56:12.203845 ==
8375 00:56:12.203914 RX Vref Scan: 0
8376 00:56:12.203970
8377 00:56:12.207116 RX Vref 0 -> 0, step: 1
8378 00:56:12.207238
8379 00:56:12.207318 RX Delay 0 -> 252, step: 8
8380 00:56:12.213802 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8381 00:56:12.217324 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8382 00:56:12.220655 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8383 00:56:12.223428 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8384 00:56:12.227214 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8385 00:56:12.233897 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8386 00:56:12.236745 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8387 00:56:12.240234 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8388 00:56:12.243649 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8389 00:56:12.246992 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8390 00:56:12.253637 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8391 00:56:12.257139 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8392 00:56:12.260125 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8393 00:56:12.263416 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8394 00:56:12.266666 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8395 00:56:12.273684 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8396 00:56:12.273780 ==
8397 00:56:12.276633 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 00:56:12.280026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 00:56:12.280120 ==
8400 00:56:12.280211 DQS Delay:
8401 00:56:12.283310 DQS0 = 0, DQS1 = 0
8402 00:56:12.283401 DQM Delay:
8403 00:56:12.286841 DQM0 = 135, DQM1 = 133
8404 00:56:12.286937 DQ Delay:
8405 00:56:12.290056 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8406 00:56:12.293428 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8407 00:56:12.296892 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8408 00:56:12.299667 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8409 00:56:12.303088
8410 00:56:12.303191
8411 00:56:12.303282 ==
8412 00:56:12.306589 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 00:56:12.310105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 00:56:12.310201 ==
8415 00:56:12.310288
8416 00:56:12.310381
8417 00:56:12.313362 TX Vref Scan disable
8418 00:56:12.313455 == TX Byte 0 ==
8419 00:56:12.320161 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8420 00:56:12.323110 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8421 00:56:12.323210 == TX Byte 1 ==
8422 00:56:12.330063 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8423 00:56:12.332823 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8424 00:56:12.332917 ==
8425 00:56:12.336226 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 00:56:12.339490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 00:56:12.339582 ==
8428 00:56:12.352681
8429 00:56:12.355912 TX Vref early break, caculate TX vref
8430 00:56:12.359143 TX Vref=16, minBit 1, minWin=21, winSum=370
8431 00:56:12.362680 TX Vref=18, minBit 0, minWin=23, winSum=379
8432 00:56:12.366135 TX Vref=20, minBit 1, minWin=23, winSum=394
8433 00:56:12.369663 TX Vref=22, minBit 1, minWin=24, winSum=403
8434 00:56:12.372493 TX Vref=24, minBit 1, minWin=24, winSum=409
8435 00:56:12.379475 TX Vref=26, minBit 1, minWin=24, winSum=418
8436 00:56:12.382900 TX Vref=28, minBit 0, minWin=24, winSum=420
8437 00:56:12.385696 TX Vref=30, minBit 2, minWin=25, winSum=419
8438 00:56:12.389005 TX Vref=32, minBit 2, minWin=23, winSum=409
8439 00:56:12.392718 TX Vref=34, minBit 2, minWin=23, winSum=397
8440 00:56:12.399279 [TxChooseVref] Worse bit 2, Min win 25, Win sum 419, Final Vref 30
8441 00:56:12.399375
8442 00:56:12.402236 Final TX Range 0 Vref 30
8443 00:56:12.402310
8444 00:56:12.402395 ==
8445 00:56:12.405671 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 00:56:12.409178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 00:56:12.409273 ==
8448 00:56:12.409359
8449 00:56:12.409440
8450 00:56:12.412495 TX Vref Scan disable
8451 00:56:12.419352 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8452 00:56:12.419449 == TX Byte 0 ==
8453 00:56:12.422448 u2DelayCellOfst[0]=16 cells (5 PI)
8454 00:56:12.425816 u2DelayCellOfst[1]=10 cells (3 PI)
8455 00:56:12.429160 u2DelayCellOfst[2]=0 cells (0 PI)
8456 00:56:12.431992 u2DelayCellOfst[3]=6 cells (2 PI)
8457 00:56:12.435391 u2DelayCellOfst[4]=6 cells (2 PI)
8458 00:56:12.438983 u2DelayCellOfst[5]=16 cells (5 PI)
8459 00:56:12.442396 u2DelayCellOfst[6]=20 cells (6 PI)
8460 00:56:12.442462 u2DelayCellOfst[7]=6 cells (2 PI)
8461 00:56:12.449019 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8462 00:56:12.452175 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8463 00:56:12.452267 == TX Byte 1 ==
8464 00:56:12.455448 u2DelayCellOfst[8]=0 cells (0 PI)
8465 00:56:12.459030 u2DelayCellOfst[9]=3 cells (1 PI)
8466 00:56:12.462343 u2DelayCellOfst[10]=10 cells (3 PI)
8467 00:56:12.465761 u2DelayCellOfst[11]=3 cells (1 PI)
8468 00:56:12.468952 u2DelayCellOfst[12]=13 cells (4 PI)
8469 00:56:12.471711 u2DelayCellOfst[13]=16 cells (5 PI)
8470 00:56:12.475122 u2DelayCellOfst[14]=16 cells (5 PI)
8471 00:56:12.478611 u2DelayCellOfst[15]=16 cells (5 PI)
8472 00:56:12.482106 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8473 00:56:12.488390 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8474 00:56:12.488488 DramC Write-DBI on
8475 00:56:12.488574 ==
8476 00:56:12.491911 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 00:56:12.495382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 00:56:12.495504 ==
8479 00:56:12.498809
8480 00:56:12.498906
8481 00:56:12.498992 TX Vref Scan disable
8482 00:56:12.502150 == TX Byte 0 ==
8483 00:56:12.505537 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8484 00:56:12.508709 == TX Byte 1 ==
8485 00:56:12.512127 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8486 00:56:12.512293 DramC Write-DBI off
8487 00:56:12.515463
8488 00:56:12.515601 [DATLAT]
8489 00:56:12.515759 Freq=1600, CH1 RK0
8490 00:56:12.515870
8491 00:56:12.518639 DATLAT Default: 0xf
8492 00:56:12.518768 0, 0xFFFF, sum = 0
8493 00:56:12.521661 1, 0xFFFF, sum = 0
8494 00:56:12.521785 2, 0xFFFF, sum = 0
8495 00:56:12.525299 3, 0xFFFF, sum = 0
8496 00:56:12.528223 4, 0xFFFF, sum = 0
8497 00:56:12.528318 5, 0xFFFF, sum = 0
8498 00:56:12.531698 6, 0xFFFF, sum = 0
8499 00:56:12.531799 7, 0xFFFF, sum = 0
8500 00:56:12.534974 8, 0xFFFF, sum = 0
8501 00:56:12.535069 9, 0xFFFF, sum = 0
8502 00:56:12.538363 10, 0xFFFF, sum = 0
8503 00:56:12.538458 11, 0xFFFF, sum = 0
8504 00:56:12.541927 12, 0xFFFF, sum = 0
8505 00:56:12.542025 13, 0xFFFF, sum = 0
8506 00:56:12.544942 14, 0x0, sum = 1
8507 00:56:12.545043 15, 0x0, sum = 2
8508 00:56:12.548426 16, 0x0, sum = 3
8509 00:56:12.548535 17, 0x0, sum = 4
8510 00:56:12.551936 best_step = 15
8511 00:56:12.552026
8512 00:56:12.552106 ==
8513 00:56:12.555225 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 00:56:12.558431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 00:56:12.558552 ==
8516 00:56:12.558634 RX Vref Scan: 1
8517 00:56:12.561551
8518 00:56:12.561670 Set Vref Range= 24 -> 127
8519 00:56:12.561754
8520 00:56:12.565077 RX Vref 24 -> 127, step: 1
8521 00:56:12.565170
8522 00:56:12.568361 RX Delay 27 -> 252, step: 4
8523 00:56:12.568461
8524 00:56:12.571771 Set Vref, RX VrefLevel [Byte0]: 24
8525 00:56:12.575514 [Byte1]: 24
8526 00:56:12.575636
8527 00:56:12.578767 Set Vref, RX VrefLevel [Byte0]: 25
8528 00:56:12.581397 [Byte1]: 25
8529 00:56:12.581511
8530 00:56:12.584981 Set Vref, RX VrefLevel [Byte0]: 26
8531 00:56:12.588471 [Byte1]: 26
8532 00:56:12.591872
8533 00:56:12.591972 Set Vref, RX VrefLevel [Byte0]: 27
8534 00:56:12.595361 [Byte1]: 27
8535 00:56:12.599641
8536 00:56:12.599725 Set Vref, RX VrefLevel [Byte0]: 28
8537 00:56:12.603106 [Byte1]: 28
8538 00:56:12.607139
8539 00:56:12.607219 Set Vref, RX VrefLevel [Byte0]: 29
8540 00:56:12.610565 [Byte1]: 29
8541 00:56:12.614530
8542 00:56:12.614610 Set Vref, RX VrefLevel [Byte0]: 30
8543 00:56:12.617888 [Byte1]: 30
8544 00:56:12.622110
8545 00:56:12.622218 Set Vref, RX VrefLevel [Byte0]: 31
8546 00:56:12.625627 [Byte1]: 31
8547 00:56:12.629853
8548 00:56:12.629929 Set Vref, RX VrefLevel [Byte0]: 32
8549 00:56:12.633091 [Byte1]: 32
8550 00:56:12.637018
8551 00:56:12.637119 Set Vref, RX VrefLevel [Byte0]: 33
8552 00:56:12.640564 [Byte1]: 33
8553 00:56:12.644825
8554 00:56:12.644902 Set Vref, RX VrefLevel [Byte0]: 34
8555 00:56:12.648132 [Byte1]: 34
8556 00:56:12.652491
8557 00:56:12.652568 Set Vref, RX VrefLevel [Byte0]: 35
8558 00:56:12.655410 [Byte1]: 35
8559 00:56:12.659889
8560 00:56:12.659965 Set Vref, RX VrefLevel [Byte0]: 36
8561 00:56:12.663153 [Byte1]: 36
8562 00:56:12.667156
8563 00:56:12.667235 Set Vref, RX VrefLevel [Byte0]: 37
8564 00:56:12.670574 [Byte1]: 37
8565 00:56:12.675090
8566 00:56:12.675198 Set Vref, RX VrefLevel [Byte0]: 38
8567 00:56:12.678228 [Byte1]: 38
8568 00:56:12.682519
8569 00:56:12.682595 Set Vref, RX VrefLevel [Byte0]: 39
8570 00:56:12.685727 [Byte1]: 39
8571 00:56:12.690290
8572 00:56:12.690395 Set Vref, RX VrefLevel [Byte0]: 40
8573 00:56:12.693354 [Byte1]: 40
8574 00:56:12.698017
8575 00:56:12.698096 Set Vref, RX VrefLevel [Byte0]: 41
8576 00:56:12.700759 [Byte1]: 41
8577 00:56:12.704916
8578 00:56:12.705002 Set Vref, RX VrefLevel [Byte0]: 42
8579 00:56:12.708375 [Byte1]: 42
8580 00:56:12.712473
8581 00:56:12.712566 Set Vref, RX VrefLevel [Byte0]: 43
8582 00:56:12.715837 [Byte1]: 43
8583 00:56:12.719810
8584 00:56:12.719914 Set Vref, RX VrefLevel [Byte0]: 44
8585 00:56:12.723804 [Byte1]: 44
8586 00:56:12.728035
8587 00:56:12.728119 Set Vref, RX VrefLevel [Byte0]: 45
8588 00:56:12.730783 [Byte1]: 45
8589 00:56:12.735061
8590 00:56:12.735139 Set Vref, RX VrefLevel [Byte0]: 46
8591 00:56:12.738436 [Byte1]: 46
8592 00:56:12.743007
8593 00:56:12.743109 Set Vref, RX VrefLevel [Byte0]: 47
8594 00:56:12.745853 [Byte1]: 47
8595 00:56:12.749957
8596 00:56:12.750067 Set Vref, RX VrefLevel [Byte0]: 48
8597 00:56:12.753354 [Byte1]: 48
8598 00:56:12.757555
8599 00:56:12.757669 Set Vref, RX VrefLevel [Byte0]: 49
8600 00:56:12.761002 [Byte1]: 49
8601 00:56:12.764985
8602 00:56:12.765089 Set Vref, RX VrefLevel [Byte0]: 50
8603 00:56:12.768790 [Byte1]: 50
8604 00:56:12.772734
8605 00:56:12.772840 Set Vref, RX VrefLevel [Byte0]: 51
8606 00:56:12.776116 [Byte1]: 51
8607 00:56:12.780116
8608 00:56:12.780220 Set Vref, RX VrefLevel [Byte0]: 52
8609 00:56:12.783869 [Byte1]: 52
8610 00:56:12.788103
8611 00:56:12.788212 Set Vref, RX VrefLevel [Byte0]: 53
8612 00:56:12.790963 [Byte1]: 53
8613 00:56:12.795450
8614 00:56:12.795555 Set Vref, RX VrefLevel [Byte0]: 54
8615 00:56:12.798710 [Byte1]: 54
8616 00:56:12.802956
8617 00:56:12.803081 Set Vref, RX VrefLevel [Byte0]: 55
8618 00:56:12.806196 [Byte1]: 55
8619 00:56:12.810483
8620 00:56:12.810599 Set Vref, RX VrefLevel [Byte0]: 56
8621 00:56:12.813770 [Byte1]: 56
8622 00:56:12.817994
8623 00:56:12.818099 Set Vref, RX VrefLevel [Byte0]: 57
8624 00:56:12.821224 [Byte1]: 57
8625 00:56:12.825246
8626 00:56:12.825352 Set Vref, RX VrefLevel [Byte0]: 58
8627 00:56:12.828746 [Byte1]: 58
8628 00:56:12.832954
8629 00:56:12.833077 Set Vref, RX VrefLevel [Byte0]: 59
8630 00:56:12.836330 [Byte1]: 59
8631 00:56:12.840421
8632 00:56:12.840564 Set Vref, RX VrefLevel [Byte0]: 60
8633 00:56:12.843808 [Byte1]: 60
8634 00:56:12.847848
8635 00:56:12.847979 Set Vref, RX VrefLevel [Byte0]: 61
8636 00:56:12.851754 [Byte1]: 61
8637 00:56:12.855850
8638 00:56:12.855974 Set Vref, RX VrefLevel [Byte0]: 62
8639 00:56:12.898810 [Byte1]: 62
8640 00:56:12.898960
8641 00:56:12.899055 Set Vref, RX VrefLevel [Byte0]: 63
8642 00:56:12.899152 [Byte1]: 63
8643 00:56:12.899235
8644 00:56:12.899315 Set Vref, RX VrefLevel [Byte0]: 64
8645 00:56:12.899407 [Byte1]: 64
8646 00:56:12.899488
8647 00:56:12.899566 Set Vref, RX VrefLevel [Byte0]: 65
8648 00:56:12.899655 [Byte1]: 65
8649 00:56:12.899735
8650 00:56:12.899813 Set Vref, RX VrefLevel [Byte0]: 66
8651 00:56:12.899909 [Byte1]: 66
8652 00:56:12.900014
8653 00:56:12.900121 Set Vref, RX VrefLevel [Byte0]: 67
8654 00:56:12.900228 [Byte1]: 67
8655 00:56:12.901069
8656 00:56:12.901187 Set Vref, RX VrefLevel [Byte0]: 68
8657 00:56:12.904340 [Byte1]: 68
8658 00:56:12.908590
8659 00:56:12.908703 Set Vref, RX VrefLevel [Byte0]: 69
8660 00:56:12.911616 [Byte1]: 69
8661 00:56:12.915797
8662 00:56:12.915940 Set Vref, RX VrefLevel [Byte0]: 70
8663 00:56:12.919165 [Byte1]: 70
8664 00:56:12.923191
8665 00:56:12.923307 Set Vref, RX VrefLevel [Byte0]: 71
8666 00:56:12.926549 [Byte1]: 71
8667 00:56:12.930877
8668 00:56:12.931045 Set Vref, RX VrefLevel [Byte0]: 72
8669 00:56:12.934478 [Byte1]: 72
8670 00:56:12.938739
8671 00:56:12.938846 Set Vref, RX VrefLevel [Byte0]: 73
8672 00:56:12.941717 [Byte1]: 73
8673 00:56:12.946199
8674 00:56:12.946307 Final RX Vref Byte 0 = 56 to rank0
8675 00:56:12.949661 Final RX Vref Byte 1 = 54 to rank0
8676 00:56:12.953061 Final RX Vref Byte 0 = 56 to rank1
8677 00:56:12.956090 Final RX Vref Byte 1 = 54 to rank1==
8678 00:56:12.959632 Dram Type= 6, Freq= 0, CH_1, rank 0
8679 00:56:12.966143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8680 00:56:12.966294 ==
8681 00:56:12.966391 DQS Delay:
8682 00:56:12.966491 DQS0 = 0, DQS1 = 0
8683 00:56:12.969765 DQM Delay:
8684 00:56:12.969893 DQM0 = 133, DQM1 = 131
8685 00:56:12.972659 DQ Delay:
8686 00:56:12.976337 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8687 00:56:12.979077 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8688 00:56:12.982508 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8689 00:56:12.985729 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8690 00:56:12.985811
8691 00:56:12.985872
8692 00:56:12.985927
8693 00:56:12.989483 [DramC_TX_OE_Calibration] TA2
8694 00:56:12.992426 Original DQ_B0 (3 6) =30, OEN = 27
8695 00:56:12.995808 Original DQ_B1 (3 6) =30, OEN = 27
8696 00:56:12.999247 24, 0x0, End_B0=24 End_B1=24
8697 00:56:12.999346 25, 0x0, End_B0=25 End_B1=25
8698 00:56:13.002699 26, 0x0, End_B0=26 End_B1=26
8699 00:56:13.006141 27, 0x0, End_B0=27 End_B1=27
8700 00:56:13.009009 28, 0x0, End_B0=28 End_B1=28
8701 00:56:13.009136 29, 0x0, End_B0=29 End_B1=29
8702 00:56:13.012603 30, 0x0, End_B0=30 End_B1=30
8703 00:56:13.016193 31, 0x5151, End_B0=30 End_B1=30
8704 00:56:13.019177 Byte0 end_step=30 best_step=27
8705 00:56:13.022683 Byte1 end_step=30 best_step=27
8706 00:56:13.026159 Byte0 TX OE(2T, 0.5T) = (3, 3)
8707 00:56:13.026239 Byte1 TX OE(2T, 0.5T) = (3, 3)
8708 00:56:13.026302
8709 00:56:13.029006
8710 00:56:13.035648 [DQSOSCAuto] RK0, (LSB)MR18= 0x1926, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8711 00:56:13.039362 CH1 RK0: MR19=303, MR18=1926
8712 00:56:13.046084 CH1_RK0: MR19=0x303, MR18=0x1926, DQSOSC=390, MR23=63, INC=24, DEC=16
8713 00:56:13.046219
8714 00:56:13.049123 ----->DramcWriteLeveling(PI) begin...
8715 00:56:13.049228 ==
8716 00:56:13.052346 Dram Type= 6, Freq= 0, CH_1, rank 1
8717 00:56:13.056001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 00:56:13.056106 ==
8719 00:56:13.059545 Write leveling (Byte 0): 25 => 25
8720 00:56:13.062576 Write leveling (Byte 1): 30 => 30
8721 00:56:13.065659 DramcWriteLeveling(PI) end<-----
8722 00:56:13.065751
8723 00:56:13.065834 ==
8724 00:56:13.069160 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 00:56:13.072545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 00:56:13.072625 ==
8727 00:56:13.075898 [Gating] SW mode calibration
8728 00:56:13.082870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8729 00:56:13.089130 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8730 00:56:13.092576 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 00:56:13.095978 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 00:56:13.102473 1 4 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8733 00:56:13.105455 1 4 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8734 00:56:13.108832 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 00:56:13.115807 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 00:56:13.119083 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 00:56:13.122651 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 00:56:13.128714 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 00:56:13.132457 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 00:56:13.135291 1 5 8 | B1->B0 | 2626 3434 | 0 1 | (1 0) (1 1)
8741 00:56:13.141908 1 5 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8742 00:56:13.145279 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 00:56:13.149194 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 00:56:13.155488 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 00:56:13.158757 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 00:56:13.161900 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 00:56:13.168768 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 00:56:13.172120 1 6 8 | B1->B0 | 4444 2323 | 0 0 | (0 0) (0 0)
8749 00:56:13.175589 1 6 12 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
8750 00:56:13.182172 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 00:56:13.185337 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 00:56:13.188421 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 00:56:13.192256 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 00:56:13.198898 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 00:56:13.202406 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 00:56:13.205137 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8757 00:56:13.212359 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8758 00:56:13.215373 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8759 00:56:13.218636 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 00:56:13.225463 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 00:56:13.228979 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 00:56:13.232237 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 00:56:13.238419 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 00:56:13.241827 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 00:56:13.245256 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 00:56:13.252091 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 00:56:13.254931 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 00:56:13.258895 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 00:56:13.265339 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 00:56:13.268598 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 00:56:13.271922 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8772 00:56:13.278212 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8773 00:56:13.282176 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8774 00:56:13.285106 Total UI for P1: 0, mck2ui 16
8775 00:56:13.288549 best dqsien dly found for B1: ( 1, 9, 6)
8776 00:56:13.292043 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8777 00:56:13.298668 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 00:56:13.298749 Total UI for P1: 0, mck2ui 16
8779 00:56:13.301751 best dqsien dly found for B0: ( 1, 9, 14)
8780 00:56:13.305424 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8781 00:56:13.311755 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8782 00:56:13.311832
8783 00:56:13.315003 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8784 00:56:13.318166 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8785 00:56:13.322000 [Gating] SW calibration Done
8786 00:56:13.322072 ==
8787 00:56:13.324955 Dram Type= 6, Freq= 0, CH_1, rank 1
8788 00:56:13.328633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 00:56:13.328706 ==
8790 00:56:13.331649 RX Vref Scan: 0
8791 00:56:13.331721
8792 00:56:13.331779 RX Vref 0 -> 0, step: 1
8793 00:56:13.331832
8794 00:56:13.334857 RX Delay 0 -> 252, step: 8
8795 00:56:13.338143 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8796 00:56:13.341615 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8797 00:56:13.348145 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8798 00:56:13.351631 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8799 00:56:13.355122 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8800 00:56:13.358594 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8801 00:56:13.361388 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8802 00:56:13.368076 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8803 00:56:13.371383 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8804 00:56:13.374631 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8805 00:56:13.378572 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8806 00:56:13.381848 iDelay=208, Bit 11, Center 131 (80 ~ 183) 104
8807 00:56:13.388153 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8808 00:56:13.391684 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8809 00:56:13.395165 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8810 00:56:13.397977 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8811 00:56:13.398069 ==
8812 00:56:13.401403 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 00:56:13.408123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 00:56:13.408203 ==
8815 00:56:13.408262 DQS Delay:
8816 00:56:13.408316 DQS0 = 0, DQS1 = 0
8817 00:56:13.411499 DQM Delay:
8818 00:56:13.411564 DQM0 = 136, DQM1 = 134
8819 00:56:13.414558 DQ Delay:
8820 00:56:13.418483 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8821 00:56:13.421692 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8822 00:56:13.424789 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =131
8823 00:56:13.428077 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8824 00:56:13.428146
8825 00:56:13.428202
8826 00:56:13.428255 ==
8827 00:56:13.431239 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 00:56:13.434557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 00:56:13.437887 ==
8830 00:56:13.437960
8831 00:56:13.438018
8832 00:56:13.438079 TX Vref Scan disable
8833 00:56:13.441499 == TX Byte 0 ==
8834 00:56:13.444726 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8835 00:56:13.447868 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8836 00:56:13.451088 == TX Byte 1 ==
8837 00:56:13.454558 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8838 00:56:13.458020 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8839 00:56:13.461413 ==
8840 00:56:13.461483 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 00:56:13.468405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 00:56:13.468491 ==
8843 00:56:13.479890
8844 00:56:13.483166 TX Vref early break, caculate TX vref
8845 00:56:13.486454 TX Vref=16, minBit 1, minWin=22, winSum=379
8846 00:56:13.489727 TX Vref=18, minBit 0, minWin=23, winSum=387
8847 00:56:13.493455 TX Vref=20, minBit 0, minWin=23, winSum=396
8848 00:56:13.496667 TX Vref=22, minBit 0, minWin=24, winSum=404
8849 00:56:13.500095 TX Vref=24, minBit 0, minWin=24, winSum=413
8850 00:56:13.506428 TX Vref=26, minBit 6, minWin=24, winSum=427
8851 00:56:13.509835 TX Vref=28, minBit 0, minWin=25, winSum=425
8852 00:56:13.513210 TX Vref=30, minBit 0, minWin=25, winSum=418
8853 00:56:13.516612 TX Vref=32, minBit 0, minWin=25, winSum=416
8854 00:56:13.519986 TX Vref=34, minBit 6, minWin=23, winSum=401
8855 00:56:13.526962 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8856 00:56:13.527034
8857 00:56:13.529580 Final TX Range 0 Vref 28
8858 00:56:13.529648
8859 00:56:13.529715 ==
8860 00:56:13.533001 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 00:56:13.536762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 00:56:13.536833 ==
8863 00:56:13.536889
8864 00:56:13.536953
8865 00:56:13.539843 TX Vref Scan disable
8866 00:56:13.546468 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8867 00:56:13.546546 == TX Byte 0 ==
8868 00:56:13.549974 u2DelayCellOfst[0]=20 cells (6 PI)
8869 00:56:13.553614 u2DelayCellOfst[1]=16 cells (5 PI)
8870 00:56:13.556736 u2DelayCellOfst[2]=0 cells (0 PI)
8871 00:56:13.559792 u2DelayCellOfst[3]=10 cells (3 PI)
8872 00:56:13.563473 u2DelayCellOfst[4]=13 cells (4 PI)
8873 00:56:13.566900 u2DelayCellOfst[5]=23 cells (7 PI)
8874 00:56:13.566969 u2DelayCellOfst[6]=23 cells (7 PI)
8875 00:56:13.570325 u2DelayCellOfst[7]=10 cells (3 PI)
8876 00:56:13.576530 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8877 00:56:13.580130 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8878 00:56:13.580196 == TX Byte 1 ==
8879 00:56:13.583516 u2DelayCellOfst[8]=0 cells (0 PI)
8880 00:56:13.586795 u2DelayCellOfst[9]=6 cells (2 PI)
8881 00:56:13.590083 u2DelayCellOfst[10]=13 cells (4 PI)
8882 00:56:13.593481 u2DelayCellOfst[11]=6 cells (2 PI)
8883 00:56:13.596217 u2DelayCellOfst[12]=16 cells (5 PI)
8884 00:56:13.599663 u2DelayCellOfst[13]=20 cells (6 PI)
8885 00:56:13.603426 u2DelayCellOfst[14]=20 cells (6 PI)
8886 00:56:13.606818 u2DelayCellOfst[15]=20 cells (6 PI)
8887 00:56:13.609552 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8888 00:56:13.616327 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8889 00:56:13.616400 DramC Write-DBI on
8890 00:56:13.616463 ==
8891 00:56:13.619770 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 00:56:13.623198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 00:56:13.623264 ==
8894 00:56:13.626520
8895 00:56:13.626583
8896 00:56:13.626641 TX Vref Scan disable
8897 00:56:13.629836 == TX Byte 0 ==
8898 00:56:13.632591 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8899 00:56:13.636136 == TX Byte 1 ==
8900 00:56:13.639674 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8901 00:56:13.643018 DramC Write-DBI off
8902 00:56:13.643092
8903 00:56:13.643147 [DATLAT]
8904 00:56:13.643199 Freq=1600, CH1 RK1
8905 00:56:13.643251
8906 00:56:13.646318 DATLAT Default: 0xf
8907 00:56:13.646387 0, 0xFFFF, sum = 0
8908 00:56:13.649826 1, 0xFFFF, sum = 0
8909 00:56:13.649894 2, 0xFFFF, sum = 0
8910 00:56:13.653082 3, 0xFFFF, sum = 0
8911 00:56:13.656347 4, 0xFFFF, sum = 0
8912 00:56:13.656418 5, 0xFFFF, sum = 0
8913 00:56:13.659748 6, 0xFFFF, sum = 0
8914 00:56:13.659814 7, 0xFFFF, sum = 0
8915 00:56:13.662914 8, 0xFFFF, sum = 0
8916 00:56:13.662985 9, 0xFFFF, sum = 0
8917 00:56:13.666049 10, 0xFFFF, sum = 0
8918 00:56:13.666118 11, 0xFFFF, sum = 0
8919 00:56:13.669642 12, 0xFFFF, sum = 0
8920 00:56:13.669715 13, 0xFFFF, sum = 0
8921 00:56:13.672787 14, 0x0, sum = 1
8922 00:56:13.672853 15, 0x0, sum = 2
8923 00:56:13.675769 16, 0x0, sum = 3
8924 00:56:13.675839 17, 0x0, sum = 4
8925 00:56:13.679420 best_step = 15
8926 00:56:13.679515
8927 00:56:13.679577 ==
8928 00:56:13.682688 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 00:56:13.686082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 00:56:13.686148 ==
8931 00:56:13.689460 RX Vref Scan: 0
8932 00:56:13.689529
8933 00:56:13.689596 RX Vref 0 -> 0, step: 1
8934 00:56:13.689649
8935 00:56:13.692810 RX Delay 19 -> 252, step: 4
8936 00:56:13.695972 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8937 00:56:13.702873 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8938 00:56:13.706295 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8939 00:56:13.709496 iDelay=195, Bit 3, Center 128 (79 ~ 178) 100
8940 00:56:13.712470 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8941 00:56:13.715895 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8942 00:56:13.722745 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8943 00:56:13.726163 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8944 00:56:13.729470 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8945 00:56:13.732768 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8946 00:56:13.736160 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8947 00:56:13.742383 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8948 00:56:13.745710 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8949 00:56:13.749133 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8950 00:56:13.752661 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8951 00:56:13.755989 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8952 00:56:13.759206 ==
8953 00:56:13.762553 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 00:56:13.765915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 00:56:13.765985 ==
8956 00:56:13.766051 DQS Delay:
8957 00:56:13.769393 DQS0 = 0, DQS1 = 0
8958 00:56:13.769459 DQM Delay:
8959 00:56:13.772029 DQM0 = 133, DQM1 = 130
8960 00:56:13.772100 DQ Delay:
8961 00:56:13.775358 DQ0 =138, DQ1 =128, DQ2 =120, DQ3 =128
8962 00:56:13.779130 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =130
8963 00:56:13.782228 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8964 00:56:13.785842 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8965 00:56:13.785921
8966 00:56:13.785979
8967 00:56:13.786037
8968 00:56:13.788893 [DramC_TX_OE_Calibration] TA2
8969 00:56:13.791976 Original DQ_B0 (3 6) =30, OEN = 27
8970 00:56:13.795768 Original DQ_B1 (3 6) =30, OEN = 27
8971 00:56:13.798893 24, 0x0, End_B0=24 End_B1=24
8972 00:56:13.802208 25, 0x0, End_B0=25 End_B1=25
8973 00:56:13.802283 26, 0x0, End_B0=26 End_B1=26
8974 00:56:13.805610 27, 0x0, End_B0=27 End_B1=27
8975 00:56:13.808723 28, 0x0, End_B0=28 End_B1=28
8976 00:56:13.812093 29, 0x0, End_B0=29 End_B1=29
8977 00:56:13.812161 30, 0x0, End_B0=30 End_B1=30
8978 00:56:13.815638 31, 0x4141, End_B0=30 End_B1=30
8979 00:56:13.818729 Byte0 end_step=30 best_step=27
8980 00:56:13.821823 Byte1 end_step=30 best_step=27
8981 00:56:13.825794 Byte0 TX OE(2T, 0.5T) = (3, 3)
8982 00:56:13.828502 Byte1 TX OE(2T, 0.5T) = (3, 3)
8983 00:56:13.828596
8984 00:56:13.828676
8985 00:56:13.835396 [DQSOSCAuto] RK1, (LSB)MR18= 0x2307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
8986 00:56:13.838705 CH1 RK1: MR19=303, MR18=2307
8987 00:56:13.845618 CH1_RK1: MR19=0x303, MR18=0x2307, DQSOSC=392, MR23=63, INC=24, DEC=16
8988 00:56:13.848413 [RxdqsGatingPostProcess] freq 1600
8989 00:56:13.855368 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8990 00:56:13.855438 best DQS0 dly(2T, 0.5T) = (1, 1)
8991 00:56:13.858789 best DQS1 dly(2T, 0.5T) = (1, 1)
8992 00:56:13.862211 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8993 00:56:13.865467 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8994 00:56:13.868631 best DQS0 dly(2T, 0.5T) = (1, 1)
8995 00:56:13.871928 best DQS1 dly(2T, 0.5T) = (1, 1)
8996 00:56:13.875184 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8997 00:56:13.878695 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8998 00:56:13.881415 Pre-setting of DQS Precalculation
8999 00:56:13.884891 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9000 00:56:13.895054 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9001 00:56:13.901411 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9002 00:56:13.901535
9003 00:56:13.901655
9004 00:56:13.905141 [Calibration Summary] 3200 Mbps
9005 00:56:13.905240 CH 0, Rank 0
9006 00:56:13.908027 SW Impedance : PASS
9007 00:56:13.908118 DUTY Scan : NO K
9008 00:56:13.911345 ZQ Calibration : PASS
9009 00:56:13.914557 Jitter Meter : NO K
9010 00:56:13.914659 CBT Training : PASS
9011 00:56:13.917874 Write leveling : PASS
9012 00:56:13.921826 RX DQS gating : PASS
9013 00:56:13.921892 RX DQ/DQS(RDDQC) : PASS
9014 00:56:13.924970 TX DQ/DQS : PASS
9015 00:56:13.928038 RX DATLAT : PASS
9016 00:56:13.928124 RX DQ/DQS(Engine): PASS
9017 00:56:13.931113 TX OE : PASS
9018 00:56:13.931213 All Pass.
9019 00:56:13.931303
9020 00:56:13.934710 CH 0, Rank 1
9021 00:56:13.934777 SW Impedance : PASS
9022 00:56:13.938133 DUTY Scan : NO K
9023 00:56:13.938219 ZQ Calibration : PASS
9024 00:56:13.941471 Jitter Meter : NO K
9025 00:56:13.944704 CBT Training : PASS
9026 00:56:13.944795 Write leveling : PASS
9027 00:56:13.947999 RX DQS gating : PASS
9028 00:56:13.951430 RX DQ/DQS(RDDQC) : PASS
9029 00:56:13.951492 TX DQ/DQS : PASS
9030 00:56:13.954913 RX DATLAT : PASS
9031 00:56:13.958398 RX DQ/DQS(Engine): PASS
9032 00:56:13.958463 TX OE : PASS
9033 00:56:13.961076 All Pass.
9034 00:56:13.961162
9035 00:56:13.961257 CH 1, Rank 0
9036 00:56:13.964593 SW Impedance : PASS
9037 00:56:13.964678 DUTY Scan : NO K
9038 00:56:13.968121 ZQ Calibration : PASS
9039 00:56:13.971664 Jitter Meter : NO K
9040 00:56:13.971759 CBT Training : PASS
9041 00:56:13.974956 Write leveling : PASS
9042 00:56:13.977680 RX DQS gating : PASS
9043 00:56:13.977760 RX DQ/DQS(RDDQC) : PASS
9044 00:56:13.980939 TX DQ/DQS : PASS
9045 00:56:13.984333 RX DATLAT : PASS
9046 00:56:13.984405 RX DQ/DQS(Engine): PASS
9047 00:56:13.987750 TX OE : PASS
9048 00:56:13.987837 All Pass.
9049 00:56:13.987917
9050 00:56:13.988011 CH 1, Rank 1
9051 00:56:13.991237 SW Impedance : PASS
9052 00:56:13.994559 DUTY Scan : NO K
9053 00:56:13.994646 ZQ Calibration : PASS
9054 00:56:13.997854 Jitter Meter : NO K
9055 00:56:14.001171 CBT Training : PASS
9056 00:56:14.001237 Write leveling : PASS
9057 00:56:14.004246 RX DQS gating : PASS
9058 00:56:14.007736 RX DQ/DQS(RDDQC) : PASS
9059 00:56:14.007808 TX DQ/DQS : PASS
9060 00:56:14.011240 RX DATLAT : PASS
9061 00:56:14.014555 RX DQ/DQS(Engine): PASS
9062 00:56:14.014626 TX OE : PASS
9063 00:56:14.017444 All Pass.
9064 00:56:14.017534
9065 00:56:14.017615 DramC Write-DBI on
9066 00:56:14.021037 PER_BANK_REFRESH: Hybrid Mode
9067 00:56:14.021104 TX_TRACKING: ON
9068 00:56:14.030936 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9069 00:56:14.041132 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9070 00:56:14.047731 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9071 00:56:14.051178 [FAST_K] Save calibration result to emmc
9072 00:56:14.054089 sync common calibartion params.
9073 00:56:14.054160 sync cbt_mode0:1, 1:1
9074 00:56:14.057400 dram_init: ddr_geometry: 2
9075 00:56:14.060849 dram_init: ddr_geometry: 2
9076 00:56:14.060922 dram_init: ddr_geometry: 2
9077 00:56:14.064231 0:dram_rank_size:100000000
9078 00:56:14.067755 1:dram_rank_size:100000000
9079 00:56:14.074039 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9080 00:56:14.074111 DFS_SHUFFLE_HW_MODE: ON
9081 00:56:14.077413 dramc_set_vcore_voltage set vcore to 725000
9082 00:56:14.080792 Read voltage for 1600, 0
9083 00:56:14.080864 Vio18 = 0
9084 00:56:14.084093 Vcore = 725000
9085 00:56:14.084161 Vdram = 0
9086 00:56:14.084216 Vddq = 0
9087 00:56:14.087347 Vmddr = 0
9088 00:56:14.087412 switch to 3200 Mbps bootup
9089 00:56:14.090743 [DramcRunTimeConfig]
9090 00:56:14.090824 PHYPLL
9091 00:56:14.094183 DPM_CONTROL_AFTERK: ON
9092 00:56:14.094250 PER_BANK_REFRESH: ON
9093 00:56:14.097646 REFRESH_OVERHEAD_REDUCTION: ON
9094 00:56:14.101093 CMD_PICG_NEW_MODE: OFF
9095 00:56:14.101189 XRTWTW_NEW_MODE: ON
9096 00:56:14.104561 XRTRTR_NEW_MODE: ON
9097 00:56:14.104654 TX_TRACKING: ON
9098 00:56:14.107791 RDSEL_TRACKING: OFF
9099 00:56:14.111007 DQS Precalculation for DVFS: ON
9100 00:56:14.111090 RX_TRACKING: OFF
9101 00:56:14.114182 HW_GATING DBG: ON
9102 00:56:14.114261 ZQCS_ENABLE_LP4: ON
9103 00:56:14.117610 RX_PICG_NEW_MODE: ON
9104 00:56:14.117690 TX_PICG_NEW_MODE: ON
9105 00:56:14.121010 ENABLE_RX_DCM_DPHY: ON
9106 00:56:14.124474 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9107 00:56:14.127997 DUMMY_READ_FOR_TRACKING: OFF
9108 00:56:14.128077 !!! SPM_CONTROL_AFTERK: OFF
9109 00:56:14.131169 !!! SPM could not control APHY
9110 00:56:14.134378 IMPEDANCE_TRACKING: ON
9111 00:56:14.134456 TEMP_SENSOR: ON
9112 00:56:14.137564 HW_SAVE_FOR_SR: OFF
9113 00:56:14.140778 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9114 00:56:14.144577 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9115 00:56:14.144655 Read ODT Tracking: ON
9116 00:56:14.147516 Refresh Rate DeBounce: ON
9117 00:56:14.150837 DFS_NO_QUEUE_FLUSH: ON
9118 00:56:14.154108 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9119 00:56:14.154187 ENABLE_DFS_RUNTIME_MRW: OFF
9120 00:56:14.157840 DDR_RESERVE_NEW_MODE: ON
9121 00:56:14.160974 MR_CBT_SWITCH_FREQ: ON
9122 00:56:14.161051 =========================
9123 00:56:14.180807 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9124 00:56:14.184129 dram_init: ddr_geometry: 2
9125 00:56:14.202465 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9126 00:56:14.205704 dram_init: dram init end (result: 0)
9127 00:56:14.212568 DRAM-K: Full calibration passed in 24429 msecs
9128 00:56:14.215996 MRC: failed to locate region type 0.
9129 00:56:14.216081 DRAM rank0 size:0x100000000,
9130 00:56:14.219245 DRAM rank1 size=0x100000000
9131 00:56:14.229135 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9132 00:56:14.235389 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9133 00:56:14.242489 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9134 00:56:14.248905 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9135 00:56:14.252278 DRAM rank0 size:0x100000000,
9136 00:56:14.255314 DRAM rank1 size=0x100000000
9137 00:56:14.255395 CBMEM:
9138 00:56:14.258612 IMD: root @ 0xfffff000 254 entries.
9139 00:56:14.262147 IMD: root @ 0xffffec00 62 entries.
9140 00:56:14.265270 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9141 00:56:14.272282 WARNING: RO_VPD is uninitialized or empty.
9142 00:56:14.275471 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9143 00:56:14.282861 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9144 00:56:14.295204 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9145 00:56:14.306659 BS: romstage times (exec / console): total (unknown) / 23964 ms
9146 00:56:14.306772
9147 00:56:14.306834
9148 00:56:14.316624 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9149 00:56:14.320020 ARM64: Exception handlers installed.
9150 00:56:14.323442 ARM64: Testing exception
9151 00:56:14.326726 ARM64: Done test exception
9152 00:56:14.326794 Enumerating buses...
9153 00:56:14.329946 Show all devs... Before device enumeration.
9154 00:56:14.333250 Root Device: enabled 1
9155 00:56:14.336782 CPU_CLUSTER: 0: enabled 1
9156 00:56:14.336859 CPU: 00: enabled 1
9157 00:56:14.340193 Compare with tree...
9158 00:56:14.340271 Root Device: enabled 1
9159 00:56:14.343556 CPU_CLUSTER: 0: enabled 1
9160 00:56:14.346842 CPU: 00: enabled 1
9161 00:56:14.346921 Root Device scanning...
9162 00:56:14.350142 scan_static_bus for Root Device
9163 00:56:14.352983 CPU_CLUSTER: 0 enabled
9164 00:56:14.356413 scan_static_bus for Root Device done
9165 00:56:14.359870 scan_bus: bus Root Device finished in 8 msecs
9166 00:56:14.359974 done
9167 00:56:14.366819 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9168 00:56:14.370181 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9169 00:56:14.376291 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9170 00:56:14.379779 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9171 00:56:14.382950 Allocating resources...
9172 00:56:14.386562 Reading resources...
9173 00:56:14.389863 Root Device read_resources bus 0 link: 0
9174 00:56:14.389944 DRAM rank0 size:0x100000000,
9175 00:56:14.393117 DRAM rank1 size=0x100000000
9176 00:56:14.396396 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9177 00:56:14.399517 CPU: 00 missing read_resources
9178 00:56:14.403216 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9179 00:56:14.409869 Root Device read_resources bus 0 link: 0 done
9180 00:56:14.409979 Done reading resources.
9181 00:56:14.416814 Show resources in subtree (Root Device)...After reading.
9182 00:56:14.420260 Root Device child on link 0 CPU_CLUSTER: 0
9183 00:56:14.422923 CPU_CLUSTER: 0 child on link 0 CPU: 00
9184 00:56:14.433184 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9185 00:56:14.433272 CPU: 00
9186 00:56:14.436476 Root Device assign_resources, bus 0 link: 0
9187 00:56:14.439644 CPU_CLUSTER: 0 missing set_resources
9188 00:56:14.443067 Root Device assign_resources, bus 0 link: 0 done
9189 00:56:14.446512 Done setting resources.
9190 00:56:14.453004 Show resources in subtree (Root Device)...After assigning values.
9191 00:56:14.456402 Root Device child on link 0 CPU_CLUSTER: 0
9192 00:56:14.459877 CPU_CLUSTER: 0 child on link 0 CPU: 00
9193 00:56:14.469615 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9194 00:56:14.469723 CPU: 00
9195 00:56:14.472995 Done allocating resources.
9196 00:56:14.475876 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9197 00:56:14.479260 Enabling resources...
9198 00:56:14.479338 done.
9199 00:56:14.485758 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9200 00:56:14.485862 Initializing devices...
9201 00:56:14.488940 Root Device init
9202 00:56:14.489019 init hardware done!
9203 00:56:14.492673 0x00000018: ctrlr->caps
9204 00:56:14.495928 52.000 MHz: ctrlr->f_max
9205 00:56:14.496008 0.400 MHz: ctrlr->f_min
9206 00:56:14.498918 0x40ff8080: ctrlr->voltages
9207 00:56:14.498998 sclk: 390625
9208 00:56:14.502403 Bus Width = 1
9209 00:56:14.502515 sclk: 390625
9210 00:56:14.505818 Bus Width = 1
9211 00:56:14.505896 Early init status = 3
9212 00:56:14.512350 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9213 00:56:14.515336 in-header: 03 fc 00 00 01 00 00 00
9214 00:56:14.515415 in-data: 00
9215 00:56:14.521884 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9216 00:56:14.525533 in-header: 03 fd 00 00 00 00 00 00
9217 00:56:14.528868 in-data:
9218 00:56:14.532058 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9219 00:56:14.536051 in-header: 03 fc 00 00 01 00 00 00
9220 00:56:14.539511 in-data: 00
9221 00:56:14.542939 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9222 00:56:14.548182 in-header: 03 fd 00 00 00 00 00 00
9223 00:56:14.551466 in-data:
9224 00:56:14.554848 [SSUSB] Setting up USB HOST controller...
9225 00:56:14.558167 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9226 00:56:14.561478 [SSUSB] phy power-on done.
9227 00:56:14.564961 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9228 00:56:14.571800 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9229 00:56:14.575176 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9230 00:56:14.581412 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9231 00:56:14.588164 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9232 00:56:14.594499 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9233 00:56:14.601365 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9234 00:56:14.607822 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9235 00:56:14.611604 SPM: binary array size = 0x9dc
9236 00:56:14.614628 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9237 00:56:14.621556 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9238 00:56:14.627898 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9239 00:56:14.631589 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9240 00:56:14.637605 configure_display: Starting display init
9241 00:56:14.671922 anx7625_power_on_init: Init interface.
9242 00:56:14.675390 anx7625_disable_pd_protocol: Disabled PD feature.
9243 00:56:14.678307 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9244 00:56:14.706466 anx7625_start_dp_work: Secure OCM version=00
9245 00:56:14.709642 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9246 00:56:14.724173 sp_tx_get_edid_block: EDID Block = 1
9247 00:56:14.827063 Extracted contents:
9248 00:56:14.830374 header: 00 ff ff ff ff ff ff 00
9249 00:56:14.833693 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9250 00:56:14.836914 version: 01 04
9251 00:56:14.840065 basic params: 95 1f 11 78 0a
9252 00:56:14.843222 chroma info: 76 90 94 55 54 90 27 21 50 54
9253 00:56:14.846699 established: 00 00 00
9254 00:56:14.853414 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9255 00:56:14.856880 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9256 00:56:14.863395 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9257 00:56:14.869872 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9258 00:56:14.876417 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9259 00:56:14.879813 extensions: 00
9260 00:56:14.879938 checksum: fb
9261 00:56:14.880026
9262 00:56:14.882956 Manufacturer: IVO Model 57d Serial Number 0
9263 00:56:14.886422 Made week 0 of 2020
9264 00:56:14.886517 EDID version: 1.4
9265 00:56:14.889772 Digital display
9266 00:56:14.893416 6 bits per primary color channel
9267 00:56:14.893525 DisplayPort interface
9268 00:56:14.896630 Maximum image size: 31 cm x 17 cm
9269 00:56:14.900111 Gamma: 220%
9270 00:56:14.900188 Check DPMS levels
9271 00:56:14.903654 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9272 00:56:14.906439 First detailed timing is preferred timing
9273 00:56:14.909838 Established timings supported:
9274 00:56:14.913362 Standard timings supported:
9275 00:56:14.913462 Detailed timings
9276 00:56:14.920266 Hex of detail: 383680a07038204018303c0035ae10000019
9277 00:56:14.923024 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9278 00:56:14.929678 0780 0798 07c8 0820 hborder 0
9279 00:56:14.932942 0438 043b 0447 0458 vborder 0
9280 00:56:14.936360 -hsync -vsync
9281 00:56:14.936460 Did detailed timing
9282 00:56:14.939772 Hex of detail: 000000000000000000000000000000000000
9283 00:56:14.943041 Manufacturer-specified data, tag 0
9284 00:56:14.949998 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9285 00:56:14.950082 ASCII string: InfoVision
9286 00:56:14.956507 Hex of detail: 000000fe00523134304e574635205248200a
9287 00:56:14.956587 ASCII string: R140NWF5 RH
9288 00:56:14.959916 Checksum
9289 00:56:14.959992 Checksum: 0xfb (valid)
9290 00:56:14.966774 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9291 00:56:14.970144 DSI data_rate: 832800000 bps
9292 00:56:14.973398 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9293 00:56:14.976596 anx7625_parse_edid: pixelclock(138800).
9294 00:56:14.983268 hactive(1920), hsync(48), hfp(24), hbp(88)
9295 00:56:14.986780 vactive(1080), vsync(12), vfp(3), vbp(17)
9296 00:56:14.989459 anx7625_dsi_config: config dsi.
9297 00:56:14.996180 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9298 00:56:15.009099 anx7625_dsi_config: success to config DSI
9299 00:56:15.012668 anx7625_dp_start: MIPI phy setup OK.
9300 00:56:15.015418 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9301 00:56:15.018876 mtk_ddp_mode_set invalid vrefresh 60
9302 00:56:15.022312 main_disp_path_setup
9303 00:56:15.022390 ovl_layer_smi_id_en
9304 00:56:15.025901 ovl_layer_smi_id_en
9305 00:56:15.025992 ccorr_config
9306 00:56:15.026051 aal_config
9307 00:56:15.029221 gamma_config
9308 00:56:15.029298 postmask_config
9309 00:56:15.032479 dither_config
9310 00:56:15.035686 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9311 00:56:15.042452 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9312 00:56:15.045873 Root Device init finished in 553 msecs
9313 00:56:15.045952 CPU_CLUSTER: 0 init
9314 00:56:15.055520 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9315 00:56:15.058831 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9316 00:56:15.062066 APU_MBOX 0x190000b0 = 0x10001
9317 00:56:15.065868 APU_MBOX 0x190001b0 = 0x10001
9318 00:56:15.069119 APU_MBOX 0x190005b0 = 0x10001
9319 00:56:15.072638 APU_MBOX 0x190006b0 = 0x10001
9320 00:56:15.075436 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9321 00:56:15.087837 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9322 00:56:15.100513 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9323 00:56:15.107215 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9324 00:56:15.118401 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9325 00:56:15.127937 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9326 00:56:15.130856 CPU_CLUSTER: 0 init finished in 81 msecs
9327 00:56:15.134220 Devices initialized
9328 00:56:15.137374 Show all devs... After init.
9329 00:56:15.137455 Root Device: enabled 1
9330 00:56:15.140684 CPU_CLUSTER: 0: enabled 1
9331 00:56:15.144425 CPU: 00: enabled 1
9332 00:56:15.147778 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9333 00:56:15.151237 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9334 00:56:15.154535 ELOG: NV offset 0x57f000 size 0x1000
9335 00:56:15.160939 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9336 00:56:15.167516 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9337 00:56:15.171274 ELOG: Event(17) added with size 13 at 2024-06-16 00:56:15 UTC
9338 00:56:15.174508 out: cmd=0x121: 03 db 21 01 00 00 00 00
9339 00:56:15.178172 in-header: 03 8e 00 00 2c 00 00 00
9340 00:56:15.191147 in-data: af 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9341 00:56:15.197999 ELOG: Event(A1) added with size 10 at 2024-06-16 00:56:15 UTC
9342 00:56:15.204671 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9343 00:56:15.211375 ELOG: Event(A0) added with size 9 at 2024-06-16 00:56:15 UTC
9344 00:56:15.214658 elog_add_boot_reason: Logged dev mode boot
9345 00:56:15.218129 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9346 00:56:15.221383 Finalize devices...
9347 00:56:15.221459 Devices finalized
9348 00:56:15.228020 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9349 00:56:15.231404 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9350 00:56:15.234859 in-header: 03 07 00 00 08 00 00 00
9351 00:56:15.237568 in-data: aa e4 47 04 13 02 00 00
9352 00:56:15.241056 Chrome EC: UHEPI supported
9353 00:56:15.247894 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9354 00:56:15.251052 in-header: 03 a9 00 00 08 00 00 00
9355 00:56:15.254226 in-data: 84 60 60 08 00 00 00 00
9356 00:56:15.257680 ELOG: Event(91) added with size 10 at 2024-06-16 00:56:15 UTC
9357 00:56:15.264425 Chrome EC: clear events_b mask to 0x0000000020004000
9358 00:56:15.270965 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9359 00:56:15.274929 in-header: 03 fd 00 00 00 00 00 00
9360 00:56:15.275040 in-data:
9361 00:56:15.281753 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9362 00:56:15.284802 Writing coreboot table at 0xffe64000
9363 00:56:15.287882 0. 000000000010a000-0000000000113fff: RAMSTAGE
9364 00:56:15.291277 1. 0000000040000000-00000000400fffff: RAM
9365 00:56:15.294696 2. 0000000040100000-000000004032afff: RAMSTAGE
9366 00:56:15.301496 3. 000000004032b000-00000000545fffff: RAM
9367 00:56:15.304695 4. 0000000054600000-000000005465ffff: BL31
9368 00:56:15.308015 5. 0000000054660000-00000000ffe63fff: RAM
9369 00:56:15.311197 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9370 00:56:15.318250 7. 0000000100000000-000000023fffffff: RAM
9371 00:56:15.318360 Passing 5 GPIOs to payload:
9372 00:56:15.324827 NAME | PORT | POLARITY | VALUE
9373 00:56:15.328124 EC in RW | 0x000000aa | low | undefined
9374 00:56:15.334735 EC interrupt | 0x00000005 | low | undefined
9375 00:56:15.338154 TPM interrupt | 0x000000ab | high | undefined
9376 00:56:15.341485 SD card detect | 0x00000011 | high | undefined
9377 00:56:15.347686 speaker enable | 0x00000093 | high | undefined
9378 00:56:15.351133 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9379 00:56:15.354420 in-header: 03 f9 00 00 02 00 00 00
9380 00:56:15.354495 in-data: 02 00
9381 00:56:15.357559 ADC[4]: Raw value=904726 ID=7
9382 00:56:15.360777 ADC[3]: Raw value=213441 ID=1
9383 00:56:15.360877 RAM Code: 0x71
9384 00:56:15.364153 ADC[6]: Raw value=75332 ID=0
9385 00:56:15.367577 ADC[5]: Raw value=212703 ID=1
9386 00:56:15.367674 SKU Code: 0x1
9387 00:56:15.374504 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7a35
9388 00:56:15.377696 coreboot table: 964 bytes.
9389 00:56:15.380866 IMD ROOT 0. 0xfffff000 0x00001000
9390 00:56:15.384545 IMD SMALL 1. 0xffffe000 0x00001000
9391 00:56:15.387666 RO MCACHE 2. 0xffffc000 0x00001104
9392 00:56:15.390928 CONSOLE 3. 0xfff7c000 0x00080000
9393 00:56:15.394599 FMAP 4. 0xfff7b000 0x00000452
9394 00:56:15.397748 TIME STAMP 5. 0xfff7a000 0x00000910
9395 00:56:15.401337 VBOOT WORK 6. 0xfff66000 0x00014000
9396 00:56:15.404093 RAMOOPS 7. 0xffe66000 0x00100000
9397 00:56:15.407416 COREBOOT 8. 0xffe64000 0x00002000
9398 00:56:15.407510 IMD small region:
9399 00:56:15.410914 IMD ROOT 0. 0xffffec00 0x00000400
9400 00:56:15.414092 VPD 1. 0xffffeb80 0x0000006c
9401 00:56:15.417645 MMC STATUS 2. 0xffffeb60 0x00000004
9402 00:56:15.424098 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9403 00:56:15.430504 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9404 00:56:15.469794 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9405 00:56:15.473258 Checking segment from ROM address 0x40100000
9406 00:56:15.476822 Checking segment from ROM address 0x4010001c
9407 00:56:15.483567 Loading segment from ROM address 0x40100000
9408 00:56:15.483663 code (compression=0)
9409 00:56:15.493389 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9410 00:56:15.499953 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9411 00:56:15.500068 it's not compressed!
9412 00:56:15.506863 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9413 00:56:15.510053 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9414 00:56:15.530547 Loading segment from ROM address 0x4010001c
9415 00:56:15.530681 Entry Point 0x80000000
9416 00:56:15.533971 Loaded segments
9417 00:56:15.537188 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9418 00:56:15.543746 Jumping to boot code at 0x80000000(0xffe64000)
9419 00:56:15.550849 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9420 00:56:15.557124 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9421 00:56:15.565357 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9422 00:56:15.568079 Checking segment from ROM address 0x40100000
9423 00:56:15.571424 Checking segment from ROM address 0x4010001c
9424 00:56:15.578301 Loading segment from ROM address 0x40100000
9425 00:56:15.578408 code (compression=1)
9426 00:56:15.585215 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9427 00:56:15.595216 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9428 00:56:15.595338 using LZMA
9429 00:56:15.603656 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9430 00:56:15.610204 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9431 00:56:15.613328 Loading segment from ROM address 0x4010001c
9432 00:56:15.613425 Entry Point 0x54601000
9433 00:56:15.616615 Loaded segments
9434 00:56:15.619783 NOTICE: MT8192 bl31_setup
9435 00:56:15.627018 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9436 00:56:15.630585 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9437 00:56:15.633434 WARNING: region 0:
9438 00:56:15.636763 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9439 00:56:15.636865 WARNING: region 1:
9440 00:56:15.643572 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9441 00:56:15.646766 WARNING: region 2:
9442 00:56:15.650106 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9443 00:56:15.653528 WARNING: region 3:
9444 00:56:15.656993 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9445 00:56:15.660440 WARNING: region 4:
9446 00:56:15.667007 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9447 00:56:15.667082 WARNING: region 5:
9448 00:56:15.670174 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 00:56:15.673892 WARNING: region 6:
9450 00:56:15.677061 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 00:56:15.680357 WARNING: region 7:
9452 00:56:15.683669 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 00:56:15.689999 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9454 00:56:15.693423 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9455 00:56:15.696834 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9456 00:56:15.703342 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9457 00:56:15.706798 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9458 00:56:15.710031 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9459 00:56:15.716492 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9460 00:56:15.719754 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9461 00:56:15.726495 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9462 00:56:15.730057 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9463 00:56:15.733428 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9464 00:56:15.740280 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9465 00:56:15.743023 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9466 00:56:15.746606 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9467 00:56:15.753425 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9468 00:56:15.756589 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9469 00:56:15.763248 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9470 00:56:15.766729 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9471 00:56:15.770132 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9472 00:56:15.776686 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9473 00:56:15.779808 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9474 00:56:15.786674 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9475 00:56:15.789884 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9476 00:56:15.792990 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9477 00:56:15.800092 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9478 00:56:15.802890 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9479 00:56:15.809460 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9480 00:56:15.815274 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9481 00:56:15.816264 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9482 00:56:15.848084 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9483 00:56:15.848248 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9484 00:56:15.848346 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9485 00:56:15.848438 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9486 00:56:15.848527 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9487 00:56:15.848616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9488 00:56:15.848700 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9489 00:56:15.853197 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9490 00:56:15.855925 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9491 00:56:15.859486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9492 00:56:15.862828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9493 00:56:15.869346 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9494 00:56:15.872943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9495 00:56:15.876416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9496 00:56:15.882880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9497 00:56:15.886144 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9498 00:56:15.889432 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9499 00:56:15.892944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9500 00:56:15.899043 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9501 00:56:15.902740 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9502 00:56:15.906040 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9503 00:56:15.912362 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9504 00:56:15.916212 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9505 00:56:15.922935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9506 00:56:15.926429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9507 00:56:15.932561 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9508 00:56:15.936380 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9509 00:56:15.939625 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9510 00:56:15.946411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9511 00:56:15.949595 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9512 00:56:15.956148 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9513 00:56:15.959521 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9514 00:56:15.966389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9515 00:56:15.969650 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9516 00:56:15.972787 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9517 00:56:15.979516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9518 00:56:15.982994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9519 00:56:15.989803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9520 00:56:15.993154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9521 00:56:15.999225 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9522 00:56:16.002609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9523 00:56:16.006124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9524 00:56:16.012813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9525 00:56:16.016038 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9526 00:56:16.022557 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9527 00:56:16.026329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9528 00:56:16.032537 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9529 00:56:16.036313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9530 00:56:16.042935 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9531 00:56:16.046024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9532 00:56:16.049430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9533 00:56:16.055891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9534 00:56:16.059311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9535 00:56:16.065891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9536 00:56:16.069327 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9537 00:56:16.075768 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9538 00:56:16.079636 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9539 00:56:16.082907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9540 00:56:16.089077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9541 00:56:16.092596 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9542 00:56:16.099416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9543 00:56:16.102700 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9544 00:56:16.109477 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9545 00:56:16.112311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9546 00:56:16.115756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9547 00:56:16.122372 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9548 00:56:16.125865 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9549 00:56:16.132814 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9550 00:56:16.135565 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9551 00:56:16.139484 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9552 00:56:16.142650 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9553 00:56:16.149346 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9554 00:56:16.152188 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9555 00:56:16.155789 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9556 00:56:16.162267 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9557 00:56:16.165879 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9558 00:56:16.172670 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9559 00:56:16.175774 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9560 00:56:16.179133 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9561 00:56:16.185838 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9562 00:56:16.188909 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9563 00:56:16.196022 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9564 00:56:16.198852 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9565 00:56:16.202335 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9566 00:56:16.209140 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9567 00:56:16.212628 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9568 00:56:16.218857 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9569 00:56:16.222089 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9570 00:56:16.225564 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9571 00:56:16.229041 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9572 00:56:16.235873 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9573 00:56:16.239342 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9574 00:56:16.242787 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9575 00:56:16.245606 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9576 00:56:16.252140 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9577 00:56:16.255562 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9578 00:56:16.258850 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9579 00:56:16.265936 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9580 00:56:16.269159 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9581 00:56:16.276186 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9582 00:56:16.279420 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9583 00:56:16.282502 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9584 00:56:16.288973 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9585 00:56:16.292597 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9586 00:56:16.296151 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9587 00:56:16.302378 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9588 00:56:16.306210 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9589 00:56:16.312364 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9590 00:56:16.315549 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9591 00:56:16.319026 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9592 00:56:16.326013 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9593 00:56:16.329409 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9594 00:56:16.335668 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9595 00:56:16.339057 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9596 00:56:16.342445 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9597 00:56:16.348672 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9598 00:56:16.352216 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9599 00:56:16.359188 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9600 00:56:16.362596 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9601 00:56:16.366070 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9602 00:56:16.372162 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9603 00:56:16.375961 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9604 00:56:16.379255 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9605 00:56:16.385984 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9606 00:56:16.389313 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9607 00:56:16.395878 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9608 00:56:16.398892 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9609 00:56:16.402770 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9610 00:56:16.408950 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9611 00:56:16.412671 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9612 00:56:16.419028 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9613 00:56:16.422094 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9614 00:56:16.425800 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9615 00:56:16.432667 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9616 00:56:16.435861 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9617 00:56:16.442153 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9618 00:56:16.445669 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9619 00:56:16.449228 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9620 00:56:16.455446 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9621 00:56:16.458918 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9622 00:56:16.462465 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9623 00:56:16.469032 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9624 00:56:16.472364 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9625 00:56:16.479151 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9626 00:56:16.482399 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9627 00:56:16.485598 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9628 00:56:16.492430 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9629 00:56:16.495796 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9630 00:56:16.501772 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9631 00:56:16.505076 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9632 00:56:16.508384 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9633 00:56:16.515661 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9634 00:56:16.518544 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9635 00:56:16.525169 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9636 00:56:16.528887 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9637 00:56:16.531816 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9638 00:56:16.538502 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9639 00:56:16.541529 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9640 00:56:16.545484 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9641 00:56:16.551665 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9642 00:56:16.555200 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9643 00:56:16.562293 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9644 00:56:16.565021 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9645 00:56:16.571930 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9646 00:56:16.575260 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9647 00:56:16.578945 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9648 00:56:16.585068 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9649 00:56:16.588249 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9650 00:56:16.594886 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9651 00:56:16.598390 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9652 00:56:16.601752 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9653 00:56:16.608727 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9654 00:56:16.611548 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9655 00:56:16.618735 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9656 00:56:16.621949 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9657 00:56:16.625355 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9658 00:56:16.632171 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9659 00:56:16.634905 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9660 00:56:16.642053 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9661 00:56:16.645210 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9662 00:56:16.651703 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9663 00:56:16.655408 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9664 00:56:16.658730 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9665 00:56:16.664944 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9666 00:56:16.668607 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9667 00:56:16.675369 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9668 00:56:16.678054 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9669 00:56:16.681508 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9670 00:56:16.688177 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9671 00:56:16.691414 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9672 00:56:16.698400 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9673 00:56:16.702113 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9674 00:56:16.704845 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9675 00:56:16.711525 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9676 00:56:16.714989 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9677 00:56:16.721775 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9678 00:56:16.724945 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9679 00:56:16.731449 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9680 00:56:16.734836 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9681 00:56:16.738252 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9682 00:56:16.745313 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9683 00:56:16.748530 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9684 00:56:16.751896 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9685 00:56:16.755106 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9686 00:56:16.758375 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9687 00:56:16.765272 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9688 00:56:16.768488 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9689 00:56:16.775146 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9690 00:56:16.778434 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9691 00:56:16.781438 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9692 00:56:16.788320 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9693 00:56:16.791770 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9694 00:56:16.795177 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9695 00:56:16.801859 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9696 00:56:16.804954 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9697 00:56:16.808443 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9698 00:56:16.815030 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9699 00:56:16.818469 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9700 00:56:16.824867 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9701 00:56:16.828345 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9702 00:56:16.831534 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9703 00:56:16.838004 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9704 00:56:16.841421 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9705 00:56:16.844857 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9706 00:56:16.851514 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9707 00:56:16.854925 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9708 00:56:16.858170 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9709 00:56:16.864977 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9710 00:56:16.868305 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9711 00:56:16.871460 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9712 00:56:16.878294 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9713 00:56:16.881651 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9714 00:56:16.888418 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9715 00:56:16.891549 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9716 00:56:16.894741 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9717 00:56:16.901508 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9718 00:56:16.904303 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9719 00:56:16.907775 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9720 00:56:16.914555 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9721 00:56:16.918296 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9722 00:56:16.921456 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9723 00:56:16.927994 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9724 00:56:16.931127 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9725 00:56:16.934735 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9726 00:56:16.938099 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9727 00:56:16.941209 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9728 00:56:16.947985 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9729 00:56:16.951428 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9730 00:56:16.954974 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9731 00:56:16.957812 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9732 00:56:16.964655 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9733 00:56:16.968075 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9734 00:56:16.971545 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9735 00:56:16.978342 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9736 00:56:16.981124 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9737 00:56:16.987951 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9738 00:56:16.991274 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9739 00:56:16.994618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9740 00:56:17.001342 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9741 00:56:17.004691 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9742 00:56:17.007980 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9743 00:56:17.014580 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9744 00:56:17.018083 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9745 00:56:17.024974 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9746 00:56:17.027779 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9747 00:56:17.034772 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9748 00:56:17.037860 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9749 00:56:17.041469 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9750 00:56:17.047851 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9751 00:56:17.051613 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9752 00:56:17.058149 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9753 00:56:17.061555 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9754 00:56:17.064380 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9755 00:56:17.071337 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9756 00:56:17.074694 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9757 00:56:17.080969 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9758 00:56:17.084907 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9759 00:56:17.087698 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9760 00:56:17.094860 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9761 00:56:17.098132 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9762 00:56:17.104852 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9763 00:56:17.108203 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9764 00:56:17.110960 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9765 00:56:17.118184 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9766 00:56:17.121452 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9767 00:56:17.127761 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9768 00:56:17.130975 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9769 00:56:17.137781 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9770 00:56:17.141203 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9771 00:56:17.143903 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9772 00:56:17.150686 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9773 00:56:17.154152 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9774 00:56:17.160894 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9775 00:56:17.164104 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9776 00:56:17.167198 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9777 00:56:17.173732 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9778 00:56:17.177054 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9779 00:56:17.183958 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9780 00:56:17.187203 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9781 00:56:17.193472 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9782 00:56:17.196878 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9783 00:56:17.200256 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9784 00:56:17.206857 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9785 00:56:17.210576 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9786 00:56:17.217096 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9787 00:56:17.220557 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9788 00:56:17.223882 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9789 00:56:17.230366 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9790 00:56:17.233834 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9791 00:56:17.240507 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9792 00:56:17.243389 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9793 00:56:17.246956 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9794 00:56:17.253937 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9795 00:56:17.257160 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9796 00:56:17.263819 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9797 00:56:17.267196 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9798 00:56:17.270306 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9799 00:56:17.277439 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9800 00:56:17.280495 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9801 00:56:17.287302 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9802 00:56:17.290639 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9803 00:56:17.293357 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9804 00:56:17.300264 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9805 00:56:17.303543 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9806 00:56:17.310459 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9807 00:56:17.314073 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9808 00:56:17.316686 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9809 00:56:17.323819 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9810 00:56:17.327029 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9811 00:56:17.333409 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9812 00:56:17.336710 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9813 00:56:17.343538 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9814 00:56:17.347023 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9815 00:56:17.350372 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9816 00:56:17.356730 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9817 00:56:17.360148 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9818 00:56:17.366983 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9819 00:56:17.370391 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9820 00:56:17.376768 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9821 00:56:17.379920 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9822 00:56:17.383496 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9823 00:56:17.390172 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9824 00:56:17.393245 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9825 00:56:17.399752 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9826 00:56:17.403494 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9827 00:56:17.410188 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9828 00:56:17.413565 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9829 00:56:17.419766 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9830 00:56:17.423175 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9831 00:56:17.426612 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9832 00:56:17.433097 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9833 00:56:17.436966 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9834 00:56:17.443562 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9835 00:56:17.446868 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9836 00:56:17.453485 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9837 00:56:17.456877 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9838 00:56:17.460313 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9839 00:56:17.466475 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9840 00:56:17.469970 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9841 00:56:17.476908 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9842 00:56:17.479798 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9843 00:56:17.486432 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9844 00:56:17.489478 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9845 00:56:17.496422 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9846 00:56:17.499869 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9847 00:56:17.503228 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9848 00:56:17.509721 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9849 00:56:17.512898 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9850 00:56:17.519389 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9851 00:56:17.522885 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9852 00:56:17.529981 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9853 00:56:17.532723 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9854 00:56:17.536040 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9855 00:56:17.542883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9856 00:56:17.546216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9857 00:56:17.552605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9858 00:56:17.556334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9859 00:56:17.562954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9860 00:56:17.565744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9861 00:56:17.572722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9862 00:56:17.575569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9863 00:56:17.579077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9864 00:56:17.585986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9865 00:56:17.589436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9866 00:56:17.595687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9867 00:56:17.598947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9868 00:56:17.605721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9869 00:56:17.609068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9870 00:56:17.615657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9871 00:56:17.619043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9872 00:56:17.625561 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9873 00:56:17.628815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9874 00:56:17.635614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9875 00:56:17.639284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9876 00:56:17.645959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9877 00:56:17.649293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9878 00:56:17.655919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9879 00:56:17.659274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9880 00:56:17.665631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9881 00:56:17.669461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9882 00:56:17.676135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9883 00:56:17.678825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9884 00:56:17.685923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9885 00:56:17.689189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9886 00:56:17.695501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9887 00:56:17.699032 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9888 00:56:17.701874 INFO: [APUAPC] vio 0
9889 00:56:17.705224 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9890 00:56:17.711978 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9891 00:56:17.715720 INFO: [APUAPC] D0_APC_0: 0x400510
9892 00:56:17.715799 INFO: [APUAPC] D0_APC_1: 0x0
9893 00:56:17.718712 INFO: [APUAPC] D0_APC_2: 0x1540
9894 00:56:17.722388 INFO: [APUAPC] D0_APC_3: 0x0
9895 00:56:17.725475 INFO: [APUAPC] D1_APC_0: 0xffffffff
9896 00:56:17.728722 INFO: [APUAPC] D1_APC_1: 0xffffffff
9897 00:56:17.732111 INFO: [APUAPC] D1_APC_2: 0x3fffff
9898 00:56:17.735430 INFO: [APUAPC] D1_APC_3: 0x0
9899 00:56:17.738826 INFO: [APUAPC] D2_APC_0: 0xffffffff
9900 00:56:17.742157 INFO: [APUAPC] D2_APC_1: 0xffffffff
9901 00:56:17.745541 INFO: [APUAPC] D2_APC_2: 0x3fffff
9902 00:56:17.748834 INFO: [APUAPC] D2_APC_3: 0x0
9903 00:56:17.752557 INFO: [APUAPC] D3_APC_0: 0xffffffff
9904 00:56:17.755527 INFO: [APUAPC] D3_APC_1: 0xffffffff
9905 00:56:17.758765 INFO: [APUAPC] D3_APC_2: 0x3fffff
9906 00:56:17.761893 INFO: [APUAPC] D3_APC_3: 0x0
9907 00:56:17.765750 INFO: [APUAPC] D4_APC_0: 0xffffffff
9908 00:56:17.769040 INFO: [APUAPC] D4_APC_1: 0xffffffff
9909 00:56:17.772242 INFO: [APUAPC] D4_APC_2: 0x3fffff
9910 00:56:17.775432 INFO: [APUAPC] D4_APC_3: 0x0
9911 00:56:17.778648 INFO: [APUAPC] D5_APC_0: 0xffffffff
9912 00:56:17.782347 INFO: [APUAPC] D5_APC_1: 0xffffffff
9913 00:56:17.785111 INFO: [APUAPC] D5_APC_2: 0x3fffff
9914 00:56:17.788473 INFO: [APUAPC] D5_APC_3: 0x0
9915 00:56:17.792199 INFO: [APUAPC] D6_APC_0: 0xffffffff
9916 00:56:17.795723 INFO: [APUAPC] D6_APC_1: 0xffffffff
9917 00:56:17.798489 INFO: [APUAPC] D6_APC_2: 0x3fffff
9918 00:56:17.801902 INFO: [APUAPC] D6_APC_3: 0x0
9919 00:56:17.805333 INFO: [APUAPC] D7_APC_0: 0xffffffff
9920 00:56:17.808857 INFO: [APUAPC] D7_APC_1: 0xffffffff
9921 00:56:17.812270 INFO: [APUAPC] D7_APC_2: 0x3fffff
9922 00:56:17.815744 INFO: [APUAPC] D7_APC_3: 0x0
9923 00:56:17.818404 INFO: [APUAPC] D8_APC_0: 0xffffffff
9924 00:56:17.821688 INFO: [APUAPC] D8_APC_1: 0xffffffff
9925 00:56:17.825463 INFO: [APUAPC] D8_APC_2: 0x3fffff
9926 00:56:17.825542 INFO: [APUAPC] D8_APC_3: 0x0
9927 00:56:17.828688 INFO: [APUAPC] D9_APC_0: 0xffffffff
9928 00:56:17.835482 INFO: [APUAPC] D9_APC_1: 0xffffffff
9929 00:56:17.838660 INFO: [APUAPC] D9_APC_2: 0x3fffff
9930 00:56:17.838739 INFO: [APUAPC] D9_APC_3: 0x0
9931 00:56:17.841842 INFO: [APUAPC] D10_APC_0: 0xffffffff
9932 00:56:17.845251 INFO: [APUAPC] D10_APC_1: 0xffffffff
9933 00:56:17.848732 INFO: [APUAPC] D10_APC_2: 0x3fffff
9934 00:56:17.852162 INFO: [APUAPC] D10_APC_3: 0x0
9935 00:56:17.855006 INFO: [APUAPC] D11_APC_0: 0xffffffff
9936 00:56:17.858986 INFO: [APUAPC] D11_APC_1: 0xffffffff
9937 00:56:17.865263 INFO: [APUAPC] D11_APC_2: 0x3fffff
9938 00:56:17.865343 INFO: [APUAPC] D11_APC_3: 0x0
9939 00:56:17.868496 INFO: [APUAPC] D12_APC_0: 0xffffffff
9940 00:56:17.875333 INFO: [APUAPC] D12_APC_1: 0xffffffff
9941 00:56:17.878598 INFO: [APUAPC] D12_APC_2: 0x3fffff
9942 00:56:17.878724 INFO: [APUAPC] D12_APC_3: 0x0
9943 00:56:17.882083 INFO: [APUAPC] D13_APC_0: 0xffffffff
9944 00:56:17.888726 INFO: [APUAPC] D13_APC_1: 0xffffffff
9945 00:56:17.891921 INFO: [APUAPC] D13_APC_2: 0x3fffff
9946 00:56:17.892003 INFO: [APUAPC] D13_APC_3: 0x0
9947 00:56:17.895056 INFO: [APUAPC] D14_APC_0: 0xffffffff
9948 00:56:17.902174 INFO: [APUAPC] D14_APC_1: 0xffffffff
9949 00:56:17.905476 INFO: [APUAPC] D14_APC_2: 0x3fffff
9950 00:56:17.905564 INFO: [APUAPC] D14_APC_3: 0x0
9951 00:56:17.908875 INFO: [APUAPC] D15_APC_0: 0xffffffff
9952 00:56:17.915001 INFO: [APUAPC] D15_APC_1: 0xffffffff
9953 00:56:17.918436 INFO: [APUAPC] D15_APC_2: 0x3fffff
9954 00:56:17.918515 INFO: [APUAPC] D15_APC_3: 0x0
9955 00:56:17.921928 INFO: [APUAPC] APC_CON: 0x4
9956 00:56:17.925359 INFO: [NOCDAPC] D0_APC_0: 0x0
9957 00:56:17.928681 INFO: [NOCDAPC] D0_APC_1: 0x0
9958 00:56:17.932127 INFO: [NOCDAPC] D1_APC_0: 0x0
9959 00:56:17.935015 INFO: [NOCDAPC] D1_APC_1: 0xfff
9960 00:56:17.938261 INFO: [NOCDAPC] D2_APC_0: 0x0
9961 00:56:17.942026 INFO: [NOCDAPC] D2_APC_1: 0xfff
9962 00:56:17.945265 INFO: [NOCDAPC] D3_APC_0: 0x0
9963 00:56:17.945357 INFO: [NOCDAPC] D3_APC_1: 0xfff
9964 00:56:17.948415 INFO: [NOCDAPC] D4_APC_0: 0x0
9965 00:56:17.951701 INFO: [NOCDAPC] D4_APC_1: 0xfff
9966 00:56:17.955072 INFO: [NOCDAPC] D5_APC_0: 0x0
9967 00:56:17.958556 INFO: [NOCDAPC] D5_APC_1: 0xfff
9968 00:56:17.962064 INFO: [NOCDAPC] D6_APC_0: 0x0
9969 00:56:17.964723 INFO: [NOCDAPC] D6_APC_1: 0xfff
9970 00:56:17.968692 INFO: [NOCDAPC] D7_APC_0: 0x0
9971 00:56:17.971410 INFO: [NOCDAPC] D7_APC_1: 0xfff
9972 00:56:17.974814 INFO: [NOCDAPC] D8_APC_0: 0x0
9973 00:56:17.978136 INFO: [NOCDAPC] D8_APC_1: 0xfff
9974 00:56:17.978228 INFO: [NOCDAPC] D9_APC_0: 0x0
9975 00:56:17.981467 INFO: [NOCDAPC] D9_APC_1: 0xfff
9976 00:56:17.985238 INFO: [NOCDAPC] D10_APC_0: 0x0
9977 00:56:17.988330 INFO: [NOCDAPC] D10_APC_1: 0xfff
9978 00:56:17.991938 INFO: [NOCDAPC] D11_APC_0: 0x0
9979 00:56:17.995412 INFO: [NOCDAPC] D11_APC_1: 0xfff
9980 00:56:17.998216 INFO: [NOCDAPC] D12_APC_0: 0x0
9981 00:56:18.001819 INFO: [NOCDAPC] D12_APC_1: 0xfff
9982 00:56:18.005233 INFO: [NOCDAPC] D13_APC_0: 0x0
9983 00:56:18.008454 INFO: [NOCDAPC] D13_APC_1: 0xfff
9984 00:56:18.011548 INFO: [NOCDAPC] D14_APC_0: 0x0
9985 00:56:18.015126 INFO: [NOCDAPC] D14_APC_1: 0xfff
9986 00:56:18.018574 INFO: [NOCDAPC] D15_APC_0: 0x0
9987 00:56:18.021708 INFO: [NOCDAPC] D15_APC_1: 0xfff
9988 00:56:18.021836 INFO: [NOCDAPC] APC_CON: 0x4
9989 00:56:18.024967 INFO: [APUAPC] set_apusys_apc done
9990 00:56:18.028580 INFO: [DEVAPC] devapc_init done
9991 00:56:18.035245 INFO: GICv3 without legacy support detected.
9992 00:56:18.038579 INFO: ARM GICv3 driver initialized in EL3
9993 00:56:18.042020 INFO: Maximum SPI INTID supported: 639
9994 00:56:18.045207 INFO: BL31: Initializing runtime services
9995 00:56:18.052001 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9996 00:56:18.055337 INFO: SPM: enable CPC mode
9997 00:56:18.058379 INFO: mcdi ready for mcusys-off-idle and system suspend
9998 00:56:18.064754 INFO: BL31: Preparing for EL3 exit to normal world
9999 00:56:18.068253 INFO: Entry point address = 0x80000000
10000 00:56:18.068340 INFO: SPSR = 0x8
10001 00:56:18.075198
10002 00:56:18.075283
10003 00:56:18.075344
10004 00:56:18.077972 Starting depthcharge on Spherion...
10005 00:56:18.078049
10006 00:56:18.078108 Wipe memory regions:
10007 00:56:18.078162
10008 00:56:18.078803 end: 2.2.3 depthcharge-start (duration 00:00:31) [common]
10009 00:56:18.078907 start: 2.2.4 bootloader-commands (timeout 00:04:20) [common]
10010 00:56:18.078983 Setting prompt string to ['asurada:']
10011 00:56:18.079055 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:20)
10012 00:56:18.081351 [0x00000040000000, 0x00000054600000)
10013 00:56:18.204321
10014 00:56:18.204481 [0x00000054660000, 0x00000080000000)
10015 00:56:18.464474
10016 00:56:18.464605 [0x000000821a7280, 0x000000ffe64000)
10017 00:56:19.209532
10018 00:56:19.209704 [0x00000100000000, 0x00000240000000)
10019 00:56:21.099987
10020 00:56:21.103119 Initializing XHCI USB controller at 0x11200000.
10021 00:56:22.142067
10022 00:56:22.145308 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10023 00:56:22.145408
10024 00:56:22.145468
10025 00:56:22.145737 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10027 00:56:22.246058 asurada: tftpboot 192.168.201.1 14368569/tftp-deploy-07bfviip/kernel/image.itb 14368569/tftp-deploy-07bfviip/kernel/cmdline
10028 00:56:22.246329 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10029 00:56:22.246451 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:16)
10030 00:56:22.250457 tftpboot 192.168.201.1 14368569/tftp-deploy-07bfviip/kernel/image.itp-deploy-07bfviip/kernel/cmdline
10031 00:56:22.250539
10032 00:56:22.250600 Waiting for link
10033 00:56:22.408959
10034 00:56:22.409108 R8152: Initializing
10035 00:56:22.409207
10036 00:56:22.411697 Version 9 (ocp_data = 6010)
10037 00:56:22.411768
10038 00:56:22.415188 R8152: Done initializing
10039 00:56:22.415260
10040 00:56:22.415324 Adding net device
10041 00:56:24.363530
10042 00:56:24.363664 done.
10043 00:56:24.363733
10044 00:56:24.363795 MAC: 00:e0:4c:78:7a:aa
10045 00:56:24.363851
10046 00:56:24.366921 Sending DHCP discover... done.
10047 00:56:24.367000
10048 00:56:24.370054 Waiting for reply... done.
10049 00:56:24.370128
10050 00:56:24.380604 Sending DHCP request... done.
10051 00:56:24.380686
10052 00:56:24.409472 Waiting for reply... done.
10053 00:56:24.409586
10054 00:56:24.409653 My ip is 192.168.201.12
10055 00:56:24.409728
10056 00:56:24.412858 The DHCP server ip is 192.168.201.1
10057 00:56:24.412935
10058 00:56:24.419667 TFTP server IP predefined by user: 192.168.201.1
10059 00:56:24.419743
10060 00:56:24.426277 Bootfile predefined by user: 14368569/tftp-deploy-07bfviip/kernel/image.itb
10061 00:56:24.426363
10062 00:56:24.429605 Sending tftp read request... done.
10063 00:56:24.429688
10064 00:56:24.433200 Waiting for the transfer...
10065 00:56:24.433276
10066 00:56:24.679993 00000000 ################################################################
10067 00:56:24.680147
10068 00:56:24.933088 00080000 ################################################################
10069 00:56:24.933218
10070 00:56:25.179756 00100000 ################################################################
10071 00:56:25.179901
10072 00:56:25.429448 00180000 ################################################################
10073 00:56:25.429605
10074 00:56:25.677587 00200000 ################################################################
10075 00:56:25.677737
10076 00:56:25.931378 00280000 ################################################################
10077 00:56:25.931502
10078 00:56:26.177482 00300000 ################################################################
10079 00:56:26.177617
10080 00:56:26.426679 00380000 ################################################################
10081 00:56:26.426827
10082 00:56:26.677679 00400000 ################################################################
10083 00:56:26.677802
10084 00:56:26.925661 00480000 ################################################################
10085 00:56:26.925795
10086 00:56:27.179648 00500000 ################################################################
10087 00:56:27.179769
10088 00:56:27.446324 00580000 ################################################################
10089 00:56:27.446470
10090 00:56:27.710501 00600000 ################################################################
10091 00:56:27.710622
10092 00:56:27.978820 00680000 ################################################################
10093 00:56:27.978933
10094 00:56:28.255179 00700000 ################################################################
10095 00:56:28.255316
10096 00:56:28.523493 00780000 ################################################################
10097 00:56:28.523608
10098 00:56:28.781460 00800000 ################################################################
10099 00:56:28.781609
10100 00:56:29.031258 00880000 ################################################################
10101 00:56:29.031383
10102 00:56:29.290944 00900000 ################################################################
10103 00:56:29.291053
10104 00:56:29.549031 00980000 ################################################################
10105 00:56:29.549146
10106 00:56:29.819565 00a00000 ################################################################
10107 00:56:29.819709
10108 00:56:30.080184 00a80000 ################################################################
10109 00:56:30.080299
10110 00:56:30.329600 00b00000 ################################################################
10111 00:56:30.329733
10112 00:56:30.578809 00b80000 ################################################################
10113 00:56:30.578937
10114 00:56:30.835189 00c00000 ################################################################
10115 00:56:30.835303
10116 00:56:31.089718 00c80000 ################################################################
10117 00:56:31.089833
10118 00:56:31.347125 00d00000 ################################################################
10119 00:56:31.347261
10120 00:56:31.608095 00d80000 ################################################################
10121 00:56:31.608230
10122 00:56:31.883167 00e00000 ################################################################
10123 00:56:31.883281
10124 00:56:32.135731 00e80000 ################################################################
10125 00:56:32.135866
10126 00:56:32.394176 00f00000 ################################################################
10127 00:56:32.394304
10128 00:56:32.644564 00f80000 ################################################################
10129 00:56:32.644687
10130 00:56:32.894492 01000000 ################################################################
10131 00:56:32.894611
10132 00:56:33.148521 01080000 ################################################################
10133 00:56:33.148695
10134 00:56:33.403696 01100000 ################################################################
10135 00:56:33.403841
10136 00:56:33.651001 01180000 ################################################################
10137 00:56:33.651168
10138 00:56:33.904867 01200000 ################################################################
10139 00:56:33.905033
10140 00:56:34.163702 01280000 ################################################################
10141 00:56:34.163847
10142 00:56:34.417473 01300000 ################################################################
10143 00:56:34.417622
10144 00:56:34.675818 01380000 ################################################################
10145 00:56:34.675939
10146 00:56:34.928052 01400000 ################################################################
10147 00:56:34.928194
10148 00:56:35.186452 01480000 ################################################################
10149 00:56:35.186572
10150 00:56:35.451260 01500000 ################################################################
10151 00:56:35.451395
10152 00:56:35.703088 01580000 ################################################################
10153 00:56:35.703207
10154 00:56:35.963005 01600000 ################################################################
10155 00:56:35.963133
10156 00:56:36.214812 01680000 ################################################################
10157 00:56:36.214929
10158 00:56:36.475923 01700000 ################################################################
10159 00:56:36.476040
10160 00:56:36.729826 01780000 ################################################################
10161 00:56:36.729943
10162 00:56:36.991555 01800000 ################################################################
10163 00:56:36.991701
10164 00:56:37.245132 01880000 ################################################################
10165 00:56:37.245244
10166 00:56:37.512090 01900000 ################################################################
10167 00:56:37.512218
10168 00:56:37.768925 01980000 ################################################################
10169 00:56:37.769045
10170 00:56:38.021425 01a00000 ################################################################
10171 00:56:38.021607
10172 00:56:38.272421 01a80000 ################################################################
10173 00:56:38.272558
10174 00:56:38.520870 01b00000 ################################################################
10175 00:56:38.520993
10176 00:56:38.772333 01b80000 ################################################################
10177 00:56:38.772483
10178 00:56:39.032488 01c00000 ################################################################
10179 00:56:39.032611
10180 00:56:39.306941 01c80000 ################################################################
10181 00:56:39.307056
10182 00:56:39.574631 01d00000 ################################################################
10183 00:56:39.574743
10184 00:56:39.835098 01d80000 ################################################################
10185 00:56:39.835219
10186 00:56:40.094880 01e00000 ################################################################
10187 00:56:40.094989
10188 00:56:40.376743 01e80000 ################################################################
10189 00:56:40.376891
10190 00:56:40.649176 01f00000 ################################################################
10191 00:56:40.649300
10192 00:56:40.923922 01f80000 ################################################################
10193 00:56:40.924148
10194 00:56:41.212059 02000000 ################################################################
10195 00:56:41.212173
10196 00:56:41.473193 02080000 ################################################################
10197 00:56:41.473329
10198 00:56:41.720086 02100000 ################################################################
10199 00:56:41.720201
10200 00:56:41.970367 02180000 ################################################################
10201 00:56:41.970480
10202 00:56:42.222448 02200000 ################################################################
10203 00:56:42.222583
10204 00:56:42.476608 02280000 ################################################################
10205 00:56:42.476746
10206 00:56:42.741569 02300000 ################################################################
10207 00:56:42.741680
10208 00:56:43.002500 02380000 ################################################################
10209 00:56:43.002634
10210 00:56:43.262356 02400000 ################################################################
10211 00:56:43.262473
10212 00:56:43.531389 02480000 ################################################################
10213 00:56:43.531508
10214 00:56:43.807412 02500000 ################################################################
10215 00:56:43.807524
10216 00:56:44.067621 02580000 ################################################################
10217 00:56:44.067765
10218 00:56:44.321514 02600000 ################################################################
10219 00:56:44.321650
10220 00:56:44.569148 02680000 ################################################################
10221 00:56:44.569266
10222 00:56:44.855194 02700000 ################################################################
10223 00:56:44.855318
10224 00:56:45.124829 02780000 ################################################################
10225 00:56:45.124957
10226 00:56:45.401658 02800000 ################################################################
10227 00:56:45.401778
10228 00:56:45.674172 02880000 ################################################################
10229 00:56:45.674315
10230 00:56:45.920146 02900000 ################################################################
10231 00:56:45.920258
10232 00:56:46.192436 02980000 ################################################################
10233 00:56:46.192580
10234 00:56:46.443147 02a00000 ################################################################
10235 00:56:46.443262
10236 00:56:46.690910 02a80000 ################################################################
10237 00:56:46.691025
10238 00:56:46.940239 02b00000 ################################################################
10239 00:56:46.940358
10240 00:56:47.195178 02b80000 ################################################################
10241 00:56:47.195287
10242 00:56:47.450675 02c00000 ################################################################
10243 00:56:47.450807
10244 00:56:47.726028 02c80000 ################################################################
10245 00:56:47.726137
10246 00:56:48.023703 02d00000 ################################################################
10247 00:56:48.023810
10248 00:56:48.310132 02d80000 ################################################################
10249 00:56:48.310245
10250 00:56:48.573365 02e00000 ################################################################
10251 00:56:48.573476
10252 00:56:48.835470 02e80000 ################################################################
10253 00:56:48.835585
10254 00:56:49.098298 02f00000 ################################################################
10255 00:56:49.098409
10256 00:56:49.347597 02f80000 ################################################################
10257 00:56:49.347712
10258 00:56:49.594015 03000000 ################################################################
10259 00:56:49.594129
10260 00:56:49.828159 03080000 ################################################################
10261 00:56:49.828271
10262 00:56:50.098973 03100000 ################################################################
10263 00:56:50.099110
10264 00:56:50.379888 03180000 ################################################################
10265 00:56:50.380001
10266 00:56:50.646616 03200000 ################################################################
10267 00:56:50.646749
10268 00:56:50.901453 03280000 ################################################################
10269 00:56:50.901608
10270 00:56:51.156750 03300000 ################################################################
10271 00:56:51.156859
10272 00:56:51.348681 03380000 ############################################### done.
10273 00:56:51.348794
10274 00:56:51.351954 The bootfile was 54385078 bytes long.
10275 00:56:51.352057
10276 00:56:51.354702 Sending tftp read request... done.
10277 00:56:51.354800
10278 00:56:51.354901 Waiting for the transfer...
10279 00:56:51.354984
10280 00:56:51.358480 00000000 # done.
10281 00:56:51.358558
10282 00:56:51.364834 Command line loaded dynamically from TFTP file: 14368569/tftp-deploy-07bfviip/kernel/cmdline
10283 00:56:51.364929
10284 00:56:51.378456 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10285 00:56:51.378556
10286 00:56:51.381502 Loading FIT.
10287 00:56:51.381648
10288 00:56:51.384790 Image ramdisk-1 has 41210746 bytes.
10289 00:56:51.384926
10290 00:56:51.385050 Image fdt-1 has 47258 bytes.
10291 00:56:51.385132
10292 00:56:51.388562 Image kernel-1 has 13125045 bytes.
10293 00:56:51.388674
10294 00:56:51.398465 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10295 00:56:51.398610
10296 00:56:51.415397 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10297 00:56:51.415678
10298 00:56:51.422079 Choosing best match conf-1 for compat google,spherion-rev2.
10299 00:56:51.425634
10300 00:56:51.430510 Connected to device vid:did:rid of 1ae0:0028:00
10301 00:56:51.437851
10302 00:56:51.441430 tpm_get_response: command 0x17b, return code 0x0
10303 00:56:51.441693
10304 00:56:51.448145 ec_init: CrosEC protocol v3 supported (256, 248)
10305 00:56:51.448337
10306 00:56:51.451710 tpm_cleanup: add release locality here.
10307 00:56:51.451947
10308 00:56:51.454698 Shutting down all USB controllers.
10309 00:56:51.454948
10310 00:56:51.458418 Removing current net device
10311 00:56:51.458647
10312 00:56:51.461243 Exiting depthcharge with code 4 at timestamp: 62632434
10313 00:56:51.461497
10314 00:56:51.464568 LZMA decompressing kernel-1 to 0x821a6718
10315 00:56:51.464751
10316 00:56:51.468467 LZMA decompressing kernel-1 to 0x40000000
10317 00:56:53.086129
10318 00:56:53.086568 jumping to kernel
10319 00:56:53.088469 end: 2.2.4 bootloader-commands (duration 00:00:35) [common]
10320 00:56:53.088959 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10321 00:56:53.089473 Setting prompt string to ['Linux version [0-9]']
10322 00:56:53.090047 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10323 00:56:53.090429 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10324 00:56:53.168375
10325 00:56:53.171249 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10326 00:56:53.175057 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10327 00:56:53.175507 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10328 00:56:53.175839 Setting prompt string to []
10329 00:56:53.176198 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10330 00:56:53.176523 Using line separator: #'\n'#
10331 00:56:53.176853 No login prompt set.
10332 00:56:53.177159 Parsing kernel messages
10333 00:56:53.177420 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10334 00:56:53.177970 [login-action] Waiting for messages, (timeout 00:03:45)
10335 00:56:53.178284 Waiting using forced prompt support (timeout 00:01:52)
10336 00:56:53.194379 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j232339-arm64-gcc-10-defconfig-arm64-chromebook-6v4sp) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024
10337 00:56:53.197544 [ 0.000000] random: crng init done
10338 00:56:53.204522 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10339 00:56:53.207737 [ 0.000000] efi: UEFI not found.
10340 00:56:53.214621 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10341 00:56:53.221295 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10342 00:56:53.230971 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10343 00:56:53.241205 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10344 00:56:53.247469 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10345 00:56:53.254133 [ 0.000000] printk: bootconsole [mtk8250] enabled
10346 00:56:53.260577 [ 0.000000] NUMA: No NUMA configuration found
10347 00:56:53.267606 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10348 00:56:53.270940 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10349 00:56:53.274292 [ 0.000000] Zone ranges:
10350 00:56:53.280961 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10351 00:56:53.283948 [ 0.000000] DMA32 empty
10352 00:56:53.290807 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10353 00:56:53.294291 [ 0.000000] Movable zone start for each node
10354 00:56:53.296993 [ 0.000000] Early memory node ranges
10355 00:56:53.304242 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10356 00:56:53.310446 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10357 00:56:53.317599 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10358 00:56:53.320737 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10359 00:56:53.327226 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10360 00:56:53.333804 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10361 00:56:53.392383 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10362 00:56:53.399299 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10363 00:56:53.406200 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10364 00:56:53.408894 [ 0.000000] psci: probing for conduit method from DT.
10365 00:56:53.415464 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10366 00:56:53.419178 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10367 00:56:53.426153 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10368 00:56:53.429112 [ 0.000000] psci: SMC Calling Convention v1.2
10369 00:56:53.435579 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10370 00:56:53.439110 [ 0.000000] Detected VIPT I-cache on CPU0
10371 00:56:53.445129 [ 0.000000] CPU features: detected: GIC system register CPU interface
10372 00:56:53.451663 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10373 00:56:53.458520 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10374 00:56:53.465170 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10375 00:56:53.475271 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10376 00:56:53.481543 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10377 00:56:53.484877 [ 0.000000] alternatives: applying boot alternatives
10378 00:56:53.491505 [ 0.000000] Fallback order for Node 0: 0
10379 00:56:53.498112 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10380 00:56:53.501423 [ 0.000000] Policy zone: Normal
10381 00:56:53.515275 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10382 00:56:53.524844 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10383 00:56:53.535948 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10384 00:56:53.545715 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10385 00:56:53.552642 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10386 00:56:53.555820 <6>[ 0.000000] software IO TLB: area num 8.
10387 00:56:53.612228 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10388 00:56:53.761697 <6>[ 0.000000] Memory: 7923812K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 428956K reserved, 32768K cma-reserved)
10389 00:56:53.768064 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10390 00:56:53.774768 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10391 00:56:53.777826 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10392 00:56:53.784692 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10393 00:56:53.791536 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10394 00:56:53.794383 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10395 00:56:53.804786 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10396 00:56:53.811631 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10397 00:56:53.817477 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10398 00:56:53.824587 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10399 00:56:53.828084 <6>[ 0.000000] GICv3: 608 SPIs implemented
10400 00:56:53.831454 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10401 00:56:53.837798 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10402 00:56:53.841245 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10403 00:56:53.847265 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10404 00:56:53.860484 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10405 00:56:53.874330 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10406 00:56:53.880411 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10407 00:56:53.888283 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10408 00:56:53.901386 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10409 00:56:53.907898 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10410 00:56:53.914586 <6>[ 0.009184] Console: colour dummy device 80x25
10411 00:56:53.924810 <6>[ 0.013912] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10412 00:56:53.927980 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10413 00:56:53.934549 <6>[ 0.029218] LSM: Security Framework initializing
10414 00:56:53.941425 <6>[ 0.034157] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10415 00:56:53.951427 <6>[ 0.042020] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10416 00:56:53.958017 <6>[ 0.051500] cblist_init_generic: Setting adjustable number of callback queues.
10417 00:56:53.964535 <6>[ 0.058944] cblist_init_generic: Setting shift to 3 and lim to 1.
10418 00:56:53.974671 <6>[ 0.065285] cblist_init_generic: Setting adjustable number of callback queues.
10419 00:56:53.977961 <6>[ 0.072712] cblist_init_generic: Setting shift to 3 and lim to 1.
10420 00:56:53.984784 <6>[ 0.079149] rcu: Hierarchical SRCU implementation.
10421 00:56:53.991256 <6>[ 0.084165] rcu: Max phase no-delay instances is 1000.
10422 00:56:53.997928 <6>[ 0.091192] EFI services will not be available.
10423 00:56:54.001075 <6>[ 0.096144] smp: Bringing up secondary CPUs ...
10424 00:56:54.008934 <6>[ 0.101223] Detected VIPT I-cache on CPU1
10425 00:56:54.015731 <6>[ 0.101293] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10426 00:56:54.022101 <6>[ 0.101325] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10427 00:56:54.026101 <6>[ 0.101660] Detected VIPT I-cache on CPU2
10428 00:56:54.032665 <6>[ 0.101713] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10429 00:56:54.039401 <6>[ 0.101731] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10430 00:56:54.045643 <6>[ 0.101989] Detected VIPT I-cache on CPU3
10431 00:56:54.052249 <6>[ 0.102036] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10432 00:56:54.058881 <6>[ 0.102051] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10433 00:56:54.062481 <6>[ 0.102354] CPU features: detected: Spectre-v4
10434 00:56:54.068773 <6>[ 0.102360] CPU features: detected: Spectre-BHB
10435 00:56:54.072212 <6>[ 0.102365] Detected PIPT I-cache on CPU4
10436 00:56:54.078465 <6>[ 0.102424] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10437 00:56:54.085328 <6>[ 0.102441] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10438 00:56:54.091932 <6>[ 0.102736] Detected PIPT I-cache on CPU5
10439 00:56:54.098828 <6>[ 0.102799] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10440 00:56:54.105664 <6>[ 0.102814] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10441 00:56:54.108857 <6>[ 0.103099] Detected PIPT I-cache on CPU6
10442 00:56:54.114946 <6>[ 0.103163] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10443 00:56:54.121858 <6>[ 0.103179] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10444 00:56:54.128555 <6>[ 0.103480] Detected PIPT I-cache on CPU7
10445 00:56:54.135379 <6>[ 0.103546] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10446 00:56:54.141828 <6>[ 0.103562] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10447 00:56:54.145370 <6>[ 0.103611] smp: Brought up 1 node, 8 CPUs
10448 00:56:54.151619 <6>[ 0.244956] SMP: Total of 8 processors activated.
10449 00:56:54.154876 <6>[ 0.249907] CPU features: detected: 32-bit EL0 Support
10450 00:56:54.164838 <6>[ 0.255270] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10451 00:56:54.171599 <6>[ 0.264070] CPU features: detected: Common not Private translations
10452 00:56:54.175226 <6>[ 0.270546] CPU features: detected: CRC32 instructions
10453 00:56:54.181662 <6>[ 0.275898] CPU features: detected: RCpc load-acquire (LDAPR)
10454 00:56:54.188306 <6>[ 0.281858] CPU features: detected: LSE atomic instructions
10455 00:56:54.194895 <6>[ 0.287675] CPU features: detected: Privileged Access Never
10456 00:56:54.197775 <6>[ 0.293454] CPU features: detected: RAS Extension Support
10457 00:56:54.207985 <6>[ 0.299063] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10458 00:56:54.211251 <6>[ 0.306328] CPU: All CPU(s) started at EL2
10459 00:56:54.217441 <6>[ 0.310644] alternatives: applying system-wide alternatives
10460 00:56:54.226524 <6>[ 0.321522] devtmpfs: initialized
10461 00:56:54.238840 <6>[ 0.330476] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10462 00:56:54.249040 <6>[ 0.340435] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10463 00:56:54.252472 <6>[ 0.348148] pinctrl core: initialized pinctrl subsystem
10464 00:56:54.260075 <6>[ 0.354841] DMI not present or invalid.
10465 00:56:54.266798 <6>[ 0.359258] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10466 00:56:54.273094 <6>[ 0.366111] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10467 00:56:54.283300 <6>[ 0.373699] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10468 00:56:54.289918 <6>[ 0.381922] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10469 00:56:54.296965 <6>[ 0.390166] audit: initializing netlink subsys (disabled)
10470 00:56:54.303543 <5>[ 0.395860] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10471 00:56:54.309945 <6>[ 0.396589] thermal_sys: Registered thermal governor 'step_wise'
10472 00:56:54.316877 <6>[ 0.403824] thermal_sys: Registered thermal governor 'power_allocator'
10473 00:56:54.319978 <6>[ 0.410081] cpuidle: using governor menu
10474 00:56:54.326226 <6>[ 0.421048] NET: Registered PF_QIPCRTR protocol family
10475 00:56:54.333022 <6>[ 0.426521] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10476 00:56:54.339728 <6>[ 0.433629] ASID allocator initialised with 32768 entries
10477 00:56:54.346293 <6>[ 0.440219] Serial: AMBA PL011 UART driver
10478 00:56:54.354107 <4>[ 0.449053] Trying to register duplicate clock ID: 134
10479 00:56:54.412941 <6>[ 0.510818] KASLR enabled
10480 00:56:54.427451 <6>[ 0.518576] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10481 00:56:54.434134 <6>[ 0.525591] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10482 00:56:54.440821 <6>[ 0.532080] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10483 00:56:54.447177 <6>[ 0.539085] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10484 00:56:54.453869 <6>[ 0.545572] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10485 00:56:54.460578 <6>[ 0.552576] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10486 00:56:54.466619 <6>[ 0.559063] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10487 00:56:54.473849 <6>[ 0.566069] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10488 00:56:54.476914 <6>[ 0.573595] ACPI: Interpreter disabled.
10489 00:56:54.484992 <6>[ 0.580031] iommu: Default domain type: Translated
10490 00:56:54.492104 <6>[ 0.585144] iommu: DMA domain TLB invalidation policy: strict mode
10491 00:56:54.495248 <5>[ 0.591805] SCSI subsystem initialized
10492 00:56:54.501779 <6>[ 0.595973] usbcore: registered new interface driver usbfs
10493 00:56:54.508391 <6>[ 0.601705] usbcore: registered new interface driver hub
10494 00:56:54.511509 <6>[ 0.607259] usbcore: registered new device driver usb
10495 00:56:54.518528 <6>[ 0.613353] pps_core: LinuxPPS API ver. 1 registered
10496 00:56:54.528684 <6>[ 0.618546] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10497 00:56:54.532014 <6>[ 0.627892] PTP clock support registered
10498 00:56:54.535236 <6>[ 0.632135] EDAC MC: Ver: 3.0.0
10499 00:56:54.542443 <6>[ 0.637287] FPGA manager framework
10500 00:56:54.549165 <6>[ 0.640973] Advanced Linux Sound Architecture Driver Initialized.
10501 00:56:54.552409 <6>[ 0.647749] vgaarb: loaded
10502 00:56:54.558862 <6>[ 0.650903] clocksource: Switched to clocksource arch_sys_counter
10503 00:56:54.562148 <5>[ 0.657344] VFS: Disk quotas dquot_6.6.0
10504 00:56:54.568616 <6>[ 0.661530] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10505 00:56:54.572440 <6>[ 0.668722] pnp: PnP ACPI: disabled
10506 00:56:54.580575 <6>[ 0.675481] NET: Registered PF_INET protocol family
10507 00:56:54.590265 <6>[ 0.681078] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10508 00:56:54.602121 <6>[ 0.693417] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10509 00:56:54.611709 <6>[ 0.702229] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10510 00:56:54.618417 <6>[ 0.710203] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10511 00:56:54.627707 <6>[ 0.718910] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10512 00:56:54.634936 <6>[ 0.728659] TCP: Hash tables configured (established 65536 bind 65536)
10513 00:56:54.641617 <6>[ 0.735520] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10514 00:56:54.650948 <6>[ 0.742720] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10515 00:56:54.654286 <6>[ 0.750424] NET: Registered PF_UNIX/PF_LOCAL protocol family
10516 00:56:54.661568 <6>[ 0.756579] RPC: Registered named UNIX socket transport module.
10517 00:56:54.667961 <6>[ 0.762732] RPC: Registered udp transport module.
10518 00:56:54.671344 <6>[ 0.767665] RPC: Registered tcp transport module.
10519 00:56:54.677942 <6>[ 0.772598] RPC: Registered tcp NFSv4.1 backchannel transport module.
10520 00:56:54.684492 <6>[ 0.779263] PCI: CLS 0 bytes, default 64
10521 00:56:54.687746 <6>[ 0.783534] Unpacking initramfs...
10522 00:56:54.710876 <6>[ 0.803020] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10523 00:56:54.720943 <6>[ 0.811674] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10524 00:56:54.724356 <6>[ 0.820508] kvm [1]: IPA Size Limit: 40 bits
10525 00:56:54.731294 <6>[ 0.825036] kvm [1]: GICv3: no GICV resource entry
10526 00:56:54.734051 <6>[ 0.830057] kvm [1]: disabling GICv2 emulation
10527 00:56:54.740897 <6>[ 0.834745] kvm [1]: GIC system register CPU interface enabled
10528 00:56:54.744182 <6>[ 0.840902] kvm [1]: vgic interrupt IRQ18
10529 00:56:54.750756 <6>[ 0.845258] kvm [1]: VHE mode initialized successfully
10530 00:56:54.757425 <5>[ 0.851708] Initialise system trusted keyrings
10531 00:56:54.764319 <6>[ 0.856524] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10532 00:56:54.771507 <6>[ 0.866612] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10533 00:56:54.778035 <5>[ 0.873013] NFS: Registering the id_resolver key type
10534 00:56:54.781334 <5>[ 0.878320] Key type id_resolver registered
10535 00:56:54.788308 <5>[ 0.882738] Key type id_legacy registered
10536 00:56:54.794957 <6>[ 0.887022] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10537 00:56:54.801553 <6>[ 0.893946] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10538 00:56:54.808289 <6>[ 0.901679] 9p: Installing v9fs 9p2000 file system support
10539 00:56:54.844629 <5>[ 0.939655] Key type asymmetric registered
10540 00:56:54.847687 <5>[ 0.943992] Asymmetric key parser 'x509' registered
10541 00:56:54.857538 <6>[ 0.949152] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10542 00:56:54.860743 <6>[ 0.956767] io scheduler mq-deadline registered
10543 00:56:54.864257 <6>[ 0.961551] io scheduler kyber registered
10544 00:56:54.883325 <6>[ 0.978480] EINJ: ACPI disabled.
10545 00:56:54.916303 <4>[ 1.004494] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10546 00:56:54.925601 <4>[ 1.015122] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10547 00:56:54.940646 <6>[ 1.035952] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10548 00:56:54.948424 <6>[ 1.043965] printk: console [ttyS0] disabled
10549 00:56:54.976854 <6>[ 1.068597] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10550 00:56:54.983310 <6>[ 1.078080] printk: console [ttyS0] enabled
10551 00:56:54.986815 <6>[ 1.078080] printk: console [ttyS0] enabled
10552 00:56:54.993272 <6>[ 1.086975] printk: bootconsole [mtk8250] disabled
10553 00:56:54.996383 <6>[ 1.086975] printk: bootconsole [mtk8250] disabled
10554 00:56:55.003017 <6>[ 1.098214] SuperH (H)SCI(F) driver initialized
10555 00:56:55.006494 <6>[ 1.103499] msm_serial: driver initialized
10556 00:56:55.020771 <6>[ 1.112439] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10557 00:56:55.030316 <6>[ 1.120990] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10558 00:56:55.037013 <6>[ 1.129534] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10559 00:56:55.047072 <6>[ 1.138164] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10560 00:56:55.053724 <6>[ 1.146871] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10561 00:56:55.063462 <6>[ 1.155591] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10562 00:56:55.074014 <6>[ 1.164132] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10563 00:56:55.080586 <6>[ 1.172937] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10564 00:56:55.090419 <6>[ 1.181481] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10565 00:56:55.101957 <6>[ 1.197083] loop: module loaded
10566 00:56:55.108568 <6>[ 1.203082] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10567 00:56:55.130994 <4>[ 1.226478] mtk-pmic-keys: Failed to locate of_node [id: -1]
10568 00:56:55.138399 <6>[ 1.233386] megasas: 07.719.03.00-rc1
10569 00:56:55.147665 <6>[ 1.242922] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10570 00:56:55.155163 <6>[ 1.250306] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10571 00:56:55.172130 <6>[ 1.267121] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10572 00:56:55.228703 <6>[ 1.317185] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10573 00:56:56.406696 <6>[ 2.502270] Freeing initrd memory: 40240K
10574 00:56:56.418536 <6>[ 2.513807] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10575 00:56:56.429434 <6>[ 2.524761] tun: Universal TUN/TAP device driver, 1.6
10576 00:56:56.432566 <6>[ 2.530813] thunder_xcv, ver 1.0
10577 00:56:56.435831 <6>[ 2.534318] thunder_bgx, ver 1.0
10578 00:56:56.439116 <6>[ 2.537815] nicpf, ver 1.0
10579 00:56:56.450130 <6>[ 2.541829] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10580 00:56:56.453465 <6>[ 2.549306] hns3: Copyright (c) 2017 Huawei Corporation.
10581 00:56:56.456897 <6>[ 2.554904] hclge is initializing
10582 00:56:56.463559 <6>[ 2.558480] e1000: Intel(R) PRO/1000 Network Driver
10583 00:56:56.470014 <6>[ 2.563609] e1000: Copyright (c) 1999-2006 Intel Corporation.
10584 00:56:56.473254 <6>[ 2.569622] e1000e: Intel(R) PRO/1000 Network Driver
10585 00:56:56.479425 <6>[ 2.574837] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10586 00:56:56.485991 <6>[ 2.581025] igb: Intel(R) Gigabit Ethernet Network Driver
10587 00:56:56.492654 <6>[ 2.586675] igb: Copyright (c) 2007-2014 Intel Corporation.
10588 00:56:56.499776 <6>[ 2.592511] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10589 00:56:56.506519 <6>[ 2.599029] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10590 00:56:56.509688 <6>[ 2.605487] sky2: driver version 1.30
10591 00:56:56.516392 <6>[ 2.610411] usbcore: registered new device driver r8152-cfgselector
10592 00:56:56.522659 <6>[ 2.616946] usbcore: registered new interface driver r8152
10593 00:56:56.529442 <6>[ 2.622763] VFIO - User Level meta-driver version: 0.3
10594 00:56:56.536193 <6>[ 2.631003] usbcore: registered new interface driver usb-storage
10595 00:56:56.542816 <6>[ 2.637442] usbcore: registered new device driver onboard-usb-hub
10596 00:56:56.551058 <6>[ 2.646594] mt6397-rtc mt6359-rtc: registered as rtc0
10597 00:56:56.561123 <6>[ 2.652062] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-16T00:56:56 UTC (1718499416)
10598 00:56:56.564358 <6>[ 2.661619] i2c_dev: i2c /dev entries driver
10599 00:56:56.578096 <4>[ 2.673612] cpu cpu0: supply cpu not found, using dummy regulator
10600 00:56:56.585122 <4>[ 2.680046] cpu cpu1: supply cpu not found, using dummy regulator
10601 00:56:56.591360 <4>[ 2.686452] cpu cpu2: supply cpu not found, using dummy regulator
10602 00:56:56.597954 <4>[ 2.692849] cpu cpu3: supply cpu not found, using dummy regulator
10603 00:56:56.604591 <4>[ 2.699248] cpu cpu4: supply cpu not found, using dummy regulator
10604 00:56:56.611152 <4>[ 2.705663] cpu cpu5: supply cpu not found, using dummy regulator
10605 00:56:56.617817 <4>[ 2.712062] cpu cpu6: supply cpu not found, using dummy regulator
10606 00:56:56.624406 <4>[ 2.718462] cpu cpu7: supply cpu not found, using dummy regulator
10607 00:56:56.643789 <6>[ 2.739105] cpu cpu0: EM: created perf domain
10608 00:56:56.647035 <6>[ 2.744013] cpu cpu4: EM: created perf domain
10609 00:56:56.654393 <6>[ 2.749599] sdhci: Secure Digital Host Controller Interface driver
10610 00:56:56.661212 <6>[ 2.756032] sdhci: Copyright(c) Pierre Ossman
10611 00:56:56.667475 <6>[ 2.760981] Synopsys Designware Multimedia Card Interface Driver
10612 00:56:56.673935 <6>[ 2.767621] sdhci-pltfm: SDHCI platform and OF driver helper
10613 00:56:56.677492 <6>[ 2.767686] mmc0: CQHCI version 5.10
10614 00:56:56.684121 <6>[ 2.777819] ledtrig-cpu: registered to indicate activity on CPUs
10615 00:56:56.690608 <6>[ 2.784837] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10616 00:56:56.697330 <6>[ 2.791889] usbcore: registered new interface driver usbhid
10617 00:56:56.700578 <6>[ 2.797711] usbhid: USB HID core driver
10618 00:56:56.707155 <6>[ 2.801912] spi_master spi0: will run message pump with realtime priority
10619 00:56:56.750016 <6>[ 2.839031] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10620 00:56:56.768830 <6>[ 2.854059] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10621 00:56:56.775340 <6>[ 2.868751] cros-ec-spi spi0.0: Chrome EC device registered
10622 00:56:56.778930 <6>[ 2.868829] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16414
10623 00:56:56.789296 <6>[ 2.884745] mmc0: Command Queue Engine enabled
10624 00:56:56.796379 <6>[ 2.889496] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10625 00:56:56.803044 <6>[ 2.896991] mmcblk0: mmc0:0001 DA4128 116 GiB
10626 00:56:56.810636 <6>[ 2.905839] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10627 00:56:56.820682 <6>[ 2.910383] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10628 00:56:56.827142 <6>[ 2.913364] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10629 00:56:56.830463 <6>[ 2.922327] NET: Registered PF_PACKET protocol family
10630 00:56:56.837210 <6>[ 2.926987] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10631 00:56:56.840530 <6>[ 2.931671] 9pnet: Installing 9P2000 support
10632 00:56:56.847078 <6>[ 2.937676] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10633 00:56:56.853421 <5>[ 2.941362] Key type dns_resolver registered
10634 00:56:56.857133 <6>[ 2.952847] registered taskstats version 1
10635 00:56:56.860403 <5>[ 2.957214] Loading compiled-in X.509 certificates
10636 00:56:56.890305 <4>[ 2.979186] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10637 00:56:56.900401 <4>[ 2.989901] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10638 00:56:56.914135 <6>[ 3.009525] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10639 00:56:56.921170 <6>[ 3.016479] xhci-mtk 11200000.usb: xHCI Host Controller
10640 00:56:56.927924 <6>[ 3.022011] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10641 00:56:56.938195 <6>[ 3.029883] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10642 00:56:56.944185 <6>[ 3.039338] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10643 00:56:56.950898 <6>[ 3.045548] xhci-mtk 11200000.usb: xHCI Host Controller
10644 00:56:56.957649 <6>[ 3.051055] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10645 00:56:56.964569 <6>[ 3.058715] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10646 00:56:56.971161 <6>[ 3.066516] hub 1-0:1.0: USB hub found
10647 00:56:56.974425 <6>[ 3.070564] hub 1-0:1.0: 1 port detected
10648 00:56:56.984374 <6>[ 3.074862] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10649 00:56:56.987437 <6>[ 3.083581] hub 2-0:1.0: USB hub found
10650 00:56:56.990705 <6>[ 3.087602] hub 2-0:1.0: 1 port detected
10651 00:56:56.999146 <6>[ 3.094215] mtk-msdc 11f70000.mmc: Got CD GPIO
10652 00:56:57.011930 <6>[ 3.104104] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10653 00:56:57.022228 <6>[ 3.112479] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10654 00:56:57.029004 <6>[ 3.120825] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10655 00:56:57.038598 <6>[ 3.129163] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10656 00:56:57.045674 <6>[ 3.137502] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10657 00:56:57.055495 <6>[ 3.145841] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10658 00:56:57.062190 <6>[ 3.154185] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10659 00:56:57.071932 <6>[ 3.162524] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10660 00:56:57.078393 <6>[ 3.170863] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10661 00:56:57.088775 <6>[ 3.179206] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10662 00:56:57.095209 <6>[ 3.187545] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10663 00:56:57.104891 <6>[ 3.195895] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10664 00:56:57.111656 <6>[ 3.204233] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10665 00:56:57.122175 <6>[ 3.212570] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10666 00:56:57.128621 <6>[ 3.220908] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10667 00:56:57.135169 <6>[ 3.229615] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10668 00:56:57.141397 <6>[ 3.236764] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10669 00:56:57.148453 <6>[ 3.243584] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10670 00:56:57.158169 <6>[ 3.250350] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10671 00:56:57.164628 <6>[ 3.257322] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10672 00:56:57.171302 <6>[ 3.264190] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10673 00:56:57.181745 <6>[ 3.273323] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10674 00:56:57.191558 <6>[ 3.282442] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10675 00:56:57.200985 <6>[ 3.291738] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10676 00:56:57.211593 <6>[ 3.301206] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10677 00:56:57.217898 <6>[ 3.310673] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10678 00:56:57.227874 <6>[ 3.319792] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10679 00:56:57.238102 <6>[ 3.329258] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10680 00:56:57.247567 <6>[ 3.338378] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10681 00:56:57.257855 <6>[ 3.347678] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10682 00:56:57.267531 <6>[ 3.357838] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10683 00:56:57.277822 <6>[ 3.369892] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10684 00:56:57.398986 <6>[ 3.491256] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10685 00:56:57.553822 <6>[ 3.649231] hub 1-1:1.0: USB hub found
10686 00:56:57.556911 <6>[ 3.653763] hub 1-1:1.0: 4 ports detected
10687 00:56:57.568318 <6>[ 3.664038] hub 1-1:1.0: USB hub found
10688 00:56:57.571866 <6>[ 3.668342] hub 1-1:1.0: 4 ports detected
10689 00:56:57.679363 <6>[ 3.771559] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10690 00:56:57.706578 <6>[ 3.802019] hub 2-1:1.0: USB hub found
10691 00:56:57.709820 <6>[ 3.806599] hub 2-1:1.0: 3 ports detected
10692 00:56:57.722247 <6>[ 3.817480] hub 2-1:1.0: USB hub found
10693 00:56:57.725445 <6>[ 3.821868] hub 2-1:1.0: 3 ports detected
10694 00:56:57.891069 <6>[ 3.983220] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10695 00:56:58.023315 <6>[ 4.118734] hub 1-1.4:1.0: USB hub found
10696 00:56:58.026435 <6>[ 4.123459] hub 1-1.4:1.0: 2 ports detected
10697 00:56:58.038274 <6>[ 4.133656] hub 1-1.4:1.0: USB hub found
10698 00:56:58.041512 <6>[ 4.138178] hub 1-1.4:1.0: 2 ports detected
10699 00:56:58.111379 <6>[ 4.203311] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10700 00:56:58.219258 <6>[ 4.311862] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10701 00:56:58.254669 <4>[ 4.347207] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10702 00:56:58.264858 <4>[ 4.356369] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10703 00:56:58.304634 <6>[ 4.400502] r8152 2-1.3:1.0 eth0: v1.12.13
10704 00:56:58.350507 <6>[ 4.443046] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10705 00:56:58.542568 <6>[ 4.635025] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10706 00:56:59.950858 <6>[ 6.046808] r8152 2-1.3:1.0 eth0: carrier on
10707 00:57:02.447107 <5>[ 6.066956] Sending DHCP requests .., OK
10708 00:57:02.453577 <6>[ 8.547317] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10709 00:57:02.456984 <6>[ 8.555622] IP-Config: Complete:
10710 00:57:02.470429 <6>[ 8.559116] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10711 00:57:02.476927 <6>[ 8.569823] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10712 00:57:02.483524 <6>[ 8.578438] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10713 00:57:02.490166 <6>[ 8.578447] nameserver0=192.168.201.1
10714 00:57:02.493453 <6>[ 8.590571] clk: Disabling unused clocks
10715 00:57:02.496690 <6>[ 8.595969] ALSA device list:
10716 00:57:02.503200 <6>[ 8.599262] No soundcards found.
10717 00:57:02.511088 <6>[ 8.606853] Freeing unused kernel memory: 8512K
10718 00:57:02.514201 <6>[ 8.611854] Run /init as init process
10719 00:57:02.546961 <6>[ 8.643208] NET: Registered PF_INET6 protocol family
10720 00:57:02.554315 <6>[ 8.650020] Segment Routing with IPv6
10721 00:57:02.557024 <6>[ 8.653998] In-situ OAM (IOAM) with IPv6
10722 00:57:02.596915 <30>[ 8.666765] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10723 00:57:02.603769 <30>[ 8.699814] systemd[1]: Detected architecture arm64.
10724 00:57:02.603853
10725 00:57:02.610424 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10726 00:57:02.610498
10727 00:57:02.623099 <30>[ 8.719246] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10728 00:57:02.745898 <30>[ 8.838687] systemd[1]: Queued start job for default target graphical.target.
10729 00:57:02.792316 <30>[ 8.885102] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10730 00:57:02.799065 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10731 00:57:02.819120 <30>[ 8.911795] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10732 00:57:02.828900 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10733 00:57:02.847316 <30>[ 8.940183] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10734 00:57:02.857676 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10735 00:57:02.876088 <30>[ 8.968757] systemd[1]: Created slice user.slice - User and Session Slice.
10736 00:57:02.882572 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10737 00:57:02.906831 <30>[ 8.996001] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10738 00:57:02.916679 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10739 00:57:02.933968 <30>[ 9.023412] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10740 00:57:02.940454 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10741 00:57:02.968776 <30>[ 9.051704] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10742 00:57:02.978851 <30>[ 9.071607] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10743 00:57:02.985318 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10744 00:57:03.003009 <30>[ 9.095596] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10745 00:57:03.012989 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10746 00:57:03.030742 <30>[ 9.123725] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10747 00:57:03.040894 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10748 00:57:03.055285 <30>[ 9.151313] systemd[1]: Reached target paths.target - Path Units.
10749 00:57:03.065098 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10750 00:57:03.083029 <30>[ 9.175670] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10751 00:57:03.089836 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10752 00:57:03.102883 <30>[ 9.199194] systemd[1]: Reached target slices.target - Slice Units.
10753 00:57:03.113346 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10754 00:57:03.127054 <30>[ 9.223262] systemd[1]: Reached target swap.target - Swaps.
10755 00:57:03.133518 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10756 00:57:03.154490 <30>[ 9.247306] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10757 00:57:03.164500 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10758 00:57:03.183012 <30>[ 9.275664] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10759 00:57:03.192923 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10760 00:57:03.212892 <30>[ 9.305443] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10761 00:57:03.222309 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10762 00:57:03.239157 <30>[ 9.331931] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10763 00:57:03.248907 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10764 00:57:03.267130 <30>[ 9.359799] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10765 00:57:03.273663 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10766 00:57:03.291057 <30>[ 9.383863] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10767 00:57:03.300982 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10768 00:57:03.319633 <30>[ 9.412611] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10769 00:57:03.329782 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10770 00:57:03.346599 <30>[ 9.439644] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10771 00:57:03.356453 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10772 00:57:03.398236 <30>[ 9.491246] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10773 00:57:03.404825 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10774 00:57:03.426582 <30>[ 9.519304] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10775 00:57:03.432949 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10776 00:57:03.454769 <30>[ 9.547593] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10777 00:57:03.461484 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10778 00:57:03.489649 <30>[ 9.575628] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10779 00:57:03.518501 <30>[ 9.611495] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10780 00:57:03.528477 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10781 00:57:03.551735 <30>[ 9.644355] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10782 00:57:03.558343 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10783 00:57:03.583406 <30>[ 9.676484] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10784 00:57:03.597122 Starting [0;1;39mmodpr<6>[ 9.687529] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10785 00:57:03.600363 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10786 00:57:03.623427 <30>[ 9.716180] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10787 00:57:03.629717 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10788 00:57:03.656088 <30>[ 9.748489] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10789 00:57:03.665366 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10790 00:57:03.723007 <30>[ 9.815771] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10791 00:57:03.729471 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10792 00:57:03.759341 <30>[ 9.851927] systemd[1]: Starting systemd-journald.service - Journal Service...
10793 00:57:03.765846 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10794 00:57:03.784952 <30>[ 9.877837] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10795 00:57:03.791561 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10796 00:57:03.817004 <30>[ 9.906284] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10797 00:57:03.823459 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10798 00:57:03.846512 <30>[ 9.939122] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10799 00:57:03.856407 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10800 00:57:03.877401 <30>[ 9.970318] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10801 00:57:03.884043 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10802 00:57:03.907734 <30>[ 10.000415] systemd[1]: Started systemd-journald.service - Journal Service.
10803 00:57:03.914474 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10804 00:57:03.936853 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10805 00:57:03.955072 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10806 00:57:03.975118 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10807 00:57:03.995950 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10808 00:57:04.017113 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10809 00:57:04.037337 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10810 00:57:04.057567 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10811 00:57:04.078679 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10812 00:57:04.103585 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10813 00:57:04.124231 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10814 00:57:04.147838 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10815 00:57:04.168658 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10816 00:57:04.175551 See 'systemctl status systemd-remount-fs.service' for details.
10817 00:57:04.185260 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10818 00:57:04.209420 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10819 00:57:04.275546 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10820 00:57:04.296982 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10821 00:57:04.308607 <46>[ 10.401467] systemd-journald[191]: Received client request to flush runtime journal.
10822 00:57:04.320801 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10823 00:57:04.342256 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10824 00:57:04.367526 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10825 00:57:04.392569 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10826 00:57:04.416014 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10827 00:57:04.440017 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10828 00:57:04.459791 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10829 00:57:04.479459 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10830 00:57:04.530980 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10831 00:57:04.553897 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10832 00:57:04.570856 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10833 00:57:04.586658 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10834 00:57:04.631037 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10835 00:57:04.656382 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10836 00:57:04.681260 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10837 00:57:04.701535 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10838 00:57:04.754729 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10839 00:57:04.936231 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10840 00:57:04.964533 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10841 00:57:04.991906 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10842 00:57:05.045054 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10843 00:57:05.055732 <5>[ 11.148692] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10844 00:57:05.066764 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10845 00:57:05.076586 <6>[ 11.169051] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10846 00:57:05.092774 <6>[ 11.185748] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10847 00:57:05.099430 <5>[ 11.191518] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10848 00:57:05.105919 <6>[ 11.194214] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10849 00:57:05.116380 <5>[ 11.202504] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10850 00:57:05.125934 <4>[ 11.208724] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10851 00:57:05.132357 <4>[ 11.216950] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10852 00:57:05.142306 <6>[ 11.226379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10853 00:57:05.145962 <6>[ 11.235092] cfg80211: failed to load regulatory.db
10854 00:57:05.155856 <6>[ 11.242882] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10855 00:57:05.162440 <6>[ 11.243139] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10856 00:57:05.168988 <3>[ 11.243376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 00:57:05.179278 <3>[ 11.243386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10858 00:57:05.185530 <3>[ 11.243389] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10859 00:57:05.195958 <3>[ 11.244121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 00:57:05.202547 <3>[ 11.244131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 00:57:05.212577 <3>[ 11.244134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 00:57:05.219256 <3>[ 11.244140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10863 00:57:05.225852 <3>[ 11.244142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10864 00:57:05.235549 <3>[ 11.244167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10865 00:57:05.242097 <3>[ 11.244200] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10866 00:57:05.252535 <3>[ 11.244203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10867 00:57:05.259194 <3>[ 11.244206] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10868 00:57:05.268922 <3>[ 11.244232] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 00:57:05.275642 <3>[ 11.244234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10870 00:57:05.285422 <3>[ 11.244237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 00:57:05.291888 <3>[ 11.244239] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 00:57:05.298699 <3>[ 11.244242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 00:57:05.309120 <3>[ 11.244258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 00:57:05.315883 <6>[ 11.257475] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10875 00:57:05.321969 <6>[ 11.264025] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10876 00:57:05.332029 <6>[ 11.272031] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10877 00:57:05.339072 <6>[ 11.280071] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10878 00:57:05.348564 <6>[ 11.280076] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10879 00:57:05.355299 <6>[ 11.298605] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10880 00:57:05.365489 <6>[ 11.304416] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10881 00:57:05.371665 <6>[ 11.385616] remoteproc remoteproc0: scp is available
10882 00:57:05.378397 <4>[ 11.406379] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10883 00:57:05.382338 <6>[ 11.408854] mc: Linux media interface: v0.10
10884 00:57:05.388922 <6>[ 11.409620] remoteproc remoteproc0: powering up scp
10885 00:57:05.394972 <6>[ 11.414399] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10886 00:57:05.401544 <4>[ 11.417244] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10887 00:57:05.411982 <6>[ 11.424978] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10888 00:57:05.415353 <6>[ 11.425155] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10889 00:57:05.422090 <6>[ 11.449923] videodev: Linux video capture interface: v2.00
10890 00:57:05.432275 <4>[ 11.451362] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10891 00:57:05.435594 <4>[ 11.451362] Fallback method does not support PEC.
10892 00:57:05.445802 <6>[ 11.460402] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10893 00:57:05.452362 <6>[ 11.510815] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10894 00:57:05.462181 <6>[ 11.514140] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10895 00:57:05.468802 <6>[ 11.518220] pci_bus 0000:00: root bus resource [bus 00-ff]
10896 00:57:05.475080 <3>[ 11.528988] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 00:57:05.485115 <6>[ 11.537527] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10898 00:57:05.495160 <6>[ 11.537531] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10899 00:57:05.498479 <6>[ 11.537570] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10900 00:57:05.508613 <6>[ 11.551061] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10901 00:57:05.515594 <6>[ 11.551095] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10902 00:57:05.523343 <6>[ 11.551102] remoteproc remoteproc0: remote processor scp is now up
10903 00:57:05.530345 <6>[ 11.554518] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10904 00:57:05.539898 <6>[ 11.568089] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10905 00:57:05.543198 <6>[ 11.569332] pci 0000:00:00.0: supports D1 D2
10906 00:57:05.550094 <6>[ 11.602258] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10907 00:57:05.557205 <6>[ 11.602641] Bluetooth: Core ver 2.22
10908 00:57:05.560550 <6>[ 11.602799] NET: Registered PF_BLUETOOTH protocol family
10909 00:57:05.568195 <6>[ 11.602803] Bluetooth: HCI device and connection manager initialized
10910 00:57:05.571590 <6>[ 11.602865] Bluetooth: HCI socket layer initialized
10911 00:57:05.578609 <6>[ 11.602879] Bluetooth: L2CAP socket layer initialized
10912 00:57:05.582146 <6>[ 11.602900] Bluetooth: SCO socket layer initialized
10913 00:57:05.588867 <6>[ 11.608370] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10914 00:57:05.599094 <6>[ 11.609735] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10915 00:57:05.605766 <6>[ 11.620456] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10916 00:57:05.612341 <6>[ 11.623460] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10917 00:57:05.619298 <6>[ 11.624587] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10918 00:57:05.633032 <6>[ 11.625806] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10919 00:57:05.639403 <6>[ 11.625991] usbcore: registered new interface driver uvcvideo
10920 00:57:05.646138 <3>[ 11.636102] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 00:57:05.656358 <3>[ 11.636801] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10922 00:57:05.663631 <6>[ 11.640181] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10923 00:57:05.670058 <6>[ 11.653810] usbcore: registered new interface driver btusb
10924 00:57:05.676458 <6>[ 11.653880] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10925 00:57:05.686918 <4>[ 11.654561] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10926 00:57:05.694031 <3>[ 11.654573] Bluetooth: hci0: Failed to load firmware file (-2)
10927 00:57:05.697220 <3>[ 11.654577] Bluetooth: hci0: Failed to set up firmware (-2)
10928 00:57:05.707385 <4>[ 11.654582] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10929 00:57:05.717470 <6>[ 11.656804] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10930 00:57:05.724166 <3>[ 11.670260] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 00:57:05.735094 <3>[ 11.672638] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10932 00:57:05.741357 <6>[ 11.674099] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10933 00:57:05.744806 <6>[ 11.674226] pci 0000:01:00.0: supports D1 D2
10934 00:57:05.754596 <3>[ 11.687589] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 00:57:05.762019 <6>[ 11.691385] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10936 00:57:05.768815 <6>[ 11.703498] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10937 00:57:05.775329 <3>[ 11.728685] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 00:57:05.785904 <6>[ 11.733700] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10939 00:57:05.793155 <6>[ 11.733703] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10940 00:57:05.803038 <3>[ 11.764016] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 00:57:05.810081 <6>[ 11.764713] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10942 00:57:05.816763 <3>[ 11.793839] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 00:57:05.827256 <6>[ 11.799364] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10944 00:57:05.834473 <6>[ 11.799377] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10945 00:57:05.844425 <3>[ 11.832311] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 00:57:05.847623 <6>[ 11.834800] pci 0000:00:00.0: PCI bridge to [bus 01]
10947 00:57:05.857634 <6>[ 11.949690] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10948 00:57:05.863941 [[0;32m OK [<6>[ 11.958211] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10949 00:57:05.870631 0m] Finished [0<6>[ 11.966138] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10950 00:57:05.877415 ;1;39msystemd-up<6>[ 11.973853] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10951 00:57:05.884300 date-ut…cord System Boot/Shutdown in UTMP.
10952 00:57:05.903887 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10953 00:57:05.945859 <6>[ 12.039221] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10954 00:57:05.952712 <6>[ 12.046870] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10955 00:57:05.959141 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10956 00:57:05.976297 [[0;32m OK [0m] Reached target [0;1;39mblue<6>[ 12.073279] mt7921e 0000:01:00.0: ASIC revision: 79610010
10957 00:57:05.982958 tooth.target[0m - Bluetooth Support.
10958 00:57:05.996121 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10959 00:57:06.015749 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10960 00:57:06.074837 Starting [0;1;39msystemd-backlight…e<6>[ 12.168051] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10961 00:57:06.077910 <6>[ 12.168051]
10962 00:57:06.081505 ss of leds:white:kbd_backlight...
10963 00:57:06.098398 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10964 00:57:06.117465 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10965 00:57:06.137084 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10966 00:57:06.155557 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10967 00:57:06.171163 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10968 00:57:06.187418 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10969 00:57:06.206298 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10970 00:57:06.222508 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10971 00:57:06.266375 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10972 00:57:06.294875 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10973 00:57:06.316827 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10974 00:57:06.341375 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10975 00:57:06.357240 [[0;32m OK [<6>[ 12.447612] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10976 00:57:06.360677 0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10977 00:57:06.384276 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10978 00:57:06.403022 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10979 00:57:06.465271 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10980 00:57:06.485377 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10981 00:57:06.503051 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10982 00:57:06.519845 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10983 00:57:06.540344 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10984 00:57:06.558731 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10985 00:57:06.610273 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10986 00:57:06.649382 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10987 00:57:06.695646
10988 00:57:06.698898 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10989 00:57:06.698990
10990 00:57:06.702259 debian-bookworm-arm64 login: root (automatic login)
10991 00:57:06.702328
10992 00:57:06.713825 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Sun Jun 16 00:43:03 UTC 2024 aarch64
10993 00:57:06.713921
10994 00:57:06.720364 The programs included with the Debian GNU/Linux system are free software;
10995 00:57:06.727457 the exact distribution terms for each program are described in the
10996 00:57:06.730229 individual files in /usr/share/doc/*/copyright.
10997 00:57:06.730298
10998 00:57:06.737285 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10999 00:57:06.740282 permitted by applicable law.
11000 00:57:06.740647 Matched prompt #10: / #
11002 00:57:06.740828 Setting prompt string to ['/ #']
11003 00:57:06.740917 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11005 00:57:06.741092 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11006 00:57:06.741171 start: 2.2.6 expect-shell-connection (timeout 00:03:31) [common]
11007 00:57:06.741239 Setting prompt string to ['/ #']
11008 00:57:06.741295 Forcing a shell prompt, looking for ['/ #']
11010 00:57:06.791466 / #
11011 00:57:06.791626 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11012 00:57:06.791695 Waiting using forced prompt support (timeout 00:02:30)
11013 00:57:06.796089
11014 00:57:06.796368 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11015 00:57:06.796481 start: 2.2.7 export-device-env (timeout 00:03:31) [common]
11016 00:57:06.796595 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11017 00:57:06.796699 end: 2.2 depthcharge-retry (duration 00:01:29) [common]
11018 00:57:06.796812 end: 2 depthcharge-action (duration 00:01:29) [common]
11019 00:57:06.796920 start: 3 lava-test-retry (timeout 00:08:07) [common]
11020 00:57:06.797029 start: 3.1 lava-test-shell (timeout 00:08:07) [common]
11021 00:57:06.797120 Using namespace: common
11023 00:57:06.897433 / # #
11024 00:57:06.897671 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11025 00:57:06.902397 #
11026 00:57:06.902651 Using /lava-14368569
11028 00:57:07.002914 / # export SHELL=/bin/sh
11029 00:57:07.007794 export SHELL=/bin/sh
11031 00:57:07.108300 / # . /lava-14368569/environment
11032 00:57:07.113455 . /lava-14368569/environment
11034 00:57:07.213997 / # /lava-14368569/bin/lava-test-runner /lava-14368569/0
11035 00:57:07.214192 Test shell timeout: 10s (minimum of the action and connection timeout)
11036 00:57:07.219447 /lava-14368569/bin/lava-test-runner /lava-14368569/0
11037 00:57:07.230593 <6>[ 13.327063] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11038 00:57:07.245809 + export TESTRUN_ID=0_v4l2-compliance-uvc
11039 00:57:07.249310 + cd /lava-14368569/0/tests/0_v4l2-compliance-uvc
11040 00:57:07.249404 + cat uuid
11041 00:57:07.252277 + UUID=14368569_1.5.2.3.1
11042 00:57:07.252345 + set +x
11043 00:57:07.259103 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14368569_1.5.2.3.1>
11044 00:57:07.259375 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14368569_1.5.2.3.1
11045 00:57:07.259465 Starting test lava.0_v4l2-compliance-uvc (14368569_1.5.2.3.1)
11046 00:57:07.259547 Skipping test definition patterns.
11047 00:57:07.262330 + /usr/bin/v4l2-parser.sh -d uvcvideo
11048 00:57:07.268821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11049 00:57:07.268914 device: /dev/video0
11050 00:57:07.269164 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11052 00:57:13.693628 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11053 00:57:13.705353 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11054 00:57:13.714762
11055 00:57:13.729357 Compliance test for uvcvideo device /dev/video0:
11056 00:57:13.740543
11057 00:57:13.750854 Driver Info:
11058 00:57:13.761047 Driver name : uvcvideo
11059 00:57:13.776037 Card type : HD User Facing: HD User Facing
11060 00:57:13.787410 Bus info : usb-11200000.usb-1.4.1
11061 00:57:13.798989 Driver version : 6.1.92
11062 00:57:13.809322 Capabilities : 0x84a00001
11063 00:57:13.824541 Metadata Capture
11064 00:57:13.836165 Streaming
11065 00:57:13.845649 Extended Pix Format
11066 00:57:13.860734 Device Capabilities
11067 00:57:13.872850 Device Caps : 0x04200001
11068 00:57:13.890655 Streaming
11069 00:57:13.904196 Extended Pix Format
11070 00:57:13.915980 Media Driver Info:
11071 00:57:13.929051 Driver name : uvcvideo
11072 00:57:13.946720 Model : HD User Facing: HD User Facing
11073 00:57:13.955043 Serial : 200901010001
11074 00:57:13.969087 Bus info : usb-11200000.usb-1.4.1
11075 00:57:13.981170 Media version : 6.1.92
11076 00:57:13.993773 Hardware revision: 0x00009758 (38744)
11077 00:57:14.003976 Driver version : 6.1.92
11078 00:57:14.013650 Interface Info:
11079 00:57:14.034117 <LAVA_SIGNAL_TESTSET START Interface-Info>
11080 00:57:14.034553 ID : 0x03000002
11081 00:57:14.035117 Received signal: <TESTSET> START Interface-Info
11082 00:57:14.035462 Starting test_set Interface-Info
11083 00:57:14.044462 Type : V4L Video
11084 00:57:14.054479 Entity Info:
11085 00:57:14.060614 <LAVA_SIGNAL_TESTSET STOP>
11086 00:57:14.061245 Received signal: <TESTSET> STOP
11087 00:57:14.061615 Closing test_set Interface-Info
11088 00:57:14.070233 <LAVA_SIGNAL_TESTSET START Entity-Info>
11089 00:57:14.071090 Received signal: <TESTSET> START Entity-Info
11090 00:57:14.071554 Starting test_set Entity-Info
11091 00:57:14.073190 ID : 0x00000001 (1)
11092 00:57:14.087176 Name : HD User Facing: HD User Facing
11093 00:57:14.096542 Function : V4L2 I/O
11094 00:57:14.110140 Flags : default
11095 00:57:14.122645 Pad 0x01000007 : 0: Sink
11096 00:57:14.144679 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11097 00:57:14.149125
11098 00:57:14.160155 Required ioctls:
11099 00:57:14.169252 <LAVA_SIGNAL_TESTSET STOP>
11100 00:57:14.170009 Received signal: <TESTSET> STOP
11101 00:57:14.170406 Closing test_set Entity-Info
11102 00:57:14.180506 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11103 00:57:14.181202 Received signal: <TESTSET> START Required-ioctls
11104 00:57:14.181531 Starting test_set Required-ioctls
11105 00:57:14.183927 test MC information (see 'Media Driver Info' above): OK
11106 00:57:14.207979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11107 00:57:14.208639 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11109 00:57:14.211356 test VIDIOC_QUERYCAP: OK
11110 00:57:14.229054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11111 00:57:14.229724 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11113 00:57:14.232349 test invalid ioctls: OK
11114 00:57:14.253414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11115 00:57:14.253958
11116 00:57:14.254568 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11118 00:57:14.270105 Allow for multiple opens:
11119 00:57:14.278011 <LAVA_SIGNAL_TESTSET STOP>
11120 00:57:14.278679 Received signal: <TESTSET> STOP
11121 00:57:14.278998 Closing test_set Required-ioctls
11122 00:57:14.286960 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11123 00:57:14.287818 Received signal: <TESTSET> START Allow-for-multiple-opens
11124 00:57:14.288166 Starting test_set Allow-for-multiple-opens
11125 00:57:14.290210 test second /dev/video0 open: OK
11126 00:57:14.312166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11127 00:57:14.312794 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11129 00:57:14.315927 test VIDIOC_QUERYCAP: OK
11130 00:57:14.337880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11131 00:57:14.338519 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11133 00:57:14.340861 test VIDIOC_G/S_PRIORITY: OK
11134 00:57:14.364382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11135 00:57:14.365054 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11137 00:57:14.367441 test for unlimited opens: OK
11138 00:57:14.388832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11139 00:57:14.389268
11140 00:57:14.389906 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11142 00:57:14.399375 Debug ioctls:
11143 00:57:14.410026 <LAVA_SIGNAL_TESTSET STOP>
11144 00:57:14.410664 Received signal: <TESTSET> STOP
11145 00:57:14.411010 Closing test_set Allow-for-multiple-opens
11146 00:57:14.420100 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11147 00:57:14.420828 Received signal: <TESTSET> START Debug-ioctls
11148 00:57:14.421185 Starting test_set Debug-ioctls
11149 00:57:14.423157 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11150 00:57:14.449661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11151 00:57:14.450373 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11153 00:57:14.456710 test VIDIOC_LOG_STATUS: OK (Not Supported)
11154 00:57:14.479206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11155 00:57:14.479652
11156 00:57:14.480290 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11158 00:57:14.492580 Input ioctls:
11159 00:57:14.500420 <LAVA_SIGNAL_TESTSET STOP>
11160 00:57:14.501150 Received signal: <TESTSET> STOP
11161 00:57:14.501488 Closing test_set Debug-ioctls
11162 00:57:14.512733 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11163 00:57:14.513463 Received signal: <TESTSET> START Input-ioctls
11164 00:57:14.513821 Starting test_set Input-ioctls
11165 00:57:14.515833 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11166 00:57:14.543968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11167 00:57:14.544643 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11169 00:57:14.547582 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11170 00:57:14.565825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11171 00:57:14.566492 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11173 00:57:14.572719 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11174 00:57:14.591869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11175 00:57:14.592579 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11177 00:57:14.598204 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11178 00:57:14.616904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11179 00:57:14.617596 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11181 00:57:14.620332 test VIDIOC_G/S/ENUMINPUT: OK
11182 00:57:14.645913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11183 00:57:14.646585 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11185 00:57:14.649215 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11186 00:57:14.672017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11187 00:57:14.672668 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11189 00:57:14.675318 Inputs: 1 Audio Inputs: 0 Tuners: 0
11190 00:57:14.685003
11191 00:57:14.705354 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11192 00:57:14.726650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11193 00:57:14.727281 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11195 00:57:14.733075 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11196 00:57:14.751831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11197 00:57:14.752468 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11199 00:57:14.755097 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11200 00:57:14.777336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11201 00:57:14.778073 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11203 00:57:14.783872 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11204 00:57:14.802572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11205 00:57:14.803201 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11207 00:57:14.808881 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11208 00:57:14.834579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11209 00:57:14.835118
11210 00:57:14.835742 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11212 00:57:14.854105 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11213 00:57:14.876037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11214 00:57:14.876736 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11216 00:57:14.882484 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11217 00:57:14.903705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11218 00:57:14.904404 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11220 00:57:14.906881 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11221 00:57:14.927424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11222 00:57:14.928124 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11224 00:57:14.930426 test VIDIOC_G/S_EDID: OK (Not Supported)
11225 00:57:14.950994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11226 00:57:14.951429
11227 00:57:14.951965 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11229 00:57:14.962901 Control ioctls (Input 0):
11230 00:57:14.968984 <LAVA_SIGNAL_TESTSET STOP>
11231 00:57:14.969620 Received signal: <TESTSET> STOP
11232 00:57:14.969931 Closing test_set Input-ioctls
11233 00:57:14.979182 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11234 00:57:14.979895 Received signal: <TESTSET> START Control-ioctls-Input-0
11235 00:57:14.980285 Starting test_set Control-ioctls-Input-0
11236 00:57:14.982477 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11237 00:57:15.007772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11238 00:57:15.008317 test VIDIOC_QUERYCTRL: OK
11239 00:57:15.008871 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11241 00:57:15.029431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11242 00:57:15.030132 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11244 00:57:15.032889 test VIDIOC_G/S_CTRL: OK
11245 00:57:15.054449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11246 00:57:15.055362 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11248 00:57:15.057084 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11249 00:57:15.079252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11250 00:57:15.079969 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11252 00:57:15.085763 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11253 00:57:15.107930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11254 00:57:15.108735 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11256 00:57:15.111045 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11257 00:57:15.128923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11258 00:57:15.129654 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11260 00:57:15.132012 Standard Controls: 16 Private Controls: 0
11261 00:57:15.139186
11262 00:57:15.150957 Format ioctls (Input 0):
11263 00:57:15.157901 <LAVA_SIGNAL_TESTSET STOP>
11264 00:57:15.158590 Received signal: <TESTSET> STOP
11265 00:57:15.158905 Closing test_set Control-ioctls-Input-0
11266 00:57:15.167808 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11267 00:57:15.168430 Received signal: <TESTSET> START Format-ioctls-Input-0
11268 00:57:15.168747 Starting test_set Format-ioctls-Input-0
11269 00:57:15.171193 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11270 00:57:15.200355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11271 00:57:15.201153 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11273 00:57:15.203501 test VIDIOC_G/S_PARM: OK
11274 00:57:15.220781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11275 00:57:15.221541 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11277 00:57:15.224077 test VIDIOC_G_FBUF: OK (Not Supported)
11278 00:57:15.248292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11279 00:57:15.249028 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11281 00:57:15.251358 test VIDIOC_G_FMT: OK
11282 00:57:15.275889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11283 00:57:15.276714 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11285 00:57:15.279779 test VIDIOC_TRY_FMT: OK
11286 00:57:15.301362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11287 00:57:15.302126 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11289 00:57:15.307648 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11290 00:57:15.313602 test VIDIOC_S_FMT: OK
11291 00:57:15.339513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11292 00:57:15.340253 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11294 00:57:15.343336 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11295 00:57:15.365440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11296 00:57:15.366214 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11298 00:57:15.368846 test Cropping: OK (Not Supported)
11299 00:57:15.391100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11300 00:57:15.391861 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11302 00:57:15.394505 test Composing: OK (Not Supported)
11303 00:57:15.415150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11304 00:57:15.415893 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11306 00:57:15.418536 test Scaling: OK (Not Supported)
11307 00:57:15.439826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11308 00:57:15.440306
11309 00:57:15.440882 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11311 00:57:15.454519 Codec ioctls (Input 0):
11312 00:57:15.461197 <LAVA_SIGNAL_TESTSET STOP>
11313 00:57:15.461973 Received signal: <TESTSET> STOP
11314 00:57:15.462318 Closing test_set Format-ioctls-Input-0
11315 00:57:15.470844 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11316 00:57:15.471543 Received signal: <TESTSET> START Codec-ioctls-Input-0
11317 00:57:15.471930 Starting test_set Codec-ioctls-Input-0
11318 00:57:15.473979 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11319 00:57:15.495601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11320 00:57:15.496549 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11322 00:57:15.502563 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11323 00:57:15.522051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11324 00:57:15.522789 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11326 00:57:15.528371 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11327 00:57:15.547648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11328 00:57:15.548137
11329 00:57:15.548713 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11331 00:57:15.558313 Buffer ioctls (Input 0):
11332 00:57:15.564607 <LAVA_SIGNAL_TESTSET STOP>
11333 00:57:15.565359 Received signal: <TESTSET> STOP
11334 00:57:15.565794 Closing test_set Codec-ioctls-Input-0
11335 00:57:15.574051 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11336 00:57:15.574716 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11337 00:57:15.575063 Starting test_set Buffer-ioctls-Input-0
11338 00:57:15.577500 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11339 00:57:15.605253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11340 00:57:15.606075 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11342 00:57:15.608302 test CREATE_BUFS maximum buffers: OK
11343 00:57:15.626573 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11345 00:57:15.629526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11346 00:57:15.630021 test VIDIOC_EXPBUF: OK
11347 00:57:15.657390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11348 00:57:15.658228 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11350 00:57:15.660774 test Requests: OK (Not Supported)
11351 00:57:15.689625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11352 00:57:15.690123
11353 00:57:15.690696 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11355 00:57:15.699528 Test input 0:
11356 00:57:15.711885
11357 00:57:15.722669 Streaming ioctls:
11358 00:57:15.729876 <LAVA_SIGNAL_TESTSET STOP>
11359 00:57:15.730546 Received signal: <TESTSET> STOP
11360 00:57:15.730890 Closing test_set Buffer-ioctls-Input-0
11361 00:57:15.739394 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11362 00:57:15.740013 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11363 00:57:15.740324 Starting test_set Streaming-ioctls_Test-input-0
11364 00:57:15.742618 test read/write: OK (Not Supported)
11365 00:57:15.765007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11366 00:57:15.765763 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11368 00:57:15.768161 test blocking wait: OK
11369 00:57:15.789667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11370 00:57:15.790419 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11372 00:57:15.795650 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11373 00:57:15.799369 test MMAP (no poll): FAIL
11374 00:57:15.824373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11375 00:57:15.825145 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11377 00:57:15.830940 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11378 00:57:15.834297 test MMAP (select): FAIL
11379 00:57:15.857896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11380 00:57:15.858630 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11382 00:57:15.864753 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11383 00:57:15.868535 test MMAP (epoll): FAIL
11384 00:57:15.892898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11385 00:57:15.893409
11386 00:57:15.894050 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11388 00:57:15.906367
11389 00:57:16.094526
11390 00:57:16.102634 test USERPTR (no poll): OK
11391 00:57:16.133031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11392 00:57:16.133525
11393 00:57:16.134143 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11395 00:57:16.147114
11396 00:57:16.336134
11397 00:57:16.344558 test USERPTR (select): OK
11398 00:57:16.367089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11399 00:57:16.367783 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11401 00:57:16.372978 test DMABUF: Cannot test, specify --expbuf-device
11402 00:57:16.377213
11403 00:57:16.393363 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11404 00:57:16.397930 <LAVA_TEST_RUNNER EXIT>
11405 00:57:16.398682 ok: lava_test_shell seems to have completed
11406 00:57:16.399051 Marking unfinished test run as failed
11408 00:57:16.403263 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11409 00:57:16.403868 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11410 00:57:16.404310 end: 3 lava-test-retry (duration 00:00:10) [common]
11411 00:57:16.404880 start: 4 finalize (timeout 00:07:58) [common]
11412 00:57:16.405315 start: 4.1 power-off (timeout 00:00:30) [common]
11413 00:57:16.406008 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11414 00:57:18.545219 >> Command sent successfully.
11415 00:57:18.560053 Returned 0 in 2 seconds
11416 00:57:18.661461 end: 4.1 power-off (duration 00:00:02) [common]
11418 00:57:18.662965 start: 4.2 read-feedback (timeout 00:07:55) [common]
11419 00:57:18.664120 Listened to connection for namespace 'common' for up to 1s
11420 00:57:19.664935 Finalising connection for namespace 'common'
11421 00:57:19.665598 Disconnecting from shell: Finalise
11422 00:57:19.666062 / #
11423 00:57:19.766887 end: 4.2 read-feedback (duration 00:00:01) [common]
11424 00:57:19.767557 end: 4 finalize (duration 00:00:03) [common]
11425 00:57:19.768136 Cleaning after the job
11426 00:57:19.768645 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/ramdisk
11427 00:57:19.787928 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/kernel
11428 00:57:19.818377 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/dtb
11429 00:57:19.818688 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14368569/tftp-deploy-07bfviip/modules
11430 00:57:19.826021 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14368569
11431 00:57:19.886884 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14368569
11432 00:57:19.887042 Job finished correctly