Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 16:33:09.530991 lava-dispatcher, installed at version: 2024.03
2 16:33:09.531193 start: 0 validate
3 16:33:09.531337 Start time: 2024-06-17 16:33:09.531328+00:00 (UTC)
4 16:33:09.531462 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:33:09.531599 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 16:33:09.790206 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:33:09.790377 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:33:10.054245 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:33:10.054421 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:33:10.318394 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:33:10.318554 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 16:33:10.582299 validate duration: 1.05
14 16:33:10.582591 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:33:10.582712 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:33:10.582824 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:33:10.582963 Not decompressing ramdisk as can be used compressed.
18 16:33:10.583055 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 16:33:10.583122 saving as /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/ramdisk/rootfs.cpio.gz
20 16:33:10.583192 total size: 28105535 (26 MB)
21 16:33:10.585225 progress 0 % (0 MB)
22 16:33:10.593846 progress 5 % (1 MB)
23 16:33:10.604528 progress 10 % (2 MB)
24 16:33:10.613676 progress 15 % (4 MB)
25 16:33:10.623708 progress 20 % (5 MB)
26 16:33:10.635662 progress 25 % (6 MB)
27 16:33:10.646104 progress 30 % (8 MB)
28 16:33:10.656056 progress 35 % (9 MB)
29 16:33:10.665330 progress 40 % (10 MB)
30 16:33:10.675727 progress 45 % (12 MB)
31 16:33:10.685567 progress 50 % (13 MB)
32 16:33:10.696899 progress 55 % (14 MB)
33 16:33:10.707760 progress 60 % (16 MB)
34 16:33:10.717560 progress 65 % (17 MB)
35 16:33:10.727897 progress 70 % (18 MB)
36 16:33:10.736990 progress 75 % (20 MB)
37 16:33:10.747834 progress 80 % (21 MB)
38 16:33:10.756404 progress 85 % (22 MB)
39 16:33:10.767971 progress 90 % (24 MB)
40 16:33:10.777330 progress 95 % (25 MB)
41 16:33:10.786330 progress 100 % (26 MB)
42 16:33:10.786599 26 MB downloaded in 0.20 s (131.77 MB/s)
43 16:33:10.786762 end: 1.1.1 http-download (duration 00:00:00) [common]
45 16:33:10.787014 end: 1.1 download-retry (duration 00:00:00) [common]
46 16:33:10.787104 start: 1.2 download-retry (timeout 00:10:00) [common]
47 16:33:10.787192 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 16:33:10.787328 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 16:33:10.787399 saving as /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/kernel/Image
50 16:33:10.787465 total size: 54813184 (52 MB)
51 16:33:10.787529 No compression specified
52 16:33:10.788624 progress 0 % (0 MB)
53 16:33:10.802607 progress 5 % (2 MB)
54 16:33:10.817282 progress 10 % (5 MB)
55 16:33:10.831525 progress 15 % (7 MB)
56 16:33:10.845713 progress 20 % (10 MB)
57 16:33:10.860008 progress 25 % (13 MB)
58 16:33:10.874097 progress 30 % (15 MB)
59 16:33:10.888419 progress 35 % (18 MB)
60 16:33:10.902807 progress 40 % (20 MB)
61 16:33:10.917300 progress 45 % (23 MB)
62 16:33:10.931790 progress 50 % (26 MB)
63 16:33:10.946312 progress 55 % (28 MB)
64 16:33:10.960410 progress 60 % (31 MB)
65 16:33:10.975224 progress 65 % (34 MB)
66 16:33:10.989541 progress 70 % (36 MB)
67 16:33:11.004088 progress 75 % (39 MB)
68 16:33:11.018891 progress 80 % (41 MB)
69 16:33:11.033455 progress 85 % (44 MB)
70 16:33:11.048189 progress 90 % (47 MB)
71 16:33:11.062849 progress 95 % (49 MB)
72 16:33:11.076977 progress 100 % (52 MB)
73 16:33:11.077255 52 MB downloaded in 0.29 s (180.39 MB/s)
74 16:33:11.077413 end: 1.2.1 http-download (duration 00:00:00) [common]
76 16:33:11.077661 end: 1.2 download-retry (duration 00:00:00) [common]
77 16:33:11.077754 start: 1.3 download-retry (timeout 00:10:00) [common]
78 16:33:11.077842 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 16:33:11.077974 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 16:33:11.078049 saving as /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/dtb/mt8192-asurada-spherion-r0.dtb
81 16:33:11.078112 total size: 47258 (0 MB)
82 16:33:11.078184 No compression specified
83 16:33:11.079564 progress 69 % (0 MB)
84 16:33:11.079846 progress 100 % (0 MB)
85 16:33:11.080006 0 MB downloaded in 0.00 s (23.83 MB/s)
86 16:33:11.080132 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:33:11.080363 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:33:11.080452 start: 1.4 download-retry (timeout 00:10:00) [common]
90 16:33:11.080539 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 16:33:11.080656 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 16:33:11.080726 saving as /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/modules/modules.tar
93 16:33:11.080790 total size: 8628772 (8 MB)
94 16:33:11.080854 Using unxz to decompress xz
95 16:33:11.085078 progress 0 % (0 MB)
96 16:33:11.108670 progress 5 % (0 MB)
97 16:33:11.136212 progress 10 % (0 MB)
98 16:33:11.163262 progress 15 % (1 MB)
99 16:33:11.192574 progress 20 % (1 MB)
100 16:33:11.228006 progress 25 % (2 MB)
101 16:33:11.255640 progress 30 % (2 MB)
102 16:33:11.285744 progress 35 % (2 MB)
103 16:33:11.313643 progress 40 % (3 MB)
104 16:33:11.340075 progress 45 % (3 MB)
105 16:33:11.367068 progress 50 % (4 MB)
106 16:33:11.392965 progress 55 % (4 MB)
107 16:33:11.419759 progress 60 % (4 MB)
108 16:33:11.449072 progress 65 % (5 MB)
109 16:33:11.475586 progress 70 % (5 MB)
110 16:33:11.500577 progress 75 % (6 MB)
111 16:33:11.526042 progress 80 % (6 MB)
112 16:33:11.557155 progress 85 % (7 MB)
113 16:33:11.588215 progress 90 % (7 MB)
114 16:33:11.616599 progress 95 % (7 MB)
115 16:33:11.643502 progress 100 % (8 MB)
116 16:33:11.649113 8 MB downloaded in 0.57 s (14.48 MB/s)
117 16:33:11.649461 end: 1.4.1 http-download (duration 00:00:01) [common]
119 16:33:11.649905 end: 1.4 download-retry (duration 00:00:01) [common]
120 16:33:11.650039 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 16:33:11.650179 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 16:33:11.650333 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:33:11.650486 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 16:33:11.650729 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof
125 16:33:11.650901 makedir: /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin
126 16:33:11.651039 makedir: /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/tests
127 16:33:11.651172 makedir: /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/results
128 16:33:11.651352 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-add-keys
129 16:33:11.651573 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-add-sources
130 16:33:11.651759 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-background-process-start
131 16:33:11.651927 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-background-process-stop
132 16:33:11.652087 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-common-functions
133 16:33:11.652250 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-echo-ipv4
134 16:33:11.652413 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-install-packages
135 16:33:11.652578 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-installed-packages
136 16:33:11.652741 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-os-build
137 16:33:11.652904 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-probe-channel
138 16:33:11.653065 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-probe-ip
139 16:33:11.653238 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-target-ip
140 16:33:11.653549 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-target-mac
141 16:33:11.653722 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-target-storage
142 16:33:11.653894 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-test-case
143 16:33:11.654056 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-test-event
144 16:33:11.654247 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-test-feedback
145 16:33:11.654481 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-test-raise
146 16:33:11.654609 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-test-reference
147 16:33:11.654750 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-test-runner
148 16:33:11.654929 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-test-set
149 16:33:11.655094 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-test-shell
150 16:33:11.655260 Updating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-install-packages (oe)
151 16:33:11.655460 Updating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/bin/lava-installed-packages (oe)
152 16:33:11.655620 Creating /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/environment
153 16:33:11.655754 LAVA metadata
154 16:33:11.655869 - LAVA_JOB_ID=14396157
155 16:33:11.655968 - LAVA_DISPATCHER_IP=192.168.201.1
156 16:33:11.656118 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 16:33:11.656215 skipped lava-vland-overlay
158 16:33:11.656322 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 16:33:11.656456 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 16:33:11.656573 skipped lava-multinode-overlay
161 16:33:11.656681 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 16:33:11.656810 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 16:33:11.656939 Loading test definitions
164 16:33:11.657083 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 16:33:11.657195 Using /lava-14396157 at stage 0
166 16:33:11.657743 uuid=14396157_1.5.2.3.1 testdef=None
167 16:33:11.657865 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 16:33:11.657995 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 16:33:11.658637 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 16:33:11.659070 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 16:33:11.660127 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 16:33:11.660505 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 16:33:11.661329 runner path: /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14396157_1.5.2.3.1
176 16:33:11.661501 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 16:33:11.661854 Creating lava-test-runner.conf files
179 16:33:11.661948 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396157/lava-overlay-_69msqof/lava-14396157/0 for stage 0
180 16:33:11.662082 - 0_v4l2-compliance-mtk-vcodec-enc
181 16:33:11.662258 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 16:33:11.662353 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 16:33:11.670425 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 16:33:11.670548 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 16:33:11.670656 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 16:33:11.670746 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 16:33:11.670853 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 16:33:12.651740 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 16:33:12.652169 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 16:33:12.652320 extracting modules file /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396157/extract-overlay-ramdisk-ijcgvymy/ramdisk
191 16:33:12.927064 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 16:33:12.927238 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 16:33:12.927333 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396157/compress-overlay-f0e5d8u7/overlay-1.5.2.4.tar.gz to ramdisk
194 16:33:12.927417 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396157/compress-overlay-f0e5d8u7/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396157/extract-overlay-ramdisk-ijcgvymy/ramdisk
195 16:33:12.934513 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 16:33:12.934651 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 16:33:12.934749 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 16:33:12.934846 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 16:33:12.934955 Building ramdisk /var/lib/lava/dispatcher/tmp/14396157/extract-overlay-ramdisk-ijcgvymy/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396157/extract-overlay-ramdisk-ijcgvymy/ramdisk
200 16:33:13.605529 >> 276012 blocks
201 16:33:17.786409 rename /var/lib/lava/dispatcher/tmp/14396157/extract-overlay-ramdisk-ijcgvymy/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/ramdisk/ramdisk.cpio.gz
202 16:33:17.786883 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 16:33:17.787022 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 16:33:17.787127 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 16:33:17.787239 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/kernel/Image']
206 16:33:32.874894 Returned 0 in 15 seconds
207 16:33:32.975531 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/kernel/image.itb
208 16:33:33.643696 output: FIT description: Kernel Image image with one or more FDT blobs
209 16:33:33.644072 output: Created: Mon Jun 17 17:33:33 2024
210 16:33:33.644145 output: Image 0 (kernel-1)
211 16:33:33.644210 output: Description:
212 16:33:33.644272 output: Created: Mon Jun 17 17:33:33 2024
213 16:33:33.644351 output: Type: Kernel Image
214 16:33:33.644417 output: Compression: lzma compressed
215 16:33:33.644484 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
216 16:33:33.644546 output: Architecture: AArch64
217 16:33:33.644645 output: OS: Linux
218 16:33:33.644706 output: Load Address: 0x00000000
219 16:33:33.644768 output: Entry Point: 0x00000000
220 16:33:33.644827 output: Hash algo: crc32
221 16:33:33.644886 output: Hash value: 106ffd6f
222 16:33:33.644945 output: Image 1 (fdt-1)
223 16:33:33.645001 output: Description: mt8192-asurada-spherion-r0
224 16:33:33.645055 output: Created: Mon Jun 17 17:33:33 2024
225 16:33:33.645109 output: Type: Flat Device Tree
226 16:33:33.645162 output: Compression: uncompressed
227 16:33:33.645216 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 16:33:33.645269 output: Architecture: AArch64
229 16:33:33.645322 output: Hash algo: crc32
230 16:33:33.645375 output: Hash value: 0f8e4d2e
231 16:33:33.645428 output: Image 2 (ramdisk-1)
232 16:33:33.645481 output: Description: unavailable
233 16:33:33.645534 output: Created: Mon Jun 17 17:33:33 2024
234 16:33:33.645587 output: Type: RAMDisk Image
235 16:33:33.645641 output: Compression: Unknown Compression
236 16:33:33.645694 output: Data Size: 41230218 Bytes = 40263.88 KiB = 39.32 MiB
237 16:33:33.645747 output: Architecture: AArch64
238 16:33:33.645800 output: OS: Linux
239 16:33:33.645854 output: Load Address: unavailable
240 16:33:33.645907 output: Entry Point: unavailable
241 16:33:33.645960 output: Hash algo: crc32
242 16:33:33.646013 output: Hash value: 4005a813
243 16:33:33.646066 output: Default Configuration: 'conf-1'
244 16:33:33.646119 output: Configuration 0 (conf-1)
245 16:33:33.646205 output: Description: mt8192-asurada-spherion-r0
246 16:33:33.646281 output: Kernel: kernel-1
247 16:33:33.646335 output: Init Ramdisk: ramdisk-1
248 16:33:33.646389 output: FDT: fdt-1
249 16:33:33.646442 output: Loadables: kernel-1
250 16:33:33.646495 output:
251 16:33:33.646704 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 16:33:33.646799 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 16:33:33.646900 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 16:33:33.646995 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 16:33:33.647079 No LXC device requested
256 16:33:33.647160 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 16:33:33.647243 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 16:33:33.647323 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 16:33:33.647388 Checking files for TFTP limit of 4294967296 bytes.
260 16:33:33.647886 end: 1 tftp-deploy (duration 00:00:23) [common]
261 16:33:33.647988 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 16:33:33.648078 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 16:33:33.648200 substitutions:
264 16:33:33.648282 - {DTB}: 14396157/tftp-deploy-7i0icuzc/dtb/mt8192-asurada-spherion-r0.dtb
265 16:33:33.648353 - {INITRD}: 14396157/tftp-deploy-7i0icuzc/ramdisk/ramdisk.cpio.gz
266 16:33:33.648414 - {KERNEL}: 14396157/tftp-deploy-7i0icuzc/kernel/Image
267 16:33:33.648472 - {LAVA_MAC}: None
268 16:33:33.648529 - {PRESEED_CONFIG}: None
269 16:33:33.648584 - {PRESEED_LOCAL}: None
270 16:33:33.648639 - {RAMDISK}: 14396157/tftp-deploy-7i0icuzc/ramdisk/ramdisk.cpio.gz
271 16:33:33.648694 - {ROOT_PART}: None
272 16:33:33.648748 - {ROOT}: None
273 16:33:33.648805 - {SERVER_IP}: 192.168.201.1
274 16:33:33.648859 - {TEE}: None
275 16:33:33.648914 Parsed boot commands:
276 16:33:33.648968 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 16:33:33.649147 Parsed boot commands: tftpboot 192.168.201.1 14396157/tftp-deploy-7i0icuzc/kernel/image.itb 14396157/tftp-deploy-7i0icuzc/kernel/cmdline
278 16:33:33.649237 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 16:33:33.649323 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 16:33:33.649413 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 16:33:33.649496 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 16:33:33.649566 Not connected, no need to disconnect.
283 16:33:33.649640 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 16:33:33.649719 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 16:33:33.649788 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 16:33:33.653653 Setting prompt string to ['lava-test: # ']
287 16:33:33.654038 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 16:33:33.654153 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 16:33:33.654310 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 16:33:33.654429 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 16:33:33.654697 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
292 16:33:47.669621 Returned 0 in 14 seconds
293 16:33:47.770658 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 16:33:47.771055 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 16:33:47.771163 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 16:33:47.771260 Setting prompt string to 'Starting depthcharge on Spherion...'
298 16:33:47.771334 Changing prompt to 'Starting depthcharge on Spherion...'
299 16:33:47.771405 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 16:33:47.771971 [Enter `^Ec?' for help]
301 16:33:47.772135
302 16:33:47.772270
303 16:33:47.772338 F0: 102B 0000
304 16:33:47.772400
305 16:33:47.772464 F3: 1001 0000 [0200]
306 16:33:47.772527
307 16:33:47.772587 F3: 1001 0000
308 16:33:47.772647
309 16:33:47.772704 F7: 102D 0000
310 16:33:47.772761
311 16:33:47.772817 F1: 0000 0000
312 16:33:47.772873
313 16:33:47.772929 V0: 0000 0000 [0001]
314 16:33:47.772984
315 16:33:47.773040 00: 0007 8000
316 16:33:47.773099
317 16:33:47.773155 01: 0000 0000
318 16:33:47.773212
319 16:33:47.773268 BP: 0C00 0209 [0000]
320 16:33:47.773323
321 16:33:47.773378 G0: 1182 0000
322 16:33:47.773433
323 16:33:47.773488 EC: 0000 0021 [4000]
324 16:33:47.773543
325 16:33:47.773598 S7: 0000 0000 [0000]
326 16:33:47.773653
327 16:33:47.773709 CC: 0000 0000 [0001]
328 16:33:47.773764
329 16:33:47.773819 T0: 0000 0040 [010F]
330 16:33:47.773875
331 16:33:47.773930 Jump to BL
332 16:33:47.773985
333 16:33:47.774040
334 16:33:47.774095
335 16:33:47.774150 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 16:33:47.774254 ARM64: Exception handlers installed.
337 16:33:47.774311 ARM64: Testing exception
338 16:33:47.774366 ARM64: Done test exception
339 16:33:47.774422 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 16:33:47.774478 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 16:33:47.774535 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 16:33:47.774591 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 16:33:47.774647 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 16:33:47.774703 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 16:33:47.774758 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 16:33:47.774814 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 16:33:47.774870 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 16:33:47.774926 WDT: Last reset was cold boot
349 16:33:47.774981 SPI1(PAD0) initialized at 2873684 Hz
350 16:33:47.775036 SPI5(PAD0) initialized at 992727 Hz
351 16:33:47.775092 VBOOT: Loading verstage.
352 16:33:47.775146 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 16:33:47.775235 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 16:33:47.775317 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 16:33:47.775375 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 16:33:47.775431 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 16:33:47.775488 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 16:33:47.775544 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 16:33:47.775600
360 16:33:47.775655
361 16:33:47.775710 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 16:33:47.775767 ARM64: Exception handlers installed.
363 16:33:47.775823 ARM64: Testing exception
364 16:33:47.775878 ARM64: Done test exception
365 16:33:47.775934 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 16:33:47.775990 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 16:33:47.776046 Probing TPM: . done!
368 16:33:47.776101 TPM ready after 0 ms
369 16:33:47.776156 Connected to device vid:did:rid of 1ae0:0028:00
370 16:33:47.776212 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
371 16:33:47.776268 Initialized TPM device CR50 revision 0
372 16:33:47.776324 tlcl_send_startup: Startup return code is 0
373 16:33:47.776380 TPM: setup succeeded
374 16:33:47.776436 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 16:33:47.776491 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 16:33:47.776546 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 16:33:47.776602 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 16:33:47.776658 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 16:33:47.776713 in-header: 03 07 00 00 08 00 00 00
380 16:33:47.776769 in-data: aa e4 47 04 13 02 00 00
381 16:33:47.776824 Chrome EC: UHEPI supported
382 16:33:47.776879 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 16:33:47.776935 in-header: 03 a9 00 00 08 00 00 00
384 16:33:47.776991 in-data: 84 60 60 08 00 00 00 00
385 16:33:47.777046 Phase 1
386 16:33:47.777101 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 16:33:47.777156 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 16:33:47.777212 VB2:vb2_check_recovery() Recovery was requested manually
389 16:33:47.777268 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 16:33:47.777324 Recovery requested (1009000e)
391 16:33:47.777379 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 16:33:47.777435 tlcl_extend: response is 0
393 16:33:47.777491 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 16:33:47.777546 tlcl_extend: response is 0
395 16:33:47.777601 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 16:33:47.777657 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 16:33:47.777712 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 16:33:47.777768
399 16:33:47.777823
400 16:33:47.777878 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 16:33:47.777934 ARM64: Exception handlers installed.
402 16:33:47.777990 ARM64: Testing exception
403 16:33:47.778044 ARM64: Done test exception
404 16:33:47.778099 pmic_efuse_setting: Set efuses in 11 msecs
405 16:33:47.778155 pmwrap_interface_init: Select PMIF_VLD_RDY
406 16:33:47.778266 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 16:33:47.778324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 16:33:47.778573 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 16:33:47.778669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 16:33:47.778754 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 16:33:47.778814 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 16:33:47.778870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 16:33:47.778926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 16:33:47.778981 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 16:33:47.779037 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 16:33:47.779093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 16:33:47.779148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 16:33:47.779204 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 16:33:47.779259 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 16:33:47.779314 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 16:33:47.779370 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 16:33:47.779425 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 16:33:47.779481 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 16:33:47.779536 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 16:33:47.779592 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 16:33:47.779648 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 16:33:47.779703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 16:33:47.779759 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 16:33:47.779814 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 16:33:47.779870 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 16:33:47.779925 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 16:33:47.779980 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 16:33:47.780036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 16:33:47.780091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 16:33:47.780146 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 16:33:47.780202 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 16:33:47.780257 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 16:33:47.780312 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 16:33:47.780386 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 16:33:47.780455 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 16:33:47.780511 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 16:33:47.780582 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 16:33:47.780638 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 16:33:47.780708 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 16:33:47.780763 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 16:33:47.780817 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 16:33:47.780872 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 16:33:47.780927 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 16:33:47.780982 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 16:33:47.781037 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 16:33:47.781093 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 16:33:47.781148 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 16:33:47.781203 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 16:33:47.781258 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 16:33:47.781313 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 16:33:47.781368 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 16:33:47.781422 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 16:33:47.781478 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 16:33:47.781534 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 16:33:47.781590 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 16:33:47.781646 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 16:33:47.781703 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 16:33:47.781761 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 16:33:47.781816 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 16:33:47.781871 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
466 16:33:47.781927 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 16:33:47.781991 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
468 16:33:47.782076 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 16:33:47.782185 [RTC]rtc_get_frequency_meter,154: input=15, output=834
470 16:33:47.782259 [RTC]rtc_get_frequency_meter,154: input=7, output=709
471 16:33:47.782315 [RTC]rtc_get_frequency_meter,154: input=11, output=771
472 16:33:47.782371 [RTC]rtc_get_frequency_meter,154: input=13, output=802
473 16:33:47.782427 [RTC]rtc_get_frequency_meter,154: input=12, output=787
474 16:33:47.782482 [RTC]rtc_get_frequency_meter,154: input=12, output=787
475 16:33:47.782538 [RTC]rtc_get_frequency_meter,154: input=13, output=804
476 16:33:47.782593 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
477 16:33:47.782648 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
478 16:33:47.782893 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 16:33:47.783032 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 16:33:47.783166 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 16:33:47.783299 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 16:33:47.783433 ADC[4]: Raw value=904509 ID=7
483 16:33:47.783567 ADC[3]: Raw value=213652 ID=1
484 16:33:47.783701 RAM Code: 0x71
485 16:33:47.783831 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 16:33:47.783966 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 16:33:47.784051 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 16:33:47.784111 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 16:33:47.784169 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 16:33:47.784226 in-header: 03 07 00 00 08 00 00 00
491 16:33:47.784282 in-data: aa e4 47 04 13 02 00 00
492 16:33:47.784340 Chrome EC: UHEPI supported
493 16:33:47.784396 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 16:33:47.784453 in-header: 03 a9 00 00 08 00 00 00
495 16:33:47.784524 in-data: 84 60 60 08 00 00 00 00
496 16:33:47.784617 MRC: failed to locate region type 0.
497 16:33:47.784687 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 16:33:47.784742 DRAM-K: Running full calibration
499 16:33:47.784814 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 16:33:47.784887 header.status = 0x0
501 16:33:47.784943 header.version = 0x6 (expected: 0x6)
502 16:33:47.784998 header.size = 0xd00 (expected: 0xd00)
503 16:33:47.785053 header.flags = 0x0
504 16:33:47.785109 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 16:33:47.785164 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
506 16:33:47.785220 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 16:33:47.785276 dram_init: ddr_geometry: 2
508 16:33:47.785331 [EMI] MDL number = 2
509 16:33:47.785386 [EMI] Get MDL freq = 0
510 16:33:47.785441 dram_init: ddr_type: 0
511 16:33:47.785496 is_discrete_lpddr4: 1
512 16:33:47.785551 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 16:33:47.785605
514 16:33:47.785660
515 16:33:47.785715 [Bian_co] ETT version 0.0.0.1
516 16:33:47.785770 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 16:33:47.785826
518 16:33:47.785885 dramc_set_vcore_voltage set vcore to 650000
519 16:33:47.785944 Read voltage for 800, 4
520 16:33:47.785999 Vio18 = 0
521 16:33:47.786055 Vcore = 650000
522 16:33:47.786110 Vdram = 0
523 16:33:47.786190 Vddq = 0
524 16:33:47.786266 Vmddr = 0
525 16:33:47.786321 dram_init: config_dvfs: 1
526 16:33:47.786377 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 16:33:47.786432 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 16:33:47.786488 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
529 16:33:47.786543 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
530 16:33:47.786598 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
531 16:33:47.786653 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
532 16:33:47.786708 MEM_TYPE=3, freq_sel=18
533 16:33:47.786763 sv_algorithm_assistance_LP4_1600
534 16:33:47.786818 ============ PULL DRAM RESETB DOWN ============
535 16:33:47.786879 ========== PULL DRAM RESETB DOWN end =========
536 16:33:47.786937 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 16:33:47.786994 ===================================
538 16:33:47.787052 LPDDR4 DRAM CONFIGURATION
539 16:33:47.787110 ===================================
540 16:33:47.787168 EX_ROW_EN[0] = 0x0
541 16:33:47.787223 EX_ROW_EN[1] = 0x0
542 16:33:47.787279 LP4Y_EN = 0x0
543 16:33:47.787333 WORK_FSP = 0x0
544 16:33:47.787388 WL = 0x2
545 16:33:47.787443 RL = 0x2
546 16:33:47.787498 BL = 0x2
547 16:33:47.787553 RPST = 0x0
548 16:33:47.787638 RD_PRE = 0x0
549 16:33:47.787692 WR_PRE = 0x1
550 16:33:47.787747 WR_PST = 0x0
551 16:33:47.787802 DBI_WR = 0x0
552 16:33:47.787857 DBI_RD = 0x0
553 16:33:47.787912 OTF = 0x1
554 16:33:47.787967 ===================================
555 16:33:47.788022 ===================================
556 16:33:47.788077 ANA top config
557 16:33:47.788135 ===================================
558 16:33:47.788193 DLL_ASYNC_EN = 0
559 16:33:47.788248 ALL_SLAVE_EN = 1
560 16:33:47.788303 NEW_RANK_MODE = 1
561 16:33:47.788359 DLL_IDLE_MODE = 1
562 16:33:47.788415 LP45_APHY_COMB_EN = 1
563 16:33:47.788469 TX_ODT_DIS = 1
564 16:33:47.788524 NEW_8X_MODE = 1
565 16:33:47.788580 ===================================
566 16:33:47.788635 ===================================
567 16:33:47.788690 data_rate = 1600
568 16:33:47.788778 CKR = 1
569 16:33:47.788834 DQ_P2S_RATIO = 8
570 16:33:47.788889 ===================================
571 16:33:47.788944 CA_P2S_RATIO = 8
572 16:33:47.789003 DQ_CA_OPEN = 0
573 16:33:47.789060 DQ_SEMI_OPEN = 0
574 16:33:47.789116 CA_SEMI_OPEN = 0
575 16:33:47.789171 CA_FULL_RATE = 0
576 16:33:47.789226 DQ_CKDIV4_EN = 1
577 16:33:47.789281 CA_CKDIV4_EN = 1
578 16:33:47.789336 CA_PREDIV_EN = 0
579 16:33:47.789395 PH8_DLY = 0
580 16:33:47.789451 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 16:33:47.789509 DQ_AAMCK_DIV = 4
582 16:33:47.789565 CA_AAMCK_DIV = 4
583 16:33:47.789623 CA_ADMCK_DIV = 4
584 16:33:47.789678 DQ_TRACK_CA_EN = 0
585 16:33:47.789733 CA_PICK = 800
586 16:33:47.789788 CA_MCKIO = 800
587 16:33:47.789843 MCKIO_SEMI = 0
588 16:33:47.789915 PLL_FREQ = 3068
589 16:33:47.789988 DQ_UI_PI_RATIO = 32
590 16:33:47.790068 CA_UI_PI_RATIO = 0
591 16:33:47.790153 ===================================
592 16:33:47.790288 ===================================
593 16:33:47.790374 memory_type:LPDDR4
594 16:33:47.790458 GP_NUM : 10
595 16:33:47.790542 SRAM_EN : 1
596 16:33:47.790626 MD32_EN : 0
597 16:33:47.790713 ===================================
598 16:33:47.791004 [ANA_INIT] >>>>>>>>>>>>>>
599 16:33:47.791139 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 16:33:47.791276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 16:33:47.791410 ===================================
602 16:33:47.791540 data_rate = 1600,PCW = 0X7600
603 16:33:47.791666 ===================================
604 16:33:47.791727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 16:33:47.791785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 16:33:47.791843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 16:33:47.791900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 16:33:47.791955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 16:33:47.792011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 16:33:47.792080 [ANA_INIT] flow start
611 16:33:47.792162 [ANA_INIT] PLL >>>>>>>>
612 16:33:47.792236 [ANA_INIT] PLL <<<<<<<<
613 16:33:47.792312 [ANA_INIT] MIDPI >>>>>>>>
614 16:33:47.792370 [ANA_INIT] MIDPI <<<<<<<<
615 16:33:47.792440 [ANA_INIT] DLL >>>>>>>>
616 16:33:47.792495 [ANA_INIT] flow end
617 16:33:47.792553 ============ LP4 DIFF to SE enter ============
618 16:33:47.792610 ============ LP4 DIFF to SE exit ============
619 16:33:47.792665 [ANA_INIT] <<<<<<<<<<<<<
620 16:33:47.792721 [Flow] Enable top DCM control >>>>>
621 16:33:47.792776 [Flow] Enable top DCM control <<<<<
622 16:33:47.792831 Enable DLL master slave shuffle
623 16:33:47.792887 ==============================================================
624 16:33:47.793021 Gating Mode config
625 16:33:47.793081 ==============================================================
626 16:33:47.793137 Config description:
627 16:33:47.793215 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 16:33:47.793277 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 16:33:47.793334 SELPH_MODE 0: By rank 1: By Phase
630 16:33:47.793391 ==============================================================
631 16:33:47.793464 GAT_TRACK_EN = 1
632 16:33:47.793533 RX_GATING_MODE = 2
633 16:33:47.793588 RX_GATING_TRACK_MODE = 2
634 16:33:47.793648 SELPH_MODE = 1
635 16:33:47.793720 PICG_EARLY_EN = 1
636 16:33:47.793794 VALID_LAT_VALUE = 1
637 16:33:47.793849 ==============================================================
638 16:33:47.793922 Enter into Gating configuration >>>>
639 16:33:47.793995 Exit from Gating configuration <<<<
640 16:33:47.794051 Enter into DVFS_PRE_config >>>>>
641 16:33:47.794123 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 16:33:47.794208 Exit from DVFS_PRE_config <<<<<
643 16:33:47.794264 Enter into PICG configuration >>>>
644 16:33:47.794341 Exit from PICG configuration <<<<
645 16:33:47.794411 [RX_INPUT] configuration >>>>>
646 16:33:47.794466 [RX_INPUT] configuration <<<<<
647 16:33:47.794522 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 16:33:47.794578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 16:33:47.794634 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 16:33:47.794689 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 16:33:47.794744 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 16:33:47.794800 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 16:33:47.794855 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 16:33:47.794915 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 16:33:47.794973 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 16:33:47.795028 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 16:33:47.795083 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 16:33:47.795139 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 16:33:47.795194 ===================================
660 16:33:47.795249 LPDDR4 DRAM CONFIGURATION
661 16:33:47.795304 ===================================
662 16:33:47.795360 EX_ROW_EN[0] = 0x0
663 16:33:47.795414 EX_ROW_EN[1] = 0x0
664 16:33:47.795485 LP4Y_EN = 0x0
665 16:33:47.795541 WORK_FSP = 0x0
666 16:33:47.795597 WL = 0x2
667 16:33:47.795662 RL = 0x2
668 16:33:47.795742 BL = 0x2
669 16:33:47.795812 RPST = 0x0
670 16:33:47.795913 RD_PRE = 0x0
671 16:33:47.795985 WR_PRE = 0x1
672 16:33:47.796064 WR_PST = 0x0
673 16:33:47.796170 DBI_WR = 0x0
674 16:33:47.796231 DBI_RD = 0x0
675 16:33:47.796287 OTF = 0x1
676 16:33:47.796344 ===================================
677 16:33:47.796400 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 16:33:47.796456 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 16:33:47.796511 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 16:33:47.796567 ===================================
681 16:33:47.796622 LPDDR4 DRAM CONFIGURATION
682 16:33:47.796679 ===================================
683 16:33:47.796734 EX_ROW_EN[0] = 0x10
684 16:33:47.796789 EX_ROW_EN[1] = 0x0
685 16:33:47.796844 LP4Y_EN = 0x0
686 16:33:47.796899 WORK_FSP = 0x0
687 16:33:47.796954 WL = 0x2
688 16:33:47.797010 RL = 0x2
689 16:33:47.797064 BL = 0x2
690 16:33:47.797119 RPST = 0x0
691 16:33:47.797174 RD_PRE = 0x0
692 16:33:47.797259 WR_PRE = 0x1
693 16:33:47.797314 WR_PST = 0x0
694 16:33:47.797369 DBI_WR = 0x0
695 16:33:47.797424 DBI_RD = 0x0
696 16:33:47.797479 OTF = 0x1
697 16:33:47.797565 ===================================
698 16:33:47.797620 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 16:33:47.797676 nWR fixed to 40
700 16:33:47.797732 [ModeRegInit_LP4] CH0 RK0
701 16:33:47.797797 [ModeRegInit_LP4] CH0 RK1
702 16:33:47.797855 [ModeRegInit_LP4] CH1 RK0
703 16:33:47.797910 [ModeRegInit_LP4] CH1 RK1
704 16:33:47.797965 match AC timing 13
705 16:33:47.798032 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 16:33:47.798317 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 16:33:47.798457 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 16:33:47.798589 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 16:33:47.798724 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 16:33:47.798887 [EMI DOE] emi_dcm 0
711 16:33:47.798977 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 16:33:47.799056 ==
713 16:33:47.799128 Dram Type= 6, Freq= 0, CH_0, rank 0
714 16:33:47.799187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 16:33:47.799244 ==
716 16:33:47.799300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 16:33:47.799355 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 16:33:47.799412 [CA 0] Center 37 (6~68) winsize 63
719 16:33:47.799468 [CA 1] Center 37 (7~68) winsize 62
720 16:33:47.799523 [CA 2] Center 34 (4~65) winsize 62
721 16:33:47.799597 [CA 3] Center 34 (4~65) winsize 62
722 16:33:47.799690 [CA 4] Center 34 (4~64) winsize 61
723 16:33:47.799749 [CA 5] Center 33 (3~64) winsize 62
724 16:33:47.799805
725 16:33:47.799861 [CmdBusTrainingLP45] Vref(ca) range 1: 30
726 16:33:47.799917
727 16:33:47.799972 [CATrainingPosCal] consider 1 rank data
728 16:33:47.800028 u2DelayCellTimex100 = 270/100 ps
729 16:33:47.800083 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
730 16:33:47.800139 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 16:33:47.800194 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 16:33:47.800274 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 16:33:47.800334 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
734 16:33:47.800390 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 16:33:47.800445
736 16:33:47.800501 CA PerBit enable=1, Macro0, CA PI delay=33
737 16:33:47.800555
738 16:33:47.800610 [CBTSetCACLKResult] CA Dly = 33
739 16:33:47.800689 CS Dly: 7 (0~38)
740 16:33:47.800778 ==
741 16:33:47.800835 Dram Type= 6, Freq= 0, CH_0, rank 1
742 16:33:47.800892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 16:33:47.800950 ==
744 16:33:47.801006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 16:33:47.801077 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 16:33:47.801132 [CA 0] Center 37 (6~68) winsize 63
747 16:33:47.801188 [CA 1] Center 37 (7~68) winsize 62
748 16:33:47.801243 [CA 2] Center 34 (4~65) winsize 62
749 16:33:47.801298 [CA 3] Center 34 (4~65) winsize 62
750 16:33:47.801353 [CA 4] Center 33 (3~64) winsize 62
751 16:33:47.801408 [CA 5] Center 33 (3~64) winsize 62
752 16:33:47.801463
753 16:33:47.801517 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 16:33:47.801572
755 16:33:47.801644 [CATrainingPosCal] consider 2 rank data
756 16:33:47.801740 u2DelayCellTimex100 = 270/100 ps
757 16:33:47.801795 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
758 16:33:47.801850 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 16:33:47.801905 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 16:33:47.801961 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 16:33:47.802015 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
762 16:33:47.802070 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 16:33:47.802124
764 16:33:47.802234 CA PerBit enable=1, Macro0, CA PI delay=33
765 16:33:47.802294
766 16:33:47.802350 [CBTSetCACLKResult] CA Dly = 33
767 16:33:47.802418 CS Dly: 7 (0~38)
768 16:33:47.802486
769 16:33:47.802543 ----->DramcWriteLeveling(PI) begin...
770 16:33:47.802616 ==
771 16:33:47.802706 Dram Type= 6, Freq= 0, CH_0, rank 0
772 16:33:47.802802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 16:33:47.802892 ==
774 16:33:47.802979 Write leveling (Byte 0): 31 => 31
775 16:33:47.803064 Write leveling (Byte 1): 29 => 29
776 16:33:47.803134 DramcWriteLeveling(PI) end<-----
777 16:33:47.803191
778 16:33:47.803246 ==
779 16:33:47.803301 Dram Type= 6, Freq= 0, CH_0, rank 0
780 16:33:47.803357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 16:33:47.803413 ==
782 16:33:47.803468 [Gating] SW mode calibration
783 16:33:47.803524 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 16:33:47.803580 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 16:33:47.803635 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 16:33:47.803691 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 16:33:47.803746 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 16:33:47.803801 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 16:33:47.803857 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 16:33:47.803912 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 16:33:47.803967 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 16:33:47.804022 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 16:33:47.804094 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 16:33:47.804165 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 16:33:47.804220 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 16:33:47.804334 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 16:33:47.804389 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 16:33:47.804444 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 16:33:47.804499 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 16:33:47.804554 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 16:33:47.804609 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 16:33:47.804681 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 16:33:47.804751 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 16:33:47.804806 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 16:33:47.804922 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 16:33:47.804993 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 16:33:47.805049 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 16:33:47.805105 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 16:33:47.805161 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 16:33:47.805218 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 16:33:47.805274 0 9 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
812 16:33:47.805342 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
813 16:33:47.805397 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 16:33:47.805650 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 16:33:47.805787 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 16:33:47.805920 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 16:33:47.806055 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 16:33:47.806233 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 16:33:47.806322 0 10 8 | B1->B0 | 2f2f 2626 | 1 1 | (1 1) (1 0)
820 16:33:47.806383 0 10 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
821 16:33:47.806441 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 16:33:47.806526 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 16:33:47.806586 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 16:33:47.806674 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 16:33:47.806730 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 16:33:47.806786 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 16:33:47.806881 0 11 8 | B1->B0 | 2626 3a3a | 0 0 | (0 0) (0 0)
828 16:33:47.806995 0 11 12 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
829 16:33:47.807053 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 16:33:47.807108 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 16:33:47.807194 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 16:33:47.807250 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 16:33:47.807306 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 16:33:47.807391 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 16:33:47.807446 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
836 16:33:47.807502 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 16:33:47.807557 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 16:33:47.807640 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 16:33:47.807709 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 16:33:47.807764 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 16:33:47.807850 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 16:33:47.807933 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 16:33:47.807988 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 16:33:47.808043 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 16:33:47.808097 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 16:33:47.808155 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 16:33:47.808210 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 16:33:47.808266 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 16:33:47.808321 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 16:33:47.808377 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 16:33:47.808432 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 16:33:47.808488 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 16:33:47.808543 Total UI for P1: 0, mck2ui 16
854 16:33:47.808599 best dqsien dly found for B0: ( 0, 14, 8)
855 16:33:47.808655 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 16:33:47.808710 Total UI for P1: 0, mck2ui 16
857 16:33:47.808786 best dqsien dly found for B1: ( 0, 14, 12)
858 16:33:47.808843 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 16:33:47.808899 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
860 16:33:47.808954
861 16:33:47.809038 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 16:33:47.809093 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
863 16:33:47.809149 [Gating] SW calibration Done
864 16:33:47.809204 ==
865 16:33:47.809260 Dram Type= 6, Freq= 0, CH_0, rank 0
866 16:33:47.809316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 16:33:47.809372 ==
868 16:33:47.809430 RX Vref Scan: 0
869 16:33:47.809502
870 16:33:47.809558 RX Vref 0 -> 0, step: 1
871 16:33:47.809615
872 16:33:47.809731 RX Delay -130 -> 252, step: 16
873 16:33:47.809806 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 16:33:47.809889 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 16:33:47.809948 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 16:33:47.810008 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 16:33:47.810094 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 16:33:47.810198 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 16:33:47.810271 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
880 16:33:47.810343 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
881 16:33:47.810412 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
882 16:33:47.810467 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
883 16:33:47.810522 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 16:33:47.810578 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 16:33:47.810634 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
886 16:33:47.810689 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
887 16:33:47.810744 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 16:33:47.810800 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
889 16:33:47.810855 ==
890 16:33:47.810911 Dram Type= 6, Freq= 0, CH_0, rank 0
891 16:33:47.810967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 16:33:47.811039 ==
893 16:33:47.811109 DQS Delay:
894 16:33:47.811165 DQS0 = 0, DQS1 = 0
895 16:33:47.811220 DQM Delay:
896 16:33:47.811276 DQM0 = 84, DQM1 = 71
897 16:33:47.811331 DQ Delay:
898 16:33:47.811387 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 16:33:47.811442 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
900 16:33:47.811498 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
901 16:33:47.811554 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
902 16:33:47.811609
903 16:33:47.811664
904 16:33:47.811719 ==
905 16:33:47.811774 Dram Type= 6, Freq= 0, CH_0, rank 0
906 16:33:47.811829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 16:33:47.811899 ==
908 16:33:47.811960
909 16:33:47.812015
910 16:33:47.812078 TX Vref Scan disable
911 16:33:47.812149 == TX Byte 0 ==
912 16:33:47.812206 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 16:33:47.812262 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 16:33:47.812317 == TX Byte 1 ==
915 16:33:47.812395 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 16:33:47.812453 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 16:33:47.812508 ==
918 16:33:47.812590 Dram Type= 6, Freq= 0, CH_0, rank 0
919 16:33:47.812649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 16:33:47.812706 ==
921 16:33:47.812762 TX Vref=22, minBit 13, minWin=26, winSum=440
922 16:33:47.813044 TX Vref=24, minBit 5, minWin=27, winSum=444
923 16:33:47.813179 TX Vref=26, minBit 8, minWin=27, winSum=449
924 16:33:47.813314 TX Vref=28, minBit 8, minWin=27, winSum=451
925 16:33:47.813444 TX Vref=30, minBit 4, minWin=27, winSum=445
926 16:33:47.813580 TX Vref=32, minBit 4, minWin=27, winSum=442
927 16:33:47.813673 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 28
928 16:33:47.813734
929 16:33:47.813792 Final TX Range 1 Vref 28
930 16:33:47.813849
931 16:33:47.813906 ==
932 16:33:47.813962 Dram Type= 6, Freq= 0, CH_0, rank 0
933 16:33:47.814035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 16:33:47.814093 ==
935 16:33:47.814150
936 16:33:47.814231
937 16:33:47.814287 TX Vref Scan disable
938 16:33:47.814342 == TX Byte 0 ==
939 16:33:47.814397 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 16:33:47.814453 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 16:33:47.814508 == TX Byte 1 ==
942 16:33:47.814563 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 16:33:47.814622 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 16:33:47.814677
945 16:33:47.814733 [DATLAT]
946 16:33:47.814788 Freq=800, CH0 RK0
947 16:33:47.814843
948 16:33:47.814919 DATLAT Default: 0xa
949 16:33:47.814975 0, 0xFFFF, sum = 0
950 16:33:47.815032 1, 0xFFFF, sum = 0
951 16:33:47.815088 2, 0xFFFF, sum = 0
952 16:33:47.815144 3, 0xFFFF, sum = 0
953 16:33:47.815200 4, 0xFFFF, sum = 0
954 16:33:47.815255 5, 0xFFFF, sum = 0
955 16:33:47.815311 6, 0xFFFF, sum = 0
956 16:33:47.815367 7, 0xFFFF, sum = 0
957 16:33:47.815423 8, 0xFFFF, sum = 0
958 16:33:47.815478 9, 0x0, sum = 1
959 16:33:47.815534 10, 0x0, sum = 2
960 16:33:47.815590 11, 0x0, sum = 3
961 16:33:47.815645 12, 0x0, sum = 4
962 16:33:47.815701 best_step = 10
963 16:33:47.815755
964 16:33:47.815810 ==
965 16:33:47.815865 Dram Type= 6, Freq= 0, CH_0, rank 0
966 16:33:47.815920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 16:33:47.815975 ==
968 16:33:47.816031 RX Vref Scan: 1
969 16:33:47.816085
970 16:33:47.816140 Set Vref Range= 32 -> 127
971 16:33:47.816195
972 16:33:47.816250 RX Vref 32 -> 127, step: 1
973 16:33:47.816305
974 16:33:47.816360 RX Delay -111 -> 252, step: 8
975 16:33:47.816415
976 16:33:47.816470 Set Vref, RX VrefLevel [Byte0]: 32
977 16:33:47.816557 [Byte1]: 32
978 16:33:47.816612
979 16:33:47.816667 Set Vref, RX VrefLevel [Byte0]: 33
980 16:33:47.816753 [Byte1]: 33
981 16:33:47.816838
982 16:33:47.816949 Set Vref, RX VrefLevel [Byte0]: 34
983 16:33:47.817034 [Byte1]: 34
984 16:33:47.817090
985 16:33:47.817146 Set Vref, RX VrefLevel [Byte0]: 35
986 16:33:47.817215 [Byte1]: 35
987 16:33:47.817270
988 16:33:47.817326 Set Vref, RX VrefLevel [Byte0]: 36
989 16:33:47.817381 [Byte1]: 36
990 16:33:47.817436
991 16:33:47.817491 Set Vref, RX VrefLevel [Byte0]: 37
992 16:33:47.817546 [Byte1]: 37
993 16:33:47.817601
994 16:33:47.817655 Set Vref, RX VrefLevel [Byte0]: 38
995 16:33:47.817710 [Byte1]: 38
996 16:33:47.817765
997 16:33:47.817820 Set Vref, RX VrefLevel [Byte0]: 39
998 16:33:47.817874 [Byte1]: 39
999 16:33:47.817929
1000 16:33:47.817983 Set Vref, RX VrefLevel [Byte0]: 40
1001 16:33:47.818038 [Byte1]: 40
1002 16:33:47.818092
1003 16:33:47.818147 Set Vref, RX VrefLevel [Byte0]: 41
1004 16:33:47.818243 [Byte1]: 41
1005 16:33:47.818298
1006 16:33:47.818353 Set Vref, RX VrefLevel [Byte0]: 42
1007 16:33:47.818408 [Byte1]: 42
1008 16:33:47.818463
1009 16:33:47.818517 Set Vref, RX VrefLevel [Byte0]: 43
1010 16:33:47.818572 [Byte1]: 43
1011 16:33:47.818627
1012 16:33:47.818682 Set Vref, RX VrefLevel [Byte0]: 44
1013 16:33:47.818738 [Byte1]: 44
1014 16:33:47.818797
1015 16:33:47.818853 Set Vref, RX VrefLevel [Byte0]: 45
1016 16:33:47.818908 [Byte1]: 45
1017 16:33:47.818967
1018 16:33:47.819023 Set Vref, RX VrefLevel [Byte0]: 46
1019 16:33:47.819078 [Byte1]: 46
1020 16:33:47.819132
1021 16:33:47.819186 Set Vref, RX VrefLevel [Byte0]: 47
1022 16:33:47.819241 [Byte1]: 47
1023 16:33:47.819296
1024 16:33:47.819351 Set Vref, RX VrefLevel [Byte0]: 48
1025 16:33:47.819412 [Byte1]: 48
1026 16:33:47.819470
1027 16:33:47.819529 Set Vref, RX VrefLevel [Byte0]: 49
1028 16:33:47.819585 [Byte1]: 49
1029 16:33:47.819639
1030 16:33:47.819710 Set Vref, RX VrefLevel [Byte0]: 50
1031 16:33:47.819779 [Byte1]: 50
1032 16:33:47.819833
1033 16:33:47.819888 Set Vref, RX VrefLevel [Byte0]: 51
1034 16:33:47.819943 [Byte1]: 51
1035 16:33:47.819996
1036 16:33:47.820050 Set Vref, RX VrefLevel [Byte0]: 52
1037 16:33:47.820104 [Byte1]: 52
1038 16:33:47.820159
1039 16:33:47.820213 Set Vref, RX VrefLevel [Byte0]: 53
1040 16:33:47.820270 [Byte1]: 53
1041 16:33:47.820325
1042 16:33:47.820379 Set Vref, RX VrefLevel [Byte0]: 54
1043 16:33:47.820433 [Byte1]: 54
1044 16:33:47.820487
1045 16:33:47.820557 Set Vref, RX VrefLevel [Byte0]: 55
1046 16:33:47.820654 [Byte1]: 55
1047 16:33:47.820738
1048 16:33:47.820792 Set Vref, RX VrefLevel [Byte0]: 56
1049 16:33:47.820846 [Byte1]: 56
1050 16:33:47.820938
1051 16:33:47.820992 Set Vref, RX VrefLevel [Byte0]: 57
1052 16:33:47.821047 [Byte1]: 57
1053 16:33:47.821101
1054 16:33:47.821154 Set Vref, RX VrefLevel [Byte0]: 58
1055 16:33:47.821209 [Byte1]: 58
1056 16:33:47.821262
1057 16:33:47.821316 Set Vref, RX VrefLevel [Byte0]: 59
1058 16:33:47.821371 [Byte1]: 59
1059 16:33:47.821425
1060 16:33:47.821479 Set Vref, RX VrefLevel [Byte0]: 60
1061 16:33:47.821533 [Byte1]: 60
1062 16:33:47.821587
1063 16:33:47.821641 Set Vref, RX VrefLevel [Byte0]: 61
1064 16:33:47.821695 [Byte1]: 61
1065 16:33:47.821749
1066 16:33:47.821803 Set Vref, RX VrefLevel [Byte0]: 62
1067 16:33:47.821857 [Byte1]: 62
1068 16:33:47.821911
1069 16:33:47.821964 Set Vref, RX VrefLevel [Byte0]: 63
1070 16:33:47.822019 [Byte1]: 63
1071 16:33:47.822073
1072 16:33:47.822126 Set Vref, RX VrefLevel [Byte0]: 64
1073 16:33:47.822223 [Byte1]: 64
1074 16:33:47.822279
1075 16:33:47.822333 Set Vref, RX VrefLevel [Byte0]: 65
1076 16:33:47.822388 [Byte1]: 65
1077 16:33:47.822442
1078 16:33:47.822496 Set Vref, RX VrefLevel [Byte0]: 66
1079 16:33:47.822551 [Byte1]: 66
1080 16:33:47.822605
1081 16:33:47.822659 Set Vref, RX VrefLevel [Byte0]: 67
1082 16:33:47.822716 [Byte1]: 67
1083 16:33:47.822771
1084 16:33:47.822857 Set Vref, RX VrefLevel [Byte0]: 68
1085 16:33:47.822974 [Byte1]: 68
1086 16:33:47.823054
1087 16:33:47.823110 Set Vref, RX VrefLevel [Byte0]: 69
1088 16:33:47.823166 [Byte1]: 69
1089 16:33:47.823220
1090 16:33:47.823471 Set Vref, RX VrefLevel [Byte0]: 70
1091 16:33:47.823537 [Byte1]: 70
1092 16:33:47.823593
1093 16:33:47.823648 Set Vref, RX VrefLevel [Byte0]: 71
1094 16:33:47.823703 [Byte1]: 71
1095 16:33:47.823757
1096 16:33:47.823811 Set Vref, RX VrefLevel [Byte0]: 72
1097 16:33:47.823865 [Byte1]: 72
1098 16:33:47.823920
1099 16:33:47.823974 Set Vref, RX VrefLevel [Byte0]: 73
1100 16:33:47.824028 [Byte1]: 73
1101 16:33:47.824082
1102 16:33:47.824137 Set Vref, RX VrefLevel [Byte0]: 74
1103 16:33:47.824208 [Byte1]: 74
1104 16:33:47.824301
1105 16:33:47.824356 Set Vref, RX VrefLevel [Byte0]: 75
1106 16:33:47.824441 [Byte1]: 75
1107 16:33:47.824524
1108 16:33:47.824579 Set Vref, RX VrefLevel [Byte0]: 76
1109 16:33:47.824663 [Byte1]: 76
1110 16:33:47.824736
1111 16:33:47.824794 Set Vref, RX VrefLevel [Byte0]: 77
1112 16:33:47.824849 [Byte1]: 77
1113 16:33:47.824922
1114 16:33:47.825015 Set Vref, RX VrefLevel [Byte0]: 78
1115 16:33:47.825076 [Byte1]: 78
1116 16:33:47.825132
1117 16:33:47.825186 Set Vref, RX VrefLevel [Byte0]: 79
1118 16:33:47.825241 [Byte1]: 79
1119 16:33:47.825296
1120 16:33:47.825350 Set Vref, RX VrefLevel [Byte0]: 80
1121 16:33:47.825404 [Byte1]: 80
1122 16:33:47.825459
1123 16:33:47.825513 Set Vref, RX VrefLevel [Byte0]: 81
1124 16:33:47.825567 [Byte1]: 81
1125 16:33:47.825622
1126 16:33:47.825676 Set Vref, RX VrefLevel [Byte0]: 82
1127 16:33:47.825731 [Byte1]: 82
1128 16:33:47.825785
1129 16:33:47.825839 Set Vref, RX VrefLevel [Byte0]: 83
1130 16:33:47.825893 [Byte1]: 83
1131 16:33:47.825948
1132 16:33:47.826002 Final RX Vref Byte 0 = 67 to rank0
1133 16:33:47.826057 Final RX Vref Byte 1 = 52 to rank0
1134 16:33:47.826111 Final RX Vref Byte 0 = 67 to rank1
1135 16:33:47.826190 Final RX Vref Byte 1 = 52 to rank1==
1136 16:33:47.826263 Dram Type= 6, Freq= 0, CH_0, rank 0
1137 16:33:47.826318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 16:33:47.826373 ==
1139 16:33:47.826428 DQS Delay:
1140 16:33:47.826482 DQS0 = 0, DQS1 = 0
1141 16:33:47.826536 DQM Delay:
1142 16:33:47.826590 DQM0 = 88, DQM1 = 76
1143 16:33:47.826644 DQ Delay:
1144 16:33:47.826701 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1145 16:33:47.826759 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =100
1146 16:33:47.826814 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1147 16:33:47.826868 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1148 16:33:47.826923
1149 16:33:47.826977
1150 16:33:47.827031 [DQSOSCAuto] RK0, (LSB)MR18= 0x482a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1151 16:33:47.827088 CH0 RK0: MR19=606, MR18=482A
1152 16:33:47.827143 CH0_RK0: MR19=0x606, MR18=0x482A, DQSOSC=391, MR23=63, INC=96, DEC=64
1153 16:33:47.827197
1154 16:33:47.827251 ----->DramcWriteLeveling(PI) begin...
1155 16:33:47.827308 ==
1156 16:33:47.827362 Dram Type= 6, Freq= 0, CH_0, rank 1
1157 16:33:47.827416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 16:33:47.827471 ==
1159 16:33:47.827525 Write leveling (Byte 0): 34 => 34
1160 16:33:47.827579 Write leveling (Byte 1): 29 => 29
1161 16:33:47.827634 DramcWriteLeveling(PI) end<-----
1162 16:33:47.827688
1163 16:33:47.827742 ==
1164 16:33:47.827796 Dram Type= 6, Freq= 0, CH_0, rank 1
1165 16:33:47.827850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1166 16:33:47.827906 ==
1167 16:33:47.827959 [Gating] SW mode calibration
1168 16:33:47.828014 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1169 16:33:47.828069 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1170 16:33:47.828124 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1171 16:33:47.828179 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1172 16:33:47.828234 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1173 16:33:47.828289 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 16:33:47.828360 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 16:33:47.828428 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 16:33:47.828483 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 16:33:47.828536 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 16:33:47.828591 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 16:33:47.828645 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 16:33:47.828699 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 16:33:47.828753 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 16:33:47.828807 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 16:33:47.828862 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 16:33:47.828916 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 16:33:47.828970 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 16:33:47.829025 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 16:33:47.829079 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 16:33:47.829134 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1189 16:33:47.829189 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 16:33:47.829244 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 16:33:47.829298 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 16:33:47.829352 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 16:33:47.829407 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 16:33:47.829461 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 16:33:47.829516 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 16:33:47.829571 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
1197 16:33:47.829625 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1198 16:33:47.829684 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 16:33:47.829741 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 16:33:47.829796 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 16:33:47.829852 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 16:33:47.829935 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1203 16:33:47.829996 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1204 16:33:47.830097 0 10 8 | B1->B0 | 3131 2c2c | 1 0 | (1 0) (0 0)
1205 16:33:47.830185 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 16:33:47.830453 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 16:33:47.830586 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 16:33:47.830717 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 16:33:47.830849 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 16:33:47.830978 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 16:33:47.831113 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
1212 16:33:47.831245 0 11 8 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (1 1)
1213 16:33:47.831375 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1214 16:33:47.831505 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 16:33:47.831632 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 16:33:47.831728 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 16:33:47.831787 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 16:33:47.831843 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 16:33:47.831899 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1220 16:33:47.831955 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1221 16:33:47.832011 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 16:33:47.832066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 16:33:47.832121 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 16:33:47.832176 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 16:33:47.832230 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 16:33:47.832286 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 16:33:47.832357 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 16:33:47.832426 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 16:33:47.832481 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 16:33:47.832554 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 16:33:47.832623 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 16:33:47.832678 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 16:33:47.832733 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 16:33:47.832788 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 16:33:47.832842 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 16:33:47.832897 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1237 16:33:47.832952 Total UI for P1: 0, mck2ui 16
1238 16:33:47.833007 best dqsien dly found for B0: ( 0, 14, 6)
1239 16:33:47.833063 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 16:33:47.833117 Total UI for P1: 0, mck2ui 16
1241 16:33:47.833173 best dqsien dly found for B1: ( 0, 14, 10)
1242 16:33:47.833228 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1243 16:33:47.833283 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1244 16:33:47.833337
1245 16:33:47.833392 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1246 16:33:47.833446 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1247 16:33:47.833501 [Gating] SW calibration Done
1248 16:33:47.833555 ==
1249 16:33:47.833610 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 16:33:47.833665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1251 16:33:47.833721 ==
1252 16:33:47.833775 RX Vref Scan: 0
1253 16:33:47.833830
1254 16:33:47.833884 RX Vref 0 -> 0, step: 1
1255 16:33:47.833939
1256 16:33:47.833994 RX Delay -130 -> 252, step: 16
1257 16:33:47.834048 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1258 16:33:47.834103 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1259 16:33:47.834158 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1260 16:33:47.834256 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1261 16:33:47.834311 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1262 16:33:47.834366 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1263 16:33:47.834421 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1264 16:33:47.834476 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1265 16:33:47.834530 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1266 16:33:47.834585 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1267 16:33:47.834640 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1268 16:33:47.834695 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1269 16:33:47.834750 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1270 16:33:47.834804 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1271 16:33:47.834859 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1272 16:33:47.834914 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1273 16:33:47.834969 ==
1274 16:33:47.835023 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 16:33:47.835079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 16:33:47.835133 ==
1277 16:33:47.835188 DQS Delay:
1278 16:33:47.835242 DQS0 = 0, DQS1 = 0
1279 16:33:47.835297 DQM Delay:
1280 16:33:47.835351 DQM0 = 84, DQM1 = 78
1281 16:33:47.835405 DQ Delay:
1282 16:33:47.835459 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1283 16:33:47.835513 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1284 16:33:47.835568 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1285 16:33:47.835623 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1286 16:33:47.835677
1287 16:33:47.835731
1288 16:33:47.835785 ==
1289 16:33:47.835839 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 16:33:47.835894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 16:33:47.835949 ==
1292 16:33:47.836004
1293 16:33:47.836057
1294 16:33:47.836111 TX Vref Scan disable
1295 16:33:47.836164 == TX Byte 0 ==
1296 16:33:47.836218 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1297 16:33:47.836290 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1298 16:33:47.836375 == TX Byte 1 ==
1299 16:33:47.836430 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1300 16:33:47.836486 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1301 16:33:47.836541 ==
1302 16:33:47.836596 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 16:33:47.836652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 16:33:47.836737 ==
1305 16:33:47.836805 TX Vref=22, minBit 9, minWin=27, winSum=446
1306 16:33:47.836859 TX Vref=24, minBit 9, minWin=27, winSum=446
1307 16:33:47.836914 TX Vref=26, minBit 8, minWin=27, winSum=445
1308 16:33:47.836967 TX Vref=28, minBit 9, minWin=27, winSum=449
1309 16:33:47.837021 TX Vref=30, minBit 8, minWin=27, winSum=448
1310 16:33:47.837075 TX Vref=32, minBit 4, minWin=27, winSum=446
1311 16:33:47.837130 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 28
1312 16:33:47.837184
1313 16:33:47.837238 Final TX Range 1 Vref 28
1314 16:33:47.837316
1315 16:33:47.837416 ==
1316 16:33:47.837509 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 16:33:47.837768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 16:33:47.837905 ==
1319 16:33:47.838037
1320 16:33:47.838200
1321 16:33:47.838346 TX Vref Scan disable
1322 16:33:47.838448 == TX Byte 0 ==
1323 16:33:47.838535 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1324 16:33:47.838620 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1325 16:33:47.838741 == TX Byte 1 ==
1326 16:33:47.838800 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1327 16:33:47.838856 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1328 16:33:47.838911
1329 16:33:47.838965 [DATLAT]
1330 16:33:47.839019 Freq=800, CH0 RK1
1331 16:33:47.839075
1332 16:33:47.839129 DATLAT Default: 0xa
1333 16:33:47.839183 0, 0xFFFF, sum = 0
1334 16:33:47.839238 1, 0xFFFF, sum = 0
1335 16:33:47.839295 2, 0xFFFF, sum = 0
1336 16:33:47.839350 3, 0xFFFF, sum = 0
1337 16:33:47.839405 4, 0xFFFF, sum = 0
1338 16:33:47.839460 5, 0xFFFF, sum = 0
1339 16:33:47.839514 6, 0xFFFF, sum = 0
1340 16:33:47.839569 7, 0xFFFF, sum = 0
1341 16:33:47.839623 8, 0xFFFF, sum = 0
1342 16:33:47.839677 9, 0x0, sum = 1
1343 16:33:47.839733 10, 0x0, sum = 2
1344 16:33:47.839787 11, 0x0, sum = 3
1345 16:33:47.839843 12, 0x0, sum = 4
1346 16:33:47.839897 best_step = 10
1347 16:33:47.839952
1348 16:33:47.840005 ==
1349 16:33:47.840059 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 16:33:47.840113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 16:33:47.840168 ==
1352 16:33:47.840222 RX Vref Scan: 0
1353 16:33:47.840276
1354 16:33:47.840329 RX Vref 0 -> 0, step: 1
1355 16:33:47.840414
1356 16:33:47.840467 RX Delay -95 -> 252, step: 8
1357 16:33:47.840522 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1358 16:33:47.840577 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1359 16:33:47.840631 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1360 16:33:47.840685 iDelay=217, Bit 3, Center 76 (-39 ~ 192) 232
1361 16:33:47.840739 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1362 16:33:47.840794 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1363 16:33:47.840848 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1364 16:33:47.840902 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1365 16:33:47.840956 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1366 16:33:47.841010 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1367 16:33:47.841063 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1368 16:33:47.841117 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1369 16:33:47.841171 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1370 16:33:47.841225 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1371 16:33:47.841279 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1372 16:33:47.841333 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1373 16:33:47.841386 ==
1374 16:33:47.841440 Dram Type= 6, Freq= 0, CH_0, rank 1
1375 16:33:47.841498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 16:33:47.841560 ==
1377 16:33:47.841640 DQS Delay:
1378 16:33:47.841703 DQS0 = 0, DQS1 = 0
1379 16:33:47.841760 DQM Delay:
1380 16:33:47.841815 DQM0 = 84, DQM1 = 75
1381 16:33:47.841877 DQ Delay:
1382 16:33:47.841932 DQ0 =84, DQ1 =88, DQ2 =76, DQ3 =76
1383 16:33:47.841988 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1384 16:33:47.842063 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68
1385 16:33:47.842148 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1386 16:33:47.842217
1387 16:33:47.842274
1388 16:33:47.842329 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e04, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1389 16:33:47.842386 CH0 RK1: MR19=606, MR18=3E04
1390 16:33:47.842441 CH0_RK1: MR19=0x606, MR18=0x3E04, DQSOSC=394, MR23=63, INC=95, DEC=63
1391 16:33:47.842498 [RxdqsGatingPostProcess] freq 800
1392 16:33:47.842553 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1393 16:33:47.842608 Pre-setting of DQS Precalculation
1394 16:33:47.842673 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1395 16:33:47.842730 ==
1396 16:33:47.842785 Dram Type= 6, Freq= 0, CH_1, rank 0
1397 16:33:47.842840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 16:33:47.842896 ==
1399 16:33:47.842951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1400 16:33:47.843007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1401 16:33:47.843063 [CA 0] Center 36 (6~67) winsize 62
1402 16:33:47.843118 [CA 1] Center 36 (6~67) winsize 62
1403 16:33:47.843173 [CA 2] Center 34 (4~65) winsize 62
1404 16:33:47.843228 [CA 3] Center 34 (3~65) winsize 63
1405 16:33:47.843282 [CA 4] Center 34 (4~65) winsize 62
1406 16:33:47.843337 [CA 5] Center 34 (4~65) winsize 62
1407 16:33:47.843391
1408 16:33:47.843446 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1409 16:33:47.843501
1410 16:33:47.843555 [CATrainingPosCal] consider 1 rank data
1411 16:33:47.843610 u2DelayCellTimex100 = 270/100 ps
1412 16:33:47.843666 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1413 16:33:47.843721 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1414 16:33:47.843776 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1415 16:33:47.843832 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1416 16:33:47.843887 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1417 16:33:47.843943 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1418 16:33:47.843997
1419 16:33:47.844052 CA PerBit enable=1, Macro0, CA PI delay=34
1420 16:33:47.844108
1421 16:33:47.844163 [CBTSetCACLKResult] CA Dly = 34
1422 16:33:47.844219 CS Dly: 5 (0~36)
1423 16:33:47.844273 ==
1424 16:33:47.844329 Dram Type= 6, Freq= 0, CH_1, rank 1
1425 16:33:47.844384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 16:33:47.844439 ==
1427 16:33:47.844494 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1428 16:33:47.844550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1429 16:33:47.844604 [CA 0] Center 36 (6~67) winsize 62
1430 16:33:47.844690 [CA 1] Center 36 (6~67) winsize 62
1431 16:33:47.844746 [CA 2] Center 34 (4~65) winsize 62
1432 16:33:47.844801 [CA 3] Center 34 (3~65) winsize 63
1433 16:33:47.844856 [CA 4] Center 34 (4~65) winsize 62
1434 16:33:47.844912 [CA 5] Center 34 (4~65) winsize 62
1435 16:33:47.844993
1436 16:33:47.845050 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1437 16:33:47.845107
1438 16:33:47.845190 [CATrainingPosCal] consider 2 rank data
1439 16:33:47.845248 u2DelayCellTimex100 = 270/100 ps
1440 16:33:47.845324 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1441 16:33:47.845426 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1442 16:33:47.845496 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1443 16:33:47.845554 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1444 16:33:47.845611 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1445 16:33:47.845667 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1446 16:33:47.845722
1447 16:33:47.845777 CA PerBit enable=1, Macro0, CA PI delay=34
1448 16:33:47.845833
1449 16:33:47.845889 [CBTSetCACLKResult] CA Dly = 34
1450 16:33:47.845944 CS Dly: 6 (0~38)
1451 16:33:47.846000
1452 16:33:47.846054 ----->DramcWriteLeveling(PI) begin...
1453 16:33:47.846110 ==
1454 16:33:47.846379 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 16:33:47.846521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 16:33:47.846657 ==
1457 16:33:47.846790 Write leveling (Byte 0): 26 => 26
1458 16:33:47.846923 Write leveling (Byte 1): 28 => 28
1459 16:33:47.847009 DramcWriteLeveling(PI) end<-----
1460 16:33:47.847071
1461 16:33:47.847128 ==
1462 16:33:47.847201 Dram Type= 6, Freq= 0, CH_1, rank 0
1463 16:33:47.847266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1464 16:33:47.847323 ==
1465 16:33:47.847379 [Gating] SW mode calibration
1466 16:33:47.847435 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1467 16:33:47.847494 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1468 16:33:47.847550 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1469 16:33:47.847607 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1470 16:33:47.847662 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1471 16:33:47.847717 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 16:33:47.847773 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 16:33:47.847852 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 16:33:47.847909 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 16:33:47.847965 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 16:33:47.848055 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 16:33:47.848115 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 16:33:47.848172 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 16:33:47.848227 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 16:33:47.848283 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 16:33:47.848339 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 16:33:47.848394 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 16:33:47.848449 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 16:33:47.848504 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1485 16:33:47.848559 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1486 16:33:47.848613 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1487 16:33:47.848686 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 16:33:47.848765 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 16:33:47.848836 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 16:33:47.848914 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 16:33:47.848974 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 16:33:47.849030 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 16:33:47.849085 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 16:33:47.849140 0 9 8 | B1->B0 | 2b2b 302f | 0 1 | (0 0) (1 1)
1495 16:33:47.849196 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 16:33:47.849251 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 16:33:47.849307 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 16:33:47.849362 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 16:33:47.849416 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 16:33:47.849472 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1501 16:33:47.849528 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1502 16:33:47.849584 0 10 8 | B1->B0 | 2f2f 2626 | 0 0 | (1 1) (0 0)
1503 16:33:47.849639 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 16:33:47.849695 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 16:33:47.849750 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 16:33:47.849805 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 16:33:47.849860 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 16:33:47.849915 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 16:33:47.849970 0 11 4 | B1->B0 | 2424 2727 | 0 0 | (0 0) (1 1)
1510 16:33:47.850025 0 11 8 | B1->B0 | 3737 4040 | 0 0 | (1 1) (0 0)
1511 16:33:47.850080 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 16:33:47.850135 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 16:33:47.850205 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 16:33:47.850261 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 16:33:47.850316 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 16:33:47.850371 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 16:33:47.850426 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1518 16:33:47.850500 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1519 16:33:47.850558 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 16:33:47.850614 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 16:33:47.850670 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 16:33:47.850735 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 16:33:47.850804 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 16:33:47.850860 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 16:33:47.850916 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 16:33:47.850972 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 16:33:47.851026 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 16:33:47.851082 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 16:33:47.851137 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 16:33:47.851193 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 16:33:47.851248 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 16:33:47.851304 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 16:33:47.851360 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1534 16:33:47.851415 Total UI for P1: 0, mck2ui 16
1535 16:33:47.851472 best dqsien dly found for B0: ( 0, 14, 2)
1536 16:33:47.851528 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 16:33:47.851583 Total UI for P1: 0, mck2ui 16
1538 16:33:47.851638 best dqsien dly found for B1: ( 0, 14, 4)
1539 16:33:47.851694 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1540 16:33:47.851948 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1541 16:33:47.852084
1542 16:33:47.852216 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1543 16:33:47.852348 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1544 16:33:47.852480 [Gating] SW calibration Done
1545 16:33:47.852603 ==
1546 16:33:47.852663 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 16:33:47.852728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1548 16:33:47.852787 ==
1549 16:33:47.852843 RX Vref Scan: 0
1550 16:33:47.852899
1551 16:33:47.852963 RX Vref 0 -> 0, step: 1
1552 16:33:47.853019
1553 16:33:47.853074 RX Delay -130 -> 252, step: 16
1554 16:33:47.853137 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1555 16:33:47.853194 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1556 16:33:47.853250 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1557 16:33:47.853312 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1558 16:33:47.853368 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1559 16:33:47.853423 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1560 16:33:47.853484 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1561 16:33:47.853570 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1562 16:33:47.853656 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1563 16:33:47.853741 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1564 16:33:47.853826 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1565 16:33:47.853889 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1566 16:33:47.853946 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1567 16:33:47.854001 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1568 16:33:47.854057 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1569 16:33:47.854112 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1570 16:33:47.854182 ==
1571 16:33:47.854240 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 16:33:47.854296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 16:33:47.854353 ==
1574 16:33:47.854407 DQS Delay:
1575 16:33:47.854462 DQS0 = 0, DQS1 = 0
1576 16:33:47.854517 DQM Delay:
1577 16:33:47.854572 DQM0 = 89, DQM1 = 77
1578 16:33:47.854627 DQ Delay:
1579 16:33:47.854682 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1580 16:33:47.854737 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1581 16:33:47.854792 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1582 16:33:47.854848 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1583 16:33:47.854903
1584 16:33:47.854957
1585 16:33:47.855012 ==
1586 16:33:47.855067 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 16:33:47.855122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 16:33:47.855177 ==
1589 16:33:47.855232
1590 16:33:47.855286
1591 16:33:47.855341 TX Vref Scan disable
1592 16:33:47.855395 == TX Byte 0 ==
1593 16:33:47.855450 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1594 16:33:47.855506 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1595 16:33:47.855562 == TX Byte 1 ==
1596 16:33:47.855616 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1597 16:33:47.855671 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1598 16:33:47.855726 ==
1599 16:33:47.855781 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 16:33:47.855838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 16:33:47.855894 ==
1602 16:33:47.855949 TX Vref=22, minBit 10, minWin=26, winSum=439
1603 16:33:47.856005 TX Vref=24, minBit 15, minWin=26, winSum=444
1604 16:33:47.856061 TX Vref=26, minBit 8, minWin=27, winSum=447
1605 16:33:47.856116 TX Vref=28, minBit 9, minWin=27, winSum=451
1606 16:33:47.856172 TX Vref=30, minBit 9, minWin=27, winSum=450
1607 16:33:47.856227 TX Vref=32, minBit 9, minWin=27, winSum=446
1608 16:33:47.856282 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 28
1609 16:33:47.856345
1610 16:33:47.856403 Final TX Range 1 Vref 28
1611 16:33:47.856459
1612 16:33:47.856514 ==
1613 16:33:47.856569 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 16:33:47.856624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 16:33:47.856679 ==
1616 16:33:47.856734
1617 16:33:47.856788
1618 16:33:47.856842 TX Vref Scan disable
1619 16:33:47.856898 == TX Byte 0 ==
1620 16:33:47.856953 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1621 16:33:47.857013 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1622 16:33:47.857068 == TX Byte 1 ==
1623 16:33:47.857123 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1624 16:33:47.857179 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1625 16:33:47.857234
1626 16:33:47.857289 [DATLAT]
1627 16:33:47.857343 Freq=800, CH1 RK0
1628 16:33:47.857399
1629 16:33:47.857453 DATLAT Default: 0xa
1630 16:33:47.857508 0, 0xFFFF, sum = 0
1631 16:33:47.857565 1, 0xFFFF, sum = 0
1632 16:33:47.857621 2, 0xFFFF, sum = 0
1633 16:33:47.857677 3, 0xFFFF, sum = 0
1634 16:33:47.857733 4, 0xFFFF, sum = 0
1635 16:33:47.857789 5, 0xFFFF, sum = 0
1636 16:33:47.857844 6, 0xFFFF, sum = 0
1637 16:33:47.857899 7, 0xFFFF, sum = 0
1638 16:33:47.857955 8, 0xFFFF, sum = 0
1639 16:33:47.858011 9, 0x0, sum = 1
1640 16:33:47.858066 10, 0x0, sum = 2
1641 16:33:47.858122 11, 0x0, sum = 3
1642 16:33:47.858189 12, 0x0, sum = 4
1643 16:33:47.858247 best_step = 10
1644 16:33:47.858302
1645 16:33:47.858367 ==
1646 16:33:47.858464 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 16:33:47.858548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 16:33:47.858607 ==
1649 16:33:47.858664 RX Vref Scan: 1
1650 16:33:47.858719
1651 16:33:47.858774 Set Vref Range= 32 -> 127
1652 16:33:47.858829
1653 16:33:47.858884 RX Vref 32 -> 127, step: 1
1654 16:33:47.858939
1655 16:33:47.858994 RX Delay -95 -> 252, step: 8
1656 16:33:47.859049
1657 16:33:47.859104 Set Vref, RX VrefLevel [Byte0]: 32
1658 16:33:47.859159 [Byte1]: 32
1659 16:33:47.859214
1660 16:33:47.859269 Set Vref, RX VrefLevel [Byte0]: 33
1661 16:33:47.859324 [Byte1]: 33
1662 16:33:47.859380
1663 16:33:47.859438 Set Vref, RX VrefLevel [Byte0]: 34
1664 16:33:47.859493 [Byte1]: 34
1665 16:33:47.859548
1666 16:33:47.859602 Set Vref, RX VrefLevel [Byte0]: 35
1667 16:33:47.859658 [Byte1]: 35
1668 16:33:47.859713
1669 16:33:47.859767 Set Vref, RX VrefLevel [Byte0]: 36
1670 16:33:47.859822 [Byte1]: 36
1671 16:33:47.859877
1672 16:33:47.859932 Set Vref, RX VrefLevel [Byte0]: 37
1673 16:33:47.859987 [Byte1]: 37
1674 16:33:47.860041
1675 16:33:47.860096 Set Vref, RX VrefLevel [Byte0]: 38
1676 16:33:47.860150 [Byte1]: 38
1677 16:33:47.860205
1678 16:33:47.860260 Set Vref, RX VrefLevel [Byte0]: 39
1679 16:33:47.860315 [Byte1]: 39
1680 16:33:47.860370
1681 16:33:47.860425 Set Vref, RX VrefLevel [Byte0]: 40
1682 16:33:47.860480 [Byte1]: 40
1683 16:33:47.860534
1684 16:33:47.860589 Set Vref, RX VrefLevel [Byte0]: 41
1685 16:33:47.860644 [Byte1]: 41
1686 16:33:47.860700
1687 16:33:47.860754 Set Vref, RX VrefLevel [Byte0]: 42
1688 16:33:47.860809 [Byte1]: 42
1689 16:33:47.860863
1690 16:33:47.860918 Set Vref, RX VrefLevel [Byte0]: 43
1691 16:33:47.860973 [Byte1]: 43
1692 16:33:47.861028
1693 16:33:47.861083 Set Vref, RX VrefLevel [Byte0]: 44
1694 16:33:47.861138 [Byte1]: 44
1695 16:33:47.861193
1696 16:33:47.861247 Set Vref, RX VrefLevel [Byte0]: 45
1697 16:33:47.861498 [Byte1]: 45
1698 16:33:47.861561
1699 16:33:47.861617 Set Vref, RX VrefLevel [Byte0]: 46
1700 16:33:47.861672 [Byte1]: 46
1701 16:33:47.861727
1702 16:33:47.861782 Set Vref, RX VrefLevel [Byte0]: 47
1703 16:33:47.861837 [Byte1]: 47
1704 16:33:47.861892
1705 16:33:47.861946 Set Vref, RX VrefLevel [Byte0]: 48
1706 16:33:47.862001 [Byte1]: 48
1707 16:33:47.862056
1708 16:33:47.862111 Set Vref, RX VrefLevel [Byte0]: 49
1709 16:33:47.862174 [Byte1]: 49
1710 16:33:47.862231
1711 16:33:47.862287 Set Vref, RX VrefLevel [Byte0]: 50
1712 16:33:47.862342 [Byte1]: 50
1713 16:33:47.862396
1714 16:33:47.862451 Set Vref, RX VrefLevel [Byte0]: 51
1715 16:33:47.862518 [Byte1]: 51
1716 16:33:47.862618
1717 16:33:47.862691 Set Vref, RX VrefLevel [Byte0]: 52
1718 16:33:47.862749 [Byte1]: 52
1719 16:33:47.862804
1720 16:33:47.862859 Set Vref, RX VrefLevel [Byte0]: 53
1721 16:33:47.862915 [Byte1]: 53
1722 16:33:47.862970
1723 16:33:47.863024 Set Vref, RX VrefLevel [Byte0]: 54
1724 16:33:47.863080 [Byte1]: 54
1725 16:33:47.863137
1726 16:33:47.863192 Set Vref, RX VrefLevel [Byte0]: 55
1727 16:33:47.863247 [Byte1]: 55
1728 16:33:47.863311
1729 16:33:47.863374 Set Vref, RX VrefLevel [Byte0]: 56
1730 16:33:47.863430 [Byte1]: 56
1731 16:33:47.863485
1732 16:33:47.863540 Set Vref, RX VrefLevel [Byte0]: 57
1733 16:33:47.863601 [Byte1]: 57
1734 16:33:47.863656
1735 16:33:47.863711 Set Vref, RX VrefLevel [Byte0]: 58
1736 16:33:47.863771 [Byte1]: 58
1737 16:33:47.863827
1738 16:33:47.863882 Set Vref, RX VrefLevel [Byte0]: 59
1739 16:33:47.863941 [Byte1]: 59
1740 16:33:47.863997
1741 16:33:47.864052 Set Vref, RX VrefLevel [Byte0]: 60
1742 16:33:47.864111 [Byte1]: 60
1743 16:33:47.864170
1744 16:33:47.864225 Set Vref, RX VrefLevel [Byte0]: 61
1745 16:33:47.864280 [Byte1]: 61
1746 16:33:47.864339
1747 16:33:47.864393 Set Vref, RX VrefLevel [Byte0]: 62
1748 16:33:47.864449 [Byte1]: 62
1749 16:33:47.864506
1750 16:33:47.864561 Set Vref, RX VrefLevel [Byte0]: 63
1751 16:33:47.864617 [Byte1]: 63
1752 16:33:47.864671
1753 16:33:47.864726 Set Vref, RX VrefLevel [Byte0]: 64
1754 16:33:47.864781 [Byte1]: 64
1755 16:33:47.864836
1756 16:33:47.864890 Set Vref, RX VrefLevel [Byte0]: 65
1757 16:33:47.864945 [Byte1]: 65
1758 16:33:47.865000
1759 16:33:47.865055 Set Vref, RX VrefLevel [Byte0]: 66
1760 16:33:47.865110 [Byte1]: 66
1761 16:33:47.865164
1762 16:33:47.865219 Set Vref, RX VrefLevel [Byte0]: 67
1763 16:33:47.865274 [Byte1]: 67
1764 16:33:47.865329
1765 16:33:47.865383 Set Vref, RX VrefLevel [Byte0]: 68
1766 16:33:47.865438 [Byte1]: 68
1767 16:33:47.865492
1768 16:33:47.865547 Set Vref, RX VrefLevel [Byte0]: 69
1769 16:33:47.865602 [Byte1]: 69
1770 16:33:47.865657
1771 16:33:47.865712 Set Vref, RX VrefLevel [Byte0]: 70
1772 16:33:47.865767 [Byte1]: 70
1773 16:33:47.865821
1774 16:33:47.865875 Set Vref, RX VrefLevel [Byte0]: 71
1775 16:33:47.865930 [Byte1]: 71
1776 16:33:47.865984
1777 16:33:47.866038 Set Vref, RX VrefLevel [Byte0]: 72
1778 16:33:47.866093 [Byte1]: 72
1779 16:33:47.866147
1780 16:33:47.866213 Set Vref, RX VrefLevel [Byte0]: 73
1781 16:33:47.866269 [Byte1]: 73
1782 16:33:47.866324
1783 16:33:47.866378 Set Vref, RX VrefLevel [Byte0]: 74
1784 16:33:47.866433 [Byte1]: 74
1785 16:33:47.866487
1786 16:33:47.866542 Final RX Vref Byte 0 = 52 to rank0
1787 16:33:47.866597 Final RX Vref Byte 1 = 64 to rank0
1788 16:33:47.866652 Final RX Vref Byte 0 = 52 to rank1
1789 16:33:47.866707 Final RX Vref Byte 1 = 64 to rank1==
1790 16:33:47.866762 Dram Type= 6, Freq= 0, CH_1, rank 0
1791 16:33:47.866817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 16:33:47.866896 ==
1793 16:33:47.866980 DQS Delay:
1794 16:33:47.867065 DQS0 = 0, DQS1 = 0
1795 16:33:47.867149 DQM Delay:
1796 16:33:47.867235 DQM0 = 86, DQM1 = 79
1797 16:33:47.867321 DQ Delay:
1798 16:33:47.867381 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1799 16:33:47.867437 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1800 16:33:47.867492 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1801 16:33:47.867548 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1802 16:33:47.867603
1803 16:33:47.867657
1804 16:33:47.867715 [DQSOSCAuto] RK0, (LSB)MR18= 0x3521, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1805 16:33:47.867772 CH1 RK0: MR19=606, MR18=3521
1806 16:33:47.867827 CH1_RK0: MR19=0x606, MR18=0x3521, DQSOSC=396, MR23=63, INC=94, DEC=62
1807 16:33:47.867882
1808 16:33:47.867936 ----->DramcWriteLeveling(PI) begin...
1809 16:33:47.867993 ==
1810 16:33:47.868048 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 16:33:47.868104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 16:33:47.868159 ==
1813 16:33:47.868217 Write leveling (Byte 0): 28 => 28
1814 16:33:47.868273 Write leveling (Byte 1): 29 => 29
1815 16:33:47.868339 DramcWriteLeveling(PI) end<-----
1816 16:33:47.868395
1817 16:33:47.868450 ==
1818 16:33:47.868505 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 16:33:47.868560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 16:33:47.868615 ==
1821 16:33:47.868670 [Gating] SW mode calibration
1822 16:33:47.868725 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1823 16:33:47.868781 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1824 16:33:47.868836 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1825 16:33:47.868891 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1826 16:33:47.868947 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1827 16:33:47.869003 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 16:33:47.869098 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 16:33:47.869159 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 16:33:47.869229 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 16:33:47.869299 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 16:33:47.869363 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 16:33:47.869435 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 16:33:47.869491 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 16:33:47.869547 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 16:33:47.869602 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 16:33:47.869856 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 16:33:47.869994 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 16:33:47.870130 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 16:33:47.870281 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 16:33:47.870416 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1842 16:33:47.870549 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1843 16:33:47.870683 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 16:33:47.870815 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 16:33:47.870948 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 16:33:47.871022 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 16:33:47.871080 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 16:33:47.871136 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 16:33:47.871192 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 16:33:47.871248 0 9 8 | B1->B0 | 3333 2727 | 1 1 | (1 1) (1 1)
1851 16:33:47.871304 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 16:33:47.871360 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 16:33:47.871416 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 16:33:47.871472 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 16:33:47.871527 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 16:33:47.871582 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 16:33:47.871638 0 10 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1858 16:33:47.871693 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 0)
1859 16:33:47.871748 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 16:33:47.871803 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 16:33:47.871863 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 16:33:47.871918 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 16:33:47.871974 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 16:33:47.872028 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 16:33:47.872083 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1866 16:33:47.872139 0 11 8 | B1->B0 | 3c3c 3636 | 0 0 | (0 0) (0 0)
1867 16:33:47.872194 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 16:33:47.872249 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 16:33:47.872304 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 16:33:47.872359 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 16:33:47.872414 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 16:33:47.872470 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 16:33:47.872525 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1874 16:33:47.872580 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1875 16:33:47.872635 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 16:33:47.872690 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 16:33:47.872744 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 16:33:47.872800 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 16:33:47.872856 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 16:33:47.872912 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 16:33:47.872967 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 16:33:47.873022 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 16:33:47.873077 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 16:33:47.873133 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 16:33:47.873188 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 16:33:47.873243 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 16:33:47.873298 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 16:33:47.873354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 16:33:47.873408 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1890 16:33:47.873464 Total UI for P1: 0, mck2ui 16
1891 16:33:47.873520 best dqsien dly found for B1: ( 0, 14, 2)
1892 16:33:47.873576 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1893 16:33:47.873631 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 16:33:47.873687 Total UI for P1: 0, mck2ui 16
1895 16:33:47.873742 best dqsien dly found for B0: ( 0, 14, 6)
1896 16:33:47.873798 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1897 16:33:47.873854 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1898 16:33:47.873909
1899 16:33:47.873972 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1900 16:33:47.874058 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1901 16:33:47.874143 [Gating] SW calibration Done
1902 16:33:47.874214 ==
1903 16:33:47.874275 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 16:33:47.874335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 16:33:47.874391 ==
1906 16:33:47.874449 RX Vref Scan: 0
1907 16:33:47.874508
1908 16:33:47.874563 RX Vref 0 -> 0, step: 1
1909 16:33:47.874619
1910 16:33:47.874676 RX Delay -130 -> 252, step: 16
1911 16:33:47.874732 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1912 16:33:47.874788 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1913 16:33:47.874844 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1914 16:33:47.874903 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1915 16:33:47.874958 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1916 16:33:48.287737 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1917 16:33:48.287908 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1918 16:33:48.288012 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1919 16:33:48.288110 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1920 16:33:48.288201 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1921 16:33:48.288290 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1922 16:33:48.288381 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1923 16:33:48.288490 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1924 16:33:48.288584 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1925 16:33:48.288677 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1926 16:33:48.288764 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1927 16:33:48.288848 ==
1928 16:33:48.288937 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 16:33:48.289241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 16:33:48.289336 ==
1931 16:33:48.289427 DQS Delay:
1932 16:33:48.289521 DQS0 = 0, DQS1 = 0
1933 16:33:48.289619 DQM Delay:
1934 16:33:48.289711 DQM0 = 86, DQM1 = 78
1935 16:33:48.289797 DQ Delay:
1936 16:33:48.289882 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =77
1937 16:33:48.289973 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1938 16:33:48.290061 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1939 16:33:48.290146 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1940 16:33:48.290219
1941 16:33:48.290279
1942 16:33:48.290338 ==
1943 16:33:48.290396 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 16:33:48.290452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 16:33:48.290508 ==
1946 16:33:48.290566
1947 16:33:48.290624
1948 16:33:48.290681 TX Vref Scan disable
1949 16:33:48.290736 == TX Byte 0 ==
1950 16:33:48.290795 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1951 16:33:48.290851 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1952 16:33:48.290924 == TX Byte 1 ==
1953 16:33:48.290990 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1954 16:33:48.291049 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1955 16:33:48.291106 ==
1956 16:33:48.291161 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 16:33:48.291217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 16:33:48.291272 ==
1959 16:33:48.291330 TX Vref=22, minBit 8, minWin=26, winSum=445
1960 16:33:48.291390 TX Vref=24, minBit 8, minWin=27, winSum=449
1961 16:33:48.291448 TX Vref=26, minBit 13, minWin=27, winSum=450
1962 16:33:48.291503 TX Vref=28, minBit 15, minWin=27, winSum=456
1963 16:33:48.291564 TX Vref=30, minBit 9, minWin=27, winSum=453
1964 16:33:48.291621 TX Vref=32, minBit 9, minWin=27, winSum=445
1965 16:33:48.291677 [TxChooseVref] Worse bit 15, Min win 27, Win sum 456, Final Vref 28
1966 16:33:48.291733
1967 16:33:48.291791 Final TX Range 1 Vref 28
1968 16:33:48.291850
1969 16:33:48.291906 ==
1970 16:33:48.291961 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 16:33:48.292017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 16:33:48.292072 ==
1973 16:33:48.292127
1974 16:33:48.292185
1975 16:33:48.292242 TX Vref Scan disable
1976 16:33:48.292299 == TX Byte 0 ==
1977 16:33:48.292353 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1978 16:33:48.292409 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1979 16:33:48.292478 == TX Byte 1 ==
1980 16:33:48.292549 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1981 16:33:48.292609 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1982 16:33:48.292666
1983 16:33:48.292721 [DATLAT]
1984 16:33:48.292779 Freq=800, CH1 RK1
1985 16:33:48.292834
1986 16:33:48.292889 DATLAT Default: 0xa
1987 16:33:48.292947 0, 0xFFFF, sum = 0
1988 16:33:48.293007 1, 0xFFFF, sum = 0
1989 16:33:48.293066 2, 0xFFFF, sum = 0
1990 16:33:48.293124 3, 0xFFFF, sum = 0
1991 16:33:48.293180 4, 0xFFFF, sum = 0
1992 16:33:48.293238 5, 0xFFFF, sum = 0
1993 16:33:48.293297 6, 0xFFFF, sum = 0
1994 16:33:48.293355 7, 0xFFFF, sum = 0
1995 16:33:48.293415 8, 0xFFFF, sum = 0
1996 16:33:48.293473 9, 0x0, sum = 1
1997 16:33:48.293529 10, 0x0, sum = 2
1998 16:33:48.293587 11, 0x0, sum = 3
1999 16:33:48.293644 12, 0x0, sum = 4
2000 16:33:48.293699 best_step = 10
2001 16:33:48.293754
2002 16:33:48.293811 ==
2003 16:33:48.293872 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 16:33:48.293927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 16:33:48.293986 ==
2006 16:33:48.294043 RX Vref Scan: 0
2007 16:33:48.294098
2008 16:33:48.294155 RX Vref 0 -> 0, step: 1
2009 16:33:48.294223
2010 16:33:48.294281 RX Delay -95 -> 252, step: 8
2011 16:33:48.294367 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2012 16:33:48.294426 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2013 16:33:48.294483 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2014 16:33:48.294548 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2015 16:33:48.294606 iDelay=217, Bit 4, Center 88 (-23 ~ 200) 224
2016 16:33:48.294662 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2017 16:33:48.294718 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2018 16:33:48.294775 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2019 16:33:48.294831 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2020 16:33:48.294890 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2021 16:33:48.294949 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2022 16:33:48.295006 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2023 16:33:48.295062 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2024 16:33:48.295121 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2025 16:33:48.295177 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2026 16:33:48.295233 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2027 16:33:48.295292 ==
2028 16:33:48.295349 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 16:33:48.295405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 16:33:48.295464 ==
2031 16:33:48.295520 DQS Delay:
2032 16:33:48.295579 DQS0 = 0, DQS1 = 0
2033 16:33:48.295636 DQM Delay:
2034 16:33:48.295691 DQM0 = 87, DQM1 = 78
2035 16:33:48.295746 DQ Delay:
2036 16:33:48.295802 DQ0 =88, DQ1 =80, DQ2 =80, DQ3 =84
2037 16:33:48.295858 DQ4 =88, DQ5 =96, DQ6 =100, DQ7 =84
2038 16:33:48.295913 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2039 16:33:48.295972 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2040 16:33:48.296033
2041 16:33:48.296088
2042 16:33:48.296146 [DQSOSCAuto] RK1, (LSB)MR18= 0x170f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2043 16:33:48.296203 CH1 RK1: MR19=606, MR18=170F
2044 16:33:48.296258 CH1_RK1: MR19=0x606, MR18=0x170F, DQSOSC=404, MR23=63, INC=90, DEC=60
2045 16:33:48.296315 [RxdqsGatingPostProcess] freq 800
2046 16:33:48.296373 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2047 16:33:48.296431 Pre-setting of DQS Precalculation
2048 16:33:48.296487 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2049 16:33:48.296559 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2050 16:33:48.296634 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2051 16:33:48.296692
2052 16:33:48.296748
2053 16:33:48.296803 [Calibration Summary] 1600 Mbps
2054 16:33:48.296859 CH 0, Rank 0
2055 16:33:48.296918 SW Impedance : PASS
2056 16:33:48.296978 DUTY Scan : NO K
2057 16:33:48.297036 ZQ Calibration : PASS
2058 16:33:48.297091 Jitter Meter : NO K
2059 16:33:48.297147 CBT Training : PASS
2060 16:33:48.297206 Write leveling : PASS
2061 16:33:48.297262 RX DQS gating : PASS
2062 16:33:48.297317 RX DQ/DQS(RDDQC) : PASS
2063 16:33:48.297374 TX DQ/DQS : PASS
2064 16:33:48.297433 RX DATLAT : PASS
2065 16:33:48.297491 RX DQ/DQS(Engine): PASS
2066 16:33:48.297546 TX OE : NO K
2067 16:33:48.297602 All Pass.
2068 16:33:48.297658
2069 16:33:48.297729 CH 0, Rank 1
2070 16:33:48.297795 SW Impedance : PASS
2071 16:33:48.297854 DUTY Scan : NO K
2072 16:33:48.297910 ZQ Calibration : PASS
2073 16:33:48.297966 Jitter Meter : NO K
2074 16:33:48.298022 CBT Training : PASS
2075 16:33:48.298077 Write leveling : PASS
2076 16:33:48.298337 RX DQS gating : PASS
2077 16:33:48.298404 RX DQ/DQS(RDDQC) : PASS
2078 16:33:48.298465 TX DQ/DQS : PASS
2079 16:33:48.298523 RX DATLAT : PASS
2080 16:33:48.298580 RX DQ/DQS(Engine): PASS
2081 16:33:48.298636 TX OE : NO K
2082 16:33:48.298692 All Pass.
2083 16:33:48.298748
2084 16:33:48.298807 CH 1, Rank 0
2085 16:33:48.298867 SW Impedance : PASS
2086 16:33:48.298924 DUTY Scan : NO K
2087 16:33:48.298982 ZQ Calibration : PASS
2088 16:33:48.299038 Jitter Meter : NO K
2089 16:33:48.299093 CBT Training : PASS
2090 16:33:48.299149 Write leveling : PASS
2091 16:33:48.299208 RX DQS gating : PASS
2092 16:33:48.299266 RX DQ/DQS(RDDQC) : PASS
2093 16:33:48.299322 TX DQ/DQS : PASS
2094 16:33:48.299381 RX DATLAT : PASS
2095 16:33:48.299436 RX DQ/DQS(Engine): PASS
2096 16:33:48.299491 TX OE : NO K
2097 16:33:48.299547 All Pass.
2098 16:33:48.299606
2099 16:33:48.299663 CH 1, Rank 1
2100 16:33:48.299718 SW Impedance : PASS
2101 16:33:48.299774 DUTY Scan : NO K
2102 16:33:48.299833 ZQ Calibration : PASS
2103 16:33:48.299888 Jitter Meter : NO K
2104 16:33:48.299944 CBT Training : PASS
2105 16:33:48.299999 Write leveling : PASS
2106 16:33:48.300058 RX DQS gating : PASS
2107 16:33:48.300115 RX DQ/DQS(RDDQC) : PASS
2108 16:33:48.300169 TX DQ/DQS : PASS
2109 16:33:48.300228 RX DATLAT : PASS
2110 16:33:48.300283 RX DQ/DQS(Engine): PASS
2111 16:33:48.300338 TX OE : NO K
2112 16:33:48.300397 All Pass.
2113 16:33:48.300456
2114 16:33:48.300513 DramC Write-DBI off
2115 16:33:48.300569 PER_BANK_REFRESH: Hybrid Mode
2116 16:33:48.300625 TX_TRACKING: ON
2117 16:33:48.300690 [GetDramInforAfterCalByMRR] Vendor 6.
2118 16:33:48.300765 [GetDramInforAfterCalByMRR] Revision 606.
2119 16:33:48.300829 [GetDramInforAfterCalByMRR] Revision 2 0.
2120 16:33:48.300887 MR0 0x3b3b
2121 16:33:48.300945 MR8 0x5151
2122 16:33:48.301004 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 16:33:48.301061
2124 16:33:48.301117 MR0 0x3b3b
2125 16:33:48.301197 MR8 0x5151
2126 16:33:48.301259 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2127 16:33:48.301318
2128 16:33:48.301375 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2129 16:33:48.301432 [FAST_K] Save calibration result to emmc
2130 16:33:48.301488 [FAST_K] Save calibration result to emmc
2131 16:33:48.301544 dram_init: config_dvfs: 1
2132 16:33:48.301603 dramc_set_vcore_voltage set vcore to 662500
2133 16:33:48.301663 Read voltage for 1200, 2
2134 16:33:48.301719 Vio18 = 0
2135 16:33:48.301775 Vcore = 662500
2136 16:33:48.301830 Vdram = 0
2137 16:33:48.301885 Vddq = 0
2138 16:33:48.301941 Vmddr = 0
2139 16:33:48.301998 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2140 16:33:48.302059 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2141 16:33:48.302116 MEM_TYPE=3, freq_sel=15
2142 16:33:48.302182 sv_algorithm_assistance_LP4_1600
2143 16:33:48.302241 ============ PULL DRAM RESETB DOWN ============
2144 16:33:48.302297 ========== PULL DRAM RESETB DOWN end =========
2145 16:33:48.302357 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2146 16:33:48.302415 ===================================
2147 16:33:48.302471 LPDDR4 DRAM CONFIGURATION
2148 16:33:48.302530 ===================================
2149 16:33:48.302585 EX_ROW_EN[0] = 0x0
2150 16:33:48.302644 EX_ROW_EN[1] = 0x0
2151 16:33:48.302699 LP4Y_EN = 0x0
2152 16:33:48.302755 WORK_FSP = 0x0
2153 16:33:48.302814 WL = 0x4
2154 16:33:48.302871 RL = 0x4
2155 16:33:48.302926 BL = 0x2
2156 16:33:48.302981 RPST = 0x0
2157 16:33:48.303039 RD_PRE = 0x0
2158 16:33:48.303094 WR_PRE = 0x1
2159 16:33:48.303149 WR_PST = 0x0
2160 16:33:48.303207 DBI_WR = 0x0
2161 16:33:48.303265 DBI_RD = 0x0
2162 16:33:48.303320 OTF = 0x1
2163 16:33:48.303375 ===================================
2164 16:33:48.303436 ===================================
2165 16:33:48.303497 ANA top config
2166 16:33:48.303553 ===================================
2167 16:33:48.303611 DLL_ASYNC_EN = 0
2168 16:33:48.303675 ALL_SLAVE_EN = 0
2169 16:33:48.303730 NEW_RANK_MODE = 1
2170 16:33:48.303792 DLL_IDLE_MODE = 1
2171 16:33:48.303847 LP45_APHY_COMB_EN = 1
2172 16:33:48.303902 TX_ODT_DIS = 1
2173 16:33:48.303961 NEW_8X_MODE = 1
2174 16:33:48.304019 ===================================
2175 16:33:48.304075 ===================================
2176 16:33:48.304130 data_rate = 2400
2177 16:33:48.304185 CKR = 1
2178 16:33:48.304241 DQ_P2S_RATIO = 8
2179 16:33:48.304299 ===================================
2180 16:33:48.304358 CA_P2S_RATIO = 8
2181 16:33:48.304415 DQ_CA_OPEN = 0
2182 16:33:48.304471 DQ_SEMI_OPEN = 0
2183 16:33:48.304539 CA_SEMI_OPEN = 0
2184 16:33:48.304606 CA_FULL_RATE = 0
2185 16:33:48.304695 DQ_CKDIV4_EN = 0
2186 16:33:48.304755 CA_CKDIV4_EN = 0
2187 16:33:48.304811 CA_PREDIV_EN = 0
2188 16:33:48.304870 PH8_DLY = 17
2189 16:33:48.304926 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2190 16:33:48.304982 DQ_AAMCK_DIV = 4
2191 16:33:48.305040 CA_AAMCK_DIV = 4
2192 16:33:48.305099 CA_ADMCK_DIV = 4
2193 16:33:48.305157 DQ_TRACK_CA_EN = 0
2194 16:33:48.305213 CA_PICK = 1200
2195 16:33:48.305268 CA_MCKIO = 1200
2196 16:33:48.305327 MCKIO_SEMI = 0
2197 16:33:48.305387 PLL_FREQ = 2366
2198 16:33:48.305444 DQ_UI_PI_RATIO = 32
2199 16:33:48.305500 CA_UI_PI_RATIO = 0
2200 16:33:48.305555 ===================================
2201 16:33:48.305611 ===================================
2202 16:33:48.305666 memory_type:LPDDR4
2203 16:33:48.305725 GP_NUM : 10
2204 16:33:48.305783 SRAM_EN : 1
2205 16:33:48.305841 MD32_EN : 0
2206 16:33:48.305895 ===================================
2207 16:33:48.305951 [ANA_INIT] >>>>>>>>>>>>>>
2208 16:33:48.306006 <<<<<< [CONFIGURE PHASE]: ANA_TX
2209 16:33:48.306063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2210 16:33:48.306124 ===================================
2211 16:33:48.306201 data_rate = 2400,PCW = 0X5b00
2212 16:33:48.306259 ===================================
2213 16:33:48.306315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2214 16:33:48.306371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 16:33:48.306427 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2216 16:33:48.306486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2217 16:33:48.306744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2218 16:33:48.306810 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2219 16:33:48.306871 [ANA_INIT] flow start
2220 16:33:48.306929 [ANA_INIT] PLL >>>>>>>>
2221 16:33:48.306986 [ANA_INIT] PLL <<<<<<<<
2222 16:33:48.307042 [ANA_INIT] MIDPI >>>>>>>>
2223 16:33:48.307098 [ANA_INIT] MIDPI <<<<<<<<
2224 16:33:48.307157 [ANA_INIT] DLL >>>>>>>>
2225 16:33:48.307214 [ANA_INIT] DLL <<<<<<<<
2226 16:33:48.307270 [ANA_INIT] flow end
2227 16:33:48.307329 ============ LP4 DIFF to SE enter ============
2228 16:33:48.307386 ============ LP4 DIFF to SE exit ============
2229 16:33:48.307442 [ANA_INIT] <<<<<<<<<<<<<
2230 16:33:48.307498 [Flow] Enable top DCM control >>>>>
2231 16:33:48.307557 [Flow] Enable top DCM control <<<<<
2232 16:33:48.307615 Enable DLL master slave shuffle
2233 16:33:48.307670 ==============================================================
2234 16:33:48.307755 Gating Mode config
2235 16:33:48.307814 ==============================================================
2236 16:33:48.307871 Config description:
2237 16:33:48.307926 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2238 16:33:48.307987 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2239 16:33:48.308049 SELPH_MODE 0: By rank 1: By Phase
2240 16:33:48.308106 ==============================================================
2241 16:33:48.308163 GAT_TRACK_EN = 1
2242 16:33:48.308218 RX_GATING_MODE = 2
2243 16:33:48.308288 RX_GATING_TRACK_MODE = 2
2244 16:33:48.308349 SELPH_MODE = 1
2245 16:33:48.308409 PICG_EARLY_EN = 1
2246 16:33:48.308467 VALID_LAT_VALUE = 1
2247 16:33:48.308523 ==============================================================
2248 16:33:48.308607 Enter into Gating configuration >>>>
2249 16:33:48.308667 Exit from Gating configuration <<<<
2250 16:33:48.308726 Enter into DVFS_PRE_config >>>>>
2251 16:33:48.308787 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2252 16:33:48.308847 Exit from DVFS_PRE_config <<<<<
2253 16:33:48.308903 Enter into PICG configuration >>>>
2254 16:33:48.308959 Exit from PICG configuration <<<<
2255 16:33:48.309015 [RX_INPUT] configuration >>>>>
2256 16:33:48.309071 [RX_INPUT] configuration <<<<<
2257 16:33:48.309133 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2258 16:33:48.309192 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2259 16:33:48.309248 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 16:33:48.309304 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 16:33:48.309367 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2262 16:33:48.309431 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2263 16:33:48.309490 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2264 16:33:48.309549 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2265 16:33:48.309606 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2266 16:33:48.309661 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2267 16:33:48.309717 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2268 16:33:48.309776 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2269 16:33:48.309835 ===================================
2270 16:33:48.309891 LPDDR4 DRAM CONFIGURATION
2271 16:33:48.309950 ===================================
2272 16:33:48.310006 EX_ROW_EN[0] = 0x0
2273 16:33:48.310062 EX_ROW_EN[1] = 0x0
2274 16:33:48.310117 LP4Y_EN = 0x0
2275 16:33:48.310190 WORK_FSP = 0x0
2276 16:33:48.310250 WL = 0x4
2277 16:33:48.310306 RL = 0x4
2278 16:33:48.310364 BL = 0x2
2279 16:33:48.310423 RPST = 0x0
2280 16:33:48.310481 RD_PRE = 0x0
2281 16:33:48.310536 WR_PRE = 0x1
2282 16:33:48.310592 WR_PST = 0x0
2283 16:33:48.310647 DBI_WR = 0x0
2284 16:33:48.310705 DBI_RD = 0x0
2285 16:33:48.310763 OTF = 0x1
2286 16:33:48.310820 ===================================
2287 16:33:48.310876 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2288 16:33:48.310933 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2289 16:33:48.311014 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2290 16:33:48.311074 ===================================
2291 16:33:48.311130 LPDDR4 DRAM CONFIGURATION
2292 16:33:48.311190 ===================================
2293 16:33:48.311249 EX_ROW_EN[0] = 0x10
2294 16:33:48.311307 EX_ROW_EN[1] = 0x0
2295 16:33:48.311363 LP4Y_EN = 0x0
2296 16:33:48.311417 WORK_FSP = 0x0
2297 16:33:48.311472 WL = 0x4
2298 16:33:48.311528 RL = 0x4
2299 16:33:48.311585 BL = 0x2
2300 16:33:48.311644 RPST = 0x0
2301 16:33:48.311701 RD_PRE = 0x0
2302 16:33:48.311756 WR_PRE = 0x1
2303 16:33:48.311811 WR_PST = 0x0
2304 16:33:48.311899 DBI_WR = 0x0
2305 16:33:48.311961 DBI_RD = 0x0
2306 16:33:48.312020 OTF = 0x1
2307 16:33:48.312079 ===================================
2308 16:33:48.312135 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2309 16:33:48.312191 ==
2310 16:33:48.312250 Dram Type= 6, Freq= 0, CH_0, rank 0
2311 16:33:48.312310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2312 16:33:48.312368 ==
2313 16:33:48.312426 [Duty_Offset_Calibration]
2314 16:33:48.312482 B0:1 B1:-1 CA:0
2315 16:33:48.312537
2316 16:33:48.312594 [DutyScan_Calibration_Flow] k_type=0
2317 16:33:48.312650
2318 16:33:48.312707 ==CLK 0==
2319 16:33:48.312765 Final CLK duty delay cell = 0
2320 16:33:48.312821 [0] MAX Duty = 5125%(X100), DQS PI = 24
2321 16:33:48.312877 [0] MIN Duty = 4875%(X100), DQS PI = 8
2322 16:33:48.312932 [0] AVG Duty = 5000%(X100)
2323 16:33:48.312989
2324 16:33:48.313046 CH0 CLK Duty spec in!! Max-Min= 250%
2325 16:33:48.313102 [DutyScan_Calibration_Flow] ====Done====
2326 16:33:48.313159
2327 16:33:48.313214 [DutyScan_Calibration_Flow] k_type=1
2328 16:33:48.313269
2329 16:33:48.313324 ==DQS 0 ==
2330 16:33:48.313379 Final DQS duty delay cell = -4
2331 16:33:48.313438 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2332 16:33:48.313497 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2333 16:33:48.313554 [-4] AVG Duty = 4968%(X100)
2334 16:33:48.313609
2335 16:33:48.313663 ==DQS 1 ==
2336 16:33:48.313718 Final DQS duty delay cell = -4
2337 16:33:48.313972 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2338 16:33:48.314034 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2339 16:33:48.314092 [-4] AVG Duty = 4938%(X100)
2340 16:33:48.314148
2341 16:33:48.314247 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2342 16:33:48.314309
2343 16:33:48.314367 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2344 16:33:48.314427 [DutyScan_Calibration_Flow] ====Done====
2345 16:33:48.314485
2346 16:33:48.314539 [DutyScan_Calibration_Flow] k_type=3
2347 16:33:48.314595
2348 16:33:48.314653 ==DQM 0 ==
2349 16:33:48.314709 Final DQM duty delay cell = 0
2350 16:33:48.314765 [0] MAX Duty = 5031%(X100), DQS PI = 16
2351 16:33:48.314821 [0] MIN Duty = 4875%(X100), DQS PI = 8
2352 16:33:48.314880 [0] AVG Duty = 4953%(X100)
2353 16:33:48.314937
2354 16:33:48.314992 ==DQM 1 ==
2355 16:33:48.315049 Final DQM duty delay cell = 4
2356 16:33:48.315109 [4] MAX Duty = 5187%(X100), DQS PI = 16
2357 16:33:48.315167 [4] MIN Duty = 4969%(X100), DQS PI = 24
2358 16:33:48.315222 [4] AVG Duty = 5078%(X100)
2359 16:33:48.315276
2360 16:33:48.315330 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2361 16:33:48.315394
2362 16:33:48.315465 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2363 16:33:48.315557 [DutyScan_Calibration_Flow] ====Done====
2364 16:33:48.315617
2365 16:33:48.315673 [DutyScan_Calibration_Flow] k_type=2
2366 16:33:48.315731
2367 16:33:48.315791 ==DQ 0 ==
2368 16:33:48.315869 Final DQ duty delay cell = -4
2369 16:33:48.315931 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2370 16:33:48.315987 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2371 16:33:48.316042 [-4] AVG Duty = 4937%(X100)
2372 16:33:48.316106
2373 16:33:48.316164 ==DQ 1 ==
2374 16:33:48.316219 Final DQ duty delay cell = -4
2375 16:33:48.316279 [-4] MAX Duty = 4969%(X100), DQS PI = 54
2376 16:33:48.316362 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2377 16:33:48.316423 [-4] AVG Duty = 4922%(X100)
2378 16:33:48.316479
2379 16:33:48.316538 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2380 16:33:48.316593
2381 16:33:48.316652 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2382 16:33:48.316711 [DutyScan_Calibration_Flow] ====Done====
2383 16:33:48.316768 ==
2384 16:33:48.316826 Dram Type= 6, Freq= 0, CH_1, rank 0
2385 16:33:48.316882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2386 16:33:48.316938 ==
2387 16:33:48.316993 [Duty_Offset_Calibration]
2388 16:33:48.317052 B0:-1 B1:1 CA:1
2389 16:33:48.317109
2390 16:33:48.317164 [DutyScan_Calibration_Flow] k_type=0
2391 16:33:48.317222
2392 16:33:48.317279 ==CLK 0==
2393 16:33:48.317335 Final CLK duty delay cell = 0
2394 16:33:48.317390 [0] MAX Duty = 5156%(X100), DQS PI = 22
2395 16:33:48.317451 [0] MIN Duty = 4969%(X100), DQS PI = 60
2396 16:33:48.317534 [0] AVG Duty = 5062%(X100)
2397 16:33:48.317591
2398 16:33:48.317649 CH1 CLK Duty spec in!! Max-Min= 187%
2399 16:33:48.317708 [DutyScan_Calibration_Flow] ====Done====
2400 16:33:48.317765
2401 16:33:48.317820 [DutyScan_Calibration_Flow] k_type=1
2402 16:33:48.317878
2403 16:33:48.317932 ==DQS 0 ==
2404 16:33:48.318005 Final DQS duty delay cell = 0
2405 16:33:48.318076 [0] MAX Duty = 5125%(X100), DQS PI = 48
2406 16:33:48.318133 [0] MIN Duty = 4907%(X100), DQS PI = 6
2407 16:33:48.318199 [0] AVG Duty = 5016%(X100)
2408 16:33:48.318267
2409 16:33:48.318326 ==DQS 1 ==
2410 16:33:48.318381 Final DQS duty delay cell = 0
2411 16:33:48.318437 [0] MAX Duty = 5062%(X100), DQS PI = 10
2412 16:33:48.318512 [0] MIN Duty = 4969%(X100), DQS PI = 56
2413 16:33:48.318568 [0] AVG Duty = 5015%(X100)
2414 16:33:48.318623
2415 16:33:48.318678 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2416 16:33:48.318738
2417 16:33:48.318793 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2418 16:33:48.318849 [DutyScan_Calibration_Flow] ====Done====
2419 16:33:48.318906
2420 16:33:48.318960 [DutyScan_Calibration_Flow] k_type=3
2421 16:33:48.319016
2422 16:33:48.319073 ==DQM 0 ==
2423 16:33:48.319134 Final DQM duty delay cell = -4
2424 16:33:48.319193 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2425 16:33:48.319250 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2426 16:33:48.319308 [-4] AVG Duty = 4937%(X100)
2427 16:33:48.319368
2428 16:33:48.319423 ==DQM 1 ==
2429 16:33:48.319478 Final DQM duty delay cell = 0
2430 16:33:48.319533 [0] MAX Duty = 5156%(X100), DQS PI = 2
2431 16:33:48.319591 [0] MIN Duty = 5000%(X100), DQS PI = 28
2432 16:33:48.319648 [0] AVG Duty = 5078%(X100)
2433 16:33:48.319706
2434 16:33:48.319762 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2435 16:33:48.319820
2436 16:33:48.319875 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2437 16:33:48.319930 [DutyScan_Calibration_Flow] ====Done====
2438 16:33:48.319988
2439 16:33:48.320046 [DutyScan_Calibration_Flow] k_type=2
2440 16:33:48.320105
2441 16:33:48.320160 ==DQ 0 ==
2442 16:33:48.320215 Final DQ duty delay cell = 0
2443 16:33:48.320273 [0] MAX Duty = 5187%(X100), DQS PI = 32
2444 16:33:48.320332 [0] MIN Duty = 4907%(X100), DQS PI = 6
2445 16:33:48.320389 [0] AVG Duty = 5047%(X100)
2446 16:33:48.320446
2447 16:33:48.320504 ==DQ 1 ==
2448 16:33:48.320561 Final DQ duty delay cell = 0
2449 16:33:48.320617 [0] MAX Duty = 5124%(X100), DQS PI = 10
2450 16:33:48.320673 [0] MIN Duty = 4969%(X100), DQS PI = 0
2451 16:33:48.320727 [0] AVG Duty = 5046%(X100)
2452 16:33:48.320782
2453 16:33:48.320881 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2454 16:33:48.320945
2455 16:33:48.321001 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2456 16:33:48.321056 [DutyScan_Calibration_Flow] ====Done====
2457 16:33:48.321111 nWR fixed to 30
2458 16:33:48.321178 [ModeRegInit_LP4] CH0 RK0
2459 16:33:48.321257 [ModeRegInit_LP4] CH0 RK1
2460 16:33:48.321317 [ModeRegInit_LP4] CH1 RK0
2461 16:33:48.321375 [ModeRegInit_LP4] CH1 RK1
2462 16:33:48.321444 match AC timing 7
2463 16:33:48.321512 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2464 16:33:48.321570 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2465 16:33:48.321638 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2466 16:33:48.321694 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2467 16:33:48.321749 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2468 16:33:48.321817 ==
2469 16:33:48.321874 Dram Type= 6, Freq= 0, CH_0, rank 0
2470 16:33:48.321930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 16:33:48.321989 ==
2472 16:33:48.322044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 16:33:48.322100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2474 16:33:48.322156 [CA 0] Center 39 (9~70) winsize 62
2475 16:33:48.322234 [CA 1] Center 39 (9~69) winsize 61
2476 16:33:48.322289 [CA 2] Center 35 (5~66) winsize 62
2477 16:33:48.322345 [CA 3] Center 35 (5~66) winsize 62
2478 16:33:48.322408 [CA 4] Center 33 (4~63) winsize 60
2479 16:33:48.322466 [CA 5] Center 33 (3~63) winsize 61
2480 16:33:48.322521
2481 16:33:48.322576 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2482 16:33:48.322632
2483 16:33:48.322690 [CATrainingPosCal] consider 1 rank data
2484 16:33:48.322749 u2DelayCellTimex100 = 270/100 ps
2485 16:33:48.322806 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2486 16:33:48.322862 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2487 16:33:48.323133 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 16:33:48.323198 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2489 16:33:48.323255 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2490 16:33:48.323311 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2491 16:33:48.323377
2492 16:33:48.323434 CA PerBit enable=1, Macro0, CA PI delay=33
2493 16:33:48.323491
2494 16:33:48.323549 [CBTSetCACLKResult] CA Dly = 33
2495 16:33:48.323609 CS Dly: 8 (0~39)
2496 16:33:48.323665 ==
2497 16:33:48.323721 Dram Type= 6, Freq= 0, CH_0, rank 1
2498 16:33:48.323780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 16:33:48.323839 ==
2500 16:33:48.323899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2501 16:33:48.323955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2502 16:33:48.324014 [CA 0] Center 39 (9~70) winsize 62
2503 16:33:48.324070 [CA 1] Center 39 (9~70) winsize 62
2504 16:33:48.324125 [CA 2] Center 35 (5~66) winsize 62
2505 16:33:48.324183 [CA 3] Center 35 (5~65) winsize 61
2506 16:33:48.324243 [CA 4] Center 33 (3~64) winsize 62
2507 16:33:48.324298 [CA 5] Center 33 (3~63) winsize 61
2508 16:33:48.324357
2509 16:33:48.324435 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2510 16:33:48.324492
2511 16:33:48.324553 [CATrainingPosCal] consider 2 rank data
2512 16:33:48.324612 u2DelayCellTimex100 = 270/100 ps
2513 16:33:48.324670 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2514 16:33:48.324729 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2515 16:33:48.324785 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2516 16:33:48.324840 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2517 16:33:48.324896 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2518 16:33:48.324955 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2519 16:33:48.325012
2520 16:33:48.325069 CA PerBit enable=1, Macro0, CA PI delay=33
2521 16:33:48.325128
2522 16:33:48.325185 [CBTSetCACLKResult] CA Dly = 33
2523 16:33:48.325241 CS Dly: 9 (0~41)
2524 16:33:48.325298
2525 16:33:48.325355 ----->DramcWriteLeveling(PI) begin...
2526 16:33:48.325414 ==
2527 16:33:48.325471 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 16:33:48.325526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 16:33:48.325583 ==
2530 16:33:48.325644 Write leveling (Byte 0): 34 => 34
2531 16:33:48.325702 Write leveling (Byte 1): 28 => 28
2532 16:33:48.325757 DramcWriteLeveling(PI) end<-----
2533 16:33:48.325815
2534 16:33:48.325873 ==
2535 16:33:48.325932 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 16:33:48.326036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 16:33:48.326122 ==
2538 16:33:48.326210 [Gating] SW mode calibration
2539 16:33:48.326268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2540 16:33:48.326326 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2541 16:33:48.326385 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2542 16:33:48.326445 0 15 4 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
2543 16:33:48.326501 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 16:33:48.326559 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 16:33:48.326627 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 16:33:48.326690 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 16:33:48.326748 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 16:33:48.326803 0 15 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
2549 16:33:48.326859 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
2550 16:33:48.326918 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
2551 16:33:48.326974 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 16:33:48.327029 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 16:33:48.327087 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 16:33:48.327162 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 16:33:48.327223 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 16:33:48.327292 1 0 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
2557 16:33:48.327348 1 1 0 | B1->B0 | 2323 4342 | 0 1 | (0 0) (0 0)
2558 16:33:48.327404 1 1 4 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
2559 16:33:48.327460 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 16:33:48.327534 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 16:33:48.327591 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 16:33:48.327646 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 16:33:48.327706 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 16:33:48.327761 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2565 16:33:48.327816 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2566 16:33:48.327875 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 16:33:48.327931 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 16:33:48.327986 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 16:33:48.328045 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 16:33:48.328100 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 16:33:48.328155 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 16:33:48.328212 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 16:33:48.328269 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 16:33:48.328328 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 16:33:48.328384 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 16:33:48.328442 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 16:33:48.328499 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 16:33:48.328555 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 16:33:48.328610 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 16:33:48.328668 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2581 16:33:48.328728 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2582 16:33:48.328784 Total UI for P1: 0, mck2ui 16
2583 16:33:48.328839 best dqsien dly found for B0: ( 1, 3, 28)
2584 16:33:48.328895 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2585 16:33:48.328951 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 16:33:48.329006 Total UI for P1: 0, mck2ui 16
2587 16:33:48.329061 best dqsien dly found for B1: ( 1, 4, 2)
2588 16:33:48.329116 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2589 16:33:48.329172 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2590 16:33:48.329229
2591 16:33:48.329486 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2592 16:33:48.329550 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2593 16:33:48.329610 [Gating] SW calibration Done
2594 16:33:48.329668 ==
2595 16:33:48.329724 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 16:33:48.329782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 16:33:48.329840 ==
2598 16:33:48.329895 RX Vref Scan: 0
2599 16:33:48.329953
2600 16:33:48.330011 RX Vref 0 -> 0, step: 1
2601 16:33:48.330068
2602 16:33:48.330123 RX Delay -40 -> 252, step: 8
2603 16:33:48.330190 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2604 16:33:48.330257 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2605 16:33:48.330315 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2606 16:33:48.330375 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2607 16:33:48.330430 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2608 16:33:48.330489 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2609 16:33:48.330545 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2610 16:33:48.330600 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2611 16:33:48.330684 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2612 16:33:48.330745 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2613 16:33:48.330806 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2614 16:33:48.330891 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2615 16:33:48.330952 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2616 16:33:48.331007 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2617 16:33:48.331063 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2618 16:33:48.331122 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2619 16:33:48.331179 ==
2620 16:33:48.331234 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 16:33:48.331330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 16:33:48.331390 ==
2623 16:33:48.331480 DQS Delay:
2624 16:33:48.331541 DQS0 = 0, DQS1 = 0
2625 16:33:48.331600 DQM Delay:
2626 16:33:48.331681 DQM0 = 119, DQM1 = 106
2627 16:33:48.331738 DQ Delay:
2628 16:33:48.331793 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2629 16:33:48.331851 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2630 16:33:48.331906 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2631 16:33:48.331966 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2632 16:33:48.332022
2633 16:33:48.332077
2634 16:33:48.332131 ==
2635 16:33:48.332186 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 16:33:48.332243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 16:33:48.332302 ==
2638 16:33:48.332359
2639 16:33:48.332418
2640 16:33:48.332473 TX Vref Scan disable
2641 16:33:48.332535 == TX Byte 0 ==
2642 16:33:48.332593 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2643 16:33:48.332651 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2644 16:33:48.332706 == TX Byte 1 ==
2645 16:33:48.332760 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2646 16:33:48.332816 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2647 16:33:48.332873 ==
2648 16:33:48.332932 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 16:33:48.332988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 16:33:48.333044 ==
2651 16:33:48.333098 TX Vref=22, minBit 13, minWin=24, winSum=415
2652 16:33:48.333154 TX Vref=24, minBit 12, minWin=25, winSum=420
2653 16:33:48.333211 TX Vref=26, minBit 1, minWin=26, winSum=429
2654 16:33:48.333269 TX Vref=28, minBit 10, minWin=26, winSum=430
2655 16:33:48.333327 TX Vref=30, minBit 10, minWin=26, winSum=431
2656 16:33:48.333384 TX Vref=32, minBit 4, minWin=26, winSum=430
2657 16:33:48.333439 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 30
2658 16:33:48.333494
2659 16:33:48.333548 Final TX Range 1 Vref 30
2660 16:33:48.333603
2661 16:33:48.333660 ==
2662 16:33:48.333718 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 16:33:48.333774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 16:33:48.333830 ==
2665 16:33:48.333887
2666 16:33:48.333944
2667 16:33:48.334000 TX Vref Scan disable
2668 16:33:48.334055 == TX Byte 0 ==
2669 16:33:48.334112 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2670 16:33:48.334190 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2671 16:33:48.334251 == TX Byte 1 ==
2672 16:33:48.334307 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2673 16:33:48.334363 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2674 16:33:48.334422
2675 16:33:48.334505 [DATLAT]
2676 16:33:48.334566 Freq=1200, CH0 RK0
2677 16:33:48.334624
2678 16:33:48.334682 DATLAT Default: 0xd
2679 16:33:48.334740 0, 0xFFFF, sum = 0
2680 16:33:48.334799 1, 0xFFFF, sum = 0
2681 16:33:48.334856 2, 0xFFFF, sum = 0
2682 16:33:48.334912 3, 0xFFFF, sum = 0
2683 16:33:48.334968 4, 0xFFFF, sum = 0
2684 16:33:48.335024 5, 0xFFFF, sum = 0
2685 16:33:48.335084 6, 0xFFFF, sum = 0
2686 16:33:48.335144 7, 0xFFFF, sum = 0
2687 16:33:48.335200 8, 0xFFFF, sum = 0
2688 16:33:48.335256 9, 0xFFFF, sum = 0
2689 16:33:48.335311 10, 0xFFFF, sum = 0
2690 16:33:48.335369 11, 0xFFFF, sum = 0
2691 16:33:48.335425 12, 0x0, sum = 1
2692 16:33:48.335481 13, 0x0, sum = 2
2693 16:33:48.335540 14, 0x0, sum = 3
2694 16:33:48.335598 15, 0x0, sum = 4
2695 16:33:48.335657 best_step = 13
2696 16:33:48.335715
2697 16:33:48.335772 ==
2698 16:33:48.335831 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 16:33:48.335888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 16:33:48.335944 ==
2701 16:33:48.335999 RX Vref Scan: 1
2702 16:33:48.336053
2703 16:33:48.336110 Set Vref Range= 32 -> 127
2704 16:33:48.336169
2705 16:33:48.336225 RX Vref 32 -> 127, step: 1
2706 16:33:48.336280
2707 16:33:48.336334 RX Delay -21 -> 252, step: 4
2708 16:33:48.336389
2709 16:33:48.336444 Set Vref, RX VrefLevel [Byte0]: 32
2710 16:33:48.336502 [Byte1]: 32
2711 16:33:48.336560
2712 16:33:48.336617 Set Vref, RX VrefLevel [Byte0]: 33
2713 16:33:48.336672 [Byte1]: 33
2714 16:33:48.336730
2715 16:33:48.336786 Set Vref, RX VrefLevel [Byte0]: 34
2716 16:33:48.336841 [Byte1]: 34
2717 16:33:48.336895
2718 16:33:48.336953 Set Vref, RX VrefLevel [Byte0]: 35
2719 16:33:48.337012 [Byte1]: 35
2720 16:33:48.337067
2721 16:33:48.337122 Set Vref, RX VrefLevel [Byte0]: 36
2722 16:33:48.337177 [Byte1]: 36
2723 16:33:48.337231
2724 16:33:48.337286 Set Vref, RX VrefLevel [Byte0]: 37
2725 16:33:48.337343 [Byte1]: 37
2726 16:33:48.337400
2727 16:33:48.337457 Set Vref, RX VrefLevel [Byte0]: 38
2728 16:33:48.337513 [Byte1]: 38
2729 16:33:48.337568
2730 16:33:48.337633 Set Vref, RX VrefLevel [Byte0]: 39
2731 16:33:48.337706 [Byte1]: 39
2732 16:33:48.337762
2733 16:33:48.337816 Set Vref, RX VrefLevel [Byte0]: 40
2734 16:33:48.337874 [Byte1]: 40
2735 16:33:48.337931
2736 16:33:48.337990 Set Vref, RX VrefLevel [Byte0]: 41
2737 16:33:48.338046 [Byte1]: 41
2738 16:33:48.338101
2739 16:33:48.338155 Set Vref, RX VrefLevel [Byte0]: 42
2740 16:33:48.338232 [Byte1]: 42
2741 16:33:48.338291
2742 16:33:48.338345 Set Vref, RX VrefLevel [Byte0]: 43
2743 16:33:48.338404 [Byte1]: 43
2744 16:33:48.338460
2745 16:33:48.338521 Set Vref, RX VrefLevel [Byte0]: 44
2746 16:33:48.338798 [Byte1]: 44
2747 16:33:48.338862
2748 16:33:48.338919 Set Vref, RX VrefLevel [Byte0]: 45
2749 16:33:48.338982 [Byte1]: 45
2750 16:33:48.339039
2751 16:33:48.339095 Set Vref, RX VrefLevel [Byte0]: 46
2752 16:33:48.339154 [Byte1]: 46
2753 16:33:48.339212
2754 16:33:48.339267 Set Vref, RX VrefLevel [Byte0]: 47
2755 16:33:48.339325 [Byte1]: 47
2756 16:33:48.339384
2757 16:33:48.339439 Set Vref, RX VrefLevel [Byte0]: 48
2758 16:33:48.339494 [Byte1]: 48
2759 16:33:48.339548
2760 16:33:48.339603 Set Vref, RX VrefLevel [Byte0]: 49
2761 16:33:48.339661 [Byte1]: 49
2762 16:33:48.339720
2763 16:33:48.339776 Set Vref, RX VrefLevel [Byte0]: 50
2764 16:33:48.339831 [Byte1]: 50
2765 16:33:48.339886
2766 16:33:48.339941 Set Vref, RX VrefLevel [Byte0]: 51
2767 16:33:48.339996 [Byte1]: 51
2768 16:33:48.340053
2769 16:33:48.340111 Set Vref, RX VrefLevel [Byte0]: 52
2770 16:33:48.340168 [Byte1]: 52
2771 16:33:48.340223
2772 16:33:48.340278 Set Vref, RX VrefLevel [Byte0]: 53
2773 16:33:48.340333 [Byte1]: 53
2774 16:33:48.340387
2775 16:33:48.340467 Set Vref, RX VrefLevel [Byte0]: 54
2776 16:33:48.340530 [Byte1]: 54
2777 16:33:48.340588
2778 16:33:48.340644 Set Vref, RX VrefLevel [Byte0]: 55
2779 16:33:48.340702 [Byte1]: 55
2780 16:33:48.340759
2781 16:33:48.340813 Set Vref, RX VrefLevel [Byte0]: 56
2782 16:33:48.340870 [Byte1]: 56
2783 16:33:48.340928
2784 16:33:48.340985 Set Vref, RX VrefLevel [Byte0]: 57
2785 16:33:48.341040 [Byte1]: 57
2786 16:33:48.341095
2787 16:33:48.341152 Set Vref, RX VrefLevel [Byte0]: 58
2788 16:33:48.341211 [Byte1]: 58
2789 16:33:48.341267
2790 16:33:48.341322 Set Vref, RX VrefLevel [Byte0]: 59
2791 16:33:48.341377 [Byte1]: 59
2792 16:33:48.341433
2793 16:33:48.341487 Set Vref, RX VrefLevel [Byte0]: 60
2794 16:33:48.341544 [Byte1]: 60
2795 16:33:48.341601
2796 16:33:48.341669 Set Vref, RX VrefLevel [Byte0]: 61
2797 16:33:48.341723 [Byte1]: 61
2798 16:33:48.341779
2799 16:33:48.341837 Set Vref, RX VrefLevel [Byte0]: 62
2800 16:33:48.341892 [Byte1]: 62
2801 16:33:48.341946
2802 16:33:48.342002 Set Vref, RX VrefLevel [Byte0]: 63
2803 16:33:48.342058 [Byte1]: 63
2804 16:33:48.342116
2805 16:33:48.342201 Set Vref, RX VrefLevel [Byte0]: 64
2806 16:33:48.342272 [Byte1]: 64
2807 16:33:48.342326
2808 16:33:48.342380 Set Vref, RX VrefLevel [Byte0]: 65
2809 16:33:48.342439 [Byte1]: 65
2810 16:33:48.342495
2811 16:33:48.342555 Set Vref, RX VrefLevel [Byte0]: 66
2812 16:33:48.342611 [Byte1]: 66
2813 16:33:48.342665
2814 16:33:48.342723 Set Vref, RX VrefLevel [Byte0]: 67
2815 16:33:48.342786 [Byte1]: 67
2816 16:33:48.342863
2817 16:33:48.342921 Set Vref, RX VrefLevel [Byte0]: 68
2818 16:33:48.342978 [Byte1]: 68
2819 16:33:48.343033
2820 16:33:48.343089 Set Vref, RX VrefLevel [Byte0]: 69
2821 16:33:48.343145 [Byte1]: 69
2822 16:33:48.343199
2823 16:33:48.343252 Set Vref, RX VrefLevel [Byte0]: 70
2824 16:33:48.343307 [Byte1]: 70
2825 16:33:48.343364
2826 16:33:48.343421 Set Vref, RX VrefLevel [Byte0]: 71
2827 16:33:48.343477 [Byte1]: 71
2828 16:33:48.343534
2829 16:33:48.343589 Set Vref, RX VrefLevel [Byte0]: 72
2830 16:33:48.343643 [Byte1]: 72
2831 16:33:48.343697
2832 16:33:48.343754 Set Vref, RX VrefLevel [Byte0]: 73
2833 16:33:48.343810 [Byte1]: 73
2834 16:33:48.343863
2835 16:33:48.343917 Set Vref, RX VrefLevel [Byte0]: 74
2836 16:33:48.343970 [Byte1]: 74
2837 16:33:48.344024
2838 16:33:48.344077 Set Vref, RX VrefLevel [Byte0]: 75
2839 16:33:48.344161 [Byte1]: 75
2840 16:33:48.344220
2841 16:33:48.344274 Set Vref, RX VrefLevel [Byte0]: 76
2842 16:33:48.344328 [Byte1]: 76
2843 16:33:48.344382
2844 16:33:48.344436 Set Vref, RX VrefLevel [Byte0]: 77
2845 16:33:48.344493 [Byte1]: 77
2846 16:33:48.344551
2847 16:33:48.344606 Set Vref, RX VrefLevel [Byte0]: 78
2848 16:33:48.344661 [Byte1]: 78
2849 16:33:48.344718
2850 16:33:48.344775 Set Vref, RX VrefLevel [Byte0]: 79
2851 16:33:48.344831 [Byte1]: 79
2852 16:33:48.344885
2853 16:33:48.344939 Final RX Vref Byte 0 = 57 to rank0
2854 16:33:48.344993 Final RX Vref Byte 1 = 48 to rank0
2855 16:33:48.345047 Final RX Vref Byte 0 = 57 to rank1
2856 16:33:48.345102 Final RX Vref Byte 1 = 48 to rank1==
2857 16:33:48.345159 Dram Type= 6, Freq= 0, CH_0, rank 0
2858 16:33:48.345218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 16:33:48.345275 ==
2860 16:33:48.345329 DQS Delay:
2861 16:33:48.345384 DQS0 = 0, DQS1 = 0
2862 16:33:48.345438 DQM Delay:
2863 16:33:48.345492 DQM0 = 118, DQM1 = 106
2864 16:33:48.345548 DQ Delay:
2865 16:33:48.345605 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =114
2866 16:33:48.345662 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2867 16:33:48.345717 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
2868 16:33:48.345770 DQ12 =110, DQ13 =108, DQ14 =118, DQ15 =116
2869 16:33:48.345824
2870 16:33:48.345877
2871 16:33:48.345934 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 405 ps
2872 16:33:48.345994 CH0 RK0: MR19=403, MR18=DF9
2873 16:33:48.346049 CH0_RK0: MR19=0x403, MR18=0xDF9, DQSOSC=405, MR23=63, INC=39, DEC=26
2874 16:33:48.346103
2875 16:33:48.346159 ----->DramcWriteLeveling(PI) begin...
2876 16:33:48.346257 ==
2877 16:33:48.346312 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 16:33:48.346396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 16:33:48.346458 ==
2880 16:33:48.346515 Write leveling (Byte 0): 33 => 33
2881 16:33:48.346570 Write leveling (Byte 1): 28 => 28
2882 16:33:48.346625 DramcWriteLeveling(PI) end<-----
2883 16:33:48.346679
2884 16:33:48.346733 ==
2885 16:33:48.346787 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 16:33:48.346871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 16:33:48.346929 ==
2888 16:33:48.346983 [Gating] SW mode calibration
2889 16:33:48.347038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2890 16:33:48.347092 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2891 16:33:48.347150 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2892 16:33:48.347208 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2893 16:33:48.347264 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 16:33:48.347318 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 16:33:48.347565 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 16:33:48.347625 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 16:33:48.347681 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2898 16:33:48.347736 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2899 16:33:48.347793 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
2900 16:33:48.347851 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 16:33:48.347907 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 16:33:48.347961 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 16:33:48.348017 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 16:33:48.348071 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 16:33:48.348125 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 16:33:48.348181 1 0 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2907 16:33:48.348239 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2908 16:33:48.348295 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 16:33:48.348349 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 16:33:48.348403 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 16:33:48.348457 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 16:33:48.348510 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 16:33:48.348567 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 16:33:48.348625 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2915 16:33:48.348680 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2916 16:33:48.348736 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 16:33:48.348793 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 16:33:48.348849 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 16:33:48.348903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 16:33:48.348957 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 16:33:48.349014 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 16:33:48.349070 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 16:33:48.349124 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 16:33:48.349177 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 16:33:48.349233 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 16:33:48.349313 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 16:33:48.349368 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 16:33:48.349445 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 16:33:48.349502 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 16:33:48.349556 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2931 16:33:48.349614 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2932 16:33:48.349672 Total UI for P1: 0, mck2ui 16
2933 16:33:48.349729 best dqsien dly found for B0: ( 1, 3, 28)
2934 16:33:48.349802 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 16:33:48.349864 Total UI for P1: 0, mck2ui 16
2936 16:33:48.349919 best dqsien dly found for B1: ( 1, 3, 30)
2937 16:33:48.500134 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2938 16:33:48.500282 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2939 16:33:48.500353
2940 16:33:48.500420 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2941 16:33:48.500485 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2942 16:33:48.500547 [Gating] SW calibration Done
2943 16:33:48.500606 ==
2944 16:33:48.500668 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 16:33:48.500727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 16:33:48.500784 ==
2947 16:33:48.500844 RX Vref Scan: 0
2948 16:33:48.500905
2949 16:33:48.500961 RX Vref 0 -> 0, step: 1
2950 16:33:48.501017
2951 16:33:48.501073 RX Delay -40 -> 252, step: 8
2952 16:33:48.501130 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2953 16:33:48.501186 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2954 16:33:48.501248 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2955 16:33:48.501306 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2956 16:33:48.501361 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2957 16:33:48.501417 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2958 16:33:48.501473 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2959 16:33:48.501528 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2960 16:33:48.501586 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2961 16:33:48.501646 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2962 16:33:48.501704 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2963 16:33:48.501759 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2964 16:33:48.501815 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2965 16:33:48.501870 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2966 16:33:48.501926 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2967 16:33:48.501984 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2968 16:33:48.502041 ==
2969 16:33:48.502100 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 16:33:48.502159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 16:33:48.502228 ==
2972 16:33:48.502283 DQS Delay:
2973 16:33:48.502339 DQS0 = 0, DQS1 = 0
2974 16:33:48.502398 DQM Delay:
2975 16:33:48.502457 DQM0 = 117, DQM1 = 108
2976 16:33:48.502514 DQ Delay:
2977 16:33:48.502569 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2978 16:33:48.502625 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2979 16:33:48.502680 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2980 16:33:48.502738 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2981 16:33:48.502797
2982 16:33:48.502854
2983 16:33:48.502912 ==
2984 16:33:48.502971 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 16:33:48.503028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 16:33:48.503085 ==
2987 16:33:48.503140
2988 16:33:48.503201
2989 16:33:48.503255 TX Vref Scan disable
2990 16:33:48.503310 == TX Byte 0 ==
2991 16:33:48.503366 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2992 16:33:48.503426 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2993 16:33:48.503483 == TX Byte 1 ==
2994 16:33:48.503541 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2995 16:33:48.503597 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2996 16:33:48.503657 ==
2997 16:33:48.503713 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 16:33:48.503786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 16:33:48.503842 ==
3000 16:33:48.503898 TX Vref=22, minBit 13, minWin=24, winSum=412
3001 16:33:48.503958 TX Vref=24, minBit 5, minWin=25, winSum=419
3002 16:33:48.504014 TX Vref=26, minBit 10, minWin=26, winSum=428
3003 16:33:48.504279 TX Vref=28, minBit 1, minWin=26, winSum=428
3004 16:33:48.504346 TX Vref=30, minBit 12, minWin=25, winSum=428
3005 16:33:48.504408 TX Vref=32, minBit 10, minWin=26, winSum=431
3006 16:33:48.504466 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 32
3007 16:33:48.504522
3008 16:33:48.504580 Final TX Range 1 Vref 32
3009 16:33:48.504638
3010 16:33:48.504692 ==
3011 16:33:48.504751 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 16:33:48.504807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 16:33:48.504864 ==
3014 16:33:48.504919
3015 16:33:48.504974
3016 16:33:48.505028 TX Vref Scan disable
3017 16:33:48.505083 == TX Byte 0 ==
3018 16:33:48.505141 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3019 16:33:48.505200 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3020 16:33:48.505258 == TX Byte 1 ==
3021 16:33:48.505314 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3022 16:33:48.505373 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3023 16:33:48.505429
3024 16:33:48.505484 [DATLAT]
3025 16:33:48.505542 Freq=1200, CH0 RK1
3026 16:33:48.505599
3027 16:33:48.505654 DATLAT Default: 0xd
3028 16:33:48.505711 0, 0xFFFF, sum = 0
3029 16:33:48.505768 1, 0xFFFF, sum = 0
3030 16:33:48.505828 2, 0xFFFF, sum = 0
3031 16:33:48.505886 3, 0xFFFF, sum = 0
3032 16:33:48.505942 4, 0xFFFF, sum = 0
3033 16:33:48.505998 5, 0xFFFF, sum = 0
3034 16:33:48.506054 6, 0xFFFF, sum = 0
3035 16:33:48.506110 7, 0xFFFF, sum = 0
3036 16:33:48.506178 8, 0xFFFF, sum = 0
3037 16:33:48.506248 9, 0xFFFF, sum = 0
3038 16:33:48.506307 10, 0xFFFF, sum = 0
3039 16:33:48.506363 11, 0xFFFF, sum = 0
3040 16:33:48.506419 12, 0x0, sum = 1
3041 16:33:48.506475 13, 0x0, sum = 2
3042 16:33:48.506531 14, 0x0, sum = 3
3043 16:33:48.506590 15, 0x0, sum = 4
3044 16:33:48.506650 best_step = 13
3045 16:33:48.506707
3046 16:33:48.506762 ==
3047 16:33:48.506818 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 16:33:48.506874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 16:33:48.506930 ==
3050 16:33:48.506988 RX Vref Scan: 0
3051 16:33:48.507047
3052 16:33:48.507105 RX Vref 0 -> 0, step: 1
3053 16:33:48.507159
3054 16:33:48.507216 RX Delay -21 -> 252, step: 4
3055 16:33:48.507272 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3056 16:33:48.507328 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3057 16:33:48.507384 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3058 16:33:48.507443 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3059 16:33:48.507500 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3060 16:33:48.507560 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3061 16:33:48.507616 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3062 16:33:48.507672 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3063 16:33:48.507731 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3064 16:33:48.507826 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3065 16:33:48.507898 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3066 16:33:48.507955 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3067 16:33:48.508012 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3068 16:33:48.508068 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3069 16:33:48.508124 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3070 16:33:48.508183 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3071 16:33:48.508243 ==
3072 16:33:48.508301 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 16:33:48.508357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 16:33:48.508417 ==
3075 16:33:48.508478 DQS Delay:
3076 16:33:48.508549 DQS0 = 0, DQS1 = 0
3077 16:33:48.508611 DQM Delay:
3078 16:33:48.508670 DQM0 = 116, DQM1 = 107
3079 16:33:48.508730 DQ Delay:
3080 16:33:48.508788 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3081 16:33:48.508846 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3082 16:33:48.508904 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3083 16:33:48.508961 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3084 16:33:48.509017
3085 16:33:48.509075
3086 16:33:48.509132 [DQSOSCAuto] RK1, (LSB)MR18= 0xae5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3087 16:33:48.509189 CH0 RK1: MR19=403, MR18=AE5
3088 16:33:48.509248 CH0_RK1: MR19=0x403, MR18=0xAE5, DQSOSC=406, MR23=63, INC=39, DEC=26
3089 16:33:48.509306 [RxdqsGatingPostProcess] freq 1200
3090 16:33:48.509364 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3091 16:33:48.509421 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 16:33:48.509482 best DQS1 dly(2T, 0.5T) = (0, 12)
3093 16:33:48.509541 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 16:33:48.509598 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3095 16:33:48.509654 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 16:33:48.509709 best DQS1 dly(2T, 0.5T) = (0, 11)
3097 16:33:48.509765 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 16:33:48.509823 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3099 16:33:48.509882 Pre-setting of DQS Precalculation
3100 16:33:48.509940 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3101 16:33:48.509997 ==
3102 16:33:48.510053 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 16:33:48.510109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 16:33:48.510176 ==
3105 16:33:48.510234 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 16:33:48.510291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3107 16:33:48.510350 [CA 0] Center 37 (7~68) winsize 62
3108 16:33:48.510410 [CA 1] Center 37 (7~68) winsize 62
3109 16:33:48.510468 [CA 2] Center 34 (4~64) winsize 61
3110 16:33:48.510524 [CA 3] Center 33 (3~64) winsize 62
3111 16:33:48.510584 [CA 4] Center 34 (4~64) winsize 61
3112 16:33:48.510641 [CA 5] Center 33 (3~64) winsize 62
3113 16:33:48.510698
3114 16:33:48.510753 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3115 16:33:48.510809
3116 16:33:48.510864 [CATrainingPosCal] consider 1 rank data
3117 16:33:48.510922 u2DelayCellTimex100 = 270/100 ps
3118 16:33:48.510980 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3119 16:33:48.511037 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 16:33:48.511095 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3121 16:33:48.511154 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3122 16:33:48.511212 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 16:33:48.511268 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3124 16:33:48.511323
3125 16:33:48.511382 CA PerBit enable=1, Macro0, CA PI delay=33
3126 16:33:48.511443
3127 16:33:48.511498 [CBTSetCACLKResult] CA Dly = 33
3128 16:33:48.511554 CS Dly: 6 (0~37)
3129 16:33:48.511609 ==
3130 16:33:48.511665 Dram Type= 6, Freq= 0, CH_1, rank 1
3131 16:33:48.511721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 16:33:48.511783 ==
3133 16:33:48.511843 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 16:33:48.511901 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3135 16:33:48.511957 [CA 0] Center 37 (7~68) winsize 62
3136 16:33:48.512211 [CA 1] Center 38 (8~68) winsize 61
3137 16:33:48.512276 [CA 2] Center 34 (3~65) winsize 63
3138 16:33:48.512334 [CA 3] Center 33 (3~64) winsize 62
3139 16:33:48.512391 [CA 4] Center 34 (4~65) winsize 62
3140 16:33:48.512447 [CA 5] Center 33 (3~64) winsize 62
3141 16:33:48.512506
3142 16:33:48.512566 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3143 16:33:48.512624
3144 16:33:48.512679 [CATrainingPosCal] consider 2 rank data
3145 16:33:48.512736 u2DelayCellTimex100 = 270/100 ps
3146 16:33:48.512794 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3147 16:33:48.512854 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3148 16:33:48.512912 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3149 16:33:48.512971 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3150 16:33:48.513029 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 16:33:48.513088 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3152 16:33:48.513143
3153 16:33:48.513199 CA PerBit enable=1, Macro0, CA PI delay=33
3154 16:33:48.513255
3155 16:33:48.513311 [CBTSetCACLKResult] CA Dly = 33
3156 16:33:48.513367 CS Dly: 7 (0~40)
3157 16:33:48.513425
3158 16:33:48.513483 ----->DramcWriteLeveling(PI) begin...
3159 16:33:48.513542 ==
3160 16:33:48.513598 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 16:33:48.513653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 16:33:48.513709 ==
3163 16:33:48.513764 Write leveling (Byte 0): 25 => 25
3164 16:33:48.513823 Write leveling (Byte 1): 27 => 27
3165 16:33:48.513882 DramcWriteLeveling(PI) end<-----
3166 16:33:48.513939
3167 16:33:48.513994 ==
3168 16:33:48.514053 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 16:33:48.514111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 16:33:48.514178 ==
3171 16:33:48.514240 [Gating] SW mode calibration
3172 16:33:48.514299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3173 16:33:48.514358 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3174 16:33:48.514415 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
3175 16:33:48.514471 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 16:33:48.514527 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 16:33:48.514583 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 16:33:48.514639 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 16:33:48.514697 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 16:33:48.514758 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3181 16:33:48.514815 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3182 16:33:48.514871 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 16:33:48.514927 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 16:33:48.514984 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 16:33:48.515043 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 16:33:48.515099 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 16:33:48.515155 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 16:33:48.515214 1 0 24 | B1->B0 | 2626 3a3a | 0 0 | (0 0) (1 1)
3189 16:33:48.515274 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3190 16:33:48.515331 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 16:33:48.515387 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 16:33:48.515443 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 16:33:48.515501 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 16:33:48.515557 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 16:33:48.515613 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 16:33:48.515668 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3197 16:33:48.515727 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3198 16:33:48.515785 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 16:33:48.515840 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 16:33:48.515901 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 16:33:48.515957 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 16:33:48.516012 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 16:33:48.516068 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 16:33:48.516126 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 16:33:48.516183 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 16:33:48.516239 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 16:33:48.516297 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 16:33:48.516355 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 16:33:48.516413 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 16:33:48.516471 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 16:33:48.516529 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 16:33:48.516585 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3213 16:33:48.516643 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3214 16:33:48.516702 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 16:33:48.516758 Total UI for P1: 0, mck2ui 16
3216 16:33:48.516816 best dqsien dly found for B0: ( 1, 3, 26)
3217 16:33:48.516871 Total UI for P1: 0, mck2ui 16
3218 16:33:48.516927 best dqsien dly found for B1: ( 1, 3, 28)
3219 16:33:48.516982 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3220 16:33:48.517038 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3221 16:33:48.517097
3222 16:33:48.517155 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3223 16:33:48.517213 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3224 16:33:48.517268 [Gating] SW calibration Done
3225 16:33:48.517323 ==
3226 16:33:48.517379 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 16:33:48.517435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 16:33:48.517491 ==
3229 16:33:48.517550 RX Vref Scan: 0
3230 16:33:48.517610
3231 16:33:48.517666 RX Vref 0 -> 0, step: 1
3232 16:33:48.517721
3233 16:33:48.517776 RX Delay -40 -> 252, step: 8
3234 16:33:48.517832 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3235 16:33:48.517888 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3236 16:33:48.517946 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3237 16:33:48.518003 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3238 16:33:48.518063 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3239 16:33:48.518121 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3240 16:33:48.518188 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3241 16:33:48.518441 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3242 16:33:48.518505 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3243 16:33:48.518562 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3244 16:33:48.518623 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3245 16:33:48.518681 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3246 16:33:48.518738 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3247 16:33:48.518797 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3248 16:33:48.518854 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3249 16:33:48.518913 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3250 16:33:48.518970 ==
3251 16:33:48.519026 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 16:33:48.519085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 16:33:48.519143 ==
3254 16:33:48.519199 DQS Delay:
3255 16:33:48.519254 DQS0 = 0, DQS1 = 0
3256 16:33:48.519310 DQM Delay:
3257 16:33:48.519369 DQM0 = 117, DQM1 = 109
3258 16:33:48.519427 DQ Delay:
3259 16:33:48.519486 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3260 16:33:48.519542 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3261 16:33:48.519598 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3262 16:33:48.519657 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3263 16:33:48.519715
3264 16:33:48.519770
3265 16:33:48.519825 ==
3266 16:33:48.519880 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 16:33:48.519936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 16:33:48.519992 ==
3269 16:33:48.520050
3270 16:33:48.520109
3271 16:33:48.520166 TX Vref Scan disable
3272 16:33:48.520225 == TX Byte 0 ==
3273 16:33:48.520280 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3274 16:33:48.520336 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3275 16:33:48.520392 == TX Byte 1 ==
3276 16:33:48.520451 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3277 16:33:48.520509 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3278 16:33:48.520565 ==
3279 16:33:48.520621 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 16:33:48.520680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 16:33:48.520739 ==
3282 16:33:48.520795 TX Vref=22, minBit 8, minWin=25, winSum=414
3283 16:33:48.520853 TX Vref=24, minBit 8, minWin=25, winSum=421
3284 16:33:48.520913 TX Vref=26, minBit 8, minWin=25, winSum=431
3285 16:33:48.520971 TX Vref=28, minBit 9, minWin=26, winSum=435
3286 16:33:48.521026 TX Vref=30, minBit 11, minWin=26, winSum=431
3287 16:33:48.521082 TX Vref=32, minBit 11, minWin=25, winSum=429
3288 16:33:48.521138 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 28
3289 16:33:48.521195
3290 16:33:48.521249 Final TX Range 1 Vref 28
3291 16:33:48.521309
3292 16:33:48.521367 ==
3293 16:33:48.521424 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 16:33:48.521482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 16:33:48.521541 ==
3296 16:33:48.521598
3297 16:33:48.521652
3298 16:33:48.521706 TX Vref Scan disable
3299 16:33:48.521761 == TX Byte 0 ==
3300 16:33:48.521820 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3301 16:33:48.521877 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3302 16:33:48.521933 == TX Byte 1 ==
3303 16:33:48.521988 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3304 16:33:48.522049 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3305 16:33:48.522110
3306 16:33:48.522177 [DATLAT]
3307 16:33:48.522234 Freq=1200, CH1 RK0
3308 16:33:48.522290
3309 16:33:48.522345 DATLAT Default: 0xd
3310 16:33:48.522400 0, 0xFFFF, sum = 0
3311 16:33:48.522460 1, 0xFFFF, sum = 0
3312 16:33:48.522520 2, 0xFFFF, sum = 0
3313 16:33:48.522577 3, 0xFFFF, sum = 0
3314 16:33:48.522634 4, 0xFFFF, sum = 0
3315 16:33:48.522689 5, 0xFFFF, sum = 0
3316 16:33:48.522744 6, 0xFFFF, sum = 0
3317 16:33:48.522800 7, 0xFFFF, sum = 0
3318 16:33:48.522859 8, 0xFFFF, sum = 0
3319 16:33:48.522914 9, 0xFFFF, sum = 0
3320 16:33:48.522970 10, 0xFFFF, sum = 0
3321 16:33:48.523028 11, 0xFFFF, sum = 0
3322 16:33:48.523086 12, 0x0, sum = 1
3323 16:33:48.523145 13, 0x0, sum = 2
3324 16:33:48.523203 14, 0x0, sum = 3
3325 16:33:48.523259 15, 0x0, sum = 4
3326 16:33:48.523315 best_step = 13
3327 16:33:48.523369
3328 16:33:48.523424 ==
3329 16:33:48.523482 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 16:33:48.523542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 16:33:48.523598 ==
3332 16:33:48.523654 RX Vref Scan: 1
3333 16:33:48.523713
3334 16:33:48.523771 Set Vref Range= 32 -> 127
3335 16:33:48.523827
3336 16:33:48.523884 RX Vref 32 -> 127, step: 1
3337 16:33:48.523939
3338 16:33:48.523994 RX Delay -21 -> 252, step: 4
3339 16:33:48.524053
3340 16:33:48.524110 Set Vref, RX VrefLevel [Byte0]: 32
3341 16:33:48.524168 [Byte1]: 32
3342 16:33:48.524222
3343 16:33:48.524277 Set Vref, RX VrefLevel [Byte0]: 33
3344 16:33:48.524331 [Byte1]: 33
3345 16:33:48.524385
3346 16:33:48.524443 Set Vref, RX VrefLevel [Byte0]: 34
3347 16:33:48.524502 [Byte1]: 34
3348 16:33:48.524558
3349 16:33:48.524613 Set Vref, RX VrefLevel [Byte0]: 35
3350 16:33:48.524668 [Byte1]: 35
3351 16:33:48.524723
3352 16:33:48.524777 Set Vref, RX VrefLevel [Byte0]: 36
3353 16:33:48.524835 [Byte1]: 36
3354 16:33:48.524893
3355 16:33:48.524949 Set Vref, RX VrefLevel [Byte0]: 37
3356 16:33:48.525005 [Byte1]: 37
3357 16:33:48.525059
3358 16:33:48.525117 Set Vref, RX VrefLevel [Byte0]: 38
3359 16:33:48.525175 [Byte1]: 38
3360 16:33:48.525232
3361 16:33:48.525289 Set Vref, RX VrefLevel [Byte0]: 39
3362 16:33:48.525345 [Byte1]: 39
3363 16:33:48.525400
3364 16:33:48.525455 Set Vref, RX VrefLevel [Byte0]: 40
3365 16:33:48.525512 [Byte1]: 40
3366 16:33:48.525567
3367 16:33:48.525623 Set Vref, RX VrefLevel [Byte0]: 41
3368 16:33:48.525682 [Byte1]: 41
3369 16:33:48.525737
3370 16:33:48.525791 Set Vref, RX VrefLevel [Byte0]: 42
3371 16:33:48.525846 [Byte1]: 42
3372 16:33:48.525904
3373 16:33:48.525961 Set Vref, RX VrefLevel [Byte0]: 43
3374 16:33:48.526015 [Byte1]: 43
3375 16:33:48.526070
3376 16:33:48.526129 Set Vref, RX VrefLevel [Byte0]: 44
3377 16:33:48.526208 [Byte1]: 44
3378 16:33:48.526276
3379 16:33:48.526334 Set Vref, RX VrefLevel [Byte0]: 45
3380 16:33:48.526390 [Byte1]: 45
3381 16:33:48.526446
3382 16:33:48.526516 Set Vref, RX VrefLevel [Byte0]: 46
3383 16:33:48.526572 [Byte1]: 46
3384 16:33:48.526627
3385 16:33:48.526694 Set Vref, RX VrefLevel [Byte0]: 47
3386 16:33:48.526751 [Byte1]: 47
3387 16:33:48.526806
3388 16:33:48.526878 Set Vref, RX VrefLevel [Byte0]: 48
3389 16:33:48.526934 [Byte1]: 48
3390 16:33:48.526989
3391 16:33:48.527049 Set Vref, RX VrefLevel [Byte0]: 49
3392 16:33:48.527104 [Byte1]: 49
3393 16:33:48.527159
3394 16:33:48.527224 Set Vref, RX VrefLevel [Byte0]: 50
3395 16:33:48.527279 [Byte1]: 50
3396 16:33:48.527334
3397 16:33:48.527393 Set Vref, RX VrefLevel [Byte0]: 51
3398 16:33:48.527449 [Byte1]: 51
3399 16:33:48.527503
3400 16:33:48.527561 Set Vref, RX VrefLevel [Byte0]: 52
3401 16:33:48.527815 [Byte1]: 52
3402 16:33:48.527881
3403 16:33:48.527938 Set Vref, RX VrefLevel [Byte0]: 53
3404 16:33:48.527998 [Byte1]: 53
3405 16:33:48.528056
3406 16:33:48.528111 Set Vref, RX VrefLevel [Byte0]: 54
3407 16:33:48.528169 [Byte1]: 54
3408 16:33:48.528224
3409 16:33:48.528278 Set Vref, RX VrefLevel [Byte0]: 55
3410 16:33:48.528334 [Byte1]: 55
3411 16:33:48.528393
3412 16:33:48.528450 Set Vref, RX VrefLevel [Byte0]: 56
3413 16:33:48.528506 [Byte1]: 56
3414 16:33:48.528564
3415 16:33:48.528619 Set Vref, RX VrefLevel [Byte0]: 57
3416 16:33:48.528675 [Byte1]: 57
3417 16:33:48.528730
3418 16:33:48.528788 Set Vref, RX VrefLevel [Byte0]: 58
3419 16:33:48.528846 [Byte1]: 58
3420 16:33:48.528901
3421 16:33:48.528959 Set Vref, RX VrefLevel [Byte0]: 59
3422 16:33:48.529017 [Byte1]: 59
3423 16:33:48.529076
3424 16:33:48.529131 Set Vref, RX VrefLevel [Byte0]: 60
3425 16:33:48.529186 [Byte1]: 60
3426 16:33:48.529241
3427 16:33:48.529295 Set Vref, RX VrefLevel [Byte0]: 61
3428 16:33:48.529351 [Byte1]: 61
3429 16:33:48.529408
3430 16:33:48.529466 Set Vref, RX VrefLevel [Byte0]: 62
3431 16:33:48.529523 [Byte1]: 62
3432 16:33:48.529577
3433 16:33:48.529631 Set Vref, RX VrefLevel [Byte0]: 63
3434 16:33:48.529687 [Byte1]: 63
3435 16:33:48.529741
3436 16:33:48.529799 Set Vref, RX VrefLevel [Byte0]: 64
3437 16:33:48.529857 [Byte1]: 64
3438 16:33:48.529913
3439 16:33:48.529968 Set Vref, RX VrefLevel [Byte0]: 65
3440 16:33:48.530023 [Byte1]: 65
3441 16:33:48.530078
3442 16:33:48.530136 Set Vref, RX VrefLevel [Byte0]: 66
3443 16:33:48.530217 [Byte1]: 66
3444 16:33:48.530275
3445 16:33:48.530330 Set Vref, RX VrefLevel [Byte0]: 67
3446 16:33:48.530385 [Byte1]: 67
3447 16:33:48.530443
3448 16:33:48.530499 Set Vref, RX VrefLevel [Byte0]: 68
3449 16:33:48.530554 [Byte1]: 68
3450 16:33:48.530609
3451 16:33:48.530667 Set Vref, RX VrefLevel [Byte0]: 69
3452 16:33:48.530724 [Byte1]: 69
3453 16:33:48.530779
3454 16:33:48.530834 Final RX Vref Byte 0 = 52 to rank0
3455 16:33:48.530940 Final RX Vref Byte 1 = 56 to rank0
3456 16:33:48.531037 Final RX Vref Byte 0 = 52 to rank1
3457 16:33:48.531096 Final RX Vref Byte 1 = 56 to rank1==
3458 16:33:48.531179 Dram Type= 6, Freq= 0, CH_1, rank 0
3459 16:33:48.531271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 16:33:48.531381 ==
3461 16:33:48.531469 DQS Delay:
3462 16:33:48.531559 DQS0 = 0, DQS1 = 0
3463 16:33:48.531619 DQM Delay:
3464 16:33:48.531685 DQM0 = 116, DQM1 = 110
3465 16:33:48.531747 DQ Delay:
3466 16:33:48.531803 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =114
3467 16:33:48.531860 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =112
3468 16:33:48.531916 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3469 16:33:48.531993 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3470 16:33:48.532087
3471 16:33:48.532145
3472 16:33:48.532201 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3473 16:33:48.532261 CH1 RK0: MR19=403, MR18=2F5
3474 16:33:48.532317 CH1_RK0: MR19=0x403, MR18=0x2F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3475 16:33:48.532373
3476 16:33:48.532428 ----->DramcWriteLeveling(PI) begin...
3477 16:33:48.532487 ==
3478 16:33:48.532543 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 16:33:48.532599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 16:33:48.532658 ==
3481 16:33:48.532716 Write leveling (Byte 0): 24 => 24
3482 16:33:48.532776 Write leveling (Byte 1): 28 => 28
3483 16:33:48.532833 DramcWriteLeveling(PI) end<-----
3484 16:33:48.532888
3485 16:33:48.532943 ==
3486 16:33:48.533001 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 16:33:48.533060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 16:33:48.533118 ==
3489 16:33:48.533173 [Gating] SW mode calibration
3490 16:33:48.533229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3491 16:33:48.533285 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3492 16:33:48.533341 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3493 16:33:48.533397 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 16:33:48.533455 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 16:33:48.533516 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 16:33:48.533571 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 16:33:48.533627 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 16:33:48.533682 0 15 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
3499 16:33:48.533738 0 15 28 | B1->B0 | 2323 2929 | 0 1 | (1 0) (1 0)
3500 16:33:48.533796 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 16:33:48.533856 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 16:33:48.533914 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 16:33:48.533971 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 16:33:48.534028 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 16:33:48.534083 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 16:33:48.534143 1 0 24 | B1->B0 | 3b3b 2b2b | 1 0 | (1 1) (0 0)
3507 16:33:48.534213 1 0 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
3508 16:33:48.534272 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 16:33:48.534329 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 16:33:48.534385 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 16:33:48.534441 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 16:33:48.534496 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 16:33:48.534551 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 16:33:48.534609 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3515 16:33:48.534668 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3516 16:33:48.534725 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 16:33:48.534781 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 16:33:48.534836 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 16:33:48.534892 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 16:33:48.534947 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 16:33:48.535005 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 16:33:48.535064 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 16:33:48.535317 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 16:33:48.535383 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 16:33:48.535444 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 16:33:48.535501 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 16:33:48.535556 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 16:33:48.535612 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 16:33:48.535667 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 16:33:48.535725 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3531 16:33:48.535784 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3532 16:33:48.535842 Total UI for P1: 0, mck2ui 16
3533 16:33:48.535897 best dqsien dly found for B1: ( 1, 3, 24)
3534 16:33:48.535952 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 16:33:48.536011 Total UI for P1: 0, mck2ui 16
3536 16:33:48.536070 best dqsien dly found for B0: ( 1, 3, 26)
3537 16:33:48.536128 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3538 16:33:48.536184 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3539 16:33:48.536239
3540 16:33:48.536294 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3541 16:33:48.536351 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3542 16:33:48.536409 [Gating] SW calibration Done
3543 16:33:48.536468 ==
3544 16:33:48.536525 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 16:33:48.536584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 16:33:48.536642 ==
3547 16:33:48.536699 RX Vref Scan: 0
3548 16:33:48.536755
3549 16:33:48.536812 RX Vref 0 -> 0, step: 1
3550 16:33:48.536870
3551 16:33:48.536925 RX Delay -40 -> 252, step: 8
3552 16:33:48.536984 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3553 16:33:48.537043 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3554 16:33:48.537099 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3555 16:33:48.537154 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3556 16:33:48.537211 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3557 16:33:48.537268 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3558 16:33:48.537327 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3559 16:33:48.537384 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3560 16:33:48.537439 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3561 16:33:48.537497 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3562 16:33:48.537553 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3563 16:33:48.537608 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3564 16:33:48.537666 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3565 16:33:48.537722 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3566 16:33:48.537777 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3567 16:33:48.537839 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3568 16:33:48.537896 ==
3569 16:33:48.537951 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 16:33:48.538007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 16:33:48.538067 ==
3572 16:33:48.538132 DQS Delay:
3573 16:33:48.538226 DQS0 = 0, DQS1 = 0
3574 16:33:48.538301 DQM Delay:
3575 16:33:48.538364 DQM0 = 116, DQM1 = 109
3576 16:33:48.538441 DQ Delay:
3577 16:33:48.538514 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3578 16:33:48.538586 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3579 16:33:48.538656 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3580 16:33:48.538724 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3581 16:33:48.538796
3582 16:33:48.538859
3583 16:33:48.538958 ==
3584 16:33:48.539061 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 16:33:48.539156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 16:33:48.539253 ==
3587 16:33:48.539359
3588 16:33:48.539460
3589 16:33:48.539548 TX Vref Scan disable
3590 16:33:48.539659 == TX Byte 0 ==
3591 16:33:48.539754 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3592 16:33:48.539830 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3593 16:33:48.539902 == TX Byte 1 ==
3594 16:33:48.539989 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3595 16:33:48.540083 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3596 16:33:48.540184 ==
3597 16:33:48.540288 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 16:33:48.540393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 16:33:48.540497 ==
3600 16:33:48.540606 TX Vref=22, minBit 8, minWin=25, winSum=423
3601 16:33:48.540707 TX Vref=24, minBit 8, minWin=25, winSum=428
3602 16:33:48.540794 TX Vref=26, minBit 9, minWin=26, winSum=432
3603 16:33:48.540886 TX Vref=28, minBit 8, minWin=26, winSum=434
3604 16:33:48.540974 TX Vref=30, minBit 8, minWin=26, winSum=436
3605 16:33:48.541064 TX Vref=32, minBit 9, minWin=25, winSum=432
3606 16:33:48.541150 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 30
3607 16:33:48.541235
3608 16:33:48.541325 Final TX Range 1 Vref 30
3609 16:33:48.541412
3610 16:33:48.541496 ==
3611 16:33:48.541581 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 16:33:48.541669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 16:33:48.541754 ==
3614 16:33:48.541841
3615 16:33:48.541927
3616 16:33:48.542013 TX Vref Scan disable
3617 16:33:48.542103 == TX Byte 0 ==
3618 16:33:48.542197 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3619 16:33:48.542314 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3620 16:33:48.542401 == TX Byte 1 ==
3621 16:33:48.542509 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3622 16:33:48.542598 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3623 16:33:48.542687
3624 16:33:48.542776 [DATLAT]
3625 16:33:48.542861 Freq=1200, CH1 RK1
3626 16:33:48.542951
3627 16:33:48.543036 DATLAT Default: 0xd
3628 16:33:48.543128 0, 0xFFFF, sum = 0
3629 16:33:48.543215 1, 0xFFFF, sum = 0
3630 16:33:48.543308 2, 0xFFFF, sum = 0
3631 16:33:48.543396 3, 0xFFFF, sum = 0
3632 16:33:48.543483 4, 0xFFFF, sum = 0
3633 16:33:48.543569 5, 0xFFFF, sum = 0
3634 16:33:48.543659 6, 0xFFFF, sum = 0
3635 16:33:48.543749 7, 0xFFFF, sum = 0
3636 16:33:48.543836 8, 0xFFFF, sum = 0
3637 16:33:48.543925 9, 0xFFFF, sum = 0
3638 16:33:48.544016 10, 0xFFFF, sum = 0
3639 16:33:48.544103 11, 0xFFFF, sum = 0
3640 16:33:48.544189 12, 0x0, sum = 1
3641 16:33:48.544278 13, 0x0, sum = 2
3642 16:33:48.544365 14, 0x0, sum = 3
3643 16:33:48.544451 15, 0x0, sum = 4
3644 16:33:48.544542 best_step = 13
3645 16:33:48.544627
3646 16:33:48.544716 ==
3647 16:33:48.544803 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 16:33:48.544888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 16:33:48.544973 ==
3650 16:33:48.545060 RX Vref Scan: 0
3651 16:33:48.545144
3652 16:33:48.545230 RX Vref 0 -> 0, step: 1
3653 16:33:48.545317
3654 16:33:48.545403 RX Delay -21 -> 252, step: 4
3655 16:33:48.545491 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3656 16:33:48.545581 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3657 16:33:48.545666 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3658 16:33:48.545756 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3659 16:33:48.545843 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3660 16:33:48.545928 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3661 16:33:48.546212 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3662 16:33:48.546281 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3663 16:33:48.546339 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3664 16:33:48.546396 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3665 16:33:48.546455 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3666 16:33:48.546513 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3667 16:33:48.546569 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3668 16:33:48.546627 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3669 16:33:48.546682 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3670 16:33:48.546738 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3671 16:33:48.546793 ==
3672 16:33:48.546849 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 16:33:48.546908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 16:33:48.546968 ==
3675 16:33:48.547024 DQS Delay:
3676 16:33:48.547079 DQS0 = 0, DQS1 = 0
3677 16:33:48.547134 DQM Delay:
3678 16:33:48.547189 DQM0 = 117, DQM1 = 110
3679 16:33:48.547244 DQ Delay:
3680 16:33:48.547302 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3681 16:33:48.547361 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =116
3682 16:33:48.547418 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3683 16:33:48.547474 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3684 16:33:48.547529
3685 16:33:48.547585
3686 16:33:48.547639 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3687 16:33:48.547699 CH1 RK1: MR19=303, MR18=F2ED
3688 16:33:48.547760 CH1_RK1: MR19=0x303, MR18=0xF2ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3689 16:33:48.547816 [RxdqsGatingPostProcess] freq 1200
3690 16:33:48.547871 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3691 16:33:48.547927 best DQS0 dly(2T, 0.5T) = (0, 11)
3692 16:33:48.547982 best DQS1 dly(2T, 0.5T) = (0, 11)
3693 16:33:48.548039 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3694 16:33:48.548098 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3695 16:33:48.548154 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 16:33:48.548209 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 16:33:48.548264 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 16:33:48.548319 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 16:33:48.548378 Pre-setting of DQS Precalculation
3700 16:33:48.548439 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3701 16:33:48.548495 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3702 16:33:48.548553 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3703 16:33:48.548608
3704 16:33:48.548663
3705 16:33:48.548720 [Calibration Summary] 2400 Mbps
3706 16:33:48.548779 CH 0, Rank 0
3707 16:33:48.548835 SW Impedance : PASS
3708 16:33:48.548890 DUTY Scan : NO K
3709 16:33:48.548948 ZQ Calibration : PASS
3710 16:33:48.549003 Jitter Meter : NO K
3711 16:33:48.549058 CBT Training : PASS
3712 16:33:48.549115 Write leveling : PASS
3713 16:33:48.549173 RX DQS gating : PASS
3714 16:33:48.549231 RX DQ/DQS(RDDQC) : PASS
3715 16:33:48.549288 TX DQ/DQS : PASS
3716 16:33:48.549343 RX DATLAT : PASS
3717 16:33:48.549403 RX DQ/DQS(Engine): PASS
3718 16:33:48.549460 TX OE : NO K
3719 16:33:48.549515 All Pass.
3720 16:33:48.549570
3721 16:33:48.549624 CH 0, Rank 1
3722 16:33:48.549682 SW Impedance : PASS
3723 16:33:48.549737 DUTY Scan : NO K
3724 16:33:48.549791 ZQ Calibration : PASS
3725 16:33:48.549846 Jitter Meter : NO K
3726 16:33:48.549904 CBT Training : PASS
3727 16:33:48.549962 Write leveling : PASS
3728 16:33:48.550019 RX DQS gating : PASS
3729 16:33:48.550074 RX DQ/DQS(RDDQC) : PASS
3730 16:33:48.550128 TX DQ/DQS : PASS
3731 16:33:48.550220 RX DATLAT : PASS
3732 16:33:48.550278 RX DQ/DQS(Engine): PASS
3733 16:33:48.550334 TX OE : NO K
3734 16:33:48.550391 All Pass.
3735 16:33:48.550450
3736 16:33:48.550507 CH 1, Rank 0
3737 16:33:48.550562 SW Impedance : PASS
3738 16:33:48.550618 DUTY Scan : NO K
3739 16:33:48.550674 ZQ Calibration : PASS
3740 16:33:48.550729 Jitter Meter : NO K
3741 16:33:48.550792 CBT Training : PASS
3742 16:33:48.550850 Write leveling : PASS
3743 16:33:48.550905 RX DQS gating : PASS
3744 16:33:48.550960 RX DQ/DQS(RDDQC) : PASS
3745 16:33:48.551018 TX DQ/DQS : PASS
3746 16:33:48.551079 RX DATLAT : PASS
3747 16:33:48.551134 RX DQ/DQS(Engine): PASS
3748 16:33:48.551192 TX OE : NO K
3749 16:33:48.551251 All Pass.
3750 16:33:48.551308
3751 16:33:48.551363 CH 1, Rank 1
3752 16:33:48.551420 SW Impedance : PASS
3753 16:33:48.551478 DUTY Scan : NO K
3754 16:33:48.551533 ZQ Calibration : PASS
3755 16:33:48.551592 Jitter Meter : NO K
3756 16:33:48.551648 CBT Training : PASS
3757 16:33:48.551703 Write leveling : PASS
3758 16:33:48.551758 RX DQS gating : PASS
3759 16:33:48.551815 RX DQ/DQS(RDDQC) : PASS
3760 16:33:48.551871 TX DQ/DQS : PASS
3761 16:33:48.551926 RX DATLAT : PASS
3762 16:33:48.551983 RX DQ/DQS(Engine): PASS
3763 16:33:48.552041 TX OE : NO K
3764 16:33:48.552098 All Pass.
3765 16:33:48.552153
3766 16:33:48.552207 DramC Write-DBI off
3767 16:33:48.552264 PER_BANK_REFRESH: Hybrid Mode
3768 16:33:48.552323 TX_TRACKING: ON
3769 16:33:48.552381 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3770 16:33:48.552437 [FAST_K] Save calibration result to emmc
3771 16:33:48.552493 dramc_set_vcore_voltage set vcore to 650000
3772 16:33:48.552548 Read voltage for 600, 5
3773 16:33:48.552603 Vio18 = 0
3774 16:33:48.552660 Vcore = 650000
3775 16:33:48.552720 Vdram = 0
3776 16:33:48.552775 Vddq = 0
3777 16:33:48.552829 Vmddr = 0
3778 16:33:48.552884 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3779 16:33:48.552939 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3780 16:33:48.552995 MEM_TYPE=3, freq_sel=19
3781 16:33:48.553053 sv_algorithm_assistance_LP4_1600
3782 16:33:48.553112 ============ PULL DRAM RESETB DOWN ============
3783 16:33:48.553171 ========== PULL DRAM RESETB DOWN end =========
3784 16:33:48.553229 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3785 16:33:48.553285 ===================================
3786 16:33:48.553340 LPDDR4 DRAM CONFIGURATION
3787 16:33:48.553396 ===================================
3788 16:33:48.553454 EX_ROW_EN[0] = 0x0
3789 16:33:48.553510 EX_ROW_EN[1] = 0x0
3790 16:33:48.553565 LP4Y_EN = 0x0
3791 16:33:48.553619 WORK_FSP = 0x0
3792 16:33:48.553677 WL = 0x2
3793 16:33:48.553732 RL = 0x2
3794 16:33:48.553787 BL = 0x2
3795 16:33:48.553844 RPST = 0x0
3796 16:33:48.553902 RD_PRE = 0x0
3797 16:33:48.553958 WR_PRE = 0x1
3798 16:33:48.554014 WR_PST = 0x0
3799 16:33:48.554068 DBI_WR = 0x0
3800 16:33:48.554122 DBI_RD = 0x0
3801 16:33:48.554185 OTF = 0x1
3802 16:33:48.554242 ===================================
3803 16:33:48.554497 ===================================
3804 16:33:48.554560 ANA top config
3805 16:33:48.554617 ===================================
3806 16:33:48.554676 DLL_ASYNC_EN = 0
3807 16:33:48.554735 ALL_SLAVE_EN = 1
3808 16:33:48.554795 NEW_RANK_MODE = 1
3809 16:33:48.554855 DLL_IDLE_MODE = 1
3810 16:33:48.554911 LP45_APHY_COMB_EN = 1
3811 16:33:48.554967 TX_ODT_DIS = 1
3812 16:33:48.555022 NEW_8X_MODE = 1
3813 16:33:48.555081 ===================================
3814 16:33:48.555139 ===================================
3815 16:33:48.555196 data_rate = 1200
3816 16:33:48.555251 CKR = 1
3817 16:33:48.555306 DQ_P2S_RATIO = 8
3818 16:33:48.555362 ===================================
3819 16:33:48.555417 CA_P2S_RATIO = 8
3820 16:33:48.555475 DQ_CA_OPEN = 0
3821 16:33:48.555529 DQ_SEMI_OPEN = 0
3822 16:33:48.555584 CA_SEMI_OPEN = 0
3823 16:33:48.555642 CA_FULL_RATE = 0
3824 16:33:48.555701 DQ_CKDIV4_EN = 1
3825 16:33:48.555758 CA_CKDIV4_EN = 1
3826 16:33:48.555812 CA_PREDIV_EN = 0
3827 16:33:48.555867 PH8_DLY = 0
3828 16:33:48.555921 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3829 16:33:48.555976 DQ_AAMCK_DIV = 4
3830 16:33:48.556033 CA_AAMCK_DIV = 4
3831 16:33:48.556091 CA_ADMCK_DIV = 4
3832 16:33:48.556148 DQ_TRACK_CA_EN = 0
3833 16:33:48.556205 CA_PICK = 600
3834 16:33:48.556263 CA_MCKIO = 600
3835 16:33:48.556321 MCKIO_SEMI = 0
3836 16:33:48.556376 PLL_FREQ = 2288
3837 16:33:48.556431 DQ_UI_PI_RATIO = 32
3838 16:33:48.556488 CA_UI_PI_RATIO = 0
3839 16:33:48.556543 ===================================
3840 16:33:48.556599 ===================================
3841 16:33:48.556656 memory_type:LPDDR4
3842 16:33:48.556714 GP_NUM : 10
3843 16:33:48.556771 SRAM_EN : 1
3844 16:33:48.556826 MD32_EN : 0
3845 16:33:48.556881 ===================================
3846 16:33:48.556936 [ANA_INIT] >>>>>>>>>>>>>>
3847 16:33:48.556991 <<<<<< [CONFIGURE PHASE]: ANA_TX
3848 16:33:48.557049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3849 16:33:48.557107 ===================================
3850 16:33:48.557169 data_rate = 1200,PCW = 0X5800
3851 16:33:48.557226 ===================================
3852 16:33:48.557281 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3853 16:33:48.557336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 16:33:48.557391 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3855 16:33:48.557450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3856 16:33:48.557509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3857 16:33:48.557567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3858 16:33:48.557625 [ANA_INIT] flow start
3859 16:33:48.557680 [ANA_INIT] PLL >>>>>>>>
3860 16:33:48.557736 [ANA_INIT] PLL <<<<<<<<
3861 16:33:48.557794 [ANA_INIT] MIDPI >>>>>>>>
3862 16:33:48.557851 [ANA_INIT] MIDPI <<<<<<<<
3863 16:33:48.557906 [ANA_INIT] DLL >>>>>>>>
3864 16:33:48.557961 [ANA_INIT] flow end
3865 16:33:48.558016 ============ LP4 DIFF to SE enter ============
3866 16:33:48.558072 ============ LP4 DIFF to SE exit ============
3867 16:33:48.558130 [ANA_INIT] <<<<<<<<<<<<<
3868 16:33:48.558206 [Flow] Enable top DCM control >>>>>
3869 16:33:48.558263 [Flow] Enable top DCM control <<<<<
3870 16:33:48.558319 Enable DLL master slave shuffle
3871 16:33:48.558378 ==============================================================
3872 16:33:48.558434 Gating Mode config
3873 16:33:48.558489 ==============================================================
3874 16:33:48.558547 Config description:
3875 16:33:48.558605 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3876 16:33:48.558661 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3877 16:33:48.558717 SELPH_MODE 0: By rank 1: By Phase
3878 16:33:48.558773 ==============================================================
3879 16:33:48.558828 GAT_TRACK_EN = 1
3880 16:33:48.558886 RX_GATING_MODE = 2
3881 16:33:48.558944 RX_GATING_TRACK_MODE = 2
3882 16:33:48.559001 SELPH_MODE = 1
3883 16:33:48.559056 PICG_EARLY_EN = 1
3884 16:33:48.559114 VALID_LAT_VALUE = 1
3885 16:33:48.559170 ==============================================================
3886 16:33:48.559226 Enter into Gating configuration >>>>
3887 16:33:48.559281 Exit from Gating configuration <<<<
3888 16:33:48.559339 Enter into DVFS_PRE_config >>>>>
3889 16:33:48.559397 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3890 16:33:48.559469 Exit from DVFS_PRE_config <<<<<
3891 16:33:48.559530 Enter into PICG configuration >>>>
3892 16:33:48.561756 Exit from PICG configuration <<<<
3893 16:33:48.564571 [RX_INPUT] configuration >>>>>
3894 16:33:48.568265 [RX_INPUT] configuration <<<<<
3895 16:33:48.571096 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3896 16:33:48.577718 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3897 16:33:48.584411 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 16:33:48.588033 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 16:33:48.594144 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 16:33:48.601045 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 16:33:48.604421 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3902 16:33:48.610996 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3903 16:33:48.613915 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3904 16:33:48.617230 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3905 16:33:48.620575 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3906 16:33:48.627483 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3907 16:33:48.630843 ===================================
3908 16:33:48.633614 LPDDR4 DRAM CONFIGURATION
3909 16:33:48.637197 ===================================
3910 16:33:48.637277 EX_ROW_EN[0] = 0x0
3911 16:33:48.640788 EX_ROW_EN[1] = 0x0
3912 16:33:48.640893 LP4Y_EN = 0x0
3913 16:33:48.643534 WORK_FSP = 0x0
3914 16:33:48.643609 WL = 0x2
3915 16:33:48.647179 RL = 0x2
3916 16:33:48.647254 BL = 0x2
3917 16:33:48.650957 RPST = 0x0
3918 16:33:48.651035 RD_PRE = 0x0
3919 16:33:48.653536 WR_PRE = 0x1
3920 16:33:48.653635 WR_PST = 0x0
3921 16:33:48.656805 DBI_WR = 0x0
3922 16:33:48.656904 DBI_RD = 0x0
3923 16:33:48.660123 OTF = 0x1
3924 16:33:48.663775 ===================================
3925 16:33:48.666514 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3926 16:33:48.670067 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3927 16:33:48.676955 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 16:33:48.680025 ===================================
3929 16:33:48.683265 LPDDR4 DRAM CONFIGURATION
3930 16:33:48.686521 ===================================
3931 16:33:48.686598 EX_ROW_EN[0] = 0x10
3932 16:33:48.690061 EX_ROW_EN[1] = 0x0
3933 16:33:48.690177 LP4Y_EN = 0x0
3934 16:33:48.693533 WORK_FSP = 0x0
3935 16:33:48.693606 WL = 0x2
3936 16:33:48.696290 RL = 0x2
3937 16:33:48.801093 BL = 0x2
3938 16:33:48.801965 RPST = 0x0
3939 16:33:48.802481 RD_PRE = 0x0
3940 16:33:48.802921 WR_PRE = 0x1
3941 16:33:48.803244 WR_PST = 0x0
3942 16:33:48.803548 DBI_WR = 0x0
3943 16:33:48.803842 DBI_RD = 0x0
3944 16:33:48.804134 OTF = 0x1
3945 16:33:48.804424 ===================================
3946 16:33:48.804735 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3947 16:33:48.805023 nWR fixed to 30
3948 16:33:48.805311 [ModeRegInit_LP4] CH0 RK0
3949 16:33:48.805592 [ModeRegInit_LP4] CH0 RK1
3950 16:33:48.805874 [ModeRegInit_LP4] CH1 RK0
3951 16:33:48.806366 [ModeRegInit_LP4] CH1 RK1
3952 16:33:48.806666 match AC timing 17
3953 16:33:48.806970 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3954 16:33:48.807273 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3955 16:33:48.807554 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3956 16:33:48.807836 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3957 16:33:48.808118 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3958 16:33:48.808401 ==
3959 16:33:48.808762 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 16:33:48.809162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 16:33:48.809455 ==
3962 16:33:48.809741 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 16:33:48.810024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3964 16:33:48.810355 [CA 0] Center 36 (6~66) winsize 61
3965 16:33:48.810641 [CA 1] Center 36 (6~66) winsize 61
3966 16:33:48.811007 [CA 2] Center 34 (4~65) winsize 62
3967 16:33:48.811305 [CA 3] Center 34 (4~65) winsize 62
3968 16:33:48.811587 [CA 4] Center 33 (3~64) winsize 62
3969 16:33:48.811864 [CA 5] Center 33 (3~64) winsize 62
3970 16:33:48.812172
3971 16:33:48.812570 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3972 16:33:48.812863
3973 16:33:48.813213 [CATrainingPosCal] consider 1 rank data
3974 16:33:48.813552 u2DelayCellTimex100 = 270/100 ps
3975 16:33:48.813929 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3976 16:33:48.814371 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3977 16:33:48.815986 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3978 16:33:48.822285 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3979 16:33:48.825740 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 16:33:48.829151 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 16:33:48.829509
3982 16:33:48.832300 CA PerBit enable=1, Macro0, CA PI delay=33
3983 16:33:48.832605
3984 16:33:48.835818 [CBTSetCACLKResult] CA Dly = 33
3985 16:33:48.836121 CS Dly: 4 (0~35)
3986 16:33:48.836364 ==
3987 16:33:48.839171 Dram Type= 6, Freq= 0, CH_0, rank 1
3988 16:33:48.845495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 16:33:48.845901 ==
3990 16:33:48.848752 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 16:33:48.855627 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3992 16:33:48.859036 [CA 0] Center 36 (6~66) winsize 61
3993 16:33:48.861797 [CA 1] Center 36 (6~66) winsize 61
3994 16:33:48.865613 [CA 2] Center 34 (4~65) winsize 62
3995 16:33:48.868583 [CA 3] Center 34 (4~64) winsize 61
3996 16:33:48.871960 [CA 4] Center 33 (2~64) winsize 63
3997 16:33:48.875512 [CA 5] Center 33 (2~64) winsize 63
3998 16:33:48.875993
3999 16:33:48.878945 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4000 16:33:48.879426
4001 16:33:48.881805 [CATrainingPosCal] consider 2 rank data
4002 16:33:48.885262 u2DelayCellTimex100 = 270/100 ps
4003 16:33:48.888678 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4004 16:33:48.895504 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4005 16:33:48.898778 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 16:33:48.901751 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4007 16:33:48.905295 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 16:33:48.908869 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4009 16:33:48.909343
4010 16:33:48.911556 CA PerBit enable=1, Macro0, CA PI delay=33
4011 16:33:48.911985
4012 16:33:48.915072 [CBTSetCACLKResult] CA Dly = 33
4013 16:33:48.918684 CS Dly: 5 (0~37)
4014 16:33:48.919108
4015 16:33:48.921394 ----->DramcWriteLeveling(PI) begin...
4016 16:33:48.921825 ==
4017 16:33:48.924788 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 16:33:48.928090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 16:33:48.928516 ==
4020 16:33:48.931515 Write leveling (Byte 0): 32 => 32
4021 16:33:48.934950 Write leveling (Byte 1): 31 => 31
4022 16:33:48.937603 DramcWriteLeveling(PI) end<-----
4023 16:33:48.938214
4024 16:33:48.938703 ==
4025 16:33:48.941055 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 16:33:48.944457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 16:33:48.944901 ==
4028 16:33:48.947746 [Gating] SW mode calibration
4029 16:33:48.954378 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4030 16:33:48.961126 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4031 16:33:48.965000 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 16:33:48.967718 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 16:33:48.974337 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 16:33:48.977649 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4035 16:33:48.981144 0 9 16 | B1->B0 | 2f2f 2828 | 0 0 | (0 1) (0 0)
4036 16:33:48.987366 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 16:33:48.990626 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 16:33:48.994124 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 16:33:49.000425 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 16:33:49.004079 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 16:33:49.007404 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 16:33:49.013839 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4043 16:33:49.017327 0 10 16 | B1->B0 | 3434 3c3c | 0 0 | (0 0) (0 0)
4044 16:33:49.020788 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 16:33:49.027049 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 16:33:49.030448 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 16:33:49.033317 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 16:33:49.040529 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 16:33:49.043330 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 16:33:49.046673 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 16:33:49.053624 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4052 16:33:49.057036 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 16:33:49.059713 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 16:33:49.066870 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 16:33:49.069618 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 16:33:49.072799 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 16:33:49.079726 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 16:33:49.083149 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 16:33:49.086279 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 16:33:49.093103 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 16:33:49.096702 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 16:33:49.099346 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 16:33:49.106340 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 16:33:49.109649 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 16:33:49.112412 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 16:33:49.119331 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4067 16:33:49.122643 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4068 16:33:49.125946 Total UI for P1: 0, mck2ui 16
4069 16:33:49.129091 best dqsien dly found for B0: ( 0, 13, 12)
4070 16:33:49.132641 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 16:33:49.135590 Total UI for P1: 0, mck2ui 16
4072 16:33:49.138931 best dqsien dly found for B1: ( 0, 13, 16)
4073 16:33:49.142284 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4074 16:33:49.149469 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4075 16:33:49.149977
4076 16:33:49.152009 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4077 16:33:49.155507 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4078 16:33:49.158858 [Gating] SW calibration Done
4079 16:33:49.159307 ==
4080 16:33:49.162233 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 16:33:49.165572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 16:33:49.166030 ==
4083 16:33:49.168954 RX Vref Scan: 0
4084 16:33:49.169373
4085 16:33:49.169704 RX Vref 0 -> 0, step: 1
4086 16:33:49.170032
4087 16:33:49.171975 RX Delay -230 -> 252, step: 16
4088 16:33:49.175448 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4089 16:33:49.182403 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4090 16:33:49.185719 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4091 16:33:49.188781 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4092 16:33:49.191844 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4093 16:33:49.198685 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4094 16:33:49.201798 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4095 16:33:49.205002 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4096 16:33:49.208685 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4097 16:33:49.211987 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4098 16:33:49.218274 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4099 16:33:49.221840 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4100 16:33:49.225248 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4101 16:33:49.228564 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4102 16:33:49.235302 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4103 16:33:49.238539 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4104 16:33:49.238987 ==
4105 16:33:49.241393 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 16:33:49.244977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 16:33:49.245397 ==
4108 16:33:49.248388 DQS Delay:
4109 16:33:49.248803 DQS0 = 0, DQS1 = 0
4110 16:33:49.251906 DQM Delay:
4111 16:33:49.252493 DQM0 = 43, DQM1 = 31
4112 16:33:49.252937 DQ Delay:
4113 16:33:49.254517 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4114 16:33:49.258116 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4115 16:33:49.261609 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4116 16:33:49.265264 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4117 16:33:49.265790
4118 16:33:49.266130
4119 16:33:49.267920 ==
4120 16:33:49.268589 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 16:33:49.274625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 16:33:49.275046 ==
4123 16:33:49.275419
4124 16:33:49.275909
4125 16:33:49.277991 TX Vref Scan disable
4126 16:33:49.278526 == TX Byte 0 ==
4127 16:33:49.281444 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4128 16:33:49.287412 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4129 16:33:49.288049 == TX Byte 1 ==
4130 16:33:49.294133 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4131 16:33:49.297715 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4132 16:33:49.298139 ==
4133 16:33:49.301079 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 16:33:49.304388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 16:33:49.304850 ==
4136 16:33:49.305225
4137 16:33:49.305551
4138 16:33:49.307680 TX Vref Scan disable
4139 16:33:49.310843 == TX Byte 0 ==
4140 16:33:49.314325 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4141 16:33:49.317594 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4142 16:33:49.320558 == TX Byte 1 ==
4143 16:33:49.324019 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4144 16:33:49.327664 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4145 16:33:49.328205
4146 16:33:49.330592 [DATLAT]
4147 16:33:49.331007 Freq=600, CH0 RK0
4148 16:33:49.331370
4149 16:33:49.333962 DATLAT Default: 0x9
4150 16:33:49.334428 0, 0xFFFF, sum = 0
4151 16:33:49.337460 1, 0xFFFF, sum = 0
4152 16:33:49.337949 2, 0xFFFF, sum = 0
4153 16:33:49.340728 3, 0xFFFF, sum = 0
4154 16:33:49.341148 4, 0xFFFF, sum = 0
4155 16:33:49.344027 5, 0xFFFF, sum = 0
4156 16:33:49.344451 6, 0xFFFF, sum = 0
4157 16:33:49.347297 7, 0xFFFF, sum = 0
4158 16:33:49.347723 8, 0x0, sum = 1
4159 16:33:49.350695 9, 0x0, sum = 2
4160 16:33:49.351121 10, 0x0, sum = 3
4161 16:33:49.353459 11, 0x0, sum = 4
4162 16:33:49.353881 best_step = 9
4163 16:33:49.354260
4164 16:33:49.354593 ==
4165 16:33:49.356944 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 16:33:49.363378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 16:33:49.363930 ==
4168 16:33:49.364419 RX Vref Scan: 1
4169 16:33:49.364744
4170 16:33:49.366673 RX Vref 0 -> 0, step: 1
4171 16:33:49.367148
4172 16:33:49.370079 RX Delay -179 -> 252, step: 8
4173 16:33:49.370540
4174 16:33:49.373490 Set Vref, RX VrefLevel [Byte0]: 57
4175 16:33:49.376600 [Byte1]: 48
4176 16:33:49.377078
4177 16:33:49.380148 Final RX Vref Byte 0 = 57 to rank0
4178 16:33:49.383629 Final RX Vref Byte 1 = 48 to rank0
4179 16:33:49.386979 Final RX Vref Byte 0 = 57 to rank1
4180 16:33:49.389950 Final RX Vref Byte 1 = 48 to rank1==
4181 16:33:49.393680 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 16:33:49.396567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 16:33:49.397090 ==
4184 16:33:49.399777 DQS Delay:
4185 16:33:49.400261 DQS0 = 0, DQS1 = 0
4186 16:33:49.400609 DQM Delay:
4187 16:33:49.403409 DQM0 = 43, DQM1 = 31
4188 16:33:49.403828 DQ Delay:
4189 16:33:49.406748 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4190 16:33:49.409571 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4191 16:33:49.413169 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4192 16:33:49.416404 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4193 16:33:49.416823
4194 16:33:49.417153
4195 16:33:49.426369 [DQSOSCAuto] RK0, (LSB)MR18= 0x653d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4196 16:33:49.430446 CH0 RK0: MR19=808, MR18=653D
4197 16:33:49.436565 CH0_RK0: MR19=0x808, MR18=0x653D, DQSOSC=390, MR23=63, INC=172, DEC=114
4198 16:33:49.437131
4199 16:33:49.439631 ----->DramcWriteLeveling(PI) begin...
4200 16:33:49.440054 ==
4201 16:33:49.442431 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 16:33:49.446106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 16:33:49.446559 ==
4204 16:33:49.449575 Write leveling (Byte 0): 33 => 33
4205 16:33:49.452875 Write leveling (Byte 1): 30 => 30
4206 16:33:49.455953 DramcWriteLeveling(PI) end<-----
4207 16:33:49.456387
4208 16:33:49.456724 ==
4209 16:33:49.459503 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 16:33:49.462026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 16:33:49.462626 ==
4212 16:33:49.465620 [Gating] SW mode calibration
4213 16:33:49.471935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4214 16:33:49.478681 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4215 16:33:49.482012 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 16:33:49.485591 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 16:33:49.491879 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 16:33:49.495000 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 16:33:49.498526 0 9 16 | B1->B0 | 2d2d 2d2d | 0 0 | (1 1) (1 1)
4220 16:33:49.505462 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 16:33:49.508253 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 16:33:49.511732 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 16:33:49.518642 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 16:33:49.522156 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 16:33:49.524756 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 16:33:49.531336 0 10 12 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4227 16:33:49.534624 0 10 16 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
4228 16:33:49.537933 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 16:33:49.545119 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 16:33:49.547872 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 16:33:49.551438 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 16:33:49.558144 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 16:33:49.561421 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 16:33:49.564756 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4235 16:33:49.571439 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 16:33:49.574272 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 16:33:49.577457 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 16:33:49.584325 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 16:33:49.587861 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 16:33:49.591408 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 16:33:49.597578 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 16:33:49.601198 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 16:33:49.603934 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 16:33:49.610947 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 16:33:49.614550 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 16:33:49.617191 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 16:33:49.624048 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 16:33:49.627227 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 16:33:49.630737 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 16:33:49.637222 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4251 16:33:49.640729 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 16:33:49.643348 Total UI for P1: 0, mck2ui 16
4253 16:33:49.646704 best dqsien dly found for B0: ( 0, 13, 12)
4254 16:33:49.650113 Total UI for P1: 0, mck2ui 16
4255 16:33:49.653540 best dqsien dly found for B1: ( 0, 13, 12)
4256 16:33:49.657187 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4257 16:33:49.659927 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4258 16:33:49.660324
4259 16:33:49.663423 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4260 16:33:49.666830 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4261 16:33:49.670194 [Gating] SW calibration Done
4262 16:33:49.670545 ==
4263 16:33:49.673512 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 16:33:49.679915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 16:33:49.680263 ==
4266 16:33:49.680544 RX Vref Scan: 0
4267 16:33:49.680808
4268 16:33:49.683277 RX Vref 0 -> 0, step: 1
4269 16:33:49.683695
4270 16:33:49.686663 RX Delay -230 -> 252, step: 16
4271 16:33:49.689880 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4272 16:33:49.693146 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4273 16:33:49.696594 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4274 16:33:49.702912 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4275 16:33:49.706467 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4276 16:33:49.709920 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4277 16:33:49.712602 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4278 16:33:49.719554 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4279 16:33:49.723001 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4280 16:33:49.725752 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4281 16:33:49.729328 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4282 16:33:49.736186 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4283 16:33:49.739424 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4284 16:33:49.742605 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4285 16:33:49.746099 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4286 16:33:49.752283 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4287 16:33:49.752696 ==
4288 16:33:49.755890 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 16:33:49.758632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 16:33:49.758947 ==
4291 16:33:49.759218 DQS Delay:
4292 16:33:49.762420 DQS0 = 0, DQS1 = 0
4293 16:33:49.762692 DQM Delay:
4294 16:33:49.765653 DQM0 = 42, DQM1 = 34
4295 16:33:49.766005 DQ Delay:
4296 16:33:49.768804 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4297 16:33:49.772009 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4298 16:33:49.775522 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4299 16:33:49.778851 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4300 16:33:49.779126
4301 16:33:49.779358
4302 16:33:49.779576 ==
4303 16:33:49.781987 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 16:33:49.785434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 16:33:49.788597 ==
4306 16:33:49.788897
4307 16:33:49.789213
4308 16:33:49.789474 TX Vref Scan disable
4309 16:33:49.791951 == TX Byte 0 ==
4310 16:33:49.795291 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4311 16:33:49.798560 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4312 16:33:49.802043 == TX Byte 1 ==
4313 16:33:49.804700 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4314 16:33:49.811423 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4315 16:33:49.811768 ==
4316 16:33:49.815032 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 16:33:49.818399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 16:33:49.818721 ==
4319 16:33:49.818935
4320 16:33:49.819135
4321 16:33:49.821824 TX Vref Scan disable
4322 16:33:49.824598 == TX Byte 0 ==
4323 16:33:49.828010 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4324 16:33:49.831537 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4325 16:33:49.835027 == TX Byte 1 ==
4326 16:33:49.838493 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4327 16:33:49.841218 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4328 16:33:49.841507
4329 16:33:49.841707 [DATLAT]
4330 16:33:49.844609 Freq=600, CH0 RK1
4331 16:33:49.844860
4332 16:33:49.847968 DATLAT Default: 0x9
4333 16:33:49.848255 0, 0xFFFF, sum = 0
4334 16:33:49.851397 1, 0xFFFF, sum = 0
4335 16:33:49.851684 2, 0xFFFF, sum = 0
4336 16:33:49.854691 3, 0xFFFF, sum = 0
4337 16:33:49.854968 4, 0xFFFF, sum = 0
4338 16:33:49.858176 5, 0xFFFF, sum = 0
4339 16:33:49.858474 6, 0xFFFF, sum = 0
4340 16:33:49.861723 7, 0xFFFF, sum = 0
4341 16:33:49.861985 8, 0x0, sum = 1
4342 16:33:49.864453 9, 0x0, sum = 2
4343 16:33:49.864767 10, 0x0, sum = 3
4344 16:33:49.867918 11, 0x0, sum = 4
4345 16:33:49.868179 best_step = 9
4346 16:33:49.868392
4347 16:33:49.868588 ==
4348 16:33:49.871341 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 16:33:49.874522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 16:33:49.874769 ==
4351 16:33:49.877795 RX Vref Scan: 0
4352 16:33:49.878061
4353 16:33:49.881008 RX Vref 0 -> 0, step: 1
4354 16:33:49.881318
4355 16:33:49.881523 RX Delay -195 -> 252, step: 8
4356 16:33:49.888960 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4357 16:33:49.892368 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4358 16:33:49.895232 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4359 16:33:49.898769 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4360 16:33:49.905498 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4361 16:33:49.908651 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4362 16:33:49.911941 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4363 16:33:49.914825 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4364 16:33:49.921781 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4365 16:33:49.924976 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4366 16:33:49.928506 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4367 16:33:49.931364 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4368 16:33:49.938076 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4369 16:33:49.941541 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4370 16:33:49.944787 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4371 16:33:49.948276 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4372 16:33:49.948366 ==
4373 16:33:49.951288 Dram Type= 6, Freq= 0, CH_0, rank 1
4374 16:33:49.957958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 16:33:49.958071 ==
4376 16:33:49.958184 DQS Delay:
4377 16:33:49.961234 DQS0 = 0, DQS1 = 0
4378 16:33:49.961355 DQM Delay:
4379 16:33:49.961443 DQM0 = 41, DQM1 = 37
4380 16:33:49.964710 DQ Delay:
4381 16:33:49.967692 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4382 16:33:49.971242 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4383 16:33:49.974712 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4384 16:33:49.978192 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4385 16:33:49.978384
4386 16:33:49.978555
4387 16:33:49.984363 [DQSOSCAuto] RK1, (LSB)MR18= 0x6217, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4388 16:33:49.987788 CH0 RK1: MR19=808, MR18=6217
4389 16:33:49.994687 CH0_RK1: MR19=0x808, MR18=0x6217, DQSOSC=391, MR23=63, INC=171, DEC=114
4390 16:33:49.997859 [RxdqsGatingPostProcess] freq 600
4391 16:33:50.001277 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4392 16:33:50.004562 Pre-setting of DQS Precalculation
4393 16:33:50.011307 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4394 16:33:50.011863 ==
4395 16:33:50.014604 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 16:33:50.017994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 16:33:50.018577 ==
4398 16:33:50.024336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 16:33:50.031268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4400 16:33:50.033941 [CA 0] Center 35 (5~66) winsize 62
4401 16:33:50.037493 [CA 1] Center 35 (5~66) winsize 62
4402 16:33:50.041055 [CA 2] Center 34 (4~65) winsize 62
4403 16:33:50.043839 [CA 3] Center 33 (3~64) winsize 62
4404 16:33:50.047361 [CA 4] Center 34 (4~65) winsize 62
4405 16:33:50.050756 [CA 5] Center 33 (3~64) winsize 62
4406 16:33:50.051317
4407 16:33:50.054124 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4408 16:33:50.054578
4409 16:33:50.056941 [CATrainingPosCal] consider 1 rank data
4410 16:33:50.060286 u2DelayCellTimex100 = 270/100 ps
4411 16:33:50.063625 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4412 16:33:50.067616 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4413 16:33:50.070317 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 16:33:50.073536 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4415 16:33:50.076978 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 16:33:50.083960 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 16:33:50.084534
4418 16:33:50.086903 CA PerBit enable=1, Macro0, CA PI delay=33
4419 16:33:50.087359
4420 16:33:50.090356 [CBTSetCACLKResult] CA Dly = 33
4421 16:33:50.090796 CS Dly: 5 (0~36)
4422 16:33:50.091333 ==
4423 16:33:50.093779 Dram Type= 6, Freq= 0, CH_1, rank 1
4424 16:33:50.096671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 16:33:50.100192 ==
4426 16:33:50.103368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4427 16:33:50.109871 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4428 16:33:50.113258 [CA 0] Center 35 (5~66) winsize 62
4429 16:33:50.116568 [CA 1] Center 36 (6~66) winsize 61
4430 16:33:50.120223 [CA 2] Center 34 (4~65) winsize 62
4431 16:33:50.122781 [CA 3] Center 34 (3~65) winsize 63
4432 16:33:50.126261 [CA 4] Center 34 (3~65) winsize 63
4433 16:33:50.129866 [CA 5] Center 34 (3~65) winsize 63
4434 16:33:50.130440
4435 16:33:50.132626 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4436 16:33:50.133048
4437 16:33:50.136164 [CATrainingPosCal] consider 2 rank data
4438 16:33:50.139838 u2DelayCellTimex100 = 270/100 ps
4439 16:33:50.143086 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 16:33:50.146018 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4441 16:33:50.149628 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 16:33:50.156066 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4443 16:33:50.159446 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4444 16:33:50.163026 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 16:33:50.163657
4446 16:33:50.165900 CA PerBit enable=1, Macro0, CA PI delay=33
4447 16:33:50.166462
4448 16:33:50.169564 [CBTSetCACLKResult] CA Dly = 33
4449 16:33:50.170133 CS Dly: 5 (0~37)
4450 16:33:50.170625
4451 16:33:50.172451 ----->DramcWriteLeveling(PI) begin...
4452 16:33:50.175839 ==
4453 16:33:50.178980 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 16:33:50.182249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 16:33:50.182820 ==
4456 16:33:50.185348 Write leveling (Byte 0): 30 => 30
4457 16:33:50.188780 Write leveling (Byte 1): 30 => 30
4458 16:33:50.192527 DramcWriteLeveling(PI) end<-----
4459 16:33:50.192956
4460 16:33:50.193295 ==
4461 16:33:50.195210 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 16:33:50.198943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 16:33:50.199467 ==
4464 16:33:50.202508 [Gating] SW mode calibration
4465 16:33:50.208905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4466 16:33:50.215070 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4467 16:33:50.218443 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 16:33:50.221896 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 16:33:50.228257 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 16:33:50.232029 0 9 12 | B1->B0 | 2f2f 3030 | 1 1 | (1 1) (1 0)
4471 16:33:50.235374 0 9 16 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
4472 16:33:50.241570 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 16:33:50.244996 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 16:33:50.247922 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 16:33:50.255112 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 16:33:50.257859 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 16:33:50.261266 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4478 16:33:50.268475 0 10 12 | B1->B0 | 2f2f 3535 | 1 0 | (0 0) (0 0)
4479 16:33:50.271163 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 16:33:50.274739 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 16:33:50.281694 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 16:33:50.284618 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 16:33:50.287853 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 16:33:50.294551 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 16:33:50.297714 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 16:33:50.300950 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4487 16:33:50.307979 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 16:33:50.310682 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 16:33:50.314275 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 16:33:50.320670 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 16:33:50.324378 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 16:33:50.327115 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 16:33:50.333548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 16:33:50.336910 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 16:33:50.340401 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 16:33:50.346674 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 16:33:50.350672 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 16:33:50.353775 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 16:33:50.360208 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 16:33:50.363583 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 16:33:50.366490 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 16:33:50.373330 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4503 16:33:50.373915 Total UI for P1: 0, mck2ui 16
4504 16:33:50.379645 best dqsien dly found for B0: ( 0, 13, 10)
4505 16:33:50.383083 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 16:33:50.386497 Total UI for P1: 0, mck2ui 16
4507 16:33:50.389621 best dqsien dly found for B1: ( 0, 13, 12)
4508 16:33:50.392894 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4509 16:33:50.396245 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4510 16:33:50.396685
4511 16:33:50.399697 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4512 16:33:50.406319 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4513 16:33:50.406924 [Gating] SW calibration Done
4514 16:33:50.407371 ==
4515 16:33:50.409743 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 16:33:50.416036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 16:33:50.416475 ==
4518 16:33:50.416853 RX Vref Scan: 0
4519 16:33:50.417315
4520 16:33:50.419688 RX Vref 0 -> 0, step: 1
4521 16:33:50.420109
4522 16:33:50.422488 RX Delay -230 -> 252, step: 16
4523 16:33:50.425880 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4524 16:33:50.429577 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4525 16:33:50.435799 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4526 16:33:50.439219 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4527 16:33:50.442204 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4528 16:33:50.445387 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4529 16:33:50.448985 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4530 16:33:50.455446 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4531 16:33:50.458562 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4532 16:33:50.462566 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4533 16:33:50.465627 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4534 16:33:50.472187 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4535 16:33:50.475576 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4536 16:33:50.478277 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4537 16:33:50.481968 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4538 16:33:50.488514 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4539 16:33:50.488669 ==
4540 16:33:50.491961 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 16:33:50.494781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 16:33:50.494919 ==
4543 16:33:50.495025 DQS Delay:
4544 16:33:50.498354 DQS0 = 0, DQS1 = 0
4545 16:33:50.498505 DQM Delay:
4546 16:33:50.501783 DQM0 = 46, DQM1 = 39
4547 16:33:50.501929 DQ Delay:
4548 16:33:50.505278 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4549 16:33:50.508294 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4550 16:33:50.511538 DQ8 =17, DQ9 =33, DQ10 =41, DQ11 =25
4551 16:33:50.515039 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4552 16:33:50.515135
4553 16:33:50.515247
4554 16:33:50.515325 ==
4555 16:33:50.518168 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 16:33:50.521629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 16:33:50.521707 ==
4558 16:33:50.524760
4559 16:33:50.524832
4560 16:33:50.524894 TX Vref Scan disable
4561 16:33:50.528236 == TX Byte 0 ==
4562 16:33:50.531085 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4563 16:33:50.534572 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4564 16:33:50.538271 == TX Byte 1 ==
4565 16:33:50.540938 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4566 16:33:50.544527 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4567 16:33:50.547476 ==
4568 16:33:50.551066 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 16:33:50.554570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 16:33:50.554654 ==
4571 16:33:50.554720
4572 16:33:50.554782
4573 16:33:50.557236 TX Vref Scan disable
4574 16:33:50.557319 == TX Byte 0 ==
4575 16:33:50.564167 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4576 16:33:50.567767 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4577 16:33:50.570505 == TX Byte 1 ==
4578 16:33:50.573974 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4579 16:33:50.577275 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4580 16:33:50.577360
4581 16:33:50.577427 [DATLAT]
4582 16:33:50.580586 Freq=600, CH1 RK0
4583 16:33:50.580675
4584 16:33:50.580746 DATLAT Default: 0x9
4585 16:33:50.583740 0, 0xFFFF, sum = 0
4586 16:33:50.587262 1, 0xFFFF, sum = 0
4587 16:33:50.587361 2, 0xFFFF, sum = 0
4588 16:33:50.590797 3, 0xFFFF, sum = 0
4589 16:33:50.590882 4, 0xFFFF, sum = 0
4590 16:33:50.593436 5, 0xFFFF, sum = 0
4591 16:33:50.593523 6, 0xFFFF, sum = 0
4592 16:33:50.597049 7, 0xFFFF, sum = 0
4593 16:33:50.597141 8, 0x0, sum = 1
4594 16:33:50.600411 9, 0x0, sum = 2
4595 16:33:50.600519 10, 0x0, sum = 3
4596 16:33:50.600611 11, 0x0, sum = 4
4597 16:33:50.603338 best_step = 9
4598 16:33:50.603432
4599 16:33:50.603502 ==
4600 16:33:50.606888 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 16:33:50.610363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 16:33:50.610448 ==
4603 16:33:50.613159 RX Vref Scan: 1
4604 16:33:50.613231
4605 16:33:50.616858 RX Vref 0 -> 0, step: 1
4606 16:33:50.616945
4607 16:33:50.617013 RX Delay -195 -> 252, step: 8
4608 16:33:50.617077
4609 16:33:50.620229 Set Vref, RX VrefLevel [Byte0]: 52
4610 16:33:50.623527 [Byte1]: 56
4611 16:33:50.628133
4612 16:33:50.628227 Final RX Vref Byte 0 = 52 to rank0
4613 16:33:50.631446 Final RX Vref Byte 1 = 56 to rank0
4614 16:33:50.634353 Final RX Vref Byte 0 = 52 to rank1
4615 16:33:50.637914 Final RX Vref Byte 1 = 56 to rank1==
4616 16:33:50.641477 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 16:33:50.647807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 16:33:50.647894 ==
4619 16:33:50.647960 DQS Delay:
4620 16:33:50.650701 DQS0 = 0, DQS1 = 0
4621 16:33:50.650784 DQM Delay:
4622 16:33:50.650850 DQM0 = 47, DQM1 = 36
4623 16:33:50.654143 DQ Delay:
4624 16:33:50.657129 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =40
4625 16:33:50.660557 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4626 16:33:50.664045 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4627 16:33:50.666781 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =48
4628 16:33:50.666866
4629 16:33:50.666932
4630 16:33:50.673923 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e34, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4631 16:33:50.677299 CH1 RK0: MR19=808, MR18=4E34
4632 16:33:50.683516 CH1_RK0: MR19=0x808, MR18=0x4E34, DQSOSC=395, MR23=63, INC=168, DEC=112
4633 16:33:50.683650
4634 16:33:50.687129 ----->DramcWriteLeveling(PI) begin...
4635 16:33:50.687216 ==
4636 16:33:50.689887 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 16:33:50.693694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 16:33:50.696869 ==
4639 16:33:50.696946 Write leveling (Byte 0): 29 => 29
4640 16:33:50.699996 Write leveling (Byte 1): 31 => 31
4641 16:33:50.703452 DramcWriteLeveling(PI) end<-----
4642 16:33:50.703538
4643 16:33:50.703603 ==
4644 16:33:50.706204 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 16:33:50.713238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 16:33:50.713330 ==
4647 16:33:50.716097 [Gating] SW mode calibration
4648 16:33:50.722710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4649 16:33:50.726408 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4650 16:33:50.732887 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 16:33:50.736074 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 16:33:50.739349 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 16:33:50.745709 0 9 12 | B1->B0 | 3131 3333 | 0 0 | (0 1) (0 1)
4654 16:33:50.749222 0 9 16 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
4655 16:33:50.752661 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 16:33:50.759710 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 16:33:50.762349 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 16:33:50.765978 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 16:33:50.772701 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 16:33:50.775695 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 16:33:50.779064 0 10 12 | B1->B0 | 2d2d 2828 | 0 0 | (0 0) (0 0)
4662 16:33:50.785489 0 10 16 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
4663 16:33:50.789051 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 16:33:50.791955 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 16:33:50.799021 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 16:33:50.801732 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 16:33:50.805110 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 16:33:50.811737 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 16:33:50.815025 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4670 16:33:50.818413 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4671 16:33:50.824757 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 16:33:50.828371 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 16:33:50.831152 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 16:33:50.837772 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 16:33:50.841173 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 16:33:50.844308 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 16:33:50.851336 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 16:33:50.854327 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 16:33:50.858044 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 16:33:50.864305 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 16:33:50.867196 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 16:33:50.870741 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 16:33:50.877719 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 16:33:50.880489 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 16:33:50.883739 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4686 16:33:50.887393 Total UI for P1: 0, mck2ui 16
4687 16:33:50.890931 best dqsien dly found for B1: ( 0, 13, 10)
4688 16:33:50.897213 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 16:33:50.897295 Total UI for P1: 0, mck2ui 16
4690 16:33:50.903589 best dqsien dly found for B0: ( 0, 13, 12)
4691 16:33:50.907013 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4692 16:33:50.910551 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4693 16:33:50.910668
4694 16:33:50.913761 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4695 16:33:50.917272 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4696 16:33:50.920139 [Gating] SW calibration Done
4697 16:33:50.920250 ==
4698 16:33:50.923447 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 16:33:50.926917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 16:33:50.927005 ==
4701 16:33:50.930200 RX Vref Scan: 0
4702 16:33:50.930284
4703 16:33:50.933579 RX Vref 0 -> 0, step: 1
4704 16:33:50.933667
4705 16:33:50.933755 RX Delay -230 -> 252, step: 16
4706 16:33:50.939765 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4707 16:33:50.943211 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4708 16:33:50.946636 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4709 16:33:50.950115 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4710 16:33:50.956227 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4711 16:33:50.959486 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4712 16:33:50.962910 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4713 16:33:50.966331 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4714 16:33:50.973327 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4715 16:33:50.976138 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4716 16:33:50.979735 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4717 16:33:50.982490 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4718 16:33:50.989374 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4719 16:33:50.992926 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4720 16:33:50.995794 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4721 16:33:50.999375 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4722 16:33:50.999503 ==
4723 16:33:51.002987 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 16:33:51.009419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 16:33:51.009511 ==
4726 16:33:51.009592 DQS Delay:
4727 16:33:51.012939 DQS0 = 0, DQS1 = 0
4728 16:33:51.013025 DQM Delay:
4729 16:33:51.013100 DQM0 = 45, DQM1 = 38
4730 16:33:51.015697 DQ Delay:
4731 16:33:51.019148 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4732 16:33:51.022091 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4733 16:33:51.025761 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4734 16:33:51.029081 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4735 16:33:51.029166
4736 16:33:51.029233
4737 16:33:51.029299 ==
4738 16:33:51.032259 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 16:33:51.035664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 16:33:51.035752 ==
4741 16:33:51.035833
4742 16:33:51.035917
4743 16:33:51.038733 TX Vref Scan disable
4744 16:33:51.042486 == TX Byte 0 ==
4745 16:33:51.045330 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4746 16:33:51.048988 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4747 16:33:51.051888 == TX Byte 1 ==
4748 16:33:51.055393 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4749 16:33:51.058892 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4750 16:33:51.058981 ==
4751 16:33:51.061651 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 16:33:51.068280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 16:33:51.068365 ==
4754 16:33:51.068434
4755 16:33:51.068495
4756 16:33:51.068554 TX Vref Scan disable
4757 16:33:51.072872 == TX Byte 0 ==
4758 16:33:51.075707 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4759 16:33:51.082082 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4760 16:33:51.082211 == TX Byte 1 ==
4761 16:33:51.085630 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4762 16:33:51.092517 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4763 16:33:51.092603
4764 16:33:51.092670 [DATLAT]
4765 16:33:51.092736 Freq=600, CH1 RK1
4766 16:33:51.092796
4767 16:33:51.095389 DATLAT Default: 0x9
4768 16:33:51.098849 0, 0xFFFF, sum = 0
4769 16:33:51.098930 1, 0xFFFF, sum = 0
4770 16:33:51.102309 2, 0xFFFF, sum = 0
4771 16:33:51.102387 3, 0xFFFF, sum = 0
4772 16:33:51.105725 4, 0xFFFF, sum = 0
4773 16:33:51.105811 5, 0xFFFF, sum = 0
4774 16:33:51.109140 6, 0xFFFF, sum = 0
4775 16:33:51.109220 7, 0xFFFF, sum = 0
4776 16:33:51.111945 8, 0x0, sum = 1
4777 16:33:51.112051 9, 0x0, sum = 2
4778 16:33:51.115481 10, 0x0, sum = 3
4779 16:33:51.115560 11, 0x0, sum = 4
4780 16:33:51.115625 best_step = 9
4781 16:33:51.115685
4782 16:33:51.118265 ==
4783 16:33:51.121855 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 16:33:51.125407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 16:33:51.125487 ==
4786 16:33:51.125552 RX Vref Scan: 0
4787 16:33:51.125617
4788 16:33:51.128275 RX Vref 0 -> 0, step: 1
4789 16:33:51.128350
4790 16:33:51.131730 RX Delay -195 -> 252, step: 8
4791 16:33:51.138709 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4792 16:33:51.141414 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4793 16:33:51.144814 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4794 16:33:51.148308 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4795 16:33:51.154554 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4796 16:33:51.158107 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4797 16:33:51.161552 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4798 16:33:51.164316 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4799 16:33:51.168055 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4800 16:33:51.174379 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4801 16:33:51.177742 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4802 16:33:51.181222 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4803 16:33:51.184395 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4804 16:33:51.190757 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4805 16:33:51.194075 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4806 16:33:51.197417 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4807 16:33:51.197505 ==
4808 16:33:51.200942 Dram Type= 6, Freq= 0, CH_1, rank 1
4809 16:33:51.203869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4810 16:33:51.207433 ==
4811 16:33:51.207543 DQS Delay:
4812 16:33:51.207640 DQS0 = 0, DQS1 = 0
4813 16:33:51.210911 DQM Delay:
4814 16:33:51.211023 DQM0 = 45, DQM1 = 37
4815 16:33:51.213829 DQ Delay:
4816 16:33:51.217356 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4817 16:33:51.217440 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4818 16:33:51.220915 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4819 16:33:51.227295 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4820 16:33:51.227401
4821 16:33:51.227498
4822 16:33:51.233473 [DQSOSCAuto] RK1, (LSB)MR18= 0x291e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4823 16:33:51.237006 CH1 RK1: MR19=808, MR18=291E
4824 16:33:51.243473 CH1_RK1: MR19=0x808, MR18=0x291E, DQSOSC=402, MR23=63, INC=162, DEC=108
4825 16:33:51.246695 [RxdqsGatingPostProcess] freq 600
4826 16:33:51.250082 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4827 16:33:51.253376 Pre-setting of DQS Precalculation
4828 16:33:51.259703 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4829 16:33:51.266704 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4830 16:33:51.272940 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4831 16:33:51.273028
4832 16:33:51.273100
4833 16:33:51.276456 [Calibration Summary] 1200 Mbps
4834 16:33:51.276558 CH 0, Rank 0
4835 16:33:51.279852 SW Impedance : PASS
4836 16:33:51.283401 DUTY Scan : NO K
4837 16:33:51.283486 ZQ Calibration : PASS
4838 16:33:51.286046 Jitter Meter : NO K
4839 16:33:51.289502 CBT Training : PASS
4840 16:33:51.289586 Write leveling : PASS
4841 16:33:51.292775 RX DQS gating : PASS
4842 16:33:51.295925 RX DQ/DQS(RDDQC) : PASS
4843 16:33:51.296043 TX DQ/DQS : PASS
4844 16:33:51.299217 RX DATLAT : PASS
4845 16:33:51.302487 RX DQ/DQS(Engine): PASS
4846 16:33:51.302601 TX OE : NO K
4847 16:33:51.306130 All Pass.
4848 16:33:51.306251
4849 16:33:51.306356 CH 0, Rank 1
4850 16:33:51.309559 SW Impedance : PASS
4851 16:33:51.309672 DUTY Scan : NO K
4852 16:33:51.312360 ZQ Calibration : PASS
4853 16:33:51.315849 Jitter Meter : NO K
4854 16:33:51.315937 CBT Training : PASS
4855 16:33:51.319416 Write leveling : PASS
4856 16:33:51.322269 RX DQS gating : PASS
4857 16:33:51.322354 RX DQ/DQS(RDDQC) : PASS
4858 16:33:51.325793 TX DQ/DQS : PASS
4859 16:33:51.329263 RX DATLAT : PASS
4860 16:33:51.329347 RX DQ/DQS(Engine): PASS
4861 16:33:51.332138 TX OE : NO K
4862 16:33:51.332246 All Pass.
4863 16:33:51.332335
4864 16:33:51.335765 CH 1, Rank 0
4865 16:33:51.335857 SW Impedance : PASS
4866 16:33:51.339161 DUTY Scan : NO K
4867 16:33:51.341865 ZQ Calibration : PASS
4868 16:33:51.341984 Jitter Meter : NO K
4869 16:33:51.345465 CBT Training : PASS
4870 16:33:51.348873 Write leveling : PASS
4871 16:33:51.348985 RX DQS gating : PASS
4872 16:33:51.351718 RX DQ/DQS(RDDQC) : PASS
4873 16:33:51.355796 TX DQ/DQS : PASS
4874 16:33:51.355880 RX DATLAT : PASS
4875 16:33:51.358491 RX DQ/DQS(Engine): PASS
4876 16:33:51.358574 TX OE : NO K
4877 16:33:51.362036 All Pass.
4878 16:33:51.362141
4879 16:33:51.362235 CH 1, Rank 1
4880 16:33:51.364892 SW Impedance : PASS
4881 16:33:51.368436 DUTY Scan : NO K
4882 16:33:51.368539 ZQ Calibration : PASS
4883 16:33:51.372087 Jitter Meter : NO K
4884 16:33:51.372174 CBT Training : PASS
4885 16:33:51.374939 Write leveling : PASS
4886 16:33:51.378582 RX DQS gating : PASS
4887 16:33:51.378692 RX DQ/DQS(RDDQC) : PASS
4888 16:33:51.381932 TX DQ/DQS : PASS
4889 16:33:51.384857 RX DATLAT : PASS
4890 16:33:51.384950 RX DQ/DQS(Engine): PASS
4891 16:33:51.388440 TX OE : NO K
4892 16:33:51.388528 All Pass.
4893 16:33:51.388616
4894 16:33:51.391190 DramC Write-DBI off
4895 16:33:51.394712 PER_BANK_REFRESH: Hybrid Mode
4896 16:33:51.394799 TX_TRACKING: ON
4897 16:33:51.404969 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4898 16:33:51.407759 [FAST_K] Save calibration result to emmc
4899 16:33:51.411082 dramc_set_vcore_voltage set vcore to 662500
4900 16:33:51.414345 Read voltage for 933, 3
4901 16:33:51.414431 Vio18 = 0
4902 16:33:51.418107 Vcore = 662500
4903 16:33:51.418207 Vdram = 0
4904 16:33:51.418274 Vddq = 0
4905 16:33:51.418335 Vmddr = 0
4906 16:33:51.424482 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4907 16:33:51.428118 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4908 16:33:51.431496 MEM_TYPE=3, freq_sel=17
4909 16:33:51.434270 sv_algorithm_assistance_LP4_1600
4910 16:33:51.437844 ============ PULL DRAM RESETB DOWN ============
4911 16:33:51.444160 ========== PULL DRAM RESETB DOWN end =========
4912 16:33:51.447539 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4913 16:33:51.451046 ===================================
4914 16:33:51.453973 LPDDR4 DRAM CONFIGURATION
4915 16:33:51.457438 ===================================
4916 16:33:51.457513 EX_ROW_EN[0] = 0x0
4917 16:33:51.460944 EX_ROW_EN[1] = 0x0
4918 16:33:51.461045 LP4Y_EN = 0x0
4919 16:33:51.464390 WORK_FSP = 0x0
4920 16:33:51.464495 WL = 0x3
4921 16:33:51.467788 RL = 0x3
4922 16:33:51.467866 BL = 0x2
4923 16:33:51.471372 RPST = 0x0
4924 16:33:51.471458 RD_PRE = 0x0
4925 16:33:51.474121 WR_PRE = 0x1
4926 16:33:51.477720 WR_PST = 0x0
4927 16:33:51.477837 DBI_WR = 0x0
4928 16:33:51.480629 DBI_RD = 0x0
4929 16:33:51.480716 OTF = 0x1
4930 16:33:51.484128 ===================================
4931 16:33:51.487508 ===================================
4932 16:33:51.490965 ANA top config
4933 16:33:51.493859 ===================================
4934 16:33:51.493971 DLL_ASYNC_EN = 0
4935 16:33:51.497384 ALL_SLAVE_EN = 1
4936 16:33:51.500240 NEW_RANK_MODE = 1
4937 16:33:51.503696 DLL_IDLE_MODE = 1
4938 16:33:51.503803 LP45_APHY_COMB_EN = 1
4939 16:33:51.507087 TX_ODT_DIS = 1
4940 16:33:51.510492 NEW_8X_MODE = 1
4941 16:33:51.514011 ===================================
4942 16:33:51.517450 ===================================
4943 16:33:51.520087 data_rate = 1866
4944 16:33:51.523444 CKR = 1
4945 16:33:51.526685 DQ_P2S_RATIO = 8
4946 16:33:51.530314 ===================================
4947 16:33:51.530440 CA_P2S_RATIO = 8
4948 16:33:51.533398 DQ_CA_OPEN = 0
4949 16:33:51.537007 DQ_SEMI_OPEN = 0
4950 16:33:51.539838 CA_SEMI_OPEN = 0
4951 16:33:51.543273 CA_FULL_RATE = 0
4952 16:33:51.546804 DQ_CKDIV4_EN = 1
4953 16:33:51.546927 CA_CKDIV4_EN = 1
4954 16:33:51.549766 CA_PREDIV_EN = 0
4955 16:33:51.553234 PH8_DLY = 0
4956 16:33:51.556846 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4957 16:33:51.559711 DQ_AAMCK_DIV = 4
4958 16:33:51.563107 CA_AAMCK_DIV = 4
4959 16:33:51.563191 CA_ADMCK_DIV = 4
4960 16:33:51.566605 DQ_TRACK_CA_EN = 0
4961 16:33:51.569401 CA_PICK = 933
4962 16:33:51.572892 CA_MCKIO = 933
4963 16:33:51.576148 MCKIO_SEMI = 0
4964 16:33:51.579543 PLL_FREQ = 3732
4965 16:33:51.583033 DQ_UI_PI_RATIO = 32
4966 16:33:51.586368 CA_UI_PI_RATIO = 0
4967 16:33:51.586454 ===================================
4968 16:33:51.589287 ===================================
4969 16:33:51.592544 memory_type:LPDDR4
4970 16:33:51.596059 GP_NUM : 10
4971 16:33:51.596171 SRAM_EN : 1
4972 16:33:51.599544 MD32_EN : 0
4973 16:33:51.602517 ===================================
4974 16:33:51.606079 [ANA_INIT] >>>>>>>>>>>>>>
4975 16:33:51.609041 <<<<<< [CONFIGURE PHASE]: ANA_TX
4976 16:33:51.612360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4977 16:33:51.615730 ===================================
4978 16:33:51.619320 data_rate = 1866,PCW = 0X8f00
4979 16:33:51.622197 ===================================
4980 16:33:51.625732 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4981 16:33:51.629328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 16:33:51.635710 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 16:33:51.638997 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4984 16:33:51.642323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4985 16:33:51.645466 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4986 16:33:51.648985 [ANA_INIT] flow start
4987 16:33:51.652404 [ANA_INIT] PLL >>>>>>>>
4988 16:33:51.652519 [ANA_INIT] PLL <<<<<<<<
4989 16:33:51.655358 [ANA_INIT] MIDPI >>>>>>>>
4990 16:33:51.658994 [ANA_INIT] MIDPI <<<<<<<<
4991 16:33:51.661883 [ANA_INIT] DLL >>>>>>>>
4992 16:33:51.661997 [ANA_INIT] flow end
4993 16:33:51.665313 ============ LP4 DIFF to SE enter ============
4994 16:33:51.672317 ============ LP4 DIFF to SE exit ============
4995 16:33:51.672426 [ANA_INIT] <<<<<<<<<<<<<
4996 16:33:51.675171 [Flow] Enable top DCM control >>>>>
4997 16:33:51.678555 [Flow] Enable top DCM control <<<<<
4998 16:33:51.681882 Enable DLL master slave shuffle
4999 16:33:51.688153 ==============================================================
5000 16:33:51.688265 Gating Mode config
5001 16:33:51.695384 ==============================================================
5002 16:33:51.698155 Config description:
5003 16:33:51.708010 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5004 16:33:51.714609 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5005 16:33:51.717950 SELPH_MODE 0: By rank 1: By Phase
5006 16:33:51.724840 ==============================================================
5007 16:33:51.728475 GAT_TRACK_EN = 1
5008 16:33:51.731433 RX_GATING_MODE = 2
5009 16:33:51.731518 RX_GATING_TRACK_MODE = 2
5010 16:33:51.735058 SELPH_MODE = 1
5011 16:33:51.737789 PICG_EARLY_EN = 1
5012 16:33:51.741333 VALID_LAT_VALUE = 1
5013 16:33:51.747800 ==============================================================
5014 16:33:51.751212 Enter into Gating configuration >>>>
5015 16:33:51.754814 Exit from Gating configuration <<<<
5016 16:33:51.757533 Enter into DVFS_PRE_config >>>>>
5017 16:33:51.767533 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5018 16:33:51.771147 Exit from DVFS_PRE_config <<<<<
5019 16:33:51.774685 Enter into PICG configuration >>>>
5020 16:33:51.777833 Exit from PICG configuration <<<<
5021 16:33:51.780746 [RX_INPUT] configuration >>>>>
5022 16:33:51.784307 [RX_INPUT] configuration <<<<<
5023 16:33:51.787642 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5024 16:33:51.794151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5025 16:33:51.800566 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5026 16:33:51.807709 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5027 16:33:51.814036 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 16:33:51.817723 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 16:33:51.823926 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5030 16:33:51.827258 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5031 16:33:51.830752 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5032 16:33:51.833671 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5033 16:33:51.840020 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5034 16:33:51.843605 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5035 16:33:51.847087 ===================================
5036 16:33:51.850038 LPDDR4 DRAM CONFIGURATION
5037 16:33:51.853548 ===================================
5038 16:33:51.853633 EX_ROW_EN[0] = 0x0
5039 16:33:51.856949 EX_ROW_EN[1] = 0x0
5040 16:33:51.857026 LP4Y_EN = 0x0
5041 16:33:51.859844 WORK_FSP = 0x0
5042 16:33:51.859953 WL = 0x3
5043 16:33:51.863286 RL = 0x3
5044 16:33:51.863365 BL = 0x2
5045 16:33:51.866785 RPST = 0x0
5046 16:33:51.870309 RD_PRE = 0x0
5047 16:33:51.870388 WR_PRE = 0x1
5048 16:33:51.873025 WR_PST = 0x0
5049 16:33:51.873105 DBI_WR = 0x0
5050 16:33:51.876483 DBI_RD = 0x0
5051 16:33:51.876563 OTF = 0x1
5052 16:33:51.879832 ===================================
5053 16:33:51.883076 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5054 16:33:51.889824 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5055 16:33:51.893190 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5056 16:33:51.896385 ===================================
5057 16:33:51.899738 LPDDR4 DRAM CONFIGURATION
5058 16:33:51.903081 ===================================
5059 16:33:51.903164 EX_ROW_EN[0] = 0x10
5060 16:33:51.906475 EX_ROW_EN[1] = 0x0
5061 16:33:51.906563 LP4Y_EN = 0x0
5062 16:33:51.909979 WORK_FSP = 0x0
5063 16:33:51.910059 WL = 0x3
5064 16:33:51.912837 RL = 0x3
5065 16:33:51.912915 BL = 0x2
5066 16:33:51.916544 RPST = 0x0
5067 16:33:51.919198 RD_PRE = 0x0
5068 16:33:51.919287 WR_PRE = 0x1
5069 16:33:51.922746 WR_PST = 0x0
5070 16:33:51.922835 DBI_WR = 0x0
5071 16:33:51.926256 DBI_RD = 0x0
5072 16:33:51.926344 OTF = 0x1
5073 16:33:51.929056 ===================================
5074 16:33:51.935850 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5075 16:33:51.940166 nWR fixed to 30
5076 16:33:51.942888 [ModeRegInit_LP4] CH0 RK0
5077 16:33:51.942966 [ModeRegInit_LP4] CH0 RK1
5078 16:33:51.946579 [ModeRegInit_LP4] CH1 RK0
5079 16:33:51.949341 [ModeRegInit_LP4] CH1 RK1
5080 16:33:51.949430 match AC timing 9
5081 16:33:51.956332 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5082 16:33:51.959819 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5083 16:33:51.962540 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5084 16:33:51.969509 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5085 16:33:51.973069 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5086 16:33:51.973180 ==
5087 16:33:51.975858 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 16:33:51.979392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 16:33:51.979473 ==
5090 16:33:51.986339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 16:33:51.992738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5092 16:33:51.995992 [CA 0] Center 37 (7~68) winsize 62
5093 16:33:51.999235 [CA 1] Center 37 (7~68) winsize 62
5094 16:33:52.002277 [CA 2] Center 34 (4~65) winsize 62
5095 16:33:52.006055 [CA 3] Center 35 (5~65) winsize 61
5096 16:33:52.009250 [CA 4] Center 33 (3~64) winsize 62
5097 16:33:52.012342 [CA 5] Center 33 (3~63) winsize 61
5098 16:33:52.012435
5099 16:33:52.015807 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5100 16:33:52.015892
5101 16:33:52.018908 [CATrainingPosCal] consider 1 rank data
5102 16:33:52.022332 u2DelayCellTimex100 = 270/100 ps
5103 16:33:52.026049 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5104 16:33:52.028878 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5105 16:33:52.031874 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5106 16:33:52.038332 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5107 16:33:52.041725 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5108 16:33:52.045216 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5109 16:33:52.045299
5110 16:33:52.048125 CA PerBit enable=1, Macro0, CA PI delay=33
5111 16:33:52.048217
5112 16:33:52.051722 [CBTSetCACLKResult] CA Dly = 33
5113 16:33:52.051814 CS Dly: 7 (0~38)
5114 16:33:52.051883 ==
5115 16:33:52.055276 Dram Type= 6, Freq= 0, CH_0, rank 1
5116 16:33:52.061934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 16:33:52.062050 ==
5118 16:33:52.064749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5119 16:33:52.071370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5120 16:33:52.074926 [CA 0] Center 37 (7~68) winsize 62
5121 16:33:52.078360 [CA 1] Center 37 (7~68) winsize 62
5122 16:33:52.081235 [CA 2] Center 34 (4~65) winsize 62
5123 16:33:52.084785 [CA 3] Center 34 (4~65) winsize 62
5124 16:33:52.088168 [CA 4] Center 33 (3~64) winsize 62
5125 16:33:52.091089 [CA 5] Center 32 (2~63) winsize 62
5126 16:33:52.091169
5127 16:33:52.094451 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5128 16:33:52.094529
5129 16:33:52.098000 [CATrainingPosCal] consider 2 rank data
5130 16:33:52.100907 u2DelayCellTimex100 = 270/100 ps
5131 16:33:52.104424 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5132 16:33:52.111156 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5133 16:33:52.114567 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5134 16:33:52.117951 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5135 16:33:52.121016 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5136 16:33:52.124160 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5137 16:33:52.124262
5138 16:33:52.127325 CA PerBit enable=1, Macro0, CA PI delay=33
5139 16:33:52.127435
5140 16:33:52.130739 [CBTSetCACLKResult] CA Dly = 33
5141 16:33:52.134519 CS Dly: 7 (0~39)
5142 16:33:52.134638
5143 16:33:52.137304 ----->DramcWriteLeveling(PI) begin...
5144 16:33:52.137393 ==
5145 16:33:52.140775 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 16:33:52.144198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 16:33:52.144277 ==
5148 16:33:52.147657 Write leveling (Byte 0): 31 => 31
5149 16:33:52.150282 Write leveling (Byte 1): 27 => 27
5150 16:33:52.153804 DramcWriteLeveling(PI) end<-----
5151 16:33:52.153920
5152 16:33:52.154015 ==
5153 16:33:52.157176 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 16:33:52.160762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 16:33:52.160871 ==
5156 16:33:52.164304 [Gating] SW mode calibration
5157 16:33:52.170673 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5158 16:33:52.176947 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5159 16:33:52.180466 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5160 16:33:52.186982 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5161 16:33:52.189798 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 16:33:52.193355 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 16:33:52.200336 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 16:33:52.203167 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 16:33:52.206583 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 16:33:52.213086 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5167 16:33:52.216532 0 15 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
5168 16:33:52.220042 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 16:33:52.226150 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 16:33:52.229499 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 16:33:52.232918 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 16:33:52.239659 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 16:33:52.242918 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 16:33:52.246220 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5175 16:33:52.252207 1 0 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
5176 16:33:52.255674 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 16:33:52.259091 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 16:33:52.265838 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 16:33:52.269213 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 16:33:52.272090 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 16:33:52.279090 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 16:33:52.282017 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 16:33:52.285435 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5184 16:33:52.291884 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5185 16:33:52.295352 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 16:33:52.298917 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 16:33:52.305142 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 16:33:52.308762 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 16:33:52.311634 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 16:33:52.318511 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 16:33:52.321470 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 16:33:52.325051 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 16:33:52.331342 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 16:33:52.334707 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 16:33:52.337969 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 16:33:52.344320 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 16:33:52.347639 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 16:33:52.351233 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5199 16:33:52.357979 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5200 16:33:52.358095 Total UI for P1: 0, mck2ui 16
5201 16:33:52.364385 best dqsien dly found for B0: ( 1, 2, 28)
5202 16:33:52.367700 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 16:33:52.371095 Total UI for P1: 0, mck2ui 16
5204 16:33:52.374354 best dqsien dly found for B1: ( 1, 2, 30)
5205 16:33:52.377933 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5206 16:33:52.380739 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5207 16:33:52.380825
5208 16:33:52.384257 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5209 16:33:52.387649 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5210 16:33:52.391328 [Gating] SW calibration Done
5211 16:33:52.391424 ==
5212 16:33:52.394667 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 16:33:52.397448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 16:33:52.401032 ==
5215 16:33:52.401122 RX Vref Scan: 0
5216 16:33:52.401191
5217 16:33:52.404393 RX Vref 0 -> 0, step: 1
5218 16:33:52.404503
5219 16:33:52.407063 RX Delay -80 -> 252, step: 8
5220 16:33:52.410639 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5221 16:33:52.414256 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5222 16:33:52.416939 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5223 16:33:52.420425 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5224 16:33:52.423832 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5225 16:33:52.430010 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5226 16:33:52.433601 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5227 16:33:52.437170 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5228 16:33:52.440539 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5229 16:33:52.443274 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5230 16:33:52.450187 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5231 16:33:52.453025 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5232 16:33:52.456803 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5233 16:33:52.460316 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5234 16:33:52.463201 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5235 16:33:52.470153 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5236 16:33:52.470284 ==
5237 16:33:52.472908 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 16:33:52.476252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 16:33:52.476361 ==
5240 16:33:52.476432 DQS Delay:
5241 16:33:52.479453 DQS0 = 0, DQS1 = 0
5242 16:33:52.479557 DQM Delay:
5243 16:33:52.483081 DQM0 = 97, DQM1 = 86
5244 16:33:52.483164 DQ Delay:
5245 16:33:52.486132 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5246 16:33:52.489388 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5247 16:33:52.492636 DQ8 =79, DQ9 =79, DQ10 =83, DQ11 =79
5248 16:33:52.496003 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5249 16:33:52.496122
5250 16:33:52.496225
5251 16:33:52.496371 ==
5252 16:33:52.499515 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 16:33:52.505779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 16:33:52.505889 ==
5255 16:33:52.505994
5256 16:33:52.506115
5257 16:33:52.506233 TX Vref Scan disable
5258 16:33:52.509342 == TX Byte 0 ==
5259 16:33:52.512244 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5260 16:33:52.519298 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5261 16:33:52.519406 == TX Byte 1 ==
5262 16:33:52.522074 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5263 16:33:52.529096 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5264 16:33:52.529210 ==
5265 16:33:52.531934 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 16:33:52.535577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 16:33:52.535660 ==
5268 16:33:52.535728
5269 16:33:52.535795
5270 16:33:52.539023 TX Vref Scan disable
5271 16:33:52.541898 == TX Byte 0 ==
5272 16:33:52.545437 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5273 16:33:52.548208 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5274 16:33:52.551499 == TX Byte 1 ==
5275 16:33:52.555102 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5276 16:33:52.558580 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5277 16:33:52.558688
5278 16:33:52.558797 [DATLAT]
5279 16:33:52.561472 Freq=933, CH0 RK0
5280 16:33:52.561578
5281 16:33:52.565356 DATLAT Default: 0xd
5282 16:33:52.565444 0, 0xFFFF, sum = 0
5283 16:33:52.568109 1, 0xFFFF, sum = 0
5284 16:33:52.568221 2, 0xFFFF, sum = 0
5285 16:33:52.571563 3, 0xFFFF, sum = 0
5286 16:33:52.571674 4, 0xFFFF, sum = 0
5287 16:33:52.574975 5, 0xFFFF, sum = 0
5288 16:33:52.575092 6, 0xFFFF, sum = 0
5289 16:33:52.578621 7, 0xFFFF, sum = 0
5290 16:33:52.578731 8, 0xFFFF, sum = 0
5291 16:33:52.581365 9, 0xFFFF, sum = 0
5292 16:33:52.581464 10, 0x0, sum = 1
5293 16:33:52.584712 11, 0x0, sum = 2
5294 16:33:52.584836 12, 0x0, sum = 3
5295 16:33:52.588205 13, 0x0, sum = 4
5296 16:33:52.588320 best_step = 11
5297 16:33:52.588423
5298 16:33:52.588519 ==
5299 16:33:52.591535 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 16:33:52.594909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 16:33:52.598340 ==
5302 16:33:52.598456 RX Vref Scan: 1
5303 16:33:52.598551
5304 16:33:52.601106 RX Vref 0 -> 0, step: 1
5305 16:33:52.601223
5306 16:33:52.604832 RX Delay -61 -> 252, step: 4
5307 16:33:52.604941
5308 16:33:52.608027 Set Vref, RX VrefLevel [Byte0]: 57
5309 16:33:52.611193 [Byte1]: 48
5310 16:33:52.611312
5311 16:33:52.614432 Final RX Vref Byte 0 = 57 to rank0
5312 16:33:52.618002 Final RX Vref Byte 1 = 48 to rank0
5313 16:33:52.620768 Final RX Vref Byte 0 = 57 to rank1
5314 16:33:52.624454 Final RX Vref Byte 1 = 48 to rank1==
5315 16:33:52.627959 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 16:33:52.630760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 16:33:52.630877 ==
5318 16:33:52.634418 DQS Delay:
5319 16:33:52.634533 DQS0 = 0, DQS1 = 0
5320 16:33:52.634629 DQM Delay:
5321 16:33:52.637186 DQM0 = 97, DQM1 = 85
5322 16:33:52.637264 DQ Delay:
5323 16:33:52.640749 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5324 16:33:52.644280 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5325 16:33:52.647176 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =78
5326 16:33:52.650612 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5327 16:33:52.650719
5328 16:33:52.650815
5329 16:33:52.660751 [DQSOSCAuto] RK0, (LSB)MR18= 0x2910, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5330 16:33:52.663503 CH0 RK0: MR19=505, MR18=2910
5331 16:33:52.670445 CH0_RK0: MR19=0x505, MR18=0x2910, DQSOSC=408, MR23=63, INC=65, DEC=43
5332 16:33:52.670555
5333 16:33:52.673315 ----->DramcWriteLeveling(PI) begin...
5334 16:33:52.673428 ==
5335 16:33:52.676725 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 16:33:52.680238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 16:33:52.680340 ==
5338 16:33:52.683752 Write leveling (Byte 0): 33 => 33
5339 16:33:52.686468 Write leveling (Byte 1): 29 => 29
5340 16:33:52.689982 DramcWriteLeveling(PI) end<-----
5341 16:33:52.690090
5342 16:33:52.690248 ==
5343 16:33:52.693574 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 16:33:52.696965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 16:33:52.697071 ==
5346 16:33:52.700204 [Gating] SW mode calibration
5347 16:33:52.706537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5348 16:33:52.713332 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5349 16:33:52.716731 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
5350 16:33:52.719867 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 16:33:52.726267 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 16:33:52.729700 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 16:33:52.732579 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 16:33:52.739445 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 16:33:52.742978 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 16:33:52.745723 0 14 28 | B1->B0 | 3232 2b2b | 1 0 | (1 0) (0 1)
5357 16:33:52.752768 0 15 0 | B1->B0 | 2d2d 2424 | 1 0 | (1 0) (0 0)
5358 16:33:52.755666 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 16:33:52.762550 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 16:33:52.765875 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 16:33:52.769248 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 16:33:52.772138 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 16:33:52.778591 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 16:33:52.782138 0 15 28 | B1->B0 | 2828 3535 | 0 0 | (0 0) (0 0)
5365 16:33:52.788539 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5366 16:33:52.791956 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5367 16:33:52.795536 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 16:33:52.798995 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 16:33:52.805287 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 16:33:52.808718 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 16:33:52.815460 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 16:33:52.818243 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5373 16:33:52.821841 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5374 16:33:52.828682 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 16:33:52.831934 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 16:33:52.835099 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 16:33:52.838131 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 16:33:52.844915 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 16:33:52.848321 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 16:33:52.851607 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 16:33:52.857789 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 16:33:52.861299 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 16:33:52.864900 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 16:33:52.871064 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 16:33:52.874375 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 16:33:52.877513 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 16:33:52.884558 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 16:33:52.887312 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5389 16:33:52.894526 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5390 16:33:52.894637 Total UI for P1: 0, mck2ui 16
5391 16:33:52.897214 best dqsien dly found for B0: ( 1, 2, 28)
5392 16:33:52.904355 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 16:33:52.907803 Total UI for P1: 0, mck2ui 16
5394 16:33:52.910510 best dqsien dly found for B1: ( 1, 3, 0)
5395 16:33:52.914081 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5396 16:33:52.917577 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5397 16:33:52.917660
5398 16:33:52.920372 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5399 16:33:52.923828 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5400 16:33:52.927469 [Gating] SW calibration Done
5401 16:33:52.927569 ==
5402 16:33:52.930356 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 16:33:52.933795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 16:33:52.933876 ==
5405 16:33:52.936689 RX Vref Scan: 0
5406 16:33:52.936770
5407 16:33:52.940241 RX Vref 0 -> 0, step: 1
5408 16:33:52.940326
5409 16:33:52.940394 RX Delay -80 -> 252, step: 8
5410 16:33:52.947164 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5411 16:33:52.950444 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5412 16:33:52.953786 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5413 16:33:52.956995 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5414 16:33:52.960387 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5415 16:33:52.963431 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5416 16:33:52.970301 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5417 16:33:52.973801 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5418 16:33:52.976583 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5419 16:33:52.980010 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5420 16:33:52.983200 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5421 16:33:52.990219 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5422 16:33:52.993024 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5423 16:33:52.996645 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5424 16:33:52.999594 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5425 16:33:53.002963 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5426 16:33:53.006532 ==
5427 16:33:53.006624 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 16:33:53.012726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 16:33:53.012823 ==
5430 16:33:53.012899 DQS Delay:
5431 16:33:53.016141 DQS0 = 0, DQS1 = 0
5432 16:33:53.016231 DQM Delay:
5433 16:33:53.019716 DQM0 = 96, DQM1 = 87
5434 16:33:53.019815 DQ Delay:
5435 16:33:53.023144 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5436 16:33:53.026135 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5437 16:33:53.029761 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5438 16:33:53.032592 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5439 16:33:53.032681
5440 16:33:53.032748
5441 16:33:53.032812 ==
5442 16:33:53.036134 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 16:33:53.039703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 16:33:53.039789 ==
5445 16:33:53.039856
5446 16:33:53.039949
5447 16:33:53.042451 TX Vref Scan disable
5448 16:33:53.045899 == TX Byte 0 ==
5449 16:33:53.049157 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5450 16:33:53.052602 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5451 16:33:53.055549 == TX Byte 1 ==
5452 16:33:53.059137 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5453 16:33:53.062719 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5454 16:33:53.062805 ==
5455 16:33:53.065607 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 16:33:53.072262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 16:33:53.072349 ==
5458 16:33:53.072446
5459 16:33:53.072512
5460 16:33:53.072584 TX Vref Scan disable
5461 16:33:53.076732 == TX Byte 0 ==
5462 16:33:53.079900 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5463 16:33:53.086380 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5464 16:33:53.086469 == TX Byte 1 ==
5465 16:33:53.089627 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5466 16:33:53.096335 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5467 16:33:53.096424
5468 16:33:53.096492 [DATLAT]
5469 16:33:53.096555 Freq=933, CH0 RK1
5470 16:33:53.096616
5471 16:33:53.099732 DATLAT Default: 0xb
5472 16:33:53.102483 0, 0xFFFF, sum = 0
5473 16:33:53.102582 1, 0xFFFF, sum = 0
5474 16:33:53.105937 2, 0xFFFF, sum = 0
5475 16:33:53.106062 3, 0xFFFF, sum = 0
5476 16:33:53.109378 4, 0xFFFF, sum = 0
5477 16:33:53.109495 5, 0xFFFF, sum = 0
5478 16:33:53.112269 6, 0xFFFF, sum = 0
5479 16:33:53.112355 7, 0xFFFF, sum = 0
5480 16:33:53.115743 8, 0xFFFF, sum = 0
5481 16:33:53.115829 9, 0xFFFF, sum = 0
5482 16:33:53.119213 10, 0x0, sum = 1
5483 16:33:53.119323 11, 0x0, sum = 2
5484 16:33:53.122611 12, 0x0, sum = 3
5485 16:33:53.122726 13, 0x0, sum = 4
5486 16:33:53.125524 best_step = 11
5487 16:33:53.125608
5488 16:33:53.125675 ==
5489 16:33:53.129014 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 16:33:53.132514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 16:33:53.132618 ==
5492 16:33:53.132687 RX Vref Scan: 0
5493 16:33:53.135380
5494 16:33:53.135464 RX Vref 0 -> 0, step: 1
5495 16:33:53.135531
5496 16:33:53.138854 RX Delay -61 -> 252, step: 4
5497 16:33:53.145265 iDelay=203, Bit 0, Center 92 (3 ~ 182) 180
5498 16:33:53.148767 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5499 16:33:53.152251 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5500 16:33:53.155133 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5501 16:33:53.158645 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5502 16:33:53.162187 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5503 16:33:53.168488 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5504 16:33:53.172036 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5505 16:33:53.174941 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5506 16:33:53.178304 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5507 16:33:53.181915 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5508 16:33:53.188220 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5509 16:33:53.191532 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5510 16:33:53.194744 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5511 16:33:53.197955 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5512 16:33:53.204571 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5513 16:33:53.204695 ==
5514 16:33:53.207967 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 16:33:53.211196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 16:33:53.211316 ==
5517 16:33:53.211413 DQS Delay:
5518 16:33:53.214458 DQS0 = 0, DQS1 = 0
5519 16:33:53.214542 DQM Delay:
5520 16:33:53.217759 DQM0 = 95, DQM1 = 85
5521 16:33:53.217864 DQ Delay:
5522 16:33:53.221027 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94
5523 16:33:53.224386 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5524 16:33:53.227817 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5525 16:33:53.231270 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5526 16:33:53.231383
5527 16:33:53.231454
5528 16:33:53.237637 [DQSOSCAuto] RK1, (LSB)MR18= 0x28f9, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5529 16:33:53.240961 CH0 RK1: MR19=504, MR18=28F9
5530 16:33:53.247477 CH0_RK1: MR19=0x504, MR18=0x28F9, DQSOSC=409, MR23=63, INC=64, DEC=43
5531 16:33:53.250986 [RxdqsGatingPostProcess] freq 933
5532 16:33:53.257875 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5533 16:33:53.260600 best DQS0 dly(2T, 0.5T) = (0, 10)
5534 16:33:53.264090 best DQS1 dly(2T, 0.5T) = (0, 10)
5535 16:33:53.267388 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5536 16:33:53.270801 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5537 16:33:53.270886 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 16:33:53.274098 best DQS1 dly(2T, 0.5T) = (0, 11)
5539 16:33:53.276963 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 16:33:53.280414 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5541 16:33:53.283924 Pre-setting of DQS Precalculation
5542 16:33:53.290267 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5543 16:33:53.290356 ==
5544 16:33:53.293823 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 16:33:53.297236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 16:33:53.297323 ==
5547 16:33:53.303521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 16:33:53.310561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5549 16:33:53.313179 [CA 0] Center 37 (7~67) winsize 61
5550 16:33:53.316967 [CA 1] Center 37 (7~68) winsize 62
5551 16:33:53.320057 [CA 2] Center 34 (4~65) winsize 62
5552 16:33:53.323248 [CA 3] Center 33 (3~64) winsize 62
5553 16:33:53.326384 [CA 4] Center 34 (4~65) winsize 62
5554 16:33:53.330172 [CA 5] Center 33 (3~64) winsize 62
5555 16:33:53.330263
5556 16:33:53.333208 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5557 16:33:53.333287
5558 16:33:53.336720 [CATrainingPosCal] consider 1 rank data
5559 16:33:53.339795 u2DelayCellTimex100 = 270/100 ps
5560 16:33:53.343028 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5561 16:33:53.346657 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5562 16:33:53.349880 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5563 16:33:53.352715 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 16:33:53.356193 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5565 16:33:53.359774 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5566 16:33:53.359886
5567 16:33:53.366506 CA PerBit enable=1, Macro0, CA PI delay=33
5568 16:33:53.366627
5569 16:33:53.369236 [CBTSetCACLKResult] CA Dly = 33
5570 16:33:53.369340 CS Dly: 6 (0~37)
5571 16:33:53.369410 ==
5572 16:33:53.372849 Dram Type= 6, Freq= 0, CH_1, rank 1
5573 16:33:53.376238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 16:33:53.376346 ==
5575 16:33:53.382657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5576 16:33:53.389129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5577 16:33:53.392754 [CA 0] Center 37 (7~67) winsize 61
5578 16:33:53.396107 [CA 1] Center 37 (7~68) winsize 62
5579 16:33:53.398961 [CA 2] Center 34 (4~65) winsize 62
5580 16:33:53.402285 [CA 3] Center 34 (4~65) winsize 62
5581 16:33:53.405669 [CA 4] Center 34 (4~65) winsize 62
5582 16:33:53.409184 [CA 5] Center 33 (3~64) winsize 62
5583 16:33:53.409294
5584 16:33:53.412116 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5585 16:33:53.412200
5586 16:33:53.415663 [CATrainingPosCal] consider 2 rank data
5587 16:33:53.419046 u2DelayCellTimex100 = 270/100 ps
5588 16:33:53.422609 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5589 16:33:53.425443 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5590 16:33:53.429214 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5591 16:33:53.432582 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5592 16:33:53.438666 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5593 16:33:53.442169 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5594 16:33:53.442266
5595 16:33:53.445463 CA PerBit enable=1, Macro0, CA PI delay=33
5596 16:33:53.445569
5597 16:33:53.448724 [CBTSetCACLKResult] CA Dly = 33
5598 16:33:53.448811 CS Dly: 7 (0~39)
5599 16:33:53.448877
5600 16:33:53.452091 ----->DramcWriteLeveling(PI) begin...
5601 16:33:53.452207 ==
5602 16:33:53.455342 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 16:33:53.462199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 16:33:53.462291 ==
5605 16:33:53.465136 Write leveling (Byte 0): 24 => 24
5606 16:33:53.468686 Write leveling (Byte 1): 25 => 25
5607 16:33:53.468804 DramcWriteLeveling(PI) end<-----
5608 16:33:53.471666
5609 16:33:53.471781 ==
5610 16:33:53.475030 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 16:33:53.478481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 16:33:53.478588 ==
5613 16:33:53.481914 [Gating] SW mode calibration
5614 16:33:53.488119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5615 16:33:53.491556 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5616 16:33:53.498361 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 16:33:53.501220 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 16:33:53.504648 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 16:33:53.511713 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 16:33:53.514455 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 16:33:53.517899 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 16:33:53.524336 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 1)
5623 16:33:53.527807 0 14 28 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)
5624 16:33:53.531299 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 16:33:53.537939 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 16:33:53.541231 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 16:33:53.544520 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 16:33:53.550811 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 16:33:53.554405 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 16:33:53.557259 0 15 24 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
5631 16:33:53.564354 0 15 28 | B1->B0 | 2e2e 3838 | 0 0 | (0 0) (0 0)
5632 16:33:53.567801 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 16:33:53.570501 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 16:33:53.577119 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 16:33:53.580378 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 16:33:53.583577 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 16:33:53.590339 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 16:33:53.593705 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5639 16:33:53.597443 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5640 16:33:53.603963 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 16:33:53.606768 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 16:33:53.610000 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 16:33:53.616517 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 16:33:53.619863 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 16:33:53.623432 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 16:33:53.629886 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 16:33:53.633231 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 16:33:53.639949 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 16:33:53.642688 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 16:33:53.646134 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 16:33:53.649542 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 16:33:53.656531 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 16:33:53.659213 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 16:33:53.666057 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5655 16:33:53.669619 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5656 16:33:53.672348 Total UI for P1: 0, mck2ui 16
5657 16:33:53.675811 best dqsien dly found for B0: ( 1, 2, 24)
5658 16:33:53.679427 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 16:33:53.682818 Total UI for P1: 0, mck2ui 16
5660 16:33:53.685646 best dqsien dly found for B1: ( 1, 2, 26)
5661 16:33:53.689175 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5662 16:33:53.692571 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5663 16:33:53.692676
5664 16:33:53.696012 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5665 16:33:53.702083 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5666 16:33:53.702181 [Gating] SW calibration Done
5667 16:33:53.705581 ==
5668 16:33:53.705664 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 16:33:53.712014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 16:33:53.712099 ==
5671 16:33:53.712167 RX Vref Scan: 0
5672 16:33:53.712229
5673 16:33:53.715751 RX Vref 0 -> 0, step: 1
5674 16:33:53.715855
5675 16:33:53.718813 RX Delay -80 -> 252, step: 8
5676 16:33:53.722414 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5677 16:33:53.725117 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5678 16:33:53.728636 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5679 16:33:53.734931 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5680 16:33:53.738544 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5681 16:33:53.741358 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5682 16:33:53.744773 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5683 16:33:53.748304 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5684 16:33:53.754686 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5685 16:33:53.758268 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5686 16:33:53.761547 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5687 16:33:53.764772 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5688 16:33:53.767821 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5689 16:33:53.774368 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5690 16:33:53.777924 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5691 16:33:53.780843 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5692 16:33:53.780946 ==
5693 16:33:53.784335 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 16:33:53.787806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 16:33:53.787888 ==
5696 16:33:53.791228 DQS Delay:
5697 16:33:53.791329 DQS0 = 0, DQS1 = 0
5698 16:33:53.791449 DQM Delay:
5699 16:33:53.793971 DQM0 = 102, DQM1 = 91
5700 16:33:53.794067 DQ Delay:
5701 16:33:53.797391 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5702 16:33:53.800889 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5703 16:33:53.803795 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5704 16:33:53.807270 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5705 16:33:53.807345
5706 16:33:53.810827
5707 16:33:53.810925 ==
5708 16:33:53.813647 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 16:33:53.817117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 16:33:53.817223 ==
5711 16:33:53.817316
5712 16:33:53.817410
5713 16:33:53.820552 TX Vref Scan disable
5714 16:33:53.820655 == TX Byte 0 ==
5715 16:33:53.826910 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5716 16:33:53.830194 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5717 16:33:53.830314 == TX Byte 1 ==
5718 16:33:53.837271 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5719 16:33:53.839955 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5720 16:33:53.840059 ==
5721 16:33:53.843342 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 16:33:53.846916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 16:33:53.847083 ==
5724 16:33:53.847239
5725 16:33:53.847351
5726 16:33:53.849896 TX Vref Scan disable
5727 16:33:53.853455 == TX Byte 0 ==
5728 16:33:53.856707 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5729 16:33:53.860203 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5730 16:33:53.863092 == TX Byte 1 ==
5731 16:33:53.866680 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5732 16:33:53.870047 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5733 16:33:53.872675
5734 16:33:53.872777 [DATLAT]
5735 16:33:53.872872 Freq=933, CH1 RK0
5736 16:33:53.872969
5737 16:33:53.875939 DATLAT Default: 0xd
5738 16:33:53.876016 0, 0xFFFF, sum = 0
5739 16:33:53.879788 1, 0xFFFF, sum = 0
5740 16:33:53.879891 2, 0xFFFF, sum = 0
5741 16:33:53.882858 3, 0xFFFF, sum = 0
5742 16:33:53.882967 4, 0xFFFF, sum = 0
5743 16:33:53.885963 5, 0xFFFF, sum = 0
5744 16:33:53.889855 6, 0xFFFF, sum = 0
5745 16:33:53.889968 7, 0xFFFF, sum = 0
5746 16:33:53.892774 8, 0xFFFF, sum = 0
5747 16:33:53.892878 9, 0xFFFF, sum = 0
5748 16:33:53.896300 10, 0x0, sum = 1
5749 16:33:53.896439 11, 0x0, sum = 2
5750 16:33:53.899735 12, 0x0, sum = 3
5751 16:33:53.899841 13, 0x0, sum = 4
5752 16:33:53.899934 best_step = 11
5753 16:33:53.900027
5754 16:33:53.902491 ==
5755 16:33:53.905952 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 16:33:53.909479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 16:33:53.909559 ==
5758 16:33:53.909624 RX Vref Scan: 1
5759 16:33:53.909684
5760 16:33:53.912917 RX Vref 0 -> 0, step: 1
5761 16:33:53.913013
5762 16:33:53.915720 RX Delay -61 -> 252, step: 4
5763 16:33:53.915813
5764 16:33:53.919266 Set Vref, RX VrefLevel [Byte0]: 52
5765 16:33:53.922539 [Byte1]: 56
5766 16:33:53.922615
5767 16:33:53.925387 Final RX Vref Byte 0 = 52 to rank0
5768 16:33:53.928983 Final RX Vref Byte 1 = 56 to rank0
5769 16:33:53.932312 Final RX Vref Byte 0 = 52 to rank1
5770 16:33:53.935814 Final RX Vref Byte 1 = 56 to rank1==
5771 16:33:53.939108 Dram Type= 6, Freq= 0, CH_1, rank 0
5772 16:33:53.945505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 16:33:53.945612 ==
5774 16:33:53.945697 DQS Delay:
5775 16:33:53.945760 DQS0 = 0, DQS1 = 0
5776 16:33:53.948940 DQM Delay:
5777 16:33:53.949040 DQM0 = 101, DQM1 = 94
5778 16:33:53.952097 DQ Delay:
5779 16:33:53.955171 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5780 16:33:53.958584 DQ4 =100, DQ5 =110, DQ6 =112, DQ7 =96
5781 16:33:53.962032 DQ8 =82, DQ9 =86, DQ10 =92, DQ11 =84
5782 16:33:53.965444 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =104
5783 16:33:53.965524
5784 16:33:53.965591
5785 16:33:53.971835 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5786 16:33:53.975393 CH1 RK0: MR19=505, MR18=1D0D
5787 16:33:53.981767 CH1_RK0: MR19=0x505, MR18=0x1D0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5788 16:33:53.981874
5789 16:33:53.984980 ----->DramcWriteLeveling(PI) begin...
5790 16:33:53.985084 ==
5791 16:33:53.988379 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 16:33:53.991744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 16:33:53.994954 ==
5794 16:33:53.995036 Write leveling (Byte 0): 26 => 26
5795 16:33:53.997955 Write leveling (Byte 1): 27 => 27
5796 16:33:54.001175 DramcWriteLeveling(PI) end<-----
5797 16:33:54.001289
5798 16:33:54.001439 ==
5799 16:33:54.004589 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 16:33:54.011310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 16:33:54.011398 ==
5802 16:33:54.014255 [Gating] SW mode calibration
5803 16:33:54.021313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5804 16:33:54.024286 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5805 16:33:54.031056 0 14 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5806 16:33:54.034420 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 16:33:54.037883 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 16:33:54.044082 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 16:33:54.047638 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 16:33:54.050969 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5811 16:33:54.057228 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5812 16:33:54.060568 0 14 28 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (0 0)
5813 16:33:54.063808 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 16:33:54.070345 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 16:33:54.074291 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 16:33:54.077163 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 16:33:54.083587 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 16:33:54.087107 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 16:33:54.090592 0 15 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5820 16:33:54.096730 0 15 28 | B1->B0 | 3838 2d2d | 1 0 | (0 0) (0 0)
5821 16:33:54.100319 1 0 0 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5822 16:33:54.103500 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 16:33:54.109822 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 16:33:54.113463 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 16:33:54.116777 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 16:33:54.122869 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 16:33:54.126305 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5828 16:33:54.129696 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5829 16:33:54.136092 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 16:33:54.139514 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 16:33:54.143026 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 16:33:54.149209 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 16:33:54.152788 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 16:33:54.156194 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 16:33:54.162618 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 16:33:54.166045 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 16:33:54.168991 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 16:33:54.175957 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 16:33:54.179284 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 16:33:54.182428 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 16:33:54.188572 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 16:33:54.192234 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 16:33:54.195643 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5844 16:33:54.201867 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 16:33:54.205253 Total UI for P1: 0, mck2ui 16
5846 16:33:54.208934 best dqsien dly found for B0: ( 1, 2, 24)
5847 16:33:54.209043 Total UI for P1: 0, mck2ui 16
5848 16:33:54.215304 best dqsien dly found for B1: ( 1, 2, 24)
5849 16:33:54.218542 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5850 16:33:54.221823 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5851 16:33:54.221927
5852 16:33:54.225017 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5853 16:33:54.228160 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5854 16:33:54.231268 [Gating] SW calibration Done
5855 16:33:54.231379 ==
5856 16:33:54.234674 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 16:33:54.238077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 16:33:54.238185 ==
5859 16:33:54.241495 RX Vref Scan: 0
5860 16:33:54.241594
5861 16:33:54.245024 RX Vref 0 -> 0, step: 1
5862 16:33:54.245108
5863 16:33:54.245176 RX Delay -80 -> 252, step: 8
5864 16:33:54.251455 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5865 16:33:54.254988 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5866 16:33:54.257702 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5867 16:33:54.261266 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5868 16:33:54.264779 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5869 16:33:54.267637 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5870 16:33:54.274503 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5871 16:33:54.277889 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5872 16:33:54.281386 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5873 16:33:54.284216 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5874 16:33:54.287688 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5875 16:33:54.294138 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5876 16:33:54.297470 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5877 16:33:54.300950 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5878 16:33:54.303815 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5879 16:33:54.307342 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5880 16:33:54.307456 ==
5881 16:33:54.310890 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 16:33:54.317258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 16:33:54.317355 ==
5884 16:33:54.317457 DQS Delay:
5885 16:33:54.320765 DQS0 = 0, DQS1 = 0
5886 16:33:54.320869 DQM Delay:
5887 16:33:54.320965 DQM0 = 99, DQM1 = 91
5888 16:33:54.323652 DQ Delay:
5889 16:33:54.327115 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5890 16:33:54.330407 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5891 16:33:54.333839 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =83
5892 16:33:54.336987 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5893 16:33:54.337090
5894 16:33:54.337184
5895 16:33:54.337274 ==
5896 16:33:54.340214 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 16:33:54.343367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 16:33:54.343514 ==
5899 16:33:54.343613
5900 16:33:54.343715
5901 16:33:54.346849 TX Vref Scan disable
5902 16:33:54.350218 == TX Byte 0 ==
5903 16:33:54.353730 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5904 16:33:54.356542 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5905 16:33:54.360142 == TX Byte 1 ==
5906 16:33:54.363611 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5907 16:33:54.367015 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5908 16:33:54.367152 ==
5909 16:33:54.369700 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 16:33:54.376739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 16:33:54.376898 ==
5912 16:33:54.376984
5913 16:33:54.377061
5914 16:33:54.377133 TX Vref Scan disable
5915 16:33:54.380174 == TX Byte 0 ==
5916 16:33:54.383890 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5917 16:33:54.390149 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5918 16:33:54.390313 == TX Byte 1 ==
5919 16:33:54.393769 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5920 16:33:54.400694 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5921 16:33:54.400793
5922 16:33:54.400858 [DATLAT]
5923 16:33:54.400919 Freq=933, CH1 RK1
5924 16:33:54.400978
5925 16:33:54.403969 DATLAT Default: 0xb
5926 16:33:54.404051 0, 0xFFFF, sum = 0
5927 16:33:54.407241 1, 0xFFFF, sum = 0
5928 16:33:54.407324 2, 0xFFFF, sum = 0
5929 16:33:54.410467 3, 0xFFFF, sum = 0
5930 16:33:54.413609 4, 0xFFFF, sum = 0
5931 16:33:54.413693 5, 0xFFFF, sum = 0
5932 16:33:54.417080 6, 0xFFFF, sum = 0
5933 16:33:54.417181 7, 0xFFFF, sum = 0
5934 16:33:54.420388 8, 0xFFFF, sum = 0
5935 16:33:54.420470 9, 0xFFFF, sum = 0
5936 16:33:54.423927 10, 0x0, sum = 1
5937 16:33:54.424042 11, 0x0, sum = 2
5938 16:33:54.426689 12, 0x0, sum = 3
5939 16:33:54.426772 13, 0x0, sum = 4
5940 16:33:54.426839 best_step = 11
5941 16:33:54.430230
5942 16:33:54.430310 ==
5943 16:33:54.433310 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 16:33:54.436930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 16:33:54.437013 ==
5946 16:33:54.437132 RX Vref Scan: 0
5947 16:33:54.437194
5948 16:33:54.440260 RX Vref 0 -> 0, step: 1
5949 16:33:54.440341
5950 16:33:54.443169 RX Delay -61 -> 252, step: 4
5951 16:33:54.449912 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5952 16:33:54.453230 iDelay=207, Bit 1, Center 96 (7 ~ 186) 180
5953 16:33:54.456325 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
5954 16:33:54.459616 iDelay=207, Bit 3, Center 98 (11 ~ 186) 176
5955 16:33:54.463211 iDelay=207, Bit 4, Center 100 (7 ~ 194) 188
5956 16:33:54.466570 iDelay=207, Bit 5, Center 110 (19 ~ 202) 184
5957 16:33:54.472707 iDelay=207, Bit 6, Center 112 (19 ~ 206) 188
5958 16:33:54.476096 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5959 16:33:54.479661 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5960 16:33:54.483145 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5961 16:33:54.486059 iDelay=207, Bit 10, Center 96 (7 ~ 186) 180
5962 16:33:54.492959 iDelay=207, Bit 11, Center 82 (-9 ~ 174) 184
5963 16:33:54.495765 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5964 16:33:54.499415 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
5965 16:33:54.502313 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
5966 16:33:54.509251 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5967 16:33:54.509343 ==
5968 16:33:54.512706 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 16:33:54.515466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 16:33:54.515550 ==
5971 16:33:54.515617 DQS Delay:
5972 16:33:54.518866 DQS0 = 0, DQS1 = 0
5973 16:33:54.518962 DQM Delay:
5974 16:33:54.522255 DQM0 = 100, DQM1 = 94
5975 16:33:54.522336 DQ Delay:
5976 16:33:54.525381 DQ0 =104, DQ1 =96, DQ2 =88, DQ3 =98
5977 16:33:54.528608 DQ4 =100, DQ5 =110, DQ6 =112, DQ7 =98
5978 16:33:54.532241 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =82
5979 16:33:54.535190 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5980 16:33:54.535261
5981 16:33:54.535324
5982 16:33:54.545358 [DQSOSCAuto] RK1, (LSB)MR18= 0x902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5983 16:33:54.545448 CH1 RK1: MR19=505, MR18=902
5984 16:33:54.552333 CH1_RK1: MR19=0x505, MR18=0x902, DQSOSC=419, MR23=63, INC=61, DEC=41
5985 16:33:54.555197 [RxdqsGatingPostProcess] freq 933
5986 16:33:54.561925 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5987 16:33:54.565159 best DQS0 dly(2T, 0.5T) = (0, 10)
5988 16:33:54.568314 best DQS1 dly(2T, 0.5T) = (0, 10)
5989 16:33:54.571786 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5990 16:33:54.575114 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5991 16:33:54.578522 best DQS0 dly(2T, 0.5T) = (0, 10)
5992 16:33:54.578596 best DQS1 dly(2T, 0.5T) = (0, 10)
5993 16:33:54.581974 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5994 16:33:54.584740 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5995 16:33:54.588220 Pre-setting of DQS Precalculation
5996 16:33:54.595041 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5997 16:33:54.601245 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5998 16:33:54.608160 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5999 16:33:54.608243
6000 16:33:54.608325
6001 16:33:54.611682 [Calibration Summary] 1866 Mbps
6002 16:33:54.614977 CH 0, Rank 0
6003 16:33:54.615047 SW Impedance : PASS
6004 16:33:54.617780 DUTY Scan : NO K
6005 16:33:54.621182 ZQ Calibration : PASS
6006 16:33:54.621278 Jitter Meter : NO K
6007 16:33:54.624724 CBT Training : PASS
6008 16:33:54.624806 Write leveling : PASS
6009 16:33:54.628128 RX DQS gating : PASS
6010 16:33:54.631585 RX DQ/DQS(RDDQC) : PASS
6011 16:33:54.631661 TX DQ/DQS : PASS
6012 16:33:54.634273 RX DATLAT : PASS
6013 16:33:54.637616 RX DQ/DQS(Engine): PASS
6014 16:33:54.637689 TX OE : NO K
6015 16:33:54.641473 All Pass.
6016 16:33:54.641554
6017 16:33:54.641617 CH 0, Rank 1
6018 16:33:54.644689 SW Impedance : PASS
6019 16:33:54.644856 DUTY Scan : NO K
6020 16:33:54.647772 ZQ Calibration : PASS
6021 16:33:54.650904 Jitter Meter : NO K
6022 16:33:54.651006 CBT Training : PASS
6023 16:33:54.654128 Write leveling : PASS
6024 16:33:54.657504 RX DQS gating : PASS
6025 16:33:54.657586 RX DQ/DQS(RDDQC) : PASS
6026 16:33:54.660844 TX DQ/DQS : PASS
6027 16:33:54.664348 RX DATLAT : PASS
6028 16:33:54.664483 RX DQ/DQS(Engine): PASS
6029 16:33:54.667823 TX OE : NO K
6030 16:33:54.667909 All Pass.
6031 16:33:54.668053
6032 16:33:54.671203 CH 1, Rank 0
6033 16:33:54.671288 SW Impedance : PASS
6034 16:33:54.673870 DUTY Scan : NO K
6035 16:33:54.677740 ZQ Calibration : PASS
6036 16:33:54.677833 Jitter Meter : NO K
6037 16:33:54.680693 CBT Training : PASS
6038 16:33:54.684356 Write leveling : PASS
6039 16:33:54.684434 RX DQS gating : PASS
6040 16:33:54.687746 RX DQ/DQS(RDDQC) : PASS
6041 16:33:54.687875 TX DQ/DQS : PASS
6042 16:33:54.690858 RX DATLAT : PASS
6043 16:33:54.693650 RX DQ/DQS(Engine): PASS
6044 16:33:54.693740 TX OE : NO K
6045 16:33:54.697218 All Pass.
6046 16:33:54.697294
6047 16:33:54.697357 CH 1, Rank 1
6048 16:33:54.700797 SW Impedance : PASS
6049 16:33:54.700868 DUTY Scan : NO K
6050 16:33:54.703615 ZQ Calibration : PASS
6051 16:33:54.707124 Jitter Meter : NO K
6052 16:33:54.707202 CBT Training : PASS
6053 16:33:54.710495 Write leveling : PASS
6054 16:33:54.713955 RX DQS gating : PASS
6055 16:33:54.714067 RX DQ/DQS(RDDQC) : PASS
6056 16:33:54.717348 TX DQ/DQS : PASS
6057 16:33:54.720162 RX DATLAT : PASS
6058 16:33:54.720238 RX DQ/DQS(Engine): PASS
6059 16:33:54.723556 TX OE : NO K
6060 16:33:54.723627 All Pass.
6061 16:33:54.723689
6062 16:33:54.726987 DramC Write-DBI off
6063 16:33:54.730431 PER_BANK_REFRESH: Hybrid Mode
6064 16:33:54.730525 TX_TRACKING: ON
6065 16:33:54.740241 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6066 16:33:54.743589 [FAST_K] Save calibration result to emmc
6067 16:33:54.746415 dramc_set_vcore_voltage set vcore to 650000
6068 16:33:54.749737 Read voltage for 400, 6
6069 16:33:54.749815 Vio18 = 0
6070 16:33:54.753022 Vcore = 650000
6071 16:33:54.753106 Vdram = 0
6072 16:33:54.753173 Vddq = 0
6073 16:33:54.753248 Vmddr = 0
6074 16:33:54.759770 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6075 16:33:54.766460 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6076 16:33:54.766554 MEM_TYPE=3, freq_sel=20
6077 16:33:54.769568 sv_algorithm_assistance_LP4_800
6078 16:33:54.772843 ============ PULL DRAM RESETB DOWN ============
6079 16:33:54.779922 ========== PULL DRAM RESETB DOWN end =========
6080 16:33:54.782576 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6081 16:33:54.786073 ===================================
6082 16:33:54.789327 LPDDR4 DRAM CONFIGURATION
6083 16:33:54.792698 ===================================
6084 16:33:54.792789 EX_ROW_EN[0] = 0x0
6085 16:33:54.795768 EX_ROW_EN[1] = 0x0
6086 16:33:54.795858 LP4Y_EN = 0x0
6087 16:33:54.799558 WORK_FSP = 0x0
6088 16:33:54.799649 WL = 0x2
6089 16:33:54.802582 RL = 0x2
6090 16:33:54.805899 BL = 0x2
6091 16:33:54.806002 RPST = 0x0
6092 16:33:54.809317 RD_PRE = 0x0
6093 16:33:54.809397 WR_PRE = 0x1
6094 16:33:54.812938 WR_PST = 0x0
6095 16:33:54.813016 DBI_WR = 0x0
6096 16:33:54.815593 DBI_RD = 0x0
6097 16:33:54.815668 OTF = 0x1
6098 16:33:54.819143 ===================================
6099 16:33:54.822847 ===================================
6100 16:33:54.825548 ANA top config
6101 16:33:54.828954 ===================================
6102 16:33:54.829071 DLL_ASYNC_EN = 0
6103 16:33:54.832484 ALL_SLAVE_EN = 1
6104 16:33:54.835352 NEW_RANK_MODE = 1
6105 16:33:54.838972 DLL_IDLE_MODE = 1
6106 16:33:54.839081 LP45_APHY_COMB_EN = 1
6107 16:33:54.842422 TX_ODT_DIS = 1
6108 16:33:54.845944 NEW_8X_MODE = 1
6109 16:33:54.848754 ===================================
6110 16:33:54.852269 ===================================
6111 16:33:54.855781 data_rate = 800
6112 16:33:54.858562 CKR = 1
6113 16:33:54.862021 DQ_P2S_RATIO = 4
6114 16:33:54.865521 ===================================
6115 16:33:54.865630 CA_P2S_RATIO = 4
6116 16:33:54.869039 DQ_CA_OPEN = 0
6117 16:33:54.872131 DQ_SEMI_OPEN = 1
6118 16:33:54.875393 CA_SEMI_OPEN = 1
6119 16:33:54.878598 CA_FULL_RATE = 0
6120 16:33:54.881744 DQ_CKDIV4_EN = 0
6121 16:33:54.881817 CA_CKDIV4_EN = 1
6122 16:33:54.884974 CA_PREDIV_EN = 0
6123 16:33:54.888455 PH8_DLY = 0
6124 16:33:54.891904 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6125 16:33:54.895456 DQ_AAMCK_DIV = 0
6126 16:33:54.898284 CA_AAMCK_DIV = 0
6127 16:33:54.898359 CA_ADMCK_DIV = 4
6128 16:33:54.901835 DQ_TRACK_CA_EN = 0
6129 16:33:54.905150 CA_PICK = 800
6130 16:33:54.908472 CA_MCKIO = 400
6131 16:33:54.911770 MCKIO_SEMI = 400
6132 16:33:54.914955 PLL_FREQ = 3016
6133 16:33:54.917957 DQ_UI_PI_RATIO = 32
6134 16:33:54.921682 CA_UI_PI_RATIO = 32
6135 16:33:54.924715 ===================================
6136 16:33:54.928388 ===================================
6137 16:33:54.928462 memory_type:LPDDR4
6138 16:33:54.931599 GP_NUM : 10
6139 16:33:54.934379 SRAM_EN : 1
6140 16:33:54.934449 MD32_EN : 0
6141 16:33:54.937835 ===================================
6142 16:33:54.941215 [ANA_INIT] >>>>>>>>>>>>>>
6143 16:33:54.944832 <<<<<< [CONFIGURE PHASE]: ANA_TX
6144 16:33:54.948280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6145 16:33:54.951078 ===================================
6146 16:33:54.954616 data_rate = 800,PCW = 0X7400
6147 16:33:54.958053 ===================================
6148 16:33:54.961405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6149 16:33:54.964696 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 16:33:54.977742 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6151 16:33:54.980953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6152 16:33:54.984185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6153 16:33:54.987439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6154 16:33:54.990869 [ANA_INIT] flow start
6155 16:33:54.990975 [ANA_INIT] PLL >>>>>>>>
6156 16:33:54.994112 [ANA_INIT] PLL <<<<<<<<
6157 16:33:54.997686 [ANA_INIT] MIDPI >>>>>>>>
6158 16:33:55.000954 [ANA_INIT] MIDPI <<<<<<<<
6159 16:33:55.001030 [ANA_INIT] DLL >>>>>>>>
6160 16:33:55.004498 [ANA_INIT] flow end
6161 16:33:55.007284 ============ LP4 DIFF to SE enter ============
6162 16:33:55.010776 ============ LP4 DIFF to SE exit ============
6163 16:33:55.014336 [ANA_INIT] <<<<<<<<<<<<<
6164 16:33:55.017198 [Flow] Enable top DCM control >>>>>
6165 16:33:55.020729 [Flow] Enable top DCM control <<<<<
6166 16:33:55.024270 Enable DLL master slave shuffle
6167 16:33:55.030374 ==============================================================
6168 16:33:55.030458 Gating Mode config
6169 16:33:55.036733 ==============================================================
6170 16:33:55.036815 Config description:
6171 16:33:55.047019 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6172 16:33:55.053852 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6173 16:33:55.060225 SELPH_MODE 0: By rank 1: By Phase
6174 16:33:55.066408 ==============================================================
6175 16:33:55.066488 GAT_TRACK_EN = 0
6176 16:33:55.069876 RX_GATING_MODE = 2
6177 16:33:55.073324 RX_GATING_TRACK_MODE = 2
6178 16:33:55.076819 SELPH_MODE = 1
6179 16:33:55.080103 PICG_EARLY_EN = 1
6180 16:33:55.083564 VALID_LAT_VALUE = 1
6181 16:33:55.089644 ==============================================================
6182 16:33:55.093071 Enter into Gating configuration >>>>
6183 16:33:55.096582 Exit from Gating configuration <<<<
6184 16:33:55.100098 Enter into DVFS_PRE_config >>>>>
6185 16:33:55.109564 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6186 16:33:55.113074 Exit from DVFS_PRE_config <<<<<
6187 16:33:55.115817 Enter into PICG configuration >>>>
6188 16:33:55.119308 Exit from PICG configuration <<<<
6189 16:33:55.122645 [RX_INPUT] configuration >>>>>
6190 16:33:55.126141 [RX_INPUT] configuration <<<<<
6191 16:33:55.128941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6192 16:33:55.135795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6193 16:33:55.141989 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6194 16:33:55.148915 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6195 16:33:55.152276 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6196 16:33:55.159043 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6197 16:33:55.162017 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6198 16:33:55.168921 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6199 16:33:55.171976 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6200 16:33:55.175158 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6201 16:33:55.178583 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6202 16:33:55.185516 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6203 16:33:55.188288 ===================================
6204 16:33:55.191910 LPDDR4 DRAM CONFIGURATION
6205 16:33:55.195219 ===================================
6206 16:33:55.195301 EX_ROW_EN[0] = 0x0
6207 16:33:55.198419 EX_ROW_EN[1] = 0x0
6208 16:33:55.198496 LP4Y_EN = 0x0
6209 16:33:55.201822 WORK_FSP = 0x0
6210 16:33:55.201902 WL = 0x2
6211 16:33:55.204590 RL = 0x2
6212 16:33:55.204667 BL = 0x2
6213 16:33:55.208066 RPST = 0x0
6214 16:33:55.208177 RD_PRE = 0x0
6215 16:33:55.211499 WR_PRE = 0x1
6216 16:33:55.214935 WR_PST = 0x0
6217 16:33:55.215017 DBI_WR = 0x0
6218 16:33:55.218423 DBI_RD = 0x0
6219 16:33:55.218517 OTF = 0x1
6220 16:33:55.221180 ===================================
6221 16:33:55.224628 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6222 16:33:55.230841 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6223 16:33:55.234308 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 16:33:55.237762 ===================================
6225 16:33:55.241194 LPDDR4 DRAM CONFIGURATION
6226 16:33:55.244112 ===================================
6227 16:33:55.244191 EX_ROW_EN[0] = 0x10
6228 16:33:55.247624 EX_ROW_EN[1] = 0x0
6229 16:33:55.247712 LP4Y_EN = 0x0
6230 16:33:55.251194 WORK_FSP = 0x0
6231 16:33:55.251275 WL = 0x2
6232 16:33:55.253888 RL = 0x2
6233 16:33:55.257827 BL = 0x2
6234 16:33:55.257911 RPST = 0x0
6235 16:33:55.260749 RD_PRE = 0x0
6236 16:33:55.260868 WR_PRE = 0x1
6237 16:33:55.263992 WR_PST = 0x0
6238 16:33:55.264096 DBI_WR = 0x0
6239 16:33:55.267395 DBI_RD = 0x0
6240 16:33:55.267478 OTF = 0x1
6241 16:33:55.270612 ===================================
6242 16:33:55.277107 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6243 16:33:55.280931 nWR fixed to 30
6244 16:33:55.284388 [ModeRegInit_LP4] CH0 RK0
6245 16:33:55.284471 [ModeRegInit_LP4] CH0 RK1
6246 16:33:55.287487 [ModeRegInit_LP4] CH1 RK0
6247 16:33:55.290751 [ModeRegInit_LP4] CH1 RK1
6248 16:33:55.290851 match AC timing 19
6249 16:33:55.298095 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6250 16:33:55.301370 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6251 16:33:55.304466 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6252 16:33:55.310969 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6253 16:33:55.313957 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6254 16:33:55.314043 ==
6255 16:33:55.317454 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 16:33:55.320877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 16:33:55.321037 ==
6258 16:33:55.327089 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 16:33:55.333838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6260 16:33:55.337208 [CA 0] Center 36 (8~64) winsize 57
6261 16:33:55.340726 [CA 1] Center 36 (8~64) winsize 57
6262 16:33:55.344035 [CA 2] Center 36 (8~64) winsize 57
6263 16:33:55.347413 [CA 3] Center 36 (8~64) winsize 57
6264 16:33:55.350166 [CA 4] Center 36 (8~64) winsize 57
6265 16:33:55.353602 [CA 5] Center 36 (8~64) winsize 57
6266 16:33:55.353687
6267 16:33:55.357119 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6268 16:33:55.357334
6269 16:33:55.359906 [CATrainingPosCal] consider 1 rank data
6270 16:33:55.363228 u2DelayCellTimex100 = 270/100 ps
6271 16:33:55.366701 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 16:33:55.370104 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 16:33:55.373582 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 16:33:55.376998 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 16:33:55.379831 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 16:33:55.383103 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 16:33:55.383189
6278 16:33:55.389981 CA PerBit enable=1, Macro0, CA PI delay=36
6279 16:33:55.390091
6280 16:33:55.390191 [CBTSetCACLKResult] CA Dly = 36
6281 16:33:55.392810 CS Dly: 1 (0~32)
6282 16:33:55.392893 ==
6283 16:33:55.396128 Dram Type= 6, Freq= 0, CH_0, rank 1
6284 16:33:55.399441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 16:33:55.399526 ==
6286 16:33:55.406064 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6287 16:33:55.412841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6288 16:33:55.416546 [CA 0] Center 36 (8~64) winsize 57
6289 16:33:55.419454 [CA 1] Center 36 (8~64) winsize 57
6290 16:33:55.422595 [CA 2] Center 36 (8~64) winsize 57
6291 16:33:55.425934 [CA 3] Center 36 (8~64) winsize 57
6292 16:33:55.426021 [CA 4] Center 36 (8~64) winsize 57
6293 16:33:55.429158 [CA 5] Center 36 (8~64) winsize 57
6294 16:33:55.429244
6295 16:33:55.435954 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6296 16:33:55.436042
6297 16:33:55.439337 [CATrainingPosCal] consider 2 rank data
6298 16:33:55.442861 u2DelayCellTimex100 = 270/100 ps
6299 16:33:55.445645 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 16:33:55.449064 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 16:33:55.452658 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 16:33:55.455998 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 16:33:55.459470 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 16:33:55.462127 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 16:33:55.462234
6306 16:33:55.465673 CA PerBit enable=1, Macro0, CA PI delay=36
6307 16:33:55.465783
6308 16:33:55.469206 [CBTSetCACLKResult] CA Dly = 36
6309 16:33:55.471997 CS Dly: 1 (0~32)
6310 16:33:55.472107
6311 16:33:55.475389 ----->DramcWriteLeveling(PI) begin...
6312 16:33:55.475512 ==
6313 16:33:55.478935 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 16:33:55.482248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 16:33:55.482395 ==
6316 16:33:55.485722 Write leveling (Byte 0): 40 => 8
6317 16:33:55.489092 Write leveling (Byte 1): 32 => 0
6318 16:33:55.492327 DramcWriteLeveling(PI) end<-----
6319 16:33:55.492498
6320 16:33:55.492634 ==
6321 16:33:55.495369 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 16:33:55.498734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 16:33:55.498979 ==
6324 16:33:55.502339 [Gating] SW mode calibration
6325 16:33:55.508629 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6326 16:33:55.515786 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6327 16:33:55.518469 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 16:33:55.525277 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6329 16:33:55.528375 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 16:33:55.532315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 16:33:55.538385 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 16:33:55.541808 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 16:33:55.545454 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 16:33:55.551748 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 16:33:55.555181 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 16:33:55.558093 Total UI for P1: 0, mck2ui 16
6337 16:33:55.561392 best dqsien dly found for B0: ( 0, 14, 24)
6338 16:33:55.564913 Total UI for P1: 0, mck2ui 16
6339 16:33:55.568692 best dqsien dly found for B1: ( 0, 14, 24)
6340 16:33:55.571522 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6341 16:33:55.575321 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6342 16:33:55.575738
6343 16:33:55.577934 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 16:33:55.581310 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6345 16:33:55.584561 [Gating] SW calibration Done
6346 16:33:55.584976 ==
6347 16:33:55.587956 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 16:33:55.594297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 16:33:55.594725 ==
6350 16:33:55.595060 RX Vref Scan: 0
6351 16:33:55.595377
6352 16:33:55.597842 RX Vref 0 -> 0, step: 1
6353 16:33:55.598395
6354 16:33:55.601253 RX Delay -410 -> 252, step: 16
6355 16:33:55.604648 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6356 16:33:55.607407 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6357 16:33:55.614543 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6358 16:33:55.617332 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6359 16:33:55.620820 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6360 16:33:55.624452 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6361 16:33:55.630596 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6362 16:33:55.634082 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6363 16:33:55.637739 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6364 16:33:55.640411 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6365 16:33:55.647132 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6366 16:33:55.650466 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6367 16:33:55.653584 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6368 16:33:55.657246 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6369 16:33:55.663840 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6370 16:33:55.667347 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6371 16:33:55.667767 ==
6372 16:33:55.670619 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 16:33:55.673474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 16:33:55.673893 ==
6375 16:33:55.676874 DQS Delay:
6376 16:33:55.677425 DQS0 = 43, DQS1 = 59
6377 16:33:55.680331 DQM Delay:
6378 16:33:55.680745 DQM0 = 9, DQM1 = 11
6379 16:33:55.683399 DQ Delay:
6380 16:33:55.683812 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6381 16:33:55.686757 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6382 16:33:55.690285 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6383 16:33:55.693037 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6384 16:33:55.693518
6385 16:33:55.693975
6386 16:33:55.694354 ==
6387 16:33:55.697019 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 16:33:55.703055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 16:33:55.703475 ==
6390 16:33:55.703813
6391 16:33:55.704140
6392 16:33:55.706085 TX Vref Scan disable
6393 16:33:55.706177 == TX Byte 0 ==
6394 16:33:55.709624 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 16:33:55.715877 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 16:33:55.715959 == TX Byte 1 ==
6397 16:33:55.719198 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6398 16:33:55.726533 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6399 16:33:55.726984 ==
6400 16:33:55.729417 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 16:33:55.732819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 16:33:55.733240 ==
6403 16:33:55.733577
6404 16:33:55.733887
6405 16:33:55.736178 TX Vref Scan disable
6406 16:33:55.736709 == TX Byte 0 ==
6407 16:33:55.739698 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 16:33:55.745959 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 16:33:55.746437 == TX Byte 1 ==
6410 16:33:55.749470 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6411 16:33:55.756140 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6412 16:33:55.756566
6413 16:33:55.756917 [DATLAT]
6414 16:33:55.759522 Freq=400, CH0 RK0
6415 16:33:55.759988
6416 16:33:55.760328 DATLAT Default: 0xf
6417 16:33:55.762285 0, 0xFFFF, sum = 0
6418 16:33:55.762727 1, 0xFFFF, sum = 0
6419 16:33:55.765768 2, 0xFFFF, sum = 0
6420 16:33:55.766233 3, 0xFFFF, sum = 0
6421 16:33:55.769059 4, 0xFFFF, sum = 0
6422 16:33:55.769657 5, 0xFFFF, sum = 0
6423 16:33:55.772259 6, 0xFFFF, sum = 0
6424 16:33:55.772877 7, 0xFFFF, sum = 0
6425 16:33:55.775619 8, 0xFFFF, sum = 0
6426 16:33:55.776205 9, 0xFFFF, sum = 0
6427 16:33:55.778822 10, 0xFFFF, sum = 0
6428 16:33:55.782045 11, 0xFFFF, sum = 0
6429 16:33:55.782556 12, 0xFFFF, sum = 0
6430 16:33:55.785563 13, 0x0, sum = 1
6431 16:33:55.786052 14, 0x0, sum = 2
6432 16:33:55.786731 15, 0x0, sum = 3
6433 16:33:55.788619 16, 0x0, sum = 4
6434 16:33:55.789091 best_step = 14
6435 16:33:55.789460
6436 16:33:55.792227 ==
6437 16:33:55.795033 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 16:33:55.798119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 16:33:55.798719 ==
6440 16:33:55.799147 RX Vref Scan: 1
6441 16:33:55.799675
6442 16:33:55.801580 RX Vref 0 -> 0, step: 1
6443 16:33:55.802544
6444 16:33:55.804811 RX Delay -359 -> 252, step: 8
6445 16:33:55.805451
6446 16:33:55.808243 Set Vref, RX VrefLevel [Byte0]: 57
6447 16:33:55.811644 [Byte1]: 48
6448 16:33:55.815006
6449 16:33:55.815559 Final RX Vref Byte 0 = 57 to rank0
6450 16:33:55.818456 Final RX Vref Byte 1 = 48 to rank0
6451 16:33:55.821973 Final RX Vref Byte 0 = 57 to rank1
6452 16:33:55.825078 Final RX Vref Byte 1 = 48 to rank1==
6453 16:33:55.828577 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 16:33:55.834877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 16:33:55.835196 ==
6456 16:33:55.835426 DQS Delay:
6457 16:33:55.838386 DQS0 = 48, DQS1 = 60
6458 16:33:55.838600 DQM Delay:
6459 16:33:55.838783 DQM0 = 11, DQM1 = 12
6460 16:33:55.841804 DQ Delay:
6461 16:33:55.844528 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6462 16:33:55.848013 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6463 16:33:55.848259 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6464 16:33:55.851414 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6465 16:33:55.854906
6466 16:33:55.855079
6467 16:33:55.861335 [DQSOSCAuto] RK0, (LSB)MR18= 0xbf84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6468 16:33:55.864655 CH0 RK0: MR19=C0C, MR18=BF84
6469 16:33:55.871398 CH0_RK0: MR19=0xC0C, MR18=0xBF84, DQSOSC=386, MR23=63, INC=396, DEC=264
6470 16:33:55.871574 ==
6471 16:33:55.874343 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 16:33:55.877892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 16:33:55.878072 ==
6474 16:33:55.881225 [Gating] SW mode calibration
6475 16:33:55.887408 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6476 16:33:55.894338 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6477 16:33:55.897558 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 16:33:55.900627 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6479 16:33:55.907436 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 16:33:55.910853 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 16:33:55.913974 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 16:33:55.920923 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 16:33:55.924289 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 16:33:55.926981 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 16:33:55.934178 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 16:33:55.934272 Total UI for P1: 0, mck2ui 16
6487 16:33:55.940359 best dqsien dly found for B0: ( 0, 14, 24)
6488 16:33:55.940444 Total UI for P1: 0, mck2ui 16
6489 16:33:55.947346 best dqsien dly found for B1: ( 0, 14, 24)
6490 16:33:55.950133 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6491 16:33:55.953869 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6492 16:33:55.953965
6493 16:33:55.956726 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 16:33:55.960317 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6495 16:33:55.963863 [Gating] SW calibration Done
6496 16:33:55.963975 ==
6497 16:33:55.967226 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 16:33:55.970551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 16:33:55.970676 ==
6500 16:33:55.973582 RX Vref Scan: 0
6501 16:33:55.973720
6502 16:33:55.977079 RX Vref 0 -> 0, step: 1
6503 16:33:55.977236
6504 16:33:55.977360 RX Delay -410 -> 252, step: 16
6505 16:33:55.983415 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6506 16:33:55.987109 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6507 16:33:55.990433 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6508 16:33:55.996696 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6509 16:33:56.000377 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6510 16:33:56.003644 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6511 16:33:56.006856 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6512 16:33:56.013226 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6513 16:33:56.016642 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6514 16:33:56.020192 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6515 16:33:56.023571 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6516 16:33:56.030057 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6517 16:33:56.033187 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6518 16:33:56.036240 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6519 16:33:56.040572 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6520 16:33:56.046274 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6521 16:33:56.046706 ==
6522 16:33:56.049922 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 16:33:56.053484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 16:33:56.053908 ==
6525 16:33:56.054298 DQS Delay:
6526 16:33:56.056461 DQS0 = 43, DQS1 = 59
6527 16:33:56.056999 DQM Delay:
6528 16:33:56.059856 DQM0 = 10, DQM1 = 16
6529 16:33:56.060277 DQ Delay:
6530 16:33:56.062843 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6531 16:33:56.066097 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6532 16:33:56.069597 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6533 16:33:56.072902 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6534 16:33:56.073324
6535 16:33:56.073658
6536 16:33:56.073971 ==
6537 16:33:56.076142 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 16:33:56.079510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 16:33:56.079936 ==
6540 16:33:56.080275
6541 16:33:56.082836
6542 16:33:56.083256 TX Vref Scan disable
6543 16:33:56.086234 == TX Byte 0 ==
6544 16:33:56.089828 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6545 16:33:56.092520 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6546 16:33:56.095901 == TX Byte 1 ==
6547 16:33:56.099544 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6548 16:33:56.102274 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6549 16:33:56.102702 ==
6550 16:33:56.105682 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 16:33:56.109142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 16:33:56.112449 ==
6553 16:33:56.112997
6554 16:33:56.113375
6555 16:33:56.113691 TX Vref Scan disable
6556 16:33:56.116068 == TX Byte 0 ==
6557 16:33:56.119242 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6558 16:33:56.122666 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6559 16:33:56.125165 == TX Byte 1 ==
6560 16:33:56.128806 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6561 16:33:56.132139 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6562 16:33:56.132563
6563 16:33:56.135589 [DATLAT]
6564 16:33:56.136131 Freq=400, CH0 RK1
6565 16:33:56.136473
6566 16:33:56.138893 DATLAT Default: 0xe
6567 16:33:56.139304 0, 0xFFFF, sum = 0
6568 16:33:56.142367 1, 0xFFFF, sum = 0
6569 16:33:56.142953 2, 0xFFFF, sum = 0
6570 16:33:56.145094 3, 0xFFFF, sum = 0
6571 16:33:56.145524 4, 0xFFFF, sum = 0
6572 16:33:56.148549 5, 0xFFFF, sum = 0
6573 16:33:56.148979 6, 0xFFFF, sum = 0
6574 16:33:56.152124 7, 0xFFFF, sum = 0
6575 16:33:56.152549 8, 0xFFFF, sum = 0
6576 16:33:56.155016 9, 0xFFFF, sum = 0
6577 16:33:56.155454 10, 0xFFFF, sum = 0
6578 16:33:56.158733 11, 0xFFFF, sum = 0
6579 16:33:56.159162 12, 0xFFFF, sum = 0
6580 16:33:56.161865 13, 0x0, sum = 1
6581 16:33:56.162333 14, 0x0, sum = 2
6582 16:33:56.165138 15, 0x0, sum = 3
6583 16:33:56.165677 16, 0x0, sum = 4
6584 16:33:56.168765 best_step = 14
6585 16:33:56.169186
6586 16:33:56.169520 ==
6587 16:33:56.171473 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 16:33:56.175108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 16:33:56.175533 ==
6590 16:33:56.178279 RX Vref Scan: 0
6591 16:33:56.178842
6592 16:33:56.179299 RX Vref 0 -> 0, step: 1
6593 16:33:56.179821
6594 16:33:56.181543 RX Delay -359 -> 252, step: 8
6595 16:33:56.189971 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6596 16:33:56.193449 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6597 16:33:56.196257 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6598 16:33:56.203084 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6599 16:33:56.206535 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6600 16:33:56.209455 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6601 16:33:56.212959 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6602 16:33:56.219699 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6603 16:33:56.222334 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6604 16:33:56.225665 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6605 16:33:56.228992 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6606 16:33:56.235858 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6607 16:33:56.239307 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6608 16:33:56.242827 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6609 16:33:56.245712 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6610 16:33:56.252328 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6611 16:33:56.252798 ==
6612 16:33:56.255788 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 16:33:56.259215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 16:33:56.259725 ==
6615 16:33:56.260107 DQS Delay:
6616 16:33:56.261975 DQS0 = 44, DQS1 = 60
6617 16:33:56.262442 DQM Delay:
6618 16:33:56.266039 DQM0 = 8, DQM1 = 15
6619 16:33:56.266558 DQ Delay:
6620 16:33:56.269278 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6621 16:33:56.272331 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6622 16:33:56.275516 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6623 16:33:56.278876 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6624 16:33:56.279291
6625 16:33:56.279619
6626 16:33:56.285718 [DQSOSCAuto] RK1, (LSB)MR18= 0xb441, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6627 16:33:56.288740 CH0 RK1: MR19=C0C, MR18=B441
6628 16:33:56.295557 CH0_RK1: MR19=0xC0C, MR18=0xB441, DQSOSC=387, MR23=63, INC=394, DEC=262
6629 16:33:56.298320 [RxdqsGatingPostProcess] freq 400
6630 16:33:56.305170 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6631 16:33:56.308456 best DQS0 dly(2T, 0.5T) = (0, 10)
6632 16:33:56.312207 best DQS1 dly(2T, 0.5T) = (0, 10)
6633 16:33:56.314868 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6634 16:33:56.318245 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6635 16:33:56.318670 best DQS0 dly(2T, 0.5T) = (0, 10)
6636 16:33:56.321818 best DQS1 dly(2T, 0.5T) = (0, 10)
6637 16:33:56.325282 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6638 16:33:56.328060 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6639 16:33:56.331547 Pre-setting of DQS Precalculation
6640 16:33:56.337959 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6641 16:33:56.338505 ==
6642 16:33:56.341393 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 16:33:56.344788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 16:33:56.345487 ==
6645 16:33:56.351576 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 16:33:56.357775 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6647 16:33:56.361303 [CA 0] Center 36 (8~64) winsize 57
6648 16:33:56.364884 [CA 1] Center 36 (8~64) winsize 57
6649 16:33:56.365305 [CA 2] Center 36 (8~64) winsize 57
6650 16:33:56.367739 [CA 3] Center 36 (8~64) winsize 57
6651 16:33:56.371212 [CA 4] Center 36 (8~64) winsize 57
6652 16:33:56.374213 [CA 5] Center 36 (8~64) winsize 57
6653 16:33:56.374746
6654 16:33:56.381102 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6655 16:33:56.381637
6656 16:33:56.384135 [CATrainingPosCal] consider 1 rank data
6657 16:33:56.387424 u2DelayCellTimex100 = 270/100 ps
6658 16:33:56.390632 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 16:33:56.393790 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 16:33:56.397390 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 16:33:56.400391 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 16:33:56.404080 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 16:33:56.407130 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 16:33:56.407687
6665 16:33:56.410578 CA PerBit enable=1, Macro0, CA PI delay=36
6666 16:33:56.411025
6667 16:33:56.414100 [CBTSetCACLKResult] CA Dly = 36
6668 16:33:56.417822 CS Dly: 1 (0~32)
6669 16:33:56.418331 ==
6670 16:33:56.420294 Dram Type= 6, Freq= 0, CH_1, rank 1
6671 16:33:56.423986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 16:33:56.424674 ==
6673 16:33:56.430296 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6674 16:33:56.436632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6675 16:33:56.440298 [CA 0] Center 36 (8~64) winsize 57
6676 16:33:56.440724 [CA 1] Center 36 (8~64) winsize 57
6677 16:33:56.443656 [CA 2] Center 36 (8~64) winsize 57
6678 16:33:56.447151 [CA 3] Center 36 (8~64) winsize 57
6679 16:33:56.449777 [CA 4] Center 36 (8~64) winsize 57
6680 16:33:56.453572 [CA 5] Center 36 (8~64) winsize 57
6681 16:33:56.454208
6682 16:33:56.456444 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6683 16:33:56.456859
6684 16:33:56.463302 [CATrainingPosCal] consider 2 rank data
6685 16:33:56.463765 u2DelayCellTimex100 = 270/100 ps
6686 16:33:56.469817 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 16:33:56.472510 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 16:33:56.475940 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 16:33:56.479485 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 16:33:56.482852 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 16:33:56.485733 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 16:33:56.485887
6693 16:33:56.489251 CA PerBit enable=1, Macro0, CA PI delay=36
6694 16:33:56.489381
6695 16:33:56.492686 [CBTSetCACLKResult] CA Dly = 36
6696 16:33:56.496325 CS Dly: 1 (0~32)
6697 16:33:56.496438
6698 16:33:56.498989 ----->DramcWriteLeveling(PI) begin...
6699 16:33:56.499072 ==
6700 16:33:56.502415 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 16:33:56.505562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 16:33:56.505671 ==
6703 16:33:56.509274 Write leveling (Byte 0): 40 => 8
6704 16:33:56.512161 Write leveling (Byte 1): 40 => 8
6705 16:33:56.515371 DramcWriteLeveling(PI) end<-----
6706 16:33:56.515452
6707 16:33:56.515517 ==
6708 16:33:56.518572 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 16:33:56.522201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 16:33:56.522297 ==
6711 16:33:56.525669 [Gating] SW mode calibration
6712 16:33:56.531855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6713 16:33:56.538676 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6714 16:33:56.542098 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 16:33:56.545033 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6716 16:33:56.551402 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 16:33:56.554764 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 16:33:56.561837 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 16:33:56.565045 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 16:33:56.567957 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 16:33:56.574810 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 16:33:56.578495 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 16:33:56.581333 Total UI for P1: 0, mck2ui 16
6724 16:33:56.584700 best dqsien dly found for B0: ( 0, 14, 24)
6725 16:33:56.588207 Total UI for P1: 0, mck2ui 16
6726 16:33:56.591634 best dqsien dly found for B1: ( 0, 14, 24)
6727 16:33:56.594328 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6728 16:33:56.598245 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6729 16:33:56.598670
6730 16:33:56.601697 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 16:33:56.604635 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6732 16:33:56.607972 [Gating] SW calibration Done
6733 16:33:56.608394 ==
6734 16:33:56.611541 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 16:33:56.614719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 16:33:56.618241 ==
6737 16:33:56.618659 RX Vref Scan: 0
6738 16:33:56.618992
6739 16:33:56.621478 RX Vref 0 -> 0, step: 1
6740 16:33:56.621924
6741 16:33:56.624390 RX Delay -410 -> 252, step: 16
6742 16:33:56.627892 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6743 16:33:56.631117 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6744 16:33:56.634332 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6745 16:33:56.641056 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6746 16:33:56.644083 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6747 16:33:56.647442 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6748 16:33:56.651191 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6749 16:33:56.657649 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6750 16:33:56.661022 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6751 16:33:56.664469 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6752 16:33:56.667243 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6753 16:33:56.673957 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6754 16:33:56.677188 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6755 16:33:56.680357 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6756 16:33:56.687158 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6757 16:33:56.690634 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6758 16:33:56.691059 ==
6759 16:33:56.694013 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 16:33:56.696731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 16:33:56.697155 ==
6762 16:33:56.700289 DQS Delay:
6763 16:33:56.700708 DQS0 = 43, DQS1 = 51
6764 16:33:56.703664 DQM Delay:
6765 16:33:56.704081 DQM0 = 12, DQM1 = 14
6766 16:33:56.704468 DQ Delay:
6767 16:33:56.707229 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6768 16:33:56.709997 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6769 16:33:56.713506 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6770 16:33:56.716942 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6771 16:33:56.717363
6772 16:33:56.717694
6773 16:33:56.718004 ==
6774 16:33:56.720467 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 16:33:56.723207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 16:33:56.726806 ==
6777 16:33:56.727431
6778 16:33:56.727993
6779 16:33:56.728509 TX Vref Scan disable
6780 16:33:56.730063 == TX Byte 0 ==
6781 16:33:56.733554 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 16:33:56.736966 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 16:33:56.739749 == TX Byte 1 ==
6784 16:33:56.743397 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 16:33:56.746684 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 16:33:56.747107 ==
6787 16:33:56.750271 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 16:33:56.756260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 16:33:56.756708 ==
6790 16:33:56.757046
6791 16:33:56.757360
6792 16:33:56.757659 TX Vref Scan disable
6793 16:33:56.759452 == TX Byte 0 ==
6794 16:33:56.763262 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 16:33:56.766442 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 16:33:56.769491 == TX Byte 1 ==
6797 16:33:56.772814 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 16:33:56.776300 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 16:33:56.776885
6800 16:33:56.779733 [DATLAT]
6801 16:33:56.780293 Freq=400, CH1 RK0
6802 16:33:56.780761
6803 16:33:56.783191 DATLAT Default: 0xf
6804 16:33:56.783615 0, 0xFFFF, sum = 0
6805 16:33:56.786015 1, 0xFFFF, sum = 0
6806 16:33:56.786524 2, 0xFFFF, sum = 0
6807 16:33:56.789629 3, 0xFFFF, sum = 0
6808 16:33:56.790192 4, 0xFFFF, sum = 0
6809 16:33:56.792761 5, 0xFFFF, sum = 0
6810 16:33:56.793351 6, 0xFFFF, sum = 0
6811 16:33:56.795908 7, 0xFFFF, sum = 0
6812 16:33:56.796492 8, 0xFFFF, sum = 0
6813 16:33:56.799111 9, 0xFFFF, sum = 0
6814 16:33:56.802559 10, 0xFFFF, sum = 0
6815 16:33:56.803002 11, 0xFFFF, sum = 0
6816 16:33:56.806029 12, 0xFFFF, sum = 0
6817 16:33:56.806519 13, 0x0, sum = 1
6818 16:33:56.809672 14, 0x0, sum = 2
6819 16:33:56.810353 15, 0x0, sum = 3
6820 16:33:56.812406 16, 0x0, sum = 4
6821 16:33:56.812850 best_step = 14
6822 16:33:56.813394
6823 16:33:56.813740 ==
6824 16:33:56.815851 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 16:33:56.819321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 16:33:56.819749 ==
6827 16:33:56.822688 RX Vref Scan: 1
6828 16:33:56.823124
6829 16:33:56.825523 RX Vref 0 -> 0, step: 1
6830 16:33:56.825962
6831 16:33:56.826465 RX Delay -343 -> 252, step: 8
6832 16:33:56.826889
6833 16:33:56.829000 Set Vref, RX VrefLevel [Byte0]: 52
6834 16:33:56.832330 [Byte1]: 56
6835 16:33:56.837873
6836 16:33:56.838483 Final RX Vref Byte 0 = 52 to rank0
6837 16:33:56.841409 Final RX Vref Byte 1 = 56 to rank0
6838 16:33:56.844199 Final RX Vref Byte 0 = 52 to rank1
6839 16:33:56.847703 Final RX Vref Byte 1 = 56 to rank1==
6840 16:33:56.851182 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 16:33:56.857957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 16:33:56.858489 ==
6843 16:33:56.858918 DQS Delay:
6844 16:33:56.861250 DQS0 = 48, DQS1 = 56
6845 16:33:56.861745 DQM Delay:
6846 16:33:56.862109 DQM0 = 11, DQM1 = 12
6847 16:33:56.864489 DQ Delay:
6848 16:33:56.867402 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6849 16:33:56.870792 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6850 16:33:56.871324 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6851 16:33:56.877473 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6852 16:33:56.878112
6853 16:33:56.878647
6854 16:33:56.883670 [DQSOSCAuto] RK0, (LSB)MR18= 0x996f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6855 16:33:56.887259 CH1 RK0: MR19=C0C, MR18=996F
6856 16:33:56.893396 CH1_RK0: MR19=0xC0C, MR18=0x996F, DQSOSC=390, MR23=63, INC=388, DEC=258
6857 16:33:56.893478 ==
6858 16:33:56.896396 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 16:33:56.899878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 16:33:56.899961 ==
6861 16:33:56.903495 [Gating] SW mode calibration
6862 16:33:56.910064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6863 16:33:56.916628 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6864 16:33:56.920171 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 16:33:56.922857 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6866 16:33:56.929814 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 16:33:56.933318 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 16:33:56.936135 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 16:33:56.943122 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 16:33:56.945962 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 16:33:56.949427 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 16:33:56.955958 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 16:33:56.959284 Total UI for P1: 0, mck2ui 16
6874 16:33:56.962786 best dqsien dly found for B0: ( 0, 14, 24)
6875 16:33:56.965699 Total UI for P1: 0, mck2ui 16
6876 16:33:56.969189 best dqsien dly found for B1: ( 0, 14, 24)
6877 16:33:56.972691 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6878 16:33:56.975940 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6879 16:33:56.976022
6880 16:33:56.979333 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 16:33:56.982061 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6882 16:33:56.985485 [Gating] SW calibration Done
6883 16:33:56.985566 ==
6884 16:33:56.988948 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 16:33:56.992518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 16:33:56.992608 ==
6887 16:33:56.995368 RX Vref Scan: 0
6888 16:33:56.995449
6889 16:33:56.998857 RX Vref 0 -> 0, step: 1
6890 16:33:56.998938
6891 16:33:56.999004 RX Delay -410 -> 252, step: 16
6892 16:33:57.005580 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6893 16:33:57.008971 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6894 16:33:57.012425 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6895 16:33:57.015646 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6896 16:33:57.022320 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6897 16:33:57.025736 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6898 16:33:57.028833 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6899 16:33:57.032296 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6900 16:33:57.039059 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6901 16:33:57.041950 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6902 16:33:57.045429 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6903 16:33:57.051843 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6904 16:33:57.055348 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6905 16:33:57.058127 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6906 16:33:57.061596 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6907 16:33:57.067990 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6908 16:33:57.068072 ==
6909 16:33:57.071488 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 16:33:57.074730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 16:33:57.074812 ==
6912 16:33:57.074877 DQS Delay:
6913 16:33:57.078016 DQS0 = 43, DQS1 = 59
6914 16:33:57.078122 DQM Delay:
6915 16:33:57.081417 DQM0 = 12, DQM1 = 21
6916 16:33:57.081498 DQ Delay:
6917 16:33:57.084796 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6918 16:33:57.088348 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6919 16:33:57.091027 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =8
6920 16:33:57.094422 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6921 16:33:57.094504
6922 16:33:57.094569
6923 16:33:57.094629 ==
6924 16:33:57.097830 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 16:33:57.101348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 16:33:57.101430 ==
6927 16:33:57.104782
6928 16:33:57.104888
6929 16:33:57.104980 TX Vref Scan disable
6930 16:33:57.108065 == TX Byte 0 ==
6931 16:33:57.111453 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6932 16:33:57.114820 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6933 16:33:57.117577 == TX Byte 1 ==
6934 16:33:57.121087 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6935 16:33:57.124375 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6936 16:33:57.124457 ==
6937 16:33:57.127674 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 16:33:57.131125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 16:33:57.134475 ==
6940 16:33:57.134581
6941 16:33:57.134673
6942 16:33:57.134761 TX Vref Scan disable
6943 16:33:57.137812 == TX Byte 0 ==
6944 16:33:57.140908 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6945 16:33:57.144274 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6946 16:33:57.147779 == TX Byte 1 ==
6947 16:33:57.150563 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6948 16:33:57.154023 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6949 16:33:57.154104
6950 16:33:57.157525 [DATLAT]
6951 16:33:57.157606 Freq=400, CH1 RK1
6952 16:33:57.157671
6953 16:33:57.160479 DATLAT Default: 0xe
6954 16:33:57.160560 0, 0xFFFF, sum = 0
6955 16:33:57.163894 1, 0xFFFF, sum = 0
6956 16:33:57.163982 2, 0xFFFF, sum = 0
6957 16:33:57.167350 3, 0xFFFF, sum = 0
6958 16:33:57.167438 4, 0xFFFF, sum = 0
6959 16:33:57.170998 5, 0xFFFF, sum = 0
6960 16:33:57.171115 6, 0xFFFF, sum = 0
6961 16:33:57.173845 7, 0xFFFF, sum = 0
6962 16:33:57.173947 8, 0xFFFF, sum = 0
6963 16:33:57.177338 9, 0xFFFF, sum = 0
6964 16:33:57.177441 10, 0xFFFF, sum = 0
6965 16:33:57.180531 11, 0xFFFF, sum = 0
6966 16:33:57.183229 12, 0xFFFF, sum = 0
6967 16:33:57.183336 13, 0x0, sum = 1
6968 16:33:57.186555 14, 0x0, sum = 2
6969 16:33:57.186666 15, 0x0, sum = 3
6970 16:33:57.186760 16, 0x0, sum = 4
6971 16:33:57.190017 best_step = 14
6972 16:33:57.190124
6973 16:33:57.190211 ==
6974 16:33:57.193437 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 16:33:57.196872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 16:33:57.196971 ==
6977 16:33:57.199679 RX Vref Scan: 0
6978 16:33:57.199785
6979 16:33:57.203305 RX Vref 0 -> 0, step: 1
6980 16:33:57.203390
6981 16:33:57.203461 RX Delay -359 -> 252, step: 8
6982 16:33:57.211830 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6983 16:33:57.215421 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6984 16:33:57.218715 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6985 16:33:57.224859 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6986 16:33:57.228281 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6987 16:33:57.231605 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6988 16:33:57.234925 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6989 16:33:57.238017 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6990 16:33:57.244890 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6991 16:33:57.248162 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6992 16:33:57.251388 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6993 16:33:57.258240 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6994 16:33:57.261101 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6995 16:33:57.264569 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6996 16:33:57.268196 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6997 16:33:57.274269 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6998 16:33:57.274351 ==
6999 16:33:57.277783 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 16:33:57.281253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 16:33:57.281353 ==
7002 16:33:57.281427 DQS Delay:
7003 16:33:57.284659 DQS0 = 48, DQS1 = 56
7004 16:33:57.284761 DQM Delay:
7005 16:33:57.288009 DQM0 = 11, DQM1 = 11
7006 16:33:57.288106 DQ Delay:
7007 16:33:57.291234 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
7008 16:33:57.294101 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
7009 16:33:57.297544 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7010 16:33:57.300983 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7011 16:33:57.301086
7012 16:33:57.301176
7013 16:33:57.307160 [DQSOSCAuto] RK1, (LSB)MR18= 0x6858, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7014 16:33:57.310717 CH1 RK1: MR19=C0C, MR18=6858
7015 16:33:57.317625 CH1_RK1: MR19=0xC0C, MR18=0x6858, DQSOSC=396, MR23=63, INC=376, DEC=251
7016 16:33:57.320430 [RxdqsGatingPostProcess] freq 400
7017 16:33:57.327281 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7018 16:33:57.330722 best DQS0 dly(2T, 0.5T) = (0, 10)
7019 16:33:57.333579 best DQS1 dly(2T, 0.5T) = (0, 10)
7020 16:33:57.336922 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7021 16:33:57.340220 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7022 16:33:57.343724 best DQS0 dly(2T, 0.5T) = (0, 10)
7023 16:33:57.343800 best DQS1 dly(2T, 0.5T) = (0, 10)
7024 16:33:57.347143 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7025 16:33:57.350749 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7026 16:33:57.354176 Pre-setting of DQS Precalculation
7027 16:33:57.360338 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7028 16:33:57.366847 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7029 16:33:57.373542 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7030 16:33:57.373723
7031 16:33:57.373835
7032 16:33:57.376837 [Calibration Summary] 800 Mbps
7033 16:33:57.376972 CH 0, Rank 0
7034 16:33:57.380195 SW Impedance : PASS
7035 16:33:57.383756 DUTY Scan : NO K
7036 16:33:57.383992 ZQ Calibration : PASS
7037 16:33:57.386720 Jitter Meter : NO K
7038 16:33:57.390218 CBT Training : PASS
7039 16:33:57.390484 Write leveling : PASS
7040 16:33:57.393767 RX DQS gating : PASS
7041 16:33:57.396471 RX DQ/DQS(RDDQC) : PASS
7042 16:33:57.396711 TX DQ/DQS : PASS
7043 16:33:57.399845 RX DATLAT : PASS
7044 16:33:57.403426 RX DQ/DQS(Engine): PASS
7045 16:33:57.403812 TX OE : NO K
7046 16:33:57.406646 All Pass.
7047 16:33:57.407028
7048 16:33:57.407376 CH 0, Rank 1
7049 16:33:57.410319 SW Impedance : PASS
7050 16:33:57.410934 DUTY Scan : NO K
7051 16:33:57.413144 ZQ Calibration : PASS
7052 16:33:57.416639 Jitter Meter : NO K
7053 16:33:57.417073 CBT Training : PASS
7054 16:33:57.420219 Write leveling : NO K
7055 16:33:57.423545 RX DQS gating : PASS
7056 16:33:57.423973 RX DQ/DQS(RDDQC) : PASS
7057 16:33:57.426872 TX DQ/DQS : PASS
7058 16:33:57.429708 RX DATLAT : PASS
7059 16:33:57.430410 RX DQ/DQS(Engine): PASS
7060 16:33:57.433558 TX OE : NO K
7061 16:33:57.434144 All Pass.
7062 16:33:57.434538
7063 16:33:57.436294 CH 1, Rank 0
7064 16:33:57.436710 SW Impedance : PASS
7065 16:33:57.439789 DUTY Scan : NO K
7066 16:33:57.443225 ZQ Calibration : PASS
7067 16:33:57.443648 Jitter Meter : NO K
7068 16:33:57.446643 CBT Training : PASS
7069 16:33:57.449872 Write leveling : PASS
7070 16:33:57.450430 RX DQS gating : PASS
7071 16:33:57.452754 RX DQ/DQS(RDDQC) : PASS
7072 16:33:57.453171 TX DQ/DQS : PASS
7073 16:33:57.456249 RX DATLAT : PASS
7074 16:33:57.459736 RX DQ/DQS(Engine): PASS
7075 16:33:57.460154 TX OE : NO K
7076 16:33:57.462556 All Pass.
7077 16:33:57.462972
7078 16:33:57.463308 CH 1, Rank 1
7079 16:33:57.465967 SW Impedance : PASS
7080 16:33:57.466433 DUTY Scan : NO K
7081 16:33:57.469352 ZQ Calibration : PASS
7082 16:33:57.472816 Jitter Meter : NO K
7083 16:33:57.473254 CBT Training : PASS
7084 16:33:57.476190 Write leveling : NO K
7085 16:33:57.478950 RX DQS gating : PASS
7086 16:33:57.479371 RX DQ/DQS(RDDQC) : PASS
7087 16:33:57.482276 TX DQ/DQS : PASS
7088 16:33:57.485990 RX DATLAT : PASS
7089 16:33:57.486564 RX DQ/DQS(Engine): PASS
7090 16:33:57.489198 TX OE : NO K
7091 16:33:57.489618 All Pass.
7092 16:33:57.489952
7093 16:33:57.492242 DramC Write-DBI off
7094 16:33:57.495948 PER_BANK_REFRESH: Hybrid Mode
7095 16:33:57.496440 TX_TRACKING: ON
7096 16:33:57.505689 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7097 16:33:57.508799 [FAST_K] Save calibration result to emmc
7098 16:33:57.512136 dramc_set_vcore_voltage set vcore to 725000
7099 16:33:57.515527 Read voltage for 1600, 0
7100 16:33:57.516072 Vio18 = 0
7101 16:33:57.519030 Vcore = 725000
7102 16:33:57.519628 Vdram = 0
7103 16:33:57.520152 Vddq = 0
7104 16:33:57.520668 Vmddr = 0
7105 16:33:57.525060 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7106 16:33:57.532194 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7107 16:33:57.532776 MEM_TYPE=3, freq_sel=13
7108 16:33:57.535311 sv_algorithm_assistance_LP4_3733
7109 16:33:57.538773 ============ PULL DRAM RESETB DOWN ============
7110 16:33:57.545638 ========== PULL DRAM RESETB DOWN end =========
7111 16:33:57.548421 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7112 16:33:57.551502 ===================================
7113 16:33:57.554832 LPDDR4 DRAM CONFIGURATION
7114 16:33:57.558146 ===================================
7115 16:33:57.558739 EX_ROW_EN[0] = 0x0
7116 16:33:57.561799 EX_ROW_EN[1] = 0x0
7117 16:33:57.562533 LP4Y_EN = 0x0
7118 16:33:57.564588 WORK_FSP = 0x1
7119 16:33:57.568119 WL = 0x5
7120 16:33:57.568549 RL = 0x5
7121 16:33:57.571653 BL = 0x2
7122 16:33:57.572318 RPST = 0x0
7123 16:33:57.574359 RD_PRE = 0x0
7124 16:33:57.574778 WR_PRE = 0x1
7125 16:33:57.577914 WR_PST = 0x1
7126 16:33:57.578506 DBI_WR = 0x0
7127 16:33:57.581238 DBI_RD = 0x0
7128 16:33:57.581882 OTF = 0x1
7129 16:33:57.584609 ===================================
7130 16:33:57.587620 ===================================
7131 16:33:57.590987 ANA top config
7132 16:33:57.594416 ===================================
7133 16:33:57.594990 DLL_ASYNC_EN = 0
7134 16:33:57.597109 ALL_SLAVE_EN = 0
7135 16:33:57.600680 NEW_RANK_MODE = 1
7136 16:33:57.603979 DLL_IDLE_MODE = 1
7137 16:33:57.607138 LP45_APHY_COMB_EN = 1
7138 16:33:57.607567 TX_ODT_DIS = 0
7139 16:33:57.610251 NEW_8X_MODE = 1
7140 16:33:57.613855 ===================================
7141 16:33:57.617001 ===================================
7142 16:33:57.620328 data_rate = 3200
7143 16:33:57.623543 CKR = 1
7144 16:33:57.626751 DQ_P2S_RATIO = 8
7145 16:33:57.630342 ===================================
7146 16:33:57.633343 CA_P2S_RATIO = 8
7147 16:33:57.633729 DQ_CA_OPEN = 0
7148 16:33:57.636771 DQ_SEMI_OPEN = 0
7149 16:33:57.640122 CA_SEMI_OPEN = 0
7150 16:33:57.642755 CA_FULL_RATE = 0
7151 16:33:57.646079 DQ_CKDIV4_EN = 0
7152 16:33:57.649486 CA_CKDIV4_EN = 0
7153 16:33:57.652953 CA_PREDIV_EN = 0
7154 16:33:57.653057 PH8_DLY = 12
7155 16:33:57.656334 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7156 16:33:57.659660 DQ_AAMCK_DIV = 4
7157 16:33:57.663116 CA_AAMCK_DIV = 4
7158 16:33:57.665945 CA_ADMCK_DIV = 4
7159 16:33:57.669372 DQ_TRACK_CA_EN = 0
7160 16:33:57.672800 CA_PICK = 1600
7161 16:33:57.672905 CA_MCKIO = 1600
7162 16:33:57.676275 MCKIO_SEMI = 0
7163 16:33:57.679079 PLL_FREQ = 3068
7164 16:33:57.682441 DQ_UI_PI_RATIO = 32
7165 16:33:57.686000 CA_UI_PI_RATIO = 0
7166 16:33:57.688760 ===================================
7167 16:33:57.692272 ===================================
7168 16:33:57.695672 memory_type:LPDDR4
7169 16:33:57.695758 GP_NUM : 10
7170 16:33:57.699177 SRAM_EN : 1
7171 16:33:57.699357 MD32_EN : 0
7172 16:33:57.702945 ===================================
7173 16:33:57.705365 [ANA_INIT] >>>>>>>>>>>>>>
7174 16:33:57.708695 <<<<<< [CONFIGURE PHASE]: ANA_TX
7175 16:33:57.712240 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7176 16:33:57.715908 ===================================
7177 16:33:57.718564 data_rate = 3200,PCW = 0X7600
7178 16:33:57.721979 ===================================
7179 16:33:57.725163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7180 16:33:57.732383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 16:33:57.735381 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7182 16:33:57.741920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7183 16:33:57.745425 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7184 16:33:57.748207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7185 16:33:57.748575 [ANA_INIT] flow start
7186 16:33:57.751590 [ANA_INIT] PLL >>>>>>>>
7187 16:33:57.755291 [ANA_INIT] PLL <<<<<<<<
7188 16:33:57.758211 [ANA_INIT] MIDPI >>>>>>>>
7189 16:33:57.758526 [ANA_INIT] MIDPI <<<<<<<<
7190 16:33:57.761832 [ANA_INIT] DLL >>>>>>>>
7191 16:33:57.765090 [ANA_INIT] DLL <<<<<<<<
7192 16:33:57.765408 [ANA_INIT] flow end
7193 16:33:57.768586 ============ LP4 DIFF to SE enter ============
7194 16:33:57.774737 ============ LP4 DIFF to SE exit ============
7195 16:33:57.775043 [ANA_INIT] <<<<<<<<<<<<<
7196 16:33:57.778273 [Flow] Enable top DCM control >>>>>
7197 16:33:57.781594 [Flow] Enable top DCM control <<<<<
7198 16:33:57.784369 Enable DLL master slave shuffle
7199 16:33:57.791354 ==============================================================
7200 16:33:57.794866 Gating Mode config
7201 16:33:57.798094 ==============================================================
7202 16:33:57.801968 Config description:
7203 16:33:57.811269 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7204 16:33:57.818031 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7205 16:33:57.821455 SELPH_MODE 0: By rank 1: By Phase
7206 16:33:57.827737 ==============================================================
7207 16:33:57.830945 GAT_TRACK_EN = 1
7208 16:33:57.834390 RX_GATING_MODE = 2
7209 16:33:57.837843 RX_GATING_TRACK_MODE = 2
7210 16:33:57.838402 SELPH_MODE = 1
7211 16:33:57.840678 PICG_EARLY_EN = 1
7212 16:33:57.844124 VALID_LAT_VALUE = 1
7213 16:33:57.851134 ==============================================================
7214 16:33:57.853794 Enter into Gating configuration >>>>
7215 16:33:57.857383 Exit from Gating configuration <<<<
7216 16:33:57.860658 Enter into DVFS_PRE_config >>>>>
7217 16:33:57.870674 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7218 16:33:57.874083 Exit from DVFS_PRE_config <<<<<
7219 16:33:57.876836 Enter into PICG configuration >>>>
7220 16:33:57.880356 Exit from PICG configuration <<<<
7221 16:33:57.884149 [RX_INPUT] configuration >>>>>
7222 16:33:57.886956 [RX_INPUT] configuration <<<<<
7223 16:33:57.890429 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7224 16:33:57.897079 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7225 16:33:57.903334 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7226 16:33:57.910130 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7227 16:33:57.916925 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7228 16:33:57.923235 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7229 16:33:57.926634 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7230 16:33:57.930025 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7231 16:33:57.933598 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7232 16:33:57.939798 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7233 16:33:57.943251 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7234 16:33:57.946631 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7235 16:33:57.949594 ===================================
7236 16:33:57.953078 LPDDR4 DRAM CONFIGURATION
7237 16:33:57.956411 ===================================
7238 16:33:57.956824 EX_ROW_EN[0] = 0x0
7239 16:33:57.959941 EX_ROW_EN[1] = 0x0
7240 16:33:57.963359 LP4Y_EN = 0x0
7241 16:33:57.964001 WORK_FSP = 0x1
7242 16:33:57.966078 WL = 0x5
7243 16:33:57.966563 RL = 0x5
7244 16:33:57.969454 BL = 0x2
7245 16:33:57.970076 RPST = 0x0
7246 16:33:57.972991 RD_PRE = 0x0
7247 16:33:57.973565 WR_PRE = 0x1
7248 16:33:57.976346 WR_PST = 0x1
7249 16:33:57.976793 DBI_WR = 0x0
7250 16:33:57.979258 DBI_RD = 0x0
7251 16:33:57.979689 OTF = 0x1
7252 16:33:57.982714 ===================================
7253 16:33:57.985855 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7254 16:33:57.992791 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7255 16:33:57.996196 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 16:33:57.999157 ===================================
7257 16:33:58.002474 LPDDR4 DRAM CONFIGURATION
7258 16:33:58.005295 ===================================
7259 16:33:58.005383 EX_ROW_EN[0] = 0x10
7260 16:33:58.008453 EX_ROW_EN[1] = 0x0
7261 16:33:58.012037 LP4Y_EN = 0x0
7262 16:33:58.012179 WORK_FSP = 0x1
7263 16:33:58.015265 WL = 0x5
7264 16:33:58.015353 RL = 0x5
7265 16:33:58.018801 BL = 0x2
7266 16:33:58.018886 RPST = 0x0
7267 16:33:58.022211 RD_PRE = 0x0
7268 16:33:58.022296 WR_PRE = 0x1
7269 16:33:58.025096 WR_PST = 0x1
7270 16:33:58.025185 DBI_WR = 0x0
7271 16:33:58.028553 DBI_RD = 0x0
7272 16:33:58.028659 OTF = 0x1
7273 16:33:58.032053 ===================================
7274 16:33:58.038311 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7275 16:33:58.038396 ==
7276 16:33:58.041709 Dram Type= 6, Freq= 0, CH_0, rank 0
7277 16:33:58.047975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7278 16:33:58.048059 ==
7279 16:33:58.048124 [Duty_Offset_Calibration]
7280 16:33:58.051331 B0:1 B1:-1 CA:0
7281 16:33:58.051426
7282 16:33:58.054818 [DutyScan_Calibration_Flow] k_type=0
7283 16:33:58.064343
7284 16:33:58.064432 ==CLK 0==
7285 16:33:58.067170 Final CLK duty delay cell = 0
7286 16:33:58.070657 [0] MAX Duty = 5125%(X100), DQS PI = 20
7287 16:33:58.074119 [0] MIN Duty = 4907%(X100), DQS PI = 4
7288 16:33:58.074243 [0] AVG Duty = 5016%(X100)
7289 16:33:58.077669
7290 16:33:58.080439 CH0 CLK Duty spec in!! Max-Min= 218%
7291 16:33:58.083903 [DutyScan_Calibration_Flow] ====Done====
7292 16:33:58.083985
7293 16:33:58.087280 [DutyScan_Calibration_Flow] k_type=1
7294 16:33:58.103448
7295 16:33:58.103557 ==DQS 0 ==
7296 16:33:58.106137 Final DQS duty delay cell = -4
7297 16:33:58.109498 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7298 16:33:58.113109 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7299 16:33:58.116233 [-4] AVG Duty = 4906%(X100)
7300 16:33:58.116308
7301 16:33:58.116370 ==DQS 1 ==
7302 16:33:58.119413 Final DQS duty delay cell = 0
7303 16:33:58.123085 [0] MAX Duty = 5156%(X100), DQS PI = 2
7304 16:33:58.126015 [0] MIN Duty = 5000%(X100), DQS PI = 20
7305 16:33:58.129500 [0] AVG Duty = 5078%(X100)
7306 16:33:58.129614
7307 16:33:58.133141 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7308 16:33:58.133236
7309 16:33:58.136326 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7310 16:33:58.139082 [DutyScan_Calibration_Flow] ====Done====
7311 16:33:58.139179
7312 16:33:58.142516 [DutyScan_Calibration_Flow] k_type=3
7313 16:33:58.160378
7314 16:33:58.160494 ==DQM 0 ==
7315 16:33:58.163854 Final DQM duty delay cell = 0
7316 16:33:58.167244 [0] MAX Duty = 5093%(X100), DQS PI = 18
7317 16:33:58.170816 [0] MIN Duty = 4875%(X100), DQS PI = 10
7318 16:33:58.174176 [0] AVG Duty = 4984%(X100)
7319 16:33:58.174272
7320 16:33:58.174337 ==DQM 1 ==
7321 16:33:58.177094 Final DQM duty delay cell = 0
7322 16:33:58.180656 [0] MAX Duty = 5031%(X100), DQS PI = 52
7323 16:33:58.183887 [0] MIN Duty = 4782%(X100), DQS PI = 20
7324 16:33:58.187319 [0] AVG Duty = 4906%(X100)
7325 16:33:58.187400
7326 16:33:58.190054 CH0 DQM 0 Duty spec in!! Max-Min= 218%
7327 16:33:58.190183
7328 16:33:58.193534 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7329 16:33:58.197269 [DutyScan_Calibration_Flow] ====Done====
7330 16:33:58.197354
7331 16:33:58.199847 [DutyScan_Calibration_Flow] k_type=2
7332 16:33:58.217180
7333 16:33:58.217282 ==DQ 0 ==
7334 16:33:58.219983 Final DQ duty delay cell = -4
7335 16:33:58.223389 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7336 16:33:58.226791 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7337 16:33:58.230099 [-4] AVG Duty = 4953%(X100)
7338 16:33:58.230220
7339 16:33:58.230294 ==DQ 1 ==
7340 16:33:58.233399 Final DQ duty delay cell = 0
7341 16:33:58.236711 [0] MAX Duty = 5125%(X100), DQS PI = 48
7342 16:33:58.240004 [0] MIN Duty = 4969%(X100), DQS PI = 38
7343 16:33:58.243140 [0] AVG Duty = 5047%(X100)
7344 16:33:58.243216
7345 16:33:58.246268 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7346 16:33:58.246341
7347 16:33:58.249852 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7348 16:33:58.253499 [DutyScan_Calibration_Flow] ====Done====
7349 16:33:58.253586 ==
7350 16:33:58.256493 Dram Type= 6, Freq= 0, CH_1, rank 0
7351 16:33:58.260115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7352 16:33:58.260192 ==
7353 16:33:58.262882 [Duty_Offset_Calibration]
7354 16:33:58.262956 B0:-1 B1:1 CA:2
7355 16:33:58.266135
7356 16:33:58.269628 [DutyScan_Calibration_Flow] k_type=0
7357 16:33:58.277787
7358 16:33:58.277898 ==CLK 0==
7359 16:33:58.281258 Final CLK duty delay cell = 0
7360 16:33:58.284118 [0] MAX Duty = 5156%(X100), DQS PI = 22
7361 16:33:58.287726 [0] MIN Duty = 4969%(X100), DQS PI = 62
7362 16:33:58.291308 [0] AVG Duty = 5062%(X100)
7363 16:33:58.291388
7364 16:33:58.294062 CH1 CLK Duty spec in!! Max-Min= 187%
7365 16:33:58.297581 [DutyScan_Calibration_Flow] ====Done====
7366 16:33:58.297671
7367 16:33:58.301032 [DutyScan_Calibration_Flow] k_type=1
7368 16:33:58.317531
7369 16:33:58.317638 ==DQS 0 ==
7370 16:33:58.321140 Final DQS duty delay cell = 0
7371 16:33:58.323831 [0] MAX Duty = 5124%(X100), DQS PI = 18
7372 16:33:58.327465 [0] MIN Duty = 4907%(X100), DQS PI = 10
7373 16:33:58.330864 [0] AVG Duty = 5015%(X100)
7374 16:33:58.330944
7375 16:33:58.331008 ==DQS 1 ==
7376 16:33:58.333493 Final DQS duty delay cell = 0
7377 16:33:58.336850 [0] MAX Duty = 5093%(X100), DQS PI = 26
7378 16:33:58.340468 [0] MIN Duty = 4969%(X100), DQS PI = 54
7379 16:33:58.344458 [0] AVG Duty = 5031%(X100)
7380 16:33:58.344536
7381 16:33:58.347289 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7382 16:33:58.347371
7383 16:33:58.350060 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7384 16:33:58.353449 [DutyScan_Calibration_Flow] ====Done====
7385 16:33:58.353576
7386 16:33:58.356909 [DutyScan_Calibration_Flow] k_type=3
7387 16:33:58.374037
7388 16:33:58.374168 ==DQM 0 ==
7389 16:33:58.377404 Final DQM duty delay cell = 0
7390 16:33:58.380755 [0] MAX Duty = 5218%(X100), DQS PI = 18
7391 16:33:58.384272 [0] MIN Duty = 5031%(X100), DQS PI = 6
7392 16:33:58.387820 [0] AVG Duty = 5124%(X100)
7393 16:33:58.387939
7394 16:33:58.388088 ==DQM 1 ==
7395 16:33:58.390634 Final DQM duty delay cell = 0
7396 16:33:58.394073 [0] MAX Duty = 5156%(X100), DQS PI = 6
7397 16:33:58.397056 [0] MIN Duty = 4969%(X100), DQS PI = 28
7398 16:33:58.400559 [0] AVG Duty = 5062%(X100)
7399 16:33:58.400657
7400 16:33:58.403917 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7401 16:33:58.403999
7402 16:33:58.407354 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7403 16:33:58.410736 [DutyScan_Calibration_Flow] ====Done====
7404 16:33:58.410818
7405 16:33:58.413543 [DutyScan_Calibration_Flow] k_type=2
7406 16:33:58.430858
7407 16:33:58.430963 ==DQ 0 ==
7408 16:33:58.434280 Final DQ duty delay cell = 0
7409 16:33:58.437763 [0] MAX Duty = 5156%(X100), DQS PI = 30
7410 16:33:58.440542 [0] MIN Duty = 4906%(X100), DQS PI = 8
7411 16:33:58.443866 [0] AVG Duty = 5031%(X100)
7412 16:33:58.443950
7413 16:33:58.444016 ==DQ 1 ==
7414 16:33:58.447255 Final DQ duty delay cell = 0
7415 16:33:58.450703 [0] MAX Duty = 5156%(X100), DQS PI = 10
7416 16:33:58.454011 [0] MIN Duty = 4969%(X100), DQS PI = 56
7417 16:33:58.457547 [0] AVG Duty = 5062%(X100)
7418 16:33:58.457634
7419 16:33:58.460523 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7420 16:33:58.460597
7421 16:33:58.464151 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7422 16:33:58.466921 [DutyScan_Calibration_Flow] ====Done====
7423 16:33:58.470381 nWR fixed to 30
7424 16:33:58.473691 [ModeRegInit_LP4] CH0 RK0
7425 16:33:58.473773 [ModeRegInit_LP4] CH0 RK1
7426 16:33:58.476984 [ModeRegInit_LP4] CH1 RK0
7427 16:33:58.480275 [ModeRegInit_LP4] CH1 RK1
7428 16:33:58.480359 match AC timing 5
7429 16:33:58.486631 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7430 16:33:58.490212 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7431 16:33:58.493456 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7432 16:33:58.500141 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7433 16:33:58.503452 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7434 16:33:58.503543 [MiockJmeterHQA]
7435 16:33:58.506434
7436 16:33:58.509941 [DramcMiockJmeter] u1RxGatingPI = 0
7437 16:33:58.510025 0 : 4255, 4029
7438 16:33:58.510122 4 : 4253, 4027
7439 16:33:58.513294 8 : 4252, 4027
7440 16:33:58.513378 12 : 4255, 4029
7441 16:33:58.516171 16 : 4252, 4027
7442 16:33:58.516263 20 : 4253, 4027
7443 16:33:58.519834 24 : 4252, 4027
7444 16:33:58.519920 28 : 4252, 4027
7445 16:33:58.520001 32 : 4253, 4026
7446 16:33:58.523357 36 : 4365, 4140
7447 16:33:58.523443 40 : 4363, 4138
7448 16:33:58.526196 44 : 4253, 4026
7449 16:33:58.526287 48 : 4252, 4027
7450 16:33:58.529746 52 : 4361, 4137
7451 16:33:58.529833 56 : 4253, 4026
7452 16:33:58.533212 60 : 4361, 4137
7453 16:33:58.533298 64 : 4250, 4027
7454 16:33:58.533367 68 : 4250, 4027
7455 16:33:58.536157 72 : 4253, 4027
7456 16:33:58.536260 76 : 4250, 4027
7457 16:33:58.539448 80 : 4250, 4027
7458 16:33:58.539572 84 : 4250, 4026
7459 16:33:58.543057 88 : 4363, 4138
7460 16:33:58.543144 92 : 4363, 539
7461 16:33:58.543214 96 : 4253, 0
7462 16:33:58.545798 100 : 4253, 0
7463 16:33:58.545882 104 : 4250, 0
7464 16:33:58.549410 108 : 4360, 0
7465 16:33:58.549498 112 : 4250, 0
7466 16:33:58.549566 116 : 4250, 0
7467 16:33:58.552810 120 : 4250, 0
7468 16:33:58.552896 124 : 4253, 0
7469 16:33:58.556060 128 : 4361, 0
7470 16:33:58.556152 132 : 4250, 0
7471 16:33:58.556221 136 : 4250, 0
7472 16:33:58.559593 140 : 4255, 0
7473 16:33:58.559678 144 : 4361, 0
7474 16:33:58.562424 148 : 4250, 0
7475 16:33:58.562510 152 : 4255, 0
7476 16:33:58.562580 156 : 4250, 0
7477 16:33:58.565841 160 : 4250, 0
7478 16:33:58.565933 164 : 4252, 0
7479 16:33:58.566006 168 : 4250, 0
7480 16:33:58.569209 172 : 4250, 0
7481 16:33:58.569342 176 : 4252, 0
7482 16:33:58.572379 180 : 4361, 0
7483 16:33:58.572501 184 : 4360, 0
7484 16:33:58.572610 188 : 4250, 0
7485 16:33:58.575996 192 : 4250, 0
7486 16:33:58.576143 196 : 4361, 0
7487 16:33:58.578823 200 : 4360, 0
7488 16:33:58.578940 204 : 4250, 0
7489 16:33:58.579032 208 : 4250, 0
7490 16:33:58.582368 212 : 4250, 0
7491 16:33:58.582483 216 : 4250, 0
7492 16:33:58.585901 220 : 4250, 0
7493 16:33:58.586024 224 : 4250, 78
7494 16:33:58.586132 228 : 4250, 3116
7495 16:33:58.589301 232 : 4363, 4137
7496 16:33:58.589397 236 : 4250, 4027
7497 16:33:58.592087 240 : 4250, 4027
7498 16:33:58.592184 244 : 4252, 4030
7499 16:33:58.595432 248 : 4250, 4026
7500 16:33:58.595510 252 : 4250, 4027
7501 16:33:58.598942 256 : 4361, 4137
7502 16:33:58.599018 260 : 4255, 4029
7503 16:33:58.602195 264 : 4250, 4026
7504 16:33:58.602271 268 : 4255, 4029
7505 16:33:58.605416 272 : 4363, 4140
7506 16:33:58.605492 276 : 4363, 4137
7507 16:33:58.608806 280 : 4250, 4026
7508 16:33:58.608896 284 : 4361, 4137
7509 16:33:58.612193 288 : 4252, 4029
7510 16:33:58.612280 292 : 4250, 4027
7511 16:33:58.612353 296 : 4250, 4027
7512 16:33:58.615547 300 : 4250, 4026
7513 16:33:58.615681 304 : 4250, 4027
7514 16:33:58.618300 308 : 4361, 4137
7515 16:33:58.618405 312 : 4255, 4029
7516 16:33:58.621536 316 : 4250, 4026
7517 16:33:58.621650 320 : 4255, 4029
7518 16:33:58.624890 324 : 4361, 4138
7519 16:33:58.625003 328 : 4363, 4137
7520 16:33:58.628488 332 : 4250, 4026
7521 16:33:58.628659 336 : 4363, 3893
7522 16:33:58.631774 340 : 4252, 2117
7523 16:33:58.631904
7524 16:33:58.632019 MIOCK jitter meter ch=0
7525 16:33:58.632115
7526 16:33:58.635354 1T = (340-92) = 248 dly cells
7527 16:33:58.641624 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7528 16:33:58.641838 ==
7529 16:33:58.645226 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 16:33:58.648624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 16:33:58.648876 ==
7532 16:33:58.655152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7533 16:33:58.658334 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7534 16:33:58.664958 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7535 16:33:58.667733 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7536 16:33:58.678566 [CA 0] Center 43 (12~74) winsize 63
7537 16:33:58.681396 [CA 1] Center 43 (13~73) winsize 61
7538 16:33:58.684891 [CA 2] Center 38 (9~68) winsize 60
7539 16:33:58.688363 [CA 3] Center 38 (9~68) winsize 60
7540 16:33:58.691807 [CA 4] Center 37 (8~66) winsize 59
7541 16:33:58.694618 [CA 5] Center 36 (6~66) winsize 61
7542 16:33:58.694958
7543 16:33:58.698045 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7544 16:33:58.698524
7545 16:33:58.701646 [CATrainingPosCal] consider 1 rank data
7546 16:33:58.704417 u2DelayCellTimex100 = 262/100 ps
7547 16:33:58.711315 CA0 delay=43 (12~74),Diff = 7 PI (26 cell)
7548 16:33:58.714723 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7549 16:33:58.718015 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7550 16:33:58.721290 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7551 16:33:58.724060 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7552 16:33:58.727372 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7553 16:33:58.727709
7554 16:33:58.730678 CA PerBit enable=1, Macro0, CA PI delay=36
7555 16:33:58.731010
7556 16:33:58.734502 [CBTSetCACLKResult] CA Dly = 36
7557 16:33:58.737548 CS Dly: 11 (0~42)
7558 16:33:58.741021 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7559 16:33:58.743917 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7560 16:33:58.744115 ==
7561 16:33:58.747492 Dram Type= 6, Freq= 0, CH_0, rank 1
7562 16:33:58.753852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7563 16:33:58.754053 ==
7564 16:33:58.757147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7565 16:33:58.763730 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7566 16:33:58.767274 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7567 16:33:58.774004 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7568 16:33:58.781811 [CA 0] Center 42 (12~73) winsize 62
7569 16:33:58.784440 [CA 1] Center 43 (13~73) winsize 61
7570 16:33:58.788028 [CA 2] Center 37 (8~67) winsize 60
7571 16:33:58.791430 [CA 3] Center 37 (7~67) winsize 61
7572 16:33:58.794815 [CA 4] Center 36 (6~66) winsize 61
7573 16:33:58.798415 [CA 5] Center 35 (5~65) winsize 61
7574 16:33:58.798628
7575 16:33:58.801158 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7576 16:33:58.801397
7577 16:33:58.804611 [CATrainingPosCal] consider 2 rank data
7578 16:33:58.808128 u2DelayCellTimex100 = 262/100 ps
7579 16:33:58.814249 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7580 16:33:58.817770 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7581 16:33:58.821228 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7582 16:33:58.824565 CA3 delay=38 (9~67),Diff = 3 PI (11 cell)
7583 16:33:58.827946 CA4 delay=37 (8~66),Diff = 2 PI (7 cell)
7584 16:33:58.831481 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7585 16:33:58.831844
7586 16:33:58.834113 CA PerBit enable=1, Macro0, CA PI delay=35
7587 16:33:58.834578
7588 16:33:58.837490 [CBTSetCACLKResult] CA Dly = 35
7589 16:33:58.840793 CS Dly: 11 (0~43)
7590 16:33:58.844017 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7591 16:33:58.847520 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7592 16:33:58.847981
7593 16:33:58.850800 ----->DramcWriteLeveling(PI) begin...
7594 16:33:58.853885 ==
7595 16:33:58.857403 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 16:33:58.860383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 16:33:58.860811 ==
7598 16:33:58.863921 Write leveling (Byte 0): 36 => 36
7599 16:33:58.867495 Write leveling (Byte 1): 26 => 26
7600 16:33:58.870273 DramcWriteLeveling(PI) end<-----
7601 16:33:58.870640
7602 16:33:58.870978 ==
7603 16:33:58.873806 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 16:33:58.877290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 16:33:58.877702 ==
7606 16:33:58.880178 [Gating] SW mode calibration
7607 16:33:58.887358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7608 16:33:58.893797 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7609 16:33:58.897014 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 16:33:58.900348 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 16:33:58.906502 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 16:33:58.910117 1 4 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
7613 16:33:58.913684 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7614 16:33:58.920316 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7615 16:33:58.923014 1 4 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7616 16:33:58.927127 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 16:33:58.933294 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 16:33:58.936173 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 16:33:58.939551 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7620 16:33:58.946567 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7621 16:33:58.949778 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7622 16:33:58.953202 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7623 16:33:58.959732 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
7624 16:33:58.962646 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 16:33:58.966352 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 16:33:58.972754 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 16:33:58.976338 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 16:33:58.979301 1 6 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7629 16:33:58.986111 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7630 16:33:58.989023 1 6 20 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7631 16:33:58.992554 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7632 16:33:58.999278 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 16:33:59.002717 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 16:33:59.005296 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 16:33:59.012487 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7636 16:33:59.015700 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7637 16:33:59.018674 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7638 16:33:59.025742 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7639 16:33:59.028609 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 16:33:59.032027 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 16:33:59.038960 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 16:33:59.041607 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 16:33:59.045217 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 16:33:59.052220 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 16:33:59.055004 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 16:33:59.058315 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 16:33:59.065119 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 16:33:59.068096 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 16:33:59.071895 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 16:33:59.077596 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 16:33:59.081349 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 16:33:59.084809 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7653 16:33:59.091304 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7654 16:33:59.091471 Total UI for P1: 0, mck2ui 16
7655 16:33:59.097992 best dqsien dly found for B0: ( 1, 9, 12)
7656 16:33:59.100928 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7657 16:33:59.104090 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 16:33:59.107483 Total UI for P1: 0, mck2ui 16
7659 16:33:59.110945 best dqsien dly found for B1: ( 1, 9, 20)
7660 16:33:59.114551 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7661 16:33:59.117257 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7662 16:33:59.117372
7663 16:33:59.123844 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7664 16:33:59.127233 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7665 16:33:59.130088 [Gating] SW calibration Done
7666 16:33:59.130268 ==
7667 16:33:59.133441 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 16:33:59.137088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 16:33:59.137298 ==
7670 16:33:59.137429 RX Vref Scan: 0
7671 16:33:59.140363
7672 16:33:59.140602 RX Vref 0 -> 0, step: 1
7673 16:33:59.140810
7674 16:33:59.143886 RX Delay 0 -> 252, step: 8
7675 16:33:59.147126 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7676 16:33:59.150294 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7677 16:33:59.157015 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7678 16:33:59.159928 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7679 16:33:59.163394 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7680 16:33:59.166792 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7681 16:33:59.170058 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7682 16:33:59.176447 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7683 16:33:59.180016 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7684 16:33:59.182724 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7685 16:33:59.186309 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7686 16:33:59.189823 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7687 16:33:59.196147 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7688 16:33:59.199713 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7689 16:33:59.203266 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7690 16:33:59.206090 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7691 16:33:59.209524 ==
7692 16:33:59.209858 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 16:33:59.215957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 16:33:59.216287 ==
7695 16:33:59.216553 DQS Delay:
7696 16:33:59.219492 DQS0 = 0, DQS1 = 0
7697 16:33:59.219811 DQM Delay:
7698 16:33:59.222533 DQM0 = 135, DQM1 = 126
7699 16:33:59.222854 DQ Delay:
7700 16:33:59.225918 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7701 16:33:59.229234 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =143
7702 16:33:59.232204 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7703 16:33:59.235748 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7704 16:33:59.236051
7705 16:33:59.236288
7706 16:33:59.238926 ==
7707 16:33:59.239289 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 16:33:59.245373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 16:33:59.245676 ==
7710 16:33:59.245921
7711 16:33:59.246224
7712 16:33:59.248428 TX Vref Scan disable
7713 16:33:59.248800 == TX Byte 0 ==
7714 16:33:59.251874 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7715 16:33:59.259023 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7716 16:33:59.259380 == TX Byte 1 ==
7717 16:33:59.262253 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7718 16:33:59.268582 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7719 16:33:59.268997 ==
7720 16:33:59.272020 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 16:33:59.274755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 16:33:59.275070 ==
7723 16:33:59.289149
7724 16:33:59.292055 TX Vref early break, caculate TX vref
7725 16:33:59.295572 TX Vref=16, minBit 1, minWin=22, winSum=370
7726 16:33:59.298974 TX Vref=18, minBit 1, minWin=23, winSum=378
7727 16:33:59.301819 TX Vref=20, minBit 1, minWin=24, winSum=391
7728 16:33:59.305293 TX Vref=22, minBit 4, minWin=24, winSum=400
7729 16:33:59.308846 TX Vref=24, minBit 6, minWin=24, winSum=404
7730 16:33:59.315038 TX Vref=26, minBit 2, minWin=25, winSum=413
7731 16:33:59.318546 TX Vref=28, minBit 4, minWin=24, winSum=415
7732 16:33:59.321518 TX Vref=30, minBit 3, minWin=25, winSum=411
7733 16:33:59.325134 TX Vref=32, minBit 0, minWin=24, winSum=398
7734 16:33:59.328442 TX Vref=34, minBit 4, minWin=23, winSum=387
7735 16:33:59.335018 [TxChooseVref] Worse bit 2, Min win 25, Win sum 413, Final Vref 26
7736 16:33:59.335132
7737 16:33:59.338339 Final TX Range 0 Vref 26
7738 16:33:59.338461
7739 16:33:59.338564 ==
7740 16:33:59.341678 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 16:33:59.344604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 16:33:59.344733 ==
7743 16:33:59.344844
7744 16:33:59.348147
7745 16:33:59.348311 TX Vref Scan disable
7746 16:33:59.354975 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7747 16:33:59.355163 == TX Byte 0 ==
7748 16:33:59.357686 u2DelayCellOfst[0]=14 cells (4 PI)
7749 16:33:59.361014 u2DelayCellOfst[1]=18 cells (5 PI)
7750 16:33:59.364782 u2DelayCellOfst[2]=14 cells (4 PI)
7751 16:33:59.368014 u2DelayCellOfst[3]=14 cells (4 PI)
7752 16:33:59.371226 u2DelayCellOfst[4]=11 cells (3 PI)
7753 16:33:59.374578 u2DelayCellOfst[5]=0 cells (0 PI)
7754 16:33:59.377500 u2DelayCellOfst[6]=22 cells (6 PI)
7755 16:33:59.380744 u2DelayCellOfst[7]=18 cells (5 PI)
7756 16:33:59.384330 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7757 16:33:59.387405 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7758 16:33:59.390837 == TX Byte 1 ==
7759 16:33:59.394337 u2DelayCellOfst[8]=0 cells (0 PI)
7760 16:33:59.397766 u2DelayCellOfst[9]=0 cells (0 PI)
7761 16:33:59.400368 u2DelayCellOfst[10]=3 cells (1 PI)
7762 16:33:59.403834 u2DelayCellOfst[11]=0 cells (0 PI)
7763 16:33:59.407529 u2DelayCellOfst[12]=11 cells (3 PI)
7764 16:33:59.410258 u2DelayCellOfst[13]=7 cells (2 PI)
7765 16:33:59.413708 u2DelayCellOfst[14]=11 cells (3 PI)
7766 16:33:59.417168 u2DelayCellOfst[15]=7 cells (2 PI)
7767 16:33:59.420552 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7768 16:33:59.423875 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7769 16:33:59.426833 DramC Write-DBI on
7770 16:33:59.427365 ==
7771 16:33:59.430156 Dram Type= 6, Freq= 0, CH_0, rank 0
7772 16:33:59.433639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7773 16:33:59.434211 ==
7774 16:33:59.434621
7775 16:33:59.435016
7776 16:33:59.437117 TX Vref Scan disable
7777 16:33:59.440462 == TX Byte 0 ==
7778 16:33:59.443289 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7779 16:33:59.443678 == TX Byte 1 ==
7780 16:33:59.450368 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7781 16:33:59.450760 DramC Write-DBI off
7782 16:33:59.450925
7783 16:33:59.450987 [DATLAT]
7784 16:33:59.452836 Freq=1600, CH0 RK0
7785 16:33:59.452919
7786 16:33:59.456275 DATLAT Default: 0xf
7787 16:33:59.456358 0, 0xFFFF, sum = 0
7788 16:33:59.459884 1, 0xFFFF, sum = 0
7789 16:33:59.459969 2, 0xFFFF, sum = 0
7790 16:33:59.463181 3, 0xFFFF, sum = 0
7791 16:33:59.463267 4, 0xFFFF, sum = 0
7792 16:33:59.466015 5, 0xFFFF, sum = 0
7793 16:33:59.466101 6, 0xFFFF, sum = 0
7794 16:33:59.469905 7, 0xFFFF, sum = 0
7795 16:33:59.469982 8, 0xFFFF, sum = 0
7796 16:33:59.472740 9, 0xFFFF, sum = 0
7797 16:33:59.472825 10, 0xFFFF, sum = 0
7798 16:33:59.475904 11, 0xFFFF, sum = 0
7799 16:33:59.475989 12, 0xFFFF, sum = 0
7800 16:33:59.479100 13, 0xFFFF, sum = 0
7801 16:33:59.479214 14, 0x0, sum = 1
7802 16:33:59.482427 15, 0x0, sum = 2
7803 16:33:59.482552 16, 0x0, sum = 3
7804 16:33:59.485904 17, 0x0, sum = 4
7805 16:33:59.485989 best_step = 15
7806 16:33:59.486055
7807 16:33:59.486115 ==
7808 16:33:59.489240 Dram Type= 6, Freq= 0, CH_0, rank 0
7809 16:33:59.496206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7810 16:33:59.496291 ==
7811 16:33:59.496378 RX Vref Scan: 1
7812 16:33:59.496457
7813 16:33:59.499482 Set Vref Range= 24 -> 127
7814 16:33:59.499566
7815 16:33:59.502733 RX Vref 24 -> 127, step: 1
7816 16:33:59.502816
7817 16:33:59.505978 RX Delay 11 -> 252, step: 4
7818 16:33:59.506061
7819 16:33:59.509104 Set Vref, RX VrefLevel [Byte0]: 24
7820 16:33:59.512199 [Byte1]: 24
7821 16:33:59.512284
7822 16:33:59.515666 Set Vref, RX VrefLevel [Byte0]: 25
7823 16:33:59.518776 [Byte1]: 25
7824 16:33:59.518895
7825 16:33:59.522307 Set Vref, RX VrefLevel [Byte0]: 26
7826 16:33:59.525132 [Byte1]: 26
7827 16:33:59.528709
7828 16:33:59.528803 Set Vref, RX VrefLevel [Byte0]: 27
7829 16:33:59.532193 [Byte1]: 27
7830 16:33:59.536427
7831 16:33:59.536509 Set Vref, RX VrefLevel [Byte0]: 28
7832 16:33:59.539944 [Byte1]: 28
7833 16:33:59.544216
7834 16:33:59.544311 Set Vref, RX VrefLevel [Byte0]: 29
7835 16:33:59.547591 [Byte1]: 29
7836 16:33:59.551760
7837 16:33:59.551851 Set Vref, RX VrefLevel [Byte0]: 30
7838 16:33:59.555315 [Byte1]: 30
7839 16:33:59.559581
7840 16:33:59.559661 Set Vref, RX VrefLevel [Byte0]: 31
7841 16:33:59.562436 [Byte1]: 31
7842 16:33:59.566774
7843 16:33:59.566856 Set Vref, RX VrefLevel [Byte0]: 32
7844 16:33:59.570254 [Byte1]: 32
7845 16:33:59.574280
7846 16:33:59.574390 Set Vref, RX VrefLevel [Byte0]: 33
7847 16:33:59.578013 [Byte1]: 33
7848 16:33:59.582005
7849 16:33:59.582107 Set Vref, RX VrefLevel [Byte0]: 34
7850 16:33:59.585219 [Byte1]: 34
7851 16:33:59.589816
7852 16:33:59.589930 Set Vref, RX VrefLevel [Byte0]: 35
7853 16:33:59.593027 [Byte1]: 35
7854 16:33:59.597804
7855 16:33:59.597911 Set Vref, RX VrefLevel [Byte0]: 36
7856 16:33:59.600444 [Byte1]: 36
7857 16:33:59.604719
7858 16:33:59.604824 Set Vref, RX VrefLevel [Byte0]: 37
7859 16:33:59.608110 [Byte1]: 37
7860 16:33:59.612880
7861 16:33:59.612989 Set Vref, RX VrefLevel [Byte0]: 38
7862 16:33:59.615623 [Byte1]: 38
7863 16:33:59.620438
7864 16:33:59.620546 Set Vref, RX VrefLevel [Byte0]: 39
7865 16:33:59.623655 [Byte1]: 39
7866 16:33:59.627526
7867 16:33:59.627630 Set Vref, RX VrefLevel [Byte0]: 40
7868 16:33:59.631202 [Byte1]: 40
7869 16:33:59.635708
7870 16:33:59.635822 Set Vref, RX VrefLevel [Byte0]: 41
7871 16:33:59.638542 [Byte1]: 41
7872 16:33:59.642868
7873 16:33:59.642974 Set Vref, RX VrefLevel [Byte0]: 42
7874 16:33:59.646070 [Byte1]: 42
7875 16:33:59.650373
7876 16:33:59.650447 Set Vref, RX VrefLevel [Byte0]: 43
7877 16:33:59.653895 [Byte1]: 43
7878 16:33:59.658129
7879 16:33:59.658255 Set Vref, RX VrefLevel [Byte0]: 44
7880 16:33:59.661798 [Byte1]: 44
7881 16:33:59.665929
7882 16:33:59.666002 Set Vref, RX VrefLevel [Byte0]: 45
7883 16:33:59.669440 [Byte1]: 45
7884 16:33:59.673770
7885 16:33:59.673872 Set Vref, RX VrefLevel [Byte0]: 46
7886 16:33:59.676578 [Byte1]: 46
7887 16:33:59.681264
7888 16:33:59.681365 Set Vref, RX VrefLevel [Byte0]: 47
7889 16:33:59.684067 [Byte1]: 47
7890 16:33:59.688849
7891 16:33:59.688930 Set Vref, RX VrefLevel [Byte0]: 48
7892 16:33:59.692207 [Byte1]: 48
7893 16:33:59.696288
7894 16:33:59.696388 Set Vref, RX VrefLevel [Byte0]: 49
7895 16:33:59.699579 [Byte1]: 49
7896 16:33:59.704139
7897 16:33:59.704245 Set Vref, RX VrefLevel [Byte0]: 50
7898 16:33:59.706892 [Byte1]: 50
7899 16:33:59.711516
7900 16:33:59.711620 Set Vref, RX VrefLevel [Byte0]: 51
7901 16:33:59.715176 [Byte1]: 51
7902 16:33:59.718823
7903 16:33:59.718929 Set Vref, RX VrefLevel [Byte0]: 52
7904 16:33:59.722389 [Byte1]: 52
7905 16:33:59.726575
7906 16:33:59.726651 Set Vref, RX VrefLevel [Byte0]: 53
7907 16:33:59.730062 [Byte1]: 53
7908 16:33:59.734134
7909 16:33:59.734249 Set Vref, RX VrefLevel [Byte0]: 54
7910 16:33:59.737565 [Byte1]: 54
7911 16:33:59.742094
7912 16:33:59.742232 Set Vref, RX VrefLevel [Byte0]: 55
7913 16:33:59.745222 [Byte1]: 55
7914 16:33:59.749735
7915 16:33:59.749846 Set Vref, RX VrefLevel [Byte0]: 56
7916 16:33:59.752569 [Byte1]: 56
7917 16:33:59.757491
7918 16:33:59.757577 Set Vref, RX VrefLevel [Byte0]: 57
7919 16:33:59.760335 [Byte1]: 57
7920 16:33:59.764946
7921 16:33:59.765048 Set Vref, RX VrefLevel [Byte0]: 58
7922 16:33:59.768312 [Byte1]: 58
7923 16:33:59.772455
7924 16:33:59.772569 Set Vref, RX VrefLevel [Byte0]: 59
7925 16:33:59.776141 [Byte1]: 59
7926 16:33:59.780301
7927 16:33:59.780410 Set Vref, RX VrefLevel [Byte0]: 60
7928 16:33:59.783702 [Byte1]: 60
7929 16:33:59.787800
7930 16:33:59.787903 Set Vref, RX VrefLevel [Byte0]: 61
7931 16:33:59.791291 [Byte1]: 61
7932 16:33:59.795389
7933 16:33:59.795535 Set Vref, RX VrefLevel [Byte0]: 62
7934 16:33:59.798817 [Byte1]: 62
7935 16:33:59.802955
7936 16:33:59.803065 Set Vref, RX VrefLevel [Byte0]: 63
7937 16:33:59.806157 [Byte1]: 63
7938 16:33:59.810153
7939 16:33:59.810291 Set Vref, RX VrefLevel [Byte0]: 64
7940 16:33:59.814123 [Byte1]: 64
7941 16:33:59.818323
7942 16:33:59.818432 Set Vref, RX VrefLevel [Byte0]: 65
7943 16:33:59.821060 [Byte1]: 65
7944 16:33:59.826077
7945 16:33:59.826230 Set Vref, RX VrefLevel [Byte0]: 66
7946 16:33:59.829013 [Byte1]: 66
7947 16:33:59.833056
7948 16:33:59.833183 Set Vref, RX VrefLevel [Byte0]: 67
7949 16:33:59.836483 [Byte1]: 67
7950 16:33:59.840623
7951 16:33:59.840753 Set Vref, RX VrefLevel [Byte0]: 68
7952 16:33:59.844155 [Byte1]: 68
7953 16:33:59.848664
7954 16:33:59.848782 Set Vref, RX VrefLevel [Byte0]: 69
7955 16:33:59.851966 [Byte1]: 69
7956 16:33:59.856260
7957 16:33:59.856367 Set Vref, RX VrefLevel [Byte0]: 70
7958 16:33:59.859452 [Byte1]: 70
7959 16:33:59.863506
7960 16:33:59.863616 Set Vref, RX VrefLevel [Byte0]: 71
7961 16:33:59.867045 [Byte1]: 71
7962 16:33:59.871078
7963 16:33:59.871193 Set Vref, RX VrefLevel [Byte0]: 72
7964 16:33:59.874520 [Byte1]: 72
7965 16:33:59.879398
7966 16:33:59.879512 Set Vref, RX VrefLevel [Byte0]: 73
7967 16:33:59.882187 [Byte1]: 73
7968 16:33:59.886439
7969 16:33:59.886522 Set Vref, RX VrefLevel [Byte0]: 74
7970 16:33:59.889886 [Byte1]: 74
7971 16:33:59.894074
7972 16:33:59.894191 Set Vref, RX VrefLevel [Byte0]: 75
7973 16:33:59.897528 [Byte1]: 75
7974 16:33:59.901760
7975 16:33:59.901918 Set Vref, RX VrefLevel [Byte0]: 76
7976 16:33:59.905087 [Byte1]: 76
7977 16:33:59.909169
7978 16:33:59.909256 Set Vref, RX VrefLevel [Byte0]: 77
7979 16:33:59.912514 [Byte1]: 77
7980 16:33:59.917138
7981 16:33:59.917266 Set Vref, RX VrefLevel [Byte0]: 78
7982 16:33:59.920408 [Byte1]: 78
7983 16:33:59.924860
7984 16:33:59.925004 Final RX Vref Byte 0 = 65 to rank0
7985 16:33:59.928199 Final RX Vref Byte 1 = 56 to rank0
7986 16:33:59.931527 Final RX Vref Byte 0 = 65 to rank1
7987 16:33:59.934407 Final RX Vref Byte 1 = 56 to rank1==
7988 16:33:59.937910 Dram Type= 6, Freq= 0, CH_0, rank 0
7989 16:33:59.944180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 16:33:59.944305 ==
7991 16:33:59.944408 DQS Delay:
7992 16:33:59.947830 DQS0 = 0, DQS1 = 0
7993 16:33:59.947943 DQM Delay:
7994 16:33:59.948038 DQM0 = 133, DQM1 = 122
7995 16:33:59.951327 DQ Delay:
7996 16:33:59.954115 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
7997 16:33:59.957782 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
7998 16:33:59.961193 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =116
7999 16:33:59.963898 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8000 16:33:59.964014
8001 16:33:59.964112
8002 16:33:59.964203
8003 16:33:59.967209 [DramC_TX_OE_Calibration] TA2
8004 16:33:59.970509 Original DQ_B0 (3 6) =30, OEN = 27
8005 16:33:59.973825 Original DQ_B1 (3 6) =30, OEN = 27
8006 16:33:59.976867 24, 0x0, End_B0=24 End_B1=24
8007 16:33:59.980818 25, 0x0, End_B0=25 End_B1=25
8008 16:33:59.980941 26, 0x0, End_B0=26 End_B1=26
8009 16:33:59.983718 27, 0x0, End_B0=27 End_B1=27
8010 16:33:59.986676 28, 0x0, End_B0=28 End_B1=28
8011 16:33:59.990221 29, 0x0, End_B0=29 End_B1=29
8012 16:33:59.993707 30, 0x0, End_B0=30 End_B1=30
8013 16:33:59.993832 31, 0x4141, End_B0=30 End_B1=30
8014 16:33:59.997071 Byte0 end_step=30 best_step=27
8015 16:33:59.999900 Byte1 end_step=30 best_step=27
8016 16:34:00.003547 Byte0 TX OE(2T, 0.5T) = (3, 3)
8017 16:34:00.006389 Byte1 TX OE(2T, 0.5T) = (3, 3)
8018 16:34:00.006489
8019 16:34:00.006591
8020 16:34:00.013342 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
8021 16:34:00.016820 CH0 RK0: MR19=303, MR18=1F10
8022 16:34:00.023247 CH0_RK0: MR19=0x303, MR18=0x1F10, DQSOSC=394, MR23=63, INC=23, DEC=15
8023 16:34:00.023400
8024 16:34:00.026701 ----->DramcWriteLeveling(PI) begin...
8025 16:34:00.026818 ==
8026 16:34:00.029907 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 16:34:00.033274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 16:34:00.036398 ==
8029 16:34:00.036514 Write leveling (Byte 0): 36 => 36
8030 16:34:00.039758 Write leveling (Byte 1): 29 => 29
8031 16:34:00.042866 DramcWriteLeveling(PI) end<-----
8032 16:34:00.042945
8033 16:34:00.043047 ==
8034 16:34:00.046045 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 16:34:00.053257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 16:34:00.053372 ==
8037 16:34:00.053461 [Gating] SW mode calibration
8038 16:34:00.062501 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8039 16:34:00.066116 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8040 16:34:00.072390 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 16:34:00.075961 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 16:34:00.079096 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 16:34:00.085794 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
8044 16:34:00.089109 1 4 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8045 16:34:00.092390 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (1 1) (1 1)
8046 16:34:00.099074 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 16:34:00.102260 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 16:34:00.105774 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 16:34:00.111998 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 16:34:00.115427 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 16:34:00.118887 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8052 16:34:00.125336 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 1)
8053 16:34:00.128898 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
8054 16:34:00.131773 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 16:34:00.138534 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 16:34:00.142022 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 16:34:00.144749 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 16:34:00.152012 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 16:34:00.155229 1 6 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8060 16:34:00.158131 1 6 16 | B1->B0 | 2c2c 4444 | 0 0 | (0 0) (0 0)
8061 16:34:00.165143 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8062 16:34:00.168605 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 16:34:00.171318 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 16:34:00.178306 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 16:34:00.181769 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 16:34:00.184519 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 16:34:00.191388 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8068 16:34:00.194954 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8069 16:34:00.198128 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8070 16:34:00.204900 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8071 16:34:00.208210 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 16:34:00.210928 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 16:34:00.217792 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 16:34:00.221119 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 16:34:00.224805 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 16:34:00.231209 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 16:34:00.234126 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 16:34:00.237642 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 16:34:00.243939 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 16:34:00.247159 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 16:34:00.250634 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 16:34:00.257729 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 16:34:00.260500 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8084 16:34:00.263828 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8085 16:34:00.270787 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8086 16:34:00.270871 Total UI for P1: 0, mck2ui 16
8087 16:34:00.277117 best dqsien dly found for B0: ( 1, 9, 14)
8088 16:34:00.280460 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 16:34:00.283923 Total UI for P1: 0, mck2ui 16
8090 16:34:00.287289 best dqsien dly found for B1: ( 1, 9, 18)
8091 16:34:00.289969 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8092 16:34:00.293388 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8093 16:34:00.293528
8094 16:34:00.296736 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8095 16:34:00.300220 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8096 16:34:00.303621 [Gating] SW calibration Done
8097 16:34:00.303725 ==
8098 16:34:00.307031 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 16:34:00.310336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 16:34:00.313537 ==
8101 16:34:00.313647 RX Vref Scan: 0
8102 16:34:00.313745
8103 16:34:00.316947 RX Vref 0 -> 0, step: 1
8104 16:34:00.317053
8105 16:34:00.317144 RX Delay 0 -> 252, step: 8
8106 16:34:00.323344 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8107 16:34:00.326812 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8108 16:34:00.330191 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8109 16:34:00.332990 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8110 16:34:00.336553 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8111 16:34:00.343025 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8112 16:34:00.346580 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8113 16:34:00.349852 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8114 16:34:00.353140 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8115 16:34:00.359286 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8116 16:34:00.362933 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8117 16:34:00.366441 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8118 16:34:00.369305 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8119 16:34:00.372819 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8120 16:34:00.379053 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8121 16:34:00.382568 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8122 16:34:00.382655 ==
8123 16:34:00.385700 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 16:34:00.389507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 16:34:00.389612 ==
8126 16:34:00.392466 DQS Delay:
8127 16:34:00.392541 DQS0 = 0, DQS1 = 0
8128 16:34:00.392606 DQM Delay:
8129 16:34:00.395516 DQM0 = 132, DQM1 = 128
8130 16:34:00.395592 DQ Delay:
8131 16:34:00.399182 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8132 16:34:00.402473 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8133 16:34:00.409222 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8134 16:34:00.412053 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8135 16:34:00.412138
8136 16:34:00.412204
8137 16:34:00.412264 ==
8138 16:34:00.415509 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 16:34:00.419055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 16:34:00.419163 ==
8141 16:34:00.419259
8142 16:34:00.419348
8143 16:34:00.422422 TX Vref Scan disable
8144 16:34:00.425760 == TX Byte 0 ==
8145 16:34:00.428566 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8146 16:34:00.431984 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8147 16:34:00.435524 == TX Byte 1 ==
8148 16:34:00.438458 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8149 16:34:00.442051 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8150 16:34:00.442133 ==
8151 16:34:00.444989 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 16:34:00.448574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 16:34:00.452085 ==
8154 16:34:00.464076
8155 16:34:00.466954 TX Vref early break, caculate TX vref
8156 16:34:00.470401 TX Vref=16, minBit 3, minWin=22, winSum=377
8157 16:34:00.473961 TX Vref=18, minBit 0, minWin=23, winSum=386
8158 16:34:00.476727 TX Vref=20, minBit 2, minWin=23, winSum=395
8159 16:34:00.480369 TX Vref=22, minBit 0, minWin=24, winSum=407
8160 16:34:00.483893 TX Vref=24, minBit 1, minWin=24, winSum=412
8161 16:34:00.490048 TX Vref=26, minBit 3, minWin=24, winSum=418
8162 16:34:00.493502 TX Vref=28, minBit 1, minWin=24, winSum=417
8163 16:34:00.496991 TX Vref=30, minBit 0, minWin=24, winSum=404
8164 16:34:00.499729 TX Vref=32, minBit 7, minWin=23, winSum=399
8165 16:34:00.503020 TX Vref=34, minBit 0, minWin=23, winSum=389
8166 16:34:00.510277 [TxChooseVref] Worse bit 3, Min win 24, Win sum 418, Final Vref 26
8167 16:34:00.510406
8168 16:34:00.513628 Final TX Range 0 Vref 26
8169 16:34:00.513712
8170 16:34:00.513778 ==
8171 16:34:00.516458 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 16:34:00.519757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 16:34:00.519861 ==
8174 16:34:00.519959
8175 16:34:00.520052
8176 16:34:00.523384 TX Vref Scan disable
8177 16:34:00.529752 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8178 16:34:00.529838 == TX Byte 0 ==
8179 16:34:00.533121 u2DelayCellOfst[0]=11 cells (3 PI)
8180 16:34:00.536187 u2DelayCellOfst[1]=14 cells (4 PI)
8181 16:34:00.539385 u2DelayCellOfst[2]=11 cells (3 PI)
8182 16:34:00.542853 u2DelayCellOfst[3]=14 cells (4 PI)
8183 16:34:00.546202 u2DelayCellOfst[4]=7 cells (2 PI)
8184 16:34:00.549733 u2DelayCellOfst[5]=0 cells (0 PI)
8185 16:34:00.553073 u2DelayCellOfst[6]=14 cells (4 PI)
8186 16:34:00.555873 u2DelayCellOfst[7]=18 cells (5 PI)
8187 16:34:00.559313 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8188 16:34:00.562764 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8189 16:34:00.566197 == TX Byte 1 ==
8190 16:34:00.569367 u2DelayCellOfst[8]=0 cells (0 PI)
8191 16:34:00.572823 u2DelayCellOfst[9]=3 cells (1 PI)
8192 16:34:00.575698 u2DelayCellOfst[10]=11 cells (3 PI)
8193 16:34:00.575781 u2DelayCellOfst[11]=3 cells (1 PI)
8194 16:34:00.579232 u2DelayCellOfst[12]=14 cells (4 PI)
8195 16:34:00.582695 u2DelayCellOfst[13]=14 cells (4 PI)
8196 16:34:00.586153 u2DelayCellOfst[14]=18 cells (5 PI)
8197 16:34:00.588943 u2DelayCellOfst[15]=11 cells (3 PI)
8198 16:34:00.595953 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8199 16:34:00.599372 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8200 16:34:00.599455 DramC Write-DBI on
8201 16:34:00.599522 ==
8202 16:34:00.602109 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 16:34:00.609024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 16:34:00.609107 ==
8205 16:34:00.609172
8206 16:34:00.609233
8207 16:34:00.612469 TX Vref Scan disable
8208 16:34:00.612610 == TX Byte 0 ==
8209 16:34:00.619204 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8210 16:34:00.619336 == TX Byte 1 ==
8211 16:34:00.621986 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8212 16:34:00.625614 DramC Write-DBI off
8213 16:34:00.625696
8214 16:34:00.625761 [DATLAT]
8215 16:34:00.628652 Freq=1600, CH0 RK1
8216 16:34:00.628791
8217 16:34:00.628950 DATLAT Default: 0xf
8218 16:34:00.631914 0, 0xFFFF, sum = 0
8219 16:34:00.632072 1, 0xFFFF, sum = 0
8220 16:34:00.635156 2, 0xFFFF, sum = 0
8221 16:34:00.635279 3, 0xFFFF, sum = 0
8222 16:34:00.638402 4, 0xFFFF, sum = 0
8223 16:34:00.638546 5, 0xFFFF, sum = 0
8224 16:34:00.641787 6, 0xFFFF, sum = 0
8225 16:34:00.645300 7, 0xFFFF, sum = 0
8226 16:34:00.645377 8, 0xFFFF, sum = 0
8227 16:34:00.648339 9, 0xFFFF, sum = 0
8228 16:34:00.648446 10, 0xFFFF, sum = 0
8229 16:34:00.651622 11, 0xFFFF, sum = 0
8230 16:34:00.651726 12, 0xFFFF, sum = 0
8231 16:34:00.655307 13, 0xFFFF, sum = 0
8232 16:34:00.655412 14, 0x0, sum = 1
8233 16:34:00.658408 15, 0x0, sum = 2
8234 16:34:00.658485 16, 0x0, sum = 3
8235 16:34:00.661786 17, 0x0, sum = 4
8236 16:34:00.661891 best_step = 15
8237 16:34:00.662030
8238 16:34:00.662123 ==
8239 16:34:00.664876 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 16:34:00.668450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 16:34:00.671236 ==
8242 16:34:00.671338 RX Vref Scan: 0
8243 16:34:00.671427
8244 16:34:00.674691 RX Vref 0 -> 0, step: 1
8245 16:34:00.674793
8246 16:34:00.677993 RX Delay 11 -> 252, step: 4
8247 16:34:00.681528 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8248 16:34:00.684856 iDelay=191, Bit 1, Center 134 (79 ~ 190) 112
8249 16:34:00.687820 iDelay=191, Bit 2, Center 126 (75 ~ 178) 104
8250 16:34:00.694773 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8251 16:34:00.697588 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8252 16:34:00.701171 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8253 16:34:00.704772 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8254 16:34:00.707597 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8255 16:34:00.714521 iDelay=191, Bit 8, Center 116 (63 ~ 170) 108
8256 16:34:00.717229 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8257 16:34:00.720791 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8258 16:34:00.724128 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8259 16:34:00.727188 iDelay=191, Bit 12, Center 132 (79 ~ 186) 108
8260 16:34:00.734158 iDelay=191, Bit 13, Center 132 (79 ~ 186) 108
8261 16:34:00.737557 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8262 16:34:00.741039 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8263 16:34:00.741147 ==
8264 16:34:00.743826 Dram Type= 6, Freq= 0, CH_0, rank 1
8265 16:34:00.747728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 16:34:00.750965 ==
8267 16:34:00.751111 DQS Delay:
8268 16:34:00.751220 DQS0 = 0, DQS1 = 0
8269 16:34:00.753833 DQM Delay:
8270 16:34:00.753977 DQM0 = 129, DQM1 = 125
8271 16:34:00.757271 DQ Delay:
8272 16:34:00.760505 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =126
8273 16:34:00.763788 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
8274 16:34:00.766773 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8275 16:34:00.770152 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8276 16:34:00.770274
8277 16:34:00.770339
8278 16:34:00.770399
8279 16:34:00.773920 [DramC_TX_OE_Calibration] TA2
8280 16:34:00.777157 Original DQ_B0 (3 6) =30, OEN = 27
8281 16:34:00.780286 Original DQ_B1 (3 6) =30, OEN = 27
8282 16:34:00.783544 24, 0x0, End_B0=24 End_B1=24
8283 16:34:00.783647 25, 0x0, End_B0=25 End_B1=25
8284 16:34:00.786997 26, 0x0, End_B0=26 End_B1=26
8285 16:34:00.790392 27, 0x0, End_B0=27 End_B1=27
8286 16:34:00.793139 28, 0x0, End_B0=28 End_B1=28
8287 16:34:00.796578 29, 0x0, End_B0=29 End_B1=29
8288 16:34:00.796684 30, 0x0, End_B0=30 End_B1=30
8289 16:34:00.800192 31, 0x4141, End_B0=30 End_B1=30
8290 16:34:00.803058 Byte0 end_step=30 best_step=27
8291 16:34:00.806590 Byte1 end_step=30 best_step=27
8292 16:34:00.810085 Byte0 TX OE(2T, 0.5T) = (3, 3)
8293 16:34:00.813514 Byte1 TX OE(2T, 0.5T) = (3, 3)
8294 16:34:00.813624
8295 16:34:00.813715
8296 16:34:00.819804 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d00, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
8297 16:34:00.823233 CH0 RK1: MR19=303, MR18=1D00
8298 16:34:00.829675 CH0_RK1: MR19=0x303, MR18=0x1D00, DQSOSC=395, MR23=63, INC=23, DEC=15
8299 16:34:00.833111 [RxdqsGatingPostProcess] freq 1600
8300 16:34:00.835954 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8301 16:34:00.839352 best DQS0 dly(2T, 0.5T) = (1, 1)
8302 16:34:00.842780 best DQS1 dly(2T, 0.5T) = (1, 1)
8303 16:34:00.846365 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8304 16:34:00.849613 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8305 16:34:00.853000 best DQS0 dly(2T, 0.5T) = (1, 1)
8306 16:34:00.856333 best DQS1 dly(2T, 0.5T) = (1, 1)
8307 16:34:00.859086 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8308 16:34:00.862496 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8309 16:34:00.866000 Pre-setting of DQS Precalculation
8310 16:34:00.869463 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8311 16:34:00.869564 ==
8312 16:34:00.872837 Dram Type= 6, Freq= 0, CH_1, rank 0
8313 16:34:00.878913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 16:34:00.879017 ==
8315 16:34:00.882214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8316 16:34:00.889081 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8317 16:34:00.892164 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8318 16:34:00.898852 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8319 16:34:00.906694 [CA 0] Center 42 (12~72) winsize 61
8320 16:34:00.909590 [CA 1] Center 42 (13~72) winsize 60
8321 16:34:00.913030 [CA 2] Center 38 (9~67) winsize 59
8322 16:34:00.916011 [CA 3] Center 37 (8~66) winsize 59
8323 16:34:00.919426 [CA 4] Center 38 (9~67) winsize 59
8324 16:34:00.922963 [CA 5] Center 37 (7~67) winsize 61
8325 16:34:00.923055
8326 16:34:00.926424 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8327 16:34:00.926504
8328 16:34:00.929350 [CATrainingPosCal] consider 1 rank data
8329 16:34:00.932903 u2DelayCellTimex100 = 262/100 ps
8330 16:34:00.939299 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8331 16:34:00.942788 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8332 16:34:00.946122 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8333 16:34:00.948924 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8334 16:34:00.952414 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8335 16:34:00.955859 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8336 16:34:00.955938
8337 16:34:00.959431 CA PerBit enable=1, Macro0, CA PI delay=37
8338 16:34:00.959505
8339 16:34:00.962811 [CBTSetCACLKResult] CA Dly = 37
8340 16:34:00.965667 CS Dly: 9 (0~40)
8341 16:34:00.969249 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8342 16:34:00.972015 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8343 16:34:00.972096 ==
8344 16:34:00.975298 Dram Type= 6, Freq= 0, CH_1, rank 1
8345 16:34:00.982029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 16:34:00.982234 ==
8347 16:34:00.985536 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8348 16:34:00.991857 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8349 16:34:00.995199 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8350 16:34:01.001693 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8351 16:34:01.009622 [CA 0] Center 42 (13~72) winsize 60
8352 16:34:01.012943 [CA 1] Center 43 (13~73) winsize 61
8353 16:34:01.015882 [CA 2] Center 37 (8~67) winsize 60
8354 16:34:01.019428 [CA 3] Center 37 (8~67) winsize 60
8355 16:34:01.022910 [CA 4] Center 38 (9~68) winsize 60
8356 16:34:01.026482 [CA 5] Center 37 (8~67) winsize 60
8357 16:34:01.026636
8358 16:34:01.029300 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8359 16:34:01.029480
8360 16:34:01.032729 [CATrainingPosCal] consider 2 rank data
8361 16:34:01.036026 u2DelayCellTimex100 = 262/100 ps
8362 16:34:01.042935 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8363 16:34:01.045703 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8364 16:34:01.049020 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8365 16:34:01.052459 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8366 16:34:01.055896 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8367 16:34:01.059253 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8368 16:34:01.059332
8369 16:34:01.062534 CA PerBit enable=1, Macro0, CA PI delay=37
8370 16:34:01.062609
8371 16:34:01.065326 [CBTSetCACLKResult] CA Dly = 37
8372 16:34:01.068687 CS Dly: 10 (0~43)
8373 16:34:01.072240 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8374 16:34:01.075810 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8375 16:34:01.075888
8376 16:34:01.078597 ----->DramcWriteLeveling(PI) begin...
8377 16:34:01.078671 ==
8378 16:34:01.082007 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 16:34:01.088862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 16:34:01.088997 ==
8381 16:34:01.092143 Write leveling (Byte 0): 22 => 22
8382 16:34:01.095585 Write leveling (Byte 1): 27 => 27
8383 16:34:01.095690 DramcWriteLeveling(PI) end<-----
8384 16:34:01.095771
8385 16:34:01.098988 ==
8386 16:34:01.101869 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 16:34:01.105407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 16:34:01.105577 ==
8389 16:34:01.108601 [Gating] SW mode calibration
8390 16:34:01.115402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8391 16:34:01.118640 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8392 16:34:01.125516 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 16:34:01.128307 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 16:34:01.131813 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 16:34:01.138234 1 4 12 | B1->B0 | 2c2c 3434 | 1 0 | (1 1) (0 0)
8396 16:34:01.141567 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 16:34:01.145192 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 16:34:01.151469 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 16:34:01.154737 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 16:34:01.158372 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 16:34:01.165214 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 16:34:01.168126 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8403 16:34:01.171183 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (0 1) (1 0)
8404 16:34:01.178121 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 16:34:01.181040 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 16:34:01.184473 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 16:34:01.190881 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 16:34:01.194343 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 16:34:01.197626 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 16:34:01.204480 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 16:34:01.207914 1 6 12 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
8412 16:34:01.214086 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 16:34:01.217387 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 16:34:01.220803 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 16:34:01.224040 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 16:34:01.230837 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 16:34:01.234157 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 16:34:01.240414 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 16:34:01.243907 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8420 16:34:01.246741 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8421 16:34:01.253861 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 16:34:01.256616 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 16:34:01.259886 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 16:34:01.267032 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 16:34:01.269765 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 16:34:01.273184 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 16:34:01.280102 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 16:34:01.283426 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 16:34:01.286232 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 16:34:01.293227 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 16:34:01.296741 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 16:34:01.299494 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 16:34:01.306260 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 16:34:01.309187 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8435 16:34:01.312937 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8436 16:34:01.318903 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8437 16:34:01.318988 Total UI for P1: 0, mck2ui 16
8438 16:34:01.325800 best dqsien dly found for B0: ( 1, 9, 10)
8439 16:34:01.329094 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 16:34:01.332007 Total UI for P1: 0, mck2ui 16
8441 16:34:01.335930 best dqsien dly found for B1: ( 1, 9, 14)
8442 16:34:01.339438 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8443 16:34:01.341950 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8444 16:34:01.342087
8445 16:34:01.345445 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8446 16:34:01.348949 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8447 16:34:01.352253 [Gating] SW calibration Done
8448 16:34:01.352375 ==
8449 16:34:01.355211 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 16:34:01.358541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 16:34:01.361980 ==
8452 16:34:01.362204 RX Vref Scan: 0
8453 16:34:01.362370
8454 16:34:01.365611 RX Vref 0 -> 0, step: 1
8455 16:34:01.365858
8456 16:34:01.368979 RX Delay 0 -> 252, step: 8
8457 16:34:01.371868 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8458 16:34:01.375246 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8459 16:34:01.378639 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8460 16:34:01.381449 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8461 16:34:01.388389 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8462 16:34:01.391752 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8463 16:34:01.395064 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8464 16:34:01.398563 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8465 16:34:01.401325 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8466 16:34:01.408168 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8467 16:34:01.411199 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8468 16:34:01.414686 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8469 16:34:01.417993 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8470 16:34:01.421272 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8471 16:34:01.427576 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8472 16:34:01.430998 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8473 16:34:01.431107 ==
8474 16:34:01.434403 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 16:34:01.437947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 16:34:01.438108 ==
8477 16:34:01.440854 DQS Delay:
8478 16:34:01.440981 DQS0 = 0, DQS1 = 0
8479 16:34:01.444133 DQM Delay:
8480 16:34:01.444233 DQM0 = 137, DQM1 = 129
8481 16:34:01.444331 DQ Delay:
8482 16:34:01.447539 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =131
8483 16:34:01.453895 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8484 16:34:01.457246 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8485 16:34:01.460584 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8486 16:34:01.460689
8487 16:34:01.460781
8488 16:34:01.460868 ==
8489 16:34:01.463993 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 16:34:01.467414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 16:34:01.467492 ==
8492 16:34:01.467557
8493 16:34:01.467617
8494 16:34:01.470746 TX Vref Scan disable
8495 16:34:01.474245 == TX Byte 0 ==
8496 16:34:01.477102 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8497 16:34:01.480488 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8498 16:34:01.483997 == TX Byte 1 ==
8499 16:34:01.486791 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8500 16:34:01.490333 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8501 16:34:01.490415 ==
8502 16:34:01.493845 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 16:34:01.500214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 16:34:01.500298 ==
8505 16:34:01.512013
8506 16:34:01.515579 TX Vref early break, caculate TX vref
8507 16:34:01.518422 TX Vref=16, minBit 0, minWin=21, winSum=373
8508 16:34:01.521902 TX Vref=18, minBit 5, minWin=22, winSum=380
8509 16:34:01.525441 TX Vref=20, minBit 0, minWin=23, winSum=387
8510 16:34:01.528254 TX Vref=22, minBit 0, minWin=23, winSum=400
8511 16:34:01.531507 TX Vref=24, minBit 0, minWin=24, winSum=409
8512 16:34:01.538595 TX Vref=26, minBit 5, minWin=24, winSum=413
8513 16:34:01.541861 TX Vref=28, minBit 0, minWin=24, winSum=418
8514 16:34:01.545185 TX Vref=30, minBit 0, minWin=23, winSum=407
8515 16:34:01.548560 TX Vref=32, minBit 0, minWin=23, winSum=400
8516 16:34:01.551385 TX Vref=34, minBit 6, minWin=22, winSum=390
8517 16:34:01.558079 [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 28
8518 16:34:01.558189
8519 16:34:01.561331 Final TX Range 0 Vref 28
8520 16:34:01.561413
8521 16:34:01.561478 ==
8522 16:34:01.564546 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 16:34:01.568007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 16:34:01.568119 ==
8525 16:34:01.568212
8526 16:34:01.568314
8527 16:34:01.571274 TX Vref Scan disable
8528 16:34:01.578360 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8529 16:34:01.578443 == TX Byte 0 ==
8530 16:34:01.581123 u2DelayCellOfst[0]=18 cells (5 PI)
8531 16:34:01.584493 u2DelayCellOfst[1]=14 cells (4 PI)
8532 16:34:01.587896 u2DelayCellOfst[2]=0 cells (0 PI)
8533 16:34:01.591132 u2DelayCellOfst[3]=7 cells (2 PI)
8534 16:34:01.593922 u2DelayCellOfst[4]=11 cells (3 PI)
8535 16:34:01.597294 u2DelayCellOfst[5]=22 cells (6 PI)
8536 16:34:01.600797 u2DelayCellOfst[6]=22 cells (6 PI)
8537 16:34:01.604133 u2DelayCellOfst[7]=7 cells (2 PI)
8538 16:34:01.607602 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8539 16:34:01.610998 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8540 16:34:01.613801 == TX Byte 1 ==
8541 16:34:01.617293 u2DelayCellOfst[8]=0 cells (0 PI)
8542 16:34:01.620514 u2DelayCellOfst[9]=3 cells (1 PI)
8543 16:34:01.624078 u2DelayCellOfst[10]=11 cells (3 PI)
8544 16:34:01.626876 u2DelayCellOfst[11]=3 cells (1 PI)
8545 16:34:01.626980 u2DelayCellOfst[12]=14 cells (4 PI)
8546 16:34:01.630425 u2DelayCellOfst[13]=18 cells (5 PI)
8547 16:34:01.633808 u2DelayCellOfst[14]=18 cells (5 PI)
8548 16:34:01.637171 u2DelayCellOfst[15]=18 cells (5 PI)
8549 16:34:01.643979 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8550 16:34:01.646624 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8551 16:34:01.646725 DramC Write-DBI on
8552 16:34:01.649971 ==
8553 16:34:01.653127 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 16:34:01.656395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 16:34:01.656514 ==
8556 16:34:01.656607
8557 16:34:01.656697
8558 16:34:01.659992 TX Vref Scan disable
8559 16:34:01.660099 == TX Byte 0 ==
8560 16:34:01.666861 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8561 16:34:01.666967 == TX Byte 1 ==
8562 16:34:01.670105 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8563 16:34:01.672802 DramC Write-DBI off
8564 16:34:01.672906
8565 16:34:01.673014 [DATLAT]
8566 16:34:01.676575 Freq=1600, CH1 RK0
8567 16:34:01.676684
8568 16:34:01.676783 DATLAT Default: 0xf
8569 16:34:01.679727 0, 0xFFFF, sum = 0
8570 16:34:01.679839 1, 0xFFFF, sum = 0
8571 16:34:01.683017 2, 0xFFFF, sum = 0
8572 16:34:01.686329 3, 0xFFFF, sum = 0
8573 16:34:01.686439 4, 0xFFFF, sum = 0
8574 16:34:01.689870 5, 0xFFFF, sum = 0
8575 16:34:01.689978 6, 0xFFFF, sum = 0
8576 16:34:01.693154 7, 0xFFFF, sum = 0
8577 16:34:01.693264 8, 0xFFFF, sum = 0
8578 16:34:01.695875 9, 0xFFFF, sum = 0
8579 16:34:01.695989 10, 0xFFFF, sum = 0
8580 16:34:01.699453 11, 0xFFFF, sum = 0
8581 16:34:01.699561 12, 0xFFFF, sum = 0
8582 16:34:01.702971 13, 0xFFFF, sum = 0
8583 16:34:01.703127 14, 0x0, sum = 1
8584 16:34:01.705662 15, 0x0, sum = 2
8585 16:34:01.705762 16, 0x0, sum = 3
8586 16:34:01.709298 17, 0x0, sum = 4
8587 16:34:01.709404 best_step = 15
8588 16:34:01.709546
8589 16:34:01.709650 ==
8590 16:34:01.712720 Dram Type= 6, Freq= 0, CH_1, rank 0
8591 16:34:01.719100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8592 16:34:01.719235 ==
8593 16:34:01.719333 RX Vref Scan: 1
8594 16:34:01.719453
8595 16:34:01.722378 Set Vref Range= 24 -> 127
8596 16:34:01.722481
8597 16:34:01.725971 RX Vref 24 -> 127, step: 1
8598 16:34:01.726080
8599 16:34:01.726229 RX Delay 11 -> 252, step: 4
8600 16:34:01.728802
8601 16:34:01.728912 Set Vref, RX VrefLevel [Byte0]: 24
8602 16:34:01.735316 [Byte1]: 24
8603 16:34:01.735427
8604 16:34:01.738644 Set Vref, RX VrefLevel [Byte0]: 25
8605 16:34:01.742065 [Byte1]: 25
8606 16:34:01.742179
8607 16:34:01.744845 Set Vref, RX VrefLevel [Byte0]: 26
8608 16:34:01.748255 [Byte1]: 26
8609 16:34:01.751594
8610 16:34:01.751699 Set Vref, RX VrefLevel [Byte0]: 27
8611 16:34:01.755130 [Byte1]: 27
8612 16:34:01.759116
8613 16:34:01.759224 Set Vref, RX VrefLevel [Byte0]: 28
8614 16:34:01.762690 [Byte1]: 28
8615 16:34:01.766684
8616 16:34:01.766792 Set Vref, RX VrefLevel [Byte0]: 29
8617 16:34:01.770063 [Byte1]: 29
8618 16:34:01.774336
8619 16:34:01.774444 Set Vref, RX VrefLevel [Byte0]: 30
8620 16:34:01.777940 [Byte1]: 30
8621 16:34:01.782054
8622 16:34:01.782177 Set Vref, RX VrefLevel [Byte0]: 31
8623 16:34:01.785312 [Byte1]: 31
8624 16:34:01.789832
8625 16:34:01.789938 Set Vref, RX VrefLevel [Byte0]: 32
8626 16:34:01.792963 [Byte1]: 32
8627 16:34:01.797606
8628 16:34:01.800799 Set Vref, RX VrefLevel [Byte0]: 33
8629 16:34:01.804121 [Byte1]: 33
8630 16:34:01.804215
8631 16:34:01.806913 Set Vref, RX VrefLevel [Byte0]: 34
8632 16:34:01.810567 [Byte1]: 34
8633 16:34:01.810652
8634 16:34:01.813949 Set Vref, RX VrefLevel [Byte0]: 35
8635 16:34:01.816822 [Byte1]: 35
8636 16:34:01.820218
8637 16:34:01.820325 Set Vref, RX VrefLevel [Byte0]: 36
8638 16:34:01.823780 [Byte1]: 36
8639 16:34:01.828177
8640 16:34:01.828294 Set Vref, RX VrefLevel [Byte0]: 37
8641 16:34:01.834559 [Byte1]: 37
8642 16:34:01.834690
8643 16:34:01.837458 Set Vref, RX VrefLevel [Byte0]: 38
8644 16:34:01.840825 [Byte1]: 38
8645 16:34:01.840904
8646 16:34:01.844304 Set Vref, RX VrefLevel [Byte0]: 39
8647 16:34:01.847853 [Byte1]: 39
8648 16:34:01.850553
8649 16:34:01.850650 Set Vref, RX VrefLevel [Byte0]: 40
8650 16:34:01.854114 [Byte1]: 40
8651 16:34:01.858232
8652 16:34:01.858313 Set Vref, RX VrefLevel [Byte0]: 41
8653 16:34:01.861707 [Byte1]: 41
8654 16:34:01.865790
8655 16:34:01.865870 Set Vref, RX VrefLevel [Byte0]: 42
8656 16:34:01.869295 [Byte1]: 42
8657 16:34:01.873287
8658 16:34:01.873370 Set Vref, RX VrefLevel [Byte0]: 43
8659 16:34:01.876869 [Byte1]: 43
8660 16:34:01.880976
8661 16:34:01.881083 Set Vref, RX VrefLevel [Byte0]: 44
8662 16:34:01.884572 [Byte1]: 44
8663 16:34:01.888796
8664 16:34:01.888900 Set Vref, RX VrefLevel [Byte0]: 45
8665 16:34:01.892179 [Byte1]: 45
8666 16:34:01.896194
8667 16:34:01.896304 Set Vref, RX VrefLevel [Byte0]: 46
8668 16:34:01.899507 [Byte1]: 46
8669 16:34:01.904103
8670 16:34:01.904207 Set Vref, RX VrefLevel [Byte0]: 47
8671 16:34:01.907498 [Byte1]: 47
8672 16:34:01.911212
8673 16:34:01.911294 Set Vref, RX VrefLevel [Byte0]: 48
8674 16:34:01.915190 [Byte1]: 48
8675 16:34:01.919498
8676 16:34:01.919581 Set Vref, RX VrefLevel [Byte0]: 49
8677 16:34:01.922187 [Byte1]: 49
8678 16:34:01.927063
8679 16:34:01.927148 Set Vref, RX VrefLevel [Byte0]: 50
8680 16:34:01.929987 [Byte1]: 50
8681 16:34:01.934181
8682 16:34:01.934267 Set Vref, RX VrefLevel [Byte0]: 51
8683 16:34:01.937865 [Byte1]: 51
8684 16:34:01.941977
8685 16:34:01.942086 Set Vref, RX VrefLevel [Byte0]: 52
8686 16:34:01.945536 [Byte1]: 52
8687 16:34:01.949756
8688 16:34:01.949841 Set Vref, RX VrefLevel [Byte0]: 53
8689 16:34:01.953236 [Byte1]: 53
8690 16:34:01.957504
8691 16:34:01.957588 Set Vref, RX VrefLevel [Byte0]: 54
8692 16:34:01.960848 [Byte1]: 54
8693 16:34:01.965097
8694 16:34:01.965182 Set Vref, RX VrefLevel [Byte0]: 55
8695 16:34:01.968457 [Byte1]: 55
8696 16:34:01.972540
8697 16:34:01.972651 Set Vref, RX VrefLevel [Byte0]: 56
8698 16:34:01.975426 [Byte1]: 56
8699 16:34:01.980197
8700 16:34:01.980282 Set Vref, RX VrefLevel [Byte0]: 57
8701 16:34:01.983850 [Byte1]: 57
8702 16:34:01.988083
8703 16:34:01.988160 Set Vref, RX VrefLevel [Byte0]: 58
8704 16:34:01.991424 [Byte1]: 58
8705 16:34:01.995519
8706 16:34:01.995601 Set Vref, RX VrefLevel [Byte0]: 59
8707 16:34:01.998861 [Byte1]: 59
8708 16:34:02.002766
8709 16:34:02.002881 Set Vref, RX VrefLevel [Byte0]: 60
8710 16:34:02.006307 [Byte1]: 60
8711 16:34:02.010317
8712 16:34:02.010403 Set Vref, RX VrefLevel [Byte0]: 61
8713 16:34:02.013694 [Byte1]: 61
8714 16:34:02.018469
8715 16:34:02.018572 Set Vref, RX VrefLevel [Byte0]: 62
8716 16:34:02.021166 [Byte1]: 62
8717 16:34:02.025478
8718 16:34:02.025592 Set Vref, RX VrefLevel [Byte0]: 63
8719 16:34:02.029222 [Byte1]: 63
8720 16:34:02.033467
8721 16:34:02.033545 Set Vref, RX VrefLevel [Byte0]: 64
8722 16:34:02.036800 [Byte1]: 64
8723 16:34:02.041067
8724 16:34:02.041152 Set Vref, RX VrefLevel [Byte0]: 65
8725 16:34:02.044646 [Byte1]: 65
8726 16:34:02.048881
8727 16:34:02.048963 Set Vref, RX VrefLevel [Byte0]: 66
8728 16:34:02.051600 [Byte1]: 66
8729 16:34:02.056571
8730 16:34:02.056686 Set Vref, RX VrefLevel [Byte0]: 67
8731 16:34:02.059327 [Byte1]: 67
8732 16:34:02.064242
8733 16:34:02.064350 Set Vref, RX VrefLevel [Byte0]: 68
8734 16:34:02.066974 [Byte1]: 68
8735 16:34:02.071870
8736 16:34:02.071953 Set Vref, RX VrefLevel [Byte0]: 69
8737 16:34:02.074534 [Byte1]: 69
8738 16:34:02.079175
8739 16:34:02.079258 Set Vref, RX VrefLevel [Byte0]: 70
8740 16:34:02.082755 [Byte1]: 70
8741 16:34:02.086834
8742 16:34:02.086915 Set Vref, RX VrefLevel [Byte0]: 71
8743 16:34:02.090122 [Byte1]: 71
8744 16:34:02.094094
8745 16:34:02.094246 Final RX Vref Byte 0 = 53 to rank0
8746 16:34:02.097639 Final RX Vref Byte 1 = 60 to rank0
8747 16:34:02.101224 Final RX Vref Byte 0 = 53 to rank1
8748 16:34:02.104598 Final RX Vref Byte 1 = 60 to rank1==
8749 16:34:02.107889 Dram Type= 6, Freq= 0, CH_1, rank 0
8750 16:34:02.113972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 16:34:02.114084 ==
8752 16:34:02.114226 DQS Delay:
8753 16:34:02.114295 DQS0 = 0, DQS1 = 0
8754 16:34:02.117386 DQM Delay:
8755 16:34:02.117467 DQM0 = 133, DQM1 = 127
8756 16:34:02.120805 DQ Delay:
8757 16:34:02.124161 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8758 16:34:02.127181 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8759 16:34:02.130579 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8760 16:34:02.133935 DQ12 =136, DQ13 =134, DQ14 =136, DQ15 =136
8761 16:34:02.134019
8762 16:34:02.134083
8763 16:34:02.134143
8764 16:34:02.137030 [DramC_TX_OE_Calibration] TA2
8765 16:34:02.140799 Original DQ_B0 (3 6) =30, OEN = 27
8766 16:34:02.144105 Original DQ_B1 (3 6) =30, OEN = 27
8767 16:34:02.147599 24, 0x0, End_B0=24 End_B1=24
8768 16:34:02.147715 25, 0x0, End_B0=25 End_B1=25
8769 16:34:02.150458 26, 0x0, End_B0=26 End_B1=26
8770 16:34:02.153940 27, 0x0, End_B0=27 End_B1=27
8771 16:34:02.157401 28, 0x0, End_B0=28 End_B1=28
8772 16:34:02.160252 29, 0x0, End_B0=29 End_B1=29
8773 16:34:02.160336 30, 0x0, End_B0=30 End_B1=30
8774 16:34:02.163647 31, 0x4141, End_B0=30 End_B1=30
8775 16:34:02.167227 Byte0 end_step=30 best_step=27
8776 16:34:02.170563 Byte1 end_step=30 best_step=27
8777 16:34:02.173950 Byte0 TX OE(2T, 0.5T) = (3, 3)
8778 16:34:02.177369 Byte1 TX OE(2T, 0.5T) = (3, 3)
8779 16:34:02.177475
8780 16:34:02.177567
8781 16:34:02.183481 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8782 16:34:02.186874 CH1 RK0: MR19=303, MR18=1A10
8783 16:34:02.193678 CH1_RK0: MR19=0x303, MR18=0x1A10, DQSOSC=396, MR23=63, INC=23, DEC=15
8784 16:34:02.193796
8785 16:34:02.196983 ----->DramcWriteLeveling(PI) begin...
8786 16:34:02.197085 ==
8787 16:34:02.200429 Dram Type= 6, Freq= 0, CH_1, rank 1
8788 16:34:02.203274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 16:34:02.203397 ==
8790 16:34:02.206708 Write leveling (Byte 0): 23 => 23
8791 16:34:02.210057 Write leveling (Byte 1): 28 => 28
8792 16:34:02.213441 DramcWriteLeveling(PI) end<-----
8793 16:34:02.213551
8794 16:34:02.213643 ==
8795 16:34:02.216624 Dram Type= 6, Freq= 0, CH_1, rank 1
8796 16:34:02.220024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8797 16:34:02.222774 ==
8798 16:34:02.222903 [Gating] SW mode calibration
8799 16:34:02.232567 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8800 16:34:02.236260 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8801 16:34:02.239761 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 16:34:02.246305 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 16:34:02.249640 1 4 8 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8804 16:34:02.252753 1 4 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8805 16:34:02.259199 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 16:34:02.262495 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 16:34:02.265933 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 16:34:02.272211 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 16:34:02.275580 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 16:34:02.279026 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 16:34:02.285930 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8812 16:34:02.288774 1 5 12 | B1->B0 | 2828 3434 | 0 1 | (1 0) (1 0)
8813 16:34:02.291954 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8814 16:34:02.298888 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 16:34:02.302128 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 16:34:02.305380 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 16:34:02.312343 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 16:34:02.315797 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 16:34:02.318439 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 16:34:02.325095 1 6 12 | B1->B0 | 4343 2525 | 0 0 | (0 0) (0 0)
8821 16:34:02.328395 1 6 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8822 16:34:02.332184 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 16:34:02.338439 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 16:34:02.341829 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 16:34:02.345279 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 16:34:02.351422 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 16:34:02.354762 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8828 16:34:02.358089 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8829 16:34:02.364999 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8830 16:34:02.367979 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 16:34:02.371202 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 16:34:02.378034 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 16:34:02.381563 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 16:34:02.384361 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 16:34:02.390944 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 16:34:02.394230 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 16:34:02.397872 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 16:34:02.404673 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 16:34:02.407446 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 16:34:02.411246 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 16:34:02.417348 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 16:34:02.420800 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 16:34:02.424220 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8844 16:34:02.430886 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8845 16:34:02.434200 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 16:34:02.437561 Total UI for P1: 0, mck2ui 16
8847 16:34:02.440770 best dqsien dly found for B0: ( 1, 9, 10)
8848 16:34:02.443626 Total UI for P1: 0, mck2ui 16
8849 16:34:02.447006 best dqsien dly found for B1: ( 1, 9, 10)
8850 16:34:02.450343 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8851 16:34:02.453812 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8852 16:34:02.453894
8853 16:34:02.457242 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8854 16:34:02.463440 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8855 16:34:02.463524 [Gating] SW calibration Done
8856 16:34:02.463591 ==
8857 16:34:02.466880 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 16:34:02.473547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 16:34:02.473638 ==
8860 16:34:02.473733 RX Vref Scan: 0
8861 16:34:02.473795
8862 16:34:02.476809 RX Vref 0 -> 0, step: 1
8863 16:34:02.476891
8864 16:34:02.480088 RX Delay 0 -> 252, step: 8
8865 16:34:02.483764 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8866 16:34:02.487108 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8867 16:34:02.489970 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8868 16:34:02.493488 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8869 16:34:02.500197 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8870 16:34:02.503594 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8871 16:34:02.507103 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8872 16:34:02.509901 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8873 16:34:02.513314 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8874 16:34:02.519965 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8875 16:34:02.523287 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8876 16:34:02.526823 iDelay=208, Bit 11, Center 119 (56 ~ 183) 128
8877 16:34:02.529511 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8878 16:34:02.536154 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8879 16:34:02.539531 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8880 16:34:02.543010 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8881 16:34:02.543118 ==
8882 16:34:02.546279 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 16:34:02.549503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 16:34:02.549597 ==
8885 16:34:02.552894 DQS Delay:
8886 16:34:02.552976 DQS0 = 0, DQS1 = 0
8887 16:34:02.556205 DQM Delay:
8888 16:34:02.556286 DQM0 = 136, DQM1 = 129
8889 16:34:02.559602 DQ Delay:
8890 16:34:02.562419 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8891 16:34:02.565834 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8892 16:34:02.569177 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8893 16:34:02.572708 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8894 16:34:02.572790
8895 16:34:02.572891
8896 16:34:02.572951 ==
8897 16:34:02.576103 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 16:34:02.578939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 16:34:02.579022 ==
8900 16:34:02.579087
8901 16:34:02.582380
8902 16:34:02.582461 TX Vref Scan disable
8903 16:34:02.585740 == TX Byte 0 ==
8904 16:34:02.589017 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8905 16:34:02.592481 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8906 16:34:02.595718 == TX Byte 1 ==
8907 16:34:02.598870 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8908 16:34:02.602098 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8909 16:34:02.602251 ==
8910 16:34:02.605535 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 16:34:02.612139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 16:34:02.612229 ==
8913 16:34:02.624129
8914 16:34:02.627242 TX Vref early break, caculate TX vref
8915 16:34:02.630585 TX Vref=16, minBit 1, minWin=22, winSum=376
8916 16:34:02.634104 TX Vref=18, minBit 0, minWin=23, winSum=388
8917 16:34:02.637705 TX Vref=20, minBit 0, minWin=24, winSum=398
8918 16:34:02.640387 TX Vref=22, minBit 1, minWin=23, winSum=404
8919 16:34:02.643820 TX Vref=24, minBit 5, minWin=24, winSum=410
8920 16:34:02.650658 TX Vref=26, minBit 0, minWin=24, winSum=415
8921 16:34:02.654065 TX Vref=28, minBit 0, minWin=24, winSum=417
8922 16:34:02.657426 TX Vref=30, minBit 0, minWin=23, winSum=406
8923 16:34:02.660048 TX Vref=32, minBit 0, minWin=23, winSum=401
8924 16:34:02.664220 TX Vref=34, minBit 0, minWin=23, winSum=391
8925 16:34:02.670429 [TxChooseVref] Worse bit 0, Min win 24, Win sum 417, Final Vref 28
8926 16:34:02.670513
8927 16:34:02.673932 Final TX Range 0 Vref 28
8928 16:34:02.674014
8929 16:34:02.674079 ==
8930 16:34:02.676592 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 16:34:02.680074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 16:34:02.680160 ==
8933 16:34:02.680226
8934 16:34:02.680287
8935 16:34:02.683499 TX Vref Scan disable
8936 16:34:02.690410 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8937 16:34:02.690493 == TX Byte 0 ==
8938 16:34:02.693215 u2DelayCellOfst[0]=18 cells (5 PI)
8939 16:34:02.696860 u2DelayCellOfst[1]=14 cells (4 PI)
8940 16:34:02.700415 u2DelayCellOfst[2]=0 cells (0 PI)
8941 16:34:02.703188 u2DelayCellOfst[3]=7 cells (2 PI)
8942 16:34:02.706589 u2DelayCellOfst[4]=7 cells (2 PI)
8943 16:34:02.709870 u2DelayCellOfst[5]=22 cells (6 PI)
8944 16:34:02.713496 u2DelayCellOfst[6]=18 cells (5 PI)
8945 16:34:02.716576 u2DelayCellOfst[7]=3 cells (1 PI)
8946 16:34:02.719858 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8947 16:34:02.723249 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8948 16:34:02.726146 == TX Byte 1 ==
8949 16:34:02.729695 u2DelayCellOfst[8]=0 cells (0 PI)
8950 16:34:02.733167 u2DelayCellOfst[9]=11 cells (3 PI)
8951 16:34:02.736338 u2DelayCellOfst[10]=14 cells (4 PI)
8952 16:34:02.736475 u2DelayCellOfst[11]=7 cells (2 PI)
8953 16:34:02.739875 u2DelayCellOfst[12]=18 cells (5 PI)
8954 16:34:02.742689 u2DelayCellOfst[13]=18 cells (5 PI)
8955 16:34:02.746182 u2DelayCellOfst[14]=22 cells (6 PI)
8956 16:34:02.749747 u2DelayCellOfst[15]=18 cells (5 PI)
8957 16:34:02.756164 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8958 16:34:02.759644 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8959 16:34:02.759992 DramC Write-DBI on
8960 16:34:02.763047 ==
8961 16:34:02.766296 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 16:34:02.769597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 16:34:02.770329 ==
8964 16:34:02.770873
8965 16:34:02.771347
8966 16:34:02.773177 TX Vref Scan disable
8967 16:34:02.773626 == TX Byte 0 ==
8968 16:34:02.779548 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8969 16:34:02.779985 == TX Byte 1 ==
8970 16:34:02.782475 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8971 16:34:02.785973 DramC Write-DBI off
8972 16:34:02.786446
8973 16:34:02.786782 [DATLAT]
8974 16:34:02.789450 Freq=1600, CH1 RK1
8975 16:34:02.789999
8976 16:34:02.790439 DATLAT Default: 0xf
8977 16:34:02.792403 0, 0xFFFF, sum = 0
8978 16:34:02.792948 1, 0xFFFF, sum = 0
8979 16:34:02.795770 2, 0xFFFF, sum = 0
8980 16:34:02.796379 3, 0xFFFF, sum = 0
8981 16:34:02.799266 4, 0xFFFF, sum = 0
8982 16:34:02.801977 5, 0xFFFF, sum = 0
8983 16:34:02.802566 6, 0xFFFF, sum = 0
8984 16:34:02.805560 7, 0xFFFF, sum = 0
8985 16:34:02.806262 8, 0xFFFF, sum = 0
8986 16:34:02.809088 9, 0xFFFF, sum = 0
8987 16:34:02.809516 10, 0xFFFF, sum = 0
8988 16:34:02.811744 11, 0xFFFF, sum = 0
8989 16:34:02.812279 12, 0xFFFF, sum = 0
8990 16:34:02.815342 13, 0xFFFF, sum = 0
8991 16:34:02.815774 14, 0x0, sum = 1
8992 16:34:02.818690 15, 0x0, sum = 2
8993 16:34:02.819165 16, 0x0, sum = 3
8994 16:34:02.822058 17, 0x0, sum = 4
8995 16:34:02.822592 best_step = 15
8996 16:34:02.823033
8997 16:34:02.823584 ==
8998 16:34:02.825336 Dram Type= 6, Freq= 0, CH_1, rank 1
8999 16:34:02.831751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9000 16:34:02.832181 ==
9001 16:34:02.832599 RX Vref Scan: 0
9002 16:34:02.832923
9003 16:34:02.835007 RX Vref 0 -> 0, step: 1
9004 16:34:02.835429
9005 16:34:02.838363 RX Delay 11 -> 252, step: 4
9006 16:34:02.841754 iDelay=199, Bit 0, Center 138 (87 ~ 190) 104
9007 16:34:02.845149 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9008 16:34:02.848134 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9009 16:34:02.854866 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9010 16:34:02.858120 iDelay=199, Bit 4, Center 132 (75 ~ 190) 116
9011 16:34:02.861444 iDelay=199, Bit 5, Center 144 (91 ~ 198) 108
9012 16:34:02.864916 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9013 16:34:02.867733 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9014 16:34:02.874843 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9015 16:34:02.877979 iDelay=199, Bit 9, Center 116 (63 ~ 170) 108
9016 16:34:02.880717 iDelay=199, Bit 10, Center 126 (71 ~ 182) 112
9017 16:34:02.884332 iDelay=199, Bit 11, Center 116 (63 ~ 170) 108
9018 16:34:02.891244 iDelay=199, Bit 12, Center 136 (83 ~ 190) 108
9019 16:34:02.894069 iDelay=199, Bit 13, Center 136 (83 ~ 190) 108
9020 16:34:02.897633 iDelay=199, Bit 14, Center 134 (79 ~ 190) 112
9021 16:34:02.900834 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9022 16:34:02.901388 ==
9023 16:34:02.904203 Dram Type= 6, Freq= 0, CH_1, rank 1
9024 16:34:02.910680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9025 16:34:02.911136 ==
9026 16:34:02.911488 DQS Delay:
9027 16:34:02.913989 DQS0 = 0, DQS1 = 0
9028 16:34:02.914543 DQM Delay:
9029 16:34:02.914886 DQM0 = 133, DQM1 = 126
9030 16:34:02.917509 DQ Delay:
9031 16:34:02.920866 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9032 16:34:02.924389 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
9033 16:34:02.927171 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9034 16:34:02.930689 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9035 16:34:02.931114
9036 16:34:02.931452
9037 16:34:02.931766
9038 16:34:02.934005 [DramC_TX_OE_Calibration] TA2
9039 16:34:02.937254 Original DQ_B0 (3 6) =30, OEN = 27
9040 16:34:02.940612 Original DQ_B1 (3 6) =30, OEN = 27
9041 16:34:02.943866 24, 0x0, End_B0=24 End_B1=24
9042 16:34:02.944317 25, 0x0, End_B0=25 End_B1=25
9043 16:34:02.947080 26, 0x0, End_B0=26 End_B1=26
9044 16:34:02.950396 27, 0x0, End_B0=27 End_B1=27
9045 16:34:02.954258 28, 0x0, End_B0=28 End_B1=28
9046 16:34:02.957361 29, 0x0, End_B0=29 End_B1=29
9047 16:34:02.957789 30, 0x0, End_B0=30 End_B1=30
9048 16:34:02.960392 31, 0x4141, End_B0=30 End_B1=30
9049 16:34:02.963620 Byte0 end_step=30 best_step=27
9050 16:34:02.967091 Byte1 end_step=30 best_step=27
9051 16:34:02.969894 Byte0 TX OE(2T, 0.5T) = (3, 3)
9052 16:34:02.973354 Byte1 TX OE(2T, 0.5T) = (3, 3)
9053 16:34:02.973799
9054 16:34:02.974333
9055 16:34:02.979945 [DQSOSCAuto] RK1, (LSB)MR18= 0xa06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9056 16:34:02.983441 CH1 RK1: MR19=303, MR18=A06
9057 16:34:02.990375 CH1_RK1: MR19=0x303, MR18=0xA06, DQSOSC=404, MR23=63, INC=22, DEC=15
9058 16:34:02.993484 [RxdqsGatingPostProcess] freq 1600
9059 16:34:02.996944 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9060 16:34:02.999669 best DQS0 dly(2T, 0.5T) = (1, 1)
9061 16:34:03.002964 best DQS1 dly(2T, 0.5T) = (1, 1)
9062 16:34:03.006457 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9063 16:34:03.009672 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9064 16:34:03.013303 best DQS0 dly(2T, 0.5T) = (1, 1)
9065 16:34:03.016716 best DQS1 dly(2T, 0.5T) = (1, 1)
9066 16:34:03.019629 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9067 16:34:03.022957 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9068 16:34:03.026590 Pre-setting of DQS Precalculation
9069 16:34:03.029160 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9070 16:34:03.039584 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9071 16:34:03.045913 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9072 16:34:03.046385
9073 16:34:03.046732
9074 16:34:03.049146 [Calibration Summary] 3200 Mbps
9075 16:34:03.049449 CH 0, Rank 0
9076 16:34:03.052353 SW Impedance : PASS
9077 16:34:03.052730 DUTY Scan : NO K
9078 16:34:03.055646 ZQ Calibration : PASS
9079 16:34:03.058951 Jitter Meter : NO K
9080 16:34:03.059395 CBT Training : PASS
9081 16:34:03.062123 Write leveling : PASS
9082 16:34:03.065444 RX DQS gating : PASS
9083 16:34:03.065779 RX DQ/DQS(RDDQC) : PASS
9084 16:34:03.068782 TX DQ/DQS : PASS
9085 16:34:03.072107 RX DATLAT : PASS
9086 16:34:03.072472 RX DQ/DQS(Engine): PASS
9087 16:34:03.075792 TX OE : PASS
9088 16:34:03.076096 All Pass.
9089 16:34:03.076336
9090 16:34:03.078483 CH 0, Rank 1
9091 16:34:03.078819 SW Impedance : PASS
9092 16:34:03.081939 DUTY Scan : NO K
9093 16:34:03.085532 ZQ Calibration : PASS
9094 16:34:03.085844 Jitter Meter : NO K
9095 16:34:03.088266 CBT Training : PASS
9096 16:34:03.091894 Write leveling : PASS
9097 16:34:03.092195 RX DQS gating : PASS
9098 16:34:03.095259 RX DQ/DQS(RDDQC) : PASS
9099 16:34:03.095576 TX DQ/DQS : PASS
9100 16:34:03.098695 RX DATLAT : PASS
9101 16:34:03.101843 RX DQ/DQS(Engine): PASS
9102 16:34:03.102142 TX OE : PASS
9103 16:34:03.105553 All Pass.
9104 16:34:03.106022
9105 16:34:03.106397 CH 1, Rank 0
9106 16:34:03.108279 SW Impedance : PASS
9107 16:34:03.108577 DUTY Scan : NO K
9108 16:34:03.111608 ZQ Calibration : PASS
9109 16:34:03.114844 Jitter Meter : NO K
9110 16:34:03.115283 CBT Training : PASS
9111 16:34:03.118448 Write leveling : PASS
9112 16:34:03.121909 RX DQS gating : PASS
9113 16:34:03.122244 RX DQ/DQS(RDDQC) : PASS
9114 16:34:03.125272 TX DQ/DQS : PASS
9115 16:34:03.128660 RX DATLAT : PASS
9116 16:34:03.128963 RX DQ/DQS(Engine): PASS
9117 16:34:03.131563 TX OE : PASS
9118 16:34:03.131867 All Pass.
9119 16:34:03.132107
9120 16:34:03.134941 CH 1, Rank 1
9121 16:34:03.135244 SW Impedance : PASS
9122 16:34:03.138406 DUTY Scan : NO K
9123 16:34:03.141930 ZQ Calibration : PASS
9124 16:34:03.142356 Jitter Meter : NO K
9125 16:34:03.144662 CBT Training : PASS
9126 16:34:03.148145 Write leveling : PASS
9127 16:34:03.148554 RX DQS gating : PASS
9128 16:34:03.151647 RX DQ/DQS(RDDQC) : PASS
9129 16:34:03.155051 TX DQ/DQS : PASS
9130 16:34:03.155627 RX DATLAT : PASS
9131 16:34:03.158435 RX DQ/DQS(Engine): PASS
9132 16:34:03.161175 TX OE : PASS
9133 16:34:03.161641 All Pass.
9134 16:34:03.162242
9135 16:34:03.162787 DramC Write-DBI on
9136 16:34:03.164609 PER_BANK_REFRESH: Hybrid Mode
9137 16:34:03.167945 TX_TRACKING: ON
9138 16:34:03.174822 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9139 16:34:03.184746 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9140 16:34:03.191224 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9141 16:34:03.194073 [FAST_K] Save calibration result to emmc
9142 16:34:03.197637 sync common calibartion params.
9143 16:34:03.201125 sync cbt_mode0:1, 1:1
9144 16:34:03.201549 dram_init: ddr_geometry: 2
9145 16:34:03.204796 dram_init: ddr_geometry: 2
9146 16:34:03.207981 dram_init: ddr_geometry: 2
9147 16:34:03.208405 0:dram_rank_size:100000000
9148 16:34:03.210683 1:dram_rank_size:100000000
9149 16:34:03.217199 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9150 16:34:03.220861 DFS_SHUFFLE_HW_MODE: ON
9151 16:34:03.224416 dramc_set_vcore_voltage set vcore to 725000
9152 16:34:03.224993 Read voltage for 1600, 0
9153 16:34:03.227221 Vio18 = 0
9154 16:34:03.227646 Vcore = 725000
9155 16:34:03.227983 Vdram = 0
9156 16:34:03.230677 Vddq = 0
9157 16:34:03.231097 Vmddr = 0
9158 16:34:03.234055 switch to 3200 Mbps bootup
9159 16:34:03.234528 [DramcRunTimeConfig]
9160 16:34:03.235077 PHYPLL
9161 16:34:03.237599 DPM_CONTROL_AFTERK: ON
9162 16:34:03.240809 PER_BANK_REFRESH: ON
9163 16:34:03.241375 REFRESH_OVERHEAD_REDUCTION: ON
9164 16:34:03.243651 CMD_PICG_NEW_MODE: OFF
9165 16:34:03.247039 XRTWTW_NEW_MODE: ON
9166 16:34:03.247594 XRTRTR_NEW_MODE: ON
9167 16:34:03.250466 TX_TRACKING: ON
9168 16:34:03.250893 RDSEL_TRACKING: OFF
9169 16:34:03.253952 DQS Precalculation for DVFS: ON
9170 16:34:03.257220 RX_TRACKING: OFF
9171 16:34:03.257783 HW_GATING DBG: ON
9172 16:34:03.260674 ZQCS_ENABLE_LP4: ON
9173 16:34:03.261189 RX_PICG_NEW_MODE: ON
9174 16:34:03.263594 TX_PICG_NEW_MODE: ON
9175 16:34:03.264013 ENABLE_RX_DCM_DPHY: ON
9176 16:34:03.266971 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9177 16:34:03.270420 DUMMY_READ_FOR_TRACKING: OFF
9178 16:34:03.273149 !!! SPM_CONTROL_AFTERK: OFF
9179 16:34:03.277088 !!! SPM could not control APHY
9180 16:34:03.277728 IMPEDANCE_TRACKING: ON
9181 16:34:03.279855 TEMP_SENSOR: ON
9182 16:34:03.280453 HW_SAVE_FOR_SR: OFF
9183 16:34:03.283377 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9184 16:34:03.287107 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9185 16:34:03.289865 Read ODT Tracking: ON
9186 16:34:03.292993 Refresh Rate DeBounce: ON
9187 16:34:03.293520 DFS_NO_QUEUE_FLUSH: ON
9188 16:34:03.296596 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9189 16:34:03.299904 ENABLE_DFS_RUNTIME_MRW: OFF
9190 16:34:03.303346 DDR_RESERVE_NEW_MODE: ON
9191 16:34:03.303738 MR_CBT_SWITCH_FREQ: ON
9192 16:34:03.306068 =========================
9193 16:34:03.324733 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9194 16:34:03.328178 dram_init: ddr_geometry: 2
9195 16:34:03.346517 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9196 16:34:03.350053 dram_init: dram init end (result: 0)
9197 16:34:03.356282 DRAM-K: Full calibration passed in 24634 msecs
9198 16:34:03.359808 MRC: failed to locate region type 0.
9199 16:34:03.359922 DRAM rank0 size:0x100000000,
9200 16:34:03.363329 DRAM rank1 size=0x100000000
9201 16:34:03.372867 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9202 16:34:03.379790 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9203 16:34:03.386343 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9204 16:34:03.392458 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9205 16:34:03.395916 DRAM rank0 size:0x100000000,
9206 16:34:03.399409 DRAM rank1 size=0x100000000
9207 16:34:03.399533 CBMEM:
9208 16:34:03.402754 IMD: root @ 0xfffff000 254 entries.
9209 16:34:03.405960 IMD: root @ 0xffffec00 62 entries.
9210 16:34:03.409379 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9211 16:34:03.415959 WARNING: RO_VPD is uninitialized or empty.
9212 16:34:03.419407 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9213 16:34:03.426995 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9214 16:34:03.439502 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9215 16:34:03.450961 BS: romstage times (exec / console): total (unknown) / 24122 ms
9216 16:34:03.451534
9217 16:34:03.452021
9218 16:34:03.460840 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9219 16:34:03.464194 ARM64: Exception handlers installed.
9220 16:34:03.467202 ARM64: Testing exception
9221 16:34:03.470528 ARM64: Done test exception
9222 16:34:03.470945 Enumerating buses...
9223 16:34:03.473976 Show all devs... Before device enumeration.
9224 16:34:03.477450 Root Device: enabled 1
9225 16:34:03.480841 CPU_CLUSTER: 0: enabled 1
9226 16:34:03.481312 CPU: 00: enabled 1
9227 16:34:03.483746 Compare with tree...
9228 16:34:03.484160 Root Device: enabled 1
9229 16:34:03.487181 CPU_CLUSTER: 0: enabled 1
9230 16:34:03.490602 CPU: 00: enabled 1
9231 16:34:03.491025 Root Device scanning...
9232 16:34:03.493700 scan_static_bus for Root Device
9233 16:34:03.497027 CPU_CLUSTER: 0 enabled
9234 16:34:03.500474 scan_static_bus for Root Device done
9235 16:34:03.504077 scan_bus: bus Root Device finished in 8 msecs
9236 16:34:03.504511 done
9237 16:34:03.510233 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9238 16:34:03.513732 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9239 16:34:03.520059 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9240 16:34:03.526482 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9241 16:34:03.526929 Allocating resources...
9242 16:34:03.529778 Reading resources...
9243 16:34:03.533312 Root Device read_resources bus 0 link: 0
9244 16:34:03.536699 DRAM rank0 size:0x100000000,
9245 16:34:03.537291 DRAM rank1 size=0x100000000
9246 16:34:03.543109 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9247 16:34:03.543784 CPU: 00 missing read_resources
9248 16:34:03.549991 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9249 16:34:03.553193 Root Device read_resources bus 0 link: 0 done
9250 16:34:03.556316 Done reading resources.
9251 16:34:03.559690 Show resources in subtree (Root Device)...After reading.
9252 16:34:03.562754 Root Device child on link 0 CPU_CLUSTER: 0
9253 16:34:03.565721 CPU_CLUSTER: 0 child on link 0 CPU: 00
9254 16:34:03.576063 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9255 16:34:03.576351 CPU: 00
9256 16:34:03.582461 Root Device assign_resources, bus 0 link: 0
9257 16:34:03.585371 CPU_CLUSTER: 0 missing set_resources
9258 16:34:03.588868 Root Device assign_resources, bus 0 link: 0 done
9259 16:34:03.592385 Done setting resources.
9260 16:34:03.595332 Show resources in subtree (Root Device)...After assigning values.
9261 16:34:03.598766 Root Device child on link 0 CPU_CLUSTER: 0
9262 16:34:03.605524 CPU_CLUSTER: 0 child on link 0 CPU: 00
9263 16:34:03.612392 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9264 16:34:03.615356 CPU: 00
9265 16:34:03.615508 Done allocating resources.
9266 16:34:03.621967 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9267 16:34:03.622207 Enabling resources...
9268 16:34:03.625220 done.
9269 16:34:03.628652 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9270 16:34:03.632091 Initializing devices...
9271 16:34:03.632267 Root Device init
9272 16:34:03.634955 init hardware done!
9273 16:34:03.635131 0x00000018: ctrlr->caps
9274 16:34:03.638315 52.000 MHz: ctrlr->f_max
9275 16:34:03.641931 0.400 MHz: ctrlr->f_min
9276 16:34:03.645425 0x40ff8080: ctrlr->voltages
9277 16:34:03.645630 sclk: 390625
9278 16:34:03.645789 Bus Width = 1
9279 16:34:03.648443 sclk: 390625
9280 16:34:03.648691 Bus Width = 1
9281 16:34:03.651958 Early init status = 3
9282 16:34:03.655407 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9283 16:34:03.658310 in-header: 03 fc 00 00 01 00 00 00
9284 16:34:03.661974 in-data: 00
9285 16:34:03.665344 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9286 16:34:03.669411 in-header: 03 fd 00 00 00 00 00 00
9287 16:34:03.673547 in-data:
9288 16:34:03.676220 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9289 16:34:03.679975 in-header: 03 fc 00 00 01 00 00 00
9290 16:34:03.683076 in-data: 00
9291 16:34:03.686140 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9292 16:34:03.691401 in-header: 03 fd 00 00 00 00 00 00
9293 16:34:03.694763 in-data:
9294 16:34:03.698066 [SSUSB] Setting up USB HOST controller...
9295 16:34:03.701591 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9296 16:34:03.705115 [SSUSB] phy power-on done.
9297 16:34:03.707818 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9298 16:34:03.714317 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9299 16:34:03.717629 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9300 16:34:03.724327 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9301 16:34:03.730985 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9302 16:34:03.737560 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9303 16:34:03.743842 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9304 16:34:03.750637 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9305 16:34:03.754019 SPM: binary array size = 0x9dc
9306 16:34:03.760749 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9307 16:34:03.763673 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9308 16:34:03.770273 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9309 16:34:03.777056 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9310 16:34:03.779885 configure_display: Starting display init
9311 16:34:03.815118 anx7625_power_on_init: Init interface.
9312 16:34:03.817707 anx7625_disable_pd_protocol: Disabled PD feature.
9313 16:34:03.821075 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9314 16:34:03.849046 anx7625_start_dp_work: Secure OCM version=00
9315 16:34:03.852498 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9316 16:34:03.867618 sp_tx_get_edid_block: EDID Block = 1
9317 16:34:03.970395 Extracted contents:
9318 16:34:03.973166 header: 00 ff ff ff ff ff ff 00
9319 16:34:03.976563 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9320 16:34:03.980091 version: 01 04
9321 16:34:03.983605 basic params: 95 1f 11 78 0a
9322 16:34:03.986624 chroma info: 76 90 94 55 54 90 27 21 50 54
9323 16:34:03.990039 established: 00 00 00
9324 16:34:03.996369 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9325 16:34:03.999726 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9326 16:34:04.006784 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9327 16:34:04.013244 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9328 16:34:04.019400 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9329 16:34:04.022714 extensions: 00
9330 16:34:04.023132 checksum: fb
9331 16:34:04.023628
9332 16:34:04.025847 Manufacturer: IVO Model 57d Serial Number 0
9333 16:34:04.030027 Made week 0 of 2020
9334 16:34:04.032518 EDID version: 1.4
9335 16:34:04.032996 Digital display
9336 16:34:04.036001 6 bits per primary color channel
9337 16:34:04.036426 DisplayPort interface
9338 16:34:04.039553 Maximum image size: 31 cm x 17 cm
9339 16:34:04.042562 Gamma: 220%
9340 16:34:04.043134 Check DPMS levels
9341 16:34:04.045625 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9342 16:34:04.052285 First detailed timing is preferred timing
9343 16:34:04.052802 Established timings supported:
9344 16:34:04.055961 Standard timings supported:
9345 16:34:04.059206 Detailed timings
9346 16:34:04.062420 Hex of detail: 383680a07038204018303c0035ae10000019
9347 16:34:04.069243 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9348 16:34:04.072641 0780 0798 07c8 0820 hborder 0
9349 16:34:04.075486 0438 043b 0447 0458 vborder 0
9350 16:34:04.079004 -hsync -vsync
9351 16:34:04.079426 Did detailed timing
9352 16:34:04.085265 Hex of detail: 000000000000000000000000000000000000
9353 16:34:04.088603 Manufacturer-specified data, tag 0
9354 16:34:04.092174 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9355 16:34:04.095654 ASCII string: InfoVision
9356 16:34:04.098628 Hex of detail: 000000fe00523134304e574635205248200a
9357 16:34:04.101958 ASCII string: R140NWF5 RH
9358 16:34:04.102042 Checksum
9359 16:34:04.105131 Checksum: 0xfb (valid)
9360 16:34:04.108326 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9361 16:34:04.111957 DSI data_rate: 832800000 bps
9362 16:34:04.118032 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9363 16:34:04.121468 anx7625_parse_edid: pixelclock(138800).
9364 16:34:04.124897 hactive(1920), hsync(48), hfp(24), hbp(88)
9365 16:34:04.128413 vactive(1080), vsync(12), vfp(3), vbp(17)
9366 16:34:04.131383 anx7625_dsi_config: config dsi.
9367 16:34:04.137924 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9368 16:34:04.151561 anx7625_dsi_config: success to config DSI
9369 16:34:04.155099 anx7625_dp_start: MIPI phy setup OK.
9370 16:34:04.158263 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9371 16:34:04.161708 mtk_ddp_mode_set invalid vrefresh 60
9372 16:34:04.165085 main_disp_path_setup
9373 16:34:04.165169 ovl_layer_smi_id_en
9374 16:34:04.168396 ovl_layer_smi_id_en
9375 16:34:04.168485 ccorr_config
9376 16:34:04.168550 aal_config
9377 16:34:04.171297 gamma_config
9378 16:34:04.171404 postmask_config
9379 16:34:04.175145 dither_config
9380 16:34:04.178198 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9381 16:34:04.184912 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9382 16:34:04.188293 Root Device init finished in 552 msecs
9383 16:34:04.191049 CPU_CLUSTER: 0 init
9384 16:34:04.197801 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9385 16:34:04.204722 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9386 16:34:04.204806 APU_MBOX 0x190000b0 = 0x10001
9387 16:34:04.208241 APU_MBOX 0x190001b0 = 0x10001
9388 16:34:04.211059 APU_MBOX 0x190005b0 = 0x10001
9389 16:34:04.214630 APU_MBOX 0x190006b0 = 0x10001
9390 16:34:04.220749 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9391 16:34:04.230575 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9392 16:34:04.243151 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9393 16:34:04.250071 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9394 16:34:04.261393 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9395 16:34:04.270122 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9396 16:34:04.273807 CPU_CLUSTER: 0 init finished in 81 msecs
9397 16:34:04.277035 Devices initialized
9398 16:34:04.280065 Show all devs... After init.
9399 16:34:04.280147 Root Device: enabled 1
9400 16:34:04.283826 CPU_CLUSTER: 0: enabled 1
9401 16:34:04.287033 CPU: 00: enabled 1
9402 16:34:04.290167 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9403 16:34:04.293200 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9404 16:34:04.297108 ELOG: NV offset 0x57f000 size 0x1000
9405 16:34:04.303635 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9406 16:34:04.310349 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9407 16:34:04.313140 ELOG: Event(17) added with size 13 at 2024-06-17 16:34:04 UTC
9408 16:34:04.320081 out: cmd=0x121: 03 db 21 01 00 00 00 00
9409 16:34:04.323073 in-header: 03 32 00 00 2c 00 00 00
9410 16:34:04.336155 in-data: 0a 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9411 16:34:04.340212 ELOG: Event(A1) added with size 10 at 2024-06-17 16:34:04 UTC
9412 16:34:04.346413 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9413 16:34:04.353130 ELOG: Event(A0) added with size 9 at 2024-06-17 16:34:04 UTC
9414 16:34:04.356529 elog_add_boot_reason: Logged dev mode boot
9415 16:34:04.362853 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9416 16:34:04.362943 Finalize devices...
9417 16:34:04.366347 Devices finalized
9418 16:34:04.369860 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9419 16:34:04.372602 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9420 16:34:04.375954 in-header: 03 07 00 00 08 00 00 00
9421 16:34:04.379196 in-data: aa e4 47 04 13 02 00 00
9422 16:34:04.382587 Chrome EC: UHEPI supported
9423 16:34:04.389027 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9424 16:34:04.392151 in-header: 03 a9 00 00 08 00 00 00
9425 16:34:04.396203 in-data: 84 60 60 08 00 00 00 00
9426 16:34:04.402852 ELOG: Event(91) added with size 10 at 2024-06-17 16:34:04 UTC
9427 16:34:04.405635 Chrome EC: clear events_b mask to 0x0000000020004000
9428 16:34:04.412173 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9429 16:34:04.416615 in-header: 03 fd 00 00 00 00 00 00
9430 16:34:04.420405 in-data:
9431 16:34:04.423713 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9432 16:34:04.426474 Writing coreboot table at 0xffe64000
9433 16:34:04.433438 0. 000000000010a000-0000000000113fff: RAMSTAGE
9434 16:34:04.436937 1. 0000000040000000-00000000400fffff: RAM
9435 16:34:04.439808 2. 0000000040100000-000000004032afff: RAMSTAGE
9436 16:34:04.443248 3. 000000004032b000-00000000545fffff: RAM
9437 16:34:04.446812 4. 0000000054600000-000000005465ffff: BL31
9438 16:34:04.450263 5. 0000000054660000-00000000ffe63fff: RAM
9439 16:34:04.456453 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9440 16:34:04.459903 7. 0000000100000000-000000023fffffff: RAM
9441 16:34:04.463325 Passing 5 GPIOs to payload:
9442 16:34:04.466770 NAME | PORT | POLARITY | VALUE
9443 16:34:04.473174 EC in RW | 0x000000aa | low | undefined
9444 16:34:04.476649 EC interrupt | 0x00000005 | low | undefined
9445 16:34:04.482948 TPM interrupt | 0x000000ab | high | undefined
9446 16:34:04.486503 SD card detect | 0x00000011 | high | undefined
9447 16:34:04.489826 speaker enable | 0x00000093 | high | undefined
9448 16:34:04.492620 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9449 16:34:04.496689 in-header: 03 f9 00 00 02 00 00 00
9450 16:34:04.500413 in-data: 02 00
9451 16:34:04.503652 ADC[4]: Raw value=904139 ID=7
9452 16:34:04.506960 ADC[3]: Raw value=212912 ID=1
9453 16:34:04.507410 RAM Code: 0x71
9454 16:34:04.510261 ADC[6]: Raw value=75406 ID=0
9455 16:34:04.513102 ADC[5]: Raw value=212912 ID=1
9456 16:34:04.513590 SKU Code: 0x1
9457 16:34:04.519859 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 42bb
9458 16:34:04.520315 coreboot table: 964 bytes.
9459 16:34:04.523312 IMD ROOT 0. 0xfffff000 0x00001000
9460 16:34:04.526585 IMD SMALL 1. 0xffffe000 0x00001000
9461 16:34:04.529859 RO MCACHE 2. 0xffffc000 0x00001104
9462 16:34:04.532803 CONSOLE 3. 0xfff7c000 0x00080000
9463 16:34:04.536557 FMAP 4. 0xfff7b000 0x00000452
9464 16:34:04.539833 TIME STAMP 5. 0xfff7a000 0x00000910
9465 16:34:04.543259 VBOOT WORK 6. 0xfff66000 0x00014000
9466 16:34:04.546132 RAMOOPS 7. 0xffe66000 0x00100000
9467 16:34:04.549645 COREBOOT 8. 0xffe64000 0x00002000
9468 16:34:04.553096 IMD small region:
9469 16:34:04.556016 IMD ROOT 0. 0xffffec00 0x00000400
9470 16:34:04.559460 VPD 1. 0xffffeb80 0x0000006c
9471 16:34:04.563015 MMC STATUS 2. 0xffffeb60 0x00000004
9472 16:34:04.569131 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9473 16:34:04.576182 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9474 16:34:04.614777 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9475 16:34:04.618111 Checking segment from ROM address 0x40100000
9476 16:34:04.620936 Checking segment from ROM address 0x4010001c
9477 16:34:04.627896 Loading segment from ROM address 0x40100000
9478 16:34:04.628357 code (compression=0)
9479 16:34:04.638040 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9480 16:34:04.644258 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9481 16:34:04.644694 it's not compressed!
9482 16:34:04.651194 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9483 16:34:04.657404 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9484 16:34:04.675366 Loading segment from ROM address 0x4010001c
9485 16:34:04.675810 Entry Point 0x80000000
9486 16:34:04.677985 Loaded segments
9487 16:34:04.681416 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9488 16:34:04.688244 Jumping to boot code at 0x80000000(0xffe64000)
9489 16:34:04.694714 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9490 16:34:04.701044 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9491 16:34:04.709447 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9492 16:34:04.712604 Checking segment from ROM address 0x40100000
9493 16:34:04.716103 Checking segment from ROM address 0x4010001c
9494 16:34:04.722662 Loading segment from ROM address 0x40100000
9495 16:34:04.723080 code (compression=1)
9496 16:34:04.728795 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9497 16:34:04.739006 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9498 16:34:04.739565 using LZMA
9499 16:34:04.747347 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9500 16:34:04.754618 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9501 16:34:04.757196 Loading segment from ROM address 0x4010001c
9502 16:34:04.757895 Entry Point 0x54601000
9503 16:34:04.760603 Loaded segments
9504 16:34:04.764129 NOTICE: MT8192 bl31_setup
9505 16:34:04.771060 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9506 16:34:04.774578 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9507 16:34:04.777885 WARNING: region 0:
9508 16:34:04.780807 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 16:34:04.781224 WARNING: region 1:
9510 16:34:04.787762 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9511 16:34:04.791224 WARNING: region 2:
9512 16:34:04.794115 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9513 16:34:04.797606 WARNING: region 3:
9514 16:34:04.804591 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9515 16:34:04.805014 WARNING: region 4:
9516 16:34:04.810515 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9517 16:34:04.810941 WARNING: region 5:
9518 16:34:04.813952 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 16:34:04.817350 WARNING: region 6:
9520 16:34:04.820741 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 16:34:04.824157 WARNING: region 7:
9522 16:34:04.827619 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 16:34:04.834302 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9524 16:34:04.836984 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9525 16:34:04.843915 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9526 16:34:04.847658 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9527 16:34:04.850266 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9528 16:34:04.857347 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9529 16:34:04.860793 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9530 16:34:04.864020 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9531 16:34:04.870658 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9532 16:34:04.873277 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9533 16:34:04.880253 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9534 16:34:04.883570 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9535 16:34:04.887112 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9536 16:34:04.893415 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9537 16:34:04.896751 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9538 16:34:04.900624 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9539 16:34:04.906866 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9540 16:34:04.910058 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9541 16:34:04.916403 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9542 16:34:04.919724 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9543 16:34:04.922742 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9544 16:34:04.929302 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9545 16:34:04.932949 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9546 16:34:04.939543 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9547 16:34:04.942914 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9548 16:34:04.946110 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9549 16:34:04.953133 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9550 16:34:04.955865 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9551 16:34:04.962794 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9552 16:34:04.965548 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9553 16:34:04.972466 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9554 16:34:04.975891 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9555 16:34:04.978681 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9556 16:34:04.982051 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9557 16:34:04.988935 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9558 16:34:04.992117 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9559 16:34:04.995561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9560 16:34:04.999234 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9561 16:34:05.005788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9562 16:34:05.008486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9563 16:34:05.012004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9564 16:34:05.015612 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9565 16:34:05.021969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9566 16:34:05.025559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9567 16:34:05.029066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9568 16:34:05.031718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9569 16:34:05.038388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9570 16:34:05.041576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9571 16:34:05.048669 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9572 16:34:05.052184 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9573 16:34:05.055311 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9574 16:34:05.061642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9575 16:34:05.065015 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9576 16:34:05.071556 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9577 16:34:05.075079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9578 16:34:05.081360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9579 16:34:05.084842 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9580 16:34:05.091209 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9581 16:34:05.094590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9582 16:34:05.097706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9583 16:34:05.104201 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9584 16:34:05.107812 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9585 16:34:05.114006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9586 16:34:05.117565 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9587 16:34:05.124343 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9588 16:34:05.127867 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9589 16:34:05.133897 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9590 16:34:05.137440 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9591 16:34:05.140961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9592 16:34:05.147406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9593 16:34:05.150882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9594 16:34:05.157625 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9595 16:34:05.161002 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9596 16:34:05.167556 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9597 16:34:05.170271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9598 16:34:05.177473 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9599 16:34:05.180295 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9600 16:34:05.183801 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9601 16:34:05.190635 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9602 16:34:05.194124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9603 16:34:05.200354 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9604 16:34:05.203692 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9605 16:34:05.210090 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9606 16:34:05.213341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9607 16:34:05.220532 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9608 16:34:05.223202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9609 16:34:05.226541 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9610 16:34:05.233625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9611 16:34:05.237050 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9612 16:34:05.243607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9613 16:34:05.246967 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9614 16:34:05.252846 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9615 16:34:05.256886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9616 16:34:05.263047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9617 16:34:05.266641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9618 16:34:05.269935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9619 16:34:05.276684 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9620 16:34:05.279755 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9621 16:34:05.283186 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9622 16:34:05.286404 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9623 16:34:05.293001 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9624 16:34:05.296327 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9625 16:34:05.302659 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9626 16:34:05.306146 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9627 16:34:05.309549 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9628 16:34:05.315600 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9629 16:34:05.319000 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9630 16:34:05.325723 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9631 16:34:05.329274 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9632 16:34:05.335904 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9633 16:34:05.339172 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9634 16:34:05.342155 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9635 16:34:05.349131 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9636 16:34:05.352540 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9637 16:34:05.358802 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9638 16:34:05.362348 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9639 16:34:05.365662 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9640 16:34:05.369148 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9641 16:34:05.375672 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9642 16:34:05.378929 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9643 16:34:05.382417 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9644 16:34:05.388482 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9645 16:34:05.391746 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9646 16:34:05.395073 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9647 16:34:05.401632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9648 16:34:05.405399 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9649 16:34:05.408642 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9650 16:34:05.414736 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9651 16:34:05.418119 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9652 16:34:05.425111 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9653 16:34:05.428374 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9654 16:34:05.431450 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9655 16:34:05.438011 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9656 16:34:05.441474 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9657 16:34:05.448001 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9658 16:34:05.451589 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9659 16:34:05.454855 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9660 16:34:05.461564 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9661 16:34:05.464787 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9662 16:34:05.470844 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9663 16:34:05.474260 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9664 16:34:05.477753 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9665 16:34:05.484530 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9666 16:34:05.487658 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9667 16:34:05.490947 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9668 16:34:05.497704 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9669 16:34:05.501113 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9670 16:34:05.507315 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9671 16:34:05.510746 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9672 16:34:05.517480 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9673 16:34:05.520361 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9674 16:34:05.524420 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9675 16:34:05.530511 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9676 16:34:05.534044 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9677 16:34:05.537304 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9678 16:34:05.543808 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9679 16:34:05.547080 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9680 16:34:05.554089 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9681 16:34:05.557434 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9682 16:34:05.560391 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9683 16:34:05.567350 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9684 16:34:05.570215 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9685 16:34:05.577200 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9686 16:34:05.580422 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9687 16:34:05.583295 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9688 16:34:05.590081 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9689 16:34:05.593268 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9690 16:34:05.600061 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9691 16:34:05.603332 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9692 16:34:05.606413 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9693 16:34:05.613138 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9694 16:34:05.616305 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9695 16:34:05.623180 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9696 16:34:05.626577 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9697 16:34:05.629228 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9698 16:34:05.636393 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9699 16:34:05.639211 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9700 16:34:05.646075 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9701 16:34:05.649355 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9702 16:34:05.652549 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9703 16:34:05.658905 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9704 16:34:05.662415 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9705 16:34:05.669318 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9706 16:34:05.672707 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9707 16:34:05.675387 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9708 16:34:05.682353 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9709 16:34:05.685827 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9710 16:34:05.692000 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9711 16:34:05.695551 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9712 16:34:05.699091 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9713 16:34:05.705241 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9714 16:34:05.708565 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9715 16:34:05.714983 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9716 16:34:05.718319 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9717 16:34:05.725124 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9718 16:34:05.728358 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9719 16:34:05.731497 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9720 16:34:05.738511 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9721 16:34:05.741342 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9722 16:34:05.748404 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9723 16:34:05.751805 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9724 16:34:05.757778 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9725 16:34:05.761112 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9726 16:34:05.764464 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9727 16:34:05.771375 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9728 16:34:05.774939 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9729 16:34:05.781197 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9730 16:34:05.784583 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9731 16:34:05.790939 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9732 16:34:05.794602 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9733 16:34:05.797957 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9734 16:34:05.804197 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9735 16:34:05.807603 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9736 16:34:05.814307 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9737 16:34:05.817746 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9738 16:34:05.824323 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9739 16:34:05.827637 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9740 16:34:05.830785 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9741 16:34:05.837209 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9742 16:34:05.840876 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9743 16:34:05.847036 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9744 16:34:05.850592 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9745 16:34:05.857060 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9746 16:34:05.860580 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9747 16:34:05.863385 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9748 16:34:05.869950 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9749 16:34:05.873387 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9750 16:34:05.880406 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9751 16:34:05.883155 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9752 16:34:05.886709 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9753 16:34:05.893704 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9754 16:34:05.896641 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9755 16:34:05.900121 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9756 16:34:05.903569 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9757 16:34:05.909647 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9758 16:34:05.913040 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9759 16:34:05.916557 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9760 16:34:05.923531 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9761 16:34:05.926322 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9762 16:34:05.929733 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9763 16:34:05.936063 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9764 16:34:05.939545 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9765 16:34:05.946551 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9766 16:34:05.949838 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9767 16:34:05.952875 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9768 16:34:05.959299 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9769 16:34:05.962645 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9770 16:34:05.969023 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9771 16:34:05.972488 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9772 16:34:05.975768 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9773 16:34:05.982264 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9774 16:34:05.985620 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9775 16:34:05.989111 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9776 16:34:05.996153 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9777 16:34:05.998705 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9778 16:34:06.005610 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9779 16:34:06.009251 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9780 16:34:06.011816 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9781 16:34:06.018658 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9782 16:34:06.022272 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9783 16:34:06.024973 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9784 16:34:06.032191 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9785 16:34:06.034858 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9786 16:34:06.038471 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9787 16:34:06.044810 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9788 16:34:06.048614 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9789 16:34:06.054682 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9790 16:34:06.058027 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9791 16:34:06.061248 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9792 16:34:06.067862 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9793 16:34:06.071220 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9794 16:34:06.074758 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9795 16:34:06.078298 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9796 16:34:06.080954 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9797 16:34:06.087666 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9798 16:34:06.090845 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9799 16:34:06.094270 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9800 16:34:06.101182 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9801 16:34:06.103873 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9802 16:34:06.107317 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9803 16:34:06.110682 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9804 16:34:06.117171 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9805 16:34:06.120428 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9806 16:34:06.127745 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9807 16:34:06.130469 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9808 16:34:06.134063 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9809 16:34:06.140114 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9810 16:34:06.143491 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9811 16:34:06.149767 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9812 16:34:06.153087 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9813 16:34:06.156485 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9814 16:34:06.162878 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9815 16:34:06.166423 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9816 16:34:06.173136 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9817 16:34:06.176231 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9818 16:34:06.183051 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9819 16:34:06.186522 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9820 16:34:06.189365 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9821 16:34:06.196193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9822 16:34:06.199406 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9823 16:34:06.206216 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9824 16:34:06.209685 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9825 16:34:06.215908 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9826 16:34:06.219529 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9827 16:34:06.222273 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9828 16:34:06.229277 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9829 16:34:06.232741 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9830 16:34:06.239038 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9831 16:34:06.242447 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9832 16:34:06.245935 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9833 16:34:06.252132 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9834 16:34:06.255572 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9835 16:34:06.262646 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9836 16:34:06.265472 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9837 16:34:06.268863 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9838 16:34:06.275708 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9839 16:34:06.278913 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9840 16:34:06.285541 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9841 16:34:06.288483 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9842 16:34:06.295122 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9843 16:34:06.298447 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9844 16:34:06.301828 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9845 16:34:06.308481 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9846 16:34:06.311847 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9847 16:34:06.318084 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9848 16:34:06.321673 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9849 16:34:06.328684 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9850 16:34:06.331841 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9851 16:34:06.335285 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9852 16:34:06.341558 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9853 16:34:06.345093 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9854 16:34:06.351364 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9855 16:34:06.354923 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9856 16:34:06.357791 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9857 16:34:06.364853 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9858 16:34:06.367716 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9859 16:34:06.374613 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9860 16:34:06.377977 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9861 16:34:06.381345 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9862 16:34:06.387593 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9863 16:34:06.391019 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9864 16:34:06.397647 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9865 16:34:06.401436 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9866 16:34:06.407961 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9867 16:34:06.411021 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9868 16:34:06.414383 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9869 16:34:06.421033 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9870 16:34:06.424467 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9871 16:34:06.430951 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9872 16:34:06.433799 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9873 16:34:06.437396 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9874 16:34:06.443840 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9875 16:34:06.447543 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9876 16:34:06.453742 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9877 16:34:06.457179 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9878 16:34:06.464290 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9879 16:34:06.467016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9880 16:34:06.470522 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9881 16:34:06.476800 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9882 16:34:06.480311 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9883 16:34:06.486765 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9884 16:34:06.490272 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9885 16:34:06.497102 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9886 16:34:06.500292 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9887 16:34:06.506934 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9888 16:34:06.510141 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9889 16:34:06.513796 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9890 16:34:06.520347 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9891 16:34:06.522916 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9892 16:34:06.530117 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9893 16:34:06.533478 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9894 16:34:06.539783 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9895 16:34:06.543105 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9896 16:34:06.549464 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9897 16:34:06.552936 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9898 16:34:06.556402 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9899 16:34:06.562658 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9900 16:34:06.566242 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9901 16:34:06.573070 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9902 16:34:06.575847 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9903 16:34:06.582740 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9904 16:34:06.586363 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9905 16:34:06.592949 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9906 16:34:06.595795 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9907 16:34:06.599241 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9908 16:34:06.605759 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9909 16:34:06.609300 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9910 16:34:06.615515 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9911 16:34:06.618911 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9912 16:34:06.625604 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9913 16:34:06.629142 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9914 16:34:06.635191 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9915 16:34:06.638508 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9916 16:34:06.641893 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9917 16:34:06.648459 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9918 16:34:06.651763 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9919 16:34:06.658527 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9920 16:34:06.661383 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9921 16:34:06.668401 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9922 16:34:06.671798 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9923 16:34:06.678315 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9924 16:34:06.681701 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9925 16:34:06.684570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9926 16:34:06.691179 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9927 16:34:06.694564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9928 16:34:06.701619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9929 16:34:06.704873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9930 16:34:06.711080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9931 16:34:06.714694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9932 16:34:06.720812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9933 16:34:06.724159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9934 16:34:06.730939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9935 16:34:06.734531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9936 16:34:06.740681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9937 16:34:06.744206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9938 16:34:06.750492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9939 16:34:06.753964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9940 16:34:06.760401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9941 16:34:06.763484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9942 16:34:06.770571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9943 16:34:06.773996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9944 16:34:06.780506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9945 16:34:06.783320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9946 16:34:06.789756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9947 16:34:06.793300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9948 16:34:06.799711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9949 16:34:06.803196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9950 16:34:06.810095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9951 16:34:06.812991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9952 16:34:06.819369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9953 16:34:06.822982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9954 16:34:06.829509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9955 16:34:06.832955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9956 16:34:06.839111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9957 16:34:06.842611 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9958 16:34:06.846181 INFO: [APUAPC] vio 0
9959 16:34:06.849266 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9960 16:34:06.856116 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9961 16:34:06.859551 INFO: [APUAPC] D0_APC_0: 0x400510
9962 16:34:06.859647 INFO: [APUAPC] D0_APC_1: 0x0
9963 16:34:06.862335 INFO: [APUAPC] D0_APC_2: 0x1540
9964 16:34:06.865755 INFO: [APUAPC] D0_APC_3: 0x0
9965 16:34:06.869034 INFO: [APUAPC] D1_APC_0: 0xffffffff
9966 16:34:06.872403 INFO: [APUAPC] D1_APC_1: 0xffffffff
9967 16:34:06.875643 INFO: [APUAPC] D1_APC_2: 0x3fffff
9968 16:34:06.878762 INFO: [APUAPC] D1_APC_3: 0x0
9969 16:34:06.882151 INFO: [APUAPC] D2_APC_0: 0xffffffff
9970 16:34:06.885632 INFO: [APUAPC] D2_APC_1: 0xffffffff
9971 16:34:06.889176 INFO: [APUAPC] D2_APC_2: 0x3fffff
9972 16:34:06.892643 INFO: [APUAPC] D2_APC_3: 0x0
9973 16:34:06.895459 INFO: [APUAPC] D3_APC_0: 0xffffffff
9974 16:34:06.898979 INFO: [APUAPC] D3_APC_1: 0xffffffff
9975 16:34:06.902586 INFO: [APUAPC] D3_APC_2: 0x3fffff
9976 16:34:06.905355 INFO: [APUAPC] D3_APC_3: 0x0
9977 16:34:06.908917 INFO: [APUAPC] D4_APC_0: 0xffffffff
9978 16:34:06.912301 INFO: [APUAPC] D4_APC_1: 0xffffffff
9979 16:34:06.915563 INFO: [APUAPC] D4_APC_2: 0x3fffff
9980 16:34:06.918882 INFO: [APUAPC] D4_APC_3: 0x0
9981 16:34:06.922511 INFO: [APUAPC] D5_APC_0: 0xffffffff
9982 16:34:06.926046 INFO: [APUAPC] D5_APC_1: 0xffffffff
9983 16:34:06.928727 INFO: [APUAPC] D5_APC_2: 0x3fffff
9984 16:34:06.932221 INFO: [APUAPC] D5_APC_3: 0x0
9985 16:34:06.935466 INFO: [APUAPC] D6_APC_0: 0xffffffff
9986 16:34:06.938908 INFO: [APUAPC] D6_APC_1: 0xffffffff
9987 16:34:06.942157 INFO: [APUAPC] D6_APC_2: 0x3fffff
9988 16:34:06.945698 INFO: [APUAPC] D6_APC_3: 0x0
9989 16:34:06.948533 INFO: [APUAPC] D7_APC_0: 0xffffffff
9990 16:34:06.952226 INFO: [APUAPC] D7_APC_1: 0xffffffff
9991 16:34:06.955090 INFO: [APUAPC] D7_APC_2: 0x3fffff
9992 16:34:06.958392 INFO: [APUAPC] D7_APC_3: 0x0
9993 16:34:06.961668 INFO: [APUAPC] D8_APC_0: 0xffffffff
9994 16:34:06.965337 INFO: [APUAPC] D8_APC_1: 0xffffffff
9995 16:34:06.968547 INFO: [APUAPC] D8_APC_2: 0x3fffff
9996 16:34:06.971411 INFO: [APUAPC] D8_APC_3: 0x0
9997 16:34:06.974979 INFO: [APUAPC] D9_APC_0: 0xffffffff
9998 16:34:06.978369 INFO: [APUAPC] D9_APC_1: 0xffffffff
9999 16:34:06.981552 INFO: [APUAPC] D9_APC_2: 0x3fffff
10000 16:34:06.984834 INFO: [APUAPC] D9_APC_3: 0x0
10001 16:34:06.987646 INFO: [APUAPC] D10_APC_0: 0xffffffff
10002 16:34:06.991324 INFO: [APUAPC] D10_APC_1: 0xffffffff
10003 16:34:06.994666 INFO: [APUAPC] D10_APC_2: 0x3fffff
10004 16:34:06.997399 INFO: [APUAPC] D10_APC_3: 0x0
10005 16:34:07.001066 INFO: [APUAPC] D11_APC_0: 0xffffffff
10006 16:34:07.004483 INFO: [APUAPC] D11_APC_1: 0xffffffff
10007 16:34:07.007462 INFO: [APUAPC] D11_APC_2: 0x3fffff
10008 16:34:07.010962 INFO: [APUAPC] D11_APC_3: 0x0
10009 16:34:07.014436 INFO: [APUAPC] D12_APC_0: 0xffffffff
10010 16:34:07.017945 INFO: [APUAPC] D12_APC_1: 0xffffffff
10011 16:34:07.020598 INFO: [APUAPC] D12_APC_2: 0x3fffff
10012 16:34:07.024094 INFO: [APUAPC] D12_APC_3: 0x0
10013 16:34:07.027662 INFO: [APUAPC] D13_APC_0: 0xffffffff
10014 16:34:07.031056 INFO: [APUAPC] D13_APC_1: 0xffffffff
10015 16:34:07.034575 INFO: [APUAPC] D13_APC_2: 0x3fffff
10016 16:34:07.037220 INFO: [APUAPC] D13_APC_3: 0x0
10017 16:34:07.040546 INFO: [APUAPC] D14_APC_0: 0xffffffff
10018 16:34:07.043820 INFO: [APUAPC] D14_APC_1: 0xffffffff
10019 16:34:07.047627 INFO: [APUAPC] D14_APC_2: 0x3fffff
10020 16:34:07.050811 INFO: [APUAPC] D14_APC_3: 0x0
10021 16:34:07.054208 INFO: [APUAPC] D15_APC_0: 0xffffffff
10022 16:34:07.057642 INFO: [APUAPC] D15_APC_1: 0xffffffff
10023 16:34:07.060870 INFO: [APUAPC] D15_APC_2: 0x3fffff
10024 16:34:07.063579 INFO: [APUAPC] D15_APC_3: 0x0
10025 16:34:07.067453 INFO: [APUAPC] APC_CON: 0x4
10026 16:34:07.070748 INFO: [NOCDAPC] D0_APC_0: 0x0
10027 16:34:07.073639 INFO: [NOCDAPC] D0_APC_1: 0x0
10028 16:34:07.077026 INFO: [NOCDAPC] D1_APC_0: 0x0
10029 16:34:07.080616 INFO: [NOCDAPC] D1_APC_1: 0xfff
10030 16:34:07.080964 INFO: [NOCDAPC] D2_APC_0: 0x0
10031 16:34:07.084154 INFO: [NOCDAPC] D2_APC_1: 0xfff
10032 16:34:07.086748 INFO: [NOCDAPC] D3_APC_0: 0x0
10033 16:34:07.090188 INFO: [NOCDAPC] D3_APC_1: 0xfff
10034 16:34:07.093438 INFO: [NOCDAPC] D4_APC_0: 0x0
10035 16:34:07.096717 INFO: [NOCDAPC] D4_APC_1: 0xfff
10036 16:34:07.099986 INFO: [NOCDAPC] D5_APC_0: 0x0
10037 16:34:07.103272 INFO: [NOCDAPC] D5_APC_1: 0xfff
10038 16:34:07.107003 INFO: [NOCDAPC] D6_APC_0: 0x0
10039 16:34:07.109760 INFO: [NOCDAPC] D6_APC_1: 0xfff
10040 16:34:07.113215 INFO: [NOCDAPC] D7_APC_0: 0x0
10041 16:34:07.113666 INFO: [NOCDAPC] D7_APC_1: 0xfff
10042 16:34:07.116691 INFO: [NOCDAPC] D8_APC_0: 0x0
10043 16:34:07.120099 INFO: [NOCDAPC] D8_APC_1: 0xfff
10044 16:34:07.122697 INFO: [NOCDAPC] D9_APC_0: 0x0
10045 16:34:07.126035 INFO: [NOCDAPC] D9_APC_1: 0xfff
10046 16:34:07.129423 INFO: [NOCDAPC] D10_APC_0: 0x0
10047 16:34:07.132976 INFO: [NOCDAPC] D10_APC_1: 0xfff
10048 16:34:07.136388 INFO: [NOCDAPC] D11_APC_0: 0x0
10049 16:34:07.139107 INFO: [NOCDAPC] D11_APC_1: 0xfff
10050 16:34:07.142507 INFO: [NOCDAPC] D12_APC_0: 0x0
10051 16:34:07.146032 INFO: [NOCDAPC] D12_APC_1: 0xfff
10052 16:34:07.149470 INFO: [NOCDAPC] D13_APC_0: 0x0
10053 16:34:07.152211 INFO: [NOCDAPC] D13_APC_1: 0xfff
10054 16:34:07.156235 INFO: [NOCDAPC] D14_APC_0: 0x0
10055 16:34:07.159548 INFO: [NOCDAPC] D14_APC_1: 0xfff
10056 16:34:07.159648 INFO: [NOCDAPC] D15_APC_0: 0x0
10057 16:34:07.162183 INFO: [NOCDAPC] D15_APC_1: 0xfff
10058 16:34:07.165928 INFO: [NOCDAPC] APC_CON: 0x4
10059 16:34:07.169368 INFO: [APUAPC] set_apusys_apc done
10060 16:34:07.172484 INFO: [DEVAPC] devapc_init done
10061 16:34:07.179117 INFO: GICv3 without legacy support detected.
10062 16:34:07.181933 INFO: ARM GICv3 driver initialized in EL3
10063 16:34:07.185485 INFO: Maximum SPI INTID supported: 639
10064 16:34:07.188870 INFO: BL31: Initializing runtime services
10065 16:34:07.195449 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10066 16:34:07.198932 INFO: SPM: enable CPC mode
10067 16:34:07.201775 INFO: mcdi ready for mcusys-off-idle and system suspend
10068 16:34:07.208469 INFO: BL31: Preparing for EL3 exit to normal world
10069 16:34:07.212023 INFO: Entry point address = 0x80000000
10070 16:34:07.212142 INFO: SPSR = 0x8
10071 16:34:07.218715
10072 16:34:07.218894
10073 16:34:07.219055
10074 16:34:07.222317 Starting depthcharge on Spherion...
10075 16:34:07.222422
10076 16:34:07.222514 Wipe memory regions:
10077 16:34:07.222604
10078 16:34:07.223345 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10079 16:34:07.223481 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10080 16:34:07.223595 Setting prompt string to ['asurada:']
10081 16:34:07.223708 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10082 16:34:07.225786 [0x00000040000000, 0x00000054600000)
10083 16:34:07.347559
10084 16:34:07.347721 [0x00000054660000, 0x00000080000000)
10085 16:34:07.608125
10086 16:34:07.611742 [0x000000821a7280, 0x000000ffe64000)
10087 16:34:08.351973
10088 16:34:08.352564 [0x00000100000000, 0x00000240000000)
10089 16:34:10.239141
10090 16:34:10.241917 Initializing XHCI USB controller at 0x11200000.
10091 16:34:11.281806
10092 16:34:11.284812 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10093 16:34:11.285245
10094 16:34:11.285581
10095 16:34:11.286413 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10097 16:34:11.387630 asurada: tftpboot 192.168.201.1 14396157/tftp-deploy-7i0icuzc/kernel/image.itb 14396157/tftp-deploy-7i0icuzc/kernel/cmdline
10098 16:34:11.388381 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10099 16:34:11.388869 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10100 16:34:11.393532 tftpboot 192.168.201.1 14396157/tftp-deploy-7i0icuzc/kernel/image.itp-deploy-7i0icuzc/kernel/cmdline
10101 16:34:11.394064
10102 16:34:11.394664 Waiting for link
10103 16:34:11.551391
10104 16:34:11.552108 R8152: Initializing
10105 16:34:11.552731
10106 16:34:11.554766 Version 6 (ocp_data = 5c30)
10107 16:34:11.555404
10108 16:34:11.557472 R8152: Done initializing
10109 16:34:11.558107
10110 16:34:11.558673 Adding net device
10111 16:34:13.555046
10112 16:34:13.555790 done.
10113 16:34:13.556358
10114 16:34:13.556835 MAC: 00:e0:4c:68:02:81
10115 16:34:13.557342
10116 16:34:13.558262 Sending DHCP discover... done.
10117 16:34:13.558735
10118 16:34:13.561552 Waiting for reply... done.
10119 16:34:13.561980
10120 16:34:13.565010 Sending DHCP request... done.
10121 16:34:13.565403
10122 16:34:13.568712 Waiting for reply... done.
10123 16:34:13.569345
10124 16:34:13.569877 My ip is 192.168.201.14
10125 16:34:13.570405
10126 16:34:13.572008 The DHCP server ip is 192.168.201.1
10127 16:34:13.572533
10128 16:34:13.578449 TFTP server IP predefined by user: 192.168.201.1
10129 16:34:13.579028
10130 16:34:13.585185 Bootfile predefined by user: 14396157/tftp-deploy-7i0icuzc/kernel/image.itb
10131 16:34:13.585766
10132 16:34:13.588587 Sending tftp read request... done.
10133 16:34:13.589171
10134 16:34:13.594767 Waiting for the transfer...
10135 16:34:13.595188
10136 16:34:14.217883 00000000 ################################################################
10137 16:34:14.218522
10138 16:34:14.810950 00080000 ################################################################
10139 16:34:14.811106
10140 16:34:15.445776 00100000 ################################################################
10141 16:34:15.445955
10142 16:34:16.088079 00180000 ################################################################
10143 16:34:16.088759
10144 16:34:16.725128 00200000 ################################################################
10145 16:34:16.725649
10146 16:34:17.370275 00280000 ################################################################
10147 16:34:17.370818
10148 16:34:17.980110 00300000 ################################################################
10149 16:34:17.980331
10150 16:34:18.618355 00380000 ################################################################
10151 16:34:18.618512
10152 16:34:19.221200 00400000 ################################################################
10153 16:34:19.221356
10154 16:34:19.786072 00480000 ################################################################
10155 16:34:19.786246
10156 16:34:20.410266 00500000 ################################################################
10157 16:34:20.410427
10158 16:34:20.979267 00580000 ################################################################
10159 16:34:20.979406
10160 16:34:21.535742 00600000 ################################################################
10161 16:34:21.535894
10162 16:34:22.091188 00680000 ################################################################
10163 16:34:22.091357
10164 16:34:22.655999 00700000 ################################################################
10165 16:34:22.656208
10166 16:34:23.225692 00780000 ################################################################
10167 16:34:23.225879
10168 16:34:23.779449 00800000 ################################################################
10169 16:34:23.779638
10170 16:34:24.373954 00880000 ################################################################
10171 16:34:24.374127
10172 16:34:24.938745 00900000 ################################################################
10173 16:34:24.938879
10174 16:34:25.557846 00980000 ################################################################
10175 16:34:25.558012
10176 16:34:26.132254 00a00000 ################################################################
10177 16:34:26.132402
10178 16:34:26.756558 00a80000 ################################################################
10179 16:34:26.756765
10180 16:34:27.341309 00b00000 ################################################################
10181 16:34:27.341461
10182 16:34:27.906292 00b80000 ################################################################
10183 16:34:27.906447
10184 16:34:28.526664 00c00000 ################################################################
10185 16:34:28.526810
10186 16:34:29.124987 00c80000 ################################################################
10187 16:34:29.125143
10188 16:34:29.751044 00d00000 ################################################################
10189 16:34:29.751688
10190 16:34:30.368354 00d80000 ################################################################
10191 16:34:30.368601
10192 16:34:30.985063 00e00000 ################################################################
10193 16:34:30.985212
10194 16:34:31.549414 00e80000 ################################################################
10195 16:34:31.549550
10196 16:34:32.098682 00f00000 ################################################################
10197 16:34:32.098862
10198 16:34:32.668209 00f80000 ################################################################
10199 16:34:32.668395
10200 16:34:33.256267 01000000 ################################################################
10201 16:34:33.256962
10202 16:34:33.899196 01080000 ################################################################
10203 16:34:33.899727
10204 16:34:34.462780 01100000 ################################################################
10205 16:34:34.462938
10206 16:34:35.100029 01180000 ################################################################
10207 16:34:35.100178
10208 16:34:35.656461 01200000 ################################################################
10209 16:34:35.656639
10210 16:34:36.215404 01280000 ################################################################
10211 16:34:36.215582
10212 16:34:36.769777 01300000 ################################################################
10213 16:34:36.769983
10214 16:34:37.404309 01380000 ################################################################
10215 16:34:37.404894
10216 16:34:38.016966 01400000 ################################################################
10217 16:34:38.017116
10218 16:34:38.582846 01480000 ################################################################
10219 16:34:38.583002
10220 16:34:39.156239 01500000 ################################################################
10221 16:34:39.156392
10222 16:34:39.719132 01580000 ################################################################
10223 16:34:39.719287
10224 16:34:40.344675 01600000 ################################################################
10225 16:34:40.344839
10226 16:34:40.910607 01680000 ################################################################
10227 16:34:40.910761
10228 16:34:41.507263 01700000 ################################################################
10229 16:34:41.507673
10230 16:34:42.096403 01780000 ################################################################
10231 16:34:42.096552
10232 16:34:42.650484 01800000 ################################################################
10233 16:34:42.650621
10234 16:34:43.238855 01880000 ################################################################
10235 16:34:43.239392
10236 16:34:43.846445 01900000 ################################################################
10237 16:34:43.846649
10238 16:34:44.417852 01980000 ################################################################
10239 16:34:44.418004
10240 16:34:44.974125 01a00000 ################################################################
10241 16:34:44.974309
10242 16:34:45.533436 01a80000 ################################################################
10243 16:34:45.533605
10244 16:34:46.080239 01b00000 ################################################################
10245 16:34:46.080391
10246 16:34:46.619514 01b80000 ################################################################
10247 16:34:46.619669
10248 16:34:47.163047 01c00000 ################################################################
10249 16:34:47.163238
10250 16:34:47.740480 01c80000 ################################################################
10251 16:34:47.741128
10252 16:34:48.373768 01d00000 ################################################################
10253 16:34:48.373934
10254 16:34:48.911555 01d80000 ################################################################
10255 16:34:48.911709
10256 16:34:49.468641 01e00000 ################################################################
10257 16:34:49.469292
10258 16:34:50.014846 01e80000 ################################################################
10259 16:34:50.015036
10260 16:34:50.560126 01f00000 ################################################################
10261 16:34:50.560319
10262 16:34:51.181722 01f80000 ################################################################
10263 16:34:51.181873
10264 16:34:51.764535 02000000 ################################################################
10265 16:34:51.764686
10266 16:34:52.302907 02080000 ################################################################
10267 16:34:52.303075
10268 16:34:52.848809 02100000 ################################################################
10269 16:34:52.848997
10270 16:34:53.389685 02180000 ################################################################
10271 16:34:53.389873
10272 16:34:53.955444 02200000 ################################################################
10273 16:34:53.955621
10274 16:34:54.576149 02280000 ################################################################
10275 16:34:54.576300
10276 16:34:55.142372 02300000 ################################################################
10277 16:34:55.142522
10278 16:34:55.698257 02380000 ################################################################
10279 16:34:55.698407
10280 16:34:56.337721 02400000 ################################################################
10281 16:34:56.337895
10282 16:34:56.982919 02480000 ################################################################
10283 16:34:56.983060
10284 16:34:57.543125 02500000 ################################################################
10285 16:34:57.543301
10286 16:34:58.085894 02580000 ################################################################
10287 16:34:58.086059
10288 16:34:58.623377 02600000 ################################################################
10289 16:34:58.623513
10290 16:34:59.165312 02680000 ################################################################
10291 16:34:59.165477
10292 16:34:59.722439 02700000 ################################################################
10293 16:34:59.722623
10294 16:35:00.279488 02780000 ################################################################
10295 16:35:00.279654
10296 16:35:00.826409 02800000 ################################################################
10297 16:35:00.826566
10298 16:35:01.381205 02880000 ################################################################
10299 16:35:01.381364
10300 16:35:01.932269 02900000 ################################################################
10301 16:35:01.932435
10302 16:35:02.479940 02980000 ################################################################
10303 16:35:02.480201
10304 16:35:03.029214 02a00000 ################################################################
10305 16:35:03.029385
10306 16:35:03.587799 02a80000 ################################################################
10307 16:35:03.587959
10308 16:35:04.193665 02b00000 ################################################################
10309 16:35:04.193821
10310 16:35:04.803923 02b80000 ################################################################
10311 16:35:04.804101
10312 16:35:05.367645 02c00000 ################################################################
10313 16:35:05.367783
10314 16:35:05.968020 02c80000 ################################################################
10315 16:35:05.968168
10316 16:35:06.549523 02d00000 ################################################################
10317 16:35:06.549673
10318 16:35:07.116027 02d80000 ################################################################
10319 16:35:07.116166
10320 16:35:07.673602 02e00000 ################################################################
10321 16:35:07.673754
10322 16:35:08.230627 02e80000 ################################################################
10323 16:35:08.230807
10324 16:35:08.819870 02f00000 ################################################################
10325 16:35:08.820035
10326 16:35:09.418859 02f80000 ################################################################
10327 16:35:09.419011
10328 16:35:09.973325 03000000 ################################################################
10329 16:35:09.973475
10330 16:35:10.516373 03080000 ################################################################
10331 16:35:10.516535
10332 16:35:11.061507 03100000 ################################################################
10333 16:35:11.061677
10334 16:35:11.608599 03180000 ################################################################
10335 16:35:11.608749
10336 16:35:12.150187 03200000 ################################################################
10337 16:35:12.150319
10338 16:35:12.693600 03280000 ################################################################
10339 16:35:12.693747
10340 16:35:13.267837 03300000 ################################################################
10341 16:35:13.267989
10342 16:35:13.693235 03380000 ################################################## done.
10343 16:35:13.693385
10344 16:35:13.696542 The bootfile was 54408266 bytes long.
10345 16:35:13.696633
10346 16:35:13.699927 Sending tftp read request... done.
10347 16:35:13.700011
10348 16:35:13.700076 Waiting for the transfer...
10349 16:35:13.700137
10350 16:35:13.703157 00000000 # done.
10351 16:35:13.703264
10352 16:35:13.709404 Command line loaded dynamically from TFTP file: 14396157/tftp-deploy-7i0icuzc/kernel/cmdline
10353 16:35:13.709501
10354 16:35:13.722534 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10355 16:35:13.722641
10356 16:35:13.725852 Loading FIT.
10357 16:35:13.725954
10358 16:35:13.729232 Image ramdisk-1 has 41230218 bytes.
10359 16:35:13.729344
10360 16:35:13.732601 Image fdt-1 has 47258 bytes.
10361 16:35:13.732685
10362 16:35:13.732750 Image kernel-1 has 13128753 bytes.
10363 16:35:13.735986
10364 16:35:13.742459 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10365 16:35:13.742548
10366 16:35:13.762172 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10367 16:35:13.762309
10368 16:35:13.765554 Choosing best match conf-1 for compat google,spherion-rev2.
10369 16:35:13.770255
10370 16:35:13.774195 Connected to device vid:did:rid of 1ae0:0028:00
10371 16:35:13.781765
10372 16:35:13.785272 tpm_get_response: command 0x17b, return code 0x0
10373 16:35:13.785356
10374 16:35:13.788575 ec_init: CrosEC protocol v3 supported (256, 248)
10375 16:35:13.792468
10376 16:35:13.796022 tpm_cleanup: add release locality here.
10377 16:35:13.796104
10378 16:35:13.796169 Shutting down all USB controllers.
10379 16:35:13.799023
10380 16:35:13.799105 Removing current net device
10381 16:35:13.799171
10382 16:35:13.805542 Exiting depthcharge with code 4 at timestamp: 96037208
10383 16:35:13.805651
10384 16:35:13.808752 LZMA decompressing kernel-1 to 0x821a6718
10385 16:35:13.808833
10386 16:35:13.812187 LZMA decompressing kernel-1 to 0x40000000
10387 16:35:15.429341
10388 16:35:15.429507 jumping to kernel
10389 16:35:15.430608 end: 2.2.4 bootloader-commands (duration 00:01:08) [common]
10390 16:35:15.430743 start: 2.2.5 auto-login-action (timeout 00:03:18) [common]
10391 16:35:15.430850 Setting prompt string to ['Linux version [0-9]']
10392 16:35:15.430983 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10393 16:35:15.431086 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10394 16:35:15.512221
10395 16:35:15.515538 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10396 16:35:15.519082 start: 2.2.5.1 login-action (timeout 00:03:18) [common]
10397 16:35:15.519212 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10398 16:35:15.519315 Setting prompt string to []
10399 16:35:15.519420 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10400 16:35:15.519579 Using line separator: #'\n'#
10401 16:35:15.519668 No login prompt set.
10402 16:35:15.519756 Parsing kernel messages
10403 16:35:15.519845 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10404 16:35:15.520021 [login-action] Waiting for messages, (timeout 00:03:18)
10405 16:35:15.520120 Waiting using forced prompt support (timeout 00:01:39)
10406 16:35:15.538427 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10407 16:35:15.541606 [ 0.000000] random: crng init done
10408 16:35:15.548040 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10409 16:35:15.551547 [ 0.000000] efi: UEFI not found.
10410 16:35:15.558347 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10411 16:35:15.568432 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10412 16:35:15.578287 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10413 16:35:15.584651 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10414 16:35:15.591365 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10415 16:35:15.597435 [ 0.000000] printk: bootconsole [mtk8250] enabled
10416 16:35:15.603997 [ 0.000000] NUMA: No NUMA configuration found
10417 16:35:15.610608 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10418 16:35:15.617127 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10419 16:35:15.617278 [ 0.000000] Zone ranges:
10420 16:35:15.623635 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10421 16:35:15.627451 [ 0.000000] DMA32 empty
10422 16:35:15.633720 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10423 16:35:15.637102 [ 0.000000] Movable zone start for each node
10424 16:35:15.640408 [ 0.000000] Early memory node ranges
10425 16:35:15.646846 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10426 16:35:15.653607 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10427 16:35:15.660154 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10428 16:35:15.666715 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10429 16:35:15.673279 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10430 16:35:15.679961 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10431 16:35:15.736198 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10432 16:35:15.742762 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10433 16:35:15.749061 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10434 16:35:15.752460 [ 0.000000] psci: probing for conduit method from DT.
10435 16:35:15.759329 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10436 16:35:15.762180 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10437 16:35:15.768784 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10438 16:35:15.771992 [ 0.000000] psci: SMC Calling Convention v1.2
10439 16:35:15.779050 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10440 16:35:15.782370 [ 0.000000] Detected VIPT I-cache on CPU0
10441 16:35:15.788842 [ 0.000000] CPU features: detected: GIC system register CPU interface
10442 16:35:15.795205 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10443 16:35:15.801781 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10444 16:35:15.808853 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10445 16:35:15.818571 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10446 16:35:15.825032 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10447 16:35:15.828422 [ 0.000000] alternatives: applying boot alternatives
10448 16:35:15.834921 [ 0.000000] Fallback order for Node 0: 0
10449 16:35:15.841325 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10450 16:35:15.844507 [ 0.000000] Policy zone: Normal
10451 16:35:15.858203 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10452 16:35:15.867877 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10453 16:35:15.880439 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10454 16:35:15.890218 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10455 16:35:15.896628 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10456 16:35:15.899955 <6>[ 0.000000] software IO TLB: area num 8.
10457 16:35:15.956851 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10458 16:35:16.106283 <6>[ 0.000000] Memory: 7923796K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 428972K reserved, 32768K cma-reserved)
10459 16:35:16.112957 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10460 16:35:16.119399 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10461 16:35:16.122839 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10462 16:35:16.129481 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10463 16:35:16.136033 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10464 16:35:16.139246 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10465 16:35:16.149447 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10466 16:35:16.155557 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10467 16:35:16.162415 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10468 16:35:16.168948 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10469 16:35:16.171901 <6>[ 0.000000] GICv3: 608 SPIs implemented
10470 16:35:16.175617 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10471 16:35:16.182311 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10472 16:35:16.185562 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10473 16:35:16.192178 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10474 16:35:16.204993 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10475 16:35:16.218557 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10476 16:35:16.224592 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10477 16:35:16.233076 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10478 16:35:16.246405 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10479 16:35:16.252869 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10480 16:35:16.259381 <6>[ 0.009179] Console: colour dummy device 80x25
10481 16:35:16.269026 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10482 16:35:16.275982 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10483 16:35:16.279111 <6>[ 0.029221] LSM: Security Framework initializing
10484 16:35:16.285484 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10485 16:35:16.295703 <6>[ 0.041972] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10486 16:35:16.305413 <6>[ 0.051387] cblist_init_generic: Setting adjustable number of callback queues.
10487 16:35:16.311985 <6>[ 0.058831] cblist_init_generic: Setting shift to 3 and lim to 1.
10488 16:35:16.318747 <6>[ 0.065171] cblist_init_generic: Setting adjustable number of callback queues.
10489 16:35:16.325073 <6>[ 0.072598] cblist_init_generic: Setting shift to 3 and lim to 1.
10490 16:35:16.328420 <6>[ 0.078997] rcu: Hierarchical SRCU implementation.
10491 16:35:16.334861 <6>[ 0.084013] rcu: Max phase no-delay instances is 1000.
10492 16:35:16.341719 <6>[ 0.091037] EFI services will not be available.
10493 16:35:16.344941 <6>[ 0.096026] smp: Bringing up secondary CPUs ...
10494 16:35:16.353443 <6>[ 0.101073] Detected VIPT I-cache on CPU1
10495 16:35:16.360610 <6>[ 0.101146] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10496 16:35:16.366850 <6>[ 0.101178] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10497 16:35:16.370077 <6>[ 0.101516] Detected VIPT I-cache on CPU2
10498 16:35:16.379891 <6>[ 0.101570] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10499 16:35:16.386487 <6>[ 0.101588] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10500 16:35:16.389738 <6>[ 0.101849] Detected VIPT I-cache on CPU3
10501 16:35:16.396578 <6>[ 0.101895] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10502 16:35:16.402943 <6>[ 0.101909] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10503 16:35:16.409497 <6>[ 0.102210] CPU features: detected: Spectre-v4
10504 16:35:16.412697 <6>[ 0.102217] CPU features: detected: Spectre-BHB
10505 16:35:16.415905 <6>[ 0.102221] Detected PIPT I-cache on CPU4
10506 16:35:16.422483 <6>[ 0.102281] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10507 16:35:16.429140 <6>[ 0.102297] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10508 16:35:16.436151 <6>[ 0.102592] Detected PIPT I-cache on CPU5
10509 16:35:16.442790 <6>[ 0.102655] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10510 16:35:16.449249 <6>[ 0.102671] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10511 16:35:16.452537 <6>[ 0.102953] Detected PIPT I-cache on CPU6
10512 16:35:16.462425 <6>[ 0.103019] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10513 16:35:16.468853 <6>[ 0.103035] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10514 16:35:16.472179 <6>[ 0.103330] Detected PIPT I-cache on CPU7
10515 16:35:16.478924 <6>[ 0.103397] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10516 16:35:16.485394 <6>[ 0.103413] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10517 16:35:16.488764 <6>[ 0.103460] smp: Brought up 1 node, 8 CPUs
10518 16:35:16.495454 <6>[ 0.244964] SMP: Total of 8 processors activated.
10519 16:35:16.501845 <6>[ 0.249915] CPU features: detected: 32-bit EL0 Support
10520 16:35:16.508433 <6>[ 0.255279] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10521 16:35:16.515550 <6>[ 0.264079] CPU features: detected: Common not Private translations
10522 16:35:16.521671 <6>[ 0.270555] CPU features: detected: CRC32 instructions
10523 16:35:16.528130 <6>[ 0.275906] CPU features: detected: RCpc load-acquire (LDAPR)
10524 16:35:16.531395 <6>[ 0.281903] CPU features: detected: LSE atomic instructions
10525 16:35:16.538037 <6>[ 0.287721] CPU features: detected: Privileged Access Never
10526 16:35:16.544665 <6>[ 0.293500] CPU features: detected: RAS Extension Support
10527 16:35:16.551206 <6>[ 0.299108] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10528 16:35:16.554570 <6>[ 0.306377] CPU: All CPU(s) started at EL2
10529 16:35:16.561064 <6>[ 0.310720] alternatives: applying system-wide alternatives
10530 16:35:16.571687 <6>[ 0.321548] devtmpfs: initialized
10531 16:35:16.583935 <6>[ 0.330503] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10532 16:35:16.593598 <6>[ 0.340460] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10533 16:35:16.600283 <6>[ 0.348488] pinctrl core: initialized pinctrl subsystem
10534 16:35:16.603694 <6>[ 0.355178] DMI not present or invalid.
10535 16:35:16.610085 <6>[ 0.359597] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10536 16:35:16.620087 <6>[ 0.366471] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10537 16:35:16.626651 <6>[ 0.374043] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10538 16:35:16.636871 <6>[ 0.382264] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10539 16:35:16.640053 <6>[ 0.390505] audit: initializing netlink subsys (disabled)
10540 16:35:16.649584 <5>[ 0.396200] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10541 16:35:16.656094 <6>[ 0.396918] thermal_sys: Registered thermal governor 'step_wise'
10542 16:35:16.662826 <6>[ 0.404166] thermal_sys: Registered thermal governor 'power_allocator'
10543 16:35:16.665955 <6>[ 0.410421] cpuidle: using governor menu
10544 16:35:16.672723 <6>[ 0.421383] NET: Registered PF_QIPCRTR protocol family
10545 16:35:16.679167 <6>[ 0.426862] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10546 16:35:16.685825 <6>[ 0.433965] ASID allocator initialised with 32768 entries
10547 16:35:16.689178 <6>[ 0.440555] Serial: AMBA PL011 UART driver
10548 16:35:16.699242 <4>[ 0.449428] Trying to register duplicate clock ID: 134
10549 16:35:16.759435 <6>[ 0.512561] KASLR enabled
10550 16:35:16.773538 <6>[ 0.520304] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10551 16:35:16.780158 <6>[ 0.527315] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10552 16:35:16.786790 <6>[ 0.533806] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10553 16:35:16.793427 <6>[ 0.540809] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10554 16:35:16.800045 <6>[ 0.547296] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10555 16:35:16.806777 <6>[ 0.554298] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10556 16:35:16.812828 <6>[ 0.560785] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10557 16:35:16.819540 <6>[ 0.567791] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10558 16:35:16.822883 <6>[ 0.575217] ACPI: Interpreter disabled.
10559 16:35:16.831492 <6>[ 0.581657] iommu: Default domain type: Translated
10560 16:35:16.838147 <6>[ 0.586805] iommu: DMA domain TLB invalidation policy: strict mode
10561 16:35:16.841433 <5>[ 0.593467] SCSI subsystem initialized
10562 16:35:16.848060 <6>[ 0.597714] usbcore: registered new interface driver usbfs
10563 16:35:16.854902 <6>[ 0.603446] usbcore: registered new interface driver hub
10564 16:35:16.857863 <6>[ 0.609000] usbcore: registered new device driver usb
10565 16:35:16.865075 <6>[ 0.615119] pps_core: LinuxPPS API ver. 1 registered
10566 16:35:16.875070 <6>[ 0.620314] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10567 16:35:16.878116 <6>[ 0.629658] PTP clock support registered
10568 16:35:16.881340 <6>[ 0.633900] EDAC MC: Ver: 3.0.0
10569 16:35:16.889271 <6>[ 0.639087] FPGA manager framework
10570 16:35:16.895852 <6>[ 0.642765] Advanced Linux Sound Architecture Driver Initialized.
10571 16:35:16.899206 <6>[ 0.649548] vgaarb: loaded
10572 16:35:16.905545 <6>[ 0.652704] clocksource: Switched to clocksource arch_sys_counter
10573 16:35:16.908788 <5>[ 0.659142] VFS: Disk quotas dquot_6.6.0
10574 16:35:16.915497 <6>[ 0.663329] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10575 16:35:16.918845 <6>[ 0.670520] pnp: PnP ACPI: disabled
10576 16:35:16.927375 <6>[ 0.677240] NET: Registered PF_INET protocol family
10577 16:35:16.937168 <6>[ 0.682833] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10578 16:35:16.948481 <6>[ 0.695166] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10579 16:35:16.958431 <6>[ 0.703981] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10580 16:35:16.964694 <6>[ 0.711950] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10581 16:35:16.974417 <6>[ 0.720649] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10582 16:35:16.981517 <6>[ 0.730396] TCP: Hash tables configured (established 65536 bind 65536)
10583 16:35:16.987710 <6>[ 0.737268] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10584 16:35:16.997682 <6>[ 0.744470] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10585 16:35:17.004475 <6>[ 0.752177] NET: Registered PF_UNIX/PF_LOCAL protocol family
10586 16:35:17.011026 <6>[ 0.758326] RPC: Registered named UNIX socket transport module.
10587 16:35:17.014325 <6>[ 0.764477] RPC: Registered udp transport module.
10588 16:35:17.021053 <6>[ 0.769409] RPC: Registered tcp transport module.
10589 16:35:17.027672 <6>[ 0.774341] RPC: Registered tcp NFSv4.1 backchannel transport module.
10590 16:35:17.030521 <6>[ 0.781007] PCI: CLS 0 bytes, default 64
10591 16:35:17.033888 <6>[ 0.785371] Unpacking initramfs...
10592 16:35:17.043919 <6>[ 0.789092] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10593 16:35:17.050542 <6>[ 0.797718] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10594 16:35:17.057160 <6>[ 0.806515] kvm [1]: IPA Size Limit: 40 bits
10595 16:35:17.060467 <6>[ 0.811042] kvm [1]: GICv3: no GICV resource entry
10596 16:35:17.067055 <6>[ 0.816063] kvm [1]: disabling GICv2 emulation
10597 16:35:17.073559 <6>[ 0.820747] kvm [1]: GIC system register CPU interface enabled
10598 16:35:17.076763 <6>[ 0.826911] kvm [1]: vgic interrupt IRQ18
10599 16:35:17.083214 <6>[ 0.832763] kvm [1]: VHE mode initialized successfully
10600 16:35:17.089475 <5>[ 0.839129] Initialise system trusted keyrings
10601 16:35:17.096443 <6>[ 0.843923] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10602 16:35:17.103900 <6>[ 0.853918] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10603 16:35:17.110907 <5>[ 0.860257] NFS: Registering the id_resolver key type
10604 16:35:17.113604 <5>[ 0.865557] Key type id_resolver registered
10605 16:35:17.120390 <5>[ 0.869970] Key type id_legacy registered
10606 16:35:17.126802 <6>[ 0.874251] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10607 16:35:17.133899 <6>[ 0.881172] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10608 16:35:17.140418 <6>[ 0.888882] 9p: Installing v9fs 9p2000 file system support
10609 16:35:17.176679 <5>[ 0.926673] Key type asymmetric registered
10610 16:35:17.179837 <5>[ 0.931004] Asymmetric key parser 'x509' registered
10611 16:35:17.190021 <6>[ 0.936139] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10612 16:35:17.193028 <6>[ 0.943751] io scheduler mq-deadline registered
10613 16:35:17.196777 <6>[ 0.948514] io scheduler kyber registered
10614 16:35:17.215139 <6>[ 0.965415] EINJ: ACPI disabled.
10615 16:35:17.248246 <4>[ 0.991784] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10616 16:35:17.258109 <4>[ 1.002400] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10617 16:35:17.273534 <6>[ 1.023397] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10618 16:35:17.281142 <6>[ 1.031325] printk: console [ttyS0] disabled
10619 16:35:17.309209 <6>[ 1.055951] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10620 16:35:17.316077 <6>[ 1.065427] printk: console [ttyS0] enabled
10621 16:35:17.319387 <6>[ 1.065427] printk: console [ttyS0] enabled
10622 16:35:17.325942 <6>[ 1.074321] printk: bootconsole [mtk8250] disabled
10623 16:35:17.329059 <6>[ 1.074321] printk: bootconsole [mtk8250] disabled
10624 16:35:17.335905 <6>[ 1.085342] SuperH (H)SCI(F) driver initialized
10625 16:35:17.339178 <6>[ 1.090599] msm_serial: driver initialized
10626 16:35:17.352792 <6>[ 1.099539] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10627 16:35:17.363138 <6>[ 1.108084] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10628 16:35:17.369762 <6>[ 1.116628] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10629 16:35:17.379514 <6>[ 1.125257] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10630 16:35:17.389506 <6>[ 1.133964] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10631 16:35:17.396144 <6>[ 1.142683] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10632 16:35:17.406046 <6>[ 1.151223] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10633 16:35:17.412204 <6>[ 1.160017] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10634 16:35:17.422490 <6>[ 1.168559] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10635 16:35:17.433957 <6>[ 1.184025] loop: module loaded
10636 16:35:17.440809 <6>[ 1.189986] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10637 16:35:17.463296 <4>[ 1.213040] mtk-pmic-keys: Failed to locate of_node [id: -1]
10638 16:35:17.469889 <6>[ 1.219787] megasas: 07.719.03.00-rc1
10639 16:35:17.479949 <6>[ 1.229462] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10640 16:35:17.486558 <6>[ 1.236096] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10641 16:35:17.502079 <6>[ 1.251980] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10642 16:35:17.560686 <6>[ 1.303980] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10643 16:35:18.749178 <6>[ 2.499468] Freeing initrd memory: 40260K
10644 16:35:18.760962 <6>[ 2.511344] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10645 16:35:18.772709 <6>[ 2.522508] tun: Universal TUN/TAP device driver, 1.6
10646 16:35:18.776005 <6>[ 2.528577] thunder_xcv, ver 1.0
10647 16:35:18.779234 <6>[ 2.532084] thunder_bgx, ver 1.0
10648 16:35:18.782544 <6>[ 2.535583] nicpf, ver 1.0
10649 16:35:18.792969 <6>[ 2.539607] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10650 16:35:18.796224 <6>[ 2.547083] hns3: Copyright (c) 2017 Huawei Corporation.
10651 16:35:18.802713 <6>[ 2.552676] hclge is initializing
10652 16:35:18.806109 <6>[ 2.556258] e1000: Intel(R) PRO/1000 Network Driver
10653 16:35:18.812532 <6>[ 2.561388] e1000: Copyright (c) 1999-2006 Intel Corporation.
10654 16:35:18.815689 <6>[ 2.567401] e1000e: Intel(R) PRO/1000 Network Driver
10655 16:35:18.822888 <6>[ 2.572616] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10656 16:35:18.829532 <6>[ 2.578802] igb: Intel(R) Gigabit Ethernet Network Driver
10657 16:35:18.835987 <6>[ 2.584452] igb: Copyright (c) 2007-2014 Intel Corporation.
10658 16:35:18.842636 <6>[ 2.590289] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10659 16:35:18.849052 <6>[ 2.596806] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10660 16:35:18.852257 <6>[ 2.603267] sky2: driver version 1.30
10661 16:35:18.858789 <6>[ 2.608199] usbcore: registered new device driver r8152-cfgselector
10662 16:35:18.865538 <6>[ 2.614737] usbcore: registered new interface driver r8152
10663 16:35:18.871726 <6>[ 2.620557] VFIO - User Level meta-driver version: 0.3
10664 16:35:18.878749 <6>[ 2.628833] usbcore: registered new interface driver usb-storage
10665 16:35:18.885190 <6>[ 2.635276] usbcore: registered new device driver onboard-usb-hub
10666 16:35:18.894191 <6>[ 2.644454] mt6397-rtc mt6359-rtc: registered as rtc0
10667 16:35:18.903943 <6>[ 2.649922] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:35:18 UTC (1718642118)
10668 16:35:18.907224 <6>[ 2.659492] i2c_dev: i2c /dev entries driver
10669 16:35:18.921724 <4>[ 2.671619] cpu cpu0: supply cpu not found, using dummy regulator
10670 16:35:18.928226 <4>[ 2.678071] cpu cpu1: supply cpu not found, using dummy regulator
10671 16:35:18.934929 <4>[ 2.684474] cpu cpu2: supply cpu not found, using dummy regulator
10672 16:35:18.941271 <4>[ 2.690881] cpu cpu3: supply cpu not found, using dummy regulator
10673 16:35:18.947779 <4>[ 2.697281] cpu cpu4: supply cpu not found, using dummy regulator
10674 16:35:18.954407 <4>[ 2.703681] cpu cpu5: supply cpu not found, using dummy regulator
10675 16:35:18.960676 <4>[ 2.710094] cpu cpu6: supply cpu not found, using dummy regulator
10676 16:35:18.967477 <4>[ 2.716490] cpu cpu7: supply cpu not found, using dummy regulator
10677 16:35:18.987125 <6>[ 2.737092] cpu cpu0: EM: created perf domain
10678 16:35:18.990114 <6>[ 2.742038] cpu cpu4: EM: created perf domain
10679 16:35:18.997582 <6>[ 2.747655] sdhci: Secure Digital Host Controller Interface driver
10680 16:35:19.004137 <6>[ 2.754088] sdhci: Copyright(c) Pierre Ossman
10681 16:35:19.010770 <6>[ 2.759041] Synopsys Designware Multimedia Card Interface Driver
10682 16:35:19.017268 <6>[ 2.765673] sdhci-pltfm: SDHCI platform and OF driver helper
10683 16:35:19.020530 <6>[ 2.765687] mmc0: CQHCI version 5.10
10684 16:35:19.027588 <6>[ 2.775881] ledtrig-cpu: registered to indicate activity on CPUs
10685 16:35:19.034168 <6>[ 2.783011] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10686 16:35:19.040676 <6>[ 2.790070] usbcore: registered new interface driver usbhid
10687 16:35:19.043842 <6>[ 2.795891] usbhid: USB HID core driver
10688 16:35:19.050621 <6>[ 2.800082] spi_master spi0: will run message pump with realtime priority
10689 16:35:19.096822 <6>[ 2.840256] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10690 16:35:19.115904 <6>[ 2.856299] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10691 16:35:19.119253 <6>[ 2.868481] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10692 16:35:19.127721 <6>[ 2.877856] cros-ec-spi spi0.0: Chrome EC device registered
10693 16:35:19.134836 <6>[ 2.883885] mmc0: Command Queue Engine enabled
10694 16:35:19.141437 <6>[ 2.888662] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10695 16:35:19.144628 <6>[ 2.896350] mmcblk0: mmc0:0001 DA4128 116 GiB
10696 16:35:19.157516 <6>[ 2.907695] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10697 16:35:19.167688 <6>[ 2.911398] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10698 16:35:19.174109 <6>[ 2.915057] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10699 16:35:19.177610 <6>[ 2.924231] NET: Registered PF_PACKET protocol family
10700 16:35:19.184229 <6>[ 2.928938] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10701 16:35:19.187276 <6>[ 2.933536] 9pnet: Installing 9P2000 support
10702 16:35:19.193739 <6>[ 2.939371] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10703 16:35:19.200510 <5>[ 2.943225] Key type dns_resolver registered
10704 16:35:19.203835 <6>[ 2.954657] registered taskstats version 1
10705 16:35:19.210563 <5>[ 2.959039] Loading compiled-in X.509 certificates
10706 16:35:19.238424 <4>[ 2.981665] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10707 16:35:19.248193 <4>[ 2.992559] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10708 16:35:19.262552 <6>[ 3.013004] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10709 16:35:19.269712 <6>[ 3.019858] xhci-mtk 11200000.usb: xHCI Host Controller
10710 16:35:19.276128 <6>[ 3.025354] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10711 16:35:19.286649 <6>[ 3.033212] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10712 16:35:19.293347 <6>[ 3.042647] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10713 16:35:19.299576 <6>[ 3.048747] xhci-mtk 11200000.usb: xHCI Host Controller
10714 16:35:19.306129 <6>[ 3.054228] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10715 16:35:19.312846 <6>[ 3.061877] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10716 16:35:19.319307 <6>[ 3.069510] hub 1-0:1.0: USB hub found
10717 16:35:19.322995 <6>[ 3.073526] hub 1-0:1.0: 1 port detected
10718 16:35:19.329630 <6>[ 3.077799] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10719 16:35:19.336093 <6>[ 3.086316] hub 2-0:1.0: USB hub found
10720 16:35:19.339526 <6>[ 3.090322] hub 2-0:1.0: 1 port detected
10721 16:35:19.347209 <6>[ 3.097502] mtk-msdc 11f70000.mmc: Got CD GPIO
10722 16:35:19.364547 <6>[ 3.111471] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10723 16:35:19.374357 <6>[ 3.119859] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10724 16:35:19.381035 <6>[ 3.128199] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10725 16:35:19.390779 <6>[ 3.136537] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10726 16:35:19.397910 <6>[ 3.144877] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10727 16:35:19.407608 <6>[ 3.153217] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10728 16:35:19.413824 <6>[ 3.161555] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10729 16:35:19.424307 <6>[ 3.169894] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10730 16:35:19.430540 <6>[ 3.178231] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10731 16:35:19.440724 <6>[ 3.186570] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10732 16:35:19.447270 <6>[ 3.194908] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10733 16:35:19.456956 <6>[ 3.203253] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10734 16:35:19.463896 <6>[ 3.211592] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10735 16:35:19.473767 <6>[ 3.219929] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10736 16:35:19.480201 <6>[ 3.228266] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10737 16:35:19.486909 <6>[ 3.236987] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10738 16:35:19.494103 <6>[ 3.244143] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10739 16:35:19.500904 <6>[ 3.250948] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10740 16:35:19.510708 <6>[ 3.257714] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10741 16:35:19.517553 <6>[ 3.264684] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10742 16:35:19.523995 <6>[ 3.271542] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10743 16:35:19.534062 <6>[ 3.280674] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10744 16:35:19.543649 <6>[ 3.289793] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10745 16:35:19.553510 <6>[ 3.299088] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10746 16:35:19.563408 <6>[ 3.308555] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10747 16:35:19.573784 <6>[ 3.318022] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10748 16:35:19.580449 <6>[ 3.327142] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10749 16:35:19.590193 <6>[ 3.336611] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10750 16:35:19.600248 <6>[ 3.345731] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10751 16:35:19.609936 <6>[ 3.355030] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10752 16:35:19.619603 <6>[ 3.365189] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10753 16:35:19.629747 <6>[ 3.376944] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10754 16:35:19.749764 <6>[ 3.496961] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10755 16:35:19.904871 <6>[ 3.654844] hub 1-1:1.0: USB hub found
10756 16:35:19.908104 <6>[ 3.659389] hub 1-1:1.0: 4 ports detected
10757 16:35:19.919919 <6>[ 3.670173] hub 1-1:1.0: USB hub found
10758 16:35:19.923373 <6>[ 3.674617] hub 1-1:1.0: 4 ports detected
10759 16:35:20.030124 <6>[ 3.777199] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10760 16:35:20.056704 <6>[ 3.806948] hub 2-1:1.0: USB hub found
10761 16:35:20.059907 <6>[ 3.811473] hub 2-1:1.0: 3 ports detected
10762 16:35:20.071506 <6>[ 3.821969] hub 2-1:1.0: USB hub found
10763 16:35:20.074703 <6>[ 3.826421] hub 2-1:1.0: 3 ports detected
10764 16:35:20.245789 <6>[ 3.993016] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10765 16:35:20.378695 <6>[ 4.128849] hub 1-1.4:1.0: USB hub found
10766 16:35:20.381888 <6>[ 4.133513] hub 1-1.4:1.0: 2 ports detected
10767 16:35:20.394374 <6>[ 4.144905] hub 1-1.4:1.0: USB hub found
10768 16:35:20.398099 <6>[ 4.149432] hub 1-1.4:1.0: 2 ports detected
10769 16:35:20.458407 <6>[ 4.205149] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10770 16:35:20.566352 <6>[ 4.313647] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10771 16:35:20.603120 <4>[ 4.350118] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10772 16:35:20.612848 <4>[ 4.359291] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10773 16:35:20.652432 <6>[ 4.402543] r8152 2-1.3:1.0 eth0: v1.12.13
10774 16:35:20.693706 <6>[ 4.440799] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10775 16:35:20.882116 <6>[ 4.629011] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10776 16:35:22.265534 <6>[ 6.015943] r8152 2-1.3:1.0 eth0: carrier on
10777 16:35:24.442121 <5>[ 6.040795] Sending DHCP requests .., OK
10778 16:35:24.448564 <6>[ 8.197143] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10779 16:35:24.452040 <6>[ 8.205479] IP-Config: Complete:
10780 16:35:24.464970 <6>[ 8.208972] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10781 16:35:24.471666 <6>[ 8.219684] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10782 16:35:24.478180 <6>[ 8.228302] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10783 16:35:24.485007 <6>[ 8.228311] nameserver0=192.168.201.1
10784 16:35:24.488315 <6>[ 8.240431] clk: Disabling unused clocks
10785 16:35:24.491739 <6>[ 8.245964] ALSA device list:
10786 16:35:24.498446 <6>[ 8.249215] No soundcards found.
10787 16:35:24.506575 <6>[ 8.257082] Freeing unused kernel memory: 8512K
10788 16:35:24.509252 <6>[ 8.262097] Run /init as init process
10789 16:35:24.543552 <6>[ 8.294135] NET: Registered PF_INET6 protocol family
10790 16:35:24.550154 <6>[ 8.300918] Segment Routing with IPv6
10791 16:35:24.553512 <6>[ 8.305074] In-situ OAM (IOAM) with IPv6
10792 16:35:24.595265 <30>[ 8.319329] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10793 16:35:24.601352 <30>[ 8.352386] systemd[1]: Detected architecture arm64.
10794 16:35:24.601452
10795 16:35:24.608156 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10796 16:35:24.608245
10797 16:35:24.622084 <30>[ 8.373083] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10798 16:35:24.740475 <30>[ 8.487947] systemd[1]: Queued start job for default target graphical.target.
10799 16:35:24.783506 <30>[ 8.530788] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10800 16:35:24.789550 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10801 16:35:24.809762 <30>[ 8.557401] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10802 16:35:24.819563 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10803 16:35:24.839000 <30>[ 8.586594] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10804 16:35:24.848972 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10805 16:35:24.866772 <30>[ 8.614398] systemd[1]: Created slice user.slice - User and Session Slice.
10806 16:35:24.873529 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10807 16:35:24.897509 <30>[ 8.641599] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10808 16:35:24.907380 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10809 16:35:24.925192 <30>[ 8.669125] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10810 16:35:24.931368 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10811 16:35:24.959590 <30>[ 8.697165] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10812 16:35:24.969472 <30>[ 8.717066] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10813 16:35:24.976158 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10814 16:35:24.993517 <30>[ 8.741032] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10815 16:35:24.999968 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10816 16:35:25.017640 <30>[ 8.765049] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10817 16:35:25.027095 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10818 16:35:25.042522 <30>[ 8.793547] systemd[1]: Reached target paths.target - Path Units.
10819 16:35:25.053105 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10820 16:35:25.070256 <30>[ 8.817451] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10821 16:35:25.076450 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10822 16:35:25.090444 <30>[ 8.840992] systemd[1]: Reached target slices.target - Slice Units.
10823 16:35:25.100071 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10824 16:35:25.114414 <30>[ 8.865070] systemd[1]: Reached target swap.target - Swaps.
10825 16:35:25.121205 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10826 16:35:25.141934 <30>[ 8.889529] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10827 16:35:25.151925 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10828 16:35:25.170786 <30>[ 8.917933] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10829 16:35:25.180213 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10830 16:35:25.199026 <30>[ 8.946239] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10831 16:35:25.208707 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10832 16:35:25.226148 <30>[ 8.973588] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10833 16:35:25.235898 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10834 16:35:25.254776 <30>[ 9.002382] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10835 16:35:25.261538 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10836 16:35:25.282440 <30>[ 9.029755] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10837 16:35:25.291874 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10838 16:35:25.310533 <30>[ 9.058308] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10839 16:35:25.320338 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10840 16:35:25.338387 <30>[ 9.086125] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10841 16:35:25.348463 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10842 16:35:25.389281 <30>[ 9.137056] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10843 16:35:25.395780 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10844 16:35:25.415339 <30>[ 9.163072] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10845 16:35:25.422569 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10846 16:35:25.444354 <30>[ 9.191862] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10847 16:35:25.451178 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10848 16:35:25.476647 <30>[ 9.217361] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10849 16:35:25.518247 <30>[ 9.265757] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10850 16:35:25.527932 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10851 16:35:25.550624 <30>[ 9.298330] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10852 16:35:25.557591 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10853 16:35:25.614062 <30>[ 9.361686] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10854 16:35:25.624063 Startin<6>[ 9.371065] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10855 16:35:25.630872 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10856 16:35:25.654662 <30>[ 9.402275] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10857 16:35:25.661201 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10858 16:35:25.687231 <30>[ 9.434538] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10859 16:35:25.696599 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10860 16:35:25.753828 <30>[ 9.501651] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10861 16:35:25.760809 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10862 16:35:25.790924 <30>[ 9.537982] systemd[1]: Starting systemd-journald.service - Journal Service...
10863 16:35:25.796808 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10864 16:35:25.834729 <30>[ 9.582102] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10865 16:35:25.841332 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10866 16:35:25.869814 <30>[ 9.614017] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10867 16:35:25.876482 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10868 16:35:25.896072 <30>[ 9.643733] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10869 16:35:25.905910 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10870 16:35:25.925217 <30>[ 9.672611] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10871 16:35:25.934814 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10872 16:35:25.959961 <30>[ 9.707747] systemd[1]: Started systemd-journald.service - Journal Service.
10873 16:35:25.966652 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10874 16:35:25.989139 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10875 16:35:26.006119 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10876 16:35:26.022265 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10877 16:35:26.039295 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10878 16:35:26.060420 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10879 16:35:26.080775 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10880 16:35:26.099974 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10881 16:35:26.120298 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10882 16:35:26.140894 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10883 16:35:26.160475 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10884 16:35:26.183506 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10885 16:35:26.204088 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10886 16:35:26.222338 See 'systemctl status systemd-remount-fs.service' for details.
10887 16:35:26.242845 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10888 16:35:26.268172 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10889 16:35:26.338059 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10890 16:35:26.362792 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10891 16:35:26.383726 <46>[ 10.131220] systemd-journald[192]: Received client request to flush runtime journal.
10892 16:35:26.396983 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10893 16:35:26.420874 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10894 16:35:26.444942 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10895 16:35:26.475632 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10896 16:35:26.499198 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10897 16:35:26.523146 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10898 16:35:26.546993 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10899 16:35:26.566928 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10900 16:35:26.609301 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10901 16:35:26.632029 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10902 16:35:26.649572 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10903 16:35:26.664979 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10904 16:35:26.701818 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10905 16:35:26.721798 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10906 16:35:26.741484 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10907 16:35:26.773056 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10908 16:35:26.795566 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10909 16:35:26.815892 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10910 16:35:26.877079 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10911 16:35:26.900771 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10912 16:35:26.929884 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10913 16:35:27.029897 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10914 16:35:27.046053 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10915 16:35:27.066865 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10916 16:35:27.086944 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10917 16:35:27.105806 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10918 16:35:27.134185 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message<6>[ 10.881406] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10919 16:35:27.134347 Bus Socket.
10920 16:35:27.144382 <3>[ 10.882552] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 16:35:27.150714 <6>[ 10.898008] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10922 16:35:27.160620 <3>[ 10.899836] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10923 16:35:27.166922 <6>[ 10.908625] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10924 16:35:27.176871 <6>[ 10.910244] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10925 16:35:27.183582 <6>[ 10.910286] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10926 16:35:27.193684 <6>[ 10.910293] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10927 16:35:27.199996 <3>[ 10.916179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10928 16:35:27.210055 <6>[ 10.918015] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10929 16:35:27.216753 <4>[ 10.924509] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10930 16:35:27.226800 <3>[ 10.936147] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10931 16:35:27.233353 <6>[ 10.941005] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10932 16:35:27.240469 <4>[ 10.942711] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10933 16:35:27.247053 <6>[ 10.945484] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10934 16:35:27.256744 <4>[ 10.945564] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10935 16:35:27.263173 <3>[ 10.948948] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10936 16:35:27.274201 <4>[ 10.950789] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10937 16:35:27.277451 <4>[ 10.950789] Fallback method does not support PEC.
10938 16:35:27.286858 <6>[ 10.957181] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10939 16:35:27.290139 <6>[ 10.962348] remoteproc remoteproc0: scp is available
10940 16:35:27.296874 <6>[ 10.962494] remoteproc remoteproc0: powering up scp
10941 16:35:27.303465 <6>[ 10.962507] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10942 16:35:27.310758 <6>[ 10.962524] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10943 16:35:27.317983 <3>[ 10.964827] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10944 16:35:27.324931 <6>[ 10.981829] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10945 16:35:27.334544 <3>[ 10.981871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10946 16:35:27.341017 <6>[ 10.989964] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10947 16:35:27.351844 <3>[ 10.997231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10948 16:35:27.358330 <3>[ 11.004542] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 16:35:27.368083 <6>[ 11.004575] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10950 16:35:27.375589 <6>[ 11.004583] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10951 16:35:27.382527 <3>[ 11.020807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10952 16:35:27.393216 <3>[ 11.027746] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 16:35:27.397163 <6>[ 11.036287] mc: Linux media interface: v0.10
10954 16:35:27.407129 <3>[ 11.043633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10955 16:35:27.413735 <6>[ 11.054909] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10956 16:35:27.421149 <6>[ 11.058342] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10957 16:35:27.430494 <3>[ 11.060553] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10958 16:35:27.437047 <3>[ 11.060557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10959 16:35:27.444041 <6>[ 11.066285] pci_bus 0000:00: root bus resource [bus 00-ff]
10960 16:35:27.454138 <3>[ 11.069766] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 16:35:27.460729 <3>[ 11.070662] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10962 16:35:27.467462 <3>[ 11.074431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10963 16:35:27.474209 <6>[ 11.082223] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10964 16:35:27.484383 <6>[ 11.088031] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10965 16:35:27.490897 <6>[ 11.088040] remoteproc remoteproc0: remote processor scp is now up
10966 16:35:27.497499 <6>[ 11.088039] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10967 16:35:27.504178 <3>[ 11.090293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10968 16:35:27.514351 <3>[ 11.090296] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10969 16:35:27.525159 <6>[ 11.098115] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10970 16:35:27.531228 <3>[ 11.106190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10971 16:35:27.541760 <3>[ 11.109577] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 16:35:27.548416 <6>[ 11.115091] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10973 16:35:27.554963 <3>[ 11.122778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10974 16:35:27.561203 <3>[ 11.122804] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10975 16:35:27.571819 <6>[ 11.131919] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10976 16:35:27.581819 <6>[ 11.133308] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10977 16:35:27.588433 <6>[ 11.133690] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10978 16:35:27.595621 <6>[ 11.149429] videodev: Linux video capture interface: v2.00
10979 16:35:27.601855 <6>[ 11.150787] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10980 16:35:27.612032 <6>[ 11.152887] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10981 16:35:27.615376 <6>[ 11.153704] pci 0000:00:00.0: supports D1 D2
10982 16:35:27.625459 <3>[ 11.164846] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 16:35:27.634892 <3>[ 11.165517] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10984 16:35:27.641623 <6>[ 11.169139] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10985 16:35:27.644928 <6>[ 11.169332] Bluetooth: Core ver 2.22
10986 16:35:27.651575 <6>[ 11.169383] NET: Registered PF_BLUETOOTH protocol family
10987 16:35:27.658133 <6>[ 11.169385] Bluetooth: HCI device and connection manager initialized
10988 16:35:27.661407 <6>[ 11.169410] Bluetooth: HCI socket layer initialized
10989 16:35:27.668156 <6>[ 11.169421] Bluetooth: L2CAP socket layer initialized
10990 16:35:27.671448 <6>[ 11.169434] Bluetooth: SCO socket layer initialized
10991 16:35:27.681580 <3>[ 11.178687] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 16:35:27.687640 <6>[ 11.187902] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10993 16:35:27.697742 <3>[ 11.217868] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 16:35:27.704132 <6>[ 11.224891] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10995 16:35:27.711089 <6>[ 11.226394] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10996 16:35:27.724502 <6>[ 11.227690] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10997 16:35:27.730505 <6>[ 11.227822] usbcore: registered new interface driver uvcvideo
10998 16:35:27.734464 <6>[ 11.241419] usbcore: registered new interface driver btusb
10999 16:35:27.747174 <4>[ 11.242193] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11000 16:35:27.750639 <3>[ 11.242208] Bluetooth: hci0: Failed to load firmware file (-2)
11001 16:35:27.757057 <3>[ 11.242212] Bluetooth: hci0: Failed to set up firmware (-2)
11002 16:35:27.767011 <4>[ 11.242219] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11003 16:35:27.777016 <6>[ 11.246863] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11004 16:35:27.783838 <6>[ 11.254894] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11005 16:35:27.790484 <3>[ 11.257591] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11006 16:35:27.800484 <6>[ 11.261968] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11007 16:35:27.806928 <6>[ 11.554683] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11008 16:35:27.809883 <6>[ 11.554798] pci 0000:01:00.0: supports D1 D2
11009 16:35:27.816722 <6>[ 11.566759] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11010 16:35:27.823200 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11011 16:35:27.836629 <6>[ 11.584129] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11012 16:35:27.843189 <6>[ 11.591033] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11013 16:35:27.849912 <6>[ 11.599126] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11014 16:35:27.860011 <6>[ 11.607124] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11015 16:35:27.866577 <6>[ 11.615126] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11016 16:35:27.875916 <6>[ 11.623127] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11017 16:35:27.879107 <6>[ 11.631127] pci 0000:00:00.0: PCI bridge to [bus 01]
11018 16:35:27.888957 <6>[ 11.636344] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11019 16:35:27.895594 <6>[ 11.644487] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11020 16:35:27.902249 <6>[ 11.651619] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11021 16:35:27.908810 <6>[ 11.658322] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11022 16:35:27.925123 <5>[ 11.673015] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11023 16:35:27.940729 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11024 16:35:27.947506 <5>[ 11.697377] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11025 16:35:27.957315 <5>[ 11.704668] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11026 16:35:27.967139 <4>[ 11.713306] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11027 16:35:27.970447 <6>[ 11.722236] cfg80211: failed to load regulatory.db
11028 16:35:27.977207 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11029 16:35:28.009986 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11030 16:35:28.016936 <6>[ 11.764927] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11031 16:35:28.023347 <6>[ 11.772441] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11032 16:35:28.038579 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11033 16:35:28.047200 <6>[ 11.798283] mt7921e 0000:01:00.0: ASIC revision: 79610010
11034 16:35:28.062118 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11035 16:35:28.081057 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11036 16:35:28.135360 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11037 16:35:28.149322 <6>[ 11.897389] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11038 16:35:28.152845 <6>[ 11.897389]
11039 16:35:28.163594 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11040 16:35:28.183849 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11041 16:35:28.204295 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11042 16:35:28.226155 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11043 16:35:28.299815 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11044 16:35:28.323899 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11045 16:35:28.345290 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11046 16:35:28.365836 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11047 16:35:28.417072 [[0;32m OK [0m] Started [0;<6>[ 12.164220] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11048 16:35:28.420333 1;39mgetty@tty1.service[0m - Getty on tty1.
11049 16:35:28.495097 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11050 16:35:28.514235 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11051 16:35:28.528507 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11052 16:35:28.547967 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11053 16:35:28.591315 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11054 16:35:28.615197 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11055 16:35:28.636388 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11056 16:35:28.676564 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11057 16:35:28.718125
11058 16:35:28.721306 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11059 16:35:28.721731
11060 16:35:28.723877 debian-bookworm-arm64 login: root (automatic login)
11061 16:35:28.724366
11062 16:35:28.741768 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024 aarch64
11063 16:35:28.742230
11064 16:35:28.748507 The programs included with the Debian GNU/Linux system are free software;
11065 16:35:28.755007 the exact distribution terms for each program are described in the
11066 16:35:28.758388 individual files in /usr/share/doc/*/copyright.
11067 16:35:28.758823
11068 16:35:28.764961 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11069 16:35:28.768325 permitted by applicable law.
11070 16:35:28.769764 Matched prompt #10: / #
11072 16:35:28.771082 Setting prompt string to ['/ #']
11073 16:35:28.771620 end: 2.2.5.1 login-action (duration 00:00:13) [common]
11075 16:35:28.772781 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
11076 16:35:28.773328 start: 2.2.6 expect-shell-connection (timeout 00:03:05) [common]
11077 16:35:28.773736 Setting prompt string to ['/ #']
11078 16:35:28.774266 Forcing a shell prompt, looking for ['/ #']
11080 16:35:28.825249 / #
11081 16:35:28.825970 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11082 16:35:28.826491 Waiting using forced prompt support (timeout 00:02:30)
11083 16:35:28.831240
11084 16:35:28.832028 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11085 16:35:28.832590 start: 2.2.7 export-device-env (timeout 00:03:05) [common]
11086 16:35:28.833117 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11087 16:35:28.833639 end: 2.2 depthcharge-retry (duration 00:01:55) [common]
11088 16:35:28.834143 end: 2 depthcharge-action (duration 00:01:55) [common]
11089 16:35:28.834735 start: 3 lava-test-retry (timeout 00:07:42) [common]
11090 16:35:28.835265 start: 3.1 lava-test-shell (timeout 00:07:42) [common]
11091 16:35:28.835710 Using namespace: common
11093 16:35:28.936928 / # #
11094 16:35:28.937560 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11095 16:35:28.942842 #
11096 16:35:28.943581 Using /lava-14396157
11098 16:35:29.044854 / # export SHELL=/bin/sh
11099 16:35:29.051095 export SHELL=/bin/sh
11101 16:35:29.152389 / # . /lava-14396157/environment
11102 16:35:29.157872 . /lava-14396157/environment
11104 16:35:29.258591 / # /lava-14396157/bin/lava-test-runner /lava-14396157/0
11105 16:35:29.259144 Test shell timeout: 10s (minimum of the action and connection timeout)
11106 16:35:29.264631 /lava-14396157/bin/lava-test-runner /lava-14396157/0
11107 16:35:29.280171 <6>[ 13.031034] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11108 16:35:29.289980 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11109 16:35:29.296400 + cd /lava-14396157/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11110 16:35:29.296928 + cat uuid
11111 16:35:29.299843 + UUID=14396157_1.5.2.3.1
11112 16:35:29.300270 + set +x
11113 16:35:29.306658 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14396157_1.5.2.3.1>
11114 16:35:29.307383 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14396157_1.5.2.3.1
11115 16:35:29.307776 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14396157_1.5.2.3.1)
11116 16:35:29.308200 Skipping test definition patterns.
11117 16:35:29.309814 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11118 16:35:29.316219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11119 16:35:29.316646 device: /dev/video2
11120 16:35:29.317240 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11122 16:35:29.329052 <4>[ 13.076311] use of bytesused == 0 is deprecated and will be removed in the future,
11123 16:35:29.332139 <4>[ 13.084194] use the actual size instead.
11124 16:35:29.347674 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11125 16:35:29.357166 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11126 16:35:29.362414
11127 16:35:29.375559 Compliance test for mtk-vcodec-enc device /dev/video2:
11128 16:35:29.381672
11129 16:35:29.392888 Driver Info:
11130 16:35:29.402615 Driver name : mtk-vcodec-enc
11131 16:35:29.417007 Card type : MT8192 video encoder
11132 16:35:29.428288 Bus info : platform:17020000.vcodec
11133 16:35:29.436016 Driver version : 6.1.92
11134 16:35:29.447384 Capabilities : 0x84204000
11135 16:35:29.457215 Video Memory-to-Memory Multiplanar
11136 16:35:29.468116 Streaming
11137 16:35:29.481073 Extended Pix Format
11138 16:35:29.494431 Device Capabilities
11139 16:35:29.506086 Device Caps : 0x04204000
11140 16:35:29.517052 Video Memory-to-Memory Multiplanar
11141 16:35:29.527065 Streaming
11142 16:35:29.540066 Extended Pix Format
11143 16:35:29.554559 Detected Stateful Encoder
11144 16:35:29.565231
11145 16:35:29.577708 Required ioctls:
11146 16:35:29.596804 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11147 16:35:29.597359 test VIDIOC_QUERYCAP: OK
11148 16:35:29.598090 Received signal: <TESTSET> START Required-ioctls
11149 16:35:29.598596 Starting test_set Required-ioctls
11150 16:35:29.620497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11151 16:35:29.621333 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11153 16:35:29.623757 test invalid ioctls: OK
11154 16:35:29.645364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11155 16:35:29.645849
11156 16:35:29.646540 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11158 16:35:29.654922 Allow for multiple opens:
11159 16:35:29.661961 <LAVA_SIGNAL_TESTSET STOP>
11160 16:35:29.662863 Received signal: <TESTSET> STOP
11161 16:35:29.663247 Closing test_set Required-ioctls
11162 16:35:29.673447 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11163 16:35:29.674158 Received signal: <TESTSET> START Allow-for-multiple-opens
11164 16:35:29.674576 Starting test_set Allow-for-multiple-opens
11165 16:35:29.676967 test second /dev/video2 open: OK
11166 16:35:29.699943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11167 16:35:29.700648 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11169 16:35:29.703205 test VIDIOC_QUERYCAP: OK
11170 16:35:29.723089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11171 16:35:29.723993 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11173 16:35:29.726433 test VIDIOC_G/S_PRIORITY: OK
11174 16:35:29.749057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11175 16:35:29.751493 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11177 16:35:29.752731 test for unlimited opens: OK
11178 16:35:29.778719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11179 16:35:29.779195
11180 16:35:29.779853 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11182 16:35:29.789600 Debug ioctls:
11183 16:35:29.797002 <LAVA_SIGNAL_TESTSET STOP>
11184 16:35:29.797706 Received signal: <TESTSET> STOP
11185 16:35:29.798098 Closing test_set Allow-for-multiple-opens
11186 16:35:29.807014 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11187 16:35:29.807300 Received signal: <TESTSET> START Debug-ioctls
11188 16:35:29.807403 Starting test_set Debug-ioctls
11189 16:35:29.810017 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11190 16:35:29.831592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11191 16:35:29.831942 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11193 16:35:29.838505 test VIDIOC_LOG_STATUS: OK (Not Supported)
11194 16:35:29.860985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11195 16:35:29.861127
11196 16:35:29.861402 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11198 16:35:29.872498 Input ioctls:
11199 16:35:29.879895 <LAVA_SIGNAL_TESTSET STOP>
11200 16:35:29.880187 Received signal: <TESTSET> STOP
11201 16:35:29.880289 Closing test_set Debug-ioctls
11202 16:35:29.888927 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11203 16:35:29.889188 Received signal: <TESTSET> START Input-ioctls
11204 16:35:29.889260 Starting test_set Input-ioctls
11205 16:35:29.892450 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11206 16:35:29.916555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11207 16:35:29.916883 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11209 16:35:29.919784 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11210 16:35:29.943318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11211 16:35:29.943588 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11213 16:35:29.950089 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11214 16:35:29.968544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11215 16:35:29.968830 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11217 16:35:29.975126 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11218 16:35:29.995458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11219 16:35:29.995764 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11221 16:35:29.998666 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11222 16:35:30.021906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11223 16:35:30.022188 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11225 16:35:30.025345 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11226 16:35:30.051633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11227 16:35:30.051955 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11229 16:35:30.054290 Inputs: 0 Audio Inputs: 0 Tuners: 0
11230 16:35:30.060257
11231 16:35:30.082151 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11232 16:35:30.107640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11233 16:35:30.107945 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11235 16:35:30.113919 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11236 16:35:30.136637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11237 16:35:30.136922 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11239 16:35:30.143542 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11240 16:35:30.165464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11241 16:35:30.165781 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11243 16:35:30.171497 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11244 16:35:30.189790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11245 16:35:30.190075 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11247 16:35:30.196585 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11248 16:35:30.214358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11249 16:35:30.214489
11250 16:35:30.214766 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11252 16:35:30.234072 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11253 16:35:30.257933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11254 16:35:30.258197 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11256 16:35:30.264400 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11257 16:35:30.286831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11258 16:35:30.287174 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11260 16:35:30.290574 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11261 16:35:30.308786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11262 16:35:30.309106 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11264 16:35:30.311561 test VIDIOC_G/S_EDID: OK (Not Supported)
11265 16:35:30.333323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11266 16:35:30.333473
11267 16:35:30.333728 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11269 16:35:30.342689 Control ioctls:
11270 16:35:30.350875 <LAVA_SIGNAL_TESTSET STOP>
11271 16:35:30.351259 Received signal: <TESTSET> STOP
11272 16:35:30.351375 Closing test_set Input-ioctls
11273 16:35:30.360084 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11274 16:35:30.360431 Received signal: <TESTSET> START Control-ioctls
11275 16:35:30.360541 Starting test_set Control-ioctls
11276 16:35:30.363681 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11277 16:35:30.388208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11278 16:35:30.388355 test VIDIOC_QUERYCTRL: OK
11279 16:35:30.388614 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11281 16:35:30.409845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11282 16:35:30.410207 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11284 16:35:30.413336 test VIDIOC_G/S_CTRL: OK
11285 16:35:30.435044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11286 16:35:30.435361 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11288 16:35:30.438422 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11289 16:35:30.459025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11290 16:35:30.459381 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11292 16:35:30.465592 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11293 16:35:30.473658 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11294 16:35:30.504451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11295 16:35:30.504818 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11297 16:35:30.508248 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11298 16:35:30.526482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11299 16:35:30.526845 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11301 16:35:30.529860 Standard Controls: 16 Private Controls: 0
11302 16:35:30.536679
11303 16:35:30.547057 Format ioctls:
11304 16:35:30.558138 <LAVA_SIGNAL_TESTSET STOP>
11305 16:35:30.558464 Received signal: <TESTSET> STOP
11306 16:35:30.558569 Closing test_set Control-ioctls
11307 16:35:30.567931 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11308 16:35:30.568226 Received signal: <TESTSET> START Format-ioctls
11309 16:35:30.568304 Starting test_set Format-ioctls
11310 16:35:30.571170 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11311 16:35:30.596575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11312 16:35:30.596894 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11314 16:35:30.599905 test VIDIOC_G/S_PARM: OK
11315 16:35:30.617529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11316 16:35:30.617833 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11318 16:35:30.621022 test VIDIOC_G_FBUF: OK (Not Supported)
11319 16:35:30.641318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11320 16:35:30.641637 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11322 16:35:30.644625 test VIDIOC_G_FMT: OK
11323 16:35:30.671075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11324 16:35:30.671384 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11326 16:35:30.674274 test VIDIOC_TRY_FMT: OK
11327 16:35:30.696117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11328 16:35:30.696468 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11330 16:35:30.702935 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11331 16:35:30.706803 test VIDIOC_S_FMT: FAIL
11332 16:35:30.731527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11333 16:35:30.731836 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11335 16:35:30.734859 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11336 16:35:30.761256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11337 16:35:30.761584 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11339 16:35:30.764534 test Cropping: OK
11340 16:35:30.791309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11341 16:35:30.791645 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11343 16:35:30.794451 test Composing: OK (Not Supported)
11344 16:35:30.814784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11345 16:35:30.815132 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11347 16:35:30.818119 test Scaling: OK (Not Supported)
11348 16:35:30.837586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11349 16:35:30.837719
11350 16:35:30.837984 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11352 16:35:30.852634 Codec ioctls:
11353 16:35:30.859464 <LAVA_SIGNAL_TESTSET STOP>
11354 16:35:30.859809 Received signal: <TESTSET> STOP
11355 16:35:30.859927 Closing test_set Format-ioctls
11356 16:35:30.868830 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11357 16:35:30.869155 Received signal: <TESTSET> START Codec-ioctls
11358 16:35:30.869263 Starting test_set Codec-ioctls
11359 16:35:30.872104 test VIDIOC_(TRY_)ENCODER_CMD: OK
11360 16:35:30.894077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11361 16:35:30.894419 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11363 16:35:30.900713 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11364 16:35:30.918090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11365 16:35:30.918424 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11367 16:35:30.924771 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11368 16:35:30.941374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11369 16:35:30.941528
11370 16:35:30.941806 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11372 16:35:30.950750 Buffer ioctls:
11373 16:35:30.958404 <LAVA_SIGNAL_TESTSET STOP>
11374 16:35:30.958685 Received signal: <TESTSET> STOP
11375 16:35:30.958758 Closing test_set Codec-ioctls
11376 16:35:30.967840 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11377 16:35:30.968099 Received signal: <TESTSET> START Buffer-ioctls
11378 16:35:30.968169 Starting test_set Buffer-ioctls
11379 16:35:30.971164 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11380 16:35:30.994798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11381 16:35:30.995098 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11383 16:35:30.997982 test CREATE_BUFS maximum buffers: OK
11384 16:35:31.015693 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11386 16:35:31.018733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11387 16:35:31.018852 test VIDIOC_EXPBUF: OK
11388 16:35:31.042787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11389 16:35:31.043131 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11391 16:35:31.046066 test Requests: OK (Not Supported)
11392 16:35:31.070058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11393 16:35:31.070197
11394 16:35:31.070448 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11396 16:35:31.081578 Test input 0:
11397 16:35:31.092360
11398 16:35:31.102572 Streaming ioctls:
11399 16:35:31.108843 <LAVA_SIGNAL_TESTSET STOP>
11400 16:35:31.109138 Received signal: <TESTSET> STOP
11401 16:35:31.109240 Closing test_set Buffer-ioctls
11402 16:35:31.118418 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11403 16:35:31.118736 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11404 16:35:31.118863 Starting test_set Streaming-ioctls_Test-input-0
11405 16:35:31.121541 test read/write: OK (Not Supported)
11406 16:35:31.144099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11407 16:35:31.144399 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11409 16:35:31.150756 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11410 16:35:31.159180 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11411 16:35:31.167223 test blocking wait: FAIL
11412 16:35:31.192240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11413 16:35:31.192552 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11415 16:35:31.198063 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11416 16:35:31.203245 test MMAP (select): FAIL
11417 16:35:31.227475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11418 16:35:31.227817 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11420 16:35:31.234401 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11421 16:35:31.240116 test MMAP (epoll): FAIL
11422 16:35:31.264303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11423 16:35:31.264629 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11425 16:35:31.270977 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11426 16:35:31.281424 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11427 16:35:31.287328 test USERPTR (select): FAIL
11428 16:35:31.311502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11429 16:35:31.311853 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11431 16:35:31.317993 test DMABUF: Cannot test, specify --expbuf-device
11432 16:35:31.321459
11433 16:35:31.339493 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11434 16:35:31.343251 <LAVA_TEST_RUNNER EXIT>
11435 16:35:31.343555 ok: lava_test_shell seems to have completed
11436 16:35:31.343661 Marking unfinished test run as failed
11438 16:35:31.345555 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11439 16:35:31.345711 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11440 16:35:31.345832 end: 3 lava-test-retry (duration 00:00:03) [common]
11441 16:35:31.345950 start: 4 finalize (timeout 00:07:39) [common]
11442 16:35:31.346075 start: 4.1 power-off (timeout 00:00:30) [common]
11443 16:35:31.346355 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11444 16:35:31.549473 >> Command sent successfully.
11445 16:35:31.552096 Returned 0 in 0 seconds
11446 16:35:31.652568 end: 4.1 power-off (duration 00:00:00) [common]
11448 16:35:31.653031 start: 4.2 read-feedback (timeout 00:07:39) [common]
11449 16:35:31.653351 Listened to connection for namespace 'common' for up to 1s
11450 16:35:32.654225 Finalising connection for namespace 'common'
11451 16:35:32.654386 Disconnecting from shell: Finalise
11452 16:35:32.654468 / #
11453 16:35:32.754778 end: 4.2 read-feedback (duration 00:00:01) [common]
11454 16:35:32.754978 end: 4 finalize (duration 00:00:01) [common]
11455 16:35:32.755125 Cleaning after the job
11456 16:35:32.755255 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/ramdisk
11457 16:35:32.759833 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/kernel
11458 16:35:32.772943 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/dtb
11459 16:35:32.773199 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396157/tftp-deploy-7i0icuzc/modules
11460 16:35:32.778967 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396157
11461 16:35:32.845089 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396157
11462 16:35:32.845257 Job finished correctly