Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 20
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 16:30:20.103476 lava-dispatcher, installed at version: 2024.03
2 16:30:20.103716 start: 0 validate
3 16:30:20.103873 Start time: 2024-06-17 16:30:20.103865+00:00 (UTC)
4 16:30:20.103993 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:30:20.104120 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 16:30:20.369703 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:30:20.369870 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:30:31.636636 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:30:31.636888 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:30:31.897434 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:30:31.897629 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 16:30:35.653505 validate duration: 15.55
14 16:30:35.653878 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:30:35.654027 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:30:35.654168 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:30:35.654328 Not decompressing ramdisk as can be used compressed.
18 16:30:35.654455 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 16:30:35.654547 saving as /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/ramdisk/rootfs.cpio.gz
20 16:30:35.654658 total size: 8181887 (7 MB)
21 16:30:35.918504 progress 0 % (0 MB)
22 16:30:35.921993 progress 5 % (0 MB)
23 16:30:35.925207 progress 10 % (0 MB)
24 16:30:35.928884 progress 15 % (1 MB)
25 16:30:35.932033 progress 20 % (1 MB)
26 16:30:35.935630 progress 25 % (1 MB)
27 16:30:35.938767 progress 30 % (2 MB)
28 16:30:35.942434 progress 35 % (2 MB)
29 16:30:35.945655 progress 40 % (3 MB)
30 16:30:35.949331 progress 45 % (3 MB)
31 16:30:35.952499 progress 50 % (3 MB)
32 16:30:35.956142 progress 55 % (4 MB)
33 16:30:35.959377 progress 60 % (4 MB)
34 16:30:35.963056 progress 65 % (5 MB)
35 16:30:35.966281 progress 70 % (5 MB)
36 16:30:35.969377 progress 75 % (5 MB)
37 16:30:35.971451 progress 80 % (6 MB)
38 16:30:35.973687 progress 85 % (6 MB)
39 16:30:35.975770 progress 90 % (7 MB)
40 16:30:35.977980 progress 95 % (7 MB)
41 16:30:35.980007 progress 100 % (7 MB)
42 16:30:35.980210 7 MB downloaded in 0.33 s (23.97 MB/s)
43 16:30:35.980376 end: 1.1.1 http-download (duration 00:00:00) [common]
45 16:30:35.980667 end: 1.1 download-retry (duration 00:00:00) [common]
46 16:30:35.980756 start: 1.2 download-retry (timeout 00:10:00) [common]
47 16:30:35.980842 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 16:30:35.980984 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 16:30:35.981056 saving as /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/kernel/Image
50 16:30:35.981138 total size: 54813184 (52 MB)
51 16:30:35.981202 No compression specified
52 16:30:35.982314 progress 0 % (0 MB)
53 16:30:35.995962 progress 5 % (2 MB)
54 16:30:36.009923 progress 10 % (5 MB)
55 16:30:36.023905 progress 15 % (7 MB)
56 16:30:36.037802 progress 20 % (10 MB)
57 16:30:36.051670 progress 25 % (13 MB)
58 16:30:36.065455 progress 30 % (15 MB)
59 16:30:36.079320 progress 35 % (18 MB)
60 16:30:36.093455 progress 40 % (20 MB)
61 16:30:36.107515 progress 45 % (23 MB)
62 16:30:36.121376 progress 50 % (26 MB)
63 16:30:36.135380 progress 55 % (28 MB)
64 16:30:36.149163 progress 60 % (31 MB)
65 16:30:36.163256 progress 65 % (34 MB)
66 16:30:36.177161 progress 70 % (36 MB)
67 16:30:36.191161 progress 75 % (39 MB)
68 16:30:36.205405 progress 80 % (41 MB)
69 16:30:36.219610 progress 85 % (44 MB)
70 16:30:36.233604 progress 90 % (47 MB)
71 16:30:36.247407 progress 95 % (49 MB)
72 16:30:36.261148 progress 100 % (52 MB)
73 16:30:36.261404 52 MB downloaded in 0.28 s (186.52 MB/s)
74 16:30:36.261570 end: 1.2.1 http-download (duration 00:00:00) [common]
76 16:30:36.261803 end: 1.2 download-retry (duration 00:00:00) [common]
77 16:30:36.261890 start: 1.3 download-retry (timeout 00:09:59) [common]
78 16:30:36.261976 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 16:30:36.262138 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 16:30:36.262210 saving as /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/dtb/mt8192-asurada-spherion-r0.dtb
81 16:30:36.262272 total size: 47258 (0 MB)
82 16:30:36.262334 No compression specified
83 16:30:36.263473 progress 69 % (0 MB)
84 16:30:36.263853 progress 100 % (0 MB)
85 16:30:36.264024 0 MB downloaded in 0.00 s (25.76 MB/s)
86 16:30:36.264151 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:30:36.264388 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:30:36.264496 start: 1.4 download-retry (timeout 00:09:59) [common]
90 16:30:36.264620 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 16:30:36.264744 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 16:30:36.264812 saving as /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/modules/modules.tar
93 16:30:36.264888 total size: 8628772 (8 MB)
94 16:30:36.264951 Using unxz to decompress xz
95 16:30:36.268671 progress 0 % (0 MB)
96 16:30:36.290200 progress 5 % (0 MB)
97 16:30:36.314921 progress 10 % (0 MB)
98 16:30:36.338867 progress 15 % (1 MB)
99 16:30:36.363764 progress 20 % (1 MB)
100 16:30:36.389314 progress 25 % (2 MB)
101 16:30:36.413994 progress 30 % (2 MB)
102 16:30:36.441000 progress 35 % (2 MB)
103 16:30:36.466201 progress 40 % (3 MB)
104 16:30:36.491153 progress 45 % (3 MB)
105 16:30:36.517633 progress 50 % (4 MB)
106 16:30:36.542771 progress 55 % (4 MB)
107 16:30:36.567851 progress 60 % (4 MB)
108 16:30:36.595702 progress 65 % (5 MB)
109 16:30:36.621862 progress 70 % (5 MB)
110 16:30:36.646999 progress 75 % (6 MB)
111 16:30:36.671954 progress 80 % (6 MB)
112 16:30:36.700127 progress 85 % (7 MB)
113 16:30:36.728522 progress 90 % (7 MB)
114 16:30:36.754296 progress 95 % (7 MB)
115 16:30:36.780035 progress 100 % (8 MB)
116 16:30:36.785458 8 MB downloaded in 0.52 s (15.81 MB/s)
117 16:30:36.785719 end: 1.4.1 http-download (duration 00:00:01) [common]
119 16:30:36.785980 end: 1.4 download-retry (duration 00:00:01) [common]
120 16:30:36.786076 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 16:30:36.786169 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 16:30:36.786250 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:30:36.786337 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 16:30:36.786559 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0
125 16:30:36.786700 makedir: /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin
126 16:30:36.786806 makedir: /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/tests
127 16:30:36.786916 makedir: /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/results
128 16:30:36.787032 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-add-keys
129 16:30:36.787189 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-add-sources
130 16:30:36.787331 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-background-process-start
131 16:30:36.787495 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-background-process-stop
132 16:30:36.787653 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-common-functions
133 16:30:36.787781 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-echo-ipv4
134 16:30:36.787903 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-install-packages
135 16:30:36.788024 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-installed-packages
136 16:30:36.788162 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-os-build
137 16:30:36.788315 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-probe-channel
138 16:30:36.788468 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-probe-ip
139 16:30:36.788636 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-target-ip
140 16:30:36.788759 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-target-mac
141 16:30:36.788882 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-target-storage
142 16:30:36.789008 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-test-case
143 16:30:36.789131 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-test-event
144 16:30:36.789249 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-test-feedback
145 16:30:36.789368 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-test-raise
146 16:30:36.789490 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-test-reference
147 16:30:36.789608 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-test-runner
148 16:30:36.789726 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-test-set
149 16:30:36.789844 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-test-shell
150 16:30:36.789970 Updating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-install-packages (oe)
151 16:30:36.790112 Updating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/bin/lava-installed-packages (oe)
152 16:30:36.790237 Creating /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/environment
153 16:30:36.790336 LAVA metadata
154 16:30:36.790410 - LAVA_JOB_ID=14396158
155 16:30:36.790474 - LAVA_DISPATCHER_IP=192.168.201.1
156 16:30:36.790576 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 16:30:36.790649 skipped lava-vland-overlay
158 16:30:36.790723 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 16:30:36.790807 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 16:30:36.790870 skipped lava-multinode-overlay
161 16:30:36.790943 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 16:30:36.791032 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 16:30:36.791105 Loading test definitions
164 16:30:36.791199 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 16:30:36.791270 Using /lava-14396158 at stage 0
166 16:30:36.791574 uuid=14396158_1.5.2.3.1 testdef=None
167 16:30:36.791661 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 16:30:36.791751 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 16:30:36.792331 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 16:30:36.792645 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 16:30:36.793284 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 16:30:36.793515 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 16:30:36.794122 runner path: /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/0/tests/0_dmesg test_uuid 14396158_1.5.2.3.1
176 16:30:36.794274 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 16:30:36.794483 Creating lava-test-runner.conf files
179 16:30:36.794546 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396158/lava-overlay-_n5bjva0/lava-14396158/0 for stage 0
180 16:30:36.794633 - 0_dmesg
181 16:30:36.794728 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 16:30:36.794814 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 16:30:36.802985 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 16:30:36.803121 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 16:30:36.803211 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 16:30:36.803298 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 16:30:36.803382 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 16:30:37.038255 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 16:30:37.038617 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 16:30:37.038731 extracting modules file /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396158/extract-overlay-ramdisk-c00c0you/ramdisk
191 16:30:37.239467 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 16:30:37.239624 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 16:30:37.239721 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396158/compress-overlay-kpundtbm/overlay-1.5.2.4.tar.gz to ramdisk
194 16:30:37.239791 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396158/compress-overlay-kpundtbm/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396158/extract-overlay-ramdisk-c00c0you/ramdisk
195 16:30:37.246084 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 16:30:37.246193 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 16:30:37.246283 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 16:30:37.246371 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 16:30:37.246446 Building ramdisk /var/lib/lava/dispatcher/tmp/14396158/extract-overlay-ramdisk-c00c0you/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396158/extract-overlay-ramdisk-c00c0you/ramdisk
200 16:30:37.569980 >> 145247 blocks
201 16:30:39.861004 rename /var/lib/lava/dispatcher/tmp/14396158/extract-overlay-ramdisk-c00c0you/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/ramdisk/ramdisk.cpio.gz
202 16:30:39.861536 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 16:30:39.861742 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 16:30:39.861900 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 16:30:39.862069 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/kernel/Image']
206 16:30:53.877458 Returned 0 in 14 seconds
207 16:30:53.978093 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/kernel/image.itb
208 16:30:54.371063 output: FIT description: Kernel Image image with one or more FDT blobs
209 16:30:54.371463 output: Created: Mon Jun 17 17:30:54 2024
210 16:30:54.371582 output: Image 0 (kernel-1)
211 16:30:54.371686 output: Description:
212 16:30:54.371789 output: Created: Mon Jun 17 17:30:54 2024
213 16:30:54.371888 output: Type: Kernel Image
214 16:30:54.371983 output: Compression: lzma compressed
215 16:30:54.372086 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
216 16:30:54.372183 output: Architecture: AArch64
217 16:30:54.372280 output: OS: Linux
218 16:30:54.372386 output: Load Address: 0x00000000
219 16:30:54.372486 output: Entry Point: 0x00000000
220 16:30:54.372588 output: Hash algo: crc32
221 16:30:54.372681 output: Hash value: 106ffd6f
222 16:30:54.372791 output: Image 1 (fdt-1)
223 16:30:54.372886 output: Description: mt8192-asurada-spherion-r0
224 16:30:54.372984 output: Created: Mon Jun 17 17:30:54 2024
225 16:30:54.373075 output: Type: Flat Device Tree
226 16:30:54.373178 output: Compression: uncompressed
227 16:30:54.373266 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 16:30:54.373353 output: Architecture: AArch64
229 16:30:54.373441 output: Hash algo: crc32
230 16:30:54.373544 output: Hash value: 0f8e4d2e
231 16:30:54.373633 output: Image 2 (ramdisk-1)
232 16:30:54.373720 output: Description: unavailable
233 16:30:54.373808 output: Created: Mon Jun 17 17:30:54 2024
234 16:30:54.373898 output: Type: RAMDisk Image
235 16:30:54.373998 output: Compression: Unknown Compression
236 16:30:54.374084 output: Data Size: 21372124 Bytes = 20871.21 KiB = 20.38 MiB
237 16:30:54.374176 output: Architecture: AArch64
238 16:30:54.374264 output: OS: Linux
239 16:30:54.374361 output: Load Address: unavailable
240 16:30:54.374465 output: Entry Point: unavailable
241 16:30:54.374555 output: Hash algo: crc32
242 16:30:54.374656 output: Hash value: cbe2174f
243 16:30:54.374749 output: Default Configuration: 'conf-1'
244 16:30:54.374845 output: Configuration 0 (conf-1)
245 16:30:54.374941 output: Description: mt8192-asurada-spherion-r0
246 16:30:54.375031 output: Kernel: kernel-1
247 16:30:54.375120 output: Init Ramdisk: ramdisk-1
248 16:30:54.375220 output: FDT: fdt-1
249 16:30:54.375309 output: Loadables: kernel-1
250 16:30:54.375399 output:
251 16:30:54.375648 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 16:30:54.375789 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 16:30:54.375930 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 16:30:54.376075 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 16:30:54.376189 No LXC device requested
256 16:30:54.376317 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 16:30:54.376447 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 16:30:54.376571 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 16:30:54.376677 Checking files for TFTP limit of 4294967296 bytes.
260 16:30:54.377381 end: 1 tftp-deploy (duration 00:00:19) [common]
261 16:30:54.377534 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 16:30:54.377674 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 16:30:54.377855 substitutions:
264 16:30:54.377958 - {DTB}: 14396158/tftp-deploy-it13sxei/dtb/mt8192-asurada-spherion-r0.dtb
265 16:30:54.378053 - {INITRD}: 14396158/tftp-deploy-it13sxei/ramdisk/ramdisk.cpio.gz
266 16:30:54.378154 - {KERNEL}: 14396158/tftp-deploy-it13sxei/kernel/Image
267 16:30:54.378249 - {LAVA_MAC}: None
268 16:30:54.378346 - {PRESEED_CONFIG}: None
269 16:30:54.378459 - {PRESEED_LOCAL}: None
270 16:30:54.378555 - {RAMDISK}: 14396158/tftp-deploy-it13sxei/ramdisk/ramdisk.cpio.gz
271 16:30:54.378652 - {ROOT_PART}: None
272 16:30:54.378741 - {ROOT}: None
273 16:30:54.378827 - {SERVER_IP}: 192.168.201.1
274 16:30:54.378917 - {TEE}: None
275 16:30:54.379004 Parsed boot commands:
276 16:30:54.379089 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 16:30:54.379314 Parsed boot commands: tftpboot 192.168.201.1 14396158/tftp-deploy-it13sxei/kernel/image.itb 14396158/tftp-deploy-it13sxei/kernel/cmdline
278 16:30:54.379439 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 16:30:54.379559 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 16:30:54.379688 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 16:30:54.379806 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 16:30:54.379910 Not connected, no need to disconnect.
283 16:30:54.380022 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 16:30:54.380141 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 16:30:54.380238 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 16:30:54.383615 Setting prompt string to ['lava-test: # ']
287 16:30:54.384000 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 16:30:54.384150 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 16:30:54.384292 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 16:30:54.384421 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 16:30:54.384644 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
292 16:31:07.969267 Returned 0 in 13 seconds
293 16:31:08.070210 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 16:31:08.070548 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 16:31:08.070648 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 16:31:08.070738 Setting prompt string to 'Starting depthcharge on Spherion...'
298 16:31:08.070804 Changing prompt to 'Starting depthcharge on Spherion...'
299 16:31:08.070874 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 16:31:08.071279 [Enter `^Ec?' for help]
301 16:31:08.071362
302 16:31:08.071443
303 16:31:08.071547 F0: 102B 0000
304 16:31:08.071638
305 16:31:08.071731 F3: 1001 0000 [0200]
306 16:31:08.071837
307 16:31:08.071941 F3: 1001 0000
308 16:31:08.072016
309 16:31:08.072119 F7: 102D 0000
310 16:31:08.072214
311 16:31:08.072307 F1: 0000 0000
312 16:31:08.072410
313 16:31:08.072514 V0: 0000 0000 [0001]
314 16:31:08.072636
315 16:31:08.072739 00: 0007 8000
316 16:31:08.072835
317 16:31:08.072938 01: 0000 0000
318 16:31:08.073044
319 16:31:08.073137 BP: 0C00 0209 [0000]
320 16:31:08.073201
321 16:31:08.073271 G0: 1182 0000
322 16:31:08.073363
323 16:31:08.073455 EC: 0000 0021 [4000]
324 16:31:08.073541
325 16:31:08.073627 S7: 0000 0000 [0000]
326 16:31:08.073712
327 16:31:08.073798 CC: 0000 0000 [0001]
328 16:31:08.073883
329 16:31:08.073968 T0: 0000 0040 [010F]
330 16:31:08.074054
331 16:31:08.074141 Jump to BL
332 16:31:08.074229
333 16:31:08.074287
334 16:31:08.074344
335 16:31:08.074403 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 16:31:08.074466 ARM64: Exception handlers installed.
337 16:31:08.074529 ARM64: Testing exception
338 16:31:08.074590 ARM64: Done test exception
339 16:31:08.074647 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 16:31:08.074706 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 16:31:08.074764 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 16:31:08.074822 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 16:31:08.074879 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 16:31:08.074936 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 16:31:08.074991 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 16:31:08.075048 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 16:31:08.075107 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 16:31:08.075162 WDT: Last reset was cold boot
349 16:31:08.075218 SPI1(PAD0) initialized at 2873684 Hz
350 16:31:08.075273 SPI5(PAD0) initialized at 992727 Hz
351 16:31:08.075328 VBOOT: Loading verstage.
352 16:31:08.075383 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 16:31:08.075439 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 16:31:08.075495 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 16:31:08.075551 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 16:31:08.075606 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 16:31:08.075662 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 16:31:08.075720 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 16:31:08.075775
360 16:31:08.075833
361 16:31:08.075900 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 16:31:08.075966 ARM64: Exception handlers installed.
363 16:31:08.076040 ARM64: Testing exception
364 16:31:08.076128 ARM64: Done test exception
365 16:31:08.076221 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 16:31:08.076320 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 16:31:08.076410 Probing TPM: . done!
368 16:31:08.076498 TPM ready after 0 ms
369 16:31:08.076592 Connected to device vid:did:rid of 1ae0:0028:00
370 16:31:08.076654 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
371 16:31:08.076712 Initialized TPM device CR50 revision 0
372 16:31:08.076770 tlcl_send_startup: Startup return code is 0
373 16:31:08.076832 TPM: setup succeeded
374 16:31:08.076897 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 16:31:08.076960 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 16:31:08.077018 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 16:31:08.077074 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 16:31:08.077129 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 16:31:08.077186 in-header: 03 07 00 00 08 00 00 00
380 16:31:08.077242 in-data: aa e4 47 04 13 02 00 00
381 16:31:08.077296 Chrome EC: UHEPI supported
382 16:31:08.077351 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 16:31:08.077407 in-header: 03 a9 00 00 08 00 00 00
384 16:31:08.077462 in-data: 84 60 60 08 00 00 00 00
385 16:31:08.077517 Phase 1
386 16:31:08.077572 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 16:31:08.077627 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 16:31:08.077683 VB2:vb2_check_recovery() Recovery was requested manually
389 16:31:08.077738 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 16:31:08.077799 Recovery requested (1009000e)
391 16:31:08.077855 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 16:31:08.077918 tlcl_extend: response is 0
393 16:31:08.077973 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 16:31:08.078028 tlcl_extend: response is 0
395 16:31:08.078082 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 16:31:08.078158 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 16:31:08.078226 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 16:31:08.078291
399 16:31:08.078350
400 16:31:08.078406 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 16:31:08.078466 ARM64: Exception handlers installed.
402 16:31:08.078523 ARM64: Testing exception
403 16:31:08.078583 ARM64: Done test exception
404 16:31:08.078639 pmic_efuse_setting: Set efuses in 11 msecs
405 16:31:08.078721 pmwrap_interface_init: Select PMIF_VLD_RDY
406 16:31:08.078857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 16:31:08.078986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 16:31:08.079350 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 16:31:08.079555 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 16:31:08.079701 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 16:31:08.079844 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 16:31:08.079925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 16:31:08.080038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 16:31:08.080133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 16:31:08.080233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 16:31:08.080324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 16:31:08.080429 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 16:31:08.080584 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 16:31:08.080675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 16:31:08.080737 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 16:31:08.080796 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 16:31:08.080853 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 16:31:08.080909 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 16:31:08.080965 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 16:31:08.081021 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 16:31:08.081077 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 16:31:08.081133 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 16:31:08.081188 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 16:31:08.081244 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 16:31:08.081299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 16:31:08.081354 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 16:31:08.081409 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 16:31:08.081464 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 16:31:08.081519 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 16:31:08.081575 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 16:31:08.081629 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 16:31:08.081684 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 16:31:08.081740 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 16:31:08.081796 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 16:31:08.081851 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 16:31:08.081906 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 16:31:08.081961 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 16:31:08.082015 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 16:31:08.082070 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 16:31:08.082128 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 16:31:08.082257 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 16:31:08.082375 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 16:31:08.082438 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 16:31:08.082497 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 16:31:08.082554 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 16:31:08.082610 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 16:31:08.082666 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 16:31:08.082723 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 16:31:08.082779 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 16:31:08.082833 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 16:31:08.082888 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 16:31:08.082953 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 16:31:08.083011 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 16:31:08.083070 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 16:31:08.083125 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 16:31:08.083229 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 16:31:08.083366 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 16:31:08.083501 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 16:31:08.083619 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 16:31:08.083691 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x16
466 16:31:08.083778 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 16:31:08.083861 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 16:31:08.083922 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 16:31:08.083980 [RTC]rtc_get_frequency_meter,154: input=15, output=774
470 16:31:08.084038 [RTC]rtc_get_frequency_meter,154: input=23, output=957
471 16:31:08.084094 [RTC]rtc_get_frequency_meter,154: input=19, output=865
472 16:31:08.084150 [RTC]rtc_get_frequency_meter,154: input=17, output=819
473 16:31:08.084205 [RTC]rtc_get_frequency_meter,154: input=16, output=796
474 16:31:08.084261 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
475 16:31:08.084316 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
476 16:31:08.084372 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
477 16:31:08.084428 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
478 16:31:08.084683 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
479 16:31:08.084751 ADC[4]: Raw value=902507 ID=7
480 16:31:08.084809 ADC[3]: Raw value=213179 ID=1
481 16:31:08.084865 RAM Code: 0x71
482 16:31:08.084942 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
483 16:31:08.085003 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
484 16:31:08.085060 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
485 16:31:08.085118 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
486 16:31:08.085174 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
487 16:31:08.085230 in-header: 03 07 00 00 08 00 00 00
488 16:31:08.085285 in-data: aa e4 47 04 13 02 00 00
489 16:31:08.085340 Chrome EC: UHEPI supported
490 16:31:08.085394 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
491 16:31:08.085450 in-header: 03 a9 00 00 08 00 00 00
492 16:31:08.085504 in-data: 84 60 60 08 00 00 00 00
493 16:31:08.085559 MRC: failed to locate region type 0.
494 16:31:08.085640 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
495 16:31:08.085769 DRAM-K: Running full calibration
496 16:31:08.085903 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
497 16:31:08.086004 header.status = 0x0
498 16:31:08.086066 header.version = 0x6 (expected: 0x6)
499 16:31:08.086125 header.size = 0xd00 (expected: 0xd00)
500 16:31:08.086182 header.flags = 0x0
501 16:31:08.086289 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
502 16:31:08.086399 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
503 16:31:08.086530 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
504 16:31:08.086666 dram_init: ddr_geometry: 2
505 16:31:08.086781 [EMI] MDL number = 2
506 16:31:08.086844 [EMI] Get MDL freq = 0
507 16:31:08.086935 dram_init: ddr_type: 0
508 16:31:08.087045 is_discrete_lpddr4: 1
509 16:31:08.087143 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
510 16:31:08.087249
511 16:31:08.087351
512 16:31:08.087446 [Bian_co] ETT version 0.0.0.1
513 16:31:08.087542 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
514 16:31:08.087639
515 16:31:08.087698 dramc_set_vcore_voltage set vcore to 650000
516 16:31:08.087753 Read voltage for 800, 4
517 16:31:08.087816 Vio18 = 0
518 16:31:08.087876 Vcore = 650000
519 16:31:08.087943 Vdram = 0
520 16:31:08.088022 Vddq = 0
521 16:31:08.088119 Vmddr = 0
522 16:31:08.088214 dram_init: config_dvfs: 1
523 16:31:08.088309 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
524 16:31:08.088410 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
525 16:31:08.088511 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
526 16:31:08.088604 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
527 16:31:08.088666 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
528 16:31:08.088722 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
529 16:31:08.088778 MEM_TYPE=3, freq_sel=18
530 16:31:08.088888 sv_algorithm_assistance_LP4_1600
531 16:31:08.088985 ============ PULL DRAM RESETB DOWN ============
532 16:31:08.089082 ========== PULL DRAM RESETB DOWN end =========
533 16:31:08.089178 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
534 16:31:08.089276 ===================================
535 16:31:08.089346 LPDDR4 DRAM CONFIGURATION
536 16:31:08.089402 ===================================
537 16:31:08.089457 EX_ROW_EN[0] = 0x0
538 16:31:08.089512 EX_ROW_EN[1] = 0x0
539 16:31:08.089567 LP4Y_EN = 0x0
540 16:31:08.089621 WORK_FSP = 0x0
541 16:31:08.089675 WL = 0x2
542 16:31:08.089730 RL = 0x2
543 16:31:08.089786 BL = 0x2
544 16:31:08.089839 RPST = 0x0
545 16:31:08.089893 RD_PRE = 0x0
546 16:31:08.089947 WR_PRE = 0x1
547 16:31:08.090001 WR_PST = 0x0
548 16:31:08.090056 DBI_WR = 0x0
549 16:31:08.090110 DBI_RD = 0x0
550 16:31:08.090164 OTF = 0x1
551 16:31:08.090218 ===================================
552 16:31:08.090274 ===================================
553 16:31:08.090328 ANA top config
554 16:31:08.090383 ===================================
555 16:31:08.090438 DLL_ASYNC_EN = 0
556 16:31:08.090492 ALL_SLAVE_EN = 1
557 16:31:08.090546 NEW_RANK_MODE = 1
558 16:31:08.090601 DLL_IDLE_MODE = 1
559 16:31:08.090656 LP45_APHY_COMB_EN = 1
560 16:31:08.090710 TX_ODT_DIS = 1
561 16:31:08.090764 NEW_8X_MODE = 1
562 16:31:08.090819 ===================================
563 16:31:08.090874 ===================================
564 16:31:08.090928 data_rate = 1600
565 16:31:08.090982 CKR = 1
566 16:31:08.091036 DQ_P2S_RATIO = 8
567 16:31:08.091090 ===================================
568 16:31:08.091144 CA_P2S_RATIO = 8
569 16:31:08.091198 DQ_CA_OPEN = 0
570 16:31:08.091252 DQ_SEMI_OPEN = 0
571 16:31:08.091306 CA_SEMI_OPEN = 0
572 16:31:08.091360 CA_FULL_RATE = 0
573 16:31:08.091414 DQ_CKDIV4_EN = 1
574 16:31:08.091468 CA_CKDIV4_EN = 1
575 16:31:08.091522 CA_PREDIV_EN = 0
576 16:31:08.091576 PH8_DLY = 0
577 16:31:08.091629 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
578 16:31:08.091683 DQ_AAMCK_DIV = 4
579 16:31:08.091737 CA_AAMCK_DIV = 4
580 16:31:08.091791 CA_ADMCK_DIV = 4
581 16:31:08.091845 DQ_TRACK_CA_EN = 0
582 16:31:08.091899 CA_PICK = 800
583 16:31:08.091952 CA_MCKIO = 800
584 16:31:08.092007 MCKIO_SEMI = 0
585 16:31:08.092061 PLL_FREQ = 3068
586 16:31:08.092123 DQ_UI_PI_RATIO = 32
587 16:31:08.092215 CA_UI_PI_RATIO = 0
588 16:31:08.092301 ===================================
589 16:31:08.092387 ===================================
590 16:31:08.092473 memory_type:LPDDR4
591 16:31:08.092593 GP_NUM : 10
592 16:31:08.092653 SRAM_EN : 1
593 16:31:08.092709 MD32_EN : 0
594 16:31:08.092763 ===================================
595 16:31:08.092818 [ANA_INIT] >>>>>>>>>>>>>>
596 16:31:08.092872 <<<<<< [CONFIGURE PHASE]: ANA_TX
597 16:31:08.092930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
598 16:31:08.092984 ===================================
599 16:31:08.093250 data_rate = 1600,PCW = 0X7600
600 16:31:08.093312 ===================================
601 16:31:08.093368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
602 16:31:08.093424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
603 16:31:08.093480 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 16:31:08.093535 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
605 16:31:08.093604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
606 16:31:08.093666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
607 16:31:08.093721 [ANA_INIT] flow start
608 16:31:08.093776 [ANA_INIT] PLL >>>>>>>>
609 16:31:08.093831 [ANA_INIT] PLL <<<<<<<<
610 16:31:08.093885 [ANA_INIT] MIDPI >>>>>>>>
611 16:31:08.093940 [ANA_INIT] MIDPI <<<<<<<<
612 16:31:08.093994 [ANA_INIT] DLL >>>>>>>>
613 16:31:08.094048 [ANA_INIT] flow end
614 16:31:08.094102 ============ LP4 DIFF to SE enter ============
615 16:31:08.094157 ============ LP4 DIFF to SE exit ============
616 16:31:08.094230 [ANA_INIT] <<<<<<<<<<<<<
617 16:31:08.094299 [Flow] Enable top DCM control >>>>>
618 16:31:08.094366 [Flow] Enable top DCM control <<<<<
619 16:31:08.094424 Enable DLL master slave shuffle
620 16:31:08.094480 ==============================================================
621 16:31:08.094535 Gating Mode config
622 16:31:08.094589 ==============================================================
623 16:31:08.094644 Config description:
624 16:31:08.094699 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
625 16:31:08.094755 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
626 16:31:08.094809 SELPH_MODE 0: By rank 1: By Phase
627 16:31:08.094865 ==============================================================
628 16:31:08.094919 GAT_TRACK_EN = 1
629 16:31:08.094974 RX_GATING_MODE = 2
630 16:31:08.095028 RX_GATING_TRACK_MODE = 2
631 16:31:08.095082 SELPH_MODE = 1
632 16:31:08.095137 PICG_EARLY_EN = 1
633 16:31:08.095191 VALID_LAT_VALUE = 1
634 16:31:08.095245 ==============================================================
635 16:31:08.095300 Enter into Gating configuration >>>>
636 16:31:08.095354 Exit from Gating configuration <<<<
637 16:31:08.095408 Enter into DVFS_PRE_config >>>>>
638 16:31:08.095472 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
639 16:31:08.095549 Exit from DVFS_PRE_config <<<<<
640 16:31:08.095637 Enter into PICG configuration >>>>
641 16:31:08.095694 Exit from PICG configuration <<<<
642 16:31:08.095750 [RX_INPUT] configuration >>>>>
643 16:31:08.095805 [RX_INPUT] configuration <<<<<
644 16:31:08.095859 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
645 16:31:08.095915 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
646 16:31:08.095969 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
647 16:31:08.096025 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
648 16:31:08.096080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
649 16:31:08.096135 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
650 16:31:08.096190 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
651 16:31:08.096245 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
652 16:31:08.096300 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
653 16:31:08.096354 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
654 16:31:08.096455 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
655 16:31:08.096542 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
656 16:31:08.096612 ===================================
657 16:31:08.096667 LPDDR4 DRAM CONFIGURATION
658 16:31:08.096722 ===================================
659 16:31:08.096777 EX_ROW_EN[0] = 0x0
660 16:31:08.096832 EX_ROW_EN[1] = 0x0
661 16:31:08.096886 LP4Y_EN = 0x0
662 16:31:08.096940 WORK_FSP = 0x0
663 16:31:08.096994 WL = 0x2
664 16:31:08.097048 RL = 0x2
665 16:31:08.097101 BL = 0x2
666 16:31:08.097155 RPST = 0x0
667 16:31:08.097210 RD_PRE = 0x0
668 16:31:08.097264 WR_PRE = 0x1
669 16:31:08.097318 WR_PST = 0x0
670 16:31:08.097371 DBI_WR = 0x0
671 16:31:08.097425 DBI_RD = 0x0
672 16:31:08.097479 OTF = 0x1
673 16:31:08.097533 ===================================
674 16:31:08.097588 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
675 16:31:08.097642 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
676 16:31:08.097698 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
677 16:31:08.097753 ===================================
678 16:31:08.097807 LPDDR4 DRAM CONFIGURATION
679 16:31:08.097862 ===================================
680 16:31:08.097915 EX_ROW_EN[0] = 0x10
681 16:31:08.097969 EX_ROW_EN[1] = 0x0
682 16:31:08.098021 LP4Y_EN = 0x0
683 16:31:08.098074 WORK_FSP = 0x0
684 16:31:08.098127 WL = 0x2
685 16:31:08.098180 RL = 0x2
686 16:31:08.098232 BL = 0x2
687 16:31:08.098285 RPST = 0x0
688 16:31:08.098339 RD_PRE = 0x0
689 16:31:08.098392 WR_PRE = 0x1
690 16:31:08.098446 WR_PST = 0x0
691 16:31:08.098500 DBI_WR = 0x0
692 16:31:08.098554 DBI_RD = 0x0
693 16:31:08.098607 OTF = 0x1
694 16:31:08.098661 ===================================
695 16:31:08.098716 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
696 16:31:08.098770 nWR fixed to 40
697 16:31:08.098824 [ModeRegInit_LP4] CH0 RK0
698 16:31:08.098878 [ModeRegInit_LP4] CH0 RK1
699 16:31:08.098943 [ModeRegInit_LP4] CH1 RK0
700 16:31:08.099011 [ModeRegInit_LP4] CH1 RK1
701 16:31:08.099087 match AC timing 13
702 16:31:08.099146 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
703 16:31:08.099202 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
704 16:31:08.099262 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
705 16:31:08.099331 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
706 16:31:08.099585 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
707 16:31:08.099646 [EMI DOE] emi_dcm 0
708 16:31:08.099703 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
709 16:31:08.099759 ==
710 16:31:08.099814 Dram Type= 6, Freq= 0, CH_0, rank 0
711 16:31:08.099869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
712 16:31:08.099924 ==
713 16:31:08.099994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
714 16:31:08.100071 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
715 16:31:08.100128 [CA 0] Center 38 (7~69) winsize 63
716 16:31:08.100183 [CA 1] Center 38 (7~69) winsize 63
717 16:31:08.100238 [CA 2] Center 35 (5~66) winsize 62
718 16:31:08.100293 [CA 3] Center 35 (4~66) winsize 63
719 16:31:08.100377 [CA 4] Center 34 (4~65) winsize 62
720 16:31:08.100489 [CA 5] Center 33 (3~64) winsize 62
721 16:31:08.100588
722 16:31:08.100667 [CmdBusTrainingLP45] Vref(ca) range 1: 34
723 16:31:08.100770
724 16:31:08.100865 [CATrainingPosCal] consider 1 rank data
725 16:31:08.100970 u2DelayCellTimex100 = 270/100 ps
726 16:31:08.101066 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
727 16:31:08.101161 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
728 16:31:08.101256 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
729 16:31:08.101350 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
730 16:31:08.101444 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
731 16:31:08.101539 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
732 16:31:08.101632
733 16:31:08.101726 CA PerBit enable=1, Macro0, CA PI delay=33
734 16:31:08.101819
735 16:31:08.101913 [CBTSetCACLKResult] CA Dly = 33
736 16:31:08.102006 CS Dly: 6 (0~37)
737 16:31:08.102099 ==
738 16:31:08.102193 Dram Type= 6, Freq= 0, CH_0, rank 1
739 16:31:08.102288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
740 16:31:08.102382 ==
741 16:31:08.102477 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
742 16:31:08.102572 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
743 16:31:08.102666 [CA 0] Center 38 (7~69) winsize 63
744 16:31:08.102761 [CA 1] Center 38 (7~69) winsize 63
745 16:31:08.102854 [CA 2] Center 36 (6~67) winsize 62
746 16:31:08.102948 [CA 3] Center 36 (5~67) winsize 63
747 16:31:08.103042 [CA 4] Center 35 (4~66) winsize 63
748 16:31:08.103136 [CA 5] Center 34 (4~65) winsize 62
749 16:31:08.103229
750 16:31:08.103322 [CmdBusTrainingLP45] Vref(ca) range 1: 34
751 16:31:08.103416
752 16:31:08.103509 [CATrainingPosCal] consider 2 rank data
753 16:31:08.103603 u2DelayCellTimex100 = 270/100 ps
754 16:31:08.103697 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
755 16:31:08.103791 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
756 16:31:08.103885 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
757 16:31:08.103979 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
758 16:31:08.104073 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
759 16:31:08.104168 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
760 16:31:08.104261
761 16:31:08.104354 CA PerBit enable=1, Macro0, CA PI delay=34
762 16:31:08.104448
763 16:31:08.104541 [CBTSetCACLKResult] CA Dly = 34
764 16:31:08.104652 CS Dly: 6 (0~38)
765 16:31:08.104708
766 16:31:08.104763 ----->DramcWriteLeveling(PI) begin...
767 16:31:08.104818 ==
768 16:31:08.104873 Dram Type= 6, Freq= 0, CH_0, rank 0
769 16:31:08.104928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
770 16:31:08.104983 ==
771 16:31:08.105037 Write leveling (Byte 0): 33 => 33
772 16:31:08.105092 Write leveling (Byte 1): 28 => 28
773 16:31:08.105146 DramcWriteLeveling(PI) end<-----
774 16:31:08.105200
775 16:31:08.105254 ==
776 16:31:08.105307 Dram Type= 6, Freq= 0, CH_0, rank 0
777 16:31:08.105362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
778 16:31:08.105439 ==
779 16:31:08.105499 [Gating] SW mode calibration
780 16:31:08.105555 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
781 16:31:08.105611 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
782 16:31:08.105665 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
783 16:31:08.105720 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
784 16:31:08.105773 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 16:31:08.105828 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 16:31:08.105881 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 16:31:08.105934 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 16:31:08.105988 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 16:31:08.106043 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 16:31:08.106097 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 16:31:08.106151 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 16:31:08.106205 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 16:31:08.106260 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 16:31:08.106314 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 16:31:08.106369 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 16:31:08.106423 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 16:31:08.106477 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 16:31:08.106532 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 16:31:08.106586 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 16:31:08.106640 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
801 16:31:08.106694 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 16:31:08.106748 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 16:31:08.106802 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 16:31:08.106856 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 16:31:08.106910 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 16:31:08.106964 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 16:31:08.107018 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
808 16:31:08.107073 0 9 8 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
809 16:31:08.107127 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
810 16:31:08.107181 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 16:31:08.107235 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 16:31:08.107289 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 16:31:08.107344 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 16:31:08.107606 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
815 16:31:08.107670 0 10 4 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
816 16:31:08.107727 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
817 16:31:08.107783 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
818 16:31:08.107839 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 16:31:08.107893 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 16:31:08.107948 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 16:31:08.108003 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 16:31:08.108057 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 16:31:08.108111 0 11 4 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
824 16:31:08.108166 0 11 8 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
825 16:31:08.108220 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
826 16:31:08.108275 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 16:31:08.108329 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 16:31:08.108383 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 16:31:08.108438 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 16:31:08.108493 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 16:31:08.108559 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 16:31:08.108617 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
833 16:31:08.108672 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 16:31:08.108727 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 16:31:08.108781 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 16:31:08.108836 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 16:31:08.108890 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 16:31:08.108944 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 16:31:08.108998 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 16:31:08.109052 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 16:31:08.109106 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 16:31:08.109159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 16:31:08.109214 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 16:31:08.109268 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 16:31:08.109322 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 16:31:08.109376 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 16:31:08.109431 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
848 16:31:08.109485 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 16:31:08.109539 Total UI for P1: 0, mck2ui 16
850 16:31:08.109594 best dqsien dly found for B0: ( 0, 14, 4)
851 16:31:08.109657 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 16:31:08.109721 Total UI for P1: 0, mck2ui 16
853 16:31:08.109777 best dqsien dly found for B1: ( 0, 14, 8)
854 16:31:08.109832 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
855 16:31:08.109887 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
856 16:31:08.109945
857 16:31:08.109999 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
858 16:31:08.110053 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
859 16:31:08.110108 [Gating] SW calibration Done
860 16:31:08.110162 ==
861 16:31:08.110216 Dram Type= 6, Freq= 0, CH_0, rank 0
862 16:31:08.110271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 16:31:08.110325 ==
864 16:31:08.110380 RX Vref Scan: 0
865 16:31:08.110434
866 16:31:08.110488 RX Vref 0 -> 0, step: 1
867 16:31:08.110541
868 16:31:08.110595 RX Delay -130 -> 252, step: 16
869 16:31:08.110649 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
870 16:31:08.110703 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
871 16:31:08.110758 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
872 16:31:08.110812 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
873 16:31:08.110866 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
874 16:31:08.110921 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 16:31:08.110975 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 16:31:08.111029 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 16:31:08.111083 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 16:31:08.111137 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
879 16:31:08.111191 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
880 16:31:08.111246 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 16:31:08.111300 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
882 16:31:08.111355 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
883 16:31:08.111409 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 16:31:08.111463 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
885 16:31:08.111517 ==
886 16:31:08.111571 Dram Type= 6, Freq= 0, CH_0, rank 0
887 16:31:08.111626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 16:31:08.111680 ==
889 16:31:08.111734 DQS Delay:
890 16:31:08.111788 DQS0 = 0, DQS1 = 0
891 16:31:08.111842 DQM Delay:
892 16:31:08.111895 DQM0 = 88, DQM1 = 77
893 16:31:08.111949 DQ Delay:
894 16:31:08.112003 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
895 16:31:08.112057 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
896 16:31:08.112111 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
897 16:31:08.112165 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =77
898 16:31:08.112219
899 16:31:08.112273
900 16:31:08.112326 ==
901 16:31:08.112381 Dram Type= 6, Freq= 0, CH_0, rank 0
902 16:31:08.112435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 16:31:08.112490 ==
904 16:31:08.112544
905 16:31:08.112606
906 16:31:08.112660 TX Vref Scan disable
907 16:31:08.112714 == TX Byte 0 ==
908 16:31:08.112768 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
909 16:31:08.112823 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
910 16:31:08.112877 == TX Byte 1 ==
911 16:31:08.112931 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
912 16:31:08.112985 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
913 16:31:08.113039 ==
914 16:31:08.113093 Dram Type= 6, Freq= 0, CH_0, rank 0
915 16:31:08.113147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 16:31:08.113201 ==
917 16:31:08.113255 TX Vref=22, minBit 11, minWin=26, winSum=444
918 16:31:08.113309 TX Vref=24, minBit 7, minWin=27, winSum=448
919 16:31:08.113364 TX Vref=26, minBit 4, minWin=28, winSum=453
920 16:31:08.113418 TX Vref=28, minBit 3, minWin=28, winSum=453
921 16:31:08.113473 TX Vref=30, minBit 5, minWin=28, winSum=456
922 16:31:08.113719 TX Vref=32, minBit 3, minWin=28, winSum=455
923 16:31:08.113781 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 30
924 16:31:08.113838
925 16:31:08.113893 Final TX Range 1 Vref 30
926 16:31:08.113949
927 16:31:08.114003 ==
928 16:31:08.114076 Dram Type= 6, Freq= 0, CH_0, rank 0
929 16:31:08.114135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 16:31:08.114190 ==
931 16:31:08.114245
932 16:31:08.114299
933 16:31:08.114353 TX Vref Scan disable
934 16:31:08.114408 == TX Byte 0 ==
935 16:31:08.114462 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
936 16:31:08.114517 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
937 16:31:08.114572 == TX Byte 1 ==
938 16:31:08.114626 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
939 16:31:08.114681 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
940 16:31:08.114735
941 16:31:08.114790 [DATLAT]
942 16:31:08.114843 Freq=800, CH0 RK0
943 16:31:08.114902
944 16:31:08.114958 DATLAT Default: 0xa
945 16:31:08.115013 0, 0xFFFF, sum = 0
946 16:31:08.115068 1, 0xFFFF, sum = 0
947 16:31:08.115124 2, 0xFFFF, sum = 0
948 16:31:08.115179 3, 0xFFFF, sum = 0
949 16:31:08.115237 4, 0xFFFF, sum = 0
950 16:31:08.115292 5, 0xFFFF, sum = 0
951 16:31:08.115346 6, 0xFFFF, sum = 0
952 16:31:08.115400 7, 0xFFFF, sum = 0
953 16:31:08.115455 8, 0xFFFF, sum = 0
954 16:31:08.115510 9, 0x0, sum = 1
955 16:31:08.115565 10, 0x0, sum = 2
956 16:31:08.115624 11, 0x0, sum = 3
957 16:31:08.115679 12, 0x0, sum = 4
958 16:31:08.115733 best_step = 10
959 16:31:08.115787
960 16:31:08.115840 ==
961 16:31:08.115894 Dram Type= 6, Freq= 0, CH_0, rank 0
962 16:31:08.115948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 16:31:08.116002 ==
964 16:31:08.116056 RX Vref Scan: 1
965 16:31:08.116109
966 16:31:08.116163 Set Vref Range= 32 -> 127
967 16:31:08.116216
968 16:31:08.116270 RX Vref 32 -> 127, step: 1
969 16:31:08.116323
970 16:31:08.116376 RX Delay -95 -> 252, step: 8
971 16:31:08.116431
972 16:31:08.116484 Set Vref, RX VrefLevel [Byte0]: 32
973 16:31:08.116538 [Byte1]: 32
974 16:31:08.116603
975 16:31:08.116657 Set Vref, RX VrefLevel [Byte0]: 33
976 16:31:08.116711 [Byte1]: 33
977 16:31:08.116764
978 16:31:08.116818 Set Vref, RX VrefLevel [Byte0]: 34
979 16:31:08.116872 [Byte1]: 34
980 16:31:08.116926
981 16:31:08.116979 Set Vref, RX VrefLevel [Byte0]: 35
982 16:31:08.117033 [Byte1]: 35
983 16:31:08.117087
984 16:31:08.117140 Set Vref, RX VrefLevel [Byte0]: 36
985 16:31:08.117194 [Byte1]: 36
986 16:31:08.117248
987 16:31:08.117302 Set Vref, RX VrefLevel [Byte0]: 37
988 16:31:08.117355 [Byte1]: 37
989 16:31:08.117409
990 16:31:08.117462 Set Vref, RX VrefLevel [Byte0]: 38
991 16:31:08.117516 [Byte1]: 38
992 16:31:08.117569
993 16:31:08.117623 Set Vref, RX VrefLevel [Byte0]: 39
994 16:31:08.117676 [Byte1]: 39
995 16:31:08.117730
996 16:31:08.117783 Set Vref, RX VrefLevel [Byte0]: 40
997 16:31:08.117837 [Byte1]: 40
998 16:31:08.117890
999 16:31:08.117944 Set Vref, RX VrefLevel [Byte0]: 41
1000 16:31:08.117997 [Byte1]: 41
1001 16:31:08.118051
1002 16:31:08.118104 Set Vref, RX VrefLevel [Byte0]: 42
1003 16:31:08.118157 [Byte1]: 42
1004 16:31:08.118211
1005 16:31:08.118283 Set Vref, RX VrefLevel [Byte0]: 43
1006 16:31:08.118340 [Byte1]: 43
1007 16:31:08.118395
1008 16:31:08.118449 Set Vref, RX VrefLevel [Byte0]: 44
1009 16:31:08.118504 [Byte1]: 44
1010 16:31:08.118557
1011 16:31:08.118611 Set Vref, RX VrefLevel [Byte0]: 45
1012 16:31:08.118666 [Byte1]: 45
1013 16:31:08.118720
1014 16:31:08.118774 Set Vref, RX VrefLevel [Byte0]: 46
1015 16:31:08.118827 [Byte1]: 46
1016 16:31:08.118882
1017 16:31:08.118937 Set Vref, RX VrefLevel [Byte0]: 47
1018 16:31:08.118993 [Byte1]: 47
1019 16:31:08.119048
1020 16:31:08.119103 Set Vref, RX VrefLevel [Byte0]: 48
1021 16:31:08.119158 [Byte1]: 48
1022 16:31:08.119213
1023 16:31:08.119267 Set Vref, RX VrefLevel [Byte0]: 49
1024 16:31:08.119321 [Byte1]: 49
1025 16:31:08.119384
1026 16:31:08.119441 Set Vref, RX VrefLevel [Byte0]: 50
1027 16:31:08.119497 [Byte1]: 50
1028 16:31:08.119553
1029 16:31:08.119607 Set Vref, RX VrefLevel [Byte0]: 51
1030 16:31:08.119662 [Byte1]: 51
1031 16:31:08.119715
1032 16:31:08.119770 Set Vref, RX VrefLevel [Byte0]: 52
1033 16:31:08.119824 [Byte1]: 52
1034 16:31:08.119877
1035 16:31:08.119931 Set Vref, RX VrefLevel [Byte0]: 53
1036 16:31:08.119984 [Byte1]: 53
1037 16:31:08.120038
1038 16:31:08.120091 Set Vref, RX VrefLevel [Byte0]: 54
1039 16:31:08.120146 [Byte1]: 54
1040 16:31:08.120200
1041 16:31:08.120253 Set Vref, RX VrefLevel [Byte0]: 55
1042 16:31:08.120307 [Byte1]: 55
1043 16:31:08.120360
1044 16:31:08.120413 Set Vref, RX VrefLevel [Byte0]: 56
1045 16:31:08.120467 [Byte1]: 56
1046 16:31:08.120521
1047 16:31:08.120611 Set Vref, RX VrefLevel [Byte0]: 57
1048 16:31:08.120699 [Byte1]: 57
1049 16:31:08.120784
1050 16:31:08.120868 Set Vref, RX VrefLevel [Byte0]: 58
1051 16:31:08.120953 [Byte1]: 58
1052 16:31:08.121037
1053 16:31:08.121121 Set Vref, RX VrefLevel [Byte0]: 59
1054 16:31:08.121206 [Byte1]: 59
1055 16:31:08.121289
1056 16:31:08.121373 Set Vref, RX VrefLevel [Byte0]: 60
1057 16:31:08.121457 [Byte1]: 60
1058 16:31:08.121541
1059 16:31:08.121625 Set Vref, RX VrefLevel [Byte0]: 61
1060 16:31:08.121709 [Byte1]: 61
1061 16:31:08.121793
1062 16:31:08.121877 Set Vref, RX VrefLevel [Byte0]: 62
1063 16:31:08.121961 [Byte1]: 62
1064 16:31:08.122045
1065 16:31:08.122129 Set Vref, RX VrefLevel [Byte0]: 63
1066 16:31:08.122213 [Byte1]: 63
1067 16:31:08.122297
1068 16:31:08.122381 Set Vref, RX VrefLevel [Byte0]: 64
1069 16:31:08.122465 [Byte1]: 64
1070 16:31:08.122548
1071 16:31:08.122632 Set Vref, RX VrefLevel [Byte0]: 65
1072 16:31:08.122717 [Byte1]: 65
1073 16:31:08.122800
1074 16:31:08.122884 Set Vref, RX VrefLevel [Byte0]: 66
1075 16:31:08.122968 [Byte1]: 66
1076 16:31:08.123051
1077 16:31:08.123135 Set Vref, RX VrefLevel [Byte0]: 67
1078 16:31:08.123219 [Byte1]: 67
1079 16:31:08.123303
1080 16:31:08.123387 Set Vref, RX VrefLevel [Byte0]: 68
1081 16:31:08.123471 [Byte1]: 68
1082 16:31:08.123554
1083 16:31:08.123637 Set Vref, RX VrefLevel [Byte0]: 69
1084 16:31:08.123722 [Byte1]: 69
1085 16:31:08.123805
1086 16:31:08.123889 Set Vref, RX VrefLevel [Byte0]: 70
1087 16:31:08.123973 [Byte1]: 70
1088 16:31:08.124056
1089 16:31:08.124140 Set Vref, RX VrefLevel [Byte0]: 71
1090 16:31:08.124224 [Byte1]: 71
1091 16:31:08.124307
1092 16:31:08.124391 Set Vref, RX VrefLevel [Byte0]: 72
1093 16:31:08.124670 [Byte1]: 72
1094 16:31:08.124762
1095 16:31:08.124847 Set Vref, RX VrefLevel [Byte0]: 73
1096 16:31:08.124932 [Byte1]: 73
1097 16:31:08.125016
1098 16:31:08.125100 Set Vref, RX VrefLevel [Byte0]: 74
1099 16:31:08.125184 [Byte1]: 74
1100 16:31:08.125268
1101 16:31:08.125352 Set Vref, RX VrefLevel [Byte0]: 75
1102 16:31:08.125436 [Byte1]: 75
1103 16:31:08.125520
1104 16:31:08.125604 Set Vref, RX VrefLevel [Byte0]: 76
1105 16:31:08.125689 [Byte1]: 76
1106 16:31:08.125772
1107 16:31:08.125855 Final RX Vref Byte 0 = 60 to rank0
1108 16:31:08.125940 Final RX Vref Byte 1 = 56 to rank0
1109 16:31:08.126025 Final RX Vref Byte 0 = 60 to rank1
1110 16:31:08.126109 Final RX Vref Byte 1 = 56 to rank1==
1111 16:31:08.126193 Dram Type= 6, Freq= 0, CH_0, rank 0
1112 16:31:08.126278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1113 16:31:08.126362 ==
1114 16:31:08.126446 DQS Delay:
1115 16:31:08.126529 DQS0 = 0, DQS1 = 0
1116 16:31:08.126613 DQM Delay:
1117 16:31:08.126697 DQM0 = 93, DQM1 = 81
1118 16:31:08.126780 DQ Delay:
1119 16:31:08.126864 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1120 16:31:08.126948 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1121 16:31:08.127032 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =76
1122 16:31:08.127117 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1123 16:31:08.127200
1124 16:31:08.127283
1125 16:31:08.127368 [DQSOSCAuto] RK0, (LSB)MR18= 0x423d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1126 16:31:08.127453 CH0 RK0: MR19=606, MR18=423D
1127 16:31:08.127538 CH0_RK0: MR19=0x606, MR18=0x423D, DQSOSC=393, MR23=63, INC=95, DEC=63
1128 16:31:08.127622
1129 16:31:08.127706 ----->DramcWriteLeveling(PI) begin...
1130 16:31:08.127791 ==
1131 16:31:08.127875 Dram Type= 6, Freq= 0, CH_0, rank 1
1132 16:31:08.127960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 16:31:08.128044 ==
1134 16:31:08.128128 Write leveling (Byte 0): 30 => 30
1135 16:31:08.128212 Write leveling (Byte 1): 27 => 27
1136 16:31:08.128296 DramcWriteLeveling(PI) end<-----
1137 16:31:08.128379
1138 16:31:08.128462 ==
1139 16:31:08.128557 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 16:31:08.128619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 16:31:08.128675 ==
1142 16:31:08.128762 [Gating] SW mode calibration
1143 16:31:08.128821 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1144 16:31:08.128877 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1145 16:31:08.128932 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1146 16:31:08.128987 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1147 16:31:08.129041 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1148 16:31:08.129115 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 16:31:08.129185 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 16:31:08.129239 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 16:31:08.129294 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 16:31:08.129347 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 16:31:08.129401 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 16:31:08.129455 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 16:31:08.129514 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 16:31:08.129570 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 16:31:08.129626 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 16:31:08.129687 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 16:31:08.129742 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 16:31:08.129811 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 16:31:08.129870 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1162 16:31:08.129924 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1163 16:31:08.129979 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1164 16:31:08.130033 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 16:31:08.130087 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 16:31:08.130141 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 16:31:08.130194 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 16:31:08.130262 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 16:31:08.130319 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 16:31:08.130374 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1171 16:31:08.130429 0 9 8 | B1->B0 | 2f2f 3333 | 0 1 | (0 0) (1 1)
1172 16:31:08.130495 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 16:31:08.130561 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 16:31:08.130615 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 16:31:08.130669 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 16:31:08.130723 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 16:31:08.130777 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1178 16:31:08.130830 0 10 4 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
1179 16:31:08.130884 0 10 8 | B1->B0 | 2a2a 2323 | 1 1 | (1 0) (1 0)
1180 16:31:08.130937 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 16:31:08.131000 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 16:31:08.131067 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 16:31:08.131123 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 16:31:08.131177 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 16:31:08.131231 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 16:31:08.131284 0 11 4 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
1187 16:31:08.131338 0 11 8 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
1188 16:31:08.131392 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 16:31:08.131446 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 16:31:08.131500 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 16:31:08.131554 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 16:31:08.131609 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 16:31:08.131662 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 16:31:08.131716 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 16:31:08.131770 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 16:31:08.132018 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 16:31:08.132079 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 16:31:08.132135 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 16:31:08.132190 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 16:31:08.132244 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 16:31:08.132299 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 16:31:08.132354 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 16:31:08.132408 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 16:31:08.132462 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 16:31:08.132516 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 16:31:08.132583 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 16:31:08.132638 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 16:31:08.132693 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 16:31:08.132747 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 16:31:08.132801 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1211 16:31:08.132855 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1212 16:31:08.132909 Total UI for P1: 0, mck2ui 16
1213 16:31:08.132964 best dqsien dly found for B1: ( 0, 14, 4)
1214 16:31:08.133019 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 16:31:08.133073 Total UI for P1: 0, mck2ui 16
1216 16:31:08.133127 best dqsien dly found for B0: ( 0, 14, 6)
1217 16:31:08.133181 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1218 16:31:08.133235 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1219 16:31:08.133290
1220 16:31:08.133344 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1221 16:31:08.133398 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1222 16:31:08.133474 [Gating] SW calibration Done
1223 16:31:08.133530 ==
1224 16:31:08.133588 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 16:31:08.133655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 16:31:08.133722 ==
1227 16:31:08.133778 RX Vref Scan: 0
1228 16:31:08.133832
1229 16:31:08.133886 RX Vref 0 -> 0, step: 1
1230 16:31:08.133940
1231 16:31:08.133993 RX Delay -130 -> 252, step: 16
1232 16:31:08.134047 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1233 16:31:08.134102 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1234 16:31:08.134155 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1235 16:31:08.134217 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1236 16:31:08.134272 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1237 16:31:08.134340 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1238 16:31:08.134394 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1239 16:31:08.134448 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1240 16:31:08.134501 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1241 16:31:08.134555 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1242 16:31:08.134609 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1243 16:31:08.134663 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1244 16:31:08.134717 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1245 16:31:08.134770 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1246 16:31:08.134824 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1247 16:31:08.134878 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1248 16:31:08.134931 ==
1249 16:31:08.134985 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 16:31:08.135040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1251 16:31:08.135094 ==
1252 16:31:08.135147 DQS Delay:
1253 16:31:08.135202 DQS0 = 0, DQS1 = 0
1254 16:31:08.135255 DQM Delay:
1255 16:31:08.135309 DQM0 = 92, DQM1 = 80
1256 16:31:08.135362 DQ Delay:
1257 16:31:08.135438 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1258 16:31:08.135495 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1259 16:31:08.135568 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1260 16:31:08.135625 DQ12 =93, DQ13 =85, DQ14 =93, DQ15 =85
1261 16:31:08.135680
1262 16:31:08.135734
1263 16:31:08.135787 ==
1264 16:31:08.135841 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 16:31:08.135896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 16:31:08.135951 ==
1267 16:31:08.136016
1268 16:31:08.136073
1269 16:31:08.136127 TX Vref Scan disable
1270 16:31:08.136181 == TX Byte 0 ==
1271 16:31:08.136235 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1272 16:31:08.136293 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1273 16:31:08.136349 == TX Byte 1 ==
1274 16:31:08.136405 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1275 16:31:08.136467 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1276 16:31:08.136522 ==
1277 16:31:08.136589 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 16:31:08.136645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 16:31:08.136717 ==
1280 16:31:08.136772 TX Vref=22, minBit 8, minWin=27, winSum=450
1281 16:31:08.136827 TX Vref=24, minBit 12, minWin=27, winSum=451
1282 16:31:08.136882 TX Vref=26, minBit 1, minWin=28, winSum=453
1283 16:31:08.136938 TX Vref=28, minBit 8, minWin=28, winSum=458
1284 16:31:08.136992 TX Vref=30, minBit 10, minWin=27, winSum=459
1285 16:31:08.137046 TX Vref=32, minBit 8, minWin=27, winSum=456
1286 16:31:08.137100 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
1287 16:31:08.137154
1288 16:31:08.137208 Final TX Range 1 Vref 28
1289 16:31:08.137262
1290 16:31:08.137315 ==
1291 16:31:08.137369 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 16:31:08.137423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 16:31:08.137477 ==
1294 16:31:08.137530
1295 16:31:08.137597
1296 16:31:08.137653 TX Vref Scan disable
1297 16:31:08.137718 == TX Byte 0 ==
1298 16:31:08.137783 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1299 16:31:08.137837 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1300 16:31:08.137890 == TX Byte 1 ==
1301 16:31:08.137943 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1302 16:31:08.137995 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1303 16:31:08.138048
1304 16:31:08.138100 [DATLAT]
1305 16:31:08.138157 Freq=800, CH0 RK1
1306 16:31:08.138223
1307 16:31:08.138277 DATLAT Default: 0xa
1308 16:31:08.138330 0, 0xFFFF, sum = 0
1309 16:31:08.138384 1, 0xFFFF, sum = 0
1310 16:31:08.138437 2, 0xFFFF, sum = 0
1311 16:31:08.138490 3, 0xFFFF, sum = 0
1312 16:31:08.138543 4, 0xFFFF, sum = 0
1313 16:31:08.138614 5, 0xFFFF, sum = 0
1314 16:31:08.138669 6, 0xFFFF, sum = 0
1315 16:31:08.138734 7, 0xFFFF, sum = 0
1316 16:31:08.138799 8, 0xFFFF, sum = 0
1317 16:31:08.138854 9, 0x0, sum = 1
1318 16:31:08.138908 10, 0x0, sum = 2
1319 16:31:08.138961 11, 0x0, sum = 3
1320 16:31:08.139014 12, 0x0, sum = 4
1321 16:31:08.139066 best_step = 10
1322 16:31:08.139119
1323 16:31:08.139171 ==
1324 16:31:08.139242 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 16:31:08.139297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 16:31:08.139350 ==
1327 16:31:08.139402 RX Vref Scan: 0
1328 16:31:08.139454
1329 16:31:08.139506 RX Vref 0 -> 0, step: 1
1330 16:31:08.139558
1331 16:31:08.139824 RX Delay -95 -> 252, step: 8
1332 16:31:08.139898 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1333 16:31:08.139965 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1334 16:31:08.140020 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1335 16:31:08.140073 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1336 16:31:08.140126 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1337 16:31:08.140179 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1338 16:31:08.140238 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1339 16:31:08.140291 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1340 16:31:08.140344 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1341 16:31:08.140396 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1342 16:31:08.140449 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1343 16:31:08.140502 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1344 16:31:08.140570 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1345 16:31:08.140625 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1346 16:31:08.140681 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1347 16:31:08.140734 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1348 16:31:08.140787 ==
1349 16:31:08.140839 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 16:31:08.140896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 16:31:08.140949 ==
1352 16:31:08.141001 DQS Delay:
1353 16:31:08.141054 DQS0 = 0, DQS1 = 0
1354 16:31:08.141106 DQM Delay:
1355 16:31:08.141158 DQM0 = 90, DQM1 = 81
1356 16:31:08.141213 DQ Delay:
1357 16:31:08.141268 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1358 16:31:08.141323 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1359 16:31:08.141375 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =80
1360 16:31:08.141433 DQ12 =84, DQ13 =88, DQ14 =88, DQ15 =88
1361 16:31:08.141485
1362 16:31:08.141537
1363 16:31:08.141589 [DQSOSCAuto] RK1, (LSB)MR18= 0x431d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1364 16:31:08.141643 CH0 RK1: MR19=606, MR18=431D
1365 16:31:08.141694 CH0_RK1: MR19=0x606, MR18=0x431D, DQSOSC=393, MR23=63, INC=95, DEC=63
1366 16:31:08.141747 [RxdqsGatingPostProcess] freq 800
1367 16:31:08.141799 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1368 16:31:08.141851 Pre-setting of DQS Precalculation
1369 16:31:08.141903 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1370 16:31:08.141955 ==
1371 16:31:08.142007 Dram Type= 6, Freq= 0, CH_1, rank 0
1372 16:31:08.142059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 16:31:08.142112 ==
1374 16:31:08.142163 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1375 16:31:08.142216 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1376 16:31:08.142270 [CA 0] Center 36 (6~67) winsize 62
1377 16:31:08.142322 [CA 1] Center 36 (6~67) winsize 62
1378 16:31:08.142374 [CA 2] Center 35 (5~65) winsize 61
1379 16:31:08.142427 [CA 3] Center 34 (4~65) winsize 62
1380 16:31:08.142479 [CA 4] Center 34 (4~65) winsize 62
1381 16:31:08.142531 [CA 5] Center 33 (3~64) winsize 62
1382 16:31:08.142583
1383 16:31:08.142635 [CmdBusTrainingLP45] Vref(ca) range 1: 28
1384 16:31:08.142687
1385 16:31:08.142738 [CATrainingPosCal] consider 1 rank data
1386 16:31:08.142790 u2DelayCellTimex100 = 270/100 ps
1387 16:31:08.142842 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1388 16:31:08.142894 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1389 16:31:08.142946 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1390 16:31:08.142998 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1391 16:31:08.143050 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1392 16:31:08.143102 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1393 16:31:08.143154
1394 16:31:08.143206 CA PerBit enable=1, Macro0, CA PI delay=33
1395 16:31:08.143258
1396 16:31:08.143309 [CBTSetCACLKResult] CA Dly = 33
1397 16:31:08.143361 CS Dly: 5 (0~36)
1398 16:31:08.143413 ==
1399 16:31:08.143471 Dram Type= 6, Freq= 0, CH_1, rank 1
1400 16:31:08.143523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 16:31:08.143576 ==
1402 16:31:08.143629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1403 16:31:08.143682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1404 16:31:08.143734 [CA 0] Center 36 (6~67) winsize 62
1405 16:31:08.143786 [CA 1] Center 37 (6~68) winsize 63
1406 16:31:08.143838 [CA 2] Center 35 (5~66) winsize 62
1407 16:31:08.143890 [CA 3] Center 34 (4~65) winsize 62
1408 16:31:08.143941 [CA 4] Center 34 (4~65) winsize 62
1409 16:31:08.144009 [CA 5] Center 34 (4~64) winsize 61
1410 16:31:08.144065
1411 16:31:08.144117 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1412 16:31:08.144183
1413 16:31:08.144236 [CATrainingPosCal] consider 2 rank data
1414 16:31:08.144288 u2DelayCellTimex100 = 270/100 ps
1415 16:31:08.144375 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1416 16:31:08.144434 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1417 16:31:08.144487 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1418 16:31:08.144542 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1419 16:31:08.144608 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1420 16:31:08.144661 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1421 16:31:08.144713
1422 16:31:08.144765 CA PerBit enable=1, Macro0, CA PI delay=34
1423 16:31:08.144825
1424 16:31:08.144878 [CBTSetCACLKResult] CA Dly = 34
1425 16:31:08.144944 CS Dly: 6 (0~38)
1426 16:31:08.145002
1427 16:31:08.145055 ----->DramcWriteLeveling(PI) begin...
1428 16:31:08.145109 ==
1429 16:31:08.145164 Dram Type= 6, Freq= 0, CH_1, rank 0
1430 16:31:08.145217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1431 16:31:08.145270 ==
1432 16:31:08.145340 Write leveling (Byte 0): 25 => 25
1433 16:31:08.145393 Write leveling (Byte 1): 29 => 29
1434 16:31:08.145459 DramcWriteLeveling(PI) end<-----
1435 16:31:08.145524
1436 16:31:08.145577 ==
1437 16:31:08.145629 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 16:31:08.145681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 16:31:08.145734 ==
1440 16:31:08.145786 [Gating] SW mode calibration
1441 16:31:08.145839 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1442 16:31:08.145898 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1443 16:31:08.145953 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1444 16:31:08.146009 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 16:31:08.146061 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 16:31:08.146113 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 16:31:08.146179 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 16:31:08.146433 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 16:31:08.146498 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 16:31:08.146555 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 16:31:08.146611 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 16:31:08.146664 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 16:31:08.146718 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 16:31:08.146771 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 16:31:08.146824 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 16:31:08.146877 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 16:31:08.146929 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 16:31:08.146981 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 16:31:08.147033 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1460 16:31:08.147085 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1461 16:31:08.147138 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1462 16:31:08.147190 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 16:31:08.147242 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 16:31:08.147294 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 16:31:08.147346 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 16:31:08.147398 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 16:31:08.147449 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 16:31:08.147502 0 9 4 | B1->B0 | 2424 2a2a | 0 1 | (0 0) (1 1)
1469 16:31:08.147554 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 16:31:08.147610 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 16:31:08.147664 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 16:31:08.147719 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 16:31:08.147773 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 16:31:08.147825 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 16:31:08.147877 0 10 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1476 16:31:08.147932 0 10 4 | B1->B0 | 2f2f 2c2c | 0 0 | (1 0) (0 0)
1477 16:31:08.147985 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 16:31:08.148037 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 16:31:08.148089 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 16:31:08.148141 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 16:31:08.148196 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 16:31:08.148251 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 16:31:08.148306 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 16:31:08.148359 0 11 4 | B1->B0 | 3030 3737 | 0 0 | (0 0) (0 0)
1485 16:31:08.148414 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 16:31:08.148468 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 16:31:08.148520 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 16:31:08.148584 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 16:31:08.148637 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 16:31:08.148690 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 16:31:08.148742 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 16:31:08.148794 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1493 16:31:08.148867 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 16:31:08.148922 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 16:31:08.148974 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 16:31:08.149026 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 16:31:08.149078 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 16:31:08.149130 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 16:31:08.149182 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 16:31:08.149234 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 16:31:08.149286 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 16:31:08.149338 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 16:31:08.149391 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 16:31:08.149443 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 16:31:08.149495 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 16:31:08.149548 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 16:31:08.149599 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1508 16:31:08.149651 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1509 16:31:08.149703 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 16:31:08.149755 Total UI for P1: 0, mck2ui 16
1511 16:31:08.149808 best dqsien dly found for B0: ( 0, 14, 2)
1512 16:31:08.149860 Total UI for P1: 0, mck2ui 16
1513 16:31:08.149913 best dqsien dly found for B1: ( 0, 14, 4)
1514 16:31:08.149966 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1515 16:31:08.150018 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1516 16:31:08.150070
1517 16:31:08.150122 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1518 16:31:08.150175 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1519 16:31:08.150227 [Gating] SW calibration Done
1520 16:31:08.150298 ==
1521 16:31:08.150355 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 16:31:08.150422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 16:31:08.150489 ==
1524 16:31:08.150542 RX Vref Scan: 0
1525 16:31:08.150593
1526 16:31:08.150645 RX Vref 0 -> 0, step: 1
1527 16:31:08.150697
1528 16:31:08.150750 RX Delay -130 -> 252, step: 16
1529 16:31:08.150802 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1530 16:31:08.150863 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1531 16:31:08.150928 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1532 16:31:08.150981 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1533 16:31:08.151034 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1534 16:31:08.151086 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1535 16:31:08.151139 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1536 16:31:08.151191 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1537 16:31:08.151243 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1538 16:31:08.151491 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1539 16:31:08.151551 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1540 16:31:08.151605 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1541 16:31:08.151658 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1542 16:31:08.151710 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1543 16:31:08.151763 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1544 16:31:08.151814 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1545 16:31:08.151866 ==
1546 16:31:08.151918 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 16:31:08.151970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1548 16:31:08.152023 ==
1549 16:31:08.152075 DQS Delay:
1550 16:31:08.152127 DQS0 = 0, DQS1 = 0
1551 16:31:08.152179 DQM Delay:
1552 16:31:08.152230 DQM0 = 89, DQM1 = 80
1553 16:31:08.152282 DQ Delay:
1554 16:31:08.152334 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1555 16:31:08.152386 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1556 16:31:08.152437 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1557 16:31:08.152489 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1558 16:31:08.152541
1559 16:31:08.152606
1560 16:31:08.152659 ==
1561 16:31:08.152712 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 16:31:08.152764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 16:31:08.152817 ==
1564 16:31:08.152868
1565 16:31:08.152920
1566 16:31:08.152970 TX Vref Scan disable
1567 16:31:08.153022 == TX Byte 0 ==
1568 16:31:08.153075 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1569 16:31:08.153127 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1570 16:31:08.153179 == TX Byte 1 ==
1571 16:31:08.153230 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1572 16:31:08.153282 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1573 16:31:08.153333 ==
1574 16:31:08.153385 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 16:31:08.153436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 16:31:08.153488 ==
1577 16:31:08.153540 TX Vref=22, minBit 10, minWin=27, winSum=448
1578 16:31:08.153592 TX Vref=24, minBit 15, minWin=27, winSum=455
1579 16:31:08.153644 TX Vref=26, minBit 15, minWin=27, winSum=457
1580 16:31:08.153697 TX Vref=28, minBit 15, minWin=27, winSum=456
1581 16:31:08.153749 TX Vref=30, minBit 15, minWin=27, winSum=459
1582 16:31:08.153801 TX Vref=32, minBit 15, minWin=27, winSum=458
1583 16:31:08.153854 [TxChooseVref] Worse bit 15, Min win 27, Win sum 459, Final Vref 30
1584 16:31:08.153907
1585 16:31:08.153972 Final TX Range 1 Vref 30
1586 16:31:08.154029
1587 16:31:08.154080 ==
1588 16:31:08.154132 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 16:31:08.154185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 16:31:08.154255 ==
1591 16:31:08.154314
1592 16:31:08.154366
1593 16:31:08.154418 TX Vref Scan disable
1594 16:31:08.154485 == TX Byte 0 ==
1595 16:31:08.154547 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1596 16:31:08.154605 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1597 16:31:08.154657 == TX Byte 1 ==
1598 16:31:08.154709 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1599 16:31:08.154762 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1600 16:31:08.154814
1601 16:31:08.154868 [DATLAT]
1602 16:31:08.154924 Freq=800, CH1 RK0
1603 16:31:08.154985
1604 16:31:08.155050 DATLAT Default: 0xa
1605 16:31:08.155106 0, 0xFFFF, sum = 0
1606 16:31:08.155162 1, 0xFFFF, sum = 0
1607 16:31:08.155215 2, 0xFFFF, sum = 0
1608 16:31:08.155268 3, 0xFFFF, sum = 0
1609 16:31:08.155320 4, 0xFFFF, sum = 0
1610 16:31:08.155373 5, 0xFFFF, sum = 0
1611 16:31:08.155426 6, 0xFFFF, sum = 0
1612 16:31:08.155478 7, 0xFFFF, sum = 0
1613 16:31:08.155530 8, 0xFFFF, sum = 0
1614 16:31:08.155583 9, 0x0, sum = 1
1615 16:31:08.155635 10, 0x0, sum = 2
1616 16:31:08.155688 11, 0x0, sum = 3
1617 16:31:08.155740 12, 0x0, sum = 4
1618 16:31:08.155793 best_step = 10
1619 16:31:08.155845
1620 16:31:08.155897 ==
1621 16:31:08.155948 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 16:31:08.156000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 16:31:08.156053 ==
1624 16:31:08.156105 RX Vref Scan: 1
1625 16:31:08.156156
1626 16:31:08.156208 Set Vref Range= 32 -> 127
1627 16:31:08.156259
1628 16:31:08.156310 RX Vref 32 -> 127, step: 1
1629 16:31:08.156362
1630 16:31:08.156413 RX Delay -95 -> 252, step: 8
1631 16:31:08.156465
1632 16:31:08.156516 Set Vref, RX VrefLevel [Byte0]: 32
1633 16:31:08.156599 [Byte1]: 32
1634 16:31:08.156664
1635 16:31:08.156730 Set Vref, RX VrefLevel [Byte0]: 33
1636 16:31:08.156783 [Byte1]: 33
1637 16:31:08.156835
1638 16:31:08.156887 Set Vref, RX VrefLevel [Byte0]: 34
1639 16:31:08.156939 [Byte1]: 34
1640 16:31:08.156992
1641 16:31:08.157044 Set Vref, RX VrefLevel [Byte0]: 35
1642 16:31:08.157103 [Byte1]: 35
1643 16:31:08.157170
1644 16:31:08.157223 Set Vref, RX VrefLevel [Byte0]: 36
1645 16:31:08.157275 [Byte1]: 36
1646 16:31:08.157327
1647 16:31:08.157382 Set Vref, RX VrefLevel [Byte0]: 37
1648 16:31:08.157435 [Byte1]: 37
1649 16:31:08.157487
1650 16:31:08.157538 Set Vref, RX VrefLevel [Byte0]: 38
1651 16:31:08.157594 [Byte1]: 38
1652 16:31:08.157647
1653 16:31:08.157699 Set Vref, RX VrefLevel [Byte0]: 39
1654 16:31:08.157751 [Byte1]: 39
1655 16:31:08.157802
1656 16:31:08.157853 Set Vref, RX VrefLevel [Byte0]: 40
1657 16:31:08.157905 [Byte1]: 40
1658 16:31:08.157960
1659 16:31:08.158013 Set Vref, RX VrefLevel [Byte0]: 41
1660 16:31:08.158068 [Byte1]: 41
1661 16:31:08.158120
1662 16:31:08.158176 Set Vref, RX VrefLevel [Byte0]: 42
1663 16:31:08.158242 [Byte1]: 42
1664 16:31:08.158299
1665 16:31:08.158354 Set Vref, RX VrefLevel [Byte0]: 43
1666 16:31:08.158406 [Byte1]: 43
1667 16:31:08.158458
1668 16:31:08.158510 Set Vref, RX VrefLevel [Byte0]: 44
1669 16:31:08.158562 [Byte1]: 44
1670 16:31:08.158614
1671 16:31:08.158669 Set Vref, RX VrefLevel [Byte0]: 45
1672 16:31:08.158723 [Byte1]: 45
1673 16:31:08.158777
1674 16:31:08.158830 Set Vref, RX VrefLevel [Byte0]: 46
1675 16:31:08.158886 [Byte1]: 46
1676 16:31:08.158939
1677 16:31:08.158991 Set Vref, RX VrefLevel [Byte0]: 47
1678 16:31:08.159061 [Byte1]: 47
1679 16:31:08.159114
1680 16:31:08.159181 Set Vref, RX VrefLevel [Byte0]: 48
1681 16:31:08.159234 [Byte1]: 48
1682 16:31:08.159286
1683 16:31:08.159341 Set Vref, RX VrefLevel [Byte0]: 49
1684 16:31:08.159405 [Byte1]: 49
1685 16:31:08.159458
1686 16:31:08.159513 Set Vref, RX VrefLevel [Byte0]: 50
1687 16:31:08.159565 [Byte1]: 50
1688 16:31:08.159618
1689 16:31:08.159670 Set Vref, RX VrefLevel [Byte0]: 51
1690 16:31:08.159723 [Byte1]: 51
1691 16:31:08.159782
1692 16:31:08.159837 Set Vref, RX VrefLevel [Byte0]: 52
1693 16:31:08.159903 [Byte1]: 52
1694 16:31:08.159956
1695 16:31:08.160021 Set Vref, RX VrefLevel [Byte0]: 53
1696 16:31:08.160080 [Byte1]: 53
1697 16:31:08.160135
1698 16:31:08.160198 Set Vref, RX VrefLevel [Byte0]: 54
1699 16:31:08.160263 [Byte1]: 54
1700 16:31:08.160319
1701 16:31:08.160576 Set Vref, RX VrefLevel [Byte0]: 55
1702 16:31:08.160645 [Byte1]: 55
1703 16:31:08.160715
1704 16:31:08.160774 Set Vref, RX VrefLevel [Byte0]: 56
1705 16:31:08.160828 [Byte1]: 56
1706 16:31:08.160882
1707 16:31:08.160936 Set Vref, RX VrefLevel [Byte0]: 57
1708 16:31:08.160989 [Byte1]: 57
1709 16:31:08.161041
1710 16:31:08.161094 Set Vref, RX VrefLevel [Byte0]: 58
1711 16:31:08.161146 [Byte1]: 58
1712 16:31:08.161198
1713 16:31:08.161254 Set Vref, RX VrefLevel [Byte0]: 59
1714 16:31:08.161314 [Byte1]: 59
1715 16:31:08.161368
1716 16:31:08.161423 Set Vref, RX VrefLevel [Byte0]: 60
1717 16:31:08.161476 [Byte1]: 60
1718 16:31:08.161528
1719 16:31:08.161580 Set Vref, RX VrefLevel [Byte0]: 61
1720 16:31:08.161631 [Byte1]: 61
1721 16:31:08.161683
1722 16:31:08.161735 Set Vref, RX VrefLevel [Byte0]: 62
1723 16:31:08.161792 [Byte1]: 62
1724 16:31:08.161845
1725 16:31:08.161910 Set Vref, RX VrefLevel [Byte0]: 63
1726 16:31:08.162009 [Byte1]: 63
1727 16:31:08.162069
1728 16:31:08.162123 Set Vref, RX VrefLevel [Byte0]: 64
1729 16:31:08.162180 [Byte1]: 64
1730 16:31:08.162233
1731 16:31:08.162285 Set Vref, RX VrefLevel [Byte0]: 65
1732 16:31:08.162342 [Byte1]: 65
1733 16:31:08.162395
1734 16:31:08.162457 Set Vref, RX VrefLevel [Byte0]: 66
1735 16:31:08.162517 [Byte1]: 66
1736 16:31:08.162569
1737 16:31:08.162621 Set Vref, RX VrefLevel [Byte0]: 67
1738 16:31:08.162678 [Byte1]: 67
1739 16:31:08.162732
1740 16:31:08.162788 Set Vref, RX VrefLevel [Byte0]: 68
1741 16:31:08.162841 [Byte1]: 68
1742 16:31:08.162897
1743 16:31:08.162949 Set Vref, RX VrefLevel [Byte0]: 69
1744 16:31:08.163001 [Byte1]: 69
1745 16:31:08.163053
1746 16:31:08.163104 Set Vref, RX VrefLevel [Byte0]: 70
1747 16:31:08.163157 [Byte1]: 70
1748 16:31:08.163208
1749 16:31:08.163260 Set Vref, RX VrefLevel [Byte0]: 71
1750 16:31:08.163313 [Byte1]: 71
1751 16:31:08.163365
1752 16:31:08.163417 Set Vref, RX VrefLevel [Byte0]: 72
1753 16:31:08.163469 [Byte1]: 72
1754 16:31:08.163539
1755 16:31:08.163596 Set Vref, RX VrefLevel [Byte0]: 73
1756 16:31:08.163650 [Byte1]: 73
1757 16:31:08.163716
1758 16:31:08.163769 Set Vref, RX VrefLevel [Byte0]: 74
1759 16:31:08.163821 [Byte1]: 74
1760 16:31:08.163874
1761 16:31:08.163925 Set Vref, RX VrefLevel [Byte0]: 75
1762 16:31:08.163977 [Byte1]: 75
1763 16:31:08.164045
1764 16:31:08.164098 Set Vref, RX VrefLevel [Byte0]: 76
1765 16:31:08.164150 [Byte1]: 76
1766 16:31:08.164202
1767 16:31:08.164253 Set Vref, RX VrefLevel [Byte0]: 77
1768 16:31:08.164305 [Byte1]: 77
1769 16:31:08.164360
1770 16:31:08.164414 Set Vref, RX VrefLevel [Byte0]: 78
1771 16:31:08.164468 [Byte1]: 78
1772 16:31:08.164528
1773 16:31:08.164608 Final RX Vref Byte 0 = 50 to rank0
1774 16:31:08.164665 Final RX Vref Byte 1 = 63 to rank0
1775 16:31:08.164718 Final RX Vref Byte 0 = 50 to rank1
1776 16:31:08.164771 Final RX Vref Byte 1 = 63 to rank1==
1777 16:31:08.164837 Dram Type= 6, Freq= 0, CH_1, rank 0
1778 16:31:08.164892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1779 16:31:08.164945 ==
1780 16:31:08.164997 DQS Delay:
1781 16:31:08.165074 DQS0 = 0, DQS1 = 0
1782 16:31:08.165128 DQM Delay:
1783 16:31:08.165180 DQM0 = 91, DQM1 = 82
1784 16:31:08.165232 DQ Delay:
1785 16:31:08.165284 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1786 16:31:08.165337 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1787 16:31:08.165389 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =80
1788 16:31:08.165441 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1789 16:31:08.165501
1790 16:31:08.165553
1791 16:31:08.165617 [DQSOSCAuto] RK0, (LSB)MR18= 0x3250, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 397 ps
1792 16:31:08.165670 CH1 RK0: MR19=606, MR18=3250
1793 16:31:08.165723 CH1_RK0: MR19=0x606, MR18=0x3250, DQSOSC=389, MR23=63, INC=97, DEC=65
1794 16:31:08.165779
1795 16:31:08.165832 ----->DramcWriteLeveling(PI) begin...
1796 16:31:08.165884 ==
1797 16:31:08.165937 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 16:31:08.165989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 16:31:08.166045 ==
1800 16:31:08.166097 Write leveling (Byte 0): 24 => 24
1801 16:31:08.166150 Write leveling (Byte 1): 31 => 31
1802 16:31:08.166203 DramcWriteLeveling(PI) end<-----
1803 16:31:08.166254
1804 16:31:08.166306 ==
1805 16:31:08.166360 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 16:31:08.166415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 16:31:08.166469 ==
1808 16:31:08.166521 [Gating] SW mode calibration
1809 16:31:08.166572 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1810 16:31:08.166626 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1811 16:31:08.166682 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1812 16:31:08.166737 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1813 16:31:08.166789 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1814 16:31:08.166843 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 16:31:08.166915 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 16:31:08.166971 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 16:31:08.167023 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 16:31:08.167076 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 16:31:08.167128 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 16:31:08.167180 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 16:31:08.167232 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 16:31:08.167284 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 16:31:08.167337 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 16:31:08.167389 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 16:31:08.167441 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 16:31:08.167493 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 16:31:08.167545 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 16:31:08.167597 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1829 16:31:08.167648 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 16:31:08.167700 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 16:31:08.167752 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 16:31:08.168001 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 16:31:08.168062 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 16:31:08.168116 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 16:31:08.168169 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 16:31:08.168221 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1837 16:31:08.168273 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 16:31:08.168326 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 16:31:08.168379 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 16:31:08.168431 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 16:31:08.168483 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 16:31:08.168535 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 16:31:08.168599 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 16:31:08.168653 0 10 4 | B1->B0 | 2d2d 3030 | 0 0 | (1 1) (1 1)
1845 16:31:08.168705 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1846 16:31:08.168757 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 16:31:08.168810 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 16:31:08.168863 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 16:31:08.168915 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 16:31:08.168968 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 16:31:08.169020 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 16:31:08.169072 0 11 4 | B1->B0 | 3535 3232 | 0 0 | (0 0) (0 0)
1853 16:31:08.169124 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 16:31:08.169177 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 16:31:08.169228 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 16:31:08.169280 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 16:31:08.169332 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 16:31:08.169384 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 16:31:08.169436 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1860 16:31:08.169488 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1861 16:31:08.169540 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1862 16:31:08.169592 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 16:31:08.169644 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 16:31:08.169696 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 16:31:08.169748 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 16:31:08.169799 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 16:31:08.169852 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 16:31:08.169904 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 16:31:08.169956 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 16:31:08.170008 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 16:31:08.170060 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 16:31:08.170112 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 16:31:08.170164 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 16:31:08.170216 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 16:31:08.170268 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1876 16:31:08.170319 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1877 16:31:08.170371 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 16:31:08.170423 Total UI for P1: 0, mck2ui 16
1879 16:31:08.170495 best dqsien dly found for B0: ( 0, 14, 2)
1880 16:31:08.170561 Total UI for P1: 0, mck2ui 16
1881 16:31:08.170629 best dqsien dly found for B1: ( 0, 14, 4)
1882 16:31:08.170682 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1883 16:31:08.170735 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1884 16:31:08.170788
1885 16:31:08.170839 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1886 16:31:08.170892 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1887 16:31:08.170944 [Gating] SW calibration Done
1888 16:31:08.171004 ==
1889 16:31:08.171070 Dram Type= 6, Freq= 0, CH_1, rank 1
1890 16:31:08.171143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1891 16:31:08.171198 ==
1892 16:31:08.171251 RX Vref Scan: 0
1893 16:31:08.171303
1894 16:31:08.171355 RX Vref 0 -> 0, step: 1
1895 16:31:08.171406
1896 16:31:08.171458 RX Delay -130 -> 252, step: 16
1897 16:31:08.171510 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1898 16:31:08.171563 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1899 16:31:08.171615 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1900 16:31:08.171667 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1901 16:31:08.171719 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1902 16:31:08.171772 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1903 16:31:08.171824 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1904 16:31:08.171876 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1905 16:31:08.171927 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1906 16:31:08.171979 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1907 16:31:08.172031 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1908 16:31:08.172083 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1909 16:31:08.172135 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1910 16:31:08.172187 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1911 16:31:08.172239 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1912 16:31:08.172290 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1913 16:31:08.172341 ==
1914 16:31:08.172393 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 16:31:08.172445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 16:31:08.172498 ==
1917 16:31:08.172556 DQS Delay:
1918 16:31:08.172611 DQS0 = 0, DQS1 = 0
1919 16:31:08.172663 DQM Delay:
1920 16:31:08.435151 DQM0 = 89, DQM1 = 80
1921 16:31:08.435292 DQ Delay:
1922 16:31:08.435359 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1923 16:31:08.435443 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1924 16:31:08.435504 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1925 16:31:08.435562 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1926 16:31:08.435618
1927 16:31:08.435673
1928 16:31:08.435727 ==
1929 16:31:08.435781 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 16:31:08.435835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 16:31:08.435889 ==
1932 16:31:08.435942
1933 16:31:08.435995
1934 16:31:08.436049 TX Vref Scan disable
1935 16:31:08.436103 == TX Byte 0 ==
1936 16:31:08.436155 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1937 16:31:08.436416 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1938 16:31:08.436479 == TX Byte 1 ==
1939 16:31:08.436534 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1940 16:31:08.436608 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1941 16:31:08.436663 ==
1942 16:31:08.436716 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 16:31:08.436769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 16:31:08.436822 ==
1945 16:31:08.436875 TX Vref=22, minBit 12, minWin=27, winSum=451
1946 16:31:08.436929 TX Vref=24, minBit 13, minWin=27, winSum=454
1947 16:31:08.436982 TX Vref=26, minBit 13, minWin=27, winSum=460
1948 16:31:08.437034 TX Vref=28, minBit 15, minWin=27, winSum=458
1949 16:31:08.437087 TX Vref=30, minBit 15, minWin=27, winSum=461
1950 16:31:08.437139 TX Vref=32, minBit 15, minWin=27, winSum=458
1951 16:31:08.437192 [TxChooseVref] Worse bit 15, Min win 27, Win sum 461, Final Vref 30
1952 16:31:08.437245
1953 16:31:08.437297 Final TX Range 1 Vref 30
1954 16:31:08.437350
1955 16:31:08.437401 ==
1956 16:31:08.437453 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 16:31:08.437505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 16:31:08.437557 ==
1959 16:31:08.437610
1960 16:31:08.437662
1961 16:31:08.437713 TX Vref Scan disable
1962 16:31:08.437765 == TX Byte 0 ==
1963 16:31:08.437818 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1964 16:31:08.437870 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1965 16:31:08.437922 == TX Byte 1 ==
1966 16:31:08.437974 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1967 16:31:08.438029 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1968 16:31:08.438097
1969 16:31:08.438151 [DATLAT]
1970 16:31:08.438203 Freq=800, CH1 RK1
1971 16:31:08.438256
1972 16:31:08.438308 DATLAT Default: 0xa
1973 16:31:08.438360 0, 0xFFFF, sum = 0
1974 16:31:08.438413 1, 0xFFFF, sum = 0
1975 16:31:08.438466 2, 0xFFFF, sum = 0
1976 16:31:08.438519 3, 0xFFFF, sum = 0
1977 16:31:08.438572 4, 0xFFFF, sum = 0
1978 16:31:08.438647 5, 0xFFFF, sum = 0
1979 16:31:08.438702 6, 0xFFFF, sum = 0
1980 16:31:08.438756 7, 0xFFFF, sum = 0
1981 16:31:08.438817 8, 0xFFFF, sum = 0
1982 16:31:08.438891 9, 0x0, sum = 1
1983 16:31:08.438946 10, 0x0, sum = 2
1984 16:31:08.439000 11, 0x0, sum = 3
1985 16:31:08.439053 12, 0x0, sum = 4
1986 16:31:08.439106 best_step = 10
1987 16:31:08.439158
1988 16:31:08.439209 ==
1989 16:31:08.439261 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 16:31:08.439314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 16:31:08.439367 ==
1992 16:31:08.439419 RX Vref Scan: 0
1993 16:31:08.439472
1994 16:31:08.439524 RX Vref 0 -> 0, step: 1
1995 16:31:08.439576
1996 16:31:08.439628 RX Delay -95 -> 252, step: 8
1997 16:31:08.439680 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
1998 16:31:08.439733 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
1999 16:31:08.439786 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2000 16:31:08.439838 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2001 16:31:08.439890 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2002 16:31:08.439942 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2003 16:31:08.439995 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2004 16:31:08.440047 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2005 16:31:08.440099 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2006 16:31:08.440151 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2007 16:31:08.440202 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2008 16:31:08.440254 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2009 16:31:08.440306 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2010 16:31:08.440358 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2011 16:31:08.440409 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2012 16:31:08.440461 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2013 16:31:08.440513 ==
2014 16:31:08.440581 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 16:31:08.440636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 16:31:08.440691 ==
2017 16:31:08.440744 DQS Delay:
2018 16:31:08.440797 DQS0 = 0, DQS1 = 0
2019 16:31:08.440849 DQM Delay:
2020 16:31:08.440902 DQM0 = 90, DQM1 = 82
2021 16:31:08.440954 DQ Delay:
2022 16:31:08.441008 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2023 16:31:08.441061 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2024 16:31:08.441114 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2025 16:31:08.441167 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2026 16:31:08.441220
2027 16:31:08.441272
2028 16:31:08.441325 [DQSOSCAuto] RK1, (LSB)MR18= 0x380e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2029 16:31:08.441380 CH1 RK1: MR19=606, MR18=380E
2030 16:31:08.441434 CH1_RK1: MR19=0x606, MR18=0x380E, DQSOSC=395, MR23=63, INC=94, DEC=63
2031 16:31:08.441488 [RxdqsGatingPostProcess] freq 800
2032 16:31:08.441542 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2033 16:31:08.441596 Pre-setting of DQS Precalculation
2034 16:31:08.441649 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2035 16:31:08.441703 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2036 16:31:08.441757 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2037 16:31:08.441811
2038 16:31:08.441864
2039 16:31:08.441917 [Calibration Summary] 1600 Mbps
2040 16:31:08.441970 CH 0, Rank 0
2041 16:31:08.442023 SW Impedance : PASS
2042 16:31:08.442077 DUTY Scan : NO K
2043 16:31:08.442131 ZQ Calibration : PASS
2044 16:31:08.442184 Jitter Meter : NO K
2045 16:31:08.442237 CBT Training : PASS
2046 16:31:08.442290 Write leveling : PASS
2047 16:31:08.442354 RX DQS gating : PASS
2048 16:31:08.442415 RX DQ/DQS(RDDQC) : PASS
2049 16:31:08.442469 TX DQ/DQS : PASS
2050 16:31:08.442524 RX DATLAT : PASS
2051 16:31:08.442578 RX DQ/DQS(Engine): PASS
2052 16:31:08.442631 TX OE : NO K
2053 16:31:08.442686 All Pass.
2054 16:31:08.442740
2055 16:31:08.442792 CH 0, Rank 1
2056 16:31:08.442846 SW Impedance : PASS
2057 16:31:08.442899 DUTY Scan : NO K
2058 16:31:08.442953 ZQ Calibration : PASS
2059 16:31:08.443008 Jitter Meter : NO K
2060 16:31:08.443061 CBT Training : PASS
2061 16:31:08.443114 Write leveling : PASS
2062 16:31:08.443168 RX DQS gating : PASS
2063 16:31:08.443222 RX DQ/DQS(RDDQC) : PASS
2064 16:31:08.443275 TX DQ/DQS : PASS
2065 16:31:08.443329 RX DATLAT : PASS
2066 16:31:08.443382 RX DQ/DQS(Engine): PASS
2067 16:31:08.443435 TX OE : NO K
2068 16:31:08.443489 All Pass.
2069 16:31:08.443542
2070 16:31:08.443594 CH 1, Rank 0
2071 16:31:08.443647 SW Impedance : PASS
2072 16:31:08.443729 DUTY Scan : NO K
2073 16:31:08.443788 ZQ Calibration : PASS
2074 16:31:08.443842 Jitter Meter : NO K
2075 16:31:08.443895 CBT Training : PASS
2076 16:31:08.443948 Write leveling : PASS
2077 16:31:08.444002 RX DQS gating : PASS
2078 16:31:08.444055 RX DQ/DQS(RDDQC) : PASS
2079 16:31:08.444109 TX DQ/DQS : PASS
2080 16:31:08.444163 RX DATLAT : PASS
2081 16:31:08.444216 RX DQ/DQS(Engine): PASS
2082 16:31:08.444270 TX OE : NO K
2083 16:31:08.444520 All Pass.
2084 16:31:08.444594
2085 16:31:08.444651 CH 1, Rank 1
2086 16:31:08.444705 SW Impedance : PASS
2087 16:31:08.444764 DUTY Scan : NO K
2088 16:31:08.444819 ZQ Calibration : PASS
2089 16:31:08.444873 Jitter Meter : NO K
2090 16:31:08.444927 CBT Training : PASS
2091 16:31:08.444980 Write leveling : PASS
2092 16:31:08.445034 RX DQS gating : PASS
2093 16:31:08.445089 RX DQ/DQS(RDDQC) : PASS
2094 16:31:08.445142 TX DQ/DQS : PASS
2095 16:31:08.445195 RX DATLAT : PASS
2096 16:31:08.445249 RX DQ/DQS(Engine): PASS
2097 16:31:08.445302 TX OE : NO K
2098 16:31:08.445356 All Pass.
2099 16:31:08.445409
2100 16:31:08.445463 DramC Write-DBI off
2101 16:31:08.445516 PER_BANK_REFRESH: Hybrid Mode
2102 16:31:08.445590 TX_TRACKING: ON
2103 16:31:08.445645 [GetDramInforAfterCalByMRR] Vendor 6.
2104 16:31:08.445699 [GetDramInforAfterCalByMRR] Revision 606.
2105 16:31:08.445753 [GetDramInforAfterCalByMRR] Revision 2 0.
2106 16:31:08.445807 MR0 0x3b3b
2107 16:31:08.445860 MR8 0x5151
2108 16:31:08.445914 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 16:31:08.445968
2110 16:31:08.446021 MR0 0x3b3b
2111 16:31:08.446074 MR8 0x5151
2112 16:31:08.446128 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 16:31:08.446183
2114 16:31:08.446236 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2115 16:31:08.446291 [FAST_K] Save calibration result to emmc
2116 16:31:08.446345 [FAST_K] Save calibration result to emmc
2117 16:31:08.446399 dram_init: config_dvfs: 1
2118 16:31:08.446452 dramc_set_vcore_voltage set vcore to 662500
2119 16:31:08.446506 Read voltage for 1200, 2
2120 16:31:08.446559 Vio18 = 0
2121 16:31:08.446612 Vcore = 662500
2122 16:31:08.446666 Vdram = 0
2123 16:31:08.446720 Vddq = 0
2124 16:31:08.446773 Vmddr = 0
2125 16:31:08.446826 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2126 16:31:08.446879 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2127 16:31:08.446934 MEM_TYPE=3, freq_sel=15
2128 16:31:08.446987 sv_algorithm_assistance_LP4_1600
2129 16:31:08.447041 ============ PULL DRAM RESETB DOWN ============
2130 16:31:08.447096 ========== PULL DRAM RESETB DOWN end =========
2131 16:31:08.447150 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 16:31:08.447204 ===================================
2133 16:31:08.447258 LPDDR4 DRAM CONFIGURATION
2134 16:31:08.447311 ===================================
2135 16:31:08.447365 EX_ROW_EN[0] = 0x0
2136 16:31:08.447418 EX_ROW_EN[1] = 0x0
2137 16:31:08.447471 LP4Y_EN = 0x0
2138 16:31:08.447525 WORK_FSP = 0x0
2139 16:31:08.447578 WL = 0x4
2140 16:31:08.447631 RL = 0x4
2141 16:31:08.447684 BL = 0x2
2142 16:31:08.447738 RPST = 0x0
2143 16:31:08.447791 RD_PRE = 0x0
2144 16:31:08.447844 WR_PRE = 0x1
2145 16:31:08.447897 WR_PST = 0x0
2146 16:31:08.447950 DBI_WR = 0x0
2147 16:31:08.448003 DBI_RD = 0x0
2148 16:31:08.448056 OTF = 0x1
2149 16:31:08.448110 ===================================
2150 16:31:08.448164 ===================================
2151 16:31:08.448218 ANA top config
2152 16:31:08.448271 ===================================
2153 16:31:08.448324 DLL_ASYNC_EN = 0
2154 16:31:08.448377 ALL_SLAVE_EN = 0
2155 16:31:08.448430 NEW_RANK_MODE = 1
2156 16:31:08.448484 DLL_IDLE_MODE = 1
2157 16:31:08.448537 LP45_APHY_COMB_EN = 1
2158 16:31:08.448602 TX_ODT_DIS = 1
2159 16:31:08.448656 NEW_8X_MODE = 1
2160 16:31:08.448710 ===================================
2161 16:31:08.448764 ===================================
2162 16:31:08.448837 data_rate = 2400
2163 16:31:08.448892 CKR = 1
2164 16:31:08.448947 DQ_P2S_RATIO = 8
2165 16:31:08.449000 ===================================
2166 16:31:08.449057 CA_P2S_RATIO = 8
2167 16:31:08.449135 DQ_CA_OPEN = 0
2168 16:31:08.449191 DQ_SEMI_OPEN = 0
2169 16:31:08.449245 CA_SEMI_OPEN = 0
2170 16:31:08.449299 CA_FULL_RATE = 0
2171 16:31:08.449353 DQ_CKDIV4_EN = 0
2172 16:31:08.449407 CA_CKDIV4_EN = 0
2173 16:31:08.449461 CA_PREDIV_EN = 0
2174 16:31:08.449514 PH8_DLY = 17
2175 16:31:08.449568 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2176 16:31:08.449622 DQ_AAMCK_DIV = 4
2177 16:31:08.449675 CA_AAMCK_DIV = 4
2178 16:31:08.449728 CA_ADMCK_DIV = 4
2179 16:31:08.449782 DQ_TRACK_CA_EN = 0
2180 16:31:08.449835 CA_PICK = 1200
2181 16:31:08.449889 CA_MCKIO = 1200
2182 16:31:08.449944 MCKIO_SEMI = 0
2183 16:31:08.449998 PLL_FREQ = 2366
2184 16:31:08.450051 DQ_UI_PI_RATIO = 32
2185 16:31:08.450104 CA_UI_PI_RATIO = 0
2186 16:31:08.450157 ===================================
2187 16:31:08.450211 ===================================
2188 16:31:08.450265 memory_type:LPDDR4
2189 16:31:08.450318 GP_NUM : 10
2190 16:31:08.450372 SRAM_EN : 1
2191 16:31:08.450425 MD32_EN : 0
2192 16:31:08.450478 ===================================
2193 16:31:08.450532 [ANA_INIT] >>>>>>>>>>>>>>
2194 16:31:08.450586 <<<<<< [CONFIGURE PHASE]: ANA_TX
2195 16:31:08.450640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2196 16:31:08.450693 ===================================
2197 16:31:08.450747 data_rate = 2400,PCW = 0X5b00
2198 16:31:08.450800 ===================================
2199 16:31:08.450854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2200 16:31:08.450907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 16:31:08.450962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 16:31:08.451016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2203 16:31:08.451070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2204 16:31:08.451123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2205 16:31:08.451177 [ANA_INIT] flow start
2206 16:31:08.451231 [ANA_INIT] PLL >>>>>>>>
2207 16:31:08.451284 [ANA_INIT] PLL <<<<<<<<
2208 16:31:08.451337 [ANA_INIT] MIDPI >>>>>>>>
2209 16:31:08.451391 [ANA_INIT] MIDPI <<<<<<<<
2210 16:31:08.451444 [ANA_INIT] DLL >>>>>>>>
2211 16:31:08.451497 [ANA_INIT] DLL <<<<<<<<
2212 16:31:08.451550 [ANA_INIT] flow end
2213 16:31:08.451603 ============ LP4 DIFF to SE enter ============
2214 16:31:08.451657 ============ LP4 DIFF to SE exit ============
2215 16:31:08.451711 [ANA_INIT] <<<<<<<<<<<<<
2216 16:31:08.451765 [Flow] Enable top DCM control >>>>>
2217 16:31:08.451818 [Flow] Enable top DCM control <<<<<
2218 16:31:08.452084 Enable DLL master slave shuffle
2219 16:31:08.452148 ==============================================================
2220 16:31:08.452204 Gating Mode config
2221 16:31:08.452259 ==============================================================
2222 16:31:08.452314 Config description:
2223 16:31:08.452368 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2224 16:31:08.452424 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2225 16:31:08.452479 SELPH_MODE 0: By rank 1: By Phase
2226 16:31:08.452533 ==============================================================
2227 16:31:08.452600 GAT_TRACK_EN = 1
2228 16:31:08.452655 RX_GATING_MODE = 2
2229 16:31:08.452709 RX_GATING_TRACK_MODE = 2
2230 16:31:08.452763 SELPH_MODE = 1
2231 16:31:08.452817 PICG_EARLY_EN = 1
2232 16:31:08.452871 VALID_LAT_VALUE = 1
2233 16:31:08.452924 ==============================================================
2234 16:31:08.452978 Enter into Gating configuration >>>>
2235 16:31:08.453032 Exit from Gating configuration <<<<
2236 16:31:08.453085 Enter into DVFS_PRE_config >>>>>
2237 16:31:08.453139 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2238 16:31:08.453195 Exit from DVFS_PRE_config <<<<<
2239 16:31:08.453249 Enter into PICG configuration >>>>
2240 16:31:08.453302 Exit from PICG configuration <<<<
2241 16:31:08.453356 [RX_INPUT] configuration >>>>>
2242 16:31:08.453409 [RX_INPUT] configuration <<<<<
2243 16:31:08.453466 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2244 16:31:08.453545 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2245 16:31:08.453601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 16:31:08.453655 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 16:31:08.453709 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 16:31:08.453763 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 16:31:08.453818 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2250 16:31:08.453871 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2251 16:31:08.453925 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2252 16:31:08.453979 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2253 16:31:08.454033 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2254 16:31:08.454087 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2255 16:31:08.454141 ===================================
2256 16:31:08.454194 LPDDR4 DRAM CONFIGURATION
2257 16:31:08.454248 ===================================
2258 16:31:08.454302 EX_ROW_EN[0] = 0x0
2259 16:31:08.454355 EX_ROW_EN[1] = 0x0
2260 16:31:08.454409 LP4Y_EN = 0x0
2261 16:31:08.454462 WORK_FSP = 0x0
2262 16:31:08.454515 WL = 0x4
2263 16:31:08.454569 RL = 0x4
2264 16:31:08.454622 BL = 0x2
2265 16:31:08.454675 RPST = 0x0
2266 16:31:08.454728 RD_PRE = 0x0
2267 16:31:08.454781 WR_PRE = 0x1
2268 16:31:08.454834 WR_PST = 0x0
2269 16:31:08.454887 DBI_WR = 0x0
2270 16:31:08.454939 DBI_RD = 0x0
2271 16:31:08.454992 OTF = 0x1
2272 16:31:08.455046 ===================================
2273 16:31:08.455100 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2274 16:31:08.455154 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2275 16:31:08.455214 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2276 16:31:08.455277 ===================================
2277 16:31:08.455332 LPDDR4 DRAM CONFIGURATION
2278 16:31:08.455386 ===================================
2279 16:31:08.455440 EX_ROW_EN[0] = 0x10
2280 16:31:08.455493 EX_ROW_EN[1] = 0x0
2281 16:31:08.455546 LP4Y_EN = 0x0
2282 16:31:08.455599 WORK_FSP = 0x0
2283 16:31:08.455653 WL = 0x4
2284 16:31:08.455706 RL = 0x4
2285 16:31:08.455760 BL = 0x2
2286 16:31:08.455813 RPST = 0x0
2287 16:31:08.455866 RD_PRE = 0x0
2288 16:31:08.455920 WR_PRE = 0x1
2289 16:31:08.455974 WR_PST = 0x0
2290 16:31:08.456027 DBI_WR = 0x0
2291 16:31:08.456081 DBI_RD = 0x0
2292 16:31:08.456134 OTF = 0x1
2293 16:31:08.456188 ===================================
2294 16:31:08.456242 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2295 16:31:08.456294 ==
2296 16:31:08.456346 Dram Type= 6, Freq= 0, CH_0, rank 0
2297 16:31:08.456398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2298 16:31:08.456451 ==
2299 16:31:08.456503 [Duty_Offset_Calibration]
2300 16:31:08.456591 B0:2 B1:0 CA:1
2301 16:31:08.456644
2302 16:31:08.456696 [DutyScan_Calibration_Flow] k_type=0
2303 16:31:08.456748
2304 16:31:08.456799 ==CLK 0==
2305 16:31:08.456852 Final CLK duty delay cell = -4
2306 16:31:08.456904 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2307 16:31:08.456956 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2308 16:31:08.457008 [-4] AVG Duty = 4953%(X100)
2309 16:31:08.457061
2310 16:31:08.457112 CH0 CLK Duty spec in!! Max-Min= 156%
2311 16:31:08.457165 [DutyScan_Calibration_Flow] ====Done====
2312 16:31:08.457217
2313 16:31:08.457269 [DutyScan_Calibration_Flow] k_type=1
2314 16:31:08.457321
2315 16:31:08.457372 ==DQS 0 ==
2316 16:31:08.457424 Final DQS duty delay cell = 0
2317 16:31:08.457476 [0] MAX Duty = 5187%(X100), DQS PI = 30
2318 16:31:08.457528 [0] MIN Duty = 4938%(X100), DQS PI = 0
2319 16:31:08.457581 [0] AVG Duty = 5062%(X100)
2320 16:31:08.457632
2321 16:31:08.457683 ==DQS 1 ==
2322 16:31:08.457759 Final DQS duty delay cell = -4
2323 16:31:08.457817 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2324 16:31:08.457870 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2325 16:31:08.457922 [-4] AVG Duty = 5031%(X100)
2326 16:31:08.457974
2327 16:31:08.458025 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2328 16:31:08.458078
2329 16:31:08.458130 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2330 16:31:08.458182 [DutyScan_Calibration_Flow] ====Done====
2331 16:31:08.458234
2332 16:31:08.458285 [DutyScan_Calibration_Flow] k_type=3
2333 16:31:08.458337
2334 16:31:08.458401 ==DQM 0 ==
2335 16:31:08.458458 Final DQM duty delay cell = 0
2336 16:31:08.458512 [0] MAX Duty = 5062%(X100), DQS PI = 24
2337 16:31:08.458565 [0] MIN Duty = 4813%(X100), DQS PI = 0
2338 16:31:08.458617 [0] AVG Duty = 4937%(X100)
2339 16:31:08.458669
2340 16:31:08.458720 ==DQM 1 ==
2341 16:31:08.458772 Final DQM duty delay cell = 0
2342 16:31:08.459023 [0] MAX Duty = 5187%(X100), DQS PI = 48
2343 16:31:08.459083 [0] MIN Duty = 5000%(X100), DQS PI = 12
2344 16:31:08.459136 [0] AVG Duty = 5093%(X100)
2345 16:31:08.459189
2346 16:31:08.459240 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2347 16:31:08.459292
2348 16:31:08.459344 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2349 16:31:08.459396 [DutyScan_Calibration_Flow] ====Done====
2350 16:31:08.459448
2351 16:31:08.459500 [DutyScan_Calibration_Flow] k_type=2
2352 16:31:08.459552
2353 16:31:08.459604 ==DQ 0 ==
2354 16:31:08.459656 Final DQ duty delay cell = 0
2355 16:31:08.459708 [0] MAX Duty = 5156%(X100), DQS PI = 34
2356 16:31:08.459760 [0] MIN Duty = 5000%(X100), DQS PI = 0
2357 16:31:08.459812 [0] AVG Duty = 5078%(X100)
2358 16:31:08.459864
2359 16:31:08.459915 ==DQ 1 ==
2360 16:31:08.459967 Final DQ duty delay cell = 4
2361 16:31:08.460019 [4] MAX Duty = 5093%(X100), DQS PI = 6
2362 16:31:08.460071 [4] MIN Duty = 5031%(X100), DQS PI = 0
2363 16:31:08.460124 [4] AVG Duty = 5062%(X100)
2364 16:31:08.460175
2365 16:31:08.460227 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2366 16:31:08.460279
2367 16:31:08.460330 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2368 16:31:08.460382 [DutyScan_Calibration_Flow] ====Done====
2369 16:31:08.460433 ==
2370 16:31:08.460485 Dram Type= 6, Freq= 0, CH_1, rank 0
2371 16:31:08.460537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 16:31:08.460602 ==
2373 16:31:08.460655 [Duty_Offset_Calibration]
2374 16:31:08.460707 B0:0 B1:-1 CA:2
2375 16:31:08.460759
2376 16:31:08.460810 [DutyScan_Calibration_Flow] k_type=0
2377 16:31:08.460862
2378 16:31:08.460914 ==CLK 0==
2379 16:31:08.460967 Final CLK duty delay cell = 0
2380 16:31:08.461020 [0] MAX Duty = 5156%(X100), DQS PI = 16
2381 16:31:08.461072 [0] MIN Duty = 4938%(X100), DQS PI = 44
2382 16:31:08.461124 [0] AVG Duty = 5047%(X100)
2383 16:31:08.461176
2384 16:31:08.461227 CH1 CLK Duty spec in!! Max-Min= 218%
2385 16:31:08.461279 [DutyScan_Calibration_Flow] ====Done====
2386 16:31:08.461330
2387 16:31:08.461381 [DutyScan_Calibration_Flow] k_type=1
2388 16:31:08.461433
2389 16:31:08.461485 ==DQS 0 ==
2390 16:31:08.461536 Final DQS duty delay cell = 0
2391 16:31:08.461588 [0] MAX Duty = 5093%(X100), DQS PI = 26
2392 16:31:08.461640 [0] MIN Duty = 4969%(X100), DQS PI = 0
2393 16:31:08.461692 [0] AVG Duty = 5031%(X100)
2394 16:31:08.461743
2395 16:31:08.461795 ==DQS 1 ==
2396 16:31:08.461846 Final DQS duty delay cell = 0
2397 16:31:08.461898 [0] MAX Duty = 5156%(X100), DQS PI = 0
2398 16:31:08.461949 [0] MIN Duty = 4844%(X100), DQS PI = 36
2399 16:31:08.462001 [0] AVG Duty = 5000%(X100)
2400 16:31:08.462062
2401 16:31:08.462150 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2402 16:31:08.462232
2403 16:31:08.462315 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2404 16:31:08.462403 [DutyScan_Calibration_Flow] ====Done====
2405 16:31:08.462492
2406 16:31:08.462549 [DutyScan_Calibration_Flow] k_type=3
2407 16:31:08.462602
2408 16:31:08.462679 ==DQM 0 ==
2409 16:31:08.462737 Final DQM duty delay cell = 4
2410 16:31:08.462791 [4] MAX Duty = 5093%(X100), DQS PI = 22
2411 16:31:08.462844 [4] MIN Duty = 4938%(X100), DQS PI = 30
2412 16:31:08.462897 [4] AVG Duty = 5015%(X100)
2413 16:31:08.462949
2414 16:31:08.463001 ==DQM 1 ==
2415 16:31:08.463053 Final DQM duty delay cell = -4
2416 16:31:08.463105 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2417 16:31:08.463158 [-4] MIN Duty = 4720%(X100), DQS PI = 36
2418 16:31:08.463210 [-4] AVG Duty = 4860%(X100)
2419 16:31:08.463275
2420 16:31:08.463363 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2421 16:31:08.463439
2422 16:31:08.463509 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2423 16:31:08.463581 [DutyScan_Calibration_Flow] ====Done====
2424 16:31:08.463635
2425 16:31:08.463687 [DutyScan_Calibration_Flow] k_type=2
2426 16:31:08.463739
2427 16:31:08.463791 ==DQ 0 ==
2428 16:31:08.463843 Final DQ duty delay cell = 0
2429 16:31:08.463896 [0] MAX Duty = 5062%(X100), DQS PI = 20
2430 16:31:08.463949 [0] MIN Duty = 4938%(X100), DQS PI = 30
2431 16:31:08.464001 [0] AVG Duty = 5000%(X100)
2432 16:31:08.464053
2433 16:31:08.464105 ==DQ 1 ==
2434 16:31:08.464157 Final DQ duty delay cell = 0
2435 16:31:08.464209 [0] MAX Duty = 5000%(X100), DQS PI = 0
2436 16:31:08.464262 [0] MIN Duty = 4813%(X100), DQS PI = 34
2437 16:31:08.464314 [0] AVG Duty = 4906%(X100)
2438 16:31:08.464366
2439 16:31:08.464418 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2440 16:31:08.464471
2441 16:31:08.464522 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2442 16:31:08.464587 [DutyScan_Calibration_Flow] ====Done====
2443 16:31:08.464640 nWR fixed to 30
2444 16:31:08.464698 [ModeRegInit_LP4] CH0 RK0
2445 16:31:08.464750 [ModeRegInit_LP4] CH0 RK1
2446 16:31:08.464802 [ModeRegInit_LP4] CH1 RK0
2447 16:31:08.464853 [ModeRegInit_LP4] CH1 RK1
2448 16:31:08.464905 match AC timing 7
2449 16:31:08.464958 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2450 16:31:08.465010 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2451 16:31:08.465062 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2452 16:31:08.465114 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2453 16:31:08.465166 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2454 16:31:08.465218 ==
2455 16:31:08.465271 Dram Type= 6, Freq= 0, CH_0, rank 0
2456 16:31:08.465323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2457 16:31:08.465376 ==
2458 16:31:08.465428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2459 16:31:08.465481 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2460 16:31:08.465534 [CA 0] Center 38 (7~69) winsize 63
2461 16:31:08.465587 [CA 1] Center 38 (8~69) winsize 62
2462 16:31:08.465655 [CA 2] Center 35 (5~66) winsize 62
2463 16:31:08.465712 [CA 3] Center 35 (4~66) winsize 63
2464 16:31:08.465763 [CA 4] Center 34 (4~65) winsize 62
2465 16:31:08.465815 [CA 5] Center 33 (3~63) winsize 61
2466 16:31:08.465867
2467 16:31:08.465919 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2468 16:31:08.465971
2469 16:31:08.466023 [CATrainingPosCal] consider 1 rank data
2470 16:31:08.466075 u2DelayCellTimex100 = 270/100 ps
2471 16:31:08.466127 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2472 16:31:08.466180 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2473 16:31:08.466231 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2474 16:31:08.466283 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2475 16:31:08.466336 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2476 16:31:08.466387 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2477 16:31:08.466439
2478 16:31:08.466491 CA PerBit enable=1, Macro0, CA PI delay=33
2479 16:31:08.466543
2480 16:31:08.466595 [CBTSetCACLKResult] CA Dly = 33
2481 16:31:08.466646 CS Dly: 6 (0~37)
2482 16:31:08.466699 ==
2483 16:31:08.466751 Dram Type= 6, Freq= 0, CH_0, rank 1
2484 16:31:08.466803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 16:31:08.466855 ==
2486 16:31:08.466907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 16:31:08.466960 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2488 16:31:08.467211 [CA 0] Center 39 (8~70) winsize 63
2489 16:31:08.467294 [CA 1] Center 38 (8~69) winsize 62
2490 16:31:08.467351 [CA 2] Center 35 (5~66) winsize 62
2491 16:31:08.467404 [CA 3] Center 35 (5~66) winsize 62
2492 16:31:08.467457 [CA 4] Center 34 (4~65) winsize 62
2493 16:31:08.467510 [CA 5] Center 34 (4~64) winsize 61
2494 16:31:08.467562
2495 16:31:08.467614 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2496 16:31:08.467666
2497 16:31:08.467718 [CATrainingPosCal] consider 2 rank data
2498 16:31:08.467771 u2DelayCellTimex100 = 270/100 ps
2499 16:31:08.467823 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2500 16:31:08.467875 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2501 16:31:08.467928 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 16:31:08.467980 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 16:31:08.468033 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2504 16:31:08.468085 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2505 16:31:08.468136
2506 16:31:08.468186 CA PerBit enable=1, Macro0, CA PI delay=33
2507 16:31:08.468238
2508 16:31:08.468290 [CBTSetCACLKResult] CA Dly = 33
2509 16:31:08.468342 CS Dly: 7 (0~39)
2510 16:31:08.468428
2511 16:31:08.468511 ----->DramcWriteLeveling(PI) begin...
2512 16:31:08.468592 ==
2513 16:31:08.468647 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 16:31:08.468709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 16:31:08.468764 ==
2516 16:31:08.468816 Write leveling (Byte 0): 35 => 35
2517 16:31:08.468869 Write leveling (Byte 1): 33 => 33
2518 16:31:08.468922 DramcWriteLeveling(PI) end<-----
2519 16:31:08.468997
2520 16:31:08.469054 ==
2521 16:31:08.469106 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 16:31:08.469159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 16:31:08.469212 ==
2524 16:31:08.469264 [Gating] SW mode calibration
2525 16:31:08.469316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2526 16:31:08.469369 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2527 16:31:08.469421 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2528 16:31:08.469474 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2529 16:31:08.469527 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 16:31:08.469579 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 16:31:08.469632 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 16:31:08.469684 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 16:31:08.469737 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2534 16:31:08.469789 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2535 16:31:08.469874 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
2536 16:31:08.469929 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 16:31:08.469982 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 16:31:08.470035 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 16:31:08.470088 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 16:31:08.470141 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 16:31:08.470193 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2542 16:31:08.470246 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2543 16:31:08.470298 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2544 16:31:08.470350 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 16:31:08.470402 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 16:31:08.470455 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 16:31:08.470506 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 16:31:08.470559 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 16:31:08.470611 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 16:31:08.470663 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2551 16:31:08.470715 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2552 16:31:08.470767 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2553 16:31:08.470820 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 16:31:08.470872 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 16:31:08.470924 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 16:31:08.470976 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 16:31:08.471028 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 16:31:08.471080 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 16:31:08.471131 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 16:31:08.471183 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 16:31:08.471235 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 16:31:08.471287 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 16:31:08.471339 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 16:31:08.471391 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 16:31:08.471442 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2566 16:31:08.471494 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2567 16:31:08.471546 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2568 16:31:08.471597 Total UI for P1: 0, mck2ui 16
2569 16:31:08.471650 best dqsien dly found for B0: ( 1, 3, 26)
2570 16:31:08.471702 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 16:31:08.471754 Total UI for P1: 0, mck2ui 16
2572 16:31:08.471846 best dqsien dly found for B1: ( 1, 3, 30)
2573 16:31:08.471905 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2574 16:31:08.471958 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2575 16:31:08.472011
2576 16:31:08.472063 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2577 16:31:08.472117 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2578 16:31:08.472190 [Gating] SW calibration Done
2579 16:31:08.472244 ==
2580 16:31:08.472297 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 16:31:08.472356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 16:31:08.472409 ==
2583 16:31:08.472462 RX Vref Scan: 0
2584 16:31:08.472514
2585 16:31:08.472595 RX Vref 0 -> 0, step: 1
2586 16:31:08.472656
2587 16:31:08.472708 RX Delay -40 -> 252, step: 8
2588 16:31:08.472761 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2589 16:31:08.472814 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2590 16:31:08.472866 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2591 16:31:08.472919 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2592 16:31:08.472972 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2593 16:31:08.473229 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2594 16:31:08.473290 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2595 16:31:08.473343 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2596 16:31:08.473397 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2597 16:31:08.473449 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2598 16:31:08.473502 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2599 16:31:08.473556 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2600 16:31:08.473608 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2601 16:31:08.473660 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2602 16:31:08.473712 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2603 16:31:08.473765 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2604 16:31:08.473816 ==
2605 16:31:08.473868 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 16:31:08.473921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 16:31:08.473973 ==
2608 16:31:08.474025 DQS Delay:
2609 16:31:08.474077 DQS0 = 0, DQS1 = 0
2610 16:31:08.474129 DQM Delay:
2611 16:31:08.474181 DQM0 = 122, DQM1 = 110
2612 16:31:08.474233 DQ Delay:
2613 16:31:08.474286 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2614 16:31:08.474338 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2615 16:31:08.474390 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2616 16:31:08.474442 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2617 16:31:08.474494
2618 16:31:08.474545
2619 16:31:08.474596 ==
2620 16:31:08.474649 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 16:31:08.474701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 16:31:08.474753 ==
2623 16:31:08.474805
2624 16:31:08.474862
2625 16:31:08.474966 TX Vref Scan disable
2626 16:31:08.475067 == TX Byte 0 ==
2627 16:31:08.475158 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2628 16:31:08.475217 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2629 16:31:08.475273 == TX Byte 1 ==
2630 16:31:08.475357 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2631 16:31:08.475416 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2632 16:31:08.475471 ==
2633 16:31:08.475524 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 16:31:08.475578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 16:31:08.475631 ==
2636 16:31:08.475683 TX Vref=22, minBit 3, minWin=23, winSum=397
2637 16:31:08.475737 TX Vref=24, minBit 6, minWin=24, winSum=409
2638 16:31:08.475789 TX Vref=26, minBit 1, minWin=25, winSum=414
2639 16:31:08.475842 TX Vref=28, minBit 0, minWin=25, winSum=417
2640 16:31:08.475895 TX Vref=30, minBit 4, minWin=25, winSum=413
2641 16:31:08.475948 TX Vref=32, minBit 1, minWin=25, winSum=414
2642 16:31:08.476001 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
2643 16:31:08.476055
2644 16:31:08.476107 Final TX Range 1 Vref 28
2645 16:31:08.476160
2646 16:31:08.476211 ==
2647 16:31:08.476263 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 16:31:08.476316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 16:31:08.476369 ==
2650 16:31:08.476420
2651 16:31:08.476472
2652 16:31:08.476524 TX Vref Scan disable
2653 16:31:08.476592 == TX Byte 0 ==
2654 16:31:08.476666 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2655 16:31:08.476731 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2656 16:31:08.476785 == TX Byte 1 ==
2657 16:31:08.476837 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2658 16:31:08.476890 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2659 16:31:08.476943
2660 16:31:08.476995 [DATLAT]
2661 16:31:08.477047 Freq=1200, CH0 RK0
2662 16:31:08.477099
2663 16:31:08.477151 DATLAT Default: 0xd
2664 16:31:08.477204 0, 0xFFFF, sum = 0
2665 16:31:08.477258 1, 0xFFFF, sum = 0
2666 16:31:08.477311 2, 0xFFFF, sum = 0
2667 16:31:08.477364 3, 0xFFFF, sum = 0
2668 16:31:08.477416 4, 0xFFFF, sum = 0
2669 16:31:08.477469 5, 0xFFFF, sum = 0
2670 16:31:08.477521 6, 0xFFFF, sum = 0
2671 16:31:08.477573 7, 0xFFFF, sum = 0
2672 16:31:08.477626 8, 0xFFFF, sum = 0
2673 16:31:08.477679 9, 0xFFFF, sum = 0
2674 16:31:08.477732 10, 0xFFFF, sum = 0
2675 16:31:08.477785 11, 0xFFFF, sum = 0
2676 16:31:08.477837 12, 0x0, sum = 1
2677 16:31:08.477890 13, 0x0, sum = 2
2678 16:31:08.477942 14, 0x0, sum = 3
2679 16:31:08.477995 15, 0x0, sum = 4
2680 16:31:08.478048 best_step = 13
2681 16:31:08.478100
2682 16:31:08.478151 ==
2683 16:31:08.478203 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 16:31:08.478256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 16:31:08.478309 ==
2686 16:31:08.478361 RX Vref Scan: 1
2687 16:31:08.478419
2688 16:31:08.478481 Set Vref Range= 32 -> 127
2689 16:31:08.478534
2690 16:31:08.478586 RX Vref 32 -> 127, step: 1
2691 16:31:08.478638
2692 16:31:08.478690 RX Delay -13 -> 252, step: 4
2693 16:31:08.478742
2694 16:31:08.478793 Set Vref, RX VrefLevel [Byte0]: 32
2695 16:31:08.478846 [Byte1]: 32
2696 16:31:08.478898
2697 16:31:08.478949 Set Vref, RX VrefLevel [Byte0]: 33
2698 16:31:08.479001 [Byte1]: 33
2699 16:31:08.479054
2700 16:31:08.479106 Set Vref, RX VrefLevel [Byte0]: 34
2701 16:31:08.479158 [Byte1]: 34
2702 16:31:08.479211
2703 16:31:08.479262 Set Vref, RX VrefLevel [Byte0]: 35
2704 16:31:08.479315 [Byte1]: 35
2705 16:31:08.479367
2706 16:31:08.479419 Set Vref, RX VrefLevel [Byte0]: 36
2707 16:31:08.479471 [Byte1]: 36
2708 16:31:08.479542
2709 16:31:08.479601 Set Vref, RX VrefLevel [Byte0]: 37
2710 16:31:08.479655 [Byte1]: 37
2711 16:31:08.479707
2712 16:31:08.479759 Set Vref, RX VrefLevel [Byte0]: 38
2713 16:31:08.479812 [Byte1]: 38
2714 16:31:08.479864
2715 16:31:08.479916 Set Vref, RX VrefLevel [Byte0]: 39
2716 16:31:08.479968 [Byte1]: 39
2717 16:31:08.480020
2718 16:31:08.480071 Set Vref, RX VrefLevel [Byte0]: 40
2719 16:31:08.480123 [Byte1]: 40
2720 16:31:08.480175
2721 16:31:08.480227 Set Vref, RX VrefLevel [Byte0]: 41
2722 16:31:08.480279 [Byte1]: 41
2723 16:31:08.480332
2724 16:31:08.480384 Set Vref, RX VrefLevel [Byte0]: 42
2725 16:31:08.480436 [Byte1]: 42
2726 16:31:08.480488
2727 16:31:08.480540 Set Vref, RX VrefLevel [Byte0]: 43
2728 16:31:08.480605 [Byte1]: 43
2729 16:31:08.480658
2730 16:31:08.480710 Set Vref, RX VrefLevel [Byte0]: 44
2731 16:31:08.480762 [Byte1]: 44
2732 16:31:08.480814
2733 16:31:08.480866 Set Vref, RX VrefLevel [Byte0]: 45
2734 16:31:08.480918 [Byte1]: 45
2735 16:31:08.480969
2736 16:31:08.481020 Set Vref, RX VrefLevel [Byte0]: 46
2737 16:31:08.481072 [Byte1]: 46
2738 16:31:08.481124
2739 16:31:08.481175 Set Vref, RX VrefLevel [Byte0]: 47
2740 16:31:08.481227 [Byte1]: 47
2741 16:31:08.481280
2742 16:31:08.481331 Set Vref, RX VrefLevel [Byte0]: 48
2743 16:31:08.481394 [Byte1]: 48
2744 16:31:08.481487
2745 16:31:08.481581 Set Vref, RX VrefLevel [Byte0]: 49
2746 16:31:08.481679 [Byte1]: 49
2747 16:31:08.481762
2748 16:31:08.481820 Set Vref, RX VrefLevel [Byte0]: 50
2749 16:31:08.481875 [Byte1]: 50
2750 16:31:08.481958
2751 16:31:08.482018 Set Vref, RX VrefLevel [Byte0]: 51
2752 16:31:08.482287 [Byte1]: 51
2753 16:31:08.482355
2754 16:31:08.482412 Set Vref, RX VrefLevel [Byte0]: 52
2755 16:31:08.482467 [Byte1]: 52
2756 16:31:08.482521
2757 16:31:08.482574 Set Vref, RX VrefLevel [Byte0]: 53
2758 16:31:08.482627 [Byte1]: 53
2759 16:31:08.482680
2760 16:31:08.482732 Set Vref, RX VrefLevel [Byte0]: 54
2761 16:31:08.482785 [Byte1]: 54
2762 16:31:08.482837
2763 16:31:08.482890 Set Vref, RX VrefLevel [Byte0]: 55
2764 16:31:08.482944 [Byte1]: 55
2765 16:31:08.482996
2766 16:31:08.483048 Set Vref, RX VrefLevel [Byte0]: 56
2767 16:31:08.483100 [Byte1]: 56
2768 16:31:08.483152
2769 16:31:08.483204 Set Vref, RX VrefLevel [Byte0]: 57
2770 16:31:08.483257 [Byte1]: 57
2771 16:31:08.483308
2772 16:31:08.483360 Set Vref, RX VrefLevel [Byte0]: 58
2773 16:31:08.483412 [Byte1]: 58
2774 16:31:08.483464
2775 16:31:08.483515 Set Vref, RX VrefLevel [Byte0]: 59
2776 16:31:08.483567 [Byte1]: 59
2777 16:31:08.483619
2778 16:31:08.483671 Set Vref, RX VrefLevel [Byte0]: 60
2779 16:31:08.483724 [Byte1]: 60
2780 16:31:08.483775
2781 16:31:08.483827 Set Vref, RX VrefLevel [Byte0]: 61
2782 16:31:08.483879 [Byte1]: 61
2783 16:31:08.483932
2784 16:31:08.484008 Set Vref, RX VrefLevel [Byte0]: 62
2785 16:31:08.484067 [Byte1]: 62
2786 16:31:08.484120
2787 16:31:08.484171 Set Vref, RX VrefLevel [Byte0]: 63
2788 16:31:08.484224 [Byte1]: 63
2789 16:31:08.484277
2790 16:31:08.484328 Set Vref, RX VrefLevel [Byte0]: 64
2791 16:31:08.484380 [Byte1]: 64
2792 16:31:08.484432
2793 16:31:08.484484 Set Vref, RX VrefLevel [Byte0]: 65
2794 16:31:08.484537 [Byte1]: 65
2795 16:31:08.484606
2796 16:31:08.484658 Set Vref, RX VrefLevel [Byte0]: 66
2797 16:31:08.484710 [Byte1]: 66
2798 16:31:08.484762
2799 16:31:08.484814 Set Vref, RX VrefLevel [Byte0]: 67
2800 16:31:08.484866 [Byte1]: 67
2801 16:31:08.484918
2802 16:31:08.484970 Set Vref, RX VrefLevel [Byte0]: 68
2803 16:31:08.485022 [Byte1]: 68
2804 16:31:08.485075
2805 16:31:08.485126 Final RX Vref Byte 0 = 57 to rank0
2806 16:31:08.485187 Final RX Vref Byte 1 = 49 to rank0
2807 16:31:08.485249 Final RX Vref Byte 0 = 57 to rank1
2808 16:31:08.485303 Final RX Vref Byte 1 = 49 to rank1==
2809 16:31:08.485355 Dram Type= 6, Freq= 0, CH_0, rank 0
2810 16:31:08.485407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2811 16:31:08.485460 ==
2812 16:31:08.485512 DQS Delay:
2813 16:31:08.485564 DQS0 = 0, DQS1 = 0
2814 16:31:08.485624 DQM Delay:
2815 16:31:08.485711 DQM0 = 122, DQM1 = 109
2816 16:31:08.485768 DQ Delay:
2817 16:31:08.485821 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2818 16:31:08.485875 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2819 16:31:08.485927 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2820 16:31:08.486004 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2821 16:31:08.486095
2822 16:31:08.486173
2823 16:31:08.486230 [DQSOSCAuto] RK0, (LSB)MR18= 0xc08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2824 16:31:08.486285 CH0 RK0: MR19=404, MR18=C08
2825 16:31:08.486339 CH0_RK0: MR19=0x404, MR18=0xC08, DQSOSC=405, MR23=63, INC=39, DEC=26
2826 16:31:08.486393
2827 16:31:08.486446 ----->DramcWriteLeveling(PI) begin...
2828 16:31:08.486500 ==
2829 16:31:08.486553 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 16:31:08.486606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 16:31:08.486659 ==
2832 16:31:08.486711 Write leveling (Byte 0): 35 => 35
2833 16:31:08.486764 Write leveling (Byte 1): 30 => 30
2834 16:31:08.486817 DramcWriteLeveling(PI) end<-----
2835 16:31:08.486869
2836 16:31:08.486920 ==
2837 16:31:08.486972 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 16:31:08.487024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2839 16:31:08.487077 ==
2840 16:31:08.487129 [Gating] SW mode calibration
2841 16:31:08.487181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2842 16:31:08.487234 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2843 16:31:08.487287 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2844 16:31:08.487340 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 16:31:08.487392 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 16:31:08.487445 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 16:31:08.487497 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 16:31:08.487549 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 16:31:08.487601 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 16:31:08.487653 0 15 28 | B1->B0 | 3131 2c2c | 1 1 | (1 1) (1 0)
2851 16:31:08.487706 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 16:31:08.487799 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 16:31:08.487858 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 16:31:08.487911 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 16:31:08.487964 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 16:31:08.488017 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 16:31:08.488069 1 0 24 | B1->B0 | 2626 2a2a | 0 0 | (0 0) (0 0)
2858 16:31:08.488123 1 0 28 | B1->B0 | 3d3d 4343 | 1 0 | (0 0) (0 0)
2859 16:31:08.488176 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 16:31:08.488230 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 16:31:08.488283 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 16:31:08.488336 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 16:31:08.488389 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 16:31:08.488441 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 16:31:08.488494 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 16:31:08.488587 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2867 16:31:08.488644 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2868 16:31:08.488698 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 16:31:08.488750 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 16:31:08.488804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 16:31:08.488857 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 16:31:08.488909 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 16:31:08.488962 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 16:31:08.489230 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 16:31:08.489295 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 16:31:08.489350 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 16:31:08.489403 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 16:31:08.489456 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 16:31:08.489509 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 16:31:08.489563 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 16:31:08.489615 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 16:31:08.489668 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2883 16:31:08.489720 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 16:31:08.489773 Total UI for P1: 0, mck2ui 16
2885 16:31:08.489826 best dqsien dly found for B0: ( 1, 3, 28)
2886 16:31:08.489877 Total UI for P1: 0, mck2ui 16
2887 16:31:08.489929 best dqsien dly found for B1: ( 1, 3, 28)
2888 16:31:08.489982 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2889 16:31:08.490034 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2890 16:31:08.490086
2891 16:31:08.490138 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2892 16:31:08.490191 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2893 16:31:08.490244 [Gating] SW calibration Done
2894 16:31:08.490296 ==
2895 16:31:08.490348 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 16:31:08.490401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 16:31:08.490454 ==
2898 16:31:08.490506 RX Vref Scan: 0
2899 16:31:08.490595
2900 16:31:08.490669 RX Vref 0 -> 0, step: 1
2901 16:31:08.490724
2902 16:31:08.490776 RX Delay -40 -> 252, step: 8
2903 16:31:08.490829 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2904 16:31:08.490881 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2905 16:31:08.490934 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2906 16:31:08.490985 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2907 16:31:08.491037 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2908 16:31:08.491089 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2909 16:31:08.491142 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2910 16:31:08.491194 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2911 16:31:08.491246 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2912 16:31:08.491299 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2913 16:31:08.491351 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2914 16:31:08.491403 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2915 16:31:08.491455 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2916 16:31:08.491507 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2917 16:31:08.491559 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2918 16:31:08.491611 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2919 16:31:08.491662 ==
2920 16:31:08.491714 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 16:31:08.491781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 16:31:08.491867 ==
2923 16:31:08.491938 DQS Delay:
2924 16:31:08.491992 DQS0 = 0, DQS1 = 0
2925 16:31:08.492077 DQM Delay:
2926 16:31:08.492136 DQM0 = 120, DQM1 = 108
2927 16:31:08.492189 DQ Delay:
2928 16:31:08.492241 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2929 16:31:08.492294 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2930 16:31:08.492346 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2931 16:31:08.492398 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2932 16:31:08.492451
2933 16:31:08.492503
2934 16:31:08.492570 ==
2935 16:31:08.492625 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 16:31:08.626892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 16:31:08.627044 ==
2938 16:31:08.627128
2939 16:31:08.627202
2940 16:31:08.627259 TX Vref Scan disable
2941 16:31:08.627315 == TX Byte 0 ==
2942 16:31:08.627370 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2943 16:31:08.627426 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2944 16:31:08.627479 == TX Byte 1 ==
2945 16:31:08.627532 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2946 16:31:08.627586 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2947 16:31:08.627639 ==
2948 16:31:08.627692 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 16:31:08.627745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 16:31:08.627798 ==
2951 16:31:08.627851 TX Vref=22, minBit 1, minWin=24, winSum=415
2952 16:31:08.627903 TX Vref=24, minBit 0, minWin=25, winSum=420
2953 16:31:08.627955 TX Vref=26, minBit 1, minWin=24, winSum=419
2954 16:31:08.628007 TX Vref=28, minBit 1, minWin=25, winSum=423
2955 16:31:08.628059 TX Vref=30, minBit 5, minWin=25, winSum=425
2956 16:31:08.628111 TX Vref=32, minBit 2, minWin=25, winSum=426
2957 16:31:08.628162 [TxChooseVref] Worse bit 2, Min win 25, Win sum 426, Final Vref 32
2958 16:31:08.628214
2959 16:31:08.628266 Final TX Range 1 Vref 32
2960 16:31:08.628318
2961 16:31:08.628369 ==
2962 16:31:08.628421 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 16:31:08.628474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 16:31:08.628525 ==
2965 16:31:08.628626
2966 16:31:08.628679
2967 16:31:08.628731 TX Vref Scan disable
2968 16:31:08.628783 == TX Byte 0 ==
2969 16:31:08.628835 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2970 16:31:08.628887 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2971 16:31:08.628939 == TX Byte 1 ==
2972 16:31:08.628990 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2973 16:31:08.629042 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2974 16:31:08.629094
2975 16:31:08.629145 [DATLAT]
2976 16:31:08.629196 Freq=1200, CH0 RK1
2977 16:31:08.629247
2978 16:31:08.629298 DATLAT Default: 0xd
2979 16:31:08.629349 0, 0xFFFF, sum = 0
2980 16:31:08.629402 1, 0xFFFF, sum = 0
2981 16:31:08.629460 2, 0xFFFF, sum = 0
2982 16:31:08.629512 3, 0xFFFF, sum = 0
2983 16:31:08.629565 4, 0xFFFF, sum = 0
2984 16:31:08.629617 5, 0xFFFF, sum = 0
2985 16:31:08.629668 6, 0xFFFF, sum = 0
2986 16:31:08.629720 7, 0xFFFF, sum = 0
2987 16:31:08.629771 8, 0xFFFF, sum = 0
2988 16:31:08.629824 9, 0xFFFF, sum = 0
2989 16:31:08.629875 10, 0xFFFF, sum = 0
2990 16:31:08.629927 11, 0xFFFF, sum = 0
2991 16:31:08.629979 12, 0x0, sum = 1
2992 16:31:08.630032 13, 0x0, sum = 2
2993 16:31:08.630083 14, 0x0, sum = 3
2994 16:31:08.630135 15, 0x0, sum = 4
2995 16:31:08.630187 best_step = 13
2996 16:31:08.630238
2997 16:31:08.630288 ==
2998 16:31:08.630340 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 16:31:08.630392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 16:31:08.630444 ==
3001 16:31:08.630495 RX Vref Scan: 0
3002 16:31:08.630547
3003 16:31:08.630597 RX Vref 0 -> 0, step: 1
3004 16:31:08.630649
3005 16:31:08.630699 RX Delay -21 -> 252, step: 4
3006 16:31:08.630750 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3007 16:31:08.630801 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3008 16:31:08.630852 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3009 16:31:08.630903 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3010 16:31:08.630955 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3011 16:31:08.631033 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3012 16:31:08.631304 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3013 16:31:08.631364 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3014 16:31:08.631418 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3015 16:31:08.631471 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3016 16:31:08.631539 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3017 16:31:08.631592 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3018 16:31:08.631645 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3019 16:31:08.631698 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3020 16:31:08.631751 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3021 16:31:08.631817 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3022 16:31:08.631869 ==
3023 16:31:08.631921 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 16:31:08.631973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 16:31:08.632025 ==
3026 16:31:08.632076 DQS Delay:
3027 16:31:08.632127 DQS0 = 0, DQS1 = 0
3028 16:31:08.632192 DQM Delay:
3029 16:31:08.632245 DQM0 = 119, DQM1 = 107
3030 16:31:08.632297 DQ Delay:
3031 16:31:08.632349 DQ0 =116, DQ1 =122, DQ2 =116, DQ3 =114
3032 16:31:08.632400 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3033 16:31:08.632452 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =106
3034 16:31:08.632503 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3035 16:31:08.632608
3036 16:31:08.632663
3037 16:31:08.632716 [DQSOSCAuto] RK1, (LSB)MR18= 0xef5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3038 16:31:08.632770 CH0 RK1: MR19=403, MR18=EF5
3039 16:31:08.632823 CH0_RK1: MR19=0x403, MR18=0xEF5, DQSOSC=404, MR23=63, INC=40, DEC=26
3040 16:31:08.632875 [RxdqsGatingPostProcess] freq 1200
3041 16:31:08.632928 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3042 16:31:08.632980 best DQS0 dly(2T, 0.5T) = (0, 11)
3043 16:31:08.633033 best DQS1 dly(2T, 0.5T) = (0, 11)
3044 16:31:08.633085 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3045 16:31:08.633137 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3046 16:31:08.633188 best DQS0 dly(2T, 0.5T) = (0, 11)
3047 16:31:08.633240 best DQS1 dly(2T, 0.5T) = (0, 11)
3048 16:31:08.633292 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3049 16:31:08.633362 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3050 16:31:08.633428 Pre-setting of DQS Precalculation
3051 16:31:08.633481 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3052 16:31:08.633534 ==
3053 16:31:08.633587 Dram Type= 6, Freq= 0, CH_1, rank 0
3054 16:31:08.633643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 16:31:08.633702 ==
3056 16:31:08.633754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3057 16:31:08.633807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=23, u1VrefScanEnd=33
3058 16:31:08.633860 [CA 0] Center 37 (7~68) winsize 62
3059 16:31:08.633913 [CA 1] Center 37 (7~68) winsize 62
3060 16:31:08.633966 [CA 2] Center 35 (5~65) winsize 61
3061 16:31:08.634018 [CA 3] Center 34 (4~65) winsize 62
3062 16:31:08.634071 [CA 4] Center 34 (4~64) winsize 61
3063 16:31:08.634123 [CA 5] Center 33 (3~64) winsize 62
3064 16:31:08.634185
3065 16:31:08.634263 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3066 16:31:08.634339
3067 16:31:08.634394 [CATrainingPosCal] consider 1 rank data
3068 16:31:08.634447 u2DelayCellTimex100 = 270/100 ps
3069 16:31:08.634500 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3070 16:31:08.634554 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3071 16:31:08.634607 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3072 16:31:08.634660 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3073 16:31:08.634714 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3074 16:31:08.634766 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3075 16:31:08.634819
3076 16:31:08.634870 CA PerBit enable=1, Macro0, CA PI delay=33
3077 16:31:08.634923
3078 16:31:08.634974 [CBTSetCACLKResult] CA Dly = 33
3079 16:31:08.635027 CS Dly: 5 (0~36)
3080 16:31:08.635106 ==
3081 16:31:08.635197 Dram Type= 6, Freq= 0, CH_1, rank 1
3082 16:31:08.635251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 16:31:08.635305 ==
3084 16:31:08.635358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3085 16:31:08.635411 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3086 16:31:08.635465 [CA 0] Center 38 (8~68) winsize 61
3087 16:31:08.635518 [CA 1] Center 38 (7~69) winsize 63
3088 16:31:08.635571 [CA 2] Center 35 (5~66) winsize 62
3089 16:31:08.635624 [CA 3] Center 35 (5~65) winsize 61
3090 16:31:08.635676 [CA 4] Center 34 (4~64) winsize 61
3091 16:31:08.635729 [CA 5] Center 34 (4~64) winsize 61
3092 16:31:08.635782
3093 16:31:08.635834 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3094 16:31:08.635888
3095 16:31:08.635940 [CATrainingPosCal] consider 2 rank data
3096 16:31:08.635992 u2DelayCellTimex100 = 270/100 ps
3097 16:31:08.636044 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3098 16:31:08.636097 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3099 16:31:08.636149 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3100 16:31:08.636203 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3101 16:31:08.636285 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3102 16:31:08.636338 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3103 16:31:08.636390
3104 16:31:08.636442 CA PerBit enable=1, Macro0, CA PI delay=34
3105 16:31:08.636494
3106 16:31:08.636567 [CBTSetCACLKResult] CA Dly = 34
3107 16:31:08.636644 CS Dly: 6 (0~39)
3108 16:31:08.636696
3109 16:31:08.636749 ----->DramcWriteLeveling(PI) begin...
3110 16:31:08.636803 ==
3111 16:31:08.636856 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 16:31:08.636908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 16:31:08.636961 ==
3114 16:31:08.637013 Write leveling (Byte 0): 24 => 24
3115 16:31:08.637066 Write leveling (Byte 1): 29 => 29
3116 16:31:08.637119 DramcWriteLeveling(PI) end<-----
3117 16:31:08.637171
3118 16:31:08.637224 ==
3119 16:31:08.637276 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 16:31:08.637330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 16:31:08.637383 ==
3122 16:31:08.637436 [Gating] SW mode calibration
3123 16:31:08.637490 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3124 16:31:08.637543 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3125 16:31:08.637596 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 16:31:08.637650 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 16:31:08.637703 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 16:31:08.637756 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 16:31:08.637809 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 16:31:08.638067 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
3131 16:31:08.638184 0 15 24 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (1 0)
3132 16:31:08.638240 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3133 16:31:08.638296 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 16:31:08.638364 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 16:31:08.638418 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 16:31:08.638470 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 16:31:08.638523 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 16:31:08.638576 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 16:31:08.638629 1 0 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3140 16:31:08.638682 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 16:31:08.638734 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 16:31:08.638787 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 16:31:08.638840 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 16:31:08.638893 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 16:31:08.638946 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 16:31:08.638998 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 16:31:08.639051 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3148 16:31:08.639104 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3149 16:31:08.639203 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 16:31:08.639260 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 16:31:08.639315 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 16:31:08.639370 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 16:31:08.639424 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 16:31:08.639491 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 16:31:08.639544 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 16:31:08.639596 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 16:31:08.639649 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 16:31:08.639702 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 16:31:08.639755 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 16:31:08.639808 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 16:31:08.639862 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 16:31:08.639914 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 16:31:08.639968 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3164 16:31:08.640020 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3165 16:31:08.640073 Total UI for P1: 0, mck2ui 16
3166 16:31:08.640126 best dqsien dly found for B0: ( 1, 3, 24)
3167 16:31:08.640179 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 16:31:08.640231 Total UI for P1: 0, mck2ui 16
3169 16:31:08.640284 best dqsien dly found for B1: ( 1, 3, 26)
3170 16:31:08.640337 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3171 16:31:08.640390 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3172 16:31:08.640442
3173 16:31:08.640495 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3174 16:31:08.640577 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3175 16:31:08.640649 [Gating] SW calibration Done
3176 16:31:08.640702 ==
3177 16:31:08.640755 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 16:31:08.640809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 16:31:08.640862 ==
3180 16:31:08.640915 RX Vref Scan: 0
3181 16:31:08.640967
3182 16:31:08.641020 RX Vref 0 -> 0, step: 1
3183 16:31:08.641073
3184 16:31:08.641157 RX Delay -40 -> 252, step: 8
3185 16:31:08.641210 iDelay=200, Bit 0, Center 119 (56 ~ 183) 128
3186 16:31:08.641263 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3187 16:31:08.641315 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3188 16:31:08.641369 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3189 16:31:08.641422 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3190 16:31:08.641475 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3191 16:31:08.641527 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3192 16:31:08.641580 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3193 16:31:08.641633 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3194 16:31:08.641686 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3195 16:31:08.641738 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3196 16:31:08.641791 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3197 16:31:08.641843 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3198 16:31:08.641896 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3199 16:31:08.641949 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3200 16:31:08.642002 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3201 16:31:08.642054 ==
3202 16:31:08.642124 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 16:31:08.642190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 16:31:08.642243 ==
3205 16:31:08.642296 DQS Delay:
3206 16:31:08.642348 DQS0 = 0, DQS1 = 0
3207 16:31:08.642401 DQM Delay:
3208 16:31:08.642454 DQM0 = 119, DQM1 = 113
3209 16:31:08.642506 DQ Delay:
3210 16:31:08.642558 DQ0 =119, DQ1 =115, DQ2 =107, DQ3 =123
3211 16:31:08.642611 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3212 16:31:08.642664 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
3213 16:31:08.642717 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3214 16:31:08.642771
3215 16:31:08.642823
3216 16:31:08.642875 ==
3217 16:31:08.642928 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 16:31:08.643006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 16:31:08.643073 ==
3220 16:31:08.643155
3221 16:31:08.643242
3222 16:31:08.643295 TX Vref Scan disable
3223 16:31:08.643348 == TX Byte 0 ==
3224 16:31:08.643402 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3225 16:31:08.643455 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3226 16:31:08.643508 == TX Byte 1 ==
3227 16:31:08.643561 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3228 16:31:08.643614 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3229 16:31:08.643667 ==
3230 16:31:08.643720 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 16:31:08.643773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 16:31:08.643827 ==
3233 16:31:08.643880 TX Vref=22, minBit 10, minWin=24, winSum=405
3234 16:31:08.643934 TX Vref=24, minBit 11, minWin=24, winSum=409
3235 16:31:08.643987 TX Vref=26, minBit 8, minWin=25, winSum=416
3236 16:31:08.644040 TX Vref=28, minBit 9, minWin=25, winSum=421
3237 16:31:08.644093 TX Vref=30, minBit 10, minWin=25, winSum=424
3238 16:31:08.644360 TX Vref=32, minBit 9, minWin=24, winSum=419
3239 16:31:08.644422 [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 30
3240 16:31:08.644479
3241 16:31:08.644533 Final TX Range 1 Vref 30
3242 16:31:08.644619
3243 16:31:08.644674 ==
3244 16:31:08.644727 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 16:31:08.644781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 16:31:08.644834 ==
3247 16:31:08.644886
3248 16:31:08.644939
3249 16:31:08.644991 TX Vref Scan disable
3250 16:31:08.645076 == TX Byte 0 ==
3251 16:31:08.645129 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3252 16:31:08.645183 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3253 16:31:08.645236 == TX Byte 1 ==
3254 16:31:08.645289 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3255 16:31:08.645371 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3256 16:31:08.645423
3257 16:31:08.645475 [DATLAT]
3258 16:31:08.645528 Freq=1200, CH1 RK0
3259 16:31:08.645581
3260 16:31:08.645672 DATLAT Default: 0xd
3261 16:31:08.645725 0, 0xFFFF, sum = 0
3262 16:31:08.645779 1, 0xFFFF, sum = 0
3263 16:31:08.645834 2, 0xFFFF, sum = 0
3264 16:31:08.645887 3, 0xFFFF, sum = 0
3265 16:31:08.645973 4, 0xFFFF, sum = 0
3266 16:31:08.646026 5, 0xFFFF, sum = 0
3267 16:31:08.646079 6, 0xFFFF, sum = 0
3268 16:31:08.646133 7, 0xFFFF, sum = 0
3269 16:31:08.646204 8, 0xFFFF, sum = 0
3270 16:31:08.646271 9, 0xFFFF, sum = 0
3271 16:31:08.646325 10, 0xFFFF, sum = 0
3272 16:31:08.646378 11, 0xFFFF, sum = 0
3273 16:31:08.646432 12, 0x0, sum = 1
3274 16:31:08.646516 13, 0x0, sum = 2
3275 16:31:08.646569 14, 0x0, sum = 3
3276 16:31:08.646622 15, 0x0, sum = 4
3277 16:31:08.646674 best_step = 13
3278 16:31:08.646753
3279 16:31:08.646829 ==
3280 16:31:08.646882 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 16:31:08.646936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 16:31:08.647006 ==
3283 16:31:08.647074 RX Vref Scan: 1
3284 16:31:08.647128
3285 16:31:08.647180 Set Vref Range= 32 -> 127
3286 16:31:08.647252
3287 16:31:08.647334 RX Vref 32 -> 127, step: 1
3288 16:31:08.647391
3289 16:31:08.647445 RX Delay -13 -> 252, step: 4
3290 16:31:08.647500
3291 16:31:08.647581 Set Vref, RX VrefLevel [Byte0]: 32
3292 16:31:08.647649 [Byte1]: 32
3293 16:31:08.647702
3294 16:31:08.647755 Set Vref, RX VrefLevel [Byte0]: 33
3295 16:31:08.647807 [Byte1]: 33
3296 16:31:08.647876
3297 16:31:08.647941 Set Vref, RX VrefLevel [Byte0]: 34
3298 16:31:08.647993 [Byte1]: 34
3299 16:31:08.648044
3300 16:31:08.648095 Set Vref, RX VrefLevel [Byte0]: 35
3301 16:31:08.648162 [Byte1]: 35
3302 16:31:08.648214
3303 16:31:08.648266 Set Vref, RX VrefLevel [Byte0]: 36
3304 16:31:08.648332 [Byte1]: 36
3305 16:31:08.648384
3306 16:31:08.648434 Set Vref, RX VrefLevel [Byte0]: 37
3307 16:31:08.648485 [Byte1]: 37
3308 16:31:08.648536
3309 16:31:08.648630 Set Vref, RX VrefLevel [Byte0]: 38
3310 16:31:08.648682 [Byte1]: 38
3311 16:31:08.648734
3312 16:31:08.648785 Set Vref, RX VrefLevel [Byte0]: 39
3313 16:31:08.648836 [Byte1]: 39
3314 16:31:08.648888
3315 16:31:08.648938 Set Vref, RX VrefLevel [Byte0]: 40
3316 16:31:08.648989 [Byte1]: 40
3317 16:31:08.649040
3318 16:31:08.649091 Set Vref, RX VrefLevel [Byte0]: 41
3319 16:31:08.649142 [Byte1]: 41
3320 16:31:08.649194
3321 16:31:08.649244 Set Vref, RX VrefLevel [Byte0]: 42
3322 16:31:08.649296 [Byte1]: 42
3323 16:31:08.649347
3324 16:31:08.649397 Set Vref, RX VrefLevel [Byte0]: 43
3325 16:31:08.649448 [Byte1]: 43
3326 16:31:08.649499
3327 16:31:08.649549 Set Vref, RX VrefLevel [Byte0]: 44
3328 16:31:08.649600 [Byte1]: 44
3329 16:31:08.649651
3330 16:31:08.649701 Set Vref, RX VrefLevel [Byte0]: 45
3331 16:31:08.649752 [Byte1]: 45
3332 16:31:08.649803
3333 16:31:08.649853 Set Vref, RX VrefLevel [Byte0]: 46
3334 16:31:08.649934 [Byte1]: 46
3335 16:31:08.649985
3336 16:31:08.650036 Set Vref, RX VrefLevel [Byte0]: 47
3337 16:31:08.650088 [Byte1]: 47
3338 16:31:08.650139
3339 16:31:08.650190 Set Vref, RX VrefLevel [Byte0]: 48
3340 16:31:08.650241 [Byte1]: 48
3341 16:31:08.650291
3342 16:31:08.650341 Set Vref, RX VrefLevel [Byte0]: 49
3343 16:31:08.650393 [Byte1]: 49
3344 16:31:08.650444
3345 16:31:08.650494 Set Vref, RX VrefLevel [Byte0]: 50
3346 16:31:08.650545 [Byte1]: 50
3347 16:31:08.650595
3348 16:31:08.650646 Set Vref, RX VrefLevel [Byte0]: 51
3349 16:31:08.650697 [Byte1]: 51
3350 16:31:08.650748
3351 16:31:08.650830 Set Vref, RX VrefLevel [Byte0]: 52
3352 16:31:08.650898 [Byte1]: 52
3353 16:31:08.650962
3354 16:31:08.651035 Set Vref, RX VrefLevel [Byte0]: 53
3355 16:31:08.651099 [Byte1]: 53
3356 16:31:08.651149
3357 16:31:08.651200 Set Vref, RX VrefLevel [Byte0]: 54
3358 16:31:08.651251 [Byte1]: 54
3359 16:31:08.651301
3360 16:31:08.651352 Set Vref, RX VrefLevel [Byte0]: 55
3361 16:31:08.651442 [Byte1]: 55
3362 16:31:08.651493
3363 16:31:08.651558 Set Vref, RX VrefLevel [Byte0]: 56
3364 16:31:08.651621 [Byte1]: 56
3365 16:31:08.651674
3366 16:31:08.651724 Set Vref, RX VrefLevel [Byte0]: 57
3367 16:31:08.651776 [Byte1]: 57
3368 16:31:08.651863
3369 16:31:08.651915 Set Vref, RX VrefLevel [Byte0]: 58
3370 16:31:08.651966 [Byte1]: 58
3371 16:31:08.652018
3372 16:31:08.652068 Set Vref, RX VrefLevel [Byte0]: 59
3373 16:31:08.652148 [Byte1]: 59
3374 16:31:08.652199
3375 16:31:08.652250 Set Vref, RX VrefLevel [Byte0]: 60
3376 16:31:08.652301 [Byte1]: 60
3377 16:31:08.652352
3378 16:31:08.652404 Set Vref, RX VrefLevel [Byte0]: 61
3379 16:31:08.652472 [Byte1]: 61
3380 16:31:08.652524
3381 16:31:08.652604 Set Vref, RX VrefLevel [Byte0]: 62
3382 16:31:08.652657 [Byte1]: 62
3383 16:31:08.652708
3384 16:31:08.652759 Set Vref, RX VrefLevel [Byte0]: 63
3385 16:31:08.652854 [Byte1]: 63
3386 16:31:08.652949
3387 16:31:08.653041 Set Vref, RX VrefLevel [Byte0]: 64
3388 16:31:08.653137 [Byte1]: 64
3389 16:31:08.653195
3390 16:31:08.653249 Set Vref, RX VrefLevel [Byte0]: 65
3391 16:31:08.653303 [Byte1]: 65
3392 16:31:08.653355
3393 16:31:08.653407 Set Vref, RX VrefLevel [Byte0]: 66
3394 16:31:08.653459 [Byte1]: 66
3395 16:31:08.653510
3396 16:31:08.653561 Set Vref, RX VrefLevel [Byte0]: 67
3397 16:31:08.653612 [Byte1]: 67
3398 16:31:08.653664
3399 16:31:08.653715 Final RX Vref Byte 0 = 52 to rank0
3400 16:31:08.653767 Final RX Vref Byte 1 = 58 to rank0
3401 16:31:08.653842 Final RX Vref Byte 0 = 52 to rank1
3402 16:31:08.653908 Final RX Vref Byte 1 = 58 to rank1==
3403 16:31:08.653959 Dram Type= 6, Freq= 0, CH_1, rank 0
3404 16:31:08.654011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 16:31:08.654064 ==
3406 16:31:08.654116 DQS Delay:
3407 16:31:08.654182 DQS0 = 0, DQS1 = 0
3408 16:31:08.654247 DQM Delay:
3409 16:31:08.654586 DQM0 = 119, DQM1 = 113
3410 16:31:08.654661 DQ Delay:
3411 16:31:08.654714 DQ0 =120, DQ1 =114, DQ2 =112, DQ3 =118
3412 16:31:08.654766 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3413 16:31:08.654848 DQ8 =102, DQ9 =100, DQ10 =116, DQ11 =106
3414 16:31:08.654915 DQ12 =124, DQ13 =118, DQ14 =120, DQ15 =122
3415 16:31:08.654967
3416 16:31:08.655019
3417 16:31:08.655071 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3418 16:31:08.655126 CH1 RK0: MR19=404, MR18=215
3419 16:31:08.655178 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3420 16:31:08.655232
3421 16:31:08.655285 ----->DramcWriteLeveling(PI) begin...
3422 16:31:08.655340 ==
3423 16:31:08.655393 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 16:31:08.655446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 16:31:08.655499 ==
3426 16:31:08.655552 Write leveling (Byte 0): 26 => 26
3427 16:31:08.655604 Write leveling (Byte 1): 28 => 28
3428 16:31:08.655657 DramcWriteLeveling(PI) end<-----
3429 16:31:08.655709
3430 16:31:08.655761 ==
3431 16:31:08.655813 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 16:31:08.655865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 16:31:08.655918 ==
3434 16:31:08.655970 [Gating] SW mode calibration
3435 16:31:08.656022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3436 16:31:08.656075 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3437 16:31:08.656128 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 16:31:08.656181 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 16:31:08.656234 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 16:31:08.656286 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 16:31:08.656339 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 16:31:08.656392 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 16:31:08.656444 0 15 24 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 0)
3444 16:31:08.656497 0 15 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3445 16:31:08.656562 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 16:31:08.656618 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 16:31:08.656670 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 16:31:08.656723 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 16:31:08.656790 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 16:31:08.656867 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 16:31:08.656922 1 0 24 | B1->B0 | 3e3e 2d2d | 0 0 | (0 0) (0 0)
3452 16:31:08.656975 1 0 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
3453 16:31:08.657028 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 16:31:08.657081 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 16:31:08.657133 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 16:31:08.657187 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 16:31:08.657239 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 16:31:08.657292 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 16:31:08.657345 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3460 16:31:08.657397 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3461 16:31:08.657450 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 16:31:08.657503 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 16:31:08.657556 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 16:31:08.657609 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 16:31:08.657661 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 16:31:08.657713 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 16:31:08.657766 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 16:31:08.657819 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 16:31:08.657871 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 16:31:08.657923 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 16:31:08.657976 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 16:31:08.658029 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 16:31:08.658082 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 16:31:08.658135 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 16:31:08.658187 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3476 16:31:08.658239 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 16:31:08.658291 Total UI for P1: 0, mck2ui 16
3478 16:31:08.658345 best dqsien dly found for B0: ( 1, 3, 24)
3479 16:31:08.658398 Total UI for P1: 0, mck2ui 16
3480 16:31:08.658451 best dqsien dly found for B1: ( 1, 3, 24)
3481 16:31:08.658504 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3482 16:31:08.658557 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3483 16:31:08.658610
3484 16:31:08.658663 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3485 16:31:08.658715 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3486 16:31:08.658767 [Gating] SW calibration Done
3487 16:31:08.658819 ==
3488 16:31:08.658872 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 16:31:08.658924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 16:31:08.658977 ==
3491 16:31:08.659030 RX Vref Scan: 0
3492 16:31:08.659083
3493 16:31:08.659135 RX Vref 0 -> 0, step: 1
3494 16:31:08.659188
3495 16:31:08.659239 RX Delay -40 -> 252, step: 8
3496 16:31:08.659291 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3497 16:31:08.659343 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3498 16:31:08.659396 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3499 16:31:08.659448 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3500 16:31:08.659501 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3501 16:31:08.659553 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3502 16:31:08.659605 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3503 16:31:08.659658 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3504 16:31:08.659710 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3505 16:31:08.659762 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3506 16:31:08.659814 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3507 16:31:08.659865 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3508 16:31:08.659918 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3509 16:31:08.660174 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3510 16:31:08.660238 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3511 16:31:08.660293 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3512 16:31:08.660347 ==
3513 16:31:08.660400 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 16:31:08.660453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 16:31:08.660506 ==
3516 16:31:08.660599 DQS Delay:
3517 16:31:08.660654 DQS0 = 0, DQS1 = 0
3518 16:31:08.660707 DQM Delay:
3519 16:31:08.660760 DQM0 = 119, DQM1 = 113
3520 16:31:08.660812 DQ Delay:
3521 16:31:08.660865 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3522 16:31:08.660918 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3523 16:31:08.660971 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3524 16:31:08.661023 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3525 16:31:08.661076
3526 16:31:08.661128
3527 16:31:08.661179 ==
3528 16:31:08.661232 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 16:31:08.661284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 16:31:08.661336 ==
3531 16:31:08.661388
3532 16:31:08.661440
3533 16:31:08.661492 TX Vref Scan disable
3534 16:31:08.661544 == TX Byte 0 ==
3535 16:31:08.661596 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3536 16:31:08.661675 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3537 16:31:08.661732 == TX Byte 1 ==
3538 16:31:08.661785 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3539 16:31:08.661837 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3540 16:31:08.661889 ==
3541 16:31:08.661941 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 16:31:08.661994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 16:31:08.662047 ==
3544 16:31:08.662098 TX Vref=22, minBit 1, minWin=25, winSum=418
3545 16:31:08.662151 TX Vref=24, minBit 3, minWin=25, winSum=424
3546 16:31:08.662206 TX Vref=26, minBit 9, minWin=25, winSum=424
3547 16:31:08.662265 TX Vref=28, minBit 1, minWin=26, winSum=429
3548 16:31:08.662317 TX Vref=30, minBit 3, minWin=26, winSum=429
3549 16:31:08.662369 TX Vref=32, minBit 1, minWin=26, winSum=427
3550 16:31:08.662422 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3551 16:31:08.662475
3552 16:31:08.662526 Final TX Range 1 Vref 28
3553 16:31:08.662578
3554 16:31:08.662629 ==
3555 16:31:08.662681 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 16:31:08.662733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 16:31:08.662790 ==
3558 16:31:08.662895
3559 16:31:08.662975
3560 16:31:08.663030 TX Vref Scan disable
3561 16:31:08.663083 == TX Byte 0 ==
3562 16:31:08.663136 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3563 16:31:08.663190 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3564 16:31:08.663242 == TX Byte 1 ==
3565 16:31:08.663295 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3566 16:31:08.663346 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3567 16:31:08.663398
3568 16:31:08.663450 [DATLAT]
3569 16:31:08.663502 Freq=1200, CH1 RK1
3570 16:31:08.663555
3571 16:31:08.663607 DATLAT Default: 0xd
3572 16:31:08.663659 0, 0xFFFF, sum = 0
3573 16:31:08.663713 1, 0xFFFF, sum = 0
3574 16:31:08.663767 2, 0xFFFF, sum = 0
3575 16:31:08.663820 3, 0xFFFF, sum = 0
3576 16:31:08.663873 4, 0xFFFF, sum = 0
3577 16:31:08.663926 5, 0xFFFF, sum = 0
3578 16:31:08.663979 6, 0xFFFF, sum = 0
3579 16:31:08.664031 7, 0xFFFF, sum = 0
3580 16:31:08.664084 8, 0xFFFF, sum = 0
3581 16:31:08.664136 9, 0xFFFF, sum = 0
3582 16:31:08.664189 10, 0xFFFF, sum = 0
3583 16:31:08.664242 11, 0xFFFF, sum = 0
3584 16:31:08.664295 12, 0x0, sum = 1
3585 16:31:08.664347 13, 0x0, sum = 2
3586 16:31:08.664400 14, 0x0, sum = 3
3587 16:31:08.664452 15, 0x0, sum = 4
3588 16:31:08.664505 best_step = 13
3589 16:31:08.664586
3590 16:31:08.664640 ==
3591 16:31:08.664715 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 16:31:08.664770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 16:31:08.664823 ==
3594 16:31:08.664875 RX Vref Scan: 0
3595 16:31:08.664927
3596 16:31:08.664979 RX Vref 0 -> 0, step: 1
3597 16:31:08.665030
3598 16:31:08.665082 RX Delay -13 -> 252, step: 4
3599 16:31:08.665133 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3600 16:31:08.665186 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3601 16:31:08.665237 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3602 16:31:08.665290 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3603 16:31:08.665342 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3604 16:31:08.665395 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3605 16:31:08.665447 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3606 16:31:08.665499 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3607 16:31:08.665552 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3608 16:31:08.665620 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3609 16:31:08.665673 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3610 16:31:08.665726 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3611 16:31:08.665779 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3612 16:31:08.665831 iDelay=195, Bit 13, Center 122 (59 ~ 186) 128
3613 16:31:08.665883 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3614 16:31:08.665935 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3615 16:31:08.665988 ==
3616 16:31:08.666041 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 16:31:08.666123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 16:31:08.666179 ==
3619 16:31:08.666232 DQS Delay:
3620 16:31:08.666284 DQS0 = 0, DQS1 = 0
3621 16:31:08.666336 DQM Delay:
3622 16:31:08.666388 DQM0 = 119, DQM1 = 113
3623 16:31:08.666441 DQ Delay:
3624 16:31:08.666493 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3625 16:31:08.666545 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3626 16:31:08.666597 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =108
3627 16:31:08.666649 DQ12 =122, DQ13 =122, DQ14 =120, DQ15 =124
3628 16:31:08.666702
3629 16:31:08.666754
3630 16:31:08.666806 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3631 16:31:08.666859 CH1 RK1: MR19=403, MR18=CF1
3632 16:31:08.666912 CH1_RK1: MR19=0x403, MR18=0xCF1, DQSOSC=405, MR23=63, INC=39, DEC=26
3633 16:31:08.666965 [RxdqsGatingPostProcess] freq 1200
3634 16:31:08.667018 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3635 16:31:08.667070 best DQS0 dly(2T, 0.5T) = (0, 11)
3636 16:31:08.667122 best DQS1 dly(2T, 0.5T) = (0, 11)
3637 16:31:08.667174 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3638 16:31:08.667226 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3639 16:31:08.667278 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 16:31:08.667330 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 16:31:08.667382 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 16:31:08.667434 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 16:31:08.667485 Pre-setting of DQS Precalculation
3644 16:31:08.667537 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3645 16:31:08.667590 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3646 16:31:08.667847 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3647 16:31:08.667907
3648 16:31:08.667960
3649 16:31:08.668013 [Calibration Summary] 2400 Mbps
3650 16:31:08.668066 CH 0, Rank 0
3651 16:31:08.668143 SW Impedance : PASS
3652 16:31:08.668201 DUTY Scan : NO K
3653 16:31:08.668255 ZQ Calibration : PASS
3654 16:31:08.668309 Jitter Meter : NO K
3655 16:31:08.668362 CBT Training : PASS
3656 16:31:08.668414 Write leveling : PASS
3657 16:31:08.668467 RX DQS gating : PASS
3658 16:31:08.668519 RX DQ/DQS(RDDQC) : PASS
3659 16:31:08.668590 TX DQ/DQS : PASS
3660 16:31:08.668644 RX DATLAT : PASS
3661 16:31:08.668697 RX DQ/DQS(Engine): PASS
3662 16:31:08.668749 TX OE : NO K
3663 16:31:08.668802 All Pass.
3664 16:31:08.668855
3665 16:31:08.668906 CH 0, Rank 1
3666 16:31:08.668958 SW Impedance : PASS
3667 16:31:08.669010 DUTY Scan : NO K
3668 16:31:08.669063 ZQ Calibration : PASS
3669 16:31:08.669115 Jitter Meter : NO K
3670 16:31:08.669167 CBT Training : PASS
3671 16:31:08.669219 Write leveling : PASS
3672 16:31:08.669272 RX DQS gating : PASS
3673 16:31:08.669324 RX DQ/DQS(RDDQC) : PASS
3674 16:31:08.669376 TX DQ/DQS : PASS
3675 16:31:08.669428 RX DATLAT : PASS
3676 16:31:08.669480 RX DQ/DQS(Engine): PASS
3677 16:31:08.669532 TX OE : NO K
3678 16:31:08.669583 All Pass.
3679 16:31:08.669635
3680 16:31:08.669687 CH 1, Rank 0
3681 16:31:08.669738 SW Impedance : PASS
3682 16:31:08.669791 DUTY Scan : NO K
3683 16:31:08.669856 ZQ Calibration : PASS
3684 16:31:08.669911 Jitter Meter : NO K
3685 16:31:08.669964 CBT Training : PASS
3686 16:31:08.670016 Write leveling : PASS
3687 16:31:08.670068 RX DQS gating : PASS
3688 16:31:08.670121 RX DQ/DQS(RDDQC) : PASS
3689 16:31:08.670173 TX DQ/DQS : PASS
3690 16:31:08.670225 RX DATLAT : PASS
3691 16:31:08.670277 RX DQ/DQS(Engine): PASS
3692 16:31:08.670330 TX OE : NO K
3693 16:31:08.670383 All Pass.
3694 16:31:08.670434
3695 16:31:08.670486 CH 1, Rank 1
3696 16:31:08.670547 SW Impedance : PASS
3697 16:31:08.670600 DUTY Scan : NO K
3698 16:31:08.670654 ZQ Calibration : PASS
3699 16:31:08.670707 Jitter Meter : NO K
3700 16:31:08.670759 CBT Training : PASS
3701 16:31:08.670845 Write leveling : PASS
3702 16:31:08.670900 RX DQS gating : PASS
3703 16:31:08.670953 RX DQ/DQS(RDDQC) : PASS
3704 16:31:08.671005 TX DQ/DQS : PASS
3705 16:31:08.671058 RX DATLAT : PASS
3706 16:31:08.671109 RX DQ/DQS(Engine): PASS
3707 16:31:08.671162 TX OE : NO K
3708 16:31:08.671214 All Pass.
3709 16:31:08.671266
3710 16:31:08.671318 DramC Write-DBI off
3711 16:31:08.671370 PER_BANK_REFRESH: Hybrid Mode
3712 16:31:08.671423 TX_TRACKING: ON
3713 16:31:08.671476 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3714 16:31:08.671529 [FAST_K] Save calibration result to emmc
3715 16:31:08.671582 dramc_set_vcore_voltage set vcore to 650000
3716 16:31:08.671635 Read voltage for 600, 5
3717 16:31:08.671686 Vio18 = 0
3718 16:31:08.671738 Vcore = 650000
3719 16:31:08.671790 Vdram = 0
3720 16:31:08.671843 Vddq = 0
3721 16:31:08.671900 Vmddr = 0
3722 16:31:08.671953 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3723 16:31:08.672005 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3724 16:31:08.672058 MEM_TYPE=3, freq_sel=19
3725 16:31:08.672136 sv_algorithm_assistance_LP4_1600
3726 16:31:08.672239 ============ PULL DRAM RESETB DOWN ============
3727 16:31:08.672342 ========== PULL DRAM RESETB DOWN end =========
3728 16:31:08.672448 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3729 16:31:08.672550 ===================================
3730 16:31:08.672611 LPDDR4 DRAM CONFIGURATION
3731 16:31:08.672667 ===================================
3732 16:31:08.672722 EX_ROW_EN[0] = 0x0
3733 16:31:08.672776 EX_ROW_EN[1] = 0x0
3734 16:31:08.672829 LP4Y_EN = 0x0
3735 16:31:08.672882 WORK_FSP = 0x0
3736 16:31:08.672934 WL = 0x2
3737 16:31:08.672985 RL = 0x2
3738 16:31:08.673038 BL = 0x2
3739 16:31:08.673091 RPST = 0x0
3740 16:31:08.673142 RD_PRE = 0x0
3741 16:31:08.673194 WR_PRE = 0x1
3742 16:31:08.673246 WR_PST = 0x0
3743 16:31:08.673298 DBI_WR = 0x0
3744 16:31:08.673349 DBI_RD = 0x0
3745 16:31:08.673401 OTF = 0x1
3746 16:31:08.673453 ===================================
3747 16:31:08.673505 ===================================
3748 16:31:08.673557 ANA top config
3749 16:31:08.673608 ===================================
3750 16:31:08.673660 DLL_ASYNC_EN = 0
3751 16:31:08.673711 ALL_SLAVE_EN = 1
3752 16:31:08.673763 NEW_RANK_MODE = 1
3753 16:31:08.673818 DLL_IDLE_MODE = 1
3754 16:31:08.673888 LP45_APHY_COMB_EN = 1
3755 16:31:08.673941 TX_ODT_DIS = 1
3756 16:31:08.673993 NEW_8X_MODE = 1
3757 16:31:08.674045 ===================================
3758 16:31:08.674098 ===================================
3759 16:31:08.674150 data_rate = 1200
3760 16:31:08.674202 CKR = 1
3761 16:31:08.674254 DQ_P2S_RATIO = 8
3762 16:31:08.674306 ===================================
3763 16:31:08.674358 CA_P2S_RATIO = 8
3764 16:31:08.674410 DQ_CA_OPEN = 0
3765 16:31:08.674466 DQ_SEMI_OPEN = 0
3766 16:31:08.674530 CA_SEMI_OPEN = 0
3767 16:31:08.674583 CA_FULL_RATE = 0
3768 16:31:08.674636 DQ_CKDIV4_EN = 1
3769 16:31:08.674689 CA_CKDIV4_EN = 1
3770 16:31:08.674741 CA_PREDIV_EN = 0
3771 16:31:08.674794 PH8_DLY = 0
3772 16:31:08.674847 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3773 16:31:08.674930 DQ_AAMCK_DIV = 4
3774 16:31:08.674985 CA_AAMCK_DIV = 4
3775 16:31:08.675037 CA_ADMCK_DIV = 4
3776 16:31:08.675090 DQ_TRACK_CA_EN = 0
3777 16:31:08.675142 CA_PICK = 600
3778 16:31:08.675194 CA_MCKIO = 600
3779 16:31:08.675248 MCKIO_SEMI = 0
3780 16:31:08.675300 PLL_FREQ = 2288
3781 16:31:08.675353 DQ_UI_PI_RATIO = 32
3782 16:31:08.675404 CA_UI_PI_RATIO = 0
3783 16:31:08.675456 ===================================
3784 16:31:08.675509 ===================================
3785 16:31:08.675561 memory_type:LPDDR4
3786 16:31:08.675612 GP_NUM : 10
3787 16:31:08.675664 SRAM_EN : 1
3788 16:31:08.675716 MD32_EN : 0
3789 16:31:08.675768 ===================================
3790 16:31:08.675821 [ANA_INIT] >>>>>>>>>>>>>>
3791 16:31:08.675872 <<<<<< [CONFIGURE PHASE]: ANA_TX
3792 16:31:08.675925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3793 16:31:08.675978 ===================================
3794 16:31:08.676030 data_rate = 1200,PCW = 0X5800
3795 16:31:08.676082 ===================================
3796 16:31:08.676134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3797 16:31:08.676393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 16:31:08.676458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 16:31:08.676513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3800 16:31:08.676581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3801 16:31:08.676636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3802 16:31:08.676689 [ANA_INIT] flow start
3803 16:31:08.676742 [ANA_INIT] PLL >>>>>>>>
3804 16:31:08.676795 [ANA_INIT] PLL <<<<<<<<
3805 16:31:08.676847 [ANA_INIT] MIDPI >>>>>>>>
3806 16:31:08.676899 [ANA_INIT] MIDPI <<<<<<<<
3807 16:31:08.676950 [ANA_INIT] DLL >>>>>>>>
3808 16:31:08.677002 [ANA_INIT] flow end
3809 16:31:08.677054 ============ LP4 DIFF to SE enter ============
3810 16:31:08.677107 ============ LP4 DIFF to SE exit ============
3811 16:31:08.677159 [ANA_INIT] <<<<<<<<<<<<<
3812 16:31:08.677212 [Flow] Enable top DCM control >>>>>
3813 16:31:08.677264 [Flow] Enable top DCM control <<<<<
3814 16:31:08.677316 Enable DLL master slave shuffle
3815 16:31:08.677368 ==============================================================
3816 16:31:08.677421 Gating Mode config
3817 16:31:08.677474 ==============================================================
3818 16:31:08.677527 Config description:
3819 16:31:08.677579 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3820 16:31:08.677633 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3821 16:31:08.677686 SELPH_MODE 0: By rank 1: By Phase
3822 16:31:08.677739 ==============================================================
3823 16:31:08.677792 GAT_TRACK_EN = 1
3824 16:31:08.677844 RX_GATING_MODE = 2
3825 16:31:08.677896 RX_GATING_TRACK_MODE = 2
3826 16:31:08.677948 SELPH_MODE = 1
3827 16:31:08.678000 PICG_EARLY_EN = 1
3828 16:31:08.678051 VALID_LAT_VALUE = 1
3829 16:31:08.681076 ==============================================================
3830 16:31:08.684494 Enter into Gating configuration >>>>
3831 16:31:08.687403 Exit from Gating configuration <<<<
3832 16:31:08.690810 Enter into DVFS_PRE_config >>>>>
3833 16:31:08.701249 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3834 16:31:08.704461 Exit from DVFS_PRE_config <<<<<
3835 16:31:08.707604 Enter into PICG configuration >>>>
3836 16:31:08.711034 Exit from PICG configuration <<<<
3837 16:31:08.714106 [RX_INPUT] configuration >>>>>
3838 16:31:08.714223 [RX_INPUT] configuration <<<<<
3839 16:31:08.721029 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3840 16:31:08.727483 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3841 16:31:08.731241 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 16:31:08.737470 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 16:31:08.744100 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 16:31:08.751149 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 16:31:08.754357 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3846 16:31:08.757527 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3847 16:31:08.763925 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3848 16:31:08.767424 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3849 16:31:08.770893 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3850 16:31:08.777376 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3851 16:31:08.780941 ===================================
3852 16:31:08.781058 LPDDR4 DRAM CONFIGURATION
3853 16:31:08.784047 ===================================
3854 16:31:08.787088 EX_ROW_EN[0] = 0x0
3855 16:31:08.787188 EX_ROW_EN[1] = 0x0
3856 16:31:08.813490 LP4Y_EN = 0x0
3857 16:31:08.813616 WORK_FSP = 0x0
3858 16:31:08.813686 WL = 0x2
3859 16:31:08.813803 RL = 0x2
3860 16:31:08.813894 BL = 0x2
3861 16:31:08.813989 RPST = 0x0
3862 16:31:08.814082 RD_PRE = 0x0
3863 16:31:08.814168 WR_PRE = 0x1
3864 16:31:08.814275 WR_PST = 0x0
3865 16:31:08.814367 DBI_WR = 0x0
3866 16:31:08.814488 DBI_RD = 0x0
3867 16:31:08.814574 OTF = 0x1
3868 16:31:08.814857 ===================================
3869 16:31:08.817602 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3870 16:31:08.820783 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3871 16:31:08.823914 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 16:31:08.827073 ===================================
3873 16:31:08.830809 LPDDR4 DRAM CONFIGURATION
3874 16:31:08.833894 ===================================
3875 16:31:08.837003 EX_ROW_EN[0] = 0x10
3876 16:31:08.837087 EX_ROW_EN[1] = 0x0
3877 16:31:08.840676 LP4Y_EN = 0x0
3878 16:31:08.840759 WORK_FSP = 0x0
3879 16:31:08.843799 WL = 0x2
3880 16:31:08.843908 RL = 0x2
3881 16:31:08.847344 BL = 0x2
3882 16:31:08.847426 RPST = 0x0
3883 16:31:08.850498 RD_PRE = 0x0
3884 16:31:08.853792 WR_PRE = 0x1
3885 16:31:08.853875 WR_PST = 0x0
3886 16:31:08.857001 DBI_WR = 0x0
3887 16:31:08.857085 DBI_RD = 0x0
3888 16:31:08.860289 OTF = 0x1
3889 16:31:08.863968 ===================================
3890 16:31:08.866974 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3891 16:31:08.872327 nWR fixed to 30
3892 16:31:08.875790 [ModeRegInit_LP4] CH0 RK0
3893 16:31:08.875907 [ModeRegInit_LP4] CH0 RK1
3894 16:31:08.878911 [ModeRegInit_LP4] CH1 RK0
3895 16:31:08.882625 [ModeRegInit_LP4] CH1 RK1
3896 16:31:08.882757 match AC timing 17
3897 16:31:08.889104 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3898 16:31:08.892207 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3899 16:31:08.895673 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3900 16:31:08.902142 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3901 16:31:08.905699 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3902 16:31:08.905788 ==
3903 16:31:08.909290 Dram Type= 6, Freq= 0, CH_0, rank 0
3904 16:31:08.912333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3905 16:31:08.912419 ==
3906 16:31:08.919046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3907 16:31:08.925868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3908 16:31:08.929077 [CA 0] Center 36 (6~67) winsize 62
3909 16:31:08.932301 [CA 1] Center 36 (6~67) winsize 62
3910 16:31:08.935562 [CA 2] Center 34 (4~65) winsize 62
3911 16:31:08.939286 [CA 3] Center 34 (3~65) winsize 63
3912 16:31:08.942452 [CA 4] Center 34 (3~65) winsize 63
3913 16:31:08.945439 [CA 5] Center 33 (3~64) winsize 62
3914 16:31:08.945529
3915 16:31:08.949140 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3916 16:31:08.949225
3917 16:31:08.952187 [CATrainingPosCal] consider 1 rank data
3918 16:31:08.955525 u2DelayCellTimex100 = 270/100 ps
3919 16:31:08.958742 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3920 16:31:08.962381 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3921 16:31:08.965604 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3922 16:31:08.968947 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3923 16:31:08.972021 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3924 16:31:08.975776 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3925 16:31:08.975887
3926 16:31:08.982024 CA PerBit enable=1, Macro0, CA PI delay=33
3927 16:31:08.982115
3928 16:31:08.985773 [CBTSetCACLKResult] CA Dly = 33
3929 16:31:08.985858 CS Dly: 4 (0~35)
3930 16:31:08.985925 ==
3931 16:31:08.988989 Dram Type= 6, Freq= 0, CH_0, rank 1
3932 16:31:08.992125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 16:31:08.992210 ==
3934 16:31:08.998903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 16:31:09.005274 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3936 16:31:09.008721 [CA 0] Center 36 (6~67) winsize 62
3937 16:31:09.012295 [CA 1] Center 36 (6~67) winsize 62
3938 16:31:09.015746 [CA 2] Center 35 (4~66) winsize 63
3939 16:31:09.018962 [CA 3] Center 34 (4~65) winsize 62
3940 16:31:09.022036 [CA 4] Center 34 (4~65) winsize 62
3941 16:31:09.025522 [CA 5] Center 34 (3~65) winsize 63
3942 16:31:09.025608
3943 16:31:09.028531 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3944 16:31:09.028643
3945 16:31:09.031835 [CATrainingPosCal] consider 2 rank data
3946 16:31:09.035139 u2DelayCellTimex100 = 270/100 ps
3947 16:31:09.038777 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3948 16:31:09.041931 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3949 16:31:09.045181 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3950 16:31:09.048430 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 16:31:09.052128 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 16:31:09.058765 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 16:31:09.058849
3954 16:31:09.062018 CA PerBit enable=1, Macro0, CA PI delay=33
3955 16:31:09.062093
3956 16:31:09.065240 [CBTSetCACLKResult] CA Dly = 33
3957 16:31:09.065329 CS Dly: 4 (0~36)
3958 16:31:09.065396
3959 16:31:09.068410 ----->DramcWriteLeveling(PI) begin...
3960 16:31:09.068517 ==
3961 16:31:09.072061 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 16:31:09.075198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 16:31:09.078127 ==
3964 16:31:09.081958 Write leveling (Byte 0): 32 => 32
3965 16:31:09.082038 Write leveling (Byte 1): 32 => 32
3966 16:31:09.085005 DramcWriteLeveling(PI) end<-----
3967 16:31:09.085078
3968 16:31:09.085147 ==
3969 16:31:09.088446 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 16:31:09.095472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 16:31:09.095578 ==
3972 16:31:09.098638 [Gating] SW mode calibration
3973 16:31:09.105078 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3974 16:31:09.108433 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3975 16:31:09.115131 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 16:31:09.118444 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 16:31:09.121894 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3978 16:31:09.124917 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
3979 16:31:09.131802 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
3980 16:31:09.134944 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 16:31:09.138555 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 16:31:09.144978 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 16:31:09.148497 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 16:31:09.151648 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 16:31:09.158512 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3986 16:31:09.161696 0 10 12 | B1->B0 | 2525 3939 | 0 0 | (0 0) (0 0)
3987 16:31:09.164948 0 10 16 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
3988 16:31:09.171849 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 16:31:09.174937 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 16:31:09.178639 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 16:31:09.185015 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 16:31:09.188351 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 16:31:09.191959 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 16:31:09.198351 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3995 16:31:09.202066 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 16:31:09.205303 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3997 16:31:09.211785 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 16:31:09.214817 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 16:31:09.218405 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 16:31:09.221837 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 16:31:09.228749 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 16:31:09.231756 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 16:31:09.235255 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 16:31:09.241865 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 16:31:09.245030 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 16:31:09.248033 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 16:31:09.255048 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 16:31:09.258125 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 16:31:09.261309 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 16:31:09.268264 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4011 16:31:09.271490 Total UI for P1: 0, mck2ui 16
4012 16:31:09.274671 best dqsien dly found for B0: ( 0, 13, 10)
4013 16:31:09.277988 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4014 16:31:09.281459 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 16:31:09.284633 Total UI for P1: 0, mck2ui 16
4016 16:31:09.287850 best dqsien dly found for B1: ( 0, 13, 16)
4017 16:31:09.291058 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4018 16:31:09.298193 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4019 16:31:09.298281
4020 16:31:09.301421 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4021 16:31:09.304542 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4022 16:31:09.307939 [Gating] SW calibration Done
4023 16:31:09.308045 ==
4024 16:31:09.311170 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 16:31:09.314265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 16:31:09.314382 ==
4027 16:31:09.314486 RX Vref Scan: 0
4028 16:31:09.318004
4029 16:31:09.318084 RX Vref 0 -> 0, step: 1
4030 16:31:09.318150
4031 16:31:09.321219 RX Delay -230 -> 252, step: 16
4032 16:31:09.324421 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4033 16:31:09.330992 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4034 16:31:09.334303 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4035 16:31:09.337675 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4036 16:31:09.341144 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4037 16:31:09.344446 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4038 16:31:09.351182 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4039 16:31:09.354316 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4040 16:31:09.357652 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4041 16:31:09.360792 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4042 16:31:09.367483 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4043 16:31:09.370523 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4044 16:31:09.374319 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4045 16:31:09.377422 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4046 16:31:09.383894 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4047 16:31:09.387494 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4048 16:31:09.387580 ==
4049 16:31:09.390777 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 16:31:09.394004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 16:31:09.394082 ==
4052 16:31:09.397651 DQS Delay:
4053 16:31:09.397725 DQS0 = 0, DQS1 = 0
4054 16:31:09.397786 DQM Delay:
4055 16:31:09.400791 DQM0 = 48, DQM1 = 39
4056 16:31:09.400872 DQ Delay:
4057 16:31:09.404104 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4058 16:31:09.407220 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4059 16:31:09.410911 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4060 16:31:09.413982 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4061 16:31:09.414075
4062 16:31:09.414179
4063 16:31:09.414280 ==
4064 16:31:09.417239 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 16:31:09.424000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 16:31:09.424088 ==
4067 16:31:09.424155
4068 16:31:09.424216
4069 16:31:09.424276 TX Vref Scan disable
4070 16:31:09.427141 == TX Byte 0 ==
4071 16:31:09.430901 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4072 16:31:09.437665 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4073 16:31:09.437752 == TX Byte 1 ==
4074 16:31:09.440595 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4075 16:31:09.447126 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4076 16:31:09.447226 ==
4077 16:31:09.450612 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 16:31:09.453987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 16:31:09.454072 ==
4080 16:31:09.454154
4081 16:31:09.454229
4082 16:31:09.457534 TX Vref Scan disable
4083 16:31:09.460500 == TX Byte 0 ==
4084 16:31:09.464126 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4085 16:31:09.467333 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4086 16:31:09.467423 == TX Byte 1 ==
4087 16:31:09.474065 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4088 16:31:09.477181 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4089 16:31:09.477267
4090 16:31:09.477333 [DATLAT]
4091 16:31:09.480966 Freq=600, CH0 RK0
4092 16:31:09.481116
4093 16:31:09.481216 DATLAT Default: 0x9
4094 16:31:09.484034 0, 0xFFFF, sum = 0
4095 16:31:09.484118 1, 0xFFFF, sum = 0
4096 16:31:09.487210 2, 0xFFFF, sum = 0
4097 16:31:09.487294 3, 0xFFFF, sum = 0
4098 16:31:09.490814 4, 0xFFFF, sum = 0
4099 16:31:09.494080 5, 0xFFFF, sum = 0
4100 16:31:09.494165 6, 0xFFFF, sum = 0
4101 16:31:09.497104 7, 0xFFFF, sum = 0
4102 16:31:09.497188 8, 0x0, sum = 1
4103 16:31:09.497256 9, 0x0, sum = 2
4104 16:31:09.500693 10, 0x0, sum = 3
4105 16:31:09.500777 11, 0x0, sum = 4
4106 16:31:09.503773 best_step = 9
4107 16:31:09.503857
4108 16:31:09.503983 ==
4109 16:31:09.506954 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 16:31:09.510212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 16:31:09.510313 ==
4112 16:31:09.513860 RX Vref Scan: 1
4113 16:31:09.513944
4114 16:31:09.514027 RX Vref 0 -> 0, step: 1
4115 16:31:09.514122
4116 16:31:09.517141 RX Delay -179 -> 252, step: 8
4117 16:31:09.517231
4118 16:31:09.520213 Set Vref, RX VrefLevel [Byte0]: 57
4119 16:31:09.523909 [Byte1]: 49
4120 16:31:09.527703
4121 16:31:09.527787 Final RX Vref Byte 0 = 57 to rank0
4122 16:31:09.530902 Final RX Vref Byte 1 = 49 to rank0
4123 16:31:09.534533 Final RX Vref Byte 0 = 57 to rank1
4124 16:31:09.537637 Final RX Vref Byte 1 = 49 to rank1==
4125 16:31:09.540892 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 16:31:09.547775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 16:31:09.547868 ==
4128 16:31:09.547996 DQS Delay:
4129 16:31:09.548107 DQS0 = 0, DQS1 = 0
4130 16:31:09.551088 DQM Delay:
4131 16:31:09.551244 DQM0 = 49, DQM1 = 38
4132 16:31:09.554041 DQ Delay:
4133 16:31:09.557508 DQ0 =44, DQ1 =48, DQ2 =48, DQ3 =44
4134 16:31:09.557611 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4135 16:31:09.560958 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4136 16:31:09.564566 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =44
4137 16:31:09.567739
4138 16:31:09.567823
4139 16:31:09.574476 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f59, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
4140 16:31:09.577980 CH0 RK0: MR19=808, MR18=5F59
4141 16:31:09.584343 CH0_RK0: MR19=0x808, MR18=0x5F59, DQSOSC=391, MR23=63, INC=171, DEC=114
4142 16:31:09.584433
4143 16:31:09.587431 ----->DramcWriteLeveling(PI) begin...
4144 16:31:09.587543 ==
4145 16:31:09.591136 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 16:31:09.594347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 16:31:09.594431 ==
4148 16:31:09.597464 Write leveling (Byte 0): 34 => 34
4149 16:31:09.601138 Write leveling (Byte 1): 30 => 30
4150 16:31:09.604409 DramcWriteLeveling(PI) end<-----
4151 16:31:09.604523
4152 16:31:09.604660 ==
4153 16:31:09.607359 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 16:31:09.611017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 16:31:09.611100 ==
4156 16:31:09.614319 [Gating] SW mode calibration
4157 16:31:09.620722 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4158 16:31:09.627510 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4159 16:31:09.630639 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 16:31:09.634472 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 16:31:09.641259 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 16:31:09.644187 0 9 12 | B1->B0 | 3232 3232 | 1 1 | (1 1) (0 0)
4163 16:31:09.647938 0 9 16 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
4164 16:31:09.654288 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 16:31:09.657729 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 16:31:09.660925 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 16:31:09.668021 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 16:31:09.670978 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 16:31:09.674544 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 16:31:09.680688 0 10 12 | B1->B0 | 3030 3232 | 0 0 | (0 0) (0 0)
4171 16:31:09.684263 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4172 16:31:09.687448 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 16:31:09.694148 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 16:31:09.697806 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 16:31:09.700971 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 16:31:09.707333 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 16:31:09.710926 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 16:31:09.714152 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4179 16:31:09.720987 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 16:31:09.724276 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 16:31:09.727454 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 16:31:09.730611 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 16:31:09.737121 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 16:31:09.740760 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 16:31:09.743987 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 16:31:09.750536 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 16:31:09.754555 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 16:31:09.757281 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 16:31:09.764251 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 16:31:09.767244 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 16:31:09.770824 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 16:31:09.777366 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 16:31:09.780583 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 16:31:09.784281 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 16:31:09.790656 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 16:31:09.790740 Total UI for P1: 0, mck2ui 16
4197 16:31:09.797429 best dqsien dly found for B0: ( 0, 13, 14)
4198 16:31:09.797512 Total UI for P1: 0, mck2ui 16
4199 16:31:09.800701 best dqsien dly found for B1: ( 0, 13, 14)
4200 16:31:09.807102 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4201 16:31:09.810926 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4202 16:31:09.811011
4203 16:31:09.814149 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4204 16:31:09.817314 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4205 16:31:09.820568 [Gating] SW calibration Done
4206 16:31:09.820667 ==
4207 16:31:09.824151 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 16:31:09.827491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 16:31:09.827593 ==
4210 16:31:09.830597 RX Vref Scan: 0
4211 16:31:09.830683
4212 16:31:09.830776 RX Vref 0 -> 0, step: 1
4213 16:31:09.830903
4214 16:31:09.833951 RX Delay -230 -> 252, step: 16
4215 16:31:09.837247 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4216 16:31:09.844219 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4217 16:31:09.847260 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4218 16:31:09.850860 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4219 16:31:09.853999 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4220 16:31:09.857530 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4221 16:31:09.864052 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4222 16:31:09.867712 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4223 16:31:09.870706 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4224 16:31:09.874259 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4225 16:31:09.880766 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4226 16:31:09.884221 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4227 16:31:09.887431 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4228 16:31:09.890991 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4229 16:31:09.897296 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4230 16:31:09.900528 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4231 16:31:09.900679 ==
4232 16:31:09.903860 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 16:31:09.907072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 16:31:09.907213 ==
4235 16:31:09.910706 DQS Delay:
4236 16:31:09.910842 DQS0 = 0, DQS1 = 0
4237 16:31:09.910957 DQM Delay:
4238 16:31:09.913880 DQM0 = 49, DQM1 = 40
4239 16:31:09.914060 DQ Delay:
4240 16:31:09.916997 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4241 16:31:09.920510 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4242 16:31:09.924114 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4243 16:31:09.927286 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4244 16:31:09.927481
4245 16:31:09.927564
4246 16:31:09.927671 ==
4247 16:31:09.930446 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 16:31:09.936883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 16:31:09.937035 ==
4250 16:31:09.937117
4251 16:31:09.937210
4252 16:31:09.937302 TX Vref Scan disable
4253 16:31:09.940730 == TX Byte 0 ==
4254 16:31:09.943892 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4255 16:31:09.950475 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4256 16:31:09.950571 == TX Byte 1 ==
4257 16:31:09.953679 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4258 16:31:09.960508 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4259 16:31:09.960617 ==
4260 16:31:09.963953 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 16:31:09.967092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 16:31:09.967282 ==
4263 16:31:09.967402
4264 16:31:09.967525
4265 16:31:09.970260 TX Vref Scan disable
4266 16:31:09.973623 == TX Byte 0 ==
4267 16:31:09.976911 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4268 16:31:09.980455 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4269 16:31:09.983684 == TX Byte 1 ==
4270 16:31:09.987162 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4271 16:31:09.990111 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4272 16:31:09.990223
4273 16:31:09.990299 [DATLAT]
4274 16:31:09.993679 Freq=600, CH0 RK1
4275 16:31:09.993777
4276 16:31:09.996900 DATLAT Default: 0x9
4277 16:31:09.996991 0, 0xFFFF, sum = 0
4278 16:31:10.000081 1, 0xFFFF, sum = 0
4279 16:31:10.000173 2, 0xFFFF, sum = 0
4280 16:31:10.003686 3, 0xFFFF, sum = 0
4281 16:31:10.003773 4, 0xFFFF, sum = 0
4282 16:31:10.006969 5, 0xFFFF, sum = 0
4283 16:31:10.007057 6, 0xFFFF, sum = 0
4284 16:31:10.010604 7, 0xFFFF, sum = 0
4285 16:31:10.010690 8, 0x0, sum = 1
4286 16:31:10.013468 9, 0x0, sum = 2
4287 16:31:10.013568 10, 0x0, sum = 3
4288 16:31:10.013640 11, 0x0, sum = 4
4289 16:31:10.016677 best_step = 9
4290 16:31:10.016804
4291 16:31:10.016909 ==
4292 16:31:10.019982 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 16:31:10.023676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 16:31:10.023769 ==
4295 16:31:10.026675 RX Vref Scan: 0
4296 16:31:10.026783
4297 16:31:10.026875 RX Vref 0 -> 0, step: 1
4298 16:31:10.029888
4299 16:31:10.030005 RX Delay -179 -> 252, step: 8
4300 16:31:10.037423 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4301 16:31:10.041145 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4302 16:31:10.044352 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4303 16:31:10.047592 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4304 16:31:10.054274 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4305 16:31:10.057538 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4306 16:31:10.060667 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4307 16:31:10.063964 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4308 16:31:10.067685 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4309 16:31:10.074102 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4310 16:31:10.077226 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4311 16:31:10.080744 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4312 16:31:10.084234 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4313 16:31:10.087365 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4314 16:31:10.093967 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4315 16:31:10.097414 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4316 16:31:10.097518 ==
4317 16:31:10.100793 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 16:31:10.103686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 16:31:10.103770 ==
4320 16:31:10.106997 DQS Delay:
4321 16:31:10.107078 DQS0 = 0, DQS1 = 0
4322 16:31:10.107142 DQM Delay:
4323 16:31:10.110678 DQM0 = 48, DQM1 = 40
4324 16:31:10.110759 DQ Delay:
4325 16:31:10.113920 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4326 16:31:10.117341 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4327 16:31:10.120711 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4328 16:31:10.123862 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4329 16:31:10.123942
4330 16:31:10.124006
4331 16:31:10.133433 [DQSOSCAuto] RK1, (LSB)MR18= 0x6432, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4332 16:31:10.137180 CH0 RK1: MR19=808, MR18=6432
4333 16:31:10.140449 CH0_RK1: MR19=0x808, MR18=0x6432, DQSOSC=391, MR23=63, INC=171, DEC=114
4334 16:31:10.143714 [RxdqsGatingPostProcess] freq 600
4335 16:31:10.150188 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4336 16:31:10.153513 Pre-setting of DQS Precalculation
4337 16:31:10.157016 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4338 16:31:10.157098 ==
4339 16:31:10.160305 Dram Type= 6, Freq= 0, CH_1, rank 0
4340 16:31:10.166498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 16:31:10.166591 ==
4342 16:31:10.170243 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4343 16:31:10.176784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4344 16:31:10.180092 [CA 0] Center 35 (5~66) winsize 62
4345 16:31:10.183371 [CA 1] Center 35 (5~66) winsize 62
4346 16:31:10.186795 [CA 2] Center 34 (3~65) winsize 63
4347 16:31:10.190028 [CA 3] Center 33 (3~64) winsize 62
4348 16:31:10.193751 [CA 4] Center 34 (3~65) winsize 63
4349 16:31:10.196828 [CA 5] Center 33 (3~64) winsize 62
4350 16:31:10.196911
4351 16:31:10.199928 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4352 16:31:10.200011
4353 16:31:10.203410 [CATrainingPosCal] consider 1 rank data
4354 16:31:10.206978 u2DelayCellTimex100 = 270/100 ps
4355 16:31:10.209927 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4356 16:31:10.216502 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4357 16:31:10.220260 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4358 16:31:10.223678 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4359 16:31:10.227023 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4360 16:31:10.230312 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4361 16:31:10.230515
4362 16:31:10.233430 CA PerBit enable=1, Macro0, CA PI delay=33
4363 16:31:10.233577
4364 16:31:10.236576 [CBTSetCACLKResult] CA Dly = 33
4365 16:31:10.236732 CS Dly: 4 (0~35)
4366 16:31:10.240245 ==
4367 16:31:10.244685 Dram Type= 6, Freq= 0, CH_1, rank 1
4368 16:31:10.246614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 16:31:10.246771 ==
4370 16:31:10.249958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4371 16:31:10.256423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4372 16:31:10.260609 [CA 0] Center 35 (5~66) winsize 62
4373 16:31:10.263725 [CA 1] Center 35 (5~66) winsize 62
4374 16:31:10.267038 [CA 2] Center 34 (4~65) winsize 62
4375 16:31:10.270197 [CA 3] Center 34 (4~64) winsize 61
4376 16:31:10.273462 [CA 4] Center 34 (4~64) winsize 61
4377 16:31:10.276670 [CA 5] Center 33 (3~64) winsize 62
4378 16:31:10.276815
4379 16:31:10.280021 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4380 16:31:10.280167
4381 16:31:10.283914 [CATrainingPosCal] consider 2 rank data
4382 16:31:10.287048 u2DelayCellTimex100 = 270/100 ps
4383 16:31:10.290339 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4384 16:31:10.296669 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 16:31:10.299976 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 16:31:10.303654 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4387 16:31:10.306862 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4388 16:31:10.310099 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 16:31:10.310192
4390 16:31:10.313614 CA PerBit enable=1, Macro0, CA PI delay=33
4391 16:31:10.313717
4392 16:31:10.316682 [CBTSetCACLKResult] CA Dly = 33
4393 16:31:10.316782 CS Dly: 5 (0~37)
4394 16:31:10.316867
4395 16:31:10.323788 ----->DramcWriteLeveling(PI) begin...
4396 16:31:10.323891 ==
4397 16:31:10.327069 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 16:31:10.330224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 16:31:10.330328 ==
4400 16:31:10.333463 Write leveling (Byte 0): 29 => 29
4401 16:31:10.336657 Write leveling (Byte 1): 32 => 32
4402 16:31:10.339757 DramcWriteLeveling(PI) end<-----
4403 16:31:10.339845
4404 16:31:10.339911 ==
4405 16:31:10.343496 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 16:31:10.346754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 16:31:10.346843 ==
4408 16:31:10.350084 [Gating] SW mode calibration
4409 16:31:10.356563 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4410 16:31:10.363479 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4411 16:31:10.366634 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 16:31:10.369954 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 16:31:10.376241 0 9 8 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
4414 16:31:10.380020 0 9 12 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 0)
4415 16:31:10.383262 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 16:31:10.389704 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 16:31:10.392926 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 16:31:10.396764 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 16:31:10.399858 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 16:31:10.406787 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 16:31:10.409933 0 10 8 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4422 16:31:10.413391 0 10 12 | B1->B0 | 3737 3a3a | 1 0 | (0 0) (0 0)
4423 16:31:10.419740 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 16:31:10.423348 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 16:31:10.426558 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 16:31:10.433032 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 16:31:10.436766 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 16:31:10.440060 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 16:31:10.446222 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 16:31:10.450033 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 16:31:10.453266 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 16:31:10.459610 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 16:31:10.462959 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 16:31:10.466303 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 16:31:10.472799 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 16:31:10.476141 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 16:31:10.479690 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 16:31:10.486359 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 16:31:10.489589 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 16:31:10.492842 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 16:31:10.496540 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 16:31:10.503081 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 16:31:10.506296 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 16:31:10.509535 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 16:31:10.516423 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 16:31:10.519565 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 16:31:10.523209 Total UI for P1: 0, mck2ui 16
4448 16:31:10.526331 best dqsien dly found for B0: ( 0, 13, 10)
4449 16:31:10.529422 Total UI for P1: 0, mck2ui 16
4450 16:31:10.532605 best dqsien dly found for B1: ( 0, 13, 10)
4451 16:31:10.535962 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4452 16:31:10.539660 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4453 16:31:10.539743
4454 16:31:10.542961 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4455 16:31:10.549369 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4456 16:31:10.549482 [Gating] SW calibration Done
4457 16:31:10.549576 ==
4458 16:31:10.552905 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 16:31:10.559495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 16:31:10.559622 ==
4461 16:31:10.559734 RX Vref Scan: 0
4462 16:31:10.559828
4463 16:31:10.562312 RX Vref 0 -> 0, step: 1
4464 16:31:10.562414
4465 16:31:10.565917 RX Delay -230 -> 252, step: 16
4466 16:31:10.569119 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4467 16:31:10.572393 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4468 16:31:10.576180 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4469 16:31:10.582588 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4470 16:31:10.585689 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4471 16:31:10.588953 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4472 16:31:10.592270 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4473 16:31:10.599157 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4474 16:31:10.602482 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4475 16:31:10.605711 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4476 16:31:10.608952 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4477 16:31:10.615529 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4478 16:31:10.618938 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4479 16:31:10.622175 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4480 16:31:10.625330 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4481 16:31:10.631998 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4482 16:31:10.632139 ==
4483 16:31:10.635147 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 16:31:10.638783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 16:31:10.638864 ==
4486 16:31:10.638927 DQS Delay:
4487 16:31:10.642086 DQS0 = 0, DQS1 = 0
4488 16:31:10.642155 DQM Delay:
4489 16:31:10.645638 DQM0 = 52, DQM1 = 45
4490 16:31:10.645710 DQ Delay:
4491 16:31:10.648810 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4492 16:31:10.652032 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4493 16:31:10.655176 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4494 16:31:10.658679 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4495 16:31:10.658756
4496 16:31:10.658820
4497 16:31:10.658883 ==
4498 16:31:10.662111 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 16:31:10.665403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 16:31:10.665474 ==
4501 16:31:10.665535
4502 16:31:10.665593
4503 16:31:10.668535 TX Vref Scan disable
4504 16:31:10.671950 == TX Byte 0 ==
4505 16:31:10.675167 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4506 16:31:10.678457 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4507 16:31:10.682230 == TX Byte 1 ==
4508 16:31:10.685469 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4509 16:31:10.688518 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4510 16:31:10.688607 ==
4511 16:31:10.692034 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 16:31:10.698474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 16:31:10.698559 ==
4514 16:31:10.698630
4515 16:31:10.698694
4516 16:31:10.698754 TX Vref Scan disable
4517 16:31:10.702916 == TX Byte 0 ==
4518 16:31:10.706098 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4519 16:31:10.709420 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4520 16:31:10.713103 == TX Byte 1 ==
4521 16:31:10.716208 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4522 16:31:10.719445 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4523 16:31:10.723187
4524 16:31:10.723267 [DATLAT]
4525 16:31:10.723332 Freq=600, CH1 RK0
4526 16:31:10.723392
4527 16:31:10.726242 DATLAT Default: 0x9
4528 16:31:10.726315 0, 0xFFFF, sum = 0
4529 16:31:10.729539 1, 0xFFFF, sum = 0
4530 16:31:10.729615 2, 0xFFFF, sum = 0
4531 16:31:10.732733 3, 0xFFFF, sum = 0
4532 16:31:10.732805 4, 0xFFFF, sum = 0
4533 16:31:10.736107 5, 0xFFFF, sum = 0
4534 16:31:10.739341 6, 0xFFFF, sum = 0
4535 16:31:10.739436 7, 0xFFFF, sum = 0
4536 16:31:10.739504 8, 0x0, sum = 1
4537 16:31:10.742706 9, 0x0, sum = 2
4538 16:31:10.742791 10, 0x0, sum = 3
4539 16:31:10.746019 11, 0x0, sum = 4
4540 16:31:10.746113 best_step = 9
4541 16:31:10.746179
4542 16:31:10.746246 ==
4543 16:31:10.749687 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 16:31:10.756093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 16:31:10.756206 ==
4546 16:31:10.756293 RX Vref Scan: 1
4547 16:31:10.756354
4548 16:31:10.759213 RX Vref 0 -> 0, step: 1
4549 16:31:10.759302
4550 16:31:10.762723 RX Delay -179 -> 252, step: 8
4551 16:31:10.762797
4552 16:31:10.766059 Set Vref, RX VrefLevel [Byte0]: 52
4553 16:31:10.769280 [Byte1]: 58
4554 16:31:10.769366
4555 16:31:10.772531 Final RX Vref Byte 0 = 52 to rank0
4556 16:31:10.776369 Final RX Vref Byte 1 = 58 to rank0
4557 16:31:10.779618 Final RX Vref Byte 0 = 52 to rank1
4558 16:31:10.782962 Final RX Vref Byte 1 = 58 to rank1==
4559 16:31:10.786187 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 16:31:10.789475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 16:31:10.789553 ==
4562 16:31:10.793055 DQS Delay:
4563 16:31:10.793151 DQS0 = 0, DQS1 = 0
4564 16:31:10.793219 DQM Delay:
4565 16:31:10.796037 DQM0 = 49, DQM1 = 41
4566 16:31:10.796121 DQ Delay:
4567 16:31:10.799288 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4568 16:31:10.803052 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4569 16:31:10.806234 DQ8 =28, DQ9 =32, DQ10 =44, DQ11 =32
4570 16:31:10.809511 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4571 16:31:10.809597
4572 16:31:10.809666
4573 16:31:10.819117 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4574 16:31:10.822451 CH1 RK0: MR19=808, MR18=4A71
4575 16:31:10.826121 CH1_RK0: MR19=0x808, MR18=0x4A71, DQSOSC=388, MR23=63, INC=174, DEC=116
4576 16:31:10.826216
4577 16:31:10.829336 ----->DramcWriteLeveling(PI) begin...
4578 16:31:10.832494 ==
4579 16:31:10.836238 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 16:31:10.839353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 16:31:10.839438 ==
4582 16:31:10.842458 Write leveling (Byte 0): 28 => 28
4583 16:31:10.845899 Write leveling (Byte 1): 28 => 28
4584 16:31:10.849134 DramcWriteLeveling(PI) end<-----
4585 16:31:10.849256
4586 16:31:10.849358 ==
4587 16:31:10.852711 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 16:31:10.855969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 16:31:10.856053 ==
4590 16:31:10.859367 [Gating] SW mode calibration
4591 16:31:10.865612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4592 16:31:10.869310 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4593 16:31:10.875713 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 16:31:10.879036 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 16:31:10.882289 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
4596 16:31:10.889293 0 9 12 | B1->B0 | 2a2a 3131 | 0 1 | (0 0) (1 1)
4597 16:31:10.892435 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4598 16:31:10.895742 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 16:31:10.902523 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 16:31:10.905803 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 16:31:10.909115 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 16:31:10.915648 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 16:31:10.918956 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4604 16:31:10.922516 0 10 12 | B1->B0 | 3939 2a2a | 0 0 | (0 0) (0 0)
4605 16:31:10.929050 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 16:31:10.932335 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 16:31:10.935638 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 16:31:10.942245 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 16:31:10.945631 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 16:31:10.948934 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 16:31:10.955740 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4612 16:31:10.959139 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 16:31:10.962349 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 16:31:10.968796 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 16:31:10.971904 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 16:31:10.975667 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 16:31:10.982241 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 16:31:10.985489 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 16:31:10.988673 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 16:31:10.995278 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 16:31:10.999121 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 16:31:11.002383 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 16:31:11.005450 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 16:31:11.012493 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 16:31:11.015738 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 16:31:11.019032 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 16:31:11.025498 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 16:31:11.028465 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4629 16:31:11.032126 Total UI for P1: 0, mck2ui 16
4630 16:31:11.035389 best dqsien dly found for B1: ( 0, 13, 10)
4631 16:31:11.038480 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 16:31:11.042053 Total UI for P1: 0, mck2ui 16
4633 16:31:11.045207 best dqsien dly found for B0: ( 0, 13, 12)
4634 16:31:11.048691 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4635 16:31:11.051828 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4636 16:31:11.055388
4637 16:31:11.058425 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4638 16:31:11.061680 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4639 16:31:11.065026 [Gating] SW calibration Done
4640 16:31:11.065120 ==
4641 16:31:11.068336 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 16:31:11.071968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 16:31:11.072085 ==
4644 16:31:11.072187 RX Vref Scan: 0
4645 16:31:11.075189
4646 16:31:11.075272 RX Vref 0 -> 0, step: 1
4647 16:31:11.075338
4648 16:31:11.078798 RX Delay -230 -> 252, step: 16
4649 16:31:11.082036 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4650 16:31:11.085363 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4651 16:31:11.091735 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4652 16:31:11.095117 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4653 16:31:11.098419 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4654 16:31:11.101565 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4655 16:31:11.108487 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4656 16:31:11.111493 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4657 16:31:11.115009 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4658 16:31:11.118188 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4659 16:31:11.121421 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4660 16:31:11.128004 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4661 16:31:11.131716 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4662 16:31:11.134766 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4663 16:31:11.138318 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4664 16:31:11.144605 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4665 16:31:11.144689 ==
4666 16:31:11.148324 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 16:31:11.151453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 16:31:11.151539 ==
4669 16:31:11.151606 DQS Delay:
4670 16:31:11.155034 DQS0 = 0, DQS1 = 0
4671 16:31:11.155126 DQM Delay:
4672 16:31:11.158539 DQM0 = 51, DQM1 = 44
4673 16:31:11.158623 DQ Delay:
4674 16:31:11.161699 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4675 16:31:11.164962 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4676 16:31:11.168157 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4677 16:31:11.171420 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4678 16:31:11.171504
4679 16:31:11.171570
4680 16:31:11.171631 ==
4681 16:31:11.174696 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 16:31:11.178345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 16:31:11.178428 ==
4684 16:31:11.181438
4685 16:31:11.181520
4686 16:31:11.181585 TX Vref Scan disable
4687 16:31:11.184682 == TX Byte 0 ==
4688 16:31:11.188026 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4689 16:31:11.191234 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4690 16:31:11.194877 == TX Byte 1 ==
4691 16:31:11.198098 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4692 16:31:11.201739 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4693 16:31:11.201822 ==
4694 16:31:11.205008 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 16:31:11.211524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 16:31:11.211618 ==
4697 16:31:11.211684
4698 16:31:11.211746
4699 16:31:11.211805 TX Vref Scan disable
4700 16:31:11.216122 == TX Byte 0 ==
4701 16:31:11.219342 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4702 16:31:11.225827 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4703 16:31:11.225912 == TX Byte 1 ==
4704 16:31:11.229554 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4705 16:31:11.236004 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4706 16:31:11.236112
4707 16:31:11.236207 [DATLAT]
4708 16:31:11.236305 Freq=600, CH1 RK1
4709 16:31:11.236401
4710 16:31:11.239259 DATLAT Default: 0x9
4711 16:31:11.239358 0, 0xFFFF, sum = 0
4712 16:31:11.242875 1, 0xFFFF, sum = 0
4713 16:31:11.242950 2, 0xFFFF, sum = 0
4714 16:31:11.246014 3, 0xFFFF, sum = 0
4715 16:31:11.246120 4, 0xFFFF, sum = 0
4716 16:31:11.249159 5, 0xFFFF, sum = 0
4717 16:31:11.252965 6, 0xFFFF, sum = 0
4718 16:31:11.253069 7, 0xFFFF, sum = 0
4719 16:31:11.253165 8, 0x0, sum = 1
4720 16:31:11.256051 9, 0x0, sum = 2
4721 16:31:11.256120 10, 0x0, sum = 3
4722 16:31:11.259079 11, 0x0, sum = 4
4723 16:31:11.259191 best_step = 9
4724 16:31:11.259284
4725 16:31:11.259375 ==
4726 16:31:11.262612 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 16:31:11.268987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 16:31:11.269110 ==
4729 16:31:11.269209 RX Vref Scan: 0
4730 16:31:11.269304
4731 16:31:11.272649 RX Vref 0 -> 0, step: 1
4732 16:31:11.272728
4733 16:31:11.275833 RX Delay -179 -> 252, step: 8
4734 16:31:11.279066 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4735 16:31:11.285442 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4736 16:31:11.289233 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4737 16:31:11.292484 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4738 16:31:11.295848 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4739 16:31:11.299156 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4740 16:31:11.305558 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4741 16:31:11.308918 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4742 16:31:11.312102 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4743 16:31:11.315361 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4744 16:31:11.319008 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4745 16:31:11.325575 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4746 16:31:11.329003 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4747 16:31:11.332184 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4748 16:31:11.335399 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4749 16:31:11.342382 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4750 16:31:11.342500 ==
4751 16:31:11.345629 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 16:31:11.348763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 16:31:11.348876 ==
4754 16:31:11.348989 DQS Delay:
4755 16:31:11.352389 DQS0 = 0, DQS1 = 0
4756 16:31:11.352499 DQM Delay:
4757 16:31:11.355361 DQM0 = 49, DQM1 = 44
4758 16:31:11.355438 DQ Delay:
4759 16:31:11.359078 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4760 16:31:11.362162 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4761 16:31:11.365677 DQ8 =28, DQ9 =32, DQ10 =44, DQ11 =40
4762 16:31:11.368589 DQ12 =56, DQ13 =52, DQ14 =48, DQ15 =56
4763 16:31:11.368672
4764 16:31:11.368737
4765 16:31:11.375583 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4766 16:31:11.378768 CH1 RK1: MR19=808, MR18=5B23
4767 16:31:11.385204 CH1_RK1: MR19=0x808, MR18=0x5B23, DQSOSC=392, MR23=63, INC=170, DEC=113
4768 16:31:11.388757 [RxdqsGatingPostProcess] freq 600
4769 16:31:11.395179 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4770 16:31:11.398289 Pre-setting of DQS Precalculation
4771 16:31:11.402070 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4772 16:31:11.408495 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4773 16:31:11.414963 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4774 16:31:11.415069
4775 16:31:11.415161
4776 16:31:11.418159 [Calibration Summary] 1200 Mbps
4777 16:31:11.421365 CH 0, Rank 0
4778 16:31:11.421440 SW Impedance : PASS
4779 16:31:11.425052 DUTY Scan : NO K
4780 16:31:11.428387 ZQ Calibration : PASS
4781 16:31:11.428487 Jitter Meter : NO K
4782 16:31:11.431693 CBT Training : PASS
4783 16:31:11.434834 Write leveling : PASS
4784 16:31:11.434937 RX DQS gating : PASS
4785 16:31:11.438040 RX DQ/DQS(RDDQC) : PASS
4786 16:31:11.441841 TX DQ/DQS : PASS
4787 16:31:11.441947 RX DATLAT : PASS
4788 16:31:11.445189 RX DQ/DQS(Engine): PASS
4789 16:31:11.445266 TX OE : NO K
4790 16:31:11.448005 All Pass.
4791 16:31:11.448104
4792 16:31:11.448196 CH 0, Rank 1
4793 16:31:11.451320 SW Impedance : PASS
4794 16:31:11.451421 DUTY Scan : NO K
4795 16:31:11.454565 ZQ Calibration : PASS
4796 16:31:11.457957 Jitter Meter : NO K
4797 16:31:11.458065 CBT Training : PASS
4798 16:31:11.461490 Write leveling : PASS
4799 16:31:11.464421 RX DQS gating : PASS
4800 16:31:11.464532 RX DQ/DQS(RDDQC) : PASS
4801 16:31:11.467665 TX DQ/DQS : PASS
4802 16:31:11.471172 RX DATLAT : PASS
4803 16:31:11.471299 RX DQ/DQS(Engine): PASS
4804 16:31:11.474538 TX OE : NO K
4805 16:31:11.474661 All Pass.
4806 16:31:11.474773
4807 16:31:11.477869 CH 1, Rank 0
4808 16:31:11.477975 SW Impedance : PASS
4809 16:31:11.481436 DUTY Scan : NO K
4810 16:31:11.484597 ZQ Calibration : PASS
4811 16:31:11.484673 Jitter Meter : NO K
4812 16:31:11.487789 CBT Training : PASS
4813 16:31:11.491033 Write leveling : PASS
4814 16:31:11.491136 RX DQS gating : PASS
4815 16:31:11.494682 RX DQ/DQS(RDDQC) : PASS
4816 16:31:11.497550 TX DQ/DQS : PASS
4817 16:31:11.497648 RX DATLAT : PASS
4818 16:31:11.501263 RX DQ/DQS(Engine): PASS
4819 16:31:11.501425 TX OE : NO K
4820 16:31:11.504475 All Pass.
4821 16:31:11.504600
4822 16:31:11.504668 CH 1, Rank 1
4823 16:31:11.507770 SW Impedance : PASS
4824 16:31:11.507870 DUTY Scan : NO K
4825 16:31:11.511044 ZQ Calibration : PASS
4826 16:31:11.514222 Jitter Meter : NO K
4827 16:31:11.514305 CBT Training : PASS
4828 16:31:11.517541 Write leveling : PASS
4829 16:31:11.520818 RX DQS gating : PASS
4830 16:31:11.520900 RX DQ/DQS(RDDQC) : PASS
4831 16:31:11.524473 TX DQ/DQS : PASS
4832 16:31:11.527627 RX DATLAT : PASS
4833 16:31:11.527712 RX DQ/DQS(Engine): PASS
4834 16:31:11.530909 TX OE : NO K
4835 16:31:11.530985 All Pass.
4836 16:31:11.531048
4837 16:31:11.534228 DramC Write-DBI off
4838 16:31:11.537399 PER_BANK_REFRESH: Hybrid Mode
4839 16:31:11.537478 TX_TRACKING: ON
4840 16:31:11.547475 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4841 16:31:11.550874 [FAST_K] Save calibration result to emmc
4842 16:31:11.554177 dramc_set_vcore_voltage set vcore to 662500
4843 16:31:11.557380 Read voltage for 933, 3
4844 16:31:11.557463 Vio18 = 0
4845 16:31:11.557529 Vcore = 662500
4846 16:31:11.560677 Vdram = 0
4847 16:31:11.560760 Vddq = 0
4848 16:31:11.560826 Vmddr = 0
4849 16:31:11.567376 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4850 16:31:11.570372 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4851 16:31:11.573782 MEM_TYPE=3, freq_sel=17
4852 16:31:11.577288 sv_algorithm_assistance_LP4_1600
4853 16:31:11.580406 ============ PULL DRAM RESETB DOWN ============
4854 16:31:11.584096 ========== PULL DRAM RESETB DOWN end =========
4855 16:31:11.590399 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4856 16:31:11.594196 ===================================
4857 16:31:11.594292 LPDDR4 DRAM CONFIGURATION
4858 16:31:11.597414 ===================================
4859 16:31:11.600555 EX_ROW_EN[0] = 0x0
4860 16:31:11.604195 EX_ROW_EN[1] = 0x0
4861 16:31:11.604279 LP4Y_EN = 0x0
4862 16:31:11.607500 WORK_FSP = 0x0
4863 16:31:11.607582 WL = 0x3
4864 16:31:11.610606 RL = 0x3
4865 16:31:11.610688 BL = 0x2
4866 16:31:11.613902 RPST = 0x0
4867 16:31:11.613981 RD_PRE = 0x0
4868 16:31:11.617596 WR_PRE = 0x1
4869 16:31:11.617695 WR_PST = 0x0
4870 16:31:11.620391 DBI_WR = 0x0
4871 16:31:11.620479 DBI_RD = 0x0
4872 16:31:11.623756 OTF = 0x1
4873 16:31:11.627049 ===================================
4874 16:31:11.630755 ===================================
4875 16:31:11.630837 ANA top config
4876 16:31:11.634045 ===================================
4877 16:31:11.637324 DLL_ASYNC_EN = 0
4878 16:31:11.640462 ALL_SLAVE_EN = 1
4879 16:31:11.643678 NEW_RANK_MODE = 1
4880 16:31:11.643778 DLL_IDLE_MODE = 1
4881 16:31:11.647377 LP45_APHY_COMB_EN = 1
4882 16:31:11.650617 TX_ODT_DIS = 1
4883 16:31:11.653983 NEW_8X_MODE = 1
4884 16:31:11.657176 ===================================
4885 16:31:11.660474 ===================================
4886 16:31:11.663647 data_rate = 1866
4887 16:31:11.663726 CKR = 1
4888 16:31:11.667323 DQ_P2S_RATIO = 8
4889 16:31:11.670425 ===================================
4890 16:31:11.674120 CA_P2S_RATIO = 8
4891 16:31:11.677092 DQ_CA_OPEN = 0
4892 16:31:11.680397 DQ_SEMI_OPEN = 0
4893 16:31:11.683994 CA_SEMI_OPEN = 0
4894 16:31:11.684071 CA_FULL_RATE = 0
4895 16:31:11.687028 DQ_CKDIV4_EN = 1
4896 16:31:11.690273 CA_CKDIV4_EN = 1
4897 16:31:11.693946 CA_PREDIV_EN = 0
4898 16:31:11.697187 PH8_DLY = 0
4899 16:31:11.700285 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4900 16:31:11.700359 DQ_AAMCK_DIV = 4
4901 16:31:11.703418 CA_AAMCK_DIV = 4
4902 16:31:11.707063 CA_ADMCK_DIV = 4
4903 16:31:11.710257 DQ_TRACK_CA_EN = 0
4904 16:31:11.713391 CA_PICK = 933
4905 16:31:11.716650 CA_MCKIO = 933
4906 16:31:11.716729 MCKIO_SEMI = 0
4907 16:31:11.719953 PLL_FREQ = 3732
4908 16:31:11.723708 DQ_UI_PI_RATIO = 32
4909 16:31:11.726992 CA_UI_PI_RATIO = 0
4910 16:31:11.730229 ===================================
4911 16:31:11.733432 ===================================
4912 16:31:11.736601 memory_type:LPDDR4
4913 16:31:11.736718 GP_NUM : 10
4914 16:31:11.740378 SRAM_EN : 1
4915 16:31:11.743599 MD32_EN : 0
4916 16:31:11.746833 ===================================
4917 16:31:11.746914 [ANA_INIT] >>>>>>>>>>>>>>
4918 16:31:11.750081 <<<<<< [CONFIGURE PHASE]: ANA_TX
4919 16:31:11.753418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4920 16:31:11.756736 ===================================
4921 16:31:11.759945 data_rate = 1866,PCW = 0X8f00
4922 16:31:11.763155 ===================================
4923 16:31:11.766432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4924 16:31:11.773517 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 16:31:11.776710 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 16:31:11.783047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4927 16:31:11.786589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4928 16:31:11.790036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4929 16:31:11.790111 [ANA_INIT] flow start
4930 16:31:11.792968 [ANA_INIT] PLL >>>>>>>>
4931 16:31:11.796447 [ANA_INIT] PLL <<<<<<<<
4932 16:31:11.799647 [ANA_INIT] MIDPI >>>>>>>>
4933 16:31:11.799748 [ANA_INIT] MIDPI <<<<<<<<
4934 16:31:11.803326 [ANA_INIT] DLL >>>>>>>>
4935 16:31:11.803424 [ANA_INIT] flow end
4936 16:31:11.809909 ============ LP4 DIFF to SE enter ============
4937 16:31:11.813231 ============ LP4 DIFF to SE exit ============
4938 16:31:11.816400 [ANA_INIT] <<<<<<<<<<<<<
4939 16:31:11.819694 [Flow] Enable top DCM control >>>>>
4940 16:31:11.823575 [Flow] Enable top DCM control <<<<<
4941 16:31:11.826812 Enable DLL master slave shuffle
4942 16:31:11.830129 ==============================================================
4943 16:31:11.833424 Gating Mode config
4944 16:31:11.836555 ==============================================================
4945 16:31:11.840223 Config description:
4946 16:31:11.849869 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4947 16:31:11.856960 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4948 16:31:11.860060 SELPH_MODE 0: By rank 1: By Phase
4949 16:31:11.866584 ==============================================================
4950 16:31:11.869867 GAT_TRACK_EN = 1
4951 16:31:11.873430 RX_GATING_MODE = 2
4952 16:31:11.876567 RX_GATING_TRACK_MODE = 2
4953 16:31:11.879750 SELPH_MODE = 1
4954 16:31:11.879823 PICG_EARLY_EN = 1
4955 16:31:11.883514 VALID_LAT_VALUE = 1
4956 16:31:11.889889 ==============================================================
4957 16:31:11.893002 Enter into Gating configuration >>>>
4958 16:31:11.896533 Exit from Gating configuration <<<<
4959 16:31:11.900290 Enter into DVFS_PRE_config >>>>>
4960 16:31:11.909949 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4961 16:31:11.917850 Exit from DVFS_PRE_config <<<<<
4962 16:31:11.917963 Enter into PICG configuration >>>>
4963 16:31:11.919559 Exit from PICG configuration <<<<
4964 16:31:11.923282 [RX_INPUT] configuration >>>>>
4965 16:31:11.926570 [RX_INPUT] configuration <<<<<
4966 16:31:11.929811 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4967 16:31:11.936188 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4968 16:31:11.943017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4969 16:31:11.949477 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4970 16:31:11.955902 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 16:31:11.962478 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 16:31:11.965860 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4973 16:31:11.969510 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4974 16:31:11.972801 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4975 16:31:11.975960 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4976 16:31:11.982964 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4977 16:31:11.986161 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4978 16:31:11.989263 ===================================
4979 16:31:11.992713 LPDDR4 DRAM CONFIGURATION
4980 16:31:11.995803 ===================================
4981 16:31:11.995888 EX_ROW_EN[0] = 0x0
4982 16:31:11.999457 EX_ROW_EN[1] = 0x0
4983 16:31:11.999541 LP4Y_EN = 0x0
4984 16:31:12.002557 WORK_FSP = 0x0
4985 16:31:12.002639 WL = 0x3
4986 16:31:12.005994 RL = 0x3
4987 16:31:12.009100 BL = 0x2
4988 16:31:12.009182 RPST = 0x0
4989 16:31:12.012209 RD_PRE = 0x0
4990 16:31:12.012290 WR_PRE = 0x1
4991 16:31:12.015887 WR_PST = 0x0
4992 16:31:12.015968 DBI_WR = 0x0
4993 16:31:12.018928 DBI_RD = 0x0
4994 16:31:12.019023 OTF = 0x1
4995 16:31:12.022605 ===================================
4996 16:31:12.025766 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4997 16:31:12.032314 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4998 16:31:12.035617 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4999 16:31:12.038938 ===================================
5000 16:31:12.042608 LPDDR4 DRAM CONFIGURATION
5001 16:31:12.045880 ===================================
5002 16:31:12.045984 EX_ROW_EN[0] = 0x10
5003 16:31:12.048915 EX_ROW_EN[1] = 0x0
5004 16:31:12.049019 LP4Y_EN = 0x0
5005 16:31:12.052259 WORK_FSP = 0x0
5006 16:31:12.052359 WL = 0x3
5007 16:31:12.055539 RL = 0x3
5008 16:31:12.055645 BL = 0x2
5009 16:31:12.058745 RPST = 0x0
5010 16:31:12.058854 RD_PRE = 0x0
5011 16:31:12.062010 WR_PRE = 0x1
5012 16:31:12.065326 WR_PST = 0x0
5013 16:31:12.065401 DBI_WR = 0x0
5014 16:31:12.068430 DBI_RD = 0x0
5015 16:31:12.068543 OTF = 0x1
5016 16:31:12.072204 ===================================
5017 16:31:12.078779 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5018 16:31:12.082144 nWR fixed to 30
5019 16:31:12.085363 [ModeRegInit_LP4] CH0 RK0
5020 16:31:12.085459 [ModeRegInit_LP4] CH0 RK1
5021 16:31:12.088734 [ModeRegInit_LP4] CH1 RK0
5022 16:31:12.091933 [ModeRegInit_LP4] CH1 RK1
5023 16:31:12.092006 match AC timing 9
5024 16:31:12.098689 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5025 16:31:12.102187 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5026 16:31:12.105406 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5027 16:31:12.112039 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5028 16:31:12.115424 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5029 16:31:12.115507 ==
5030 16:31:12.118898 Dram Type= 6, Freq= 0, CH_0, rank 0
5031 16:31:12.122282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5032 16:31:12.122360 ==
5033 16:31:12.128541 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5034 16:31:12.135107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5035 16:31:12.138896 [CA 0] Center 38 (8~69) winsize 62
5036 16:31:12.141702 [CA 1] Center 38 (8~69) winsize 62
5037 16:31:12.145073 [CA 2] Center 35 (5~66) winsize 62
5038 16:31:12.148451 [CA 3] Center 35 (4~66) winsize 63
5039 16:31:12.152118 [CA 4] Center 34 (4~65) winsize 62
5040 16:31:12.154956 [CA 5] Center 33 (3~64) winsize 62
5041 16:31:12.155070
5042 16:31:12.158542 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5043 16:31:12.158656
5044 16:31:12.161883 [CATrainingPosCal] consider 1 rank data
5045 16:31:12.165093 u2DelayCellTimex100 = 270/100 ps
5046 16:31:12.168850 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5047 16:31:12.172077 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5048 16:31:12.175298 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5049 16:31:12.178477 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5050 16:31:12.181764 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5051 16:31:12.185577 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5052 16:31:12.188789
5053 16:31:12.191948 CA PerBit enable=1, Macro0, CA PI delay=33
5054 16:31:12.192032
5055 16:31:12.195224 [CBTSetCACLKResult] CA Dly = 33
5056 16:31:12.195308 CS Dly: 7 (0~38)
5057 16:31:12.195396 ==
5058 16:31:12.198910 Dram Type= 6, Freq= 0, CH_0, rank 1
5059 16:31:12.202079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5060 16:31:12.202164 ==
5061 16:31:12.208702 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5062 16:31:12.215243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5063 16:31:12.218691 [CA 0] Center 38 (8~69) winsize 62
5064 16:31:12.221741 [CA 1] Center 38 (8~69) winsize 62
5065 16:31:12.225080 [CA 2] Center 36 (6~66) winsize 61
5066 16:31:12.228407 [CA 3] Center 35 (5~66) winsize 62
5067 16:31:12.231941 [CA 4] Center 35 (4~66) winsize 63
5068 16:31:12.234951 [CA 5] Center 34 (4~65) winsize 62
5069 16:31:12.235035
5070 16:31:12.238225 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5071 16:31:12.238310
5072 16:31:12.242023 [CATrainingPosCal] consider 2 rank data
5073 16:31:12.245287 u2DelayCellTimex100 = 270/100 ps
5074 16:31:12.248530 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5075 16:31:12.251774 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5076 16:31:12.254904 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5077 16:31:12.258433 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5078 16:31:12.262087 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5079 16:31:12.268577 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5080 16:31:12.268693
5081 16:31:12.271916 CA PerBit enable=1, Macro0, CA PI delay=34
5082 16:31:12.272024
5083 16:31:12.275107 [CBTSetCACLKResult] CA Dly = 34
5084 16:31:12.275208 CS Dly: 7 (0~39)
5085 16:31:12.275300
5086 16:31:12.278452 ----->DramcWriteLeveling(PI) begin...
5087 16:31:12.278560 ==
5088 16:31:12.282003 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 16:31:12.285248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 16:31:12.288477 ==
5091 16:31:12.288609 Write leveling (Byte 0): 30 => 30
5092 16:31:12.291795 Write leveling (Byte 1): 29 => 29
5093 16:31:12.294971 DramcWriteLeveling(PI) end<-----
5094 16:31:12.295056
5095 16:31:12.295122 ==
5096 16:31:12.298171 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 16:31:12.305211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 16:31:12.305294 ==
5099 16:31:12.308457 [Gating] SW mode calibration
5100 16:31:12.314878 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5101 16:31:12.318106 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5102 16:31:12.324808 0 14 0 | B1->B0 | 2f2e 3434 | 1 1 | (1 0) (1 1)
5103 16:31:12.328209 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 16:31:12.331205 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 16:31:12.337851 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 16:31:12.341475 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 16:31:12.344670 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 16:31:12.351305 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5109 16:31:12.354661 0 14 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
5110 16:31:12.358192 0 15 0 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)
5111 16:31:12.361231 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 16:31:12.368075 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 16:31:12.371315 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 16:31:12.375039 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 16:31:12.381487 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 16:31:12.384623 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5117 16:31:12.387880 0 15 28 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
5118 16:31:12.394914 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5119 16:31:12.397990 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 16:31:12.401111 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 16:31:12.408169 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 16:31:12.411384 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 16:31:12.414547 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 16:31:12.421051 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5125 16:31:12.424659 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5126 16:31:12.427745 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 16:31:12.434481 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 16:31:12.437982 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 16:31:12.441339 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 16:31:12.447879 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 16:31:12.451183 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 16:31:12.454469 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 16:31:12.461194 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 16:31:12.464703 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 16:31:12.468170 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 16:31:12.474673 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 16:31:12.477932 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 16:31:12.481217 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 16:31:12.485032 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 16:31:12.491095 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5141 16:31:12.494451 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5142 16:31:12.498181 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 16:31:12.501386 Total UI for P1: 0, mck2ui 16
5144 16:31:12.504675 best dqsien dly found for B0: ( 1, 2, 26)
5145 16:31:12.507956 Total UI for P1: 0, mck2ui 16
5146 16:31:12.511009 best dqsien dly found for B1: ( 1, 2, 28)
5147 16:31:12.514508 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5148 16:31:12.517645 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5149 16:31:12.517728
5150 16:31:12.524780 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5151 16:31:12.527981 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5152 16:31:12.531209 [Gating] SW calibration Done
5153 16:31:12.531350 ==
5154 16:31:12.534467 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 16:31:12.537981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 16:31:12.538065 ==
5157 16:31:12.538130 RX Vref Scan: 0
5158 16:31:12.538190
5159 16:31:12.540901 RX Vref 0 -> 0, step: 1
5160 16:31:12.540986
5161 16:31:12.544374 RX Delay -80 -> 252, step: 8
5162 16:31:12.547948 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5163 16:31:12.550984 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5164 16:31:12.557443 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5165 16:31:12.561149 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5166 16:31:12.564424 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5167 16:31:12.567541 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5168 16:31:12.570711 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5169 16:31:12.574417 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5170 16:31:12.581060 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5171 16:31:12.584306 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5172 16:31:12.587485 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5173 16:31:12.590766 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5174 16:31:12.594108 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5175 16:31:12.597402 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5176 16:31:12.604301 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5177 16:31:12.607510 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5178 16:31:12.607587 ==
5179 16:31:12.610827 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 16:31:12.614086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 16:31:12.614165 ==
5182 16:31:12.614231 DQS Delay:
5183 16:31:12.617284 DQS0 = 0, DQS1 = 0
5184 16:31:12.617360 DQM Delay:
5185 16:31:12.620465 DQM0 = 105, DQM1 = 90
5186 16:31:12.620591 DQ Delay:
5187 16:31:12.623823 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5188 16:31:12.627488 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5189 16:31:12.630852 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =87
5190 16:31:12.634051 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5191 16:31:12.634166
5192 16:31:12.634268
5193 16:31:12.634377 ==
5194 16:31:12.637281 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 16:31:12.643726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 16:31:12.643811 ==
5197 16:31:12.643876
5198 16:31:12.643936
5199 16:31:12.643993 TX Vref Scan disable
5200 16:31:12.647749 == TX Byte 0 ==
5201 16:31:12.650615 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5202 16:31:12.657426 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5203 16:31:12.657513 == TX Byte 1 ==
5204 16:31:12.660874 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5205 16:31:12.664241 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5206 16:31:12.667431 ==
5207 16:31:12.671027 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 16:31:12.674074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 16:31:12.674181 ==
5210 16:31:12.674279
5211 16:31:12.674355
5212 16:31:12.677725 TX Vref Scan disable
5213 16:31:12.677825 == TX Byte 0 ==
5214 16:31:12.684268 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5215 16:31:12.687488 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5216 16:31:12.687573 == TX Byte 1 ==
5217 16:31:12.693868 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5218 16:31:12.697135 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5219 16:31:12.697218
5220 16:31:12.697281 [DATLAT]
5221 16:31:12.700456 Freq=933, CH0 RK0
5222 16:31:12.700539
5223 16:31:12.700642 DATLAT Default: 0xd
5224 16:31:12.704216 0, 0xFFFF, sum = 0
5225 16:31:12.704299 1, 0xFFFF, sum = 0
5226 16:31:12.707548 2, 0xFFFF, sum = 0
5227 16:31:12.707647 3, 0xFFFF, sum = 0
5228 16:31:12.710730 4, 0xFFFF, sum = 0
5229 16:31:12.710814 5, 0xFFFF, sum = 0
5230 16:31:12.714023 6, 0xFFFF, sum = 0
5231 16:31:12.717288 7, 0xFFFF, sum = 0
5232 16:31:12.717372 8, 0xFFFF, sum = 0
5233 16:31:12.720389 9, 0xFFFF, sum = 0
5234 16:31:12.720499 10, 0x0, sum = 1
5235 16:31:12.720621 11, 0x0, sum = 2
5236 16:31:12.723672 12, 0x0, sum = 3
5237 16:31:12.723756 13, 0x0, sum = 4
5238 16:31:12.727001 best_step = 11
5239 16:31:12.727084
5240 16:31:12.727149 ==
5241 16:31:12.730766 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 16:31:12.733921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 16:31:12.734005 ==
5244 16:31:12.737136 RX Vref Scan: 1
5245 16:31:12.737219
5246 16:31:12.737289 RX Vref 0 -> 0, step: 1
5247 16:31:12.737369
5248 16:31:12.740459 RX Delay -53 -> 252, step: 4
5249 16:31:12.740602
5250 16:31:12.743790 Set Vref, RX VrefLevel [Byte0]: 57
5251 16:31:12.746901 [Byte1]: 49
5252 16:31:12.751584
5253 16:31:12.751669 Final RX Vref Byte 0 = 57 to rank0
5254 16:31:12.754699 Final RX Vref Byte 1 = 49 to rank0
5255 16:31:12.758174 Final RX Vref Byte 0 = 57 to rank1
5256 16:31:12.761295 Final RX Vref Byte 1 = 49 to rank1==
5257 16:31:12.764874 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 16:31:12.771344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 16:31:12.771486 ==
5260 16:31:12.771625 DQS Delay:
5261 16:31:12.771716 DQS0 = 0, DQS1 = 0
5262 16:31:12.774517 DQM Delay:
5263 16:31:12.774602 DQM0 = 107, DQM1 = 91
5264 16:31:12.778059 DQ Delay:
5265 16:31:12.781137 DQ0 =108, DQ1 =106, DQ2 =102, DQ3 =106
5266 16:31:12.784310 DQ4 =108, DQ5 =98, DQ6 =114, DQ7 =114
5267 16:31:12.787742 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5268 16:31:12.790964 DQ12 =94, DQ13 =94, DQ14 =102, DQ15 =98
5269 16:31:12.791049
5270 16:31:12.791117
5271 16:31:12.797958 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5272 16:31:12.801086 CH0 RK0: MR19=505, MR18=2824
5273 16:31:12.807547 CH0_RK0: MR19=0x505, MR18=0x2824, DQSOSC=409, MR23=63, INC=64, DEC=43
5274 16:31:12.807624
5275 16:31:12.810887 ----->DramcWriteLeveling(PI) begin...
5276 16:31:12.810972 ==
5277 16:31:12.814674 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 16:31:12.817706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 16:31:12.817791 ==
5280 16:31:12.820927 Write leveling (Byte 0): 30 => 30
5281 16:31:12.824478 Write leveling (Byte 1): 29 => 29
5282 16:31:12.827357 DramcWriteLeveling(PI) end<-----
5283 16:31:12.827440
5284 16:31:12.827504 ==
5285 16:31:12.830612 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 16:31:12.837581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 16:31:12.837665 ==
5288 16:31:12.837730 [Gating] SW mode calibration
5289 16:31:12.847402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 16:31:12.851104 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 16:31:12.854166 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 16:31:12.861018 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 16:31:12.864155 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 16:31:12.867521 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 16:31:12.874601 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 16:31:12.878022 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 16:31:12.880905 0 14 24 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 1)
5298 16:31:12.887600 0 14 28 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (1 0)
5299 16:31:12.890784 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 16:31:12.894542 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 16:31:12.901076 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 16:31:12.904324 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 16:31:12.907595 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 16:31:12.914239 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 16:31:12.917500 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5306 16:31:12.920860 0 15 28 | B1->B0 | 3838 3d3d | 0 0 | (0 0) (1 1)
5307 16:31:12.927390 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 16:31:12.930723 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 16:31:12.934044 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 16:31:12.940476 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 16:31:12.943722 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 16:31:12.947026 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 16:31:12.954013 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 16:31:12.957144 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5315 16:31:12.960756 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 16:31:12.963989 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 16:31:12.970353 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 16:31:12.973800 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 16:31:12.980383 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 16:31:12.983369 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 16:31:12.986609 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 16:31:12.990134 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 16:31:12.996896 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 16:31:13.000453 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 16:31:13.003795 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 16:31:13.010039 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 16:31:13.013280 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 16:31:13.016964 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 16:31:13.023638 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 16:31:13.026951 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 16:31:13.030106 Total UI for P1: 0, mck2ui 16
5332 16:31:13.033835 best dqsien dly found for B0: ( 1, 2, 26)
5333 16:31:13.037134 Total UI for P1: 0, mck2ui 16
5334 16:31:13.039890 best dqsien dly found for B1: ( 1, 2, 26)
5335 16:31:13.043089 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5336 16:31:13.046913 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5337 16:31:13.047019
5338 16:31:13.050200 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5339 16:31:13.053371 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5340 16:31:13.056524 [Gating] SW calibration Done
5341 16:31:13.056696 ==
5342 16:31:13.059697 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 16:31:13.066509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 16:31:13.066630 ==
5345 16:31:13.066735 RX Vref Scan: 0
5346 16:31:13.066833
5347 16:31:13.069716 RX Vref 0 -> 0, step: 1
5348 16:31:13.069814
5349 16:31:13.072996 RX Delay -80 -> 252, step: 8
5350 16:31:13.076647 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5351 16:31:13.079677 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5352 16:31:13.083018 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5353 16:31:13.086593 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5354 16:31:13.089940 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5355 16:31:13.096439 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5356 16:31:13.100067 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5357 16:31:13.103033 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5358 16:31:13.106536 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5359 16:31:13.109814 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5360 16:31:13.113046 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5361 16:31:13.119568 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5362 16:31:13.122964 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5363 16:31:13.126316 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5364 16:31:13.129425 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5365 16:31:13.133165 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5366 16:31:13.133250 ==
5367 16:31:13.136436 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 16:31:13.142914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 16:31:13.143022 ==
5370 16:31:13.143115 DQS Delay:
5371 16:31:13.146192 DQS0 = 0, DQS1 = 0
5372 16:31:13.146266 DQM Delay:
5373 16:31:13.149458 DQM0 = 104, DQM1 = 90
5374 16:31:13.149531 DQ Delay:
5375 16:31:13.152703 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5376 16:31:13.155970 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5377 16:31:13.159683 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5378 16:31:13.162982 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5379 16:31:13.163064
5380 16:31:13.163156
5381 16:31:13.163247 ==
5382 16:31:13.166093 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 16:31:13.169235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 16:31:13.169338 ==
5385 16:31:13.169428
5386 16:31:13.169594
5387 16:31:13.172504 TX Vref Scan disable
5388 16:31:13.175883 == TX Byte 0 ==
5389 16:31:13.179254 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5390 16:31:13.182523 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5391 16:31:13.186095 == TX Byte 1 ==
5392 16:31:13.189202 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5393 16:31:13.192345 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5394 16:31:13.192450 ==
5395 16:31:13.195863 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 16:31:13.202446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 16:31:13.202535 ==
5398 16:31:13.202600
5399 16:31:13.202660
5400 16:31:13.202717 TX Vref Scan disable
5401 16:31:13.206503 == TX Byte 0 ==
5402 16:31:13.209592 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5403 16:31:13.216582 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5404 16:31:13.216679 == TX Byte 1 ==
5405 16:31:13.219971 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5406 16:31:13.226450 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5407 16:31:13.226562
5408 16:31:13.226653 [DATLAT]
5409 16:31:13.226716 Freq=933, CH0 RK1
5410 16:31:13.226776
5411 16:31:13.229595 DATLAT Default: 0xb
5412 16:31:13.229678 0, 0xFFFF, sum = 0
5413 16:31:13.232994 1, 0xFFFF, sum = 0
5414 16:31:13.233079 2, 0xFFFF, sum = 0
5415 16:31:13.236698 3, 0xFFFF, sum = 0
5416 16:31:13.239975 4, 0xFFFF, sum = 0
5417 16:31:13.240076 5, 0xFFFF, sum = 0
5418 16:31:13.243289 6, 0xFFFF, sum = 0
5419 16:31:13.243423 7, 0xFFFF, sum = 0
5420 16:31:13.246553 8, 0xFFFF, sum = 0
5421 16:31:13.246634 9, 0xFFFF, sum = 0
5422 16:31:13.249908 10, 0x0, sum = 1
5423 16:31:13.249981 11, 0x0, sum = 2
5424 16:31:13.250042 12, 0x0, sum = 3
5425 16:31:13.253081 13, 0x0, sum = 4
5426 16:31:13.253152 best_step = 11
5427 16:31:13.253228
5428 16:31:13.256345 ==
5429 16:31:13.256463 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 16:31:13.263434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 16:31:13.263543 ==
5432 16:31:13.263635 RX Vref Scan: 0
5433 16:31:13.263722
5434 16:31:13.266574 RX Vref 0 -> 0, step: 1
5435 16:31:13.266648
5436 16:31:13.269662 RX Delay -53 -> 252, step: 4
5437 16:31:13.273304 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5438 16:31:13.279964 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5439 16:31:13.283176 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5440 16:31:13.286462 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5441 16:31:13.289669 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5442 16:31:13.293095 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5443 16:31:13.296313 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5444 16:31:13.302939 iDelay=199, Bit 7, Center 114 (31 ~ 198) 168
5445 16:31:13.306386 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5446 16:31:13.309802 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5447 16:31:13.312983 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5448 16:31:13.316026 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5449 16:31:13.323043 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5450 16:31:13.326332 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5451 16:31:13.329635 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5452 16:31:13.332941 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5453 16:31:13.333046 ==
5454 16:31:13.336196 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 16:31:13.342809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 16:31:13.342894 ==
5457 16:31:13.342960 DQS Delay:
5458 16:31:13.343021 DQS0 = 0, DQS1 = 0
5459 16:31:13.346051 DQM Delay:
5460 16:31:13.346134 DQM0 = 104, DQM1 = 91
5461 16:31:13.349346 DQ Delay:
5462 16:31:13.352571 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5463 16:31:13.355928 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =114
5464 16:31:13.359167 DQ8 =84, DQ9 =78, DQ10 =94, DQ11 =90
5465 16:31:13.362837 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5466 16:31:13.362943
5467 16:31:13.363050
5468 16:31:13.369384 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5469 16:31:13.372585 CH0 RK1: MR19=505, MR18=2D0D
5470 16:31:13.379003 CH0_RK1: MR19=0x505, MR18=0x2D0D, DQSOSC=407, MR23=63, INC=65, DEC=43
5471 16:31:13.382758 [RxdqsGatingPostProcess] freq 933
5472 16:31:13.386095 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5473 16:31:13.389466 best DQS0 dly(2T, 0.5T) = (0, 10)
5474 16:31:13.392538 best DQS1 dly(2T, 0.5T) = (0, 10)
5475 16:31:13.396037 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5476 16:31:13.399471 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5477 16:31:13.402723 best DQS0 dly(2T, 0.5T) = (0, 10)
5478 16:31:13.405923 best DQS1 dly(2T, 0.5T) = (0, 10)
5479 16:31:13.409523 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5480 16:31:13.412850 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5481 16:31:13.415788 Pre-setting of DQS Precalculation
5482 16:31:13.419555 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5483 16:31:13.419661 ==
5484 16:31:13.422669 Dram Type= 6, Freq= 0, CH_1, rank 0
5485 16:31:13.429391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 16:31:13.429500 ==
5487 16:31:13.432459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5488 16:31:13.438924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5489 16:31:13.442691 [CA 0] Center 37 (7~68) winsize 62
5490 16:31:13.445954 [CA 1] Center 37 (7~68) winsize 62
5491 16:31:13.449114 [CA 2] Center 35 (5~66) winsize 62
5492 16:31:13.452852 [CA 3] Center 35 (5~65) winsize 61
5493 16:31:13.456081 [CA 4] Center 35 (5~65) winsize 61
5494 16:31:13.459431 [CA 5] Center 34 (4~65) winsize 62
5495 16:31:13.459515
5496 16:31:13.462700 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5497 16:31:13.462784
5498 16:31:13.465859 [CATrainingPosCal] consider 1 rank data
5499 16:31:13.469565 u2DelayCellTimex100 = 270/100 ps
5500 16:31:13.472800 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5501 16:31:13.476093 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5502 16:31:13.483052 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5503 16:31:13.485747 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5504 16:31:13.489483 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5505 16:31:13.492721 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5506 16:31:13.492803
5507 16:31:13.495950 CA PerBit enable=1, Macro0, CA PI delay=34
5508 16:31:13.496032
5509 16:31:13.499027 [CBTSetCACLKResult] CA Dly = 34
5510 16:31:13.499110 CS Dly: 6 (0~37)
5511 16:31:13.502887 ==
5512 16:31:13.502970 Dram Type= 6, Freq= 0, CH_1, rank 1
5513 16:31:13.509211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 16:31:13.509294 ==
5515 16:31:13.512795 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 16:31:13.519171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5517 16:31:13.522615 [CA 0] Center 37 (7~68) winsize 62
5518 16:31:13.526178 [CA 1] Center 38 (8~68) winsize 61
5519 16:31:13.529148 [CA 2] Center 36 (6~66) winsize 61
5520 16:31:13.532609 [CA 3] Center 35 (6~65) winsize 60
5521 16:31:13.535774 [CA 4] Center 35 (6~65) winsize 60
5522 16:31:13.539299 [CA 5] Center 35 (5~65) winsize 61
5523 16:31:13.539382
5524 16:31:13.542509 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5525 16:31:13.542591
5526 16:31:13.545843 [CATrainingPosCal] consider 2 rank data
5527 16:31:13.549119 u2DelayCellTimex100 = 270/100 ps
5528 16:31:13.552376 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5529 16:31:13.558984 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5530 16:31:13.562282 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5531 16:31:13.565405 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5532 16:31:13.569097 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
5533 16:31:13.572321 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5534 16:31:13.572409
5535 16:31:13.575484 CA PerBit enable=1, Macro0, CA PI delay=35
5536 16:31:13.575577
5537 16:31:13.578777 [CBTSetCACLKResult] CA Dly = 35
5538 16:31:13.578855 CS Dly: 7 (0~39)
5539 16:31:13.582529
5540 16:31:13.585694 ----->DramcWriteLeveling(PI) begin...
5541 16:31:13.585777 ==
5542 16:31:13.588980 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 16:31:13.592181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 16:31:13.592266 ==
5545 16:31:13.595847 Write leveling (Byte 0): 27 => 27
5546 16:31:13.599088 Write leveling (Byte 1): 28 => 28
5547 16:31:13.602364 DramcWriteLeveling(PI) end<-----
5548 16:31:13.602446
5549 16:31:13.602510 ==
5550 16:31:13.605556 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 16:31:13.608720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 16:31:13.608803 ==
5553 16:31:13.612459 [Gating] SW mode calibration
5554 16:31:13.618836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5555 16:31:13.625405 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5556 16:31:13.628650 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 16:31:13.632183 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 16:31:13.638985 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 16:31:13.642440 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 16:31:13.645312 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 16:31:13.651982 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5562 16:31:13.655172 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 1)
5563 16:31:13.659006 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5564 16:31:13.662217 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 16:31:13.668573 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 16:31:13.671901 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 16:31:13.675488 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 16:31:13.682076 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 16:31:13.685383 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 16:31:13.688579 0 15 24 | B1->B0 | 2626 3030 | 0 0 | (0 0) (0 0)
5571 16:31:13.695503 0 15 28 | B1->B0 | 4040 4443 | 0 1 | (0 0) (0 0)
5572 16:31:13.698730 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 16:31:13.702034 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 16:31:13.708908 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 16:31:13.712263 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 16:31:13.715367 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 16:31:13.721723 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 16:31:13.725402 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5579 16:31:13.728716 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5580 16:31:13.735529 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 16:31:13.738638 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 16:31:13.742213 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 16:31:13.748849 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 16:31:13.751841 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 16:31:13.755513 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 16:31:13.762073 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 16:31:13.765337 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 16:31:13.768422 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 16:31:13.772024 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 16:31:13.778535 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 16:31:13.781844 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 16:31:13.785076 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 16:31:13.791598 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5594 16:31:13.795339 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5595 16:31:13.798551 Total UI for P1: 0, mck2ui 16
5596 16:31:13.801740 best dqsien dly found for B0: ( 1, 2, 20)
5597 16:31:13.805025 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5598 16:31:13.811895 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 16:31:13.811971 Total UI for P1: 0, mck2ui 16
5600 16:31:13.818447 best dqsien dly found for B1: ( 1, 2, 26)
5601 16:31:13.821716 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5602 16:31:13.825051 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5603 16:31:13.825163
5604 16:31:13.828322 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5605 16:31:13.831944 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5606 16:31:13.834983 [Gating] SW calibration Done
5607 16:31:13.835067 ==
5608 16:31:13.838215 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 16:31:13.841858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 16:31:13.841959 ==
5611 16:31:13.844921 RX Vref Scan: 0
5612 16:31:13.845120
5613 16:31:13.845230 RX Vref 0 -> 0, step: 1
5614 16:31:13.845361
5615 16:31:13.848469 RX Delay -80 -> 252, step: 8
5616 16:31:13.854963 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5617 16:31:13.858305 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5618 16:31:13.861294 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5619 16:31:13.864678 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5620 16:31:13.868461 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5621 16:31:13.871637 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5622 16:31:13.874883 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5623 16:31:13.881370 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5624 16:31:13.884756 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5625 16:31:13.887903 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5626 16:31:13.891767 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5627 16:31:13.894959 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5628 16:31:13.898041 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5629 16:31:13.905068 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5630 16:31:13.908264 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5631 16:31:13.911574 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5632 16:31:13.911683 ==
5633 16:31:13.914742 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 16:31:13.918302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 16:31:13.918408 ==
5636 16:31:13.921541 DQS Delay:
5637 16:31:13.921615 DQS0 = 0, DQS1 = 0
5638 16:31:13.924755 DQM Delay:
5639 16:31:13.924829 DQM0 = 102, DQM1 = 95
5640 16:31:13.924891 DQ Delay:
5641 16:31:13.928045 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5642 16:31:13.931291 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5643 16:31:13.934529 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5644 16:31:13.941164 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =103
5645 16:31:13.941253
5646 16:31:13.941320
5647 16:31:13.941383 ==
5648 16:31:13.944450 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 16:31:13.947844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 16:31:13.947919 ==
5651 16:31:13.948020
5652 16:31:13.948123
5653 16:31:13.951413 TX Vref Scan disable
5654 16:31:13.951485 == TX Byte 0 ==
5655 16:31:13.957917 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5656 16:31:13.960929 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5657 16:31:13.961004 == TX Byte 1 ==
5658 16:31:13.967889 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5659 16:31:13.971118 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5660 16:31:13.971199 ==
5661 16:31:13.974269 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 16:31:13.977499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 16:31:13.977583 ==
5664 16:31:13.977653
5665 16:31:13.977715
5666 16:31:13.980846 TX Vref Scan disable
5667 16:31:13.984565 == TX Byte 0 ==
5668 16:31:13.987919 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5669 16:31:13.991289 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5670 16:31:13.994460 == TX Byte 1 ==
5671 16:31:13.997810 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5672 16:31:14.000966 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5673 16:31:14.001040
5674 16:31:14.004095 [DATLAT]
5675 16:31:14.004171 Freq=933, CH1 RK0
5676 16:31:14.004234
5677 16:31:14.007838 DATLAT Default: 0xd
5678 16:31:14.007914 0, 0xFFFF, sum = 0
5679 16:31:14.010993 1, 0xFFFF, sum = 0
5680 16:31:14.011069 2, 0xFFFF, sum = 0
5681 16:31:14.014213 3, 0xFFFF, sum = 0
5682 16:31:14.014287 4, 0xFFFF, sum = 0
5683 16:31:14.017432 5, 0xFFFF, sum = 0
5684 16:31:14.017514 6, 0xFFFF, sum = 0
5685 16:31:14.021053 7, 0xFFFF, sum = 0
5686 16:31:14.021135 8, 0xFFFF, sum = 0
5687 16:31:14.024359 9, 0xFFFF, sum = 0
5688 16:31:14.024432 10, 0x0, sum = 1
5689 16:31:14.027516 11, 0x0, sum = 2
5690 16:31:14.027596 12, 0x0, sum = 3
5691 16:31:14.030829 13, 0x0, sum = 4
5692 16:31:14.030906 best_step = 11
5693 16:31:14.030966
5694 16:31:14.031025 ==
5695 16:31:14.034180 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 16:31:14.040951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 16:31:14.041049 ==
5698 16:31:14.041115 RX Vref Scan: 1
5699 16:31:14.041177
5700 16:31:14.044049 RX Vref 0 -> 0, step: 1
5701 16:31:14.044123
5702 16:31:14.047306 RX Delay -53 -> 252, step: 4
5703 16:31:14.047385
5704 16:31:14.051002 Set Vref, RX VrefLevel [Byte0]: 52
5705 16:31:14.054061 [Byte1]: 58
5706 16:31:14.054142
5707 16:31:14.057312 Final RX Vref Byte 0 = 52 to rank0
5708 16:31:14.060896 Final RX Vref Byte 1 = 58 to rank0
5709 16:31:14.064420 Final RX Vref Byte 0 = 52 to rank1
5710 16:31:14.067346 Final RX Vref Byte 1 = 58 to rank1==
5711 16:31:14.070748 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 16:31:14.074000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 16:31:14.074081 ==
5714 16:31:14.077727 DQS Delay:
5715 16:31:14.077806 DQS0 = 0, DQS1 = 0
5716 16:31:14.077872 DQM Delay:
5717 16:31:14.080971 DQM0 = 104, DQM1 = 97
5718 16:31:14.081106 DQ Delay:
5719 16:31:14.084186 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =104
5720 16:31:14.087412 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =102
5721 16:31:14.090712 DQ8 =90, DQ9 =86, DQ10 =102, DQ11 =92
5722 16:31:14.094024 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5723 16:31:14.094104
5724 16:31:14.097340
5725 16:31:14.103923 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5726 16:31:14.107556 CH1 RK0: MR19=505, MR18=1B34
5727 16:31:14.113885 CH1_RK0: MR19=0x505, MR18=0x1B34, DQSOSC=405, MR23=63, INC=66, DEC=44
5728 16:31:14.114001
5729 16:31:14.117190 ----->DramcWriteLeveling(PI) begin...
5730 16:31:14.117269 ==
5731 16:31:14.121012 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 16:31:14.124115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 16:31:14.124194 ==
5734 16:31:14.127364 Write leveling (Byte 0): 27 => 27
5735 16:31:14.130611 Write leveling (Byte 1): 28 => 28
5736 16:31:14.133942 DramcWriteLeveling(PI) end<-----
5737 16:31:14.134021
5738 16:31:14.134084 ==
5739 16:31:14.137171 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 16:31:14.140399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 16:31:14.140474 ==
5742 16:31:14.144183 [Gating] SW mode calibration
5743 16:31:14.150684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5744 16:31:14.157186 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5745 16:31:14.160975 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 16:31:14.164083 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 16:31:14.170950 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 16:31:14.173879 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 16:31:14.177295 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 16:31:14.183951 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 16:31:14.187136 0 14 24 | B1->B0 | 3333 3434 | 1 0 | (1 0) (0 0)
5752 16:31:14.190419 0 14 28 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (1 0)
5753 16:31:14.197069 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 16:31:14.200834 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 16:31:14.204095 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 16:31:14.210588 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 16:31:14.214173 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 16:31:14.217482 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 16:31:14.220719 0 15 24 | B1->B0 | 2c2c 2626 | 0 0 | (0 0) (0 0)
5760 16:31:14.227240 0 15 28 | B1->B0 | 3e3e 3838 | 0 1 | (1 1) (0 0)
5761 16:31:14.230809 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 16:31:14.234004 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 16:31:14.240455 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 16:31:14.244240 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 16:31:14.247006 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 16:31:14.253912 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5767 16:31:14.257077 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5768 16:31:14.260837 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5769 16:31:14.267256 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 16:31:14.270515 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 16:31:14.274170 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 16:31:14.280878 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 16:31:14.283926 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 16:31:14.287281 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 16:31:14.294053 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 16:31:14.297306 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 16:31:14.300479 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 16:31:14.307442 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 16:31:14.310607 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 16:31:14.313855 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 16:31:14.317089 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 16:31:14.324072 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 16:31:14.327300 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5784 16:31:14.330412 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5785 16:31:14.337410 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 16:31:14.340686 Total UI for P1: 0, mck2ui 16
5787 16:31:14.343765 best dqsien dly found for B0: ( 1, 2, 26)
5788 16:31:14.347427 Total UI for P1: 0, mck2ui 16
5789 16:31:14.350577 best dqsien dly found for B1: ( 1, 2, 26)
5790 16:31:14.353867 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5791 16:31:14.356932 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5792 16:31:14.357018
5793 16:31:14.360535 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5794 16:31:14.363756 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5795 16:31:14.366918 [Gating] SW calibration Done
5796 16:31:14.367018 ==
5797 16:31:14.370676 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 16:31:14.374035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 16:31:14.374148 ==
5800 16:31:14.377122 RX Vref Scan: 0
5801 16:31:14.377226
5802 16:31:14.377329 RX Vref 0 -> 0, step: 1
5803 16:31:14.377420
5804 16:31:14.380345 RX Delay -80 -> 252, step: 8
5805 16:31:14.386923 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5806 16:31:14.390425 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5807 16:31:14.393834 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5808 16:31:14.396771 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5809 16:31:14.400491 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5810 16:31:14.403869 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5811 16:31:14.410374 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5812 16:31:14.413718 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5813 16:31:14.416876 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5814 16:31:14.420142 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5815 16:31:14.423825 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5816 16:31:14.427002 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5817 16:31:14.433448 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5818 16:31:14.437048 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5819 16:31:14.440312 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5820 16:31:14.443598 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5821 16:31:14.443679 ==
5822 16:31:14.446819 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 16:31:14.453609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 16:31:14.453685 ==
5825 16:31:14.453757 DQS Delay:
5826 16:31:14.453847 DQS0 = 0, DQS1 = 0
5827 16:31:14.456895 DQM Delay:
5828 16:31:14.457007 DQM0 = 103, DQM1 = 95
5829 16:31:14.460199 DQ Delay:
5830 16:31:14.463815 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5831 16:31:14.466996 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5832 16:31:14.470575 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5833 16:31:14.473881 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5834 16:31:14.473966
5835 16:31:14.474031
5836 16:31:14.474090 ==
5837 16:31:14.477123 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 16:31:14.480348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 16:31:14.480449 ==
5840 16:31:14.480545
5841 16:31:14.480645
5842 16:31:14.483577 TX Vref Scan disable
5843 16:31:14.486849 == TX Byte 0 ==
5844 16:31:14.490380 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5845 16:31:14.493371 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5846 16:31:14.496849 == TX Byte 1 ==
5847 16:31:14.499925 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5848 16:31:14.503431 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5849 16:31:14.503532 ==
5850 16:31:14.506979 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 16:31:14.510249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 16:31:14.510336 ==
5853 16:31:14.513475
5854 16:31:14.513553
5855 16:31:14.513629 TX Vref Scan disable
5856 16:31:14.516607 == TX Byte 0 ==
5857 16:31:14.519940 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5858 16:31:14.523218 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5859 16:31:14.526903 == TX Byte 1 ==
5860 16:31:14.530192 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5861 16:31:14.533402 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5862 16:31:14.536651
5863 16:31:14.536758 [DATLAT]
5864 16:31:14.536851 Freq=933, CH1 RK1
5865 16:31:14.536940
5866 16:31:14.540355 DATLAT Default: 0xb
5867 16:31:14.540470 0, 0xFFFF, sum = 0
5868 16:31:14.543545 1, 0xFFFF, sum = 0
5869 16:31:14.543628 2, 0xFFFF, sum = 0
5870 16:31:14.546800 3, 0xFFFF, sum = 0
5871 16:31:14.546884 4, 0xFFFF, sum = 0
5872 16:31:14.549970 5, 0xFFFF, sum = 0
5873 16:31:14.550055 6, 0xFFFF, sum = 0
5874 16:31:14.553797 7, 0xFFFF, sum = 0
5875 16:31:14.556976 8, 0xFFFF, sum = 0
5876 16:31:14.557060 9, 0xFFFF, sum = 0
5877 16:31:14.557126 10, 0x0, sum = 1
5878 16:31:14.560066 11, 0x0, sum = 2
5879 16:31:14.560153 12, 0x0, sum = 3
5880 16:31:14.563311 13, 0x0, sum = 4
5881 16:31:14.563394 best_step = 11
5882 16:31:14.563459
5883 16:31:14.563520 ==
5884 16:31:14.567028 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 16:31:14.573422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 16:31:14.573512 ==
5887 16:31:14.573582 RX Vref Scan: 0
5888 16:31:14.573645
5889 16:31:14.577001 RX Vref 0 -> 0, step: 1
5890 16:31:14.577084
5891 16:31:14.580195 RX Delay -53 -> 252, step: 4
5892 16:31:14.583448 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5893 16:31:14.590153 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5894 16:31:14.593285 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5895 16:31:14.597020 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5896 16:31:14.600270 iDelay=199, Bit 4, Center 108 (27 ~ 190) 164
5897 16:31:14.603273 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5898 16:31:14.610007 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5899 16:31:14.613110 iDelay=199, Bit 7, Center 100 (19 ~ 182) 164
5900 16:31:14.616864 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5901 16:31:14.620038 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5902 16:31:14.623263 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5903 16:31:14.626614 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5904 16:31:14.633633 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5905 16:31:14.636884 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5906 16:31:14.640023 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5907 16:31:14.643382 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5908 16:31:14.643465 ==
5909 16:31:14.646524 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 16:31:14.652992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 16:31:14.653076 ==
5912 16:31:14.653141 DQS Delay:
5913 16:31:14.656810 DQS0 = 0, DQS1 = 0
5914 16:31:14.656891 DQM Delay:
5915 16:31:14.656957 DQM0 = 105, DQM1 = 98
5916 16:31:14.660089 DQ Delay:
5917 16:31:14.663431 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =102
5918 16:31:14.666637 DQ4 =108, DQ5 =116, DQ6 =112, DQ7 =100
5919 16:31:14.669769 DQ8 =88, DQ9 =86, DQ10 =98, DQ11 =92
5920 16:31:14.672902 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
5921 16:31:14.672987
5922 16:31:14.673051
5923 16:31:14.679839 [DQSOSCAuto] RK1, (LSB)MR18= 0x2704, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
5924 16:31:14.683118 CH1 RK1: MR19=505, MR18=2704
5925 16:31:14.689651 CH1_RK1: MR19=0x505, MR18=0x2704, DQSOSC=409, MR23=63, INC=64, DEC=43
5926 16:31:14.692925 [RxdqsGatingPostProcess] freq 933
5927 16:31:14.699926 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5928 16:31:14.703163 best DQS0 dly(2T, 0.5T) = (0, 10)
5929 16:31:14.703273 best DQS1 dly(2T, 0.5T) = (0, 10)
5930 16:31:14.706389 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5931 16:31:14.709519 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5932 16:31:14.713181 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 16:31:14.716173 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 16:31:14.719692 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 16:31:14.722774 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 16:31:14.726054 Pre-setting of DQS Precalculation
5937 16:31:14.732916 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5938 16:31:14.739423 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5939 16:31:14.745992 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5940 16:31:14.746095
5941 16:31:14.746162
5942 16:31:14.749640 [Calibration Summary] 1866 Mbps
5943 16:31:14.749742 CH 0, Rank 0
5944 16:31:14.752881 SW Impedance : PASS
5945 16:31:14.756022 DUTY Scan : NO K
5946 16:31:14.756122 ZQ Calibration : PASS
5947 16:31:14.759257 Jitter Meter : NO K
5948 16:31:14.762489 CBT Training : PASS
5949 16:31:14.762583 Write leveling : PASS
5950 16:31:14.765738 RX DQS gating : PASS
5951 16:31:14.769610 RX DQ/DQS(RDDQC) : PASS
5952 16:31:14.769692 TX DQ/DQS : PASS
5953 16:31:14.772699 RX DATLAT : PASS
5954 16:31:14.772783 RX DQ/DQS(Engine): PASS
5955 16:31:14.775864 TX OE : NO K
5956 16:31:14.775947 All Pass.
5957 16:31:14.776023
5958 16:31:14.778965 CH 0, Rank 1
5959 16:31:14.779047 SW Impedance : PASS
5960 16:31:14.782613 DUTY Scan : NO K
5961 16:31:14.785830 ZQ Calibration : PASS
5962 16:31:14.785921 Jitter Meter : NO K
5963 16:31:14.789179 CBT Training : PASS
5964 16:31:14.792424 Write leveling : PASS
5965 16:31:14.792500 RX DQS gating : PASS
5966 16:31:14.795667 RX DQ/DQS(RDDQC) : PASS
5967 16:31:14.798953 TX DQ/DQS : PASS
5968 16:31:14.799025 RX DATLAT : PASS
5969 16:31:14.802710 RX DQ/DQS(Engine): PASS
5970 16:31:14.805468 TX OE : NO K
5971 16:31:14.805552 All Pass.
5972 16:31:14.805618
5973 16:31:14.805695 CH 1, Rank 0
5974 16:31:14.809305 SW Impedance : PASS
5975 16:31:14.812480 DUTY Scan : NO K
5976 16:31:14.812589 ZQ Calibration : PASS
5977 16:31:14.815537 Jitter Meter : NO K
5978 16:31:14.819099 CBT Training : PASS
5979 16:31:14.819192 Write leveling : PASS
5980 16:31:14.822075 RX DQS gating : PASS
5981 16:31:14.822157 RX DQ/DQS(RDDQC) : PASS
5982 16:31:14.825520 TX DQ/DQS : PASS
5983 16:31:14.829074 RX DATLAT : PASS
5984 16:31:14.829158 RX DQ/DQS(Engine): PASS
5985 16:31:14.832286 TX OE : NO K
5986 16:31:14.832375 All Pass.
5987 16:31:14.832439
5988 16:31:14.835493 CH 1, Rank 1
5989 16:31:14.835576 SW Impedance : PASS
5990 16:31:14.839219 DUTY Scan : NO K
5991 16:31:14.842003 ZQ Calibration : PASS
5992 16:31:14.842086 Jitter Meter : NO K
5993 16:31:14.845854 CBT Training : PASS
5994 16:31:14.849202 Write leveling : PASS
5995 16:31:14.849302 RX DQS gating : PASS
5996 16:31:14.852409 RX DQ/DQS(RDDQC) : PASS
5997 16:31:14.855975 TX DQ/DQS : PASS
5998 16:31:14.856054 RX DATLAT : PASS
5999 16:31:14.859256 RX DQ/DQS(Engine): PASS
6000 16:31:14.862523 TX OE : NO K
6001 16:31:14.862636 All Pass.
6002 16:31:14.862710
6003 16:31:14.862798 DramC Write-DBI off
6004 16:31:14.865847 PER_BANK_REFRESH: Hybrid Mode
6005 16:31:14.869122 TX_TRACKING: ON
6006 16:31:14.875685 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6007 16:31:14.878706 [FAST_K] Save calibration result to emmc
6008 16:31:14.885500 dramc_set_vcore_voltage set vcore to 650000
6009 16:31:14.885585 Read voltage for 400, 6
6010 16:31:14.889109 Vio18 = 0
6011 16:31:14.889192 Vcore = 650000
6012 16:31:14.889257 Vdram = 0
6013 16:31:14.889317 Vddq = 0
6014 16:31:14.892382 Vmddr = 0
6015 16:31:14.895496 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6016 16:31:14.902342 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6017 16:31:14.905719 MEM_TYPE=3, freq_sel=20
6018 16:31:14.905802 sv_algorithm_assistance_LP4_800
6019 16:31:14.912269 ============ PULL DRAM RESETB DOWN ============
6020 16:31:14.915526 ========== PULL DRAM RESETB DOWN end =========
6021 16:31:14.918689 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6022 16:31:14.922283 ===================================
6023 16:31:14.925423 LPDDR4 DRAM CONFIGURATION
6024 16:31:14.928931 ===================================
6025 16:31:14.932036 EX_ROW_EN[0] = 0x0
6026 16:31:14.932118 EX_ROW_EN[1] = 0x0
6027 16:31:14.935555 LP4Y_EN = 0x0
6028 16:31:14.935637 WORK_FSP = 0x0
6029 16:31:14.938935 WL = 0x2
6030 16:31:14.939018 RL = 0x2
6031 16:31:14.941932 BL = 0x2
6032 16:31:14.942014 RPST = 0x0
6033 16:31:14.945655 RD_PRE = 0x0
6034 16:31:14.945737 WR_PRE = 0x1
6035 16:31:14.948949 WR_PST = 0x0
6036 16:31:14.949031 DBI_WR = 0x0
6037 16:31:14.952242 DBI_RD = 0x0
6038 16:31:14.952324 OTF = 0x1
6039 16:31:14.955476 ===================================
6040 16:31:14.958601 ===================================
6041 16:31:14.962271 ANA top config
6042 16:31:14.965520 ===================================
6043 16:31:14.968537 DLL_ASYNC_EN = 0
6044 16:31:14.968658 ALL_SLAVE_EN = 1
6045 16:31:14.971954 NEW_RANK_MODE = 1
6046 16:31:14.975192 DLL_IDLE_MODE = 1
6047 16:31:14.978440 LP45_APHY_COMB_EN = 1
6048 16:31:14.978524 TX_ODT_DIS = 1
6049 16:31:14.981978 NEW_8X_MODE = 1
6050 16:31:14.985087 ===================================
6051 16:31:14.988250 ===================================
6052 16:31:14.991881 data_rate = 800
6053 16:31:14.995068 CKR = 1
6054 16:31:14.998215 DQ_P2S_RATIO = 4
6055 16:31:15.001564 ===================================
6056 16:31:15.005261 CA_P2S_RATIO = 4
6057 16:31:15.005343 DQ_CA_OPEN = 0
6058 16:31:15.008533 DQ_SEMI_OPEN = 1
6059 16:31:15.011728 CA_SEMI_OPEN = 1
6060 16:31:15.014982 CA_FULL_RATE = 0
6061 16:31:15.018131 DQ_CKDIV4_EN = 0
6062 16:31:15.021317 CA_CKDIV4_EN = 1
6063 16:31:15.021401 CA_PREDIV_EN = 0
6064 16:31:15.024957 PH8_DLY = 0
6065 16:31:15.028064 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6066 16:31:15.031566 DQ_AAMCK_DIV = 0
6067 16:31:15.035217 CA_AAMCK_DIV = 0
6068 16:31:15.038290 CA_ADMCK_DIV = 4
6069 16:31:15.038372 DQ_TRACK_CA_EN = 0
6070 16:31:15.041617 CA_PICK = 800
6071 16:31:15.044857 CA_MCKIO = 400
6072 16:31:15.047954 MCKIO_SEMI = 400
6073 16:31:15.051215 PLL_FREQ = 3016
6074 16:31:15.054531 DQ_UI_PI_RATIO = 32
6075 16:31:15.058361 CA_UI_PI_RATIO = 32
6076 16:31:15.061517 ===================================
6077 16:31:15.064519 ===================================
6078 16:31:15.064631 memory_type:LPDDR4
6079 16:31:15.068303 GP_NUM : 10
6080 16:31:15.071551 SRAM_EN : 1
6081 16:31:15.071634 MD32_EN : 0
6082 16:31:15.074889 ===================================
6083 16:31:15.078086 [ANA_INIT] >>>>>>>>>>>>>>
6084 16:31:15.081279 <<<<<< [CONFIGURE PHASE]: ANA_TX
6085 16:31:15.085003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6086 16:31:15.088097 ===================================
6087 16:31:15.091347 data_rate = 800,PCW = 0X7400
6088 16:31:15.094857 ===================================
6089 16:31:15.097998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6090 16:31:15.101637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 16:31:15.114935 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6092 16:31:15.118142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6093 16:31:15.121380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6094 16:31:15.124637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6095 16:31:15.127867 [ANA_INIT] flow start
6096 16:31:15.131016 [ANA_INIT] PLL >>>>>>>>
6097 16:31:15.131119 [ANA_INIT] PLL <<<<<<<<
6098 16:31:15.134559 [ANA_INIT] MIDPI >>>>>>>>
6099 16:31:15.138071 [ANA_INIT] MIDPI <<<<<<<<
6100 16:31:15.138176 [ANA_INIT] DLL >>>>>>>>
6101 16:31:15.141100 [ANA_INIT] flow end
6102 16:31:15.144476 ============ LP4 DIFF to SE enter ============
6103 16:31:15.148111 ============ LP4 DIFF to SE exit ============
6104 16:31:15.151230 [ANA_INIT] <<<<<<<<<<<<<
6105 16:31:15.154453 [Flow] Enable top DCM control >>>>>
6106 16:31:15.157581 [Flow] Enable top DCM control <<<<<
6107 16:31:15.161427 Enable DLL master slave shuffle
6108 16:31:15.167633 ==============================================================
6109 16:31:15.167750 Gating Mode config
6110 16:31:15.174539 ==============================================================
6111 16:31:15.174620 Config description:
6112 16:31:15.184682 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6113 16:31:15.190948 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6114 16:31:15.197778 SELPH_MODE 0: By rank 1: By Phase
6115 16:31:15.201034 ==============================================================
6116 16:31:15.204458 GAT_TRACK_EN = 0
6117 16:31:15.207656 RX_GATING_MODE = 2
6118 16:31:15.211311 RX_GATING_TRACK_MODE = 2
6119 16:31:15.214461 SELPH_MODE = 1
6120 16:31:15.217706 PICG_EARLY_EN = 1
6121 16:31:15.220988 VALID_LAT_VALUE = 1
6122 16:31:15.224263 ==============================================================
6123 16:31:15.227478 Enter into Gating configuration >>>>
6124 16:31:15.231295 Exit from Gating configuration <<<<
6125 16:31:15.234516 Enter into DVFS_PRE_config >>>>>
6126 16:31:15.247771 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6127 16:31:15.250757 Exit from DVFS_PRE_config <<<<<
6128 16:31:15.254343 Enter into PICG configuration >>>>
6129 16:31:15.257591 Exit from PICG configuration <<<<
6130 16:31:15.257695 [RX_INPUT] configuration >>>>>
6131 16:31:15.260951 [RX_INPUT] configuration <<<<<
6132 16:31:15.267373 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6133 16:31:15.271115 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6134 16:31:15.277554 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6135 16:31:15.284208 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6136 16:31:15.290758 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 16:31:15.297391 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 16:31:15.300948 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6139 16:31:15.304071 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6140 16:31:15.307581 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6141 16:31:15.313918 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6142 16:31:15.317640 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6143 16:31:15.320878 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6144 16:31:15.323948 ===================================
6145 16:31:15.327162 LPDDR4 DRAM CONFIGURATION
6146 16:31:15.330468 ===================================
6147 16:31:15.334292 EX_ROW_EN[0] = 0x0
6148 16:31:15.334376 EX_ROW_EN[1] = 0x0
6149 16:31:15.337535 LP4Y_EN = 0x0
6150 16:31:15.337618 WORK_FSP = 0x0
6151 16:31:15.340740 WL = 0x2
6152 16:31:15.340898 RL = 0x2
6153 16:31:15.344087 BL = 0x2
6154 16:31:15.344170 RPST = 0x0
6155 16:31:15.347123 RD_PRE = 0x0
6156 16:31:15.347205 WR_PRE = 0x1
6157 16:31:15.350705 WR_PST = 0x0
6158 16:31:15.350802 DBI_WR = 0x0
6159 16:31:15.353822 DBI_RD = 0x0
6160 16:31:15.353904 OTF = 0x1
6161 16:31:15.357356 ===================================
6162 16:31:15.363736 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6163 16:31:15.367171 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6164 16:31:15.370409 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6165 16:31:15.373641 ===================================
6166 16:31:15.377378 LPDDR4 DRAM CONFIGURATION
6167 16:31:15.380422 ===================================
6168 16:31:15.383691 EX_ROW_EN[0] = 0x10
6169 16:31:15.383768 EX_ROW_EN[1] = 0x0
6170 16:31:15.386945 LP4Y_EN = 0x0
6171 16:31:15.387016 WORK_FSP = 0x0
6172 16:31:15.390229 WL = 0x2
6173 16:31:15.390310 RL = 0x2
6174 16:31:15.394044 BL = 0x2
6175 16:31:15.394121 RPST = 0x0
6176 16:31:15.396778 RD_PRE = 0x0
6177 16:31:15.396861 WR_PRE = 0x1
6178 16:31:15.400055 WR_PST = 0x0
6179 16:31:15.400170 DBI_WR = 0x0
6180 16:31:15.403880 DBI_RD = 0x0
6181 16:31:15.404005 OTF = 0x1
6182 16:31:15.406857 ===================================
6183 16:31:15.413829 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6184 16:31:15.418147 nWR fixed to 30
6185 16:31:15.421964 [ModeRegInit_LP4] CH0 RK0
6186 16:31:15.422060 [ModeRegInit_LP4] CH0 RK1
6187 16:31:15.424752 [ModeRegInit_LP4] CH1 RK0
6188 16:31:15.428446 [ModeRegInit_LP4] CH1 RK1
6189 16:31:15.428521 match AC timing 19
6190 16:31:15.434979 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6191 16:31:15.438281 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6192 16:31:15.441396 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6193 16:31:15.448363 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6194 16:31:15.451594 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6195 16:31:15.451726 ==
6196 16:31:15.455104 Dram Type= 6, Freq= 0, CH_0, rank 0
6197 16:31:15.458468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6198 16:31:15.458555 ==
6199 16:31:15.464944 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6200 16:31:15.471592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6201 16:31:15.474697 [CA 0] Center 36 (8~64) winsize 57
6202 16:31:15.478455 [CA 1] Center 36 (8~64) winsize 57
6203 16:31:15.481515 [CA 2] Center 36 (8~64) winsize 57
6204 16:31:15.481601 [CA 3] Center 36 (8~64) winsize 57
6205 16:31:15.485248 [CA 4] Center 36 (8~64) winsize 57
6206 16:31:15.488242 [CA 5] Center 36 (8~64) winsize 57
6207 16:31:15.488340
6208 16:31:15.491611 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6209 16:31:15.494894
6210 16:31:15.498047 [CATrainingPosCal] consider 1 rank data
6211 16:31:15.498131 u2DelayCellTimex100 = 270/100 ps
6212 16:31:15.504833 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 16:31:15.508340 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 16:31:15.511373 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 16:31:15.514591 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 16:31:15.518320 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 16:31:15.521625 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 16:31:15.521708
6219 16:31:15.524865 CA PerBit enable=1, Macro0, CA PI delay=36
6220 16:31:15.524948
6221 16:31:15.528132 [CBTSetCACLKResult] CA Dly = 36
6222 16:31:15.531399 CS Dly: 1 (0~32)
6223 16:31:15.531481 ==
6224 16:31:15.534637 Dram Type= 6, Freq= 0, CH_0, rank 1
6225 16:31:15.537882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6226 16:31:15.537966 ==
6227 16:31:15.544902 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6228 16:31:15.548160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6229 16:31:15.551348 [CA 0] Center 36 (8~64) winsize 57
6230 16:31:15.554591 [CA 1] Center 36 (8~64) winsize 57
6231 16:31:15.557934 [CA 2] Center 36 (8~64) winsize 57
6232 16:31:15.561068 [CA 3] Center 36 (8~64) winsize 57
6233 16:31:15.564478 [CA 4] Center 36 (8~64) winsize 57
6234 16:31:15.568044 [CA 5] Center 36 (8~64) winsize 57
6235 16:31:15.568127
6236 16:31:15.571122 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6237 16:31:15.571205
6238 16:31:15.574726 [CATrainingPosCal] consider 2 rank data
6239 16:31:15.577822 u2DelayCellTimex100 = 270/100 ps
6240 16:31:15.581090 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 16:31:15.584372 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 16:31:15.590585 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 16:31:15.594407 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 16:31:15.597647 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 16:31:15.600876 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 16:31:15.600960
6247 16:31:15.604196 CA PerBit enable=1, Macro0, CA PI delay=36
6248 16:31:15.604320
6249 16:31:15.607430 [CBTSetCACLKResult] CA Dly = 36
6250 16:31:15.607547 CS Dly: 1 (0~32)
6251 16:31:15.607648
6252 16:31:15.611077 ----->DramcWriteLeveling(PI) begin...
6253 16:31:15.611199 ==
6254 16:31:15.614229 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 16:31:15.621163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 16:31:15.621247 ==
6257 16:31:15.624410 Write leveling (Byte 0): 40 => 8
6258 16:31:15.627671 Write leveling (Byte 1): 32 => 0
6259 16:31:15.627756 DramcWriteLeveling(PI) end<-----
6260 16:31:15.627825
6261 16:31:15.630918 ==
6262 16:31:15.634128 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 16:31:15.637368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 16:31:15.637452 ==
6265 16:31:15.641218 [Gating] SW mode calibration
6266 16:31:15.647649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6267 16:31:15.650944 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6268 16:31:15.657389 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 16:31:15.661037 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6270 16:31:15.664297 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 16:31:15.670730 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 16:31:15.673995 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 16:31:15.677323 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 16:31:15.683917 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 16:31:15.687381 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 16:31:15.690572 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 16:31:15.693541 Total UI for P1: 0, mck2ui 16
6278 16:31:15.697324 best dqsien dly found for B0: ( 0, 14, 24)
6279 16:31:15.700503 Total UI for P1: 0, mck2ui 16
6280 16:31:15.703824 best dqsien dly found for B1: ( 0, 14, 24)
6281 16:31:15.706928 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6282 16:31:15.710189 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6283 16:31:15.710291
6284 16:31:15.717142 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 16:31:15.720288 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6286 16:31:15.723894 [Gating] SW calibration Done
6287 16:31:15.724012 ==
6288 16:31:15.727070 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 16:31:15.730303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 16:31:15.730403 ==
6291 16:31:15.730494 RX Vref Scan: 0
6292 16:31:15.730581
6293 16:31:15.733506 RX Vref 0 -> 0, step: 1
6294 16:31:15.733602
6295 16:31:15.737260 RX Delay -410 -> 252, step: 16
6296 16:31:15.740443 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6297 16:31:15.743843 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6298 16:31:15.750228 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6299 16:31:15.753453 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6300 16:31:15.757282 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6301 16:31:15.760040 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6302 16:31:15.767147 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6303 16:31:15.770336 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6304 16:31:15.773335 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6305 16:31:15.776928 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6306 16:31:15.783464 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6307 16:31:15.786870 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6308 16:31:15.790328 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6309 16:31:15.797080 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6310 16:31:15.800063 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6311 16:31:15.803516 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6312 16:31:15.803629 ==
6313 16:31:15.806491 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 16:31:15.810084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 16:31:15.810188 ==
6316 16:31:15.813895 DQS Delay:
6317 16:31:15.813991 DQS0 = 19, DQS1 = 43
6318 16:31:15.817144 DQM Delay:
6319 16:31:15.817256 DQM0 = 5, DQM1 = 15
6320 16:31:15.817347 DQ Delay:
6321 16:31:15.820204 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6322 16:31:15.823249 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6323 16:31:15.826769 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6324 16:31:15.830053 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6325 16:31:15.830153
6326 16:31:15.830243
6327 16:31:15.830328 ==
6328 16:31:15.833303 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 16:31:15.839792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 16:31:15.839894 ==
6331 16:31:15.839985
6332 16:31:15.840073
6333 16:31:15.840159 TX Vref Scan disable
6334 16:31:15.843514 == TX Byte 0 ==
6335 16:31:15.846748 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 16:31:15.849953 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 16:31:15.853326 == TX Byte 1 ==
6338 16:31:15.856657 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6339 16:31:15.859870 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6340 16:31:15.859970 ==
6341 16:31:15.863235 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 16:31:15.869690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 16:31:15.869792 ==
6344 16:31:15.869882
6345 16:31:15.869969
6346 16:31:15.870053 TX Vref Scan disable
6347 16:31:15.873388 == TX Byte 0 ==
6348 16:31:15.876479 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 16:31:15.879659 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 16:31:15.883377 == TX Byte 1 ==
6351 16:31:15.886589 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6352 16:31:15.889619 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6353 16:31:15.893253
6354 16:31:15.893350 [DATLAT]
6355 16:31:15.893446 Freq=400, CH0 RK0
6356 16:31:15.893533
6357 16:31:15.896213 DATLAT Default: 0xf
6358 16:31:15.896309 0, 0xFFFF, sum = 0
6359 16:31:15.899633 1, 0xFFFF, sum = 0
6360 16:31:15.899709 2, 0xFFFF, sum = 0
6361 16:31:15.903275 3, 0xFFFF, sum = 0
6362 16:31:15.903376 4, 0xFFFF, sum = 0
6363 16:31:15.906410 5, 0xFFFF, sum = 0
6364 16:31:15.909744 6, 0xFFFF, sum = 0
6365 16:31:15.909850 7, 0xFFFF, sum = 0
6366 16:31:15.913117 8, 0xFFFF, sum = 0
6367 16:31:15.913214 9, 0xFFFF, sum = 0
6368 16:31:15.916520 10, 0xFFFF, sum = 0
6369 16:31:15.916637 11, 0xFFFF, sum = 0
6370 16:31:15.919923 12, 0xFFFF, sum = 0
6371 16:31:15.920024 13, 0x0, sum = 1
6372 16:31:15.923029 14, 0x0, sum = 2
6373 16:31:15.923124 15, 0x0, sum = 3
6374 16:31:15.926692 16, 0x0, sum = 4
6375 16:31:15.926786 best_step = 14
6376 16:31:15.926873
6377 16:31:15.926965 ==
6378 16:31:15.929833 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 16:31:15.932952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 16:31:15.933049 ==
6381 16:31:15.936372 RX Vref Scan: 1
6382 16:31:15.936464
6383 16:31:15.939574 RX Vref 0 -> 0, step: 1
6384 16:31:15.939670
6385 16:31:15.939737 RX Delay -327 -> 252, step: 8
6386 16:31:15.939803
6387 16:31:15.942882 Set Vref, RX VrefLevel [Byte0]: 57
6388 16:31:15.946115 [Byte1]: 49
6389 16:31:15.951881
6390 16:31:15.951988 Final RX Vref Byte 0 = 57 to rank0
6391 16:31:15.955118 Final RX Vref Byte 1 = 49 to rank0
6392 16:31:15.958301 Final RX Vref Byte 0 = 57 to rank1
6393 16:31:15.961420 Final RX Vref Byte 1 = 49 to rank1==
6394 16:31:15.965228 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 16:31:15.971897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 16:31:15.972009 ==
6397 16:31:15.972102 DQS Delay:
6398 16:31:15.975057 DQS0 = 28, DQS1 = 48
6399 16:31:15.975178 DQM Delay:
6400 16:31:15.975270 DQM0 = 12, DQM1 = 15
6401 16:31:15.978353 DQ Delay:
6402 16:31:15.981524 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6403 16:31:15.981624 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6404 16:31:15.985285 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6405 16:31:15.988431 DQ12 =24, DQ13 =16, DQ14 =28, DQ15 =24
6406 16:31:15.991556
6407 16:31:15.991638
6408 16:31:15.998346 [DQSOSCAuto] RK0, (LSB)MR18= 0xb5ab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6409 16:31:16.001507 CH0 RK0: MR19=C0C, MR18=B5AB
6410 16:31:16.008462 CH0_RK0: MR19=0xC0C, MR18=0xB5AB, DQSOSC=387, MR23=63, INC=394, DEC=262
6411 16:31:16.008555 ==
6412 16:31:16.011617 Dram Type= 6, Freq= 0, CH_0, rank 1
6413 16:31:16.015154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 16:31:16.015239 ==
6415 16:31:16.018207 [Gating] SW mode calibration
6416 16:31:16.024973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6417 16:31:16.031691 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6418 16:31:16.034837 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 16:31:16.038144 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 16:31:16.041485 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 16:31:16.048441 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 16:31:16.051741 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 16:31:16.055011 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 16:31:16.061500 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 16:31:16.064749 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 16:31:16.068050 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 16:31:16.071407 Total UI for P1: 0, mck2ui 16
6428 16:31:16.074667 best dqsien dly found for B0: ( 0, 14, 24)
6429 16:31:16.077955 Total UI for P1: 0, mck2ui 16
6430 16:31:16.081159 best dqsien dly found for B1: ( 0, 14, 24)
6431 16:31:16.085064 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6432 16:31:16.088227 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6433 16:31:16.091502
6434 16:31:16.094721 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 16:31:16.097874 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6436 16:31:16.101495 [Gating] SW calibration Done
6437 16:31:16.101620 ==
6438 16:31:16.104779 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 16:31:16.107955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 16:31:16.108039 ==
6441 16:31:16.108106 RX Vref Scan: 0
6442 16:31:16.111068
6443 16:31:16.111172 RX Vref 0 -> 0, step: 1
6444 16:31:16.111253
6445 16:31:16.114580 RX Delay -410 -> 252, step: 16
6446 16:31:16.117754 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6447 16:31:16.124705 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6448 16:31:16.127713 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6449 16:31:16.131400 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6450 16:31:16.134442 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6451 16:31:16.141060 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6452 16:31:16.144282 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6453 16:31:16.147557 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6454 16:31:16.150792 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6455 16:31:16.157763 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6456 16:31:16.161008 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6457 16:31:16.164292 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6458 16:31:16.167458 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6459 16:31:16.173994 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6460 16:31:16.177251 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6461 16:31:16.180428 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6462 16:31:16.180525 ==
6463 16:31:16.184209 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 16:31:16.190753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 16:31:16.190836 ==
6466 16:31:16.190907 DQS Delay:
6467 16:31:16.194119 DQS0 = 27, DQS1 = 35
6468 16:31:16.194204 DQM Delay:
6469 16:31:16.194269 DQM0 = 9, DQM1 = 7
6470 16:31:16.197283 DQ Delay:
6471 16:31:16.200481 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6472 16:31:16.200598 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6473 16:31:16.203842 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6474 16:31:16.207351 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =8
6475 16:31:16.207430
6476 16:31:16.207503
6477 16:31:16.210440 ==
6478 16:31:16.210535 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 16:31:16.217026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 16:31:16.217123 ==
6481 16:31:16.217188
6482 16:31:16.217248
6483 16:31:16.220580 TX Vref Scan disable
6484 16:31:16.220666 == TX Byte 0 ==
6485 16:31:16.224010 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6486 16:31:16.230606 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6487 16:31:16.230685 == TX Byte 1 ==
6488 16:31:16.233957 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6489 16:31:16.237154 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6490 16:31:16.240371 ==
6491 16:31:16.243376 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 16:31:16.247081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 16:31:16.247164 ==
6494 16:31:16.247229
6495 16:31:16.247288
6496 16:31:16.250423 TX Vref Scan disable
6497 16:31:16.250507 == TX Byte 0 ==
6498 16:31:16.253666 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6499 16:31:16.260272 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6500 16:31:16.260355 == TX Byte 1 ==
6501 16:31:16.263456 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6502 16:31:16.270083 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6503 16:31:16.270167
6504 16:31:16.270232 [DATLAT]
6505 16:31:16.270299 Freq=400, CH0 RK1
6506 16:31:16.270377
6507 16:31:16.273392 DATLAT Default: 0xe
6508 16:31:16.273474 0, 0xFFFF, sum = 0
6509 16:31:16.276627 1, 0xFFFF, sum = 0
6510 16:31:16.279978 2, 0xFFFF, sum = 0
6511 16:31:16.280061 3, 0xFFFF, sum = 0
6512 16:31:16.283322 4, 0xFFFF, sum = 0
6513 16:31:16.283423 5, 0xFFFF, sum = 0
6514 16:31:16.286648 6, 0xFFFF, sum = 0
6515 16:31:16.286748 7, 0xFFFF, sum = 0
6516 16:31:16.289840 8, 0xFFFF, sum = 0
6517 16:31:16.289941 9, 0xFFFF, sum = 0
6518 16:31:16.293130 10, 0xFFFF, sum = 0
6519 16:31:16.293232 11, 0xFFFF, sum = 0
6520 16:31:16.296704 12, 0xFFFF, sum = 0
6521 16:31:16.296813 13, 0x0, sum = 1
6522 16:31:16.300324 14, 0x0, sum = 2
6523 16:31:16.300430 15, 0x0, sum = 3
6524 16:31:16.303454 16, 0x0, sum = 4
6525 16:31:16.303528 best_step = 14
6526 16:31:16.303588
6527 16:31:16.303645 ==
6528 16:31:16.306641 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 16:31:16.309777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 16:31:16.313450 ==
6531 16:31:16.313544 RX Vref Scan: 0
6532 16:31:16.313633
6533 16:31:16.316504 RX Vref 0 -> 0, step: 1
6534 16:31:16.316615
6535 16:31:16.319777 RX Delay -311 -> 252, step: 8
6536 16:31:16.323021 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6537 16:31:16.329863 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6538 16:31:16.333324 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6539 16:31:16.336444 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6540 16:31:16.339955 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6541 16:31:16.346592 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6542 16:31:16.349876 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6543 16:31:16.353300 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6544 16:31:16.356454 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6545 16:31:16.363015 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6546 16:31:16.366518 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6547 16:31:16.370202 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6548 16:31:16.373430 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6549 16:31:16.380004 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6550 16:31:16.383209 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6551 16:31:16.386543 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6552 16:31:16.386626 ==
6553 16:31:16.389797 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 16:31:16.396258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 16:31:16.396367 ==
6556 16:31:16.396460 DQS Delay:
6557 16:31:16.399428 DQS0 = 28, DQS1 = 40
6558 16:31:16.399511 DQM Delay:
6559 16:31:16.399575 DQM0 = 10, DQM1 = 12
6560 16:31:16.402908 DQ Delay:
6561 16:31:16.406291 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6562 16:31:16.406366 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6563 16:31:16.409834 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6564 16:31:16.413074 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6565 16:31:16.413160
6566 16:31:16.416255
6567 16:31:16.423013 [DQSOSCAuto] RK1, (LSB)MR18= 0xc174, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 385 ps
6568 16:31:16.426294 CH0 RK1: MR19=C0C, MR18=C174
6569 16:31:16.432821 CH0_RK1: MR19=0xC0C, MR18=0xC174, DQSOSC=385, MR23=63, INC=398, DEC=265
6570 16:31:16.436009 [RxdqsGatingPostProcess] freq 400
6571 16:31:16.439569 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6572 16:31:16.442518 best DQS0 dly(2T, 0.5T) = (0, 10)
6573 16:31:16.445906 best DQS1 dly(2T, 0.5T) = (0, 10)
6574 16:31:16.449373 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6575 16:31:16.452898 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6576 16:31:16.455927 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 16:31:16.459574 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 16:31:16.462670 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 16:31:16.465906 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 16:31:16.469151 Pre-setting of DQS Precalculation
6581 16:31:16.472450 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6582 16:31:16.472538 ==
6583 16:31:16.475663 Dram Type= 6, Freq= 0, CH_1, rank 0
6584 16:31:16.482868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 16:31:16.482955 ==
6586 16:31:16.486097 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6587 16:31:16.492682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6588 16:31:16.496054 [CA 0] Center 36 (8~64) winsize 57
6589 16:31:16.499291 [CA 1] Center 36 (8~64) winsize 57
6590 16:31:16.502530 [CA 2] Center 36 (8~64) winsize 57
6591 16:31:16.505715 [CA 3] Center 36 (8~64) winsize 57
6592 16:31:16.509268 [CA 4] Center 36 (8~64) winsize 57
6593 16:31:16.512244 [CA 5] Center 36 (8~64) winsize 57
6594 16:31:16.512331
6595 16:31:16.515797 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6596 16:31:16.515876
6597 16:31:16.518955 [CATrainingPosCal] consider 1 rank data
6598 16:31:16.522595 u2DelayCellTimex100 = 270/100 ps
6599 16:31:16.525808 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 16:31:16.529019 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 16:31:16.532262 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 16:31:16.535569 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 16:31:16.538839 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 16:31:16.542003 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 16:31:16.542082
6606 16:31:16.548617 CA PerBit enable=1, Macro0, CA PI delay=36
6607 16:31:16.548699
6608 16:31:16.552177 [CBTSetCACLKResult] CA Dly = 36
6609 16:31:16.552279 CS Dly: 1 (0~32)
6610 16:31:16.552383 ==
6611 16:31:16.555653 Dram Type= 6, Freq= 0, CH_1, rank 1
6612 16:31:16.558641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 16:31:16.558804 ==
6614 16:31:16.565671 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6615 16:31:16.572180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6616 16:31:16.575522 [CA 0] Center 36 (8~64) winsize 57
6617 16:31:16.578698 [CA 1] Center 36 (8~64) winsize 57
6618 16:31:16.582460 [CA 2] Center 36 (8~64) winsize 57
6619 16:31:16.582545 [CA 3] Center 36 (8~64) winsize 57
6620 16:31:16.585768 [CA 4] Center 36 (8~64) winsize 57
6621 16:31:16.589029 [CA 5] Center 36 (8~64) winsize 57
6622 16:31:16.589109
6623 16:31:16.595610 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6624 16:31:16.595692
6625 16:31:16.598814 [CATrainingPosCal] consider 2 rank data
6626 16:31:16.602043 u2DelayCellTimex100 = 270/100 ps
6627 16:31:16.605803 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 16:31:16.609022 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 16:31:16.612183 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 16:31:16.615832 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 16:31:16.618805 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 16:31:16.622435 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 16:31:16.622522
6634 16:31:16.625406 CA PerBit enable=1, Macro0, CA PI delay=36
6635 16:31:16.625506
6636 16:31:16.629155 [CBTSetCACLKResult] CA Dly = 36
6637 16:31:16.632253 CS Dly: 1 (0~32)
6638 16:31:16.632326
6639 16:31:16.635563 ----->DramcWriteLeveling(PI) begin...
6640 16:31:16.635639 ==
6641 16:31:16.638921 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 16:31:16.642229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 16:31:16.642312 ==
6644 16:31:16.645486 Write leveling (Byte 0): 40 => 8
6645 16:31:16.648734 Write leveling (Byte 1): 32 => 0
6646 16:31:16.652442 DramcWriteLeveling(PI) end<-----
6647 16:31:16.652585
6648 16:31:16.652692 ==
6649 16:31:16.655408 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 16:31:16.658813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 16:31:16.658892 ==
6652 16:31:16.662373 [Gating] SW mode calibration
6653 16:31:16.668737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6654 16:31:16.675581 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6655 16:31:16.678678 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 16:31:16.681938 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 16:31:16.688511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 16:31:16.692331 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 16:31:16.695086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 16:31:16.702091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 16:31:16.705378 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 16:31:16.708530 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 16:31:16.715343 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 16:31:16.715437 Total UI for P1: 0, mck2ui 16
6665 16:31:16.718496 best dqsien dly found for B0: ( 0, 14, 24)
6666 16:31:16.721834 Total UI for P1: 0, mck2ui 16
6667 16:31:16.724966 best dqsien dly found for B1: ( 0, 14, 24)
6668 16:31:16.731965 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6669 16:31:16.735528 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6670 16:31:16.735650
6671 16:31:16.738704 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 16:31:16.741852 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6673 16:31:16.745306 [Gating] SW calibration Done
6674 16:31:16.745431 ==
6675 16:31:16.748737 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 16:31:16.751660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 16:31:16.751800 ==
6678 16:31:16.754967 RX Vref Scan: 0
6679 16:31:16.755082
6680 16:31:16.755180 RX Vref 0 -> 0, step: 1
6681 16:31:16.755276
6682 16:31:16.758760 RX Delay -410 -> 252, step: 16
6683 16:31:16.761800 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6684 16:31:16.768436 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6685 16:31:16.772078 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6686 16:31:16.775239 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6687 16:31:16.778749 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6688 16:31:16.785227 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6689 16:31:16.788521 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6690 16:31:16.791790 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6691 16:31:16.795013 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6692 16:31:16.801547 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6693 16:31:16.804999 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6694 16:31:16.808380 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6695 16:31:16.811828 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6696 16:31:16.818432 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6697 16:31:16.821837 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6698 16:31:16.825012 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6699 16:31:16.825090 ==
6700 16:31:16.828332 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 16:31:16.835180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 16:31:16.835265 ==
6703 16:31:16.835333 DQS Delay:
6704 16:31:16.838326 DQS0 = 27, DQS1 = 43
6705 16:31:16.838438 DQM Delay:
6706 16:31:16.838527 DQM0 = 9, DQM1 = 16
6707 16:31:16.841647 DQ Delay:
6708 16:31:16.845084 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6709 16:31:16.845227 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6710 16:31:16.847983 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6711 16:31:16.851404 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6712 16:31:16.851511
6713 16:31:16.854782
6714 16:31:16.854889 ==
6715 16:31:16.858313 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 16:31:16.861791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 16:31:16.861943 ==
6718 16:31:16.862052
6719 16:31:16.862125
6720 16:31:16.864860 TX Vref Scan disable
6721 16:31:16.864971 == TX Byte 0 ==
6722 16:31:16.868042 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 16:31:16.874382 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 16:31:16.874467 == TX Byte 1 ==
6725 16:31:16.877677 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6726 16:31:16.884133 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6727 16:31:16.884253 ==
6728 16:31:16.887477 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 16:31:16.891161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 16:31:16.891284 ==
6731 16:31:16.891393
6732 16:31:16.891503
6733 16:31:16.894537 TX Vref Scan disable
6734 16:31:16.894645 == TX Byte 0 ==
6735 16:31:16.901364 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 16:31:16.904076 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 16:31:16.904183 == TX Byte 1 ==
6738 16:31:16.911220 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6739 16:31:16.914355 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6740 16:31:16.914430
6741 16:31:16.914497 [DATLAT]
6742 16:31:16.917598 Freq=400, CH1 RK0
6743 16:31:16.917673
6744 16:31:16.917735 DATLAT Default: 0xf
6745 16:31:16.920880 0, 0xFFFF, sum = 0
6746 16:31:16.920982 1, 0xFFFF, sum = 0
6747 16:31:16.924476 2, 0xFFFF, sum = 0
6748 16:31:16.924582 3, 0xFFFF, sum = 0
6749 16:31:16.927759 4, 0xFFFF, sum = 0
6750 16:31:16.927862 5, 0xFFFF, sum = 0
6751 16:31:16.930955 6, 0xFFFF, sum = 0
6752 16:31:16.931033 7, 0xFFFF, sum = 0
6753 16:31:16.934064 8, 0xFFFF, sum = 0
6754 16:31:16.934166 9, 0xFFFF, sum = 0
6755 16:31:16.937493 10, 0xFFFF, sum = 0
6756 16:31:16.941014 11, 0xFFFF, sum = 0
6757 16:31:16.941086 12, 0xFFFF, sum = 0
6758 16:31:16.944175 13, 0x0, sum = 1
6759 16:31:16.944246 14, 0x0, sum = 2
6760 16:31:16.944310 15, 0x0, sum = 3
6761 16:31:16.947498 16, 0x0, sum = 4
6762 16:31:16.947570 best_step = 14
6763 16:31:16.947630
6764 16:31:16.950729 ==
6765 16:31:16.950800 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 16:31:16.957193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 16:31:16.957270 ==
6768 16:31:16.957332 RX Vref Scan: 1
6769 16:31:16.957392
6770 16:31:16.961134 RX Vref 0 -> 0, step: 1
6771 16:31:16.961234
6772 16:31:16.964333 RX Delay -327 -> 252, step: 8
6773 16:31:16.964403
6774 16:31:16.967481 Set Vref, RX VrefLevel [Byte0]: 52
6775 16:31:16.970593 [Byte1]: 58
6776 16:31:16.974078
6777 16:31:16.974166 Final RX Vref Byte 0 = 52 to rank0
6778 16:31:16.977308 Final RX Vref Byte 1 = 58 to rank0
6779 16:31:16.980569 Final RX Vref Byte 0 = 52 to rank1
6780 16:31:16.984272 Final RX Vref Byte 1 = 58 to rank1==
6781 16:31:16.987345 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 16:31:16.994187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 16:31:16.994303 ==
6784 16:31:16.994378 DQS Delay:
6785 16:31:16.997411 DQS0 = 32, DQS1 = 40
6786 16:31:16.997533 DQM Delay:
6787 16:31:16.997646 DQM0 = 11, DQM1 = 12
6788 16:31:17.000540 DQ Delay:
6789 16:31:17.003883 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6790 16:31:17.003992 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6791 16:31:17.007120 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6792 16:31:17.010435 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6793 16:31:17.010523
6794 16:31:17.010610
6795 16:31:17.020668 [DQSOSCAuto] RK0, (LSB)MR18= 0x98d3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6796 16:31:17.023924 CH1 RK0: MR19=C0C, MR18=98D3
6797 16:31:17.030850 CH1_RK0: MR19=0xC0C, MR18=0x98D3, DQSOSC=383, MR23=63, INC=402, DEC=268
6798 16:31:17.030963 ==
6799 16:31:17.033985 Dram Type= 6, Freq= 0, CH_1, rank 1
6800 16:31:17.037198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 16:31:17.037286 ==
6802 16:31:17.040750 [Gating] SW mode calibration
6803 16:31:17.047390 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6804 16:31:17.050633 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6805 16:31:17.057105 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 16:31:17.060464 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6807 16:31:17.063717 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 16:31:17.070662 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 16:31:17.073969 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 16:31:17.077130 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 16:31:17.083919 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 16:31:17.087428 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 16:31:17.090508 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 16:31:17.093659 Total UI for P1: 0, mck2ui 16
6815 16:31:17.097365 best dqsien dly found for B0: ( 0, 14, 24)
6816 16:31:17.100498 Total UI for P1: 0, mck2ui 16
6817 16:31:17.103884 best dqsien dly found for B1: ( 0, 14, 24)
6818 16:31:17.106934 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6819 16:31:17.110295 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6820 16:31:17.110407
6821 16:31:17.116831 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 16:31:17.120531 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6823 16:31:17.123806 [Gating] SW calibration Done
6824 16:31:17.123883 ==
6825 16:31:17.126862 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 16:31:17.130602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 16:31:17.130713 ==
6828 16:31:17.130807 RX Vref Scan: 0
6829 16:31:17.130897
6830 16:31:17.133752 RX Vref 0 -> 0, step: 1
6831 16:31:17.133854
6832 16:31:17.136997 RX Delay -410 -> 252, step: 16
6833 16:31:17.140323 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6834 16:31:17.146676 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6835 16:31:17.150339 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6836 16:31:17.153507 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6837 16:31:17.156811 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6838 16:31:17.163823 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6839 16:31:17.167055 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6840 16:31:17.170251 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6841 16:31:17.173445 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6842 16:31:17.177371 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6843 16:31:17.183839 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6844 16:31:17.186927 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6845 16:31:17.190497 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6846 16:31:17.197153 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6847 16:31:17.200288 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6848 16:31:17.203525 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6849 16:31:17.203625 ==
6850 16:31:17.206814 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 16:31:17.210074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 16:31:17.210151 ==
6853 16:31:17.213367 DQS Delay:
6854 16:31:17.213436 DQS0 = 35, DQS1 = 43
6855 16:31:17.217203 DQM Delay:
6856 16:31:17.217276 DQM0 = 16, DQM1 = 18
6857 16:31:17.220397 DQ Delay:
6858 16:31:17.220482 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6859 16:31:17.223528 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6860 16:31:17.226857 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6861 16:31:17.230346 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6862 16:31:17.230451
6863 16:31:17.230544
6864 16:31:17.233513 ==
6865 16:31:17.236668 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 16:31:17.240428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 16:31:17.240542 ==
6868 16:31:17.240649
6869 16:31:17.240710
6870 16:31:17.243558 TX Vref Scan disable
6871 16:31:17.243657 == TX Byte 0 ==
6872 16:31:17.246877 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6873 16:31:17.253634 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6874 16:31:17.253714 == TX Byte 1 ==
6875 16:31:17.256846 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6876 16:31:17.260121 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6877 16:31:17.263343 ==
6878 16:31:17.266627 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 16:31:17.269860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 16:31:17.269960 ==
6881 16:31:17.270054
6882 16:31:17.270145
6883 16:31:17.273528 TX Vref Scan disable
6884 16:31:17.273626 == TX Byte 0 ==
6885 16:31:17.276800 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6886 16:31:17.283330 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6887 16:31:17.283435 == TX Byte 1 ==
6888 16:31:17.286338 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6889 16:31:17.293320 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6890 16:31:17.293424
6891 16:31:17.293517 [DATLAT]
6892 16:31:17.293606 Freq=400, CH1 RK1
6893 16:31:17.293693
6894 16:31:17.296317 DATLAT Default: 0xe
6895 16:31:17.296412 0, 0xFFFF, sum = 0
6896 16:31:17.299841 1, 0xFFFF, sum = 0
6897 16:31:17.299940 2, 0xFFFF, sum = 0
6898 16:31:17.303119 3, 0xFFFF, sum = 0
6899 16:31:17.306240 4, 0xFFFF, sum = 0
6900 16:31:17.306342 5, 0xFFFF, sum = 0
6901 16:31:17.310067 6, 0xFFFF, sum = 0
6902 16:31:17.310179 7, 0xFFFF, sum = 0
6903 16:31:17.313309 8, 0xFFFF, sum = 0
6904 16:31:17.313408 9, 0xFFFF, sum = 0
6905 16:31:17.316531 10, 0xFFFF, sum = 0
6906 16:31:17.316647 11, 0xFFFF, sum = 0
6907 16:31:17.319880 12, 0xFFFF, sum = 0
6908 16:31:17.319950 13, 0x0, sum = 1
6909 16:31:17.323241 14, 0x0, sum = 2
6910 16:31:17.323339 15, 0x0, sum = 3
6911 16:31:17.326406 16, 0x0, sum = 4
6912 16:31:17.326504 best_step = 14
6913 16:31:17.326590
6914 16:31:17.326678 ==
6915 16:31:17.329668 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 16:31:17.333165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 16:31:17.336417 ==
6918 16:31:17.336519 RX Vref Scan: 0
6919 16:31:17.336630
6920 16:31:17.339573 RX Vref 0 -> 0, step: 1
6921 16:31:17.339667
6922 16:31:17.342903 RX Delay -327 -> 252, step: 8
6923 16:31:17.346162 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6924 16:31:17.352719 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6925 16:31:17.356232 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6926 16:31:17.359916 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6927 16:31:17.363070 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6928 16:31:17.370144 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6929 16:31:17.373310 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6930 16:31:17.376457 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6931 16:31:17.379666 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6932 16:31:17.386730 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6933 16:31:17.389795 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6934 16:31:17.393398 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6935 16:31:17.396399 iDelay=217, Bit 12, Center -16 (-247 ~ 216) 464
6936 16:31:17.403051 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6937 16:31:17.406342 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6938 16:31:17.410103 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6939 16:31:17.410178 ==
6940 16:31:17.413287 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 16:31:17.416534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 16:31:17.419856 ==
6943 16:31:17.419929 DQS Delay:
6944 16:31:17.420022 DQS0 = 32, DQS1 = 40
6945 16:31:17.423136 DQM Delay:
6946 16:31:17.423233 DQM0 = 12, DQM1 = 15
6947 16:31:17.426488 DQ Delay:
6948 16:31:17.426586 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6949 16:31:17.429668 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =12
6950 16:31:17.433341 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6951 16:31:17.436567 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6952 16:31:17.436663
6953 16:31:17.436756
6954 16:31:17.446498 [DQSOSCAuto] RK1, (LSB)MR18= 0xa953, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6955 16:31:17.449752 CH1 RK1: MR19=C0C, MR18=A953
6956 16:31:17.456573 CH1_RK1: MR19=0xC0C, MR18=0xA953, DQSOSC=388, MR23=63, INC=392, DEC=261
6957 16:31:17.456663 [RxdqsGatingPostProcess] freq 400
6958 16:31:17.462808 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6959 16:31:17.466564 best DQS0 dly(2T, 0.5T) = (0, 10)
6960 16:31:17.469903 best DQS1 dly(2T, 0.5T) = (0, 10)
6961 16:31:17.473141 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6962 16:31:17.476411 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6963 16:31:17.479684 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 16:31:17.482917 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 16:31:17.486114 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 16:31:17.489876 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 16:31:17.492929 Pre-setting of DQS Precalculation
6968 16:31:17.495973 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6969 16:31:17.503029 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6970 16:31:17.509261 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6971 16:31:17.512940
6972 16:31:17.513032
6973 16:31:17.513108 [Calibration Summary] 800 Mbps
6974 16:31:17.516186 CH 0, Rank 0
6975 16:31:17.516301 SW Impedance : PASS
6976 16:31:17.519337 DUTY Scan : NO K
6977 16:31:17.522690 ZQ Calibration : PASS
6978 16:31:17.522801 Jitter Meter : NO K
6979 16:31:17.525980 CBT Training : PASS
6980 16:31:17.529758 Write leveling : PASS
6981 16:31:17.529840 RX DQS gating : PASS
6982 16:31:17.532472 RX DQ/DQS(RDDQC) : PASS
6983 16:31:17.536239 TX DQ/DQS : PASS
6984 16:31:17.536322 RX DATLAT : PASS
6985 16:31:17.539576 RX DQ/DQS(Engine): PASS
6986 16:31:17.542691 TX OE : NO K
6987 16:31:17.542790 All Pass.
6988 16:31:17.542869
6989 16:31:17.542971 CH 0, Rank 1
6990 16:31:17.545778 SW Impedance : PASS
6991 16:31:17.549388 DUTY Scan : NO K
6992 16:31:17.549471 ZQ Calibration : PASS
6993 16:31:17.552482 Jitter Meter : NO K
6994 16:31:17.555881 CBT Training : PASS
6995 16:31:17.555957 Write leveling : NO K
6996 16:31:17.559273 RX DQS gating : PASS
6997 16:31:17.559373 RX DQ/DQS(RDDQC) : PASS
6998 16:31:17.562399 TX DQ/DQS : PASS
6999 16:31:17.566045 RX DATLAT : PASS
7000 16:31:17.566122 RX DQ/DQS(Engine): PASS
7001 16:31:17.569171 TX OE : NO K
7002 16:31:17.569253 All Pass.
7003 16:31:17.569319
7004 16:31:17.572397 CH 1, Rank 0
7005 16:31:17.572517 SW Impedance : PASS
7006 16:31:17.576198 DUTY Scan : NO K
7007 16:31:17.579367 ZQ Calibration : PASS
7008 16:31:17.579483 Jitter Meter : NO K
7009 16:31:17.582673 CBT Training : PASS
7010 16:31:17.585912 Write leveling : PASS
7011 16:31:17.586003 RX DQS gating : PASS
7012 16:31:17.589176 RX DQ/DQS(RDDQC) : PASS
7013 16:31:17.592361 TX DQ/DQS : PASS
7014 16:31:17.592443 RX DATLAT : PASS
7015 16:31:17.596091 RX DQ/DQS(Engine): PASS
7016 16:31:17.599148 TX OE : NO K
7017 16:31:17.599230 All Pass.
7018 16:31:17.599295
7019 16:31:17.599355 CH 1, Rank 1
7020 16:31:17.602585 SW Impedance : PASS
7021 16:31:17.605707 DUTY Scan : NO K
7022 16:31:17.605789 ZQ Calibration : PASS
7023 16:31:17.609255 Jitter Meter : NO K
7024 16:31:17.612538 CBT Training : PASS
7025 16:31:17.612689 Write leveling : NO K
7026 16:31:17.615694 RX DQS gating : PASS
7027 16:31:17.615775 RX DQ/DQS(RDDQC) : PASS
7028 16:31:17.619263 TX DQ/DQS : PASS
7029 16:31:17.622562 RX DATLAT : PASS
7030 16:31:17.622644 RX DQ/DQS(Engine): PASS
7031 16:31:17.625855 TX OE : NO K
7032 16:31:17.625936 All Pass.
7033 16:31:17.626001
7034 16:31:17.629080 DramC Write-DBI off
7035 16:31:17.632224 PER_BANK_REFRESH: Hybrid Mode
7036 16:31:17.632317 TX_TRACKING: ON
7037 16:31:17.642338 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7038 16:31:17.645467 [FAST_K] Save calibration result to emmc
7039 16:31:17.649172 dramc_set_vcore_voltage set vcore to 725000
7040 16:31:17.652188 Read voltage for 1600, 0
7041 16:31:17.652297 Vio18 = 0
7042 16:31:17.652372 Vcore = 725000
7043 16:31:17.655555 Vdram = 0
7044 16:31:17.655704 Vddq = 0
7045 16:31:17.655827 Vmddr = 0
7046 16:31:17.662071 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7047 16:31:17.665821 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7048 16:31:17.668936 MEM_TYPE=3, freq_sel=13
7049 16:31:17.671999 sv_algorithm_assistance_LP4_3733
7050 16:31:17.675818 ============ PULL DRAM RESETB DOWN ============
7051 16:31:17.682251 ========== PULL DRAM RESETB DOWN end =========
7052 16:31:17.685419 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7053 16:31:17.688657 ===================================
7054 16:31:17.691832 LPDDR4 DRAM CONFIGURATION
7055 16:31:17.695053 ===================================
7056 16:31:17.695130 EX_ROW_EN[0] = 0x0
7057 16:31:17.698466 EX_ROW_EN[1] = 0x0
7058 16:31:17.698542 LP4Y_EN = 0x0
7059 16:31:17.702084 WORK_FSP = 0x1
7060 16:31:17.702159 WL = 0x5
7061 16:31:17.705364 RL = 0x5
7062 16:31:17.705452 BL = 0x2
7063 16:31:17.708442 RPST = 0x0
7064 16:31:17.708541 RD_PRE = 0x0
7065 16:31:17.711653 WR_PRE = 0x1
7066 16:31:17.711725 WR_PST = 0x1
7067 16:31:17.715337 DBI_WR = 0x0
7068 16:31:17.718332 DBI_RD = 0x0
7069 16:31:17.718407 OTF = 0x1
7070 16:31:17.721799 ===================================
7071 16:31:17.725436 ===================================
7072 16:31:17.725513 ANA top config
7073 16:31:17.728307 ===================================
7074 16:31:17.732052 DLL_ASYNC_EN = 0
7075 16:31:17.735335 ALL_SLAVE_EN = 0
7076 16:31:17.738454 NEW_RANK_MODE = 1
7077 16:31:17.741557 DLL_IDLE_MODE = 1
7078 16:31:17.741632 LP45_APHY_COMB_EN = 1
7079 16:31:17.744897 TX_ODT_DIS = 0
7080 16:31:17.748063 NEW_8X_MODE = 1
7081 16:31:17.751373 ===================================
7082 16:31:17.755093 ===================================
7083 16:31:17.758346 data_rate = 3200
7084 16:31:17.761541 CKR = 1
7085 16:31:17.761616 DQ_P2S_RATIO = 8
7086 16:31:17.764758 ===================================
7087 16:31:17.768369 CA_P2S_RATIO = 8
7088 16:31:17.771502 DQ_CA_OPEN = 0
7089 16:31:17.774726 DQ_SEMI_OPEN = 0
7090 16:31:17.778477 CA_SEMI_OPEN = 0
7091 16:31:17.781812 CA_FULL_RATE = 0
7092 16:31:17.781928 DQ_CKDIV4_EN = 0
7093 16:31:17.784940 CA_CKDIV4_EN = 0
7094 16:31:17.788197 CA_PREDIV_EN = 0
7095 16:31:17.791509 PH8_DLY = 12
7096 16:31:17.794748 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7097 16:31:17.798479 DQ_AAMCK_DIV = 4
7098 16:31:17.798552 CA_AAMCK_DIV = 4
7099 16:31:17.801683 CA_ADMCK_DIV = 4
7100 16:31:17.804926 DQ_TRACK_CA_EN = 0
7101 16:31:17.808049 CA_PICK = 1600
7102 16:31:17.811808 CA_MCKIO = 1600
7103 16:31:17.814943 MCKIO_SEMI = 0
7104 16:31:17.818271 PLL_FREQ = 3068
7105 16:31:17.818357 DQ_UI_PI_RATIO = 32
7106 16:31:17.821289 CA_UI_PI_RATIO = 0
7107 16:31:17.824795 ===================================
7108 16:31:17.828241 ===================================
7109 16:31:17.831853 memory_type:LPDDR4
7110 16:31:17.835115 GP_NUM : 10
7111 16:31:17.835197 SRAM_EN : 1
7112 16:31:17.838323 MD32_EN : 0
7113 16:31:17.841526 ===================================
7114 16:31:17.844673 [ANA_INIT] >>>>>>>>>>>>>>
7115 16:31:17.844755 <<<<<< [CONFIGURE PHASE]: ANA_TX
7116 16:31:17.847966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7117 16:31:17.851316 ===================================
7118 16:31:17.854556 data_rate = 3200,PCW = 0X7600
7119 16:31:17.858263 ===================================
7120 16:31:17.861513 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7121 16:31:17.867956 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 16:31:17.874631 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7123 16:31:17.878271 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7124 16:31:17.881444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7125 16:31:17.884531 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7126 16:31:17.887863 [ANA_INIT] flow start
7127 16:31:17.887945 [ANA_INIT] PLL >>>>>>>>
7128 16:31:17.891652 [ANA_INIT] PLL <<<<<<<<
7129 16:31:17.894981 [ANA_INIT] MIDPI >>>>>>>>
7130 16:31:17.895064 [ANA_INIT] MIDPI <<<<<<<<
7131 16:31:17.898278 [ANA_INIT] DLL >>>>>>>>
7132 16:31:17.901356 [ANA_INIT] DLL <<<<<<<<
7133 16:31:17.901439 [ANA_INIT] flow end
7134 16:31:17.907899 ============ LP4 DIFF to SE enter ============
7135 16:31:17.911199 ============ LP4 DIFF to SE exit ============
7136 16:31:17.914794 [ANA_INIT] <<<<<<<<<<<<<
7137 16:31:17.917849 [Flow] Enable top DCM control >>>>>
7138 16:31:17.921189 [Flow] Enable top DCM control <<<<<
7139 16:31:17.921267 Enable DLL master slave shuffle
7140 16:31:17.928041 ==============================================================
7141 16:31:17.931395 Gating Mode config
7142 16:31:17.934517 ==============================================================
7143 16:31:17.938155 Config description:
7144 16:31:17.947967 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7145 16:31:17.954425 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7146 16:31:17.958127 SELPH_MODE 0: By rank 1: By Phase
7147 16:31:17.964477 ==============================================================
7148 16:31:17.967824 GAT_TRACK_EN = 1
7149 16:31:17.971063 RX_GATING_MODE = 2
7150 16:31:17.974301 RX_GATING_TRACK_MODE = 2
7151 16:31:17.974376 SELPH_MODE = 1
7152 16:31:17.977957 PICG_EARLY_EN = 1
7153 16:31:17.981044 VALID_LAT_VALUE = 1
7154 16:31:17.987900 ==============================================================
7155 16:31:17.991108 Enter into Gating configuration >>>>
7156 16:31:17.994406 Exit from Gating configuration <<<<
7157 16:31:17.997688 Enter into DVFS_PRE_config >>>>>
7158 16:31:18.007750 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7159 16:31:18.010991 Exit from DVFS_PRE_config <<<<<
7160 16:31:18.014184 Enter into PICG configuration >>>>
7161 16:31:18.017761 Exit from PICG configuration <<<<
7162 16:31:18.021050 [RX_INPUT] configuration >>>>>
7163 16:31:18.024300 [RX_INPUT] configuration <<<<<
7164 16:31:18.027494 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7165 16:31:18.034317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7166 16:31:18.041110 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7167 16:31:18.047368 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7168 16:31:18.051326 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 16:31:18.057611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 16:31:18.061397 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7171 16:31:18.067783 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7172 16:31:18.071032 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7173 16:31:18.074236 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7174 16:31:18.078039 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7175 16:31:18.084272 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7176 16:31:18.087432 ===================================
7177 16:31:18.087539 LPDDR4 DRAM CONFIGURATION
7178 16:31:18.090988 ===================================
7179 16:31:18.094195 EX_ROW_EN[0] = 0x0
7180 16:31:18.097499 EX_ROW_EN[1] = 0x0
7181 16:31:18.097573 LP4Y_EN = 0x0
7182 16:31:18.100786 WORK_FSP = 0x1
7183 16:31:18.100885 WL = 0x5
7184 16:31:18.104447 RL = 0x5
7185 16:31:18.104551 BL = 0x2
7186 16:31:18.107809 RPST = 0x0
7187 16:31:18.107885 RD_PRE = 0x0
7188 16:31:18.111027 WR_PRE = 0x1
7189 16:31:18.111127 WR_PST = 0x1
7190 16:31:18.114314 DBI_WR = 0x0
7191 16:31:18.114386 DBI_RD = 0x0
7192 16:31:18.117523 OTF = 0x1
7193 16:31:18.120812 ===================================
7194 16:31:18.124409 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7195 16:31:18.127537 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7196 16:31:18.134594 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7197 16:31:18.137852 ===================================
7198 16:31:18.137960 LPDDR4 DRAM CONFIGURATION
7199 16:31:18.140813 ===================================
7200 16:31:18.144382 EX_ROW_EN[0] = 0x10
7201 16:31:18.144479 EX_ROW_EN[1] = 0x0
7202 16:31:18.147905 LP4Y_EN = 0x0
7203 16:31:18.150910 WORK_FSP = 0x1
7204 16:31:18.151021 WL = 0x5
7205 16:31:18.154365 RL = 0x5
7206 16:31:18.154469 BL = 0x2
7207 16:31:18.157870 RPST = 0x0
7208 16:31:18.157954 RD_PRE = 0x0
7209 16:31:18.161050 WR_PRE = 0x1
7210 16:31:18.161164 WR_PST = 0x1
7211 16:31:18.164148 DBI_WR = 0x0
7212 16:31:18.164231 DBI_RD = 0x0
7213 16:31:18.167433 OTF = 0x1
7214 16:31:18.171145 ===================================
7215 16:31:18.177696 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7216 16:31:18.177830 ==
7217 16:31:18.180894 Dram Type= 6, Freq= 0, CH_0, rank 0
7218 16:31:18.184155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7219 16:31:18.184240 ==
7220 16:31:18.187494 [Duty_Offset_Calibration]
7221 16:31:18.187603 B0:2 B1:0 CA:1
7222 16:31:18.187697
7223 16:31:18.191072 [DutyScan_Calibration_Flow] k_type=0
7224 16:31:18.200363
7225 16:31:18.200472 ==CLK 0==
7226 16:31:18.203491 Final CLK duty delay cell = -4
7227 16:31:18.206635 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7228 16:31:18.209992 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7229 16:31:18.213760 [-4] AVG Duty = 4906%(X100)
7230 16:31:18.213843
7231 16:31:18.217059 CH0 CLK Duty spec in!! Max-Min= 187%
7232 16:31:18.220266 [DutyScan_Calibration_Flow] ====Done====
7233 16:31:18.220375
7234 16:31:18.223540 [DutyScan_Calibration_Flow] k_type=1
7235 16:31:18.239413
7236 16:31:18.239498 ==DQS 0 ==
7237 16:31:18.243089 Final DQS duty delay cell = 0
7238 16:31:18.246119 [0] MAX Duty = 5249%(X100), DQS PI = 36
7239 16:31:18.249847 [0] MIN Duty = 4938%(X100), DQS PI = 62
7240 16:31:18.252711 [0] AVG Duty = 5093%(X100)
7241 16:31:18.252793
7242 16:31:18.252856 ==DQS 1 ==
7243 16:31:18.256108 Final DQS duty delay cell = -4
7244 16:31:18.259715 [-4] MAX Duty = 5094%(X100), DQS PI = 30
7245 16:31:18.262729 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7246 16:31:18.266085 [-4] AVG Duty = 4969%(X100)
7247 16:31:18.266201
7248 16:31:18.269598 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7249 16:31:18.269676
7250 16:31:18.272434 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7251 16:31:18.276174 [DutyScan_Calibration_Flow] ====Done====
7252 16:31:18.276249
7253 16:31:18.279461 [DutyScan_Calibration_Flow] k_type=3
7254 16:31:18.297093
7255 16:31:18.297186 ==DQM 0 ==
7256 16:31:18.300135 Final DQM duty delay cell = 0
7257 16:31:18.303998 [0] MAX Duty = 5093%(X100), DQS PI = 26
7258 16:31:18.306785 [0] MIN Duty = 4813%(X100), DQS PI = 2
7259 16:31:18.306867 [0] AVG Duty = 4953%(X100)
7260 16:31:18.310575
7261 16:31:18.310682 ==DQM 1 ==
7262 16:31:18.313964 Final DQM duty delay cell = 0
7263 16:31:18.317177 [0] MAX Duty = 5249%(X100), DQS PI = 44
7264 16:31:18.320480 [0] MIN Duty = 5000%(X100), DQS PI = 20
7265 16:31:18.320614 [0] AVG Duty = 5124%(X100)
7266 16:31:18.323684
7267 16:31:18.326970 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7268 16:31:18.327047
7269 16:31:18.330559 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7270 16:31:18.333779 [DutyScan_Calibration_Flow] ====Done====
7271 16:31:18.333865
7272 16:31:18.336987 [DutyScan_Calibration_Flow] k_type=2
7273 16:31:18.354401
7274 16:31:18.354483 ==DQ 0 ==
7275 16:31:18.357484 Final DQ duty delay cell = 0
7276 16:31:18.360545 [0] MAX Duty = 5124%(X100), DQS PI = 34
7277 16:31:18.364281 [0] MIN Duty = 4969%(X100), DQS PI = 16
7278 16:31:18.364357 [0] AVG Duty = 5046%(X100)
7279 16:31:18.367378
7280 16:31:18.367460 ==DQ 1 ==
7281 16:31:18.370471 Final DQ duty delay cell = 0
7282 16:31:18.374015 [0] MAX Duty = 4969%(X100), DQS PI = 50
7283 16:31:18.377164 [0] MIN Duty = 4875%(X100), DQS PI = 0
7284 16:31:18.377256 [0] AVG Duty = 4922%(X100)
7285 16:31:18.377340
7286 16:31:18.381003 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7287 16:31:18.384238
7288 16:31:18.387546 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7289 16:31:18.390824 [DutyScan_Calibration_Flow] ====Done====
7290 16:31:18.390905 ==
7291 16:31:18.394109 Dram Type= 6, Freq= 0, CH_1, rank 0
7292 16:31:18.397269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7293 16:31:18.397343 ==
7294 16:31:18.400465 [Duty_Offset_Calibration]
7295 16:31:18.400541 B0:0 B1:-1 CA:2
7296 16:31:18.400643
7297 16:31:18.403756 [DutyScan_Calibration_Flow] k_type=0
7298 16:31:18.414423
7299 16:31:18.414535 ==CLK 0==
7300 16:31:18.417717 Final CLK duty delay cell = 0
7301 16:31:18.421001 [0] MAX Duty = 5156%(X100), DQS PI = 10
7302 16:31:18.424153 [0] MIN Duty = 4906%(X100), DQS PI = 46
7303 16:31:18.424251 [0] AVG Duty = 5031%(X100)
7304 16:31:18.427501
7305 16:31:18.430829 CH1 CLK Duty spec in!! Max-Min= 250%
7306 16:31:18.434523 [DutyScan_Calibration_Flow] ====Done====
7307 16:31:18.434637
7308 16:31:18.437407 [DutyScan_Calibration_Flow] k_type=1
7309 16:31:18.454122
7310 16:31:18.454243 ==DQS 0 ==
7311 16:31:18.457337 Final DQS duty delay cell = 0
7312 16:31:18.460432 [0] MAX Duty = 5093%(X100), DQS PI = 24
7313 16:31:18.463758 [0] MIN Duty = 4969%(X100), DQS PI = 0
7314 16:31:18.467431 [0] AVG Duty = 5031%(X100)
7315 16:31:18.467537
7316 16:31:18.467613 ==DQS 1 ==
7317 16:31:18.470549 Final DQS duty delay cell = 0
7318 16:31:18.474131 [0] MAX Duty = 5187%(X100), DQS PI = 62
7319 16:31:18.477113 [0] MIN Duty = 4844%(X100), DQS PI = 34
7320 16:31:18.480447 [0] AVG Duty = 5015%(X100)
7321 16:31:18.480588
7322 16:31:18.483595 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7323 16:31:18.483672
7324 16:31:18.486896 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7325 16:31:18.490647 [DutyScan_Calibration_Flow] ====Done====
7326 16:31:18.490751
7327 16:31:18.493436 [DutyScan_Calibration_Flow] k_type=3
7328 16:31:18.511364
7329 16:31:18.511455 ==DQM 0 ==
7330 16:31:18.515128 Final DQM duty delay cell = 4
7331 16:31:18.518458 [4] MAX Duty = 5125%(X100), DQS PI = 8
7332 16:31:18.521657 [4] MIN Duty = 4969%(X100), DQS PI = 32
7333 16:31:18.521730 [4] AVG Duty = 5047%(X100)
7334 16:31:18.524980
7335 16:31:18.525060 ==DQM 1 ==
7336 16:31:18.528176 Final DQM duty delay cell = 0
7337 16:31:18.531412 [0] MAX Duty = 5281%(X100), DQS PI = 58
7338 16:31:18.535053 [0] MIN Duty = 4876%(X100), DQS PI = 34
7339 16:31:18.538330 [0] AVG Duty = 5078%(X100)
7340 16:31:18.538484
7341 16:31:18.541264 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7342 16:31:18.541351
7343 16:31:18.545027 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7344 16:31:18.548263 [DutyScan_Calibration_Flow] ====Done====
7345 16:31:18.548392
7346 16:31:18.551489 [DutyScan_Calibration_Flow] k_type=2
7347 16:31:18.568779
7348 16:31:18.568880 ==DQ 0 ==
7349 16:31:18.572039 Final DQ duty delay cell = 0
7350 16:31:18.575085 [0] MAX Duty = 5062%(X100), DQS PI = 20
7351 16:31:18.578733 [0] MIN Duty = 4969%(X100), DQS PI = 0
7352 16:31:18.578817 [0] AVG Duty = 5015%(X100)
7353 16:31:18.578886
7354 16:31:18.582090 ==DQ 1 ==
7355 16:31:18.585108 Final DQ duty delay cell = 0
7356 16:31:18.588331 [0] MAX Duty = 5062%(X100), DQS PI = 2
7357 16:31:18.592157 [0] MIN Duty = 4813%(X100), DQS PI = 32
7358 16:31:18.592236 [0] AVG Duty = 4937%(X100)
7359 16:31:18.592301
7360 16:31:18.594941 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7361 16:31:18.595038
7362 16:31:18.598630 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7363 16:31:18.605000 [DutyScan_Calibration_Flow] ====Done====
7364 16:31:18.608129 nWR fixed to 30
7365 16:31:18.608235 [ModeRegInit_LP4] CH0 RK0
7366 16:31:18.611838 [ModeRegInit_LP4] CH0 RK1
7367 16:31:18.614909 [ModeRegInit_LP4] CH1 RK0
7368 16:31:18.614989 [ModeRegInit_LP4] CH1 RK1
7369 16:31:18.618124 match AC timing 5
7370 16:31:18.621385 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7371 16:31:18.624738 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7372 16:31:18.631612 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7373 16:31:18.634910 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7374 16:31:18.641358 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7375 16:31:18.641438 [MiockJmeterHQA]
7376 16:31:18.641501
7377 16:31:18.644458 [DramcMiockJmeter] u1RxGatingPI = 0
7378 16:31:18.648067 0 : 4260, 4031
7379 16:31:18.648147 4 : 4252, 4027
7380 16:31:18.648210 8 : 4255, 4030
7381 16:31:18.651178 12 : 4368, 4137
7382 16:31:18.651252 16 : 4255, 4029
7383 16:31:18.654295 20 : 4252, 4027
7384 16:31:18.654369 24 : 4252, 4027
7385 16:31:18.657924 28 : 4366, 4139
7386 16:31:18.657994 32 : 4363, 4137
7387 16:31:18.660963 36 : 4363, 4137
7388 16:31:18.661039 40 : 4252, 4027
7389 16:31:18.661102 44 : 4252, 4027
7390 16:31:18.664474 48 : 4363, 4138
7391 16:31:18.664566 52 : 4253, 4027
7392 16:31:18.667729 56 : 4366, 4140
7393 16:31:18.667811 60 : 4250, 4027
7394 16:31:18.671288 64 : 4363, 4140
7395 16:31:18.671372 68 : 4250, 4027
7396 16:31:18.674381 72 : 4252, 4029
7397 16:31:18.674467 76 : 4360, 4137
7398 16:31:18.674558 80 : 4253, 4027
7399 16:31:18.677624 84 : 4361, 4138
7400 16:31:18.677745 88 : 4363, 3901
7401 16:31:18.680876 92 : 4250, 0
7402 16:31:18.681003 96 : 4361, 0
7403 16:31:18.681114 100 : 4250, 0
7404 16:31:18.684340 104 : 4249, 0
7405 16:31:18.684468 108 : 4252, 0
7406 16:31:18.687529 112 : 4250, 0
7407 16:31:18.687614 116 : 4250, 0
7408 16:31:18.687681 120 : 4252, 0
7409 16:31:18.690792 124 : 4361, 0
7410 16:31:18.690880 128 : 4252, 0
7411 16:31:18.694016 132 : 4252, 0
7412 16:31:18.694102 136 : 4252, 0
7413 16:31:18.694170 140 : 4360, 0
7414 16:31:18.697327 144 : 4250, 0
7415 16:31:18.697413 148 : 4250, 0
7416 16:31:18.701068 152 : 4250, 0
7417 16:31:18.701155 156 : 4250, 0
7418 16:31:18.701222 160 : 4253, 0
7419 16:31:18.704297 164 : 4250, 0
7420 16:31:18.704375 168 : 4250, 0
7421 16:31:18.707465 172 : 4255, 0
7422 16:31:18.707543 176 : 4361, 0
7423 16:31:18.707609 180 : 4250, 0
7424 16:31:18.710938 184 : 4250, 0
7425 16:31:18.711016 188 : 4250, 0
7426 16:31:18.711082 192 : 4360, 0
7427 16:31:18.714585 196 : 4250, 0
7428 16:31:18.714658 200 : 4250, 2
7429 16:31:18.717675 204 : 4250, 2667
7430 16:31:18.717760 208 : 4250, 4026
7431 16:31:18.720765 212 : 4255, 4032
7432 16:31:18.720851 216 : 4252, 4029
7433 16:31:18.723975 220 : 4363, 4139
7434 16:31:18.724060 224 : 4250, 4026
7435 16:31:18.724127 228 : 4253, 4029
7436 16:31:18.727766 232 : 4250, 4027
7437 16:31:18.727852 236 : 4363, 4140
7438 16:31:18.731056 240 : 4360, 4138
7439 16:31:18.731141 244 : 4250, 4027
7440 16:31:18.734279 248 : 4252, 4029
7441 16:31:18.734365 252 : 4253, 4029
7442 16:31:18.737671 256 : 4250, 4027
7443 16:31:18.737757 260 : 4250, 4027
7444 16:31:18.740775 264 : 4253, 4029
7445 16:31:18.740860 268 : 4250, 4027
7446 16:31:18.744092 272 : 4363, 4139
7447 16:31:18.744210 276 : 4250, 4026
7448 16:31:18.747249 280 : 4250, 4027
7449 16:31:18.747366 284 : 4250, 4027
7450 16:31:18.747473 288 : 4363, 4139
7451 16:31:18.750954 292 : 4360, 4138
7452 16:31:18.751031 296 : 4248, 4025
7453 16:31:18.754102 300 : 4363, 4140
7454 16:31:18.754177 304 : 4253, 4029
7455 16:31:18.757351 308 : 4250, 4027
7456 16:31:18.757437 312 : 4252, 3969
7457 16:31:18.760487 316 : 4253, 1982
7458 16:31:18.760606
7459 16:31:18.760705 MIOCK jitter meter ch=0
7460 16:31:18.764164
7461 16:31:18.764276 1T = (316-92) = 224 dly cells
7462 16:31:18.770440 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7463 16:31:18.770526 ==
7464 16:31:18.774135 Dram Type= 6, Freq= 0, CH_0, rank 0
7465 16:31:18.777062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7466 16:31:18.777141 ==
7467 16:31:18.783928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7468 16:31:18.787136 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7469 16:31:18.793813 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7470 16:31:18.797428 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7471 16:31:18.807346 [CA 0] Center 42 (12~72) winsize 61
7472 16:31:18.810652 [CA 1] Center 42 (12~72) winsize 61
7473 16:31:18.813822 [CA 2] Center 37 (7~67) winsize 61
7474 16:31:18.817011 [CA 3] Center 37 (7~67) winsize 61
7475 16:31:18.820243 [CA 4] Center 36 (6~66) winsize 61
7476 16:31:18.823865 [CA 5] Center 35 (5~65) winsize 61
7477 16:31:18.823953
7478 16:31:18.827118 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7479 16:31:18.827209
7480 16:31:18.830532 [CATrainingPosCal] consider 1 rank data
7481 16:31:18.833792 u2DelayCellTimex100 = 290/100 ps
7482 16:31:18.836893 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7483 16:31:18.843806 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7484 16:31:18.847071 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7485 16:31:18.850347 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7486 16:31:18.853545 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7487 16:31:18.857176 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7488 16:31:18.857305
7489 16:31:18.860386 CA PerBit enable=1, Macro0, CA PI delay=35
7490 16:31:18.860518
7491 16:31:18.863656 [CBTSetCACLKResult] CA Dly = 35
7492 16:31:18.866941 CS Dly: 9 (0~40)
7493 16:31:18.870478 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7494 16:31:18.873570 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7495 16:31:18.873661 ==
7496 16:31:18.876923 Dram Type= 6, Freq= 0, CH_0, rank 1
7497 16:31:18.880629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7498 16:31:18.880714 ==
7499 16:31:18.886752 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7500 16:31:18.890374 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7501 16:31:18.896942 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7502 16:31:18.900172 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7503 16:31:18.910455 [CA 0] Center 43 (13~73) winsize 61
7504 16:31:18.913693 [CA 1] Center 43 (13~73) winsize 61
7505 16:31:18.916915 [CA 2] Center 38 (8~68) winsize 61
7506 16:31:18.920467 [CA 3] Center 38 (8~68) winsize 61
7507 16:31:18.923695 [CA 4] Center 36 (6~66) winsize 61
7508 16:31:18.926843 [CA 5] Center 36 (6~66) winsize 61
7509 16:31:18.926927
7510 16:31:18.930114 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7511 16:31:18.930215
7512 16:31:18.933466 [CATrainingPosCal] consider 2 rank data
7513 16:31:18.936716 u2DelayCellTimex100 = 290/100 ps
7514 16:31:18.939974 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7515 16:31:18.946962 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7516 16:31:18.950202 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7517 16:31:18.953360 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7518 16:31:18.957040 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7519 16:31:18.960165 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7520 16:31:18.960284
7521 16:31:18.963387 CA PerBit enable=1, Macro0, CA PI delay=35
7522 16:31:18.963468
7523 16:31:18.966546 [CBTSetCACLKResult] CA Dly = 35
7524 16:31:18.969771 CS Dly: 10 (0~43)
7525 16:31:18.973395 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7526 16:31:18.976881 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7527 16:31:18.976958
7528 16:31:18.979978 ----->DramcWriteLeveling(PI) begin...
7529 16:31:18.980062 ==
7530 16:31:18.983245 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 16:31:18.986893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 16:31:18.989816 ==
7533 16:31:18.993581 Write leveling (Byte 0): 38 => 38
7534 16:31:18.993664 Write leveling (Byte 1): 32 => 32
7535 16:31:18.996798 DramcWriteLeveling(PI) end<-----
7536 16:31:18.996884
7537 16:31:18.996953 ==
7538 16:31:18.999882 Dram Type= 6, Freq= 0, CH_0, rank 0
7539 16:31:19.006908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 16:31:19.006999 ==
7541 16:31:19.010174 [Gating] SW mode calibration
7542 16:31:19.016538 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7543 16:31:19.019850 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7544 16:31:19.026678 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7545 16:31:19.029860 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7546 16:31:19.033386 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7547 16:31:19.039864 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7548 16:31:19.043132 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7549 16:31:19.046827 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7550 16:31:19.050113 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7551 16:31:19.056592 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7552 16:31:19.059800 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7553 16:31:19.063280 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 16:31:19.070025 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
7555 16:31:19.073273 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7556 16:31:19.076532 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7557 16:31:19.083282 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
7558 16:31:19.086531 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 16:31:19.089791 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 16:31:19.096360 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 16:31:19.099607 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 16:31:19.103285 1 6 8 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7563 16:31:19.109660 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7564 16:31:19.112840 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (1 1) (0 0)
7565 16:31:19.116810 1 6 20 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
7566 16:31:19.123226 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 16:31:19.126818 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 16:31:19.129902 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 16:31:19.136364 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 16:31:19.139524 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 16:31:19.143301 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 16:31:19.149834 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7573 16:31:19.153104 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7574 16:31:19.156303 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7575 16:31:19.162994 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 16:31:19.166725 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 16:31:19.169766 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 16:31:19.173046 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 16:31:19.179397 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 16:31:19.182712 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 16:31:19.186254 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 16:31:19.192458 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 16:31:19.196281 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 16:31:19.199187 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 16:31:19.206114 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 16:31:19.209348 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7587 16:31:19.212651 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7588 16:31:19.219103 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7589 16:31:19.222391 Total UI for P1: 0, mck2ui 16
7590 16:31:19.225939 best dqsien dly found for B0: ( 1, 9, 10)
7591 16:31:19.229016 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7592 16:31:19.232511 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7593 16:31:19.236053 Total UI for P1: 0, mck2ui 16
7594 16:31:19.239211 best dqsien dly found for B1: ( 1, 9, 18)
7595 16:31:19.242289 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7596 16:31:19.245558 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7597 16:31:19.248771
7598 16:31:19.252087 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7599 16:31:19.255528 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7600 16:31:19.259161 [Gating] SW calibration Done
7601 16:31:19.259247 ==
7602 16:31:19.262464 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 16:31:19.265781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 16:31:19.265910 ==
7605 16:31:19.268804 RX Vref Scan: 0
7606 16:31:19.268917
7607 16:31:19.269032 RX Vref 0 -> 0, step: 1
7608 16:31:19.269136
7609 16:31:19.271945 RX Delay 0 -> 252, step: 8
7610 16:31:19.275406 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7611 16:31:19.278659 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7612 16:31:19.285117 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7613 16:31:19.288391 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7614 16:31:19.292036 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7615 16:31:19.295129 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7616 16:31:19.298360 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7617 16:31:19.304932 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7618 16:31:19.308569 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7619 16:31:19.311932 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7620 16:31:19.315103 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7621 16:31:19.318367 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7622 16:31:19.324832 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7623 16:31:19.328463 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7624 16:31:19.331636 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7625 16:31:19.334935 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7626 16:31:19.335026 ==
7627 16:31:19.338103 Dram Type= 6, Freq= 0, CH_0, rank 0
7628 16:31:19.344919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7629 16:31:19.345012 ==
7630 16:31:19.345085 DQS Delay:
7631 16:31:19.348191 DQS0 = 0, DQS1 = 0
7632 16:31:19.348270 DQM Delay:
7633 16:31:19.348334 DQM0 = 138, DQM1 = 126
7634 16:31:19.351494 DQ Delay:
7635 16:31:19.354643 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7636 16:31:19.358399 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7637 16:31:19.361594 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
7638 16:31:19.364939 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7639 16:31:19.365026
7640 16:31:19.365097
7641 16:31:19.365193 ==
7642 16:31:19.368245 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 16:31:19.371410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 16:31:19.375000 ==
7645 16:31:19.375115
7646 16:31:19.375218
7647 16:31:19.375322 TX Vref Scan disable
7648 16:31:19.378138 == TX Byte 0 ==
7649 16:31:19.381322 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7650 16:31:19.384675 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7651 16:31:19.388447 == TX Byte 1 ==
7652 16:31:19.391700 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7653 16:31:19.394899 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7654 16:31:19.395023 ==
7655 16:31:19.398433 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 16:31:19.404673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 16:31:19.404760 ==
7658 16:31:19.417317
7659 16:31:19.420470 TX Vref early break, caculate TX vref
7660 16:31:19.423797 TX Vref=16, minBit 6, minWin=22, winSum=374
7661 16:31:19.427155 TX Vref=18, minBit 6, minWin=23, winSum=386
7662 16:31:19.430265 TX Vref=20, minBit 4, minWin=24, winSum=395
7663 16:31:19.433904 TX Vref=22, minBit 7, minWin=24, winSum=407
7664 16:31:19.437225 TX Vref=24, minBit 2, minWin=25, winSum=419
7665 16:31:19.443935 TX Vref=26, minBit 12, minWin=25, winSum=426
7666 16:31:19.447262 TX Vref=28, minBit 12, minWin=25, winSum=428
7667 16:31:19.450450 TX Vref=30, minBit 0, minWin=26, winSum=423
7668 16:31:19.453643 TX Vref=32, minBit 2, minWin=25, winSum=417
7669 16:31:19.456988 TX Vref=34, minBit 0, minWin=25, winSum=405
7670 16:31:19.463685 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
7671 16:31:19.463778
7672 16:31:19.466993 Final TX Range 0 Vref 30
7673 16:31:19.467098
7674 16:31:19.467194 ==
7675 16:31:19.470159 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 16:31:19.473393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 16:31:19.473501 ==
7678 16:31:19.473597
7679 16:31:19.473692
7680 16:31:19.477047 TX Vref Scan disable
7681 16:31:19.483361 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7682 16:31:19.483478 == TX Byte 0 ==
7683 16:31:19.486482 u2DelayCellOfst[0]=13 cells (4 PI)
7684 16:31:19.489805 u2DelayCellOfst[1]=20 cells (6 PI)
7685 16:31:19.493455 u2DelayCellOfst[2]=13 cells (4 PI)
7686 16:31:19.496666 u2DelayCellOfst[3]=13 cells (4 PI)
7687 16:31:19.499867 u2DelayCellOfst[4]=10 cells (3 PI)
7688 16:31:19.503419 u2DelayCellOfst[5]=0 cells (0 PI)
7689 16:31:19.506582 u2DelayCellOfst[6]=20 cells (6 PI)
7690 16:31:19.510662 u2DelayCellOfst[7]=16 cells (5 PI)
7691 16:31:19.513232 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7692 16:31:19.516391 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7693 16:31:19.519643 == TX Byte 1 ==
7694 16:31:19.522911 u2DelayCellOfst[8]=0 cells (0 PI)
7695 16:31:19.522989 u2DelayCellOfst[9]=0 cells (0 PI)
7696 16:31:19.526586 u2DelayCellOfst[10]=6 cells (2 PI)
7697 16:31:19.529785 u2DelayCellOfst[11]=3 cells (1 PI)
7698 16:31:19.532953 u2DelayCellOfst[12]=13 cells (4 PI)
7699 16:31:19.536565 u2DelayCellOfst[13]=10 cells (3 PI)
7700 16:31:19.539934 u2DelayCellOfst[14]=13 cells (4 PI)
7701 16:31:19.543342 u2DelayCellOfst[15]=10 cells (3 PI)
7702 16:31:19.546372 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7703 16:31:19.553046 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7704 16:31:19.553142 DramC Write-DBI on
7705 16:31:19.553210 ==
7706 16:31:19.556401 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 16:31:19.562802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 16:31:19.562891 ==
7709 16:31:19.562974
7710 16:31:19.563042
7711 16:31:19.563107 TX Vref Scan disable
7712 16:31:19.566654 == TX Byte 0 ==
7713 16:31:19.569897 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7714 16:31:19.573234 == TX Byte 1 ==
7715 16:31:19.577167 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7716 16:31:19.577243 DramC Write-DBI off
7717 16:31:19.580238
7718 16:31:19.580342 [DATLAT]
7719 16:31:19.580434 Freq=1600, CH0 RK0
7720 16:31:19.580524
7721 16:31:19.583471 DATLAT Default: 0xf
7722 16:31:19.583581 0, 0xFFFF, sum = 0
7723 16:31:19.587139 1, 0xFFFF, sum = 0
7724 16:31:19.587225 2, 0xFFFF, sum = 0
7725 16:31:19.590261 3, 0xFFFF, sum = 0
7726 16:31:19.590346 4, 0xFFFF, sum = 0
7727 16:31:19.593428 5, 0xFFFF, sum = 0
7728 16:31:19.596649 6, 0xFFFF, sum = 0
7729 16:31:19.596733 7, 0xFFFF, sum = 0
7730 16:31:19.600078 8, 0xFFFF, sum = 0
7731 16:31:19.600165 9, 0xFFFF, sum = 0
7732 16:31:19.603246 10, 0xFFFF, sum = 0
7733 16:31:19.603351 11, 0xFFFF, sum = 0
7734 16:31:19.606853 12, 0xFFFF, sum = 0
7735 16:31:19.606928 13, 0xFFFF, sum = 0
7736 16:31:19.609793 14, 0x0, sum = 1
7737 16:31:19.609870 15, 0x0, sum = 2
7738 16:31:19.613502 16, 0x0, sum = 3
7739 16:31:19.613588 17, 0x0, sum = 4
7740 16:31:19.616639 best_step = 15
7741 16:31:19.616723
7742 16:31:19.616789 ==
7743 16:31:19.620273 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 16:31:19.623556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 16:31:19.623662 ==
7746 16:31:19.623731 RX Vref Scan: 1
7747 16:31:19.626901
7748 16:31:19.626986 Set Vref Range= 24 -> 127
7749 16:31:19.627059
7750 16:31:19.630007 RX Vref 24 -> 127, step: 1
7751 16:31:19.630091
7752 16:31:19.633535 RX Delay 19 -> 252, step: 4
7753 16:31:19.633619
7754 16:31:19.636736 Set Vref, RX VrefLevel [Byte0]: 24
7755 16:31:19.639986 [Byte1]: 24
7756 16:31:19.640092
7757 16:31:19.643283 Set Vref, RX VrefLevel [Byte0]: 25
7758 16:31:19.646591 [Byte1]: 25
7759 16:31:19.646676
7760 16:31:19.649746 Set Vref, RX VrefLevel [Byte0]: 26
7761 16:31:19.653424 [Byte1]: 26
7762 16:31:19.657078
7763 16:31:19.657161 Set Vref, RX VrefLevel [Byte0]: 27
7764 16:31:19.660326 [Byte1]: 27
7765 16:31:19.664570
7766 16:31:19.664668 Set Vref, RX VrefLevel [Byte0]: 28
7767 16:31:19.667957 [Byte1]: 28
7768 16:31:19.672219
7769 16:31:19.672301 Set Vref, RX VrefLevel [Byte0]: 29
7770 16:31:19.675487 [Byte1]: 29
7771 16:31:19.679852
7772 16:31:19.679941 Set Vref, RX VrefLevel [Byte0]: 30
7773 16:31:19.683023 [Byte1]: 30
7774 16:31:19.687399
7775 16:31:19.687484 Set Vref, RX VrefLevel [Byte0]: 31
7776 16:31:19.690970 [Byte1]: 31
7777 16:31:19.695080
7778 16:31:19.695162 Set Vref, RX VrefLevel [Byte0]: 32
7779 16:31:19.698012 [Byte1]: 32
7780 16:31:19.702349
7781 16:31:19.702431 Set Vref, RX VrefLevel [Byte0]: 33
7782 16:31:19.706067 [Byte1]: 33
7783 16:31:19.710287
7784 16:31:19.710370 Set Vref, RX VrefLevel [Byte0]: 34
7785 16:31:19.713307 [Byte1]: 34
7786 16:31:19.717426
7787 16:31:19.717545 Set Vref, RX VrefLevel [Byte0]: 35
7788 16:31:19.721116 [Byte1]: 35
7789 16:31:19.725289
7790 16:31:19.725372 Set Vref, RX VrefLevel [Byte0]: 36
7791 16:31:19.728466 [Byte1]: 36
7792 16:31:19.732777
7793 16:31:19.732859 Set Vref, RX VrefLevel [Byte0]: 37
7794 16:31:19.735966 [Byte1]: 37
7795 16:31:19.740179
7796 16:31:19.740267 Set Vref, RX VrefLevel [Byte0]: 38
7797 16:31:19.744022 [Byte1]: 38
7798 16:31:19.747809
7799 16:31:19.747892 Set Vref, RX VrefLevel [Byte0]: 39
7800 16:31:19.751140 [Byte1]: 39
7801 16:31:19.755385
7802 16:31:19.755472 Set Vref, RX VrefLevel [Byte0]: 40
7803 16:31:19.758611 [Byte1]: 40
7804 16:31:19.763200
7805 16:31:19.763280 Set Vref, RX VrefLevel [Byte0]: 41
7806 16:31:19.766533 [Byte1]: 41
7807 16:31:19.770864
7808 16:31:19.770940 Set Vref, RX VrefLevel [Byte0]: 42
7809 16:31:19.774074 [Byte1]: 42
7810 16:31:19.778380
7811 16:31:19.778493 Set Vref, RX VrefLevel [Byte0]: 43
7812 16:31:19.781428 [Byte1]: 43
7813 16:31:19.785671
7814 16:31:19.785780 Set Vref, RX VrefLevel [Byte0]: 44
7815 16:31:19.788963 [Byte1]: 44
7816 16:31:19.793081
7817 16:31:19.793161 Set Vref, RX VrefLevel [Byte0]: 45
7818 16:31:19.796746 [Byte1]: 45
7819 16:31:19.800941
7820 16:31:19.801020 Set Vref, RX VrefLevel [Byte0]: 46
7821 16:31:19.804450 [Byte1]: 46
7822 16:31:19.808304
7823 16:31:19.808385 Set Vref, RX VrefLevel [Byte0]: 47
7824 16:31:19.812019 [Byte1]: 47
7825 16:31:19.816084
7826 16:31:19.816163 Set Vref, RX VrefLevel [Byte0]: 48
7827 16:31:19.819199 [Byte1]: 48
7828 16:31:19.823461
7829 16:31:19.823546 Set Vref, RX VrefLevel [Byte0]: 49
7830 16:31:19.826668 [Byte1]: 49
7831 16:31:19.831444
7832 16:31:19.831517 Set Vref, RX VrefLevel [Byte0]: 50
7833 16:31:19.834808 [Byte1]: 50
7834 16:31:19.838566
7835 16:31:19.838641 Set Vref, RX VrefLevel [Byte0]: 51
7836 16:31:19.842325 [Byte1]: 51
7837 16:31:19.846538
7838 16:31:19.846613 Set Vref, RX VrefLevel [Byte0]: 52
7839 16:31:19.849794 [Byte1]: 52
7840 16:31:19.854159
7841 16:31:19.854241 Set Vref, RX VrefLevel [Byte0]: 53
7842 16:31:19.857451 [Byte1]: 53
7843 16:31:19.861644
7844 16:31:19.861730 Set Vref, RX VrefLevel [Byte0]: 54
7845 16:31:19.864739 [Byte1]: 54
7846 16:31:19.869175
7847 16:31:19.869256 Set Vref, RX VrefLevel [Byte0]: 55
7848 16:31:19.872429 [Byte1]: 55
7849 16:31:19.876777
7850 16:31:19.876960 Set Vref, RX VrefLevel [Byte0]: 56
7851 16:31:19.880176 [Byte1]: 56
7852 16:31:19.883965
7853 16:31:19.884105 Set Vref, RX VrefLevel [Byte0]: 57
7854 16:31:19.887585 [Byte1]: 57
7855 16:31:19.891816
7856 16:31:19.891892 Set Vref, RX VrefLevel [Byte0]: 58
7857 16:31:19.895010 [Byte1]: 58
7858 16:31:19.899253
7859 16:31:19.899336 Set Vref, RX VrefLevel [Byte0]: 59
7860 16:31:19.902907 [Byte1]: 59
7861 16:31:19.907091
7862 16:31:19.907173 Set Vref, RX VrefLevel [Byte0]: 60
7863 16:31:19.910193 [Byte1]: 60
7864 16:31:19.914468
7865 16:31:19.914551 Set Vref, RX VrefLevel [Byte0]: 61
7866 16:31:19.917624 [Byte1]: 61
7867 16:31:19.921984
7868 16:31:19.922067 Set Vref, RX VrefLevel [Byte0]: 62
7869 16:31:19.925570 [Byte1]: 62
7870 16:31:19.929807
7871 16:31:19.929889 Set Vref, RX VrefLevel [Byte0]: 63
7872 16:31:19.932974 [Byte1]: 63
7873 16:31:19.937052
7874 16:31:19.937134 Set Vref, RX VrefLevel [Byte0]: 64
7875 16:31:19.940297 [Byte1]: 64
7876 16:31:19.944563
7877 16:31:19.944653 Set Vref, RX VrefLevel [Byte0]: 65
7878 16:31:19.948366 [Byte1]: 65
7879 16:31:19.952180
7880 16:31:19.952271 Set Vref, RX VrefLevel [Byte0]: 66
7881 16:31:19.955970 [Byte1]: 66
7882 16:31:19.960162
7883 16:31:19.960245 Set Vref, RX VrefLevel [Byte0]: 67
7884 16:31:19.963419 [Byte1]: 67
7885 16:31:19.967458
7886 16:31:19.967541 Set Vref, RX VrefLevel [Byte0]: 68
7887 16:31:19.970679 [Byte1]: 68
7888 16:31:19.975204
7889 16:31:19.975286 Set Vref, RX VrefLevel [Byte0]: 69
7890 16:31:19.978377 [Byte1]: 69
7891 16:31:19.982750
7892 16:31:19.982834 Set Vref, RX VrefLevel [Byte0]: 70
7893 16:31:19.985995 [Byte1]: 70
7894 16:31:19.990287
7895 16:31:19.990369 Set Vref, RX VrefLevel [Byte0]: 71
7896 16:31:19.993352 [Byte1]: 71
7897 16:31:19.997639
7898 16:31:19.997718 Set Vref, RX VrefLevel [Byte0]: 72
7899 16:31:20.000945 [Byte1]: 72
7900 16:31:20.005240
7901 16:31:20.005323 Set Vref, RX VrefLevel [Byte0]: 73
7902 16:31:20.011647 [Byte1]: 73
7903 16:31:20.011744
7904 16:31:20.015266 Set Vref, RX VrefLevel [Byte0]: 74
7905 16:31:20.018363 [Byte1]: 74
7906 16:31:20.018487
7907 16:31:20.021997 Set Vref, RX VrefLevel [Byte0]: 75
7908 16:31:20.025230 [Byte1]: 75
7909 16:31:20.025304
7910 16:31:20.028237 Set Vref, RX VrefLevel [Byte0]: 76
7911 16:31:20.031926 [Byte1]: 76
7912 16:31:20.035752
7913 16:31:20.035850 Set Vref, RX VrefLevel [Byte0]: 77
7914 16:31:20.038937 [Byte1]: 77
7915 16:31:20.043165
7916 16:31:20.043261 Set Vref, RX VrefLevel [Byte0]: 78
7917 16:31:20.046466 [Byte1]: 78
7918 16:31:20.050897
7919 16:31:20.051000 Set Vref, RX VrefLevel [Byte0]: 79
7920 16:31:20.054137 [Byte1]: 79
7921 16:31:20.058480
7922 16:31:20.058563 Set Vref, RX VrefLevel [Byte0]: 80
7923 16:31:20.061761 [Byte1]: 80
7924 16:31:20.066073
7925 16:31:20.066156 Final RX Vref Byte 0 = 63 to rank0
7926 16:31:20.069221 Final RX Vref Byte 1 = 62 to rank0
7927 16:31:20.072799 Final RX Vref Byte 0 = 63 to rank1
7928 16:31:20.076062 Final RX Vref Byte 1 = 62 to rank1==
7929 16:31:20.079381 Dram Type= 6, Freq= 0, CH_0, rank 0
7930 16:31:20.085976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7931 16:31:20.086058 ==
7932 16:31:20.086127 DQS Delay:
7933 16:31:20.086189 DQS0 = 0, DQS1 = 0
7934 16:31:20.089125 DQM Delay:
7935 16:31:20.089197 DQM0 = 136, DQM1 = 124
7936 16:31:20.092393 DQ Delay:
7937 16:31:20.095637 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
7938 16:31:20.098985 DQ4 =138, DQ5 =126, DQ6 =146, DQ7 =144
7939 16:31:20.102350 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7940 16:31:20.105540 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7941 16:31:20.105622
7942 16:31:20.105687
7943 16:31:20.105746
7944 16:31:20.109348 [DramC_TX_OE_Calibration] TA2
7945 16:31:20.112485 Original DQ_B0 (3 6) =30, OEN = 27
7946 16:31:20.115420 Original DQ_B1 (3 6) =30, OEN = 27
7947 16:31:20.118984 24, 0x0, End_B0=24 End_B1=24
7948 16:31:20.119071 25, 0x0, End_B0=25 End_B1=25
7949 16:31:20.122509 26, 0x0, End_B0=26 End_B1=26
7950 16:31:20.125764 27, 0x0, End_B0=27 End_B1=27
7951 16:31:20.128900 28, 0x0, End_B0=28 End_B1=28
7952 16:31:20.132470 29, 0x0, End_B0=29 End_B1=29
7953 16:31:20.132624 30, 0x0, End_B0=30 End_B1=30
7954 16:31:20.135591 31, 0x4141, End_B0=30 End_B1=30
7955 16:31:20.138886 Byte0 end_step=30 best_step=27
7956 16:31:20.142558 Byte1 end_step=30 best_step=27
7957 16:31:20.145579 Byte0 TX OE(2T, 0.5T) = (3, 3)
7958 16:31:20.148832 Byte1 TX OE(2T, 0.5T) = (3, 3)
7959 16:31:20.148908
7960 16:31:20.148984
7961 16:31:20.155765 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7962 16:31:20.159046 CH0 RK0: MR19=303, MR18=1E1C
7963 16:31:20.165562 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7964 16:31:20.165645
7965 16:31:20.168746 ----->DramcWriteLeveling(PI) begin...
7966 16:31:20.168829 ==
7967 16:31:20.172415 Dram Type= 6, Freq= 0, CH_0, rank 1
7968 16:31:20.175520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7969 16:31:20.175603 ==
7970 16:31:20.178712 Write leveling (Byte 0): 38 => 38
7971 16:31:20.182092 Write leveling (Byte 1): 29 => 29
7972 16:31:20.185239 DramcWriteLeveling(PI) end<-----
7973 16:31:20.185326
7974 16:31:20.185391 ==
7975 16:31:20.188408 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 16:31:20.192306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 16:31:20.192422 ==
7978 16:31:20.195653 [Gating] SW mode calibration
7979 16:31:20.201947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7980 16:31:20.208396 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7981 16:31:20.211839 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 16:31:20.218676 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 16:31:20.221675 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 16:31:20.225240 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7985 16:31:20.228530 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 16:31:20.235136 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 16:31:20.238644 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7988 16:31:20.241935 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7989 16:31:20.248518 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 16:31:20.251788 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 16:31:20.255017 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7992 16:31:20.261708 1 5 12 | B1->B0 | 3333 2626 | 1 1 | (1 1) (1 0)
7993 16:31:20.264925 1 5 16 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
7994 16:31:20.268146 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 16:31:20.275170 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 16:31:20.278316 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 16:31:20.281493 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 16:31:20.288012 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 16:31:20.291346 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8000 16:31:20.294640 1 6 12 | B1->B0 | 2e2e 4444 | 0 0 | (0 0) (0 0)
8001 16:31:20.301363 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 16:31:20.304615 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 16:31:20.307852 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 16:31:20.314886 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 16:31:20.318113 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 16:31:20.321357 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 16:31:20.327872 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8008 16:31:20.331203 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8009 16:31:20.334954 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8010 16:31:20.341296 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 16:31:20.344861 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 16:31:20.347845 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 16:31:20.351230 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 16:31:20.358014 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 16:31:20.361188 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 16:31:20.364935 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 16:31:20.371412 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 16:31:20.374724 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 16:31:20.377866 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 16:31:20.384567 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 16:31:20.387756 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 16:31:20.390961 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 16:31:20.398114 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8024 16:31:20.401361 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8025 16:31:20.404489 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 16:31:20.407831 Total UI for P1: 0, mck2ui 16
8027 16:31:20.411074 best dqsien dly found for B0: ( 1, 9, 10)
8028 16:31:20.414309 Total UI for P1: 0, mck2ui 16
8029 16:31:20.417576 best dqsien dly found for B1: ( 1, 9, 14)
8030 16:31:20.420878 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8031 16:31:20.424106 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8032 16:31:20.427886
8033 16:31:20.431124 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8034 16:31:20.434416 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8035 16:31:20.437647 [Gating] SW calibration Done
8036 16:31:20.437773 ==
8037 16:31:20.440845 Dram Type= 6, Freq= 0, CH_0, rank 1
8038 16:31:20.443812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 16:31:20.443896 ==
8040 16:31:20.447293 RX Vref Scan: 0
8041 16:31:20.447446
8042 16:31:20.447547 RX Vref 0 -> 0, step: 1
8043 16:31:20.447628
8044 16:31:20.450936 RX Delay 0 -> 252, step: 8
8045 16:31:20.453925 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8046 16:31:20.457322 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8047 16:31:20.464013 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8048 16:31:20.467280 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8049 16:31:20.470547 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8050 16:31:20.473764 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8051 16:31:20.476987 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8052 16:31:20.484042 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8053 16:31:20.487257 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8054 16:31:20.490267 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8055 16:31:20.493628 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8056 16:31:20.497316 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8057 16:31:20.503553 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8058 16:31:20.506760 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8059 16:31:20.509940 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8060 16:31:20.513566 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8061 16:31:20.516800 ==
8062 16:31:20.516883 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 16:31:20.523381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 16:31:20.523465 ==
8065 16:31:20.523530 DQS Delay:
8066 16:31:20.526800 DQS0 = 0, DQS1 = 0
8067 16:31:20.526882 DQM Delay:
8068 16:31:20.530013 DQM0 = 135, DQM1 = 125
8069 16:31:20.530113 DQ Delay:
8070 16:31:20.533125 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8071 16:31:20.536453 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8072 16:31:20.539669 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =123
8073 16:31:20.542898 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8074 16:31:20.542994
8075 16:31:20.543061
8076 16:31:20.543180 ==
8077 16:31:20.546607 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 16:31:20.552844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 16:31:20.552935 ==
8080 16:31:20.553016
8081 16:31:20.553094
8082 16:31:20.553170 TX Vref Scan disable
8083 16:31:20.556498 == TX Byte 0 ==
8084 16:31:20.559843 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8085 16:31:20.566875 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8086 16:31:20.566961 == TX Byte 1 ==
8087 16:31:20.569985 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8088 16:31:20.576450 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8089 16:31:20.576586 ==
8090 16:31:20.579816 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 16:31:20.582992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 16:31:20.583135 ==
8093 16:31:20.596734
8094 16:31:20.599798 TX Vref early break, caculate TX vref
8095 16:31:20.603626 TX Vref=16, minBit 8, minWin=23, winSum=392
8096 16:31:20.606796 TX Vref=18, minBit 8, minWin=23, winSum=401
8097 16:31:20.610062 TX Vref=20, minBit 0, minWin=24, winSum=404
8098 16:31:20.613399 TX Vref=22, minBit 0, minWin=25, winSum=412
8099 16:31:20.616718 TX Vref=24, minBit 0, minWin=25, winSum=426
8100 16:31:20.623178 TX Vref=26, minBit 0, minWin=26, winSum=432
8101 16:31:20.626504 TX Vref=28, minBit 0, minWin=26, winSum=432
8102 16:31:20.629646 TX Vref=30, minBit 0, minWin=26, winSum=422
8103 16:31:20.633455 TX Vref=32, minBit 0, minWin=25, winSum=421
8104 16:31:20.636697 TX Vref=34, minBit 2, minWin=24, winSum=407
8105 16:31:20.643228 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 26
8106 16:31:20.643365
8107 16:31:20.646379 Final TX Range 0 Vref 26
8108 16:31:20.646497
8109 16:31:20.646602 ==
8110 16:31:20.649537 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 16:31:20.652763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 16:31:20.652849 ==
8113 16:31:20.652919
8114 16:31:20.653004
8115 16:31:20.656441 TX Vref Scan disable
8116 16:31:20.662873 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8117 16:31:20.663037 == TX Byte 0 ==
8118 16:31:20.666086 u2DelayCellOfst[0]=13 cells (4 PI)
8119 16:31:20.669566 u2DelayCellOfst[1]=20 cells (6 PI)
8120 16:31:20.672563 u2DelayCellOfst[2]=10 cells (3 PI)
8121 16:31:20.676264 u2DelayCellOfst[3]=13 cells (4 PI)
8122 16:31:20.679514 u2DelayCellOfst[4]=10 cells (3 PI)
8123 16:31:20.682720 u2DelayCellOfst[5]=0 cells (0 PI)
8124 16:31:20.685977 u2DelayCellOfst[6]=20 cells (6 PI)
8125 16:31:20.689724 u2DelayCellOfst[7]=20 cells (6 PI)
8126 16:31:20.692727 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8127 16:31:20.695937 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8128 16:31:20.699419 == TX Byte 1 ==
8129 16:31:20.702603 u2DelayCellOfst[8]=0 cells (0 PI)
8130 16:31:20.702723 u2DelayCellOfst[9]=3 cells (1 PI)
8131 16:31:20.706277 u2DelayCellOfst[10]=6 cells (2 PI)
8132 16:31:20.709416 u2DelayCellOfst[11]=3 cells (1 PI)
8133 16:31:20.712536 u2DelayCellOfst[12]=13 cells (4 PI)
8134 16:31:20.715881 u2DelayCellOfst[13]=10 cells (3 PI)
8135 16:31:20.719018 u2DelayCellOfst[14]=13 cells (4 PI)
8136 16:31:20.722322 u2DelayCellOfst[15]=10 cells (3 PI)
8137 16:31:20.725995 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8138 16:31:20.732351 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8139 16:31:20.732434 DramC Write-DBI on
8140 16:31:20.732499 ==
8141 16:31:20.735560 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 16:31:20.742466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 16:31:20.742549 ==
8144 16:31:20.742613
8145 16:31:20.742673
8146 16:31:20.742730 TX Vref Scan disable
8147 16:31:20.746279 == TX Byte 0 ==
8148 16:31:20.749551 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8149 16:31:20.752849 == TX Byte 1 ==
8150 16:31:20.756161 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8151 16:31:20.759497 DramC Write-DBI off
8152 16:31:20.759579
8153 16:31:20.759644 [DATLAT]
8154 16:31:20.759704 Freq=1600, CH0 RK1
8155 16:31:20.759763
8156 16:31:20.762679 DATLAT Default: 0xf
8157 16:31:20.762761 0, 0xFFFF, sum = 0
8158 16:31:20.766305 1, 0xFFFF, sum = 0
8159 16:31:20.766418 2, 0xFFFF, sum = 0
8160 16:31:20.769373 3, 0xFFFF, sum = 0
8161 16:31:20.772992 4, 0xFFFF, sum = 0
8162 16:31:20.773104 5, 0xFFFF, sum = 0
8163 16:31:20.775959 6, 0xFFFF, sum = 0
8164 16:31:20.776148 7, 0xFFFF, sum = 0
8165 16:31:20.779380 8, 0xFFFF, sum = 0
8166 16:31:20.779543 9, 0xFFFF, sum = 0
8167 16:31:20.783057 10, 0xFFFF, sum = 0
8168 16:31:20.783157 11, 0xFFFF, sum = 0
8169 16:31:20.786265 12, 0xFFFF, sum = 0
8170 16:31:20.786343 13, 0xFFFF, sum = 0
8171 16:31:20.789515 14, 0x0, sum = 1
8172 16:31:20.789594 15, 0x0, sum = 2
8173 16:31:20.792879 16, 0x0, sum = 3
8174 16:31:20.792958 17, 0x0, sum = 4
8175 16:31:20.795936 best_step = 15
8176 16:31:20.796047
8177 16:31:20.796149 ==
8178 16:31:20.799538 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 16:31:20.802715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 16:31:20.802809 ==
8181 16:31:20.802922 RX Vref Scan: 0
8182 16:31:20.805943
8183 16:31:20.806026 RX Vref 0 -> 0, step: 1
8184 16:31:20.806091
8185 16:31:20.809193 RX Delay 19 -> 252, step: 4
8186 16:31:20.812784 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8187 16:31:20.819152 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8188 16:31:20.823018 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8189 16:31:20.826292 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8190 16:31:20.829517 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8191 16:31:20.832832 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8192 16:31:20.839249 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8193 16:31:20.842544 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8194 16:31:20.845860 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8195 16:31:20.849531 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8196 16:31:20.852731 iDelay=191, Bit 10, Center 122 (75 ~ 170) 96
8197 16:31:20.855967 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8198 16:31:20.862960 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8199 16:31:20.866148 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8200 16:31:20.869207 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8201 16:31:20.872839 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8202 16:31:20.872946 ==
8203 16:31:20.875820 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 16:31:20.882594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 16:31:20.882706 ==
8206 16:31:20.882816 DQS Delay:
8207 16:31:20.886142 DQS0 = 0, DQS1 = 0
8208 16:31:20.886247 DQM Delay:
8209 16:31:20.889411 DQM0 = 133, DQM1 = 122
8210 16:31:20.889488 DQ Delay:
8211 16:31:20.892663 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8212 16:31:20.896068 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8213 16:31:20.899284 DQ8 =116, DQ9 =110, DQ10 =122, DQ11 =120
8214 16:31:20.902877 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8215 16:31:20.903003
8216 16:31:20.903124
8217 16:31:20.903239
8218 16:31:20.906089 [DramC_TX_OE_Calibration] TA2
8219 16:31:20.909319 Original DQ_B0 (3 6) =30, OEN = 27
8220 16:31:20.912636 Original DQ_B1 (3 6) =30, OEN = 27
8221 16:31:20.915875 24, 0x0, End_B0=24 End_B1=24
8222 16:31:20.919052 25, 0x0, End_B0=25 End_B1=25
8223 16:31:20.919170 26, 0x0, End_B0=26 End_B1=26
8224 16:31:20.922391 27, 0x0, End_B0=27 End_B1=27
8225 16:31:20.925710 28, 0x0, End_B0=28 End_B1=28
8226 16:31:20.928937 29, 0x0, End_B0=29 End_B1=29
8227 16:31:20.929050 30, 0x0, End_B0=30 End_B1=30
8228 16:31:20.932192 31, 0x5151, End_B0=30 End_B1=30
8229 16:31:20.935947 Byte0 end_step=30 best_step=27
8230 16:31:20.939236 Byte1 end_step=30 best_step=27
8231 16:31:20.942457 Byte0 TX OE(2T, 0.5T) = (3, 3)
8232 16:31:20.945678 Byte1 TX OE(2T, 0.5T) = (3, 3)
8233 16:31:20.945788
8234 16:31:20.945890
8235 16:31:20.952135 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8236 16:31:20.955851 CH0 RK1: MR19=303, MR18=210E
8237 16:31:20.962394 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8238 16:31:20.965789 [RxdqsGatingPostProcess] freq 1600
8239 16:31:20.968825 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8240 16:31:20.972063 best DQS0 dly(2T, 0.5T) = (1, 1)
8241 16:31:20.975797 best DQS1 dly(2T, 0.5T) = (1, 1)
8242 16:31:20.978863 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8243 16:31:20.982284 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8244 16:31:20.985840 best DQS0 dly(2T, 0.5T) = (1, 1)
8245 16:31:20.988941 best DQS1 dly(2T, 0.5T) = (1, 1)
8246 16:31:20.992337 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8247 16:31:20.995516 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8248 16:31:20.998816 Pre-setting of DQS Precalculation
8249 16:31:21.002104 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8250 16:31:21.002187 ==
8251 16:31:21.005746 Dram Type= 6, Freq= 0, CH_1, rank 0
8252 16:31:21.008773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 16:31:21.012100 ==
8254 16:31:21.015752 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8255 16:31:21.019035 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8256 16:31:21.025387 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8257 16:31:21.028659 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8258 16:31:21.039203 [CA 0] Center 41 (12~71) winsize 60
8259 16:31:21.042475 [CA 1] Center 41 (11~72) winsize 62
8260 16:31:21.046124 [CA 2] Center 38 (9~67) winsize 59
8261 16:31:21.049311 [CA 3] Center 36 (7~66) winsize 60
8262 16:31:21.052483 [CA 4] Center 37 (7~68) winsize 62
8263 16:31:21.055757 [CA 5] Center 36 (7~66) winsize 60
8264 16:31:21.055841
8265 16:31:21.059472 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8266 16:31:21.059588
8267 16:31:21.062905 [CATrainingPosCal] consider 1 rank data
8268 16:31:21.066124 u2DelayCellTimex100 = 290/100 ps
8269 16:31:21.069330 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8270 16:31:21.073053 CA1 delay=41 (11~72),Diff = 5 PI (16 cell)
8271 16:31:21.079432 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8272 16:31:21.082569 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8273 16:31:21.085869 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8274 16:31:21.089369 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8275 16:31:21.089459
8276 16:31:21.092779 CA PerBit enable=1, Macro0, CA PI delay=36
8277 16:31:21.092890
8278 16:31:21.095818 [CBTSetCACLKResult] CA Dly = 36
8279 16:31:21.095892 CS Dly: 8 (0~39)
8280 16:31:21.102414 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8281 16:31:21.106242 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8282 16:31:21.106325 ==
8283 16:31:21.109516 Dram Type= 6, Freq= 0, CH_1, rank 1
8284 16:31:21.112671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 16:31:21.112766 ==
8286 16:31:21.119056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8287 16:31:21.122377 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8288 16:31:21.126096 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8289 16:31:21.132461 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8290 16:31:21.142115 [CA 0] Center 43 (14~72) winsize 59
8291 16:31:21.145846 [CA 1] Center 42 (12~72) winsize 61
8292 16:31:21.149119 [CA 2] Center 38 (9~68) winsize 60
8293 16:31:21.152343 [CA 3] Center 37 (8~67) winsize 60
8294 16:31:21.155481 [CA 4] Center 38 (9~68) winsize 60
8295 16:31:21.159253 [CA 5] Center 37 (8~67) winsize 60
8296 16:31:21.159365
8297 16:31:21.162360 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8298 16:31:21.162442
8299 16:31:21.165634 [CATrainingPosCal] consider 2 rank data
8300 16:31:21.168807 u2DelayCellTimex100 = 290/100 ps
8301 16:31:21.172043 CA0 delay=42 (14~71),Diff = 5 PI (16 cell)
8302 16:31:21.179027 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8303 16:31:21.182211 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8304 16:31:21.185466 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8305 16:31:21.188676 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8306 16:31:21.191885 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8307 16:31:21.191959
8308 16:31:21.195476 CA PerBit enable=1, Macro0, CA PI delay=37
8309 16:31:21.195597
8310 16:31:21.198852 [CBTSetCACLKResult] CA Dly = 37
8311 16:31:21.201924 CS Dly: 10 (0~43)
8312 16:31:21.205239 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8313 16:31:21.208593 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8314 16:31:21.208708
8315 16:31:21.212125 ----->DramcWriteLeveling(PI) begin...
8316 16:31:21.212206 ==
8317 16:31:21.215815 Dram Type= 6, Freq= 0, CH_1, rank 0
8318 16:31:21.218824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 16:31:21.222296 ==
8320 16:31:21.222401 Write leveling (Byte 0): 24 => 24
8321 16:31:21.225376 Write leveling (Byte 1): 28 => 28
8322 16:31:21.229148 DramcWriteLeveling(PI) end<-----
8323 16:31:21.229228
8324 16:31:21.229290 ==
8325 16:31:21.232218 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 16:31:21.239132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 16:31:21.239212 ==
8328 16:31:21.239276 [Gating] SW mode calibration
8329 16:31:21.248676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8330 16:31:21.252137 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8331 16:31:21.255282 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 16:31:21.262302 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 16:31:21.265480 1 4 8 | B1->B0 | 2b2b 3333 | 1 0 | (0 0) (0 0)
8334 16:31:21.268574 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 16:31:21.275152 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 16:31:21.279055 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 16:31:21.282275 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 16:31:21.288962 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 16:31:21.292241 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 16:31:21.295538 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8341 16:31:21.302101 1 5 8 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (1 0)
8342 16:31:21.305238 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 16:31:21.308400 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 16:31:21.315428 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 16:31:21.319021 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 16:31:21.321777 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 16:31:21.328609 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 16:31:21.331756 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8349 16:31:21.335342 1 6 8 | B1->B0 | 4040 4343 | 0 0 | (0 0) (0 0)
8350 16:31:21.342120 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 16:31:21.345296 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 16:31:21.348490 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 16:31:21.355505 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 16:31:21.358843 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 16:31:21.361967 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 16:31:21.365173 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 16:31:21.372355 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8358 16:31:21.375483 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8359 16:31:21.378756 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 16:31:21.385293 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 16:31:21.388500 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 16:31:21.392252 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 16:31:21.398422 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 16:31:21.402207 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 16:31:21.404970 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 16:31:21.411776 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 16:31:21.414906 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 16:31:21.418351 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 16:31:21.424976 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 16:31:21.428444 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 16:31:21.431557 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 16:31:21.438125 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8373 16:31:21.441831 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8374 16:31:21.445130 Total UI for P1: 0, mck2ui 16
8375 16:31:21.448295 best dqsien dly found for B0: ( 1, 9, 4)
8376 16:31:21.451471 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 16:31:21.454809 Total UI for P1: 0, mck2ui 16
8378 16:31:21.458510 best dqsien dly found for B1: ( 1, 9, 8)
8379 16:31:21.461793 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8380 16:31:21.464952 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8381 16:31:21.465032
8382 16:31:21.471478 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8383 16:31:21.474548 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8384 16:31:21.474674 [Gating] SW calibration Done
8385 16:31:21.477883 ==
8386 16:31:21.477995 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 16:31:21.484984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 16:31:21.485093 ==
8389 16:31:21.485188 RX Vref Scan: 0
8390 16:31:21.485285
8391 16:31:21.487772 RX Vref 0 -> 0, step: 1
8392 16:31:21.487867
8393 16:31:21.491457 RX Delay 0 -> 252, step: 8
8394 16:31:21.494658 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8395 16:31:21.497895 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8396 16:31:21.501206 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8397 16:31:21.504393 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8398 16:31:21.511110 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8399 16:31:21.514763 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8400 16:31:21.517981 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8401 16:31:21.521082 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8402 16:31:21.524260 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8403 16:31:21.530996 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8404 16:31:21.534368 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8405 16:31:21.537921 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8406 16:31:21.540908 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8407 16:31:21.544457 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8408 16:31:21.550964 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8409 16:31:21.554588 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8410 16:31:21.554665 ==
8411 16:31:21.557762 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 16:31:21.561060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 16:31:21.561177 ==
8414 16:31:21.564317 DQS Delay:
8415 16:31:21.564420 DQS0 = 0, DQS1 = 0
8416 16:31:21.564529 DQM Delay:
8417 16:31:21.567553 DQM0 = 138, DQM1 = 130
8418 16:31:21.567663 DQ Delay:
8419 16:31:21.571031 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8420 16:31:21.574282 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8421 16:31:21.580806 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8422 16:31:21.584465 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8423 16:31:21.584601
8424 16:31:21.584669
8425 16:31:21.584729 ==
8426 16:31:21.587839 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 16:31:21.591020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 16:31:21.591105 ==
8429 16:31:21.591171
8430 16:31:21.591233
8431 16:31:21.594263 TX Vref Scan disable
8432 16:31:21.594346 == TX Byte 0 ==
8433 16:31:21.600873 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8434 16:31:21.604166 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8435 16:31:21.604337 == TX Byte 1 ==
8436 16:31:21.611005 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8437 16:31:21.614058 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8438 16:31:21.614141 ==
8439 16:31:21.617266 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 16:31:21.621048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 16:31:21.621202 ==
8442 16:31:21.635993
8443 16:31:21.638968 TX Vref early break, caculate TX vref
8444 16:31:21.642322 TX Vref=16, minBit 10, minWin=21, winSum=368
8445 16:31:21.645777 TX Vref=18, minBit 10, minWin=22, winSum=378
8446 16:31:21.649332 TX Vref=20, minBit 10, minWin=23, winSum=389
8447 16:31:21.652273 TX Vref=22, minBit 12, minWin=24, winSum=403
8448 16:31:21.659057 TX Vref=24, minBit 10, minWin=24, winSum=407
8449 16:31:21.662627 TX Vref=26, minBit 10, minWin=24, winSum=418
8450 16:31:21.665834 TX Vref=28, minBit 10, minWin=24, winSum=416
8451 16:31:21.669108 TX Vref=30, minBit 8, minWin=24, winSum=413
8452 16:31:21.672241 TX Vref=32, minBit 8, minWin=24, winSum=407
8453 16:31:21.675494 TX Vref=34, minBit 11, minWin=23, winSum=397
8454 16:31:21.682493 TX Vref=36, minBit 9, minWin=22, winSum=385
8455 16:31:21.685845 [TxChooseVref] Worse bit 10, Min win 24, Win sum 418, Final Vref 26
8456 16:31:21.685950
8457 16:31:21.689018 Final TX Range 0 Vref 26
8458 16:31:21.689116
8459 16:31:21.689198 ==
8460 16:31:21.692259 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 16:31:21.696059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 16:31:21.699309 ==
8463 16:31:21.699431
8464 16:31:21.699537
8465 16:31:21.699661 TX Vref Scan disable
8466 16:31:21.705812 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8467 16:31:21.705910 == TX Byte 0 ==
8468 16:31:21.709094 u2DelayCellOfst[0]=13 cells (4 PI)
8469 16:31:21.712292 u2DelayCellOfst[1]=10 cells (3 PI)
8470 16:31:21.715566 u2DelayCellOfst[2]=0 cells (0 PI)
8471 16:31:21.718794 u2DelayCellOfst[3]=6 cells (2 PI)
8472 16:31:21.722413 u2DelayCellOfst[4]=6 cells (2 PI)
8473 16:31:21.725631 u2DelayCellOfst[5]=16 cells (5 PI)
8474 16:31:21.728725 u2DelayCellOfst[6]=13 cells (4 PI)
8475 16:31:21.732067 u2DelayCellOfst[7]=3 cells (1 PI)
8476 16:31:21.735383 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8477 16:31:21.738678 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8478 16:31:21.742344 == TX Byte 1 ==
8479 16:31:21.745456 u2DelayCellOfst[8]=0 cells (0 PI)
8480 16:31:21.749326 u2DelayCellOfst[9]=3 cells (1 PI)
8481 16:31:21.751921 u2DelayCellOfst[10]=10 cells (3 PI)
8482 16:31:21.755338 u2DelayCellOfst[11]=3 cells (1 PI)
8483 16:31:21.755462 u2DelayCellOfst[12]=13 cells (4 PI)
8484 16:31:21.758642 u2DelayCellOfst[13]=16 cells (5 PI)
8485 16:31:21.761809 u2DelayCellOfst[14]=16 cells (5 PI)
8486 16:31:21.765427 u2DelayCellOfst[15]=16 cells (5 PI)
8487 16:31:21.771845 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8488 16:31:21.775557 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8489 16:31:21.775647 DramC Write-DBI on
8490 16:31:21.778762 ==
8491 16:31:21.782101 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 16:31:21.785212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 16:31:21.785302 ==
8494 16:31:21.785373
8495 16:31:21.785440
8496 16:31:21.788335 TX Vref Scan disable
8497 16:31:21.788423 == TX Byte 0 ==
8498 16:31:21.794883 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8499 16:31:21.794969 == TX Byte 1 ==
8500 16:31:21.798560 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8501 16:31:21.801916 DramC Write-DBI off
8502 16:31:21.802009
8503 16:31:21.802093 [DATLAT]
8504 16:31:21.805395 Freq=1600, CH1 RK0
8505 16:31:21.805481
8506 16:31:21.805549 DATLAT Default: 0xf
8507 16:31:21.808253 0, 0xFFFF, sum = 0
8508 16:31:21.808361 1, 0xFFFF, sum = 0
8509 16:31:21.811594 2, 0xFFFF, sum = 0
8510 16:31:21.811708 3, 0xFFFF, sum = 0
8511 16:31:21.814996 4, 0xFFFF, sum = 0
8512 16:31:21.815111 5, 0xFFFF, sum = 0
8513 16:31:21.818326 6, 0xFFFF, sum = 0
8514 16:31:21.818439 7, 0xFFFF, sum = 0
8515 16:31:21.821844 8, 0xFFFF, sum = 0
8516 16:31:21.821937 9, 0xFFFF, sum = 0
8517 16:31:21.824894 10, 0xFFFF, sum = 0
8518 16:31:21.828224 11, 0xFFFF, sum = 0
8519 16:31:21.828345 12, 0xFFFF, sum = 0
8520 16:31:21.831552 13, 0xFFFF, sum = 0
8521 16:31:21.831643 14, 0x0, sum = 1
8522 16:31:21.834829 15, 0x0, sum = 2
8523 16:31:21.834916 16, 0x0, sum = 3
8524 16:31:21.838180 17, 0x0, sum = 4
8525 16:31:21.838264 best_step = 15
8526 16:31:21.838342
8527 16:31:21.838414 ==
8528 16:31:21.841535 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 16:31:21.844770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 16:31:21.844885 ==
8531 16:31:21.848304 RX Vref Scan: 1
8532 16:31:21.848427
8533 16:31:21.851460 Set Vref Range= 24 -> 127
8534 16:31:21.851580
8535 16:31:21.851694 RX Vref 24 -> 127, step: 1
8536 16:31:21.851807
8537 16:31:21.854605 RX Delay 19 -> 252, step: 4
8538 16:31:21.854724
8539 16:31:21.858265 Set Vref, RX VrefLevel [Byte0]: 24
8540 16:31:21.861437 [Byte1]: 24
8541 16:31:21.864583
8542 16:31:21.864697 Set Vref, RX VrefLevel [Byte0]: 25
8543 16:31:21.868241 [Byte1]: 25
8544 16:31:21.872422
8545 16:31:21.872529 Set Vref, RX VrefLevel [Byte0]: 26
8546 16:31:21.875692 [Byte1]: 26
8547 16:31:21.879686
8548 16:31:21.879803 Set Vref, RX VrefLevel [Byte0]: 27
8549 16:31:21.883491 [Byte1]: 27
8550 16:31:21.887350
8551 16:31:21.887470 Set Vref, RX VrefLevel [Byte0]: 28
8552 16:31:21.890688 [Byte1]: 28
8553 16:31:21.895041
8554 16:31:21.895153 Set Vref, RX VrefLevel [Byte0]: 29
8555 16:31:21.898208 [Byte1]: 29
8556 16:31:21.902476
8557 16:31:21.902581 Set Vref, RX VrefLevel [Byte0]: 30
8558 16:31:21.905932 [Byte1]: 30
8559 16:31:21.910362
8560 16:31:21.910450 Set Vref, RX VrefLevel [Byte0]: 31
8561 16:31:21.913674 [Byte1]: 31
8562 16:31:21.917753
8563 16:31:21.917841 Set Vref, RX VrefLevel [Byte0]: 32
8564 16:31:21.921103 [Byte1]: 32
8565 16:31:21.925465
8566 16:31:21.925550 Set Vref, RX VrefLevel [Byte0]: 33
8567 16:31:21.928497 [Byte1]: 33
8568 16:31:21.933210
8569 16:31:21.933321 Set Vref, RX VrefLevel [Byte0]: 34
8570 16:31:21.936035 [Byte1]: 34
8571 16:31:21.940324
8572 16:31:21.940426 Set Vref, RX VrefLevel [Byte0]: 35
8573 16:31:21.943577 [Byte1]: 35
8574 16:31:21.947903
8575 16:31:21.947980 Set Vref, RX VrefLevel [Byte0]: 36
8576 16:31:21.951243 [Byte1]: 36
8577 16:31:21.955437
8578 16:31:21.955523 Set Vref, RX VrefLevel [Byte0]: 37
8579 16:31:21.959178 [Byte1]: 37
8580 16:31:21.963273
8581 16:31:21.963356 Set Vref, RX VrefLevel [Byte0]: 38
8582 16:31:21.966382 [Byte1]: 38
8583 16:31:21.971057
8584 16:31:21.971141 Set Vref, RX VrefLevel [Byte0]: 39
8585 16:31:21.974046 [Byte1]: 39
8586 16:31:21.978230
8587 16:31:21.978369 Set Vref, RX VrefLevel [Byte0]: 40
8588 16:31:21.981670 [Byte1]: 40
8589 16:31:21.986183
8590 16:31:21.986296 Set Vref, RX VrefLevel [Byte0]: 41
8591 16:31:21.989233 [Byte1]: 41
8592 16:31:21.993447
8593 16:31:21.993558 Set Vref, RX VrefLevel [Byte0]: 42
8594 16:31:21.996870 [Byte1]: 42
8595 16:31:22.001015
8596 16:31:22.001120 Set Vref, RX VrefLevel [Byte0]: 43
8597 16:31:22.004191 [Byte1]: 43
8598 16:31:22.008516
8599 16:31:22.008624 Set Vref, RX VrefLevel [Byte0]: 44
8600 16:31:22.011755 [Byte1]: 44
8601 16:31:22.016221
8602 16:31:22.016338 Set Vref, RX VrefLevel [Byte0]: 45
8603 16:31:22.019421 [Byte1]: 45
8604 16:31:22.023803
8605 16:31:22.023895 Set Vref, RX VrefLevel [Byte0]: 46
8606 16:31:22.027037 [Byte1]: 46
8607 16:31:22.031307
8608 16:31:22.031413 Set Vref, RX VrefLevel [Byte0]: 47
8609 16:31:22.034491 [Byte1]: 47
8610 16:31:22.038820
8611 16:31:22.038924 Set Vref, RX VrefLevel [Byte0]: 48
8612 16:31:22.042502 [Byte1]: 48
8613 16:31:22.046356
8614 16:31:22.046473 Set Vref, RX VrefLevel [Byte0]: 49
8615 16:31:22.050125 [Byte1]: 49
8616 16:31:22.053940
8617 16:31:22.054025 Set Vref, RX VrefLevel [Byte0]: 50
8618 16:31:22.057791 [Byte1]: 50
8619 16:31:22.061743
8620 16:31:22.061828 Set Vref, RX VrefLevel [Byte0]: 51
8621 16:31:22.064707 [Byte1]: 51
8622 16:31:22.069289
8623 16:31:22.069401 Set Vref, RX VrefLevel [Byte0]: 52
8624 16:31:22.072464 [Byte1]: 52
8625 16:31:22.076593
8626 16:31:22.076683 Set Vref, RX VrefLevel [Byte0]: 53
8627 16:31:22.080298 [Byte1]: 53
8628 16:31:22.084561
8629 16:31:22.084670 Set Vref, RX VrefLevel [Byte0]: 54
8630 16:31:22.087915 [Byte1]: 54
8631 16:31:22.091911
8632 16:31:22.092002 Set Vref, RX VrefLevel [Byte0]: 55
8633 16:31:22.095090 [Byte1]: 55
8634 16:31:22.099464
8635 16:31:22.099558 Set Vref, RX VrefLevel [Byte0]: 56
8636 16:31:22.102735 [Byte1]: 56
8637 16:31:22.107035
8638 16:31:22.107123 Set Vref, RX VrefLevel [Byte0]: 57
8639 16:31:22.110353 [Byte1]: 57
8640 16:31:22.114827
8641 16:31:22.114919 Set Vref, RX VrefLevel [Byte0]: 58
8642 16:31:22.118103 [Byte1]: 58
8643 16:31:22.122440
8644 16:31:22.122522 Set Vref, RX VrefLevel [Byte0]: 59
8645 16:31:22.125817 [Byte1]: 59
8646 16:31:22.130024
8647 16:31:22.130107 Set Vref, RX VrefLevel [Byte0]: 60
8648 16:31:22.133184 [Byte1]: 60
8649 16:31:22.137327
8650 16:31:22.137414 Set Vref, RX VrefLevel [Byte0]: 61
8651 16:31:22.140536 [Byte1]: 61
8652 16:31:22.144960
8653 16:31:22.145039 Set Vref, RX VrefLevel [Byte0]: 62
8654 16:31:22.148163 [Byte1]: 62
8655 16:31:22.152504
8656 16:31:22.152606 Set Vref, RX VrefLevel [Byte0]: 63
8657 16:31:22.155830 [Byte1]: 63
8658 16:31:22.160144
8659 16:31:22.160250 Set Vref, RX VrefLevel [Byte0]: 64
8660 16:31:22.163238 [Byte1]: 64
8661 16:31:22.167763
8662 16:31:22.167865 Set Vref, RX VrefLevel [Byte0]: 65
8663 16:31:22.170895 [Byte1]: 65
8664 16:31:22.175273
8665 16:31:22.175357 Set Vref, RX VrefLevel [Byte0]: 66
8666 16:31:22.178390 [Byte1]: 66
8667 16:31:22.182867
8668 16:31:22.182948 Set Vref, RX VrefLevel [Byte0]: 67
8669 16:31:22.186171 [Byte1]: 67
8670 16:31:22.190590
8671 16:31:22.190703 Set Vref, RX VrefLevel [Byte0]: 68
8672 16:31:22.193720 [Byte1]: 68
8673 16:31:22.197947
8674 16:31:22.198032 Set Vref, RX VrefLevel [Byte0]: 69
8675 16:31:22.201540 [Byte1]: 69
8676 16:31:22.205811
8677 16:31:22.205922 Set Vref, RX VrefLevel [Byte0]: 70
8678 16:31:22.209132 [Byte1]: 70
8679 16:31:22.212897
8680 16:31:22.212985 Set Vref, RX VrefLevel [Byte0]: 71
8681 16:31:22.216705 [Byte1]: 71
8682 16:31:22.220523
8683 16:31:22.220648 Set Vref, RX VrefLevel [Byte0]: 72
8684 16:31:22.224028 [Byte1]: 72
8685 16:31:22.228426
8686 16:31:22.228565 Set Vref, RX VrefLevel [Byte0]: 73
8687 16:31:22.231750 [Byte1]: 73
8688 16:31:22.236021
8689 16:31:22.236132 Final RX Vref Byte 0 = 53 to rank0
8690 16:31:22.239213 Final RX Vref Byte 1 = 60 to rank0
8691 16:31:22.242346 Final RX Vref Byte 0 = 53 to rank1
8692 16:31:22.245731 Final RX Vref Byte 1 = 60 to rank1==
8693 16:31:22.248981 Dram Type= 6, Freq= 0, CH_1, rank 0
8694 16:31:22.255505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8695 16:31:22.255614 ==
8696 16:31:22.255715 DQS Delay:
8697 16:31:22.255813 DQS0 = 0, DQS1 = 0
8698 16:31:22.259335 DQM Delay:
8699 16:31:22.259441 DQM0 = 133, DQM1 = 129
8700 16:31:22.262527 DQ Delay:
8701 16:31:22.265798 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8702 16:31:22.268891 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8703 16:31:22.272627 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8704 16:31:22.275641 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =136
8705 16:31:22.275725
8706 16:31:22.275839
8707 16:31:22.275934
8708 16:31:22.279231 [DramC_TX_OE_Calibration] TA2
8709 16:31:22.282408 Original DQ_B0 (3 6) =30, OEN = 27
8710 16:31:22.285719 Original DQ_B1 (3 6) =30, OEN = 27
8711 16:31:22.289285 24, 0x0, End_B0=24 End_B1=24
8712 16:31:22.289399 25, 0x0, End_B0=25 End_B1=25
8713 16:31:22.292277 26, 0x0, End_B0=26 End_B1=26
8714 16:31:22.295754 27, 0x0, End_B0=27 End_B1=27
8715 16:31:22.299313 28, 0x0, End_B0=28 End_B1=28
8716 16:31:22.299419 29, 0x0, End_B0=29 End_B1=29
8717 16:31:22.302380 30, 0x0, End_B0=30 End_B1=30
8718 16:31:22.305396 31, 0x4141, End_B0=30 End_B1=30
8719 16:31:22.309094 Byte0 end_step=30 best_step=27
8720 16:31:22.312289 Byte1 end_step=30 best_step=27
8721 16:31:22.315502 Byte0 TX OE(2T, 0.5T) = (3, 3)
8722 16:31:22.318803 Byte1 TX OE(2T, 0.5T) = (3, 3)
8723 16:31:22.318909
8724 16:31:22.319010
8725 16:31:22.325759 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8726 16:31:22.329039 CH1 RK0: MR19=303, MR18=1826
8727 16:31:22.335607 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8728 16:31:22.335692
8729 16:31:22.338831 ----->DramcWriteLeveling(PI) begin...
8730 16:31:22.338914 ==
8731 16:31:22.342126 Dram Type= 6, Freq= 0, CH_1, rank 1
8732 16:31:22.345375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 16:31:22.345467 ==
8734 16:31:22.348986 Write leveling (Byte 0): 24 => 24
8735 16:31:22.352229 Write leveling (Byte 1): 29 => 29
8736 16:31:22.355564 DramcWriteLeveling(PI) end<-----
8737 16:31:22.355667
8738 16:31:22.355749 ==
8739 16:31:22.358824 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 16:31:22.362167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 16:31:22.362258 ==
8742 16:31:22.365485 [Gating] SW mode calibration
8743 16:31:22.371850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8744 16:31:22.378742 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8745 16:31:22.381859 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 16:31:22.385174 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 16:31:22.392223 1 4 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
8748 16:31:22.395250 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 0)
8749 16:31:22.398681 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 16:31:22.405341 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 16:31:22.408833 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 16:31:22.411668 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 16:31:22.418730 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 16:31:22.421945 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 16:31:22.425313 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 0)
8756 16:31:22.431806 1 5 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
8757 16:31:22.435049 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 16:31:22.438913 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 16:31:22.444974 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 16:31:22.448757 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 16:31:22.451848 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 16:31:22.458436 1 6 4 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
8763 16:31:22.461665 1 6 8 | B1->B0 | 4646 2323 | 0 1 | (0 0) (0 0)
8764 16:31:22.464889 1 6 12 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
8765 16:31:22.471917 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 16:31:22.475185 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 16:31:22.478441 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 16:31:22.484540 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 16:31:22.488222 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 16:31:22.491463 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 16:31:22.498062 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8772 16:31:22.501670 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8773 16:31:22.504809 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8774 16:31:22.511174 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 16:31:22.514775 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 16:31:22.517972 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 16:31:22.525008 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 16:31:22.528261 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 16:31:22.531402 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 16:31:22.535315 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 16:31:22.541739 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 16:31:22.545007 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 16:31:22.548284 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 16:31:22.554766 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 16:31:22.557934 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 16:31:22.561182 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 16:31:22.568001 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8788 16:31:22.571102 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8789 16:31:22.574562 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 16:31:22.577732 Total UI for P1: 0, mck2ui 16
8791 16:31:22.581308 best dqsien dly found for B0: ( 1, 9, 10)
8792 16:31:22.584607 Total UI for P1: 0, mck2ui 16
8793 16:31:22.587966 best dqsien dly found for B1: ( 1, 9, 10)
8794 16:31:22.590953 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8795 16:31:22.594431 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8796 16:31:22.598215
8797 16:31:22.601299 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8798 16:31:22.604410 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8799 16:31:22.607529 [Gating] SW calibration Done
8800 16:31:22.608096 ==
8801 16:31:22.611231 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 16:31:22.614351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 16:31:22.615045 ==
8804 16:31:22.615523 RX Vref Scan: 0
8805 16:31:22.617445
8806 16:31:22.617965 RX Vref 0 -> 0, step: 1
8807 16:31:22.618332
8808 16:31:22.621281 RX Delay 0 -> 252, step: 8
8809 16:31:22.624403 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8810 16:31:22.627420 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8811 16:31:22.634437 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8812 16:31:22.637518 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8813 16:31:22.640747 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8814 16:31:22.643824 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8815 16:31:22.647601 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8816 16:31:22.651029 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8817 16:31:22.657429 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8818 16:31:22.661127 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8819 16:31:22.664189 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8820 16:31:22.667495 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8821 16:31:22.674329 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8822 16:31:22.677649 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8823 16:31:22.680905 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8824 16:31:22.684263 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8825 16:31:22.684616 ==
8826 16:31:22.687481 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 16:31:22.693804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 16:31:22.694208 ==
8829 16:31:22.694842 DQS Delay:
8830 16:31:22.695251 DQS0 = 0, DQS1 = 0
8831 16:31:22.697463 DQM Delay:
8832 16:31:22.697864 DQM0 = 136, DQM1 = 132
8833 16:31:22.700956 DQ Delay:
8834 16:31:22.704359 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8835 16:31:22.707446 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8836 16:31:22.711156 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8837 16:31:22.714202 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8838 16:31:22.714685
8839 16:31:22.715012
8840 16:31:22.715489 ==
8841 16:31:22.717449 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 16:31:22.720537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 16:31:22.720946 ==
8844 16:31:22.724195
8845 16:31:22.724734
8846 16:31:22.725195 TX Vref Scan disable
8847 16:31:22.727367 == TX Byte 0 ==
8848 16:31:22.730628 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8849 16:31:22.733934 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8850 16:31:22.737186 == TX Byte 1 ==
8851 16:31:22.740920 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8852 16:31:22.744165 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8853 16:31:22.744683 ==
8854 16:31:22.747327 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 16:31:22.753821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 16:31:22.754299 ==
8857 16:31:22.766863
8858 16:31:22.770166 TX Vref early break, caculate TX vref
8859 16:31:22.773497 TX Vref=16, minBit 10, minWin=21, winSum=378
8860 16:31:22.777149 TX Vref=18, minBit 11, minWin=22, winSum=387
8861 16:31:22.780376 TX Vref=20, minBit 8, minWin=23, winSum=394
8862 16:31:22.783672 TX Vref=22, minBit 9, minWin=22, winSum=400
8863 16:31:22.786867 TX Vref=24, minBit 9, minWin=23, winSum=408
8864 16:31:22.793349 TX Vref=26, minBit 11, minWin=24, winSum=417
8865 16:31:22.796515 TX Vref=28, minBit 8, minWin=25, winSum=417
8866 16:31:22.800128 TX Vref=30, minBit 0, minWin=25, winSum=411
8867 16:31:22.803466 TX Vref=32, minBit 8, minWin=24, winSum=402
8868 16:31:22.806735 TX Vref=34, minBit 0, minWin=24, winSum=396
8869 16:31:22.810133 TX Vref=36, minBit 8, minWin=22, winSum=387
8870 16:31:22.817106 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
8871 16:31:22.817611
8872 16:31:22.820144 Final TX Range 0 Vref 28
8873 16:31:22.820508
8874 16:31:22.820845 ==
8875 16:31:22.823379 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 16:31:22.827071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 16:31:22.827436 ==
8878 16:31:22.827724
8879 16:31:22.830138
8880 16:31:22.830558 TX Vref Scan disable
8881 16:31:22.836760 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8882 16:31:22.837270 == TX Byte 0 ==
8883 16:31:22.839881 u2DelayCellOfst[0]=16 cells (5 PI)
8884 16:31:22.843386 u2DelayCellOfst[1]=13 cells (4 PI)
8885 16:31:22.846570 u2DelayCellOfst[2]=0 cells (0 PI)
8886 16:31:22.850279 u2DelayCellOfst[3]=6 cells (2 PI)
8887 16:31:22.853452 u2DelayCellOfst[4]=10 cells (3 PI)
8888 16:31:22.856975 u2DelayCellOfst[5]=20 cells (6 PI)
8889 16:31:22.860086 u2DelayCellOfst[6]=20 cells (6 PI)
8890 16:31:22.863391 u2DelayCellOfst[7]=6 cells (2 PI)
8891 16:31:22.866559 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8892 16:31:22.869797 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8893 16:31:22.873080 == TX Byte 1 ==
8894 16:31:22.876741 u2DelayCellOfst[8]=0 cells (0 PI)
8895 16:31:22.877000 u2DelayCellOfst[9]=3 cells (1 PI)
8896 16:31:22.879983 u2DelayCellOfst[10]=10 cells (3 PI)
8897 16:31:22.883228 u2DelayCellOfst[11]=3 cells (1 PI)
8898 16:31:22.886440 u2DelayCellOfst[12]=13 cells (4 PI)
8899 16:31:22.889740 u2DelayCellOfst[13]=13 cells (4 PI)
8900 16:31:22.892997 u2DelayCellOfst[14]=16 cells (5 PI)
8901 16:31:22.896296 u2DelayCellOfst[15]=16 cells (5 PI)
8902 16:31:22.903156 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8903 16:31:22.906295 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8904 16:31:22.906671 DramC Write-DBI on
8905 16:31:22.906987 ==
8906 16:31:22.909963 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 16:31:22.916010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 16:31:22.916384 ==
8909 16:31:22.916697
8910 16:31:22.916921
8911 16:31:22.917159 TX Vref Scan disable
8912 16:31:22.920143 == TX Byte 0 ==
8913 16:31:22.923793 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8914 16:31:22.927066 == TX Byte 1 ==
8915 16:31:22.930336 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8916 16:31:22.933506 DramC Write-DBI off
8917 16:31:22.933846
8918 16:31:22.934159 [DATLAT]
8919 16:31:22.934516 Freq=1600, CH1 RK1
8920 16:31:22.934881
8921 16:31:22.937199 DATLAT Default: 0xf
8922 16:31:22.937562 0, 0xFFFF, sum = 0
8923 16:31:22.940329 1, 0xFFFF, sum = 0
8924 16:31:22.943530 2, 0xFFFF, sum = 0
8925 16:31:22.943886 3, 0xFFFF, sum = 0
8926 16:31:22.946672 4, 0xFFFF, sum = 0
8927 16:31:22.947029 5, 0xFFFF, sum = 0
8928 16:31:22.949970 6, 0xFFFF, sum = 0
8929 16:31:22.950254 7, 0xFFFF, sum = 0
8930 16:31:22.953748 8, 0xFFFF, sum = 0
8931 16:31:22.954022 9, 0xFFFF, sum = 0
8932 16:31:22.956939 10, 0xFFFF, sum = 0
8933 16:31:22.957207 11, 0xFFFF, sum = 0
8934 16:31:22.960262 12, 0xFFFF, sum = 0
8935 16:31:22.960624 13, 0xFFFF, sum = 0
8936 16:31:22.963605 14, 0x0, sum = 1
8937 16:31:22.963882 15, 0x0, sum = 2
8938 16:31:22.966735 16, 0x0, sum = 3
8939 16:31:22.967097 17, 0x0, sum = 4
8940 16:31:22.970543 best_step = 15
8941 16:31:22.970936
8942 16:31:22.971174 ==
8943 16:31:22.973603 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 16:31:22.976689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 16:31:22.977042 ==
8946 16:31:22.977342 RX Vref Scan: 0
8947 16:31:22.980411
8948 16:31:22.980755 RX Vref 0 -> 0, step: 1
8949 16:31:22.981030
8950 16:31:22.983760 RX Delay 19 -> 252, step: 4
8951 16:31:22.986984 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8952 16:31:22.990336 iDelay=195, Bit 1, Center 128 (83 ~ 174) 92
8953 16:31:22.996732 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8954 16:31:23.000451 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8955 16:31:23.003549 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8956 16:31:23.006805 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8957 16:31:23.010413 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8958 16:31:23.013551 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
8959 16:31:23.020093 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
8960 16:31:23.023827 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8961 16:31:23.027052 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8962 16:31:23.030292 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8963 16:31:23.033920 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8964 16:31:23.040345 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8965 16:31:23.043633 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8966 16:31:23.046432 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8967 16:31:23.046546 ==
8968 16:31:23.050178 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 16:31:23.053338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 16:31:23.056700 ==
8971 16:31:23.056821 DQS Delay:
8972 16:31:23.056891 DQS0 = 0, DQS1 = 0
8973 16:31:23.060335 DQM Delay:
8974 16:31:23.060430 DQM0 = 133, DQM1 = 130
8975 16:31:23.063486 DQ Delay:
8976 16:31:23.066740 DQ0 =138, DQ1 =128, DQ2 =120, DQ3 =130
8977 16:31:23.069980 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
8978 16:31:23.073211 DQ8 =114, DQ9 =120, DQ10 =130, DQ11 =126
8979 16:31:23.076460 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =140
8980 16:31:23.076619
8981 16:31:23.076728
8982 16:31:23.076830
8983 16:31:23.079626 [DramC_TX_OE_Calibration] TA2
8984 16:31:23.082852 Original DQ_B0 (3 6) =30, OEN = 27
8985 16:31:23.086530 Original DQ_B1 (3 6) =30, OEN = 27
8986 16:31:23.089792 24, 0x0, End_B0=24 End_B1=24
8987 16:31:23.089918 25, 0x0, End_B0=25 End_B1=25
8988 16:31:23.093080 26, 0x0, End_B0=26 End_B1=26
8989 16:31:23.096250 27, 0x0, End_B0=27 End_B1=27
8990 16:31:23.100151 28, 0x0, End_B0=28 End_B1=28
8991 16:31:23.100312 29, 0x0, End_B0=29 End_B1=29
8992 16:31:23.102760 30, 0x0, End_B0=30 End_B1=30
8993 16:31:23.106665 31, 0x4141, End_B0=30 End_B1=30
8994 16:31:23.109540 Byte0 end_step=30 best_step=27
8995 16:31:23.112907 Byte1 end_step=30 best_step=27
8996 16:31:23.116432 Byte0 TX OE(2T, 0.5T) = (3, 3)
8997 16:31:23.116537 Byte1 TX OE(2T, 0.5T) = (3, 3)
8998 16:31:23.119521
8999 16:31:23.119603
9000 16:31:23.125990 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9001 16:31:23.129334 CH1 RK1: MR19=303, MR18=1E09
9002 16:31:23.136059 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9003 16:31:23.139608 [RxdqsGatingPostProcess] freq 1600
9004 16:31:23.143109 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9005 16:31:23.145848 best DQS0 dly(2T, 0.5T) = (1, 1)
9006 16:31:23.149379 best DQS1 dly(2T, 0.5T) = (1, 1)
9007 16:31:23.152403 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9008 16:31:23.156132 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9009 16:31:23.159287 best DQS0 dly(2T, 0.5T) = (1, 1)
9010 16:31:23.162531 best DQS1 dly(2T, 0.5T) = (1, 1)
9011 16:31:23.165833 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9012 16:31:23.169178 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9013 16:31:23.172444 Pre-setting of DQS Precalculation
9014 16:31:23.175731 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9015 16:31:23.182195 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9016 16:31:23.192762 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9017 16:31:23.193313
9018 16:31:23.193645
9019 16:31:23.195705 [Calibration Summary] 3200 Mbps
9020 16:31:23.196261 CH 0, Rank 0
9021 16:31:23.199460 SW Impedance : PASS
9022 16:31:23.199921 DUTY Scan : NO K
9023 16:31:23.202720 ZQ Calibration : PASS
9024 16:31:23.203213 Jitter Meter : NO K
9025 16:31:23.206016 CBT Training : PASS
9026 16:31:23.209192 Write leveling : PASS
9027 16:31:23.209659 RX DQS gating : PASS
9028 16:31:23.212438 RX DQ/DQS(RDDQC) : PASS
9029 16:31:23.215661 TX DQ/DQS : PASS
9030 16:31:23.216124 RX DATLAT : PASS
9031 16:31:23.219381 RX DQ/DQS(Engine): PASS
9032 16:31:23.222313 TX OE : PASS
9033 16:31:23.222774 All Pass.
9034 16:31:23.223135
9035 16:31:23.223470 CH 0, Rank 1
9036 16:31:23.225818 SW Impedance : PASS
9037 16:31:23.229065 DUTY Scan : NO K
9038 16:31:23.229525 ZQ Calibration : PASS
9039 16:31:23.232236 Jitter Meter : NO K
9040 16:31:23.235582 CBT Training : PASS
9041 16:31:23.236044 Write leveling : PASS
9042 16:31:23.238720 RX DQS gating : PASS
9043 16:31:23.242173 RX DQ/DQS(RDDQC) : PASS
9044 16:31:23.242659 TX DQ/DQS : PASS
9045 16:31:23.245816 RX DATLAT : PASS
9046 16:31:23.246399 RX DQ/DQS(Engine): PASS
9047 16:31:23.248979 TX OE : PASS
9048 16:31:23.249596 All Pass.
9049 16:31:23.250166
9050 16:31:23.252174 CH 1, Rank 0
9051 16:31:23.252744 SW Impedance : PASS
9052 16:31:23.255712 DUTY Scan : NO K
9053 16:31:23.258908 ZQ Calibration : PASS
9054 16:31:23.259530 Jitter Meter : NO K
9055 16:31:23.262155 CBT Training : PASS
9056 16:31:23.265196 Write leveling : PASS
9057 16:31:23.265605 RX DQS gating : PASS
9058 16:31:23.268960 RX DQ/DQS(RDDQC) : PASS
9059 16:31:23.272160 TX DQ/DQS : PASS
9060 16:31:23.272467 RX DATLAT : PASS
9061 16:31:23.274938 RX DQ/DQS(Engine): PASS
9062 16:31:23.278707 TX OE : PASS
9063 16:31:23.278982 All Pass.
9064 16:31:23.279207
9065 16:31:23.279472 CH 1, Rank 1
9066 16:31:23.281958 SW Impedance : PASS
9067 16:31:23.285233 DUTY Scan : NO K
9068 16:31:23.285380 ZQ Calibration : PASS
9069 16:31:23.288305 Jitter Meter : NO K
9070 16:31:23.292059 CBT Training : PASS
9071 16:31:23.292226 Write leveling : PASS
9072 16:31:23.294822 RX DQS gating : PASS
9073 16:31:23.298500 RX DQ/DQS(RDDQC) : PASS
9074 16:31:23.298615 TX DQ/DQS : PASS
9075 16:31:23.301755 RX DATLAT : PASS
9076 16:31:23.301968 RX DQ/DQS(Engine): PASS
9077 16:31:23.304976 TX OE : PASS
9078 16:31:23.305066 All Pass.
9079 16:31:23.305136
9080 16:31:23.308213 DramC Write-DBI on
9081 16:31:23.311399 PER_BANK_REFRESH: Hybrid Mode
9082 16:31:23.311519 TX_TRACKING: ON
9083 16:31:23.321470 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9084 16:31:23.328153 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9085 16:31:23.338344 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9086 16:31:23.341453 [FAST_K] Save calibration result to emmc
9087 16:31:23.341551 sync common calibartion params.
9088 16:31:23.345003 sync cbt_mode0:1, 1:1
9089 16:31:23.348317 dram_init: ddr_geometry: 2
9090 16:31:23.351568 dram_init: ddr_geometry: 2
9091 16:31:23.351697 dram_init: ddr_geometry: 2
9092 16:31:23.355007 0:dram_rank_size:100000000
9093 16:31:23.358341 1:dram_rank_size:100000000
9094 16:31:23.361943 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9095 16:31:23.365267 DFS_SHUFFLE_HW_MODE: ON
9096 16:31:23.368622 dramc_set_vcore_voltage set vcore to 725000
9097 16:31:23.371887 Read voltage for 1600, 0
9098 16:31:23.372378 Vio18 = 0
9099 16:31:23.375256 Vcore = 725000
9100 16:31:23.375719 Vdram = 0
9101 16:31:23.376082 Vddq = 0
9102 16:31:23.376422 Vmddr = 0
9103 16:31:23.378670 switch to 3200 Mbps bootup
9104 16:31:23.381775 [DramcRunTimeConfig]
9105 16:31:23.382265 PHYPLL
9106 16:31:23.385106 DPM_CONTROL_AFTERK: ON
9107 16:31:23.385570 PER_BANK_REFRESH: ON
9108 16:31:23.388246 REFRESH_OVERHEAD_REDUCTION: ON
9109 16:31:23.391387 CMD_PICG_NEW_MODE: OFF
9110 16:31:23.391852 XRTWTW_NEW_MODE: ON
9111 16:31:23.394873 XRTRTR_NEW_MODE: ON
9112 16:31:23.395298 TX_TRACKING: ON
9113 16:31:23.398072 RDSEL_TRACKING: OFF
9114 16:31:23.401356 DQS Precalculation for DVFS: ON
9115 16:31:23.401608 RX_TRACKING: OFF
9116 16:31:23.401804 HW_GATING DBG: ON
9117 16:31:23.404521 ZQCS_ENABLE_LP4: ON
9118 16:31:23.407679 RX_PICG_NEW_MODE: ON
9119 16:31:23.408004 TX_PICG_NEW_MODE: ON
9120 16:31:23.411369 ENABLE_RX_DCM_DPHY: ON
9121 16:31:23.414627 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9122 16:31:23.414853 DUMMY_READ_FOR_TRACKING: OFF
9123 16:31:23.417977 !!! SPM_CONTROL_AFTERK: OFF
9124 16:31:23.421164 !!! SPM could not control APHY
9125 16:31:23.424352 IMPEDANCE_TRACKING: ON
9126 16:31:23.424523 TEMP_SENSOR: ON
9127 16:31:23.427545 HW_SAVE_FOR_SR: OFF
9128 16:31:23.431225 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9129 16:31:23.434496 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9130 16:31:23.434602 Read ODT Tracking: ON
9131 16:31:23.438105 Refresh Rate DeBounce: ON
9132 16:31:23.441416 DFS_NO_QUEUE_FLUSH: ON
9133 16:31:23.444659 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9134 16:31:23.444763 ENABLE_DFS_RUNTIME_MRW: OFF
9135 16:31:23.447880 DDR_RESERVE_NEW_MODE: ON
9136 16:31:23.451239 MR_CBT_SWITCH_FREQ: ON
9137 16:31:23.451330 =========================
9138 16:31:23.471226 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9139 16:31:23.474433 dram_init: ddr_geometry: 2
9140 16:31:23.493204 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9141 16:31:23.496151 dram_init: dram init end (result: 0)
9142 16:31:23.502534 DRAM-K: Full calibration passed in 24483 msecs
9143 16:31:23.506196 MRC: failed to locate region type 0.
9144 16:31:23.506827 DRAM rank0 size:0x100000000,
9145 16:31:23.509468 DRAM rank1 size=0x100000000
9146 16:31:23.519571 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9147 16:31:23.526072 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9148 16:31:23.532369 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9149 16:31:23.539105 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9150 16:31:23.542169 DRAM rank0 size:0x100000000,
9151 16:31:23.545421 DRAM rank1 size=0x100000000
9152 16:31:23.545907 CBMEM:
9153 16:31:23.549205 IMD: root @ 0xfffff000 254 entries.
9154 16:31:23.552371 IMD: root @ 0xffffec00 62 entries.
9155 16:31:23.555448 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9156 16:31:23.562146 WARNING: RO_VPD is uninitialized or empty.
9157 16:31:23.565242 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9158 16:31:23.573015 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9159 16:31:23.585207 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9160 16:31:23.596754 BS: romstage times (exec / console): total (unknown) / 23980 ms
9161 16:31:23.597112
9162 16:31:23.597372
9163 16:31:23.607245 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9164 16:31:23.610381 ARM64: Exception handlers installed.
9165 16:31:23.613675 ARM64: Testing exception
9166 16:31:23.616975 ARM64: Done test exception
9167 16:31:23.617494 Enumerating buses...
9168 16:31:23.620191 Show all devs... Before device enumeration.
9169 16:31:23.623431 Root Device: enabled 1
9170 16:31:23.626709 CPU_CLUSTER: 0: enabled 1
9171 16:31:23.627180 CPU: 00: enabled 1
9172 16:31:23.630119 Compare with tree...
9173 16:31:23.630611 Root Device: enabled 1
9174 16:31:23.633416 CPU_CLUSTER: 0: enabled 1
9175 16:31:23.636618 CPU: 00: enabled 1
9176 16:31:23.636955 Root Device scanning...
9177 16:31:23.640309 scan_static_bus for Root Device
9178 16:31:23.643395 CPU_CLUSTER: 0 enabled
9179 16:31:23.646630 scan_static_bus for Root Device done
9180 16:31:23.650330 scan_bus: bus Root Device finished in 8 msecs
9181 16:31:23.650662 done
9182 16:31:23.656800 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9183 16:31:23.659810 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9184 16:31:23.666538 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9185 16:31:23.670113 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9186 16:31:23.673191 Allocating resources...
9187 16:31:23.676801 Reading resources...
9188 16:31:23.680069 Root Device read_resources bus 0 link: 0
9189 16:31:23.680507 DRAM rank0 size:0x100000000,
9190 16:31:23.683309 DRAM rank1 size=0x100000000
9191 16:31:23.686673 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9192 16:31:23.689824 CPU: 00 missing read_resources
9193 16:31:23.693110 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9194 16:31:23.700246 Root Device read_resources bus 0 link: 0 done
9195 16:31:23.700718 Done reading resources.
9196 16:31:23.706646 Show resources in subtree (Root Device)...After reading.
9197 16:31:23.709776 Root Device child on link 0 CPU_CLUSTER: 0
9198 16:31:23.712862 CPU_CLUSTER: 0 child on link 0 CPU: 00
9199 16:31:23.722975 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9200 16:31:23.723413 CPU: 00
9201 16:31:23.726294 Root Device assign_resources, bus 0 link: 0
9202 16:31:23.729595 CPU_CLUSTER: 0 missing set_resources
9203 16:31:23.733505 Root Device assign_resources, bus 0 link: 0 done
9204 16:31:23.736751 Done setting resources.
9205 16:31:23.743031 Show resources in subtree (Root Device)...After assigning values.
9206 16:31:23.746745 Root Device child on link 0 CPU_CLUSTER: 0
9207 16:31:23.749732 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 16:31:23.759472 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 16:31:23.759963 CPU: 00
9210 16:31:23.763141 Done allocating resources.
9211 16:31:23.766273 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9212 16:31:23.769757 Enabling resources...
9213 16:31:23.770196 done.
9214 16:31:23.776471 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9215 16:31:23.777003 Initializing devices...
9216 16:31:23.779516 Root Device init
9217 16:31:23.779971 init hardware done!
9218 16:31:23.783210 0x00000018: ctrlr->caps
9219 16:31:23.786577 52.000 MHz: ctrlr->f_max
9220 16:31:23.786908 0.400 MHz: ctrlr->f_min
9221 16:31:23.789822 0x40ff8080: ctrlr->voltages
9222 16:31:23.790300 sclk: 390625
9223 16:31:23.793233 Bus Width = 1
9224 16:31:23.793556 sclk: 390625
9225 16:31:23.793855 Bus Width = 1
9226 16:31:23.796472 Early init status = 3
9227 16:31:23.802988 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9228 16:31:23.806283 in-header: 03 fc 00 00 01 00 00 00
9229 16:31:23.806754 in-data: 00
9230 16:31:23.813055 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9231 16:31:23.816513 in-header: 03 fd 00 00 00 00 00 00
9232 16:31:23.819785 in-data:
9233 16:31:23.822993 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9234 16:31:23.826338 in-header: 03 fc 00 00 01 00 00 00
9235 16:31:23.829638 in-data: 00
9236 16:31:23.832868 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9237 16:31:23.836686 in-header: 03 fd 00 00 00 00 00 00
9238 16:31:23.840534 in-data:
9239 16:31:23.843680 [SSUSB] Setting up USB HOST controller...
9240 16:31:23.847010 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9241 16:31:23.849957 [SSUSB] phy power-on done.
9242 16:31:23.853634 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9243 16:31:23.859939 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9244 16:31:23.863229 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9245 16:31:23.870294 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9246 16:31:23.876798 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9247 16:31:23.883043 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9248 16:31:23.889744 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9249 16:31:23.896276 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9250 16:31:23.899494 SPM: binary array size = 0x9dc
9251 16:31:23.902785 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9252 16:31:23.909754 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9253 16:31:23.916291 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9254 16:31:23.920022 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9255 16:31:23.926161 configure_display: Starting display init
9256 16:31:23.960233 anx7625_power_on_init: Init interface.
9257 16:31:23.963644 anx7625_disable_pd_protocol: Disabled PD feature.
9258 16:31:23.966747 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9259 16:31:23.994945 anx7625_start_dp_work: Secure OCM version=00
9260 16:31:23.998079 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9261 16:31:24.012255 sp_tx_get_edid_block: EDID Block = 1
9262 16:31:24.115133 Extracted contents:
9263 16:31:24.118316 header: 00 ff ff ff ff ff ff 00
9264 16:31:24.121599 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9265 16:31:24.124945 version: 01 04
9266 16:31:24.128056 basic params: 95 1f 11 78 0a
9267 16:31:24.131526 chroma info: 76 90 94 55 54 90 27 21 50 54
9268 16:31:24.134833 established: 00 00 00
9269 16:31:24.141175 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9270 16:31:24.144891 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9271 16:31:24.151439 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9272 16:31:24.157877 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9273 16:31:24.164681 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9274 16:31:24.167845 extensions: 00
9275 16:31:24.167948 checksum: fb
9276 16:31:24.168047
9277 16:31:24.171026 Manufacturer: IVO Model 57d Serial Number 0
9278 16:31:24.174749 Made week 0 of 2020
9279 16:31:24.174877 EDID version: 1.4
9280 16:31:24.178096 Digital display
9281 16:31:24.181334 6 bits per primary color channel
9282 16:31:24.181448 DisplayPort interface
9283 16:31:24.184443 Maximum image size: 31 cm x 17 cm
9284 16:31:24.188053 Gamma: 220%
9285 16:31:24.188168 Check DPMS levels
9286 16:31:24.191299 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9287 16:31:24.194387 First detailed timing is preferred timing
9288 16:31:24.197804 Established timings supported:
9289 16:31:24.201454 Standard timings supported:
9290 16:31:24.204507 Detailed timings
9291 16:31:24.207771 Hex of detail: 383680a07038204018303c0035ae10000019
9292 16:31:24.211497 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9293 16:31:24.218019 0780 0798 07c8 0820 hborder 0
9294 16:31:24.221183 0438 043b 0447 0458 vborder 0
9295 16:31:24.224543 -hsync -vsync
9296 16:31:24.224684 Did detailed timing
9297 16:31:24.230810 Hex of detail: 000000000000000000000000000000000000
9298 16:31:24.230917 Manufacturer-specified data, tag 0
9299 16:31:24.237765 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9300 16:31:24.240941 ASCII string: InfoVision
9301 16:31:24.244248 Hex of detail: 000000fe00523134304e574635205248200a
9302 16:31:24.247543 ASCII string: R140NWF5 RH
9303 16:31:24.247661 Checksum
9304 16:31:24.250892 Checksum: 0xfb (valid)
9305 16:31:24.254194 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9306 16:31:24.257429 DSI data_rate: 832800000 bps
9307 16:31:24.264067 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9308 16:31:24.267918 anx7625_parse_edid: pixelclock(138800).
9309 16:31:24.270976 hactive(1920), hsync(48), hfp(24), hbp(88)
9310 16:31:24.274167 vactive(1080), vsync(12), vfp(3), vbp(17)
9311 16:31:24.277897 anx7625_dsi_config: config dsi.
9312 16:31:24.284280 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9313 16:31:24.296931 anx7625_dsi_config: success to config DSI
9314 16:31:24.300152 anx7625_dp_start: MIPI phy setup OK.
9315 16:31:24.303875 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9316 16:31:24.306991 mtk_ddp_mode_set invalid vrefresh 60
9317 16:31:24.310189 main_disp_path_setup
9318 16:31:24.310288 ovl_layer_smi_id_en
9319 16:31:24.313418 ovl_layer_smi_id_en
9320 16:31:24.313520 ccorr_config
9321 16:31:24.313609 aal_config
9322 16:31:24.316627 gamma_config
9323 16:31:24.316726 postmask_config
9324 16:31:24.320453 dither_config
9325 16:31:24.323639 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9326 16:31:24.330054 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9327 16:31:24.333756 Root Device init finished in 551 msecs
9328 16:31:24.333862 CPU_CLUSTER: 0 init
9329 16:31:24.343463 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9330 16:31:24.347224 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9331 16:31:24.350562 APU_MBOX 0x190000b0 = 0x10001
9332 16:31:24.353681 APU_MBOX 0x190001b0 = 0x10001
9333 16:31:24.357074 APU_MBOX 0x190005b0 = 0x10001
9334 16:31:24.360372 APU_MBOX 0x190006b0 = 0x10001
9335 16:31:24.363726 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9336 16:31:24.376086 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9337 16:31:24.388407 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9338 16:31:24.394965 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9339 16:31:24.406542 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9340 16:31:24.416087 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9341 16:31:24.419460 CPU_CLUSTER: 0 init finished in 81 msecs
9342 16:31:24.422656 Devices initialized
9343 16:31:24.425796 Show all devs... After init.
9344 16:31:24.425901 Root Device: enabled 1
9345 16:31:24.429421 CPU_CLUSTER: 0: enabled 1
9346 16:31:24.432505 CPU: 00: enabled 1
9347 16:31:24.435778 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9348 16:31:24.439468 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9349 16:31:24.442799 ELOG: NV offset 0x57f000 size 0x1000
9350 16:31:24.449281 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9351 16:31:24.455633 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9352 16:31:24.459454 ELOG: Event(17) added with size 13 at 2024-06-17 16:29:58 UTC
9353 16:31:24.462669 out: cmd=0x121: 03 db 21 01 00 00 00 00
9354 16:31:24.465940 in-header: 03 6f 00 00 2c 00 00 00
9355 16:31:24.479019 in-data: d0 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9356 16:31:24.486135 ELOG: Event(A1) added with size 10 at 2024-06-17 16:29:58 UTC
9357 16:31:24.492825 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9358 16:31:24.499179 ELOG: Event(A0) added with size 9 at 2024-06-17 16:29:58 UTC
9359 16:31:24.502925 elog_add_boot_reason: Logged dev mode boot
9360 16:31:24.506062 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9361 16:31:24.509414 Finalize devices...
9362 16:31:24.509500 Devices finalized
9363 16:31:24.516132 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9364 16:31:24.519285 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9365 16:31:24.522491 in-header: 03 07 00 00 08 00 00 00
9366 16:31:24.525801 in-data: aa e4 47 04 13 02 00 00
9367 16:31:24.529070 Chrome EC: UHEPI supported
9368 16:31:24.535531 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9369 16:31:24.538770 in-header: 03 a9 00 00 08 00 00 00
9370 16:31:24.542567 in-data: 84 60 60 08 00 00 00 00
9371 16:31:24.549065 ELOG: Event(91) added with size 10 at 2024-06-17 16:29:58 UTC
9372 16:31:24.552344 Chrome EC: clear events_b mask to 0x0000000020004000
9373 16:31:24.559238 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9374 16:31:24.562425 in-header: 03 fd 00 00 00 00 00 00
9375 16:31:24.565921 in-data:
9376 16:31:24.569168 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9377 16:31:24.572454 Writing coreboot table at 0xffe64000
9378 16:31:24.576188 0. 000000000010a000-0000000000113fff: RAMSTAGE
9379 16:31:24.579335 1. 0000000040000000-00000000400fffff: RAM
9380 16:31:24.585584 2. 0000000040100000-000000004032afff: RAMSTAGE
9381 16:31:24.589173 3. 000000004032b000-00000000545fffff: RAM
9382 16:31:24.592288 4. 0000000054600000-000000005465ffff: BL31
9383 16:31:24.595496 5. 0000000054660000-00000000ffe63fff: RAM
9384 16:31:24.602526 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9385 16:31:24.605817 7. 0000000100000000-000000023fffffff: RAM
9386 16:31:24.608957 Passing 5 GPIOs to payload:
9387 16:31:24.612586 NAME | PORT | POLARITY | VALUE
9388 16:31:24.618956 EC in RW | 0x000000aa | low | undefined
9389 16:31:24.622426 EC interrupt | 0x00000005 | low | undefined
9390 16:31:24.625658 TPM interrupt | 0x000000ab | high | undefined
9391 16:31:24.632201 SD card detect | 0x00000011 | high | undefined
9392 16:31:24.635833 speaker enable | 0x00000093 | high | undefined
9393 16:31:24.639127 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9394 16:31:24.642356 in-header: 03 f9 00 00 02 00 00 00
9395 16:31:24.645623 in-data: 02 00
9396 16:31:24.645703 ADC[4]: Raw value=900663 ID=7
9397 16:31:24.648961 ADC[3]: Raw value=213179 ID=1
9398 16:31:24.652020 RAM Code: 0x71
9399 16:31:24.652125 ADC[6]: Raw value=74502 ID=0
9400 16:31:24.655255 ADC[5]: Raw value=212810 ID=1
9401 16:31:24.659093 SKU Code: 0x1
9402 16:31:24.662305 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ceea
9403 16:31:24.665572 coreboot table: 964 bytes.
9404 16:31:24.668757 IMD ROOT 0. 0xfffff000 0x00001000
9405 16:31:24.672075 IMD SMALL 1. 0xffffe000 0x00001000
9406 16:31:24.675446 RO MCACHE 2. 0xffffc000 0x00001104
9407 16:31:24.678649 CONSOLE 3. 0xfff7c000 0x00080000
9408 16:31:24.682423 FMAP 4. 0xfff7b000 0x00000452
9409 16:31:24.685492 TIME STAMP 5. 0xfff7a000 0x00000910
9410 16:31:24.688704 VBOOT WORK 6. 0xfff66000 0x00014000
9411 16:31:24.691967 RAMOOPS 7. 0xffe66000 0x00100000
9412 16:31:24.695543 COREBOOT 8. 0xffe64000 0x00002000
9413 16:31:24.695631 IMD small region:
9414 16:31:24.702101 IMD ROOT 0. 0xffffec00 0x00000400
9415 16:31:24.705385 VPD 1. 0xffffeb80 0x0000006c
9416 16:31:24.708487 MMC STATUS 2. 0xffffeb60 0x00000004
9417 16:31:24.712099 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9418 16:31:24.718397 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9419 16:31:24.758740 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9420 16:31:24.762534 Checking segment from ROM address 0x40100000
9421 16:31:24.765768 Checking segment from ROM address 0x4010001c
9422 16:31:24.772163 Loading segment from ROM address 0x40100000
9423 16:31:24.772296 code (compression=0)
9424 16:31:24.782030 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9425 16:31:24.789089 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9426 16:31:24.789181 it's not compressed!
9427 16:31:24.795746 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9428 16:31:24.798923 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9429 16:31:24.819139 Loading segment from ROM address 0x4010001c
9430 16:31:24.819233 Entry Point 0x80000000
9431 16:31:24.822972 Loaded segments
9432 16:31:24.826088 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9433 16:31:24.832325 Jumping to boot code at 0x80000000(0xffe64000)
9434 16:31:24.839396 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9435 16:31:24.845631 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9436 16:31:24.853719 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9437 16:31:24.857362 Checking segment from ROM address 0x40100000
9438 16:31:24.860464 Checking segment from ROM address 0x4010001c
9439 16:31:24.867090 Loading segment from ROM address 0x40100000
9440 16:31:24.867181 code (compression=1)
9441 16:31:24.873473 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9442 16:31:24.883636 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9443 16:31:24.883789 using LZMA
9444 16:31:24.892388 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9445 16:31:24.898987 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9446 16:31:24.902090 Loading segment from ROM address 0x4010001c
9447 16:31:24.902253 Entry Point 0x54601000
9448 16:31:24.905151 Loaded segments
9449 16:31:24.908874 NOTICE: MT8192 bl31_setup
9450 16:31:24.915932 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9451 16:31:24.919032 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9452 16:31:24.922188 WARNING: region 0:
9453 16:31:24.925959 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 16:31:24.926069 WARNING: region 1:
9455 16:31:24.932381 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9456 16:31:24.935948 WARNING: region 2:
9457 16:31:24.939289 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9458 16:31:24.942414 WARNING: region 3:
9459 16:31:24.945568 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 16:31:24.948797 WARNING: region 4:
9461 16:31:24.955877 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 16:31:24.955962 WARNING: region 5:
9463 16:31:24.959029 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 16:31:24.962347 WARNING: region 6:
9465 16:31:24.966021 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 16:31:24.966141 WARNING: region 7:
9467 16:31:24.972281 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 16:31:24.979171 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9469 16:31:24.982429 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9470 16:31:24.985648 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9471 16:31:24.992825 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9472 16:31:24.996087 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9473 16:31:24.999375 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9474 16:31:25.005675 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9475 16:31:25.009277 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9476 16:31:25.016101 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9477 16:31:25.019334 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9478 16:31:25.022495 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9479 16:31:25.029379 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9480 16:31:25.032538 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9481 16:31:25.035944 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9482 16:31:25.042668 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9483 16:31:25.046106 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9484 16:31:25.052615 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9485 16:31:25.055975 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9486 16:31:25.059481 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9487 16:31:25.065912 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9488 16:31:25.069119 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9489 16:31:25.072973 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9490 16:31:25.079387 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9491 16:31:25.082585 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9492 16:31:25.089201 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9493 16:31:25.092678 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9494 16:31:25.096346 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9495 16:31:25.102554 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9496 16:31:25.106341 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9497 16:31:25.112633 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9498 16:31:25.116109 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9499 16:31:25.119132 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9500 16:31:25.126068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9501 16:31:25.129317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9502 16:31:25.132438 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9503 16:31:25.135944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9504 16:31:25.142842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9505 16:31:25.145871 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9506 16:31:25.149135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9507 16:31:25.152419 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9508 16:31:25.159576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9509 16:31:25.162819 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9510 16:31:25.165959 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9511 16:31:25.169317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9512 16:31:25.175867 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9513 16:31:25.178956 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9514 16:31:25.182734 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9515 16:31:25.186002 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9516 16:31:25.192623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9517 16:31:25.195747 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9518 16:31:25.202272 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9519 16:31:25.205489 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9520 16:31:25.212146 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9521 16:31:25.215474 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9522 16:31:25.219366 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9523 16:31:25.225750 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9524 16:31:25.229094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9525 16:31:25.235626 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9526 16:31:25.238861 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9527 16:31:25.245569 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9528 16:31:25.248790 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9529 16:31:25.255446 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9530 16:31:25.258761 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9531 16:31:25.262587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9532 16:31:25.269210 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9533 16:31:25.272385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9534 16:31:25.279274 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9535 16:31:25.282394 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9536 16:31:25.285500 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9537 16:31:25.291960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9538 16:31:25.295299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9539 16:31:25.301994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9540 16:31:25.305397 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9541 16:31:25.311747 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9542 16:31:25.315158 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9543 16:31:25.322076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9544 16:31:25.325429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9545 16:31:25.328508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9546 16:31:25.335313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9547 16:31:25.338577 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9548 16:31:25.345330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9549 16:31:25.348804 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9550 16:31:25.355472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9551 16:31:25.358744 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9552 16:31:25.361871 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9553 16:31:25.368440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9554 16:31:25.371654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9555 16:31:25.378749 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9556 16:31:25.381791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9557 16:31:25.388627 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9558 16:31:25.391801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9559 16:31:25.398392 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9560 16:31:25.402096 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9561 16:31:25.405286 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9562 16:31:25.411838 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9563 16:31:25.415124 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9564 16:31:25.421902 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9565 16:31:25.425291 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9566 16:31:25.428400 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9567 16:31:25.431582 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9568 16:31:25.438508 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9569 16:31:25.441697 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9570 16:31:25.445152 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9571 16:31:25.451682 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9572 16:31:25.455252 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9573 16:31:25.461841 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9574 16:31:25.465027 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9575 16:31:25.468430 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9576 16:31:25.474815 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9577 16:31:25.478173 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9578 16:31:25.484645 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9579 16:31:25.488441 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9580 16:31:25.491435 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9581 16:31:25.498464 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9582 16:31:25.501555 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9583 16:31:25.508447 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9584 16:31:25.511729 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9585 16:31:25.515002 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9586 16:31:25.518289 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9587 16:31:25.524816 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9588 16:31:25.528215 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9589 16:31:25.531427 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9590 16:31:25.534785 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9591 16:31:25.541420 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9592 16:31:25.544635 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9593 16:31:25.548467 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9594 16:31:25.555113 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9595 16:31:25.558239 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9596 16:31:25.564871 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9597 16:31:25.568184 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9598 16:31:25.571247 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9599 16:31:25.578419 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9600 16:31:25.581812 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9601 16:31:25.588325 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9602 16:31:25.591592 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9603 16:31:25.594733 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9604 16:31:25.601507 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9605 16:31:25.604786 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9606 16:31:25.608027 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9607 16:31:25.614983 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9608 16:31:25.618249 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9609 16:31:25.624749 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9610 16:31:25.628394 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9611 16:31:25.631600 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9612 16:31:25.638075 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9613 16:31:25.641737 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9614 16:31:25.648033 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9615 16:31:25.651209 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9616 16:31:25.654504 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9617 16:31:25.661057 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9618 16:31:25.664682 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9619 16:31:25.667730 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9620 16:31:25.674278 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9621 16:31:25.677713 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9622 16:31:25.684456 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9623 16:31:25.687701 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9624 16:31:25.690941 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9625 16:31:25.697594 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9626 16:31:25.700840 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9627 16:31:25.707755 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9628 16:31:25.711118 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9629 16:31:25.714243 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9630 16:31:25.721389 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9631 16:31:25.724625 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9632 16:31:25.731572 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9633 16:31:25.734679 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9634 16:31:25.738245 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9635 16:31:25.744874 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9636 16:31:25.747816 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9637 16:31:25.751653 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9638 16:31:25.758130 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9639 16:31:25.761311 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9640 16:31:25.767748 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9641 16:31:25.771050 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9642 16:31:25.774588 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9643 16:31:25.780999 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9644 16:31:25.784288 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9645 16:31:25.790795 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9646 16:31:25.794101 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9647 16:31:25.797408 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9648 16:31:25.803875 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9649 16:31:25.807482 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9650 16:31:25.814011 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9651 16:31:25.817302 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9652 16:31:25.820443 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9653 16:31:25.827093 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9654 16:31:25.830408 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9655 16:31:25.836979 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9656 16:31:25.840681 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9657 16:31:25.843468 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9658 16:31:25.850080 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9659 16:31:25.853634 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9660 16:31:25.860128 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9661 16:31:25.863619 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9662 16:31:25.867297 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9663 16:31:25.873941 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9664 16:31:25.876791 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9665 16:31:25.883712 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9666 16:31:25.886746 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9667 16:31:25.893783 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9668 16:31:25.897160 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9669 16:31:25.900439 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9670 16:31:25.906822 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9671 16:31:25.910070 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9672 16:31:25.917069 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9673 16:31:25.920298 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9674 16:31:25.923589 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9675 16:31:25.930217 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9676 16:31:25.933471 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9677 16:31:25.940608 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9678 16:31:25.943956 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9679 16:31:25.947203 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9680 16:31:25.953824 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9681 16:31:25.957083 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9682 16:31:25.963926 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9683 16:31:25.967171 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9684 16:31:25.970868 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9685 16:31:25.977412 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9686 16:31:25.980522 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9687 16:31:25.987564 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9688 16:31:25.990489 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9689 16:31:25.997249 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9690 16:31:26.000697 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9691 16:31:26.003966 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9692 16:31:26.010426 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9693 16:31:26.013656 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9694 16:31:26.020323 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9695 16:31:26.023531 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9696 16:31:26.027104 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9697 16:31:26.034175 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9698 16:31:26.037466 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9699 16:31:26.040801 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9700 16:31:26.044137 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9701 16:31:26.047368 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9702 16:31:26.053743 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9703 16:31:26.056992 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9704 16:31:26.063446 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9705 16:31:26.067132 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9706 16:31:26.070319 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9707 16:31:26.076742 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9708 16:31:26.080379 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9709 16:31:26.086944 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9710 16:31:26.090253 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9711 16:31:26.093265 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9712 16:31:26.099943 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9713 16:31:26.103589 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9714 16:31:26.107583 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9715 16:31:26.113978 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9716 16:31:26.117034 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9717 16:31:26.120688 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9718 16:31:26.126980 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9719 16:31:26.130782 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9720 16:31:26.137245 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9721 16:31:26.140541 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9722 16:31:26.143807 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9723 16:31:26.150442 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9724 16:31:26.153581 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9725 16:31:26.156888 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9726 16:31:26.163734 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9727 16:31:26.166962 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9728 16:31:26.170277 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9729 16:31:26.177087 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9730 16:31:26.180250 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9731 16:31:26.183549 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9732 16:31:26.190032 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9733 16:31:26.193442 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9734 16:31:26.200179 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9735 16:31:26.203171 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9736 16:31:26.206718 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9737 16:31:26.210300 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9738 16:31:26.216944 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9739 16:31:26.220362 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9740 16:31:26.223379 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9741 16:31:26.226800 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9742 16:31:26.233315 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9743 16:31:26.237050 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9744 16:31:26.240313 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9745 16:31:26.243498 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9746 16:31:26.250031 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9747 16:31:26.253281 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9748 16:31:26.256455 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9749 16:31:26.260304 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9750 16:31:26.266647 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9751 16:31:26.269800 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9752 16:31:26.276939 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9753 16:31:26.279929 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9754 16:31:26.286899 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9755 16:31:26.290510 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9756 16:31:26.293624 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9757 16:31:26.300067 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9758 16:31:26.303720 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9759 16:31:26.306696 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9760 16:31:26.313278 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9761 16:31:26.316415 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9762 16:31:26.323256 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9763 16:31:26.326619 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9764 16:31:26.333416 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9765 16:31:26.336429 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9766 16:31:26.339739 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9767 16:31:26.346259 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9768 16:31:26.349567 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9769 16:31:26.356237 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9770 16:31:26.359526 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9771 16:31:26.366463 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9772 16:31:26.369619 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9773 16:31:26.372867 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9774 16:31:26.379546 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9775 16:31:26.382442 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9776 16:31:26.389304 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9777 16:31:26.392530 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9778 16:31:26.396347 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9779 16:31:26.403049 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9780 16:31:26.406036 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9781 16:31:26.412710 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9782 16:31:26.415900 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9783 16:31:26.419289 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9784 16:31:26.425951 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9785 16:31:26.429091 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9786 16:31:26.436193 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9787 16:31:26.439648 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9788 16:31:26.442570 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9789 16:31:26.449251 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9790 16:31:26.452325 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9791 16:31:26.459449 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9792 16:31:26.462756 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9793 16:31:26.466055 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9794 16:31:26.472488 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9795 16:31:26.475759 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9796 16:31:26.482785 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9797 16:31:26.485805 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9798 16:31:26.489343 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9799 16:31:26.495602 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9800 16:31:26.498770 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9801 16:31:26.505882 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9802 16:31:26.509340 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9803 16:31:26.516036 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9804 16:31:26.519314 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9805 16:31:26.522667 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9806 16:31:26.529065 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9807 16:31:26.532346 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9808 16:31:26.539289 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9809 16:31:26.542450 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9810 16:31:26.545542 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9811 16:31:26.552392 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9812 16:31:26.555928 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9813 16:31:26.558902 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9814 16:31:26.565698 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9815 16:31:26.568922 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9816 16:31:26.575366 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9817 16:31:26.579037 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9818 16:31:26.585330 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9819 16:31:26.588512 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9820 16:31:26.592211 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9821 16:31:26.598383 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9822 16:31:26.601751 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9823 16:31:26.608612 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9824 16:31:26.611714 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9825 16:31:26.618696 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9826 16:31:26.621865 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9827 16:31:26.625233 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9828 16:31:26.632210 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9829 16:31:26.635719 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9830 16:31:26.642060 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9831 16:31:26.645341 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9832 16:31:26.652326 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9833 16:31:26.655287 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9834 16:31:26.658741 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9835 16:31:26.665225 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9836 16:31:26.668918 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9837 16:31:26.675336 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9838 16:31:26.678667 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9839 16:31:26.685252 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9840 16:31:26.688905 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9841 16:31:26.692126 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9842 16:31:26.698348 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9843 16:31:26.702106 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9844 16:31:26.708430 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9845 16:31:26.712118 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9846 16:31:26.718616 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9847 16:31:26.721750 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9848 16:31:26.725281 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9849 16:31:26.731779 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9850 16:31:26.735115 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9851 16:31:26.741704 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9852 16:31:26.744999 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9853 16:31:26.751350 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9854 16:31:26.754574 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9855 16:31:26.758391 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9856 16:31:26.764924 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9857 16:31:26.768183 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9858 16:31:26.774797 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9859 16:31:26.777866 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9860 16:31:26.784912 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9861 16:31:26.788100 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9862 16:31:26.791341 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9863 16:31:26.797774 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9864 16:31:26.801059 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9865 16:31:26.807812 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9866 16:31:26.811049 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9867 16:31:26.818044 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9868 16:31:26.820940 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9869 16:31:26.824194 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9870 16:31:26.831150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9871 16:31:26.834311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9872 16:31:26.840874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9873 16:31:26.844732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9874 16:31:26.851142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9875 16:31:26.854434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9876 16:31:26.861029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9877 16:31:26.864327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9878 16:31:26.871283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9879 16:31:26.874311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9880 16:31:26.881103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9881 16:31:26.884091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9882 16:31:26.890978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9883 16:31:26.894245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9884 16:31:26.897473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9885 16:31:26.904472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9886 16:31:26.907675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9887 16:31:26.914079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9888 16:31:26.917873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9889 16:31:26.924265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9890 16:31:26.927479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9891 16:31:26.934379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9892 16:31:26.937683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9893 16:31:26.944217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9894 16:31:26.947296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9895 16:31:26.954096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9896 16:31:26.957292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9897 16:31:26.964013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9898 16:31:26.967235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9899 16:31:26.974296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9900 16:31:26.977478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9901 16:31:26.984090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9902 16:31:26.987376 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9903 16:31:26.990507 INFO: [APUAPC] vio 0
9904 16:31:26.994278 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9905 16:31:27.000773 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9906 16:31:27.003936 INFO: [APUAPC] D0_APC_0: 0x400510
9907 16:31:27.007269 INFO: [APUAPC] D0_APC_1: 0x0
9908 16:31:27.007355 INFO: [APUAPC] D0_APC_2: 0x1540
9909 16:31:27.010511 INFO: [APUAPC] D0_APC_3: 0x0
9910 16:31:27.014155 INFO: [APUAPC] D1_APC_0: 0xffffffff
9911 16:31:27.017394 INFO: [APUAPC] D1_APC_1: 0xffffffff
9912 16:31:27.020760 INFO: [APUAPC] D1_APC_2: 0x3fffff
9913 16:31:27.023905 INFO: [APUAPC] D1_APC_3: 0x0
9914 16:31:27.027139 INFO: [APUAPC] D2_APC_0: 0xffffffff
9915 16:31:27.030441 INFO: [APUAPC] D2_APC_1: 0xffffffff
9916 16:31:27.033856 INFO: [APUAPC] D2_APC_2: 0x3fffff
9917 16:31:27.036934 INFO: [APUAPC] D2_APC_3: 0x0
9918 16:31:27.040624 INFO: [APUAPC] D3_APC_0: 0xffffffff
9919 16:31:27.043847 INFO: [APUAPC] D3_APC_1: 0xffffffff
9920 16:31:27.047082 INFO: [APUAPC] D3_APC_2: 0x3fffff
9921 16:31:27.050284 INFO: [APUAPC] D3_APC_3: 0x0
9922 16:31:27.053514 INFO: [APUAPC] D4_APC_0: 0xffffffff
9923 16:31:27.057292 INFO: [APUAPC] D4_APC_1: 0xffffffff
9924 16:31:27.060453 INFO: [APUAPC] D4_APC_2: 0x3fffff
9925 16:31:27.063823 INFO: [APUAPC] D4_APC_3: 0x0
9926 16:31:27.067095 INFO: [APUAPC] D5_APC_0: 0xffffffff
9927 16:31:27.070378 INFO: [APUAPC] D5_APC_1: 0xffffffff
9928 16:31:27.073503 INFO: [APUAPC] D5_APC_2: 0x3fffff
9929 16:31:27.077258 INFO: [APUAPC] D5_APC_3: 0x0
9930 16:31:27.080438 INFO: [APUAPC] D6_APC_0: 0xffffffff
9931 16:31:27.083645 INFO: [APUAPC] D6_APC_1: 0xffffffff
9932 16:31:27.087246 INFO: [APUAPC] D6_APC_2: 0x3fffff
9933 16:31:27.090181 INFO: [APUAPC] D6_APC_3: 0x0
9934 16:31:27.093436 INFO: [APUAPC] D7_APC_0: 0xffffffff
9935 16:31:27.097168 INFO: [APUAPC] D7_APC_1: 0xffffffff
9936 16:31:27.100167 INFO: [APUAPC] D7_APC_2: 0x3fffff
9937 16:31:27.103645 INFO: [APUAPC] D7_APC_3: 0x0
9938 16:31:27.106857 INFO: [APUAPC] D8_APC_0: 0xffffffff
9939 16:31:27.110150 INFO: [APUAPC] D8_APC_1: 0xffffffff
9940 16:31:27.113894 INFO: [APUAPC] D8_APC_2: 0x3fffff
9941 16:31:27.117057 INFO: [APUAPC] D8_APC_3: 0x0
9942 16:31:27.120243 INFO: [APUAPC] D9_APC_0: 0xffffffff
9943 16:31:27.123615 INFO: [APUAPC] D9_APC_1: 0xffffffff
9944 16:31:27.126891 INFO: [APUAPC] D9_APC_2: 0x3fffff
9945 16:31:27.130147 INFO: [APUAPC] D9_APC_3: 0x0
9946 16:31:27.133477 INFO: [APUAPC] D10_APC_0: 0xffffffff
9947 16:31:27.136794 INFO: [APUAPC] D10_APC_1: 0xffffffff
9948 16:31:27.140023 INFO: [APUAPC] D10_APC_2: 0x3fffff
9949 16:31:27.143515 INFO: [APUAPC] D10_APC_3: 0x0
9950 16:31:27.146763 INFO: [APUAPC] D11_APC_0: 0xffffffff
9951 16:31:27.149825 INFO: [APUAPC] D11_APC_1: 0xffffffff
9952 16:31:27.153557 INFO: [APUAPC] D11_APC_2: 0x3fffff
9953 16:31:27.156589 INFO: [APUAPC] D11_APC_3: 0x0
9954 16:31:27.160349 INFO: [APUAPC] D12_APC_0: 0xffffffff
9955 16:31:27.163553 INFO: [APUAPC] D12_APC_1: 0xffffffff
9956 16:31:27.166883 INFO: [APUAPC] D12_APC_2: 0x3fffff
9957 16:31:27.170202 INFO: [APUAPC] D12_APC_3: 0x0
9958 16:31:27.173457 INFO: [APUAPC] D13_APC_0: 0xffffffff
9959 16:31:27.176559 INFO: [APUAPC] D13_APC_1: 0xffffffff
9960 16:31:27.180271 INFO: [APUAPC] D13_APC_2: 0x3fffff
9961 16:31:27.183592 INFO: [APUAPC] D13_APC_3: 0x0
9962 16:31:27.186867 INFO: [APUAPC] D14_APC_0: 0xffffffff
9963 16:31:27.190179 INFO: [APUAPC] D14_APC_1: 0xffffffff
9964 16:31:27.193448 INFO: [APUAPC] D14_APC_2: 0x3fffff
9965 16:31:27.196896 INFO: [APUAPC] D14_APC_3: 0x0
9966 16:31:27.199972 INFO: [APUAPC] D15_APC_0: 0xffffffff
9967 16:31:27.203421 INFO: [APUAPC] D15_APC_1: 0xffffffff
9968 16:31:27.206443 INFO: [APUAPC] D15_APC_2: 0x3fffff
9969 16:31:27.210048 INFO: [APUAPC] D15_APC_3: 0x0
9970 16:31:27.210159 INFO: [APUAPC] APC_CON: 0x4
9971 16:31:27.213281 INFO: [NOCDAPC] D0_APC_0: 0x0
9972 16:31:27.216483 INFO: [NOCDAPC] D0_APC_1: 0x0
9973 16:31:27.219741 INFO: [NOCDAPC] D1_APC_0: 0x0
9974 16:31:27.223397 INFO: [NOCDAPC] D1_APC_1: 0xfff
9975 16:31:27.226472 INFO: [NOCDAPC] D2_APC_0: 0x0
9976 16:31:27.229719 INFO: [NOCDAPC] D2_APC_1: 0xfff
9977 16:31:27.232963 INFO: [NOCDAPC] D3_APC_0: 0x0
9978 16:31:27.236725 INFO: [NOCDAPC] D3_APC_1: 0xfff
9979 16:31:27.239986 INFO: [NOCDAPC] D4_APC_0: 0x0
9980 16:31:27.243228 INFO: [NOCDAPC] D4_APC_1: 0xfff
9981 16:31:27.243330 INFO: [NOCDAPC] D5_APC_0: 0x0
9982 16:31:27.246355 INFO: [NOCDAPC] D5_APC_1: 0xfff
9983 16:31:27.249984 INFO: [NOCDAPC] D6_APC_0: 0x0
9984 16:31:27.253234 INFO: [NOCDAPC] D6_APC_1: 0xfff
9985 16:31:27.256349 INFO: [NOCDAPC] D7_APC_0: 0x0
9986 16:31:27.259901 INFO: [NOCDAPC] D7_APC_1: 0xfff
9987 16:31:27.263113 INFO: [NOCDAPC] D8_APC_0: 0x0
9988 16:31:27.266428 INFO: [NOCDAPC] D8_APC_1: 0xfff
9989 16:31:27.269803 INFO: [NOCDAPC] D9_APC_0: 0x0
9990 16:31:27.272957 INFO: [NOCDAPC] D9_APC_1: 0xfff
9991 16:31:27.276261 INFO: [NOCDAPC] D10_APC_0: 0x0
9992 16:31:27.276388 INFO: [NOCDAPC] D10_APC_1: 0xfff
9993 16:31:27.279425 INFO: [NOCDAPC] D11_APC_0: 0x0
9994 16:31:27.283097 INFO: [NOCDAPC] D11_APC_1: 0xfff
9995 16:31:27.286260 INFO: [NOCDAPC] D12_APC_0: 0x0
9996 16:31:27.289536 INFO: [NOCDAPC] D12_APC_1: 0xfff
9997 16:31:27.292792 INFO: [NOCDAPC] D13_APC_0: 0x0
9998 16:31:27.296445 INFO: [NOCDAPC] D13_APC_1: 0xfff
9999 16:31:27.299937 INFO: [NOCDAPC] D14_APC_0: 0x0
10000 16:31:27.303295 INFO: [NOCDAPC] D14_APC_1: 0xfff
10001 16:31:27.306551 INFO: [NOCDAPC] D15_APC_0: 0x0
10002 16:31:27.309700 INFO: [NOCDAPC] D15_APC_1: 0xfff
10003 16:31:27.313320 INFO: [NOCDAPC] APC_CON: 0x4
10004 16:31:27.316689 INFO: [APUAPC] set_apusys_apc done
10005 16:31:27.319566 INFO: [DEVAPC] devapc_init done
10006 16:31:27.323163 INFO: GICv3 without legacy support detected.
10007 16:31:27.326259 INFO: ARM GICv3 driver initialized in EL3
10008 16:31:27.329775 INFO: Maximum SPI INTID supported: 639
10009 16:31:27.332987 INFO: BL31: Initializing runtime services
10010 16:31:27.339563 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10011 16:31:27.342811 INFO: SPM: enable CPC mode
10012 16:31:27.346422 INFO: mcdi ready for mcusys-off-idle and system suspend
10013 16:31:27.353031 INFO: BL31: Preparing for EL3 exit to normal world
10014 16:31:27.356160 INFO: Entry point address = 0x80000000
10015 16:31:27.359418 INFO: SPSR = 0x8
10016 16:31:27.363648
10017 16:31:27.363732
10018 16:31:27.363797
10019 16:31:27.366966 Starting depthcharge on Spherion...
10020 16:31:27.367050
10021 16:31:27.367115 Wipe memory regions:
10022 16:31:27.367176
10023 16:31:27.367739 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10024 16:31:27.367837 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10025 16:31:27.367921 Setting prompt string to ['asurada:']
10026 16:31:27.368003 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10027 16:31:27.370806 [0x00000040000000, 0x00000054600000)
10028 16:31:27.492867
10029 16:31:27.493020 [0x00000054660000, 0x00000080000000)
10030 16:31:27.753342
10031 16:31:27.753502 [0x000000821a7280, 0x000000ffe64000)
10032 16:31:28.499032
10033 16:31:28.499597 [0x00000100000000, 0x00000240000000)
10034 16:31:30.388244
10035 16:31:30.391721 Initializing XHCI USB controller at 0x11200000.
10036 16:31:31.430790
10037 16:31:31.433901 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10038 16:31:31.434370
10039 16:31:31.434818
10040 16:31:31.435708 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10042 16:31:31.537149 asurada: tftpboot 192.168.201.1 14396158/tftp-deploy-it13sxei/kernel/image.itb 14396158/tftp-deploy-it13sxei/kernel/cmdline
10043 16:31:31.537979 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10044 16:31:31.538659 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10045 16:31:31.543965 tftpboot 192.168.201.1 14396158/tftp-deploy-it13sxei/kernel/image.ittp-deploy-it13sxei/kernel/cmdline
10046 16:31:31.544623
10047 16:31:31.545169 Waiting for link
10048 16:31:31.700393
10049 16:31:31.700560 R8152: Initializing
10050 16:31:31.700661
10051 16:31:31.703500 Version 9 (ocp_data = 6010)
10052 16:31:31.703603
10053 16:31:31.707110 R8152: Done initializing
10054 16:31:31.707206
10055 16:31:31.707295 Adding net device
10056 16:31:33.578018
10057 16:31:33.578239 done.
10058 16:31:33.578363
10059 16:31:33.578444 MAC: 00:e0:4c:72:2d:d6
10060 16:31:33.578507
10061 16:31:33.581407 Sending DHCP discover... done.
10062 16:31:33.581546
10063 16:31:33.584519 Waiting for reply... done.
10064 16:31:33.584684
10065 16:31:33.587903 Sending DHCP request... done.
10066 16:31:33.588022
10067 16:31:33.588117 Waiting for reply... done.
10068 16:31:33.588207
10069 16:31:33.591011 My ip is 192.168.201.21
10070 16:31:33.591145
10071 16:31:33.594734 The DHCP server ip is 192.168.201.1
10072 16:31:33.594847
10073 16:31:33.597952 TFTP server IP predefined by user: 192.168.201.1
10074 16:31:33.598037
10075 16:31:33.604430 Bootfile predefined by user: 14396158/tftp-deploy-it13sxei/kernel/image.itb
10076 16:31:33.604540
10077 16:31:33.607712 Sending tftp read request... done.
10078 16:31:33.607795
10079 16:31:33.610848 Waiting for the transfer...
10080 16:31:33.610932
10081 16:31:33.866103 00000000 ################################################################
10082 16:31:33.866243
10083 16:31:34.118520 00080000 ################################################################
10084 16:31:34.118695
10085 16:31:34.390441 00100000 ################################################################
10086 16:31:34.390609
10087 16:31:34.647747 00180000 ################################################################
10088 16:31:34.647881
10089 16:31:34.915083 00200000 ################################################################
10090 16:31:34.915256
10091 16:31:35.180919 00280000 ################################################################
10092 16:31:35.181086
10093 16:31:35.461086 00300000 ################################################################
10094 16:31:35.461229
10095 16:31:35.717699 00380000 ################################################################
10096 16:31:35.717840
10097 16:31:35.987205 00400000 ################################################################
10098 16:31:35.987343
10099 16:31:36.252502 00480000 ################################################################
10100 16:31:36.252682
10101 16:31:36.530165 00500000 ################################################################
10102 16:31:36.530332
10103 16:31:36.801158 00580000 ################################################################
10104 16:31:36.801321
10105 16:31:37.058392 00600000 ################################################################
10106 16:31:37.058554
10107 16:31:37.310755 00680000 ################################################################
10108 16:31:37.310899
10109 16:31:37.568879 00700000 ################################################################
10110 16:31:37.569011
10111 16:31:37.833125 00780000 ################################################################
10112 16:31:37.833275
10113 16:31:38.094141 00800000 ################################################################
10114 16:31:38.094293
10115 16:31:38.359820 00880000 ################################################################
10116 16:31:38.359963
10117 16:31:38.622630 00900000 ################################################################
10118 16:31:38.622803
10119 16:31:38.882035 00980000 ################################################################
10120 16:31:38.882202
10121 16:31:39.156108 00a00000 ################################################################
10122 16:31:39.156291
10123 16:31:39.412540 00a80000 ################################################################
10124 16:31:39.412696
10125 16:31:39.674892 00b00000 ################################################################
10126 16:31:39.675055
10127 16:31:39.938949 00b80000 ################################################################
10128 16:31:39.939131
10129 16:31:40.190565 00c00000 ################################################################
10130 16:31:40.190758
10131 16:31:40.467270 00c80000 ################################################################
10132 16:31:40.467496
10133 16:31:40.746913 00d00000 ################################################################
10134 16:31:40.747068
10135 16:31:41.011382 00d80000 ################################################################
10136 16:31:41.011564
10137 16:31:41.271005 00e00000 ################################################################
10138 16:31:41.271155
10139 16:31:41.536553 00e80000 ################################################################
10140 16:31:41.536803
10141 16:31:41.811309 00f00000 ################################################################
10142 16:31:41.811459
10143 16:31:42.071955 00f80000 ################################################################
10144 16:31:42.072138
10145 16:31:42.346749 01000000 ################################################################
10146 16:31:42.346930
10147 16:31:42.607177 01080000 ################################################################
10148 16:31:42.607342
10149 16:31:42.861394 01100000 ################################################################
10150 16:31:42.861535
10151 16:31:43.122267 01180000 ################################################################
10152 16:31:43.122413
10153 16:31:43.379924 01200000 ################################################################
10154 16:31:43.380061
10155 16:31:43.639730 01280000 ################################################################
10156 16:31:43.639916
10157 16:31:43.895338 01300000 ################################################################
10158 16:31:43.895514
10159 16:31:44.148917 01380000 ################################################################
10160 16:31:44.149182
10161 16:31:44.405143 01400000 ################################################################
10162 16:31:44.405295
10163 16:31:44.654683 01480000 ################################################################
10164 16:31:44.654852
10165 16:31:44.910712 01500000 ################################################################
10166 16:31:44.910926
10167 16:31:45.177442 01580000 ################################################################
10168 16:31:45.177582
10169 16:31:45.435449 01600000 ################################################################
10170 16:31:45.435599
10171 16:31:45.694742 01680000 ################################################################
10172 16:31:45.694896
10173 16:31:45.952227 01700000 ################################################################
10174 16:31:45.952373
10175 16:31:46.226832 01780000 ################################################################
10176 16:31:46.226975
10177 16:31:46.488705 01800000 ################################################################
10178 16:31:46.488887
10179 16:31:46.736938 01880000 ################################################################
10180 16:31:46.737089
10181 16:31:46.990460 01900000 ################################################################
10182 16:31:46.990613
10183 16:31:47.238241 01980000 ################################################################
10184 16:31:47.238422
10185 16:31:47.513842 01a00000 ################################################################
10186 16:31:47.514023
10187 16:31:47.765179 01a80000 ################################################################
10188 16:31:47.765350
10189 16:31:48.013948 01b00000 ################################################################
10190 16:31:48.014128
10191 16:31:48.270106 01b80000 ################################################################
10192 16:31:48.270264
10193 16:31:48.522001 01c00000 ################################################################
10194 16:31:48.522180
10195 16:31:48.778425 01c80000 ################################################################
10196 16:31:48.778580
10197 16:31:49.036091 01d00000 ################################################################
10198 16:31:49.036273
10199 16:31:49.326099 01d80000 ################################################################
10200 16:31:49.326280
10201 16:31:49.653722 01e00000 ################################################################
10202 16:31:49.653927
10203 16:31:49.978895 01e80000 ################################################################
10204 16:31:49.979096
10205 16:31:50.238309 01f00000 ################################################################
10206 16:31:50.238463
10207 16:31:50.490974 01f80000 ################################################################
10208 16:31:50.491146
10209 16:31:50.748873 02000000 ################################################################
10210 16:31:50.749107
10211 16:31:50.993183 02080000 ########################################################## done.
10212 16:31:50.993372
10213 16:31:50.997041 The bootfile was 34550170 bytes long.
10214 16:31:50.997164
10215 16:31:51.000411 Sending tftp read request... done.
10216 16:31:51.000526
10217 16:31:51.003478 Waiting for the transfer...
10218 16:31:51.003594
10219 16:31:51.006737 00000000 # done.
10220 16:31:51.006850
10221 16:31:51.013254 Command line loaded dynamically from TFTP file: 14396158/tftp-deploy-it13sxei/kernel/cmdline
10222 16:31:51.013363
10223 16:31:51.026304 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10224 16:31:51.026451
10225 16:31:51.026558 Loading FIT.
10226 16:31:51.026661
10227 16:31:51.029749 Image ramdisk-1 has 21372124 bytes.
10228 16:31:51.029842
10229 16:31:51.033360 Image fdt-1 has 47258 bytes.
10230 16:31:51.033477
10231 16:31:51.036506 Image kernel-1 has 13128753 bytes.
10232 16:31:51.036607
10233 16:31:51.046140 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10234 16:31:51.046298
10235 16:31:51.062742 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10236 16:31:51.062913
10237 16:31:51.069150 Choosing best match conf-1 for compat google,spherion-rev2.
10238 16:31:51.069266
10239 16:31:51.077260 Connected to device vid:did:rid of 1ae0:0028:00
10240 16:31:51.085369
10241 16:31:51.088652 tpm_get_response: command 0x17b, return code 0x0
10242 16:31:51.088786
10243 16:31:51.095566 ec_init: CrosEC protocol v3 supported (256, 248)
10244 16:31:51.095676
10245 16:31:51.098688 tpm_cleanup: add release locality here.
10246 16:31:51.098807
10247 16:31:51.101953 Shutting down all USB controllers.
10248 16:31:51.102068
10249 16:31:51.105194 Removing current net device
10250 16:31:51.105286
10251 16:31:51.111621 Exiting depthcharge with code 4 at timestamp: 53046483
10252 16:31:51.111732
10253 16:31:51.115266 LZMA decompressing kernel-1 to 0x821a6718
10254 16:31:51.115386
10255 16:31:51.118608 LZMA decompressing kernel-1 to 0x40000000
10256 16:31:52.735003
10257 16:31:52.735180 jumping to kernel
10258 16:31:52.736082 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10259 16:31:52.736237 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10260 16:31:52.736355 Setting prompt string to ['Linux version [0-9]']
10261 16:31:52.736467 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10262 16:31:52.736589 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10263 16:31:52.816933
10264 16:31:52.820105 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10265 16:31:52.823553 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10266 16:31:52.823662 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10267 16:31:52.823739 Setting prompt string to []
10268 16:31:52.823816 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10269 16:31:52.823894 Using line separator: #'\n'#
10270 16:31:52.823955 No login prompt set.
10271 16:31:52.824016 Parsing kernel messages
10272 16:31:52.824073 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10273 16:31:52.824180 [login-action] Waiting for messages, (timeout 00:04:02)
10274 16:31:52.824247 Waiting using forced prompt support (timeout 00:02:01)
10275 16:31:52.843389 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10276 16:31:52.846769 [ 0.000000] random: crng init done
10277 16:31:52.853353 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10278 16:31:52.856533 [ 0.000000] efi: UEFI not found.
10279 16:31:52.863054 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10280 16:31:52.873222 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10281 16:31:52.879665 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10282 16:31:52.889758 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10283 16:31:52.896318 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10284 16:31:52.902924 [ 0.000000] printk: bootconsole [mtk8250] enabled
10285 16:31:52.909524 [ 0.000000] NUMA: No NUMA configuration found
10286 16:31:52.915804 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10287 16:31:52.919130 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10288 16:31:52.922880 [ 0.000000] Zone ranges:
10289 16:31:52.929423 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10290 16:31:52.932632 [ 0.000000] DMA32 empty
10291 16:31:52.939194 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10292 16:31:52.942718 [ 0.000000] Movable zone start for each node
10293 16:31:52.945634 [ 0.000000] Early memory node ranges
10294 16:31:52.952723 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10295 16:31:52.959228 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10296 16:31:52.965709 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10297 16:31:52.972522 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10298 16:31:52.975586 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10299 16:31:52.985604 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10300 16:31:53.041586 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10301 16:31:53.048015 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10302 16:31:53.054728 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10303 16:31:53.057964 [ 0.000000] psci: probing for conduit method from DT.
10304 16:31:53.064917 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10305 16:31:53.068173 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10306 16:31:53.074789 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10307 16:31:53.078064 [ 0.000000] psci: SMC Calling Convention v1.2
10308 16:31:53.084507 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10309 16:31:53.088083 [ 0.000000] Detected VIPT I-cache on CPU0
10310 16:31:53.094569 [ 0.000000] CPU features: detected: GIC system register CPU interface
10311 16:31:53.100825 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10312 16:31:53.107663 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10313 16:31:53.114183 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10314 16:31:53.124228 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10315 16:31:53.130590 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10316 16:31:53.133856 [ 0.000000] alternatives: applying boot alternatives
10317 16:31:53.140451 [ 0.000000] Fallback order for Node 0: 0
10318 16:31:53.147536 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10319 16:31:53.150611 [ 0.000000] Policy zone: Normal
10320 16:31:53.163941 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10321 16:31:53.173900 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10322 16:31:53.185933 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10323 16:31:53.196057 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10324 16:31:53.202712 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10325 16:31:53.205710 <6>[ 0.000000] software IO TLB: area num 8.
10326 16:31:53.263089 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10327 16:31:53.412736 <6>[ 0.000000] Memory: 7943188K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 409580K reserved, 32768K cma-reserved)
10328 16:31:53.419210 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10329 16:31:53.425708 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10330 16:31:53.429079 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10331 16:31:53.435525 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10332 16:31:53.442366 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10333 16:31:53.445643 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10334 16:31:53.455383 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10335 16:31:53.461894 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10336 16:31:53.468348 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10337 16:31:53.474941 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10338 16:31:53.478224 <6>[ 0.000000] GICv3: 608 SPIs implemented
10339 16:31:53.481970 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10340 16:31:53.488499 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10341 16:31:53.491693 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10342 16:31:53.498173 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10343 16:31:53.511410 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10344 16:31:53.524697 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10345 16:31:53.531181 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10346 16:31:53.539244 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10347 16:31:53.552537 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10348 16:31:53.559137 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10349 16:31:53.565615 <6>[ 0.009204] Console: colour dummy device 80x25
10350 16:31:53.575549 <6>[ 0.013923] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10351 16:31:53.582178 <6>[ 0.024429] pid_max: default: 32768 minimum: 301
10352 16:31:53.585402 <6>[ 0.029331] LSM: Security Framework initializing
10353 16:31:53.592295 <6>[ 0.034270] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10354 16:31:53.601885 <6>[ 0.042133] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10355 16:31:53.611947 <6>[ 0.051597] cblist_init_generic: Setting adjustable number of callback queues.
10356 16:31:53.615151 <6>[ 0.059041] cblist_init_generic: Setting shift to 3 and lim to 1.
10357 16:31:53.625528 <6>[ 0.065381] cblist_init_generic: Setting adjustable number of callback queues.
10358 16:31:53.631629 <6>[ 0.072807] cblist_init_generic: Setting shift to 3 and lim to 1.
10359 16:31:53.635126 <6>[ 0.079247] rcu: Hierarchical SRCU implementation.
10360 16:31:53.641746 <6>[ 0.084293] rcu: Max phase no-delay instances is 1000.
10361 16:31:53.648404 <6>[ 0.091316] EFI services will not be available.
10362 16:31:53.651715 <6>[ 0.096306] smp: Bringing up secondary CPUs ...
10363 16:31:53.660567 <6>[ 0.101355] Detected VIPT I-cache on CPU1
10364 16:31:53.666978 <6>[ 0.101426] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10365 16:31:53.673316 <6>[ 0.101460] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10366 16:31:53.676969 <6>[ 0.101799] Detected VIPT I-cache on CPU2
10367 16:31:53.683602 <6>[ 0.101853] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10368 16:31:53.693369 <6>[ 0.101871] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10369 16:31:53.696642 <6>[ 0.102132] Detected VIPT I-cache on CPU3
10370 16:31:53.703051 <6>[ 0.102180] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10371 16:31:53.710033 <6>[ 0.102195] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10372 16:31:53.713292 <6>[ 0.102500] CPU features: detected: Spectre-v4
10373 16:31:53.719711 <6>[ 0.102506] CPU features: detected: Spectre-BHB
10374 16:31:53.722968 <6>[ 0.102511] Detected PIPT I-cache on CPU4
10375 16:31:53.729806 <6>[ 0.102570] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10376 16:31:53.736488 <6>[ 0.102587] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10377 16:31:53.743018 <6>[ 0.102879] Detected PIPT I-cache on CPU5
10378 16:31:53.749853 <6>[ 0.102941] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10379 16:31:53.756216 <6>[ 0.102957] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10380 16:31:53.759650 <6>[ 0.103239] Detected PIPT I-cache on CPU6
10381 16:31:53.766163 <6>[ 0.103305] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10382 16:31:53.772876 <6>[ 0.103321] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10383 16:31:53.779605 <6>[ 0.103620] Detected PIPT I-cache on CPU7
10384 16:31:53.786360 <6>[ 0.103684] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10385 16:31:53.792787 <6>[ 0.103700] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10386 16:31:53.796098 <6>[ 0.103747] smp: Brought up 1 node, 8 CPUs
10387 16:31:53.802685 <6>[ 0.245161] SMP: Total of 8 processors activated.
10388 16:31:53.806028 <6>[ 0.250082] CPU features: detected: 32-bit EL0 Support
10389 16:31:53.816082 <6>[ 0.255479] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10390 16:31:53.822492 <6>[ 0.264280] CPU features: detected: Common not Private translations
10391 16:31:53.828910 <6>[ 0.270795] CPU features: detected: CRC32 instructions
10392 16:31:53.832294 <6>[ 0.276147] CPU features: detected: RCpc load-acquire (LDAPR)
10393 16:31:53.839041 <6>[ 0.282144] CPU features: detected: LSE atomic instructions
10394 16:31:53.845837 <6>[ 0.287961] CPU features: detected: Privileged Access Never
10395 16:31:53.852127 <6>[ 0.293741] CPU features: detected: RAS Extension Support
10396 16:31:53.858977 <6>[ 0.299349] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10397 16:31:53.862260 <6>[ 0.306567] CPU: All CPU(s) started at EL2
10398 16:31:53.868674 <6>[ 0.310910] alternatives: applying system-wide alternatives
10399 16:31:53.878309 <6>[ 0.321763] devtmpfs: initialized
10400 16:31:53.890531 <6>[ 0.330709] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10401 16:31:53.900578 <6>[ 0.340671] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10402 16:31:53.907044 <6>[ 0.348686] pinctrl core: initialized pinctrl subsystem
10403 16:31:53.910295 <6>[ 0.355377] DMI not present or invalid.
10404 16:31:53.916670 <6>[ 0.359792] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10405 16:31:53.926631 <6>[ 0.366609] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10406 16:31:53.933571 <6>[ 0.374199] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10407 16:31:53.943126 <6>[ 0.382414] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10408 16:31:53.946458 <6>[ 0.390658] audit: initializing netlink subsys (disabled)
10409 16:31:53.956114 <5>[ 0.396352] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10410 16:31:53.962660 <6>[ 0.397074] thermal_sys: Registered thermal governor 'step_wise'
10411 16:31:53.969551 <6>[ 0.404321] thermal_sys: Registered thermal governor 'power_allocator'
10412 16:31:53.972756 <6>[ 0.410577] cpuidle: using governor menu
10413 16:31:53.979256 <6>[ 0.421540] NET: Registered PF_QIPCRTR protocol family
10414 16:31:53.985780 <6>[ 0.427015] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10415 16:31:53.992467 <6>[ 0.434117] ASID allocator initialised with 32768 entries
10416 16:31:53.995738 <6>[ 0.440704] Serial: AMBA PL011 UART driver
10417 16:31:54.005935 <4>[ 0.449525] Trying to register duplicate clock ID: 134
10418 16:31:54.065727 <6>[ 0.512521] KASLR enabled
10419 16:31:54.079638 <6>[ 0.520215] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10420 16:31:54.086833 <6>[ 0.527228] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10421 16:31:54.093062 <6>[ 0.533718] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10422 16:31:54.099529 <6>[ 0.540727] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10423 16:31:54.106486 <6>[ 0.547216] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10424 16:31:54.112571 <6>[ 0.554222] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10425 16:31:54.119656 <6>[ 0.560708] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10426 16:31:54.125974 <6>[ 0.567711] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10427 16:31:54.129216 <6>[ 0.575174] ACPI: Interpreter disabled.
10428 16:31:54.138187 <6>[ 0.581611] iommu: Default domain type: Translated
10429 16:31:54.144523 <6>[ 0.586763] iommu: DMA domain TLB invalidation policy: strict mode
10430 16:31:54.147804 <5>[ 0.593424] SCSI subsystem initialized
10431 16:31:54.154791 <6>[ 0.597669] usbcore: registered new interface driver usbfs
10432 16:31:54.161269 <6>[ 0.603400] usbcore: registered new interface driver hub
10433 16:31:54.164306 <6>[ 0.608953] usbcore: registered new device driver usb
10434 16:31:54.171714 <6>[ 0.615069] pps_core: LinuxPPS API ver. 1 registered
10435 16:31:54.181388 <6>[ 0.620262] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10436 16:31:54.184667 <6>[ 0.629604] PTP clock support registered
10437 16:31:54.187942 <6>[ 0.633839] EDAC MC: Ver: 3.0.0
10438 16:31:54.195483 <6>[ 0.639028] FPGA manager framework
10439 16:31:54.201866 <6>[ 0.642706] Advanced Linux Sound Architecture Driver Initialized.
10440 16:31:54.205265 <6>[ 0.649487] vgaarb: loaded
10441 16:31:54.212182 <6>[ 0.652635] clocksource: Switched to clocksource arch_sys_counter
10442 16:31:54.215411 <5>[ 0.659082] VFS: Disk quotas dquot_6.6.0
10443 16:31:54.221755 <6>[ 0.663267] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10444 16:31:54.225442 <6>[ 0.670464] pnp: PnP ACPI: disabled
10445 16:31:54.233597 <6>[ 0.677212] NET: Registered PF_INET protocol family
10446 16:31:54.243369 <6>[ 0.682803] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10447 16:31:54.254691 <6>[ 0.695141] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10448 16:31:54.264983 <6>[ 0.703956] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10449 16:31:54.271654 <6>[ 0.711929] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10450 16:31:54.281513 <6>[ 0.720633] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10451 16:31:54.287802 <6>[ 0.730384] TCP: Hash tables configured (established 65536 bind 65536)
10452 16:31:54.294444 <6>[ 0.737249] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10453 16:31:54.304453 <6>[ 0.744449] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10454 16:31:54.307834 <6>[ 0.752160] NET: Registered PF_UNIX/PF_LOCAL protocol family
10455 16:31:54.314955 <6>[ 0.758308] RPC: Registered named UNIX socket transport module.
10456 16:31:54.321635 <6>[ 0.764463] RPC: Registered udp transport module.
10457 16:31:54.324802 <6>[ 0.769396] RPC: Registered tcp transport module.
10458 16:31:54.331230 <6>[ 0.774329] RPC: Registered tcp NFSv4.1 backchannel transport module.
10459 16:31:54.337704 <6>[ 0.780996] PCI: CLS 0 bytes, default 64
10460 16:31:54.341302 <6>[ 0.785370] Unpacking initramfs...
10461 16:31:54.347698 <6>[ 0.789092] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10462 16:31:54.357681 <6>[ 0.797730] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10463 16:31:54.361448 <6>[ 0.806530] kvm [1]: IPA Size Limit: 40 bits
10464 16:31:54.367946 <6>[ 0.811057] kvm [1]: GICv3: no GICV resource entry
10465 16:31:54.371116 <6>[ 0.816078] kvm [1]: disabling GICv2 emulation
10466 16:31:54.377769 <6>[ 0.820766] kvm [1]: GIC system register CPU interface enabled
10467 16:31:54.380685 <6>[ 0.826929] kvm [1]: vgic interrupt IRQ18
10468 16:31:54.388901 <6>[ 0.832708] kvm [1]: VHE mode initialized successfully
10469 16:31:54.395525 <5>[ 0.839146] Initialise system trusted keyrings
10470 16:31:54.402278 <6>[ 0.843945] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10471 16:31:54.410115 <6>[ 0.853930] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10472 16:31:54.417090 <5>[ 0.860314] NFS: Registering the id_resolver key type
10473 16:31:54.420323 <5>[ 0.865615] Key type id_resolver registered
10474 16:31:54.427002 <5>[ 0.870029] Key type id_legacy registered
10475 16:31:54.433308 <6>[ 0.874312] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10476 16:31:54.440448 <6>[ 0.881234] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10477 16:31:54.446813 <6>[ 0.888945] 9p: Installing v9fs 9p2000 file system support
10478 16:31:54.483089 <5>[ 0.926721] Key type asymmetric registered
10479 16:31:54.486183 <5>[ 0.931054] Asymmetric key parser 'x509' registered
10480 16:31:54.496296 <6>[ 0.936188] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10481 16:31:54.499804 <6>[ 0.943804] io scheduler mq-deadline registered
10482 16:31:54.502880 <6>[ 0.948565] io scheduler kyber registered
10483 16:31:54.522046 <6>[ 0.965716] EINJ: ACPI disabled.
10484 16:31:54.554862 <4>[ 0.992159] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10485 16:31:54.565208 <4>[ 1.002751] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10486 16:31:54.579987 <6>[ 1.023584] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10487 16:31:54.587595 <6>[ 1.031448] printk: console [ttyS0] disabled
10488 16:31:54.615833 <6>[ 1.056072] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10489 16:31:54.622262 <6>[ 1.065548] printk: console [ttyS0] enabled
10490 16:31:54.625593 <6>[ 1.065548] printk: console [ttyS0] enabled
10491 16:31:54.632172 <6>[ 1.074445] printk: bootconsole [mtk8250] disabled
10492 16:31:54.635376 <6>[ 1.074445] printk: bootconsole [mtk8250] disabled
10493 16:31:54.642319 <6>[ 1.085459] SuperH (H)SCI(F) driver initialized
10494 16:31:54.645603 <6>[ 1.090724] msm_serial: driver initialized
10495 16:31:54.659550 <6>[ 1.099629] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10496 16:31:54.669390 <6>[ 1.108176] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10497 16:31:54.675968 <6>[ 1.116718] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10498 16:31:54.685791 <6>[ 1.125346] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10499 16:31:54.692535 <6>[ 1.134054] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10500 16:31:54.702798 <6>[ 1.142772] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10501 16:31:54.712297 <6>[ 1.151312] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10502 16:31:54.719322 <6>[ 1.160107] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10503 16:31:54.728781 <6>[ 1.168652] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10504 16:31:54.740624 <6>[ 1.184126] loop: module loaded
10505 16:31:54.747189 <6>[ 1.190082] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10506 16:31:54.769808 <4>[ 1.213430] mtk-pmic-keys: Failed to locate of_node [id: -1]
10507 16:31:54.776210 <6>[ 1.220213] megasas: 07.719.03.00-rc1
10508 16:31:54.785878 <6>[ 1.229751] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10509 16:31:54.792916 <6>[ 1.236116] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10510 16:31:54.809146 <6>[ 1.252646] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10511 16:31:54.864874 <6>[ 1.302045] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10512 16:31:55.246566 <6>[ 1.690340] Freeing initrd memory: 20868K
10513 16:31:55.262615 <6>[ 1.706237] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10514 16:31:55.273434 <6>[ 1.717115] tun: Universal TUN/TAP device driver, 1.6
10515 16:31:55.276732 <6>[ 1.723170] thunder_xcv, ver 1.0
10516 16:31:55.280327 <6>[ 1.726677] thunder_bgx, ver 1.0
10517 16:31:55.283129 <6>[ 1.730173] nicpf, ver 1.0
10518 16:31:55.293618 <6>[ 1.734191] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10519 16:31:55.297293 <6>[ 1.741668] hns3: Copyright (c) 2017 Huawei Corporation.
10520 16:31:55.300473 <6>[ 1.747254] hclge is initializing
10521 16:31:55.307004 <6>[ 1.750841] e1000: Intel(R) PRO/1000 Network Driver
10522 16:31:55.313904 <6>[ 1.755971] e1000: Copyright (c) 1999-2006 Intel Corporation.
10523 16:31:55.317208 <6>[ 1.761984] e1000e: Intel(R) PRO/1000 Network Driver
10524 16:31:55.323702 <6>[ 1.767199] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10525 16:31:55.330641 <6>[ 1.773383] igb: Intel(R) Gigabit Ethernet Network Driver
10526 16:31:55.337153 <6>[ 1.779034] igb: Copyright (c) 2007-2014 Intel Corporation.
10527 16:31:55.343805 <6>[ 1.784873] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10528 16:31:55.347047 <6>[ 1.791390] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10529 16:31:55.353943 <6>[ 1.797853] sky2: driver version 1.30
10530 16:31:55.360890 <6>[ 1.802776] usbcore: registered new device driver r8152-cfgselector
10531 16:31:55.367202 <6>[ 1.809310] usbcore: registered new interface driver r8152
10532 16:31:55.370572 <6>[ 1.815121] VFIO - User Level meta-driver version: 0.3
10533 16:31:55.379878 <6>[ 1.823362] usbcore: registered new interface driver usb-storage
10534 16:31:55.386370 <6>[ 1.829803] usbcore: registered new device driver onboard-usb-hub
10535 16:31:55.395045 <6>[ 1.838922] mt6397-rtc mt6359-rtc: registered as rtc0
10536 16:31:55.405264 <6>[ 1.844391] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:30:29 UTC (1718641829)
10537 16:31:55.408575 <6>[ 1.853951] i2c_dev: i2c /dev entries driver
10538 16:31:55.422126 <4>[ 1.865894] cpu cpu0: supply cpu not found, using dummy regulator
10539 16:31:55.428838 <4>[ 1.872320] cpu cpu1: supply cpu not found, using dummy regulator
10540 16:31:55.435427 <4>[ 1.878727] cpu cpu2: supply cpu not found, using dummy regulator
10541 16:31:55.441947 <4>[ 1.885142] cpu cpu3: supply cpu not found, using dummy regulator
10542 16:31:55.448912 <4>[ 1.891540] cpu cpu4: supply cpu not found, using dummy regulator
10543 16:31:55.455506 <4>[ 1.897942] cpu cpu5: supply cpu not found, using dummy regulator
10544 16:31:55.462064 <4>[ 1.904339] cpu cpu6: supply cpu not found, using dummy regulator
10545 16:31:55.468521 <4>[ 1.910735] cpu cpu7: supply cpu not found, using dummy regulator
10546 16:31:55.487668 <6>[ 1.931384] cpu cpu0: EM: created perf domain
10547 16:31:55.490960 <6>[ 1.936301] cpu cpu4: EM: created perf domain
10548 16:31:55.498023 <6>[ 1.941625] sdhci: Secure Digital Host Controller Interface driver
10549 16:31:55.504775 <6>[ 1.948057] sdhci: Copyright(c) Pierre Ossman
10550 16:31:55.511390 <6>[ 1.953015] Synopsys Designware Multimedia Card Interface Driver
10551 16:31:55.518271 <6>[ 1.959648] sdhci-pltfm: SDHCI platform and OF driver helper
10552 16:31:55.521522 <6>[ 1.959704] mmc0: CQHCI version 5.10
10553 16:31:55.528035 <6>[ 1.969982] ledtrig-cpu: registered to indicate activity on CPUs
10554 16:31:55.534924 <6>[ 1.976990] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10555 16:31:55.541429 <6>[ 1.984036] usbcore: registered new interface driver usbhid
10556 16:31:55.544807 <6>[ 1.989859] usbhid: USB HID core driver
10557 16:31:55.551544 <6>[ 1.994060] spi_master spi0: will run message pump with realtime priority
10558 16:31:55.598762 <6>[ 2.035818] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10559 16:31:55.618032 <6>[ 2.051922] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10560 16:31:55.621268 <6>[ 2.061851] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10561 16:31:55.628867 <6>[ 2.072450] cros-ec-spi spi0.0: Chrome EC device registered
10562 16:31:55.635787 <6>[ 2.078437] mmc0: Command Queue Engine enabled
10563 16:31:55.642151 <6>[ 2.083163] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10564 16:31:55.645404 <6>[ 2.090588] mmcblk0: mmc0:0001 DA4128 116 GiB
10565 16:31:55.655173 <6>[ 2.098824] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10566 16:31:55.662226 <6>[ 2.106104] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10567 16:31:55.669087 <6>[ 2.111952] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10568 16:31:55.679197 <6>[ 2.117350] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10569 16:31:55.686115 <6>[ 2.117823] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10570 16:31:55.689306 <6>[ 2.128046] NET: Registered PF_PACKET protocol family
10571 16:31:55.696034 <6>[ 2.138590] 9pnet: Installing 9P2000 support
10572 16:31:55.699264 <5>[ 2.143157] Key type dns_resolver registered
10573 16:31:55.702614 <6>[ 2.148159] registered taskstats version 1
10574 16:31:55.709229 <5>[ 2.152545] Loading compiled-in X.509 certificates
10575 16:31:55.739053 <4>[ 2.176085] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10576 16:31:55.748973 <4>[ 2.186863] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10577 16:31:55.763123 <6>[ 2.206722] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10578 16:31:55.770117 <6>[ 2.213692] xhci-mtk 11200000.usb: xHCI Host Controller
10579 16:31:55.776729 <6>[ 2.219206] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10580 16:31:55.786890 <6>[ 2.227070] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10581 16:31:55.793541 <6>[ 2.236500] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10582 16:31:55.800371 <6>[ 2.242681] xhci-mtk 11200000.usb: xHCI Host Controller
10583 16:31:55.806516 <6>[ 2.248182] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10584 16:31:55.813118 <6>[ 2.255842] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10585 16:31:55.820123 <6>[ 2.263656] hub 1-0:1.0: USB hub found
10586 16:31:55.823624 <6>[ 2.267682] hub 1-0:1.0: 1 port detected
10587 16:31:55.833110 <6>[ 2.271982] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10588 16:31:55.836439 <6>[ 2.280756] hub 2-0:1.0: USB hub found
10589 16:31:55.839688 <6>[ 2.284778] hub 2-0:1.0: 1 port detected
10590 16:31:55.847878 <6>[ 2.291662] mtk-msdc 11f70000.mmc: Got CD GPIO
10591 16:31:55.865859 <6>[ 2.306349] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10592 16:31:55.875704 <6>[ 2.314734] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10593 16:31:55.882672 <6>[ 2.323075] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10594 16:31:55.892447 <6>[ 2.331413] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10595 16:31:55.899185 <6>[ 2.339753] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10596 16:31:55.909292 <6>[ 2.348091] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10597 16:31:55.915931 <6>[ 2.356429] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10598 16:31:55.925602 <6>[ 2.364768] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10599 16:31:55.932100 <6>[ 2.373105] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10600 16:31:55.942090 <6>[ 2.381443] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10601 16:31:55.948709 <6>[ 2.389780] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10602 16:31:55.958552 <6>[ 2.398127] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10603 16:31:55.965340 <6>[ 2.406465] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10604 16:31:55.975150 <6>[ 2.414803] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10605 16:31:55.981757 <6>[ 2.423141] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10606 16:31:55.988258 <6>[ 2.431847] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10607 16:31:55.995420 <6>[ 2.439001] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10608 16:31:56.002286 <6>[ 2.445802] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10609 16:31:56.012289 <6>[ 2.452566] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10610 16:31:56.018771 <6>[ 2.459551] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10611 16:31:56.025163 <6>[ 2.466419] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10612 16:31:56.034991 <6>[ 2.475553] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10613 16:31:56.045302 <6>[ 2.484675] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10614 16:31:56.054910 <6>[ 2.493968] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10615 16:31:56.064916 <6>[ 2.503434] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10616 16:31:56.071531 <6>[ 2.512906] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10617 16:31:56.081929 <6>[ 2.522027] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10618 16:31:56.091528 <6>[ 2.531493] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10619 16:31:56.101540 <6>[ 2.540613] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10620 16:31:56.111457 <6>[ 2.549910] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10621 16:31:56.121700 <6>[ 2.560069] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10622 16:31:56.131857 <6>[ 2.572191] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10623 16:31:56.252221 <6>[ 2.692916] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10624 16:31:56.407316 <6>[ 2.850891] hub 1-1:1.0: USB hub found
10625 16:31:56.410491 <6>[ 2.855416] hub 1-1:1.0: 4 ports detected
10626 16:31:56.422478 <6>[ 2.866168] hub 1-1:1.0: USB hub found
10627 16:31:56.425685 <6>[ 2.870521] hub 1-1:1.0: 4 ports detected
10628 16:31:56.532626 <6>[ 2.973241] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10629 16:31:56.558130 <6>[ 3.001676] hub 2-1:1.0: USB hub found
10630 16:31:56.561171 <6>[ 3.006145] hub 2-1:1.0: 3 ports detected
10631 16:31:56.572407 <6>[ 3.015775] hub 2-1:1.0: USB hub found
10632 16:31:56.575114 <6>[ 3.020159] hub 2-1:1.0: 3 ports detected
10633 16:31:56.748260 <6>[ 3.188959] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10634 16:31:56.880954 <6>[ 3.324856] hub 1-1.4:1.0: USB hub found
10635 16:31:56.884056 <6>[ 3.329537] hub 1-1.4:1.0: 2 ports detected
10636 16:31:56.899684 <6>[ 3.343777] hub 1-1.4:1.0: USB hub found
10637 16:31:56.902984 <6>[ 3.348405] hub 1-1.4:1.0: 2 ports detected
10638 16:31:56.960780 <6>[ 3.401181] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10639 16:31:57.069140 <6>[ 3.509644] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10640 16:31:57.104808 <4>[ 3.545328] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10641 16:31:57.114505 <4>[ 3.554429] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10642 16:31:57.158822 <6>[ 3.602535] r8152 2-1.3:1.0 eth0: v1.12.13
10643 16:31:57.199987 <6>[ 3.640722] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10644 16:31:57.392306 <6>[ 3.832868] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10645 16:31:58.767981 <6>[ 5.212212] r8152 2-1.3:1.0 eth0: carrier on
10646 16:31:58.804469 <5>[ 5.232747] Sending DHCP requests ., OK
10647 16:31:58.811403 <6>[ 5.253065] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10648 16:31:58.814701 <6>[ 5.261347] IP-Config: Complete:
10649 16:31:58.827972 <6>[ 5.264827] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10650 16:31:58.834529 <6>[ 5.275528] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10651 16:31:58.841089 <6>[ 5.284143] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10652 16:31:58.847720 <6>[ 5.284152] nameserver0=192.168.201.1
10653 16:31:58.850908 <6>[ 5.296277] clk: Disabling unused clocks
10654 16:31:58.854654 <6>[ 5.301655] ALSA device list:
10655 16:31:58.860948 <6>[ 5.304931] No soundcards found.
10656 16:31:58.868170 <6>[ 5.312382] Freeing unused kernel memory: 8512K
10657 16:31:58.871554 <6>[ 5.317391] Run /init as init process
10658 16:31:58.901029 Starting syslogd: OK
10659 16:31:58.905783 Starting klogd: OK
10660 16:31:58.915011 Running sysctl: OK
10661 16:31:58.924634 Populating /dev using udev: <30>[ 5.367650] udevd[195]: starting version 3.2.9
10662 16:31:58.931486 <27>[ 5.375682] udevd[195]: specified user 'tss' unknown
10663 16:31:58.938073 <27>[ 5.381058] udevd[195]: specified group 'tss' unknown
10664 16:31:58.941598 <30>[ 5.387511] udevd[196]: starting eudev-3.2.9
10665 16:31:59.103973 <6>[ 5.544974] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10666 16:31:59.118033 <6>[ 5.558839] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10667 16:31:59.124668 <6>[ 5.567556] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10668 16:31:59.134654 <3>[ 5.567625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 16:31:59.144815 <4>[ 5.576523] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10670 16:31:59.150962 <6>[ 5.578034] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10671 16:31:59.161384 <6>[ 5.578068] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10672 16:31:59.167829 <6>[ 5.578078] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10673 16:31:59.177813 <3>[ 5.583614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 16:31:59.184234 <3>[ 5.583628] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 16:31:59.191249 <3>[ 5.583782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 16:31:59.198127 <6>[ 5.592835] mc: Linux media interface: v0.10
10677 16:31:59.204657 <6>[ 5.593204] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10678 16:31:59.214435 <6>[ 5.593208] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10679 16:31:59.220766 <6>[ 5.593548] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10680 16:31:59.227882 <6>[ 5.593561] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10681 16:31:59.237581 <6>[ 5.593567] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10682 16:31:59.247253 <6>[ 5.593577] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10683 16:31:59.254343 <3>[ 5.600246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 16:31:59.260464 <3>[ 5.600255] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 16:31:59.270474 <6>[ 5.608687] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10686 16:31:59.277327 <6>[ 5.622204] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10687 16:31:59.283556 <3>[ 5.625715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 16:31:59.293652 <3>[ 5.625722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 16:31:59.300203 <3>[ 5.625792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 16:31:59.307010 <6>[ 5.626781] videodev: Linux video capture interface: v2.00
10691 16:31:59.316462 <4>[ 5.640113] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10692 16:31:59.320013 <4>[ 5.640113] Fallback method does not support PEC.
10693 16:31:59.330213 <3>[ 5.642407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 16:31:59.333443 <6>[ 5.650927] remoteproc remoteproc0: scp is available
10695 16:31:59.339838 <4>[ 5.651009] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10696 16:31:59.350150 <4>[ 5.651171] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10697 16:31:59.356542 <3>[ 5.654589] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 16:31:59.366482 <3>[ 5.654592] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 16:31:59.369535 <6>[ 5.662590] remoteproc remoteproc0: powering up scp
10700 16:31:59.379633 <3>[ 5.670482] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 16:31:59.386296 <6>[ 5.679031] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10702 16:31:59.396074 <3>[ 5.686102] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 16:31:59.402998 <3>[ 5.686107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 16:31:59.409380 <3>[ 5.686117] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 16:31:59.415730 <6>[ 5.695351] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10706 16:31:59.422708 <6>[ 5.698023] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10707 16:31:59.429169 <6>[ 5.698029] pci_bus 0000:00: root bus resource [bus 00-ff]
10708 16:31:59.435637 <6>[ 5.698035] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10709 16:31:59.445718 <6>[ 5.698037] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10710 16:31:59.452207 <6>[ 5.698090] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10711 16:31:59.458707 <6>[ 5.698107] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10712 16:31:59.465546 <6>[ 5.698185] pci 0000:00:00.0: supports D1 D2
10713 16:31:59.472355 <6>[ 5.698189] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10714 16:31:59.478507 <6>[ 5.699233] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10715 16:31:59.485421 <6>[ 5.699357] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10716 16:31:59.491962 <6>[ 5.699385] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10717 16:31:59.502076 <6>[ 5.699407] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10718 16:31:59.508526 <6>[ 5.699421] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10719 16:31:59.512032 <6>[ 5.699539] pci 0000:01:00.0: supports D1 D2
10720 16:31:59.518643 <6>[ 5.699541] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10721 16:31:59.528515 <3>[ 5.703332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 16:31:59.535178 <3>[ 5.703366] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 16:31:59.541575 <6>[ 5.708746] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10724 16:31:59.551537 <6>[ 5.708806] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10725 16:31:59.557931 <6>[ 5.708809] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10726 16:31:59.568052 <6>[ 5.708821] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10727 16:31:59.574503 <6>[ 5.708836] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10728 16:31:59.584407 <6>[ 5.708848] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10729 16:31:59.587409 <6>[ 5.708863] pci 0000:00:00.0: PCI bridge to [bus 01]
10730 16:31:59.597753 <6>[ 5.708869] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10731 16:31:59.601056 <6>[ 5.709072] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10732 16:31:59.607414 <6>[ 5.709873] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10733 16:31:59.614224 <6>[ 5.710212] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10734 16:31:59.624172 <6>[ 5.760987] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10735 16:31:59.633634 <6>[ 5.769260] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10736 16:31:59.643795 <6>[ 5.769504] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10737 16:31:59.650185 <6>[ 5.837416] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10738 16:31:59.657113 <6>[ 5.837459] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10739 16:31:59.663485 <6>[ 5.837467] remoteproc remoteproc0: remote processor scp is now up
10740 16:31:59.675205 <6>[ 6.119599] Bluetooth: Core ver 2.22
10741 16:31:59.678452 <6>[ 6.123926] NET: Registered PF_BLUETOOTH protocol family
10742 16:31:59.689012 <6>[ 6.125052] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10743 16:31:59.695595 <6>[ 6.129515] Bluetooth: HCI device and connection manager initialized
10744 16:31:59.698670 <6>[ 6.129529] Bluetooth: HCI socket layer initialized
10745 16:31:59.711551 <6>[ 6.138540] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10746 16:31:59.718350 <6>[ 6.143172] Bluetooth: L2CAP socket layer initialized
10747 16:31:59.721588 <6>[ 6.143181] Bluetooth: SCO socket layer initialized
10748 16:31:59.728190 <6>[ 6.162026] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10749 16:31:59.734698 <6>[ 6.166656] usbcore: registered new interface driver uvcvideo
10750 16:31:59.741617 <6>[ 6.178410] usbcore: registered new interface driver btusb
10751 16:31:59.751210 <4>[ 6.179042] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10752 16:31:59.758111 <3>[ 6.179052] Bluetooth: hci0: Failed to load firmware file (-2)
10753 16:31:59.761368 <3>[ 6.179055] Bluetooth: hci0: Failed to set up firmware (-2)
10754 16:31:59.774509 <4>[ 6.179059] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10755 16:31:59.781027 <5>[ 6.216163] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10756 16:31:59.791539 <6>[ 6.232367] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10757 16:31:59.801934 <6>[ 6.243052] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10758 16:31:59.823350 <5>[ 6.264016] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10759 16:31:59.829685 <5>[ 6.271270] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10760 16:31:59.839892 <4>[ 6.279731] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10761 16:31:59.843113 <6>[ 6.288636] cfg80211: failed to load regulatory.db
10762 16:31:59.886676 <6>[ 6.327531] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10763 16:31:59.893098 <6>[ 6.335029] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10764 16:31:59.917268 <6>[ 6.361709] mt7921e 0000:01:00.0: ASIC revision: 79610010
10765 16:32:00.019430 <6>[ 6.460095] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10766 16:32:00.022203 <6>[ 6.460095]
10767 16:32:00.111594 done
10768 16:32:00.122777 Saving random seed: OK
10769 16:32:00.133867 Starting network: ip: RTNETLINK answers: File exists
10770 16:32:00.137136 FAIL
10771 16:32:00.171151 Starting dropbear sshd: <6>[ 6.615546] NET: Registered PF_INET6 protocol family
10772 16:32:00.177824 <6>[ 6.622206] Segment Routing with IPv6
10773 16:32:00.181124 <6>[ 6.626171] In-situ OAM (IOAM) with IPv6
10774 16:32:00.184927 OK
10775 16:32:00.194115 /bin/sh: can't access tty; job control turned off
10776 16:32:00.194664 Matched prompt #10: / #
10778 16:32:00.194992 Setting prompt string to ['/ #']
10779 16:32:00.195121 end: 2.2.5.1 login-action (duration 00:00:07) [common]
10781 16:32:00.195440 end: 2.2.5 auto-login-action (duration 00:00:07) [common]
10782 16:32:00.195563 start: 2.2.6 expect-shell-connection (timeout 00:03:54) [common]
10783 16:32:00.195666 Setting prompt string to ['/ #']
10784 16:32:00.195758 Forcing a shell prompt, looking for ['/ #']
10786 16:32:00.246012 / #
10787 16:32:00.246193 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10788 16:32:00.246307 Waiting using forced prompt support (timeout 00:02:30)
10789 16:32:00.251097
10790 16:32:00.251418 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10791 16:32:00.251556 start: 2.2.7 export-device-env (timeout 00:03:54) [common]
10792 16:32:00.251696 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10793 16:32:00.251830 end: 2.2 depthcharge-retry (duration 00:01:06) [common]
10794 16:32:00.251977 end: 2 depthcharge-action (duration 00:01:06) [common]
10795 16:32:00.252105 start: 3 lava-test-retry (timeout 00:01:00) [common]
10796 16:32:00.252229 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10797 16:32:00.252341 Using namespace: common
10799 16:32:00.352701 / # #
10800 16:32:00.352852 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10801 16:32:00.352972 <6>[ 6.727844] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10802 16:32:00.358060 #
10803 16:32:00.358327 Using /lava-14396158
10805 16:32:00.458811 / # export SHELL=/bin/sh
10806 16:32:00.464190 export SHELL=/bin/sh
10808 16:32:00.564752 / # . /lava-14396158/environment
10809 16:32:00.570065 . /lava-14396158/environment
10811 16:32:00.670632 / # /lava-14396158/bin/lava-test-runner /lava-14396158/0
10812 16:32:00.670847 Test shell timeout: 10s (minimum of the action and connection timeout)
10813 16:32:00.676280 /lava-14396158/bin/lava-test-runner /lava-14396158/0
10814 16:32:00.697693 + export 'TESTRUN_ID=0_dmesg'
10815 16:32:00.703944 +<8>[ 7.146619] <LAVA_SIGNAL_STARTRUN 0_dmesg 14396158_1.5.2.3.1>
10816 16:32:00.704232 Received signal: <STARTRUN> 0_dmesg 14396158_1.5.2.3.1
10817 16:32:00.704338 Starting test lava.0_dmesg (14396158_1.5.2.3.1)
10818 16:32:00.704458 Skipping test definition patterns.
10819 16:32:00.707697 cd /lava-14396158/0/tests/0_dmesg
10820 16:32:00.707797 + cat uuid
10821 16:32:00.710976 + UUID=14396158_1.5.2.3.1
10822 16:32:00.711051 + set +x
10823 16:32:00.717546 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10824 16:32:00.724216 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10826 16:32:00.727199 <8>[ 7.166476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10827 16:32:00.747089 <8>[ 7.188031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10828 16:32:00.747371 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10830 16:32:00.768096 <8>[ 7.209348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10831 16:32:00.768385 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10833 16:32:00.771489 + set +x
10834 16:32:00.775045 <8>[ 7.218725] <LAVA_SIGNAL_ENDRUN 0_dmesg 14396158_1.5.2.3.1>
10835 16:32:00.775324 Received signal: <ENDRUN> 0_dmesg 14396158_1.5.2.3.1
10836 16:32:00.775436 Ending use of test pattern.
10837 16:32:00.775531 Ending test lava.0_dmesg (14396158_1.5.2.3.1), duration 0.07
10839 16:32:00.778579 <LAVA_TEST_RUNNER EXIT>
10840 16:32:00.778854 ok: lava_test_shell seems to have completed
10841 16:32:00.778968 alert: pass
crit: pass
emerg: pass
10842 16:32:00.779059 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10843 16:32:00.779143 end: 3 lava-test-retry (duration 00:00:01) [common]
10844 16:32:00.779237 start: 4 finalize (timeout 00:08:35) [common]
10845 16:32:00.779327 start: 4.1 power-off (timeout 00:00:30) [common]
10846 16:32:00.779484 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
10847 16:32:00.978024 >> Command sent successfully.
10848 16:32:00.980394 Returned 0 in 0 seconds
10849 16:32:01.080789 end: 4.1 power-off (duration 00:00:00) [common]
10851 16:32:01.081166 start: 4.2 read-feedback (timeout 00:08:35) [common]
10852 16:32:01.081440 Listened to connection for namespace 'common' for up to 1s
10853 16:32:02.081745 Finalising connection for namespace 'common'
10854 16:32:02.081952 Disconnecting from shell: Finalise
10855 16:32:02.082082 / #
10856 16:32:02.182402 end: 4.2 read-feedback (duration 00:00:01) [common]
10857 16:32:02.182552 end: 4 finalize (duration 00:00:01) [common]
10858 16:32:02.182668 Cleaning after the job
10859 16:32:02.182769 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/ramdisk
10860 16:32:02.185294 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/kernel
10861 16:32:02.192783 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/dtb
10862 16:32:02.192995 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396158/tftp-deploy-it13sxei/modules
10863 16:32:02.198750 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396158
10864 16:32:02.235297 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396158
10865 16:32:02.235492 Job finished correctly