Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 16:28:54.446684 lava-dispatcher, installed at version: 2024.03
2 16:28:54.446907 start: 0 validate
3 16:28:54.447025 Start time: 2024-06-17 16:28:54.447017+00:00 (UTC)
4 16:28:54.447186 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:28:54.447344 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 16:28:54.713011 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:28:54.713219 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:30:25.790777 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:30:25.791556 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:30:26.060441 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:30:26.060576 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:30:26.587268 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:30:26.587420 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-32-g0d904242fc145%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:30:26.852628 validate duration: 92.41
16 16:30:26.852904 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:30:26.853005 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:30:26.853151 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:30:26.853330 Not decompressing ramdisk as can be used compressed.
20 16:30:26.853418 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 16:30:26.853509 saving as /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/ramdisk/initrd.cpio.gz
22 16:30:26.853594 total size: 5628182 (5 MB)
23 16:30:27.110866 progress 0 % (0 MB)
24 16:30:27.112681 progress 5 % (0 MB)
25 16:30:27.114285 progress 10 % (0 MB)
26 16:30:27.115760 progress 15 % (0 MB)
27 16:30:27.117392 progress 20 % (1 MB)
28 16:30:27.118874 progress 25 % (1 MB)
29 16:30:27.120585 progress 30 % (1 MB)
30 16:30:27.122334 progress 35 % (1 MB)
31 16:30:27.123834 progress 40 % (2 MB)
32 16:30:27.125459 progress 45 % (2 MB)
33 16:30:27.126914 progress 50 % (2 MB)
34 16:30:27.128573 progress 55 % (2 MB)
35 16:30:27.130165 progress 60 % (3 MB)
36 16:30:27.131643 progress 65 % (3 MB)
37 16:30:27.133288 progress 70 % (3 MB)
38 16:30:27.134753 progress 75 % (4 MB)
39 16:30:27.136381 progress 80 % (4 MB)
40 16:30:27.137923 progress 85 % (4 MB)
41 16:30:27.139553 progress 90 % (4 MB)
42 16:30:27.141160 progress 95 % (5 MB)
43 16:30:27.142554 progress 100 % (5 MB)
44 16:30:27.142769 5 MB downloaded in 0.29 s (18.56 MB/s)
45 16:30:27.142925 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:30:27.143152 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:30:27.143239 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:30:27.143348 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:30:27.143511 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:30:27.143598 saving as /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/kernel/Image
52 16:30:27.143680 total size: 54813184 (52 MB)
53 16:30:27.143763 No compression specified
54 16:30:27.145172 progress 0 % (0 MB)
55 16:30:27.160036 progress 5 % (2 MB)
56 16:30:27.174627 progress 10 % (5 MB)
57 16:30:27.188982 progress 15 % (7 MB)
58 16:30:27.203213 progress 20 % (10 MB)
59 16:30:27.217710 progress 25 % (13 MB)
60 16:30:27.231890 progress 30 % (15 MB)
61 16:30:27.246146 progress 35 % (18 MB)
62 16:30:27.260622 progress 40 % (20 MB)
63 16:30:27.275396 progress 45 % (23 MB)
64 16:30:27.290416 progress 50 % (26 MB)
65 16:30:27.304583 progress 55 % (28 MB)
66 16:30:27.318285 progress 60 % (31 MB)
67 16:30:27.332201 progress 65 % (34 MB)
68 16:30:27.346192 progress 70 % (36 MB)
69 16:30:27.360157 progress 75 % (39 MB)
70 16:30:27.374048 progress 80 % (41 MB)
71 16:30:27.388017 progress 85 % (44 MB)
72 16:30:27.401990 progress 90 % (47 MB)
73 16:30:27.415737 progress 95 % (49 MB)
74 16:30:27.429614 progress 100 % (52 MB)
75 16:30:27.429866 52 MB downloaded in 0.29 s (182.66 MB/s)
76 16:30:27.430025 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:30:27.430239 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:30:27.430322 start: 1.3 download-retry (timeout 00:09:59) [common]
80 16:30:27.430400 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 16:30:27.430535 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 16:30:27.430601 saving as /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/dtb/mt8192-asurada-spherion-r0.dtb
83 16:30:27.430657 total size: 47258 (0 MB)
84 16:30:27.430712 No compression specified
85 16:30:27.431769 progress 69 % (0 MB)
86 16:30:27.432028 progress 100 % (0 MB)
87 16:30:27.432178 0 MB downloaded in 0.00 s (29.69 MB/s)
88 16:30:27.432293 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:30:27.432498 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:30:27.432578 start: 1.4 download-retry (timeout 00:09:59) [common]
92 16:30:27.432666 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 16:30:27.432776 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 16:30:27.432837 saving as /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/nfsrootfs/full.rootfs.tar
95 16:30:27.432892 total size: 107552908 (102 MB)
96 16:30:27.432947 Using unxz to decompress xz
97 16:30:27.434095 progress 0 % (0 MB)
98 16:30:27.725969 progress 5 % (5 MB)
99 16:30:28.058852 progress 10 % (10 MB)
100 16:30:28.389761 progress 15 % (15 MB)
101 16:30:28.716177 progress 20 % (20 MB)
102 16:30:28.998975 progress 25 % (25 MB)
103 16:30:29.298284 progress 30 % (30 MB)
104 16:30:29.612675 progress 35 % (35 MB)
105 16:30:29.794879 progress 40 % (41 MB)
106 16:30:30.002878 progress 45 % (46 MB)
107 16:30:30.325833 progress 50 % (51 MB)
108 16:30:30.636108 progress 55 % (56 MB)
109 16:30:30.970091 progress 60 % (61 MB)
110 16:30:31.302963 progress 65 % (66 MB)
111 16:30:31.617805 progress 70 % (71 MB)
112 16:30:31.943842 progress 75 % (76 MB)
113 16:30:32.257452 progress 80 % (82 MB)
114 16:30:32.583482 progress 85 % (87 MB)
115 16:30:32.879152 progress 90 % (92 MB)
116 16:30:33.185464 progress 95 % (97 MB)
117 16:30:33.508954 progress 100 % (102 MB)
118 16:30:33.514138 102 MB downloaded in 6.08 s (16.87 MB/s)
119 16:30:33.514347 end: 1.4.1 http-download (duration 00:00:06) [common]
121 16:30:33.514674 end: 1.4 download-retry (duration 00:00:06) [common]
122 16:30:33.514788 start: 1.5 download-retry (timeout 00:09:53) [common]
123 16:30:33.514896 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 16:30:33.515070 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-32-g0d904242fc145/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:30:33.515162 saving as /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/modules/modules.tar
126 16:30:33.515246 total size: 8628772 (8 MB)
127 16:30:33.515332 Using unxz to decompress xz
128 16:30:33.516917 progress 0 % (0 MB)
129 16:30:33.537770 progress 5 % (0 MB)
130 16:30:33.561746 progress 10 % (0 MB)
131 16:30:33.585276 progress 15 % (1 MB)
132 16:30:33.609385 progress 20 % (1 MB)
133 16:30:33.633727 progress 25 % (2 MB)
134 16:30:33.657628 progress 30 % (2 MB)
135 16:30:33.684569 progress 35 % (2 MB)
136 16:30:33.709781 progress 40 % (3 MB)
137 16:30:33.735042 progress 45 % (3 MB)
138 16:30:33.761442 progress 50 % (4 MB)
139 16:30:33.787129 progress 55 % (4 MB)
140 16:30:33.811667 progress 60 % (4 MB)
141 16:30:33.839568 progress 65 % (5 MB)
142 16:30:33.865088 progress 70 % (5 MB)
143 16:30:33.889329 progress 75 % (6 MB)
144 16:30:33.912662 progress 80 % (6 MB)
145 16:30:33.939948 progress 85 % (7 MB)
146 16:30:33.967751 progress 90 % (7 MB)
147 16:30:33.994022 progress 95 % (7 MB)
148 16:30:34.019468 progress 100 % (8 MB)
149 16:30:34.024461 8 MB downloaded in 0.51 s (16.16 MB/s)
150 16:30:34.024666 end: 1.5.1 http-download (duration 00:00:01) [common]
152 16:30:34.024884 end: 1.5 download-retry (duration 00:00:01) [common]
153 16:30:34.024966 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 16:30:34.025045 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 16:30:36.283160 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14396120/extract-nfsrootfs-7a_4oqnq
156 16:30:36.283333 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 16:30:36.283426 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 16:30:36.283932 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb
159 16:30:36.284057 makedir: /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin
160 16:30:36.284153 makedir: /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/tests
161 16:30:36.284244 makedir: /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/results
162 16:30:36.284328 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-add-keys
163 16:30:36.284455 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-add-sources
164 16:30:36.284574 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-background-process-start
165 16:30:36.284891 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-background-process-stop
166 16:30:36.286210 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-common-functions
167 16:30:36.286333 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-echo-ipv4
168 16:30:36.286449 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-install-packages
169 16:30:36.286576 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-installed-packages
170 16:30:36.286691 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-os-build
171 16:30:36.286815 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-probe-channel
172 16:30:36.286930 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-probe-ip
173 16:30:36.287070 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-target-ip
174 16:30:36.287199 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-target-mac
175 16:30:36.287314 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-target-storage
176 16:30:36.287458 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-test-case
177 16:30:36.287575 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-test-event
178 16:30:36.287692 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-test-feedback
179 16:30:36.287804 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-test-raise
180 16:30:36.287914 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-test-reference
181 16:30:36.288026 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-test-runner
182 16:30:36.288137 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-test-set
183 16:30:36.288248 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-test-shell
184 16:30:36.288361 Updating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-install-packages (oe)
185 16:30:36.288497 Updating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/bin/lava-installed-packages (oe)
186 16:30:36.288612 Creating /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/environment
187 16:30:36.288716 LAVA metadata
188 16:30:36.288781 - LAVA_JOB_ID=14396120
189 16:30:36.288837 - LAVA_DISPATCHER_IP=192.168.201.1
190 16:30:36.288936 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 16:30:36.288992 skipped lava-vland-overlay
192 16:30:36.289060 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 16:30:36.289134 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 16:30:36.289187 skipped lava-multinode-overlay
195 16:30:36.289252 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 16:30:36.289322 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 16:30:36.289385 Loading test definitions
198 16:30:36.289460 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 16:30:36.289518 Using /lava-14396120 at stage 0
200 16:30:36.289816 uuid=14396120_1.6.2.3.1 testdef=None
201 16:30:36.289898 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 16:30:36.289974 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 16:30:36.290427 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 16:30:36.290633 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 16:30:36.291221 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 16:30:36.291432 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 16:30:36.291998 runner path: /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/0/tests/0_dmesg test_uuid 14396120_1.6.2.3.1
210 16:30:36.292142 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 16:30:36.292353 Creating lava-test-runner.conf files
213 16:30:36.292433 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14396120/lava-overlay-l630k6cb/lava-14396120/0 for stage 0
214 16:30:36.292517 - 0_dmesg
215 16:30:36.292619 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 16:30:36.292717 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 16:30:36.298237 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 16:30:36.298347 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 16:30:36.298428 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 16:30:36.298508 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 16:30:36.298587 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 16:30:36.470391 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 16:30:36.470554 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
224 16:30:36.470643 extracting modules file /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396120/extract-nfsrootfs-7a_4oqnq
225 16:30:36.709362 extracting modules file /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14396120/extract-overlay-ramdisk-w3nhwmf6/ramdisk
226 16:30:36.966498 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 16:30:36.966646 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
228 16:30:36.966740 [common] Applying overlay to NFS
229 16:30:36.966833 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14396120/compress-overlay-3fa390s3/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14396120/extract-nfsrootfs-7a_4oqnq
230 16:30:36.975415 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 16:30:36.975576 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
232 16:30:36.975702 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 16:30:36.975820 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
234 16:30:36.975900 Building ramdisk /var/lib/lava/dispatcher/tmp/14396120/extract-overlay-ramdisk-w3nhwmf6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14396120/extract-overlay-ramdisk-w3nhwmf6/ramdisk
235 16:30:38.196873 >> 130466 blocks
236 16:30:40.420376 rename /var/lib/lava/dispatcher/tmp/14396120/extract-overlay-ramdisk-w3nhwmf6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/ramdisk/ramdisk.cpio.gz
237 16:30:40.420561 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
238 16:30:40.420702 start: 1.6.8 prepare-kernel (timeout 00:09:46) [common]
239 16:30:40.420800 start: 1.6.8.1 prepare-fit (timeout 00:09:46) [common]
240 16:30:40.420919 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/kernel/Image']
241 16:30:55.483018 Returned 0 in 15 seconds
242 16:30:55.583592 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/kernel/image.itb
243 16:30:57.626661 output: FIT description: Kernel Image image with one or more FDT blobs
244 16:30:57.626806 output: Created: Mon Jun 17 17:30:56 2024
245 16:30:57.626902 output: Image 0 (kernel-1)
246 16:30:57.626993 output: Description:
247 16:30:57.627082 output: Created: Mon Jun 17 17:30:56 2024
248 16:30:57.627167 output: Type: Kernel Image
249 16:30:57.627254 output: Compression: lzma compressed
250 16:30:57.627342 output: Data Size: 13128753 Bytes = 12821.05 KiB = 12.52 MiB
251 16:30:57.627434 output: Architecture: AArch64
252 16:30:57.627528 output: OS: Linux
253 16:30:57.627615 output: Load Address: 0x00000000
254 16:30:57.627706 output: Entry Point: 0x00000000
255 16:30:57.627790 output: Hash algo: crc32
256 16:30:57.627871 output: Hash value: 106ffd6f
257 16:30:57.627948 output: Image 1 (fdt-1)
258 16:30:57.628025 output: Description: mt8192-asurada-spherion-r0
259 16:30:57.628102 output: Created: Mon Jun 17 17:30:56 2024
260 16:30:57.628183 output: Type: Flat Device Tree
261 16:30:57.628263 output: Compression: uncompressed
262 16:30:57.628342 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 16:30:57.628423 output: Architecture: AArch64
264 16:30:57.628507 output: Hash algo: crc32
265 16:30:57.628583 output: Hash value: 0f8e4d2e
266 16:30:57.628685 output: Image 2 (ramdisk-1)
267 16:30:57.628764 output: Description: unavailable
268 16:30:57.628841 output: Created: Mon Jun 17 17:30:56 2024
269 16:30:57.628919 output: Type: RAMDisk Image
270 16:30:57.628996 output: Compression: uncompressed
271 16:30:57.629072 output: Data Size: 18744549 Bytes = 18305.22 KiB = 17.88 MiB
272 16:30:57.629149 output: Architecture: AArch64
273 16:30:57.629226 output: OS: Linux
274 16:30:57.629303 output: Load Address: unavailable
275 16:30:57.629379 output: Entry Point: unavailable
276 16:30:57.629460 output: Hash algo: crc32
277 16:30:57.629546 output: Hash value: 72199d96
278 16:30:57.629633 output: Default Configuration: 'conf-1'
279 16:30:57.629750 output: Configuration 0 (conf-1)
280 16:30:57.629857 output: Description: mt8192-asurada-spherion-r0
281 16:30:57.629947 output: Kernel: kernel-1
282 16:30:57.630038 output: Init Ramdisk: ramdisk-1
283 16:30:57.630114 output: FDT: fdt-1
284 16:30:57.630190 output: Loadables: kernel-1
285 16:30:57.630267 output:
286 16:30:57.630440 end: 1.6.8.1 prepare-fit (duration 00:00:17) [common]
287 16:30:57.630561 end: 1.6.8 prepare-kernel (duration 00:00:17) [common]
288 16:30:57.630684 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
289 16:30:57.630793 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:29) [common]
290 16:30:57.630890 No LXC device requested
291 16:30:57.630989 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 16:30:57.631096 start: 1.8 deploy-device-env (timeout 00:09:29) [common]
293 16:30:57.631194 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 16:30:57.631282 Checking files for TFTP limit of 4294967296 bytes.
295 16:30:57.631873 end: 1 tftp-deploy (duration 00:00:31) [common]
296 16:30:57.632002 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 16:30:57.632118 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 16:30:57.632272 substitutions:
299 16:30:57.632359 - {DTB}: 14396120/tftp-deploy-i999hvlk/dtb/mt8192-asurada-spherion-r0.dtb
300 16:30:57.632444 - {INITRD}: 14396120/tftp-deploy-i999hvlk/ramdisk/ramdisk.cpio.gz
301 16:30:57.632527 - {KERNEL}: 14396120/tftp-deploy-i999hvlk/kernel/Image
302 16:30:57.632607 - {LAVA_MAC}: None
303 16:30:57.632708 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14396120/extract-nfsrootfs-7a_4oqnq
304 16:30:57.632765 - {NFS_SERVER_IP}: 192.168.201.1
305 16:30:57.632815 - {PRESEED_CONFIG}: None
306 16:30:57.632878 - {PRESEED_LOCAL}: None
307 16:30:57.632929 - {RAMDISK}: 14396120/tftp-deploy-i999hvlk/ramdisk/ramdisk.cpio.gz
308 16:30:57.632979 - {ROOT_PART}: None
309 16:30:57.633027 - {ROOT}: None
310 16:30:57.633109 - {SERVER_IP}: 192.168.201.1
311 16:30:57.633156 - {TEE}: None
312 16:30:57.633204 Parsed boot commands:
313 16:30:57.633250 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 16:30:57.633443 Parsed boot commands: tftpboot 192.168.201.1 14396120/tftp-deploy-i999hvlk/kernel/image.itb 14396120/tftp-deploy-i999hvlk/kernel/cmdline
315 16:30:57.633543 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 16:30:57.633653 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 16:30:57.633764 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 16:30:57.633841 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 16:30:57.633902 Not connected, no need to disconnect.
320 16:30:57.633969 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 16:30:57.634043 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 16:30:57.634103 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
323 16:30:57.637593 Setting prompt string to ['lava-test: # ']
324 16:30:57.637983 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 16:30:57.638101 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 16:30:57.638223 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 16:30:57.638336 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 16:30:57.638529 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-8']
329 16:31:11.287796 Returned 0 in 13 seconds
330 16:31:11.388390 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
332 16:31:11.388780 end: 2.2.2 reset-device (duration 00:00:14) [common]
333 16:31:11.388880 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
334 16:31:11.388974 Setting prompt string to 'Starting depthcharge on Spherion...'
335 16:31:11.389042 Changing prompt to 'Starting depthcharge on Spherion...'
336 16:31:11.389110 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
337 16:31:11.389607 [Enter `^Ec?' for help]
338 16:31:11.389725
339 16:31:11.389824
340 16:31:11.389928 F0: 102B 0000
341 16:31:11.390020
342 16:31:11.390105 F3: 1001 0000 [0200]
343 16:31:11.390193
344 16:31:11.390282 F3: 1001 0000
345 16:31:11.390368
346 16:31:11.390454 F7: 102D 0000
347 16:31:11.390542
348 16:31:11.390624 F1: 0000 0000
349 16:31:11.390710
350 16:31:11.390791 V0: 0000 0000 [0001]
351 16:31:11.390870
352 16:31:11.390956 00: 0007 8000
353 16:31:11.391039
354 16:31:11.391116 01: 0000 0000
355 16:31:11.391198
356 16:31:11.391277 BP: 0C00 0209 [0000]
357 16:31:11.391354
358 16:31:11.391435 G0: 1182 0000
359 16:31:11.391516
360 16:31:11.391606 EC: 0000 0021 [4000]
361 16:31:11.391683
362 16:31:11.391748 S7: 0000 0000 [0000]
363 16:31:11.391808
364 16:31:11.391858 CC: 0000 0000 [0001]
365 16:31:11.391907
366 16:31:11.391966 T0: 0000 0040 [010F]
367 16:31:11.392044
368 16:31:11.392120 Jump to BL
369 16:31:11.392200
370 16:31:11.392277
371 16:31:11.392363
372 16:31:11.392452 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
373 16:31:11.392533 ARM64: Exception handlers installed.
374 16:31:11.392611 ARM64: Testing exception
375 16:31:11.392688 ARM64: Done test exception
376 16:31:11.392740 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
377 16:31:11.392791 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
378 16:31:11.392847 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
379 16:31:11.392902 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
380 16:31:11.392954 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
381 16:31:11.393004 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
382 16:31:11.393054 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
383 16:31:11.393105 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
384 16:31:11.393165 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
385 16:31:11.393245 WDT: Last reset was cold boot
386 16:31:11.393323 SPI1(PAD0) initialized at 2873684 Hz
387 16:31:11.393403 SPI5(PAD0) initialized at 992727 Hz
388 16:31:11.393482 VBOOT: Loading verstage.
389 16:31:11.393566 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
390 16:31:11.393654 FMAP: Found "FLASH" version 1.1 at 0x20000.
391 16:31:11.393744 FMAP: base = 0x0 size = 0x800000 #areas = 25
392 16:31:11.393828 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
393 16:31:11.393908 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
394 16:31:11.394000 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
395 16:31:11.394080 read SPI 0x96554 0xa1eb: 4596 us, 9018 KB/s, 72.144 Mbps
396 16:31:11.394165
397 16:31:11.394251
398 16:31:11.394331 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
399 16:31:11.394417 ARM64: Exception handlers installed.
400 16:31:11.394500 ARM64: Testing exception
401 16:31:11.394578 ARM64: Done test exception
402 16:31:11.394671 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
403 16:31:11.394752 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
404 16:31:11.394839 Probing TPM: . done!
405 16:31:11.394918 TPM ready after 0 ms
406 16:31:11.395000 Connected to device vid:did:rid of 1ae0:0028:00
407 16:31:11.395095 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
408 16:31:11.395175 Initialized TPM device CR50 revision 0
409 16:31:11.395264 tlcl_send_startup: Startup return code is 0
410 16:31:11.395348 TPM: setup succeeded
411 16:31:11.395427 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
412 16:31:11.395513 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
413 16:31:11.395602 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
414 16:31:11.395684 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 16:31:11.395741 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
416 16:31:11.395793 in-header: 03 07 00 00 08 00 00 00
417 16:31:11.395843 in-data: aa e4 47 04 13 02 00 00
418 16:31:11.395892 Chrome EC: UHEPI supported
419 16:31:11.395947 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
420 16:31:11.396027 in-header: 03 a9 00 00 08 00 00 00
421 16:31:11.396106 in-data: 84 60 60 08 00 00 00 00
422 16:31:11.396183 Phase 1
423 16:31:11.396265 FMAP: area GBB found @ 3f5000 (12032 bytes)
424 16:31:11.396355 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
425 16:31:11.396452 VB2:vb2_check_recovery() Recovery was requested manually
426 16:31:11.396537 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
427 16:31:11.396616 Recovery requested (1009000e)
428 16:31:11.396701 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 16:31:11.396773 tlcl_extend: response is 0
430 16:31:11.396826 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 16:31:11.396875 tlcl_extend: response is 0
432 16:31:11.396948 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 16:31:11.397029 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
434 16:31:11.397111 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 16:31:11.397190
436 16:31:11.397267
437 16:31:11.397347 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 16:31:11.397430 ARM64: Exception handlers installed.
439 16:31:11.397508 ARM64: Testing exception
440 16:31:11.397586 ARM64: Done test exception
441 16:31:11.397666 pmic_efuse_setting: Set efuses in 11 msecs
442 16:31:11.397745 pmwrap_interface_init: Select PMIF_VLD_RDY
443 16:31:11.397823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 16:31:11.397902 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 16:31:11.398186 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 16:31:11.398276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 16:31:11.398357 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 16:31:11.398435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 16:31:11.398517 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 16:31:11.398597 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 16:31:11.398675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 16:31:11.398756 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 16:31:11.398835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 16:31:11.398913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 16:31:11.398993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 16:31:11.399072 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 16:31:11.399151 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 16:31:11.399231 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 16:31:11.399312 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 16:31:11.399391 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 16:31:11.399469 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 16:31:11.399550 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 16:31:11.399630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 16:31:11.399709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 16:31:11.399790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 16:31:11.399869 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 16:31:11.399947 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 16:31:11.400029 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 16:31:11.400108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 16:31:11.400187 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 16:31:11.400268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 16:31:11.400347 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 16:31:11.400426 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 16:31:11.400507 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 16:31:11.400586 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 16:31:11.400673 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 16:31:11.400755 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 16:31:11.400833 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 16:31:11.400912 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 16:31:11.401006 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 16:31:11.401091 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 16:31:11.401170 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 16:31:11.401248 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 16:31:11.401301 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 16:31:11.401351 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 16:31:11.401401 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 16:31:11.401451 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 16:31:11.401505 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 16:31:11.401556 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 16:31:11.401605 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 16:31:11.401654 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 16:31:11.401702 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 16:31:11.401760 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 16:31:11.401840 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
495 16:31:11.401920 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 16:31:11.402002 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 16:31:11.402074 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 16:31:11.402127 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 16:31:11.402178 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 16:31:11.402228 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 16:31:11.402282 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 16:31:11.402332 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x1
503 16:31:11.402383 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 16:31:11.402433 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
505 16:31:11.402488 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 16:31:11.402539 [RTC]rtc_get_frequency_meter,154: input=15, output=793
507 16:31:11.402588 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
508 16:31:11.402638 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
509 16:31:11.402687 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
510 16:31:11.402744 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
511 16:31:11.402824 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
512 16:31:11.402902 ADC[4]: Raw value=893711 ID=7
513 16:31:11.402981 ADC[3]: Raw value=212700 ID=1
514 16:31:11.403061 RAM Code: 0x71
515 16:31:11.403139 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
516 16:31:11.403218 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
517 16:31:11.403501 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
518 16:31:11.403590 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
519 16:31:11.403677 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
520 16:31:11.403734 in-header: 03 07 00 00 08 00 00 00
521 16:31:11.403787 in-data: aa e4 47 04 13 02 00 00
522 16:31:11.403837 Chrome EC: UHEPI supported
523 16:31:11.403887 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
524 16:31:11.403937 in-header: 03 a9 00 00 08 00 00 00
525 16:31:11.403990 in-data: 84 60 60 08 00 00 00 00
526 16:31:11.404040 MRC: failed to locate region type 0.
527 16:31:11.404089 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
528 16:31:11.404140 DRAM-K: Running full calibration
529 16:31:11.404190 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
530 16:31:11.404273 header.status = 0x0
531 16:31:11.404353 header.version = 0x6 (expected: 0x6)
532 16:31:11.404432 header.size = 0xd00 (expected: 0xd00)
533 16:31:11.404512 header.flags = 0x0
534 16:31:11.404592 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
535 16:31:11.404679 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
536 16:31:11.404741 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
537 16:31:11.404816 dram_init: ddr_geometry: 2
538 16:31:11.404867 [EMI] MDL number = 2
539 16:31:11.404916 [EMI] Get MDL freq = 0
540 16:31:11.404965 dram_init: ddr_type: 0
541 16:31:11.405021 is_discrete_lpddr4: 1
542 16:31:11.405071 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
543 16:31:11.405120
544 16:31:11.405169
545 16:31:11.405217 [Bian_co] ETT version 0.0.0.1
546 16:31:11.405274 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
547 16:31:11.405333
548 16:31:11.405404 dramc_set_vcore_voltage set vcore to 650000
549 16:31:11.405455 Read voltage for 800, 4
550 16:31:11.405521 Vio18 = 0
551 16:31:11.405598 Vcore = 650000
552 16:31:11.405675 Vdram = 0
553 16:31:11.405755 Vddq = 0
554 16:31:11.405832 Vmddr = 0
555 16:31:11.405909 dram_init: config_dvfs: 1
556 16:31:11.405989 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
557 16:31:11.406084 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
558 16:31:11.406165 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
559 16:31:11.406246 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
560 16:31:11.406326 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
561 16:31:11.406404 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
562 16:31:11.406482 MEM_TYPE=3, freq_sel=18
563 16:31:11.406562 sv_algorithm_assistance_LP4_1600
564 16:31:11.406640 ============ PULL DRAM RESETB DOWN ============
565 16:31:11.406722 ========== PULL DRAM RESETB DOWN end =========
566 16:31:11.406803 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
567 16:31:11.406882 ===================================
568 16:31:11.406959 LPDDR4 DRAM CONFIGURATION
569 16:31:11.407052 ===================================
570 16:31:11.407132 EX_ROW_EN[0] = 0x0
571 16:31:11.407209 EX_ROW_EN[1] = 0x0
572 16:31:11.407290 LP4Y_EN = 0x0
573 16:31:11.407367 WORK_FSP = 0x0
574 16:31:11.407444 WL = 0x2
575 16:31:11.407524 RL = 0x2
576 16:31:11.407601 BL = 0x2
577 16:31:11.407678 RPST = 0x0
578 16:31:11.407742 RD_PRE = 0x0
579 16:31:11.407793 WR_PRE = 0x1
580 16:31:11.407843 WR_PST = 0x0
581 16:31:11.407891 DBI_WR = 0x0
582 16:31:11.407940 DBI_RD = 0x0
583 16:31:11.407996 OTF = 0x1
584 16:31:11.408088 ===================================
585 16:31:11.408167 ===================================
586 16:31:11.408247 ANA top config
587 16:31:11.408326 ===================================
588 16:31:11.408403 DLL_ASYNC_EN = 0
589 16:31:11.408482 ALL_SLAVE_EN = 1
590 16:31:11.408559 NEW_RANK_MODE = 1
591 16:31:11.408638 DLL_IDLE_MODE = 1
592 16:31:11.408707 LP45_APHY_COMB_EN = 1
593 16:31:11.408757 TX_ODT_DIS = 1
594 16:31:11.408806 NEW_8X_MODE = 1
595 16:31:11.408855 ===================================
596 16:31:11.408905 ===================================
597 16:31:11.408954 data_rate = 1600
598 16:31:11.409008 CKR = 1
599 16:31:11.409077 DQ_P2S_RATIO = 8
600 16:31:11.409127 ===================================
601 16:31:11.409178 CA_P2S_RATIO = 8
602 16:31:11.409241 DQ_CA_OPEN = 0
603 16:31:11.409304 DQ_SEMI_OPEN = 0
604 16:31:11.409355 CA_SEMI_OPEN = 0
605 16:31:11.409410 CA_FULL_RATE = 0
606 16:31:11.409460 DQ_CKDIV4_EN = 1
607 16:31:11.409509 CA_CKDIV4_EN = 1
608 16:31:11.409557 CA_PREDIV_EN = 0
609 16:31:11.409606 PH8_DLY = 0
610 16:31:11.409686 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
611 16:31:11.409764 DQ_AAMCK_DIV = 4
612 16:31:11.409859 CA_AAMCK_DIV = 4
613 16:31:11.409947 CA_ADMCK_DIV = 4
614 16:31:11.410025 DQ_TRACK_CA_EN = 0
615 16:31:11.410121 CA_PICK = 800
616 16:31:11.410202 CA_MCKIO = 800
617 16:31:11.410280 MCKIO_SEMI = 0
618 16:31:11.410359 PLL_FREQ = 3068
619 16:31:11.410440 DQ_UI_PI_RATIO = 32
620 16:31:11.410519 CA_UI_PI_RATIO = 0
621 16:31:11.410596 ===================================
622 16:31:11.410678 ===================================
623 16:31:11.410756 memory_type:LPDDR4
624 16:31:11.410834 GP_NUM : 10
625 16:31:11.410914 SRAM_EN : 1
626 16:31:11.410992 MD32_EN : 0
627 16:31:11.411070 ===================================
628 16:31:11.411150 [ANA_INIT] >>>>>>>>>>>>>>
629 16:31:11.411229 <<<<<< [CONFIGURE PHASE]: ANA_TX
630 16:31:11.411312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
631 16:31:11.411392 ===================================
632 16:31:11.411471 data_rate = 1600,PCW = 0X7600
633 16:31:11.411549 ===================================
634 16:31:11.411628 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
635 16:31:11.411709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
636 16:31:11.411788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
637 16:31:11.412088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
638 16:31:11.412176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
639 16:31:11.412255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
640 16:31:11.412334 [ANA_INIT] flow start
641 16:31:11.412416 [ANA_INIT] PLL >>>>>>>>
642 16:31:11.412493 [ANA_INIT] PLL <<<<<<<<
643 16:31:11.412571 [ANA_INIT] MIDPI >>>>>>>>
644 16:31:11.412667 [ANA_INIT] MIDPI <<<<<<<<
645 16:31:11.412745 [ANA_INIT] DLL >>>>>>>>
646 16:31:11.412797 [ANA_INIT] flow end
647 16:31:11.412847 ============ LP4 DIFF to SE enter ============
648 16:31:11.412904 ============ LP4 DIFF to SE exit ============
649 16:31:11.412954 [ANA_INIT] <<<<<<<<<<<<<
650 16:31:11.413003 [Flow] Enable top DCM control >>>>>
651 16:31:11.413052 [Flow] Enable top DCM control <<<<<
652 16:31:11.413129 Enable DLL master slave shuffle
653 16:31:11.413181 ==============================================================
654 16:31:11.413231 Gating Mode config
655 16:31:11.413280 ==============================================================
656 16:31:11.413342 Config description:
657 16:31:11.413407 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
658 16:31:11.413459 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
659 16:31:11.413509 SELPH_MODE 0: By rank 1: By Phase
660 16:31:11.413559 ==============================================================
661 16:31:11.413612 GAT_TRACK_EN = 1
662 16:31:11.413691 RX_GATING_MODE = 2
663 16:31:11.413775 RX_GATING_TRACK_MODE = 2
664 16:31:11.413858 SELPH_MODE = 1
665 16:31:11.413950 PICG_EARLY_EN = 1
666 16:31:11.414029 VALID_LAT_VALUE = 1
667 16:31:11.414110 ==============================================================
668 16:31:11.414201 Enter into Gating configuration >>>>
669 16:31:11.414281 Exit from Gating configuration <<<<
670 16:31:11.414360 Enter into DVFS_PRE_config >>>>>
671 16:31:11.414452 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
672 16:31:11.414536 Exit from DVFS_PRE_config <<<<<
673 16:31:11.414618 Enter into PICG configuration >>>>
674 16:31:11.414697 Exit from PICG configuration <<<<
675 16:31:11.414776 [RX_INPUT] configuration >>>>>
676 16:31:11.414853 [RX_INPUT] configuration <<<<<
677 16:31:11.414935 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
678 16:31:11.415014 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
679 16:31:11.415093 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
680 16:31:11.415175 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
681 16:31:11.415254 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
682 16:31:11.415333 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
683 16:31:11.415414 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
684 16:31:11.415493 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
685 16:31:11.415571 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
686 16:31:11.415652 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
687 16:31:11.415731 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
688 16:31:11.415809 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
689 16:31:11.415883 ===================================
690 16:31:11.415935 LPDDR4 DRAM CONFIGURATION
691 16:31:11.415985 ===================================
692 16:31:11.416035 EX_ROW_EN[0] = 0x0
693 16:31:11.416083 EX_ROW_EN[1] = 0x0
694 16:31:11.416171 LP4Y_EN = 0x0
695 16:31:11.416249 WORK_FSP = 0x0
696 16:31:11.416327 WL = 0x2
697 16:31:11.416412 RL = 0x2
698 16:31:11.416496 BL = 0x2
699 16:31:11.416573 RPST = 0x0
700 16:31:11.416661 RD_PRE = 0x0
701 16:31:11.416715 WR_PRE = 0x1
702 16:31:11.416765 WR_PST = 0x0
703 16:31:11.416813 DBI_WR = 0x0
704 16:31:11.416866 DBI_RD = 0x0
705 16:31:11.416944 OTF = 0x1
706 16:31:11.417022 ===================================
707 16:31:11.417100 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
708 16:31:11.417192 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
709 16:31:11.417285 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
710 16:31:11.417368 ===================================
711 16:31:11.417447 LPDDR4 DRAM CONFIGURATION
712 16:31:11.417529 ===================================
713 16:31:11.417615 EX_ROW_EN[0] = 0x10
714 16:31:11.417694 EX_ROW_EN[1] = 0x0
715 16:31:11.417771 LP4Y_EN = 0x0
716 16:31:11.417848 WORK_FSP = 0x0
717 16:31:11.417920 WL = 0x2
718 16:31:11.417975 RL = 0x2
719 16:31:11.418063 BL = 0x2
720 16:31:11.418151 RPST = 0x0
721 16:31:11.418237 RD_PRE = 0x0
722 16:31:11.418317 WR_PRE = 0x1
723 16:31:11.418401 WR_PST = 0x0
724 16:31:11.418482 DBI_WR = 0x0
725 16:31:11.418560 DBI_RD = 0x0
726 16:31:11.418641 OTF = 0x1
727 16:31:11.418727 ===================================
728 16:31:11.418812 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
729 16:31:11.418901 nWR fixed to 40
730 16:31:11.418980 [ModeRegInit_LP4] CH0 RK0
731 16:31:11.419058 [ModeRegInit_LP4] CH0 RK1
732 16:31:11.419140 [ModeRegInit_LP4] CH1 RK0
733 16:31:11.419226 [ModeRegInit_LP4] CH1 RK1
734 16:31:11.419304 match AC timing 13
735 16:31:11.419384 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
736 16:31:11.419471 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
737 16:31:11.419550 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
738 16:31:11.419632 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
739 16:31:11.419711 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
740 16:31:11.419788 [EMI DOE] emi_dcm 0
741 16:31:11.419870 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
742 16:31:11.419933 ==
743 16:31:11.419984 Dram Type= 6, Freq= 0, CH_0, rank 0
744 16:31:11.420064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
745 16:31:11.420154 ==
746 16:31:11.420448 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
747 16:31:11.420546 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
748 16:31:11.420629 [CA 0] Center 38 (7~69) winsize 63
749 16:31:11.420721 [CA 1] Center 37 (7~68) winsize 62
750 16:31:11.420810 [CA 2] Center 35 (5~66) winsize 62
751 16:31:11.420892 [CA 3] Center 35 (5~66) winsize 62
752 16:31:11.420971 [CA 4] Center 34 (4~65) winsize 62
753 16:31:11.421045 [CA 5] Center 34 (3~65) winsize 63
754 16:31:11.421097
755 16:31:11.421157 [CmdBusTrainingLP45] Vref(ca) range 1: 32
756 16:31:11.421224
757 16:31:11.421281 [CATrainingPosCal] consider 1 rank data
758 16:31:11.421343 u2DelayCellTimex100 = 270/100 ps
759 16:31:11.421418 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
760 16:31:11.421503 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
761 16:31:11.421587 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
762 16:31:11.421680 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
763 16:31:11.421764 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
764 16:31:11.421848 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
765 16:31:11.421934
766 16:31:11.422026 CA PerBit enable=1, Macro0, CA PI delay=34
767 16:31:11.422108
768 16:31:11.422187 [CBTSetCACLKResult] CA Dly = 34
769 16:31:11.422265 CS Dly: 6 (0~37)
770 16:31:11.422342 ==
771 16:31:11.422423 Dram Type= 6, Freq= 0, CH_0, rank 1
772 16:31:11.422501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 16:31:11.422579 ==
774 16:31:11.422661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
775 16:31:11.422740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
776 16:31:11.422818 [CA 0] Center 38 (7~69) winsize 63
777 16:31:11.422899 [CA 1] Center 38 (7~69) winsize 63
778 16:31:11.422976 [CA 2] Center 35 (5~66) winsize 62
779 16:31:11.423053 [CA 3] Center 35 (5~66) winsize 62
780 16:31:11.423133 [CA 4] Center 34 (4~65) winsize 62
781 16:31:11.423211 [CA 5] Center 34 (4~65) winsize 62
782 16:31:11.423291
783 16:31:11.423378 [CmdBusTrainingLP45] Vref(ca) range 1: 32
784 16:31:11.423464
785 16:31:11.423547 [CATrainingPosCal] consider 2 rank data
786 16:31:11.423633 u2DelayCellTimex100 = 270/100 ps
787 16:31:11.423719 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
788 16:31:11.423804 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
789 16:31:11.423893 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
790 16:31:11.423976 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
791 16:31:11.424067 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
792 16:31:11.424150 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
793 16:31:11.424227
794 16:31:11.424306 CA PerBit enable=1, Macro0, CA PI delay=34
795 16:31:11.424385
796 16:31:11.424463 [CBTSetCACLKResult] CA Dly = 34
797 16:31:11.424541 CS Dly: 6 (0~37)
798 16:31:11.424620
799 16:31:11.424713 ----->DramcWriteLeveling(PI) begin...
800 16:31:11.424795 ==
801 16:31:11.424875 Dram Type= 6, Freq= 0, CH_0, rank 0
802 16:31:11.424955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
803 16:31:11.425032 ==
804 16:31:11.425111 Write leveling (Byte 0): 31 => 31
805 16:31:11.425192 Write leveling (Byte 1): 30 => 30
806 16:31:11.425269 DramcWriteLeveling(PI) end<-----
807 16:31:11.425345
808 16:31:11.425425 ==
809 16:31:11.425504 Dram Type= 6, Freq= 0, CH_0, rank 0
810 16:31:11.425584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 16:31:11.425673 ==
812 16:31:11.425752 [Gating] SW mode calibration
813 16:31:11.425845 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
814 16:31:11.425932 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
815 16:31:11.426014 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
816 16:31:11.426109 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
817 16:31:11.426190 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
818 16:31:11.426274 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
819 16:31:11.426359 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 16:31:11.426438 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 16:31:11.426522 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 16:31:11.426607 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 16:31:11.426699 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 16:31:11.426797 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 16:31:11.426880 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 16:31:11.426960 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 16:31:11.427041 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 16:31:11.427131 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 16:31:11.427215 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 16:31:11.427310 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 16:31:11.427393 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 16:31:11.427471 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
833 16:31:11.427554 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
834 16:31:11.427633 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 16:31:11.427711 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 16:31:11.427784 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 16:31:11.427835 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 16:31:11.427886 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 16:31:11.427936 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 16:31:11.427985 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 16:31:11.428066 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 16:31:11.428145 0 9 12 | B1->B0 | 2c2c 2f2f | 0 1 | (0 0) (1 1)
843 16:31:11.428223 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
844 16:31:11.428305 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
845 16:31:11.428383 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
846 16:31:11.428463 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
847 16:31:11.428560 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
848 16:31:11.428640 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 16:31:11.428707 0 10 8 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
850 16:31:11.428769 0 10 12 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
851 16:31:11.428852 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 16:31:11.429147 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 16:31:11.429253 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 16:31:11.429353 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 16:31:11.429451 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 16:31:11.429550 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 16:31:11.429646 0 11 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
858 16:31:11.429733 0 11 12 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
859 16:31:11.429836 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 16:31:11.429938 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
861 16:31:11.430033 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 16:31:11.430114 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 16:31:11.430193 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 16:31:11.430282 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 16:31:11.430378 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
866 16:31:11.430459 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
867 16:31:11.430550 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 16:31:11.430629 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 16:31:11.430705 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 16:31:11.430798 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 16:31:11.430878 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 16:31:11.430957 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 16:31:11.431045 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 16:31:11.431124 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 16:31:11.431202 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 16:31:11.431279 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 16:31:11.431332 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 16:31:11.431382 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 16:31:11.431432 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 16:31:11.431485 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
881 16:31:11.431573 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
882 16:31:11.431652 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
883 16:31:11.431732 Total UI for P1: 0, mck2ui 16
884 16:31:11.431797 best dqsien dly found for B0: ( 0, 14, 6)
885 16:31:11.431862 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 16:31:11.431914 Total UI for P1: 0, mck2ui 16
887 16:31:11.431965 best dqsien dly found for B1: ( 0, 14, 12)
888 16:31:11.432044 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
889 16:31:11.432124 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
890 16:31:11.432201
891 16:31:11.432289 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
892 16:31:11.432369 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
893 16:31:11.432447 [Gating] SW calibration Done
894 16:31:11.432536 ==
895 16:31:11.432627 Dram Type= 6, Freq= 0, CH_0, rank 0
896 16:31:11.432718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
897 16:31:11.432792 ==
898 16:31:11.432870 RX Vref Scan: 0
899 16:31:11.432933
900 16:31:11.433024 RX Vref 0 -> 0, step: 1
901 16:31:11.433115
902 16:31:11.433197 RX Delay -130 -> 252, step: 16
903 16:31:11.433279 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
904 16:31:11.433359 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
905 16:31:11.433437 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
906 16:31:11.433519 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
907 16:31:11.433597 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
908 16:31:11.433676 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
909 16:31:11.433750 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
910 16:31:11.433802 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
911 16:31:11.433853 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
912 16:31:11.433902 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
913 16:31:11.433952 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
914 16:31:11.434022 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
915 16:31:11.434113 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
916 16:31:11.434197 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
917 16:31:11.434282 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
918 16:31:11.434359 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
919 16:31:11.434436 ==
920 16:31:11.434520 Dram Type= 6, Freq= 0, CH_0, rank 0
921 16:31:11.434599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
922 16:31:11.434677 ==
923 16:31:11.434758 DQS Delay:
924 16:31:11.434844 DQS0 = 0, DQS1 = 0
925 16:31:11.434935 DQM Delay:
926 16:31:11.435035 DQM0 = 81, DQM1 = 70
927 16:31:11.435139 DQ Delay:
928 16:31:11.435245 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
929 16:31:11.435336 DQ4 =85, DQ5 =61, DQ6 =93, DQ7 =93
930 16:31:11.435436 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
931 16:31:11.435535 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
932 16:31:11.435629
933 16:31:11.435724
934 16:31:11.435821 ==
935 16:31:11.435918 Dram Type= 6, Freq= 0, CH_0, rank 0
936 16:31:11.436015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 16:31:11.436114 ==
938 16:31:11.436212
939 16:31:11.436309
940 16:31:11.436409 TX Vref Scan disable
941 16:31:11.436503 == TX Byte 0 ==
942 16:31:11.436599 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
943 16:31:11.436709 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
944 16:31:11.436804 == TX Byte 1 ==
945 16:31:11.436896 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 16:31:11.436994 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 16:31:11.437092 ==
948 16:31:11.437190 Dram Type= 6, Freq= 0, CH_0, rank 0
949 16:31:11.437291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 16:31:11.437389 ==
951 16:31:11.437482 TX Vref=22, minBit 11, minWin=26, winSum=435
952 16:31:11.437576 TX Vref=24, minBit 7, minWin=27, winSum=440
953 16:31:11.437671 TX Vref=26, minBit 11, minWin=27, winSum=443
954 16:31:11.437770 TX Vref=28, minBit 11, minWin=27, winSum=444
955 16:31:11.437873 TX Vref=30, minBit 9, minWin=27, winSum=443
956 16:31:11.437972 TX Vref=32, minBit 10, minWin=26, winSum=440
957 16:31:11.438073 [TxChooseVref] Worse bit 11, Min win 27, Win sum 444, Final Vref 28
958 16:31:11.438168
959 16:31:11.438265 Final TX Range 1 Vref 28
960 16:31:11.438361
961 16:31:11.438455 ==
962 16:31:11.438552 Dram Type= 6, Freq= 0, CH_0, rank 0
963 16:31:11.438885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 16:31:11.438998 ==
965 16:31:11.439098
966 16:31:11.439204
967 16:31:11.439307 TX Vref Scan disable
968 16:31:11.439403 == TX Byte 0 ==
969 16:31:11.439498 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
970 16:31:11.439591 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
971 16:31:11.439699 == TX Byte 1 ==
972 16:31:11.439801 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
973 16:31:11.439905 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
974 16:31:11.440001
975 16:31:11.440100 [DATLAT]
976 16:31:11.440205 Freq=800, CH0 RK0
977 16:31:11.440302
978 16:31:11.440400 DATLAT Default: 0xa
979 16:31:11.440502 0, 0xFFFF, sum = 0
980 16:31:11.440608 1, 0xFFFF, sum = 0
981 16:31:11.440722 2, 0xFFFF, sum = 0
982 16:31:11.440820 3, 0xFFFF, sum = 0
983 16:31:11.440925 4, 0xFFFF, sum = 0
984 16:31:11.441030 5, 0xFFFF, sum = 0
985 16:31:11.441126 6, 0xFFFF, sum = 0
986 16:31:11.441223 7, 0xFFFF, sum = 0
987 16:31:11.441318 8, 0xFFFF, sum = 0
988 16:31:11.441417 9, 0x0, sum = 1
989 16:31:11.441521 10, 0x0, sum = 2
990 16:31:11.441629 11, 0x0, sum = 3
991 16:31:11.441727 12, 0x0, sum = 4
992 16:31:11.441834 best_step = 10
993 16:31:11.441932
994 16:31:11.442027 ==
995 16:31:11.442132 Dram Type= 6, Freq= 0, CH_0, rank 0
996 16:31:11.442242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 16:31:11.442337 ==
998 16:31:11.442430 RX Vref Scan: 1
999 16:31:11.442534
1000 16:31:11.442631 Set Vref Range= 32 -> 127
1001 16:31:11.442723
1002 16:31:11.442815 RX Vref 32 -> 127, step: 1
1003 16:31:11.442909
1004 16:31:11.443007 RX Delay -111 -> 252, step: 8
1005 16:31:11.443099
1006 16:31:11.443193 Set Vref, RX VrefLevel [Byte0]: 32
1007 16:31:11.443290 [Byte1]: 32
1008 16:31:11.443383
1009 16:31:11.443477 Set Vref, RX VrefLevel [Byte0]: 33
1010 16:31:11.443570 [Byte1]: 33
1011 16:31:11.443664
1012 16:31:11.443767 Set Vref, RX VrefLevel [Byte0]: 34
1013 16:31:11.443864 [Byte1]: 34
1014 16:31:11.443967
1015 16:31:11.444060 Set Vref, RX VrefLevel [Byte0]: 35
1016 16:31:11.444151 [Byte1]: 35
1017 16:31:11.444246
1018 16:31:11.444348 Set Vref, RX VrefLevel [Byte0]: 36
1019 16:31:11.444444 [Byte1]: 36
1020 16:31:11.444541
1021 16:31:11.444662 Set Vref, RX VrefLevel [Byte0]: 37
1022 16:31:11.444765 [Byte1]: 37
1023 16:31:11.444851
1024 16:31:11.444952 Set Vref, RX VrefLevel [Byte0]: 38
1025 16:31:11.445053 [Byte1]: 38
1026 16:31:11.445156
1027 16:31:11.445255 Set Vref, RX VrefLevel [Byte0]: 39
1028 16:31:11.445365 [Byte1]: 39
1029 16:31:11.445468
1030 16:31:11.445567 Set Vref, RX VrefLevel [Byte0]: 40
1031 16:31:11.445669 [Byte1]: 40
1032 16:31:11.445769
1033 16:31:11.445861 Set Vref, RX VrefLevel [Byte0]: 41
1034 16:31:11.445958 [Byte1]: 41
1035 16:31:11.446055
1036 16:31:11.446154 Set Vref, RX VrefLevel [Byte0]: 42
1037 16:31:11.446253 [Byte1]: 42
1038 16:31:11.446349
1039 16:31:11.446445 Set Vref, RX VrefLevel [Byte0]: 43
1040 16:31:11.446543 [Byte1]: 43
1041 16:31:11.446637
1042 16:31:11.446735 Set Vref, RX VrefLevel [Byte0]: 44
1043 16:31:11.446829 [Byte1]: 44
1044 16:31:11.446918
1045 16:31:11.447012 Set Vref, RX VrefLevel [Byte0]: 45
1046 16:31:11.447105 [Byte1]: 45
1047 16:31:11.447200
1048 16:31:11.447310 Set Vref, RX VrefLevel [Byte0]: 46
1049 16:31:11.447415 [Byte1]: 46
1050 16:31:11.447509
1051 16:31:11.447599 Set Vref, RX VrefLevel [Byte0]: 47
1052 16:31:11.447693 [Byte1]: 47
1053 16:31:11.447797
1054 16:31:11.447900 Set Vref, RX VrefLevel [Byte0]: 48
1055 16:31:11.447997 [Byte1]: 48
1056 16:31:11.448090
1057 16:31:11.448188 Set Vref, RX VrefLevel [Byte0]: 49
1058 16:31:11.448291 [Byte1]: 49
1059 16:31:11.448384
1060 16:31:11.448482 Set Vref, RX VrefLevel [Byte0]: 50
1061 16:31:11.448580 [Byte1]: 50
1062 16:31:11.448689
1063 16:31:11.448789 Set Vref, RX VrefLevel [Byte0]: 51
1064 16:31:11.448891 [Byte1]: 51
1065 16:31:11.448986
1066 16:31:11.449078 Set Vref, RX VrefLevel [Byte0]: 52
1067 16:31:11.449176 [Byte1]: 52
1068 16:31:11.449281
1069 16:31:11.449374 Set Vref, RX VrefLevel [Byte0]: 53
1070 16:31:11.449465 [Byte1]: 53
1071 16:31:11.449559
1072 16:31:11.449651 Set Vref, RX VrefLevel [Byte0]: 54
1073 16:31:11.449743 [Byte1]: 54
1074 16:31:11.449829
1075 16:31:11.449912 Set Vref, RX VrefLevel [Byte0]: 55
1076 16:31:11.450002 [Byte1]: 55
1077 16:31:11.450094
1078 16:31:11.450187 Set Vref, RX VrefLevel [Byte0]: 56
1079 16:31:11.450281 [Byte1]: 56
1080 16:31:11.450380
1081 16:31:11.450475 Set Vref, RX VrefLevel [Byte0]: 57
1082 16:31:11.450570 [Byte1]: 57
1083 16:31:11.450664
1084 16:31:11.450755 Set Vref, RX VrefLevel [Byte0]: 58
1085 16:31:11.450848 [Byte1]: 58
1086 16:31:11.450952
1087 16:31:11.451050 Set Vref, RX VrefLevel [Byte0]: 59
1088 16:31:11.451147 [Byte1]: 59
1089 16:31:11.451243
1090 16:31:11.451341 Set Vref, RX VrefLevel [Byte0]: 60
1091 16:31:11.451446 [Byte1]: 60
1092 16:31:11.451546
1093 16:31:11.451651 Set Vref, RX VrefLevel [Byte0]: 61
1094 16:31:11.451747 [Byte1]: 61
1095 16:31:11.451840
1096 16:31:11.451937 Set Vref, RX VrefLevel [Byte0]: 62
1097 16:31:11.452034 [Byte1]: 62
1098 16:31:11.452128
1099 16:31:11.452220 Set Vref, RX VrefLevel [Byte0]: 63
1100 16:31:11.452314 [Byte1]: 63
1101 16:31:11.452408
1102 16:31:11.452503 Set Vref, RX VrefLevel [Byte0]: 64
1103 16:31:11.452594 [Byte1]: 64
1104 16:31:11.452695
1105 16:31:11.452786 Set Vref, RX VrefLevel [Byte0]: 65
1106 16:31:11.452877 [Byte1]: 65
1107 16:31:11.452968
1108 16:31:11.453060 Set Vref, RX VrefLevel [Byte0]: 66
1109 16:31:11.453153 [Byte1]: 66
1110 16:31:11.453251
1111 16:31:11.453356 Set Vref, RX VrefLevel [Byte0]: 67
1112 16:31:11.453454 [Byte1]: 67
1113 16:31:11.453549
1114 16:31:11.453647 Set Vref, RX VrefLevel [Byte0]: 68
1115 16:31:11.453745 [Byte1]: 68
1116 16:31:11.453838
1117 16:31:11.453933 Set Vref, RX VrefLevel [Byte0]: 69
1118 16:31:11.454029 [Byte1]: 69
1119 16:31:11.454127
1120 16:31:11.454233 Set Vref, RX VrefLevel [Byte0]: 70
1121 16:31:11.454329 [Byte1]: 70
1122 16:31:11.454427
1123 16:31:11.454531 Set Vref, RX VrefLevel [Byte0]: 71
1124 16:31:11.454628 [Byte1]: 71
1125 16:31:11.454722
1126 16:31:11.454814 Set Vref, RX VrefLevel [Byte0]: 72
1127 16:31:11.454906 [Byte1]: 72
1128 16:31:11.455001
1129 16:31:11.455098 Set Vref, RX VrefLevel [Byte0]: 73
1130 16:31:11.455196 [Byte1]: 73
1131 16:31:11.455293
1132 16:31:11.455405 Set Vref, RX VrefLevel [Byte0]: 74
1133 16:31:11.455510 [Byte1]: 74
1134 16:31:11.455621
1135 16:31:11.455954 Set Vref, RX VrefLevel [Byte0]: 75
1136 16:31:11.456060 [Byte1]: 75
1137 16:31:11.456161
1138 16:31:11.456256 Set Vref, RX VrefLevel [Byte0]: 76
1139 16:31:11.456352 [Byte1]: 76
1140 16:31:11.456457
1141 16:31:11.456563 Set Vref, RX VrefLevel [Byte0]: 77
1142 16:31:11.456685 [Byte1]: 77
1143 16:31:11.456790
1144 16:31:11.456892 Set Vref, RX VrefLevel [Byte0]: 78
1145 16:31:11.456999 [Byte1]: 78
1146 16:31:11.457099
1147 16:31:11.457202 Set Vref, RX VrefLevel [Byte0]: 79
1148 16:31:11.457301 [Byte1]: 79
1149 16:31:11.457397
1150 16:31:11.457503 Final RX Vref Byte 0 = 56 to rank0
1151 16:31:11.457606 Final RX Vref Byte 1 = 56 to rank0
1152 16:31:11.457703 Final RX Vref Byte 0 = 56 to rank1
1153 16:31:11.457805 Final RX Vref Byte 1 = 56 to rank1==
1154 16:31:11.457900 Dram Type= 6, Freq= 0, CH_0, rank 0
1155 16:31:11.457995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1156 16:31:11.458089 ==
1157 16:31:11.458182 DQS Delay:
1158 16:31:11.458277 DQS0 = 0, DQS1 = 0
1159 16:31:11.458370 DQM Delay:
1160 16:31:11.458465 DQM0 = 82, DQM1 = 67
1161 16:31:11.458555 DQ Delay:
1162 16:31:11.458647 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1163 16:31:11.458743 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1164 16:31:11.458842 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1165 16:31:11.458937 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1166 16:31:11.459038
1167 16:31:11.459135
1168 16:31:11.459240 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f2e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1169 16:31:11.459330 CH0 RK0: MR19=606, MR18=2F2E
1170 16:31:11.459423 CH0_RK0: MR19=0x606, MR18=0x2F2E, DQSOSC=397, MR23=63, INC=93, DEC=62
1171 16:31:11.459514
1172 16:31:11.459606 ----->DramcWriteLeveling(PI) begin...
1173 16:31:11.459701 ==
1174 16:31:11.459792 Dram Type= 6, Freq= 0, CH_0, rank 1
1175 16:31:11.459886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 16:31:11.459981 ==
1177 16:31:11.460076 Write leveling (Byte 0): 34 => 34
1178 16:31:11.460173 Write leveling (Byte 1): 31 => 31
1179 16:31:11.460275 DramcWriteLeveling(PI) end<-----
1180 16:31:11.460371
1181 16:31:11.460464 ==
1182 16:31:11.460556 Dram Type= 6, Freq= 0, CH_0, rank 1
1183 16:31:11.460661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 16:31:11.460755 ==
1185 16:31:11.460866 [Gating] SW mode calibration
1186 16:31:11.460967 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1187 16:31:11.461072 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1188 16:31:11.461172 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1189 16:31:11.461284 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 16:31:11.461397 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1191 16:31:11.461505 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 16:31:11.461597 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 16:31:11.461694 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 16:31:11.461777 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 16:31:11.461858 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 16:31:11.461938 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 16:31:11.462017 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 16:31:11.462097 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 16:31:11.462177 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 16:31:11.462259 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 16:31:11.462362 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 16:31:11.462445 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 16:31:11.462527 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 16:31:11.462606 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 16:31:11.462687 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1206 16:31:11.462767 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1207 16:31:11.462846 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1208 16:31:11.462925 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 16:31:11.463003 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 16:31:11.463084 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 16:31:11.463163 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 16:31:11.463241 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 16:31:11.463322 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 16:31:11.463401 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1215 16:31:11.463480 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1216 16:31:11.463560 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 16:31:11.463639 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 16:31:11.463718 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 16:31:11.463796 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 16:31:11.463848 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 16:31:11.463898 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1222 16:31:11.463948 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
1223 16:31:11.463997 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 16:31:11.464063 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 16:31:11.464142 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 16:31:11.464220 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 16:31:11.464301 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 16:31:11.464380 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 16:31:11.464459 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1230 16:31:11.464540 0 11 8 | B1->B0 | 3232 3b3b | 0 0 | (0 0) (0 0)
1231 16:31:11.464618 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
1232 16:31:11.464703 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 16:31:11.464759 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 16:31:11.464809 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 16:31:11.464859 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 16:31:11.464908 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 16:31:11.464958 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1238 16:31:11.465224 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1239 16:31:11.465289 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1240 16:31:11.465340 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 16:31:11.465390 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 16:31:11.465441 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 16:31:11.465493 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 16:31:11.465544 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 16:31:11.465593 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 16:31:11.465642 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 16:31:11.465691 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 16:31:11.465745 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 16:31:11.465825 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 16:31:11.465902 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 16:31:11.465983 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 16:31:11.466061 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1253 16:31:11.466140 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 16:31:11.466217 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1255 16:31:11.466297 Total UI for P1: 0, mck2ui 16
1256 16:31:11.466377 best dqsien dly found for B0: ( 0, 14, 6)
1257 16:31:11.466456 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 16:31:11.466537 Total UI for P1: 0, mck2ui 16
1259 16:31:11.466616 best dqsien dly found for B1: ( 0, 14, 8)
1260 16:31:11.466694 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1261 16:31:11.466776 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1262 16:31:11.466853
1263 16:31:11.466931 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1264 16:31:11.467013 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1265 16:31:11.467091 [Gating] SW calibration Done
1266 16:31:11.467168 ==
1267 16:31:11.467248 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 16:31:11.467327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 16:31:11.467404 ==
1270 16:31:11.467485 RX Vref Scan: 0
1271 16:31:11.467563
1272 16:31:11.467640 RX Vref 0 -> 0, step: 1
1273 16:31:11.467716
1274 16:31:11.467797 RX Delay -130 -> 252, step: 16
1275 16:31:11.467875 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1276 16:31:11.467953 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1277 16:31:11.468034 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1278 16:31:11.468113 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1279 16:31:11.468190 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1280 16:31:11.468271 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1281 16:31:11.468349 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1282 16:31:11.468427 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1283 16:31:11.468507 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1284 16:31:11.468585 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1285 16:31:11.468679 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1286 16:31:11.468760 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1287 16:31:11.468812 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1288 16:31:11.468862 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1289 16:31:11.468910 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1290 16:31:11.468961 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1291 16:31:11.469016 ==
1292 16:31:11.469066 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 16:31:11.469115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 16:31:11.469165 ==
1295 16:31:11.469213 DQS Delay:
1296 16:31:11.469267 DQS0 = 0, DQS1 = 0
1297 16:31:11.469316 DQM Delay:
1298 16:31:11.469366 DQM0 = 81, DQM1 = 72
1299 16:31:11.469415 DQ Delay:
1300 16:31:11.469464 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1301 16:31:11.469520 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
1302 16:31:11.469569 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1303 16:31:11.469619 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1304 16:31:11.469668
1305 16:31:11.469717
1306 16:31:11.469787 ==
1307 16:31:11.469864 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 16:31:11.469942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 16:31:11.470022 ==
1310 16:31:11.470099
1311 16:31:11.470175
1312 16:31:11.470255 TX Vref Scan disable
1313 16:31:11.470333 == TX Byte 0 ==
1314 16:31:11.470411 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1315 16:31:11.470492 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1316 16:31:11.470570 == TX Byte 1 ==
1317 16:31:11.470647 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1318 16:31:11.470726 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1319 16:31:11.470805 ==
1320 16:31:11.470882 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 16:31:11.470959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 16:31:11.471039 ==
1323 16:31:11.471117 TX Vref=22, minBit 5, minWin=26, winSum=431
1324 16:31:11.471195 TX Vref=24, minBit 12, minWin=26, winSum=438
1325 16:31:11.471276 TX Vref=26, minBit 11, minWin=26, winSum=438
1326 16:31:11.471354 TX Vref=28, minBit 1, minWin=27, winSum=439
1327 16:31:11.471432 TX Vref=30, minBit 1, minWin=27, winSum=444
1328 16:31:11.471513 TX Vref=32, minBit 8, minWin=27, winSum=441
1329 16:31:11.471592 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 30
1330 16:31:11.471670
1331 16:31:11.471748 Final TX Range 1 Vref 30
1332 16:31:11.471826
1333 16:31:11.471901 ==
1334 16:31:11.471979 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 16:31:11.472058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 16:31:11.472134 ==
1337 16:31:11.472209
1338 16:31:11.472294
1339 16:31:11.472370 TX Vref Scan disable
1340 16:31:11.472449 == TX Byte 0 ==
1341 16:31:11.472538 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1342 16:31:11.472621 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1343 16:31:11.472730 == TX Byte 1 ==
1344 16:31:11.472831 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1345 16:31:11.472934 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1346 16:31:11.473032
1347 16:31:11.473139 [DATLAT]
1348 16:31:11.473245 Freq=800, CH0 RK1
1349 16:31:11.473351
1350 16:31:11.473459 DATLAT Default: 0xa
1351 16:31:11.473565 0, 0xFFFF, sum = 0
1352 16:31:11.473666 1, 0xFFFF, sum = 0
1353 16:31:11.473729 2, 0xFFFF, sum = 0
1354 16:31:11.473782 3, 0xFFFF, sum = 0
1355 16:31:11.473833 4, 0xFFFF, sum = 0
1356 16:31:11.473883 5, 0xFFFF, sum = 0
1357 16:31:11.473937 6, 0xFFFF, sum = 0
1358 16:31:11.473990 7, 0xFFFF, sum = 0
1359 16:31:11.474069 8, 0xFFFF, sum = 0
1360 16:31:11.474149 9, 0x0, sum = 1
1361 16:31:11.474231 10, 0x0, sum = 2
1362 16:31:11.474310 11, 0x0, sum = 3
1363 16:31:11.474389 12, 0x0, sum = 4
1364 16:31:11.474470 best_step = 10
1365 16:31:11.474547
1366 16:31:11.474623 ==
1367 16:31:11.474703 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 16:31:11.474782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 16:31:11.474860 ==
1370 16:31:11.475142 RX Vref Scan: 0
1371 16:31:11.475228
1372 16:31:11.475307 RX Vref 0 -> 0, step: 1
1373 16:31:11.475384
1374 16:31:11.475465 RX Delay -111 -> 252, step: 8
1375 16:31:11.475543 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1376 16:31:11.475623 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1377 16:31:11.475689 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1378 16:31:11.475739 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1379 16:31:11.475788 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1380 16:31:11.475836 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1381 16:31:11.475885 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1382 16:31:11.475948 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1383 16:31:11.476039 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1384 16:31:11.476147 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1385 16:31:11.476242 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1386 16:31:11.476323 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1387 16:31:11.476422 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1388 16:31:11.476512 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1389 16:31:11.476590 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1390 16:31:11.476688 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1391 16:31:11.476767 ==
1392 16:31:11.476845 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 16:31:11.476921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 16:31:11.476975 ==
1395 16:31:11.477024 DQS Delay:
1396 16:31:11.477074 DQS0 = 0, DQS1 = 0
1397 16:31:11.477123 DQM Delay:
1398 16:31:11.477190 DQM0 = 79, DQM1 = 69
1399 16:31:11.477267 DQ Delay:
1400 16:31:11.477344 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1401 16:31:11.477425 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =92
1402 16:31:11.477503 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1403 16:31:11.477580 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1404 16:31:11.477659
1405 16:31:11.477737
1406 16:31:11.477813 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
1407 16:31:11.477866 CH0 RK1: MR19=606, MR18=4C27
1408 16:31:11.477921 CH0_RK1: MR19=0x606, MR18=0x4C27, DQSOSC=390, MR23=63, INC=97, DEC=64
1409 16:31:11.477972 [RxdqsGatingPostProcess] freq 800
1410 16:31:11.478022 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1411 16:31:11.478071 Pre-setting of DQS Precalculation
1412 16:31:11.478120 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1413 16:31:11.478176 ==
1414 16:31:11.478226 Dram Type= 6, Freq= 0, CH_1, rank 0
1415 16:31:11.478275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 16:31:11.478324 ==
1417 16:31:11.478372 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1418 16:31:11.478454 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1419 16:31:11.478532 [CA 0] Center 36 (6~66) winsize 61
1420 16:31:11.478609 [CA 1] Center 36 (6~67) winsize 62
1421 16:31:11.478689 [CA 2] Center 34 (4~64) winsize 61
1422 16:31:11.478766 [CA 3] Center 34 (4~64) winsize 61
1423 16:31:11.478843 [CA 4] Center 35 (5~65) winsize 61
1424 16:31:11.478920 [CA 5] Center 34 (4~64) winsize 61
1425 16:31:11.479000
1426 16:31:11.479077 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1427 16:31:11.479154
1428 16:31:11.479238 [CATrainingPosCal] consider 1 rank data
1429 16:31:11.479326 u2DelayCellTimex100 = 270/100 ps
1430 16:31:11.479410 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1431 16:31:11.479492 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 16:31:11.479578 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1433 16:31:11.479663 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1434 16:31:11.479746 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1435 16:31:11.479830 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1436 16:31:11.479912
1437 16:31:11.479996 CA PerBit enable=1, Macro0, CA PI delay=34
1438 16:31:11.480080
1439 16:31:11.480162 [CBTSetCACLKResult] CA Dly = 34
1440 16:31:11.480243 CS Dly: 5 (0~36)
1441 16:31:11.480326 ==
1442 16:31:11.480411 Dram Type= 6, Freq= 0, CH_1, rank 1
1443 16:31:11.480495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 16:31:11.480581 ==
1445 16:31:11.480670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 16:31:11.480755 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 16:31:11.480839 [CA 0] Center 36 (6~66) winsize 61
1448 16:31:11.480922 [CA 1] Center 36 (6~67) winsize 62
1449 16:31:11.481003 [CA 2] Center 35 (5~65) winsize 61
1450 16:31:11.481087 [CA 3] Center 33 (3~64) winsize 62
1451 16:31:11.481169 [CA 4] Center 34 (4~65) winsize 62
1452 16:31:11.481252 [CA 5] Center 33 (3~64) winsize 62
1453 16:31:11.481333
1454 16:31:11.481415 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1455 16:31:11.481492
1456 16:31:11.481574 [CATrainingPosCal] consider 2 rank data
1457 16:31:11.481654 u2DelayCellTimex100 = 270/100 ps
1458 16:31:11.481732 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1459 16:31:11.481810 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 16:31:11.481898 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1461 16:31:11.481961 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1462 16:31:11.482012 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1463 16:31:11.482060 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1464 16:31:11.482109
1465 16:31:11.482188 CA PerBit enable=1, Macro0, CA PI delay=34
1466 16:31:11.482265
1467 16:31:11.482341 [CBTSetCACLKResult] CA Dly = 34
1468 16:31:11.482427 CS Dly: 5 (0~37)
1469 16:31:11.482507
1470 16:31:11.482588 ----->DramcWriteLeveling(PI) begin...
1471 16:31:11.482680 ==
1472 16:31:11.482777 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 16:31:11.482877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 16:31:11.482960 ==
1475 16:31:11.483035 Write leveling (Byte 0): 27 => 27
1476 16:31:11.483116 Write leveling (Byte 1): 30 => 30
1477 16:31:11.483200 DramcWriteLeveling(PI) end<-----
1478 16:31:11.483278
1479 16:31:11.483355 ==
1480 16:31:11.483437 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 16:31:11.483516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 16:31:11.483593 ==
1483 16:31:11.483673 [Gating] SW mode calibration
1484 16:31:11.483753 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1485 16:31:11.483831 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1486 16:31:11.483898 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1487 16:31:11.483949 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1488 16:31:11.483998 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1489 16:31:11.484047 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 16:31:11.484301 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 16:31:11.484390 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 16:31:11.484470 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 16:31:11.484548 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 16:31:11.484639 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 16:31:11.484703 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 16:31:11.484753 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 16:31:11.484803 0 7 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1498 16:31:11.484853 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 16:31:11.484907 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 16:31:11.484956 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 16:31:11.485004 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 16:31:11.485052 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 16:31:11.485101 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1504 16:31:11.485154 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1505 16:31:11.485203 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 16:31:11.485252 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 16:31:11.485300 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 16:31:11.485349 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 16:31:11.485404 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 16:31:11.485453 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 16:31:11.485502 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 16:31:11.485550 0 9 8 | B1->B0 | 2a2a 2e2d | 0 1 | (0 0) (0 0)
1513 16:31:11.485599 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 16:31:11.485653 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 16:31:11.485701 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 16:31:11.485750 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 16:31:11.485807 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 16:31:11.485892 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 16:31:11.485970 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
1520 16:31:11.486048 0 10 8 | B1->B0 | 2e2e 2626 | 0 0 | (1 1) (0 0)
1521 16:31:11.486132 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 16:31:11.486218 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 16:31:11.486302 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 16:31:11.486406 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 16:31:11.486486 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 16:31:11.486565 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1527 16:31:11.486656 0 11 4 | B1->B0 | 2424 2626 | 1 1 | (0 0) (0 0)
1528 16:31:11.486740 0 11 8 | B1->B0 | 3434 3636 | 1 1 | (0 0) (0 0)
1529 16:31:11.486829 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 16:31:11.486926 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 16:31:11.487009 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 16:31:11.487096 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 16:31:11.487182 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 16:31:11.487268 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 16:31:11.487367 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 16:31:11.487468 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1537 16:31:11.487554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 16:31:11.487637 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 16:31:11.487719 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 16:31:11.487786 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 16:31:11.487838 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 16:31:11.487894 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 16:31:11.487944 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 16:31:11.487994 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 16:31:11.488043 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 16:31:11.488092 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 16:31:11.488167 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 16:31:11.488249 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 16:31:11.488328 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 16:31:11.488409 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 16:31:11.488486 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1552 16:31:11.488564 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1553 16:31:11.488653 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 16:31:11.488735 Total UI for P1: 0, mck2ui 16
1555 16:31:11.488813 best dqsien dly found for B0: ( 0, 14, 6)
1556 16:31:11.488894 Total UI for P1: 0, mck2ui 16
1557 16:31:11.488973 best dqsien dly found for B1: ( 0, 14, 6)
1558 16:31:11.489051 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1559 16:31:11.489132 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1560 16:31:11.489208
1561 16:31:11.489285 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1562 16:31:11.489362 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1563 16:31:11.489442 [Gating] SW calibration Done
1564 16:31:11.489520 ==
1565 16:31:11.489597 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 16:31:11.489675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 16:31:11.489755 ==
1568 16:31:11.489834 RX Vref Scan: 0
1569 16:31:11.489920
1570 16:31:11.489999 RX Vref 0 -> 0, step: 1
1571 16:31:11.490076
1572 16:31:11.490152 RX Delay -130 -> 252, step: 16
1573 16:31:11.490229 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1574 16:31:11.490309 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1575 16:31:11.490386 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1576 16:31:11.490463 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1577 16:31:11.490540 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1578 16:31:11.490620 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1579 16:31:11.490698 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1580 16:31:11.490977 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1581 16:31:11.491062 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1582 16:31:11.491143 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1583 16:31:11.491222 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1584 16:31:11.491300 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1585 16:31:11.491377 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1586 16:31:11.491457 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1587 16:31:11.491535 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1588 16:31:11.491612 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1589 16:31:11.491688 ==
1590 16:31:11.491748 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 16:31:11.491799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 16:31:11.491857 ==
1593 16:31:11.491928 DQS Delay:
1594 16:31:11.492012 DQS0 = 0, DQS1 = 0
1595 16:31:11.492065 DQM Delay:
1596 16:31:11.492114 DQM0 = 82, DQM1 = 76
1597 16:31:11.492164 DQ Delay:
1598 16:31:11.492212 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1599 16:31:11.492291 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1600 16:31:11.492368 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1601 16:31:11.492445 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1602 16:31:11.492524
1603 16:31:11.492600
1604 16:31:11.492680 ==
1605 16:31:11.492731 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 16:31:11.492786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 16:31:11.492835 ==
1608 16:31:11.492883
1609 16:31:11.492931
1610 16:31:11.492979 TX Vref Scan disable
1611 16:31:11.493032 == TX Byte 0 ==
1612 16:31:11.493082 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1613 16:31:11.493131 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1614 16:31:11.493179 == TX Byte 1 ==
1615 16:31:11.493228 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1616 16:31:11.493281 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1617 16:31:11.493330 ==
1618 16:31:11.493378 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 16:31:11.493427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 16:31:11.493476 ==
1621 16:31:11.493524 TX Vref=22, minBit 1, minWin=27, winSum=443
1622 16:31:11.493580 TX Vref=24, minBit 1, minWin=27, winSum=446
1623 16:31:11.493630 TX Vref=26, minBit 1, minWin=27, winSum=447
1624 16:31:11.493679 TX Vref=28, minBit 6, minWin=27, winSum=447
1625 16:31:11.493727 TX Vref=30, minBit 6, minWin=27, winSum=449
1626 16:31:11.493776 TX Vref=32, minBit 4, minWin=27, winSum=446
1627 16:31:11.493854 [TxChooseVref] Worse bit 6, Min win 27, Win sum 449, Final Vref 30
1628 16:31:11.493933
1629 16:31:11.494010 Final TX Range 1 Vref 30
1630 16:31:11.494087
1631 16:31:11.494172 ==
1632 16:31:11.494263 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 16:31:11.494344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 16:31:11.494426 ==
1635 16:31:11.494502
1636 16:31:11.494578
1637 16:31:11.494655 TX Vref Scan disable
1638 16:31:11.494734 == TX Byte 0 ==
1639 16:31:11.494812 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1640 16:31:11.494890 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1641 16:31:11.494970 == TX Byte 1 ==
1642 16:31:11.495047 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1643 16:31:11.495125 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1644 16:31:11.495203
1645 16:31:11.495280 [DATLAT]
1646 16:31:11.495356 Freq=800, CH1 RK0
1647 16:31:11.495433
1648 16:31:11.495513 DATLAT Default: 0xa
1649 16:31:11.495590 0, 0xFFFF, sum = 0
1650 16:31:11.495669 1, 0xFFFF, sum = 0
1651 16:31:11.495726 2, 0xFFFF, sum = 0
1652 16:31:11.495775 3, 0xFFFF, sum = 0
1653 16:31:11.495825 4, 0xFFFF, sum = 0
1654 16:31:11.495875 5, 0xFFFF, sum = 0
1655 16:31:11.495928 6, 0xFFFF, sum = 0
1656 16:31:11.495978 7, 0xFFFF, sum = 0
1657 16:31:11.496027 8, 0xFFFF, sum = 0
1658 16:31:11.496076 9, 0x0, sum = 1
1659 16:31:11.496125 10, 0x0, sum = 2
1660 16:31:11.496174 11, 0x0, sum = 3
1661 16:31:11.496231 12, 0x0, sum = 4
1662 16:31:11.496310 best_step = 10
1663 16:31:11.496386
1664 16:31:11.496461 ==
1665 16:31:11.496541 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 16:31:11.496619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 16:31:11.496708 ==
1668 16:31:11.496761 RX Vref Scan: 1
1669 16:31:11.496810
1670 16:31:11.496858 Set Vref Range= 32 -> 127
1671 16:31:11.496906
1672 16:31:11.496961 RX Vref 32 -> 127, step: 1
1673 16:31:11.497010
1674 16:31:11.497058 RX Delay -111 -> 252, step: 8
1675 16:31:11.497105
1676 16:31:11.497154 Set Vref, RX VrefLevel [Byte0]: 32
1677 16:31:11.497202 [Byte1]: 32
1678 16:31:11.497257
1679 16:31:11.497305 Set Vref, RX VrefLevel [Byte0]: 33
1680 16:31:11.497354 [Byte1]: 33
1681 16:31:11.497403
1682 16:31:11.497450 Set Vref, RX VrefLevel [Byte0]: 34
1683 16:31:11.497500 [Byte1]: 34
1684 16:31:11.497554
1685 16:31:11.497602 Set Vref, RX VrefLevel [Byte0]: 35
1686 16:31:11.497650 [Byte1]: 35
1687 16:31:11.497698
1688 16:31:11.497746 Set Vref, RX VrefLevel [Byte0]: 36
1689 16:31:11.497795 [Byte1]: 36
1690 16:31:11.497873
1691 16:31:11.497950 Set Vref, RX VrefLevel [Byte0]: 37
1692 16:31:11.498026 [Byte1]: 37
1693 16:31:11.498108
1694 16:31:11.498193 Set Vref, RX VrefLevel [Byte0]: 38
1695 16:31:11.498271 [Byte1]: 38
1696 16:31:11.498346
1697 16:31:11.498433 Set Vref, RX VrefLevel [Byte0]: 39
1698 16:31:11.498516 [Byte1]: 39
1699 16:31:11.498597
1700 16:31:11.498679 Set Vref, RX VrefLevel [Byte0]: 40
1701 16:31:11.498767 [Byte1]: 40
1702 16:31:11.498846
1703 16:31:11.498926 Set Vref, RX VrefLevel [Byte0]: 41
1704 16:31:11.499004 [Byte1]: 41
1705 16:31:11.499081
1706 16:31:11.499157 Set Vref, RX VrefLevel [Byte0]: 42
1707 16:31:11.499238 [Byte1]: 42
1708 16:31:11.499314
1709 16:31:11.499390 Set Vref, RX VrefLevel [Byte0]: 43
1710 16:31:11.499471 [Byte1]: 43
1711 16:31:11.499547
1712 16:31:11.499624 Set Vref, RX VrefLevel [Byte0]: 44
1713 16:31:11.499688 [Byte1]: 44
1714 16:31:11.499738
1715 16:31:11.499787 Set Vref, RX VrefLevel [Byte0]: 45
1716 16:31:11.499836 [Byte1]: 45
1717 16:31:11.499884
1718 16:31:11.499938 Set Vref, RX VrefLevel [Byte0]: 46
1719 16:31:11.499987 [Byte1]: 46
1720 16:31:11.500035
1721 16:31:11.500083 Set Vref, RX VrefLevel [Byte0]: 47
1722 16:31:11.500137 [Byte1]: 47
1723 16:31:11.500214
1724 16:31:11.500291 Set Vref, RX VrefLevel [Byte0]: 48
1725 16:31:11.500370 [Byte1]: 48
1726 16:31:11.500447
1727 16:31:11.500524 Set Vref, RX VrefLevel [Byte0]: 49
1728 16:31:11.500601 [Byte1]: 49
1729 16:31:11.500687
1730 16:31:11.500764 Set Vref, RX VrefLevel [Byte0]: 50
1731 16:31:11.500840 [Byte1]: 50
1732 16:31:11.500920
1733 16:31:11.500997 Set Vref, RX VrefLevel [Byte0]: 51
1734 16:31:11.501074 [Byte1]: 51
1735 16:31:11.501153
1736 16:31:11.501230 Set Vref, RX VrefLevel [Byte0]: 52
1737 16:31:11.501306 [Byte1]: 52
1738 16:31:11.501381
1739 16:31:11.501432 Set Vref, RX VrefLevel [Byte0]: 53
1740 16:31:11.501481 [Byte1]: 53
1741 16:31:11.501529
1742 16:31:11.501777 Set Vref, RX VrefLevel [Byte0]: 54
1743 16:31:11.501838 [Byte1]: 54
1744 16:31:11.501916
1745 16:31:11.501996 Set Vref, RX VrefLevel [Byte0]: 55
1746 16:31:11.502079 [Byte1]: 55
1747 16:31:11.502167
1748 16:31:11.502228 Set Vref, RX VrefLevel [Byte0]: 56
1749 16:31:11.502279 [Byte1]: 56
1750 16:31:11.502336
1751 16:31:11.502386 Set Vref, RX VrefLevel [Byte0]: 57
1752 16:31:11.502436 [Byte1]: 57
1753 16:31:11.502485
1754 16:31:11.502534 Set Vref, RX VrefLevel [Byte0]: 58
1755 16:31:11.502600 [Byte1]: 58
1756 16:31:11.502676
1757 16:31:11.502752 Set Vref, RX VrefLevel [Byte0]: 59
1758 16:31:11.502833 [Byte1]: 59
1759 16:31:11.502909
1760 16:31:11.502986 Set Vref, RX VrefLevel [Byte0]: 60
1761 16:31:11.503067 [Byte1]: 60
1762 16:31:11.503143
1763 16:31:11.503219 Set Vref, RX VrefLevel [Byte0]: 61
1764 16:31:11.503299 [Byte1]: 61
1765 16:31:11.503376
1766 16:31:11.503453 Set Vref, RX VrefLevel [Byte0]: 62
1767 16:31:11.503534 [Byte1]: 62
1768 16:31:11.503612
1769 16:31:11.503689 Set Vref, RX VrefLevel [Byte0]: 63
1770 16:31:11.503765 [Byte1]: 63
1771 16:31:11.503816
1772 16:31:11.503864 Set Vref, RX VrefLevel [Byte0]: 64
1773 16:31:11.503914 [Byte1]: 64
1774 16:31:11.503963
1775 16:31:11.504018 Set Vref, RX VrefLevel [Byte0]: 65
1776 16:31:11.504068 [Byte1]: 65
1777 16:31:11.504116
1778 16:31:11.504165 Set Vref, RX VrefLevel [Byte0]: 66
1779 16:31:11.504213 [Byte1]: 66
1780 16:31:11.504297
1781 16:31:11.504376 Set Vref, RX VrefLevel [Byte0]: 67
1782 16:31:11.504456 [Byte1]: 67
1783 16:31:11.504543
1784 16:31:11.504626 Set Vref, RX VrefLevel [Byte0]: 68
1785 16:31:11.504715 [Byte1]: 68
1786 16:31:11.504793
1787 16:31:11.504874 Set Vref, RX VrefLevel [Byte0]: 69
1788 16:31:11.504955 [Byte1]: 69
1789 16:31:11.505032
1790 16:31:11.505109 Set Vref, RX VrefLevel [Byte0]: 70
1791 16:31:11.505189 [Byte1]: 70
1792 16:31:11.505265
1793 16:31:11.505332 Set Vref, RX VrefLevel [Byte0]: 71
1794 16:31:11.505413 [Byte1]: 71
1795 16:31:11.505506
1796 16:31:11.505587 Set Vref, RX VrefLevel [Byte0]: 72
1797 16:31:11.505673 [Byte1]: 72
1798 16:31:11.505750
1799 16:31:11.505826 Set Vref, RX VrefLevel [Byte0]: 73
1800 16:31:11.505910 [Byte1]: 73
1801 16:31:11.505987
1802 16:31:11.506064 Set Vref, RX VrefLevel [Byte0]: 74
1803 16:31:11.506143 [Byte1]: 74
1804 16:31:11.506222
1805 16:31:11.506298 Final RX Vref Byte 0 = 58 to rank0
1806 16:31:11.506376 Final RX Vref Byte 1 = 55 to rank0
1807 16:31:11.506456 Final RX Vref Byte 0 = 58 to rank1
1808 16:31:11.506534 Final RX Vref Byte 1 = 55 to rank1==
1809 16:31:11.506614 Dram Type= 6, Freq= 0, CH_1, rank 0
1810 16:31:11.506693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 16:31:11.506770 ==
1812 16:31:11.506847 DQS Delay:
1813 16:31:11.506925 DQS0 = 0, DQS1 = 0
1814 16:31:11.507002 DQM Delay:
1815 16:31:11.507078 DQM0 = 81, DQM1 = 71
1816 16:31:11.507160 DQ Delay:
1817 16:31:11.507238 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1818 16:31:11.507315 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1819 16:31:11.507395 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1820 16:31:11.507480 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1821 16:31:11.507566
1822 16:31:11.507646
1823 16:31:11.507725 [DQSOSCAuto] RK0, (LSB)MR18= 0x1620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1824 16:31:11.507803 CH1 RK0: MR19=606, MR18=1620
1825 16:31:11.507884 CH1_RK0: MR19=0x606, MR18=0x1620, DQSOSC=401, MR23=63, INC=91, DEC=61
1826 16:31:11.507962
1827 16:31:11.508038 ----->DramcWriteLeveling(PI) begin...
1828 16:31:11.508122 ==
1829 16:31:11.508201 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 16:31:11.508279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 16:31:11.508359 ==
1832 16:31:11.508437 Write leveling (Byte 0): 29 => 29
1833 16:31:11.508514 Write leveling (Byte 1): 31 => 31
1834 16:31:11.508594 DramcWriteLeveling(PI) end<-----
1835 16:31:11.508676
1836 16:31:11.508730 ==
1837 16:31:11.508793 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 16:31:11.508872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 16:31:11.508949 ==
1840 16:31:11.509028 [Gating] SW mode calibration
1841 16:31:11.509107 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1842 16:31:11.509185 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1843 16:31:11.509266 0 6 0 | B1->B0 | 2323 2322 | 0 1 | (1 1) (1 1)
1844 16:31:11.509345 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1845 16:31:11.509427 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 16:31:11.509508 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 16:31:11.509586 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 16:31:11.509664 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 16:31:11.509745 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 16:31:11.509824 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 16:31:11.509901 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 16:31:11.509979 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 16:31:11.510063 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 16:31:11.510143 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 16:31:11.510220 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 16:31:11.510300 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 16:31:11.510378 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 16:31:11.510455 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 16:31:11.510535 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1860 16:31:11.510613 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1861 16:31:11.510690 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1862 16:31:11.510770 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 16:31:11.510848 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 16:31:11.510927 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 16:31:11.511009 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 16:31:11.511088 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 16:31:11.511165 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1868 16:31:11.511244 0 9 4 | B1->B0 | 2323 3030 | 0 0 | (1 1) (0 0)
1869 16:31:11.511524 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1870 16:31:11.511608 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 16:31:11.511692 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 16:31:11.511754 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 16:31:11.511805 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 16:31:11.511854 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 16:31:11.511903 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1876 16:31:11.511975 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 0)
1877 16:31:11.512026 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1878 16:31:11.512075 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 16:31:11.512124 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 16:31:11.512187 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 16:31:11.512269 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 16:31:11.512346 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 16:31:11.512434 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 16:31:11.512513 0 11 4 | B1->B0 | 2c2c 3737 | 0 0 | (0 0) (0 0)
1885 16:31:11.512590 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1886 16:31:11.512685 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 16:31:11.512739 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 16:31:11.512788 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 16:31:11.512837 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 16:31:11.512889 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 16:31:11.512951 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 16:31:11.513011 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1893 16:31:11.513077 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1894 16:31:11.513161 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 16:31:11.513238 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 16:31:11.513331 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 16:31:11.513413 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 16:31:11.513496 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 16:31:11.513576 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 16:31:11.513654 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 16:31:11.513748 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 16:31:11.513831 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 16:31:11.513909 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 16:31:11.513994 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 16:31:11.514083 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 16:31:11.514162 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 16:31:11.514241 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 16:31:11.514319 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1909 16:31:11.514396 Total UI for P1: 0, mck2ui 16
1910 16:31:11.514492 best dqsien dly found for B0: ( 0, 14, 2)
1911 16:31:11.514573 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 16:31:11.514651 Total UI for P1: 0, mck2ui 16
1913 16:31:11.514752 best dqsien dly found for B1: ( 0, 14, 4)
1914 16:31:11.514832 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1915 16:31:11.514913 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1916 16:31:11.514990
1917 16:31:11.515067 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1918 16:31:11.515147 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1919 16:31:11.515238 [Gating] SW calibration Done
1920 16:31:11.515315 ==
1921 16:31:11.515397 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 16:31:11.515481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 16:31:11.515559 ==
1924 16:31:11.515648 RX Vref Scan: 0
1925 16:31:11.515723
1926 16:31:11.515774 RX Vref 0 -> 0, step: 1
1927 16:31:11.515823
1928 16:31:11.515873 RX Delay -130 -> 252, step: 16
1929 16:31:11.515950 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1930 16:31:11.516002 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1931 16:31:11.516051 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1932 16:31:11.516113 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1933 16:31:11.516199 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1934 16:31:11.516278 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1935 16:31:11.516363 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1936 16:31:11.516443 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1937 16:31:11.516520 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1938 16:31:11.516606 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1939 16:31:11.516703 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1940 16:31:11.516782 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1941 16:31:11.516870 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1942 16:31:11.516949 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1943 16:31:11.517026 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1944 16:31:11.517098 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1945 16:31:11.517157 ==
1946 16:31:11.517207 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 16:31:11.517268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 16:31:11.517359 ==
1949 16:31:11.517441 DQS Delay:
1950 16:31:11.517519 DQS0 = 0, DQS1 = 0
1951 16:31:11.517608 DQM Delay:
1952 16:31:11.517691 DQM0 = 78, DQM1 = 71
1953 16:31:11.517774 DQ Delay:
1954 16:31:11.517854 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1955 16:31:11.735407 DQ4 =69, DQ5 =93, DQ6 =93, DQ7 =77
1956 16:31:11.735554 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1957 16:31:11.735648 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1958 16:31:11.735732
1959 16:31:11.735814
1960 16:31:11.735870 ==
1961 16:31:11.735922 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 16:31:11.735974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 16:31:11.736025 ==
1964 16:31:11.736081
1965 16:31:11.736147
1966 16:31:11.736200 TX Vref Scan disable
1967 16:31:11.736283 == TX Byte 0 ==
1968 16:31:11.736375 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1969 16:31:11.736455 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1970 16:31:11.736534 == TX Byte 1 ==
1971 16:31:11.736616 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1972 16:31:11.736691 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1973 16:31:11.736743 ==
1974 16:31:11.736794 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 16:31:11.737050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 16:31:11.737109 ==
1977 16:31:11.737161 TX Vref=22, minBit 3, minWin=27, winSum=449
1978 16:31:11.737212 TX Vref=24, minBit 3, minWin=27, winSum=451
1979 16:31:11.737262 TX Vref=26, minBit 1, minWin=27, winSum=451
1980 16:31:11.737317 TX Vref=28, minBit 0, minWin=28, winSum=458
1981 16:31:11.737368 TX Vref=30, minBit 1, minWin=27, winSum=458
1982 16:31:11.737417 TX Vref=32, minBit 1, minWin=27, winSum=458
1983 16:31:11.737466 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1984 16:31:11.737516
1985 16:31:11.737572 Final TX Range 1 Vref 28
1986 16:31:11.737623
1987 16:31:11.737671 ==
1988 16:31:11.737719 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 16:31:11.737768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 16:31:11.737824 ==
1991 16:31:11.737873
1992 16:31:11.737921
1993 16:31:11.737969 TX Vref Scan disable
1994 16:31:11.738018 == TX Byte 0 ==
1995 16:31:11.738088 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1996 16:31:11.738166 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1997 16:31:11.738243 == TX Byte 1 ==
1998 16:31:11.738323 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1999 16:31:11.738402 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2000 16:31:11.738478
2001 16:31:11.738556 [DATLAT]
2002 16:31:11.738633 Freq=800, CH1 RK1
2003 16:31:11.738710
2004 16:31:11.738786 DATLAT Default: 0xa
2005 16:31:11.738866 0, 0xFFFF, sum = 0
2006 16:31:11.738945 1, 0xFFFF, sum = 0
2007 16:31:11.739023 2, 0xFFFF, sum = 0
2008 16:31:11.739104 3, 0xFFFF, sum = 0
2009 16:31:11.739183 4, 0xFFFF, sum = 0
2010 16:31:11.739261 5, 0xFFFF, sum = 0
2011 16:31:11.739342 6, 0xFFFF, sum = 0
2012 16:31:11.739422 7, 0xFFFF, sum = 0
2013 16:31:11.739500 8, 0xFFFF, sum = 0
2014 16:31:11.739582 9, 0x0, sum = 1
2015 16:31:11.739661 10, 0x0, sum = 2
2016 16:31:11.739740 11, 0x0, sum = 3
2017 16:31:11.739822 12, 0x0, sum = 4
2018 16:31:11.739901 best_step = 10
2019 16:31:11.739977
2020 16:31:11.740059 ==
2021 16:31:11.740143 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 16:31:11.740221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 16:31:11.740301 ==
2024 16:31:11.740379 RX Vref Scan: 0
2025 16:31:11.740455
2026 16:31:11.740534 RX Vref 0 -> 0, step: 1
2027 16:31:11.740611
2028 16:31:11.740689 RX Delay -111 -> 252, step: 8
2029 16:31:11.740740 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2030 16:31:11.740798 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2031 16:31:11.740848 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2032 16:31:11.740897 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2033 16:31:11.740945 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2034 16:31:11.740994 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2035 16:31:11.741048 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2036 16:31:11.741096 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2037 16:31:11.741145 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2038 16:31:11.741194 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2039 16:31:11.741246 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2040 16:31:11.741297 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2041 16:31:11.741345 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2042 16:31:11.741396 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2043 16:31:11.741445 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2044 16:31:11.741503 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2045 16:31:11.741554 ==
2046 16:31:11.741603 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 16:31:11.741652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 16:31:11.741701 ==
2049 16:31:11.741754 DQS Delay:
2050 16:31:11.741804 DQS0 = 0, DQS1 = 0
2051 16:31:11.741852 DQM Delay:
2052 16:31:11.741900 DQM0 = 77, DQM1 = 74
2053 16:31:11.741948 DQ Delay:
2054 16:31:11.742006 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2055 16:31:11.742085 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2056 16:31:11.742162 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
2057 16:31:11.742241 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2058 16:31:11.742318
2059 16:31:11.742394
2060 16:31:11.742473 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2061 16:31:11.742554 CH1 RK1: MR19=606, MR18=2139
2062 16:31:11.742632 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2063 16:31:11.742709 [RxdqsGatingPostProcess] freq 800
2064 16:31:11.742790 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2065 16:31:11.742867 Pre-setting of DQS Precalculation
2066 16:31:11.742945 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2067 16:31:11.743026 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2068 16:31:11.743107 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2069 16:31:11.743184
2070 16:31:11.743263
2071 16:31:11.743340 [Calibration Summary] 1600 Mbps
2072 16:31:11.743416 CH 0, Rank 0
2073 16:31:11.743495 SW Impedance : PASS
2074 16:31:11.743574 DUTY Scan : NO K
2075 16:31:11.743651 ZQ Calibration : PASS
2076 16:31:11.743728 Jitter Meter : NO K
2077 16:31:11.743808 CBT Training : PASS
2078 16:31:11.743860 Write leveling : PASS
2079 16:31:11.743909 RX DQS gating : PASS
2080 16:31:11.743957 RX DQ/DQS(RDDQC) : PASS
2081 16:31:11.744010 TX DQ/DQS : PASS
2082 16:31:11.744061 RX DATLAT : PASS
2083 16:31:11.744110 RX DQ/DQS(Engine): PASS
2084 16:31:11.744159 TX OE : NO K
2085 16:31:11.744208 All Pass.
2086 16:31:11.744264
2087 16:31:11.744342 CH 0, Rank 1
2088 16:31:11.744418 SW Impedance : PASS
2089 16:31:11.744501 DUTY Scan : NO K
2090 16:31:11.744579 ZQ Calibration : PASS
2091 16:31:11.744665 Jitter Meter : NO K
2092 16:31:11.744746 CBT Training : PASS
2093 16:31:11.744824 Write leveling : PASS
2094 16:31:11.744901 RX DQS gating : PASS
2095 16:31:11.744979 RX DQ/DQS(RDDQC) : PASS
2096 16:31:11.745058 TX DQ/DQS : PASS
2097 16:31:11.745135 RX DATLAT : PASS
2098 16:31:11.745220 RX DQ/DQS(Engine): PASS
2099 16:31:11.745275 TX OE : NO K
2100 16:31:11.745324 All Pass.
2101 16:31:11.745374
2102 16:31:11.745423 CH 1, Rank 0
2103 16:31:11.745479 SW Impedance : PASS
2104 16:31:11.745529 DUTY Scan : NO K
2105 16:31:11.745578 ZQ Calibration : PASS
2106 16:31:11.745627 Jitter Meter : NO K
2107 16:31:11.745676 CBT Training : PASS
2108 16:31:11.745730 Write leveling : PASS
2109 16:31:11.745779 RX DQS gating : PASS
2110 16:31:11.745828 RX DQ/DQS(RDDQC) : PASS
2111 16:31:11.745877 TX DQ/DQS : PASS
2112 16:31:11.745931 RX DATLAT : PASS
2113 16:31:11.745982 RX DQ/DQS(Engine): PASS
2114 16:31:11.746030 TX OE : NO K
2115 16:31:11.746079 All Pass.
2116 16:31:11.746128
2117 16:31:11.746185 CH 1, Rank 1
2118 16:31:11.746263 SW Impedance : PASS
2119 16:31:11.746340 DUTY Scan : NO K
2120 16:31:11.746420 ZQ Calibration : PASS
2121 16:31:11.746498 Jitter Meter : NO K
2122 16:31:11.746574 CBT Training : PASS
2123 16:31:11.746654 Write leveling : PASS
2124 16:31:11.746732 RX DQS gating : PASS
2125 16:31:11.746810 RX DQ/DQS(RDDQC) : PASS
2126 16:31:11.747098 TX DQ/DQS : PASS
2127 16:31:11.747183 RX DATLAT : PASS
2128 16:31:11.747261 RX DQ/DQS(Engine): PASS
2129 16:31:11.747339 TX OE : NO K
2130 16:31:11.747420 All Pass.
2131 16:31:11.747497
2132 16:31:11.747575 DramC Write-DBI off
2133 16:31:11.747656 PER_BANK_REFRESH: Hybrid Mode
2134 16:31:11.747733 TX_TRACKING: ON
2135 16:31:11.747811 [GetDramInforAfterCalByMRR] Vendor 6.
2136 16:31:11.747892 [GetDramInforAfterCalByMRR] Revision 606.
2137 16:31:11.747970 [GetDramInforAfterCalByMRR] Revision 2 0.
2138 16:31:11.748048 MR0 0x3b3b
2139 16:31:11.748128 MR8 0x5151
2140 16:31:11.748206 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2141 16:31:11.748283
2142 16:31:11.748363 MR0 0x3b3b
2143 16:31:11.748440 MR8 0x5151
2144 16:31:11.748517 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2145 16:31:11.748598
2146 16:31:11.748680 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2147 16:31:11.748734 [FAST_K] Save calibration result to emmc
2148 16:31:11.748785 [FAST_K] Save calibration result to emmc
2149 16:31:11.748840 dram_init: config_dvfs: 1
2150 16:31:11.748890 dramc_set_vcore_voltage set vcore to 662500
2151 16:31:11.748938 Read voltage for 1200, 2
2152 16:31:11.748988 Vio18 = 0
2153 16:31:11.749041 Vcore = 662500
2154 16:31:11.749091 Vdram = 0
2155 16:31:11.749140 Vddq = 0
2156 16:31:11.749188 Vmddr = 0
2157 16:31:11.749236 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2158 16:31:11.749289 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2159 16:31:11.749341 MEM_TYPE=3, freq_sel=15
2160 16:31:11.749389 sv_algorithm_assistance_LP4_1600
2161 16:31:11.749438 ============ PULL DRAM RESETB DOWN ============
2162 16:31:11.749488 ========== PULL DRAM RESETB DOWN end =========
2163 16:31:11.749540 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2164 16:31:11.749591 ===================================
2165 16:31:11.749640 LPDDR4 DRAM CONFIGURATION
2166 16:31:11.749688 ===================================
2167 16:31:11.749737 EX_ROW_EN[0] = 0x0
2168 16:31:11.749790 EX_ROW_EN[1] = 0x0
2169 16:31:11.749840 LP4Y_EN = 0x0
2170 16:31:11.749888 WORK_FSP = 0x0
2171 16:31:11.749936 WL = 0x4
2172 16:31:11.749985 RL = 0x4
2173 16:31:11.750038 BL = 0x2
2174 16:31:11.750116 RPST = 0x0
2175 16:31:11.750193 RD_PRE = 0x0
2176 16:31:11.750269 WR_PRE = 0x1
2177 16:31:11.750349 WR_PST = 0x0
2178 16:31:11.750426 DBI_WR = 0x0
2179 16:31:11.750503 DBI_RD = 0x0
2180 16:31:11.750583 OTF = 0x1
2181 16:31:11.750661 ===================================
2182 16:31:11.750739 ===================================
2183 16:31:11.750820 ANA top config
2184 16:31:11.750898 ===================================
2185 16:31:11.750976 DLL_ASYNC_EN = 0
2186 16:31:11.751057 ALL_SLAVE_EN = 0
2187 16:31:11.751134 NEW_RANK_MODE = 1
2188 16:31:11.751212 DLL_IDLE_MODE = 1
2189 16:31:11.751293 LP45_APHY_COMB_EN = 1
2190 16:31:11.751370 TX_ODT_DIS = 1
2191 16:31:11.751448 NEW_8X_MODE = 1
2192 16:31:11.751529 ===================================
2193 16:31:11.751607 ===================================
2194 16:31:11.751685 data_rate = 2400
2195 16:31:11.751766 CKR = 1
2196 16:31:11.751844 DQ_P2S_RATIO = 8
2197 16:31:11.751922 ===================================
2198 16:31:11.752002 CA_P2S_RATIO = 8
2199 16:31:11.752080 DQ_CA_OPEN = 0
2200 16:31:11.752157 DQ_SEMI_OPEN = 0
2201 16:31:11.752236 CA_SEMI_OPEN = 0
2202 16:31:11.752315 CA_FULL_RATE = 0
2203 16:31:11.752392 DQ_CKDIV4_EN = 0
2204 16:31:11.752469 CA_CKDIV4_EN = 0
2205 16:31:11.752549 CA_PREDIV_EN = 0
2206 16:31:11.752627 PH8_DLY = 17
2207 16:31:11.752712 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2208 16:31:11.752775 DQ_AAMCK_DIV = 4
2209 16:31:11.752826 CA_AAMCK_DIV = 4
2210 16:31:11.752875 CA_ADMCK_DIV = 4
2211 16:31:11.752924 DQ_TRACK_CA_EN = 0
2212 16:31:11.752973 CA_PICK = 1200
2213 16:31:11.753028 CA_MCKIO = 1200
2214 16:31:11.753077 MCKIO_SEMI = 0
2215 16:31:11.753126 PLL_FREQ = 2366
2216 16:31:11.753175 DQ_UI_PI_RATIO = 32
2217 16:31:11.753226 CA_UI_PI_RATIO = 0
2218 16:31:11.753279 ===================================
2219 16:31:11.753328 ===================================
2220 16:31:11.753377 memory_type:LPDDR4
2221 16:31:11.753426 GP_NUM : 10
2222 16:31:11.753477 SRAM_EN : 1
2223 16:31:11.753529 MD32_EN : 0
2224 16:31:11.753577 ===================================
2225 16:31:11.753627 [ANA_INIT] >>>>>>>>>>>>>>
2226 16:31:11.753676 <<<<<< [CONFIGURE PHASE]: ANA_TX
2227 16:31:11.753725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2228 16:31:11.753779 ===================================
2229 16:31:11.753829 data_rate = 2400,PCW = 0X5b00
2230 16:31:11.753879 ===================================
2231 16:31:11.753928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2232 16:31:11.753977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2233 16:31:11.754057 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2234 16:31:11.754136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2235 16:31:11.754214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2236 16:31:11.754296 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2237 16:31:11.754374 [ANA_INIT] flow start
2238 16:31:11.754451 [ANA_INIT] PLL >>>>>>>>
2239 16:31:11.754531 [ANA_INIT] PLL <<<<<<<<
2240 16:31:11.754609 [ANA_INIT] MIDPI >>>>>>>>
2241 16:31:11.754686 [ANA_INIT] MIDPI <<<<<<<<
2242 16:31:11.754767 [ANA_INIT] DLL >>>>>>>>
2243 16:31:11.754844 [ANA_INIT] DLL <<<<<<<<
2244 16:31:11.754921 [ANA_INIT] flow end
2245 16:31:11.755001 ============ LP4 DIFF to SE enter ============
2246 16:31:11.755080 ============ LP4 DIFF to SE exit ============
2247 16:31:11.755158 [ANA_INIT] <<<<<<<<<<<<<
2248 16:31:11.755237 [Flow] Enable top DCM control >>>>>
2249 16:31:11.755316 [Flow] Enable top DCM control <<<<<
2250 16:31:11.755393 Enable DLL master slave shuffle
2251 16:31:11.755471 ==============================================================
2252 16:31:11.755552 Gating Mode config
2253 16:31:11.755630 ==============================================================
2254 16:31:11.755708 Config description:
2255 16:31:11.755995 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2256 16:31:11.756082 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2257 16:31:11.756162 SELPH_MODE 0: By rank 1: By Phase
2258 16:31:11.756243 ==============================================================
2259 16:31:11.756323 GAT_TRACK_EN = 1
2260 16:31:11.756400 RX_GATING_MODE = 2
2261 16:31:11.756478 RX_GATING_TRACK_MODE = 2
2262 16:31:11.756559 SELPH_MODE = 1
2263 16:31:11.756637 PICG_EARLY_EN = 1
2264 16:31:11.756727 VALID_LAT_VALUE = 1
2265 16:31:11.756784 ==============================================================
2266 16:31:11.756834 Enter into Gating configuration >>>>
2267 16:31:11.756883 Exit from Gating configuration <<<<
2268 16:31:11.756932 Enter into DVFS_PRE_config >>>>>
2269 16:31:11.756986 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2270 16:31:11.757039 Exit from DVFS_PRE_config <<<<<
2271 16:31:11.757088 Enter into PICG configuration >>>>
2272 16:31:11.757138 Exit from PICG configuration <<<<
2273 16:31:11.757186 [RX_INPUT] configuration >>>>>
2274 16:31:11.757239 [RX_INPUT] configuration <<<<<
2275 16:31:11.757290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2276 16:31:11.757339 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2277 16:31:11.757388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2278 16:31:11.757438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2279 16:31:11.757491 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2280 16:31:11.757543 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2281 16:31:11.757592 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2282 16:31:11.757641 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2283 16:31:11.757690 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2284 16:31:11.757742 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2285 16:31:11.757793 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2286 16:31:11.757842 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 16:31:11.757892 ===================================
2288 16:31:11.757941 LPDDR4 DRAM CONFIGURATION
2289 16:31:11.757998 ===================================
2290 16:31:11.758076 EX_ROW_EN[0] = 0x0
2291 16:31:11.758153 EX_ROW_EN[1] = 0x0
2292 16:31:11.758231 LP4Y_EN = 0x0
2293 16:31:11.758310 WORK_FSP = 0x0
2294 16:31:11.758387 WL = 0x4
2295 16:31:11.758463 RL = 0x4
2296 16:31:11.758543 BL = 0x2
2297 16:31:11.758620 RPST = 0x0
2298 16:31:11.758697 RD_PRE = 0x0
2299 16:31:11.758777 WR_PRE = 0x1
2300 16:31:11.758854 WR_PST = 0x0
2301 16:31:11.758931 DBI_WR = 0x0
2302 16:31:11.759010 DBI_RD = 0x0
2303 16:31:11.759087 OTF = 0x1
2304 16:31:11.759164 ===================================
2305 16:31:11.759245 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2306 16:31:11.759324 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2307 16:31:11.759402 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2308 16:31:11.759480 ===================================
2309 16:31:11.759561 LPDDR4 DRAM CONFIGURATION
2310 16:31:11.759638 ===================================
2311 16:31:11.759715 EX_ROW_EN[0] = 0x10
2312 16:31:11.759795 EX_ROW_EN[1] = 0x0
2313 16:31:11.759872 LP4Y_EN = 0x0
2314 16:31:11.759949 WORK_FSP = 0x0
2315 16:31:11.760028 WL = 0x4
2316 16:31:11.760105 RL = 0x4
2317 16:31:11.760182 BL = 0x2
2318 16:31:11.760261 RPST = 0x0
2319 16:31:11.760338 RD_PRE = 0x0
2320 16:31:11.760415 WR_PRE = 0x1
2321 16:31:11.760494 WR_PST = 0x0
2322 16:31:11.760572 DBI_WR = 0x0
2323 16:31:11.760655 DBI_RD = 0x0
2324 16:31:11.760735 OTF = 0x1
2325 16:31:11.760789 ===================================
2326 16:31:11.760839 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2327 16:31:11.760889 ==
2328 16:31:11.760938 Dram Type= 6, Freq= 0, CH_0, rank 0
2329 16:31:11.760992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2330 16:31:11.761043 ==
2331 16:31:11.761091 [Duty_Offset_Calibration]
2332 16:31:11.761139 B0:2 B1:0 CA:3
2333 16:31:11.761187
2334 16:31:11.761239 [DutyScan_Calibration_Flow] k_type=0
2335 16:31:11.761290
2336 16:31:11.761338 ==CLK 0==
2337 16:31:11.761385 Final CLK duty delay cell = 0
2338 16:31:11.761434 [0] MAX Duty = 5062%(X100), DQS PI = 12
2339 16:31:11.761485 [0] MIN Duty = 4906%(X100), DQS PI = 52
2340 16:31:11.761537 [0] AVG Duty = 4984%(X100)
2341 16:31:11.761585
2342 16:31:11.761632 CH0 CLK Duty spec in!! Max-Min= 156%
2343 16:31:11.761681 [DutyScan_Calibration_Flow] ====Done====
2344 16:31:11.761730
2345 16:31:11.761809 [DutyScan_Calibration_Flow] k_type=1
2346 16:31:11.761885
2347 16:31:11.761960 ==DQS 0 ==
2348 16:31:11.762040 Final DQS duty delay cell = 0
2349 16:31:11.762118 [0] MAX Duty = 5062%(X100), DQS PI = 12
2350 16:31:11.762195 [0] MIN Duty = 4907%(X100), DQS PI = 2
2351 16:31:11.762275 [0] AVG Duty = 4984%(X100)
2352 16:31:11.762351
2353 16:31:11.762427 ==DQS 1 ==
2354 16:31:11.762506 Final DQS duty delay cell = 0
2355 16:31:11.762585 [0] MAX Duty = 5125%(X100), DQS PI = 36
2356 16:31:11.762662 [0] MIN Duty = 5031%(X100), DQS PI = 0
2357 16:31:11.762741 [0] AVG Duty = 5078%(X100)
2358 16:31:11.762817
2359 16:31:11.762893 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2360 16:31:11.762969
2361 16:31:11.763049 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2362 16:31:11.763126 [DutyScan_Calibration_Flow] ====Done====
2363 16:31:11.763202
2364 16:31:11.763282 [DutyScan_Calibration_Flow] k_type=3
2365 16:31:11.763358
2366 16:31:11.763434 ==DQM 0 ==
2367 16:31:11.763514 Final DQM duty delay cell = 0
2368 16:31:11.763592 [0] MAX Duty = 5124%(X100), DQS PI = 12
2369 16:31:11.763668 [0] MIN Duty = 4876%(X100), DQS PI = 0
2370 16:31:11.763747 [0] AVG Duty = 5000%(X100)
2371 16:31:11.763824
2372 16:31:11.763899 ==DQM 1 ==
2373 16:31:11.763976 Final DQM duty delay cell = 4
2374 16:31:11.764058 [4] MAX Duty = 5124%(X100), DQS PI = 50
2375 16:31:11.764135 [4] MIN Duty = 5000%(X100), DQS PI = 10
2376 16:31:11.764211 [4] AVG Duty = 5062%(X100)
2377 16:31:11.764290
2378 16:31:11.764381 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2379 16:31:11.764457
2380 16:31:11.764537 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2381 16:31:11.764615 [DutyScan_Calibration_Flow] ====Done====
2382 16:31:11.764689
2383 16:31:11.764942 [DutyScan_Calibration_Flow] k_type=2
2384 16:31:11.765002
2385 16:31:11.765053 ==DQ 0 ==
2386 16:31:11.765103 Final DQ duty delay cell = -4
2387 16:31:11.765152 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2388 16:31:11.765201 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2389 16:31:11.765258 [-4] AVG Duty = 4969%(X100)
2390 16:31:11.765308
2391 16:31:11.765356 ==DQ 1 ==
2392 16:31:11.765404 Final DQ duty delay cell = -4
2393 16:31:11.765453 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2394 16:31:11.765508 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2395 16:31:11.765558 [-4] AVG Duty = 4938%(X100)
2396 16:31:11.765606
2397 16:31:11.765654 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2398 16:31:11.765703
2399 16:31:11.765757 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2400 16:31:11.765807 [DutyScan_Calibration_Flow] ====Done====
2401 16:31:11.765856 ==
2402 16:31:11.765904 Dram Type= 6, Freq= 0, CH_1, rank 0
2403 16:31:11.765953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2404 16:31:11.766010 ==
2405 16:31:11.766059 [Duty_Offset_Calibration]
2406 16:31:11.766107 B0:1 B1:-2 CA:0
2407 16:31:11.766155
2408 16:31:11.766203 [DutyScan_Calibration_Flow] k_type=0
2409 16:31:11.766258
2410 16:31:11.766307 ==CLK 0==
2411 16:31:11.766354 Final CLK duty delay cell = 0
2412 16:31:11.766404 [0] MAX Duty = 5031%(X100), DQS PI = 18
2413 16:31:11.766453 [0] MIN Duty = 4844%(X100), DQS PI = 58
2414 16:31:11.766506 [0] AVG Duty = 4937%(X100)
2415 16:31:11.766555
2416 16:31:11.766603 CH1 CLK Duty spec in!! Max-Min= 187%
2417 16:31:11.766652 [DutyScan_Calibration_Flow] ====Done====
2418 16:31:11.766702
2419 16:31:11.766758 [DutyScan_Calibration_Flow] k_type=1
2420 16:31:11.766835
2421 16:31:11.766910 ==DQS 0 ==
2422 16:31:11.766990 Final DQS duty delay cell = -4
2423 16:31:11.767068 [-4] MAX Duty = 4969%(X100), DQS PI = 8
2424 16:31:11.767145 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2425 16:31:11.767223 [-4] AVG Duty = 4938%(X100)
2426 16:31:11.767300
2427 16:31:11.767376 ==DQS 1 ==
2428 16:31:11.767452 Final DQS duty delay cell = 0
2429 16:31:11.767532 [0] MAX Duty = 5093%(X100), DQS PI = 0
2430 16:31:11.767609 [0] MIN Duty = 4844%(X100), DQS PI = 26
2431 16:31:11.767685 [0] AVG Duty = 4968%(X100)
2432 16:31:11.767764
2433 16:31:11.767841 CH1 DQS 0 Duty spec in!! Max-Min= 62%
2434 16:31:11.767917
2435 16:31:11.767996 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2436 16:31:11.768082 [DutyScan_Calibration_Flow] ====Done====
2437 16:31:11.768169
2438 16:31:11.768255 [DutyScan_Calibration_Flow] k_type=3
2439 16:31:11.768348
2440 16:31:11.768426 ==DQM 0 ==
2441 16:31:11.768520 Final DQM duty delay cell = 0
2442 16:31:11.768599 [0] MAX Duty = 5000%(X100), DQS PI = 24
2443 16:31:11.768700 [0] MIN Duty = 4844%(X100), DQS PI = 54
2444 16:31:11.768778 [0] AVG Duty = 4922%(X100)
2445 16:31:11.768854
2446 16:31:11.768931 ==DQM 1 ==
2447 16:31:11.769012 Final DQM duty delay cell = 0
2448 16:31:11.769090 [0] MAX Duty = 5031%(X100), DQS PI = 36
2449 16:31:11.769167 [0] MIN Duty = 4907%(X100), DQS PI = 4
2450 16:31:11.769231 [0] AVG Duty = 4969%(X100)
2451 16:31:11.769281
2452 16:31:11.769329 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2453 16:31:11.769378
2454 16:31:11.769427 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2455 16:31:11.769506 [DutyScan_Calibration_Flow] ====Done====
2456 16:31:11.769570
2457 16:31:11.769620 [DutyScan_Calibration_Flow] k_type=2
2458 16:31:11.769674
2459 16:31:11.769723 ==DQ 0 ==
2460 16:31:11.769773 Final DQ duty delay cell = 0
2461 16:31:11.769823 [0] MAX Duty = 5062%(X100), DQS PI = 18
2462 16:31:11.769872 [0] MIN Duty = 4938%(X100), DQS PI = 54
2463 16:31:11.769929 [0] AVG Duty = 5000%(X100)
2464 16:31:11.769979
2465 16:31:11.770027 ==DQ 1 ==
2466 16:31:11.770076 Final DQ duty delay cell = 0
2467 16:31:11.770124 [0] MAX Duty = 5125%(X100), DQS PI = 36
2468 16:31:11.770173 [0] MIN Duty = 4938%(X100), DQS PI = 26
2469 16:31:11.770251 [0] AVG Duty = 5031%(X100)
2470 16:31:11.770327
2471 16:31:11.770422 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2472 16:31:11.770502
2473 16:31:11.770581 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2474 16:31:11.770659 [DutyScan_Calibration_Flow] ====Done====
2475 16:31:11.770735 nWR fixed to 30
2476 16:31:11.770817 [ModeRegInit_LP4] CH0 RK0
2477 16:31:11.770894 [ModeRegInit_LP4] CH0 RK1
2478 16:31:11.770970 [ModeRegInit_LP4] CH1 RK0
2479 16:31:11.771050 [ModeRegInit_LP4] CH1 RK1
2480 16:31:11.771127 match AC timing 7
2481 16:31:11.771205 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2482 16:31:11.771286 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2483 16:31:11.771364 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2484 16:31:11.771442 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2485 16:31:11.771523 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2486 16:31:11.771600 ==
2487 16:31:11.771676 Dram Type= 6, Freq= 0, CH_0, rank 0
2488 16:31:11.771753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 16:31:11.771806 ==
2490 16:31:11.771855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 16:31:11.771904 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2492 16:31:11.771953 [CA 0] Center 40 (10~71) winsize 62
2493 16:31:11.772009 [CA 1] Center 39 (9~70) winsize 62
2494 16:31:11.772059 [CA 2] Center 36 (6~66) winsize 61
2495 16:31:11.772107 [CA 3] Center 35 (5~66) winsize 62
2496 16:31:11.772155 [CA 4] Center 34 (4~65) winsize 62
2497 16:31:11.772203 [CA 5] Center 33 (3~63) winsize 61
2498 16:31:11.772274
2499 16:31:11.772356 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2500 16:31:11.772434
2501 16:31:11.772514 [CATrainingPosCal] consider 1 rank data
2502 16:31:11.772593 u2DelayCellTimex100 = 270/100 ps
2503 16:31:11.772696 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2504 16:31:11.772777 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2505 16:31:11.772854 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2506 16:31:11.772932 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2507 16:31:11.772985 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2508 16:31:11.773034 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2509 16:31:11.773082
2510 16:31:11.773130 CA PerBit enable=1, Macro0, CA PI delay=33
2511 16:31:11.773183
2512 16:31:11.773232 [CBTSetCACLKResult] CA Dly = 33
2513 16:31:11.773281 CS Dly: 7 (0~38)
2514 16:31:11.773330 ==
2515 16:31:11.773378 Dram Type= 6, Freq= 0, CH_0, rank 1
2516 16:31:11.773434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 16:31:11.773484 ==
2518 16:31:11.773532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 16:31:11.773582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2520 16:31:11.773635 [CA 0] Center 40 (10~70) winsize 61
2521 16:31:11.773686 [CA 1] Center 39 (9~70) winsize 62
2522 16:31:11.773736 [CA 2] Center 35 (5~66) winsize 62
2523 16:31:11.773785 [CA 3] Center 35 (5~66) winsize 62
2524 16:31:11.773833 [CA 4] Center 34 (4~65) winsize 62
2525 16:31:11.773898 [CA 5] Center 33 (3~64) winsize 62
2526 16:31:11.773974
2527 16:31:11.774257 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2528 16:31:11.774345
2529 16:31:11.774427 [CATrainingPosCal] consider 2 rank data
2530 16:31:11.774505 u2DelayCellTimex100 = 270/100 ps
2531 16:31:11.774583 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2532 16:31:11.774664 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2533 16:31:11.774742 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2534 16:31:11.774819 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 16:31:11.774900 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2536 16:31:11.774978 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2537 16:31:11.775067
2538 16:31:11.775163 CA PerBit enable=1, Macro0, CA PI delay=33
2539 16:31:11.775243
2540 16:31:11.775332 [CBTSetCACLKResult] CA Dly = 33
2541 16:31:11.775411 CS Dly: 8 (0~40)
2542 16:31:11.775490
2543 16:31:11.775582 ----->DramcWriteLeveling(PI) begin...
2544 16:31:11.775668 ==
2545 16:31:11.775747 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 16:31:11.775799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 16:31:11.775849 ==
2548 16:31:11.775898 Write leveling (Byte 0): 34 => 34
2549 16:31:11.775950 Write leveling (Byte 1): 28 => 28
2550 16:31:11.776015 DramcWriteLeveling(PI) end<-----
2551 16:31:11.776067
2552 16:31:11.776140 ==
2553 16:31:11.776229 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 16:31:11.776311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 16:31:11.776404 ==
2556 16:31:11.776484 [Gating] SW mode calibration
2557 16:31:11.776563 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2558 16:31:11.776662 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2559 16:31:11.776744 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
2560 16:31:11.776796 0 15 4 | B1->B0 | 2928 3434 | 1 1 | (0 0) (1 1)
2561 16:31:11.776874 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 16:31:11.776952 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 16:31:11.777033 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 16:31:11.777113 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 16:31:11.777190 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 16:31:11.777268 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2567 16:31:11.777348 1 0 0 | B1->B0 | 3030 2525 | 0 1 | (0 0) (1 0)
2568 16:31:11.777426 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 16:31:11.777503 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 16:31:11.777580 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 16:31:11.777660 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 16:31:11.777739 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 16:31:11.777816 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 16:31:11.777894 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2575 16:31:11.777982 1 1 0 | B1->B0 | 2b2b 3232 | 0 0 | (0 0) (0 0)
2576 16:31:11.778063 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2577 16:31:11.778141 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 16:31:11.778218 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 16:31:11.778298 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 16:31:11.778376 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 16:31:11.778453 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 16:31:11.778532 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2583 16:31:11.778610 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2584 16:31:11.778687 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2585 16:31:11.778763 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 16:31:11.778844 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 16:31:11.778922 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 16:31:11.778999 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 16:31:11.779078 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 16:31:11.779156 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 16:31:11.779233 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 16:31:11.779310 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 16:31:11.779392 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 16:31:11.779474 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 16:31:11.779557 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 16:31:11.779634 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 16:31:11.779715 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 16:31:11.779792 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2599 16:31:11.779869 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2600 16:31:11.779933 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 16:31:11.779983 Total UI for P1: 0, mck2ui 16
2602 16:31:11.780033 best dqsien dly found for B0: ( 1, 3, 30)
2603 16:31:11.780082 Total UI for P1: 0, mck2ui 16
2604 16:31:11.780134 best dqsien dly found for B1: ( 1, 4, 0)
2605 16:31:11.780214 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2606 16:31:11.780291 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2607 16:31:11.780368
2608 16:31:11.780448 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2609 16:31:11.780526 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2610 16:31:11.780610 [Gating] SW calibration Done
2611 16:31:11.780715 ==
2612 16:31:11.780795 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 16:31:11.780873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 16:31:11.780954 ==
2615 16:31:11.781031 RX Vref Scan: 0
2616 16:31:11.781107
2617 16:31:11.781187 RX Vref 0 -> 0, step: 1
2618 16:31:11.781263
2619 16:31:11.781339 RX Delay -40 -> 252, step: 8
2620 16:31:11.781425 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2621 16:31:11.781479 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2622 16:31:11.781529 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2623 16:31:11.781578 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2624 16:31:11.781627 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2625 16:31:11.781718 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2626 16:31:11.781796 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2627 16:31:11.781874 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2628 16:31:11.781965 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2629 16:31:11.782045 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2630 16:31:11.782351 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2631 16:31:11.782450 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2632 16:31:11.782541 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2633 16:31:11.782636 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2634 16:31:11.782723 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2635 16:31:11.782809 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2636 16:31:11.782893 ==
2637 16:31:11.782980 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 16:31:11.783063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 16:31:11.783145 ==
2640 16:31:11.783222 DQS Delay:
2641 16:31:11.783299 DQS0 = 0, DQS1 = 0
2642 16:31:11.783387 DQM Delay:
2643 16:31:11.783464 DQM0 = 112, DQM1 = 102
2644 16:31:11.783540 DQ Delay:
2645 16:31:11.783631 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2646 16:31:11.783711 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2647 16:31:11.783788 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2648 16:31:11.783871 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2649 16:31:11.783925
2650 16:31:11.783974
2651 16:31:11.784024 ==
2652 16:31:11.784087 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 16:31:11.784168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 16:31:11.784251 ==
2655 16:31:11.784339
2656 16:31:11.784423
2657 16:31:11.784518 TX Vref Scan disable
2658 16:31:11.784611 == TX Byte 0 ==
2659 16:31:11.784732 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2660 16:31:11.784815 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2661 16:31:11.784909 == TX Byte 1 ==
2662 16:31:11.784991 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2663 16:31:11.785075 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2664 16:31:11.785153 ==
2665 16:31:11.785234 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 16:31:11.785314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 16:31:11.785391 ==
2668 16:31:11.785469 TX Vref=22, minBit 1, minWin=25, winSum=416
2669 16:31:11.785550 TX Vref=24, minBit 0, minWin=25, winSum=415
2670 16:31:11.785629 TX Vref=26, minBit 3, minWin=26, winSum=427
2671 16:31:11.785707 TX Vref=28, minBit 8, minWin=25, winSum=430
2672 16:31:11.785784 TX Vref=30, minBit 2, minWin=26, winSum=429
2673 16:31:11.785865 TX Vref=32, minBit 8, minWin=25, winSum=423
2674 16:31:11.785943 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
2675 16:31:11.786024
2676 16:31:11.786114 Final TX Range 1 Vref 30
2677 16:31:11.786193
2678 16:31:11.786270 ==
2679 16:31:11.786357 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 16:31:11.786436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 16:31:11.786513 ==
2682 16:31:11.786600
2683 16:31:11.786677
2684 16:31:11.786754 TX Vref Scan disable
2685 16:31:11.786841 == TX Byte 0 ==
2686 16:31:11.786919 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2687 16:31:11.786997 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2688 16:31:11.787084 == TX Byte 1 ==
2689 16:31:11.787163 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2690 16:31:11.787241 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2691 16:31:11.787331
2692 16:31:11.787411 [DATLAT]
2693 16:31:11.787488 Freq=1200, CH0 RK0
2694 16:31:11.787581
2695 16:31:11.787658 DATLAT Default: 0xd
2696 16:31:11.787739 0, 0xFFFF, sum = 0
2697 16:31:11.787830 1, 0xFFFF, sum = 0
2698 16:31:11.787910 2, 0xFFFF, sum = 0
2699 16:31:11.787993 3, 0xFFFF, sum = 0
2700 16:31:11.788087 4, 0xFFFF, sum = 0
2701 16:31:11.788171 5, 0xFFFF, sum = 0
2702 16:31:11.788253 6, 0xFFFF, sum = 0
2703 16:31:11.788332 7, 0xFFFF, sum = 0
2704 16:31:11.788415 8, 0xFFFF, sum = 0
2705 16:31:11.788500 9, 0xFFFF, sum = 0
2706 16:31:11.788579 10, 0xFFFF, sum = 0
2707 16:31:11.788667 11, 0xFFFF, sum = 0
2708 16:31:11.788721 12, 0x0, sum = 1
2709 16:31:11.788772 13, 0x0, sum = 2
2710 16:31:11.788848 14, 0x0, sum = 3
2711 16:31:11.788902 15, 0x0, sum = 4
2712 16:31:11.788952 best_step = 13
2713 16:31:11.789000
2714 16:31:11.789062 ==
2715 16:31:11.789143 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 16:31:11.789221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 16:31:11.789313 ==
2718 16:31:11.789393 RX Vref Scan: 1
2719 16:31:11.789477
2720 16:31:11.789561 Set Vref Range= 32 -> 127
2721 16:31:11.789644
2722 16:31:11.789720 RX Vref 32 -> 127, step: 1
2723 16:31:11.789803
2724 16:31:11.789880 RX Delay -37 -> 252, step: 4
2725 16:31:11.789964
2726 16:31:11.790045 Set Vref, RX VrefLevel [Byte0]: 32
2727 16:31:11.790123 [Byte1]: 32
2728 16:31:11.790208
2729 16:31:11.790287 Set Vref, RX VrefLevel [Byte0]: 33
2730 16:31:11.790376 [Byte1]: 33
2731 16:31:11.790463
2732 16:31:11.790541 Set Vref, RX VrefLevel [Byte0]: 34
2733 16:31:11.790618 [Byte1]: 34
2734 16:31:11.790704
2735 16:31:11.790782 Set Vref, RX VrefLevel [Byte0]: 35
2736 16:31:11.790859 [Byte1]: 35
2737 16:31:11.790946
2738 16:31:11.791024 Set Vref, RX VrefLevel [Byte0]: 36
2739 16:31:11.791102 [Byte1]: 36
2740 16:31:11.791189
2741 16:31:11.791267 Set Vref, RX VrefLevel [Byte0]: 37
2742 16:31:11.791344 [Byte1]: 37
2743 16:31:11.791430
2744 16:31:11.791508 Set Vref, RX VrefLevel [Byte0]: 38
2745 16:31:11.791585 [Byte1]: 38
2746 16:31:11.791671
2747 16:31:11.791748 Set Vref, RX VrefLevel [Byte0]: 39
2748 16:31:11.791825 [Byte1]: 39
2749 16:31:11.791911
2750 16:31:11.791988 Set Vref, RX VrefLevel [Byte0]: 40
2751 16:31:11.792065 [Byte1]: 40
2752 16:31:11.792152
2753 16:31:11.792230 Set Vref, RX VrefLevel [Byte0]: 41
2754 16:31:11.792307 [Byte1]: 41
2755 16:31:11.792392
2756 16:31:11.792475 Set Vref, RX VrefLevel [Byte0]: 42
2757 16:31:11.792555 [Byte1]: 42
2758 16:31:11.792641
2759 16:31:11.792712 Set Vref, RX VrefLevel [Byte0]: 43
2760 16:31:11.792762 [Byte1]: 43
2761 16:31:11.792812
2762 16:31:11.792864 Set Vref, RX VrefLevel [Byte0]: 44
2763 16:31:11.792929 [Byte1]: 44
2764 16:31:11.792978
2765 16:31:11.793027 Set Vref, RX VrefLevel [Byte0]: 45
2766 16:31:11.793075 [Byte1]: 45
2767 16:31:11.793138
2768 16:31:11.793197 Set Vref, RX VrefLevel [Byte0]: 46
2769 16:31:11.793262 [Byte1]: 46
2770 16:31:11.793342
2771 16:31:11.793432 Set Vref, RX VrefLevel [Byte0]: 47
2772 16:31:11.793510 [Byte1]: 47
2773 16:31:11.793594
2774 16:31:11.793683 Set Vref, RX VrefLevel [Byte0]: 48
2775 16:31:11.793762 [Byte1]: 48
2776 16:31:11.793838
2777 16:31:11.793925 Set Vref, RX VrefLevel [Byte0]: 49
2778 16:31:11.794003 [Byte1]: 49
2779 16:31:11.794081
2780 16:31:11.794166 Set Vref, RX VrefLevel [Byte0]: 50
2781 16:31:11.794246 [Byte1]: 50
2782 16:31:11.794333
2783 16:31:11.794421 Set Vref, RX VrefLevel [Byte0]: 51
2784 16:31:11.794501 [Byte1]: 51
2785 16:31:11.794577
2786 16:31:11.794668 Set Vref, RX VrefLevel [Byte0]: 52
2787 16:31:11.794753 [Byte1]: 52
2788 16:31:11.794833
2789 16:31:11.794922 Set Vref, RX VrefLevel [Byte0]: 53
2790 16:31:11.795011 [Byte1]: 53
2791 16:31:11.795090
2792 16:31:11.795179 Set Vref, RX VrefLevel [Byte0]: 54
2793 16:31:11.795472 [Byte1]: 54
2794 16:31:11.795559
2795 16:31:11.795645 Set Vref, RX VrefLevel [Byte0]: 55
2796 16:31:11.795739 [Byte1]: 55
2797 16:31:11.795841
2798 16:31:11.795934 Set Vref, RX VrefLevel [Byte0]: 56
2799 16:31:11.796022 [Byte1]: 56
2800 16:31:11.796105
2801 16:31:11.796189 Set Vref, RX VrefLevel [Byte0]: 57
2802 16:31:11.796273 [Byte1]: 57
2803 16:31:11.796356
2804 16:31:11.796435 Set Vref, RX VrefLevel [Byte0]: 58
2805 16:31:11.796531 [Byte1]: 58
2806 16:31:11.796608
2807 16:31:11.796698 Set Vref, RX VrefLevel [Byte0]: 59
2808 16:31:11.796776 [Byte1]: 59
2809 16:31:11.796852
2810 16:31:11.796932 Set Vref, RX VrefLevel [Byte0]: 60
2811 16:31:11.797010 [Byte1]: 60
2812 16:31:11.797087
2813 16:31:11.797166 Set Vref, RX VrefLevel [Byte0]: 61
2814 16:31:11.797244 [Byte1]: 61
2815 16:31:11.797320
2816 16:31:11.797400 Set Vref, RX VrefLevel [Byte0]: 62
2817 16:31:11.797480 [Byte1]: 62
2818 16:31:11.797569
2819 16:31:11.797658 Set Vref, RX VrefLevel [Byte0]: 63
2820 16:31:11.797741 [Byte1]: 63
2821 16:31:11.797819
2822 16:31:11.797900 Set Vref, RX VrefLevel [Byte0]: 64
2823 16:31:11.797977 [Byte1]: 64
2824 16:31:11.798054
2825 16:31:11.798133 Set Vref, RX VrefLevel [Byte0]: 65
2826 16:31:11.798211 [Byte1]: 65
2827 16:31:11.798287
2828 16:31:11.798365 Set Vref, RX VrefLevel [Byte0]: 66
2829 16:31:11.798444 [Byte1]: 66
2830 16:31:11.798519
2831 16:31:11.798596 Set Vref, RX VrefLevel [Byte0]: 67
2832 16:31:11.798677 [Byte1]: 67
2833 16:31:11.798753
2834 16:31:11.798829 Set Vref, RX VrefLevel [Byte0]: 68
2835 16:31:11.798909 [Byte1]: 68
2836 16:31:11.798985
2837 16:31:11.799061 Set Vref, RX VrefLevel [Byte0]: 69
2838 16:31:11.799138 [Byte1]: 69
2839 16:31:11.799217
2840 16:31:11.799294 Set Vref, RX VrefLevel [Byte0]: 70
2841 16:31:11.799370 [Byte1]: 70
2842 16:31:11.799446
2843 16:31:11.799525 Set Vref, RX VrefLevel [Byte0]: 71
2844 16:31:11.799602 [Byte1]: 71
2845 16:31:11.799677
2846 16:31:11.799756 Set Vref, RX VrefLevel [Byte0]: 72
2847 16:31:11.799833 [Byte1]: 72
2848 16:31:11.799909
2849 16:31:11.799985 Set Vref, RX VrefLevel [Byte0]: 73
2850 16:31:11.800065 [Byte1]: 73
2851 16:31:11.800141
2852 16:31:11.800218 Final RX Vref Byte 0 = 59 to rank0
2853 16:31:11.800298 Final RX Vref Byte 1 = 53 to rank0
2854 16:31:11.800376 Final RX Vref Byte 0 = 59 to rank1
2855 16:31:11.800454 Final RX Vref Byte 1 = 53 to rank1==
2856 16:31:11.800531 Dram Type= 6, Freq= 0, CH_0, rank 0
2857 16:31:11.800612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 16:31:11.800687 ==
2859 16:31:11.800738 DQS Delay:
2860 16:31:11.800786 DQS0 = 0, DQS1 = 0
2861 16:31:11.800854 DQM Delay:
2862 16:31:11.800906 DQM0 = 112, DQM1 = 101
2863 16:31:11.800956 DQ Delay:
2864 16:31:11.801005 DQ0 =110, DQ1 =112, DQ2 =110, DQ3 =108
2865 16:31:11.801054 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =122
2866 16:31:11.801103 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2867 16:31:11.801158 DQ12 =108, DQ13 =106, DQ14 =114, DQ15 =110
2868 16:31:11.801207
2869 16:31:11.801270
2870 16:31:11.801320 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2871 16:31:11.801389 CH0 RK0: MR19=303, MR18=FDFC
2872 16:31:11.801440 CH0_RK0: MR19=0x303, MR18=0xFDFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2873 16:31:11.801490
2874 16:31:11.801574 ----->DramcWriteLeveling(PI) begin...
2875 16:31:11.801662 ==
2876 16:31:11.801741 Dram Type= 6, Freq= 0, CH_0, rank 1
2877 16:31:11.801824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 16:31:11.801906 ==
2879 16:31:11.801984 Write leveling (Byte 0): 33 => 33
2880 16:31:11.802067 Write leveling (Byte 1): 31 => 31
2881 16:31:11.802150 DramcWriteLeveling(PI) end<-----
2882 16:31:11.802232
2883 16:31:11.802308 ==
2884 16:31:11.802388 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 16:31:11.802467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 16:31:11.802544 ==
2887 16:31:11.802627 [Gating] SW mode calibration
2888 16:31:11.802707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2889 16:31:11.802786 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2890 16:31:11.802866 0 15 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2891 16:31:11.802950 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 16:31:11.803028 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 16:31:11.803116 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 16:31:11.803206 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 16:31:11.803286 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 16:31:11.803366 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2897 16:31:11.803452 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2898 16:31:11.803530 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2899 16:31:11.803621 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 16:31:11.803704 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 16:31:11.803784 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 16:31:11.803837 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 16:31:11.803893 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 16:31:11.803981 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2905 16:31:11.804067 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2906 16:31:11.804155 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2907 16:31:11.804236 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 16:31:11.804315 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 16:31:11.804393 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 16:31:11.804473 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 16:31:11.804551 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 16:31:11.804628 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2913 16:31:11.804711 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2914 16:31:11.804790 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2915 16:31:11.804872 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 16:31:11.804962 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 16:31:11.805041 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 16:31:11.805322 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 16:31:11.805414 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 16:31:11.805495 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 16:31:11.805573 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 16:31:11.805659 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 16:31:11.805739 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 16:31:11.805817 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 16:31:11.805902 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 16:31:11.805983 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 16:31:11.806060 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 16:31:11.806141 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 16:31:11.806226 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2930 16:31:11.806303 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 16:31:11.806381 Total UI for P1: 0, mck2ui 16
2932 16:31:11.806469 best dqsien dly found for B0: ( 1, 3, 28)
2933 16:31:11.806547 Total UI for P1: 0, mck2ui 16
2934 16:31:11.806625 best dqsien dly found for B1: ( 1, 3, 30)
2935 16:31:11.806713 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2936 16:31:11.806792 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2937 16:31:11.806868
2938 16:31:11.806954 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2939 16:31:11.807033 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2940 16:31:11.807109 [Gating] SW calibration Done
2941 16:31:11.807195 ==
2942 16:31:11.807274 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 16:31:11.807352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 16:31:11.807438 ==
2945 16:31:11.807516 RX Vref Scan: 0
2946 16:31:11.807592
2947 16:31:11.807678 RX Vref 0 -> 0, step: 1
2948 16:31:11.807755
2949 16:31:11.807832 RX Delay -40 -> 252, step: 8
2950 16:31:11.807920 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2951 16:31:11.807999 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2952 16:31:11.808076 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2953 16:31:11.808163 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2954 16:31:11.808242 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2955 16:31:11.808320 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2956 16:31:11.808406 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2957 16:31:11.808485 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2958 16:31:11.808564 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2959 16:31:11.808658 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2960 16:31:11.808745 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2961 16:31:11.808798 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2962 16:31:11.808848 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2963 16:31:11.808896 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2964 16:31:11.808945 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2965 16:31:11.808994 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2966 16:31:11.809042 ==
2967 16:31:11.809091 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 16:31:11.809139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 16:31:11.809188 ==
2970 16:31:11.809237 DQS Delay:
2971 16:31:11.809285 DQS0 = 0, DQS1 = 0
2972 16:31:11.809332 DQM Delay:
2973 16:31:11.809379 DQM0 = 112, DQM1 = 101
2974 16:31:11.926405 DQ Delay:
2975 16:31:11.926551 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2976 16:31:11.926646 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =119
2977 16:31:11.926741 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2978 16:31:11.926827 DQ12 =111, DQ13 =107, DQ14 =111, DQ15 =107
2979 16:31:11.926908
2980 16:31:11.926992
2981 16:31:11.927071 ==
2982 16:31:11.927149 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 16:31:11.927231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 16:31:11.927310 ==
2985 16:31:11.927387
2986 16:31:11.927463
2987 16:31:11.927543 TX Vref Scan disable
2988 16:31:11.927621 == TX Byte 0 ==
2989 16:31:11.927699 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2990 16:31:11.927777 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2991 16:31:11.927832 == TX Byte 1 ==
2992 16:31:11.927882 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2993 16:31:11.927932 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2994 16:31:11.927980 ==
2995 16:31:11.928028 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 16:31:11.928081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 16:31:11.928131 ==
2998 16:31:11.928181 TX Vref=22, minBit 1, minWin=25, winSum=430
2999 16:31:11.928230 TX Vref=24, minBit 0, minWin=27, winSum=435
3000 16:31:11.928279 TX Vref=26, minBit 0, minWin=27, winSum=440
3001 16:31:11.928328 TX Vref=28, minBit 1, minWin=27, winSum=444
3002 16:31:11.928392 TX Vref=30, minBit 1, minWin=27, winSum=441
3003 16:31:11.928470 TX Vref=32, minBit 1, minWin=27, winSum=442
3004 16:31:11.928548 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 28
3005 16:31:11.928625
3006 16:31:11.928697 Final TX Range 1 Vref 28
3007 16:31:11.928747
3008 16:31:11.928795 ==
3009 16:31:11.928843 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 16:31:11.928896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 16:31:11.928946 ==
3012 16:31:11.928994
3013 16:31:11.929042
3014 16:31:11.929090 TX Vref Scan disable
3015 16:31:11.929142 == TX Byte 0 ==
3016 16:31:11.929192 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3017 16:31:11.929240 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3018 16:31:11.929288 == TX Byte 1 ==
3019 16:31:11.929336 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3020 16:31:11.929389 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3021 16:31:11.929438
3022 16:31:11.929485 [DATLAT]
3023 16:31:11.929533 Freq=1200, CH0 RK1
3024 16:31:11.929581
3025 16:31:11.929634 DATLAT Default: 0xd
3026 16:31:11.929684 0, 0xFFFF, sum = 0
3027 16:31:11.929733 1, 0xFFFF, sum = 0
3028 16:31:11.929782 2, 0xFFFF, sum = 0
3029 16:31:11.929831 3, 0xFFFF, sum = 0
3030 16:31:11.929887 4, 0xFFFF, sum = 0
3031 16:31:11.929936 5, 0xFFFF, sum = 0
3032 16:31:11.929986 6, 0xFFFF, sum = 0
3033 16:31:11.930035 7, 0xFFFF, sum = 0
3034 16:31:11.930085 8, 0xFFFF, sum = 0
3035 16:31:11.930164 9, 0xFFFF, sum = 0
3036 16:31:11.930242 10, 0xFFFF, sum = 0
3037 16:31:11.930321 11, 0xFFFF, sum = 0
3038 16:31:11.930404 12, 0x0, sum = 1
3039 16:31:11.930490 13, 0x0, sum = 2
3040 16:31:11.930568 14, 0x0, sum = 3
3041 16:31:11.930651 15, 0x0, sum = 4
3042 16:31:11.930736 best_step = 13
3043 16:31:11.930812
3044 16:31:11.930891 ==
3045 16:31:11.930976 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 16:31:11.931054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 16:31:11.931131 ==
3048 16:31:11.931219 RX Vref Scan: 0
3049 16:31:11.931297
3050 16:31:11.931373 RX Vref 0 -> 0, step: 1
3051 16:31:11.931459
3052 16:31:11.931536 RX Delay -37 -> 252, step: 4
3053 16:31:11.931614 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3054 16:31:11.931703 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3055 16:31:11.931782 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3056 16:31:11.932061 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3057 16:31:11.932155 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3058 16:31:11.932237 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3059 16:31:11.932315 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3060 16:31:11.932400 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3061 16:31:11.932481 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3062 16:31:11.932560 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3063 16:31:11.932642 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3064 16:31:11.932734 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3065 16:31:11.932812 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3066 16:31:11.932893 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3067 16:31:11.932978 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3068 16:31:11.933057 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3069 16:31:11.933141 ==
3070 16:31:11.933223 Dram Type= 6, Freq= 0, CH_0, rank 1
3071 16:31:11.933302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 16:31:11.933386 ==
3073 16:31:11.933474 DQS Delay:
3074 16:31:11.933563 DQS0 = 0, DQS1 = 0
3075 16:31:11.933649 DQM Delay:
3076 16:31:11.933732 DQM0 = 110, DQM1 = 101
3077 16:31:11.933824 DQ Delay:
3078 16:31:11.933884 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3079 16:31:11.933936 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3080 16:31:11.933986 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3081 16:31:11.934040 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3082 16:31:11.934091
3083 16:31:11.934139
3084 16:31:11.934189 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3085 16:31:11.934240 CH0 RK1: MR19=403, MR18=15FD
3086 16:31:11.934306 CH0_RK1: MR19=0x403, MR18=0x15FD, DQSOSC=401, MR23=63, INC=40, DEC=27
3087 16:31:11.934385 [RxdqsGatingPostProcess] freq 1200
3088 16:31:11.934473 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3089 16:31:11.934558 best DQS0 dly(2T, 0.5T) = (0, 11)
3090 16:31:11.934639 best DQS1 dly(2T, 0.5T) = (0, 12)
3091 16:31:11.934717 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3092 16:31:11.934804 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3093 16:31:11.934885 best DQS0 dly(2T, 0.5T) = (0, 11)
3094 16:31:11.934963 best DQS1 dly(2T, 0.5T) = (0, 11)
3095 16:31:11.935044 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3096 16:31:11.935122 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3097 16:31:11.935199 Pre-setting of DQS Precalculation
3098 16:31:11.935281 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3099 16:31:11.935358 ==
3100 16:31:11.935436 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 16:31:11.935517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 16:31:11.935595 ==
3103 16:31:11.935673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3104 16:31:11.935753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3105 16:31:11.935807 [CA 0] Center 37 (7~67) winsize 61
3106 16:31:11.935857 [CA 1] Center 37 (7~68) winsize 62
3107 16:31:11.935907 [CA 2] Center 34 (4~64) winsize 61
3108 16:31:11.935956 [CA 3] Center 34 (4~64) winsize 61
3109 16:31:11.936009 [CA 4] Center 34 (4~64) winsize 61
3110 16:31:11.936060 [CA 5] Center 33 (3~63) winsize 61
3111 16:31:11.936109
3112 16:31:11.936159 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3113 16:31:11.936208
3114 16:31:11.936262 [CATrainingPosCal] consider 1 rank data
3115 16:31:11.936341 u2DelayCellTimex100 = 270/100 ps
3116 16:31:11.936418 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3117 16:31:11.936498 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3118 16:31:11.936578 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3119 16:31:11.936663 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 16:31:11.936745 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3121 16:31:11.936798 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3122 16:31:11.936848
3123 16:31:11.936897 CA PerBit enable=1, Macro0, CA PI delay=33
3124 16:31:11.936946
3125 16:31:11.936998 [CBTSetCACLKResult] CA Dly = 33
3126 16:31:11.937049 CS Dly: 6 (0~37)
3127 16:31:11.937099 ==
3128 16:31:11.937148 Dram Type= 6, Freq= 0, CH_1, rank 1
3129 16:31:11.937197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 16:31:11.937251 ==
3131 16:31:11.937301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3132 16:31:11.937352 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3133 16:31:11.937401 [CA 0] Center 38 (8~68) winsize 61
3134 16:31:11.937451 [CA 1] Center 37 (7~68) winsize 62
3135 16:31:11.937504 [CA 2] Center 34 (4~65) winsize 62
3136 16:31:11.937554 [CA 3] Center 33 (3~64) winsize 62
3137 16:31:11.937603 [CA 4] Center 34 (4~65) winsize 62
3138 16:31:11.937651 [CA 5] Center 32 (2~63) winsize 62
3139 16:31:11.937700
3140 16:31:11.937756 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3141 16:31:11.937834
3142 16:31:11.937911 [CATrainingPosCal] consider 2 rank data
3143 16:31:11.937990 u2DelayCellTimex100 = 270/100 ps
3144 16:31:11.938069 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3145 16:31:11.938148 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3146 16:31:11.938229 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3147 16:31:11.938313 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 16:31:11.938402 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3149 16:31:11.938482 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3150 16:31:11.938561
3151 16:31:11.938638 CA PerBit enable=1, Macro0, CA PI delay=33
3152 16:31:11.938716
3153 16:31:11.938796 [CBTSetCACLKResult] CA Dly = 33
3154 16:31:11.938874 CS Dly: 7 (0~40)
3155 16:31:11.938950
3156 16:31:11.939031 ----->DramcWriteLeveling(PI) begin...
3157 16:31:11.939110 ==
3158 16:31:11.939187 Dram Type= 6, Freq= 0, CH_1, rank 0
3159 16:31:11.939269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 16:31:11.939347 ==
3161 16:31:11.939425 Write leveling (Byte 0): 26 => 26
3162 16:31:11.939505 Write leveling (Byte 1): 28 => 28
3163 16:31:11.939583 DramcWriteLeveling(PI) end<-----
3164 16:31:11.939659
3165 16:31:11.939735 ==
3166 16:31:11.939786 Dram Type= 6, Freq= 0, CH_1, rank 0
3167 16:31:11.939836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3168 16:31:11.939886 ==
3169 16:31:11.939935 [Gating] SW mode calibration
3170 16:31:11.939990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3171 16:31:11.940041 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3172 16:31:11.940090 0 15 0 | B1->B0 | 2e2e 2e2e | 1 0 | (1 1) (1 1)
3173 16:31:11.940139 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 16:31:11.940389 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 16:31:11.940475 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 16:31:11.940555 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 16:31:11.940633 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 16:31:11.940714 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 16:31:11.940766 0 15 28 | B1->B0 | 2c2c 2c2c | 0 0 | (0 0) (0 0)
3180 16:31:11.940816 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3181 16:31:11.940865 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 16:31:11.940913 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 16:31:11.940968 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 16:31:11.941017 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 16:31:11.941066 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 16:31:11.941114 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3187 16:31:11.941163 1 0 28 | B1->B0 | 4040 3f3f | 1 0 | (0 0) (0 0)
3188 16:31:11.941225 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 16:31:11.941308 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 16:31:11.941397 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 16:31:11.941474 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 16:31:11.941558 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 16:31:11.941638 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 16:31:11.941716 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 16:31:11.941798 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3196 16:31:11.941876 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3197 16:31:11.941954 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 16:31:11.942036 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 16:31:11.942114 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 16:31:11.942191 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 16:31:11.942273 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 16:31:11.942351 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 16:31:11.942434 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 16:31:11.942520 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 16:31:11.942599 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 16:31:11.942677 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 16:31:11.942757 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 16:31:11.942836 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 16:31:11.942914 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 16:31:11.942994 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 16:31:11.943079 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3212 16:31:11.943162 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 16:31:11.943247 Total UI for P1: 0, mck2ui 16
3214 16:31:11.943326 best dqsien dly found for B0: ( 1, 3, 28)
3215 16:31:11.943418 Total UI for P1: 0, mck2ui 16
3216 16:31:11.943498 best dqsien dly found for B1: ( 1, 3, 28)
3217 16:31:11.943578 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3218 16:31:11.943656 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3219 16:31:11.943736
3220 16:31:11.943806 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3221 16:31:11.943858 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3222 16:31:11.943909 [Gating] SW calibration Done
3223 16:31:11.943958 ==
3224 16:31:11.944015 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 16:31:11.944066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 16:31:11.944116 ==
3227 16:31:11.944164 RX Vref Scan: 0
3228 16:31:11.944212
3229 16:31:11.944286 RX Vref 0 -> 0, step: 1
3230 16:31:11.944364
3231 16:31:11.944448 RX Delay -40 -> 252, step: 8
3232 16:31:11.944537 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3233 16:31:11.944625 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3234 16:31:11.944695 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3235 16:31:11.944752 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3236 16:31:11.944803 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3237 16:31:11.944852 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3238 16:31:11.944901 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3239 16:31:11.944950 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3240 16:31:11.945008 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3241 16:31:11.945087 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3242 16:31:11.945165 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3243 16:31:11.945244 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3244 16:31:11.945324 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3245 16:31:11.945402 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3246 16:31:11.945479 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3247 16:31:11.945536 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3248 16:31:11.945586 ==
3249 16:31:11.945635 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 16:31:11.945685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 16:31:11.945738 ==
3252 16:31:11.945817 DQS Delay:
3253 16:31:11.945894 DQS0 = 0, DQS1 = 0
3254 16:31:11.945971 DQM Delay:
3255 16:31:11.946050 DQM0 = 115, DQM1 = 106
3256 16:31:11.946127 DQ Delay:
3257 16:31:11.946204 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3258 16:31:11.946285 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3259 16:31:11.946363 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3260 16:31:11.946441 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3261 16:31:11.946520
3262 16:31:11.946597
3263 16:31:11.946672 ==
3264 16:31:11.946753 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 16:31:11.946831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 16:31:11.946909 ==
3267 16:31:11.946987
3268 16:31:11.947064
3269 16:31:11.947140 TX Vref Scan disable
3270 16:31:11.947217 == TX Byte 0 ==
3271 16:31:11.947297 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3272 16:31:11.947376 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3273 16:31:11.947453 == TX Byte 1 ==
3274 16:31:11.947534 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3275 16:31:11.947613 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3276 16:31:11.947696 ==
3277 16:31:11.947786 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 16:31:11.947877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 16:31:11.947957 ==
3280 16:31:11.948016 TX Vref=22, minBit 10, minWin=24, winSum=406
3281 16:31:11.948079 TX Vref=24, minBit 11, minWin=24, winSum=412
3282 16:31:11.948358 TX Vref=26, minBit 10, minWin=24, winSum=418
3283 16:31:11.948443 TX Vref=28, minBit 9, minWin=25, winSum=420
3284 16:31:11.948526 TX Vref=30, minBit 8, minWin=25, winSum=421
3285 16:31:11.948605 TX Vref=32, minBit 9, minWin=24, winSum=424
3286 16:31:11.948686 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 30
3287 16:31:11.948773
3288 16:31:11.948854 Final TX Range 1 Vref 30
3289 16:31:11.948932
3290 16:31:11.948988 ==
3291 16:31:11.949038 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 16:31:11.949088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 16:31:11.949138 ==
3294 16:31:11.949193
3295 16:31:11.949270
3296 16:31:11.949346 TX Vref Scan disable
3297 16:31:11.949425 == TX Byte 0 ==
3298 16:31:11.949504 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3299 16:31:11.949582 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3300 16:31:11.949660 == TX Byte 1 ==
3301 16:31:11.949741 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3302 16:31:11.949819 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3303 16:31:11.949895
3304 16:31:11.949975 [DATLAT]
3305 16:31:11.950052 Freq=1200, CH1 RK0
3306 16:31:11.950130
3307 16:31:11.950210 DATLAT Default: 0xd
3308 16:31:11.950287 0, 0xFFFF, sum = 0
3309 16:31:11.950366 1, 0xFFFF, sum = 0
3310 16:31:11.950449 2, 0xFFFF, sum = 0
3311 16:31:11.950527 3, 0xFFFF, sum = 0
3312 16:31:11.950608 4, 0xFFFF, sum = 0
3313 16:31:11.950688 5, 0xFFFF, sum = 0
3314 16:31:11.950768 6, 0xFFFF, sum = 0
3315 16:31:11.950848 7, 0xFFFF, sum = 0
3316 16:31:11.950929 8, 0xFFFF, sum = 0
3317 16:31:11.951017 9, 0xFFFF, sum = 0
3318 16:31:11.951097 10, 0xFFFF, sum = 0
3319 16:31:11.951191 11, 0xFFFF, sum = 0
3320 16:31:11.951274 12, 0x0, sum = 1
3321 16:31:11.951354 13, 0x0, sum = 2
3322 16:31:11.951437 14, 0x0, sum = 3
3323 16:31:11.951516 15, 0x0, sum = 4
3324 16:31:11.951601 best_step = 13
3325 16:31:11.951687
3326 16:31:11.951765 ==
3327 16:31:11.951835 Dram Type= 6, Freq= 0, CH_1, rank 0
3328 16:31:11.951888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3329 16:31:11.951939 ==
3330 16:31:11.951989 RX Vref Scan: 1
3331 16:31:11.952056
3332 16:31:11.952135 Set Vref Range= 32 -> 127
3333 16:31:11.952211
3334 16:31:11.952287 RX Vref 32 -> 127, step: 1
3335 16:31:11.952366
3336 16:31:11.952442 RX Delay -21 -> 252, step: 4
3337 16:31:11.952519
3338 16:31:11.952599 Set Vref, RX VrefLevel [Byte0]: 32
3339 16:31:11.952682 [Byte1]: 32
3340 16:31:11.952734
3341 16:31:11.952783 Set Vref, RX VrefLevel [Byte0]: 33
3342 16:31:11.952853 [Byte1]: 33
3343 16:31:11.952930
3344 16:31:11.953006 Set Vref, RX VrefLevel [Byte0]: 34
3345 16:31:11.953062 [Byte1]: 34
3346 16:31:11.953142
3347 16:31:11.953218 Set Vref, RX VrefLevel [Byte0]: 35
3348 16:31:11.953298 [Byte1]: 35
3349 16:31:11.953376
3350 16:31:11.953452 Set Vref, RX VrefLevel [Byte0]: 36
3351 16:31:11.953528 [Byte1]: 36
3352 16:31:11.953607
3353 16:31:11.953683 Set Vref, RX VrefLevel [Byte0]: 37
3354 16:31:11.953759 [Byte1]: 37
3355 16:31:11.953838
3356 16:31:11.953915 Set Vref, RX VrefLevel [Byte0]: 38
3357 16:31:11.953992 [Byte1]: 38
3358 16:31:11.954072
3359 16:31:11.954148 Set Vref, RX VrefLevel [Byte0]: 39
3360 16:31:11.954225 [Byte1]: 39
3361 16:31:11.954305
3362 16:31:11.954382 Set Vref, RX VrefLevel [Byte0]: 40
3363 16:31:11.954459 [Byte1]: 40
3364 16:31:11.954537
3365 16:31:11.954614 Set Vref, RX VrefLevel [Byte0]: 41
3366 16:31:11.954691 [Byte1]: 41
3367 16:31:11.954770
3368 16:31:11.954861 Set Vref, RX VrefLevel [Byte0]: 42
3369 16:31:11.954947 [Byte1]: 42
3370 16:31:11.955041
3371 16:31:11.955121 Set Vref, RX VrefLevel [Byte0]: 43
3372 16:31:11.955199 [Byte1]: 43
3373 16:31:11.955284
3374 16:31:11.955365 Set Vref, RX VrefLevel [Byte0]: 44
3375 16:31:11.955480 [Byte1]: 44
3376 16:31:11.955619
3377 16:31:11.955713 Set Vref, RX VrefLevel [Byte0]: 45
3378 16:31:11.955792 [Byte1]: 45
3379 16:31:11.955844
3380 16:31:11.955893 Set Vref, RX VrefLevel [Byte0]: 46
3381 16:31:11.955943 [Byte1]: 46
3382 16:31:11.955991
3383 16:31:11.956071 Set Vref, RX VrefLevel [Byte0]: 47
3384 16:31:11.956148 [Byte1]: 47
3385 16:31:11.956226
3386 16:31:11.956304 Set Vref, RX VrefLevel [Byte0]: 48
3387 16:31:11.956381 [Byte1]: 48
3388 16:31:11.956457
3389 16:31:11.956533 Set Vref, RX VrefLevel [Byte0]: 49
3390 16:31:11.956614 [Byte1]: 49
3391 16:31:11.956686
3392 16:31:11.956737 Set Vref, RX VrefLevel [Byte0]: 50
3393 16:31:11.956789 [Byte1]: 50
3394 16:31:11.956840
3395 16:31:11.956888 Set Vref, RX VrefLevel [Byte0]: 51
3396 16:31:11.956937 [Byte1]: 51
3397 16:31:11.956986
3398 16:31:11.957034 Set Vref, RX VrefLevel [Byte0]: 52
3399 16:31:11.957087 [Byte1]: 52
3400 16:31:11.957164
3401 16:31:11.957241 Set Vref, RX VrefLevel [Byte0]: 53
3402 16:31:11.957318 [Byte1]: 53
3403 16:31:11.957397
3404 16:31:11.957474 Set Vref, RX VrefLevel [Byte0]: 54
3405 16:31:11.957551 [Byte1]: 54
3406 16:31:11.957626
3407 16:31:11.957705 Set Vref, RX VrefLevel [Byte0]: 55
3408 16:31:11.957783 [Byte1]: 55
3409 16:31:11.957858
3410 16:31:11.957935 Set Vref, RX VrefLevel [Byte0]: 56
3411 16:31:11.958011 [Byte1]: 56
3412 16:31:11.958092
3413 16:31:11.958173 Set Vref, RX VrefLevel [Byte0]: 57
3414 16:31:11.958260 [Byte1]: 57
3415 16:31:11.958347
3416 16:31:11.958430 Set Vref, RX VrefLevel [Byte0]: 58
3417 16:31:11.958510 [Byte1]: 58
3418 16:31:11.958587
3419 16:31:11.958664 Set Vref, RX VrefLevel [Byte0]: 59
3420 16:31:11.958743 [Byte1]: 59
3421 16:31:11.958820
3422 16:31:11.958897 Set Vref, RX VrefLevel [Byte0]: 60
3423 16:31:11.958973 [Byte1]: 60
3424 16:31:11.959052
3425 16:31:11.959128 Set Vref, RX VrefLevel [Byte0]: 61
3426 16:31:11.959206 [Byte1]: 61
3427 16:31:11.959285
3428 16:31:11.959361 Set Vref, RX VrefLevel [Byte0]: 62
3429 16:31:11.959438 [Byte1]: 62
3430 16:31:11.959517
3431 16:31:11.959594 Set Vref, RX VrefLevel [Byte0]: 63
3432 16:31:11.959670 [Byte1]: 63
3433 16:31:11.959747
3434 16:31:11.959798 Set Vref, RX VrefLevel [Byte0]: 64
3435 16:31:11.959847 [Byte1]: 64
3436 16:31:11.959895
3437 16:31:11.959943 Set Vref, RX VrefLevel [Byte0]: 65
3438 16:31:11.960009 [Byte1]: 65
3439 16:31:11.960085
3440 16:31:11.960161 Set Vref, RX VrefLevel [Byte0]: 66
3441 16:31:11.960241 [Byte1]: 66
3442 16:31:11.960318
3443 16:31:11.960393 Set Vref, RX VrefLevel [Byte0]: 67
3444 16:31:11.960473 [Byte1]: 67
3445 16:31:11.960550
3446 16:31:11.960627 Final RX Vref Byte 0 = 58 to rank0
3447 16:31:11.960703 Final RX Vref Byte 1 = 49 to rank0
3448 16:31:11.960755 Final RX Vref Byte 0 = 58 to rank1
3449 16:31:11.961056 Final RX Vref Byte 1 = 49 to rank1==
3450 16:31:11.961181 Dram Type= 6, Freq= 0, CH_1, rank 0
3451 16:31:11.961278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 16:31:11.961335 ==
3453 16:31:11.961396 DQS Delay:
3454 16:31:11.961480 DQS0 = 0, DQS1 = 0
3455 16:31:11.961559 DQM Delay:
3456 16:31:11.961640 DQM0 = 114, DQM1 = 105
3457 16:31:11.961717 DQ Delay:
3458 16:31:11.961795 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =112
3459 16:31:11.961876 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =112
3460 16:31:11.961954 DQ8 =92, DQ9 =96, DQ10 =106, DQ11 =100
3461 16:31:11.962031 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =112
3462 16:31:11.962109
3463 16:31:11.962187
3464 16:31:11.962265 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3465 16:31:11.962342 CH1 RK0: MR19=303, MR18=F0F7
3466 16:31:11.962422 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3467 16:31:11.962499
3468 16:31:11.962575 ----->DramcWriteLeveling(PI) begin...
3469 16:31:11.962657 ==
3470 16:31:11.962734 Dram Type= 6, Freq= 0, CH_1, rank 1
3471 16:31:11.962811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3472 16:31:11.962891 ==
3473 16:31:11.962968 Write leveling (Byte 0): 26 => 26
3474 16:31:11.963045 Write leveling (Byte 1): 28 => 28
3475 16:31:11.963124 DramcWriteLeveling(PI) end<-----
3476 16:31:11.963201
3477 16:31:11.963276 ==
3478 16:31:11.963352 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 16:31:11.963433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 16:31:11.963509 ==
3481 16:31:11.963586 [Gating] SW mode calibration
3482 16:31:11.963667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3483 16:31:11.963746 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3484 16:31:11.963824 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3485 16:31:11.963904 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 16:31:11.963982 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 16:31:11.964059 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 16:31:11.964139 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 16:31:11.964217 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3490 16:31:11.964294 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
3491 16:31:11.964373 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3492 16:31:11.964451 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 16:31:11.964528 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 16:31:11.964610 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 16:31:11.964707 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 16:31:11.964796 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 16:31:11.964876 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3498 16:31:11.964928 1 0 24 | B1->B0 | 2e2d 4646 | 1 0 | (1 1) (0 0)
3499 16:31:11.964977 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 16:31:11.965026 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 16:31:11.965075 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 16:31:11.965128 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 16:31:11.965178 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 16:31:11.965226 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 16:31:11.965274 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 16:31:11.965322 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3507 16:31:11.965374 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 16:31:11.965424 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 16:31:11.965472 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 16:31:11.965521 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 16:31:11.965569 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 16:31:11.965621 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 16:31:11.965671 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 16:31:11.965719 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 16:31:11.965768 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 16:31:11.965815 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 16:31:11.965868 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 16:31:11.965917 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 16:31:11.965966 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 16:31:11.966014 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 16:31:11.966062 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3522 16:31:11.966114 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3523 16:31:11.966192 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3524 16:31:11.966269 Total UI for P1: 0, mck2ui 16
3525 16:31:11.966347 best dqsien dly found for B0: ( 1, 3, 22)
3526 16:31:11.966428 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 16:31:11.966505 Total UI for P1: 0, mck2ui 16
3528 16:31:11.966587 best dqsien dly found for B1: ( 1, 3, 26)
3529 16:31:11.966669 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3530 16:31:11.966748 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3531 16:31:11.966824
3532 16:31:11.966904 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3533 16:31:11.966982 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3534 16:31:11.967058 [Gating] SW calibration Done
3535 16:31:11.967138 ==
3536 16:31:11.967215 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 16:31:11.967292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 16:31:11.967373 ==
3539 16:31:11.967449 RX Vref Scan: 0
3540 16:31:11.967525
3541 16:31:11.967607 RX Vref 0 -> 0, step: 1
3542 16:31:11.967684
3543 16:31:11.967760 RX Delay -40 -> 252, step: 8
3544 16:31:11.967817 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3545 16:31:11.967867 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3546 16:31:11.967924 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3547 16:31:11.968011 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3548 16:31:11.968100 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3549 16:31:11.968189 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3550 16:31:11.968270 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3551 16:31:11.968348 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3552 16:31:11.968426 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3553 16:31:11.968695 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3554 16:31:11.968761 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3555 16:31:11.968812 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3556 16:31:11.968862 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3557 16:31:11.968911 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3558 16:31:11.968960 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3559 16:31:11.969015 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3560 16:31:11.969064 ==
3561 16:31:11.969113 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 16:31:11.969162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 16:31:11.969211 ==
3564 16:31:11.969266 DQS Delay:
3565 16:31:11.969315 DQS0 = 0, DQS1 = 0
3566 16:31:11.969364 DQM Delay:
3567 16:31:11.969412 DQM0 = 110, DQM1 = 105
3568 16:31:11.969495 DQ Delay:
3569 16:31:11.969578 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3570 16:31:11.969664 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3571 16:31:11.969742 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =95
3572 16:31:11.969825 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3573 16:31:11.969910
3574 16:31:11.969991
3575 16:31:11.970071 ==
3576 16:31:11.970155 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 16:31:11.970240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 16:31:11.970329 ==
3579 16:31:11.970410
3580 16:31:11.970491
3581 16:31:11.970577 TX Vref Scan disable
3582 16:31:11.970660 == TX Byte 0 ==
3583 16:31:11.970748 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3584 16:31:11.970828 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3585 16:31:11.970909 == TX Byte 1 ==
3586 16:31:11.970988 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3587 16:31:11.971075 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3588 16:31:11.971161 ==
3589 16:31:11.971254 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 16:31:11.971333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 16:31:11.971410 ==
3592 16:31:11.971493 TX Vref=22, minBit 9, minWin=25, winSum=420
3593 16:31:11.971573 TX Vref=24, minBit 1, minWin=26, winSum=427
3594 16:31:11.971651 TX Vref=26, minBit 8, minWin=26, winSum=435
3595 16:31:11.971729 TX Vref=28, minBit 8, minWin=26, winSum=436
3596 16:31:11.971781 TX Vref=30, minBit 8, minWin=25, winSum=436
3597 16:31:11.971831 TX Vref=32, minBit 8, minWin=25, winSum=434
3598 16:31:11.971880 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 28
3599 16:31:11.971929
3600 16:31:11.971977 Final TX Range 1 Vref 28
3601 16:31:11.972031
3602 16:31:11.972080 ==
3603 16:31:11.972128 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 16:31:11.972176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 16:31:11.972225 ==
3606 16:31:11.972304
3607 16:31:11.972379
3608 16:31:11.972455 TX Vref Scan disable
3609 16:31:11.972534 == TX Byte 0 ==
3610 16:31:11.972612 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3611 16:31:11.972715 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3612 16:31:11.972796 == TX Byte 1 ==
3613 16:31:11.972874 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3614 16:31:11.972951 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3615 16:31:11.973030
3616 16:31:11.973107 [DATLAT]
3617 16:31:11.973183 Freq=1200, CH1 RK1
3618 16:31:11.973262
3619 16:31:11.973339 DATLAT Default: 0xd
3620 16:31:11.973415 0, 0xFFFF, sum = 0
3621 16:31:11.973496 1, 0xFFFF, sum = 0
3622 16:31:11.973575 2, 0xFFFF, sum = 0
3623 16:31:11.973654 3, 0xFFFF, sum = 0
3624 16:31:11.973734 4, 0xFFFF, sum = 0
3625 16:31:11.973813 5, 0xFFFF, sum = 0
3626 16:31:11.973891 6, 0xFFFF, sum = 0
3627 16:31:11.973970 7, 0xFFFF, sum = 0
3628 16:31:11.974051 8, 0xFFFF, sum = 0
3629 16:31:11.974129 9, 0xFFFF, sum = 0
3630 16:31:11.974213 10, 0xFFFF, sum = 0
3631 16:31:11.974307 11, 0xFFFF, sum = 0
3632 16:31:11.974391 12, 0x0, sum = 1
3633 16:31:11.974472 13, 0x0, sum = 2
3634 16:31:11.974552 14, 0x0, sum = 3
3635 16:31:11.974631 15, 0x0, sum = 4
3636 16:31:11.974710 best_step = 13
3637 16:31:11.974791
3638 16:31:11.974869 ==
3639 16:31:11.974946 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 16:31:11.975024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 16:31:11.975106 ==
3642 16:31:11.975185 RX Vref Scan: 0
3643 16:31:11.975265
3644 16:31:11.975342 RX Vref 0 -> 0, step: 1
3645 16:31:11.975418
3646 16:31:11.975497 RX Delay -21 -> 252, step: 4
3647 16:31:11.975574 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3648 16:31:11.975652 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3649 16:31:11.975725 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3650 16:31:11.975776 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3651 16:31:11.975825 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3652 16:31:11.975873 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3653 16:31:11.975921 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3654 16:31:11.975977 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3655 16:31:11.976026 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3656 16:31:11.976074 iDelay=195, Bit 9, Center 104 (39 ~ 170) 132
3657 16:31:11.976123 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3658 16:31:11.976171 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3659 16:31:11.976220 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3660 16:31:11.976296 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3661 16:31:11.976373 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3662 16:31:11.976450 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3663 16:31:11.976526 ==
3664 16:31:11.976607 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 16:31:11.976681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 16:31:11.976732 ==
3667 16:31:11.976781 DQS Delay:
3668 16:31:11.976835 DQS0 = 0, DQS1 = 0
3669 16:31:11.976885 DQM Delay:
3670 16:31:11.976933 DQM0 = 111, DQM1 = 109
3671 16:31:11.976981 DQ Delay:
3672 16:31:11.977028 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3673 16:31:11.977077 DQ4 =110, DQ5 =120, DQ6 =120, DQ7 =110
3674 16:31:11.977129 DQ8 =94, DQ9 =104, DQ10 =112, DQ11 =106
3675 16:31:11.977179 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =116
3676 16:31:11.977227
3677 16:31:11.977274
3678 16:31:11.977322 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe0e, (MSB)MR19= 0x304, tDQSOscB0 = 404 ps tDQSOscB1 = 410 ps
3679 16:31:11.977372 CH1 RK1: MR19=304, MR18=FE0E
3680 16:31:11.977426 CH1_RK1: MR19=0x304, MR18=0xFE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
3681 16:31:11.977475 [RxdqsGatingPostProcess] freq 1200
3682 16:31:11.977524 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3683 16:31:11.977572 best DQS0 dly(2T, 0.5T) = (0, 11)
3684 16:31:11.977620 best DQS1 dly(2T, 0.5T) = (0, 11)
3685 16:31:11.977672 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3686 16:31:11.977722 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3687 16:31:11.977771 best DQS0 dly(2T, 0.5T) = (0, 11)
3688 16:31:11.977819 best DQS1 dly(2T, 0.5T) = (0, 11)
3689 16:31:11.977867 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3690 16:31:11.977921 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3691 16:31:11.977999 Pre-setting of DQS Precalculation
3692 16:31:11.978279 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3693 16:31:11.978367 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3694 16:31:11.978451 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3695 16:31:11.978529
3696 16:31:11.978605
3697 16:31:11.978686 [Calibration Summary] 2400 Mbps
3698 16:31:11.978769 CH 0, Rank 0
3699 16:31:11.978846 SW Impedance : PASS
3700 16:31:11.978926 DUTY Scan : NO K
3701 16:31:11.979001 ZQ Calibration : PASS
3702 16:31:11.979082 Jitter Meter : NO K
3703 16:31:11.979163 CBT Training : PASS
3704 16:31:11.979240 Write leveling : PASS
3705 16:31:11.979317 RX DQS gating : PASS
3706 16:31:11.979397 RX DQ/DQS(RDDQC) : PASS
3707 16:31:11.979474 TX DQ/DQS : PASS
3708 16:31:11.979551 RX DATLAT : PASS
3709 16:31:11.979636 RX DQ/DQS(Engine): PASS
3710 16:31:11.979711 TX OE : NO K
3711 16:31:11.979762 All Pass.
3712 16:31:11.979811
3713 16:31:11.979859 CH 0, Rank 1
3714 16:31:11.979920 SW Impedance : PASS
3715 16:31:11.979972 DUTY Scan : NO K
3716 16:31:11.980021 ZQ Calibration : PASS
3717 16:31:11.980070 Jitter Meter : NO K
3718 16:31:11.980118 CBT Training : PASS
3719 16:31:11.980185 Write leveling : PASS
3720 16:31:11.980237 RX DQS gating : PASS
3721 16:31:11.980286 RX DQ/DQS(RDDQC) : PASS
3722 16:31:11.980334 TX DQ/DQS : PASS
3723 16:31:11.980383 RX DATLAT : PASS
3724 16:31:11.980470 RX DQ/DQS(Engine): PASS
3725 16:31:11.980554 TX OE : NO K
3726 16:31:11.980632 All Pass.
3727 16:31:11.980717
3728 16:31:11.980808 CH 1, Rank 0
3729 16:31:11.980885 SW Impedance : PASS
3730 16:31:11.980952 DUTY Scan : NO K
3731 16:31:11.981002 ZQ Calibration : PASS
3732 16:31:11.981051 Jitter Meter : NO K
3733 16:31:11.981100 CBT Training : PASS
3734 16:31:11.981171 Write leveling : PASS
3735 16:31:11.981223 RX DQS gating : PASS
3736 16:31:11.981278 RX DQ/DQS(RDDQC) : PASS
3737 16:31:11.981364 TX DQ/DQS : PASS
3738 16:31:11.981454 RX DATLAT : PASS
3739 16:31:11.981542 RX DQ/DQS(Engine): PASS
3740 16:31:11.981622 TX OE : NO K
3741 16:31:11.981700 All Pass.
3742 16:31:11.981776
3743 16:31:11.981852 CH 1, Rank 1
3744 16:31:11.981935 SW Impedance : PASS
3745 16:31:11.982014 DUTY Scan : NO K
3746 16:31:11.982090 ZQ Calibration : PASS
3747 16:31:11.982169 Jitter Meter : NO K
3748 16:31:11.982246 CBT Training : PASS
3749 16:31:11.982322 Write leveling : PASS
3750 16:31:11.982402 RX DQS gating : PASS
3751 16:31:11.982478 RX DQ/DQS(RDDQC) : PASS
3752 16:31:11.982554 TX DQ/DQS : PASS
3753 16:31:11.982633 RX DATLAT : PASS
3754 16:31:11.982710 RX DQ/DQS(Engine): PASS
3755 16:31:11.982786 TX OE : NO K
3756 16:31:11.982866 All Pass.
3757 16:31:11.982942
3758 16:31:11.983017 DramC Write-DBI off
3759 16:31:11.983097 PER_BANK_REFRESH: Hybrid Mode
3760 16:31:11.983177 TX_TRACKING: ON
3761 16:31:11.983256 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3762 16:31:11.983342 [FAST_K] Save calibration result to emmc
3763 16:31:11.983421 dramc_set_vcore_voltage set vcore to 650000
3764 16:31:11.983497 Read voltage for 600, 5
3765 16:31:11.983573 Vio18 = 0
3766 16:31:11.983656 Vcore = 650000
3767 16:31:11.983733 Vdram = 0
3768 16:31:11.983798 Vddq = 0
3769 16:31:11.983848 Vmddr = 0
3770 16:31:11.983897 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3771 16:31:11.983947 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3772 16:31:11.984000 MEM_TYPE=3, freq_sel=19
3773 16:31:11.984051 sv_algorithm_assistance_LP4_1600
3774 16:31:11.984100 ============ PULL DRAM RESETB DOWN ============
3775 16:31:11.984150 ========== PULL DRAM RESETB DOWN end =========
3776 16:31:11.984201 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3777 16:31:11.984270 ===================================
3778 16:31:11.984347 LPDDR4 DRAM CONFIGURATION
3779 16:31:11.984424 ===================================
3780 16:31:11.984508 EX_ROW_EN[0] = 0x0
3781 16:31:11.984597 EX_ROW_EN[1] = 0x0
3782 16:31:11.984692 LP4Y_EN = 0x0
3783 16:31:11.984771 WORK_FSP = 0x0
3784 16:31:11.984856 WL = 0x2
3785 16:31:11.984947 RL = 0x2
3786 16:31:11.985047 BL = 0x2
3787 16:31:11.985128 RPST = 0x0
3788 16:31:11.985205 RD_PRE = 0x0
3789 16:31:11.985292 WR_PRE = 0x1
3790 16:31:11.985373 WR_PST = 0x0
3791 16:31:11.985456 DBI_WR = 0x0
3792 16:31:11.985548 DBI_RD = 0x0
3793 16:31:11.985628 OTF = 0x1
3794 16:31:11.985710 ===================================
3795 16:31:11.985793 ===================================
3796 16:31:11.985870 ANA top config
3797 16:31:11.985953 ===================================
3798 16:31:11.986034 DLL_ASYNC_EN = 0
3799 16:31:11.986111 ALL_SLAVE_EN = 1
3800 16:31:11.986190 NEW_RANK_MODE = 1
3801 16:31:11.986275 DLL_IDLE_MODE = 1
3802 16:31:11.986352 LP45_APHY_COMB_EN = 1
3803 16:31:11.986430 TX_ODT_DIS = 1
3804 16:31:11.986515 NEW_8X_MODE = 1
3805 16:31:11.986594 ===================================
3806 16:31:11.986674 ===================================
3807 16:31:11.986758 data_rate = 1200
3808 16:31:11.986835 CKR = 1
3809 16:31:11.986917 DQ_P2S_RATIO = 8
3810 16:31:11.986999 ===================================
3811 16:31:11.987077 CA_P2S_RATIO = 8
3812 16:31:11.987159 DQ_CA_OPEN = 0
3813 16:31:11.987242 DQ_SEMI_OPEN = 0
3814 16:31:11.987319 CA_SEMI_OPEN = 0
3815 16:31:11.987397 CA_FULL_RATE = 0
3816 16:31:11.987473 DQ_CKDIV4_EN = 1
3817 16:31:11.987555 CA_CKDIV4_EN = 1
3818 16:31:11.987634 CA_PREDIV_EN = 0
3819 16:31:11.987714 PH8_DLY = 0
3820 16:31:11.987788 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3821 16:31:11.987839 DQ_AAMCK_DIV = 4
3822 16:31:11.987907 CA_AAMCK_DIV = 4
3823 16:31:11.987962 CA_ADMCK_DIV = 4
3824 16:31:11.988011 DQ_TRACK_CA_EN = 0
3825 16:31:11.988060 CA_PICK = 600
3826 16:31:11.988113 CA_MCKIO = 600
3827 16:31:11.988200 MCKIO_SEMI = 0
3828 16:31:11.988281 PLL_FREQ = 2288
3829 16:31:11.988365 DQ_UI_PI_RATIO = 32
3830 16:31:11.988449 CA_UI_PI_RATIO = 0
3831 16:31:11.988526 ===================================
3832 16:31:11.988610 ===================================
3833 16:31:11.988700 memory_type:LPDDR4
3834 16:31:11.988777 GP_NUM : 10
3835 16:31:11.988861 SRAM_EN : 1
3836 16:31:11.988945 MD32_EN : 0
3837 16:31:11.989037 ===================================
3838 16:31:11.989119 [ANA_INIT] >>>>>>>>>>>>>>
3839 16:31:11.989196 <<<<<< [CONFIGURE PHASE]: ANA_TX
3840 16:31:11.989479 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3841 16:31:11.989569 ===================================
3842 16:31:11.989648 data_rate = 1200,PCW = 0X5800
3843 16:31:11.989729 ===================================
3844 16:31:11.989814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3845 16:31:11.989893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 16:31:11.989972 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3847 16:31:11.990060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3848 16:31:11.990138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3849 16:31:11.990215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3850 16:31:11.990303 [ANA_INIT] flow start
3851 16:31:11.990381 [ANA_INIT] PLL >>>>>>>>
3852 16:31:11.990457 [ANA_INIT] PLL <<<<<<<<
3853 16:31:11.990544 [ANA_INIT] MIDPI >>>>>>>>
3854 16:31:11.990622 [ANA_INIT] MIDPI <<<<<<<<
3855 16:31:11.990698 [ANA_INIT] DLL >>>>>>>>
3856 16:31:11.990787 [ANA_INIT] flow end
3857 16:31:11.990866 ============ LP4 DIFF to SE enter ============
3858 16:31:11.990944 ============ LP4 DIFF to SE exit ============
3859 16:31:11.991031 [ANA_INIT] <<<<<<<<<<<<<
3860 16:31:11.991111 [Flow] Enable top DCM control >>>>>
3861 16:31:11.991193 [Flow] Enable top DCM control <<<<<
3862 16:31:11.991282 Enable DLL master slave shuffle
3863 16:31:11.991360 ==============================================================
3864 16:31:11.991438 Gating Mode config
3865 16:31:11.991529 ==============================================================
3866 16:31:11.991610 Config description:
3867 16:31:11.991689 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3868 16:31:11.991772 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3869 16:31:11.991826 SELPH_MODE 0: By rank 1: By Phase
3870 16:31:11.991876 ==============================================================
3871 16:31:11.991925 GAT_TRACK_EN = 1
3872 16:31:11.991981 RX_GATING_MODE = 2
3873 16:31:11.992064 RX_GATING_TRACK_MODE = 2
3874 16:31:11.992142 SELPH_MODE = 1
3875 16:31:11.992224 PICG_EARLY_EN = 1
3876 16:31:11.992306 VALID_LAT_VALUE = 1
3877 16:31:11.992384 ==============================================================
3878 16:31:11.992462 Enter into Gating configuration >>>>
3879 16:31:11.992549 Exit from Gating configuration <<<<
3880 16:31:11.992627 Enter into DVFS_PRE_config >>>>>
3881 16:31:11.992696 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3882 16:31:11.992771 Exit from DVFS_PRE_config <<<<<
3883 16:31:11.992855 Enter into PICG configuration >>>>
3884 16:31:11.993369 Exit from PICG configuration <<<<
3885 16:31:11.993466 [RX_INPUT] configuration >>>>>
3886 16:31:11.996738 [RX_INPUT] configuration <<<<<
3887 16:31:12.003270 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3888 16:31:12.010005 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3889 16:31:12.013412 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3890 16:31:12.020256 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3891 16:31:12.026655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3892 16:31:12.033492 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3893 16:31:12.036403 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3894 16:31:12.039766 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3895 16:31:12.046474 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3896 16:31:12.049564 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3897 16:31:12.053195 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3898 16:31:12.059717 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3899 16:31:12.062965 ===================================
3900 16:31:12.063090 LPDDR4 DRAM CONFIGURATION
3901 16:31:12.066315 ===================================
3902 16:31:12.069648 EX_ROW_EN[0] = 0x0
3903 16:31:12.069771 EX_ROW_EN[1] = 0x0
3904 16:31:12.072915 LP4Y_EN = 0x0
3905 16:31:12.076181 WORK_FSP = 0x0
3906 16:31:12.076280 WL = 0x2
3907 16:31:12.079242 RL = 0x2
3908 16:31:12.079317 BL = 0x2
3909 16:31:12.083090 RPST = 0x0
3910 16:31:12.083181 RD_PRE = 0x0
3911 16:31:12.086326 WR_PRE = 0x1
3912 16:31:12.086399 WR_PST = 0x0
3913 16:31:12.089552 DBI_WR = 0x0
3914 16:31:12.089631 DBI_RD = 0x0
3915 16:31:12.092783 OTF = 0x1
3916 16:31:12.096037 ===================================
3917 16:31:12.099228 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3918 16:31:12.102450 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3919 16:31:12.109097 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3920 16:31:12.112883 ===================================
3921 16:31:12.112968 LPDDR4 DRAM CONFIGURATION
3922 16:31:12.115920 ===================================
3923 16:31:12.118774 EX_ROW_EN[0] = 0x10
3924 16:31:12.122481 EX_ROW_EN[1] = 0x0
3925 16:31:12.122561 LP4Y_EN = 0x0
3926 16:31:12.125503 WORK_FSP = 0x0
3927 16:31:12.125595 WL = 0x2
3928 16:31:12.128750 RL = 0x2
3929 16:31:12.128848 BL = 0x2
3930 16:31:12.131983 RPST = 0x0
3931 16:31:12.132059 RD_PRE = 0x0
3932 16:31:12.135270 WR_PRE = 0x1
3933 16:31:12.135352 WR_PST = 0x0
3934 16:31:12.138920 DBI_WR = 0x0
3935 16:31:12.139023 DBI_RD = 0x0
3936 16:31:12.142004 OTF = 0x1
3937 16:31:12.145190 ===================================
3938 16:31:12.151717 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3939 16:31:12.155388 nWR fixed to 30
3940 16:31:12.155510 [ModeRegInit_LP4] CH0 RK0
3941 16:31:12.158315 [ModeRegInit_LP4] CH0 RK1
3942 16:31:12.161659 [ModeRegInit_LP4] CH1 RK0
3943 16:31:12.165259 [ModeRegInit_LP4] CH1 RK1
3944 16:31:12.165347 match AC timing 17
3945 16:31:12.171592 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3946 16:31:12.174955 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3947 16:31:12.178290 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3948 16:31:12.185216 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3949 16:31:12.188375 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3950 16:31:12.188484 ==
3951 16:31:12.191689 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 16:31:12.194726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 16:31:12.194827 ==
3954 16:31:12.201151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3955 16:31:12.208236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3956 16:31:12.211503 [CA 0] Center 37 (7~67) winsize 61
3957 16:31:12.214748 [CA 1] Center 37 (7~67) winsize 61
3958 16:31:12.217946 [CA 2] Center 35 (5~65) winsize 61
3959 16:31:12.221081 [CA 3] Center 35 (5~65) winsize 61
3960 16:31:12.224963 [CA 4] Center 34 (4~65) winsize 62
3961 16:31:12.227828 [CA 5] Center 34 (4~64) winsize 61
3962 16:31:12.227899
3963 16:31:12.230991 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3964 16:31:12.231088
3965 16:31:12.234416 [CATrainingPosCal] consider 1 rank data
3966 16:31:12.237625 u2DelayCellTimex100 = 270/100 ps
3967 16:31:12.241404 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3968 16:31:12.244500 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3969 16:31:12.273415 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3970 16:31:12.273560 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3971 16:31:12.273651 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3972 16:31:12.273746 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3973 16:31:12.273830
3974 16:31:12.273913 CA PerBit enable=1, Macro0, CA PI delay=34
3975 16:31:12.274006
3976 16:31:12.274087 [CBTSetCACLKResult] CA Dly = 34
3977 16:31:12.274174 CS Dly: 5 (0~36)
3978 16:31:12.274268 ==
3979 16:31:12.274350 Dram Type= 6, Freq= 0, CH_0, rank 1
3980 16:31:12.274462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 16:31:12.277470 ==
3982 16:31:12.280559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3983 16:31:12.286960 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3984 16:31:12.290829 [CA 0] Center 37 (7~67) winsize 61
3985 16:31:12.294076 [CA 1] Center 36 (6~67) winsize 62
3986 16:31:12.297404 [CA 2] Center 35 (5~65) winsize 61
3987 16:31:12.300686 [CA 3] Center 35 (5~65) winsize 61
3988 16:31:12.303976 [CA 4] Center 34 (3~65) winsize 63
3989 16:31:12.307134 [CA 5] Center 33 (3~64) winsize 62
3990 16:31:12.307243
3991 16:31:12.310418 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3992 16:31:12.310543
3993 16:31:12.313612 [CATrainingPosCal] consider 2 rank data
3994 16:31:12.316921 u2DelayCellTimex100 = 270/100 ps
3995 16:31:12.320336 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3996 16:31:12.323534 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3997 16:31:12.326936 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3998 16:31:12.333789 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3999 16:31:12.337008 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4000 16:31:12.340112 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4001 16:31:12.340185
4002 16:31:12.343130 CA PerBit enable=1, Macro0, CA PI delay=34
4003 16:31:12.343233
4004 16:31:12.346991 [CBTSetCACLKResult] CA Dly = 34
4005 16:31:12.347090 CS Dly: 5 (0~37)
4006 16:31:12.347184
4007 16:31:12.350106 ----->DramcWriteLeveling(PI) begin...
4008 16:31:12.353337 ==
4009 16:31:12.353422 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 16:31:12.359807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 16:31:12.359904 ==
4012 16:31:12.362997 Write leveling (Byte 0): 33 => 33
4013 16:31:12.366174 Write leveling (Byte 1): 31 => 31
4014 16:31:12.370124 DramcWriteLeveling(PI) end<-----
4015 16:31:12.370218
4016 16:31:12.370312 ==
4017 16:31:12.373339 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 16:31:12.376545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 16:31:12.376648 ==
4020 16:31:12.379578 [Gating] SW mode calibration
4021 16:31:12.386258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4022 16:31:12.392709 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4023 16:31:12.396233 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 16:31:12.399210 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 16:31:12.405897 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 16:31:12.409688 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4027 16:31:12.412902 0 9 16 | B1->B0 | 3232 2e2e | 0 0 | (0 1) (0 0)
4028 16:31:12.419300 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 16:31:12.422667 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 16:31:12.425744 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 16:31:12.432245 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 16:31:12.436097 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 16:31:12.439264 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 16:31:12.442536 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (1 1)
4035 16:31:12.448788 0 10 16 | B1->B0 | 3131 3939 | 0 0 | (0 0) (0 0)
4036 16:31:12.452456 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 16:31:12.458675 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 16:31:12.461906 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 16:31:12.465162 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 16:31:12.472054 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 16:31:12.475271 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 16:31:12.478602 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4043 16:31:12.481892 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 16:31:12.488365 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 16:31:12.491658 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 16:31:12.494905 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 16:31:12.501639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 16:31:12.505209 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 16:31:12.508482 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 16:31:12.515296 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 16:31:12.518199 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 16:31:12.521303 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 16:31:12.528449 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 16:31:12.531714 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 16:31:12.535023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 16:31:12.541409 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 16:31:12.544811 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 16:31:12.548090 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 16:31:12.554534 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4060 16:31:12.558140 Total UI for P1: 0, mck2ui 16
4061 16:31:12.561147 best dqsien dly found for B0: ( 0, 13, 14)
4062 16:31:12.564723 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 16:31:12.567756 Total UI for P1: 0, mck2ui 16
4064 16:31:12.570996 best dqsien dly found for B1: ( 0, 13, 16)
4065 16:31:12.574889 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4066 16:31:12.577475 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4067 16:31:12.577551
4068 16:31:12.581449 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4069 16:31:12.587930 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4070 16:31:12.588015 [Gating] SW calibration Done
4071 16:31:12.588077 ==
4072 16:31:12.591271 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 16:31:12.597791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 16:31:12.597875 ==
4075 16:31:12.597958 RX Vref Scan: 0
4076 16:31:12.598019
4077 16:31:12.601081 RX Vref 0 -> 0, step: 1
4078 16:31:12.601156
4079 16:31:12.604436 RX Delay -230 -> 252, step: 16
4080 16:31:12.607700 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4081 16:31:12.610986 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4082 16:31:12.617161 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4083 16:31:12.620775 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4084 16:31:12.624372 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4085 16:31:12.627331 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4086 16:31:12.630682 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4087 16:31:12.637277 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4088 16:31:12.640330 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4089 16:31:12.644173 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4090 16:31:12.646940 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4091 16:31:12.653974 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4092 16:31:12.657223 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4093 16:31:12.660514 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4094 16:31:12.663799 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4095 16:31:12.670701 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4096 16:31:12.670818 ==
4097 16:31:12.673590 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 16:31:12.677179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 16:31:12.677262 ==
4100 16:31:12.677325 DQS Delay:
4101 16:31:12.680241 DQS0 = 0, DQS1 = 0
4102 16:31:12.680336 DQM Delay:
4103 16:31:12.683240 DQM0 = 37, DQM1 = 29
4104 16:31:12.683312 DQ Delay:
4105 16:31:12.686463 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4106 16:31:12.690428 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4107 16:31:12.693683 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4108 16:31:12.696863 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4109 16:31:12.696967
4110 16:31:12.697069
4111 16:31:12.697153 ==
4112 16:31:12.700261 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 16:31:12.703344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 16:31:12.703443 ==
4115 16:31:12.706568
4116 16:31:12.706664
4117 16:31:12.706750 TX Vref Scan disable
4118 16:31:12.710014 == TX Byte 0 ==
4119 16:31:12.713255 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4120 16:31:12.716400 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4121 16:31:12.720222 == TX Byte 1 ==
4122 16:31:12.723473 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4123 16:31:12.726618 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4124 16:31:12.726719 ==
4125 16:31:12.729942 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 16:31:12.736580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 16:31:12.736707 ==
4128 16:31:12.736791
4129 16:31:12.736867
4130 16:31:12.736923 TX Vref Scan disable
4131 16:31:12.741476 == TX Byte 0 ==
4132 16:31:12.744547 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4133 16:31:12.751238 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4134 16:31:12.751338 == TX Byte 1 ==
4135 16:31:12.754906 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4136 16:31:12.761409 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4137 16:31:12.761506
4138 16:31:12.761591 [DATLAT]
4139 16:31:12.761674 Freq=600, CH0 RK0
4140 16:31:12.761761
4141 16:31:12.764611 DATLAT Default: 0x9
4142 16:31:12.764709 0, 0xFFFF, sum = 0
4143 16:31:12.767883 1, 0xFFFF, sum = 0
4144 16:31:12.767952 2, 0xFFFF, sum = 0
4145 16:31:12.771167 3, 0xFFFF, sum = 0
4146 16:31:12.774287 4, 0xFFFF, sum = 0
4147 16:31:12.774379 5, 0xFFFF, sum = 0
4148 16:31:12.777952 6, 0xFFFF, sum = 0
4149 16:31:12.778043 7, 0xFFFF, sum = 0
4150 16:31:12.780966 8, 0x0, sum = 1
4151 16:31:12.781058 9, 0x0, sum = 2
4152 16:31:12.781143 10, 0x0, sum = 3
4153 16:31:12.784092 11, 0x0, sum = 4
4154 16:31:12.784187 best_step = 9
4155 16:31:12.784270
4156 16:31:12.784353 ==
4157 16:31:12.787565 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 16:31:12.794067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 16:31:12.794164 ==
4160 16:31:12.794251 RX Vref Scan: 1
4161 16:31:12.794336
4162 16:31:12.797876 RX Vref 0 -> 0, step: 1
4163 16:31:12.797967
4164 16:31:12.801189 RX Delay -195 -> 252, step: 8
4165 16:31:12.801268
4166 16:31:12.804536 Set Vref, RX VrefLevel [Byte0]: 59
4167 16:31:12.807642 [Byte1]: 53
4168 16:31:12.807718
4169 16:31:12.810988 Final RX Vref Byte 0 = 59 to rank0
4170 16:31:12.814232 Final RX Vref Byte 1 = 53 to rank0
4171 16:31:12.817518 Final RX Vref Byte 0 = 59 to rank1
4172 16:31:12.820651 Final RX Vref Byte 1 = 53 to rank1==
4173 16:31:12.824520 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 16:31:12.827646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 16:31:12.827747 ==
4176 16:31:12.830770 DQS Delay:
4177 16:31:12.830863 DQS0 = 0, DQS1 = 0
4178 16:31:12.834039 DQM Delay:
4179 16:31:12.834109 DQM0 = 34, DQM1 = 28
4180 16:31:12.834168 DQ Delay:
4181 16:31:12.837305 DQ0 =32, DQ1 =40, DQ2 =32, DQ3 =32
4182 16:31:12.841048 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4183 16:31:12.844109 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4184 16:31:12.847767 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =36
4185 16:31:12.847868
4186 16:31:12.847952
4187 16:31:12.857724 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4188 16:31:12.860690 CH0 RK0: MR19=808, MR18=3E3C
4189 16:31:12.864296 CH0_RK0: MR19=0x808, MR18=0x3E3C, DQSOSC=398, MR23=63, INC=165, DEC=110
4190 16:31:12.867653
4191 16:31:12.870806 ----->DramcWriteLeveling(PI) begin...
4192 16:31:12.870909 ==
4193 16:31:12.874042 Dram Type= 6, Freq= 0, CH_0, rank 1
4194 16:31:12.877283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 16:31:12.877386 ==
4196 16:31:12.880604 Write leveling (Byte 0): 30 => 30
4197 16:31:12.884463 Write leveling (Byte 1): 30 => 30
4198 16:31:12.887613 DramcWriteLeveling(PI) end<-----
4199 16:31:12.887773
4200 16:31:12.887871 ==
4201 16:31:12.890746 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 16:31:12.894427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 16:31:12.894575 ==
4204 16:31:12.897550 [Gating] SW mode calibration
4205 16:31:12.904254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4206 16:31:12.910703 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4207 16:31:12.914049 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 16:31:12.917417 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 16:31:12.924088 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 16:31:12.927228 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4211 16:31:12.930505 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4212 16:31:12.936873 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 16:31:12.940248 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 16:31:12.944197 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 16:31:12.946925 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 16:31:12.953899 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 16:31:12.957133 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 16:31:12.960285 0 10 12 | B1->B0 | 2828 3333 | 0 0 | (1 1) (0 0)
4219 16:31:12.966809 0 10 16 | B1->B0 | 3535 4141 | 0 0 | (0 0) (0 0)
4220 16:31:12.970676 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 16:31:12.973856 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 16:31:12.980491 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 16:31:12.983879 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 16:31:12.986701 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 16:31:12.993260 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 16:31:12.996454 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4227 16:31:13.000183 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 16:31:13.006726 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 16:31:13.010031 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 16:31:13.013232 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 16:31:13.020026 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 16:31:13.023347 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 16:31:13.026759 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 16:31:13.033237 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 16:31:13.036476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 16:31:13.039533 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 16:31:13.046066 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 16:31:13.049455 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 16:31:13.052650 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 16:31:13.059579 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 16:31:13.062767 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 16:31:13.065955 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4243 16:31:13.072510 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4244 16:31:13.075735 Total UI for P1: 0, mck2ui 16
4245 16:31:13.079029 best dqsien dly found for B0: ( 0, 13, 12)
4246 16:31:13.082291 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 16:31:13.085587 Total UI for P1: 0, mck2ui 16
4248 16:31:13.089037 best dqsien dly found for B1: ( 0, 13, 14)
4249 16:31:13.092201 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4250 16:31:13.095567 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4251 16:31:13.095648
4252 16:31:13.099018 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4253 16:31:13.105541 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4254 16:31:13.105658 [Gating] SW calibration Done
4255 16:31:13.105720 ==
4256 16:31:13.108780 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 16:31:13.115239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 16:31:13.115371 ==
4259 16:31:13.115476 RX Vref Scan: 0
4260 16:31:13.115570
4261 16:31:13.118575 RX Vref 0 -> 0, step: 1
4262 16:31:13.118653
4263 16:31:13.121943 RX Delay -230 -> 252, step: 16
4264 16:31:13.125190 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4265 16:31:13.128818 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4266 16:31:13.135417 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4267 16:31:13.138648 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4268 16:31:13.141935 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4269 16:31:13.145019 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4270 16:31:13.148346 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4271 16:31:13.155502 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4272 16:31:13.158698 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4273 16:31:13.161922 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4274 16:31:13.165232 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4275 16:31:13.171711 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4276 16:31:13.174851 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4277 16:31:13.178747 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4278 16:31:13.181951 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4279 16:31:13.188109 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4280 16:31:13.188194 ==
4281 16:31:13.191499 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 16:31:13.194739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 16:31:13.194841 ==
4284 16:31:13.194922 DQS Delay:
4285 16:31:13.198092 DQS0 = 0, DQS1 = 0
4286 16:31:13.198169 DQM Delay:
4287 16:31:13.201480 DQM0 = 35, DQM1 = 30
4288 16:31:13.201585 DQ Delay:
4289 16:31:13.204898 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4290 16:31:13.208227 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4291 16:31:13.211398 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4292 16:31:13.214539 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4293 16:31:13.214625
4294 16:31:13.214707
4295 16:31:13.214781 ==
4296 16:31:13.217783 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 16:31:13.221062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 16:31:13.221171 ==
4299 16:31:13.224408
4300 16:31:13.224532
4301 16:31:13.224626 TX Vref Scan disable
4302 16:31:13.228410 == TX Byte 0 ==
4303 16:31:13.231554 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4304 16:31:13.234614 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4305 16:31:13.238253 == TX Byte 1 ==
4306 16:31:13.241429 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4307 16:31:13.244753 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4308 16:31:13.244876 ==
4309 16:31:13.247818 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 16:31:13.254512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 16:31:13.254685 ==
4312 16:31:13.254785
4313 16:31:13.254879
4314 16:31:13.254977 TX Vref Scan disable
4315 16:31:13.259350 == TX Byte 0 ==
4316 16:31:13.262468 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4317 16:31:13.268956 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4318 16:31:13.269088 == TX Byte 1 ==
4319 16:31:13.272155 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4320 16:31:13.279160 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4321 16:31:13.279313
4322 16:31:13.279405 [DATLAT]
4323 16:31:13.279504 Freq=600, CH0 RK1
4324 16:31:13.279589
4325 16:31:13.282493 DATLAT Default: 0x9
4326 16:31:13.282605 0, 0xFFFF, sum = 0
4327 16:31:13.285852 1, 0xFFFF, sum = 0
4328 16:31:13.285941 2, 0xFFFF, sum = 0
4329 16:31:13.289301 3, 0xFFFF, sum = 0
4330 16:31:13.292365 4, 0xFFFF, sum = 0
4331 16:31:13.292473 5, 0xFFFF, sum = 0
4332 16:31:13.295627 6, 0xFFFF, sum = 0
4333 16:31:13.295706 7, 0xFFFF, sum = 0
4334 16:31:13.298803 8, 0x0, sum = 1
4335 16:31:13.298908 9, 0x0, sum = 2
4336 16:31:13.299002 10, 0x0, sum = 3
4337 16:31:13.302056 11, 0x0, sum = 4
4338 16:31:13.302161 best_step = 9
4339 16:31:13.302248
4340 16:31:13.302332 ==
4341 16:31:13.305463 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 16:31:13.311919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 16:31:13.312026 ==
4344 16:31:13.312114 RX Vref Scan: 0
4345 16:31:13.312207
4346 16:31:13.315800 RX Vref 0 -> 0, step: 1
4347 16:31:13.315899
4348 16:31:13.319046 RX Delay -195 -> 252, step: 8
4349 16:31:13.322296 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4350 16:31:13.328598 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4351 16:31:13.331976 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4352 16:31:13.335370 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4353 16:31:13.338562 iDelay=205, Bit 4, Center 28 (-131 ~ 188) 320
4354 16:31:13.345408 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4355 16:31:13.348507 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4356 16:31:13.351654 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4357 16:31:13.355434 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4358 16:31:13.358767 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4359 16:31:13.365409 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4360 16:31:13.368735 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4361 16:31:13.371418 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4362 16:31:13.375310 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4363 16:31:13.381943 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4364 16:31:13.385032 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4365 16:31:13.385124 ==
4366 16:31:13.388350 Dram Type= 6, Freq= 0, CH_0, rank 1
4367 16:31:13.391649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 16:31:13.391737 ==
4369 16:31:13.394964 DQS Delay:
4370 16:31:13.395047 DQS0 = 0, DQS1 = 0
4371 16:31:13.398354 DQM Delay:
4372 16:31:13.398435 DQM0 = 32, DQM1 = 27
4373 16:31:13.398505 DQ Delay:
4374 16:31:13.401502 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4375 16:31:13.404770 DQ4 =28, DQ5 =20, DQ6 =44, DQ7 =44
4376 16:31:13.408252 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4377 16:31:13.411524 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4378 16:31:13.411659
4379 16:31:13.411757
4380 16:31:13.422013 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4381 16:31:13.424713 CH0 RK1: MR19=808, MR18=6D3C
4382 16:31:13.427913 CH0_RK1: MR19=0x808, MR18=0x6D3C, DQSOSC=389, MR23=63, INC=173, DEC=115
4383 16:31:13.431795 [RxdqsGatingPostProcess] freq 600
4384 16:31:13.438437 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4385 16:31:13.441687 Pre-setting of DQS Precalculation
4386 16:31:13.444935 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4387 16:31:13.445056 ==
4388 16:31:13.448024 Dram Type= 6, Freq= 0, CH_1, rank 0
4389 16:31:13.455013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 16:31:13.455158 ==
4391 16:31:13.457936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4392 16:31:13.464663 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4393 16:31:13.467803 [CA 0] Center 35 (5~66) winsize 62
4394 16:31:13.471118 [CA 1] Center 35 (5~66) winsize 62
4395 16:31:13.475002 [CA 2] Center 34 (4~65) winsize 62
4396 16:31:13.478189 [CA 3] Center 34 (3~65) winsize 63
4397 16:31:13.481319 [CA 4] Center 34 (4~65) winsize 62
4398 16:31:13.484590 [CA 5] Center 33 (3~64) winsize 62
4399 16:31:13.484709
4400 16:31:13.487917 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4401 16:31:13.488012
4402 16:31:13.491269 [CATrainingPosCal] consider 1 rank data
4403 16:31:13.494545 u2DelayCellTimex100 = 270/100 ps
4404 16:31:13.497977 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4405 16:31:13.501371 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4406 16:31:13.508425 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4407 16:31:13.511629 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4408 16:31:13.514965 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 16:31:13.518246 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4410 16:31:13.518343
4411 16:31:13.521444 CA PerBit enable=1, Macro0, CA PI delay=33
4412 16:31:13.521551
4413 16:31:13.524779 [CBTSetCACLKResult] CA Dly = 33
4414 16:31:13.524875 CS Dly: 5 (0~36)
4415 16:31:13.528249 ==
4416 16:31:13.528341 Dram Type= 6, Freq= 0, CH_1, rank 1
4417 16:31:13.534785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 16:31:13.534886 ==
4419 16:31:13.538097 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4420 16:31:13.544714 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4421 16:31:13.548086 [CA 0] Center 35 (5~66) winsize 62
4422 16:31:13.551401 [CA 1] Center 35 (5~66) winsize 62
4423 16:31:13.554924 [CA 2] Center 34 (4~65) winsize 62
4424 16:31:13.557946 [CA 3] Center 34 (3~65) winsize 63
4425 16:31:13.561182 [CA 4] Center 34 (4~65) winsize 62
4426 16:31:13.565034 [CA 5] Center 33 (3~64) winsize 62
4427 16:31:13.565105
4428 16:31:13.568150 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4429 16:31:13.568307
4430 16:31:13.571333 [CATrainingPosCal] consider 2 rank data
4431 16:31:13.574496 u2DelayCellTimex100 = 270/100 ps
4432 16:31:13.578175 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4433 16:31:13.584744 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4434 16:31:13.587890 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 16:31:13.591128 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4436 16:31:13.594395 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4437 16:31:13.597635 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4438 16:31:13.597734
4439 16:31:13.601099 CA PerBit enable=1, Macro0, CA PI delay=33
4440 16:31:13.601173
4441 16:31:13.604419 [CBTSetCACLKResult] CA Dly = 33
4442 16:31:13.604527 CS Dly: 5 (0~36)
4443 16:31:13.607713
4444 16:31:13.611079 ----->DramcWriteLeveling(PI) begin...
4445 16:31:13.611183 ==
4446 16:31:13.614899 Dram Type= 6, Freq= 0, CH_1, rank 0
4447 16:31:13.618036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 16:31:13.618141 ==
4449 16:31:13.621467 Write leveling (Byte 0): 28 => 28
4450 16:31:13.624662 Write leveling (Byte 1): 32 => 32
4451 16:31:13.627876 DramcWriteLeveling(PI) end<-----
4452 16:31:13.627978
4453 16:31:13.628069 ==
4454 16:31:13.631243 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 16:31:13.634536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 16:31:13.634632 ==
4457 16:31:13.637904 [Gating] SW mode calibration
4458 16:31:13.644293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4459 16:31:13.650937 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4460 16:31:13.654242 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 16:31:13.657636 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4462 16:31:13.664180 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 16:31:13.667558 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
4464 16:31:13.670860 0 9 16 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
4465 16:31:13.677126 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 16:31:13.680379 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 16:31:13.683686 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 16:31:13.690083 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 16:31:13.693769 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 16:31:13.696758 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 16:31:13.703589 0 10 12 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
4472 16:31:13.706751 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4473 16:31:13.710010 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 16:31:13.716600 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 16:31:13.719863 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 16:31:13.723090 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 16:31:13.730061 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 16:31:13.733212 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4479 16:31:13.736576 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 16:31:13.743260 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 16:31:13.746396 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 16:31:13.750316 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 16:31:13.756299 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 16:31:13.760285 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 16:31:13.763504 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 16:31:13.770128 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 16:31:13.772862 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 16:31:13.776744 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 16:31:13.782958 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 16:31:13.786191 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 16:31:13.789914 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 16:31:13.795904 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 16:31:13.799763 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 16:31:13.802436 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 16:31:13.809471 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4496 16:31:13.812469 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4497 16:31:13.816055 Total UI for P1: 0, mck2ui 16
4498 16:31:13.819549 best dqsien dly found for B0: ( 0, 13, 12)
4499 16:31:13.822652 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 16:31:13.826061 Total UI for P1: 0, mck2ui 16
4501 16:31:13.829249 best dqsien dly found for B1: ( 0, 13, 14)
4502 16:31:13.832345 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4503 16:31:13.836168 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4504 16:31:13.836277
4505 16:31:13.839425 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4506 16:31:13.845964 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4507 16:31:13.846074 [Gating] SW calibration Done
4508 16:31:13.846152 ==
4509 16:31:13.849117 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 16:31:13.855635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 16:31:13.855712 ==
4512 16:31:13.855788 RX Vref Scan: 0
4513 16:31:13.855861
4514 16:31:13.858988 RX Vref 0 -> 0, step: 1
4515 16:31:13.859081
4516 16:31:13.862241 RX Delay -230 -> 252, step: 16
4517 16:31:13.865617 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4518 16:31:13.869035 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4519 16:31:13.875592 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4520 16:31:13.878860 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4521 16:31:13.882189 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4522 16:31:13.885296 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4523 16:31:13.889242 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4524 16:31:13.895947 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4525 16:31:13.898527 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4526 16:31:13.901954 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4527 16:31:13.905858 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4528 16:31:13.912423 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4529 16:31:13.915635 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4530 16:31:13.918983 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4531 16:31:13.922229 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4532 16:31:13.928808 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4533 16:31:13.928885 ==
4534 16:31:13.931778 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 16:31:13.935528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 16:31:13.935607 ==
4537 16:31:13.935670 DQS Delay:
4538 16:31:13.938646 DQS0 = 0, DQS1 = 0
4539 16:31:13.938738 DQM Delay:
4540 16:31:13.941663 DQM0 = 38, DQM1 = 29
4541 16:31:13.941741 DQ Delay:
4542 16:31:13.945258 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4543 16:31:13.948812 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4544 16:31:13.951939 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4545 16:31:13.955216 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4546 16:31:13.955295
4547 16:31:13.955356
4548 16:31:13.955411 ==
4549 16:31:13.958391 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 16:31:13.961720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 16:31:13.961800 ==
4552 16:31:13.961861
4553 16:31:13.965121
4554 16:31:13.965199 TX Vref Scan disable
4555 16:31:13.968472 == TX Byte 0 ==
4556 16:31:13.971751 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4557 16:31:13.975131 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4558 16:31:13.978545 == TX Byte 1 ==
4559 16:31:13.981726 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4560 16:31:13.984964 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4561 16:31:13.985057 ==
4562 16:31:13.988296 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 16:31:13.994711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 16:31:13.994796 ==
4565 16:31:13.994864
4566 16:31:13.994920
4567 16:31:13.994973 TX Vref Scan disable
4568 16:31:13.999669 == TX Byte 0 ==
4569 16:31:14.002780 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4570 16:31:14.009962 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4571 16:31:14.010045 == TX Byte 1 ==
4572 16:31:14.013193 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4573 16:31:14.019732 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4574 16:31:14.019835
4575 16:31:14.019922 [DATLAT]
4576 16:31:14.020007 Freq=600, CH1 RK0
4577 16:31:14.020089
4578 16:31:14.023025 DATLAT Default: 0x9
4579 16:31:14.023126 0, 0xFFFF, sum = 0
4580 16:31:14.026342 1, 0xFFFF, sum = 0
4581 16:31:14.026418 2, 0xFFFF, sum = 0
4582 16:31:14.029745 3, 0xFFFF, sum = 0
4583 16:31:14.032890 4, 0xFFFF, sum = 0
4584 16:31:14.032968 5, 0xFFFF, sum = 0
4585 16:31:14.036037 6, 0xFFFF, sum = 0
4586 16:31:14.036153 7, 0xFFFF, sum = 0
4587 16:31:14.039213 8, 0x0, sum = 1
4588 16:31:14.039329 9, 0x0, sum = 2
4589 16:31:14.039419 10, 0x0, sum = 3
4590 16:31:14.042431 11, 0x0, sum = 4
4591 16:31:14.042549 best_step = 9
4592 16:31:14.042638
4593 16:31:14.042720 ==
4594 16:31:14.045741 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 16:31:14.052792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 16:31:14.053001 ==
4597 16:31:14.053100 RX Vref Scan: 1
4598 16:31:14.053184
4599 16:31:14.055961 RX Vref 0 -> 0, step: 1
4600 16:31:14.056072
4601 16:31:14.059022 RX Delay -195 -> 252, step: 8
4602 16:31:14.059125
4603 16:31:14.062381 Set Vref, RX VrefLevel [Byte0]: 58
4604 16:31:14.065721 [Byte1]: 49
4605 16:31:14.065868
4606 16:31:14.069410 Final RX Vref Byte 0 = 58 to rank0
4607 16:31:14.072607 Final RX Vref Byte 1 = 49 to rank0
4608 16:31:14.075944 Final RX Vref Byte 0 = 58 to rank1
4609 16:31:14.079257 Final RX Vref Byte 1 = 49 to rank1==
4610 16:31:14.082555 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 16:31:14.085939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 16:31:14.086045 ==
4613 16:31:14.089208 DQS Delay:
4614 16:31:14.089303 DQS0 = 0, DQS1 = 0
4615 16:31:14.091973 DQM Delay:
4616 16:31:14.092068 DQM0 = 38, DQM1 = 28
4617 16:31:14.092153 DQ Delay:
4618 16:31:14.095221 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =36
4619 16:31:14.098760 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4620 16:31:14.102153 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4621 16:31:14.105437 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4622 16:31:14.105544
4623 16:31:14.105637
4624 16:31:14.115429 [DQSOSCAuto] RK0, (LSB)MR18= 0x2936, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
4625 16:31:14.118760 CH1 RK0: MR19=808, MR18=2936
4626 16:31:14.125526 CH1_RK0: MR19=0x808, MR18=0x2936, DQSOSC=399, MR23=63, INC=164, DEC=109
4627 16:31:14.125630
4628 16:31:14.128429 ----->DramcWriteLeveling(PI) begin...
4629 16:31:14.128520 ==
4630 16:31:14.131822 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 16:31:14.135292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 16:31:14.135391 ==
4633 16:31:14.138653 Write leveling (Byte 0): 28 => 28
4634 16:31:14.142035 Write leveling (Byte 1): 31 => 31
4635 16:31:14.145450 DramcWriteLeveling(PI) end<-----
4636 16:31:14.145554
4637 16:31:14.145616 ==
4638 16:31:14.148589 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 16:31:14.152000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 16:31:14.152097 ==
4641 16:31:14.155416 [Gating] SW mode calibration
4642 16:31:14.161671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4643 16:31:14.168567 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4644 16:31:14.171624 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4645 16:31:14.175235 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 16:31:14.181813 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 16:31:14.184902 0 9 12 | B1->B0 | 3030 2d2d | 1 1 | (1 1) (1 1)
4648 16:31:14.188104 0 9 16 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
4649 16:31:14.194823 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 16:31:14.198173 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 16:31:14.201632 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 16:31:14.207715 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 16:31:14.211580 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 16:31:14.214393 0 10 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
4655 16:31:14.221026 0 10 12 | B1->B0 | 2e2e 3838 | 0 1 | (0 0) (0 0)
4656 16:31:14.224440 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4657 16:31:14.227693 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 16:31:14.234671 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 16:31:14.238139 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 16:31:14.240938 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 16:31:14.247675 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 16:31:14.250999 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 16:31:14.254209 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 16:31:14.261076 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 16:31:14.264488 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 16:31:14.267316 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 16:31:14.274173 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 16:31:14.277560 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 16:31:14.280887 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 16:31:14.287063 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 16:31:14.290374 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 16:31:14.293565 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 16:31:14.300378 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 16:31:14.303539 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 16:31:14.306899 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 16:31:14.313807 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 16:31:14.317211 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 16:31:14.320391 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 16:31:14.327167 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4680 16:31:14.327252 Total UI for P1: 0, mck2ui 16
4681 16:31:14.333316 best dqsien dly found for B0: ( 0, 13, 10)
4682 16:31:14.336749 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 16:31:14.340216 Total UI for P1: 0, mck2ui 16
4684 16:31:14.343536 best dqsien dly found for B1: ( 0, 13, 12)
4685 16:31:14.346894 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4686 16:31:14.349633 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4687 16:31:14.349734
4688 16:31:14.352984 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4689 16:31:14.356974 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4690 16:31:14.360125 [Gating] SW calibration Done
4691 16:31:14.360219 ==
4692 16:31:14.363562 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 16:31:14.369781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 16:31:14.369890 ==
4695 16:31:14.369979 RX Vref Scan: 0
4696 16:31:14.370062
4697 16:31:14.373269 RX Vref 0 -> 0, step: 1
4698 16:31:14.373363
4699 16:31:14.376586 RX Delay -230 -> 252, step: 16
4700 16:31:14.380127 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4701 16:31:14.382965 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4702 16:31:14.386222 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4703 16:31:14.393421 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4704 16:31:14.396103 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4705 16:31:14.399406 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4706 16:31:14.402739 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4707 16:31:14.409824 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4708 16:31:14.412935 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4709 16:31:14.416478 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4710 16:31:14.419455 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4711 16:31:14.422575 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4712 16:31:14.429279 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4713 16:31:14.432660 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4714 16:31:14.435998 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4715 16:31:14.439536 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4716 16:31:14.442987 ==
4717 16:31:14.446417 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 16:31:14.449214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 16:31:14.449338 ==
4720 16:31:14.449432 DQS Delay:
4721 16:31:14.452979 DQS0 = 0, DQS1 = 0
4722 16:31:14.453087 DQM Delay:
4723 16:31:14.456220 DQM0 = 34, DQM1 = 29
4724 16:31:14.456335 DQ Delay:
4725 16:31:14.458994 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4726 16:31:14.462415 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4727 16:31:14.465637 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4728 16:31:14.469108 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4729 16:31:14.469183
4730 16:31:14.469258
4731 16:31:14.469351 ==
4732 16:31:14.472395 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 16:31:14.475990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 16:31:14.476087 ==
4735 16:31:14.476179
4736 16:31:14.476269
4737 16:31:14.479454 TX Vref Scan disable
4738 16:31:14.482284 == TX Byte 0 ==
4739 16:31:14.485844 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4740 16:31:14.489319 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4741 16:31:14.492488 == TX Byte 1 ==
4742 16:31:14.495694 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4743 16:31:14.498868 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4744 16:31:14.498971 ==
4745 16:31:14.502219 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 16:31:14.509071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 16:31:14.509170 ==
4748 16:31:14.509249
4749 16:31:14.509309
4750 16:31:14.509364 TX Vref Scan disable
4751 16:31:14.513045 == TX Byte 0 ==
4752 16:31:14.516485 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4753 16:31:14.522856 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4754 16:31:14.522951 == TX Byte 1 ==
4755 16:31:14.526101 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4756 16:31:14.532770 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4757 16:31:14.532855
4758 16:31:14.532916 [DATLAT]
4759 16:31:14.532972 Freq=600, CH1 RK1
4760 16:31:14.533027
4761 16:31:14.536246 DATLAT Default: 0x9
4762 16:31:14.536315 0, 0xFFFF, sum = 0
4763 16:31:14.539253 1, 0xFFFF, sum = 0
4764 16:31:14.543031 2, 0xFFFF, sum = 0
4765 16:31:14.543153 3, 0xFFFF, sum = 0
4766 16:31:14.546008 4, 0xFFFF, sum = 0
4767 16:31:14.546086 5, 0xFFFF, sum = 0
4768 16:31:14.549757 6, 0xFFFF, sum = 0
4769 16:31:14.549864 7, 0xFFFF, sum = 0
4770 16:31:14.552461 8, 0x0, sum = 1
4771 16:31:14.552569 9, 0x0, sum = 2
4772 16:31:14.552681 10, 0x0, sum = 3
4773 16:31:14.555935 11, 0x0, sum = 4
4774 16:31:14.556024 best_step = 9
4775 16:31:14.556102
4776 16:31:14.559136 ==
4777 16:31:14.559213 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 16:31:14.565967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 16:31:14.566057 ==
4780 16:31:14.566135 RX Vref Scan: 0
4781 16:31:14.566209
4782 16:31:14.569242 RX Vref 0 -> 0, step: 1
4783 16:31:14.569327
4784 16:31:14.572399 RX Delay -195 -> 252, step: 8
4785 16:31:14.579092 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4786 16:31:14.582533 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4787 16:31:14.585951 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4788 16:31:14.589317 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4789 16:31:14.592769 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4790 16:31:14.599274 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4791 16:31:14.602580 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4792 16:31:14.605949 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4793 16:31:14.609170 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4794 16:31:14.615968 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4795 16:31:14.618710 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4796 16:31:14.622091 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4797 16:31:14.625503 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4798 16:31:14.631867 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4799 16:31:14.635262 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4800 16:31:14.638685 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4801 16:31:14.638816 ==
4802 16:31:14.642014 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 16:31:14.645720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 16:31:14.645803 ==
4805 16:31:14.648979 DQS Delay:
4806 16:31:14.649058 DQS0 = 0, DQS1 = 0
4807 16:31:14.651934 DQM Delay:
4808 16:31:14.652013 DQM0 = 36, DQM1 = 30
4809 16:31:14.652074 DQ Delay:
4810 16:31:14.655580 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4811 16:31:14.658642 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =36
4812 16:31:14.662253 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4813 16:31:14.665205 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4814 16:31:14.665277
4815 16:31:14.665338
4816 16:31:14.675313 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4817 16:31:14.678637 CH1 RK1: MR19=808, MR18=3C5C
4818 16:31:14.685483 CH1_RK1: MR19=0x808, MR18=0x3C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4819 16:31:14.685588 [RxdqsGatingPostProcess] freq 600
4820 16:31:14.691931 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4821 16:31:14.695392 Pre-setting of DQS Precalculation
4822 16:31:14.698210 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4823 16:31:14.708365 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4824 16:31:14.714998 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4825 16:31:14.715082
4826 16:31:14.715163
4827 16:31:14.718409 [Calibration Summary] 1200 Mbps
4828 16:31:14.718512 CH 0, Rank 0
4829 16:31:14.721886 SW Impedance : PASS
4830 16:31:14.721968 DUTY Scan : NO K
4831 16:31:14.725340 ZQ Calibration : PASS
4832 16:31:14.728191 Jitter Meter : NO K
4833 16:31:14.728273 CBT Training : PASS
4834 16:31:14.731664 Write leveling : PASS
4835 16:31:14.735131 RX DQS gating : PASS
4836 16:31:14.735235 RX DQ/DQS(RDDQC) : PASS
4837 16:31:14.737922 TX DQ/DQS : PASS
4838 16:31:14.741351 RX DATLAT : PASS
4839 16:31:14.741430 RX DQ/DQS(Engine): PASS
4840 16:31:14.744782 TX OE : NO K
4841 16:31:14.744858 All Pass.
4842 16:31:14.744919
4843 16:31:14.748114 CH 0, Rank 1
4844 16:31:14.748184 SW Impedance : PASS
4845 16:31:14.751675 DUTY Scan : NO K
4846 16:31:14.755017 ZQ Calibration : PASS
4847 16:31:14.755086 Jitter Meter : NO K
4848 16:31:14.757795 CBT Training : PASS
4849 16:31:14.761146 Write leveling : PASS
4850 16:31:14.761218 RX DQS gating : PASS
4851 16:31:14.764482 RX DQ/DQS(RDDQC) : PASS
4852 16:31:14.767848 TX DQ/DQS : PASS
4853 16:31:14.767922 RX DATLAT : PASS
4854 16:31:14.771145 RX DQ/DQS(Engine): PASS
4855 16:31:14.771222 TX OE : NO K
4856 16:31:14.774403 All Pass.
4857 16:31:14.774471
4858 16:31:14.774532 CH 1, Rank 0
4859 16:31:14.777656 SW Impedance : PASS
4860 16:31:14.777733 DUTY Scan : NO K
4861 16:31:14.781228 ZQ Calibration : PASS
4862 16:31:14.784328 Jitter Meter : NO K
4863 16:31:14.784393 CBT Training : PASS
4864 16:31:14.787962 Write leveling : PASS
4865 16:31:14.791916 RX DQS gating : PASS
4866 16:31:14.791996 RX DQ/DQS(RDDQC) : PASS
4867 16:31:14.794163 TX DQ/DQS : PASS
4868 16:31:14.797626 RX DATLAT : PASS
4869 16:31:14.797706 RX DQ/DQS(Engine): PASS
4870 16:31:14.801420 TX OE : NO K
4871 16:31:14.801520 All Pass.
4872 16:31:14.801582
4873 16:31:14.804631 CH 1, Rank 1
4874 16:31:14.804716 SW Impedance : PASS
4875 16:31:14.807979 DUTY Scan : NO K
4876 16:31:14.810662 ZQ Calibration : PASS
4877 16:31:14.810737 Jitter Meter : NO K
4878 16:31:14.814041 CBT Training : PASS
4879 16:31:14.817630 Write leveling : PASS
4880 16:31:14.817700 RX DQS gating : PASS
4881 16:31:14.820532 RX DQ/DQS(RDDQC) : PASS
4882 16:31:14.824038 TX DQ/DQS : PASS
4883 16:31:14.824116 RX DATLAT : PASS
4884 16:31:14.827414 RX DQ/DQS(Engine): PASS
4885 16:31:14.830932 TX OE : NO K
4886 16:31:14.831012 All Pass.
4887 16:31:14.831096
4888 16:31:14.831155 DramC Write-DBI off
4889 16:31:14.834370 PER_BANK_REFRESH: Hybrid Mode
4890 16:31:14.837128 TX_TRACKING: ON
4891 16:31:14.844035 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4892 16:31:14.847533 [FAST_K] Save calibration result to emmc
4893 16:31:14.853933 dramc_set_vcore_voltage set vcore to 662500
4894 16:31:14.854009 Read voltage for 933, 3
4895 16:31:14.857279 Vio18 = 0
4896 16:31:14.857348 Vcore = 662500
4897 16:31:14.857409 Vdram = 0
4898 16:31:14.857467 Vddq = 0
4899 16:31:14.860696 Vmddr = 0
4900 16:31:14.863899 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4901 16:31:14.870774 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4902 16:31:14.873532 MEM_TYPE=3, freq_sel=17
4903 16:31:14.873607 sv_algorithm_assistance_LP4_1600
4904 16:31:14.880184 ============ PULL DRAM RESETB DOWN ============
4905 16:31:14.883573 ========== PULL DRAM RESETB DOWN end =========
4906 16:31:14.886860 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4907 16:31:14.890730 ===================================
4908 16:31:14.893764 LPDDR4 DRAM CONFIGURATION
4909 16:31:14.896897 ===================================
4910 16:31:14.900812 EX_ROW_EN[0] = 0x0
4911 16:31:14.900894 EX_ROW_EN[1] = 0x0
4912 16:31:14.903865 LP4Y_EN = 0x0
4913 16:31:14.903934 WORK_FSP = 0x0
4914 16:31:14.906890 WL = 0x3
4915 16:31:14.906960 RL = 0x3
4916 16:31:14.910526 BL = 0x2
4917 16:31:14.910597 RPST = 0x0
4918 16:31:14.913428 RD_PRE = 0x0
4919 16:31:14.913509 WR_PRE = 0x1
4920 16:31:14.916845 WR_PST = 0x0
4921 16:31:14.916916 DBI_WR = 0x0
4922 16:31:14.920229 DBI_RD = 0x0
4923 16:31:14.920322 OTF = 0x1
4924 16:31:14.923506 ===================================
4925 16:31:14.927193 ===================================
4926 16:31:14.930560 ANA top config
4927 16:31:14.933386 ===================================
4928 16:31:14.936861 DLL_ASYNC_EN = 0
4929 16:31:14.936938 ALL_SLAVE_EN = 1
4930 16:31:14.940348 NEW_RANK_MODE = 1
4931 16:31:14.943780 DLL_IDLE_MODE = 1
4932 16:31:14.947019 LP45_APHY_COMB_EN = 1
4933 16:31:14.949756 TX_ODT_DIS = 1
4934 16:31:14.949846 NEW_8X_MODE = 1
4935 16:31:14.953205 ===================================
4936 16:31:14.956597 ===================================
4937 16:31:14.960079 data_rate = 1866
4938 16:31:14.963430 CKR = 1
4939 16:31:14.966532 DQ_P2S_RATIO = 8
4940 16:31:14.969802 ===================================
4941 16:31:14.973226 CA_P2S_RATIO = 8
4942 16:31:14.976657 DQ_CA_OPEN = 0
4943 16:31:14.976726 DQ_SEMI_OPEN = 0
4944 16:31:14.979977 CA_SEMI_OPEN = 0
4945 16:31:14.983349 CA_FULL_RATE = 0
4946 16:31:14.986672 DQ_CKDIV4_EN = 1
4947 16:31:14.990097 CA_CKDIV4_EN = 1
4948 16:31:14.993308 CA_PREDIV_EN = 0
4949 16:31:14.993395 PH8_DLY = 0
4950 16:31:14.996617 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4951 16:31:14.999838 DQ_AAMCK_DIV = 4
4952 16:31:15.003021 CA_AAMCK_DIV = 4
4953 16:31:15.006370 CA_ADMCK_DIV = 4
4954 16:31:15.009745 DQ_TRACK_CA_EN = 0
4955 16:31:15.009808 CA_PICK = 933
4956 16:31:15.013128 CA_MCKIO = 933
4957 16:31:15.016635 MCKIO_SEMI = 0
4958 16:31:15.019461 PLL_FREQ = 3732
4959 16:31:15.022674 DQ_UI_PI_RATIO = 32
4960 16:31:15.025901 CA_UI_PI_RATIO = 0
4961 16:31:15.029503 ===================================
4962 16:31:15.032638 ===================================
4963 16:31:15.032717 memory_type:LPDDR4
4964 16:31:15.036265 GP_NUM : 10
4965 16:31:15.039383 SRAM_EN : 1
4966 16:31:15.039484 MD32_EN : 0
4967 16:31:15.042444 ===================================
4968 16:31:15.046065 [ANA_INIT] >>>>>>>>>>>>>>
4969 16:31:15.049063 <<<<<< [CONFIGURE PHASE]: ANA_TX
4970 16:31:15.052458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4971 16:31:15.055865 ===================================
4972 16:31:15.059359 data_rate = 1866,PCW = 0X8f00
4973 16:31:15.062680 ===================================
4974 16:31:15.066031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4975 16:31:15.069466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4976 16:31:15.075556 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4977 16:31:15.082350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4978 16:31:15.085686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4979 16:31:15.089036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4980 16:31:15.089112 [ANA_INIT] flow start
4981 16:31:15.092470 [ANA_INIT] PLL >>>>>>>>
4982 16:31:15.095839 [ANA_INIT] PLL <<<<<<<<
4983 16:31:15.095909 [ANA_INIT] MIDPI >>>>>>>>
4984 16:31:15.099335 [ANA_INIT] MIDPI <<<<<<<<
4985 16:31:15.102704 [ANA_INIT] DLL >>>>>>>>
4986 16:31:15.102779 [ANA_INIT] flow end
4987 16:31:15.108703 ============ LP4 DIFF to SE enter ============
4988 16:31:15.111956 ============ LP4 DIFF to SE exit ============
4989 16:31:15.112028 [ANA_INIT] <<<<<<<<<<<<<
4990 16:31:15.115757 [Flow] Enable top DCM control >>>>>
4991 16:31:15.119137 [Flow] Enable top DCM control <<<<<
4992 16:31:15.121981 Enable DLL master slave shuffle
4993 16:31:15.128660 ==============================================================
4994 16:31:15.131885 Gating Mode config
4995 16:31:15.135175 ==============================================================
4996 16:31:15.138642 Config description:
4997 16:31:15.148739 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4998 16:31:15.155680 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4999 16:31:15.158695 SELPH_MODE 0: By rank 1: By Phase
5000 16:31:15.165779 ==============================================================
5001 16:31:15.168550 GAT_TRACK_EN = 1
5002 16:31:15.171777 RX_GATING_MODE = 2
5003 16:31:15.171855 RX_GATING_TRACK_MODE = 2
5004 16:31:15.175126 SELPH_MODE = 1
5005 16:31:15.178401 PICG_EARLY_EN = 1
5006 16:31:15.181775 VALID_LAT_VALUE = 1
5007 16:31:15.188688 ==============================================================
5008 16:31:15.191997 Enter into Gating configuration >>>>
5009 16:31:15.195365 Exit from Gating configuration <<<<
5010 16:31:15.198692 Enter into DVFS_PRE_config >>>>>
5011 16:31:15.208269 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5012 16:31:15.211588 Exit from DVFS_PRE_config <<<<<
5013 16:31:15.214994 Enter into PICG configuration >>>>
5014 16:31:15.218199 Exit from PICG configuration <<<<
5015 16:31:15.221500 [RX_INPUT] configuration >>>>>
5016 16:31:15.224713 [RX_INPUT] configuration <<<<<
5017 16:31:15.228651 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5018 16:31:15.234745 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5019 16:31:15.241414 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5020 16:31:15.248405 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5021 16:31:15.254978 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5022 16:31:15.257665 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5023 16:31:15.264859 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5024 16:31:15.267723 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5025 16:31:15.271028 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5026 16:31:15.274262 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5027 16:31:15.281419 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5028 16:31:15.284418 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5029 16:31:15.288133 ===================================
5030 16:31:15.290886 LPDDR4 DRAM CONFIGURATION
5031 16:31:15.294396 ===================================
5032 16:31:15.294477 EX_ROW_EN[0] = 0x0
5033 16:31:15.297613 EX_ROW_EN[1] = 0x0
5034 16:31:15.297694 LP4Y_EN = 0x0
5035 16:31:15.301080 WORK_FSP = 0x0
5036 16:31:15.301161 WL = 0x3
5037 16:31:15.304355 RL = 0x3
5038 16:31:15.304436 BL = 0x2
5039 16:31:15.307679 RPST = 0x0
5040 16:31:15.307759 RD_PRE = 0x0
5041 16:31:15.311109 WR_PRE = 0x1
5042 16:31:15.314507 WR_PST = 0x0
5043 16:31:15.314607 DBI_WR = 0x0
5044 16:31:15.317851 DBI_RD = 0x0
5045 16:31:15.317935 OTF = 0x1
5046 16:31:15.320564 ===================================
5047 16:31:15.324062 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5048 16:31:15.327441 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5049 16:31:15.334413 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5050 16:31:15.337608 ===================================
5051 16:31:15.340911 LPDDR4 DRAM CONFIGURATION
5052 16:31:15.343728 ===================================
5053 16:31:15.343834 EX_ROW_EN[0] = 0x10
5054 16:31:15.347234 EX_ROW_EN[1] = 0x0
5055 16:31:15.347336 LP4Y_EN = 0x0
5056 16:31:15.350677 WORK_FSP = 0x0
5057 16:31:15.350753 WL = 0x3
5058 16:31:15.354194 RL = 0x3
5059 16:31:15.354268 BL = 0x2
5060 16:31:15.357484 RPST = 0x0
5061 16:31:15.357566 RD_PRE = 0x0
5062 16:31:15.360937 WR_PRE = 0x1
5063 16:31:15.361016 WR_PST = 0x0
5064 16:31:15.364279 DBI_WR = 0x0
5065 16:31:15.364386 DBI_RD = 0x0
5066 16:31:15.367573 OTF = 0x1
5067 16:31:15.370460 ===================================
5068 16:31:15.377367 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5069 16:31:15.380804 nWR fixed to 30
5070 16:31:15.384199 [ModeRegInit_LP4] CH0 RK0
5071 16:31:15.384282 [ModeRegInit_LP4] CH0 RK1
5072 16:31:15.387630 [ModeRegInit_LP4] CH1 RK0
5073 16:31:15.391003 [ModeRegInit_LP4] CH1 RK1
5074 16:31:15.391084 match AC timing 9
5075 16:31:15.397221 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5076 16:31:15.400628 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5077 16:31:15.404179 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5078 16:31:15.410698 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5079 16:31:15.414309 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5080 16:31:15.414394 ==
5081 16:31:15.417049 Dram Type= 6, Freq= 0, CH_0, rank 0
5082 16:31:15.420236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 16:31:15.420340 ==
5084 16:31:15.427187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 16:31:15.433733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5086 16:31:15.437102 [CA 0] Center 38 (8~69) winsize 62
5087 16:31:15.440270 [CA 1] Center 38 (8~69) winsize 62
5088 16:31:15.444079 [CA 2] Center 35 (5~66) winsize 62
5089 16:31:15.447226 [CA 3] Center 34 (4~65) winsize 62
5090 16:31:15.450296 [CA 4] Center 34 (4~65) winsize 62
5091 16:31:15.453641 [CA 5] Center 33 (3~64) winsize 62
5092 16:31:15.453745
5093 16:31:15.457167 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5094 16:31:15.457241
5095 16:31:15.460466 [CATrainingPosCal] consider 1 rank data
5096 16:31:15.463763 u2DelayCellTimex100 = 270/100 ps
5097 16:31:15.467080 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5098 16:31:15.470200 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5099 16:31:15.473654 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5100 16:31:15.477082 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5101 16:31:15.480427 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5102 16:31:15.483855 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5103 16:31:15.486705
5104 16:31:15.490081 CA PerBit enable=1, Macro0, CA PI delay=33
5105 16:31:15.490150
5106 16:31:15.493510 [CBTSetCACLKResult] CA Dly = 33
5107 16:31:15.493578 CS Dly: 7 (0~38)
5108 16:31:15.493637 ==
5109 16:31:15.496991 Dram Type= 6, Freq= 0, CH_0, rank 1
5110 16:31:15.500413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 16:31:15.500488 ==
5112 16:31:15.506550 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5113 16:31:15.513324 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5114 16:31:15.516329 [CA 0] Center 38 (8~69) winsize 62
5115 16:31:15.520092 [CA 1] Center 38 (8~69) winsize 62
5116 16:31:15.523447 [CA 2] Center 35 (5~66) winsize 62
5117 16:31:15.526882 [CA 3] Center 35 (5~65) winsize 61
5118 16:31:15.530050 [CA 4] Center 34 (3~65) winsize 63
5119 16:31:15.533375 [CA 5] Center 34 (3~65) winsize 63
5120 16:31:15.533448
5121 16:31:15.536779 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5122 16:31:15.536848
5123 16:31:15.540149 [CATrainingPosCal] consider 2 rank data
5124 16:31:15.542972 u2DelayCellTimex100 = 270/100 ps
5125 16:31:15.546264 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5126 16:31:15.549702 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5127 16:31:15.552988 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5128 16:31:15.556164 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5129 16:31:15.563329 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5130 16:31:15.566663 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5131 16:31:15.566737
5132 16:31:15.569455 CA PerBit enable=1, Macro0, CA PI delay=33
5133 16:31:15.569528
5134 16:31:15.572737 [CBTSetCACLKResult] CA Dly = 33
5135 16:31:15.572842 CS Dly: 7 (0~38)
5136 16:31:15.572931
5137 16:31:15.576753 ----->DramcWriteLeveling(PI) begin...
5138 16:31:15.576833 ==
5139 16:31:15.579389 Dram Type= 6, Freq= 0, CH_0, rank 0
5140 16:31:15.586140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 16:31:15.586221 ==
5142 16:31:15.589426 Write leveling (Byte 0): 29 => 29
5143 16:31:15.592803 Write leveling (Byte 1): 29 => 29
5144 16:31:15.592883 DramcWriteLeveling(PI) end<-----
5145 16:31:15.592948
5146 16:31:15.596245 ==
5147 16:31:15.599595 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 16:31:15.603057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 16:31:15.603142 ==
5150 16:31:15.605909 [Gating] SW mode calibration
5151 16:31:15.612716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5152 16:31:15.616191 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5153 16:31:15.622949 0 14 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5154 16:31:15.626358 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5155 16:31:15.629586 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 16:31:15.635902 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 16:31:15.639425 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 16:31:15.642488 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 16:31:15.649035 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 16:31:15.652352 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
5161 16:31:15.655892 0 15 0 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
5162 16:31:15.662673 0 15 4 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5163 16:31:15.665743 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 16:31:15.669175 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 16:31:15.675982 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 16:31:15.679238 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 16:31:15.682539 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 16:31:15.688951 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 16:31:15.692429 1 0 0 | B1->B0 | 2d2d 4040 | 0 1 | (0 0) (0 0)
5170 16:31:15.695858 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5171 16:31:15.702071 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 16:31:15.705432 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 16:31:15.708880 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 16:31:15.715692 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 16:31:15.719125 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 16:31:15.721877 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5177 16:31:15.728797 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5178 16:31:15.732293 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 16:31:15.735690 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 16:31:15.742264 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 16:31:15.745518 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 16:31:15.748777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 16:31:15.754983 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 16:31:15.758611 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 16:31:15.761750 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 16:31:15.765266 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 16:31:15.771753 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 16:31:15.775231 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 16:31:15.778559 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 16:31:15.784847 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 16:31:15.788631 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 16:31:15.791626 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5193 16:31:15.798423 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5194 16:31:15.801538 Total UI for P1: 0, mck2ui 16
5195 16:31:15.804904 best dqsien dly found for B0: ( 1, 2, 28)
5196 16:31:15.808349 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 16:31:15.811802 Total UI for P1: 0, mck2ui 16
5198 16:31:15.815294 best dqsien dly found for B1: ( 1, 3, 0)
5199 16:31:15.818098 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5200 16:31:15.821422 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5201 16:31:15.821496
5202 16:31:15.824990 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5203 16:31:15.828343 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5204 16:31:15.831666 [Gating] SW calibration Done
5205 16:31:15.831734 ==
5206 16:31:15.834566 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 16:31:15.838037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 16:31:15.841461 ==
5209 16:31:15.841539 RX Vref Scan: 0
5210 16:31:15.841601
5211 16:31:15.844840 RX Vref 0 -> 0, step: 1
5212 16:31:15.844910
5213 16:31:15.848181 RX Delay -80 -> 252, step: 8
5214 16:31:15.851496 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5215 16:31:15.854981 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5216 16:31:15.858367 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5217 16:31:15.861626 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5218 16:31:15.864988 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5219 16:31:15.871110 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5220 16:31:15.874948 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5221 16:31:15.878144 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5222 16:31:15.881889 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5223 16:31:15.884600 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5224 16:31:15.888233 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5225 16:31:15.894885 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5226 16:31:15.897984 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5227 16:31:15.901239 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5228 16:31:15.905082 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5229 16:31:15.911371 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5230 16:31:15.911454 ==
5231 16:31:15.914701 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 16:31:15.918136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 16:31:15.918210 ==
5234 16:31:15.918270 DQS Delay:
5235 16:31:15.920983 DQS0 = 0, DQS1 = 0
5236 16:31:15.921065 DQM Delay:
5237 16:31:15.924460 DQM0 = 93, DQM1 = 81
5238 16:31:15.924537 DQ Delay:
5239 16:31:15.927850 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5240 16:31:15.931215 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5241 16:31:15.934526 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5242 16:31:15.937924 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =87
5243 16:31:15.937992
5244 16:31:15.938066
5245 16:31:15.938130 ==
5246 16:31:15.941374 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 16:31:15.944776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 16:31:15.944858 ==
5249 16:31:15.944918
5250 16:31:15.947508
5251 16:31:15.947575 TX Vref Scan disable
5252 16:31:15.951239 == TX Byte 0 ==
5253 16:31:15.954598 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5254 16:31:15.957435 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5255 16:31:15.960963 == TX Byte 1 ==
5256 16:31:15.964334 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5257 16:31:15.967606 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5258 16:31:15.967710 ==
5259 16:31:15.970964 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 16:31:15.977716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 16:31:15.977787 ==
5262 16:31:15.977846
5263 16:31:15.977907
5264 16:31:15.977961 TX Vref Scan disable
5265 16:31:15.981865 == TX Byte 0 ==
5266 16:31:15.985368 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5267 16:31:15.991905 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5268 16:31:15.991980 == TX Byte 1 ==
5269 16:31:15.994871 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5270 16:31:15.998374 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5271 16:31:16.002022
5272 16:31:16.002098 [DATLAT]
5273 16:31:16.002156 Freq=933, CH0 RK0
5274 16:31:16.002212
5275 16:31:16.005145 DATLAT Default: 0xd
5276 16:31:16.005230 0, 0xFFFF, sum = 0
5277 16:31:16.008138 1, 0xFFFF, sum = 0
5278 16:31:16.008205 2, 0xFFFF, sum = 0
5279 16:31:16.011665 3, 0xFFFF, sum = 0
5280 16:31:16.015076 4, 0xFFFF, sum = 0
5281 16:31:16.015142 5, 0xFFFF, sum = 0
5282 16:31:16.018016 6, 0xFFFF, sum = 0
5283 16:31:16.018121 7, 0xFFFF, sum = 0
5284 16:31:16.021658 8, 0xFFFF, sum = 0
5285 16:31:16.021730 9, 0xFFFF, sum = 0
5286 16:31:16.024849 10, 0x0, sum = 1
5287 16:31:16.024920 11, 0x0, sum = 2
5288 16:31:16.028040 12, 0x0, sum = 3
5289 16:31:16.028123 13, 0x0, sum = 4
5290 16:31:16.028187 best_step = 11
5291 16:31:16.028242
5292 16:31:16.031494 ==
5293 16:31:16.031559 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 16:31:16.038250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 16:31:16.038321 ==
5296 16:31:16.038378 RX Vref Scan: 1
5297 16:31:16.038431
5298 16:31:16.041691 RX Vref 0 -> 0, step: 1
5299 16:31:16.041776
5300 16:31:16.044995 RX Delay -77 -> 252, step: 4
5301 16:31:16.045064
5302 16:31:16.048216 Set Vref, RX VrefLevel [Byte0]: 59
5303 16:31:16.051586 [Byte1]: 53
5304 16:31:16.051663
5305 16:31:16.055000 Final RX Vref Byte 0 = 59 to rank0
5306 16:31:16.057934 Final RX Vref Byte 1 = 53 to rank0
5307 16:31:16.061286 Final RX Vref Byte 0 = 59 to rank1
5308 16:31:16.064577 Final RX Vref Byte 1 = 53 to rank1==
5309 16:31:16.067924 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 16:31:16.071615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 16:31:16.074960 ==
5312 16:31:16.075037 DQS Delay:
5313 16:31:16.075103 DQS0 = 0, DQS1 = 0
5314 16:31:16.078257 DQM Delay:
5315 16:31:16.078338 DQM0 = 95, DQM1 = 83
5316 16:31:16.081081 DQ Delay:
5317 16:31:16.081153 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =94
5318 16:31:16.085004 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =104
5319 16:31:16.087686 DQ8 =76, DQ9 =70, DQ10 =84, DQ11 =76
5320 16:31:16.091151 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =90
5321 16:31:16.094559
5322 16:31:16.094626
5323 16:31:16.101401 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5324 16:31:16.104471 CH0 RK0: MR19=505, MR18=1514
5325 16:31:16.110911 CH0_RK0: MR19=0x505, MR18=0x1514, DQSOSC=415, MR23=63, INC=62, DEC=41
5326 16:31:16.110984
5327 16:31:16.114470 ----->DramcWriteLeveling(PI) begin...
5328 16:31:16.114547 ==
5329 16:31:16.117891 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 16:31:16.121230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 16:31:16.121322 ==
5332 16:31:16.124485 Write leveling (Byte 0): 33 => 33
5333 16:31:16.127496 Write leveling (Byte 1): 29 => 29
5334 16:31:16.131154 DramcWriteLeveling(PI) end<-----
5335 16:31:16.131224
5336 16:31:16.131280 ==
5337 16:31:16.134290 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 16:31:16.137676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 16:31:16.137746 ==
5340 16:31:16.140831 [Gating] SW mode calibration
5341 16:31:16.147737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5342 16:31:16.154294 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5343 16:31:16.157737 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5344 16:31:16.161175 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 16:31:16.167351 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 16:31:16.170845 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 16:31:16.174165 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 16:31:16.180976 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 16:31:16.184345 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5350 16:31:16.187856 0 14 28 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (1 1)
5351 16:31:16.194031 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5352 16:31:16.197397 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 16:31:16.200770 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 16:31:16.207030 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 16:31:16.210371 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 16:31:16.213650 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 16:31:16.220723 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5358 16:31:16.224082 0 15 28 | B1->B0 | 2929 3636 | 0 0 | (0 0) (1 1)
5359 16:31:16.227399 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5360 16:31:16.233707 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 16:31:16.237098 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 16:31:16.240482 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 16:31:16.246892 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 16:31:16.250529 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 16:31:16.253480 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 16:31:16.260119 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5367 16:31:16.263678 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5368 16:31:16.266646 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 16:31:16.273972 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 16:31:16.277208 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 16:31:16.280495 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 16:31:16.286594 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 16:31:16.289963 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 16:31:16.293248 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 16:31:16.300103 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 16:31:16.303581 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 16:31:16.306999 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 16:31:16.313289 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 16:31:16.316616 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 16:31:16.320114 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 16:31:16.323456 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5382 16:31:16.330184 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 16:31:16.333630 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5384 16:31:16.336884 Total UI for P1: 0, mck2ui 16
5385 16:31:16.340225 best dqsien dly found for B0: ( 1, 2, 30)
5386 16:31:16.342983 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 16:31:16.346314 Total UI for P1: 0, mck2ui 16
5388 16:31:16.349705 best dqsien dly found for B1: ( 1, 3, 0)
5389 16:31:16.353103 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5390 16:31:16.356468 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5391 16:31:16.359710
5392 16:31:16.362978 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5393 16:31:16.366237 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5394 16:31:16.369740 [Gating] SW calibration Done
5395 16:31:16.369811 ==
5396 16:31:16.373072 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 16:31:16.376330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 16:31:16.376393 ==
5399 16:31:16.376447 RX Vref Scan: 0
5400 16:31:16.376503
5401 16:31:16.380058 RX Vref 0 -> 0, step: 1
5402 16:31:16.380128
5403 16:31:16.383073 RX Delay -80 -> 252, step: 8
5404 16:31:16.386673 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5405 16:31:16.390220 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5406 16:31:16.393145 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5407 16:31:16.399685 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5408 16:31:16.403124 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5409 16:31:16.406520 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5410 16:31:16.409838 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5411 16:31:16.413334 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5412 16:31:16.419543 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5413 16:31:16.423017 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5414 16:31:16.426398 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5415 16:31:16.429701 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5416 16:31:16.433045 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5417 16:31:16.439364 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5418 16:31:16.442929 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5419 16:31:16.446112 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5420 16:31:16.446205 ==
5421 16:31:16.449521 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 16:31:16.453053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 16:31:16.453120 ==
5424 16:31:16.455865 DQS Delay:
5425 16:31:16.455929 DQS0 = 0, DQS1 = 0
5426 16:31:16.459397 DQM Delay:
5427 16:31:16.459462 DQM0 = 91, DQM1 = 82
5428 16:31:16.459517 DQ Delay:
5429 16:31:16.462748 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =87
5430 16:31:16.466236 DQ4 =91, DQ5 =79, DQ6 =99, DQ7 =103
5431 16:31:16.468968 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79
5432 16:31:16.472273 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =87
5433 16:31:16.472345
5434 16:31:16.472404
5435 16:31:16.476184 ==
5436 16:31:16.478926 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 16:31:16.482497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 16:31:16.482575 ==
5439 16:31:16.482633
5440 16:31:16.482687
5441 16:31:16.485872 TX Vref Scan disable
5442 16:31:16.485942 == TX Byte 0 ==
5443 16:31:16.492501 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5444 16:31:16.495773 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5445 16:31:16.495844 == TX Byte 1 ==
5446 16:31:16.502246 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5447 16:31:16.505467 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5448 16:31:16.505541 ==
5449 16:31:16.508641 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 16:31:16.512384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 16:31:16.512490 ==
5452 16:31:16.512579
5453 16:31:16.512676
5454 16:31:16.515723 TX Vref Scan disable
5455 16:31:16.519126 == TX Byte 0 ==
5456 16:31:16.521927 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5457 16:31:16.525330 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5458 16:31:16.528775 == TX Byte 1 ==
5459 16:31:16.532326 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5460 16:31:16.535720 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5461 16:31:16.535797
5462 16:31:16.538520 [DATLAT]
5463 16:31:16.538591 Freq=933, CH0 RK1
5464 16:31:16.538650
5465 16:31:16.542058 DATLAT Default: 0xb
5466 16:31:16.542139 0, 0xFFFF, sum = 0
5467 16:31:16.545300 1, 0xFFFF, sum = 0
5468 16:31:16.545375 2, 0xFFFF, sum = 0
5469 16:31:16.548616 3, 0xFFFF, sum = 0
5470 16:31:16.548702 4, 0xFFFF, sum = 0
5471 16:31:16.551712 5, 0xFFFF, sum = 0
5472 16:31:16.551804 6, 0xFFFF, sum = 0
5473 16:31:16.555307 7, 0xFFFF, sum = 0
5474 16:31:16.555378 8, 0xFFFF, sum = 0
5475 16:31:16.558547 9, 0xFFFF, sum = 0
5476 16:31:16.558622 10, 0x0, sum = 1
5477 16:31:16.562100 11, 0x0, sum = 2
5478 16:31:16.562177 12, 0x0, sum = 3
5479 16:31:16.564745 13, 0x0, sum = 4
5480 16:31:16.564823 best_step = 11
5481 16:31:16.564882
5482 16:31:16.564937 ==
5483 16:31:16.568609 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 16:31:16.574781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 16:31:16.574869 ==
5486 16:31:16.574935 RX Vref Scan: 0
5487 16:31:16.574996
5488 16:31:16.578522 RX Vref 0 -> 0, step: 1
5489 16:31:16.578608
5490 16:31:16.581799 RX Delay -77 -> 252, step: 4
5491 16:31:16.584920 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5492 16:31:16.591736 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5493 16:31:16.595164 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5494 16:31:16.597928 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5495 16:31:16.601871 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5496 16:31:16.605081 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5497 16:31:16.608366 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5498 16:31:16.614538 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5499 16:31:16.617807 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5500 16:31:16.621531 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5501 16:31:16.624660 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5502 16:31:16.627948 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5503 16:31:16.634707 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5504 16:31:16.637999 iDelay=199, Bit 13, Center 90 (-5 ~ 186) 192
5505 16:31:16.641473 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5506 16:31:16.644879 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5507 16:31:16.644958 ==
5508 16:31:16.648351 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 16:31:16.651073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 16:31:16.654485 ==
5511 16:31:16.654562 DQS Delay:
5512 16:31:16.654623 DQS0 = 0, DQS1 = 0
5513 16:31:16.658005 DQM Delay:
5514 16:31:16.658082 DQM0 = 92, DQM1 = 84
5515 16:31:16.661145 DQ Delay:
5516 16:31:16.664275 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =86
5517 16:31:16.664353 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =104
5518 16:31:16.667681 DQ8 =80, DQ9 =68, DQ10 =84, DQ11 =76
5519 16:31:16.674738 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5520 16:31:16.674843
5521 16:31:16.674931
5522 16:31:16.680851 [DQSOSCAuto] RK1, (LSB)MR18= 0x3315, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
5523 16:31:16.684749 CH0 RK1: MR19=505, MR18=3315
5524 16:31:16.691313 CH0_RK1: MR19=0x505, MR18=0x3315, DQSOSC=405, MR23=63, INC=66, DEC=44
5525 16:31:16.694733 [RxdqsGatingPostProcess] freq 933
5526 16:31:16.697497 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5527 16:31:16.700871 best DQS0 dly(2T, 0.5T) = (0, 10)
5528 16:31:16.704292 best DQS1 dly(2T, 0.5T) = (0, 11)
5529 16:31:16.707748 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5530 16:31:16.711113 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5531 16:31:16.714405 best DQS0 dly(2T, 0.5T) = (0, 10)
5532 16:31:16.717641 best DQS1 dly(2T, 0.5T) = (0, 11)
5533 16:31:16.721121 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5534 16:31:16.724455 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5535 16:31:16.727646 Pre-setting of DQS Precalculation
5536 16:31:16.730841 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5537 16:31:16.730917 ==
5538 16:31:16.734112 Dram Type= 6, Freq= 0, CH_1, rank 0
5539 16:31:16.741041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 16:31:16.741159 ==
5541 16:31:16.744311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5542 16:31:16.751124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5543 16:31:16.753909 [CA 0] Center 37 (7~67) winsize 61
5544 16:31:16.757402 [CA 1] Center 37 (7~68) winsize 62
5545 16:31:16.760780 [CA 2] Center 34 (5~64) winsize 60
5546 16:31:16.764263 [CA 3] Center 34 (5~64) winsize 60
5547 16:31:16.767629 [CA 4] Center 34 (5~64) winsize 60
5548 16:31:16.770965 [CA 5] Center 34 (4~64) winsize 61
5549 16:31:16.771060
5550 16:31:16.774243 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5551 16:31:16.774323
5552 16:31:16.777246 [CATrainingPosCal] consider 1 rank data
5553 16:31:16.780523 u2DelayCellTimex100 = 270/100 ps
5554 16:31:16.784128 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5555 16:31:16.787346 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5556 16:31:16.790709 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5557 16:31:16.797119 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5558 16:31:16.800609 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5559 16:31:16.804066 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5560 16:31:16.804162
5561 16:31:16.807422 CA PerBit enable=1, Macro0, CA PI delay=34
5562 16:31:16.807512
5563 16:31:16.810705 [CBTSetCACLKResult] CA Dly = 34
5564 16:31:16.810801 CS Dly: 6 (0~37)
5565 16:31:16.810864 ==
5566 16:31:16.814109 Dram Type= 6, Freq= 0, CH_1, rank 1
5567 16:31:16.820820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 16:31:16.820902 ==
5569 16:31:16.824139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5570 16:31:16.830293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5571 16:31:16.833647 [CA 0] Center 37 (8~67) winsize 60
5572 16:31:16.836889 [CA 1] Center 37 (7~68) winsize 62
5573 16:31:16.840486 [CA 2] Center 35 (6~65) winsize 60
5574 16:31:16.843807 [CA 3] Center 34 (4~64) winsize 61
5575 16:31:16.846964 [CA 4] Center 35 (5~65) winsize 61
5576 16:31:16.850334 [CA 5] Center 34 (4~64) winsize 61
5577 16:31:16.850413
5578 16:31:16.853606 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5579 16:31:16.853685
5580 16:31:16.856989 [CATrainingPosCal] consider 2 rank data
5581 16:31:16.860428 u2DelayCellTimex100 = 270/100 ps
5582 16:31:16.863825 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5583 16:31:16.870357 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5584 16:31:16.873741 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5585 16:31:16.876982 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5586 16:31:16.880455 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5587 16:31:16.883220 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5588 16:31:16.883297
5589 16:31:16.886569 CA PerBit enable=1, Macro0, CA PI delay=34
5590 16:31:16.886660
5591 16:31:16.889813 [CBTSetCACLKResult] CA Dly = 34
5592 16:31:16.889887 CS Dly: 6 (0~38)
5593 16:31:16.893379
5594 16:31:16.896745 ----->DramcWriteLeveling(PI) begin...
5595 16:31:16.896825 ==
5596 16:31:16.900014 Dram Type= 6, Freq= 0, CH_1, rank 0
5597 16:31:16.903047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5598 16:31:16.903121 ==
5599 16:31:16.906872 Write leveling (Byte 0): 23 => 23
5600 16:31:16.910033 Write leveling (Byte 1): 29 => 29
5601 16:31:16.913129 DramcWriteLeveling(PI) end<-----
5602 16:31:16.913210
5603 16:31:16.913271 ==
5604 16:31:16.916489 Dram Type= 6, Freq= 0, CH_1, rank 0
5605 16:31:16.920034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5606 16:31:16.920113 ==
5607 16:31:16.923409 [Gating] SW mode calibration
5608 16:31:16.930038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5609 16:31:16.936652 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5610 16:31:16.939473 0 14 0 | B1->B0 | 3232 3433 | 1 1 | (1 1) (0 0)
5611 16:31:16.943423 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 16:31:16.949572 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 16:31:16.952983 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 16:31:16.956248 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 16:31:16.963068 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 16:31:16.965840 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 16:31:16.969269 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
5618 16:31:16.976258 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 16:31:16.979086 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 16:31:16.982514 0 15 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
5621 16:31:16.989429 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 16:31:16.992957 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 16:31:16.995661 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 16:31:17.002891 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 16:31:17.005924 0 15 28 | B1->B0 | 3737 3434 | 0 1 | (0 0) (0 0)
5626 16:31:17.009026 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 16:31:17.015888 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 16:31:17.019208 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 16:31:17.022179 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 16:31:17.025646 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 16:31:17.032423 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 16:31:17.035517 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 16:31:17.039543 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5634 16:31:17.045571 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 16:31:17.049048 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 16:31:17.052291 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 16:31:17.059076 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 16:31:17.062332 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 16:31:17.065570 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 16:31:17.072709 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 16:31:17.075388 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 16:31:17.078834 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 16:31:17.085640 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 16:31:17.089193 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 16:31:17.092652 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 16:31:17.098987 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 16:31:17.102372 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 16:31:17.105831 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 16:31:17.111990 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 16:31:17.115262 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 16:31:17.119121 Total UI for P1: 0, mck2ui 16
5652 16:31:17.122264 best dqsien dly found for B0: ( 1, 2, 30)
5653 16:31:17.125551 Total UI for P1: 0, mck2ui 16
5654 16:31:17.128716 best dqsien dly found for B1: ( 1, 2, 30)
5655 16:31:17.132228 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5656 16:31:17.135249 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5657 16:31:17.135328
5658 16:31:17.138920 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5659 16:31:17.142021 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5660 16:31:17.145604 [Gating] SW calibration Done
5661 16:31:17.145683 ==
5662 16:31:17.148519 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 16:31:17.151926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 16:31:17.155509 ==
5665 16:31:17.155587 RX Vref Scan: 0
5666 16:31:17.155648
5667 16:31:17.158543 RX Vref 0 -> 0, step: 1
5668 16:31:17.158621
5669 16:31:17.158682 RX Delay -80 -> 252, step: 8
5670 16:31:17.165440 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5671 16:31:17.168589 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5672 16:31:17.171793 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5673 16:31:17.175295 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5674 16:31:17.178760 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5675 16:31:17.185154 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5676 16:31:17.188538 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5677 16:31:17.191953 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5678 16:31:17.195379 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5679 16:31:17.198800 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5680 16:31:17.202372 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5681 16:31:17.208752 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5682 16:31:17.212291 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5683 16:31:17.215721 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5684 16:31:17.218452 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5685 16:31:17.221794 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5686 16:31:17.221907 ==
5687 16:31:17.225100 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 16:31:17.231688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 16:31:17.231785 ==
5690 16:31:17.231846 DQS Delay:
5691 16:31:17.235025 DQS0 = 0, DQS1 = 0
5692 16:31:17.235102 DQM Delay:
5693 16:31:17.238231 DQM0 = 94, DQM1 = 86
5694 16:31:17.238313 DQ Delay:
5695 16:31:17.241496 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5696 16:31:17.245358 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5697 16:31:17.248680 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5698 16:31:17.252046 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5699 16:31:17.252119
5700 16:31:17.252178
5701 16:31:17.252232 ==
5702 16:31:17.255229 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 16:31:17.258363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 16:31:17.258434 ==
5705 16:31:17.258492
5706 16:31:17.258566
5707 16:31:17.261521 TX Vref Scan disable
5708 16:31:17.265290 == TX Byte 0 ==
5709 16:31:17.267915 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5710 16:31:17.271313 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5711 16:31:17.274549 == TX Byte 1 ==
5712 16:31:17.278196 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5713 16:31:17.281241 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5714 16:31:17.281321 ==
5715 16:31:17.284781 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 16:31:17.291435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 16:31:17.291536 ==
5718 16:31:17.291624
5719 16:31:17.291708
5720 16:31:17.291792 TX Vref Scan disable
5721 16:31:17.295524 == TX Byte 0 ==
5722 16:31:17.298358 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5723 16:31:17.305341 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5724 16:31:17.305417 == TX Byte 1 ==
5725 16:31:17.308792 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5726 16:31:17.315008 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5727 16:31:17.315079
5728 16:31:17.315168 [DATLAT]
5729 16:31:17.315251 Freq=933, CH1 RK0
5730 16:31:17.315325
5731 16:31:17.318551 DATLAT Default: 0xd
5732 16:31:17.318639 0, 0xFFFF, sum = 0
5733 16:31:17.321911 1, 0xFFFF, sum = 0
5734 16:31:17.322008 2, 0xFFFF, sum = 0
5735 16:31:17.325324 3, 0xFFFF, sum = 0
5736 16:31:17.328737 4, 0xFFFF, sum = 0
5737 16:31:17.328821 5, 0xFFFF, sum = 0
5738 16:31:17.332014 6, 0xFFFF, sum = 0
5739 16:31:17.332111 7, 0xFFFF, sum = 0
5740 16:31:17.334831 8, 0xFFFF, sum = 0
5741 16:31:17.334935 9, 0xFFFF, sum = 0
5742 16:31:17.338324 10, 0x0, sum = 1
5743 16:31:17.338409 11, 0x0, sum = 2
5744 16:31:17.341662 12, 0x0, sum = 3
5745 16:31:17.341731 13, 0x0, sum = 4
5746 16:31:17.341788 best_step = 11
5747 16:31:17.341841
5748 16:31:17.345037 ==
5749 16:31:17.348254 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 16:31:17.351510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 16:31:17.351601 ==
5752 16:31:17.351664 RX Vref Scan: 1
5753 16:31:17.351718
5754 16:31:17.354618 RX Vref 0 -> 0, step: 1
5755 16:31:17.354723
5756 16:31:17.358099 RX Delay -69 -> 252, step: 4
5757 16:31:17.358171
5758 16:31:17.361404 Set Vref, RX VrefLevel [Byte0]: 58
5759 16:31:17.364659 [Byte1]: 49
5760 16:31:17.364731
5761 16:31:17.367949 Final RX Vref Byte 0 = 58 to rank0
5762 16:31:17.371534 Final RX Vref Byte 1 = 49 to rank0
5763 16:31:17.374902 Final RX Vref Byte 0 = 58 to rank1
5764 16:31:17.378180 Final RX Vref Byte 1 = 49 to rank1==
5765 16:31:17.381668 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 16:31:17.385035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 16:31:17.388438 ==
5768 16:31:17.388517 DQS Delay:
5769 16:31:17.388578 DQS0 = 0, DQS1 = 0
5770 16:31:17.391535 DQM Delay:
5771 16:31:17.391615 DQM0 = 95, DQM1 = 88
5772 16:31:17.394602 DQ Delay:
5773 16:31:17.397987 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =92
5774 16:31:17.401089 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =94
5775 16:31:17.404945 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =80
5776 16:31:17.407747 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =94
5777 16:31:17.407821
5778 16:31:17.407882
5779 16:31:17.414364 [DQSOSCAuto] RK0, (LSB)MR18= 0x50d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5780 16:31:17.417795 CH1 RK0: MR19=505, MR18=50D
5781 16:31:17.424726 CH1_RK0: MR19=0x505, MR18=0x50D, DQSOSC=417, MR23=63, INC=62, DEC=41
5782 16:31:17.424802
5783 16:31:17.428132 ----->DramcWriteLeveling(PI) begin...
5784 16:31:17.428203 ==
5785 16:31:17.430930 Dram Type= 6, Freq= 0, CH_1, rank 1
5786 16:31:17.434275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 16:31:17.434352 ==
5788 16:31:17.437786 Write leveling (Byte 0): 24 => 24
5789 16:31:17.441320 Write leveling (Byte 1): 25 => 25
5790 16:31:17.444084 DramcWriteLeveling(PI) end<-----
5791 16:31:17.444163
5792 16:31:17.444225 ==
5793 16:31:17.447502 Dram Type= 6, Freq= 0, CH_1, rank 1
5794 16:31:17.451026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 16:31:17.451105 ==
5796 16:31:17.454304 [Gating] SW mode calibration
5797 16:31:17.460779 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5798 16:31:17.467357 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5799 16:31:17.470771 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5800 16:31:17.473984 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 16:31:17.480675 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 16:31:17.484374 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 16:31:17.487619 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 16:31:17.494481 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 16:31:17.497684 0 14 24 | B1->B0 | 3333 3030 | 1 0 | (1 0) (1 0)
5806 16:31:17.500799 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
5807 16:31:17.507531 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5808 16:31:17.511008 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 16:31:17.514028 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 16:31:17.520803 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 16:31:17.523906 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 16:31:17.527173 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 16:31:17.534037 0 15 24 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
5814 16:31:17.537432 0 15 28 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5815 16:31:17.540619 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 16:31:17.547571 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 16:31:17.550369 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 16:31:17.553681 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 16:31:17.560562 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 16:31:17.563959 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 16:31:17.567379 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5822 16:31:17.573602 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5823 16:31:17.577076 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 16:31:17.580496 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 16:31:17.587226 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 16:31:17.590413 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 16:31:17.593357 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 16:31:17.600104 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 16:31:17.603516 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 16:31:17.606791 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 16:31:17.613291 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 16:31:17.616635 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 16:31:17.620033 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 16:31:17.623483 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 16:31:17.629880 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 16:31:17.633579 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 16:31:17.636772 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5838 16:31:17.643605 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 16:31:17.646800 Total UI for P1: 0, mck2ui 16
5840 16:31:17.650026 best dqsien dly found for B0: ( 1, 2, 24)
5841 16:31:17.653324 Total UI for P1: 0, mck2ui 16
5842 16:31:17.656675 best dqsien dly found for B1: ( 1, 2, 26)
5843 16:31:17.660021 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5844 16:31:17.663447 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5845 16:31:17.663538
5846 16:31:17.666250 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5847 16:31:17.669671 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5848 16:31:17.673111 [Gating] SW calibration Done
5849 16:31:17.673209 ==
5850 16:31:17.676324 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 16:31:17.680017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 16:31:17.680089 ==
5853 16:31:17.683079 RX Vref Scan: 0
5854 16:31:17.683162
5855 16:31:17.686368 RX Vref 0 -> 0, step: 1
5856 16:31:17.686444
5857 16:31:17.686507 RX Delay -80 -> 252, step: 8
5858 16:31:17.693035 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5859 16:31:17.696362 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5860 16:31:17.699674 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5861 16:31:17.702753 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5862 16:31:17.706006 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5863 16:31:17.709221 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5864 16:31:17.716343 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5865 16:31:17.719547 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5866 16:31:17.722993 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5867 16:31:17.725793 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5868 16:31:17.729135 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5869 16:31:17.735863 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5870 16:31:17.739181 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5871 16:31:17.742609 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5872 16:31:17.745928 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5873 16:31:17.749549 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5874 16:31:17.749642 ==
5875 16:31:17.752509 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 16:31:17.758892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 16:31:17.758978 ==
5878 16:31:17.759051 DQS Delay:
5879 16:31:17.762745 DQS0 = 0, DQS1 = 0
5880 16:31:17.762815 DQM Delay:
5881 16:31:17.765576 DQM0 = 93, DQM1 = 88
5882 16:31:17.765641 DQ Delay:
5883 16:31:17.769042 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5884 16:31:17.772459 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5885 16:31:17.776007 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5886 16:31:17.778732 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5887 16:31:17.778796
5888 16:31:17.778851
5889 16:31:17.778903 ==
5890 16:31:17.782115 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 16:31:17.785471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 16:31:17.785541 ==
5893 16:31:17.785595
5894 16:31:17.785647
5895 16:31:17.788885 TX Vref Scan disable
5896 16:31:17.792581 == TX Byte 0 ==
5897 16:31:17.796087 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5898 16:31:17.798728 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5899 16:31:17.802243 == TX Byte 1 ==
5900 16:31:17.805545 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5901 16:31:17.808752 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5902 16:31:17.808820 ==
5903 16:31:17.812599 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 16:31:17.815653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 16:31:17.819064 ==
5906 16:31:17.819130
5907 16:31:17.819188
5908 16:31:17.819247 TX Vref Scan disable
5909 16:31:17.822422 == TX Byte 0 ==
5910 16:31:17.825572 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5911 16:31:17.828893 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5912 16:31:17.832191 == TX Byte 1 ==
5913 16:31:17.835571 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5914 16:31:17.839107 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5915 16:31:17.842376
5916 16:31:17.842454 [DATLAT]
5917 16:31:17.842511 Freq=933, CH1 RK1
5918 16:31:17.842569
5919 16:31:17.845578 DATLAT Default: 0xb
5920 16:31:17.845651 0, 0xFFFF, sum = 0
5921 16:31:17.848993 1, 0xFFFF, sum = 0
5922 16:31:17.849061 2, 0xFFFF, sum = 0
5923 16:31:17.852393 3, 0xFFFF, sum = 0
5924 16:31:17.855791 4, 0xFFFF, sum = 0
5925 16:31:17.855854 5, 0xFFFF, sum = 0
5926 16:31:17.859213 6, 0xFFFF, sum = 0
5927 16:31:17.859277 7, 0xFFFF, sum = 0
5928 16:31:17.862391 8, 0xFFFF, sum = 0
5929 16:31:17.862457 9, 0xFFFF, sum = 0
5930 16:31:17.865644 10, 0x0, sum = 1
5931 16:31:17.865710 11, 0x0, sum = 2
5932 16:31:17.868718 12, 0x0, sum = 3
5933 16:31:17.868784 13, 0x0, sum = 4
5934 16:31:17.868838 best_step = 11
5935 16:31:17.868892
5936 16:31:17.871888 ==
5937 16:31:17.875601 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 16:31:17.879049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 16:31:17.879112 ==
5940 16:31:17.879169 RX Vref Scan: 0
5941 16:31:17.879223
5942 16:31:17.881791 RX Vref 0 -> 0, step: 1
5943 16:31:17.881850
5944 16:31:17.885324 RX Delay -69 -> 252, step: 4
5945 16:31:17.892213 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5946 16:31:17.895584 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5947 16:31:17.898739 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5948 16:31:17.901968 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5949 16:31:17.905319 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5950 16:31:17.908601 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5951 16:31:17.915266 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5952 16:31:17.918530 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5953 16:31:17.921955 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5954 16:31:17.925323 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5955 16:31:17.928080 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5956 16:31:17.935170 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5957 16:31:17.938639 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5958 16:31:17.941350 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5959 16:31:17.944718 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5960 16:31:17.948107 iDelay=203, Bit 15, Center 100 (11 ~ 190) 180
5961 16:31:17.951306 ==
5962 16:31:17.951405 Dram Type= 6, Freq= 0, CH_1, rank 1
5963 16:31:17.958099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5964 16:31:17.958197 ==
5965 16:31:17.958290 DQS Delay:
5966 16:31:17.961598 DQS0 = 0, DQS1 = 0
5967 16:31:17.961668 DQM Delay:
5968 16:31:17.964417 DQM0 = 92, DQM1 = 92
5969 16:31:17.964508 DQ Delay:
5970 16:31:17.967743 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5971 16:31:17.971166 DQ4 =90, DQ5 =100, DQ6 =106, DQ7 =88
5972 16:31:17.974414 DQ8 =78, DQ9 =82, DQ10 =94, DQ11 =86
5973 16:31:17.977723 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =100
5974 16:31:17.977801
5975 16:31:17.977869
5976 16:31:17.984739 [DQSOSCAuto] RK1, (LSB)MR18= 0xf22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5977 16:31:17.988060 CH1 RK1: MR19=505, MR18=F22
5978 16:31:17.994251 CH1_RK1: MR19=0x505, MR18=0xF22, DQSOSC=411, MR23=63, INC=64, DEC=42
5979 16:31:17.997707 [RxdqsGatingPostProcess] freq 933
5980 16:31:18.004151 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5981 16:31:18.008033 best DQS0 dly(2T, 0.5T) = (0, 10)
5982 16:31:18.008129 best DQS1 dly(2T, 0.5T) = (0, 10)
5983 16:31:18.010758 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5984 16:31:18.014220 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5985 16:31:18.017583 best DQS0 dly(2T, 0.5T) = (0, 10)
5986 16:31:18.020923 best DQS1 dly(2T, 0.5T) = (0, 10)
5987 16:31:18.024359 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5988 16:31:18.027640 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5989 16:31:18.030871 Pre-setting of DQS Precalculation
5990 16:31:18.037194 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5991 16:31:18.043691 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5992 16:31:18.050600 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5993 16:31:18.050732
5994 16:31:18.050822
5995 16:31:18.053959 [Calibration Summary] 1866 Mbps
5996 16:31:18.054032 CH 0, Rank 0
5997 16:31:18.057124 SW Impedance : PASS
5998 16:31:18.060293 DUTY Scan : NO K
5999 16:31:18.060395 ZQ Calibration : PASS
6000 16:31:18.063664 Jitter Meter : NO K
6001 16:31:18.066769 CBT Training : PASS
6002 16:31:18.066839 Write leveling : PASS
6003 16:31:18.069939 RX DQS gating : PASS
6004 16:31:18.073924 RX DQ/DQS(RDDQC) : PASS
6005 16:31:18.074004 TX DQ/DQS : PASS
6006 16:31:18.076642 RX DATLAT : PASS
6007 16:31:18.080024 RX DQ/DQS(Engine): PASS
6008 16:31:18.080094 TX OE : NO K
6009 16:31:18.083312 All Pass.
6010 16:31:18.083383
6011 16:31:18.083444 CH 0, Rank 1
6012 16:31:18.086531 SW Impedance : PASS
6013 16:31:18.086603 DUTY Scan : NO K
6014 16:31:18.090391 ZQ Calibration : PASS
6015 16:31:18.093684 Jitter Meter : NO K
6016 16:31:18.093754 CBT Training : PASS
6017 16:31:18.096887 Write leveling : PASS
6018 16:31:18.099661 RX DQS gating : PASS
6019 16:31:18.099730 RX DQ/DQS(RDDQC) : PASS
6020 16:31:18.103044 TX DQ/DQS : PASS
6021 16:31:18.103116 RX DATLAT : PASS
6022 16:31:18.106421 RX DQ/DQS(Engine): PASS
6023 16:31:18.109646 TX OE : NO K
6024 16:31:18.109715 All Pass.
6025 16:31:18.109773
6026 16:31:18.109827 CH 1, Rank 0
6027 16:31:18.113421 SW Impedance : PASS
6028 16:31:18.116839 DUTY Scan : NO K
6029 16:31:18.116905 ZQ Calibration : PASS
6030 16:31:18.119567 Jitter Meter : NO K
6031 16:31:18.123001 CBT Training : PASS
6032 16:31:18.123073 Write leveling : PASS
6033 16:31:18.126212 RX DQS gating : PASS
6034 16:31:18.129610 RX DQ/DQS(RDDQC) : PASS
6035 16:31:18.129700 TX DQ/DQS : PASS
6036 16:31:18.133049 RX DATLAT : PASS
6037 16:31:18.136320 RX DQ/DQS(Engine): PASS
6038 16:31:18.136389 TX OE : NO K
6039 16:31:18.139442 All Pass.
6040 16:31:18.139509
6041 16:31:18.139564 CH 1, Rank 1
6042 16:31:18.143008 SW Impedance : PASS
6043 16:31:18.143104 DUTY Scan : NO K
6044 16:31:18.146297 ZQ Calibration : PASS
6045 16:31:18.149456 Jitter Meter : NO K
6046 16:31:18.149558 CBT Training : PASS
6047 16:31:18.152663 Write leveling : PASS
6048 16:31:18.156134 RX DQS gating : PASS
6049 16:31:18.156233 RX DQ/DQS(RDDQC) : PASS
6050 16:31:18.159555 TX DQ/DQS : PASS
6051 16:31:18.162791 RX DATLAT : PASS
6052 16:31:18.162884 RX DQ/DQS(Engine): PASS
6053 16:31:18.166006 TX OE : NO K
6054 16:31:18.166090 All Pass.
6055 16:31:18.166173
6056 16:31:18.169268 DramC Write-DBI off
6057 16:31:18.172544 PER_BANK_REFRESH: Hybrid Mode
6058 16:31:18.172651 TX_TRACKING: ON
6059 16:31:18.182956 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6060 16:31:18.186392 [FAST_K] Save calibration result to emmc
6061 16:31:18.189585 dramc_set_vcore_voltage set vcore to 650000
6062 16:31:18.192871 Read voltage for 400, 6
6063 16:31:18.192945 Vio18 = 0
6064 16:31:18.193027 Vcore = 650000
6065 16:31:18.196006 Vdram = 0
6066 16:31:18.196106 Vddq = 0
6067 16:31:18.196201 Vmddr = 0
6068 16:31:18.202649 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6069 16:31:18.205902 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6070 16:31:18.209208 MEM_TYPE=3, freq_sel=20
6071 16:31:18.212619 sv_algorithm_assistance_LP4_800
6072 16:31:18.215768 ============ PULL DRAM RESETB DOWN ============
6073 16:31:18.218796 ========== PULL DRAM RESETB DOWN end =========
6074 16:31:18.225601 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6075 16:31:18.228902 ===================================
6076 16:31:18.228999 LPDDR4 DRAM CONFIGURATION
6077 16:31:18.232224 ===================================
6078 16:31:18.235669 EX_ROW_EN[0] = 0x0
6079 16:31:18.239156 EX_ROW_EN[1] = 0x0
6080 16:31:18.239232 LP4Y_EN = 0x0
6081 16:31:18.242527 WORK_FSP = 0x0
6082 16:31:18.242625 WL = 0x2
6083 16:31:18.245914 RL = 0x2
6084 16:31:18.245988 BL = 0x2
6085 16:31:18.249019 RPST = 0x0
6086 16:31:18.249102 RD_PRE = 0x0
6087 16:31:18.252392 WR_PRE = 0x1
6088 16:31:18.252460 WR_PST = 0x0
6089 16:31:18.255719 DBI_WR = 0x0
6090 16:31:18.255788 DBI_RD = 0x0
6091 16:31:18.258932 OTF = 0x1
6092 16:31:18.262301 ===================================
6093 16:31:18.265702 ===================================
6094 16:31:18.265786 ANA top config
6095 16:31:18.268956 ===================================
6096 16:31:18.272236 DLL_ASYNC_EN = 0
6097 16:31:18.275539 ALL_SLAVE_EN = 1
6098 16:31:18.278731 NEW_RANK_MODE = 1
6099 16:31:18.278813 DLL_IDLE_MODE = 1
6100 16:31:18.282034 LP45_APHY_COMB_EN = 1
6101 16:31:18.285502 TX_ODT_DIS = 1
6102 16:31:18.288908 NEW_8X_MODE = 1
6103 16:31:18.291666 ===================================
6104 16:31:18.295105 ===================================
6105 16:31:18.298449 data_rate = 800
6106 16:31:18.298516 CKR = 1
6107 16:31:18.301638 DQ_P2S_RATIO = 4
6108 16:31:18.304991 ===================================
6109 16:31:18.308311 CA_P2S_RATIO = 4
6110 16:31:18.311456 DQ_CA_OPEN = 0
6111 16:31:18.315383 DQ_SEMI_OPEN = 1
6112 16:31:18.318154 CA_SEMI_OPEN = 1
6113 16:31:18.318227 CA_FULL_RATE = 0
6114 16:31:18.321478 DQ_CKDIV4_EN = 0
6115 16:31:18.325347 CA_CKDIV4_EN = 1
6116 16:31:18.328120 CA_PREDIV_EN = 0
6117 16:31:18.331527 PH8_DLY = 0
6118 16:31:18.334772 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6119 16:31:18.334842 DQ_AAMCK_DIV = 0
6120 16:31:18.338154 CA_AAMCK_DIV = 0
6121 16:31:18.341516 CA_ADMCK_DIV = 4
6122 16:31:18.344944 DQ_TRACK_CA_EN = 0
6123 16:31:18.348438 CA_PICK = 800
6124 16:31:18.351707 CA_MCKIO = 400
6125 16:31:18.354740 MCKIO_SEMI = 400
6126 16:31:18.354814 PLL_FREQ = 3016
6127 16:31:18.358130 DQ_UI_PI_RATIO = 32
6128 16:31:18.361504 CA_UI_PI_RATIO = 32
6129 16:31:18.364735 ===================================
6130 16:31:18.368043 ===================================
6131 16:31:18.371369 memory_type:LPDDR4
6132 16:31:18.374732 GP_NUM : 10
6133 16:31:18.374809 SRAM_EN : 1
6134 16:31:18.378009 MD32_EN : 0
6135 16:31:18.381208 ===================================
6136 16:31:18.381282 [ANA_INIT] >>>>>>>>>>>>>>
6137 16:31:18.384458 <<<<<< [CONFIGURE PHASE]: ANA_TX
6138 16:31:18.387606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6139 16:31:18.391070 ===================================
6140 16:31:18.394495 data_rate = 800,PCW = 0X7400
6141 16:31:18.397931 ===================================
6142 16:31:18.400685 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6143 16:31:18.407629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 16:31:18.417573 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6145 16:31:18.424225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6146 16:31:18.427424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6147 16:31:18.430624 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6148 16:31:18.430694 [ANA_INIT] flow start
6149 16:31:18.434114 [ANA_INIT] PLL >>>>>>>>
6150 16:31:18.437318 [ANA_INIT] PLL <<<<<<<<
6151 16:31:18.440747 [ANA_INIT] MIDPI >>>>>>>>
6152 16:31:18.440821 [ANA_INIT] MIDPI <<<<<<<<
6153 16:31:18.444125 [ANA_INIT] DLL >>>>>>>>
6154 16:31:18.447004 [ANA_INIT] flow end
6155 16:31:18.450503 ============ LP4 DIFF to SE enter ============
6156 16:31:18.453909 ============ LP4 DIFF to SE exit ============
6157 16:31:18.457282 [ANA_INIT] <<<<<<<<<<<<<
6158 16:31:18.460571 [Flow] Enable top DCM control >>>>>
6159 16:31:18.463922 [Flow] Enable top DCM control <<<<<
6160 16:31:18.467348 Enable DLL master slave shuffle
6161 16:31:18.470637 ==============================================================
6162 16:31:18.473900 Gating Mode config
6163 16:31:18.476959 ==============================================================
6164 16:31:18.480257 Config description:
6165 16:31:18.490292 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6166 16:31:18.497073 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6167 16:31:18.500404 SELPH_MODE 0: By rank 1: By Phase
6168 16:31:18.507180 ==============================================================
6169 16:31:18.510410 GAT_TRACK_EN = 0
6170 16:31:18.513552 RX_GATING_MODE = 2
6171 16:31:18.517296 RX_GATING_TRACK_MODE = 2
6172 16:31:18.520033 SELPH_MODE = 1
6173 16:31:18.523246 PICG_EARLY_EN = 1
6174 16:31:18.523319 VALID_LAT_VALUE = 1
6175 16:31:18.530381 ==============================================================
6176 16:31:18.533584 Enter into Gating configuration >>>>
6177 16:31:18.536815 Exit from Gating configuration <<<<
6178 16:31:18.540119 Enter into DVFS_PRE_config >>>>>
6179 16:31:18.550424 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6180 16:31:18.553796 Exit from DVFS_PRE_config <<<<<
6181 16:31:18.556606 Enter into PICG configuration >>>>
6182 16:31:18.560205 Exit from PICG configuration <<<<
6183 16:31:18.563617 [RX_INPUT] configuration >>>>>
6184 16:31:18.566385 [RX_INPUT] configuration <<<<<
6185 16:31:18.573357 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6186 16:31:18.576884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6187 16:31:18.583238 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6188 16:31:18.590040 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6189 16:31:18.596563 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6190 16:31:18.603322 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6191 16:31:18.606089 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6192 16:31:18.609479 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6193 16:31:18.612954 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6194 16:31:18.619497 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6195 16:31:18.623372 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6196 16:31:18.626194 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6197 16:31:18.629639 ===================================
6198 16:31:18.632850 LPDDR4 DRAM CONFIGURATION
6199 16:31:18.636106 ===================================
6200 16:31:18.636183 EX_ROW_EN[0] = 0x0
6201 16:31:18.639855 EX_ROW_EN[1] = 0x0
6202 16:31:18.639931 LP4Y_EN = 0x0
6203 16:31:18.643021 WORK_FSP = 0x0
6204 16:31:18.646619 WL = 0x2
6205 16:31:18.646697 RL = 0x2
6206 16:31:18.649782 BL = 0x2
6207 16:31:18.649858 RPST = 0x0
6208 16:31:18.653192 RD_PRE = 0x0
6209 16:31:18.653267 WR_PRE = 0x1
6210 16:31:18.656565 WR_PST = 0x0
6211 16:31:18.656650 DBI_WR = 0x0
6212 16:31:18.659979 DBI_RD = 0x0
6213 16:31:18.660055 OTF = 0x1
6214 16:31:18.662691 ===================================
6215 16:31:18.666090 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6216 16:31:18.672907 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6217 16:31:18.676314 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6218 16:31:18.679466 ===================================
6219 16:31:18.682868 LPDDR4 DRAM CONFIGURATION
6220 16:31:18.686244 ===================================
6221 16:31:18.686320 EX_ROW_EN[0] = 0x10
6222 16:31:18.689644 EX_ROW_EN[1] = 0x0
6223 16:31:18.689720 LP4Y_EN = 0x0
6224 16:31:18.692620 WORK_FSP = 0x0
6225 16:31:18.692723 WL = 0x2
6226 16:31:18.696226 RL = 0x2
6227 16:31:18.696302 BL = 0x2
6228 16:31:18.699553 RPST = 0x0
6229 16:31:18.702789 RD_PRE = 0x0
6230 16:31:18.702860 WR_PRE = 0x1
6231 16:31:18.706112 WR_PST = 0x0
6232 16:31:18.706177 DBI_WR = 0x0
6233 16:31:18.709479 DBI_RD = 0x0
6234 16:31:18.709551 OTF = 0x1
6235 16:31:18.712912 ===================================
6236 16:31:18.719722 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6237 16:31:18.722999 nWR fixed to 30
6238 16:31:18.726297 [ModeRegInit_LP4] CH0 RK0
6239 16:31:18.726366 [ModeRegInit_LP4] CH0 RK1
6240 16:31:18.730015 [ModeRegInit_LP4] CH1 RK0
6241 16:31:18.732737 [ModeRegInit_LP4] CH1 RK1
6242 16:31:18.732814 match AC timing 19
6243 16:31:18.739510 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6244 16:31:18.742855 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6245 16:31:18.746118 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6246 16:31:18.752658 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6247 16:31:18.756330 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6248 16:31:18.756410 ==
6249 16:31:18.759316 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 16:31:18.762595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 16:31:18.762673 ==
6252 16:31:18.769274 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6253 16:31:18.776151 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6254 16:31:18.779559 [CA 0] Center 36 (8~64) winsize 57
6255 16:31:18.782993 [CA 1] Center 36 (8~64) winsize 57
6256 16:31:18.786124 [CA 2] Center 36 (8~64) winsize 57
6257 16:31:18.789253 [CA 3] Center 36 (8~64) winsize 57
6258 16:31:18.792654 [CA 4] Center 36 (8~64) winsize 57
6259 16:31:18.792747 [CA 5] Center 36 (8~64) winsize 57
6260 16:31:18.795993
6261 16:31:18.799375 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6262 16:31:18.799448
6263 16:31:18.802687 [CATrainingPosCal] consider 1 rank data
6264 16:31:18.805801 u2DelayCellTimex100 = 270/100 ps
6265 16:31:18.808832 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 16:31:18.812087 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 16:31:18.815369 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 16:31:18.818900 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 16:31:18.822221 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 16:31:18.825639 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 16:31:18.825715
6272 16:31:18.829077 CA PerBit enable=1, Macro0, CA PI delay=36
6273 16:31:18.829152
6274 16:31:18.832344 [CBTSetCACLKResult] CA Dly = 36
6275 16:31:18.835517 CS Dly: 1 (0~32)
6276 16:31:18.835593 ==
6277 16:31:18.838832 Dram Type= 6, Freq= 0, CH_0, rank 1
6278 16:31:18.842373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 16:31:18.842450 ==
6280 16:31:18.848543 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6281 16:31:18.855488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6282 16:31:18.858972 [CA 0] Center 36 (8~64) winsize 57
6283 16:31:18.859050 [CA 1] Center 36 (8~64) winsize 57
6284 16:31:18.862313 [CA 2] Center 36 (8~64) winsize 57
6285 16:31:18.865440 [CA 3] Center 36 (8~64) winsize 57
6286 16:31:18.868465 [CA 4] Center 36 (8~64) winsize 57
6287 16:31:18.872373 [CA 5] Center 36 (8~64) winsize 57
6288 16:31:18.872450
6289 16:31:18.875742 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6290 16:31:18.875818
6291 16:31:18.878587 [CATrainingPosCal] consider 2 rank data
6292 16:31:18.882027 u2DelayCellTimex100 = 270/100 ps
6293 16:31:18.885551 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 16:31:18.892262 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 16:31:18.895320 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 16:31:18.898484 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 16:31:18.901831 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 16:31:18.905114 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 16:31:18.905181
6300 16:31:18.908532 CA PerBit enable=1, Macro0, CA PI delay=36
6301 16:31:18.908628
6302 16:31:18.911945 [CBTSetCACLKResult] CA Dly = 36
6303 16:31:18.912024 CS Dly: 1 (0~32)
6304 16:31:18.914953
6305 16:31:18.918653 ----->DramcWriteLeveling(PI) begin...
6306 16:31:18.918757 ==
6307 16:31:18.922001 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 16:31:18.925327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 16:31:18.925429 ==
6310 16:31:18.928790 Write leveling (Byte 0): 40 => 8
6311 16:31:18.931647 Write leveling (Byte 1): 40 => 8
6312 16:31:18.935138 DramcWriteLeveling(PI) end<-----
6313 16:31:18.935229
6314 16:31:18.935313 ==
6315 16:31:18.938370 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 16:31:18.941532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 16:31:18.941626 ==
6318 16:31:18.944701 [Gating] SW mode calibration
6319 16:31:18.951253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6320 16:31:18.957978 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6321 16:31:18.961400 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 16:31:18.964852 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6323 16:31:18.971580 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 16:31:18.974659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 16:31:18.977756 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 16:31:18.984315 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 16:31:18.987671 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 16:31:18.991167 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 16:31:18.997945 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 16:31:18.998072 Total UI for P1: 0, mck2ui 16
6331 16:31:19.004625 best dqsien dly found for B0: ( 0, 14, 24)
6332 16:31:19.004799 Total UI for P1: 0, mck2ui 16
6333 16:31:19.010965 best dqsien dly found for B1: ( 0, 14, 24)
6334 16:31:19.014474 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6335 16:31:19.017894 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6336 16:31:19.018018
6337 16:31:19.021247 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 16:31:19.024350 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6339 16:31:19.027646 [Gating] SW calibration Done
6340 16:31:19.027717 ==
6341 16:31:19.030700 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 16:31:19.033968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 16:31:19.034036 ==
6344 16:31:19.037636 RX Vref Scan: 0
6345 16:31:19.037706
6346 16:31:19.037770 RX Vref 0 -> 0, step: 1
6347 16:31:19.037827
6348 16:31:19.041066 RX Delay -410 -> 252, step: 16
6349 16:31:19.047774 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6350 16:31:19.050365 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6351 16:31:19.053818 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6352 16:31:19.057215 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6353 16:31:19.063662 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6354 16:31:19.067022 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6355 16:31:19.070426 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6356 16:31:19.073937 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6357 16:31:19.080589 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6358 16:31:19.083870 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6359 16:31:19.087014 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6360 16:31:19.090089 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6361 16:31:19.096772 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6362 16:31:19.100122 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6363 16:31:19.103607 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6364 16:31:19.110179 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6365 16:31:19.110248 ==
6366 16:31:19.113756 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 16:31:19.116543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 16:31:19.116656 ==
6369 16:31:19.116736 DQS Delay:
6370 16:31:19.119972 DQS0 = 59, DQS1 = 59
6371 16:31:19.120071 DQM Delay:
6372 16:31:19.123395 DQM0 = 18, DQM1 = 9
6373 16:31:19.123471 DQ Delay:
6374 16:31:19.126671 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6375 16:31:19.129976 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6376 16:31:19.133333 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6377 16:31:19.136531 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6378 16:31:19.136623
6379 16:31:19.136753
6380 16:31:19.136835 ==
6381 16:31:19.140336 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 16:31:19.143388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 16:31:19.143466 ==
6384 16:31:19.143525
6385 16:31:19.143580
6386 16:31:19.146649 TX Vref Scan disable
6387 16:31:19.146726 == TX Byte 0 ==
6388 16:31:19.153415 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 16:31:19.156517 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 16:31:19.156597 == TX Byte 1 ==
6391 16:31:19.163394 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 16:31:19.166202 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 16:31:19.166277 ==
6394 16:31:19.169480 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 16:31:19.173330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 16:31:19.173407 ==
6397 16:31:19.173470
6398 16:31:19.173535
6399 16:31:19.176712 TX Vref Scan disable
6400 16:31:19.179379 == TX Byte 0 ==
6401 16:31:19.182800 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 16:31:19.186133 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 16:31:19.189344 == TX Byte 1 ==
6404 16:31:19.192753 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 16:31:19.196092 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 16:31:19.196167
6407 16:31:19.196225 [DATLAT]
6408 16:31:19.199214 Freq=400, CH0 RK0
6409 16:31:19.199292
6410 16:31:19.199351 DATLAT Default: 0xf
6411 16:31:19.202482 0, 0xFFFF, sum = 0
6412 16:31:19.205916 1, 0xFFFF, sum = 0
6413 16:31:19.205996 2, 0xFFFF, sum = 0
6414 16:31:19.209307 3, 0xFFFF, sum = 0
6415 16:31:19.209385 4, 0xFFFF, sum = 0
6416 16:31:19.212583 5, 0xFFFF, sum = 0
6417 16:31:19.212697 6, 0xFFFF, sum = 0
6418 16:31:19.215900 7, 0xFFFF, sum = 0
6419 16:31:19.215997 8, 0xFFFF, sum = 0
6420 16:31:19.219385 9, 0xFFFF, sum = 0
6421 16:31:19.219466 10, 0xFFFF, sum = 0
6422 16:31:19.222762 11, 0xFFFF, sum = 0
6423 16:31:19.222839 12, 0xFFFF, sum = 0
6424 16:31:19.225441 13, 0x0, sum = 1
6425 16:31:19.225519 14, 0x0, sum = 2
6426 16:31:19.228915 15, 0x0, sum = 3
6427 16:31:19.228992 16, 0x0, sum = 4
6428 16:31:19.232256 best_step = 14
6429 16:31:19.232332
6430 16:31:19.232391 ==
6431 16:31:19.235603 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 16:31:19.239106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 16:31:19.239243 ==
6434 16:31:19.242413 RX Vref Scan: 1
6435 16:31:19.242524
6436 16:31:19.242618 RX Vref 0 -> 0, step: 1
6437 16:31:19.242700
6438 16:31:19.245677 RX Delay -359 -> 252, step: 8
6439 16:31:19.245766
6440 16:31:19.248986 Set Vref, RX VrefLevel [Byte0]: 59
6441 16:31:19.252215 [Byte1]: 53
6442 16:31:19.256715
6443 16:31:19.256790 Final RX Vref Byte 0 = 59 to rank0
6444 16:31:19.260374 Final RX Vref Byte 1 = 53 to rank0
6445 16:31:19.263422 Final RX Vref Byte 0 = 59 to rank1
6446 16:31:19.266416 Final RX Vref Byte 1 = 53 to rank1==
6447 16:31:19.269833 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 16:31:19.276465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 16:31:19.276543 ==
6450 16:31:19.276602 DQS Delay:
6451 16:31:19.279818 DQS0 = 60, DQS1 = 68
6452 16:31:19.279893 DQM Delay:
6453 16:31:19.279951 DQM0 = 15, DQM1 = 13
6454 16:31:19.283281 DQ Delay:
6455 16:31:19.286885 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6456 16:31:19.289694 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6457 16:31:19.289771 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6458 16:31:19.296350 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6459 16:31:19.296425
6460 16:31:19.296482
6461 16:31:19.303034 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d8c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6462 16:31:19.306283 CH0 RK0: MR19=C0C, MR18=8D8C
6463 16:31:19.313359 CH0_RK0: MR19=0xC0C, MR18=0x8D8C, DQSOSC=392, MR23=63, INC=384, DEC=256
6464 16:31:19.313435 ==
6465 16:31:19.316084 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 16:31:19.319473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 16:31:19.319549 ==
6468 16:31:19.323289 [Gating] SW mode calibration
6469 16:31:19.329575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6470 16:31:19.336406 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6471 16:31:19.339929 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 16:31:19.342754 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6473 16:31:19.349450 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 16:31:19.352680 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 16:31:19.356061 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 16:31:19.363005 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 16:31:19.366386 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 16:31:19.369606 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 16:31:19.375905 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 16:31:19.375986 Total UI for P1: 0, mck2ui 16
6481 16:31:19.379227 best dqsien dly found for B0: ( 0, 14, 24)
6482 16:31:19.382571 Total UI for P1: 0, mck2ui 16
6483 16:31:19.385897 best dqsien dly found for B1: ( 0, 14, 24)
6484 16:31:19.392911 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6485 16:31:19.396297 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6486 16:31:19.396375
6487 16:31:19.399665 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 16:31:19.403060 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6489 16:31:19.406398 [Gating] SW calibration Done
6490 16:31:19.406476 ==
6491 16:31:19.409712 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 16:31:19.413230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 16:31:19.413308 ==
6494 16:31:19.415921 RX Vref Scan: 0
6495 16:31:19.415997
6496 16:31:19.416057 RX Vref 0 -> 0, step: 1
6497 16:31:19.416112
6498 16:31:19.419617 RX Delay -410 -> 252, step: 16
6499 16:31:19.422647 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6500 16:31:19.429680 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6501 16:31:19.432427 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6502 16:31:19.435781 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6503 16:31:19.442722 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6504 16:31:19.445493 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6505 16:31:19.448878 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6506 16:31:19.452221 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6507 16:31:19.455705 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6508 16:31:19.462521 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6509 16:31:19.465454 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6510 16:31:19.469382 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6511 16:31:19.475465 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6512 16:31:19.478675 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6513 16:31:19.482479 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6514 16:31:19.485558 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6515 16:31:19.485694 ==
6516 16:31:19.489302 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 16:31:19.495752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 16:31:19.495835 ==
6519 16:31:19.495928 DQS Delay:
6520 16:31:19.499188 DQS0 = 59, DQS1 = 59
6521 16:31:19.499282 DQM Delay:
6522 16:31:19.501900 DQM0 = 16, DQM1 = 10
6523 16:31:19.501976 DQ Delay:
6524 16:31:19.505199 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6525 16:31:19.508592 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6526 16:31:19.512246 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6527 16:31:19.515640 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6528 16:31:19.515724
6529 16:31:19.515809
6530 16:31:19.515865 ==
6531 16:31:19.519057 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 16:31:19.521916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 16:31:19.521994 ==
6534 16:31:19.522069
6535 16:31:19.522128
6536 16:31:19.525263 TX Vref Scan disable
6537 16:31:19.525339 == TX Byte 0 ==
6538 16:31:19.531672 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6539 16:31:19.535265 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6540 16:31:19.535344 == TX Byte 1 ==
6541 16:31:19.542028 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6542 16:31:19.545502 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6543 16:31:19.545608 ==
6544 16:31:19.549000 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 16:31:19.551810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 16:31:19.551888 ==
6547 16:31:19.551947
6548 16:31:19.552034
6549 16:31:19.555370 TX Vref Scan disable
6550 16:31:19.555464 == TX Byte 0 ==
6551 16:31:19.561940 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6552 16:31:19.565359 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6553 16:31:19.565429 == TX Byte 1 ==
6554 16:31:19.572098 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6555 16:31:19.575501 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6556 16:31:19.575569
6557 16:31:19.575624 [DATLAT]
6558 16:31:19.578297 Freq=400, CH0 RK1
6559 16:31:19.578362
6560 16:31:19.578416 DATLAT Default: 0xe
6561 16:31:19.581681 0, 0xFFFF, sum = 0
6562 16:31:19.581751 1, 0xFFFF, sum = 0
6563 16:31:19.584909 2, 0xFFFF, sum = 0
6564 16:31:19.584972 3, 0xFFFF, sum = 0
6565 16:31:19.588195 4, 0xFFFF, sum = 0
6566 16:31:19.588267 5, 0xFFFF, sum = 0
6567 16:31:19.591510 6, 0xFFFF, sum = 0
6568 16:31:19.591576 7, 0xFFFF, sum = 0
6569 16:31:19.594837 8, 0xFFFF, sum = 0
6570 16:31:19.594910 9, 0xFFFF, sum = 0
6571 16:31:19.597991 10, 0xFFFF, sum = 0
6572 16:31:19.601397 11, 0xFFFF, sum = 0
6573 16:31:19.601477 12, 0xFFFF, sum = 0
6574 16:31:19.605312 13, 0x0, sum = 1
6575 16:31:19.605416 14, 0x0, sum = 2
6576 16:31:19.605507 15, 0x0, sum = 3
6577 16:31:19.608039 16, 0x0, sum = 4
6578 16:31:19.608118 best_step = 14
6579 16:31:19.608178
6580 16:31:19.611403 ==
6581 16:31:19.611481 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 16:31:19.618446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 16:31:19.618526 ==
6584 16:31:19.618587 RX Vref Scan: 0
6585 16:31:19.618643
6586 16:31:19.621216 RX Vref 0 -> 0, step: 1
6587 16:31:19.621294
6588 16:31:19.624640 RX Delay -359 -> 252, step: 8
6589 16:31:19.631483 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6590 16:31:19.635036 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6591 16:31:19.638405 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6592 16:31:19.644940 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6593 16:31:19.648034 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6594 16:31:19.651637 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6595 16:31:19.654518 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6596 16:31:19.661413 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6597 16:31:19.664718 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6598 16:31:19.667990 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6599 16:31:19.671407 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6600 16:31:19.677997 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6601 16:31:19.681457 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6602 16:31:19.684325 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6603 16:31:19.687971 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6604 16:31:19.694638 iDelay=217, Bit 15, Center -52 (-303 ~ 200) 504
6605 16:31:19.694712 ==
6606 16:31:19.697993 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 16:31:19.700711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 16:31:19.700816 ==
6609 16:31:19.700901 DQS Delay:
6610 16:31:19.704555 DQS0 = 60, DQS1 = 72
6611 16:31:19.704631 DQM Delay:
6612 16:31:19.707827 DQM0 = 11, DQM1 = 16
6613 16:31:19.707900 DQ Delay:
6614 16:31:19.710991 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6615 16:31:19.714182 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6616 16:31:19.717230 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6617 16:31:19.720486 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =20
6618 16:31:19.720587
6619 16:31:19.720699
6620 16:31:19.727395 [DQSOSCAuto] RK1, (LSB)MR18= 0xcd84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6621 16:31:19.730742 CH0 RK1: MR19=C0C, MR18=CD84
6622 16:31:19.736921 CH0_RK1: MR19=0xC0C, MR18=0xCD84, DQSOSC=384, MR23=63, INC=400, DEC=267
6623 16:31:19.740527 [RxdqsGatingPostProcess] freq 400
6624 16:31:19.747476 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6625 16:31:19.750854 best DQS0 dly(2T, 0.5T) = (0, 10)
6626 16:31:19.753586 best DQS1 dly(2T, 0.5T) = (0, 10)
6627 16:31:19.757394 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6628 16:31:19.760733 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6629 16:31:19.760822 best DQS0 dly(2T, 0.5T) = (0, 10)
6630 16:31:19.763922 best DQS1 dly(2T, 0.5T) = (0, 10)
6631 16:31:19.766936 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6632 16:31:19.770361 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6633 16:31:19.773535 Pre-setting of DQS Precalculation
6634 16:31:19.780397 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6635 16:31:19.780486 ==
6636 16:31:19.783751 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 16:31:19.787118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 16:31:19.787214 ==
6639 16:31:19.793612 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6640 16:31:19.800276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6641 16:31:19.803892 [CA 0] Center 36 (8~64) winsize 57
6642 16:31:19.803995 [CA 1] Center 36 (8~64) winsize 57
6643 16:31:19.806619 [CA 2] Center 36 (8~64) winsize 57
6644 16:31:19.809904 [CA 3] Center 36 (8~64) winsize 57
6645 16:31:19.813470 [CA 4] Center 36 (8~64) winsize 57
6646 16:31:19.817209 [CA 5] Center 36 (8~64) winsize 57
6647 16:31:19.817324
6648 16:31:19.819908 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6649 16:31:19.820023
6650 16:31:19.823328 [CATrainingPosCal] consider 1 rank data
6651 16:31:19.826589 u2DelayCellTimex100 = 270/100 ps
6652 16:31:19.829872 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 16:31:19.836890 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 16:31:19.839745 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 16:31:19.843372 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 16:31:19.846921 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 16:31:19.849676 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 16:31:19.849799
6659 16:31:19.853333 CA PerBit enable=1, Macro0, CA PI delay=36
6660 16:31:19.853450
6661 16:31:19.856280 [CBTSetCACLKResult] CA Dly = 36
6662 16:31:19.859765 CS Dly: 1 (0~32)
6663 16:31:19.859871 ==
6664 16:31:19.863427 Dram Type= 6, Freq= 0, CH_1, rank 1
6665 16:31:19.866248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 16:31:19.866355 ==
6667 16:31:19.873048 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6668 16:31:19.876478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6669 16:31:19.879919 [CA 0] Center 36 (8~64) winsize 57
6670 16:31:19.883389 [CA 1] Center 36 (8~64) winsize 57
6671 16:31:19.886020 [CA 2] Center 36 (8~64) winsize 57
6672 16:31:19.889644 [CA 3] Center 36 (8~64) winsize 57
6673 16:31:19.893160 [CA 4] Center 36 (8~64) winsize 57
6674 16:31:19.895940 [CA 5] Center 36 (8~64) winsize 57
6675 16:31:19.896056
6676 16:31:19.899509 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6677 16:31:19.899600
6678 16:31:19.902989 [CATrainingPosCal] consider 2 rank data
6679 16:31:19.906399 u2DelayCellTimex100 = 270/100 ps
6680 16:31:19.909910 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 16:31:19.913120 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 16:31:19.916420 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 16:31:19.919773 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 16:31:19.925926 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 16:31:19.929300 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 16:31:19.929374
6687 16:31:19.932488 CA PerBit enable=1, Macro0, CA PI delay=36
6688 16:31:19.932564
6689 16:31:19.935866 [CBTSetCACLKResult] CA Dly = 36
6690 16:31:19.935944 CS Dly: 1 (0~32)
6691 16:31:19.936004
6692 16:31:19.939141 ----->DramcWriteLeveling(PI) begin...
6693 16:31:19.939215 ==
6694 16:31:19.942552 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 16:31:19.949466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 16:31:19.949546 ==
6697 16:31:19.952943 Write leveling (Byte 0): 40 => 8
6698 16:31:19.955618 Write leveling (Byte 1): 40 => 8
6699 16:31:19.955686 DramcWriteLeveling(PI) end<-----
6700 16:31:19.955744
6701 16:31:19.959044 ==
6702 16:31:19.962515 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 16:31:19.965768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 16:31:19.965847 ==
6705 16:31:19.969286 [Gating] SW mode calibration
6706 16:31:19.975950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6707 16:31:19.978770 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6708 16:31:19.985566 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 16:31:19.988914 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6710 16:31:19.992535 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 16:31:19.998930 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 16:31:20.002320 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 16:31:20.005694 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 16:31:20.012423 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 16:31:20.015243 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 16:31:20.018553 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 16:31:20.021666 Total UI for P1: 0, mck2ui 16
6718 16:31:20.025184 best dqsien dly found for B0: ( 0, 14, 24)
6719 16:31:20.028641 Total UI for P1: 0, mck2ui 16
6720 16:31:20.032108 best dqsien dly found for B1: ( 0, 14, 24)
6721 16:31:20.035490 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6722 16:31:20.038766 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6723 16:31:20.041497
6724 16:31:20.044847 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 16:31:20.048190 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6726 16:31:20.051857 [Gating] SW calibration Done
6727 16:31:20.051937 ==
6728 16:31:20.055310 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 16:31:20.058768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 16:31:20.058860 ==
6731 16:31:20.058924 RX Vref Scan: 0
6732 16:31:20.058981
6733 16:31:20.061488 RX Vref 0 -> 0, step: 1
6734 16:31:20.061564
6735 16:31:20.065086 RX Delay -410 -> 252, step: 16
6736 16:31:20.068341 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6737 16:31:20.075148 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6738 16:31:20.077972 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6739 16:31:20.081459 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6740 16:31:20.084880 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6741 16:31:20.091264 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6742 16:31:20.094616 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6743 16:31:20.098023 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6744 16:31:20.101158 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6745 16:31:20.108137 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6746 16:31:20.111261 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6747 16:31:20.114437 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6748 16:31:20.117796 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6749 16:31:20.124606 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6750 16:31:20.128012 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6751 16:31:20.131202 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6752 16:31:20.131279 ==
6753 16:31:20.134624 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 16:31:20.141501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 16:31:20.141584 ==
6756 16:31:20.141647 DQS Delay:
6757 16:31:20.144284 DQS0 = 51, DQS1 = 67
6758 16:31:20.144357 DQM Delay:
6759 16:31:20.144415 DQM0 = 13, DQM1 = 20
6760 16:31:20.147541 DQ Delay:
6761 16:31:20.150922 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6762 16:31:20.151002 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6763 16:31:20.154340 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6764 16:31:20.157720 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6765 16:31:20.157807
6766 16:31:20.161019
6767 16:31:20.161104 ==
6768 16:31:20.164444 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 16:31:20.167996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 16:31:20.168076 ==
6771 16:31:20.168137
6772 16:31:20.168220
6773 16:31:20.171391 TX Vref Scan disable
6774 16:31:20.171469 == TX Byte 0 ==
6775 16:31:20.174670 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 16:31:20.181333 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 16:31:20.181413 == TX Byte 1 ==
6778 16:31:20.184126 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 16:31:20.191015 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 16:31:20.191118 ==
6781 16:31:20.194261 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 16:31:20.197429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 16:31:20.197505 ==
6784 16:31:20.197573
6785 16:31:20.197628
6786 16:31:20.201111 TX Vref Scan disable
6787 16:31:20.201187 == TX Byte 0 ==
6788 16:31:20.204448 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 16:31:20.210984 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 16:31:20.211061 == TX Byte 1 ==
6791 16:31:20.214338 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 16:31:20.220995 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 16:31:20.221073
6794 16:31:20.221141 [DATLAT]
6795 16:31:20.221198 Freq=400, CH1 RK0
6796 16:31:20.221251
6797 16:31:20.224062 DATLAT Default: 0xf
6798 16:31:20.227570 0, 0xFFFF, sum = 0
6799 16:31:20.227693 1, 0xFFFF, sum = 0
6800 16:31:20.231148 2, 0xFFFF, sum = 0
6801 16:31:20.231252 3, 0xFFFF, sum = 0
6802 16:31:20.234414 4, 0xFFFF, sum = 0
6803 16:31:20.234493 5, 0xFFFF, sum = 0
6804 16:31:20.237241 6, 0xFFFF, sum = 0
6805 16:31:20.237319 7, 0xFFFF, sum = 0
6806 16:31:20.240701 8, 0xFFFF, sum = 0
6807 16:31:20.240783 9, 0xFFFF, sum = 0
6808 16:31:20.244126 10, 0xFFFF, sum = 0
6809 16:31:20.244194 11, 0xFFFF, sum = 0
6810 16:31:20.247466 12, 0xFFFF, sum = 0
6811 16:31:20.247540 13, 0x0, sum = 1
6812 16:31:20.250777 14, 0x0, sum = 2
6813 16:31:20.250848 15, 0x0, sum = 3
6814 16:31:20.254235 16, 0x0, sum = 4
6815 16:31:20.254305 best_step = 14
6816 16:31:20.254362
6817 16:31:20.254432 ==
6818 16:31:20.257543 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 16:31:20.260911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 16:31:20.264372 ==
6821 16:31:20.264481 RX Vref Scan: 1
6822 16:31:20.264579
6823 16:31:20.267199 RX Vref 0 -> 0, step: 1
6824 16:31:20.267263
6825 16:31:20.270743 RX Delay -375 -> 252, step: 8
6826 16:31:20.270853
6827 16:31:20.274090 Set Vref, RX VrefLevel [Byte0]: 58
6828 16:31:20.277653 [Byte1]: 49
6829 16:31:20.277719
6830 16:31:20.280810 Final RX Vref Byte 0 = 58 to rank0
6831 16:31:20.284201 Final RX Vref Byte 1 = 49 to rank0
6832 16:31:20.287535 Final RX Vref Byte 0 = 58 to rank1
6833 16:31:20.290492 Final RX Vref Byte 1 = 49 to rank1==
6834 16:31:20.293991 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 16:31:20.297410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 16:31:20.297500 ==
6837 16:31:20.300736 DQS Delay:
6838 16:31:20.300823 DQS0 = 56, DQS1 = 64
6839 16:31:20.304129 DQM Delay:
6840 16:31:20.304205 DQM0 = 13, DQM1 = 10
6841 16:31:20.307300 DQ Delay:
6842 16:31:20.307372 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6843 16:31:20.310458 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6844 16:31:20.313593 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6845 16:31:20.317445 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6846 16:31:20.317550
6847 16:31:20.317627
6848 16:31:20.327215 [DQSOSCAuto] RK0, (LSB)MR18= 0x586c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6849 16:31:20.330440 CH1 RK0: MR19=C0C, MR18=586C
6850 16:31:20.336982 CH1_RK0: MR19=0xC0C, MR18=0x586C, DQSOSC=396, MR23=63, INC=376, DEC=251
6851 16:31:20.337080 ==
6852 16:31:20.340251 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 16:31:20.343509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 16:31:20.343623 ==
6855 16:31:20.346952 [Gating] SW mode calibration
6856 16:31:20.353687 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6857 16:31:20.356536 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6858 16:31:20.363355 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 16:31:20.366614 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6860 16:31:20.370071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 16:31:20.377134 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 16:31:20.379902 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 16:31:20.383207 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 16:31:20.389865 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 16:31:20.393713 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 16:31:20.397131 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 16:31:20.400470 Total UI for P1: 0, mck2ui 16
6868 16:31:20.403198 best dqsien dly found for B0: ( 0, 14, 24)
6869 16:31:20.406628 Total UI for P1: 0, mck2ui 16
6870 16:31:20.410155 best dqsien dly found for B1: ( 0, 14, 24)
6871 16:31:20.413499 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6872 16:31:20.416684 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6873 16:31:20.416783
6874 16:31:20.423120 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 16:31:20.426488 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6876 16:31:20.430198 [Gating] SW calibration Done
6877 16:31:20.430277 ==
6878 16:31:20.432927 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 16:31:20.436348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 16:31:20.436422 ==
6881 16:31:20.436482 RX Vref Scan: 0
6882 16:31:20.436575
6883 16:31:20.439488 RX Vref 0 -> 0, step: 1
6884 16:31:20.439562
6885 16:31:20.443398 RX Delay -410 -> 252, step: 16
6886 16:31:20.446161 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6887 16:31:20.452882 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6888 16:31:20.456260 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6889 16:31:20.459584 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6890 16:31:20.462976 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6891 16:31:20.469695 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6892 16:31:20.473008 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6893 16:31:20.476304 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6894 16:31:20.479165 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6895 16:31:20.486032 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6896 16:31:20.489498 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6897 16:31:20.492945 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6898 16:31:20.496293 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6899 16:31:20.502500 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6900 16:31:20.506086 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6901 16:31:20.509476 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6902 16:31:20.509588 ==
6903 16:31:20.512322 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 16:31:20.519232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 16:31:20.519308 ==
6906 16:31:20.519369 DQS Delay:
6907 16:31:20.522497 DQS0 = 59, DQS1 = 59
6908 16:31:20.522570 DQM Delay:
6909 16:31:20.522630 DQM0 = 19, DQM1 = 12
6910 16:31:20.525564 DQ Delay:
6911 16:31:20.528650 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6912 16:31:20.532011 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6913 16:31:20.532088 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6914 16:31:20.539209 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6915 16:31:20.539308
6916 16:31:20.539405
6917 16:31:20.539493 ==
6918 16:31:20.542283 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 16:31:20.545642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 16:31:20.545722 ==
6921 16:31:20.545812
6922 16:31:20.545884
6923 16:31:20.548768 TX Vref Scan disable
6924 16:31:20.548849 == TX Byte 0 ==
6925 16:31:20.551939 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6926 16:31:20.558685 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6927 16:31:20.558771 == TX Byte 1 ==
6928 16:31:20.562075 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6929 16:31:20.568782 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6930 16:31:20.568862 ==
6931 16:31:20.572249 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 16:31:20.575103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 16:31:20.575183 ==
6934 16:31:20.575284
6935 16:31:20.575369
6936 16:31:20.578435 TX Vref Scan disable
6937 16:31:20.578525 == TX Byte 0 ==
6938 16:31:20.585171 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6939 16:31:20.588733 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6940 16:31:20.588813 == TX Byte 1 ==
6941 16:31:20.594947 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6942 16:31:20.598335 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6943 16:31:20.598434
6944 16:31:20.598523 [DATLAT]
6945 16:31:20.601600 Freq=400, CH1 RK1
6946 16:31:20.601688
6947 16:31:20.601750 DATLAT Default: 0xe
6948 16:31:20.605178 0, 0xFFFF, sum = 0
6949 16:31:20.605262 1, 0xFFFF, sum = 0
6950 16:31:20.608586 2, 0xFFFF, sum = 0
6951 16:31:20.608675 3, 0xFFFF, sum = 0
6952 16:31:20.612044 4, 0xFFFF, sum = 0
6953 16:31:20.612124 5, 0xFFFF, sum = 0
6954 16:31:20.615504 6, 0xFFFF, sum = 0
6955 16:31:20.615580 7, 0xFFFF, sum = 0
6956 16:31:20.618379 8, 0xFFFF, sum = 0
6957 16:31:20.618449 9, 0xFFFF, sum = 0
6958 16:31:20.621868 10, 0xFFFF, sum = 0
6959 16:31:20.621939 11, 0xFFFF, sum = 0
6960 16:31:20.625359 12, 0xFFFF, sum = 0
6961 16:31:20.625427 13, 0x0, sum = 1
6962 16:31:20.628057 14, 0x0, sum = 2
6963 16:31:20.628124 15, 0x0, sum = 3
6964 16:31:20.631340 16, 0x0, sum = 4
6965 16:31:20.631407 best_step = 14
6966 16:31:20.631461
6967 16:31:20.631514 ==
6968 16:31:20.638178 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 16:31:20.641192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 16:31:20.641272 ==
6971 16:31:20.641332 RX Vref Scan: 0
6972 16:31:20.641388
6973 16:31:20.644480 RX Vref 0 -> 0, step: 1
6974 16:31:20.644584
6975 16:31:20.647581 RX Delay -359 -> 252, step: 8
6976 16:31:20.654690 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6977 16:31:20.658041 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6978 16:31:20.661611 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6979 16:31:20.664600 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6980 16:31:20.671310 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6981 16:31:20.674616 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6982 16:31:20.677997 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6983 16:31:20.681420 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6984 16:31:20.688051 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6985 16:31:20.691559 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6986 16:31:20.695028 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6987 16:31:20.697737 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6988 16:31:20.704387 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6989 16:31:20.707655 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6990 16:31:20.711071 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6991 16:31:20.717949 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6992 16:31:20.718039 ==
6993 16:31:20.721259 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 16:31:20.724711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 16:31:20.724787 ==
6996 16:31:20.724860 DQS Delay:
6997 16:31:20.727441 DQS0 = 60, DQS1 = 64
6998 16:31:20.727527 DQM Delay:
6999 16:31:20.730981 DQM0 = 12, DQM1 = 10
7000 16:31:20.731068 DQ Delay:
7001 16:31:20.734427 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7002 16:31:20.737896 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7003 16:31:20.741298 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7004 16:31:20.744058 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7005 16:31:20.744136
7006 16:31:20.744197
7007 16:31:20.751195 [DQSOSCAuto] RK1, (LSB)MR18= 0x82b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
7008 16:31:20.754363 CH1 RK1: MR19=C0C, MR18=82B1
7009 16:31:20.760811 CH1_RK1: MR19=0xC0C, MR18=0x82B1, DQSOSC=387, MR23=63, INC=394, DEC=262
7010 16:31:20.764586 [RxdqsGatingPostProcess] freq 400
7011 16:31:20.770980 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7012 16:31:20.771062 best DQS0 dly(2T, 0.5T) = (0, 10)
7013 16:31:20.774004 best DQS1 dly(2T, 0.5T) = (0, 10)
7014 16:31:20.777566 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7015 16:31:20.781062 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7016 16:31:20.784291 best DQS0 dly(2T, 0.5T) = (0, 10)
7017 16:31:20.787605 best DQS1 dly(2T, 0.5T) = (0, 10)
7018 16:31:20.790789 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7019 16:31:20.794029 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7020 16:31:20.797440 Pre-setting of DQS Precalculation
7021 16:31:20.804228 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7022 16:31:20.810861 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7023 16:31:20.817123 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7024 16:31:20.817206
7025 16:31:20.817268
7026 16:31:20.820529 [Calibration Summary] 800 Mbps
7027 16:31:20.820603 CH 0, Rank 0
7028 16:31:20.824027 SW Impedance : PASS
7029 16:31:20.827553 DUTY Scan : NO K
7030 16:31:20.827653 ZQ Calibration : PASS
7031 16:31:20.830381 Jitter Meter : NO K
7032 16:31:20.833845 CBT Training : PASS
7033 16:31:20.833941 Write leveling : PASS
7034 16:31:20.837336 RX DQS gating : PASS
7035 16:31:20.837407 RX DQ/DQS(RDDQC) : PASS
7036 16:31:20.840677 TX DQ/DQS : PASS
7037 16:31:20.843448 RX DATLAT : PASS
7038 16:31:20.843542 RX DQ/DQS(Engine): PASS
7039 16:31:20.847001 TX OE : NO K
7040 16:31:20.847096 All Pass.
7041 16:31:20.847184
7042 16:31:20.850306 CH 0, Rank 1
7043 16:31:20.850397 SW Impedance : PASS
7044 16:31:20.853436 DUTY Scan : NO K
7045 16:31:20.856867 ZQ Calibration : PASS
7046 16:31:20.856974 Jitter Meter : NO K
7047 16:31:20.860208 CBT Training : PASS
7048 16:31:20.863575 Write leveling : NO K
7049 16:31:20.863675 RX DQS gating : PASS
7050 16:31:20.866943 RX DQ/DQS(RDDQC) : PASS
7051 16:31:20.870116 TX DQ/DQS : PASS
7052 16:31:20.870220 RX DATLAT : PASS
7053 16:31:20.873151 RX DQ/DQS(Engine): PASS
7054 16:31:20.876872 TX OE : NO K
7055 16:31:20.876956 All Pass.
7056 16:31:20.877046
7057 16:31:20.877138 CH 1, Rank 0
7058 16:31:20.880117 SW Impedance : PASS
7059 16:31:20.883527 DUTY Scan : NO K
7060 16:31:20.883606 ZQ Calibration : PASS
7061 16:31:20.886711 Jitter Meter : NO K
7062 16:31:20.889984 CBT Training : PASS
7063 16:31:20.890085 Write leveling : PASS
7064 16:31:20.893099 RX DQS gating : PASS
7065 16:31:20.896933 RX DQ/DQS(RDDQC) : PASS
7066 16:31:20.897025 TX DQ/DQS : PASS
7067 16:31:20.900210 RX DATLAT : PASS
7068 16:31:20.900317 RX DQ/DQS(Engine): PASS
7069 16:31:20.902910 TX OE : NO K
7070 16:31:20.903008 All Pass.
7071 16:31:20.903096
7072 16:31:20.906359 CH 1, Rank 1
7073 16:31:20.906461 SW Impedance : PASS
7074 16:31:20.909676 DUTY Scan : NO K
7075 16:31:20.913066 ZQ Calibration : PASS
7076 16:31:20.913146 Jitter Meter : NO K
7077 16:31:20.916515 CBT Training : PASS
7078 16:31:20.919994 Write leveling : NO K
7079 16:31:20.920099 RX DQS gating : PASS
7080 16:31:20.922943 RX DQ/DQS(RDDQC) : PASS
7081 16:31:20.926322 TX DQ/DQS : PASS
7082 16:31:20.926403 RX DATLAT : PASS
7083 16:31:20.929782 RX DQ/DQS(Engine): PASS
7084 16:31:20.933369 TX OE : NO K
7085 16:31:20.933510 All Pass.
7086 16:31:20.933633
7087 16:31:20.936671 DramC Write-DBI off
7088 16:31:20.936792 PER_BANK_REFRESH: Hybrid Mode
7089 16:31:20.939477 TX_TRACKING: ON
7090 16:31:20.946107 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7091 16:31:20.953073 [FAST_K] Save calibration result to emmc
7092 16:31:20.956306 dramc_set_vcore_voltage set vcore to 725000
7093 16:31:20.956422 Read voltage for 1600, 0
7094 16:31:20.959571 Vio18 = 0
7095 16:31:20.959671 Vcore = 725000
7096 16:31:20.959758 Vdram = 0
7097 16:31:20.962848 Vddq = 0
7098 16:31:20.962917 Vmddr = 0
7099 16:31:20.966113 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7100 16:31:20.973058 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7101 16:31:20.976183 MEM_TYPE=3, freq_sel=13
7102 16:31:20.979446 sv_algorithm_assistance_LP4_3733
7103 16:31:20.982652 ============ PULL DRAM RESETB DOWN ============
7104 16:31:20.986441 ========== PULL DRAM RESETB DOWN end =========
7105 16:31:20.992565 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7106 16:31:20.995784 ===================================
7107 16:31:20.995868 LPDDR4 DRAM CONFIGURATION
7108 16:31:20.999033 ===================================
7109 16:31:21.002891 EX_ROW_EN[0] = 0x0
7110 16:31:21.002972 EX_ROW_EN[1] = 0x0
7111 16:31:21.005942 LP4Y_EN = 0x0
7112 16:31:21.006052 WORK_FSP = 0x1
7113 16:31:21.008919 WL = 0x5
7114 16:31:21.012914 RL = 0x5
7115 16:31:21.012991 BL = 0x2
7116 16:31:21.016074 RPST = 0x0
7117 16:31:21.016173 RD_PRE = 0x0
7118 16:31:21.019281 WR_PRE = 0x1
7119 16:31:21.019385 WR_PST = 0x1
7120 16:31:21.022662 DBI_WR = 0x0
7121 16:31:21.022741 DBI_RD = 0x0
7122 16:31:21.025505 OTF = 0x1
7123 16:31:21.028961 ===================================
7124 16:31:21.032661 ===================================
7125 16:31:21.032764 ANA top config
7126 16:31:21.035513 ===================================
7127 16:31:21.038929 DLL_ASYNC_EN = 0
7128 16:31:21.042422 ALL_SLAVE_EN = 0
7129 16:31:21.042497 NEW_RANK_MODE = 1
7130 16:31:21.045286 DLL_IDLE_MODE = 1
7131 16:31:21.048609 LP45_APHY_COMB_EN = 1
7132 16:31:21.052093 TX_ODT_DIS = 0
7133 16:31:21.055493 NEW_8X_MODE = 1
7134 16:31:21.058970 ===================================
7135 16:31:21.062401 ===================================
7136 16:31:21.062520 data_rate = 3200
7137 16:31:21.065176 CKR = 1
7138 16:31:21.068497 DQ_P2S_RATIO = 8
7139 16:31:21.072360 ===================================
7140 16:31:21.075146 CA_P2S_RATIO = 8
7141 16:31:21.078560 DQ_CA_OPEN = 0
7142 16:31:21.082120 DQ_SEMI_OPEN = 0
7143 16:31:21.082217 CA_SEMI_OPEN = 0
7144 16:31:21.085350 CA_FULL_RATE = 0
7145 16:31:21.088648 DQ_CKDIV4_EN = 0
7146 16:31:21.092007 CA_CKDIV4_EN = 0
7147 16:31:21.095239 CA_PREDIV_EN = 0
7148 16:31:21.099069 PH8_DLY = 12
7149 16:31:21.099147 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7150 16:31:21.102070 DQ_AAMCK_DIV = 4
7151 16:31:21.105367 CA_AAMCK_DIV = 4
7152 16:31:21.108733 CA_ADMCK_DIV = 4
7153 16:31:21.112102 DQ_TRACK_CA_EN = 0
7154 16:31:21.115353 CA_PICK = 1600
7155 16:31:21.118502 CA_MCKIO = 1600
7156 16:31:21.118600 MCKIO_SEMI = 0
7157 16:31:21.121975 PLL_FREQ = 3068
7158 16:31:21.124927 DQ_UI_PI_RATIO = 32
7159 16:31:21.128515 CA_UI_PI_RATIO = 0
7160 16:31:21.131494 ===================================
7161 16:31:21.135129 ===================================
7162 16:31:21.138393 memory_type:LPDDR4
7163 16:31:21.138468 GP_NUM : 10
7164 16:31:21.141788 SRAM_EN : 1
7165 16:31:21.145304 MD32_EN : 0
7166 16:31:21.148031 ===================================
7167 16:31:21.148142 [ANA_INIT] >>>>>>>>>>>>>>
7168 16:31:21.151416 <<<<<< [CONFIGURE PHASE]: ANA_TX
7169 16:31:21.154911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7170 16:31:21.158412 ===================================
7171 16:31:21.161735 data_rate = 3200,PCW = 0X7600
7172 16:31:21.165201 ===================================
7173 16:31:21.168554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7174 16:31:21.175255 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 16:31:21.177906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7176 16:31:21.184885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7177 16:31:21.188262 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7178 16:31:21.191445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7179 16:31:21.191525 [ANA_INIT] flow start
7180 16:31:21.194712 [ANA_INIT] PLL >>>>>>>>
7181 16:31:21.198061 [ANA_INIT] PLL <<<<<<<<
7182 16:31:21.201327 [ANA_INIT] MIDPI >>>>>>>>
7183 16:31:21.201436 [ANA_INIT] MIDPI <<<<<<<<
7184 16:31:21.204708 [ANA_INIT] DLL >>>>>>>>
7185 16:31:21.208075 [ANA_INIT] DLL <<<<<<<<
7186 16:31:21.208188 [ANA_INIT] flow end
7187 16:31:21.211160 ============ LP4 DIFF to SE enter ============
7188 16:31:21.218173 ============ LP4 DIFF to SE exit ============
7189 16:31:21.218280 [ANA_INIT] <<<<<<<<<<<<<
7190 16:31:21.220988 [Flow] Enable top DCM control >>>>>
7191 16:31:21.224362 [Flow] Enable top DCM control <<<<<
7192 16:31:21.227793 Enable DLL master slave shuffle
7193 16:31:21.234273 ==============================================================
7194 16:31:21.234422 Gating Mode config
7195 16:31:21.241003 ==============================================================
7196 16:31:21.244461 Config description:
7197 16:31:21.254290 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7198 16:31:21.260987 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7199 16:31:21.264290 SELPH_MODE 0: By rank 1: By Phase
7200 16:31:21.270904 ==============================================================
7201 16:31:21.274469 GAT_TRACK_EN = 1
7202 16:31:21.277790 RX_GATING_MODE = 2
7203 16:31:21.277904 RX_GATING_TRACK_MODE = 2
7204 16:31:21.281182 SELPH_MODE = 1
7205 16:31:21.283989 PICG_EARLY_EN = 1
7206 16:31:21.287422 VALID_LAT_VALUE = 1
7207 16:31:21.294293 ==============================================================
7208 16:31:21.297747 Enter into Gating configuration >>>>
7209 16:31:21.301021 Exit from Gating configuration <<<<
7210 16:31:21.304352 Enter into DVFS_PRE_config >>>>>
7211 16:31:21.314094 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7212 16:31:21.317473 Exit from DVFS_PRE_config <<<<<
7213 16:31:21.320791 Enter into PICG configuration >>>>
7214 16:31:21.323996 Exit from PICG configuration <<<<
7215 16:31:21.327261 [RX_INPUT] configuration >>>>>
7216 16:31:21.330760 [RX_INPUT] configuration <<<<<
7217 16:31:21.334207 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7218 16:31:21.340951 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7219 16:31:21.347723 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7220 16:31:21.350939 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7221 16:31:21.357288 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7222 16:31:21.363884 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7223 16:31:21.367514 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7224 16:31:21.374230 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7225 16:31:21.377456 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7226 16:31:21.380805 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7227 16:31:21.383609 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7228 16:31:21.390468 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7229 16:31:21.393709 ===================================
7230 16:31:21.393790 LPDDR4 DRAM CONFIGURATION
7231 16:31:21.397183 ===================================
7232 16:31:21.399961 EX_ROW_EN[0] = 0x0
7233 16:31:21.403392 EX_ROW_EN[1] = 0x0
7234 16:31:21.403514 LP4Y_EN = 0x0
7235 16:31:21.406680 WORK_FSP = 0x1
7236 16:31:21.406761 WL = 0x5
7237 16:31:21.410110 RL = 0x5
7238 16:31:21.410255 BL = 0x2
7239 16:31:21.413683 RPST = 0x0
7240 16:31:21.413768 RD_PRE = 0x0
7241 16:31:21.417083 WR_PRE = 0x1
7242 16:31:21.417153 WR_PST = 0x1
7243 16:31:21.420460 DBI_WR = 0x0
7244 16:31:21.420556 DBI_RD = 0x0
7245 16:31:21.423798 OTF = 0x1
7246 16:31:21.426568 ===================================
7247 16:31:21.429970 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7248 16:31:21.433087 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7249 16:31:21.439840 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7250 16:31:21.443222 ===================================
7251 16:31:21.443305 LPDDR4 DRAM CONFIGURATION
7252 16:31:21.446676 ===================================
7253 16:31:21.450119 EX_ROW_EN[0] = 0x10
7254 16:31:21.453460 EX_ROW_EN[1] = 0x0
7255 16:31:21.453543 LP4Y_EN = 0x0
7256 16:31:21.456765 WORK_FSP = 0x1
7257 16:31:21.456836 WL = 0x5
7258 16:31:21.459470 RL = 0x5
7259 16:31:21.459568 BL = 0x2
7260 16:31:21.463363 RPST = 0x0
7261 16:31:21.463471 RD_PRE = 0x0
7262 16:31:21.466721 WR_PRE = 0x1
7263 16:31:21.466801 WR_PST = 0x1
7264 16:31:21.469387 DBI_WR = 0x0
7265 16:31:21.469481 DBI_RD = 0x0
7266 16:31:21.473229 OTF = 0x1
7267 16:31:21.476410 ===================================
7268 16:31:21.482718 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7269 16:31:21.482830 ==
7270 16:31:21.486449 Dram Type= 6, Freq= 0, CH_0, rank 0
7271 16:31:21.489745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7272 16:31:21.489819 ==
7273 16:31:21.492946 [Duty_Offset_Calibration]
7274 16:31:21.493018 B0:2 B1:0 CA:3
7275 16:31:21.493077
7276 16:31:21.496000 [DutyScan_Calibration_Flow] k_type=0
7277 16:31:21.506670
7278 16:31:21.506748 ==CLK 0==
7279 16:31:21.510125 Final CLK duty delay cell = 0
7280 16:31:21.513435 [0] MAX Duty = 5031%(X100), DQS PI = 12
7281 16:31:21.516988 [0] MIN Duty = 4907%(X100), DQS PI = 6
7282 16:31:21.517064 [0] AVG Duty = 4969%(X100)
7283 16:31:21.520305
7284 16:31:21.523702 CH0 CLK Duty spec in!! Max-Min= 124%
7285 16:31:21.527113 [DutyScan_Calibration_Flow] ====Done====
7286 16:31:21.527211
7287 16:31:21.529892 [DutyScan_Calibration_Flow] k_type=1
7288 16:31:21.546673
7289 16:31:21.546786 ==DQS 0 ==
7290 16:31:21.550029 Final DQS duty delay cell = 0
7291 16:31:21.553432 [0] MAX Duty = 5094%(X100), DQS PI = 30
7292 16:31:21.556305 [0] MIN Duty = 4875%(X100), DQS PI = 48
7293 16:31:21.559653 [0] AVG Duty = 4984%(X100)
7294 16:31:21.559760
7295 16:31:21.559851 ==DQS 1 ==
7296 16:31:21.563055 Final DQS duty delay cell = 0
7297 16:31:21.566434 [0] MAX Duty = 5156%(X100), DQS PI = 30
7298 16:31:21.569857 [0] MIN Duty = 5031%(X100), DQS PI = 14
7299 16:31:21.573157 [0] AVG Duty = 5093%(X100)
7300 16:31:21.573238
7301 16:31:21.576443 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7302 16:31:21.576540
7303 16:31:21.579940 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7304 16:31:21.583278 [DutyScan_Calibration_Flow] ====Done====
7305 16:31:21.583382
7306 16:31:21.586531 [DutyScan_Calibration_Flow] k_type=3
7307 16:31:21.604621
7308 16:31:21.604723 ==DQM 0 ==
7309 16:31:21.607716 Final DQM duty delay cell = 0
7310 16:31:21.611100 [0] MAX Duty = 5156%(X100), DQS PI = 28
7311 16:31:21.614242 [0] MIN Duty = 4844%(X100), DQS PI = 52
7312 16:31:21.617483 [0] AVG Duty = 5000%(X100)
7313 16:31:21.617573
7314 16:31:21.617665 ==DQM 1 ==
7315 16:31:21.621023 Final DQM duty delay cell = 4
7316 16:31:21.624459 [4] MAX Duty = 5187%(X100), DQS PI = 62
7317 16:31:21.627876 [4] MIN Duty = 5000%(X100), DQS PI = 40
7318 16:31:21.631296 [4] AVG Duty = 5093%(X100)
7319 16:31:21.631397
7320 16:31:21.634113 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7321 16:31:21.634221
7322 16:31:21.637665 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7323 16:31:21.641118 [DutyScan_Calibration_Flow] ====Done====
7324 16:31:21.641198
7325 16:31:21.644466 [DutyScan_Calibration_Flow] k_type=2
7326 16:31:21.660947
7327 16:31:21.661046 ==DQ 0 ==
7328 16:31:21.664297 Final DQ duty delay cell = -4
7329 16:31:21.667637 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7330 16:31:21.670327 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7331 16:31:21.674243 [-4] AVG Duty = 4938%(X100)
7332 16:31:21.674350
7333 16:31:21.674436 ==DQ 1 ==
7334 16:31:21.677548 Final DQ duty delay cell = 0
7335 16:31:21.680265 [0] MAX Duty = 5156%(X100), DQS PI = 60
7336 16:31:21.683728 [0] MIN Duty = 5000%(X100), DQS PI = 16
7337 16:31:21.687071 [0] AVG Duty = 5078%(X100)
7338 16:31:21.687157
7339 16:31:21.690396 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7340 16:31:21.690506
7341 16:31:21.693758 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7342 16:31:21.697002 [DutyScan_Calibration_Flow] ====Done====
7343 16:31:21.697127 ==
7344 16:31:21.700410 Dram Type= 6, Freq= 0, CH_1, rank 0
7345 16:31:21.703960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7346 16:31:21.704049 ==
7347 16:31:21.706660 [Duty_Offset_Calibration]
7348 16:31:21.706735 B0:1 B1:-2 CA:1
7349 16:31:21.706792
7350 16:31:21.709945 [DutyScan_Calibration_Flow] k_type=0
7351 16:31:21.721251
7352 16:31:21.721326 ==CLK 0==
7353 16:31:21.724433 Final CLK duty delay cell = 0
7354 16:31:21.727717 [0] MAX Duty = 5062%(X100), DQS PI = 20
7355 16:31:21.731150 [0] MIN Duty = 4813%(X100), DQS PI = 60
7356 16:31:21.734490 [0] AVG Duty = 4937%(X100)
7357 16:31:21.734587
7358 16:31:21.737308 CH1 CLK Duty spec in!! Max-Min= 249%
7359 16:31:21.740716 [DutyScan_Calibration_Flow] ====Done====
7360 16:31:21.740806
7361 16:31:21.744191 [DutyScan_Calibration_Flow] k_type=1
7362 16:31:21.760788
7363 16:31:21.760888 ==DQS 0 ==
7364 16:31:21.764071 Final DQS duty delay cell = 0
7365 16:31:21.767505 [0] MAX Duty = 5187%(X100), DQS PI = 24
7366 16:31:21.770896 [0] MIN Duty = 5031%(X100), DQS PI = 52
7367 16:31:21.774164 [0] AVG Duty = 5109%(X100)
7368 16:31:21.774238
7369 16:31:21.774297 ==DQS 1 ==
7370 16:31:21.777562 Final DQS duty delay cell = 0
7371 16:31:21.780987 [0] MAX Duty = 5093%(X100), DQS PI = 62
7372 16:31:21.783889 [0] MIN Duty = 4844%(X100), DQS PI = 24
7373 16:31:21.787326 [0] AVG Duty = 4968%(X100)
7374 16:31:21.787450
7375 16:31:21.790650 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7376 16:31:21.790730
7377 16:31:21.794005 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7378 16:31:21.797208 [DutyScan_Calibration_Flow] ====Done====
7379 16:31:21.797305
7380 16:31:21.800455 [DutyScan_Calibration_Flow] k_type=3
7381 16:31:21.817713
7382 16:31:21.817800 ==DQM 0 ==
7383 16:31:21.820991 Final DQM duty delay cell = 0
7384 16:31:21.824275 [0] MAX Duty = 5031%(X100), DQS PI = 26
7385 16:31:21.827564 [0] MIN Duty = 4813%(X100), DQS PI = 56
7386 16:31:21.830745 [0] AVG Duty = 4922%(X100)
7387 16:31:21.830838
7388 16:31:21.830923 ==DQM 1 ==
7389 16:31:21.834064 Final DQM duty delay cell = 0
7390 16:31:21.837236 [0] MAX Duty = 5062%(X100), DQS PI = 34
7391 16:31:21.840515 [0] MIN Duty = 4875%(X100), DQS PI = 26
7392 16:31:21.843971 [0] AVG Duty = 4968%(X100)
7393 16:31:21.844042
7394 16:31:21.847618 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7395 16:31:21.847683
7396 16:31:21.850888 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7397 16:31:21.854256 [DutyScan_Calibration_Flow] ====Done====
7398 16:31:21.854373
7399 16:31:21.857013 [DutyScan_Calibration_Flow] k_type=2
7400 16:31:21.874730
7401 16:31:21.874829 ==DQ 0 ==
7402 16:31:21.877941 Final DQ duty delay cell = 0
7403 16:31:21.881264 [0] MAX Duty = 5093%(X100), DQS PI = 20
7404 16:31:21.884602 [0] MIN Duty = 4907%(X100), DQS PI = 62
7405 16:31:21.884723 [0] AVG Duty = 5000%(X100)
7406 16:31:21.887883
7407 16:31:21.887956 ==DQ 1 ==
7408 16:31:21.891296 Final DQ duty delay cell = 0
7409 16:31:21.894663 [0] MAX Duty = 5125%(X100), DQS PI = 34
7410 16:31:21.898044 [0] MIN Duty = 4969%(X100), DQS PI = 24
7411 16:31:21.898160 [0] AVG Duty = 5047%(X100)
7412 16:31:21.898254
7413 16:31:21.904424 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7414 16:31:21.904526
7415 16:31:21.907659 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7416 16:31:21.910956 [DutyScan_Calibration_Flow] ====Done====
7417 16:31:21.914338 nWR fixed to 30
7418 16:31:21.914419 [ModeRegInit_LP4] CH0 RK0
7419 16:31:21.917772 [ModeRegInit_LP4] CH0 RK1
7420 16:31:21.921213 [ModeRegInit_LP4] CH1 RK0
7421 16:31:21.924547 [ModeRegInit_LP4] CH1 RK1
7422 16:31:21.924656 match AC timing 5
7423 16:31:21.927757 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7424 16:31:21.934556 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7425 16:31:21.937373 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7426 16:31:21.944056 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7427 16:31:21.947369 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7428 16:31:21.947478 [MiockJmeterHQA]
7429 16:31:21.947586
7430 16:31:21.950490 [DramcMiockJmeter] u1RxGatingPI = 0
7431 16:31:21.954038 0 : 4257, 4030
7432 16:31:21.954151 4 : 4368, 4142
7433 16:31:21.957412 8 : 4365, 4140
7434 16:31:21.957488 12 : 4255, 4029
7435 16:31:21.957563 16 : 4257, 4029
7436 16:31:21.960927 20 : 4257, 4030
7437 16:31:21.961007 24 : 4259, 4032
7438 16:31:21.964268 28 : 4257, 4029
7439 16:31:21.964347 32 : 4255, 4029
7440 16:31:21.966990 36 : 4258, 4029
7441 16:31:21.967068 40 : 4255, 4029
7442 16:31:21.970358 44 : 4260, 4032
7443 16:31:21.970436 48 : 4254, 4029
7444 16:31:21.970498 52 : 4366, 4139
7445 16:31:21.973727 56 : 4258, 4030
7446 16:31:21.973806 60 : 4257, 4030
7447 16:31:21.976924 64 : 4258, 4029
7448 16:31:21.977003 68 : 4257, 4029
7449 16:31:21.980530 72 : 4252, 4029
7450 16:31:21.980632 76 : 4370, 4142
7451 16:31:21.983719 80 : 4363, 4140
7452 16:31:21.983796 84 : 4255, 4029
7453 16:31:21.983855 88 : 4252, 4029
7454 16:31:21.987376 92 : 4363, 4140
7455 16:31:21.987463 96 : 4255, 4029
7456 16:31:21.990578 100 : 4250, 4026
7457 16:31:21.990653 104 : 4250, 3578
7458 16:31:21.993652 108 : 4363, 1
7459 16:31:21.993729 112 : 4366, 0
7460 16:31:21.993790 116 : 4365, 0
7461 16:31:21.997047 120 : 4255, 0
7462 16:31:21.997150 124 : 4253, 0
7463 16:31:22.000569 128 : 4255, 0
7464 16:31:22.000672 132 : 4257, 0
7465 16:31:22.000738 136 : 4252, 0
7466 16:31:22.003367 140 : 4253, 0
7467 16:31:22.003435 144 : 4368, 0
7468 16:31:22.006685 148 : 4363, 0
7469 16:31:22.006754 152 : 4252, 0
7470 16:31:22.006811 156 : 4252, 0
7471 16:31:22.010527 160 : 4252, 0
7472 16:31:22.010597 164 : 4252, 0
7473 16:31:22.010657 168 : 4368, 0
7474 16:31:22.013987 172 : 4252, 0
7475 16:31:22.014054 176 : 4363, 0
7476 16:31:22.016706 180 : 4253, 0
7477 16:31:22.016773 184 : 4255, 0
7478 16:31:22.016829 188 : 4250, 0
7479 16:31:22.020111 192 : 4253, 0
7480 16:31:22.020180 196 : 4258, 0
7481 16:31:22.023686 200 : 4255, 0
7482 16:31:22.023753 204 : 4363, 0
7483 16:31:22.023809 208 : 4253, 0
7484 16:31:22.026425 212 : 4252, 0
7485 16:31:22.026538 216 : 4363, 0
7486 16:31:22.030318 220 : 4253, 0
7487 16:31:22.030394 224 : 4252, 0
7488 16:31:22.030487 228 : 4252, 0
7489 16:31:22.033507 232 : 4362, 0
7490 16:31:22.033603 236 : 4255, 809
7491 16:31:22.036859 240 : 4366, 4140
7492 16:31:22.036950 244 : 4252, 4030
7493 16:31:22.040205 248 : 4255, 4029
7494 16:31:22.040276 252 : 4257, 4032
7495 16:31:22.043072 256 : 4252, 4029
7496 16:31:22.043164 260 : 4253, 4029
7497 16:31:22.043240 264 : 4363, 4139
7498 16:31:22.046474 268 : 4254, 4029
7499 16:31:22.046602 272 : 4255, 4029
7500 16:31:22.049903 276 : 4363, 4140
7501 16:31:22.050033 280 : 4253, 4029
7502 16:31:22.053319 284 : 4255, 4029
7503 16:31:22.053401 288 : 4255, 4029
7504 16:31:22.056542 292 : 4366, 4140
7505 16:31:22.056680 296 : 4363, 4140
7506 16:31:22.059889 300 : 4252, 4026
7507 16:31:22.059993 304 : 4250, 4027
7508 16:31:22.063316 308 : 4255, 4029
7509 16:31:22.063386 312 : 4253, 4029
7510 16:31:22.066565 316 : 4252, 4029
7511 16:31:22.066637 320 : 4252, 4029
7512 16:31:22.069457 324 : 4255, 4029
7513 16:31:22.069526 328 : 4363, 4140
7514 16:31:22.069583 332 : 4252, 4030
7515 16:31:22.073022 336 : 4255, 4029
7516 16:31:22.073103 340 : 4254, 4030
7517 16:31:22.076417 344 : 4255, 4029
7518 16:31:22.076535 348 : 4253, 4029
7519 16:31:22.079915 352 : 4257, 4007
7520 16:31:22.080022 356 : 4255, 2894
7521 16:31:22.082661 360 : 4255, 0
7522 16:31:22.082758
7523 16:31:22.082839 MIOCK jitter meter ch=0
7524 16:31:22.082914
7525 16:31:22.085937 1T = (360-108) = 252 dly cells
7526 16:31:22.092947 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7527 16:31:22.093043 ==
7528 16:31:22.096140 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 16:31:22.099290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 16:31:22.099365 ==
7531 16:31:22.106063 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7532 16:31:22.109335 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7533 16:31:22.115727 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7534 16:31:22.119250 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7535 16:31:22.129633 [CA 0] Center 44 (14~75) winsize 62
7536 16:31:22.132982 [CA 1] Center 43 (13~74) winsize 62
7537 16:31:22.136264 [CA 2] Center 39 (11~68) winsize 58
7538 16:31:22.139505 [CA 3] Center 39 (10~69) winsize 60
7539 16:31:22.142900 [CA 4] Center 37 (8~67) winsize 60
7540 16:31:22.145686 [CA 5] Center 36 (7~66) winsize 60
7541 16:31:22.145763
7542 16:31:22.149096 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7543 16:31:22.149169
7544 16:31:22.155391 [CATrainingPosCal] consider 1 rank data
7545 16:31:22.155471 u2DelayCellTimex100 = 258/100 ps
7546 16:31:22.162228 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7547 16:31:22.165422 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7548 16:31:22.169181 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7549 16:31:22.172228 CA3 delay=39 (10~69),Diff = 3 PI (11 cell)
7550 16:31:22.175714 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7551 16:31:22.178502 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7552 16:31:22.178597
7553 16:31:22.182116 CA PerBit enable=1, Macro0, CA PI delay=36
7554 16:31:22.184966
7555 16:31:22.185057 [CBTSetCACLKResult] CA Dly = 36
7556 16:31:22.188480 CS Dly: 11 (0~42)
7557 16:31:22.191893 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7558 16:31:22.195154 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7559 16:31:22.198456 ==
7560 16:31:22.198534 Dram Type= 6, Freq= 0, CH_0, rank 1
7561 16:31:22.205250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 16:31:22.205340 ==
7563 16:31:22.208608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7564 16:31:22.215019 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7565 16:31:22.218151 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7566 16:31:22.225060 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7567 16:31:22.233635 [CA 0] Center 43 (13~74) winsize 62
7568 16:31:22.236371 [CA 1] Center 43 (13~74) winsize 62
7569 16:31:22.239650 [CA 2] Center 39 (10~68) winsize 59
7570 16:31:22.243498 [CA 3] Center 39 (10~68) winsize 59
7571 16:31:22.246670 [CA 4] Center 36 (6~67) winsize 62
7572 16:31:22.249443 [CA 5] Center 36 (6~66) winsize 61
7573 16:31:22.249518
7574 16:31:22.252908 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7575 16:31:22.253031
7576 16:31:22.259975 [CATrainingPosCal] consider 2 rank data
7577 16:31:22.260076 u2DelayCellTimex100 = 258/100 ps
7578 16:31:22.266213 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7579 16:31:22.269618 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7580 16:31:22.273082 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7581 16:31:22.276222 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7582 16:31:22.280154 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7583 16:31:22.283367 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7584 16:31:22.283448
7585 16:31:22.286761 CA PerBit enable=1, Macro0, CA PI delay=36
7586 16:31:22.286839
7587 16:31:22.289429 [CBTSetCACLKResult] CA Dly = 36
7588 16:31:22.292938 CS Dly: 11 (0~43)
7589 16:31:22.296269 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7590 16:31:22.299556 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7591 16:31:22.299659
7592 16:31:22.302883 ----->DramcWriteLeveling(PI) begin...
7593 16:31:22.302966 ==
7594 16:31:22.306200 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 16:31:22.313140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 16:31:22.313217 ==
7597 16:31:22.316581 Write leveling (Byte 0): 36 => 36
7598 16:31:22.319958 Write leveling (Byte 1): 28 => 28
7599 16:31:22.320055 DramcWriteLeveling(PI) end<-----
7600 16:31:22.323250
7601 16:31:22.323320 ==
7602 16:31:22.326423 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 16:31:22.329484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 16:31:22.329562 ==
7605 16:31:22.332574 [Gating] SW mode calibration
7606 16:31:22.339355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7607 16:31:22.342642 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7608 16:31:22.349735 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 16:31:22.352901 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 16:31:22.356069 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 16:31:22.362966 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 16:31:22.365737 1 4 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7613 16:31:22.369109 1 4 20 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
7614 16:31:22.375860 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
7615 16:31:22.379211 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 16:31:22.382625 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 16:31:22.389203 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 16:31:22.392540 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 16:31:22.396004 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7620 16:31:22.402621 1 5 16 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7621 16:31:22.406044 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7622 16:31:22.409286 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
7623 16:31:22.416073 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 16:31:22.418930 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 16:31:22.422288 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 16:31:22.429008 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 16:31:22.432309 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7628 16:31:22.435774 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7629 16:31:22.442231 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7630 16:31:22.445291 1 6 24 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
7631 16:31:22.448783 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 16:31:22.455216 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 16:31:22.458920 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 16:31:22.462384 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 16:31:22.468601 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7636 16:31:22.472122 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7637 16:31:22.475582 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7638 16:31:22.481443 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7639 16:31:22.484697 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 16:31:22.488196 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 16:31:22.495391 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 16:31:22.498141 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 16:31:22.501418 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 16:31:22.507930 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 16:31:22.511328 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 16:31:22.514515 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 16:31:22.521619 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 16:31:22.525039 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 16:31:22.528489 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 16:31:22.534665 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 16:31:22.538219 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7652 16:31:22.541124 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7653 16:31:22.547685 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7654 16:31:22.547797 Total UI for P1: 0, mck2ui 16
7655 16:31:22.554299 best dqsien dly found for B0: ( 1, 9, 14)
7656 16:31:22.557458 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7657 16:31:22.560621 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 16:31:22.564508 Total UI for P1: 0, mck2ui 16
7659 16:31:22.567658 best dqsien dly found for B1: ( 1, 9, 24)
7660 16:31:22.570958 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7661 16:31:22.574144 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7662 16:31:22.574222
7663 16:31:22.580468 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7664 16:31:22.584381 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7665 16:31:22.584460 [Gating] SW calibration Done
7666 16:31:22.587821 ==
7667 16:31:22.590472 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 16:31:22.593924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 16:31:22.594004 ==
7670 16:31:22.594065 RX Vref Scan: 0
7671 16:31:22.594121
7672 16:31:22.597274 RX Vref 0 -> 0, step: 1
7673 16:31:22.597357
7674 16:31:22.600531 RX Delay 0 -> 252, step: 8
7675 16:31:22.604126 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7676 16:31:22.607420 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7677 16:31:22.610910 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7678 16:31:22.617012 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7679 16:31:22.620153 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7680 16:31:22.623594 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7681 16:31:22.627008 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7682 16:31:22.630402 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7683 16:31:22.637243 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7684 16:31:22.640631 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7685 16:31:22.644053 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7686 16:31:22.646764 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7687 16:31:22.653524 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7688 16:31:22.656816 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7689 16:31:22.660203 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7690 16:31:22.663560 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7691 16:31:22.663633 ==
7692 16:31:22.666933 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 16:31:22.673309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 16:31:22.673387 ==
7695 16:31:22.673448 DQS Delay:
7696 16:31:22.673520 DQS0 = 0, DQS1 = 0
7697 16:31:22.676528 DQM Delay:
7698 16:31:22.676621 DQM0 = 128, DQM1 = 123
7699 16:31:22.679900 DQ Delay:
7700 16:31:22.683282 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7701 16:31:22.686511 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7702 16:31:22.689930 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7703 16:31:22.693308 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7704 16:31:22.693379
7705 16:31:22.693437
7706 16:31:22.693492 ==
7707 16:31:22.696822 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 16:31:22.699551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 16:31:22.703025 ==
7710 16:31:22.703096
7711 16:31:22.703158
7712 16:31:22.703219 TX Vref Scan disable
7713 16:31:22.706207 == TX Byte 0 ==
7714 16:31:22.709673 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7715 16:31:22.713020 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7716 16:31:22.716264 == TX Byte 1 ==
7717 16:31:22.719692 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7718 16:31:22.723090 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7719 16:31:22.726523 ==
7720 16:31:22.729389 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 16:31:22.732821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 16:31:22.732892 ==
7723 16:31:22.746386
7724 16:31:22.749088 TX Vref early break, caculate TX vref
7725 16:31:22.752403 TX Vref=16, minBit 8, minWin=21, winSum=363
7726 16:31:22.755792 TX Vref=18, minBit 11, minWin=21, winSum=371
7727 16:31:22.759203 TX Vref=20, minBit 4, minWin=23, winSum=380
7728 16:31:22.762566 TX Vref=22, minBit 8, minWin=23, winSum=393
7729 16:31:22.765910 TX Vref=24, minBit 11, minWin=23, winSum=397
7730 16:31:22.772762 TX Vref=26, minBit 4, minWin=24, winSum=407
7731 16:31:22.776017 TX Vref=28, minBit 8, minWin=24, winSum=411
7732 16:31:22.779119 TX Vref=30, minBit 8, minWin=24, winSum=401
7733 16:31:22.782136 TX Vref=32, minBit 8, minWin=23, winSum=396
7734 16:31:22.785388 TX Vref=34, minBit 8, minWin=22, winSum=382
7735 16:31:22.792018 [TxChooseVref] Worse bit 8, Min win 24, Win sum 411, Final Vref 28
7736 16:31:22.792097
7737 16:31:22.795252 Final TX Range 0 Vref 28
7738 16:31:22.795355
7739 16:31:22.795441 ==
7740 16:31:22.798577 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 16:31:22.802065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 16:31:22.802135 ==
7743 16:31:22.802193
7744 16:31:22.802248
7745 16:31:22.805482 TX Vref Scan disable
7746 16:31:22.812320 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7747 16:31:22.812422 == TX Byte 0 ==
7748 16:31:22.815599 u2DelayCellOfst[0]=15 cells (4 PI)
7749 16:31:22.818781 u2DelayCellOfst[1]=18 cells (5 PI)
7750 16:31:22.822003 u2DelayCellOfst[2]=15 cells (4 PI)
7751 16:31:22.825145 u2DelayCellOfst[3]=15 cells (4 PI)
7752 16:31:22.828566 u2DelayCellOfst[4]=11 cells (3 PI)
7753 16:31:22.832098 u2DelayCellOfst[5]=0 cells (0 PI)
7754 16:31:22.834947 u2DelayCellOfst[6]=22 cells (6 PI)
7755 16:31:22.838441 u2DelayCellOfst[7]=18 cells (5 PI)
7756 16:31:22.841819 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7757 16:31:22.845112 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7758 16:31:22.848446 == TX Byte 1 ==
7759 16:31:22.851896 u2DelayCellOfst[8]=0 cells (0 PI)
7760 16:31:22.855160 u2DelayCellOfst[9]=3 cells (1 PI)
7761 16:31:22.855245 u2DelayCellOfst[10]=7 cells (2 PI)
7762 16:31:22.858610 u2DelayCellOfst[11]=3 cells (1 PI)
7763 16:31:22.862058 u2DelayCellOfst[12]=11 cells (3 PI)
7764 16:31:22.864792 u2DelayCellOfst[13]=11 cells (3 PI)
7765 16:31:22.868140 u2DelayCellOfst[14]=15 cells (4 PI)
7766 16:31:22.871606 u2DelayCellOfst[15]=11 cells (3 PI)
7767 16:31:22.878448 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7768 16:31:22.881206 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7769 16:31:22.881276 DramC Write-DBI on
7770 16:31:22.881335 ==
7771 16:31:22.884504 Dram Type= 6, Freq= 0, CH_0, rank 0
7772 16:31:22.891374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7773 16:31:22.891452 ==
7774 16:31:22.891514
7775 16:31:22.891569
7776 16:31:22.891623 TX Vref Scan disable
7777 16:31:22.895336 == TX Byte 0 ==
7778 16:31:22.899172 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7779 16:31:22.902518 == TX Byte 1 ==
7780 16:31:22.905366 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7781 16:31:22.908704 DramC Write-DBI off
7782 16:31:22.908770
7783 16:31:22.908826 [DATLAT]
7784 16:31:22.908880 Freq=1600, CH0 RK0
7785 16:31:22.908933
7786 16:31:22.912273 DATLAT Default: 0xf
7787 16:31:22.912333 0, 0xFFFF, sum = 0
7788 16:31:22.915668 1, 0xFFFF, sum = 0
7789 16:31:22.915748 2, 0xFFFF, sum = 0
7790 16:31:22.918972 3, 0xFFFF, sum = 0
7791 16:31:22.922286 4, 0xFFFF, sum = 0
7792 16:31:22.922373 5, 0xFFFF, sum = 0
7793 16:31:22.925570 6, 0xFFFF, sum = 0
7794 16:31:22.925679 7, 0xFFFF, sum = 0
7795 16:31:22.928701 8, 0xFFFF, sum = 0
7796 16:31:22.928780 9, 0xFFFF, sum = 0
7797 16:31:22.932335 10, 0xFFFF, sum = 0
7798 16:31:22.932415 11, 0xFFFF, sum = 0
7799 16:31:22.935318 12, 0xFFFF, sum = 0
7800 16:31:22.935399 13, 0xCFFF, sum = 0
7801 16:31:22.938719 14, 0x0, sum = 1
7802 16:31:22.938791 15, 0x0, sum = 2
7803 16:31:22.942148 16, 0x0, sum = 3
7804 16:31:22.942223 17, 0x0, sum = 4
7805 16:31:22.945565 best_step = 15
7806 16:31:22.945638
7807 16:31:22.945696 ==
7808 16:31:22.948434 Dram Type= 6, Freq= 0, CH_0, rank 0
7809 16:31:22.951876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7810 16:31:22.951969 ==
7811 16:31:22.955291 RX Vref Scan: 1
7812 16:31:22.955400
7813 16:31:22.955490 Set Vref Range= 24 -> 127
7814 16:31:22.955575
7815 16:31:22.958706 RX Vref 24 -> 127, step: 1
7816 16:31:22.958785
7817 16:31:22.961949 RX Delay 11 -> 252, step: 4
7818 16:31:22.962029
7819 16:31:22.965395 Set Vref, RX VrefLevel [Byte0]: 24
7820 16:31:22.968780 [Byte1]: 24
7821 16:31:22.968882
7822 16:31:22.972021 Set Vref, RX VrefLevel [Byte0]: 25
7823 16:31:22.975415 [Byte1]: 25
7824 16:31:22.975494
7825 16:31:22.978897 Set Vref, RX VrefLevel [Byte0]: 26
7826 16:31:22.981609 [Byte1]: 26
7827 16:31:22.986448
7828 16:31:22.986526 Set Vref, RX VrefLevel [Byte0]: 27
7829 16:31:22.989214 [Byte1]: 27
7830 16:31:22.993883
7831 16:31:22.993962 Set Vref, RX VrefLevel [Byte0]: 28
7832 16:31:22.996611 [Byte1]: 28
7833 16:31:23.001125
7834 16:31:23.001203 Set Vref, RX VrefLevel [Byte0]: 29
7835 16:31:23.004365 [Byte1]: 29
7836 16:31:23.008984
7837 16:31:23.009063 Set Vref, RX VrefLevel [Byte0]: 30
7838 16:31:23.012309 [Byte1]: 30
7839 16:31:23.016519
7840 16:31:23.016600 Set Vref, RX VrefLevel [Byte0]: 31
7841 16:31:23.019984 [Byte1]: 31
7842 16:31:23.024001
7843 16:31:23.024079 Set Vref, RX VrefLevel [Byte0]: 32
7844 16:31:23.027389 [Byte1]: 32
7845 16:31:23.031393
7846 16:31:23.031470 Set Vref, RX VrefLevel [Byte0]: 33
7847 16:31:23.034835 [Byte1]: 33
7848 16:31:23.039453
7849 16:31:23.039545 Set Vref, RX VrefLevel [Byte0]: 34
7850 16:31:23.042618 [Byte1]: 34
7851 16:31:23.046865
7852 16:31:23.046942 Set Vref, RX VrefLevel [Byte0]: 35
7853 16:31:23.050280 [Byte1]: 35
7854 16:31:23.054496
7855 16:31:23.054601 Set Vref, RX VrefLevel [Byte0]: 36
7856 16:31:23.058305 [Byte1]: 36
7857 16:31:23.062384
7858 16:31:23.062464 Set Vref, RX VrefLevel [Byte0]: 37
7859 16:31:23.065805 [Byte1]: 37
7860 16:31:23.069872
7861 16:31:23.069951 Set Vref, RX VrefLevel [Byte0]: 38
7862 16:31:23.073406 [Byte1]: 38
7863 16:31:23.077258
7864 16:31:23.077338 Set Vref, RX VrefLevel [Byte0]: 39
7865 16:31:23.080749 [Byte1]: 39
7866 16:31:23.084908
7867 16:31:23.084986 Set Vref, RX VrefLevel [Byte0]: 40
7868 16:31:23.088306 [Byte1]: 40
7869 16:31:23.092362
7870 16:31:23.092438 Set Vref, RX VrefLevel [Byte0]: 41
7871 16:31:23.096226 [Byte1]: 41
7872 16:31:23.100299
7873 16:31:23.100375 Set Vref, RX VrefLevel [Byte0]: 42
7874 16:31:23.103578 [Byte1]: 42
7875 16:31:23.107634
7876 16:31:23.107791 Set Vref, RX VrefLevel [Byte0]: 43
7877 16:31:23.111132 [Byte1]: 43
7878 16:31:23.115475
7879 16:31:23.115552 Set Vref, RX VrefLevel [Byte0]: 44
7880 16:31:23.118873 [Byte1]: 44
7881 16:31:23.123063
7882 16:31:23.123143 Set Vref, RX VrefLevel [Byte0]: 45
7883 16:31:23.126522 [Byte1]: 45
7884 16:31:23.130684
7885 16:31:23.130761 Set Vref, RX VrefLevel [Byte0]: 46
7886 16:31:23.134107 [Byte1]: 46
7887 16:31:23.138243
7888 16:31:23.138319 Set Vref, RX VrefLevel [Byte0]: 47
7889 16:31:23.141781 [Byte1]: 47
7890 16:31:23.145825
7891 16:31:23.145900 Set Vref, RX VrefLevel [Byte0]: 48
7892 16:31:23.149298 [Byte1]: 48
7893 16:31:23.153331
7894 16:31:23.153408 Set Vref, RX VrefLevel [Byte0]: 49
7895 16:31:23.156609 [Byte1]: 49
7896 16:31:23.161255
7897 16:31:23.161355 Set Vref, RX VrefLevel [Byte0]: 50
7898 16:31:23.164316 [Byte1]: 50
7899 16:31:23.169046
7900 16:31:23.169127 Set Vref, RX VrefLevel [Byte0]: 51
7901 16:31:23.172090 [Byte1]: 51
7902 16:31:23.176487
7903 16:31:23.176605 Set Vref, RX VrefLevel [Byte0]: 52
7904 16:31:23.179648 [Byte1]: 52
7905 16:31:23.183924
7906 16:31:23.184071 Set Vref, RX VrefLevel [Byte0]: 53
7907 16:31:23.187235 [Byte1]: 53
7908 16:31:23.191426
7909 16:31:23.191502 Set Vref, RX VrefLevel [Byte0]: 54
7910 16:31:23.194791 [Byte1]: 54
7911 16:31:23.199495
7912 16:31:23.199596 Set Vref, RX VrefLevel [Byte0]: 55
7913 16:31:23.202793 [Byte1]: 55
7914 16:31:23.207141
7915 16:31:23.207218 Set Vref, RX VrefLevel [Byte0]: 56
7916 16:31:23.210424 [Byte1]: 56
7917 16:31:23.214512
7918 16:31:23.214590 Set Vref, RX VrefLevel [Byte0]: 57
7919 16:31:23.217805 [Byte1]: 57
7920 16:31:23.222354
7921 16:31:23.222430 Set Vref, RX VrefLevel [Byte0]: 58
7922 16:31:23.225636 [Byte1]: 58
7923 16:31:23.229823
7924 16:31:23.229899 Set Vref, RX VrefLevel [Byte0]: 59
7925 16:31:23.233220 [Byte1]: 59
7926 16:31:23.237315
7927 16:31:23.237410 Set Vref, RX VrefLevel [Byte0]: 60
7928 16:31:23.240567 [Byte1]: 60
7929 16:31:23.244842
7930 16:31:23.244918 Set Vref, RX VrefLevel [Byte0]: 61
7931 16:31:23.248382 [Byte1]: 61
7932 16:31:23.252495
7933 16:31:23.252600 Set Vref, RX VrefLevel [Byte0]: 62
7934 16:31:23.255944 [Byte1]: 62
7935 16:31:23.260128
7936 16:31:23.260223 Set Vref, RX VrefLevel [Byte0]: 63
7937 16:31:23.263540 [Byte1]: 63
7938 16:31:23.267602
7939 16:31:23.267733 Set Vref, RX VrefLevel [Byte0]: 64
7940 16:31:23.270932 [Byte1]: 64
7941 16:31:23.275360
7942 16:31:23.275438 Set Vref, RX VrefLevel [Byte0]: 65
7943 16:31:23.278592 [Byte1]: 65
7944 16:31:23.283088
7945 16:31:23.283165 Set Vref, RX VrefLevel [Byte0]: 66
7946 16:31:23.286234 [Byte1]: 66
7947 16:31:23.290761
7948 16:31:23.290837 Set Vref, RX VrefLevel [Byte0]: 67
7949 16:31:23.293921 [Byte1]: 67
7950 16:31:23.298365
7951 16:31:23.298441 Set Vref, RX VrefLevel [Byte0]: 68
7952 16:31:23.301558 [Byte1]: 68
7953 16:31:23.305643
7954 16:31:23.305768 Set Vref, RX VrefLevel [Byte0]: 69
7955 16:31:23.309050 [Byte1]: 69
7956 16:31:23.313253
7957 16:31:23.313331 Set Vref, RX VrefLevel [Byte0]: 70
7958 16:31:23.316504 [Byte1]: 70
7959 16:31:23.321207
7960 16:31:23.321284 Set Vref, RX VrefLevel [Byte0]: 71
7961 16:31:23.324553 [Byte1]: 71
7962 16:31:23.328590
7963 16:31:23.328720 Set Vref, RX VrefLevel [Byte0]: 72
7964 16:31:23.331922 [Byte1]: 72
7965 16:31:23.336332
7966 16:31:23.336431 Set Vref, RX VrefLevel [Byte0]: 73
7967 16:31:23.339629 [Byte1]: 73
7968 16:31:23.343728
7969 16:31:23.343804 Set Vref, RX VrefLevel [Byte0]: 74
7970 16:31:23.347291 [Byte1]: 74
7971 16:31:23.351420
7972 16:31:23.351496 Set Vref, RX VrefLevel [Byte0]: 75
7973 16:31:23.354750 [Byte1]: 75
7974 16:31:23.358858
7975 16:31:23.358992 Set Vref, RX VrefLevel [Byte0]: 76
7976 16:31:23.362196 [Byte1]: 76
7977 16:31:23.366472
7978 16:31:23.366571 Final RX Vref Byte 0 = 63 to rank0
7979 16:31:23.369974 Final RX Vref Byte 1 = 58 to rank0
7980 16:31:23.373343 Final RX Vref Byte 0 = 63 to rank1
7981 16:31:23.376738 Final RX Vref Byte 1 = 58 to rank1==
7982 16:31:23.379967 Dram Type= 6, Freq= 0, CH_0, rank 0
7983 16:31:23.386362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 16:31:23.386441 ==
7985 16:31:23.386501 DQS Delay:
7986 16:31:23.389468 DQS0 = 0, DQS1 = 0
7987 16:31:23.389567 DQM Delay:
7988 16:31:23.389673 DQM0 = 126, DQM1 = 119
7989 16:31:23.393410 DQ Delay:
7990 16:31:23.396063 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7991 16:31:23.399438 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7992 16:31:23.402759 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7993 16:31:23.405947 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7994 16:31:23.406050
7995 16:31:23.406126
7996 16:31:23.406187
7997 16:31:23.409656 [DramC_TX_OE_Calibration] TA2
7998 16:31:23.412621 Original DQ_B0 (3 6) =30, OEN = 27
7999 16:31:23.416262 Original DQ_B1 (3 6) =30, OEN = 27
8000 16:31:23.419596 24, 0x0, End_B0=24 End_B1=24
8001 16:31:23.419677 25, 0x0, End_B0=25 End_B1=25
8002 16:31:23.422958 26, 0x0, End_B0=26 End_B1=26
8003 16:31:23.426323 27, 0x0, End_B0=27 End_B1=27
8004 16:31:23.429758 28, 0x0, End_B0=28 End_B1=28
8005 16:31:23.432461 29, 0x0, End_B0=29 End_B1=29
8006 16:31:23.432542 30, 0x0, End_B0=30 End_B1=30
8007 16:31:23.436001 31, 0x4141, End_B0=30 End_B1=30
8008 16:31:23.439330 Byte0 end_step=30 best_step=27
8009 16:31:23.442475 Byte1 end_step=30 best_step=27
8010 16:31:23.446237 Byte0 TX OE(2T, 0.5T) = (3, 3)
8011 16:31:23.449588 Byte1 TX OE(2T, 0.5T) = (3, 3)
8012 16:31:23.449692
8013 16:31:23.449756
8014 16:31:23.455597 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8015 16:31:23.459102 CH0 RK0: MR19=303, MR18=1615
8016 16:31:23.465940 CH0_RK0: MR19=0x303, MR18=0x1615, DQSOSC=398, MR23=63, INC=23, DEC=15
8017 16:31:23.466020
8018 16:31:23.469409 ----->DramcWriteLeveling(PI) begin...
8019 16:31:23.469513 ==
8020 16:31:23.472820 Dram Type= 6, Freq= 0, CH_0, rank 1
8021 16:31:23.476273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 16:31:23.476352 ==
8023 16:31:23.479015 Write leveling (Byte 0): 33 => 33
8024 16:31:23.482471 Write leveling (Byte 1): 28 => 28
8025 16:31:23.485843 DramcWriteLeveling(PI) end<-----
8026 16:31:23.485922
8027 16:31:23.485983 ==
8028 16:31:23.489327 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 16:31:23.492609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 16:31:23.492734 ==
8031 16:31:23.495654 [Gating] SW mode calibration
8032 16:31:23.502580 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8033 16:31:23.508789 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8034 16:31:23.512176 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 16:31:23.518639 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 16:31:23.522457 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 16:31:23.526034 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8038 16:31:23.532095 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8039 16:31:23.535715 1 4 20 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
8040 16:31:23.538986 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 16:31:23.545210 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 16:31:23.548545 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 16:31:23.551698 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8044 16:31:23.559032 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8045 16:31:23.561768 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
8046 16:31:23.565147 1 5 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8047 16:31:23.571770 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
8048 16:31:23.575415 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 16:31:23.578918 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 16:31:23.582366 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 16:31:23.588408 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 16:31:23.592008 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8053 16:31:23.595346 1 6 12 | B1->B0 | 2323 3d3c | 0 1 | (0 0) (0 0)
8054 16:31:23.602157 1 6 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8055 16:31:23.605409 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 16:31:23.608579 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 16:31:23.615277 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 16:31:23.618669 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 16:31:23.622000 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 16:31:23.628719 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8061 16:31:23.631952 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8062 16:31:23.635259 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8063 16:31:23.641848 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8064 16:31:23.645167 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8065 16:31:23.648413 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 16:31:23.654636 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 16:31:23.658444 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 16:31:23.661632 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 16:31:23.668069 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 16:31:23.671420 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 16:31:23.674954 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 16:31:23.681826 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 16:31:23.684582 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 16:31:23.688002 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 16:31:23.695036 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 16:31:23.697676 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 16:31:23.701047 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8078 16:31:23.707954 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8079 16:31:23.708059 Total UI for P1: 0, mck2ui 16
8080 16:31:23.714637 best dqsien dly found for B0: ( 1, 9, 12)
8081 16:31:23.717890 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 16:31:23.721418 Total UI for P1: 0, mck2ui 16
8083 16:31:23.724574 best dqsien dly found for B1: ( 1, 9, 16)
8084 16:31:23.727958 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8085 16:31:23.731315 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8086 16:31:23.731388
8087 16:31:23.734604 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8088 16:31:23.737943 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8089 16:31:23.741257 [Gating] SW calibration Done
8090 16:31:23.741332 ==
8091 16:31:23.744666 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 16:31:23.748080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 16:31:23.748152 ==
8094 16:31:23.751961 RX Vref Scan: 0
8095 16:31:23.752032
8096 16:31:23.754694 RX Vref 0 -> 0, step: 1
8097 16:31:23.754770
8098 16:31:23.754836 RX Delay 0 -> 252, step: 8
8099 16:31:23.761247 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8100 16:31:23.764569 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8101 16:31:23.768005 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8102 16:31:23.771096 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8103 16:31:23.774298 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8104 16:31:23.781293 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8105 16:31:23.784631 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8106 16:31:23.787448 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8107 16:31:23.790732 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8108 16:31:23.793998 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8109 16:31:23.801113 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8110 16:31:23.804525 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8111 16:31:23.807258 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8112 16:31:23.810585 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8113 16:31:23.817654 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8114 16:31:23.820978 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8115 16:31:23.821056 ==
8116 16:31:23.824185 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 16:31:23.827420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 16:31:23.827559 ==
8119 16:31:23.827621 DQS Delay:
8120 16:31:23.830705 DQS0 = 0, DQS1 = 0
8121 16:31:23.830836 DQM Delay:
8122 16:31:23.833863 DQM0 = 128, DQM1 = 121
8123 16:31:23.833981 DQ Delay:
8124 16:31:23.837466 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8125 16:31:23.840368 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8126 16:31:23.843924 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8127 16:31:23.850203 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8128 16:31:23.850319
8129 16:31:23.850381
8130 16:31:23.850437 ==
8131 16:31:23.853540 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 16:31:23.857058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 16:31:23.857181 ==
8134 16:31:23.857267
8135 16:31:23.857348
8136 16:31:23.860412 TX Vref Scan disable
8137 16:31:23.860532 == TX Byte 0 ==
8138 16:31:23.867175 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8139 16:31:23.870458 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8140 16:31:23.870536 == TX Byte 1 ==
8141 16:31:23.877140 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8142 16:31:23.880276 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8143 16:31:23.880369 ==
8144 16:31:23.883420 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 16:31:23.886766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 16:31:23.886858 ==
8147 16:31:23.902375
8148 16:31:23.905814 TX Vref early break, caculate TX vref
8149 16:31:23.908518 TX Vref=16, minBit 8, minWin=22, winSum=370
8150 16:31:23.912117 TX Vref=18, minBit 7, minWin=22, winSum=370
8151 16:31:23.915360 TX Vref=20, minBit 8, minWin=22, winSum=381
8152 16:31:23.918798 TX Vref=22, minBit 1, minWin=23, winSum=386
8153 16:31:23.922285 TX Vref=24, minBit 4, minWin=24, winSum=405
8154 16:31:23.928619 TX Vref=26, minBit 0, minWin=25, winSum=406
8155 16:31:23.932006 TX Vref=28, minBit 8, minWin=24, winSum=408
8156 16:31:23.935390 TX Vref=30, minBit 8, minWin=24, winSum=405
8157 16:31:23.938800 TX Vref=32, minBit 8, minWin=22, winSum=393
8158 16:31:23.942027 TX Vref=34, minBit 8, minWin=22, winSum=388
8159 16:31:23.945066 TX Vref=36, minBit 8, minWin=22, winSum=379
8160 16:31:23.952069 [TxChooseVref] Worse bit 0, Min win 25, Win sum 406, Final Vref 26
8161 16:31:23.952141
8162 16:31:23.955026 Final TX Range 0 Vref 26
8163 16:31:23.955103
8164 16:31:23.955163 ==
8165 16:31:23.958553 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 16:31:23.961810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 16:31:23.961883 ==
8168 16:31:23.961943
8169 16:31:23.964906
8170 16:31:23.964984 TX Vref Scan disable
8171 16:31:23.971664 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8172 16:31:23.971771 == TX Byte 0 ==
8173 16:31:23.974950 u2DelayCellOfst[0]=15 cells (4 PI)
8174 16:31:23.978254 u2DelayCellOfst[1]=22 cells (6 PI)
8175 16:31:23.981651 u2DelayCellOfst[2]=15 cells (4 PI)
8176 16:31:23.985091 u2DelayCellOfst[3]=15 cells (4 PI)
8177 16:31:23.988305 u2DelayCellOfst[4]=11 cells (3 PI)
8178 16:31:23.991384 u2DelayCellOfst[5]=0 cells (0 PI)
8179 16:31:23.994896 u2DelayCellOfst[6]=22 cells (6 PI)
8180 16:31:23.998194 u2DelayCellOfst[7]=22 cells (6 PI)
8181 16:31:24.001727 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8182 16:31:24.004967 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8183 16:31:24.008476 == TX Byte 1 ==
8184 16:31:24.011210 u2DelayCellOfst[8]=0 cells (0 PI)
8185 16:31:24.014662 u2DelayCellOfst[9]=0 cells (0 PI)
8186 16:31:24.018053 u2DelayCellOfst[10]=7 cells (2 PI)
8187 16:31:24.021502 u2DelayCellOfst[11]=3 cells (1 PI)
8188 16:31:24.024935 u2DelayCellOfst[12]=15 cells (4 PI)
8189 16:31:24.025022 u2DelayCellOfst[13]=11 cells (3 PI)
8190 16:31:24.027741 u2DelayCellOfst[14]=15 cells (4 PI)
8191 16:31:24.031174 u2DelayCellOfst[15]=11 cells (3 PI)
8192 16:31:24.037889 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8193 16:31:24.041399 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8194 16:31:24.041497 DramC Write-DBI on
8195 16:31:24.044752 ==
8196 16:31:24.048124 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 16:31:24.051481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 16:31:24.051581 ==
8199 16:31:24.051670
8200 16:31:24.051754
8201 16:31:24.054262 TX Vref Scan disable
8202 16:31:24.054362 == TX Byte 0 ==
8203 16:31:24.060948 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8204 16:31:24.061061 == TX Byte 1 ==
8205 16:31:24.064143 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8206 16:31:24.067535 DramC Write-DBI off
8207 16:31:24.067632
8208 16:31:24.067720 [DATLAT]
8209 16:31:24.070889 Freq=1600, CH0 RK1
8210 16:31:24.070987
8211 16:31:24.071074 DATLAT Default: 0xf
8212 16:31:24.074041 0, 0xFFFF, sum = 0
8213 16:31:24.074112 1, 0xFFFF, sum = 0
8214 16:31:24.077123 2, 0xFFFF, sum = 0
8215 16:31:24.077197 3, 0xFFFF, sum = 0
8216 16:31:24.080796 4, 0xFFFF, sum = 0
8217 16:31:24.083871 5, 0xFFFF, sum = 0
8218 16:31:24.083943 6, 0xFFFF, sum = 0
8219 16:31:24.086977 7, 0xFFFF, sum = 0
8220 16:31:24.087078 8, 0xFFFF, sum = 0
8221 16:31:24.090664 9, 0xFFFF, sum = 0
8222 16:31:24.090763 10, 0xFFFF, sum = 0
8223 16:31:24.093899 11, 0xFFFF, sum = 0
8224 16:31:24.093987 12, 0xFFFF, sum = 0
8225 16:31:24.097082 13, 0xCFFF, sum = 0
8226 16:31:24.097157 14, 0x0, sum = 1
8227 16:31:24.100267 15, 0x0, sum = 2
8228 16:31:24.100337 16, 0x0, sum = 3
8229 16:31:24.104228 17, 0x0, sum = 4
8230 16:31:24.104337 best_step = 15
8231 16:31:24.104426
8232 16:31:24.104510 ==
8233 16:31:24.106931 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 16:31:24.110286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 16:31:24.113730 ==
8236 16:31:24.113812 RX Vref Scan: 0
8237 16:31:24.113875
8238 16:31:24.117116 RX Vref 0 -> 0, step: 1
8239 16:31:24.117187
8240 16:31:24.120514 RX Delay 3 -> 252, step: 4
8241 16:31:24.123703 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8242 16:31:24.127101 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8243 16:31:24.130642 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8244 16:31:24.136810 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8245 16:31:24.140110 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8246 16:31:24.143426 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8247 16:31:24.146903 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8248 16:31:24.150308 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8249 16:31:24.156412 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8250 16:31:24.159987 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8251 16:31:24.163318 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8252 16:31:24.166402 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8253 16:31:24.169654 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8254 16:31:24.176445 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8255 16:31:24.179950 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8256 16:31:24.183263 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8257 16:31:24.183354 ==
8258 16:31:24.186587 Dram Type= 6, Freq= 0, CH_0, rank 1
8259 16:31:24.189617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 16:31:24.192901 ==
8261 16:31:24.192983 DQS Delay:
8262 16:31:24.193045 DQS0 = 0, DQS1 = 0
8263 16:31:24.196847 DQM Delay:
8264 16:31:24.196942 DQM0 = 124, DQM1 = 118
8265 16:31:24.199959 DQ Delay:
8266 16:31:24.203326 DQ0 =124, DQ1 =124, DQ2 =120, DQ3 =122
8267 16:31:24.206574 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8268 16:31:24.209510 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8269 16:31:24.213109 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8270 16:31:24.213189
8271 16:31:24.213250
8272 16:31:24.213305
8273 16:31:24.216346 [DramC_TX_OE_Calibration] TA2
8274 16:31:24.219757 Original DQ_B0 (3 6) =30, OEN = 27
8275 16:31:24.223279 Original DQ_B1 (3 6) =30, OEN = 27
8276 16:31:24.223374 24, 0x0, End_B0=24 End_B1=24
8277 16:31:24.225954 25, 0x0, End_B0=25 End_B1=25
8278 16:31:24.229339 26, 0x0, End_B0=26 End_B1=26
8279 16:31:24.232826 27, 0x0, End_B0=27 End_B1=27
8280 16:31:24.236211 28, 0x0, End_B0=28 End_B1=28
8281 16:31:24.236301 29, 0x0, End_B0=29 End_B1=29
8282 16:31:24.239651 30, 0x0, End_B0=30 End_B1=30
8283 16:31:24.242972 31, 0x4141, End_B0=30 End_B1=30
8284 16:31:24.245674 Byte0 end_step=30 best_step=27
8285 16:31:24.249121 Byte1 end_step=30 best_step=27
8286 16:31:24.252525 Byte0 TX OE(2T, 0.5T) = (3, 3)
8287 16:31:24.252621 Byte1 TX OE(2T, 0.5T) = (3, 3)
8288 16:31:24.255843
8289 16:31:24.255945
8290 16:31:24.262623 [DQSOSCAuto] RK1, (LSB)MR18= 0x2614, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
8291 16:31:24.265482 CH0 RK1: MR19=303, MR18=2614
8292 16:31:24.272126 CH0_RK1: MR19=0x303, MR18=0x2614, DQSOSC=390, MR23=63, INC=24, DEC=16
8293 16:31:24.276017 [RxdqsGatingPostProcess] freq 1600
8294 16:31:24.279008 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8295 16:31:24.282464 best DQS0 dly(2T, 0.5T) = (1, 1)
8296 16:31:24.286024 best DQS1 dly(2T, 0.5T) = (1, 1)
8297 16:31:24.288678 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8298 16:31:24.291978 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8299 16:31:24.295716 best DQS0 dly(2T, 0.5T) = (1, 1)
8300 16:31:24.299023 best DQS1 dly(2T, 0.5T) = (1, 1)
8301 16:31:24.302393 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8302 16:31:24.305624 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8303 16:31:24.308971 Pre-setting of DQS Precalculation
8304 16:31:24.312406 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8305 16:31:24.312480 ==
8306 16:31:24.315094 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 16:31:24.318953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 16:31:24.322300 ==
8309 16:31:24.325318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8310 16:31:24.328384 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8311 16:31:24.335464 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8312 16:31:24.338322 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8313 16:31:24.349148 [CA 0] Center 41 (12~70) winsize 59
8314 16:31:24.351962 [CA 1] Center 42 (12~72) winsize 61
8315 16:31:24.355406 [CA 2] Center 38 (9~67) winsize 59
8316 16:31:24.358713 [CA 3] Center 37 (8~66) winsize 59
8317 16:31:24.361935 [CA 4] Center 37 (8~67) winsize 60
8318 16:31:24.365507 [CA 5] Center 36 (7~66) winsize 60
8319 16:31:24.365606
8320 16:31:24.368352 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8321 16:31:24.368449
8322 16:31:24.372339 [CATrainingPosCal] consider 1 rank data
8323 16:31:24.375066 u2DelayCellTimex100 = 258/100 ps
8324 16:31:24.378506 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8325 16:31:24.385629 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8326 16:31:24.388988 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8327 16:31:24.392402 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8328 16:31:24.395052 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8329 16:31:24.398293 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8330 16:31:24.398390
8331 16:31:24.402061 CA PerBit enable=1, Macro0, CA PI delay=36
8332 16:31:24.402131
8333 16:31:24.405542 [CBTSetCACLKResult] CA Dly = 36
8334 16:31:24.408669 CS Dly: 10 (0~41)
8335 16:31:24.412094 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8336 16:31:24.415481 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8337 16:31:24.415555 ==
8338 16:31:24.418791 Dram Type= 6, Freq= 0, CH_1, rank 1
8339 16:31:24.422154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 16:31:24.425518 ==
8341 16:31:24.428383 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8342 16:31:24.431660 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8343 16:31:24.438484 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8344 16:31:24.441568 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8345 16:31:24.452247 [CA 0] Center 41 (12~71) winsize 60
8346 16:31:24.455010 [CA 1] Center 42 (12~72) winsize 61
8347 16:31:24.458401 [CA 2] Center 37 (8~67) winsize 60
8348 16:31:24.461836 [CA 3] Center 36 (7~66) winsize 60
8349 16:31:24.465318 [CA 4] Center 37 (8~67) winsize 60
8350 16:31:24.468453 [CA 5] Center 36 (6~66) winsize 61
8351 16:31:24.468527
8352 16:31:24.471958 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8353 16:31:24.472026
8354 16:31:24.478158 [CATrainingPosCal] consider 2 rank data
8355 16:31:24.478231 u2DelayCellTimex100 = 258/100 ps
8356 16:31:24.485033 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8357 16:31:24.488387 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8358 16:31:24.491654 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8359 16:31:24.494967 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8360 16:31:24.498410 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8361 16:31:24.501760 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8362 16:31:24.501827
8363 16:31:24.504444 CA PerBit enable=1, Macro0, CA PI delay=36
8364 16:31:24.504530
8365 16:31:24.508246 [CBTSetCACLKResult] CA Dly = 36
8366 16:31:24.511592 CS Dly: 11 (0~43)
8367 16:31:24.514902 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8368 16:31:24.518421 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8369 16:31:24.518487
8370 16:31:24.521002 ----->DramcWriteLeveling(PI) begin...
8371 16:31:24.521067 ==
8372 16:31:24.524512 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 16:31:24.531528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 16:31:24.531598 ==
8375 16:31:24.534316 Write leveling (Byte 0): 24 => 24
8376 16:31:24.537744 Write leveling (Byte 1): 28 => 28
8377 16:31:24.537810 DramcWriteLeveling(PI) end<-----
8378 16:31:24.541036
8379 16:31:24.541099 ==
8380 16:31:24.544258 Dram Type= 6, Freq= 0, CH_1, rank 0
8381 16:31:24.547560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8382 16:31:24.547652 ==
8383 16:31:24.550945 [Gating] SW mode calibration
8384 16:31:24.557391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8385 16:31:24.561156 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8386 16:31:24.567585 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 16:31:24.570743 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 16:31:24.574041 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 16:31:24.580999 1 4 12 | B1->B0 | 2525 2322 | 0 1 | (0 0) (0 0)
8390 16:31:24.583732 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 16:31:24.587287 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 16:31:24.593531 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 16:31:24.597360 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 16:31:24.600523 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 16:31:24.607088 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 16:31:24.610417 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 16:31:24.613785 1 5 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
8398 16:31:24.619918 1 5 16 | B1->B0 | 2424 2424 | 0 1 | (1 0) (1 0)
8399 16:31:24.623880 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 16:31:24.626573 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 16:31:24.633503 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 16:31:24.636966 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 16:31:24.639835 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 16:31:24.646553 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 16:31:24.650015 1 6 12 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
8406 16:31:24.653423 1 6 16 | B1->B0 | 4545 4242 | 0 0 | (0 0) (0 0)
8407 16:31:24.659633 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 16:31:24.663048 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 16:31:24.666264 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 16:31:24.673303 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 16:31:24.676381 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 16:31:24.679481 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 16:31:24.686083 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8414 16:31:24.689430 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8415 16:31:24.692948 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 16:31:24.699960 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 16:31:24.702691 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 16:31:24.706576 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 16:31:24.713108 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 16:31:24.716260 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 16:31:24.719666 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 16:31:24.726008 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 16:31:24.729259 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 16:31:24.732564 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 16:31:24.738781 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 16:31:24.742324 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 16:31:24.745921 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 16:31:24.752583 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 16:31:24.755344 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 16:31:24.758748 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8431 16:31:24.762089 Total UI for P1: 0, mck2ui 16
8432 16:31:24.765587 best dqsien dly found for B1: ( 1, 9, 14)
8433 16:31:24.771852 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 16:31:24.771960 Total UI for P1: 0, mck2ui 16
8435 16:31:24.778621 best dqsien dly found for B0: ( 1, 9, 16)
8436 16:31:24.782125 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8437 16:31:24.785367 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8438 16:31:24.785461
8439 16:31:24.788558 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8440 16:31:24.791654 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8441 16:31:24.794860 [Gating] SW calibration Done
8442 16:31:24.794939 ==
8443 16:31:24.798264 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 16:31:24.801807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 16:31:24.801887 ==
8446 16:31:24.805361 RX Vref Scan: 0
8447 16:31:24.805439
8448 16:31:24.808118 RX Vref 0 -> 0, step: 1
8449 16:31:24.808228
8450 16:31:24.808320 RX Delay 0 -> 252, step: 8
8451 16:31:24.815167 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8452 16:31:24.818295 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8453 16:31:24.821466 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8454 16:31:24.825320 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8455 16:31:24.828278 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8456 16:31:24.835024 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8457 16:31:24.838413 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8458 16:31:24.841304 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8459 16:31:24.844561 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8460 16:31:24.848076 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8461 16:31:24.854511 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8462 16:31:24.857912 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8463 16:31:24.860881 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8464 16:31:24.864274 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8465 16:31:24.867979 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8466 16:31:24.874272 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8467 16:31:24.874346 ==
8468 16:31:24.877960 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 16:31:24.881373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 16:31:24.881452 ==
8471 16:31:24.881544 DQS Delay:
8472 16:31:24.884209 DQS0 = 0, DQS1 = 0
8473 16:31:24.884312 DQM Delay:
8474 16:31:24.887559 DQM0 = 132, DQM1 = 125
8475 16:31:24.887666 DQ Delay:
8476 16:31:24.891077 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8477 16:31:24.894400 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8478 16:31:24.897733 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =115
8479 16:31:24.900878 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8480 16:31:24.904139
8481 16:31:24.904220
8482 16:31:24.904281 ==
8483 16:31:24.907657 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 16:31:24.910478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 16:31:24.910559 ==
8486 16:31:24.910645
8487 16:31:24.910704
8488 16:31:24.913926 TX Vref Scan disable
8489 16:31:24.914008 == TX Byte 0 ==
8490 16:31:24.920893 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8491 16:31:24.924076 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8492 16:31:24.924156 == TX Byte 1 ==
8493 16:31:24.930686 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8494 16:31:24.933983 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8495 16:31:24.934063 ==
8496 16:31:24.937172 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 16:31:24.940280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 16:31:24.940359 ==
8499 16:31:24.955255
8500 16:31:24.958688 TX Vref early break, caculate TX vref
8501 16:31:24.962057 TX Vref=16, minBit 11, minWin=21, winSum=362
8502 16:31:24.965489 TX Vref=18, minBit 8, minWin=22, winSum=375
8503 16:31:24.968790 TX Vref=20, minBit 11, minWin=22, winSum=384
8504 16:31:24.972290 TX Vref=22, minBit 5, minWin=24, winSum=396
8505 16:31:24.975132 TX Vref=24, minBit 8, minWin=24, winSum=405
8506 16:31:24.981883 TX Vref=26, minBit 11, minWin=24, winSum=415
8507 16:31:24.985173 TX Vref=28, minBit 5, minWin=25, winSum=417
8508 16:31:24.988566 TX Vref=30, minBit 15, minWin=24, winSum=414
8509 16:31:24.992008 TX Vref=32, minBit 0, minWin=24, winSum=402
8510 16:31:24.995469 TX Vref=34, minBit 5, minWin=24, winSum=400
8511 16:31:25.001642 TX Vref=36, minBit 0, minWin=23, winSum=383
8512 16:31:25.004907 [TxChooseVref] Worse bit 5, Min win 25, Win sum 417, Final Vref 28
8513 16:31:25.004976
8514 16:31:25.008789 Final TX Range 0 Vref 28
8515 16:31:25.008867
8516 16:31:25.008928 ==
8517 16:31:25.011452 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 16:31:25.014873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 16:31:25.014951 ==
8520 16:31:25.018321
8521 16:31:25.018398
8522 16:31:25.018459 TX Vref Scan disable
8523 16:31:25.024960 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8524 16:31:25.025041 == TX Byte 0 ==
8525 16:31:25.028357 u2DelayCellOfst[0]=18 cells (5 PI)
8526 16:31:25.031759 u2DelayCellOfst[1]=15 cells (4 PI)
8527 16:31:25.034947 u2DelayCellOfst[2]=0 cells (0 PI)
8528 16:31:25.038206 u2DelayCellOfst[3]=7 cells (2 PI)
8529 16:31:25.041472 u2DelayCellOfst[4]=7 cells (2 PI)
8530 16:31:25.044609 u2DelayCellOfst[5]=22 cells (6 PI)
8531 16:31:25.047894 u2DelayCellOfst[6]=18 cells (5 PI)
8532 16:31:25.051413 u2DelayCellOfst[7]=7 cells (2 PI)
8533 16:31:25.054791 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8534 16:31:25.058313 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8535 16:31:25.061720 == TX Byte 1 ==
8536 16:31:25.065088 u2DelayCellOfst[8]=0 cells (0 PI)
8537 16:31:25.068331 u2DelayCellOfst[9]=7 cells (2 PI)
8538 16:31:25.071655 u2DelayCellOfst[10]=15 cells (4 PI)
8539 16:31:25.071752 u2DelayCellOfst[11]=7 cells (2 PI)
8540 16:31:25.075109 u2DelayCellOfst[12]=18 cells (5 PI)
8541 16:31:25.077887 u2DelayCellOfst[13]=22 cells (6 PI)
8542 16:31:25.081183 u2DelayCellOfst[14]=22 cells (6 PI)
8543 16:31:25.084604 u2DelayCellOfst[15]=22 cells (6 PI)
8544 16:31:25.091244 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8545 16:31:25.094566 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8546 16:31:25.094642 DramC Write-DBI on
8547 16:31:25.094701 ==
8548 16:31:25.098008 Dram Type= 6, Freq= 0, CH_1, rank 0
8549 16:31:25.104705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8550 16:31:25.104789 ==
8551 16:31:25.104860
8552 16:31:25.104915
8553 16:31:25.108050 TX Vref Scan disable
8554 16:31:25.108141 == TX Byte 0 ==
8555 16:31:25.114400 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8556 16:31:25.114479 == TX Byte 1 ==
8557 16:31:25.117647 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8558 16:31:25.120850 DramC Write-DBI off
8559 16:31:25.120920
8560 16:31:25.120977 [DATLAT]
8561 16:31:25.124217 Freq=1600, CH1 RK0
8562 16:31:25.124308
8563 16:31:25.124390 DATLAT Default: 0xf
8564 16:31:25.127561 0, 0xFFFF, sum = 0
8565 16:31:25.127655 1, 0xFFFF, sum = 0
8566 16:31:25.130893 2, 0xFFFF, sum = 0
8567 16:31:25.130964 3, 0xFFFF, sum = 0
8568 16:31:25.134266 4, 0xFFFF, sum = 0
8569 16:31:25.134338 5, 0xFFFF, sum = 0
8570 16:31:25.137467 6, 0xFFFF, sum = 0
8571 16:31:25.137565 7, 0xFFFF, sum = 0
8572 16:31:25.140788 8, 0xFFFF, sum = 0
8573 16:31:25.140865 9, 0xFFFF, sum = 0
8574 16:31:25.143965 10, 0xFFFF, sum = 0
8575 16:31:25.147615 11, 0xFFFF, sum = 0
8576 16:31:25.147714 12, 0xFFFF, sum = 0
8577 16:31:25.150930 13, 0x8FFF, sum = 0
8578 16:31:25.151033 14, 0x0, sum = 1
8579 16:31:25.153965 15, 0x0, sum = 2
8580 16:31:25.154069 16, 0x0, sum = 3
8581 16:31:25.157322 17, 0x0, sum = 4
8582 16:31:25.157397 best_step = 15
8583 16:31:25.157454
8584 16:31:25.157509 ==
8585 16:31:25.160749 Dram Type= 6, Freq= 0, CH_1, rank 0
8586 16:31:25.164092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8587 16:31:25.164182 ==
8588 16:31:25.167607 RX Vref Scan: 1
8589 16:31:25.167697
8590 16:31:25.170883 Set Vref Range= 24 -> 127
8591 16:31:25.170980
8592 16:31:25.171068 RX Vref 24 -> 127, step: 1
8593 16:31:25.171149
8594 16:31:25.174298 RX Delay 11 -> 252, step: 4
8595 16:31:25.174392
8596 16:31:25.177603 Set Vref, RX VrefLevel [Byte0]: 24
8597 16:31:25.180319 [Byte1]: 24
8598 16:31:25.183867
8599 16:31:25.183934 Set Vref, RX VrefLevel [Byte0]: 25
8600 16:31:25.187218 [Byte1]: 25
8601 16:31:25.191376
8602 16:31:25.191443 Set Vref, RX VrefLevel [Byte0]: 26
8603 16:31:25.194646 [Byte1]: 26
8604 16:31:25.199432
8605 16:31:25.199525 Set Vref, RX VrefLevel [Byte0]: 27
8606 16:31:25.202182 [Byte1]: 27
8607 16:31:25.206913
8608 16:31:25.207009 Set Vref, RX VrefLevel [Byte0]: 28
8609 16:31:25.210265 [Byte1]: 28
8610 16:31:25.214235
8611 16:31:25.214305 Set Vref, RX VrefLevel [Byte0]: 29
8612 16:31:25.217632 [Byte1]: 29
8613 16:31:25.221696
8614 16:31:25.221766 Set Vref, RX VrefLevel [Byte0]: 30
8615 16:31:25.225589 [Byte1]: 30
8616 16:31:25.229604
8617 16:31:25.229711 Set Vref, RX VrefLevel [Byte0]: 31
8618 16:31:25.233053 [Byte1]: 31
8619 16:31:25.237196
8620 16:31:25.237339 Set Vref, RX VrefLevel [Byte0]: 32
8621 16:31:25.240589 [Byte1]: 32
8622 16:31:25.244807
8623 16:31:25.244881 Set Vref, RX VrefLevel [Byte0]: 33
8624 16:31:25.248216 [Byte1]: 33
8625 16:31:25.252640
8626 16:31:25.252761 Set Vref, RX VrefLevel [Byte0]: 34
8627 16:31:25.255938 [Byte1]: 34
8628 16:31:25.260153
8629 16:31:25.260254 Set Vref, RX VrefLevel [Byte0]: 35
8630 16:31:25.263307 [Byte1]: 35
8631 16:31:25.268060
8632 16:31:25.268137 Set Vref, RX VrefLevel [Byte0]: 36
8633 16:31:25.270919 [Byte1]: 36
8634 16:31:25.275446
8635 16:31:25.275522 Set Vref, RX VrefLevel [Byte0]: 37
8636 16:31:25.278735 [Byte1]: 37
8637 16:31:25.282683
8638 16:31:25.282761 Set Vref, RX VrefLevel [Byte0]: 38
8639 16:31:25.286121 [Byte1]: 38
8640 16:31:25.290821
8641 16:31:25.290918 Set Vref, RX VrefLevel [Byte0]: 39
8642 16:31:25.294213 [Byte1]: 39
8643 16:31:25.298387
8644 16:31:25.298466 Set Vref, RX VrefLevel [Byte0]: 40
8645 16:31:25.301591 [Byte1]: 40
8646 16:31:25.305603
8647 16:31:25.305705 Set Vref, RX VrefLevel [Byte0]: 41
8648 16:31:25.308894 [Byte1]: 41
8649 16:31:25.313575
8650 16:31:25.313653 Set Vref, RX VrefLevel [Byte0]: 42
8651 16:31:25.316435 [Byte1]: 42
8652 16:31:25.321040
8653 16:31:25.321119 Set Vref, RX VrefLevel [Byte0]: 43
8654 16:31:25.324334 [Byte1]: 43
8655 16:31:25.328902
8656 16:31:25.328981 Set Vref, RX VrefLevel [Byte0]: 44
8657 16:31:25.332235 [Byte1]: 44
8658 16:31:25.335965
8659 16:31:25.336043 Set Vref, RX VrefLevel [Byte0]: 45
8660 16:31:25.339695 [Byte1]: 45
8661 16:31:25.343619
8662 16:31:25.343698 Set Vref, RX VrefLevel [Byte0]: 46
8663 16:31:25.347085 [Byte1]: 46
8664 16:31:25.351709
8665 16:31:25.351787 Set Vref, RX VrefLevel [Byte0]: 47
8666 16:31:25.354406 [Byte1]: 47
8667 16:31:25.359170
8668 16:31:25.359250 Set Vref, RX VrefLevel [Byte0]: 48
8669 16:31:25.362474 [Byte1]: 48
8670 16:31:25.366406
8671 16:31:25.366487 Set Vref, RX VrefLevel [Byte0]: 49
8672 16:31:25.370280 [Byte1]: 49
8673 16:31:25.374051
8674 16:31:25.374130 Set Vref, RX VrefLevel [Byte0]: 50
8675 16:31:25.377408 [Byte1]: 50
8676 16:31:25.382002
8677 16:31:25.382080 Set Vref, RX VrefLevel [Byte0]: 51
8678 16:31:25.385289 [Byte1]: 51
8679 16:31:25.389267
8680 16:31:25.389345 Set Vref, RX VrefLevel [Byte0]: 52
8681 16:31:25.392746 [Byte1]: 52
8682 16:31:25.396921
8683 16:31:25.397000 Set Vref, RX VrefLevel [Byte0]: 53
8684 16:31:25.400326 [Byte1]: 53
8685 16:31:25.404971
8686 16:31:25.405090 Set Vref, RX VrefLevel [Byte0]: 54
8687 16:31:25.408279 [Byte1]: 54
8688 16:31:25.412213
8689 16:31:25.412277 Set Vref, RX VrefLevel [Byte0]: 55
8690 16:31:25.415688 [Byte1]: 55
8691 16:31:25.419792
8692 16:31:25.419859 Set Vref, RX VrefLevel [Byte0]: 56
8693 16:31:25.423120 [Byte1]: 56
8694 16:31:25.427730
8695 16:31:25.427794 Set Vref, RX VrefLevel [Byte0]: 57
8696 16:31:25.430993 [Byte1]: 57
8697 16:31:25.435026
8698 16:31:25.435094 Set Vref, RX VrefLevel [Byte0]: 58
8699 16:31:25.438343 [Byte1]: 58
8700 16:31:25.442971
8701 16:31:25.443048 Set Vref, RX VrefLevel [Byte0]: 59
8702 16:31:25.446266 [Byte1]: 59
8703 16:31:25.450047
8704 16:31:25.450124 Set Vref, RX VrefLevel [Byte0]: 60
8705 16:31:25.453475 [Byte1]: 60
8706 16:31:25.457651
8707 16:31:25.457735 Set Vref, RX VrefLevel [Byte0]: 61
8708 16:31:25.461419 [Byte1]: 61
8709 16:31:25.465512
8710 16:31:25.465600 Set Vref, RX VrefLevel [Byte0]: 62
8711 16:31:25.468904 [Byte1]: 62
8712 16:31:25.472945
8713 16:31:25.473021 Set Vref, RX VrefLevel [Byte0]: 63
8714 16:31:25.476318 [Byte1]: 63
8715 16:31:25.480796
8716 16:31:25.480889 Set Vref, RX VrefLevel [Byte0]: 64
8717 16:31:25.484142 [Byte1]: 64
8718 16:31:25.488551
8719 16:31:25.488650 Set Vref, RX VrefLevel [Byte0]: 65
8720 16:31:25.491741 [Byte1]: 65
8721 16:31:25.496466
8722 16:31:25.496559 Set Vref, RX VrefLevel [Byte0]: 66
8723 16:31:25.499149 [Byte1]: 66
8724 16:31:25.504023
8725 16:31:25.504093 Set Vref, RX VrefLevel [Byte0]: 67
8726 16:31:25.506717 [Byte1]: 67
8727 16:31:25.511251
8728 16:31:25.511319 Set Vref, RX VrefLevel [Byte0]: 68
8729 16:31:25.514568 [Byte1]: 68
8730 16:31:25.518657
8731 16:31:25.518723 Set Vref, RX VrefLevel [Byte0]: 69
8732 16:31:25.522148 [Byte1]: 69
8733 16:31:25.526241
8734 16:31:25.526310 Set Vref, RX VrefLevel [Byte0]: 70
8735 16:31:25.529515 [Byte1]: 70
8736 16:31:25.534238
8737 16:31:25.534347 Set Vref, RX VrefLevel [Byte0]: 71
8738 16:31:25.537631 [Byte1]: 71
8739 16:31:25.541667
8740 16:31:25.541749 Set Vref, RX VrefLevel [Byte0]: 72
8741 16:31:25.544947 [Byte1]: 72
8742 16:31:25.549566
8743 16:31:25.549640 Final RX Vref Byte 0 = 54 to rank0
8744 16:31:25.552363 Final RX Vref Byte 1 = 52 to rank0
8745 16:31:25.556172 Final RX Vref Byte 0 = 54 to rank1
8746 16:31:25.559660 Final RX Vref Byte 1 = 52 to rank1==
8747 16:31:25.562358 Dram Type= 6, Freq= 0, CH_1, rank 0
8748 16:31:25.569070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 16:31:25.569143 ==
8750 16:31:25.569203 DQS Delay:
8751 16:31:25.572460 DQS0 = 0, DQS1 = 0
8752 16:31:25.572526 DQM Delay:
8753 16:31:25.572580 DQM0 = 130, DQM1 = 123
8754 16:31:25.575569 DQ Delay:
8755 16:31:25.578993 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8756 16:31:25.582355 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
8757 16:31:25.585648 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =114
8758 16:31:25.588919 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8759 16:31:25.589006
8760 16:31:25.589064
8761 16:31:25.589117
8762 16:31:25.592212 [DramC_TX_OE_Calibration] TA2
8763 16:31:25.596096 Original DQ_B0 (3 6) =30, OEN = 27
8764 16:31:25.599337 Original DQ_B1 (3 6) =30, OEN = 27
8765 16:31:25.602369 24, 0x0, End_B0=24 End_B1=24
8766 16:31:25.602439 25, 0x0, End_B0=25 End_B1=25
8767 16:31:25.605741 26, 0x0, End_B0=26 End_B1=26
8768 16:31:25.609117 27, 0x0, End_B0=27 End_B1=27
8769 16:31:25.612536 28, 0x0, End_B0=28 End_B1=28
8770 16:31:25.615922 29, 0x0, End_B0=29 End_B1=29
8771 16:31:25.615989 30, 0x0, End_B0=30 End_B1=30
8772 16:31:25.619392 31, 0x4141, End_B0=30 End_B1=30
8773 16:31:25.622695 Byte0 end_step=30 best_step=27
8774 16:31:25.625360 Byte1 end_step=30 best_step=27
8775 16:31:25.628732 Byte0 TX OE(2T, 0.5T) = (3, 3)
8776 16:31:25.632020 Byte1 TX OE(2T, 0.5T) = (3, 3)
8777 16:31:25.632136
8778 16:31:25.632250
8779 16:31:25.638800 [DQSOSCAuto] RK0, (LSB)MR18= 0x80c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8780 16:31:25.642138 CH1 RK0: MR19=303, MR18=80C
8781 16:31:25.649060 CH1_RK0: MR19=0x303, MR18=0x80C, DQSOSC=403, MR23=63, INC=22, DEC=15
8782 16:31:25.649139
8783 16:31:25.652266 ----->DramcWriteLeveling(PI) begin...
8784 16:31:25.652382 ==
8785 16:31:25.655406 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 16:31:25.658482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 16:31:25.658577 ==
8788 16:31:25.661731 Write leveling (Byte 0): 24 => 24
8789 16:31:25.665722 Write leveling (Byte 1): 25 => 25
8790 16:31:25.669024 DramcWriteLeveling(PI) end<-----
8791 16:31:25.669100
8792 16:31:25.669160 ==
8793 16:31:25.671741 Dram Type= 6, Freq= 0, CH_1, rank 1
8794 16:31:25.675136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 16:31:25.675228 ==
8796 16:31:25.678448 [Gating] SW mode calibration
8797 16:31:25.685055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8798 16:31:25.691763 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8799 16:31:25.695253 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 16:31:25.698647 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 16:31:25.704924 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8802 16:31:25.708063 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8803 16:31:25.711638 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 16:31:25.718408 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 16:31:25.721712 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 16:31:25.724451 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 16:31:25.731348 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 16:31:25.734655 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 16:31:25.737912 1 5 8 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8810 16:31:25.744745 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8811 16:31:25.748084 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 16:31:25.751528 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 16:31:25.757622 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 16:31:25.760996 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 16:31:25.764151 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 16:31:25.771049 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8817 16:31:25.774164 1 6 8 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
8818 16:31:25.777527 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8819 16:31:25.784260 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 16:31:25.787612 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 16:31:25.791040 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 16:31:25.797703 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 16:31:25.801009 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 16:31:25.804455 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 16:31:25.810984 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8826 16:31:25.814509 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8827 16:31:25.817697 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8828 16:31:25.824403 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 16:31:25.827586 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 16:31:25.831093 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 16:31:25.837283 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 16:31:25.840554 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 16:31:25.844425 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 16:31:25.851036 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 16:31:25.853785 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 16:31:25.857311 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 16:31:25.864039 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 16:31:25.867400 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 16:31:25.870971 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 16:31:25.877461 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 16:31:25.880594 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8842 16:31:25.883541 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8843 16:31:25.887206 Total UI for P1: 0, mck2ui 16
8844 16:31:25.890476 best dqsien dly found for B0: ( 1, 9, 8)
8845 16:31:25.893575 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 16:31:25.896740 Total UI for P1: 0, mck2ui 16
8847 16:31:25.900604 best dqsien dly found for B1: ( 1, 9, 12)
8848 16:31:25.904019 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8849 16:31:25.910076 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8850 16:31:25.910147
8851 16:31:25.913488 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8852 16:31:25.916804 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8853 16:31:25.920102 [Gating] SW calibration Done
8854 16:31:25.920168 ==
8855 16:31:25.923363 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 16:31:25.926653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 16:31:25.926718 ==
8858 16:31:25.929914 RX Vref Scan: 0
8859 16:31:25.929976
8860 16:31:25.930030 RX Vref 0 -> 0, step: 1
8861 16:31:25.930082
8862 16:31:25.933218 RX Delay 0 -> 252, step: 8
8863 16:31:25.936707 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8864 16:31:25.940125 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8865 16:31:25.946928 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8866 16:31:25.950207 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8867 16:31:25.953614 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8868 16:31:25.956481 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8869 16:31:25.959956 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8870 16:31:25.966722 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8871 16:31:25.970011 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8872 16:31:25.973387 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8873 16:31:25.976780 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8874 16:31:25.982994 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8875 16:31:25.986121 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8876 16:31:25.989358 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8877 16:31:25.993051 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8878 16:31:25.996223 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8879 16:31:25.999383 ==
8880 16:31:26.002865 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 16:31:26.006009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 16:31:26.006079 ==
8883 16:31:26.006137 DQS Delay:
8884 16:31:26.009693 DQS0 = 0, DQS1 = 0
8885 16:31:26.009783 DQM Delay:
8886 16:31:26.012635 DQM0 = 132, DQM1 = 127
8887 16:31:26.012745 DQ Delay:
8888 16:31:26.015894 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8889 16:31:26.019129 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =131
8890 16:31:26.022544 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8891 16:31:26.025847 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8892 16:31:26.025922
8893 16:31:26.025982
8894 16:31:26.026036 ==
8895 16:31:26.029157 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 16:31:26.035659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 16:31:26.035737 ==
8898 16:31:26.035797
8899 16:31:26.035851
8900 16:31:26.035904 TX Vref Scan disable
8901 16:31:26.039567 == TX Byte 0 ==
8902 16:31:26.042980 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8903 16:31:26.049642 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8904 16:31:26.049719 == TX Byte 1 ==
8905 16:31:26.052910 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8906 16:31:26.059521 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8907 16:31:26.059605 ==
8908 16:31:26.062980 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 16:31:26.066439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 16:31:26.066547 ==
8911 16:31:26.078612
8912 16:31:26.081368 TX Vref early break, caculate TX vref
8913 16:31:26.084916 TX Vref=16, minBit 0, minWin=23, winSum=388
8914 16:31:26.088329 TX Vref=18, minBit 0, minWin=23, winSum=398
8915 16:31:26.091748 TX Vref=20, minBit 0, minWin=24, winSum=406
8916 16:31:26.095060 TX Vref=22, minBit 0, minWin=25, winSum=410
8917 16:31:26.098477 TX Vref=24, minBit 0, minWin=25, winSum=423
8918 16:31:26.104774 TX Vref=26, minBit 0, minWin=25, winSum=427
8919 16:31:26.108238 TX Vref=28, minBit 0, minWin=26, winSum=428
8920 16:31:26.111488 TX Vref=30, minBit 1, minWin=25, winSum=422
8921 16:31:26.114849 TX Vref=32, minBit 1, minWin=24, winSum=413
8922 16:31:26.118062 TX Vref=34, minBit 5, minWin=23, winSum=405
8923 16:31:26.124710 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8924 16:31:26.124788
8925 16:31:26.128215 Final TX Range 0 Vref 28
8926 16:31:26.128293
8927 16:31:26.128353 ==
8928 16:31:26.131362 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 16:31:26.134487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 16:31:26.134566 ==
8931 16:31:26.134626
8932 16:31:26.134681
8933 16:31:26.137623 TX Vref Scan disable
8934 16:31:26.144191 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8935 16:31:26.144268 == TX Byte 0 ==
8936 16:31:26.147589 u2DelayCellOfst[0]=18 cells (5 PI)
8937 16:31:26.151102 u2DelayCellOfst[1]=11 cells (3 PI)
8938 16:31:26.154426 u2DelayCellOfst[2]=0 cells (0 PI)
8939 16:31:26.157803 u2DelayCellOfst[3]=7 cells (2 PI)
8940 16:31:26.161235 u2DelayCellOfst[4]=7 cells (2 PI)
8941 16:31:26.163934 u2DelayCellOfst[5]=18 cells (5 PI)
8942 16:31:26.167435 u2DelayCellOfst[6]=18 cells (5 PI)
8943 16:31:26.170988 u2DelayCellOfst[7]=7 cells (2 PI)
8944 16:31:26.174332 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8945 16:31:26.177126 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8946 16:31:26.180533 == TX Byte 1 ==
8947 16:31:26.184142 u2DelayCellOfst[8]=0 cells (0 PI)
8948 16:31:26.184214 u2DelayCellOfst[9]=7 cells (2 PI)
8949 16:31:26.186940 u2DelayCellOfst[10]=15 cells (4 PI)
8950 16:31:26.190400 u2DelayCellOfst[11]=7 cells (2 PI)
8951 16:31:26.193807 u2DelayCellOfst[12]=18 cells (5 PI)
8952 16:31:26.197239 u2DelayCellOfst[13]=18 cells (5 PI)
8953 16:31:26.200560 u2DelayCellOfst[14]=18 cells (5 PI)
8954 16:31:26.203986 u2DelayCellOfst[15]=22 cells (6 PI)
8955 16:31:26.210655 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8956 16:31:26.213421 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8957 16:31:26.213501 DramC Write-DBI on
8958 16:31:26.213581 ==
8959 16:31:26.216895 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 16:31:26.223756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 16:31:26.223847 ==
8962 16:31:26.223925
8963 16:31:26.223995
8964 16:31:26.224047 TX Vref Scan disable
8965 16:31:26.227935 == TX Byte 0 ==
8966 16:31:26.231222 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8967 16:31:26.234402 == TX Byte 1 ==
8968 16:31:26.237458 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8969 16:31:26.240946 DramC Write-DBI off
8970 16:31:26.241023
8971 16:31:26.241083 [DATLAT]
8972 16:31:26.241138 Freq=1600, CH1 RK1
8973 16:31:26.241190
8974 16:31:26.244123 DATLAT Default: 0xf
8975 16:31:26.244198 0, 0xFFFF, sum = 0
8976 16:31:26.247197 1, 0xFFFF, sum = 0
8977 16:31:26.250883 2, 0xFFFF, sum = 0
8978 16:31:26.250960 3, 0xFFFF, sum = 0
8979 16:31:26.254045 4, 0xFFFF, sum = 0
8980 16:31:26.254122 5, 0xFFFF, sum = 0
8981 16:31:26.257220 6, 0xFFFF, sum = 0
8982 16:31:26.257299 7, 0xFFFF, sum = 0
8983 16:31:26.260631 8, 0xFFFF, sum = 0
8984 16:31:26.260731 9, 0xFFFF, sum = 0
8985 16:31:26.264180 10, 0xFFFF, sum = 0
8986 16:31:26.264281 11, 0xFFFF, sum = 0
8987 16:31:26.267347 12, 0xFFFF, sum = 0
8988 16:31:26.267424 13, 0x8FFF, sum = 0
8989 16:31:26.270705 14, 0x0, sum = 1
8990 16:31:26.270782 15, 0x0, sum = 2
8991 16:31:26.274481 16, 0x0, sum = 3
8992 16:31:26.274558 17, 0x0, sum = 4
8993 16:31:26.277769 best_step = 15
8994 16:31:26.277845
8995 16:31:26.277904 ==
8996 16:31:26.280441 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 16:31:26.283841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 16:31:26.283937 ==
8999 16:31:26.287094 RX Vref Scan: 0
9000 16:31:26.287169
9001 16:31:26.287244 RX Vref 0 -> 0, step: 1
9002 16:31:26.287302
9003 16:31:26.290545 RX Delay 11 -> 252, step: 4
9004 16:31:26.294011 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9005 16:31:26.300975 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9006 16:31:26.304134 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9007 16:31:26.307254 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9008 16:31:26.310491 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9009 16:31:26.314014 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9010 16:31:26.320631 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9011 16:31:26.323948 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9012 16:31:26.327332 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9013 16:31:26.330653 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9014 16:31:26.334112 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9015 16:31:26.340437 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9016 16:31:26.343883 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9017 16:31:26.347110 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9018 16:31:26.350115 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9019 16:31:26.356940 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9020 16:31:26.357061 ==
9021 16:31:26.360300 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 16:31:26.363644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 16:31:26.363774 ==
9024 16:31:26.363839 DQS Delay:
9025 16:31:26.367106 DQS0 = 0, DQS1 = 0
9026 16:31:26.367182 DQM Delay:
9027 16:31:26.370143 DQM0 = 129, DQM1 = 125
9028 16:31:26.370262 DQ Delay:
9029 16:31:26.373386 DQ0 =132, DQ1 =128, DQ2 =118, DQ3 =124
9030 16:31:26.376866 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
9031 16:31:26.380385 DQ8 =112, DQ9 =112, DQ10 =130, DQ11 =120
9032 16:31:26.383372 DQ12 =132, DQ13 =136, DQ14 =130, DQ15 =134
9033 16:31:26.383448
9034 16:31:26.383509
9035 16:31:26.383564
9036 16:31:26.386971 [DramC_TX_OE_Calibration] TA2
9037 16:31:26.390508 Original DQ_B0 (3 6) =30, OEN = 27
9038 16:31:26.393425 Original DQ_B1 (3 6) =30, OEN = 27
9039 16:31:26.396718 24, 0x0, End_B0=24 End_B1=24
9040 16:31:26.400053 25, 0x0, End_B0=25 End_B1=25
9041 16:31:26.400130 26, 0x0, End_B0=26 End_B1=26
9042 16:31:26.403572 27, 0x0, End_B0=27 End_B1=27
9043 16:31:26.407076 28, 0x0, End_B0=28 End_B1=28
9044 16:31:26.409798 29, 0x0, End_B0=29 End_B1=29
9045 16:31:26.413107 30, 0x0, End_B0=30 End_B1=30
9046 16:31:26.413185 31, 0x5151, End_B0=30 End_B1=30
9047 16:31:26.416968 Byte0 end_step=30 best_step=27
9048 16:31:26.419676 Byte1 end_step=30 best_step=27
9049 16:31:26.423128 Byte0 TX OE(2T, 0.5T) = (3, 3)
9050 16:31:26.426510 Byte1 TX OE(2T, 0.5T) = (3, 3)
9051 16:31:26.426588
9052 16:31:26.426672
9053 16:31:26.433130 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9054 16:31:26.436585 CH1 RK1: MR19=303, MR18=101C
9055 16:31:26.442790 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9056 16:31:26.446286 [RxdqsGatingPostProcess] freq 1600
9057 16:31:26.453179 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9058 16:31:26.456531 best DQS0 dly(2T, 0.5T) = (1, 1)
9059 16:31:26.456617 best DQS1 dly(2T, 0.5T) = (1, 1)
9060 16:31:26.459786 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9061 16:31:26.462934 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9062 16:31:26.466391 best DQS0 dly(2T, 0.5T) = (1, 1)
9063 16:31:26.469534 best DQS1 dly(2T, 0.5T) = (1, 1)
9064 16:31:26.472723 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9065 16:31:26.476057 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9066 16:31:26.479390 Pre-setting of DQS Precalculation
9067 16:31:26.482692 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9068 16:31:26.493320 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9069 16:31:26.499507 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 16:31:26.499585
9071 16:31:26.499644
9072 16:31:26.502753 [Calibration Summary] 3200 Mbps
9073 16:31:26.502832 CH 0, Rank 0
9074 16:31:26.506162 SW Impedance : PASS
9075 16:31:26.506239 DUTY Scan : NO K
9076 16:31:26.509673 ZQ Calibration : PASS
9077 16:31:26.512526 Jitter Meter : NO K
9078 16:31:26.512626 CBT Training : PASS
9079 16:31:26.515953 Write leveling : PASS
9080 16:31:26.519209 RX DQS gating : PASS
9081 16:31:26.519286 RX DQ/DQS(RDDQC) : PASS
9082 16:31:26.522691 TX DQ/DQS : PASS
9083 16:31:26.526031 RX DATLAT : PASS
9084 16:31:26.526107 RX DQ/DQS(Engine): PASS
9085 16:31:26.529231 TX OE : PASS
9086 16:31:26.529307 All Pass.
9087 16:31:26.529367
9088 16:31:26.532764 CH 0, Rank 1
9089 16:31:26.532841 SW Impedance : PASS
9090 16:31:26.535972 DUTY Scan : NO K
9091 16:31:26.539445 ZQ Calibration : PASS
9092 16:31:26.539522 Jitter Meter : NO K
9093 16:31:26.542897 CBT Training : PASS
9094 16:31:26.546295 Write leveling : PASS
9095 16:31:26.546371 RX DQS gating : PASS
9096 16:31:26.549067 RX DQ/DQS(RDDQC) : PASS
9097 16:31:26.549143 TX DQ/DQS : PASS
9098 16:31:26.552477 RX DATLAT : PASS
9099 16:31:26.555867 RX DQ/DQS(Engine): PASS
9100 16:31:26.555936 TX OE : PASS
9101 16:31:26.559241 All Pass.
9102 16:31:26.559314
9103 16:31:26.559373 CH 1, Rank 0
9104 16:31:26.562577 SW Impedance : PASS
9105 16:31:26.562642 DUTY Scan : NO K
9106 16:31:26.565915 ZQ Calibration : PASS
9107 16:31:26.569315 Jitter Meter : NO K
9108 16:31:26.569383 CBT Training : PASS
9109 16:31:26.572499 Write leveling : PASS
9110 16:31:26.575573 RX DQS gating : PASS
9111 16:31:26.575637 RX DQ/DQS(RDDQC) : PASS
9112 16:31:26.579475 TX DQ/DQS : PASS
9113 16:31:26.582697 RX DATLAT : PASS
9114 16:31:26.582773 RX DQ/DQS(Engine): PASS
9115 16:31:26.585752 TX OE : PASS
9116 16:31:26.585829 All Pass.
9117 16:31:26.585889
9118 16:31:26.588967 CH 1, Rank 1
9119 16:31:26.589043 SW Impedance : PASS
9120 16:31:26.592400 DUTY Scan : NO K
9121 16:31:26.595731 ZQ Calibration : PASS
9122 16:31:26.595806 Jitter Meter : NO K
9123 16:31:26.599301 CBT Training : PASS
9124 16:31:26.602651 Write leveling : PASS
9125 16:31:26.602727 RX DQS gating : PASS
9126 16:31:26.605851 RX DQ/DQS(RDDQC) : PASS
9127 16:31:26.605926 TX DQ/DQS : PASS
9128 16:31:26.608989 RX DATLAT : PASS
9129 16:31:26.612018 RX DQ/DQS(Engine): PASS
9130 16:31:26.612094 TX OE : PASS
9131 16:31:26.615869 All Pass.
9132 16:31:26.616072
9133 16:31:26.616208 DramC Write-DBI on
9134 16:31:26.618532 PER_BANK_REFRESH: Hybrid Mode
9135 16:31:26.622006 TX_TRACKING: ON
9136 16:31:26.629059 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9137 16:31:26.639036 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9138 16:31:26.645119 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9139 16:31:26.648498 [FAST_K] Save calibration result to emmc
9140 16:31:26.651889 sync common calibartion params.
9141 16:31:26.651965 sync cbt_mode0:1, 1:1
9142 16:31:26.655378 dram_init: ddr_geometry: 2
9143 16:31:26.658875 dram_init: ddr_geometry: 2
9144 16:31:26.662315 dram_init: ddr_geometry: 2
9145 16:31:26.662393 0:dram_rank_size:100000000
9146 16:31:26.665018 1:dram_rank_size:100000000
9147 16:31:26.671561 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9148 16:31:26.671638 DFS_SHUFFLE_HW_MODE: ON
9149 16:31:26.678210 dramc_set_vcore_voltage set vcore to 725000
9150 16:31:26.678309 Read voltage for 1600, 0
9151 16:31:26.678394 Vio18 = 0
9152 16:31:26.681572 Vcore = 725000
9153 16:31:26.681653 Vdram = 0
9154 16:31:26.681709 Vddq = 0
9155 16:31:26.684919 Vmddr = 0
9156 16:31:26.685039 switch to 3200 Mbps bootup
9157 16:31:26.688239 [DramcRunTimeConfig]
9158 16:31:26.688330 PHYPLL
9159 16:31:26.692009 DPM_CONTROL_AFTERK: ON
9160 16:31:26.692144 PER_BANK_REFRESH: ON
9161 16:31:26.695117 REFRESH_OVERHEAD_REDUCTION: ON
9162 16:31:26.698130 CMD_PICG_NEW_MODE: OFF
9163 16:31:26.698194 XRTWTW_NEW_MODE: ON
9164 16:31:26.701864 XRTRTR_NEW_MODE: ON
9165 16:31:26.701930 TX_TRACKING: ON
9166 16:31:26.705185 RDSEL_TRACKING: OFF
9167 16:31:26.708631 DQS Precalculation for DVFS: ON
9168 16:31:26.708745 RX_TRACKING: OFF
9169 16:31:26.712006 HW_GATING DBG: ON
9170 16:31:26.712111 ZQCS_ENABLE_LP4: ON
9171 16:31:26.715240 RX_PICG_NEW_MODE: ON
9172 16:31:26.715330 TX_PICG_NEW_MODE: ON
9173 16:31:26.718502 ENABLE_RX_DCM_DPHY: ON
9174 16:31:26.721861 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9175 16:31:26.724925 DUMMY_READ_FOR_TRACKING: OFF
9176 16:31:26.728556 !!! SPM_CONTROL_AFTERK: OFF
9177 16:31:26.728638 !!! SPM could not control APHY
9178 16:31:26.731703 IMPEDANCE_TRACKING: ON
9179 16:31:26.731779 TEMP_SENSOR: ON
9180 16:31:26.734816 HW_SAVE_FOR_SR: OFF
9181 16:31:26.738416 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9182 16:31:26.741567 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9183 16:31:26.744959 Read ODT Tracking: ON
9184 16:31:26.745042 Refresh Rate DeBounce: ON
9185 16:31:26.748417 DFS_NO_QUEUE_FLUSH: ON
9186 16:31:26.751122 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9187 16:31:26.754487 ENABLE_DFS_RUNTIME_MRW: OFF
9188 16:31:26.754581 DDR_RESERVE_NEW_MODE: ON
9189 16:31:26.757810 MR_CBT_SWITCH_FREQ: ON
9190 16:31:26.761029 =========================
9191 16:31:26.779176 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9192 16:31:26.782471 dram_init: ddr_geometry: 2
9193 16:31:26.800532 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9194 16:31:26.803718 dram_init: dram init end (result: 0)
9195 16:31:26.810951 DRAM-K: Full calibration passed in 24558 msecs
9196 16:31:26.814219 MRC: failed to locate region type 0.
9197 16:31:26.814316 DRAM rank0 size:0x100000000,
9198 16:31:26.817068 DRAM rank1 size=0x100000000
9199 16:31:26.827487 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9200 16:31:26.833742 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9201 16:31:26.840403 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9202 16:31:26.846906 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9203 16:31:26.850599 DRAM rank0 size:0x100000000,
9204 16:31:26.853649 DRAM rank1 size=0x100000000
9205 16:31:26.853732 CBMEM:
9206 16:31:26.856738 IMD: root @ 0xfffff000 254 entries.
9207 16:31:26.860020 IMD: root @ 0xffffec00 62 entries.
9208 16:31:26.863404 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9209 16:31:26.870346 WARNING: RO_VPD is uninitialized or empty.
9210 16:31:26.873092 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9211 16:31:26.880425 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9212 16:31:26.893754 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9213 16:31:26.905238 BS: romstage times (exec / console): total (unknown) / 24022 ms
9214 16:31:26.905360
9215 16:31:26.905447
9216 16:31:26.914567 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9217 16:31:26.918444 ARM64: Exception handlers installed.
9218 16:31:26.921549 ARM64: Testing exception
9219 16:31:26.924891 ARM64: Done test exception
9220 16:31:26.924990 Enumerating buses...
9221 16:31:26.928110 Show all devs... Before device enumeration.
9222 16:31:26.931642 Root Device: enabled 1
9223 16:31:26.935100 CPU_CLUSTER: 0: enabled 1
9224 16:31:26.935194 CPU: 00: enabled 1
9225 16:31:26.938226 Compare with tree...
9226 16:31:26.938316 Root Device: enabled 1
9227 16:31:26.941298 CPU_CLUSTER: 0: enabled 1
9228 16:31:26.944353 CPU: 00: enabled 1
9229 16:31:26.944459 Root Device scanning...
9230 16:31:26.948358 scan_static_bus for Root Device
9231 16:31:26.951623 CPU_CLUSTER: 0 enabled
9232 16:31:26.954332 scan_static_bus for Root Device done
9233 16:31:26.958300 scan_bus: bus Root Device finished in 8 msecs
9234 16:31:26.958401 done
9235 16:31:26.964707 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9236 16:31:26.967916 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9237 16:31:26.974650 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9238 16:31:26.978096 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9239 16:31:26.981437 Allocating resources...
9240 16:31:26.984766 Reading resources...
9241 16:31:26.987609 Root Device read_resources bus 0 link: 0
9242 16:31:26.987693 DRAM rank0 size:0x100000000,
9243 16:31:26.990973 DRAM rank1 size=0x100000000
9244 16:31:26.994401 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9245 16:31:26.997962 CPU: 00 missing read_resources
9246 16:31:27.001390 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9247 16:31:27.007470 Root Device read_resources bus 0 link: 0 done
9248 16:31:27.007573 Done reading resources.
9249 16:31:27.014302 Show resources in subtree (Root Device)...After reading.
9250 16:31:27.017616 Root Device child on link 0 CPU_CLUSTER: 0
9251 16:31:27.020851 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 16:31:27.030762 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 16:31:27.030843 CPU: 00
9254 16:31:27.034515 Root Device assign_resources, bus 0 link: 0
9255 16:31:27.037392 CPU_CLUSTER: 0 missing set_resources
9256 16:31:27.044264 Root Device assign_resources, bus 0 link: 0 done
9257 16:31:27.044343 Done setting resources.
9258 16:31:27.050865 Show resources in subtree (Root Device)...After assigning values.
9259 16:31:27.054053 Root Device child on link 0 CPU_CLUSTER: 0
9260 16:31:27.057874 CPU_CLUSTER: 0 child on link 0 CPU: 00
9261 16:31:27.067752 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9262 16:31:27.067833 CPU: 00
9263 16:31:27.071019 Done allocating resources.
9264 16:31:27.074243 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9265 16:31:27.077481 Enabling resources...
9266 16:31:27.077560 done.
9267 16:31:27.083947 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9268 16:31:27.084027 Initializing devices...
9269 16:31:27.087197 Root Device init
9270 16:31:27.087290 init hardware done!
9271 16:31:27.090683 0x00000018: ctrlr->caps
9272 16:31:27.094228 52.000 MHz: ctrlr->f_max
9273 16:31:27.094296 0.400 MHz: ctrlr->f_min
9274 16:31:27.097405 0x40ff8080: ctrlr->voltages
9275 16:31:27.097483 sclk: 390625
9276 16:31:27.100764 Bus Width = 1
9277 16:31:27.100840 sclk: 390625
9278 16:31:27.104234 Bus Width = 1
9279 16:31:27.104310 Early init status = 3
9280 16:31:27.110424 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9281 16:31:27.113919 in-header: 03 fc 00 00 01 00 00 00
9282 16:31:27.113994 in-data: 00
9283 16:31:27.120653 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9284 16:31:27.124103 in-header: 03 fd 00 00 00 00 00 00
9285 16:31:27.127374 in-data:
9286 16:31:27.130136 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9287 16:31:27.133590 in-header: 03 fc 00 00 01 00 00 00
9288 16:31:27.136946 in-data: 00
9289 16:31:27.140093 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9290 16:31:27.144604 in-header: 03 fd 00 00 00 00 00 00
9291 16:31:27.148079 in-data:
9292 16:31:27.151564 [SSUSB] Setting up USB HOST controller...
9293 16:31:27.154887 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9294 16:31:27.158173 [SSUSB] phy power-on done.
9295 16:31:27.161457 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9296 16:31:27.167935 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9297 16:31:27.171211 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9298 16:31:27.177921 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9299 16:31:27.184511 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9300 16:31:27.191376 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9301 16:31:27.198308 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9302 16:31:27.204518 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9303 16:31:27.207843 SPM: binary array size = 0x9dc
9304 16:31:27.211335 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9305 16:31:27.218184 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9306 16:31:27.224128 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9307 16:31:27.227482 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9308 16:31:27.234147 configure_display: Starting display init
9309 16:31:27.268189 anx7625_power_on_init: Init interface.
9310 16:31:27.271381 anx7625_disable_pd_protocol: Disabled PD feature.
9311 16:31:27.274536 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9312 16:31:27.302648 anx7625_start_dp_work: Secure OCM version=00
9313 16:31:27.305979 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9314 16:31:27.320461 sp_tx_get_edid_block: EDID Block = 1
9315 16:31:27.423496 Extracted contents:
9316 16:31:27.426798 header: 00 ff ff ff ff ff ff 00
9317 16:31:27.430057 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9318 16:31:27.432812 version: 01 04
9319 16:31:27.436226 basic params: 95 1f 11 78 0a
9320 16:31:27.439554 chroma info: 76 90 94 55 54 90 27 21 50 54
9321 16:31:27.443011 established: 00 00 00
9322 16:31:27.449226 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9323 16:31:27.452623 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9324 16:31:27.459309 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9325 16:31:27.465951 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9326 16:31:27.472757 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9327 16:31:27.475979 extensions: 00
9328 16:31:27.476085 checksum: fb
9329 16:31:27.476172
9330 16:31:27.479254 Manufacturer: IVO Model 57d Serial Number 0
9331 16:31:27.482879 Made week 0 of 2020
9332 16:31:27.482957 EDID version: 1.4
9333 16:31:27.486039 Digital display
9334 16:31:27.489173 6 bits per primary color channel
9335 16:31:27.489252 DisplayPort interface
9336 16:31:27.492298 Maximum image size: 31 cm x 17 cm
9337 16:31:27.495878 Gamma: 220%
9338 16:31:27.495955 Check DPMS levels
9339 16:31:27.499314 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9340 16:31:27.505766 First detailed timing is preferred timing
9341 16:31:27.505845 Established timings supported:
9342 16:31:27.509031 Standard timings supported:
9343 16:31:27.512413 Detailed timings
9344 16:31:27.515900 Hex of detail: 383680a07038204018303c0035ae10000019
9345 16:31:27.519013 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9346 16:31:27.525629 0780 0798 07c8 0820 hborder 0
9347 16:31:27.529053 0438 043b 0447 0458 vborder 0
9348 16:31:27.532429 -hsync -vsync
9349 16:31:27.532522 Did detailed timing
9350 16:31:27.539135 Hex of detail: 000000000000000000000000000000000000
9351 16:31:27.542519 Manufacturer-specified data, tag 0
9352 16:31:27.545854 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9353 16:31:27.549344 ASCII string: InfoVision
9354 16:31:27.552074 Hex of detail: 000000fe00523134304e574635205248200a
9355 16:31:27.555514 ASCII string: R140NWF5 RH
9356 16:31:27.555590 Checksum
9357 16:31:27.558972 Checksum: 0xfb (valid)
9358 16:31:27.562426 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9359 16:31:27.565715 DSI data_rate: 832800000 bps
9360 16:31:27.572454 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9361 16:31:27.575223 anx7625_parse_edid: pixelclock(138800).
9362 16:31:27.578748 hactive(1920), hsync(48), hfp(24), hbp(88)
9363 16:31:27.582196 vactive(1080), vsync(12), vfp(3), vbp(17)
9364 16:31:27.585500 anx7625_dsi_config: config dsi.
9365 16:31:27.592000 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9366 16:31:27.605264 anx7625_dsi_config: success to config DSI
9367 16:31:27.608335 anx7625_dp_start: MIPI phy setup OK.
9368 16:31:27.611848 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9369 16:31:27.615235 mtk_ddp_mode_set invalid vrefresh 60
9370 16:31:27.618466 main_disp_path_setup
9371 16:31:27.618560 ovl_layer_smi_id_en
9372 16:31:27.621980 ovl_layer_smi_id_en
9373 16:31:27.622070 ccorr_config
9374 16:31:27.622151 aal_config
9375 16:31:27.624879 gamma_config
9376 16:31:27.624943 postmask_config
9377 16:31:27.628347 dither_config
9378 16:31:27.631338 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9379 16:31:27.638293 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9380 16:31:27.641625 Root Device init finished in 551 msecs
9381 16:31:27.644989 CPU_CLUSTER: 0 init
9382 16:31:27.651696 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9383 16:31:27.657754 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9384 16:31:27.657832 APU_MBOX 0x190000b0 = 0x10001
9385 16:31:27.661095 APU_MBOX 0x190001b0 = 0x10001
9386 16:31:27.664499 APU_MBOX 0x190005b0 = 0x10001
9387 16:31:27.667934 APU_MBOX 0x190006b0 = 0x10001
9388 16:31:27.674598 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9389 16:31:27.684116 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9390 16:31:27.696611 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9391 16:31:27.703169 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9392 16:31:27.714901 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9393 16:31:27.724145 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9394 16:31:27.727365 CPU_CLUSTER: 0 init finished in 81 msecs
9395 16:31:27.730340 Devices initialized
9396 16:31:27.733682 Show all devs... After init.
9397 16:31:27.733829 Root Device: enabled 1
9398 16:31:27.737280 CPU_CLUSTER: 0: enabled 1
9399 16:31:27.740320 CPU: 00: enabled 1
9400 16:31:27.743979 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9401 16:31:27.746965 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9402 16:31:27.750137 ELOG: NV offset 0x57f000 size 0x1000
9403 16:31:27.756944 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9404 16:31:27.763803 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9405 16:31:27.767256 ELOG: Event(17) added with size 13 at 2024-06-17 16:31:27 UTC
9406 16:31:27.773191 out: cmd=0x121: 03 db 21 01 00 00 00 00
9407 16:31:27.776999 in-header: 03 72 00 00 2c 00 00 00
9408 16:31:27.790036 in-data: cc 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9409 16:31:27.793380 ELOG: Event(A1) added with size 10 at 2024-06-17 16:31:27 UTC
9410 16:31:27.799901 ELOG: Event(16) added with size 11 at 2024-06-17 16:31:27 UTC
9411 16:31:27.880255 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9412 16:31:27.886693 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9413 16:31:27.893349 ELOG: Event(A0) added with size 9 at 2024-06-17 16:31:27 UTC
9414 16:31:27.896747 elog_add_boot_reason: Logged dev mode boot
9415 16:31:27.900009 BS: BS_POST_DEVICE entry times (exec / console): 78 / 74 ms
9416 16:31:27.903589 Finalize devices...
9417 16:31:27.906809 Devices finalized
9418 16:31:27.910233 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9419 16:31:27.913629 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9420 16:31:27.916350 in-header: 03 07 00 00 08 00 00 00
9421 16:31:27.919749 in-data: aa e4 47 04 13 02 00 00
9422 16:31:27.923206 Chrome EC: UHEPI supported
9423 16:31:27.930042 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9424 16:31:27.933456 in-header: 03 a9 00 00 08 00 00 00
9425 16:31:27.936264 in-data: 84 60 60 08 00 00 00 00
9426 16:31:27.942916 ELOG: Event(91) added with size 10 at 2024-06-17 16:31:27 UTC
9427 16:31:27.946407 Chrome EC: clear events_b mask to 0x0000000020004000
9428 16:31:27.953158 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9429 16:31:27.956858 in-header: 03 fd 00 00 00 00 00 00
9430 16:31:27.960213 in-data:
9431 16:31:27.963757 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9432 16:31:27.966396 Writing coreboot table at 0xffe64000
9433 16:31:27.973330 0. 000000000010a000-0000000000113fff: RAMSTAGE
9434 16:31:27.976430 1. 0000000040000000-00000000400fffff: RAM
9435 16:31:27.979860 2. 0000000040100000-000000004032afff: RAMSTAGE
9436 16:31:27.983145 3. 000000004032b000-00000000545fffff: RAM
9437 16:31:27.986446 4. 0000000054600000-000000005465ffff: BL31
9438 16:31:27.989920 5. 0000000054660000-00000000ffe63fff: RAM
9439 16:31:27.996527 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9440 16:31:27.999563 7. 0000000100000000-000000023fffffff: RAM
9441 16:31:28.003107 Passing 5 GPIOs to payload:
9442 16:31:28.006141 NAME | PORT | POLARITY | VALUE
9443 16:31:28.013189 EC in RW | 0x000000aa | low | undefined
9444 16:31:28.016077 EC interrupt | 0x00000005 | low | undefined
9445 16:31:28.022883 TPM interrupt | 0x000000ab | high | undefined
9446 16:31:28.026182 SD card detect | 0x00000011 | high | undefined
9447 16:31:28.029667 speaker enable | 0x00000093 | high | undefined
9448 16:31:28.033046 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9449 16:31:28.036401 in-header: 03 f9 00 00 02 00 00 00
9450 16:31:28.039872 in-data: 02 00
9451 16:31:28.042656 ADC[4]: Raw value=896300 ID=7
9452 16:31:28.046004 ADC[3]: Raw value=213440 ID=1
9453 16:31:28.046106 RAM Code: 0x71
9454 16:31:28.049328 ADC[6]: Raw value=74722 ID=0
9455 16:31:28.052774 ADC[5]: Raw value=212330 ID=1
9456 16:31:28.052851 SKU Code: 0x1
9457 16:31:28.059679 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1895
9458 16:31:28.059763 coreboot table: 964 bytes.
9459 16:31:28.062853 IMD ROOT 0. 0xfffff000 0x00001000
9460 16:31:28.065769 IMD SMALL 1. 0xffffe000 0x00001000
9461 16:31:28.069408 RO MCACHE 2. 0xffffc000 0x00001104
9462 16:31:28.072749 CONSOLE 3. 0xfff7c000 0x00080000
9463 16:31:28.076081 FMAP 4. 0xfff7b000 0x00000452
9464 16:31:28.079385 TIME STAMP 5. 0xfff7a000 0x00000910
9465 16:31:28.082283 VBOOT WORK 6. 0xfff66000 0x00014000
9466 16:31:28.086010 RAMOOPS 7. 0xffe66000 0x00100000
9467 16:31:28.089375 COREBOOT 8. 0xffe64000 0x00002000
9468 16:31:28.092635 IMD small region:
9469 16:31:28.096060 IMD ROOT 0. 0xffffec00 0x00000400
9470 16:31:28.099421 VPD 1. 0xffffeb80 0x0000006c
9471 16:31:28.102920 MMC STATUS 2. 0xffffeb60 0x00000004
9472 16:31:28.105599 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9473 16:31:28.112525 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9474 16:31:28.153768 read SPI 0x3990ec 0x4f1b0: 34862 us, 9294 KB/s, 74.352 Mbps
9475 16:31:28.157218 Checking segment from ROM address 0x40100000
9476 16:31:28.160703 Checking segment from ROM address 0x4010001c
9477 16:31:28.166855 Loading segment from ROM address 0x40100000
9478 16:31:28.166946 code (compression=0)
9479 16:31:28.177075 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9480 16:31:28.183674 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9481 16:31:28.183770 it's not compressed!
9482 16:31:28.190217 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9483 16:31:28.196522 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9484 16:31:28.213933 Loading segment from ROM address 0x4010001c
9485 16:31:28.214032 Entry Point 0x80000000
9486 16:31:28.217916 Loaded segments
9487 16:31:28.221285 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9488 16:31:28.227444 Jumping to boot code at 0x80000000(0xffe64000)
9489 16:31:28.234503 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9490 16:31:28.240598 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9491 16:31:28.248484 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9492 16:31:28.252001 Checking segment from ROM address 0x40100000
9493 16:31:28.255342 Checking segment from ROM address 0x4010001c
9494 16:31:28.261819 Loading segment from ROM address 0x40100000
9495 16:31:28.261921 code (compression=1)
9496 16:31:28.268183 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9497 16:31:28.278525 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9498 16:31:28.278622 using LZMA
9499 16:31:28.286923 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9500 16:31:28.293728 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9501 16:31:28.296896 Loading segment from ROM address 0x4010001c
9502 16:31:28.297003 Entry Point 0x54601000
9503 16:31:28.300187 Loaded segments
9504 16:31:28.303396 NOTICE: MT8192 bl31_setup
9505 16:31:28.310205 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9506 16:31:28.313604 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9507 16:31:28.316942 WARNING: region 0:
9508 16:31:28.320280 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 16:31:28.320359 WARNING: region 1:
9510 16:31:28.327002 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9511 16:31:28.330479 WARNING: region 2:
9512 16:31:28.333321 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9513 16:31:28.336593 WARNING: region 3:
9514 16:31:28.343606 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9515 16:31:28.343738 WARNING: region 4:
9516 16:31:28.349874 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9517 16:31:28.349952 WARNING: region 5:
9518 16:31:28.353085 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 16:31:28.356876 WARNING: region 6:
9520 16:31:28.360105 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 16:31:28.363413 WARNING: region 7:
9522 16:31:28.366713 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 16:31:28.373054 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9524 16:31:28.376371 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9525 16:31:28.383322 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9526 16:31:28.386047 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9527 16:31:28.389336 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9528 16:31:28.395925 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9529 16:31:28.399171 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9530 16:31:28.402804 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9531 16:31:28.409564 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9532 16:31:28.412547 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9533 16:31:28.419327 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9534 16:31:28.422567 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9535 16:31:28.425957 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9536 16:31:28.432705 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9537 16:31:28.436054 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9538 16:31:28.439454 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9539 16:31:28.445493 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9540 16:31:28.449249 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9541 16:31:28.455504 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9542 16:31:28.458647 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9543 16:31:28.462451 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9544 16:31:28.468668 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9545 16:31:28.471965 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9546 16:31:28.479224 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9547 16:31:28.481995 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9548 16:31:28.485269 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9549 16:31:28.491921 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9550 16:31:28.495218 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9551 16:31:28.502048 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9552 16:31:28.505371 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9553 16:31:28.511877 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9554 16:31:28.515060 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9555 16:31:28.518868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9556 16:31:28.521905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9557 16:31:28.528373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9558 16:31:28.531503 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9559 16:31:28.534885 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9560 16:31:28.538365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9561 16:31:28.545330 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9562 16:31:28.548056 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9563 16:31:28.551411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9564 16:31:28.554712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9565 16:31:28.561494 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9566 16:31:28.564900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9567 16:31:28.568280 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9568 16:31:28.571684 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9569 16:31:28.577893 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9570 16:31:28.581563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9571 16:31:28.584569 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9572 16:31:28.591634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9573 16:31:28.594372 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9574 16:31:28.600968 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9575 16:31:28.604309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9576 16:31:28.611248 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9577 16:31:28.614521 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9578 16:31:28.621270 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9579 16:31:28.624460 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9580 16:31:28.627937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9581 16:31:28.634198 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9582 16:31:28.637338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9583 16:31:28.643962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9584 16:31:28.647350 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9585 16:31:28.654036 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9586 16:31:28.657502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9587 16:31:28.664046 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9588 16:31:28.667455 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9589 16:31:28.670203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9590 16:31:28.677098 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9591 16:31:28.680524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9592 16:31:28.687294 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9593 16:31:28.690535 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9594 16:31:28.697080 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9595 16:31:28.700141 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9596 16:31:28.706538 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9597 16:31:28.709959 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9598 16:31:28.713375 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9599 16:31:28.720172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9600 16:31:28.723610 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9601 16:31:28.729605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9602 16:31:28.732953 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9603 16:31:28.740129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9604 16:31:28.743450 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9605 16:31:28.749697 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9606 16:31:28.753253 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9607 16:31:28.756397 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9608 16:31:28.762959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9609 16:31:28.766262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9610 16:31:28.772934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9611 16:31:28.776397 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9612 16:31:28.783116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9613 16:31:28.786455 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9614 16:31:28.793065 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9615 16:31:28.796484 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9616 16:31:28.799200 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9617 16:31:28.806071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9618 16:31:28.809266 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9619 16:31:28.815564 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9620 16:31:28.819307 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9621 16:31:28.822109 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9622 16:31:28.825664 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9623 16:31:28.832381 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9624 16:31:28.835822 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9625 16:31:28.839170 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9626 16:31:28.845682 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9627 16:31:28.849111 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9628 16:31:28.855625 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9629 16:31:28.858874 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9630 16:31:28.865622 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9631 16:31:28.868571 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9632 16:31:28.871948 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9633 16:31:28.878502 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9634 16:31:28.881904 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9635 16:31:28.888790 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9636 16:31:28.891545 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9637 16:31:28.895011 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9638 16:31:28.901805 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9639 16:31:28.905332 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9640 16:31:28.908749 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9641 16:31:28.915031 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9642 16:31:28.918338 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9643 16:31:28.921800 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9644 16:31:28.924543 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9645 16:31:28.931588 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9646 16:31:28.934666 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9647 16:31:28.938264 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9648 16:31:28.944817 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9649 16:31:28.947813 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9650 16:31:28.954864 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9651 16:31:28.957868 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9652 16:31:28.961222 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9653 16:31:28.967960 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9654 16:31:28.971244 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9655 16:31:28.977479 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9656 16:31:28.981151 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9657 16:31:28.984160 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9658 16:31:28.990808 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9659 16:31:28.994233 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9660 16:31:29.000995 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9661 16:31:29.004288 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9662 16:31:29.007626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9663 16:31:29.013717 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9664 16:31:29.017024 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9665 16:31:29.023926 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9666 16:31:29.027406 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9667 16:31:29.030168 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9668 16:31:29.036838 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9669 16:31:29.040111 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9670 16:31:29.046917 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9671 16:31:29.050160 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9672 16:31:29.053613 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9673 16:31:29.060142 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9674 16:31:29.063156 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9675 16:31:29.069859 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9676 16:31:29.073566 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9677 16:31:29.076453 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9678 16:31:29.083119 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9679 16:31:29.086202 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9680 16:31:29.093028 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9681 16:31:29.095908 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9682 16:31:29.099228 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9683 16:31:29.106138 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9684 16:31:29.109589 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9685 16:31:29.115859 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9686 16:31:29.119389 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9687 16:31:29.122748 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9688 16:31:29.129590 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9689 16:31:29.132325 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9690 16:31:29.139030 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9691 16:31:29.142491 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9692 16:31:29.145841 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9693 16:31:29.152630 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9694 16:31:29.155343 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9695 16:31:29.162379 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9696 16:31:29.165654 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9697 16:31:29.169013 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9698 16:31:29.175504 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9699 16:31:29.178807 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9700 16:31:29.185069 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9701 16:31:29.188680 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9702 16:31:29.192222 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9703 16:31:29.198818 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9704 16:31:29.202089 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9705 16:31:29.208521 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9706 16:31:29.211518 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9707 16:31:29.215287 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9708 16:31:29.221444 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9709 16:31:29.224929 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9710 16:31:29.231848 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9711 16:31:29.235284 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9712 16:31:29.238005 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9713 16:31:29.244805 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9714 16:31:29.248231 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9715 16:31:29.255009 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9716 16:31:29.258265 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9717 16:31:29.264963 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9718 16:31:29.268430 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9719 16:31:29.271062 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9720 16:31:29.278199 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9721 16:31:29.281613 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9722 16:31:29.287776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9723 16:31:29.291249 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9724 16:31:29.294528 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9725 16:31:29.301417 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9726 16:31:29.304592 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9727 16:31:29.310770 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9728 16:31:29.314431 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9729 16:31:29.321112 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9730 16:31:29.324291 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9731 16:31:29.327682 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9732 16:31:29.334351 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9733 16:31:29.337744 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9734 16:31:29.343933 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9735 16:31:29.347404 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9736 16:31:29.354268 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9737 16:31:29.357657 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9738 16:31:29.360387 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9739 16:31:29.366900 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9740 16:31:29.370316 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9741 16:31:29.377121 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9742 16:31:29.380327 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9743 16:31:29.386881 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9744 16:31:29.390194 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9745 16:31:29.393676 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9746 16:31:29.400704 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9747 16:31:29.403360 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9748 16:31:29.410682 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9749 16:31:29.414008 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9750 16:31:29.417273 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9751 16:31:29.423417 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9752 16:31:29.426860 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9753 16:31:29.430078 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9754 16:31:29.433852 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9755 16:31:29.440061 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9756 16:31:29.443292 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9757 16:31:29.446852 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9758 16:31:29.453570 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9759 16:31:29.457026 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9760 16:31:29.463719 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9761 16:31:29.466465 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9762 16:31:29.469673 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9763 16:31:29.476498 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9764 16:31:29.479947 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9765 16:31:29.483287 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9766 16:31:29.489908 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9767 16:31:29.493428 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9768 16:31:29.496272 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9769 16:31:29.503021 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9770 16:31:29.506292 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9771 16:31:29.512899 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9772 16:31:29.516321 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9773 16:31:29.519598 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9774 16:31:29.525891 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9775 16:31:29.529214 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9776 16:31:29.532641 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9777 16:31:29.538895 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9778 16:31:29.542304 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9779 16:31:29.548918 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9780 16:31:29.552724 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9781 16:31:29.555870 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9782 16:31:29.562351 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9783 16:31:29.565842 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9784 16:31:29.568808 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9785 16:31:29.575619 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9786 16:31:29.578818 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9787 16:31:29.585594 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9788 16:31:29.588954 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9789 16:31:29.592253 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9790 16:31:29.598749 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9791 16:31:29.602272 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9792 16:31:29.604951 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9793 16:31:29.608275 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9794 16:31:29.614993 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9795 16:31:29.618285 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9796 16:31:29.621607 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9797 16:31:29.624958 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9798 16:31:29.631423 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9799 16:31:29.635297 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9800 16:31:29.638002 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9801 16:31:29.641389 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9802 16:31:29.648176 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9803 16:31:29.651523 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9804 16:31:29.655003 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9805 16:31:29.661050 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9806 16:31:29.664486 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9807 16:31:29.671261 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9808 16:31:29.674487 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9809 16:31:29.680701 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9810 16:31:29.684211 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9811 16:31:29.687740 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9812 16:31:29.694027 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9813 16:31:29.697580 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9814 16:31:29.703947 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9815 16:31:29.707468 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9816 16:31:29.710294 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9817 16:31:29.717149 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9818 16:31:29.720572 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9819 16:31:29.727620 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9820 16:31:29.730366 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9821 16:31:29.733728 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9822 16:31:29.740829 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9823 16:31:29.743959 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9824 16:31:29.750767 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9825 16:31:29.754324 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9826 16:31:29.760501 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9827 16:31:29.763956 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9828 16:31:29.767225 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9829 16:31:29.773995 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9830 16:31:29.777280 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9831 16:31:29.783874 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9832 16:31:29.786684 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9833 16:31:29.789994 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9834 16:31:29.796723 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9835 16:31:29.799906 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9836 16:31:29.806582 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9837 16:31:29.810119 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9838 16:31:29.813510 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9839 16:31:29.820165 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9840 16:31:29.823705 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9841 16:31:29.830289 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9842 16:31:29.833661 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9843 16:31:29.839872 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9844 16:31:29.843207 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9845 16:31:29.846409 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9846 16:31:29.852975 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9847 16:31:29.856382 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9848 16:31:29.863329 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9849 16:31:29.865995 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9850 16:31:29.869347 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9851 16:31:29.876331 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9852 16:31:29.879654 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9853 16:31:29.886408 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9854 16:31:29.889117 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9855 16:31:29.892444 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9856 16:31:29.899103 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9857 16:31:29.902410 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9858 16:31:29.909136 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9859 16:31:29.912446 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9860 16:31:29.919112 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9861 16:31:29.922189 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9862 16:31:29.925840 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9863 16:31:29.932129 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9864 16:31:29.935740 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9865 16:31:29.942376 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9866 16:31:29.945374 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9867 16:31:29.951885 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9868 16:31:29.955147 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9869 16:31:29.958585 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9870 16:31:29.965375 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9871 16:31:29.968858 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9872 16:31:29.974965 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9873 16:31:29.978385 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9874 16:31:29.981558 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9875 16:31:29.988274 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9876 16:31:29.991474 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9877 16:31:29.998332 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9878 16:31:30.001540 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9879 16:31:30.008351 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9880 16:31:30.011810 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9881 16:31:30.015135 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9882 16:31:30.021454 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9883 16:31:30.024977 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9884 16:31:30.031097 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9885 16:31:30.034814 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9886 16:31:30.041272 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9887 16:31:30.044395 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9888 16:31:30.051134 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9889 16:31:30.054482 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9890 16:31:30.057506 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9891 16:31:30.064159 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9892 16:31:30.067753 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9893 16:31:30.074444 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9894 16:31:30.077893 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9895 16:31:30.083986 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9896 16:31:30.087344 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9897 16:31:30.093969 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9898 16:31:30.097136 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9899 16:31:30.100614 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9900 16:31:30.107371 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9901 16:31:30.110644 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9902 16:31:30.117437 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9903 16:31:30.120221 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9904 16:31:30.127067 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9905 16:31:30.130441 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9906 16:31:30.137209 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9907 16:31:30.140288 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9908 16:31:30.143574 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9909 16:31:30.150372 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9910 16:31:30.153530 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9911 16:31:30.160325 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9912 16:31:30.163504 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9913 16:31:30.169860 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9914 16:31:30.173698 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9915 16:31:30.176969 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9916 16:31:30.183090 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9917 16:31:30.186945 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9918 16:31:30.193524 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9919 16:31:30.196827 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9920 16:31:30.203404 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9921 16:31:30.206784 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9922 16:31:30.212833 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9923 16:31:30.216209 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9924 16:31:30.219703 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9925 16:31:30.226714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9926 16:31:30.229484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9927 16:31:30.236377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9928 16:31:30.239848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9929 16:31:30.246449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9930 16:31:30.249557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9931 16:31:30.256267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9932 16:31:30.259652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9933 16:31:30.263078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9934 16:31:30.269282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9935 16:31:30.272489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9936 16:31:30.279513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9937 16:31:30.282845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9938 16:31:30.289284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9939 16:31:30.292547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9940 16:31:30.298843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9941 16:31:30.302408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9942 16:31:30.309236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9943 16:31:30.312420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9944 16:31:30.319021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9945 16:31:30.322572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9946 16:31:30.329392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9947 16:31:30.332631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9948 16:31:30.339402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9949 16:31:30.342168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9950 16:31:30.348926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9951 16:31:30.351939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9952 16:31:30.358836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9953 16:31:30.362016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9954 16:31:30.368958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9955 16:31:30.372458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9956 16:31:30.378640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9957 16:31:30.381896 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9958 16:31:30.385559 INFO: [APUAPC] vio 0
9959 16:31:30.388681 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9960 16:31:30.395322 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9961 16:31:30.398644 INFO: [APUAPC] D0_APC_0: 0x400510
9962 16:31:30.401960 INFO: [APUAPC] D0_APC_1: 0x0
9963 16:31:30.402029 INFO: [APUAPC] D0_APC_2: 0x1540
9964 16:31:30.405242 INFO: [APUAPC] D0_APC_3: 0x0
9965 16:31:30.408206 INFO: [APUAPC] D1_APC_0: 0xffffffff
9966 16:31:30.411542 INFO: [APUAPC] D1_APC_1: 0xffffffff
9967 16:31:30.414936 INFO: [APUAPC] D1_APC_2: 0x3fffff
9968 16:31:30.418051 INFO: [APUAPC] D1_APC_3: 0x0
9969 16:31:30.421708 INFO: [APUAPC] D2_APC_0: 0xffffffff
9970 16:31:30.424769 INFO: [APUAPC] D2_APC_1: 0xffffffff
9971 16:31:30.427942 INFO: [APUAPC] D2_APC_2: 0x3fffff
9972 16:31:30.431512 INFO: [APUAPC] D2_APC_3: 0x0
9973 16:31:30.434978 INFO: [APUAPC] D3_APC_0: 0xffffffff
9974 16:31:30.438407 INFO: [APUAPC] D3_APC_1: 0xffffffff
9975 16:31:30.441122 INFO: [APUAPC] D3_APC_2: 0x3fffff
9976 16:31:30.444598 INFO: [APUAPC] D3_APC_3: 0x0
9977 16:31:30.448150 INFO: [APUAPC] D4_APC_0: 0xffffffff
9978 16:31:30.451470 INFO: [APUAPC] D4_APC_1: 0xffffffff
9979 16:31:30.454933 INFO: [APUAPC] D4_APC_2: 0x3fffff
9980 16:31:30.458191 INFO: [APUAPC] D4_APC_3: 0x0
9981 16:31:30.460914 INFO: [APUAPC] D5_APC_0: 0xffffffff
9982 16:31:30.464105 INFO: [APUAPC] D5_APC_1: 0xffffffff
9983 16:31:30.467301 INFO: [APUAPC] D5_APC_2: 0x3fffff
9984 16:31:30.470928 INFO: [APUAPC] D5_APC_3: 0x0
9985 16:31:30.474321 INFO: [APUAPC] D6_APC_0: 0xffffffff
9986 16:31:30.477714 INFO: [APUAPC] D6_APC_1: 0xffffffff
9987 16:31:30.481121 INFO: [APUAPC] D6_APC_2: 0x3fffff
9988 16:31:30.483940 INFO: [APUAPC] D6_APC_3: 0x0
9989 16:31:30.487311 INFO: [APUAPC] D7_APC_0: 0xffffffff
9990 16:31:30.490596 INFO: [APUAPC] D7_APC_1: 0xffffffff
9991 16:31:30.493980 INFO: [APUAPC] D7_APC_2: 0x3fffff
9992 16:31:30.496999 INFO: [APUAPC] D7_APC_3: 0x0
9993 16:31:30.500654 INFO: [APUAPC] D8_APC_0: 0xffffffff
9994 16:31:30.504060 INFO: [APUAPC] D8_APC_1: 0xffffffff
9995 16:31:30.507371 INFO: [APUAPC] D8_APC_2: 0x3fffff
9996 16:31:30.510741 INFO: [APUAPC] D8_APC_3: 0x0
9997 16:31:30.513983 INFO: [APUAPC] D9_APC_0: 0xffffffff
9998 16:31:30.516658 INFO: [APUAPC] D9_APC_1: 0xffffffff
9999 16:31:30.520628 INFO: [APUAPC] D9_APC_2: 0x3fffff
10000 16:31:30.523313 INFO: [APUAPC] D9_APC_3: 0x0
10001 16:31:30.526644 INFO: [APUAPC] D10_APC_0: 0xffffffff
10002 16:31:30.529967 INFO: [APUAPC] D10_APC_1: 0xffffffff
10003 16:31:30.533533 INFO: [APUAPC] D10_APC_2: 0x3fffff
10004 16:31:30.536531 INFO: [APUAPC] D10_APC_3: 0x0
10005 16:31:30.540087 INFO: [APUAPC] D11_APC_0: 0xffffffff
10006 16:31:30.543779 INFO: [APUAPC] D11_APC_1: 0xffffffff
10007 16:31:30.547100 INFO: [APUAPC] D11_APC_2: 0x3fffff
10008 16:31:30.549922 INFO: [APUAPC] D11_APC_3: 0x0
10009 16:31:30.553295 INFO: [APUAPC] D12_APC_0: 0xffffffff
10010 16:31:30.556716 INFO: [APUAPC] D12_APC_1: 0xffffffff
10011 16:31:30.560077 INFO: [APUAPC] D12_APC_2: 0x3fffff
10012 16:31:30.562876 INFO: [APUAPC] D12_APC_3: 0x0
10013 16:31:30.566420 INFO: [APUAPC] D13_APC_0: 0xffffffff
10014 16:31:30.569780 INFO: [APUAPC] D13_APC_1: 0xffffffff
10015 16:31:30.572930 INFO: [APUAPC] D13_APC_2: 0x3fffff
10016 16:31:30.576239 INFO: [APUAPC] D13_APC_3: 0x0
10017 16:31:30.579332 INFO: [APUAPC] D14_APC_0: 0xffffffff
10018 16:31:30.582520 INFO: [APUAPC] D14_APC_1: 0xffffffff
10019 16:31:30.586004 INFO: [APUAPC] D14_APC_2: 0x3fffff
10020 16:31:30.589475 INFO: [APUAPC] D14_APC_3: 0x0
10021 16:31:30.592345 INFO: [APUAPC] D15_APC_0: 0xffffffff
10022 16:31:30.595696 INFO: [APUAPC] D15_APC_1: 0xffffffff
10023 16:31:30.599201 INFO: [APUAPC] D15_APC_2: 0x3fffff
10024 16:31:30.602382 INFO: [APUAPC] D15_APC_3: 0x0
10025 16:31:30.605536 INFO: [APUAPC] APC_CON: 0x4
10026 16:31:30.609207 INFO: [NOCDAPC] D0_APC_0: 0x0
10027 16:31:30.612295 INFO: [NOCDAPC] D0_APC_1: 0x0
10028 16:31:30.615573 INFO: [NOCDAPC] D1_APC_0: 0x0
10029 16:31:30.618972 INFO: [NOCDAPC] D1_APC_1: 0xfff
10030 16:31:30.622125 INFO: [NOCDAPC] D2_APC_0: 0x0
10031 16:31:30.625619 INFO: [NOCDAPC] D2_APC_1: 0xfff
10032 16:31:30.625716 INFO: [NOCDAPC] D3_APC_0: 0x0
10033 16:31:30.629097 INFO: [NOCDAPC] D3_APC_1: 0xfff
10034 16:31:30.631895 INFO: [NOCDAPC] D4_APC_0: 0x0
10035 16:31:30.635334 INFO: [NOCDAPC] D4_APC_1: 0xfff
10036 16:31:30.639229 INFO: [NOCDAPC] D5_APC_0: 0x0
10037 16:31:30.642589 INFO: [NOCDAPC] D5_APC_1: 0xfff
10038 16:31:30.645807 INFO: [NOCDAPC] D6_APC_0: 0x0
10039 16:31:30.648937 INFO: [NOCDAPC] D6_APC_1: 0xfff
10040 16:31:30.651907 INFO: [NOCDAPC] D7_APC_0: 0x0
10041 16:31:30.655581 INFO: [NOCDAPC] D7_APC_1: 0xfff
10042 16:31:30.658341 INFO: [NOCDAPC] D8_APC_0: 0x0
10043 16:31:30.661711 INFO: [NOCDAPC] D8_APC_1: 0xfff
10044 16:31:30.661788 INFO: [NOCDAPC] D9_APC_0: 0x0
10045 16:31:30.665033 INFO: [NOCDAPC] D9_APC_1: 0xfff
10046 16:31:30.668417 INFO: [NOCDAPC] D10_APC_0: 0x0
10047 16:31:30.671747 INFO: [NOCDAPC] D10_APC_1: 0xfff
10048 16:31:30.675091 INFO: [NOCDAPC] D11_APC_0: 0x0
10049 16:31:30.678379 INFO: [NOCDAPC] D11_APC_1: 0xfff
10050 16:31:30.681673 INFO: [NOCDAPC] D12_APC_0: 0x0
10051 16:31:30.684903 INFO: [NOCDAPC] D12_APC_1: 0xfff
10052 16:31:30.687991 INFO: [NOCDAPC] D13_APC_0: 0x0
10053 16:31:30.691845 INFO: [NOCDAPC] D13_APC_1: 0xfff
10054 16:31:30.694636 INFO: [NOCDAPC] D14_APC_0: 0x0
10055 16:31:30.698061 INFO: [NOCDAPC] D14_APC_1: 0xfff
10056 16:31:30.701395 INFO: [NOCDAPC] D15_APC_0: 0x0
10057 16:31:30.704866 INFO: [NOCDAPC] D15_APC_1: 0xfff
10058 16:31:30.708269 INFO: [NOCDAPC] APC_CON: 0x4
10059 16:31:30.711054 INFO: [APUAPC] set_apusys_apc done
10060 16:31:30.711127 INFO: [DEVAPC] devapc_init done
10061 16:31:30.717636 INFO: GICv3 without legacy support detected.
10062 16:31:30.721179 INFO: ARM GICv3 driver initialized in EL3
10063 16:31:30.724248 INFO: Maximum SPI INTID supported: 639
10064 16:31:30.727566 INFO: BL31: Initializing runtime services
10065 16:31:30.734491 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10066 16:31:30.737738 INFO: SPM: enable CPC mode
10067 16:31:30.741073 INFO: mcdi ready for mcusys-off-idle and system suspend
10068 16:31:30.747707 INFO: BL31: Preparing for EL3 exit to normal world
10069 16:31:30.751274 INFO: Entry point address = 0x80000000
10070 16:31:30.753885 INFO: SPSR = 0x8
10071 16:31:30.758409
10072 16:31:30.758495
10073 16:31:30.758554
10074 16:31:30.761668 Starting depthcharge on Spherion...
10075 16:31:30.761745
10076 16:31:30.761804 Wipe memory regions:
10077 16:31:30.761860
10078 16:31:30.762479 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10079 16:31:30.762574 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10080 16:31:30.762650 Setting prompt string to ['asurada:']
10081 16:31:30.762722 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10082 16:31:30.764919 [0x00000040000000, 0x00000054600000)
10083 16:31:30.886463
10084 16:31:30.886593 [0x00000054660000, 0x00000080000000)
10085 16:31:31.146290
10086 16:31:31.146419 [0x000000821a7280, 0x000000ffe64000)
10087 16:31:31.890476
10088 16:31:31.890628 [0x00000100000000, 0x00000240000000)
10089 16:31:33.778044
10090 16:31:33.781157 Initializing XHCI USB controller at 0x11200000.
10091 16:31:34.820053
10092 16:31:34.822824 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10093 16:31:34.822896
10094 16:31:34.822954
10095 16:31:34.823222 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10097 16:31:34.923578 asurada: tftpboot 192.168.201.1 14396120/tftp-deploy-i999hvlk/kernel/image.itb 14396120/tftp-deploy-i999hvlk/kernel/cmdline
10098 16:31:34.923764 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10099 16:31:34.923857 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10100 16:31:34.928197 tftpboot 192.168.201.1 14396120/tftp-deploy-i999hvlk/kernel/image.ittp-deploy-i999hvlk/kernel/cmdline
10101 16:31:34.928292
10102 16:31:34.928353 Waiting for link
10103 16:31:35.085782
10104 16:31:35.085919 R8152: Initializing
10105 16:31:35.086005
10106 16:31:35.089154 Version 6 (ocp_data = 5c30)
10107 16:31:35.089231
10108 16:31:35.092642 R8152: Done initializing
10109 16:31:35.092739
10110 16:31:35.092803 Adding net device
10111 16:31:37.014882
10112 16:31:37.015023 done.
10113 16:31:37.015102
10114 16:31:37.015157 MAC: 00:24:32:30:78:ff
10115 16:31:37.015210
10116 16:31:37.018177 Sending DHCP discover... done.
10117 16:31:37.018255
10118 16:31:37.021647 Waiting for reply... done.
10119 16:31:37.021724
10120 16:31:37.024443 Sending DHCP request... done.
10121 16:31:37.024519
10122 16:31:37.028563 Waiting for reply... done.
10123 16:31:37.028689
10124 16:31:37.028782 My ip is 192.168.201.21
10125 16:31:37.028837
10126 16:31:37.031989 The DHCP server ip is 192.168.201.1
10127 16:31:37.032065
10128 16:31:37.038899 TFTP server IP predefined by user: 192.168.201.1
10129 16:31:37.039027
10130 16:31:37.045674 Bootfile predefined by user: 14396120/tftp-deploy-i999hvlk/kernel/image.itb
10131 16:31:37.045756
10132 16:31:37.048677 Sending tftp read request... done.
10133 16:31:37.048789
10134 16:31:37.048863 Waiting for the transfer...
10135 16:31:37.049009
10136 16:31:37.597490 00000000 ################################################################
10137 16:31:37.597633
10138 16:31:38.130698 00080000 ################################################################
10139 16:31:38.130846
10140 16:31:38.661485 00100000 ################################################################
10141 16:31:38.661644
10142 16:31:39.191303 00180000 ################################################################
10143 16:31:39.191442
10144 16:31:39.730333 00200000 ################################################################
10145 16:31:39.730459
10146 16:31:40.258564 00280000 ################################################################
10147 16:31:40.258708
10148 16:31:40.788718 00300000 ################################################################
10149 16:31:40.788856
10150 16:31:41.313508 00380000 ################################################################
10151 16:31:41.313636
10152 16:31:41.843877 00400000 ################################################################
10153 16:31:41.844009
10154 16:31:42.383478 00480000 ################################################################
10155 16:31:42.383643
10156 16:31:42.920494 00500000 ################################################################
10157 16:31:42.920666
10158 16:31:43.462552 00580000 ################################################################
10159 16:31:43.462726
10160 16:31:44.000570 00600000 ################################################################
10161 16:31:44.000739
10162 16:31:44.522514 00680000 ################################################################
10163 16:31:44.522671
10164 16:31:45.037978 00700000 ################################################################
10165 16:31:45.038110
10166 16:31:45.551552 00780000 ################################################################
10167 16:31:45.551712
10168 16:31:46.125828 00800000 ################################################################
10169 16:31:46.125960
10170 16:31:46.653585 00880000 ################################################################
10171 16:31:46.653740
10172 16:31:47.168752 00900000 ################################################################
10173 16:31:47.168888
10174 16:31:47.684306 00980000 ################################################################
10175 16:31:47.684462
10176 16:31:48.209987 00a00000 ################################################################
10177 16:31:48.210133
10178 16:31:48.754720 00a80000 ################################################################
10179 16:31:48.754883
10180 16:31:49.283277 00b00000 ################################################################
10181 16:31:49.283403
10182 16:31:49.798275 00b80000 ################################################################
10183 16:31:49.798421
10184 16:31:50.327621 00c00000 ################################################################
10185 16:31:50.327763
10186 16:31:50.853600 00c80000 ################################################################
10187 16:31:50.853734
10188 16:31:51.377185 00d00000 ################################################################
10189 16:31:51.377318
10190 16:31:51.895969 00d80000 ################################################################
10191 16:31:51.896099
10192 16:31:52.414076 00e00000 ################################################################
10193 16:31:52.414223
10194 16:31:52.950314 00e80000 ################################################################
10195 16:31:52.950431
10196 16:31:53.491557 00f00000 ################################################################
10197 16:31:53.491704
10198 16:31:54.035656 00f80000 ################################################################
10199 16:31:54.035771
10200 16:31:54.607428 01000000 ################################################################
10201 16:31:54.607577
10202 16:31:55.161817 01080000 ################################################################
10203 16:31:55.161944
10204 16:31:55.714558 01100000 ################################################################
10205 16:31:55.714710
10206 16:31:56.258517 01180000 ################################################################
10207 16:31:56.258658
10208 16:31:56.808411 01200000 ################################################################
10209 16:31:56.808560
10210 16:31:57.329949 01280000 ################################################################
10211 16:31:57.330106
10212 16:31:57.862000 01300000 ################################################################
10213 16:31:57.862119
10214 16:31:58.464527 01380000 ################################################################
10215 16:31:58.464712
10216 16:31:59.053329 01400000 ################################################################
10217 16:31:59.053458
10218 16:31:59.686920 01480000 ################################################################
10219 16:31:59.687040
10220 16:32:00.247957 01500000 ################################################################
10221 16:32:00.248082
10222 16:32:00.852581 01580000 ################################################################
10223 16:32:00.852734
10224 16:32:01.518094 01600000 ################################################################
10225 16:32:01.518727
10226 16:32:02.158040 01680000 ################################################################
10227 16:32:02.158157
10228 16:32:02.801806 01700000 ################################################################
10229 16:32:02.802283
10230 16:32:03.472606 01780000 ################################################################
10231 16:32:03.473172
10232 16:32:04.124218 01800000 ################################################################
10233 16:32:04.124455
10234 16:32:04.740980 01880000 ################################################################
10235 16:32:04.741119
10236 16:32:05.311963 01900000 ################################################################
10237 16:32:05.312441
10238 16:32:05.934205 01980000 ################################################################
10239 16:32:05.934321
10240 16:32:06.484315 01a00000 ################################################################
10241 16:32:06.484429
10242 16:32:07.069328 01a80000 ################################################################
10243 16:32:07.069443
10244 16:32:07.663099 01b00000 ################################################################
10245 16:32:07.663228
10246 16:32:08.264783 01b80000 ################################################################
10247 16:32:08.264902
10248 16:32:08.824131 01c00000 ################################################################
10249 16:32:08.824258
10250 16:32:09.392059 01c80000 ################################################################
10251 16:32:09.392184
10252 16:32:09.953466 01d00000 ################################################################
10253 16:32:09.953620
10254 16:32:10.527756 01d80000 ################################################################
10255 16:32:10.527872
10256 16:32:11.045499 01e00000 ######################################################### done.
10257 16:32:11.046179
10258 16:32:11.049029 The bootfile was 31922590 bytes long.
10259 16:32:11.049609
10260 16:32:11.052193 Sending tftp read request... done.
10261 16:32:11.052625
10262 16:32:11.057320 Waiting for the transfer...
10263 16:32:11.057905
10264 16:32:11.058536 00000000 # done.
10265 16:32:11.059162
10266 16:32:11.063782 Command line loaded dynamically from TFTP file: 14396120/tftp-deploy-i999hvlk/kernel/cmdline
10267 16:32:11.064400
10268 16:32:11.087736 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396120/extract-nfsrootfs-7a_4oqnq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10269 16:32:11.088230
10270 16:32:11.088802 Loading FIT.
10271 16:32:11.090575
10272 16:32:11.091020 Image ramdisk-1 has 18744549 bytes.
10273 16:32:11.091466
10274 16:32:11.094088 Image fdt-1 has 47258 bytes.
10275 16:32:11.094538
10276 16:32:11.097610 Image kernel-1 has 13128753 bytes.
10277 16:32:11.098058
10278 16:32:11.107028 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10279 16:32:11.107601
10280 16:32:11.123648 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10281 16:32:11.124020
10282 16:32:11.130547 Choosing best match conf-1 for compat google,spherion-rev2.
10283 16:32:11.130965
10284 16:32:11.138425 Connected to device vid:did:rid of 1ae0:0028:00
10285 16:32:11.145101
10286 16:32:11.148430 tpm_get_response: command 0x17b, return code 0x0
10287 16:32:11.148772
10288 16:32:11.154817 ec_init: CrosEC protocol v3 supported (256, 248)
10289 16:32:11.155253
10290 16:32:11.158338 tpm_cleanup: add release locality here.
10291 16:32:11.158773
10292 16:32:11.161553 Shutting down all USB controllers.
10293 16:32:11.161993
10294 16:32:11.164812 Removing current net device
10295 16:32:11.165249
10296 16:32:11.168600 Exiting depthcharge with code 4 at timestamp: 69838280
10297 16:32:11.169116
10298 16:32:11.171717 LZMA decompressing kernel-1 to 0x821a6718
10299 16:32:11.174763
10300 16:32:11.178534 LZMA decompressing kernel-1 to 0x40000000
10301 16:32:12.793531
10302 16:32:12.793691 jumping to kernel
10303 16:32:12.794557 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10304 16:32:12.794685 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10305 16:32:12.794785 Setting prompt string to ['Linux version [0-9]']
10306 16:32:12.794877 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10307 16:32:12.794973 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10308 16:32:12.876269
10309 16:32:12.879718 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10310 16:32:12.883439 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10311 16:32:12.883541 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10312 16:32:12.883611 Setting prompt string to []
10313 16:32:12.883683 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10314 16:32:12.883752 Using line separator: #'\n'#
10315 16:32:12.883807 No login prompt set.
10316 16:32:12.883865 Parsing kernel messages
10317 16:32:12.883917 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10318 16:32:12.884018 [login-action] Waiting for messages, (timeout 00:03:45)
10319 16:32:12.884082 Waiting using forced prompt support (timeout 00:01:52)
10320 16:32:12.903539 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j234605-arm64-gcc-10-defconfig-arm64-chromebook-rs2lc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024
10321 16:32:12.906259 [ 0.000000] random: crng init done
10322 16:32:12.913037 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10323 16:32:12.915812 [ 0.000000] efi: UEFI not found.
10324 16:32:12.922654 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10325 16:32:12.932395 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10326 16:32:12.939170 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10327 16:32:12.949032 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10328 16:32:12.955988 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10329 16:32:12.962248 [ 0.000000] printk: bootconsole [mtk8250] enabled
10330 16:32:12.969303 [ 0.000000] NUMA: No NUMA configuration found
10331 16:32:12.975712 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10332 16:32:12.979027 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10333 16:32:12.982443 [ 0.000000] Zone ranges:
10334 16:32:12.988963 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10335 16:32:12.992565 [ 0.000000] DMA32 empty
10336 16:32:12.998762 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10337 16:32:13.002159 [ 0.000000] Movable zone start for each node
10338 16:32:13.005411 [ 0.000000] Early memory node ranges
10339 16:32:13.011781 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10340 16:32:13.018749 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10341 16:32:13.025434 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10342 16:32:13.031713 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10343 16:32:13.038287 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10344 16:32:13.044780 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10345 16:32:13.101474 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10346 16:32:13.108206 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10347 16:32:13.114411 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10348 16:32:13.117889 [ 0.000000] psci: probing for conduit method from DT.
10349 16:32:13.124500 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10350 16:32:13.127624 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10351 16:32:13.134284 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10352 16:32:13.137385 [ 0.000000] psci: SMC Calling Convention v1.2
10353 16:32:13.144500 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10354 16:32:13.147824 [ 0.000000] Detected VIPT I-cache on CPU0
10355 16:32:13.154077 [ 0.000000] CPU features: detected: GIC system register CPU interface
10356 16:32:13.160953 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10357 16:32:13.167204 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10358 16:32:13.174380 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10359 16:32:13.180536 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10360 16:32:13.190760 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10361 16:32:13.194259 [ 0.000000] alternatives: applying boot alternatives
10362 16:32:13.200320 [ 0.000000] Fallback order for Node 0: 0
10363 16:32:13.206940 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10364 16:32:13.210274 [ 0.000000] Policy zone: Normal
10365 16:32:13.233963 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14396120/extract-nfsrootfs-7a_4oqnq,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10366 16:32:13.243396 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10367 16:32:13.253130 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10368 16:32:13.263360 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10369 16:32:13.270072 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10370 16:32:13.272783 <6>[ 0.000000] software IO TLB: area num 8.
10371 16:32:13.329762 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10372 16:32:13.478728 <6>[ 0.000000] Memory: 7945752K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407016K reserved, 32768K cma-reserved)
10373 16:32:13.485964 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10374 16:32:13.491979 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10375 16:32:13.495208 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10376 16:32:13.501764 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10377 16:32:13.508993 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10378 16:32:13.511908 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10379 16:32:13.521530 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10380 16:32:13.528173 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10381 16:32:13.535158 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10382 16:32:13.541434 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10383 16:32:13.544910 <6>[ 0.000000] GICv3: 608 SPIs implemented
10384 16:32:13.548241 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10385 16:32:13.554841 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10386 16:32:13.558272 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10387 16:32:13.565309 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10388 16:32:13.578091 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10389 16:32:13.591054 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10390 16:32:13.597957 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10391 16:32:13.605521 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10392 16:32:13.618650 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10393 16:32:13.625576 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10394 16:32:13.632212 <6>[ 0.009183] Console: colour dummy device 80x25
10395 16:32:13.642324 <6>[ 0.013914] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10396 16:32:13.648916 <6>[ 0.024356] pid_max: default: 32768 minimum: 301
10397 16:32:13.652195 <6>[ 0.029250] LSM: Security Framework initializing
10398 16:32:13.658938 <6>[ 0.034188] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10399 16:32:13.668342 <6>[ 0.042003] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10400 16:32:13.678507 <6>[ 0.051419] cblist_init_generic: Setting adjustable number of callback queues.
10401 16:32:13.681985 <6>[ 0.058909] cblist_init_generic: Setting shift to 3 and lim to 1.
10402 16:32:13.691588 <6>[ 0.065247] cblist_init_generic: Setting adjustable number of callback queues.
10403 16:32:13.698125 <6>[ 0.072719] cblist_init_generic: Setting shift to 3 and lim to 1.
10404 16:32:13.701529 <6>[ 0.079120] rcu: Hierarchical SRCU implementation.
10405 16:32:13.707723 <6>[ 0.084134] rcu: Max phase no-delay instances is 1000.
10406 16:32:13.714750 <6>[ 0.091169] EFI services will not be available.
10407 16:32:13.718178 <6>[ 0.096116] smp: Bringing up secondary CPUs ...
10408 16:32:13.726281 <6>[ 0.101168] Detected VIPT I-cache on CPU1
10409 16:32:13.732688 <6>[ 0.101240] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10410 16:32:13.739476 <6>[ 0.101271] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10411 16:32:13.742680 <6>[ 0.101606] Detected VIPT I-cache on CPU2
10412 16:32:13.749323 <6>[ 0.101655] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10413 16:32:13.759263 <6>[ 0.101672] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10414 16:32:13.762914 <6>[ 0.101927] Detected VIPT I-cache on CPU3
10415 16:32:13.769089 <6>[ 0.101975] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10416 16:32:13.775962 <6>[ 0.101989] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10417 16:32:13.779312 <6>[ 0.102293] CPU features: detected: Spectre-v4
10418 16:32:13.786024 <6>[ 0.102299] CPU features: detected: Spectre-BHB
10419 16:32:13.789199 <6>[ 0.102304] Detected PIPT I-cache on CPU4
10420 16:32:13.795727 <6>[ 0.102363] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10421 16:32:13.802237 <6>[ 0.102379] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10422 16:32:13.808912 <6>[ 0.102669] Detected PIPT I-cache on CPU5
10423 16:32:13.815741 <6>[ 0.102731] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10424 16:32:13.822076 <6>[ 0.102747] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10425 16:32:13.825471 <6>[ 0.103029] Detected PIPT I-cache on CPU6
10426 16:32:13.832185 <6>[ 0.103091] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10427 16:32:13.838826 <6>[ 0.103107] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10428 16:32:13.845282 <6>[ 0.103403] Detected PIPT I-cache on CPU7
10429 16:32:13.851782 <6>[ 0.103466] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10430 16:32:13.858456 <6>[ 0.103482] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10431 16:32:13.861767 <6>[ 0.103530] smp: Brought up 1 node, 8 CPUs
10432 16:32:13.868473 <6>[ 0.244879] SMP: Total of 8 processors activated.
10433 16:32:13.871714 <6>[ 0.249800] CPU features: detected: 32-bit EL0 Support
10434 16:32:13.881744 <6>[ 0.255196] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10435 16:32:13.887980 <6>[ 0.264051] CPU features: detected: Common not Private translations
10436 16:32:13.894795 <6>[ 0.270526] CPU features: detected: CRC32 instructions
10437 16:32:13.898174 <6>[ 0.275911] CPU features: detected: RCpc load-acquire (LDAPR)
10438 16:32:13.904807 <6>[ 0.281871] CPU features: detected: LSE atomic instructions
10439 16:32:13.911549 <6>[ 0.287653] CPU features: detected: Privileged Access Never
10440 16:32:13.918427 <6>[ 0.293432] CPU features: detected: RAS Extension Support
10441 16:32:13.924532 <6>[ 0.299041] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10442 16:32:13.928081 <6>[ 0.306304] CPU: All CPU(s) started at EL2
10443 16:32:13.934923 <6>[ 0.310621] alternatives: applying system-wide alternatives
10444 16:32:13.944379 <6>[ 0.321497] devtmpfs: initialized
10445 16:32:13.956387 <6>[ 0.330425] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10446 16:32:13.966861 <6>[ 0.340387] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10447 16:32:13.970122 <6>[ 0.348095] pinctrl core: initialized pinctrl subsystem
10448 16:32:13.977592 <6>[ 0.354790] DMI not present or invalid.
10449 16:32:13.984232 <6>[ 0.359201] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10450 16:32:13.990738 <6>[ 0.366060] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10451 16:32:14.000820 <6>[ 0.373648] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10452 16:32:14.007513 <6>[ 0.381867] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10453 16:32:14.013980 <6>[ 0.390109] audit: initializing netlink subsys (disabled)
10454 16:32:14.020851 <5>[ 0.395804] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10455 16:32:14.027722 <6>[ 0.396525] thermal_sys: Registered thermal governor 'step_wise'
10456 16:32:14.034002 <6>[ 0.403769] thermal_sys: Registered thermal governor 'power_allocator'
10457 16:32:14.037452 <6>[ 0.410027] cpuidle: using governor menu
10458 16:32:14.044064 <6>[ 0.420988] NET: Registered PF_QIPCRTR protocol family
10459 16:32:14.050795 <6>[ 0.426475] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10460 16:32:14.056820 <6>[ 0.433576] ASID allocator initialised with 32768 entries
10461 16:32:14.063264 <6>[ 0.440167] Serial: AMBA PL011 UART driver
10462 16:32:14.071717 <4>[ 0.449001] Trying to register duplicate clock ID: 134
10463 16:32:14.130040 <6>[ 0.510637] KASLR enabled
10464 16:32:14.144527 <6>[ 0.518373] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10465 16:32:14.151166 <6>[ 0.525384] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10466 16:32:14.157841 <6>[ 0.531873] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10467 16:32:14.164335 <6>[ 0.538877] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10468 16:32:14.171140 <6>[ 0.545363] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10469 16:32:14.177452 <6>[ 0.552370] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10470 16:32:14.184046 <6>[ 0.558855] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10471 16:32:14.190948 <6>[ 0.565860] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10472 16:32:14.194278 <6>[ 0.573398] ACPI: Interpreter disabled.
10473 16:32:14.202485 <6>[ 0.579825] iommu: Default domain type: Translated
10474 16:32:14.209241 <6>[ 0.584939] iommu: DMA domain TLB invalidation policy: strict mode
10475 16:32:14.212569 <5>[ 0.591600] SCSI subsystem initialized
10476 16:32:14.219370 <6>[ 0.595769] usbcore: registered new interface driver usbfs
10477 16:32:14.284980 <6>[ 0.601499] usbcore: registered new interface driver hub
10478 16:32:14.285141 <6>[ 0.607053] usbcore: registered new device driver usb
10479 16:32:14.285206 <6>[ 0.613153] pps_core: LinuxPPS API ver. 1 registered
10480 16:32:14.285264 <6>[ 0.618346] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10481 16:32:14.285321 <6>[ 0.627693] PTP clock support registered
10482 16:32:14.285374 <6>[ 0.631938] EDAC MC: Ver: 3.0.0
10483 16:32:14.285427 <6>[ 0.637097] FPGA manager framework
10484 16:32:14.285479 <6>[ 0.640782] Advanced Linux Sound Architecture Driver Initialized.
10485 16:32:14.285531 <6>[ 0.647570] vgaarb: loaded
10486 16:32:14.285582 <6>[ 0.650731] clocksource: Switched to clocksource arch_sys_counter
10487 16:32:14.285634 <5>[ 0.657173] VFS: Disk quotas dquot_6.6.0
10488 16:32:14.286462 <6>[ 0.661360] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10489 16:32:14.289935 <6>[ 0.668551] pnp: PnP ACPI: disabled
10490 16:32:14.298041 <6>[ 0.675326] NET: Registered PF_INET protocol family
10491 16:32:14.308162 <6>[ 0.680924] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10492 16:32:14.319232 <6>[ 0.693262] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10493 16:32:14.329550 <6>[ 0.702077] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10494 16:32:14.336273 <6>[ 0.710050] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10495 16:32:14.342892 <6>[ 0.718752] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10496 16:32:14.354769 <6>[ 0.728508] TCP: Hash tables configured (established 65536 bind 65536)
10497 16:32:14.361422 <6>[ 0.735375] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10498 16:32:14.368108 <6>[ 0.742577] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10499 16:32:14.374199 <6>[ 0.750281] NET: Registered PF_UNIX/PF_LOCAL protocol family
10500 16:32:14.381164 <6>[ 0.756435] RPC: Registered named UNIX socket transport module.
10501 16:32:14.384428 <6>[ 0.762588] RPC: Registered udp transport module.
10502 16:32:14.390873 <6>[ 0.767521] RPC: Registered tcp transport module.
10503 16:32:14.397868 <6>[ 0.772451] RPC: Registered tcp NFSv4.1 backchannel transport module.
10504 16:32:14.401309 <6>[ 0.779117] PCI: CLS 0 bytes, default 64
10505 16:32:14.404444 <6>[ 0.783388] Unpacking initramfs...
10506 16:32:14.428939 <6>[ 0.802834] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10507 16:32:14.438824 <6>[ 0.811490] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10508 16:32:14.442293 <6>[ 0.820361] kvm [1]: IPA Size Limit: 40 bits
10509 16:32:14.448804 <6>[ 0.824886] kvm [1]: GICv3: no GICV resource entry
10510 16:32:14.452221 <6>[ 0.829908] kvm [1]: disabling GICv2 emulation
10511 16:32:14.458744 <6>[ 0.834602] kvm [1]: GIC system register CPU interface enabled
10512 16:32:14.461966 <6>[ 0.840759] kvm [1]: vgic interrupt IRQ18
10513 16:32:14.468442 <6>[ 0.845113] kvm [1]: VHE mode initialized successfully
10514 16:32:14.475004 <5>[ 0.851503] Initialise system trusted keyrings
10515 16:32:14.481454 <6>[ 0.856346] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10516 16:32:14.488791 <6>[ 0.866322] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10517 16:32:14.496046 <5>[ 0.872720] NFS: Registering the id_resolver key type
10518 16:32:14.499247 <5>[ 0.878022] Key type id_resolver registered
10519 16:32:14.505443 <5>[ 0.882437] Key type id_legacy registered
10520 16:32:14.512129 <6>[ 0.886737] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10521 16:32:14.518743 <6>[ 0.893659] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10522 16:32:14.525201 <6>[ 0.901373] 9p: Installing v9fs 9p2000 file system support
10523 16:32:14.562192 <5>[ 0.939551] Key type asymmetric registered
10524 16:32:14.565705 <5>[ 0.943883] Asymmetric key parser 'x509' registered
10525 16:32:14.575406 <6>[ 0.949046] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10526 16:32:14.579234 <6>[ 0.956659] io scheduler mq-deadline registered
10527 16:32:14.581813 <6>[ 0.961440] io scheduler kyber registered
10528 16:32:14.601318 <6>[ 0.978561] EINJ: ACPI disabled.
10529 16:32:14.634162 <4>[ 1.004767] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10530 16:32:14.644318 <4>[ 1.015417] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10531 16:32:14.659344 <6>[ 1.036633] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10532 16:32:14.667795 <6>[ 1.044703] printk: console [ttyS0] disabled
10533 16:32:14.695239 <6>[ 1.069332] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10534 16:32:14.701841 <6>[ 1.078807] printk: console [ttyS0] enabled
10535 16:32:14.705496 <6>[ 1.078807] printk: console [ttyS0] enabled
10536 16:32:14.711883 <6>[ 1.087701] printk: bootconsole [mtk8250] disabled
10537 16:32:14.715090 <6>[ 1.087701] printk: bootconsole [mtk8250] disabled
10538 16:32:14.721815 <6>[ 1.098832] SuperH (H)SCI(F) driver initialized
10539 16:32:14.724868 <6>[ 1.104115] msm_serial: driver initialized
10540 16:32:14.739109 <6>[ 1.113072] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10541 16:32:14.749205 <6>[ 1.121626] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10542 16:32:14.755976 <6>[ 1.130171] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10543 16:32:14.765451 <6>[ 1.138801] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10544 16:32:14.775865 <6>[ 1.147508] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10545 16:32:14.782515 <6>[ 1.156222] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10546 16:32:14.792532 <6>[ 1.164769] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10547 16:32:14.798624 <6>[ 1.173568] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10548 16:32:14.808652 <6>[ 1.182110] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10549 16:32:14.820631 <6>[ 1.197737] loop: module loaded
10550 16:32:14.826762 <6>[ 1.203601] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10551 16:32:14.849855 <4>[ 1.226938] mtk-pmic-keys: Failed to locate of_node [id: -1]
10552 16:32:14.856093 <6>[ 1.233724] megasas: 07.719.03.00-rc1
10553 16:32:14.866252 <6>[ 1.243573] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10554 16:32:14.873071 <6>[ 1.250125] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10555 16:32:14.889964 <6>[ 1.266871] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10556 16:32:14.946011 <6>[ 1.316665] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10557 16:32:15.191028 <6>[ 1.568293] Freeing initrd memory: 18304K
10558 16:32:15.202965 <6>[ 1.580033] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10559 16:32:15.213778 <6>[ 1.590961] tun: Universal TUN/TAP device driver, 1.6
10560 16:32:15.217168 <6>[ 1.597013] thunder_xcv, ver 1.0
10561 16:32:15.220641 <6>[ 1.600516] thunder_bgx, ver 1.0
10562 16:32:15.223977 <6>[ 1.604011] nicpf, ver 1.0
10563 16:32:15.234207 <6>[ 1.608030] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10564 16:32:15.237591 <6>[ 1.615505] hns3: Copyright (c) 2017 Huawei Corporation.
10565 16:32:15.243782 <6>[ 1.621093] hclge is initializing
10566 16:32:15.247125 <6>[ 1.624675] e1000: Intel(R) PRO/1000 Network Driver
10567 16:32:15.253950 <6>[ 1.629803] e1000: Copyright (c) 1999-2006 Intel Corporation.
10568 16:32:15.257270 <6>[ 1.635823] e1000e: Intel(R) PRO/1000 Network Driver
10569 16:32:15.263582 <6>[ 1.641039] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10570 16:32:15.270703 <6>[ 1.647224] igb: Intel(R) Gigabit Ethernet Network Driver
10571 16:32:15.277385 <6>[ 1.652873] igb: Copyright (c) 2007-2014 Intel Corporation.
10572 16:32:15.283578 <6>[ 1.658709] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10573 16:32:15.290472 <6>[ 1.665227] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10574 16:32:15.293810 <6>[ 1.671687] sky2: driver version 1.30
10575 16:32:15.300185 <6>[ 1.676622] usbcore: registered new device driver r8152-cfgselector
10576 16:32:15.307471 <6>[ 1.683156] usbcore: registered new interface driver r8152
10577 16:32:15.310568 <6>[ 1.688975] VFIO - User Level meta-driver version: 0.3
10578 16:32:15.319951 <6>[ 1.697210] usbcore: registered new interface driver usb-storage
10579 16:32:15.326816 <6>[ 1.703656] usbcore: registered new device driver onboard-usb-hub
10580 16:32:15.335753 <6>[ 1.712841] mt6397-rtc mt6359-rtc: registered as rtc0
10581 16:32:15.345374 <6>[ 1.718312] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-17T16:32:14 UTC (1718641934)
10582 16:32:15.348757 <6>[ 1.727876] i2c_dev: i2c /dev entries driver
10583 16:32:15.362574 <4>[ 1.739949] cpu cpu0: supply cpu not found, using dummy regulator
10584 16:32:15.369682 <4>[ 1.746379] cpu cpu1: supply cpu not found, using dummy regulator
10585 16:32:15.376036 <4>[ 1.752785] cpu cpu2: supply cpu not found, using dummy regulator
10586 16:32:15.382927 <4>[ 1.759184] cpu cpu3: supply cpu not found, using dummy regulator
10587 16:32:15.389284 <4>[ 1.765583] cpu cpu4: supply cpu not found, using dummy regulator
10588 16:32:15.396182 <4>[ 1.771977] cpu cpu5: supply cpu not found, using dummy regulator
10589 16:32:15.402803 <4>[ 1.778390] cpu cpu6: supply cpu not found, using dummy regulator
10590 16:32:15.409419 <4>[ 1.784790] cpu cpu7: supply cpu not found, using dummy regulator
10591 16:32:15.428266 <6>[ 1.805434] cpu cpu0: EM: created perf domain
10592 16:32:15.431384 <6>[ 1.810365] cpu cpu4: EM: created perf domain
10593 16:32:15.438973 <6>[ 1.815998] sdhci: Secure Digital Host Controller Interface driver
10594 16:32:15.445719 <6>[ 1.822430] sdhci: Copyright(c) Pierre Ossman
10595 16:32:15.451841 <6>[ 1.827385] Synopsys Designware Multimedia Card Interface Driver
10596 16:32:15.458507 <6>[ 1.834025] sdhci-pltfm: SDHCI platform and OF driver helper
10597 16:32:15.461881 <6>[ 1.834148] mmc0: CQHCI version 5.10
10598 16:32:15.468800 <6>[ 1.844111] ledtrig-cpu: registered to indicate activity on CPUs
10599 16:32:15.475206 <6>[ 1.851170] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10600 16:32:15.481798 <6>[ 1.858241] usbcore: registered new interface driver usbhid
10601 16:32:15.485044 <6>[ 1.864062] usbhid: USB HID core driver
10602 16:32:15.491899 <6>[ 1.868277] spi_master spi0: will run message pump with realtime priority
10603 16:32:15.535137 <6>[ 1.905793] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10604 16:32:15.553024 <6>[ 1.920757] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10605 16:32:15.556988 <6>[ 1.931378] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17c14
10606 16:32:15.564509 <6>[ 1.941201] cros-ec-spi spi0.0: Chrome EC device registered
10607 16:32:15.570743 <6>[ 1.947208] mmc0: Command Queue Engine enabled
10608 16:32:15.577700 <6>[ 1.951941] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10609 16:32:15.581142 <6>[ 1.959674] mmcblk0: mmc0:0001 DA4128 116 GiB
10610 16:32:15.590995 <6>[ 1.968452] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10611 16:32:15.598976 <6>[ 1.976143] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10612 16:32:15.608777 <6>[ 1.981659] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10613 16:32:15.615636 <6>[ 1.982083] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10614 16:32:15.618436 <6>[ 1.992429] NET: Registered PF_PACKET protocol family
10615 16:32:15.625364 <6>[ 1.996840] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10616 16:32:15.628898 <6>[ 2.001575] 9pnet: Installing 9P2000 support
10617 16:32:15.635385 <5>[ 2.012587] Key type dns_resolver registered
10618 16:32:15.638779 <6>[ 2.017555] registered taskstats version 1
10619 16:32:15.645386 <5>[ 2.021939] Loading compiled-in X.509 certificates
10620 16:32:15.673710 <4>[ 2.044454] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10621 16:32:15.683970 <4>[ 2.055187] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10622 16:32:15.698818 <6>[ 2.076150] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10623 16:32:15.705553 <6>[ 2.083024] xhci-mtk 11200000.usb: xHCI Host Controller
10624 16:32:15.712898 <6>[ 2.088533] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10625 16:32:15.722588 <6>[ 2.096378] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10626 16:32:15.729123 <6>[ 2.105802] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10627 16:32:15.735708 <6>[ 2.111885] xhci-mtk 11200000.usb: xHCI Host Controller
10628 16:32:15.742287 <6>[ 2.117364] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10629 16:32:15.749061 <6>[ 2.125017] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10630 16:32:15.755769 <6>[ 2.132636] hub 1-0:1.0: USB hub found
10631 16:32:15.759063 <6>[ 2.136653] hub 1-0:1.0: 1 port detected
10632 16:32:15.765900 <6>[ 2.140913] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10633 16:32:15.772312 <6>[ 2.149445] hub 2-0:1.0: USB hub found
10634 16:32:15.775449 <6>[ 2.153453] hub 2-0:1.0: 1 port detected
10635 16:32:15.783154 <6>[ 2.160464] mtk-msdc 11f70000.mmc: Got CD GPIO
10636 16:32:15.800405 <6>[ 2.174644] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10637 16:32:15.810407 <6>[ 2.183213] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10638 16:32:15.817059 <6>[ 2.191671] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10639 16:32:15.827348 <6>[ 2.200043] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10640 16:32:15.833881 <6>[ 2.208476] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10641 16:32:15.844007 <6>[ 2.216849] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10642 16:32:15.850105 <6>[ 2.225253] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10643 16:32:15.860251 <6>[ 2.233591] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10644 16:32:15.867169 <6>[ 2.241943] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10645 16:32:15.877233 <6>[ 2.250282] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10646 16:32:15.883935 <6>[ 2.258631] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10647 16:32:15.894201 <6>[ 2.266975] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10648 16:32:15.900243 <6>[ 2.275324] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10649 16:32:15.910571 <6>[ 2.283663] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10650 16:32:15.917063 <6>[ 2.292012] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10651 16:32:15.923811 <6>[ 2.300810] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10652 16:32:15.931258 <6>[ 2.308060] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10653 16:32:15.937456 <6>[ 2.314848] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10654 16:32:15.947270 <6>[ 2.321612] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10655 16:32:15.954480 <6>[ 2.328559] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10656 16:32:15.960611 <6>[ 2.335428] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10657 16:32:15.970313 <6>[ 2.344556] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10658 16:32:15.980891 <6>[ 2.353676] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10659 16:32:15.990352 <6>[ 2.362971] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10660 16:32:16.000070 <6>[ 2.372438] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10661 16:32:16.009953 <6>[ 2.381905] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10662 16:32:16.017089 <6>[ 2.391025] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10663 16:32:16.027036 <6>[ 2.400491] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10664 16:32:16.036432 <6>[ 2.409610] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10665 16:32:16.046470 <6>[ 2.418905] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10666 16:32:16.056036 <6>[ 2.429064] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10667 16:32:16.066756 <6>[ 2.440683] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10668 16:32:16.074231 <6>[ 2.451809] Trying to probe devices needed for running init ...
10669 16:32:16.084722 <3>[ 2.459080] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10670 16:32:16.192622 <6>[ 2.567012] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10671 16:32:16.347422 <6>[ 2.725059] hub 1-1:1.0: USB hub found
10672 16:32:16.350857 <6>[ 2.729581] hub 1-1:1.0: 4 ports detected
10673 16:32:16.362853 <6>[ 2.740441] hub 1-1:1.0: USB hub found
10674 16:32:16.366375 <6>[ 2.744743] hub 1-1:1.0: 4 ports detected
10675 16:32:16.472957 <6>[ 2.847182] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10676 16:32:16.498732 <6>[ 2.876162] hub 2-1:1.0: USB hub found
10677 16:32:16.501797 <6>[ 2.880616] hub 2-1:1.0: 3 ports detected
10678 16:32:16.513919 <6>[ 2.891124] hub 2-1:1.0: USB hub found
10679 16:32:16.517035 <6>[ 2.895645] hub 2-1:1.0: 3 ports detected
10680 16:32:16.688806 <6>[ 3.063042] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10681 16:32:16.821173 <6>[ 3.198677] hub 1-1.4:1.0: USB hub found
10682 16:32:16.824428 <6>[ 3.203337] hub 1-1.4:1.0: 2 ports detected
10683 16:32:16.837325 <6>[ 3.214681] hub 1-1.4:1.0: USB hub found
10684 16:32:16.840505 <6>[ 3.219294] hub 1-1.4:1.0: 2 ports detected
10685 16:32:16.901113 <6>[ 3.275200] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10686 16:32:17.009315 <6>[ 3.383689] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10687 16:32:17.046200 <4>[ 3.420599] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10688 16:32:17.056521 <4>[ 3.429725] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10689 16:32:17.095076 <6>[ 3.472636] r8152 2-1.3:1.0 eth0: v1.12.13
10690 16:32:17.148481 <6>[ 3.522971] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10691 16:32:17.340775 <6>[ 3.714856] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10692 16:32:18.669615 <6>[ 5.047130] r8152 2-1.3:1.0 eth0: carrier on
10693 16:32:21.365146 <5>[ 5.070846] Sending DHCP requests .., OK
10694 16:32:21.371549 <6>[ 7.747236] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10695 16:32:21.374898 <6>[ 7.755557] IP-Config: Complete:
10696 16:32:21.388120 <6>[ 7.759052] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10697 16:32:21.394830 <6>[ 7.769761] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10698 16:32:21.401175 <6>[ 7.778378] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10699 16:32:21.407661 <6>[ 7.778387] nameserver0=192.168.201.1
10700 16:32:21.411221 <6>[ 7.790543] clk: Disabling unused clocks
10701 16:32:21.415066 <6>[ 7.796011] ALSA device list:
10702 16:32:21.421389 <6>[ 7.799312] No soundcards found.
10703 16:32:21.429152 <6>[ 7.806954] Freeing unused kernel memory: 8512K
10704 16:32:21.432114 <6>[ 7.811891] Run /init as init process
10705 16:32:21.442817 Loading, please wait...
10706 16:32:21.469148 Starting systemd-udevd version 252.22-1~deb12u1
10707 16:32:21.724603 <6>[ 8.099363] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10708 16:32:21.738597 <6>[ 8.113364] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10709 16:32:21.745039 <6>[ 8.118592] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10710 16:32:21.755034 <6>[ 8.121142] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10711 16:32:21.765409 <6>[ 8.121156] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10712 16:32:21.771715 <6>[ 8.146790] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10713 16:32:21.781721 <4>[ 8.155061] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10714 16:32:21.787933 <3>[ 8.158657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 16:32:21.797820 <6>[ 8.164727] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10716 16:32:21.804492 <3>[ 8.172357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 16:32:21.814373 <6>[ 8.180331] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10718 16:32:21.821076 <3>[ 8.188407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 16:32:21.827632 <6>[ 8.197525] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10720 16:32:21.837954 <6>[ 8.212395] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10721 16:32:21.844167 <3>[ 8.213583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 16:32:21.854228 <6>[ 8.220218] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10723 16:32:21.860798 <6>[ 8.220221] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10724 16:32:21.870609 <4>[ 8.230038] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10725 16:32:21.877181 <3>[ 8.236208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 16:32:21.884238 <6>[ 8.252213] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10727 16:32:21.890839 <6>[ 8.252304] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10728 16:32:21.900584 <3>[ 8.252586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 16:32:21.906911 <6>[ 8.260796] pci_bus 0000:00: root bus resource [bus 00-ff]
10730 16:32:21.913610 <3>[ 8.267525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 16:32:21.920463 <3>[ 8.267529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 16:32:21.930244 <4>[ 8.291669] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10733 16:32:21.933731 <6>[ 8.293177] remoteproc remoteproc0: scp is available
10734 16:32:21.939837 <6>[ 8.296770] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10735 16:32:21.946738 <6>[ 8.296953] remoteproc remoteproc0: powering up scp
10736 16:32:21.956744 <6>[ 8.296960] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10737 16:32:21.959739 <6>[ 8.296993] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10738 16:32:21.970198 <3>[ 8.305477] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 16:32:21.979458 <6>[ 8.313895] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10740 16:32:21.986559 <3>[ 8.321673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 16:32:21.993048 <6>[ 8.324670] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10742 16:32:21.999586 <3>[ 8.329761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 16:32:22.009564 <6>[ 8.335524] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10744 16:32:22.019604 <6>[ 8.338195] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10745 16:32:22.026188 <3>[ 8.343834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 16:32:22.032452 <6>[ 8.351989] pci 0000:00:00.0: supports D1 D2
10747 16:32:22.039177 <3>[ 8.362646] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 16:32:22.049236 <6>[ 8.362710] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10749 16:32:22.056046 <6>[ 8.363646] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10750 16:32:22.062535 <6>[ 8.369887] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10751 16:32:22.072263 <6>[ 8.370865] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10752 16:32:22.078943 <3>[ 8.376146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 16:32:22.088745 <4>[ 8.389098] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10754 16:32:22.092624 <4>[ 8.389098] Fallback method does not support PEC.
10755 16:32:22.102402 <3>[ 8.394303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 16:32:22.108943 <3>[ 8.394310] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 16:32:22.119039 <3>[ 8.394313] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 16:32:22.125540 <6>[ 8.422831] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10759 16:32:22.131988 <6>[ 8.422839] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10760 16:32:22.138710 <6>[ 8.422852] remoteproc remoteproc0: remote processor scp is now up
10761 16:32:22.145532 <6>[ 8.523045] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10762 16:32:22.152233 <6>[ 8.523574] mc: Linux media interface: v0.10
10763 16:32:22.158910 <3>[ 8.524290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 16:32:22.165595 <6>[ 8.529367] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10765 16:32:22.175779 <3>[ 8.537685] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10766 16:32:22.182567 <6>[ 8.541945] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10767 16:32:22.192925 <6>[ 8.554800] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10768 16:32:22.199571 <6>[ 8.558195] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10769 16:32:22.209420 <3>[ 8.574115] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10770 16:32:22.212769 <6>[ 8.575053] pci 0000:01:00.0: supports D1 D2
10771 16:32:22.219467 <6>[ 8.595705] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10772 16:32:22.242873 <6>[ 8.621166] videodev: Linux video capture interface: v2.00
10773 16:32:22.250132 <6>[ 8.622844] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10774 16:32:22.259929 <6>[ 8.628699] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10775 16:32:22.266245 <6>[ 8.633893] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10776 16:32:22.276326 <6>[ 8.633899] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10777 16:32:22.282734 <6>[ 8.633911] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10778 16:32:22.292830 <6>[ 8.633925] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10779 16:32:22.299643 <6>[ 8.633938] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10780 16:32:22.302787 <6>[ 8.633951] pci 0000:00:00.0: PCI bridge to [bus 01]
10781 16:32:22.312743 <6>[ 8.633957] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10782 16:32:22.319265 <6>[ 8.634125] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10783 16:32:22.325940 <6>[ 8.645589] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10784 16:32:22.332584 <6>[ 8.651045] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10785 16:32:22.335979 <6>[ 8.651098] Bluetooth: Core ver 2.22
10786 16:32:22.342756 <6>[ 8.651160] NET: Registered PF_BLUETOOTH protocol family
10787 16:32:22.349389 <6>[ 8.651163] Bluetooth: HCI device and connection manager initialized
10788 16:32:22.356011 <6>[ 8.651182] Bluetooth: HCI socket layer initialized
10789 16:32:22.359336 <6>[ 8.651188] Bluetooth: L2CAP socket layer initialized
10790 16:32:22.365606 <6>[ 8.651199] Bluetooth: SCO socket layer initialized
10791 16:32:22.372232 <6>[ 8.683906] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10792 16:32:22.378798 <6>[ 8.688739] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10793 16:32:22.389195 <6>[ 8.697394] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10794 16:32:22.395472 <6>[ 8.703006] usbcore: registered new interface driver btusb
10795 16:32:22.405648 <4>[ 8.704092] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10796 16:32:22.412163 <3>[ 8.704099] Bluetooth: hci0: Failed to load firmware file (-2)
10797 16:32:22.418725 <3>[ 8.704100] Bluetooth: hci0: Failed to set up firmware (-2)
10798 16:32:22.428831 <4>[ 8.704102] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10799 16:32:22.435379 <6>[ 8.710672] usbcore: registered new interface driver uvcvideo
10800 16:32:22.441788 <6>[ 8.711028] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10801 16:32:22.448238 <5>[ 8.719257] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10802 16:32:22.477881 <5>[ 8.852932] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10803 16:32:22.484560 <5>[ 8.860084] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10804 16:32:22.494945 <4>[ 8.868502] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10805 16:32:22.498044 <6>[ 8.877375] cfg80211: failed to load regulatory.db
10806 16:32:22.545791 <6>[ 8.920439] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10807 16:32:22.552370 <6>[ 8.927940] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10808 16:32:22.576871 <6>[ 8.954677] mt7921e 0000:01:00.0: ASIC revision: 79610010
10809 16:32:22.679614 <6>[ 9.054621] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10810 16:32:22.682915 <6>[ 9.054621]
10811 16:32:22.697972 Begin: Loading essential drivers ... done.
10812 16:32:22.701292 Begin: Running /scripts/init-premount ... done.
10813 16:32:22.707875 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10814 16:32:22.717284 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10815 16:32:22.720953 Device /sys/class/net/eth0 found
10816 16:32:22.721023 done.
10817 16:32:22.732141 Begin: Waiting up to 180 secs for any network device to become available ... done.
10818 16:32:22.780832 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10819 16:32:22.787971 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10820 16:32:22.794514 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10821 16:32:22.801572 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10822 16:32:22.808121 host : mt8192-asurada-spherion-r0-cbg-8
10823 16:32:22.814764 domain : lava-rack
10824 16:32:22.817979 rootserver: 192.168.201.1 rootpath:
10825 16:32:22.820982 filename :
10826 16:32:22.824294 done.
10827 16:32:22.832037 Begin: Running /scripts/nfs-bottom ... done.
10828 16:32:22.855554 Begin: Running /scripts/init-bottom ... done.
10829 16:32:22.948414 <6>[ 9.323107] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10830 16:32:24.197172 <6>[ 10.575605] NET: Registered PF_INET6 protocol family
10831 16:32:24.204789 <6>[ 10.583028] Segment Routing with IPv6
10832 16:32:24.207986 <6>[ 10.587023] In-situ OAM (IOAM) with IPv6
10833 16:32:24.382698 <30>[ 10.734669] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10834 16:32:24.389280 <30>[ 10.767822] systemd[1]: Detected architecture arm64.
10835 16:32:24.398647
10836 16:32:24.401808 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10837 16:32:24.401904
10838 16:32:24.430408 <30>[ 10.808852] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10839 16:32:25.473136 <30>[ 11.848597] systemd[1]: Queued start job for default target graphical.target.
10840 16:32:25.504850 <30>[ 11.880068] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10841 16:32:25.511297 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10842 16:32:25.534036 <30>[ 11.908875] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10843 16:32:25.543733 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10844 16:32:25.561905 <30>[ 11.936742] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10845 16:32:25.571339 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10846 16:32:25.589885 <30>[ 11.965217] systemd[1]: Created slice user.slice - User and Session Slice.
10847 16:32:25.596467 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10848 16:32:25.620181 <30>[ 11.991796] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10849 16:32:25.629696 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10850 16:32:25.647800 <30>[ 12.019261] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10851 16:32:25.653767 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10852 16:32:25.682218 <30>[ 12.047661] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10853 16:32:25.692223 <30>[ 12.067560] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10854 16:32:25.698756 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10855 16:32:25.715894 <30>[ 12.091400] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10856 16:32:25.725810 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10857 16:32:25.743874 <30>[ 12.118959] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10858 16:32:25.753445 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10859 16:32:25.768692 <30>[ 12.147106] systemd[1]: Reached target paths.target - Path Units.
10860 16:32:25.778538 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10861 16:32:25.796076 <30>[ 12.171066] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10862 16:32:25.802357 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10863 16:32:25.816539 <30>[ 12.195003] systemd[1]: Reached target slices.target - Slice Units.
10864 16:32:25.826887 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10865 16:32:25.840378 <30>[ 12.219061] systemd[1]: Reached target swap.target - Swaps.
10866 16:32:25.847482 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10867 16:32:25.868376 <30>[ 12.243498] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10868 16:32:25.878783 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10869 16:32:25.896968 <30>[ 12.272013] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10870 16:32:25.906862 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10871 16:32:25.927629 <30>[ 12.302630] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10872 16:32:25.937264 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10873 16:32:25.953653 <30>[ 12.328681] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10874 16:32:25.963200 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10875 16:32:25.980274 <30>[ 12.355778] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10876 16:32:25.987459 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10877 16:32:26.004973 <30>[ 12.380497] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10878 16:32:26.015027 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10879 16:32:26.034757 <30>[ 12.409907] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10880 16:32:26.044531 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10881 16:32:26.060241 <30>[ 12.435500] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10882 16:32:26.069902 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10883 16:32:26.120593 <30>[ 12.495537] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10884 16:32:26.127217 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10885 16:32:26.146523 <30>[ 12.521626] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10886 16:32:26.153125 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10887 16:32:26.176987 <30>[ 12.552001] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10888 16:32:26.183291 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10889 16:32:26.211132 <30>[ 12.579640] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10890 16:32:26.226813 <30>[ 12.601834] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10891 16:32:26.236219 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10892 16:32:26.256956 <30>[ 12.632510] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10893 16:32:26.263667 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10894 16:32:26.292221 <30>[ 12.667434] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10895 16:32:26.298557 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10896 16:32:26.329757 <30>[ 12.705138] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10897 16:32:26.336346 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10898 16:32:26.346371 <6>[ 12.721043] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10899 16:32:26.360900 <30>[ 12.736170] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10900 16:32:26.367859 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10901 16:32:26.440511 <30>[ 12.815656] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10902 16:32:26.446955 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10903 16:32:26.473786 <30>[ 12.848976] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10904 16:32:26.483929 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 12.863343] fuse: init (API version 7.37)
10905 16:32:26.484032 .
10906 16:32:26.532283 <30>[ 12.907680] systemd[1]: Starting systemd-journald.service - Journal Service...
10907 16:32:26.539125 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10908 16:32:26.564307 <30>[ 12.939600] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10909 16:32:26.570926 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10910 16:32:26.599908 <30>[ 12.971991] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10911 16:32:26.606450 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10912 16:32:26.633952 <30>[ 13.009022] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10913 16:32:26.644047 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10914 16:32:26.664174 <30>[ 13.039599] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10915 16:32:26.671048 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10916 16:32:26.702070 <30>[ 13.077436] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10917 16:32:26.709093 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10918 16:32:26.729091 <30>[ 13.104062] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10919 16:32:26.738852 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10920 16:32:26.757640 <3>[ 13.132968] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 16:32:26.767639 <30>[ 13.142433] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10922 16:32:26.777611 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10923 16:32:26.792723 <30>[ 13.167657] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10924 16:32:26.802775 <3>[ 13.169841] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 16:32:26.809547 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10926 16:32:26.828933 <30>[ 13.204039] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10927 16:32:26.839006 <30>[ 13.212226] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10928 16:32:26.845161 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10929 16:32:26.864753 <3>[ 13.239542] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 16:32:26.870622 <30>[ 13.239834] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10931 16:32:26.881257 <30>[ 13.256490] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10932 16:32:26.890949 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10933 16:32:26.908194 <3>[ 13.283420] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 16:32:26.914961 <30>[ 13.283761] systemd[1]: modprobe@drm.service: Deactivated successfully.
10935 16:32:26.924920 <30>[ 13.299799] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10936 16:32:26.938535 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 13.313507] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 16:32:26.941830 ule drm.
10938 16:32:26.961427 <30>[ 13.335932] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10939 16:32:26.967581 <30>[ 13.343988] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10940 16:32:26.977895 <3>[ 13.346041] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 16:32:26.987715 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10942 16:32:27.002457 <30>[ 13.380793] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10943 16:32:27.012513 <3>[ 13.386843] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 16:32:27.019303 <30>[ 13.388380] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10945 16:32:27.029714 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10946 16:32:27.047482 <3>[ 13.423072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 16:32:27.054838 <30>[ 13.423935] systemd[1]: modprobe@loop.service: Deactivated successfully.
10948 16:32:27.064573 <30>[ 13.439865] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10949 16:32:27.071110 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10950 16:32:27.092829 <30>[ 13.467921] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10951 16:32:27.099291 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10952 16:32:27.121806 <4>[ 13.489998] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10953 16:32:27.128475 <3>[ 13.505683] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10954 16:32:27.138445 <30>[ 13.506082] systemd[1]: Started systemd-journald.service - Journal Service.
10955 16:32:27.145185 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10956 16:32:27.166107 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10957 16:32:27.188800 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10958 16:32:27.209671 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10959 16:32:27.230418 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10960 16:32:27.268830 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10961 16:32:27.293285 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10962 16:32:27.318436 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10963 16:32:27.341814 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10964 16:32:27.370857 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10965 16:32:27.385757 <46>[ 13.760955] systemd-journald[309]: Received client request to flush runtime journal.
10966 16:32:27.399345 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10967 16:32:27.428257 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10968 16:32:27.444230 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10969 16:32:27.465407 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10970 16:32:27.485525 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10971 16:32:28.490263 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10972 16:32:28.528990 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10973 16:32:28.786675 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10974 16:32:28.906038 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10975 16:32:28.928615 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10976 16:32:28.948325 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10977 16:32:28.998041 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10978 16:32:29.023561 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10979 16:32:29.235278 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10980 16:32:29.269342 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10981 16:32:29.365545 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10982 16:32:29.657579 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10983 16:32:29.706433 <6>[ 16.085189] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10984 16:32:29.716875 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10985 16:32:29.743347 [[0;32m OK [0m] Finished [0<4>[ 16.120644] power_supply_show_property: 4 callbacks suppressed
10986 16:32:29.752719 <3>[ 16.120682] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 16:32:29.763843 ;1;39msystemd-tm<3>[ 16.127318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10988 16:32:29.773538 pfiles-…te Volatile Files and <3>[ 16.148404] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 16:32:29.776605 Directories.
10990 16:32:29.807505 <3>[ 16.183132] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 16:32:29.838384 <3>[ 16.213865] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 16:32:29.849635 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10993 16:32:29.870767 <3>[ 16.246603] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 16:32:29.880864 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10995 16:32:29.904432 <3>[ 16.279529] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 16:32:29.933392 <3>[ 16.308849] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 16:32:29.939649 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10998 16:32:29.962414 <3>[ 16.337698] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 16:32:29.968831 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11000 16:32:29.992448 <3>[ 16.367882] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 16:32:30.002549 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11002 16:32:30.030135 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11003 16:32:30.076349 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11004 16:32:30.141114 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11005 16:32:30.160849 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11006 16:32:30.182316 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11007 16:32:30.203335 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11008 16:32:30.219970 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11009 16:32:30.235736 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11010 16:32:30.261124 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11011 16:32:30.283827 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11012 16:32:30.300376 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11013 16:32:30.319746 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11014 16:32:30.382980 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11015 16:32:30.399267 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11016 16:32:30.423901 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11017 16:32:30.439300 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11018 16:32:30.456483 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11019 16:32:30.510335 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11020 16:32:30.585217 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11021 16:32:30.681203 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11022 16:32:30.706825 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11023 16:32:30.728120 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11024 16:32:30.859196 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11025 16:32:30.918745 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11026 16:32:30.951732 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11027 16:32:30.968513 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11028 16:32:30.985662 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11029 16:32:31.020238 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11030 16:32:31.045646 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11031 16:32:31.065751 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11032 16:32:31.084623 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11033 16:32:31.149818 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11034 16:32:31.193656 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11035 16:32:31.278953
11036 16:32:31.282648 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11037 16:32:31.283048
11038 16:32:31.285783 debian-bookworm-arm64 login: root (automatic login)
11039 16:32:31.286380
11040 16:32:31.593403 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Mon Jun 17 16:16:56 UTC 2024 aarch64
11041 16:32:31.593522
11042 16:32:31.599973 The programs included with the Debian GNU/Linux system are free software;
11043 16:32:31.606327 the exact distribution terms for each program are described in the
11044 16:32:31.609632 individual files in /usr/share/doc/*/copyright.
11045 16:32:31.609708
11046 16:32:31.616594 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11047 16:32:31.619844 permitted by applicable law.
11048 16:32:31.711712 Matched prompt #10: / #
11050 16:32:31.712105 Setting prompt string to ['/ #']
11051 16:32:31.712220 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11053 16:32:31.712502 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11054 16:32:31.712611 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
11055 16:32:31.712749 Setting prompt string to ['/ #']
11056 16:32:31.712831 Forcing a shell prompt, looking for ['/ #']
11058 16:32:31.763076 / #
11059 16:32:31.763314 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11060 16:32:31.763412 Waiting using forced prompt support (timeout 00:02:30)
11061 16:32:31.767718
11062 16:32:31.768040 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11063 16:32:31.768166 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
11065 16:32:31.868540 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396120/extract-nfsrootfs-7a_4oqnq'
11066 16:32:31.873250 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14396120/extract-nfsrootfs-7a_4oqnq'
11068 16:32:31.973856 / # export NFS_SERVER_IP='192.168.201.1'
11069 16:32:31.980107 export NFS_SERVER_IP='192.168.201.1'
11070 16:32:31.980873 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11071 16:32:31.981571 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
11072 16:32:31.982159 end: 2 depthcharge-action (duration 00:01:34) [common]
11073 16:32:31.982757 start: 3 lava-test-retry (timeout 00:01:00) [common]
11074 16:32:31.983316 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11075 16:32:31.983781 Using namespace: common
11077 16:32:32.084839 / # #
11078 16:32:32.085478 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11079 16:32:32.091521 #
11080 16:32:32.092353 Using /lava-14396120
11082 16:32:32.193554 / # export SHELL=/bin/sh
11083 16:32:32.199957 export SHELL=/bin/sh
11085 16:32:32.301609 / # . /lava-14396120/environment
11086 16:32:32.308334 . /lava-14396120/environment
11088 16:32:32.416296 / # /lava-14396120/bin/lava-test-runner /lava-14396120/0
11089 16:32:32.416917 Test shell timeout: 10s (minimum of the action and connection timeout)
11090 16:32:32.422348 /lava-14396120/bin/lava-test-runner /lava-14396120/0
11091 16:32:32.690098 + export TESTRUN_ID=0_dmesg
11092 16:32:32.693767 + cd /lava-14396120/0/tests/0_dmesg
11093 16:32:32.696914 + cat uuid
11094 16:32:32.711687 + UUID=14396120_<8>[ 19.087293] <LAVA_SIGNAL_STARTRUN 0_dmesg 14396120_1.6.2.3.1>
11095 16:32:32.711785 1.6.2.3.1
11096 16:32:32.711859 + set +x
11097 16:32:32.712108 Received signal: <STARTRUN> 0_dmesg 14396120_1.6.2.3.1
11098 16:32:32.712183 Starting test lava.0_dmesg (14396120_1.6.2.3.1)
11099 16:32:32.712271 Skipping test definition patterns.
11100 16:32:32.718149 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11101 16:32:32.835913 <8>[ 19.211623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11102 16:32:32.836210 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11104 16:32:32.924048 <8>[ 19.299633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11105 16:32:32.924768 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11107 16:32:33.016952 <8>[ 19.393000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11108 16:32:33.017380 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11110 16:32:33.020482 + set +x
11111 16:32:33.023402 <8>[ 19.402624] <LAVA_SIGNAL_ENDRUN 0_dmesg 14396120_1.6.2.3.1>
11112 16:32:33.023881 Received signal: <ENDRUN> 0_dmesg 14396120_1.6.2.3.1
11113 16:32:33.024041 Ending use of test pattern.
11114 16:32:33.024161 Ending test lava.0_dmesg (14396120_1.6.2.3.1), duration 0.31
11116 16:32:33.036593 <LAVA_TEST_RUNNER EXIT>
11117 16:32:33.037018 ok: lava_test_shell seems to have completed
11118 16:32:33.037208 alert: pass
crit: pass
emerg: pass
11119 16:32:33.037384 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11120 16:32:33.037570 end: 3 lava-test-retry (duration 00:00:01) [common]
11121 16:32:33.037777 start: 4 finalize (timeout 00:07:54) [common]
11122 16:32:33.037956 start: 4.1 power-off (timeout 00:00:30) [common]
11123 16:32:33.038215 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11124 16:32:33.259892 >> Command sent successfully.
11125 16:32:33.273938 Returned 0 in 0 seconds
11126 16:32:33.375264 end: 4.1 power-off (duration 00:00:00) [common]
11128 16:32:33.376638 start: 4.2 read-feedback (timeout 00:07:53) [common]
11129 16:32:33.377805 Listened to connection for namespace 'common' for up to 1s
11130 16:32:34.378495 Finalising connection for namespace 'common'
11131 16:32:34.379113 Disconnecting from shell: Finalise
11132 16:32:34.379479 / #
11133 16:32:34.480059 end: 4.2 read-feedback (duration 00:00:01) [common]
11134 16:32:34.480303 end: 4 finalize (duration 00:00:01) [common]
11135 16:32:34.480519 Cleaning after the job
11136 16:32:34.480709 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/ramdisk
11137 16:32:34.482880 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/kernel
11138 16:32:34.493879 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/dtb
11139 16:32:34.494061 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/nfsrootfs
11140 16:32:34.614431 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14396120/tftp-deploy-i999hvlk/modules
11141 16:32:34.637368 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14396120
11142 16:32:34.970234 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14396120
11143 16:32:34.970415 Job finished correctly